Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 14
- Kernel Errors: 35
- Errors: 0
1 23:08:49.674206 lava-dispatcher, installed at version: 2023.10
2 23:08:49.674432 start: 0 validate
3 23:08:49.674563 Start time: 2023-12-27 23:08:49.674555+00:00 (UTC)
4 23:08:49.674677 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:08:49.674808 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 23:08:49.935038 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:08:49.935766 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:08:50.198713 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:08:50.199754 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:08:50.470358 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:08:50.471093 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:08:50.731787 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:08:50.732688 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:08:50.994399 validate duration: 1.32
16 23:08:50.994678 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:08:50.994781 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:08:50.994875 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:08:50.994998 Not decompressing ramdisk as can be used compressed.
20 23:08:50.995085 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 23:08:50.995154 saving as /var/lib/lava/dispatcher/tmp/12395371/tftp-deploy-3o67wms0/ramdisk/initrd.cpio.gz
22 23:08:50.995220 total size: 4665395 (4 MB)
23 23:08:50.996422 progress 0 % (0 MB)
24 23:08:50.998021 progress 5 % (0 MB)
25 23:08:50.999389 progress 10 % (0 MB)
26 23:08:51.000698 progress 15 % (0 MB)
27 23:08:51.001960 progress 20 % (0 MB)
28 23:08:51.003297 progress 25 % (1 MB)
29 23:08:51.004592 progress 30 % (1 MB)
30 23:08:51.005839 progress 35 % (1 MB)
31 23:08:51.007074 progress 40 % (1 MB)
32 23:08:51.008541 progress 45 % (2 MB)
33 23:08:51.009880 progress 50 % (2 MB)
34 23:08:51.011140 progress 55 % (2 MB)
35 23:08:51.012419 progress 60 % (2 MB)
36 23:08:51.013654 progress 65 % (2 MB)
37 23:08:51.014909 progress 70 % (3 MB)
38 23:08:51.016203 progress 75 % (3 MB)
39 23:08:51.017442 progress 80 % (3 MB)
40 23:08:51.018841 progress 85 % (3 MB)
41 23:08:51.020116 progress 90 % (4 MB)
42 23:08:51.021414 progress 95 % (4 MB)
43 23:08:51.022717 progress 100 % (4 MB)
44 23:08:51.022873 4 MB downloaded in 0.03 s (160.90 MB/s)
45 23:08:51.023029 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:08:51.023274 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:08:51.023362 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:08:51.023447 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:08:51.023575 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:08:51.023645 saving as /var/lib/lava/dispatcher/tmp/12395371/tftp-deploy-3o67wms0/kernel/Image
52 23:08:51.023751 total size: 50024960 (47 MB)
53 23:08:51.023815 No compression specified
54 23:08:51.025052 progress 0 % (0 MB)
55 23:08:51.038453 progress 5 % (2 MB)
56 23:08:51.051640 progress 10 % (4 MB)
57 23:08:51.064973 progress 15 % (7 MB)
58 23:08:51.078383 progress 20 % (9 MB)
59 23:08:51.091963 progress 25 % (11 MB)
60 23:08:51.105057 progress 30 % (14 MB)
61 23:08:51.118489 progress 35 % (16 MB)
62 23:08:51.131817 progress 40 % (19 MB)
63 23:08:51.144878 progress 45 % (21 MB)
64 23:08:51.158124 progress 50 % (23 MB)
65 23:08:51.171243 progress 55 % (26 MB)
66 23:08:51.184480 progress 60 % (28 MB)
67 23:08:51.197744 progress 65 % (31 MB)
68 23:08:51.210848 progress 70 % (33 MB)
69 23:08:51.224044 progress 75 % (35 MB)
70 23:08:51.237409 progress 80 % (38 MB)
71 23:08:51.250510 progress 85 % (40 MB)
72 23:08:51.263546 progress 90 % (42 MB)
73 23:08:51.276540 progress 95 % (45 MB)
74 23:08:51.289379 progress 100 % (47 MB)
75 23:08:51.289615 47 MB downloaded in 0.27 s (179.45 MB/s)
76 23:08:51.289772 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:08:51.290011 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:08:51.290100 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:08:51.290189 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:08:51.290326 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:08:51.290396 saving as /var/lib/lava/dispatcher/tmp/12395371/tftp-deploy-3o67wms0/dtb/mt8192-asurada-spherion-r0.dtb
83 23:08:51.290458 total size: 47278 (0 MB)
84 23:08:51.290520 No compression specified
85 23:08:51.291656 progress 69 % (0 MB)
86 23:08:51.291983 progress 100 % (0 MB)
87 23:08:51.292140 0 MB downloaded in 0.00 s (26.85 MB/s)
88 23:08:51.292261 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:08:51.292493 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:08:51.292624 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:08:51.292708 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:08:51.292823 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 23:08:51.292892 saving as /var/lib/lava/dispatcher/tmp/12395371/tftp-deploy-3o67wms0/nfsrootfs/full.rootfs.tar
95 23:08:51.292952 total size: 200813988 (191 MB)
96 23:08:51.293015 Using unxz to decompress xz
97 23:08:51.297125 progress 0 % (0 MB)
98 23:08:51.826276 progress 5 % (9 MB)
99 23:08:52.342525 progress 10 % (19 MB)
100 23:08:52.926468 progress 15 % (28 MB)
101 23:08:53.314898 progress 20 % (38 MB)
102 23:08:53.638390 progress 25 % (47 MB)
103 23:08:54.228884 progress 30 % (57 MB)
104 23:08:54.785714 progress 35 % (67 MB)
105 23:08:55.379636 progress 40 % (76 MB)
106 23:08:55.942441 progress 45 % (86 MB)
107 23:08:56.530094 progress 50 % (95 MB)
108 23:08:57.159026 progress 55 % (105 MB)
109 23:08:57.825899 progress 60 % (114 MB)
110 23:08:57.949906 progress 65 % (124 MB)
111 23:08:58.090811 progress 70 % (134 MB)
112 23:08:58.187502 progress 75 % (143 MB)
113 23:08:58.258868 progress 80 % (153 MB)
114 23:08:58.327410 progress 85 % (162 MB)
115 23:08:58.428417 progress 90 % (172 MB)
116 23:08:58.708810 progress 95 % (181 MB)
117 23:08:59.287407 progress 100 % (191 MB)
118 23:08:59.292828 191 MB downloaded in 8.00 s (23.94 MB/s)
119 23:08:59.293149 end: 1.4.1 http-download (duration 00:00:08) [common]
121 23:08:59.293553 end: 1.4 download-retry (duration 00:00:08) [common]
122 23:08:59.293674 start: 1.5 download-retry (timeout 00:09:52) [common]
123 23:08:59.293792 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 23:08:59.293964 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:08:59.294063 saving as /var/lib/lava/dispatcher/tmp/12395371/tftp-deploy-3o67wms0/modules/modules.tar
126 23:08:59.294165 total size: 8633892 (8 MB)
127 23:08:59.294270 Using unxz to decompress xz
128 23:08:59.298618 progress 0 % (0 MB)
129 23:08:59.319832 progress 5 % (0 MB)
130 23:08:59.343911 progress 10 % (0 MB)
131 23:08:59.367753 progress 15 % (1 MB)
132 23:08:59.391620 progress 20 % (1 MB)
133 23:08:59.417532 progress 25 % (2 MB)
134 23:08:59.445815 progress 30 % (2 MB)
135 23:08:59.470219 progress 35 % (2 MB)
136 23:08:59.493570 progress 40 % (3 MB)
137 23:08:59.518180 progress 45 % (3 MB)
138 23:08:59.543843 progress 50 % (4 MB)
139 23:08:59.568662 progress 55 % (4 MB)
140 23:08:59.595494 progress 60 % (4 MB)
141 23:08:59.621198 progress 65 % (5 MB)
142 23:08:59.646012 progress 70 % (5 MB)
143 23:08:59.669586 progress 75 % (6 MB)
144 23:08:59.697234 progress 80 % (6 MB)
145 23:08:59.723308 progress 85 % (7 MB)
146 23:08:59.751178 progress 90 % (7 MB)
147 23:08:59.781172 progress 95 % (7 MB)
148 23:08:59.809019 progress 100 % (8 MB)
149 23:08:59.814506 8 MB downloaded in 0.52 s (15.82 MB/s)
150 23:08:59.814769 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:08:59.815033 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:08:59.815126 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 23:08:59.815222 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 23:09:03.355965 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12395371/extract-nfsrootfs-1s5co7bz
156 23:09:03.356195 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:09:03.356305 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 23:09:03.356489 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6
159 23:09:03.356635 makedir: /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin
160 23:09:03.356742 makedir: /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/tests
161 23:09:03.356844 makedir: /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/results
162 23:09:03.356947 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-add-keys
163 23:09:03.357094 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-add-sources
164 23:09:03.357223 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-background-process-start
165 23:09:03.357353 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-background-process-stop
166 23:09:03.357480 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-common-functions
167 23:09:03.357606 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-echo-ipv4
168 23:09:03.357731 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-install-packages
169 23:09:03.357856 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-installed-packages
170 23:09:03.357981 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-os-build
171 23:09:03.358105 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-probe-channel
172 23:09:03.358273 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-probe-ip
173 23:09:03.358412 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-target-ip
174 23:09:03.358536 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-target-mac
175 23:09:03.358658 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-target-storage
176 23:09:03.358785 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-test-case
177 23:09:03.358908 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-test-event
178 23:09:03.359031 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-test-feedback
179 23:09:03.359153 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-test-raise
180 23:09:03.359277 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-test-reference
181 23:09:03.359400 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-test-runner
182 23:09:03.359523 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-test-set
183 23:09:03.359646 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-test-shell
184 23:09:03.359817 Updating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-add-keys (debian)
185 23:09:03.359982 Updating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-add-sources (debian)
186 23:09:03.360122 Updating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-install-packages (debian)
187 23:09:03.360262 Updating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-installed-packages (debian)
188 23:09:03.360414 Updating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/bin/lava-os-build (debian)
189 23:09:03.360537 Creating /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/environment
190 23:09:03.360638 LAVA metadata
191 23:09:03.360711 - LAVA_JOB_ID=12395371
192 23:09:03.360776 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:09:03.360890 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 23:09:03.360958 skipped lava-vland-overlay
195 23:09:03.361033 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:09:03.361115 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 23:09:03.361175 skipped lava-multinode-overlay
198 23:09:03.361262 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:09:03.361341 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 23:09:03.361417 Loading test definitions
201 23:09:03.361509 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 23:09:03.361581 Using /lava-12395371 at stage 0
203 23:09:03.361882 uuid=12395371_1.6.2.3.1 testdef=None
204 23:09:03.361971 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:09:03.362056 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 23:09:03.362529 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:09:03.362749 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 23:09:03.363304 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:09:03.363533 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 23:09:03.364131 runner path: /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/0/tests/0_timesync-off test_uuid 12395371_1.6.2.3.1
213 23:09:03.364292 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:09:03.364518 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 23:09:03.364592 Using /lava-12395371 at stage 0
217 23:09:03.364691 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:09:03.364770 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/0/tests/1_kselftest-tpm2'
219 23:09:08.318201 Running '/usr/bin/git checkout kernelci.org
220 23:09:08.468893 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 23:09:08.469682 uuid=12395371_1.6.2.3.5 testdef=None
222 23:09:08.469854 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 23:09:08.470108 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 23:09:08.470859 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:09:08.471089 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 23:09:08.472133 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:09:08.472367 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 23:09:08.473382 runner path: /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/0/tests/1_kselftest-tpm2 test_uuid 12395371_1.6.2.3.5
232 23:09:08.473476 BOARD='mt8192-asurada-spherion-r0'
233 23:09:08.473541 BRANCH='cip-gitlab'
234 23:09:08.473600 SKIPFILE='/dev/null'
235 23:09:08.473658 SKIP_INSTALL='True'
236 23:09:08.473713 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:09:08.473770 TST_CASENAME=''
238 23:09:08.473825 TST_CMDFILES='tpm2'
239 23:09:08.473970 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:09:08.474176 Creating lava-test-runner.conf files
242 23:09:08.474241 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12395371/lava-overlay-z0ak1ar6/lava-12395371/0 for stage 0
243 23:09:08.474336 - 0_timesync-off
244 23:09:08.474405 - 1_kselftest-tpm2
245 23:09:08.474501 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 23:09:08.474595 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 23:09:16.064916 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 23:09:16.065076 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 23:09:16.065173 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:09:16.065274 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 23:09:16.065363 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 23:09:16.188756 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:09:16.189310 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 23:09:16.189500 extracting modules file /var/lib/lava/dispatcher/tmp/12395371/tftp-deploy-3o67wms0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12395371/extract-nfsrootfs-1s5co7bz
255 23:09:16.453194 extracting modules file /var/lib/lava/dispatcher/tmp/12395371/tftp-deploy-3o67wms0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12395371/extract-overlay-ramdisk-bxp96d4w/ramdisk
256 23:09:16.681989 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:09:16.682167 start: 1.6.5 apply-overlay-tftp (timeout 00:09:34) [common]
258 23:09:16.682264 [common] Applying overlay to NFS
259 23:09:16.682338 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12395371/compress-overlay-tn1mqz8q/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12395371/extract-nfsrootfs-1s5co7bz
260 23:09:17.600066 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:09:17.600234 start: 1.6.6 configure-preseed-file (timeout 00:09:33) [common]
262 23:09:17.600327 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:09:17.600416 start: 1.6.7 compress-ramdisk (timeout 00:09:33) [common]
264 23:09:17.600497 Building ramdisk /var/lib/lava/dispatcher/tmp/12395371/extract-overlay-ramdisk-bxp96d4w/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12395371/extract-overlay-ramdisk-bxp96d4w/ramdisk
265 23:09:17.894781 >> 119421 blocks
266 23:09:19.776278 rename /var/lib/lava/dispatcher/tmp/12395371/extract-overlay-ramdisk-bxp96d4w/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12395371/tftp-deploy-3o67wms0/ramdisk/ramdisk.cpio.gz
267 23:09:19.776735 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:09:19.776857 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 23:09:19.776957 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 23:09:19.777060 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12395371/tftp-deploy-3o67wms0/kernel/Image'
271 23:09:32.127799 Returned 0 in 12 seconds
272 23:09:32.228641 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12395371/tftp-deploy-3o67wms0/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12395371/tftp-deploy-3o67wms0/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12395371/tftp-deploy-3o67wms0/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12395371/tftp-deploy-3o67wms0/kernel/image.itb
273 23:09:32.629288 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:09:32.629727 output: Created: Wed Dec 27 23:09:32 2023
275 23:09:32.629838 output: Image 0 (kernel-1)
276 23:09:32.629954 output: Description:
277 23:09:32.630055 output: Created: Wed Dec 27 23:09:32 2023
278 23:09:32.630156 output: Type: Kernel Image
279 23:09:32.630256 output: Compression: lzma compressed
280 23:09:32.630353 output: Data Size: 11480388 Bytes = 11211.32 KiB = 10.95 MiB
281 23:09:32.630434 output: Architecture: AArch64
282 23:09:32.630513 output: OS: Linux
283 23:09:32.630609 output: Load Address: 0x00000000
284 23:09:32.630707 output: Entry Point: 0x00000000
285 23:09:32.630803 output: Hash algo: crc32
286 23:09:32.630900 output: Hash value: a55b2f0b
287 23:09:32.631000 output: Image 1 (fdt-1)
288 23:09:32.631093 output: Description: mt8192-asurada-spherion-r0
289 23:09:32.631186 output: Created: Wed Dec 27 23:09:32 2023
290 23:09:32.631279 output: Type: Flat Device Tree
291 23:09:32.631370 output: Compression: uncompressed
292 23:09:32.631462 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 23:09:32.631554 output: Architecture: AArch64
294 23:09:32.631645 output: Hash algo: crc32
295 23:09:32.631784 output: Hash value: cc4352de
296 23:09:32.631878 output: Image 2 (ramdisk-1)
297 23:09:32.631970 output: Description: unavailable
298 23:09:32.632062 output: Created: Wed Dec 27 23:09:32 2023
299 23:09:32.632155 output: Type: RAMDisk Image
300 23:09:32.632247 output: Compression: Unknown Compression
301 23:09:32.632338 output: Data Size: 17800711 Bytes = 17383.51 KiB = 16.98 MiB
302 23:09:32.632431 output: Architecture: AArch64
303 23:09:32.632523 output: OS: Linux
304 23:09:32.632615 output: Load Address: unavailable
305 23:09:32.632710 output: Entry Point: unavailable
306 23:09:32.632803 output: Hash algo: crc32
307 23:09:32.632896 output: Hash value: 84979392
308 23:09:32.632988 output: Default Configuration: 'conf-1'
309 23:09:32.633080 output: Configuration 0 (conf-1)
310 23:09:32.633172 output: Description: mt8192-asurada-spherion-r0
311 23:09:32.633264 output: Kernel: kernel-1
312 23:09:32.633356 output: Init Ramdisk: ramdisk-1
313 23:09:32.633447 output: FDT: fdt-1
314 23:09:32.633538 output: Loadables: kernel-1
315 23:09:32.633628 output:
316 23:09:32.633885 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 23:09:32.634022 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 23:09:32.634175 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 23:09:32.634316 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 23:09:32.634430 No LXC device requested
321 23:09:32.634529 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:09:32.634636 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 23:09:32.634735 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:09:32.634821 Checking files for TFTP limit of 4294967296 bytes.
325 23:09:32.635491 end: 1 tftp-deploy (duration 00:00:42) [common]
326 23:09:32.635635 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:09:32.635795 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:09:32.635965 substitutions:
329 23:09:32.636043 - {DTB}: 12395371/tftp-deploy-3o67wms0/dtb/mt8192-asurada-spherion-r0.dtb
330 23:09:32.636128 - {INITRD}: 12395371/tftp-deploy-3o67wms0/ramdisk/ramdisk.cpio.gz
331 23:09:32.636208 - {KERNEL}: 12395371/tftp-deploy-3o67wms0/kernel/Image
332 23:09:32.636286 - {LAVA_MAC}: None
333 23:09:32.636364 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12395371/extract-nfsrootfs-1s5co7bz
334 23:09:32.636461 - {NFS_SERVER_IP}: 192.168.201.1
335 23:09:32.636560 - {PRESEED_CONFIG}: None
336 23:09:32.636656 - {PRESEED_LOCAL}: None
337 23:09:32.636752 - {RAMDISK}: 12395371/tftp-deploy-3o67wms0/ramdisk/ramdisk.cpio.gz
338 23:09:32.636847 - {ROOT_PART}: None
339 23:09:32.636942 - {ROOT}: None
340 23:09:32.637037 - {SERVER_IP}: 192.168.201.1
341 23:09:32.637131 - {TEE}: None
342 23:09:32.637225 Parsed boot commands:
343 23:09:32.637317 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:09:32.637567 Parsed boot commands: tftpboot 192.168.201.1 12395371/tftp-deploy-3o67wms0/kernel/image.itb 12395371/tftp-deploy-3o67wms0/kernel/cmdline
345 23:09:32.637704 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:09:32.637834 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:09:32.637974 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:09:32.638107 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:09:32.638217 Not connected, no need to disconnect.
350 23:09:32.638338 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:09:32.638465 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:09:32.638567 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 23:09:32.642809 Setting prompt string to ['lava-test: # ']
354 23:09:32.643198 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:09:32.643323 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:09:32.643467 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:09:32.643613 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:09:32.643993 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 23:09:37.778735 >> Command sent successfully.
360 23:09:37.781149 Returned 0 in 5 seconds
361 23:09:37.881595 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:09:37.882048 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:09:37.882190 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:09:37.882297 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:09:37.882376 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:09:37.882468 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:09:37.882754 [Enter `^Ec?' for help]
369 23:09:38.053852
370 23:09:38.054006
371 23:09:38.054103 F0: 102B 0000
372 23:09:38.054188
373 23:09:38.054268 F3: 1001 0000 [0200]
374 23:09:38.054347
375 23:09:38.057627 F3: 1001 0000
376 23:09:38.057721
377 23:09:38.057808 F7: 102D 0000
378 23:09:38.057890
379 23:09:38.061027 F1: 0000 0000
380 23:09:38.061113
381 23:09:38.061199 V0: 0000 0000 [0001]
382 23:09:38.061300
383 23:09:38.061399 00: 0007 8000
384 23:09:38.061501
385 23:09:38.064813 01: 0000 0000
386 23:09:38.064900
387 23:09:38.065002 BP: 0C00 0209 [0000]
388 23:09:38.065104
389 23:09:38.068587 G0: 1182 0000
390 23:09:38.068671
391 23:09:38.068758 EC: 0000 0021 [4000]
392 23:09:38.068839
393 23:09:38.071620 S7: 0000 0000 [0000]
394 23:09:38.071742
395 23:09:38.071828 CC: 0000 0000 [0001]
396 23:09:38.071909
397 23:09:38.075029 T0: 0000 0040 [010F]
398 23:09:38.075115
399 23:09:38.075217 Jump to BL
400 23:09:38.075318
401 23:09:38.100764
402 23:09:38.100857
403 23:09:38.100943
404 23:09:38.107761 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 23:09:38.110626 ARM64: Exception handlers installed.
406 23:09:38.114733 ARM64: Testing exception
407 23:09:38.118046 ARM64: Done test exception
408 23:09:38.125350 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 23:09:38.136228 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 23:09:38.143175 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 23:09:38.150791 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 23:09:38.157568 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 23:09:38.168229 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 23:09:38.178046 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 23:09:38.184948 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 23:09:38.203681 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 23:09:38.206577 WDT: Last reset was cold boot
418 23:09:38.210076 SPI1(PAD0) initialized at 2873684 Hz
419 23:09:38.213603 SPI5(PAD0) initialized at 992727 Hz
420 23:09:38.216972 VBOOT: Loading verstage.
421 23:09:38.223766 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:09:38.226452 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 23:09:38.230294 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 23:09:38.233578 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 23:09:38.241317 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 23:09:38.247823 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 23:09:38.258384 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 23:09:38.258493
429 23:09:38.258598
430 23:09:38.268533 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 23:09:38.271541 ARM64: Exception handlers installed.
432 23:09:38.274900 ARM64: Testing exception
433 23:09:38.275006 ARM64: Done test exception
434 23:09:38.281559 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 23:09:38.285117 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 23:09:38.299928 Probing TPM: . done!
437 23:09:38.300023 TPM ready after 0 ms
438 23:09:38.306320 Connected to device vid:did:rid of 1ae0:0028:00
439 23:09:38.316378 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 23:09:38.354555 Initialized TPM device CR50 revision 0
441 23:09:38.366245 tlcl_send_startup: Startup return code is 0
442 23:09:38.366370 TPM: setup succeeded
443 23:09:38.377695 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 23:09:38.385966 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:09:38.396949 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 23:09:38.405124 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 23:09:38.408803 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 23:09:38.411786 in-header: 03 07 00 00 08 00 00 00
449 23:09:38.415399 in-data: aa e4 47 04 13 02 00 00
450 23:09:38.418799 Chrome EC: UHEPI supported
451 23:09:38.425081 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 23:09:38.428233 in-header: 03 ad 00 00 08 00 00 00
453 23:09:38.431707 in-data: 00 20 20 08 00 00 00 00
454 23:09:38.431803 Phase 1
455 23:09:38.438388 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 23:09:38.445171 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 23:09:38.448624 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 23:09:38.451794 Recovery requested (1009000e)
459 23:09:38.460131 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 23:09:38.464783 tlcl_extend: response is 0
461 23:09:38.473188 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 23:09:38.478329 tlcl_extend: response is 0
463 23:09:38.484721 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 23:09:38.505161 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 23:09:38.511668 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 23:09:38.511759
467 23:09:38.511840
468 23:09:38.522665 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 23:09:38.526229 ARM64: Exception handlers installed.
470 23:09:38.526336 ARM64: Testing exception
471 23:09:38.529138 ARM64: Done test exception
472 23:09:38.550616 pmic_efuse_setting: Set efuses in 11 msecs
473 23:09:38.555227 pmwrap_interface_init: Select PMIF_VLD_RDY
474 23:09:38.558640 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 23:09:38.565418 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 23:09:38.568511 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 23:09:38.575576 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 23:09:38.578393 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 23:09:38.585691 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 23:09:38.588607 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 23:09:38.595710 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 23:09:38.598593 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 23:09:38.601952 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 23:09:38.608387 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 23:09:38.611588 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 23:09:38.614875 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 23:09:38.622162 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 23:09:38.628843 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 23:09:38.635487 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 23:09:38.638653 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 23:09:38.645532 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 23:09:38.652473 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 23:09:38.658722 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 23:09:38.662321 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 23:09:38.668878 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 23:09:38.672343 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 23:09:38.679893 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 23:09:38.682989 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 23:09:38.689926 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 23:09:38.696622 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 23:09:38.699898 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 23:09:38.703830 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 23:09:38.710511 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 23:09:38.713870 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 23:09:38.721804 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 23:09:38.724888 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 23:09:38.728233 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 23:09:38.735109 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 23:09:38.738105 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 23:09:38.744641 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 23:09:38.748537 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 23:09:38.756066 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 23:09:38.758753 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 23:09:38.762251 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 23:09:38.765997 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 23:09:38.772988 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 23:09:38.776645 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 23:09:38.779702 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 23:09:38.786229 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 23:09:38.789901 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 23:09:38.792684 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 23:09:38.796070 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 23:09:38.802634 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 23:09:38.805980 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 23:09:38.812595 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 23:09:38.822868 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 23:09:38.826811 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 23:09:38.835872 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 23:09:38.842920 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 23:09:38.849075 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 23:09:38.852621 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:09:38.856111 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 23:09:38.863283 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x0
534 23:09:38.870361 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 23:09:38.873755 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 23:09:38.877086 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 23:09:38.888015 [RTC]rtc_get_frequency_meter,154: input=15, output=834
538 23:09:38.897880 [RTC]rtc_get_frequency_meter,154: input=7, output=709
539 23:09:38.907195 [RTC]rtc_get_frequency_meter,154: input=11, output=773
540 23:09:38.916756 [RTC]rtc_get_frequency_meter,154: input=13, output=805
541 23:09:38.925772 [RTC]rtc_get_frequency_meter,154: input=12, output=788
542 23:09:38.935796 [RTC]rtc_get_frequency_meter,154: input=12, output=787
543 23:09:38.944887 [RTC]rtc_get_frequency_meter,154: input=13, output=804
544 23:09:38.947937 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 23:09:38.955246 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 23:09:38.958558 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 23:09:38.962583 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 23:09:38.968593 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 23:09:38.972135 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 23:09:38.975763 ADC[4]: Raw value=907466 ID=7
551 23:09:38.975863 ADC[3]: Raw value=213652 ID=1
552 23:09:38.978661 RAM Code: 0x71
553 23:09:38.982289 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 23:09:38.988591 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 23:09:38.995330 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 23:09:39.002244 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 23:09:39.005118 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 23:09:39.008667 in-header: 03 07 00 00 08 00 00 00
559 23:09:39.011934 in-data: aa e4 47 04 13 02 00 00
560 23:09:39.015259 Chrome EC: UHEPI supported
561 23:09:39.022701 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 23:09:39.025110 in-header: 03 dd 00 00 08 00 00 00
563 23:09:39.029085 in-data: 90 20 60 08 00 00 00 00
564 23:09:39.031880 MRC: failed to locate region type 0.
565 23:09:39.038101 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 23:09:39.041879 DRAM-K: Running full calibration
567 23:09:39.048425 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 23:09:39.048504 header.status = 0x0
569 23:09:39.051639 header.version = 0x6 (expected: 0x6)
570 23:09:39.054842 header.size = 0xd00 (expected: 0xd00)
571 23:09:39.058341 header.flags = 0x0
572 23:09:39.064880 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 23:09:39.082366 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 23:09:39.088676 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 23:09:39.091868 dram_init: ddr_geometry: 2
576 23:09:39.095375 [EMI] MDL number = 2
577 23:09:39.095462 [EMI] Get MDL freq = 0
578 23:09:39.098280 dram_init: ddr_type: 0
579 23:09:39.098365 is_discrete_lpddr4: 1
580 23:09:39.101587 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 23:09:39.101672
582 23:09:39.105096
583 23:09:39.105183 [Bian_co] ETT version 0.0.0.1
584 23:09:39.111705 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 23:09:39.111802
586 23:09:39.114971 dramc_set_vcore_voltage set vcore to 650000
587 23:09:39.118262 Read voltage for 800, 4
588 23:09:39.118345 Vio18 = 0
589 23:09:39.118410 Vcore = 650000
590 23:09:39.121434 Vdram = 0
591 23:09:39.121519 Vddq = 0
592 23:09:39.121585 Vmddr = 0
593 23:09:39.125127 dram_init: config_dvfs: 1
594 23:09:39.128042 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 23:09:39.135011 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 23:09:39.138174 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 23:09:39.141439 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 23:09:39.145373 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 23:09:39.152136 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 23:09:39.152219 MEM_TYPE=3, freq_sel=18
601 23:09:39.154704 sv_algorithm_assistance_LP4_1600
602 23:09:39.157826 ============ PULL DRAM RESETB DOWN ============
603 23:09:39.164874 ========== PULL DRAM RESETB DOWN end =========
604 23:09:39.168215 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 23:09:39.171573 ===================================
606 23:09:39.174699 LPDDR4 DRAM CONFIGURATION
607 23:09:39.178156 ===================================
608 23:09:39.178240 EX_ROW_EN[0] = 0x0
609 23:09:39.181343 EX_ROW_EN[1] = 0x0
610 23:09:39.181441 LP4Y_EN = 0x0
611 23:09:39.184976 WORK_FSP = 0x0
612 23:09:39.185085 WL = 0x2
613 23:09:39.188663 RL = 0x2
614 23:09:39.188740 BL = 0x2
615 23:09:39.191657 RPST = 0x0
616 23:09:39.194319 RD_PRE = 0x0
617 23:09:39.194402 WR_PRE = 0x1
618 23:09:39.197711 WR_PST = 0x0
619 23:09:39.197795 DBI_WR = 0x0
620 23:09:39.201440 DBI_RD = 0x0
621 23:09:39.201523 OTF = 0x1
622 23:09:39.204417 ===================================
623 23:09:39.207636 ===================================
624 23:09:39.211562 ANA top config
625 23:09:39.214357 ===================================
626 23:09:39.214440 DLL_ASYNC_EN = 0
627 23:09:39.217518 ALL_SLAVE_EN = 1
628 23:09:39.220792 NEW_RANK_MODE = 1
629 23:09:39.225176 DLL_IDLE_MODE = 1
630 23:09:39.225274 LP45_APHY_COMB_EN = 1
631 23:09:39.227550 TX_ODT_DIS = 1
632 23:09:39.231172 NEW_8X_MODE = 1
633 23:09:39.234447 ===================================
634 23:09:39.237649 ===================================
635 23:09:39.241062 data_rate = 1600
636 23:09:39.243958 CKR = 1
637 23:09:39.247540 DQ_P2S_RATIO = 8
638 23:09:39.251175 ===================================
639 23:09:39.251258 CA_P2S_RATIO = 8
640 23:09:39.254043 DQ_CA_OPEN = 0
641 23:09:39.257415 DQ_SEMI_OPEN = 0
642 23:09:39.260448 CA_SEMI_OPEN = 0
643 23:09:39.264040 CA_FULL_RATE = 0
644 23:09:39.267479 DQ_CKDIV4_EN = 1
645 23:09:39.267589 CA_CKDIV4_EN = 1
646 23:09:39.270387 CA_PREDIV_EN = 0
647 23:09:39.273978 PH8_DLY = 0
648 23:09:39.277253 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 23:09:39.280506 DQ_AAMCK_DIV = 4
650 23:09:39.284011 CA_AAMCK_DIV = 4
651 23:09:39.284094 CA_ADMCK_DIV = 4
652 23:09:39.287445 DQ_TRACK_CA_EN = 0
653 23:09:39.290211 CA_PICK = 800
654 23:09:39.294402 CA_MCKIO = 800
655 23:09:39.297309 MCKIO_SEMI = 0
656 23:09:39.300414 PLL_FREQ = 3068
657 23:09:39.304084 DQ_UI_PI_RATIO = 32
658 23:09:39.304191 CA_UI_PI_RATIO = 0
659 23:09:39.306700 ===================================
660 23:09:39.310423 ===================================
661 23:09:39.313435 memory_type:LPDDR4
662 23:09:39.316868 GP_NUM : 10
663 23:09:39.316971 SRAM_EN : 1
664 23:09:39.320180 MD32_EN : 0
665 23:09:39.323556 ===================================
666 23:09:39.327281 [ANA_INIT] >>>>>>>>>>>>>>
667 23:09:39.331581 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 23:09:39.333670 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 23:09:39.336764 ===================================
670 23:09:39.336868 data_rate = 1600,PCW = 0X7600
671 23:09:39.340058 ===================================
672 23:09:39.343825 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 23:09:39.350317 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:09:39.357123 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 23:09:39.359966 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 23:09:39.363384 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:09:39.366575 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 23:09:39.369869 [ANA_INIT] flow start
679 23:09:39.369951 [ANA_INIT] PLL >>>>>>>>
680 23:09:39.373231 [ANA_INIT] PLL <<<<<<<<
681 23:09:39.376964 [ANA_INIT] MIDPI >>>>>>>>
682 23:09:39.380492 [ANA_INIT] MIDPI <<<<<<<<
683 23:09:39.380574 [ANA_INIT] DLL >>>>>>>>
684 23:09:39.383193 [ANA_INIT] flow end
685 23:09:39.386984 ============ LP4 DIFF to SE enter ============
686 23:09:39.390500 ============ LP4 DIFF to SE exit ============
687 23:09:39.393396 [ANA_INIT] <<<<<<<<<<<<<
688 23:09:39.396459 [Flow] Enable top DCM control >>>>>
689 23:09:39.399948 [Flow] Enable top DCM control <<<<<
690 23:09:39.402852 Enable DLL master slave shuffle
691 23:09:39.409535 ==============================================================
692 23:09:39.409647 Gating Mode config
693 23:09:39.416153 ==============================================================
694 23:09:39.416230 Config description:
695 23:09:39.426710 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 23:09:39.433674 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 23:09:39.439488 SELPH_MODE 0: By rank 1: By Phase
698 23:09:39.443009 ==============================================================
699 23:09:39.446417 GAT_TRACK_EN = 1
700 23:09:39.449679 RX_GATING_MODE = 2
701 23:09:39.452972 RX_GATING_TRACK_MODE = 2
702 23:09:39.457083 SELPH_MODE = 1
703 23:09:39.459599 PICG_EARLY_EN = 1
704 23:09:39.463838 VALID_LAT_VALUE = 1
705 23:09:39.469268 ==============================================================
706 23:09:39.473155 Enter into Gating configuration >>>>
707 23:09:39.476118 Exit from Gating configuration <<<<
708 23:09:39.476200 Enter into DVFS_PRE_config >>>>>
709 23:09:39.489093 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 23:09:39.492707 Exit from DVFS_PRE_config <<<<<
711 23:09:39.495801 Enter into PICG configuration >>>>
712 23:09:39.499202 Exit from PICG configuration <<<<
713 23:09:39.499286 [RX_INPUT] configuration >>>>>
714 23:09:39.502400 [RX_INPUT] configuration <<<<<
715 23:09:39.509571 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 23:09:39.513301 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 23:09:39.520297 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 23:09:39.527855 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 23:09:39.531456 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 23:09:39.538710 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 23:09:39.542627 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 23:09:39.545686 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 23:09:39.550054 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 23:09:39.556821 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 23:09:39.560438 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 23:09:39.564164 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 23:09:39.567681 ===================================
728 23:09:39.571086 LPDDR4 DRAM CONFIGURATION
729 23:09:39.571196 ===================================
730 23:09:39.575189 EX_ROW_EN[0] = 0x0
731 23:09:39.578857 EX_ROW_EN[1] = 0x0
732 23:09:39.578961 LP4Y_EN = 0x0
733 23:09:39.579063 WORK_FSP = 0x0
734 23:09:39.582255 WL = 0x2
735 23:09:39.582356 RL = 0x2
736 23:09:39.585967 BL = 0x2
737 23:09:39.586076 RPST = 0x0
738 23:09:39.589625 RD_PRE = 0x0
739 23:09:39.589729 WR_PRE = 0x1
740 23:09:39.593378 WR_PST = 0x0
741 23:09:39.593480 DBI_WR = 0x0
742 23:09:39.597614 DBI_RD = 0x0
743 23:09:39.597716 OTF = 0x1
744 23:09:39.601109 ===================================
745 23:09:39.604756 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 23:09:39.608376 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 23:09:39.614794 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 23:09:39.614900 ===================================
749 23:09:39.618475 LPDDR4 DRAM CONFIGURATION
750 23:09:39.622083 ===================================
751 23:09:39.625563 EX_ROW_EN[0] = 0x10
752 23:09:39.625640 EX_ROW_EN[1] = 0x0
753 23:09:39.629546 LP4Y_EN = 0x0
754 23:09:39.629661 WORK_FSP = 0x0
755 23:09:39.632993 WL = 0x2
756 23:09:39.633100 RL = 0x2
757 23:09:39.636712 BL = 0x2
758 23:09:39.636792 RPST = 0x0
759 23:09:39.636877 RD_PRE = 0x0
760 23:09:39.640649 WR_PRE = 0x1
761 23:09:39.640723 WR_PST = 0x0
762 23:09:39.644676 DBI_WR = 0x0
763 23:09:39.644747 DBI_RD = 0x0
764 23:09:39.648153 OTF = 0x1
765 23:09:39.651739 ===================================
766 23:09:39.655519 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 23:09:39.660544 nWR fixed to 40
768 23:09:39.664354 [ModeRegInit_LP4] CH0 RK0
769 23:09:39.664471 [ModeRegInit_LP4] CH0 RK1
770 23:09:39.667147 [ModeRegInit_LP4] CH1 RK0
771 23:09:39.670929 [ModeRegInit_LP4] CH1 RK1
772 23:09:39.671031 match AC timing 13
773 23:09:39.674956 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 23:09:39.678276 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 23:09:39.684600 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 23:09:39.687618 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 23:09:39.694631 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 23:09:39.694740 [EMI DOE] emi_dcm 0
779 23:09:39.698149 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 23:09:39.701496 ==
781 23:09:39.704842 Dram Type= 6, Freq= 0, CH_0, rank 0
782 23:09:39.707718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 23:09:39.707806 ==
784 23:09:39.711575 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 23:09:39.717629 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 23:09:39.727638 [CA 0] Center 37 (6~68) winsize 63
787 23:09:39.730903 [CA 1] Center 36 (6~67) winsize 62
788 23:09:39.734186 [CA 2] Center 34 (4~65) winsize 62
789 23:09:39.737348 [CA 3] Center 34 (4~65) winsize 62
790 23:09:39.741327 [CA 4] Center 33 (3~64) winsize 62
791 23:09:39.745309 [CA 5] Center 33 (3~64) winsize 62
792 23:09:39.745407
793 23:09:39.748632 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 23:09:39.748735
795 23:09:39.751574 [CATrainingPosCal] consider 1 rank data
796 23:09:39.754792 u2DelayCellTimex100 = 270/100 ps
797 23:09:39.758082 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
798 23:09:39.761610 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
799 23:09:39.764608 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 23:09:39.768135 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 23:09:39.774739 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 23:09:39.778048 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 23:09:39.778148
804 23:09:39.781444 CA PerBit enable=1, Macro0, CA PI delay=33
805 23:09:39.781548
806 23:09:39.784901 [CBTSetCACLKResult] CA Dly = 33
807 23:09:39.785002 CS Dly: 6 (0~37)
808 23:09:39.785096 ==
809 23:09:39.788649 Dram Type= 6, Freq= 0, CH_0, rank 1
810 23:09:39.794789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 23:09:39.794895 ==
812 23:09:39.798498 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 23:09:39.804738 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 23:09:39.814096 [CA 0] Center 37 (6~68) winsize 63
815 23:09:39.817511 [CA 1] Center 37 (7~68) winsize 62
816 23:09:39.820438 [CA 2] Center 34 (4~65) winsize 62
817 23:09:39.823596 [CA 3] Center 34 (4~65) winsize 62
818 23:09:39.827007 [CA 4] Center 33 (3~64) winsize 62
819 23:09:39.830670 [CA 5] Center 33 (3~64) winsize 62
820 23:09:39.830769
821 23:09:39.833866 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 23:09:39.833946
823 23:09:39.837498 [CATrainingPosCal] consider 2 rank data
824 23:09:39.840664 u2DelayCellTimex100 = 270/100 ps
825 23:09:39.843946 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
826 23:09:39.850314 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
827 23:09:39.854350 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 23:09:39.858006 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 23:09:39.861382 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 23:09:39.865444 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 23:09:39.865553
832 23:09:39.869044 CA PerBit enable=1, Macro0, CA PI delay=33
833 23:09:39.869148
834 23:09:39.869244 [CBTSetCACLKResult] CA Dly = 33
835 23:09:39.873154 CS Dly: 6 (0~38)
836 23:09:39.873254
837 23:09:39.876821 ----->DramcWriteLeveling(PI) begin...
838 23:09:39.876925 ==
839 23:09:39.879501 Dram Type= 6, Freq= 0, CH_0, rank 0
840 23:09:39.883373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 23:09:39.883474 ==
842 23:09:39.886757 Write leveling (Byte 0): 31 => 31
843 23:09:39.890364 Write leveling (Byte 1): 29 => 29
844 23:09:39.893388 DramcWriteLeveling(PI) end<-----
845 23:09:39.893485
846 23:09:39.893577 ==
847 23:09:39.896756 Dram Type= 6, Freq= 0, CH_0, rank 0
848 23:09:39.899979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 23:09:39.900064 ==
850 23:09:39.903685 [Gating] SW mode calibration
851 23:09:39.910296 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 23:09:39.916942 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 23:09:39.920650 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 23:09:39.923987 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 23:09:39.929957 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 23:09:39.933830 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:09:39.936817 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:09:39.943422 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:09:39.946843 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:09:39.949922 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:09:39.953015 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:09:39.960101 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:09:39.963454 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:09:39.966598 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:09:39.973155 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:09:39.976859 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:09:39.980744 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:09:39.986674 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:09:39.989670 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 23:09:39.993332 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 23:09:39.999811 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
872 23:09:40.003874 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:09:40.006577 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:09:40.012882 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:09:40.016625 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:09:40.019930 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:09:40.026717 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:09:40.029653 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
879 23:09:40.033222 0 9 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
880 23:09:40.039676 0 9 12 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
881 23:09:40.042907 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:09:40.046327 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:09:40.052956 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:09:40.056615 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:09:40.059214 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 23:09:40.066019 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
887 23:09:40.069529 0 10 8 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (1 1)
888 23:09:40.072738 0 10 12 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
889 23:09:40.079140 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:09:40.082510 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:09:40.086037 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:09:40.092721 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:09:40.096094 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 23:09:40.099386 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 23:09:40.102658 0 11 8 | B1->B0 | 2727 3939 | 0 1 | (0 0) (0 0)
896 23:09:40.109351 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
897 23:09:40.112487 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:09:40.118754 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:09:40.122490 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:09:40.125728 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:09:40.128759 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 23:09:40.135598 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 23:09:40.138831 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 23:09:40.142145 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:09:40.148717 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:09:40.152106 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:09:40.155471 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:09:40.162296 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:09:40.165526 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:09:40.168712 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:09:40.175129 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:09:40.178921 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:09:40.182108 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:09:40.188411 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:09:40.192343 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:09:40.195224 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 23:09:40.202256 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 23:09:40.205229 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 23:09:40.208490 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 23:09:40.212323 Total UI for P1: 0, mck2ui 16
921 23:09:40.215353 best dqsien dly found for B0: ( 0, 14, 6)
922 23:09:40.221733 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 23:09:40.221840 Total UI for P1: 0, mck2ui 16
924 23:09:40.228280 best dqsien dly found for B1: ( 0, 14, 8)
925 23:09:40.231298 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 23:09:40.234880 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 23:09:40.234985
928 23:09:40.238077 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 23:09:40.241574 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 23:09:40.244447 [Gating] SW calibration Done
931 23:09:40.244529 ==
932 23:09:40.248132 Dram Type= 6, Freq= 0, CH_0, rank 0
933 23:09:40.252084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 23:09:40.252165 ==
935 23:09:40.255736 RX Vref Scan: 0
936 23:09:40.255812
937 23:09:40.255876 RX Vref 0 -> 0, step: 1
938 23:09:40.255945
939 23:09:40.259142 RX Delay -130 -> 252, step: 16
940 23:09:40.263013 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 23:09:40.266419 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 23:09:40.269995 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 23:09:40.273399 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 23:09:40.280683 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 23:09:40.284562 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 23:09:40.289094 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 23:09:40.292040 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 23:09:40.295827 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 23:09:40.299353 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
950 23:09:40.303571 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 23:09:40.306881 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 23:09:40.310128 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
953 23:09:40.313453 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 23:09:40.320320 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 23:09:40.323116 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 23:09:40.323220 ==
957 23:09:40.326760 Dram Type= 6, Freq= 0, CH_0, rank 0
958 23:09:40.329947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 23:09:40.330047 ==
960 23:09:40.333531 DQS Delay:
961 23:09:40.333635 DQS0 = 0, DQS1 = 0
962 23:09:40.336887 DQM Delay:
963 23:09:40.336987 DQM0 = 89, DQM1 = 76
964 23:09:40.337082 DQ Delay:
965 23:09:40.339818 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
966 23:09:40.343411 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
967 23:09:40.347097 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
968 23:09:40.349915 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
969 23:09:40.350016
970 23:09:40.350083
971 23:09:40.353689 ==
972 23:09:40.353775 Dram Type= 6, Freq= 0, CH_0, rank 0
973 23:09:40.360452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 23:09:40.360550 ==
975 23:09:40.360648
976 23:09:40.360738
977 23:09:40.360832 TX Vref Scan disable
978 23:09:40.363906 == TX Byte 0 ==
979 23:09:40.367902 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
980 23:09:40.371631 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
981 23:09:40.374934 == TX Byte 1 ==
982 23:09:40.378869 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
983 23:09:40.382498 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
984 23:09:40.382601 ==
985 23:09:40.386429 Dram Type= 6, Freq= 0, CH_0, rank 0
986 23:09:40.389161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 23:09:40.389266 ==
988 23:09:40.403198 TX Vref=22, minBit 5, minWin=27, winSum=440
989 23:09:40.406505 TX Vref=24, minBit 4, minWin=27, winSum=442
990 23:09:40.409354 TX Vref=26, minBit 8, minWin=27, winSum=445
991 23:09:40.412803 TX Vref=28, minBit 8, minWin=27, winSum=448
992 23:09:40.415930 TX Vref=30, minBit 10, minWin=27, winSum=449
993 23:09:40.422940 TX Vref=32, minBit 4, minWin=27, winSum=443
994 23:09:40.425915 [TxChooseVref] Worse bit 10, Min win 27, Win sum 449, Final Vref 30
995 23:09:40.426014
996 23:09:40.429261 Final TX Range 1 Vref 30
997 23:09:40.429359
998 23:09:40.429450 ==
999 23:09:40.433222 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 23:09:40.436480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 23:09:40.439422 ==
1002 23:09:40.439525
1003 23:09:40.439620
1004 23:09:40.439728 TX Vref Scan disable
1005 23:09:40.442721 == TX Byte 0 ==
1006 23:09:40.446974 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1007 23:09:40.449862 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1008 23:09:40.452765 == TX Byte 1 ==
1009 23:09:40.456516 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1010 23:09:40.459403 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1011 23:09:40.463258
1012 23:09:40.463341 [DATLAT]
1013 23:09:40.463407 Freq=800, CH0 RK0
1014 23:09:40.463467
1015 23:09:40.466183 DATLAT Default: 0xa
1016 23:09:40.466290 0, 0xFFFF, sum = 0
1017 23:09:40.469411 1, 0xFFFF, sum = 0
1018 23:09:40.469525 2, 0xFFFF, sum = 0
1019 23:09:40.472601 3, 0xFFFF, sum = 0
1020 23:09:40.475974 4, 0xFFFF, sum = 0
1021 23:09:40.476050 5, 0xFFFF, sum = 0
1022 23:09:40.479381 6, 0xFFFF, sum = 0
1023 23:09:40.479492 7, 0xFFFF, sum = 0
1024 23:09:40.482800 8, 0xFFFF, sum = 0
1025 23:09:40.482914 9, 0x0, sum = 1
1026 23:09:40.486290 10, 0x0, sum = 2
1027 23:09:40.486397 11, 0x0, sum = 3
1028 23:09:40.486488 12, 0x0, sum = 4
1029 23:09:40.489304 best_step = 10
1030 23:09:40.489401
1031 23:09:40.489488 ==
1032 23:09:40.492641 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 23:09:40.496024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 23:09:40.496123 ==
1035 23:09:40.499473 RX Vref Scan: 1
1036 23:09:40.499568
1037 23:09:40.502563 Set Vref Range= 32 -> 127
1038 23:09:40.502643
1039 23:09:40.502704 RX Vref 32 -> 127, step: 1
1040 23:09:40.502761
1041 23:09:40.506048 RX Delay -95 -> 252, step: 8
1042 23:09:40.506148
1043 23:09:40.509807 Set Vref, RX VrefLevel [Byte0]: 32
1044 23:09:40.512911 [Byte1]: 32
1045 23:09:40.512983
1046 23:09:40.516136 Set Vref, RX VrefLevel [Byte0]: 33
1047 23:09:40.519088 [Byte1]: 33
1048 23:09:40.523747
1049 23:09:40.523853 Set Vref, RX VrefLevel [Byte0]: 34
1050 23:09:40.527790 [Byte1]: 34
1051 23:09:40.530715
1052 23:09:40.530811 Set Vref, RX VrefLevel [Byte0]: 35
1053 23:09:40.534164 [Byte1]: 35
1054 23:09:40.538277
1055 23:09:40.538375 Set Vref, RX VrefLevel [Byte0]: 36
1056 23:09:40.541578 [Byte1]: 36
1057 23:09:40.546351
1058 23:09:40.546448 Set Vref, RX VrefLevel [Byte0]: 37
1059 23:09:40.549803 [Byte1]: 37
1060 23:09:40.553475
1061 23:09:40.553585 Set Vref, RX VrefLevel [Byte0]: 38
1062 23:09:40.557324 [Byte1]: 38
1063 23:09:40.561375
1064 23:09:40.561473 Set Vref, RX VrefLevel [Byte0]: 39
1065 23:09:40.564220 [Byte1]: 39
1066 23:09:40.568588
1067 23:09:40.568690 Set Vref, RX VrefLevel [Byte0]: 40
1068 23:09:40.571926 [Byte1]: 40
1069 23:09:40.576447
1070 23:09:40.576549 Set Vref, RX VrefLevel [Byte0]: 41
1071 23:09:40.580223 [Byte1]: 41
1072 23:09:40.584316
1073 23:09:40.584416 Set Vref, RX VrefLevel [Byte0]: 42
1074 23:09:40.587185 [Byte1]: 42
1075 23:09:40.592370
1076 23:09:40.592471 Set Vref, RX VrefLevel [Byte0]: 43
1077 23:09:40.594731 [Byte1]: 43
1078 23:09:40.599543
1079 23:09:40.599646 Set Vref, RX VrefLevel [Byte0]: 44
1080 23:09:40.602503 [Byte1]: 44
1081 23:09:40.606898
1082 23:09:40.606996 Set Vref, RX VrefLevel [Byte0]: 45
1083 23:09:40.610023 [Byte1]: 45
1084 23:09:40.614317
1085 23:09:40.614451 Set Vref, RX VrefLevel [Byte0]: 46
1086 23:09:40.617690 [Byte1]: 46
1087 23:09:40.621681
1088 23:09:40.621775 Set Vref, RX VrefLevel [Byte0]: 47
1089 23:09:40.625131 [Byte1]: 47
1090 23:09:40.629800
1091 23:09:40.629938 Set Vref, RX VrefLevel [Byte0]: 48
1092 23:09:40.633250 [Byte1]: 48
1093 23:09:40.637112
1094 23:09:40.637223 Set Vref, RX VrefLevel [Byte0]: 49
1095 23:09:40.644025 [Byte1]: 49
1096 23:09:40.644103
1097 23:09:40.646866 Set Vref, RX VrefLevel [Byte0]: 50
1098 23:09:40.650772 [Byte1]: 50
1099 23:09:40.650862
1100 23:09:40.653757 Set Vref, RX VrefLevel [Byte0]: 51
1101 23:09:40.658090 [Byte1]: 51
1102 23:09:40.659972
1103 23:09:40.660063 Set Vref, RX VrefLevel [Byte0]: 52
1104 23:09:40.663564 [Byte1]: 52
1105 23:09:40.667600
1106 23:09:40.667745 Set Vref, RX VrefLevel [Byte0]: 53
1107 23:09:40.670580 [Byte1]: 53
1108 23:09:40.675051
1109 23:09:40.675167 Set Vref, RX VrefLevel [Byte0]: 54
1110 23:09:40.678521 [Byte1]: 54
1111 23:09:40.682891
1112 23:09:40.682994 Set Vref, RX VrefLevel [Byte0]: 55
1113 23:09:40.686080 [Byte1]: 55
1114 23:09:40.690226
1115 23:09:40.690333 Set Vref, RX VrefLevel [Byte0]: 56
1116 23:09:40.693358 [Byte1]: 56
1117 23:09:40.697881
1118 23:09:40.697977 Set Vref, RX VrefLevel [Byte0]: 57
1119 23:09:40.701548 [Byte1]: 57
1120 23:09:40.705494
1121 23:09:40.705594 Set Vref, RX VrefLevel [Byte0]: 58
1122 23:09:40.708892 [Byte1]: 58
1123 23:09:40.712815
1124 23:09:40.712913 Set Vref, RX VrefLevel [Byte0]: 59
1125 23:09:40.716382 [Byte1]: 59
1126 23:09:40.720963
1127 23:09:40.721066 Set Vref, RX VrefLevel [Byte0]: 60
1128 23:09:40.724418 [Byte1]: 60
1129 23:09:40.728728
1130 23:09:40.728830 Set Vref, RX VrefLevel [Byte0]: 61
1131 23:09:40.731844 [Byte1]: 61
1132 23:09:40.736563
1133 23:09:40.736662 Set Vref, RX VrefLevel [Byte0]: 62
1134 23:09:40.740044 [Byte1]: 62
1135 23:09:40.743996
1136 23:09:40.744077 Set Vref, RX VrefLevel [Byte0]: 63
1137 23:09:40.747014 [Byte1]: 63
1138 23:09:40.750693
1139 23:09:40.754442 Set Vref, RX VrefLevel [Byte0]: 64
1140 23:09:40.754538 [Byte1]: 64
1141 23:09:40.758942
1142 23:09:40.759050 Set Vref, RX VrefLevel [Byte0]: 65
1143 23:09:40.762918 [Byte1]: 65
1144 23:09:40.766402
1145 23:09:40.766509 Set Vref, RX VrefLevel [Byte0]: 66
1146 23:09:40.770071 [Byte1]: 66
1147 23:09:40.774290
1148 23:09:40.774394 Set Vref, RX VrefLevel [Byte0]: 67
1149 23:09:40.777594 [Byte1]: 67
1150 23:09:40.781712
1151 23:09:40.781816 Set Vref, RX VrefLevel [Byte0]: 68
1152 23:09:40.785492 [Byte1]: 68
1153 23:09:40.789086
1154 23:09:40.789190 Set Vref, RX VrefLevel [Byte0]: 69
1155 23:09:40.792543 [Byte1]: 69
1156 23:09:40.796713
1157 23:09:40.796817 Set Vref, RX VrefLevel [Byte0]: 70
1158 23:09:40.800693 [Byte1]: 70
1159 23:09:40.804684
1160 23:09:40.807587 Set Vref, RX VrefLevel [Byte0]: 71
1161 23:09:40.810464 [Byte1]: 71
1162 23:09:40.810546
1163 23:09:40.814870 Set Vref, RX VrefLevel [Byte0]: 72
1164 23:09:40.818010 [Byte1]: 72
1165 23:09:40.818092
1166 23:09:40.821815 Set Vref, RX VrefLevel [Byte0]: 73
1167 23:09:40.825716 [Byte1]: 73
1168 23:09:40.825798
1169 23:09:40.828934 Set Vref, RX VrefLevel [Byte0]: 74
1170 23:09:40.832704 [Byte1]: 74
1171 23:09:40.832786
1172 23:09:40.836401 Set Vref, RX VrefLevel [Byte0]: 75
1173 23:09:40.839544 [Byte1]: 75
1174 23:09:40.839628
1175 23:09:40.843388 Set Vref, RX VrefLevel [Byte0]: 76
1176 23:09:40.847901 [Byte1]: 76
1177 23:09:40.850437
1178 23:09:40.850518 Set Vref, RX VrefLevel [Byte0]: 77
1179 23:09:40.853567 [Byte1]: 77
1180 23:09:40.857633
1181 23:09:40.857716 Set Vref, RX VrefLevel [Byte0]: 78
1182 23:09:40.861187 [Byte1]: 78
1183 23:09:40.866332
1184 23:09:40.866414 Set Vref, RX VrefLevel [Byte0]: 79
1185 23:09:40.869296 [Byte1]: 79
1186 23:09:40.873047
1187 23:09:40.873129 Set Vref, RX VrefLevel [Byte0]: 80
1188 23:09:40.876305 [Byte1]: 80
1189 23:09:40.880210
1190 23:09:40.880292 Set Vref, RX VrefLevel [Byte0]: 81
1191 23:09:40.883459 [Byte1]: 81
1192 23:09:40.888045
1193 23:09:40.888128 Final RX Vref Byte 0 = 69 to rank0
1194 23:09:40.892182 Final RX Vref Byte 1 = 52 to rank0
1195 23:09:40.894992 Final RX Vref Byte 0 = 69 to rank1
1196 23:09:40.898581 Final RX Vref Byte 1 = 52 to rank1==
1197 23:09:40.902054 Dram Type= 6, Freq= 0, CH_0, rank 0
1198 23:09:40.905165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1199 23:09:40.905264 ==
1200 23:09:40.909561 DQS Delay:
1201 23:09:40.909659 DQS0 = 0, DQS1 = 0
1202 23:09:40.909757 DQM Delay:
1203 23:09:40.912878 DQM0 = 89, DQM1 = 75
1204 23:09:40.912980 DQ Delay:
1205 23:09:40.916608 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1206 23:09:40.920418 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =100
1207 23:09:40.923537 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1208 23:09:40.927315 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1209 23:09:40.927435
1210 23:09:40.927545
1211 23:09:40.934444 [DQSOSCAuto] RK0, (LSB)MR18= 0x4425, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
1212 23:09:40.938331 CH0 RK0: MR19=606, MR18=4425
1213 23:09:40.945314 CH0_RK0: MR19=0x606, MR18=0x4425, DQSOSC=392, MR23=63, INC=96, DEC=64
1214 23:09:40.945397
1215 23:09:40.949227 ----->DramcWriteLeveling(PI) begin...
1216 23:09:40.949311 ==
1217 23:09:40.949377 Dram Type= 6, Freq= 0, CH_0, rank 1
1218 23:09:40.956267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1219 23:09:40.956351 ==
1220 23:09:40.956417 Write leveling (Byte 0): 32 => 32
1221 23:09:40.959656 Write leveling (Byte 1): 31 => 31
1222 23:09:40.963604 DramcWriteLeveling(PI) end<-----
1223 23:09:40.963730
1224 23:09:40.963805 ==
1225 23:09:40.967060 Dram Type= 6, Freq= 0, CH_0, rank 1
1226 23:09:40.970650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1227 23:09:40.970746 ==
1228 23:09:40.974599 [Gating] SW mode calibration
1229 23:09:41.018505 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1230 23:09:41.018598 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1231 23:09:41.018677 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1232 23:09:41.019118 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1233 23:09:41.019634 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1234 23:09:41.020090 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:09:41.020172 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 23:09:41.020587 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 23:09:41.020947 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 23:09:41.063091 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 23:09:41.063411 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 23:09:41.063534 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 23:09:41.063611 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 23:09:41.064020 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 23:09:41.064622 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 23:09:41.064892 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 23:09:41.064964 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 23:09:41.065659 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 23:09:41.066193 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 23:09:41.106424 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1249 23:09:41.106520 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1250 23:09:41.106587 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 23:09:41.106858 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 23:09:41.107441 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 23:09:41.107537 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 23:09:41.107892 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 23:09:41.107988 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 23:09:41.108252 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 23:09:41.108318 0 9 8 | B1->B0 | 2322 3030 | 1 0 | (0 0) (0 0)
1258 23:09:41.150965 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1259 23:09:41.151239 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1260 23:09:41.151309 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1261 23:09:41.151586 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1262 23:09:41.151690 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1263 23:09:41.152455 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1264 23:09:41.152803 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1265 23:09:41.152885 0 10 8 | B1->B0 | 3131 2a2a | 1 0 | (1 0) (0 0)
1266 23:09:41.153618 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 23:09:41.153989 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1268 23:09:41.156786 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1269 23:09:41.159976 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1270 23:09:41.162895 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1271 23:09:41.166887 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1272 23:09:41.170275 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1273 23:09:41.177664 0 11 8 | B1->B0 | 2e2e 4141 | 0 1 | (0 0) (0 0)
1274 23:09:41.180775 0 11 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
1275 23:09:41.184385 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 23:09:41.188276 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1277 23:09:41.195788 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 23:09:41.198872 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1279 23:09:41.202785 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 23:09:41.205860 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1281 23:09:41.212056 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1282 23:09:41.215999 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 23:09:41.219031 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 23:09:41.225742 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 23:09:41.229217 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 23:09:41.232272 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 23:09:41.239113 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 23:09:41.241764 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 23:09:41.245522 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 23:09:41.252301 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 23:09:41.255247 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 23:09:41.258388 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 23:09:41.265071 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 23:09:41.268608 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 23:09:41.271495 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 23:09:41.278592 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1297 23:09:41.281612 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1298 23:09:41.285503 Total UI for P1: 0, mck2ui 16
1299 23:09:41.288253 best dqsien dly found for B0: ( 0, 14, 4)
1300 23:09:41.291865 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1301 23:09:41.295538 Total UI for P1: 0, mck2ui 16
1302 23:09:41.298551 best dqsien dly found for B1: ( 0, 14, 8)
1303 23:09:41.301672 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1304 23:09:41.306512 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1305 23:09:41.306594
1306 23:09:41.308216 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1307 23:09:41.312162 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1308 23:09:41.314918 [Gating] SW calibration Done
1309 23:09:41.314999 ==
1310 23:09:41.318145 Dram Type= 6, Freq= 0, CH_0, rank 1
1311 23:09:41.324836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1312 23:09:41.324919 ==
1313 23:09:41.324984 RX Vref Scan: 0
1314 23:09:41.325044
1315 23:09:41.327868 RX Vref 0 -> 0, step: 1
1316 23:09:41.327994
1317 23:09:41.331225 RX Delay -130 -> 252, step: 16
1318 23:09:41.334877 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1319 23:09:41.338190 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1320 23:09:41.341894 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1321 23:09:41.348406 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1322 23:09:41.351082 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1323 23:09:41.354916 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1324 23:09:41.357875 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1325 23:09:41.361094 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1326 23:09:41.367781 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1327 23:09:41.371325 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1328 23:09:41.374791 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1329 23:09:41.377733 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1330 23:09:41.381019 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1331 23:09:41.388101 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1332 23:09:41.391152 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1333 23:09:41.394611 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1334 23:09:41.394723 ==
1335 23:09:41.398362 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 23:09:41.401212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 23:09:41.404040 ==
1338 23:09:41.404150 DQS Delay:
1339 23:09:41.404230 DQS0 = 0, DQS1 = 0
1340 23:09:41.407547 DQM Delay:
1341 23:09:41.407632 DQM0 = 85, DQM1 = 77
1342 23:09:41.410947 DQ Delay:
1343 23:09:41.414460 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1344 23:09:41.417312 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1345 23:09:41.421146 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1346 23:09:41.424092 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1347 23:09:41.424173
1348 23:09:41.424238
1349 23:09:41.424297 ==
1350 23:09:41.427625 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 23:09:41.430795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1352 23:09:41.430877 ==
1353 23:09:41.430942
1354 23:09:41.431003
1355 23:09:41.433828 TX Vref Scan disable
1356 23:09:41.433910 == TX Byte 0 ==
1357 23:09:41.440382 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1358 23:09:41.444043 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1359 23:09:41.444160 == TX Byte 1 ==
1360 23:09:41.450472 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1361 23:09:41.453478 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1362 23:09:41.453560 ==
1363 23:09:41.456973 Dram Type= 6, Freq= 0, CH_0, rank 1
1364 23:09:41.460401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1365 23:09:41.460519 ==
1366 23:09:41.474496 TX Vref=22, minBit 1, minWin=27, winSum=443
1367 23:09:41.477409 TX Vref=24, minBit 8, minWin=27, winSum=446
1368 23:09:41.480877 TX Vref=26, minBit 9, minWin=27, winSum=447
1369 23:09:41.484203 TX Vref=28, minBit 9, minWin=27, winSum=447
1370 23:09:41.487383 TX Vref=30, minBit 9, minWin=27, winSum=448
1371 23:09:41.494315 TX Vref=32, minBit 9, minWin=27, winSum=447
1372 23:09:41.497447 [TxChooseVref] Worse bit 9, Min win 27, Win sum 448, Final Vref 30
1373 23:09:41.497561
1374 23:09:41.500848 Final TX Range 1 Vref 30
1375 23:09:41.500947
1376 23:09:41.501011 ==
1377 23:09:41.503864 Dram Type= 6, Freq= 0, CH_0, rank 1
1378 23:09:41.507475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1379 23:09:41.511032 ==
1380 23:09:41.511113
1381 23:09:41.511177
1382 23:09:41.511236 TX Vref Scan disable
1383 23:09:41.514871 == TX Byte 0 ==
1384 23:09:41.518020 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1385 23:09:41.524622 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1386 23:09:41.524704 == TX Byte 1 ==
1387 23:09:41.527910 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1388 23:09:41.534621 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1389 23:09:41.534703
1390 23:09:41.534766 [DATLAT]
1391 23:09:41.534826 Freq=800, CH0 RK1
1392 23:09:41.534884
1393 23:09:41.537959 DATLAT Default: 0xa
1394 23:09:41.538040 0, 0xFFFF, sum = 0
1395 23:09:41.540815 1, 0xFFFF, sum = 0
1396 23:09:41.540898 2, 0xFFFF, sum = 0
1397 23:09:41.544101 3, 0xFFFF, sum = 0
1398 23:09:41.547324 4, 0xFFFF, sum = 0
1399 23:09:41.547407 5, 0xFFFF, sum = 0
1400 23:09:41.550773 6, 0xFFFF, sum = 0
1401 23:09:41.550855 7, 0xFFFF, sum = 0
1402 23:09:41.554567 8, 0xFFFF, sum = 0
1403 23:09:41.554650 9, 0x0, sum = 1
1404 23:09:41.554715 10, 0x0, sum = 2
1405 23:09:41.557853 11, 0x0, sum = 3
1406 23:09:41.557971 12, 0x0, sum = 4
1407 23:09:41.561507 best_step = 10
1408 23:09:41.561598
1409 23:09:41.561663 ==
1410 23:09:41.564492 Dram Type= 6, Freq= 0, CH_0, rank 1
1411 23:09:41.567343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 23:09:41.567425 ==
1413 23:09:41.570785 RX Vref Scan: 0
1414 23:09:41.570879
1415 23:09:41.570942 RX Vref 0 -> 0, step: 1
1416 23:09:41.573859
1417 23:09:41.573936 RX Delay -111 -> 252, step: 8
1418 23:09:41.581604 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1419 23:09:41.584532 iDelay=217, Bit 1, Center 88 (-23 ~ 200) 224
1420 23:09:41.587435 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1421 23:09:41.590768 iDelay=217, Bit 3, Center 80 (-31 ~ 192) 224
1422 23:09:41.594194 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1423 23:09:41.601414 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1424 23:09:41.604154 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1425 23:09:41.607811 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1426 23:09:41.611073 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1427 23:09:41.614210 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1428 23:09:41.620931 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1429 23:09:41.624211 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1430 23:09:41.628479 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1431 23:09:41.630631 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1432 23:09:41.637527 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1433 23:09:41.640980 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1434 23:09:41.641062 ==
1435 23:09:41.643924 Dram Type= 6, Freq= 0, CH_0, rank 1
1436 23:09:41.647386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 23:09:41.647468 ==
1438 23:09:41.650624 DQS Delay:
1439 23:09:41.650705 DQS0 = 0, DQS1 = 0
1440 23:09:41.650770 DQM Delay:
1441 23:09:41.653766 DQM0 = 85, DQM1 = 77
1442 23:09:41.653847 DQ Delay:
1443 23:09:41.657260 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =80
1444 23:09:41.660935 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1445 23:09:41.663906 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1446 23:09:41.667528 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1447 23:09:41.667611
1448 23:09:41.667698
1449 23:09:41.677198 [DQSOSCAuto] RK1, (LSB)MR18= 0x4006, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1450 23:09:41.677284 CH0 RK1: MR19=606, MR18=4006
1451 23:09:41.684260 CH0_RK1: MR19=0x606, MR18=0x4006, DQSOSC=393, MR23=63, INC=95, DEC=63
1452 23:09:41.687299 [RxdqsGatingPostProcess] freq 800
1453 23:09:41.694104 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1454 23:09:41.697196 Pre-setting of DQS Precalculation
1455 23:09:41.701009 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1456 23:09:41.701092 ==
1457 23:09:41.703496 Dram Type= 6, Freq= 0, CH_1, rank 0
1458 23:09:41.710926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1459 23:09:41.711009 ==
1460 23:09:41.713545 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1461 23:09:41.720318 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1462 23:09:41.729513 [CA 0] Center 36 (6~67) winsize 62
1463 23:09:41.732781 [CA 1] Center 36 (6~67) winsize 62
1464 23:09:41.736309 [CA 2] Center 34 (4~65) winsize 62
1465 23:09:41.739270 [CA 3] Center 34 (3~65) winsize 63
1466 23:09:41.743086 [CA 4] Center 34 (4~65) winsize 62
1467 23:09:41.746443 [CA 5] Center 34 (3~65) winsize 63
1468 23:09:41.746516
1469 23:09:41.749323 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1470 23:09:41.749393
1471 23:09:41.752903 [CATrainingPosCal] consider 1 rank data
1472 23:09:41.755493 u2DelayCellTimex100 = 270/100 ps
1473 23:09:41.759160 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1474 23:09:41.765768 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1475 23:09:41.769590 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1476 23:09:41.772217 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1477 23:09:41.776045 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1478 23:09:41.779543 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1479 23:09:41.779623
1480 23:09:41.782648 CA PerBit enable=1, Macro0, CA PI delay=34
1481 23:09:41.782734
1482 23:09:41.786009 [CBTSetCACLKResult] CA Dly = 34
1483 23:09:41.786086 CS Dly: 5 (0~36)
1484 23:09:41.789128 ==
1485 23:09:41.792515 Dram Type= 6, Freq= 0, CH_1, rank 1
1486 23:09:41.795958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1487 23:09:41.796064 ==
1488 23:09:41.798977 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1489 23:09:41.805714 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1490 23:09:41.815923 [CA 0] Center 36 (6~67) winsize 62
1491 23:09:41.819324 [CA 1] Center 36 (6~67) winsize 62
1492 23:09:41.822232 [CA 2] Center 34 (4~65) winsize 62
1493 23:09:41.825719 [CA 3] Center 34 (3~65) winsize 63
1494 23:09:41.828926 [CA 4] Center 34 (4~65) winsize 62
1495 23:09:41.832883 [CA 5] Center 34 (3~65) winsize 63
1496 23:09:41.832959
1497 23:09:41.836408 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1498 23:09:41.836492
1499 23:09:41.838821 [CATrainingPosCal] consider 2 rank data
1500 23:09:41.842106 u2DelayCellTimex100 = 270/100 ps
1501 23:09:41.845610 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1502 23:09:41.848494 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1503 23:09:41.855838 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1504 23:09:41.858326 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1505 23:09:41.862530 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1506 23:09:41.865086 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1507 23:09:41.865165
1508 23:09:41.868849 CA PerBit enable=1, Macro0, CA PI delay=34
1509 23:09:41.868930
1510 23:09:41.872055 [CBTSetCACLKResult] CA Dly = 34
1511 23:09:41.872132 CS Dly: 6 (0~38)
1512 23:09:41.872214
1513 23:09:41.878796 ----->DramcWriteLeveling(PI) begin...
1514 23:09:41.878880 ==
1515 23:09:41.882004 Dram Type= 6, Freq= 0, CH_1, rank 0
1516 23:09:41.885197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1517 23:09:41.885283 ==
1518 23:09:41.888883 Write leveling (Byte 0): 25 => 25
1519 23:09:41.892093 Write leveling (Byte 1): 29 => 29
1520 23:09:41.895053 DramcWriteLeveling(PI) end<-----
1521 23:09:41.895130
1522 23:09:41.895211 ==
1523 23:09:41.898869 Dram Type= 6, Freq= 0, CH_1, rank 0
1524 23:09:41.901800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1525 23:09:41.901879 ==
1526 23:09:41.905613 [Gating] SW mode calibration
1527 23:09:41.911666 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1528 23:09:41.918582 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1529 23:09:41.921596 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1530 23:09:41.925175 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1531 23:09:41.931323 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:09:41.934682 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:09:41.938930 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:09:41.944950 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 23:09:41.947902 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:09:41.951750 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 23:09:41.958500 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 23:09:41.961601 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 23:09:41.964713 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 23:09:41.968110 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 23:09:41.974717 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 23:09:41.978559 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 23:09:41.981644 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 23:09:41.988202 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 23:09:41.991534 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 23:09:41.994892 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1547 23:09:42.001429 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1548 23:09:42.004586 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 23:09:42.007709 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 23:09:42.014529 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 23:09:42.018151 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 23:09:42.021248 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 23:09:42.027895 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 23:09:42.031378 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 23:09:42.034383 0 9 8 | B1->B0 | 2e2e 3131 | 0 0 | (0 0) (0 0)
1556 23:09:42.041102 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1557 23:09:42.044437 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1558 23:09:42.047557 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1559 23:09:42.054649 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1560 23:09:42.058866 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1561 23:09:42.060951 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1562 23:09:42.067753 0 10 4 | B1->B0 | 3434 3030 | 0 1 | (0 1) (1 0)
1563 23:09:42.071086 0 10 8 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
1564 23:09:42.074665 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 23:09:42.081364 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1566 23:09:42.084277 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1567 23:09:42.087741 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1568 23:09:42.094405 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1569 23:09:42.097354 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1570 23:09:42.100918 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1571 23:09:42.107647 0 11 8 | B1->B0 | 3a3a 4343 | 0 1 | (0 0) (0 0)
1572 23:09:42.110532 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 23:09:42.114194 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 23:09:42.121112 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 23:09:42.125042 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 23:09:42.127249 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1577 23:09:42.133979 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1578 23:09:42.137219 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1579 23:09:42.140292 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1580 23:09:42.146963 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 23:09:42.150785 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 23:09:42.154332 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 23:09:42.157020 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 23:09:42.163911 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 23:09:42.167464 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 23:09:42.170145 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 23:09:42.177119 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 23:09:42.180162 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 23:09:42.183785 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 23:09:42.190810 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 23:09:42.194071 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 23:09:42.197071 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 23:09:42.203525 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1594 23:09:42.207204 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1595 23:09:42.210251 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1596 23:09:42.213922 Total UI for P1: 0, mck2ui 16
1597 23:09:42.217186 best dqsien dly found for B0: ( 0, 14, 2)
1598 23:09:42.220400 Total UI for P1: 0, mck2ui 16
1599 23:09:42.223788 best dqsien dly found for B1: ( 0, 14, 2)
1600 23:09:42.227008 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1601 23:09:42.230250 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1602 23:09:42.230325
1603 23:09:42.237130 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1604 23:09:42.240227 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1605 23:09:42.240304 [Gating] SW calibration Done
1606 23:09:42.240392 ==
1607 23:09:42.243627 Dram Type= 6, Freq= 0, CH_1, rank 0
1608 23:09:42.250367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1609 23:09:42.250445 ==
1610 23:09:42.250526 RX Vref Scan: 0
1611 23:09:42.250612
1612 23:09:42.253056 RX Vref 0 -> 0, step: 1
1613 23:09:42.253161
1614 23:09:42.256322 RX Delay -130 -> 252, step: 16
1615 23:09:42.259705 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1616 23:09:42.263399 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1617 23:09:42.270179 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1618 23:09:42.272990 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1619 23:09:42.276492 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1620 23:09:42.279815 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1621 23:09:42.283370 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1622 23:09:42.289765 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1623 23:09:42.292853 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1624 23:09:42.296591 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1625 23:09:42.300195 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1626 23:09:42.303217 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1627 23:09:42.310061 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1628 23:09:42.312882 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1629 23:09:42.316312 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1630 23:09:42.319195 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1631 23:09:42.319269 ==
1632 23:09:42.322910 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 23:09:42.329726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 23:09:42.329803 ==
1635 23:09:42.329891 DQS Delay:
1636 23:09:42.332808 DQS0 = 0, DQS1 = 0
1637 23:09:42.332890 DQM Delay:
1638 23:09:42.332987 DQM0 = 89, DQM1 = 78
1639 23:09:42.336609 DQ Delay:
1640 23:09:42.339948 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1641 23:09:42.342939 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1642 23:09:42.345942 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1643 23:09:42.349318 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1644 23:09:42.349402
1645 23:09:42.349499
1646 23:09:42.349595 ==
1647 23:09:42.352944 Dram Type= 6, Freq= 0, CH_1, rank 0
1648 23:09:42.355758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1649 23:09:42.355832 ==
1650 23:09:42.355937
1651 23:09:42.356033
1652 23:09:42.359386 TX Vref Scan disable
1653 23:09:42.362742 == TX Byte 0 ==
1654 23:09:42.365822 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1655 23:09:42.369748 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1656 23:09:42.372903 == TX Byte 1 ==
1657 23:09:42.375585 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1658 23:09:42.379339 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1659 23:09:42.379444 ==
1660 23:09:42.382589 Dram Type= 6, Freq= 0, CH_1, rank 0
1661 23:09:42.385907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1662 23:09:42.388995 ==
1663 23:09:42.400778 TX Vref=22, minBit 10, minWin=26, winSum=436
1664 23:09:42.404181 TX Vref=24, minBit 3, minWin=27, winSum=443
1665 23:09:42.406865 TX Vref=26, minBit 0, minWin=27, winSum=444
1666 23:09:42.410295 TX Vref=28, minBit 9, minWin=27, winSum=445
1667 23:09:42.414437 TX Vref=30, minBit 8, minWin=27, winSum=446
1668 23:09:42.420471 TX Vref=32, minBit 8, minWin=27, winSum=443
1669 23:09:42.424021 [TxChooseVref] Worse bit 8, Min win 27, Win sum 446, Final Vref 30
1670 23:09:42.424102
1671 23:09:42.427305 Final TX Range 1 Vref 30
1672 23:09:42.427385
1673 23:09:42.427448 ==
1674 23:09:42.430577 Dram Type= 6, Freq= 0, CH_1, rank 0
1675 23:09:42.433533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1676 23:09:42.433614 ==
1677 23:09:42.437105
1678 23:09:42.437210
1679 23:09:42.437301 TX Vref Scan disable
1680 23:09:42.440451 == TX Byte 0 ==
1681 23:09:42.443589 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1682 23:09:42.450480 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1683 23:09:42.450560 == TX Byte 1 ==
1684 23:09:42.453506 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1685 23:09:42.460212 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1686 23:09:42.460293
1687 23:09:42.460358 [DATLAT]
1688 23:09:42.460418 Freq=800, CH1 RK0
1689 23:09:42.460475
1690 23:09:42.463423 DATLAT Default: 0xa
1691 23:09:42.463503 0, 0xFFFF, sum = 0
1692 23:09:42.467321 1, 0xFFFF, sum = 0
1693 23:09:42.467402 2, 0xFFFF, sum = 0
1694 23:09:42.469950 3, 0xFFFF, sum = 0
1695 23:09:42.473450 4, 0xFFFF, sum = 0
1696 23:09:42.473532 5, 0xFFFF, sum = 0
1697 23:09:42.476836 6, 0xFFFF, sum = 0
1698 23:09:42.476917 7, 0xFFFF, sum = 0
1699 23:09:42.480053 8, 0xFFFF, sum = 0
1700 23:09:42.480135 9, 0x0, sum = 1
1701 23:09:42.483854 10, 0x0, sum = 2
1702 23:09:42.483936 11, 0x0, sum = 3
1703 23:09:42.484000 12, 0x0, sum = 4
1704 23:09:42.486671 best_step = 10
1705 23:09:42.486750
1706 23:09:42.486813 ==
1707 23:09:42.489855 Dram Type= 6, Freq= 0, CH_1, rank 0
1708 23:09:42.493350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1709 23:09:42.493433 ==
1710 23:09:42.496534 RX Vref Scan: 1
1711 23:09:42.496612
1712 23:09:42.499773 Set Vref Range= 32 -> 127
1713 23:09:42.499851
1714 23:09:42.499933 RX Vref 32 -> 127, step: 1
1715 23:09:42.500017
1716 23:09:42.503403 RX Delay -95 -> 252, step: 8
1717 23:09:42.503484
1718 23:09:42.506660 Set Vref, RX VrefLevel [Byte0]: 32
1719 23:09:42.510024 [Byte1]: 32
1720 23:09:42.513412
1721 23:09:42.513494 Set Vref, RX VrefLevel [Byte0]: 33
1722 23:09:42.517459 [Byte1]: 33
1723 23:09:42.521296
1724 23:09:42.521369 Set Vref, RX VrefLevel [Byte0]: 34
1725 23:09:42.524067 [Byte1]: 34
1726 23:09:42.528192
1727 23:09:42.528270 Set Vref, RX VrefLevel [Byte0]: 35
1728 23:09:42.531759 [Byte1]: 35
1729 23:09:42.535937
1730 23:09:42.536030 Set Vref, RX VrefLevel [Byte0]: 36
1731 23:09:42.539517 [Byte1]: 36
1732 23:09:42.543661
1733 23:09:42.543780 Set Vref, RX VrefLevel [Byte0]: 37
1734 23:09:42.546742 [Byte1]: 37
1735 23:09:42.551040
1736 23:09:42.551119 Set Vref, RX VrefLevel [Byte0]: 38
1737 23:09:42.554929 [Byte1]: 38
1738 23:09:42.558982
1739 23:09:42.559062 Set Vref, RX VrefLevel [Byte0]: 39
1740 23:09:42.561964 [Byte1]: 39
1741 23:09:42.566980
1742 23:09:42.567060 Set Vref, RX VrefLevel [Byte0]: 40
1743 23:09:42.569718 [Byte1]: 40
1744 23:09:42.573877
1745 23:09:42.573960 Set Vref, RX VrefLevel [Byte0]: 41
1746 23:09:42.579988 [Byte1]: 41
1747 23:09:42.580068
1748 23:09:42.583424 Set Vref, RX VrefLevel [Byte0]: 42
1749 23:09:42.586990 [Byte1]: 42
1750 23:09:42.587070
1751 23:09:42.590447 Set Vref, RX VrefLevel [Byte0]: 43
1752 23:09:42.593972 [Byte1]: 43
1753 23:09:42.596754
1754 23:09:42.596834 Set Vref, RX VrefLevel [Byte0]: 44
1755 23:09:42.600153 [Byte1]: 44
1756 23:09:42.604657
1757 23:09:42.604736 Set Vref, RX VrefLevel [Byte0]: 45
1758 23:09:42.607415 [Byte1]: 45
1759 23:09:42.611612
1760 23:09:42.611731 Set Vref, RX VrefLevel [Byte0]: 46
1761 23:09:42.614907 [Byte1]: 46
1762 23:09:42.620114
1763 23:09:42.620193 Set Vref, RX VrefLevel [Byte0]: 47
1764 23:09:42.622853 [Byte1]: 47
1765 23:09:42.626978
1766 23:09:42.627058 Set Vref, RX VrefLevel [Byte0]: 48
1767 23:09:42.630423 [Byte1]: 48
1768 23:09:42.635408
1769 23:09:42.635559 Set Vref, RX VrefLevel [Byte0]: 49
1770 23:09:42.638029 [Byte1]: 49
1771 23:09:42.642620
1772 23:09:42.642700 Set Vref, RX VrefLevel [Byte0]: 50
1773 23:09:42.646103 [Byte1]: 50
1774 23:09:42.649955
1775 23:09:42.650035 Set Vref, RX VrefLevel [Byte0]: 51
1776 23:09:42.653311 [Byte1]: 51
1777 23:09:42.657403
1778 23:09:42.657530 Set Vref, RX VrefLevel [Byte0]: 52
1779 23:09:42.660685 [Byte1]: 52
1780 23:09:42.664840
1781 23:09:42.664920 Set Vref, RX VrefLevel [Byte0]: 53
1782 23:09:42.668556 [Byte1]: 53
1783 23:09:42.672861
1784 23:09:42.672942 Set Vref, RX VrefLevel [Byte0]: 54
1785 23:09:42.679205 [Byte1]: 54
1786 23:09:42.679285
1787 23:09:42.682441 Set Vref, RX VrefLevel [Byte0]: 55
1788 23:09:42.685765 [Byte1]: 55
1789 23:09:42.685845
1790 23:09:42.688963 Set Vref, RX VrefLevel [Byte0]: 56
1791 23:09:42.692482 [Byte1]: 56
1792 23:09:42.692563
1793 23:09:42.695458 Set Vref, RX VrefLevel [Byte0]: 57
1794 23:09:42.698823 [Byte1]: 57
1795 23:09:42.702910
1796 23:09:42.702990 Set Vref, RX VrefLevel [Byte0]: 58
1797 23:09:42.706533 [Byte1]: 58
1798 23:09:42.711071
1799 23:09:42.711178 Set Vref, RX VrefLevel [Byte0]: 59
1800 23:09:42.713728 [Byte1]: 59
1801 23:09:42.718675
1802 23:09:42.718780 Set Vref, RX VrefLevel [Byte0]: 60
1803 23:09:42.721348 [Byte1]: 60
1804 23:09:42.725953
1805 23:09:42.726033 Set Vref, RX VrefLevel [Byte0]: 61
1806 23:09:42.729146 [Byte1]: 61
1807 23:09:42.733203
1808 23:09:42.733282 Set Vref, RX VrefLevel [Byte0]: 62
1809 23:09:42.736568 [Byte1]: 62
1810 23:09:42.740779
1811 23:09:42.740859 Set Vref, RX VrefLevel [Byte0]: 63
1812 23:09:42.744225 [Byte1]: 63
1813 23:09:42.748386
1814 23:09:42.748466 Set Vref, RX VrefLevel [Byte0]: 64
1815 23:09:42.751586 [Byte1]: 64
1816 23:09:42.755909
1817 23:09:42.755993 Set Vref, RX VrefLevel [Byte0]: 65
1818 23:09:42.760206 [Byte1]: 65
1819 23:09:42.764502
1820 23:09:42.764577 Set Vref, RX VrefLevel [Byte0]: 66
1821 23:09:42.767292 [Byte1]: 66
1822 23:09:42.771288
1823 23:09:42.771390 Set Vref, RX VrefLevel [Byte0]: 67
1824 23:09:42.774596 [Byte1]: 67
1825 23:09:42.779171
1826 23:09:42.779252 Set Vref, RX VrefLevel [Byte0]: 68
1827 23:09:42.782239 [Byte1]: 68
1828 23:09:42.786602
1829 23:09:42.786703 Set Vref, RX VrefLevel [Byte0]: 69
1830 23:09:42.789600 [Byte1]: 69
1831 23:09:42.794066
1832 23:09:42.794142 Set Vref, RX VrefLevel [Byte0]: 70
1833 23:09:42.797710 [Byte1]: 70
1834 23:09:42.801638
1835 23:09:42.801706 Set Vref, RX VrefLevel [Byte0]: 71
1836 23:09:42.805309 [Byte1]: 71
1837 23:09:42.810083
1838 23:09:42.810150 Set Vref, RX VrefLevel [Byte0]: 72
1839 23:09:42.812576 [Byte1]: 72
1840 23:09:42.816935
1841 23:09:42.817006 Set Vref, RX VrefLevel [Byte0]: 73
1842 23:09:42.820035 [Byte1]: 73
1843 23:09:42.824697
1844 23:09:42.824774 Set Vref, RX VrefLevel [Byte0]: 74
1845 23:09:42.827613 [Byte1]: 74
1846 23:09:42.832051
1847 23:09:42.832123 Set Vref, RX VrefLevel [Byte0]: 75
1848 23:09:42.835762 [Byte1]: 75
1849 23:09:42.840052
1850 23:09:42.840119 Set Vref, RX VrefLevel [Byte0]: 76
1851 23:09:42.843364 [Byte1]: 76
1852 23:09:42.847675
1853 23:09:42.847762 Set Vref, RX VrefLevel [Byte0]: 77
1854 23:09:42.851200 [Byte1]: 77
1855 23:09:42.855124
1856 23:09:42.855190 Set Vref, RX VrefLevel [Byte0]: 78
1857 23:09:42.858209 [Byte1]: 78
1858 23:09:42.863260
1859 23:09:42.863334 Final RX Vref Byte 0 = 54 to rank0
1860 23:09:42.865893 Final RX Vref Byte 1 = 66 to rank0
1861 23:09:42.869113 Final RX Vref Byte 0 = 54 to rank1
1862 23:09:42.872560 Final RX Vref Byte 1 = 66 to rank1==
1863 23:09:42.875612 Dram Type= 6, Freq= 0, CH_1, rank 0
1864 23:09:42.882722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1865 23:09:42.882802 ==
1866 23:09:42.882864 DQS Delay:
1867 23:09:42.885758 DQS0 = 0, DQS1 = 0
1868 23:09:42.885833 DQM Delay:
1869 23:09:42.885895 DQM0 = 86, DQM1 = 78
1870 23:09:42.889252 DQ Delay:
1871 23:09:42.892177 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1872 23:09:42.895907 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =80
1873 23:09:42.898970 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
1874 23:09:42.902104 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1875 23:09:42.902178
1876 23:09:42.902264
1877 23:09:42.908922 [DQSOSCAuto] RK0, (LSB)MR18= 0x311d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1878 23:09:42.911938 CH1 RK0: MR19=606, MR18=311D
1879 23:09:42.919171 CH1_RK0: MR19=0x606, MR18=0x311D, DQSOSC=397, MR23=63, INC=93, DEC=62
1880 23:09:42.919253
1881 23:09:42.921903 ----->DramcWriteLeveling(PI) begin...
1882 23:09:42.921984 ==
1883 23:09:42.925350 Dram Type= 6, Freq= 0, CH_1, rank 1
1884 23:09:42.928689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1885 23:09:42.928772 ==
1886 23:09:42.931613 Write leveling (Byte 0): 28 => 28
1887 23:09:42.935209 Write leveling (Byte 1): 31 => 31
1888 23:09:42.938327 DramcWriteLeveling(PI) end<-----
1889 23:09:42.938404
1890 23:09:42.938490 ==
1891 23:09:42.941923 Dram Type= 6, Freq= 0, CH_1, rank 1
1892 23:09:42.945180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1893 23:09:42.945259 ==
1894 23:09:42.948370 [Gating] SW mode calibration
1895 23:09:42.955355 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1896 23:09:42.961835 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1897 23:09:42.965009 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1898 23:09:42.971862 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1899 23:09:42.974932 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 23:09:42.978149 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 23:09:42.984847 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 23:09:42.988726 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 23:09:42.991600 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 23:09:42.998274 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 23:09:43.001479 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 23:09:43.005204 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 23:09:43.008046 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 23:09:43.015278 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 23:09:43.018596 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 23:09:43.021531 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 23:09:43.028463 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 23:09:43.032333 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 23:09:43.034691 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 23:09:43.041792 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1915 23:09:43.045377 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 23:09:43.048368 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 23:09:43.055346 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 23:09:43.058571 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 23:09:43.062056 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 23:09:43.068511 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 23:09:43.071441 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 23:09:43.074880 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 23:09:43.081763 0 9 8 | B1->B0 | 3131 2a2a | 0 1 | (0 0) (0 0)
1924 23:09:43.085389 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1925 23:09:43.088253 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1926 23:09:43.094851 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1927 23:09:43.098037 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1928 23:09:43.101193 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1929 23:09:43.108094 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1930 23:09:43.111530 0 10 4 | B1->B0 | 2f2f 3333 | 0 1 | (0 1) (1 0)
1931 23:09:43.114774 0 10 8 | B1->B0 | 2727 2f2f | 0 0 | (0 0) (0 0)
1932 23:09:43.122020 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1933 23:09:43.124799 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1934 23:09:43.127783 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1935 23:09:43.134547 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1936 23:09:43.137779 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1937 23:09:43.141098 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1938 23:09:43.147895 0 11 4 | B1->B0 | 2d2d 2626 | 1 0 | (0 0) (0 0)
1939 23:09:43.151889 0 11 8 | B1->B0 | 3d3d 3c3c | 0 0 | (0 0) (0 0)
1940 23:09:43.154172 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1941 23:09:43.157659 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1942 23:09:43.164392 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1943 23:09:43.168119 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1944 23:09:43.170755 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1945 23:09:43.177698 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1946 23:09:43.181196 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1947 23:09:43.184613 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1948 23:09:43.190462 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 23:09:43.193999 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 23:09:43.197893 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 23:09:43.203839 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 23:09:43.207402 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 23:09:43.211017 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 23:09:43.217640 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1955 23:09:43.220514 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1956 23:09:43.224493 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1957 23:09:43.230505 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1958 23:09:43.233782 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1959 23:09:43.237733 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1960 23:09:43.243871 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1961 23:09:43.247421 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1962 23:09:43.250845 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1963 23:09:43.256949 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1964 23:09:43.257031 Total UI for P1: 0, mck2ui 16
1965 23:09:43.263552 best dqsien dly found for B0: ( 0, 14, 6)
1966 23:09:43.263655 Total UI for P1: 0, mck2ui 16
1967 23:09:43.270216 best dqsien dly found for B1: ( 0, 14, 4)
1968 23:09:43.273734 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1969 23:09:43.276978 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1970 23:09:43.277055
1971 23:09:43.280216 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1972 23:09:43.283499 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1973 23:09:43.287137 [Gating] SW calibration Done
1974 23:09:43.287213 ==
1975 23:09:43.290109 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 23:09:43.293364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 23:09:43.293445 ==
1978 23:09:43.296926 RX Vref Scan: 0
1979 23:09:43.297007
1980 23:09:43.297070 RX Vref 0 -> 0, step: 1
1981 23:09:43.297129
1982 23:09:43.300623 RX Delay -130 -> 252, step: 16
1983 23:09:43.303259 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1984 23:09:43.310188 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1985 23:09:43.313174 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1986 23:09:43.316939 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1987 23:09:43.319744 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1988 23:09:43.323451 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1989 23:09:43.329754 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1990 23:09:43.333613 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1991 23:09:43.336328 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1992 23:09:43.339766 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1993 23:09:43.343102 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1994 23:09:43.349475 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1995 23:09:43.353224 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1996 23:09:43.356387 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1997 23:09:43.360016 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1998 23:09:43.366485 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1999 23:09:43.366565 ==
2000 23:09:43.370142 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 23:09:43.373591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 23:09:43.373671 ==
2003 23:09:43.373734 DQS Delay:
2004 23:09:43.376408 DQS0 = 0, DQS1 = 0
2005 23:09:43.376488 DQM Delay:
2006 23:09:43.379457 DQM0 = 88, DQM1 = 80
2007 23:09:43.379575 DQ Delay:
2008 23:09:43.382631 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
2009 23:09:43.386461 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2010 23:09:43.389479 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
2011 23:09:43.392618 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
2012 23:09:43.392696
2013 23:09:43.392780
2014 23:09:43.392856 ==
2015 23:09:43.395755 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 23:09:43.399122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 23:09:43.402629 ==
2018 23:09:43.402703
2019 23:09:43.402786
2020 23:09:43.402861 TX Vref Scan disable
2021 23:09:43.405896 == TX Byte 0 ==
2022 23:09:43.409603 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2023 23:09:43.413077 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2024 23:09:43.415969 == TX Byte 1 ==
2025 23:09:43.419717 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2026 23:09:43.423135 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2027 23:09:43.425729 ==
2028 23:09:43.425808 Dram Type= 6, Freq= 0, CH_1, rank 1
2029 23:09:43.432676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2030 23:09:43.432758 ==
2031 23:09:43.444846 TX Vref=22, minBit 9, minWin=26, winSum=445
2032 23:09:43.448566 TX Vref=24, minBit 8, minWin=27, winSum=447
2033 23:09:43.451806 TX Vref=26, minBit 8, minWin=27, winSum=450
2034 23:09:43.454560 TX Vref=28, minBit 8, minWin=27, winSum=449
2035 23:09:43.458313 TX Vref=30, minBit 8, minWin=27, winSum=451
2036 23:09:43.464661 TX Vref=32, minBit 8, minWin=27, winSum=451
2037 23:09:43.468013 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 30
2038 23:09:43.468093
2039 23:09:43.471576 Final TX Range 1 Vref 30
2040 23:09:43.471653
2041 23:09:43.471776 ==
2042 23:09:43.474697 Dram Type= 6, Freq= 0, CH_1, rank 1
2043 23:09:43.478162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2044 23:09:43.478243 ==
2045 23:09:43.481286
2046 23:09:43.481359
2047 23:09:43.481438 TX Vref Scan disable
2048 23:09:43.485061 == TX Byte 0 ==
2049 23:09:43.488162 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2050 23:09:43.494861 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2051 23:09:43.494938 == TX Byte 1 ==
2052 23:09:43.498190 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2053 23:09:43.504755 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2054 23:09:43.504834
2055 23:09:43.504915 [DATLAT]
2056 23:09:43.504997 Freq=800, CH1 RK1
2057 23:09:43.505073
2058 23:09:43.508218 DATLAT Default: 0xa
2059 23:09:43.508295 0, 0xFFFF, sum = 0
2060 23:09:43.511217 1, 0xFFFF, sum = 0
2061 23:09:43.514884 2, 0xFFFF, sum = 0
2062 23:09:43.514956 3, 0xFFFF, sum = 0
2063 23:09:43.517937 4, 0xFFFF, sum = 0
2064 23:09:43.518015 5, 0xFFFF, sum = 0
2065 23:09:43.521294 6, 0xFFFF, sum = 0
2066 23:09:43.521366 7, 0xFFFF, sum = 0
2067 23:09:43.524329 8, 0xFFFF, sum = 0
2068 23:09:43.524402 9, 0x0, sum = 1
2069 23:09:43.527764 10, 0x0, sum = 2
2070 23:09:43.527835 11, 0x0, sum = 3
2071 23:09:43.527913 12, 0x0, sum = 4
2072 23:09:43.531256 best_step = 10
2073 23:09:43.531331
2074 23:09:43.531409 ==
2075 23:09:43.534341 Dram Type= 6, Freq= 0, CH_1, rank 1
2076 23:09:43.537899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2077 23:09:43.537980 ==
2078 23:09:43.541392 RX Vref Scan: 0
2079 23:09:43.541466
2080 23:09:43.541549 RX Vref 0 -> 0, step: 1
2081 23:09:43.544524
2082 23:09:43.544604 RX Delay -95 -> 252, step: 8
2083 23:09:43.551624 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2084 23:09:43.554709 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2085 23:09:43.558250 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2086 23:09:43.562220 iDelay=217, Bit 3, Center 88 (-23 ~ 200) 224
2087 23:09:43.564731 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2088 23:09:43.571323 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2089 23:09:43.574595 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2090 23:09:43.577819 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2091 23:09:43.581298 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2092 23:09:43.587512 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2093 23:09:43.591225 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
2094 23:09:43.594302 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2095 23:09:43.598120 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2096 23:09:43.600912 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2097 23:09:43.607812 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2098 23:09:43.611532 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2099 23:09:43.611632 ==
2100 23:09:43.614475 Dram Type= 6, Freq= 0, CH_1, rank 1
2101 23:09:43.618004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2102 23:09:43.618088 ==
2103 23:09:43.620942 DQS Delay:
2104 23:09:43.621024 DQS0 = 0, DQS1 = 0
2105 23:09:43.621089 DQM Delay:
2106 23:09:43.624050 DQM0 = 87, DQM1 = 77
2107 23:09:43.624132 DQ Delay:
2108 23:09:43.627403 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =88
2109 23:09:43.630904 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2110 23:09:43.634360 DQ8 =68, DQ9 =68, DQ10 =76, DQ11 =68
2111 23:09:43.637530 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2112 23:09:43.637611
2113 23:09:43.637675
2114 23:09:43.648075 [DQSOSCAuto] RK1, (LSB)MR18= 0x1811, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2115 23:09:43.650813 CH1 RK1: MR19=606, MR18=1811
2116 23:09:43.654500 CH1_RK1: MR19=0x606, MR18=0x1811, DQSOSC=403, MR23=63, INC=90, DEC=60
2117 23:09:43.657829 [RxdqsGatingPostProcess] freq 800
2118 23:09:43.663916 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2119 23:09:43.667667 Pre-setting of DQS Precalculation
2120 23:09:43.670707 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2121 23:09:43.680612 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2122 23:09:43.687367 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2123 23:09:43.687449
2124 23:09:43.687514
2125 23:09:43.691122 [Calibration Summary] 1600 Mbps
2126 23:09:43.691203 CH 0, Rank 0
2127 23:09:43.694243 SW Impedance : PASS
2128 23:09:43.694325 DUTY Scan : NO K
2129 23:09:43.697307 ZQ Calibration : PASS
2130 23:09:43.700930 Jitter Meter : NO K
2131 23:09:43.701011 CBT Training : PASS
2132 23:09:43.704266 Write leveling : PASS
2133 23:09:43.707640 RX DQS gating : PASS
2134 23:09:43.707747 RX DQ/DQS(RDDQC) : PASS
2135 23:09:43.710875 TX DQ/DQS : PASS
2136 23:09:43.710957 RX DATLAT : PASS
2137 23:09:43.714001 RX DQ/DQS(Engine): PASS
2138 23:09:43.717007 TX OE : NO K
2139 23:09:43.717088 All Pass.
2140 23:09:43.717153
2141 23:09:43.717244 CH 0, Rank 1
2142 23:09:43.720462 SW Impedance : PASS
2143 23:09:43.724335 DUTY Scan : NO K
2144 23:09:43.724417 ZQ Calibration : PASS
2145 23:09:43.727484 Jitter Meter : NO K
2146 23:09:43.731095 CBT Training : PASS
2147 23:09:43.731177 Write leveling : PASS
2148 23:09:43.733577 RX DQS gating : PASS
2149 23:09:43.736869 RX DQ/DQS(RDDQC) : PASS
2150 23:09:43.736950 TX DQ/DQS : PASS
2151 23:09:43.740412 RX DATLAT : PASS
2152 23:09:43.743874 RX DQ/DQS(Engine): PASS
2153 23:09:43.743955 TX OE : NO K
2154 23:09:43.746941 All Pass.
2155 23:09:43.747022
2156 23:09:43.747086 CH 1, Rank 0
2157 23:09:43.750755 SW Impedance : PASS
2158 23:09:43.750837 DUTY Scan : NO K
2159 23:09:43.753461 ZQ Calibration : PASS
2160 23:09:43.757179 Jitter Meter : NO K
2161 23:09:43.757261 CBT Training : PASS
2162 23:09:43.760516 Write leveling : PASS
2163 23:09:43.763994 RX DQS gating : PASS
2164 23:09:43.764076 RX DQ/DQS(RDDQC) : PASS
2165 23:09:43.767020 TX DQ/DQS : PASS
2166 23:09:43.767101 RX DATLAT : PASS
2167 23:09:43.770714 RX DQ/DQS(Engine): PASS
2168 23:09:43.773687 TX OE : NO K
2169 23:09:43.773769 All Pass.
2170 23:09:43.773832
2171 23:09:43.773892 CH 1, Rank 1
2172 23:09:43.777041 SW Impedance : PASS
2173 23:09:43.780464 DUTY Scan : NO K
2174 23:09:43.780545 ZQ Calibration : PASS
2175 23:09:43.783469 Jitter Meter : NO K
2176 23:09:43.786928 CBT Training : PASS
2177 23:09:43.787010 Write leveling : PASS
2178 23:09:43.789860 RX DQS gating : PASS
2179 23:09:43.793753 RX DQ/DQS(RDDQC) : PASS
2180 23:09:43.793835 TX DQ/DQS : PASS
2181 23:09:43.796833 RX DATLAT : PASS
2182 23:09:43.800022 RX DQ/DQS(Engine): PASS
2183 23:09:43.800103 TX OE : NO K
2184 23:09:43.803118 All Pass.
2185 23:09:43.803199
2186 23:09:43.803264 DramC Write-DBI off
2187 23:09:43.807170 PER_BANK_REFRESH: Hybrid Mode
2188 23:09:43.807252 TX_TRACKING: ON
2189 23:09:43.810189 [GetDramInforAfterCalByMRR] Vendor 6.
2190 23:09:43.816655 [GetDramInforAfterCalByMRR] Revision 606.
2191 23:09:43.819943 [GetDramInforAfterCalByMRR] Revision 2 0.
2192 23:09:43.820025 MR0 0x3b3b
2193 23:09:43.820091 MR8 0x5151
2194 23:09:43.823652 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2195 23:09:43.823777
2196 23:09:43.826981 MR0 0x3b3b
2197 23:09:43.827087 MR8 0x5151
2198 23:09:43.830557 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2199 23:09:43.830639
2200 23:09:43.839625 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2201 23:09:43.843254 [FAST_K] Save calibration result to emmc
2202 23:09:43.846476 [FAST_K] Save calibration result to emmc
2203 23:09:43.849425 dram_init: config_dvfs: 1
2204 23:09:43.852797 dramc_set_vcore_voltage set vcore to 662500
2205 23:09:43.856156 Read voltage for 1200, 2
2206 23:09:43.856239 Vio18 = 0
2207 23:09:43.856338 Vcore = 662500
2208 23:09:43.859323 Vdram = 0
2209 23:09:43.859408 Vddq = 0
2210 23:09:43.859506 Vmddr = 0
2211 23:09:43.866490 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2212 23:09:43.869742 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2213 23:09:43.872642 MEM_TYPE=3, freq_sel=15
2214 23:09:43.875892 sv_algorithm_assistance_LP4_1600
2215 23:09:43.879700 ============ PULL DRAM RESETB DOWN ============
2216 23:09:43.882449 ========== PULL DRAM RESETB DOWN end =========
2217 23:09:43.889241 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2218 23:09:43.892769 ===================================
2219 23:09:43.895781 LPDDR4 DRAM CONFIGURATION
2220 23:09:43.899192 ===================================
2221 23:09:43.899294 EX_ROW_EN[0] = 0x0
2222 23:09:43.903162 EX_ROW_EN[1] = 0x0
2223 23:09:43.903252 LP4Y_EN = 0x0
2224 23:09:43.906063 WORK_FSP = 0x0
2225 23:09:43.906167 WL = 0x4
2226 23:09:43.909413 RL = 0x4
2227 23:09:43.909489 BL = 0x2
2228 23:09:43.912738 RPST = 0x0
2229 23:09:43.912830 RD_PRE = 0x0
2230 23:09:43.916212 WR_PRE = 0x1
2231 23:09:43.916286 WR_PST = 0x0
2232 23:09:43.919823 DBI_WR = 0x0
2233 23:09:43.919900 DBI_RD = 0x0
2234 23:09:43.922720 OTF = 0x1
2235 23:09:43.925523 ===================================
2236 23:09:43.929147 ===================================
2237 23:09:43.929221 ANA top config
2238 23:09:43.932853 ===================================
2239 23:09:43.935659 DLL_ASYNC_EN = 0
2240 23:09:43.938818 ALL_SLAVE_EN = 0
2241 23:09:43.942307 NEW_RANK_MODE = 1
2242 23:09:43.942382 DLL_IDLE_MODE = 1
2243 23:09:43.946063 LP45_APHY_COMB_EN = 1
2244 23:09:43.949535 TX_ODT_DIS = 1
2245 23:09:43.952241 NEW_8X_MODE = 1
2246 23:09:43.955607 ===================================
2247 23:09:43.959271 ===================================
2248 23:09:43.962368 data_rate = 2400
2249 23:09:43.965232 CKR = 1
2250 23:09:43.965309 DQ_P2S_RATIO = 8
2251 23:09:43.968798 ===================================
2252 23:09:43.972493 CA_P2S_RATIO = 8
2253 23:09:43.975243 DQ_CA_OPEN = 0
2254 23:09:43.978833 DQ_SEMI_OPEN = 0
2255 23:09:43.982028 CA_SEMI_OPEN = 0
2256 23:09:43.985738 CA_FULL_RATE = 0
2257 23:09:43.985825 DQ_CKDIV4_EN = 0
2258 23:09:43.988881 CA_CKDIV4_EN = 0
2259 23:09:43.992515 CA_PREDIV_EN = 0
2260 23:09:43.995621 PH8_DLY = 17
2261 23:09:43.998956 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2262 23:09:44.002375 DQ_AAMCK_DIV = 4
2263 23:09:44.002458 CA_AAMCK_DIV = 4
2264 23:09:44.005553 CA_ADMCK_DIV = 4
2265 23:09:44.008788 DQ_TRACK_CA_EN = 0
2266 23:09:44.011702 CA_PICK = 1200
2267 23:09:44.015158 CA_MCKIO = 1200
2268 23:09:44.018225 MCKIO_SEMI = 0
2269 23:09:44.021592 PLL_FREQ = 2366
2270 23:09:44.021671 DQ_UI_PI_RATIO = 32
2271 23:09:44.025495 CA_UI_PI_RATIO = 0
2272 23:09:44.028586 ===================================
2273 23:09:44.031613 ===================================
2274 23:09:44.034951 memory_type:LPDDR4
2275 23:09:44.038341 GP_NUM : 10
2276 23:09:44.038415 SRAM_EN : 1
2277 23:09:44.041914 MD32_EN : 0
2278 23:09:44.045729 ===================================
2279 23:09:44.048034 [ANA_INIT] >>>>>>>>>>>>>>
2280 23:09:44.048137 <<<<<< [CONFIGURE PHASE]: ANA_TX
2281 23:09:44.051611 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2282 23:09:44.055034 ===================================
2283 23:09:44.058465 data_rate = 2400,PCW = 0X5b00
2284 23:09:44.061771 ===================================
2285 23:09:44.065585 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2286 23:09:44.071684 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2287 23:09:44.078605 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2288 23:09:44.081464 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2289 23:09:44.084559 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2290 23:09:44.088040 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2291 23:09:44.091698 [ANA_INIT] flow start
2292 23:09:44.091783 [ANA_INIT] PLL >>>>>>>>
2293 23:09:44.094717 [ANA_INIT] PLL <<<<<<<<
2294 23:09:44.098203 [ANA_INIT] MIDPI >>>>>>>>
2295 23:09:44.101417 [ANA_INIT] MIDPI <<<<<<<<
2296 23:09:44.101504 [ANA_INIT] DLL >>>>>>>>
2297 23:09:44.104807 [ANA_INIT] DLL <<<<<<<<
2298 23:09:44.104884 [ANA_INIT] flow end
2299 23:09:44.111424 ============ LP4 DIFF to SE enter ============
2300 23:09:44.114577 ============ LP4 DIFF to SE exit ============
2301 23:09:44.117844 [ANA_INIT] <<<<<<<<<<<<<
2302 23:09:44.121385 [Flow] Enable top DCM control >>>>>
2303 23:09:44.124872 [Flow] Enable top DCM control <<<<<
2304 23:09:44.124955 Enable DLL master slave shuffle
2305 23:09:44.131564 ==============================================================
2306 23:09:44.134609 Gating Mode config
2307 23:09:44.138170 ==============================================================
2308 23:09:44.141055 Config description:
2309 23:09:44.150975 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2310 23:09:44.157475 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2311 23:09:44.161334 SELPH_MODE 0: By rank 1: By Phase
2312 23:09:44.167666 ==============================================================
2313 23:09:44.170908 GAT_TRACK_EN = 1
2314 23:09:44.174341 RX_GATING_MODE = 2
2315 23:09:44.178278 RX_GATING_TRACK_MODE = 2
2316 23:09:44.181166 SELPH_MODE = 1
2317 23:09:44.181250 PICG_EARLY_EN = 1
2318 23:09:44.184418 VALID_LAT_VALUE = 1
2319 23:09:44.191467 ==============================================================
2320 23:09:44.194336 Enter into Gating configuration >>>>
2321 23:09:44.197731 Exit from Gating configuration <<<<
2322 23:09:44.201033 Enter into DVFS_PRE_config >>>>>
2323 23:09:44.211240 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2324 23:09:44.214692 Exit from DVFS_PRE_config <<<<<
2325 23:09:44.217597 Enter into PICG configuration >>>>
2326 23:09:44.220879 Exit from PICG configuration <<<<
2327 23:09:44.224568 [RX_INPUT] configuration >>>>>
2328 23:09:44.227237 [RX_INPUT] configuration <<<<<
2329 23:09:44.231046 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2330 23:09:44.238041 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2331 23:09:44.243897 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2332 23:09:44.250481 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2333 23:09:44.257175 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2334 23:09:44.264075 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2335 23:09:44.267368 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2336 23:09:44.271265 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2337 23:09:44.273929 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2338 23:09:44.280574 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2339 23:09:44.283609 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2340 23:09:44.287531 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2341 23:09:44.290352 ===================================
2342 23:09:44.293487 LPDDR4 DRAM CONFIGURATION
2343 23:09:44.297377 ===================================
2344 23:09:44.297480 EX_ROW_EN[0] = 0x0
2345 23:09:44.300240 EX_ROW_EN[1] = 0x0
2346 23:09:44.300338 LP4Y_EN = 0x0
2347 23:09:44.303761 WORK_FSP = 0x0
2348 23:09:44.303833 WL = 0x4
2349 23:09:44.307136 RL = 0x4
2350 23:09:44.310375 BL = 0x2
2351 23:09:44.310473 RPST = 0x0
2352 23:09:44.314006 RD_PRE = 0x0
2353 23:09:44.314102 WR_PRE = 0x1
2354 23:09:44.317019 WR_PST = 0x0
2355 23:09:44.317115 DBI_WR = 0x0
2356 23:09:44.320430 DBI_RD = 0x0
2357 23:09:44.320529 OTF = 0x1
2358 23:09:44.323850 ===================================
2359 23:09:44.326830 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2360 23:09:44.333402 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2361 23:09:44.336855 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2362 23:09:44.339960 ===================================
2363 23:09:44.344174 LPDDR4 DRAM CONFIGURATION
2364 23:09:44.346903 ===================================
2365 23:09:44.347007 EX_ROW_EN[0] = 0x10
2366 23:09:44.350254 EX_ROW_EN[1] = 0x0
2367 23:09:44.350349 LP4Y_EN = 0x0
2368 23:09:44.354376 WORK_FSP = 0x0
2369 23:09:44.354464 WL = 0x4
2370 23:09:44.357483 RL = 0x4
2371 23:09:44.357563 BL = 0x2
2372 23:09:44.359992 RPST = 0x0
2373 23:09:44.363173 RD_PRE = 0x0
2374 23:09:44.363253 WR_PRE = 0x1
2375 23:09:44.366384 WR_PST = 0x0
2376 23:09:44.366463 DBI_WR = 0x0
2377 23:09:44.369856 DBI_RD = 0x0
2378 23:09:44.369939 OTF = 0x1
2379 23:09:44.372986 ===================================
2380 23:09:44.380858 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2381 23:09:44.380939 ==
2382 23:09:44.383230 Dram Type= 6, Freq= 0, CH_0, rank 0
2383 23:09:44.387628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2384 23:09:44.387773 ==
2385 23:09:44.389591 [Duty_Offset_Calibration]
2386 23:09:44.393326 B0:1 B1:-1 CA:0
2387 23:09:44.393406
2388 23:09:44.396187 [DutyScan_Calibration_Flow] k_type=0
2389 23:09:44.404575
2390 23:09:44.404655 ==CLK 0==
2391 23:09:44.407434 Final CLK duty delay cell = 0
2392 23:09:44.410949 [0] MAX Duty = 5125%(X100), DQS PI = 24
2393 23:09:44.414541 [0] MIN Duty = 4875%(X100), DQS PI = 8
2394 23:09:44.414662 [0] AVG Duty = 5000%(X100)
2395 23:09:44.417727
2396 23:09:44.421129 CH0 CLK Duty spec in!! Max-Min= 250%
2397 23:09:44.424421 [DutyScan_Calibration_Flow] ====Done====
2398 23:09:44.424499
2399 23:09:44.427118 [DutyScan_Calibration_Flow] k_type=1
2400 23:09:44.443119
2401 23:09:44.443201 ==DQS 0 ==
2402 23:09:44.445886 Final DQS duty delay cell = -4
2403 23:09:44.449845 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2404 23:09:44.453013 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2405 23:09:44.456492 [-4] AVG Duty = 4968%(X100)
2406 23:09:44.456602
2407 23:09:44.456710 ==DQS 1 ==
2408 23:09:44.459190 Final DQS duty delay cell = 0
2409 23:09:44.462531 [0] MAX Duty = 5124%(X100), DQS PI = 4
2410 23:09:44.465820 [0] MIN Duty = 5000%(X100), DQS PI = 24
2411 23:09:44.469518 [0] AVG Duty = 5062%(X100)
2412 23:09:44.469615
2413 23:09:44.473048 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2414 23:09:44.473176
2415 23:09:44.475890 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2416 23:09:44.479452 [DutyScan_Calibration_Flow] ====Done====
2417 23:09:44.479561
2418 23:09:44.482394 [DutyScan_Calibration_Flow] k_type=3
2419 23:09:44.500477
2420 23:09:44.500585 ==DQM 0 ==
2421 23:09:44.503768 Final DQM duty delay cell = 0
2422 23:09:44.507059 [0] MAX Duty = 5062%(X100), DQS PI = 18
2423 23:09:44.510666 [0] MIN Duty = 4875%(X100), DQS PI = 6
2424 23:09:44.510768 [0] AVG Duty = 4968%(X100)
2425 23:09:44.514340
2426 23:09:44.514441 ==DQM 1 ==
2427 23:09:44.517433 Final DQM duty delay cell = 4
2428 23:09:44.520611 [4] MAX Duty = 5187%(X100), DQS PI = 14
2429 23:09:44.523559 [4] MIN Duty = 5000%(X100), DQS PI = 24
2430 23:09:44.523659 [4] AVG Duty = 5093%(X100)
2431 23:09:44.527038
2432 23:09:44.530703 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2433 23:09:44.530820
2434 23:09:44.534268 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2435 23:09:44.536985 [DutyScan_Calibration_Flow] ====Done====
2436 23:09:44.537061
2437 23:09:44.540428 [DutyScan_Calibration_Flow] k_type=2
2438 23:09:44.555902
2439 23:09:44.556002 ==DQ 0 ==
2440 23:09:44.559280 Final DQ duty delay cell = -4
2441 23:09:44.563090 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2442 23:09:44.565891 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2443 23:09:44.569458 [-4] AVG Duty = 4969%(X100)
2444 23:09:44.569558
2445 23:09:44.569654 ==DQ 1 ==
2446 23:09:44.572761 Final DQ duty delay cell = 0
2447 23:09:44.576321 [0] MAX Duty = 5125%(X100), DQS PI = 52
2448 23:09:44.579568 [0] MIN Duty = 5000%(X100), DQS PI = 24
2449 23:09:44.582763 [0] AVG Duty = 5062%(X100)
2450 23:09:44.582865
2451 23:09:44.586357 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2452 23:09:44.586455
2453 23:09:44.589694 CH0 DQ 1 Duty spec in!! Max-Min= 125%
2454 23:09:44.592480 [DutyScan_Calibration_Flow] ====Done====
2455 23:09:44.592582 ==
2456 23:09:44.595988 Dram Type= 6, Freq= 0, CH_1, rank 0
2457 23:09:44.599491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2458 23:09:44.599612 ==
2459 23:09:44.603488 [Duty_Offset_Calibration]
2460 23:09:44.603602 B0:-1 B1:1 CA:1
2461 23:09:44.603714
2462 23:09:44.605780 [DutyScan_Calibration_Flow] k_type=0
2463 23:09:44.616592
2464 23:09:44.616667 ==CLK 0==
2465 23:09:44.619755 Final CLK duty delay cell = 0
2466 23:09:44.623132 [0] MAX Duty = 5156%(X100), DQS PI = 22
2467 23:09:44.626422 [0] MIN Duty = 4969%(X100), DQS PI = 60
2468 23:09:44.630015 [0] AVG Duty = 5062%(X100)
2469 23:09:44.630115
2470 23:09:44.633370 CH1 CLK Duty spec in!! Max-Min= 187%
2471 23:09:44.636661 [DutyScan_Calibration_Flow] ====Done====
2472 23:09:44.636735
2473 23:09:44.639787 [DutyScan_Calibration_Flow] k_type=1
2474 23:09:44.656115
2475 23:09:44.656206 ==DQS 0 ==
2476 23:09:44.659265 Final DQS duty delay cell = 0
2477 23:09:44.662510 [0] MAX Duty = 5156%(X100), DQS PI = 48
2478 23:09:44.665856 [0] MIN Duty = 4907%(X100), DQS PI = 8
2479 23:09:44.668848 [0] AVG Duty = 5031%(X100)
2480 23:09:44.668948
2481 23:09:44.669077 ==DQS 1 ==
2482 23:09:44.672063 Final DQS duty delay cell = 0
2483 23:09:44.675772 [0] MAX Duty = 5094%(X100), DQS PI = 14
2484 23:09:44.678742 [0] MIN Duty = 4969%(X100), DQS PI = 56
2485 23:09:44.682447 [0] AVG Duty = 5031%(X100)
2486 23:09:44.682521
2487 23:09:44.685454 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2488 23:09:44.685528
2489 23:09:44.688667 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2490 23:09:44.691999 [DutyScan_Calibration_Flow] ====Done====
2491 23:09:44.692085
2492 23:09:44.694974 [DutyScan_Calibration_Flow] k_type=3
2493 23:09:44.711419
2494 23:09:44.711506 ==DQM 0 ==
2495 23:09:44.714578 Final DQM duty delay cell = -4
2496 23:09:44.718608 [-4] MAX Duty = 5062%(X100), DQS PI = 36
2497 23:09:44.721000 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2498 23:09:44.724984 [-4] AVG Duty = 4953%(X100)
2499 23:09:44.725069
2500 23:09:44.725156 ==DQM 1 ==
2501 23:09:44.728392 Final DQM duty delay cell = 0
2502 23:09:44.731277 [0] MAX Duty = 5187%(X100), DQS PI = 2
2503 23:09:44.734437 [0] MIN Duty = 5000%(X100), DQS PI = 28
2504 23:09:44.737953 [0] AVG Duty = 5093%(X100)
2505 23:09:44.738038
2506 23:09:44.741417 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2507 23:09:44.741503
2508 23:09:44.744847 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2509 23:09:44.747909 [DutyScan_Calibration_Flow] ====Done====
2510 23:09:44.747995
2511 23:09:44.751602 [DutyScan_Calibration_Flow] k_type=2
2512 23:09:44.768482
2513 23:09:44.768568 ==DQ 0 ==
2514 23:09:44.771507 Final DQ duty delay cell = 0
2515 23:09:44.775452 [0] MAX Duty = 5156%(X100), DQS PI = 28
2516 23:09:44.778297 [0] MIN Duty = 4876%(X100), DQS PI = 8
2517 23:09:44.778381 [0] AVG Duty = 5016%(X100)
2518 23:09:44.778447
2519 23:09:44.781416 ==DQ 1 ==
2520 23:09:44.785176 Final DQ duty delay cell = 0
2521 23:09:44.788238 [0] MAX Duty = 5156%(X100), DQS PI = 10
2522 23:09:44.791748 [0] MIN Duty = 4938%(X100), DQS PI = 62
2523 23:09:44.791857 [0] AVG Duty = 5047%(X100)
2524 23:09:44.791951
2525 23:09:44.794910 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2526 23:09:44.794987
2527 23:09:44.798403 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2528 23:09:44.804897 [DutyScan_Calibration_Flow] ====Done====
2529 23:09:44.808170 nWR fixed to 30
2530 23:09:44.808280 [ModeRegInit_LP4] CH0 RK0
2531 23:09:44.811908 [ModeRegInit_LP4] CH0 RK1
2532 23:09:44.815291 [ModeRegInit_LP4] CH1 RK0
2533 23:09:44.815394 [ModeRegInit_LP4] CH1 RK1
2534 23:09:44.818833 match AC timing 7
2535 23:09:44.821628 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2536 23:09:44.824713 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2537 23:09:44.831432 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2538 23:09:44.834607 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2539 23:09:44.841739 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2540 23:09:44.841821 ==
2541 23:09:44.844803 Dram Type= 6, Freq= 0, CH_0, rank 0
2542 23:09:44.847609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2543 23:09:44.847712 ==
2544 23:09:44.854863 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2545 23:09:44.861062 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2546 23:09:44.868259 [CA 0] Center 39 (9~70) winsize 62
2547 23:09:44.871492 [CA 1] Center 39 (9~69) winsize 61
2548 23:09:44.874899 [CA 2] Center 35 (5~66) winsize 62
2549 23:09:44.878799 [CA 3] Center 35 (5~66) winsize 62
2550 23:09:44.881586 [CA 4] Center 33 (4~63) winsize 60
2551 23:09:44.885081 [CA 5] Center 33 (3~63) winsize 61
2552 23:09:44.885183
2553 23:09:44.888590 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2554 23:09:44.888693
2555 23:09:44.891798 [CATrainingPosCal] consider 1 rank data
2556 23:09:44.894725 u2DelayCellTimex100 = 270/100 ps
2557 23:09:44.898326 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2558 23:09:44.901466 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2559 23:09:44.908073 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2560 23:09:44.911414 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2561 23:09:44.914656 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2562 23:09:44.918138 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2563 23:09:44.918212
2564 23:09:44.921602 CA PerBit enable=1, Macro0, CA PI delay=33
2565 23:09:44.921710
2566 23:09:44.924570 [CBTSetCACLKResult] CA Dly = 33
2567 23:09:44.924670 CS Dly: 8 (0~39)
2568 23:09:44.928073 ==
2569 23:09:44.928179 Dram Type= 6, Freq= 0, CH_0, rank 1
2570 23:09:44.934622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 23:09:44.934742 ==
2572 23:09:44.937726 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2573 23:09:44.944450 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2574 23:09:44.954067 [CA 0] Center 39 (9~70) winsize 62
2575 23:09:44.957331 [CA 1] Center 39 (9~70) winsize 62
2576 23:09:44.960306 [CA 2] Center 35 (5~66) winsize 62
2577 23:09:44.963832 [CA 3] Center 34 (4~65) winsize 62
2578 23:09:44.967106 [CA 4] Center 33 (3~64) winsize 62
2579 23:09:44.970438 [CA 5] Center 33 (3~63) winsize 61
2580 23:09:44.970538
2581 23:09:44.973848 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2582 23:09:44.973924
2583 23:09:44.976610 [CATrainingPosCal] consider 2 rank data
2584 23:09:44.980008 u2DelayCellTimex100 = 270/100 ps
2585 23:09:44.983735 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2586 23:09:44.990251 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2587 23:09:44.993516 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2588 23:09:44.996818 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2589 23:09:44.999936 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2590 23:09:45.003257 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2591 23:09:45.003356
2592 23:09:45.006731 CA PerBit enable=1, Macro0, CA PI delay=33
2593 23:09:45.006812
2594 23:09:45.009926 [CBTSetCACLKResult] CA Dly = 33
2595 23:09:45.013067 CS Dly: 9 (0~41)
2596 23:09:45.013165
2597 23:09:45.016589 ----->DramcWriteLeveling(PI) begin...
2598 23:09:45.016689 ==
2599 23:09:45.019818 Dram Type= 6, Freq= 0, CH_0, rank 0
2600 23:09:45.023200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2601 23:09:45.023301 ==
2602 23:09:45.026936 Write leveling (Byte 0): 32 => 32
2603 23:09:45.029819 Write leveling (Byte 1): 29 => 29
2604 23:09:45.033197 DramcWriteLeveling(PI) end<-----
2605 23:09:45.033299
2606 23:09:45.033390 ==
2607 23:09:45.036732 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 23:09:45.040028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2609 23:09:45.040106 ==
2610 23:09:45.043309 [Gating] SW mode calibration
2611 23:09:45.050078 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2612 23:09:45.056965 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2613 23:09:45.060304 0 15 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2614 23:09:45.063932 0 15 4 | B1->B0 | 2827 3434 | 1 1 | (0 0) (1 1)
2615 23:09:45.069969 0 15 8 | B1->B0 | 3332 3434 | 1 1 | (0 0) (1 1)
2616 23:09:45.073178 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2617 23:09:45.076330 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2618 23:09:45.082985 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2619 23:09:45.086956 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2620 23:09:45.089947 0 15 28 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
2621 23:09:45.096181 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
2622 23:09:45.100081 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2623 23:09:45.102824 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2624 23:09:45.110221 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2625 23:09:45.112984 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2626 23:09:45.116180 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2627 23:09:45.122684 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2628 23:09:45.126466 1 0 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
2629 23:09:45.129309 1 1 0 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
2630 23:09:45.136306 1 1 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2631 23:09:45.139434 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2632 23:09:45.142531 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2633 23:09:45.149070 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2634 23:09:45.152704 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2635 23:09:45.155662 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2636 23:09:45.159398 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2637 23:09:45.165807 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2638 23:09:45.168973 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 23:09:45.172685 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 23:09:45.179594 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 23:09:45.182700 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 23:09:45.185799 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 23:09:45.192298 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2644 23:09:45.196478 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2645 23:09:45.199036 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2646 23:09:45.205371 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2647 23:09:45.208739 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2648 23:09:45.212151 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2649 23:09:45.218620 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2650 23:09:45.222563 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2651 23:09:45.225388 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2652 23:09:45.232112 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2653 23:09:45.235345 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2654 23:09:45.238366 Total UI for P1: 0, mck2ui 16
2655 23:09:45.242502 best dqsien dly found for B0: ( 1, 3, 26)
2656 23:09:45.245429 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2657 23:09:45.248742 Total UI for P1: 0, mck2ui 16
2658 23:09:45.251584 best dqsien dly found for B1: ( 1, 4, 0)
2659 23:09:45.254831 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2660 23:09:45.258249 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2661 23:09:45.258350
2662 23:09:45.265171 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2663 23:09:45.268404 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2664 23:09:45.268503 [Gating] SW calibration Done
2665 23:09:45.271946 ==
2666 23:09:45.274999 Dram Type= 6, Freq= 0, CH_0, rank 0
2667 23:09:45.278530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2668 23:09:45.278634 ==
2669 23:09:45.278724 RX Vref Scan: 0
2670 23:09:45.278792
2671 23:09:45.281587 RX Vref 0 -> 0, step: 1
2672 23:09:45.281699
2673 23:09:45.285045 RX Delay -40 -> 252, step: 8
2674 23:09:45.288299 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2675 23:09:45.291489 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2676 23:09:45.298325 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2677 23:09:45.301357 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2678 23:09:45.304752 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2679 23:09:45.308278 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2680 23:09:45.311572 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2681 23:09:45.317724 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2682 23:09:45.321239 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2683 23:09:45.324411 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2684 23:09:45.327901 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2685 23:09:45.331319 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2686 23:09:45.337852 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2687 23:09:45.341336 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2688 23:09:45.344762 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2689 23:09:45.347694 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2690 23:09:45.347802 ==
2691 23:09:45.351277 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 23:09:45.357886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 23:09:45.357995 ==
2694 23:09:45.358093 DQS Delay:
2695 23:09:45.361556 DQS0 = 0, DQS1 = 0
2696 23:09:45.361660 DQM Delay:
2697 23:09:45.361754 DQM0 = 119, DQM1 = 107
2698 23:09:45.363936 DQ Delay:
2699 23:09:45.367390 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2700 23:09:45.370805 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2701 23:09:45.374533 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2702 23:09:45.377411 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2703 23:09:45.377514
2704 23:09:45.377607
2705 23:09:45.377696 ==
2706 23:09:45.380678 Dram Type= 6, Freq= 0, CH_0, rank 0
2707 23:09:45.383802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2708 23:09:45.387311 ==
2709 23:09:45.387414
2710 23:09:45.387506
2711 23:09:45.387596 TX Vref Scan disable
2712 23:09:45.390385 == TX Byte 0 ==
2713 23:09:45.393720 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2714 23:09:45.397386 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2715 23:09:45.400976 == TX Byte 1 ==
2716 23:09:45.404170 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2717 23:09:45.407566 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2718 23:09:45.410485 ==
2719 23:09:45.410564 Dram Type= 6, Freq= 0, CH_0, rank 0
2720 23:09:45.417103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2721 23:09:45.417210 ==
2722 23:09:45.428093 TX Vref=22, minBit 6, minWin=25, winSum=420
2723 23:09:45.432013 TX Vref=24, minBit 1, minWin=26, winSum=427
2724 23:09:45.435059 TX Vref=26, minBit 1, minWin=26, winSum=432
2725 23:09:45.438088 TX Vref=28, minBit 3, minWin=27, winSum=438
2726 23:09:45.441733 TX Vref=30, minBit 5, minWin=26, winSum=435
2727 23:09:45.448225 TX Vref=32, minBit 5, minWin=26, winSum=432
2728 23:09:45.451539 [TxChooseVref] Worse bit 3, Min win 27, Win sum 438, Final Vref 28
2729 23:09:45.451642
2730 23:09:45.454794 Final TX Range 1 Vref 28
2731 23:09:45.454873
2732 23:09:45.454936 ==
2733 23:09:45.457954 Dram Type= 6, Freq= 0, CH_0, rank 0
2734 23:09:45.461397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2735 23:09:45.464520 ==
2736 23:09:45.464623
2737 23:09:45.464718
2738 23:09:45.464810 TX Vref Scan disable
2739 23:09:45.468282 == TX Byte 0 ==
2740 23:09:45.471356 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2741 23:09:45.478926 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2742 23:09:45.479036 == TX Byte 1 ==
2743 23:09:45.481762 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2744 23:09:45.487954 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2745 23:09:45.488059
2746 23:09:45.488151 [DATLAT]
2747 23:09:45.488243 Freq=1200, CH0 RK0
2748 23:09:45.488336
2749 23:09:45.490868 DATLAT Default: 0xd
2750 23:09:45.490965 0, 0xFFFF, sum = 0
2751 23:09:45.495033 1, 0xFFFF, sum = 0
2752 23:09:45.497887 2, 0xFFFF, sum = 0
2753 23:09:45.498001 3, 0xFFFF, sum = 0
2754 23:09:45.501384 4, 0xFFFF, sum = 0
2755 23:09:45.501490 5, 0xFFFF, sum = 0
2756 23:09:45.504565 6, 0xFFFF, sum = 0
2757 23:09:45.504675 7, 0xFFFF, sum = 0
2758 23:09:45.508361 8, 0xFFFF, sum = 0
2759 23:09:45.508469 9, 0xFFFF, sum = 0
2760 23:09:45.511284 10, 0xFFFF, sum = 0
2761 23:09:45.511391 11, 0xFFFF, sum = 0
2762 23:09:45.514471 12, 0x0, sum = 1
2763 23:09:45.514580 13, 0x0, sum = 2
2764 23:09:45.517534 14, 0x0, sum = 3
2765 23:09:45.517636 15, 0x0, sum = 4
2766 23:09:45.520853 best_step = 13
2767 23:09:45.520959
2768 23:09:45.521052 ==
2769 23:09:45.524846 Dram Type= 6, Freq= 0, CH_0, rank 0
2770 23:09:45.527974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2771 23:09:45.528054 ==
2772 23:09:45.528118 RX Vref Scan: 1
2773 23:09:45.528178
2774 23:09:45.531220 Set Vref Range= 32 -> 127
2775 23:09:45.531312
2776 23:09:45.534623 RX Vref 32 -> 127, step: 1
2777 23:09:45.534698
2778 23:09:45.537541 RX Delay -21 -> 252, step: 4
2779 23:09:45.537616
2780 23:09:45.541214 Set Vref, RX VrefLevel [Byte0]: 32
2781 23:09:45.544168 [Byte1]: 32
2782 23:09:45.544246
2783 23:09:45.547184 Set Vref, RX VrefLevel [Byte0]: 33
2784 23:09:45.550673 [Byte1]: 33
2785 23:09:45.555159
2786 23:09:45.555237 Set Vref, RX VrefLevel [Byte0]: 34
2787 23:09:45.557650 [Byte1]: 34
2788 23:09:45.562526
2789 23:09:45.562629 Set Vref, RX VrefLevel [Byte0]: 35
2790 23:09:45.565780 [Byte1]: 35
2791 23:09:45.570538
2792 23:09:45.570622 Set Vref, RX VrefLevel [Byte0]: 36
2793 23:09:45.574066 [Byte1]: 36
2794 23:09:45.578147
2795 23:09:45.578259 Set Vref, RX VrefLevel [Byte0]: 37
2796 23:09:45.581441 [Byte1]: 37
2797 23:09:45.586089
2798 23:09:45.586195 Set Vref, RX VrefLevel [Byte0]: 38
2799 23:09:45.589551 [Byte1]: 38
2800 23:09:45.594029
2801 23:09:45.594148 Set Vref, RX VrefLevel [Byte0]: 39
2802 23:09:45.597245 [Byte1]: 39
2803 23:09:45.601928
2804 23:09:45.602036 Set Vref, RX VrefLevel [Byte0]: 40
2805 23:09:45.605547 [Byte1]: 40
2806 23:09:45.610116
2807 23:09:45.610221 Set Vref, RX VrefLevel [Byte0]: 41
2808 23:09:45.613074 [Byte1]: 41
2809 23:09:45.617811
2810 23:09:45.617914 Set Vref, RX VrefLevel [Byte0]: 42
2811 23:09:45.621207 [Byte1]: 42
2812 23:09:45.625786
2813 23:09:45.625888 Set Vref, RX VrefLevel [Byte0]: 43
2814 23:09:45.629690 [Byte1]: 43
2815 23:09:45.633851
2816 23:09:45.633957 Set Vref, RX VrefLevel [Byte0]: 44
2817 23:09:45.637196 [Byte1]: 44
2818 23:09:45.641890
2819 23:09:45.641998 Set Vref, RX VrefLevel [Byte0]: 45
2820 23:09:45.645371 [Byte1]: 45
2821 23:09:45.649660
2822 23:09:45.649741 Set Vref, RX VrefLevel [Byte0]: 46
2823 23:09:45.653099 [Byte1]: 46
2824 23:09:45.657613
2825 23:09:45.657722 Set Vref, RX VrefLevel [Byte0]: 47
2826 23:09:45.660867 [Byte1]: 47
2827 23:09:45.665545
2828 23:09:45.665649 Set Vref, RX VrefLevel [Byte0]: 48
2829 23:09:45.668907 [Byte1]: 48
2830 23:09:45.673461
2831 23:09:45.673571 Set Vref, RX VrefLevel [Byte0]: 49
2832 23:09:45.676716 [Byte1]: 49
2833 23:09:45.681491
2834 23:09:45.684576 Set Vref, RX VrefLevel [Byte0]: 50
2835 23:09:45.688085 [Byte1]: 50
2836 23:09:45.688168
2837 23:09:45.691234 Set Vref, RX VrefLevel [Byte0]: 51
2838 23:09:45.694536 [Byte1]: 51
2839 23:09:45.694619
2840 23:09:45.697851 Set Vref, RX VrefLevel [Byte0]: 52
2841 23:09:45.701114 [Byte1]: 52
2842 23:09:45.704947
2843 23:09:45.705029 Set Vref, RX VrefLevel [Byte0]: 53
2844 23:09:45.708355 [Byte1]: 53
2845 23:09:45.713520
2846 23:09:45.713602 Set Vref, RX VrefLevel [Byte0]: 54
2847 23:09:45.716695 [Byte1]: 54
2848 23:09:45.721943
2849 23:09:45.722028 Set Vref, RX VrefLevel [Byte0]: 55
2850 23:09:45.724518 [Byte1]: 55
2851 23:09:45.729114
2852 23:09:45.729195 Set Vref, RX VrefLevel [Byte0]: 56
2853 23:09:45.731840 [Byte1]: 56
2854 23:09:45.736515
2855 23:09:45.736595 Set Vref, RX VrefLevel [Byte0]: 57
2856 23:09:45.740243 [Byte1]: 57
2857 23:09:45.744570
2858 23:09:45.744651 Set Vref, RX VrefLevel [Byte0]: 58
2859 23:09:45.748203 [Byte1]: 58
2860 23:09:45.752805
2861 23:09:45.752885 Set Vref, RX VrefLevel [Byte0]: 59
2862 23:09:45.756172 [Byte1]: 59
2863 23:09:45.760517
2864 23:09:45.760600 Set Vref, RX VrefLevel [Byte0]: 60
2865 23:09:45.764403 [Byte1]: 60
2866 23:09:45.768441
2867 23:09:45.768521 Set Vref, RX VrefLevel [Byte0]: 61
2868 23:09:45.772243 [Byte1]: 61
2869 23:09:45.776204
2870 23:09:45.776283 Set Vref, RX VrefLevel [Byte0]: 62
2871 23:09:45.779494 [Byte1]: 62
2872 23:09:45.784031
2873 23:09:45.784111 Set Vref, RX VrefLevel [Byte0]: 63
2874 23:09:45.787909 [Byte1]: 63
2875 23:09:45.792111
2876 23:09:45.792191 Set Vref, RX VrefLevel [Byte0]: 64
2877 23:09:45.795322 [Byte1]: 64
2878 23:09:45.800199
2879 23:09:45.800279 Set Vref, RX VrefLevel [Byte0]: 65
2880 23:09:45.803354 [Byte1]: 65
2881 23:09:45.808327
2882 23:09:45.808410 Set Vref, RX VrefLevel [Byte0]: 66
2883 23:09:45.811287 [Byte1]: 66
2884 23:09:45.816247
2885 23:09:45.816327 Set Vref, RX VrefLevel [Byte0]: 67
2886 23:09:45.819217 [Byte1]: 67
2887 23:09:45.824537
2888 23:09:45.824646 Set Vref, RX VrefLevel [Byte0]: 68
2889 23:09:45.827336 [Byte1]: 68
2890 23:09:45.832058
2891 23:09:45.832153 Set Vref, RX VrefLevel [Byte0]: 69
2892 23:09:45.835103 [Byte1]: 69
2893 23:09:45.839972
2894 23:09:45.840070 Set Vref, RX VrefLevel [Byte0]: 70
2895 23:09:45.843974 [Byte1]: 70
2896 23:09:45.847792
2897 23:09:45.847896 Set Vref, RX VrefLevel [Byte0]: 71
2898 23:09:45.851129 [Byte1]: 71
2899 23:09:45.855604
2900 23:09:45.855717 Set Vref, RX VrefLevel [Byte0]: 72
2901 23:09:45.858888 [Byte1]: 72
2902 23:09:45.864048
2903 23:09:45.864157 Set Vref, RX VrefLevel [Byte0]: 73
2904 23:09:45.867192 [Byte1]: 73
2905 23:09:45.871344
2906 23:09:45.871449 Set Vref, RX VrefLevel [Byte0]: 74
2907 23:09:45.874841 [Byte1]: 74
2908 23:09:45.879355
2909 23:09:45.879460 Set Vref, RX VrefLevel [Byte0]: 75
2910 23:09:45.882473 [Byte1]: 75
2911 23:09:45.887437
2912 23:09:45.887535 Set Vref, RX VrefLevel [Byte0]: 76
2913 23:09:45.890488 [Byte1]: 76
2914 23:09:45.895210
2915 23:09:45.895307 Set Vref, RX VrefLevel [Byte0]: 77
2916 23:09:45.898641 [Byte1]: 77
2917 23:09:45.903111
2918 23:09:45.903231 Set Vref, RX VrefLevel [Byte0]: 78
2919 23:09:45.906636 [Byte1]: 78
2920 23:09:45.910843
2921 23:09:45.910980 Set Vref, RX VrefLevel [Byte0]: 79
2922 23:09:45.914665 [Byte1]: 79
2923 23:09:45.919034
2924 23:09:45.919115 Final RX Vref Byte 0 = 61 to rank0
2925 23:09:45.922429 Final RX Vref Byte 1 = 48 to rank0
2926 23:09:45.925960 Final RX Vref Byte 0 = 61 to rank1
2927 23:09:45.929452 Final RX Vref Byte 1 = 48 to rank1==
2928 23:09:45.933387 Dram Type= 6, Freq= 0, CH_0, rank 0
2929 23:09:45.939302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 23:09:45.939385 ==
2931 23:09:45.939450 DQS Delay:
2932 23:09:45.939511 DQS0 = 0, DQS1 = 0
2933 23:09:45.942892 DQM Delay:
2934 23:09:45.942973 DQM0 = 119, DQM1 = 106
2935 23:09:45.946142 DQ Delay:
2936 23:09:45.949407 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2937 23:09:45.952285 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
2938 23:09:45.955484 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =100
2939 23:09:45.959242 DQ12 =112, DQ13 =108, DQ14 =118, DQ15 =116
2940 23:09:45.959325
2941 23:09:45.959424
2942 23:09:45.965603 [DQSOSCAuto] RK0, (LSB)MR18= 0xdf8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 405 ps
2943 23:09:45.969487 CH0 RK0: MR19=403, MR18=DF8
2944 23:09:45.975923 CH0_RK0: MR19=0x403, MR18=0xDF8, DQSOSC=405, MR23=63, INC=39, DEC=26
2945 23:09:45.976006
2946 23:09:45.978491 ----->DramcWriteLeveling(PI) begin...
2947 23:09:45.978574 ==
2948 23:09:45.981685 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 23:09:45.985076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 23:09:45.988909 ==
2951 23:09:45.989006 Write leveling (Byte 0): 31 => 31
2952 23:09:45.992439 Write leveling (Byte 1): 29 => 29
2953 23:09:45.995430 DramcWriteLeveling(PI) end<-----
2954 23:09:45.995514
2955 23:09:45.995580 ==
2956 23:09:45.998826 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 23:09:46.005062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 23:09:46.005159 ==
2959 23:09:46.008258 [Gating] SW mode calibration
2960 23:09:46.014737 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2961 23:09:46.018174 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2962 23:09:46.024805 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2963 23:09:46.028423 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2964 23:09:46.032043 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2965 23:09:46.038556 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2966 23:09:46.041994 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2967 23:09:46.045467 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2968 23:09:46.051245 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2969 23:09:46.054694 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2970 23:09:46.057859 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2971 23:09:46.064468 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2972 23:09:46.067981 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2973 23:09:46.071161 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2974 23:09:46.077941 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2975 23:09:46.081267 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2976 23:09:46.084515 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2977 23:09:46.091087 1 0 28 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
2978 23:09:46.094425 1 1 0 | B1->B0 | 3737 4545 | 1 0 | (0 0) (0 0)
2979 23:09:46.097677 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 23:09:46.104119 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2981 23:09:46.107651 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2982 23:09:46.110721 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2983 23:09:46.117347 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2984 23:09:46.120708 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2985 23:09:46.124412 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2986 23:09:46.130552 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2987 23:09:46.134158 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 23:09:46.137095 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 23:09:46.140888 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 23:09:46.147028 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 23:09:46.150406 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 23:09:46.153871 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 23:09:46.160680 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 23:09:46.163560 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 23:09:46.166978 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 23:09:46.174195 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 23:09:46.176811 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2998 23:09:46.180350 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 23:09:46.187289 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3000 23:09:46.190507 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3001 23:09:46.193634 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3002 23:09:46.200170 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3003 23:09:46.203532 Total UI for P1: 0, mck2ui 16
3004 23:09:46.207178 best dqsien dly found for B0: ( 1, 3, 26)
3005 23:09:46.210546 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3006 23:09:46.213389 Total UI for P1: 0, mck2ui 16
3007 23:09:46.217264 best dqsien dly found for B1: ( 1, 3, 30)
3008 23:09:46.220137 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3009 23:09:46.224177 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3010 23:09:46.224256
3011 23:09:46.227191 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3012 23:09:46.230352 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3013 23:09:46.233541 [Gating] SW calibration Done
3014 23:09:46.233616 ==
3015 23:09:46.236682 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 23:09:46.240564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 23:09:46.244439 ==
3018 23:09:46.244516 RX Vref Scan: 0
3019 23:09:46.244580
3020 23:09:46.246777 RX Vref 0 -> 0, step: 1
3021 23:09:46.246850
3022 23:09:46.250173 RX Delay -40 -> 252, step: 8
3023 23:09:46.253608 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3024 23:09:46.256582 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
3025 23:09:46.260656 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3026 23:09:46.263143 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3027 23:09:46.269614 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3028 23:09:46.273300 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3029 23:09:46.276752 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3030 23:09:46.279726 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3031 23:09:46.283616 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3032 23:09:46.289504 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3033 23:09:46.293198 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3034 23:09:46.296167 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3035 23:09:46.299424 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3036 23:09:46.303097 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3037 23:09:46.309303 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3038 23:09:46.312812 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3039 23:09:46.312896 ==
3040 23:09:46.316250 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 23:09:46.319227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 23:09:46.319311 ==
3043 23:09:46.323012 DQS Delay:
3044 23:09:46.323095 DQS0 = 0, DQS1 = 0
3045 23:09:46.325863 DQM Delay:
3046 23:09:46.325946 DQM0 = 116, DQM1 = 108
3047 23:09:46.326012 DQ Delay:
3048 23:09:46.329443 DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115
3049 23:09:46.332982 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
3050 23:09:46.339373 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3051 23:09:46.342830 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3052 23:09:46.342914
3053 23:09:46.342981
3054 23:09:46.343042 ==
3055 23:09:46.346053 Dram Type= 6, Freq= 0, CH_0, rank 1
3056 23:09:46.349442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3057 23:09:46.349526 ==
3058 23:09:46.349592
3059 23:09:46.349653
3060 23:09:46.353016 TX Vref Scan disable
3061 23:09:46.356015 == TX Byte 0 ==
3062 23:09:46.359248 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3063 23:09:46.362315 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3064 23:09:46.367085 == TX Byte 1 ==
3065 23:09:46.369959 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3066 23:09:46.372439 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3067 23:09:46.372525 ==
3068 23:09:46.376129 Dram Type= 6, Freq= 0, CH_0, rank 1
3069 23:09:46.379248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3070 23:09:46.379360 ==
3071 23:09:46.392358 TX Vref=22, minBit 4, minWin=25, winSum=420
3072 23:09:46.396385 TX Vref=24, minBit 1, minWin=26, winSum=428
3073 23:09:46.399145 TX Vref=26, minBit 1, minWin=26, winSum=429
3074 23:09:46.403127 TX Vref=28, minBit 1, minWin=26, winSum=430
3075 23:09:46.405587 TX Vref=30, minBit 10, minWin=26, winSum=435
3076 23:09:46.412374 TX Vref=32, minBit 4, minWin=26, winSum=426
3077 23:09:46.415640 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 30
3078 23:09:46.415737
3079 23:09:46.418754 Final TX Range 1 Vref 30
3080 23:09:46.418826
3081 23:09:46.418886 ==
3082 23:09:46.422189 Dram Type= 6, Freq= 0, CH_0, rank 1
3083 23:09:46.425507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3084 23:09:46.428785 ==
3085 23:09:46.428866
3086 23:09:46.428931
3087 23:09:46.429051 TX Vref Scan disable
3088 23:09:46.432520 == TX Byte 0 ==
3089 23:09:46.435419 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3090 23:09:46.442206 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3091 23:09:46.442290 == TX Byte 1 ==
3092 23:09:46.445630 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3093 23:09:46.452025 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3094 23:09:46.452102
3095 23:09:46.452165 [DATLAT]
3096 23:09:46.452241 Freq=1200, CH0 RK1
3097 23:09:46.452346
3098 23:09:46.455621 DATLAT Default: 0xd
3099 23:09:46.459193 0, 0xFFFF, sum = 0
3100 23:09:46.459285 1, 0xFFFF, sum = 0
3101 23:09:46.462167 2, 0xFFFF, sum = 0
3102 23:09:46.462240 3, 0xFFFF, sum = 0
3103 23:09:46.465610 4, 0xFFFF, sum = 0
3104 23:09:46.465684 5, 0xFFFF, sum = 0
3105 23:09:46.468555 6, 0xFFFF, sum = 0
3106 23:09:46.468652 7, 0xFFFF, sum = 0
3107 23:09:46.471883 8, 0xFFFF, sum = 0
3108 23:09:46.471957 9, 0xFFFF, sum = 0
3109 23:09:46.476140 10, 0xFFFF, sum = 0
3110 23:09:46.476249 11, 0xFFFF, sum = 0
3111 23:09:46.479276 12, 0x0, sum = 1
3112 23:09:46.479348 13, 0x0, sum = 2
3113 23:09:46.482042 14, 0x0, sum = 3
3114 23:09:46.482115 15, 0x0, sum = 4
3115 23:09:46.485308 best_step = 13
3116 23:09:46.485380
3117 23:09:46.485440 ==
3118 23:09:46.488756 Dram Type= 6, Freq= 0, CH_0, rank 1
3119 23:09:46.492232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 23:09:46.492334 ==
3121 23:09:46.492421 RX Vref Scan: 0
3122 23:09:46.495177
3123 23:09:46.495250 RX Vref 0 -> 0, step: 1
3124 23:09:46.495310
3125 23:09:46.498401 RX Delay -21 -> 252, step: 4
3126 23:09:46.505515 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3127 23:09:46.508392 iDelay=199, Bit 1, Center 120 (47 ~ 194) 148
3128 23:09:46.512117 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3129 23:09:46.514844 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3130 23:09:46.518726 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3131 23:09:46.525091 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3132 23:09:46.528238 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3133 23:09:46.531574 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3134 23:09:46.534836 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3135 23:09:46.538151 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3136 23:09:46.541315 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3137 23:09:46.548072 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3138 23:09:46.551325 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3139 23:09:46.554606 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3140 23:09:46.558027 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3141 23:09:46.564532 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3142 23:09:46.564610 ==
3143 23:09:46.568108 Dram Type= 6, Freq= 0, CH_0, rank 1
3144 23:09:46.571034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3145 23:09:46.571106 ==
3146 23:09:46.571172 DQS Delay:
3147 23:09:46.574659 DQS0 = 0, DQS1 = 0
3148 23:09:46.574767 DQM Delay:
3149 23:09:46.577783 DQM0 = 116, DQM1 = 107
3150 23:09:46.577864 DQ Delay:
3151 23:09:46.581337 DQ0 =114, DQ1 =120, DQ2 =110, DQ3 =114
3152 23:09:46.585054 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3153 23:09:46.588486 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3154 23:09:46.591457 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
3155 23:09:46.591545
3156 23:09:46.594470
3157 23:09:46.601099 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe4, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 405 ps
3158 23:09:46.604449 CH0 RK1: MR19=403, MR18=BE4
3159 23:09:46.608177 CH0_RK1: MR19=0x403, MR18=0xBE4, DQSOSC=405, MR23=63, INC=39, DEC=26
3160 23:09:46.611016 [RxdqsGatingPostProcess] freq 1200
3161 23:09:46.617713 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3162 23:09:46.621128 best DQS0 dly(2T, 0.5T) = (0, 11)
3163 23:09:46.624265 best DQS1 dly(2T, 0.5T) = (0, 12)
3164 23:09:46.627593 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3165 23:09:46.631138 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3166 23:09:46.634641 best DQS0 dly(2T, 0.5T) = (0, 11)
3167 23:09:46.637623 best DQS1 dly(2T, 0.5T) = (0, 11)
3168 23:09:46.640970 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3169 23:09:46.644384 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3170 23:09:46.647650 Pre-setting of DQS Precalculation
3171 23:09:46.651399 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3172 23:09:46.651883 ==
3173 23:09:46.654672 Dram Type= 6, Freq= 0, CH_1, rank 0
3174 23:09:46.657767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3175 23:09:46.660841 ==
3176 23:09:46.664703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3177 23:09:46.671021 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3178 23:09:46.678888 [CA 0] Center 37 (7~68) winsize 62
3179 23:09:46.682106 [CA 1] Center 37 (7~68) winsize 62
3180 23:09:46.686131 [CA 2] Center 34 (4~64) winsize 61
3181 23:09:46.688923 [CA 3] Center 33 (3~64) winsize 62
3182 23:09:46.692465 [CA 4] Center 34 (5~64) winsize 60
3183 23:09:46.696145 [CA 5] Center 33 (3~64) winsize 62
3184 23:09:46.696792
3185 23:09:46.699069 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3186 23:09:46.699532
3187 23:09:46.702445 [CATrainingPosCal] consider 1 rank data
3188 23:09:46.705481 u2DelayCellTimex100 = 270/100 ps
3189 23:09:46.708595 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3190 23:09:46.715172 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3191 23:09:46.718973 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3192 23:09:46.722256 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3193 23:09:46.725362 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3194 23:09:46.728845 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3195 23:09:46.729268
3196 23:09:46.732365 CA PerBit enable=1, Macro0, CA PI delay=33
3197 23:09:46.732789
3198 23:09:46.735664 [CBTSetCACLKResult] CA Dly = 33
3199 23:09:46.736233 CS Dly: 5 (0~36)
3200 23:09:46.739052 ==
3201 23:09:46.742627 Dram Type= 6, Freq= 0, CH_1, rank 1
3202 23:09:46.745519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3203 23:09:46.745940 ==
3204 23:09:46.752205 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3205 23:09:46.755118 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3206 23:09:46.764925 [CA 0] Center 37 (7~68) winsize 62
3207 23:09:46.767916 [CA 1] Center 38 (8~68) winsize 61
3208 23:09:46.771463 [CA 2] Center 34 (4~65) winsize 62
3209 23:09:46.774832 [CA 3] Center 33 (3~64) winsize 62
3210 23:09:46.777892 [CA 4] Center 34 (3~65) winsize 63
3211 23:09:46.781788 [CA 5] Center 33 (3~64) winsize 62
3212 23:09:46.782279
3213 23:09:46.784602 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3214 23:09:46.785075
3215 23:09:46.787922 [CATrainingPosCal] consider 2 rank data
3216 23:09:46.791194 u2DelayCellTimex100 = 270/100 ps
3217 23:09:46.794643 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3218 23:09:46.800959 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3219 23:09:46.804359 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3220 23:09:46.808384 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3221 23:09:46.810782 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3222 23:09:46.814391 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3223 23:09:46.814950
3224 23:09:46.817642 CA PerBit enable=1, Macro0, CA PI delay=33
3225 23:09:46.818198
3226 23:09:46.821747 [CBTSetCACLKResult] CA Dly = 33
3227 23:09:46.822296 CS Dly: 7 (0~40)
3228 23:09:46.825066
3229 23:09:46.827567 ----->DramcWriteLeveling(PI) begin...
3230 23:09:46.828189 ==
3231 23:09:46.831055 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 23:09:46.834202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 23:09:46.834757 ==
3234 23:09:46.838210 Write leveling (Byte 0): 23 => 23
3235 23:09:46.840958 Write leveling (Byte 1): 29 => 29
3236 23:09:46.844340 DramcWriteLeveling(PI) end<-----
3237 23:09:46.844800
3238 23:09:46.845165 ==
3239 23:09:46.847385 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 23:09:46.850809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 23:09:46.851368 ==
3242 23:09:46.853938 [Gating] SW mode calibration
3243 23:09:46.860597 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3244 23:09:46.867453 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3245 23:09:46.870257 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (0 0)
3246 23:09:46.874212 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3247 23:09:46.880391 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3248 23:09:46.884018 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3249 23:09:46.887654 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3250 23:09:46.894263 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3251 23:09:46.897059 0 15 24 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
3252 23:09:46.900460 0 15 28 | B1->B0 | 2727 2323 | 1 0 | (1 0) (1 0)
3253 23:09:46.907579 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3254 23:09:46.910601 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3255 23:09:46.913875 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3256 23:09:46.920563 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3257 23:09:46.923285 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3258 23:09:46.927034 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3259 23:09:46.934196 1 0 24 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
3260 23:09:46.936778 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3261 23:09:46.941232 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3262 23:09:46.943794 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3263 23:09:46.950504 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3264 23:09:46.953609 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3265 23:09:46.957068 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3266 23:09:46.963258 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3267 23:09:46.967083 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3268 23:09:46.970221 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3269 23:09:46.976514 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 23:09:46.980212 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3271 23:09:46.983279 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3272 23:09:46.989991 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3273 23:09:46.993171 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3274 23:09:46.996534 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3275 23:09:47.003836 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3276 23:09:47.006449 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3277 23:09:47.009843 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3278 23:09:47.016675 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3279 23:09:47.020013 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3280 23:09:47.023262 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3281 23:09:47.030273 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3282 23:09:47.032904 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3283 23:09:47.036605 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3284 23:09:47.042886 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3285 23:09:47.046810 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3286 23:09:47.050592 Total UI for P1: 0, mck2ui 16
3287 23:09:47.053071 best dqsien dly found for B0: ( 1, 3, 26)
3288 23:09:47.056633 Total UI for P1: 0, mck2ui 16
3289 23:09:47.060149 best dqsien dly found for B1: ( 1, 3, 26)
3290 23:09:47.062987 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3291 23:09:47.066291 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3292 23:09:47.066864
3293 23:09:47.069638 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3294 23:09:47.072731 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3295 23:09:47.076712 [Gating] SW calibration Done
3296 23:09:47.077176 ==
3297 23:09:47.079208 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 23:09:47.082813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 23:09:47.086044 ==
3300 23:09:47.086598 RX Vref Scan: 0
3301 23:09:47.086967
3302 23:09:47.089664 RX Vref 0 -> 0, step: 1
3303 23:09:47.090126
3304 23:09:47.093237 RX Delay -40 -> 252, step: 8
3305 23:09:47.096072 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3306 23:09:47.099206 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3307 23:09:47.102591 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3308 23:09:47.105585 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3309 23:09:47.112425 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3310 23:09:47.115862 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3311 23:09:47.119234 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3312 23:09:47.122622 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3313 23:09:47.126027 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3314 23:09:47.132337 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3315 23:09:47.135379 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3316 23:09:47.138904 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3317 23:09:47.141677 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3318 23:09:47.145151 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3319 23:09:47.151825 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3320 23:09:47.155139 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3321 23:09:47.155741 ==
3322 23:09:47.158515 Dram Type= 6, Freq= 0, CH_1, rank 0
3323 23:09:47.161571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3324 23:09:47.162044 ==
3325 23:09:47.165417 DQS Delay:
3326 23:09:47.165875 DQS0 = 0, DQS1 = 0
3327 23:09:47.166239 DQM Delay:
3328 23:09:47.168658 DQM0 = 118, DQM1 = 108
3329 23:09:47.169117 DQ Delay:
3330 23:09:47.172754 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =115
3331 23:09:47.175384 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3332 23:09:47.179062 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3333 23:09:47.185200 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =119
3334 23:09:47.185759
3335 23:09:47.186123
3336 23:09:47.186460 ==
3337 23:09:47.188313 Dram Type= 6, Freq= 0, CH_1, rank 0
3338 23:09:47.192285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3339 23:09:47.192846 ==
3340 23:09:47.193216
3341 23:09:47.193557
3342 23:09:47.195085 TX Vref Scan disable
3343 23:09:47.195542 == TX Byte 0 ==
3344 23:09:47.201693 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3345 23:09:47.204834 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3346 23:09:47.208016 == TX Byte 1 ==
3347 23:09:47.211726 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3348 23:09:47.215269 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3349 23:09:47.215874 ==
3350 23:09:47.217979 Dram Type= 6, Freq= 0, CH_1, rank 0
3351 23:09:47.221593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3352 23:09:47.222156 ==
3353 23:09:47.234958 TX Vref=22, minBit 8, minWin=24, winSum=411
3354 23:09:47.238520 TX Vref=24, minBit 11, minWin=24, winSum=418
3355 23:09:47.241530 TX Vref=26, minBit 8, minWin=25, winSum=429
3356 23:09:47.244990 TX Vref=28, minBit 9, minWin=25, winSum=427
3357 23:09:47.248251 TX Vref=30, minBit 8, minWin=25, winSum=425
3358 23:09:47.254961 TX Vref=32, minBit 9, minWin=24, winSum=421
3359 23:09:47.257711 [TxChooseVref] Worse bit 8, Min win 25, Win sum 429, Final Vref 26
3360 23:09:47.258170
3361 23:09:47.261311 Final TX Range 1 Vref 26
3362 23:09:47.261770
3363 23:09:47.262127 ==
3364 23:09:47.264772 Dram Type= 6, Freq= 0, CH_1, rank 0
3365 23:09:47.268482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3366 23:09:47.271013 ==
3367 23:09:47.271468
3368 23:09:47.271866
3369 23:09:47.272199 TX Vref Scan disable
3370 23:09:47.274686 == TX Byte 0 ==
3371 23:09:47.278028 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3372 23:09:47.284559 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3373 23:09:47.285075 == TX Byte 1 ==
3374 23:09:47.288552 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3375 23:09:47.294862 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3376 23:09:47.295412
3377 23:09:47.295829 [DATLAT]
3378 23:09:47.296176 Freq=1200, CH1 RK0
3379 23:09:47.296520
3380 23:09:47.298494 DATLAT Default: 0xd
3381 23:09:47.299236 0, 0xFFFF, sum = 0
3382 23:09:47.301413 1, 0xFFFF, sum = 0
3383 23:09:47.304512 2, 0xFFFF, sum = 0
3384 23:09:47.304975 3, 0xFFFF, sum = 0
3385 23:09:47.307666 4, 0xFFFF, sum = 0
3386 23:09:47.308275 5, 0xFFFF, sum = 0
3387 23:09:47.310942 6, 0xFFFF, sum = 0
3388 23:09:47.311382 7, 0xFFFF, sum = 0
3389 23:09:47.315093 8, 0xFFFF, sum = 0
3390 23:09:47.315611 9, 0xFFFF, sum = 0
3391 23:09:47.317757 10, 0xFFFF, sum = 0
3392 23:09:47.318178 11, 0xFFFF, sum = 0
3393 23:09:47.321102 12, 0x0, sum = 1
3394 23:09:47.321523 13, 0x0, sum = 2
3395 23:09:47.324360 14, 0x0, sum = 3
3396 23:09:47.324777 15, 0x0, sum = 4
3397 23:09:47.327906 best_step = 13
3398 23:09:47.328411
3399 23:09:47.328735 ==
3400 23:09:47.331071 Dram Type= 6, Freq= 0, CH_1, rank 0
3401 23:09:47.334224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3402 23:09:47.334788 ==
3403 23:09:47.335130 RX Vref Scan: 1
3404 23:09:47.337935
3405 23:09:47.338442 Set Vref Range= 32 -> 127
3406 23:09:47.338769
3407 23:09:47.340901 RX Vref 32 -> 127, step: 1
3408 23:09:47.341410
3409 23:09:47.344160 RX Delay -21 -> 252, step: 4
3410 23:09:47.344646
3411 23:09:47.347292 Set Vref, RX VrefLevel [Byte0]: 32
3412 23:09:47.350907 [Byte1]: 32
3413 23:09:47.351502
3414 23:09:47.354526 Set Vref, RX VrefLevel [Byte0]: 33
3415 23:09:47.357297 [Byte1]: 33
3416 23:09:47.361202
3417 23:09:47.361780 Set Vref, RX VrefLevel [Byte0]: 34
3418 23:09:47.364486 [Byte1]: 34
3419 23:09:47.368679
3420 23:09:47.368995 Set Vref, RX VrefLevel [Byte0]: 35
3421 23:09:47.372496 [Byte1]: 35
3422 23:09:47.376772
3423 23:09:47.377071 Set Vref, RX VrefLevel [Byte0]: 36
3424 23:09:47.379901 [Byte1]: 36
3425 23:09:47.385123
3426 23:09:47.385531 Set Vref, RX VrefLevel [Byte0]: 37
3427 23:09:47.388020 [Byte1]: 37
3428 23:09:47.393591
3429 23:09:47.394084 Set Vref, RX VrefLevel [Byte0]: 38
3430 23:09:47.396258 [Byte1]: 38
3431 23:09:47.401428
3432 23:09:47.404333 Set Vref, RX VrefLevel [Byte0]: 39
3433 23:09:47.404749 [Byte1]: 39
3434 23:09:47.409042
3435 23:09:47.409554 Set Vref, RX VrefLevel [Byte0]: 40
3436 23:09:47.412319 [Byte1]: 40
3437 23:09:47.416781
3438 23:09:47.417294 Set Vref, RX VrefLevel [Byte0]: 41
3439 23:09:47.420455 [Byte1]: 41
3440 23:09:47.424649
3441 23:09:47.425157 Set Vref, RX VrefLevel [Byte0]: 42
3442 23:09:47.428051 [Byte1]: 42
3443 23:09:47.432630
3444 23:09:47.433144 Set Vref, RX VrefLevel [Byte0]: 43
3445 23:09:47.435524 [Byte1]: 43
3446 23:09:47.440340
3447 23:09:47.440769 Set Vref, RX VrefLevel [Byte0]: 44
3448 23:09:47.443663 [Byte1]: 44
3449 23:09:47.448211
3450 23:09:47.448625 Set Vref, RX VrefLevel [Byte0]: 45
3451 23:09:47.451325 [Byte1]: 45
3452 23:09:47.455781
3453 23:09:47.456222 Set Vref, RX VrefLevel [Byte0]: 46
3454 23:09:47.459588 [Byte1]: 46
3455 23:09:47.464125
3456 23:09:47.464663 Set Vref, RX VrefLevel [Byte0]: 47
3457 23:09:47.467444 [Byte1]: 47
3458 23:09:47.472017
3459 23:09:47.472429 Set Vref, RX VrefLevel [Byte0]: 48
3460 23:09:47.475780 [Byte1]: 48
3461 23:09:47.480355
3462 23:09:47.480856 Set Vref, RX VrefLevel [Byte0]: 49
3463 23:09:47.483951 [Byte1]: 49
3464 23:09:47.487719
3465 23:09:47.488136 Set Vref, RX VrefLevel [Byte0]: 50
3466 23:09:47.491137 [Byte1]: 50
3467 23:09:47.495918
3468 23:09:47.496556 Set Vref, RX VrefLevel [Byte0]: 51
3469 23:09:47.498891 [Byte1]: 51
3470 23:09:47.503496
3471 23:09:47.504130 Set Vref, RX VrefLevel [Byte0]: 52
3472 23:09:47.506909 [Byte1]: 52
3473 23:09:47.511740
3474 23:09:47.512156 Set Vref, RX VrefLevel [Byte0]: 53
3475 23:09:47.514450 [Byte1]: 53
3476 23:09:47.519405
3477 23:09:47.519861 Set Vref, RX VrefLevel [Byte0]: 54
3478 23:09:47.523220 [Byte1]: 54
3479 23:09:47.527108
3480 23:09:47.527519 Set Vref, RX VrefLevel [Byte0]: 55
3481 23:09:47.530857 [Byte1]: 55
3482 23:09:47.535079
3483 23:09:47.535524 Set Vref, RX VrefLevel [Byte0]: 56
3484 23:09:47.538576 [Byte1]: 56
3485 23:09:47.543608
3486 23:09:47.544070 Set Vref, RX VrefLevel [Byte0]: 57
3487 23:09:47.546317 [Byte1]: 57
3488 23:09:47.551303
3489 23:09:47.551880 Set Vref, RX VrefLevel [Byte0]: 58
3490 23:09:47.554527 [Byte1]: 58
3491 23:09:47.558933
3492 23:09:47.559443 Set Vref, RX VrefLevel [Byte0]: 59
3493 23:09:47.562040 [Byte1]: 59
3494 23:09:47.567375
3495 23:09:47.568032 Set Vref, RX VrefLevel [Byte0]: 60
3496 23:09:47.570247 [Byte1]: 60
3497 23:09:47.575133
3498 23:09:47.575605 Set Vref, RX VrefLevel [Byte0]: 61
3499 23:09:47.578457 [Byte1]: 61
3500 23:09:47.582531
3501 23:09:47.583004 Set Vref, RX VrefLevel [Byte0]: 62
3502 23:09:47.586985 [Byte1]: 62
3503 23:09:47.590797
3504 23:09:47.591350 Set Vref, RX VrefLevel [Byte0]: 63
3505 23:09:47.594034 [Byte1]: 63
3506 23:09:47.598628
3507 23:09:47.602175 Set Vref, RX VrefLevel [Byte0]: 64
3508 23:09:47.602720 [Byte1]: 64
3509 23:09:47.606928
3510 23:09:47.607460 Set Vref, RX VrefLevel [Byte0]: 65
3511 23:09:47.610120 [Byte1]: 65
3512 23:09:47.614689
3513 23:09:47.615204 Set Vref, RX VrefLevel [Byte0]: 66
3514 23:09:47.618225 [Byte1]: 66
3515 23:09:47.623158
3516 23:09:47.623718 Set Vref, RX VrefLevel [Byte0]: 67
3517 23:09:47.625516 [Byte1]: 67
3518 23:09:47.630308
3519 23:09:47.630820 Set Vref, RX VrefLevel [Byte0]: 68
3520 23:09:47.634010 [Byte1]: 68
3521 23:09:47.638688
3522 23:09:47.639209 Final RX Vref Byte 0 = 51 to rank0
3523 23:09:47.642167 Final RX Vref Byte 1 = 58 to rank0
3524 23:09:47.644786 Final RX Vref Byte 0 = 51 to rank1
3525 23:09:47.648402 Final RX Vref Byte 1 = 58 to rank1==
3526 23:09:47.652034 Dram Type= 6, Freq= 0, CH_1, rank 0
3527 23:09:47.658148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 23:09:47.658852 ==
3529 23:09:47.659287 DQS Delay:
3530 23:09:47.659719 DQS0 = 0, DQS1 = 0
3531 23:09:47.661646 DQM Delay:
3532 23:09:47.662104 DQM0 = 116, DQM1 = 112
3533 23:09:47.664872 DQ Delay:
3534 23:09:47.668276 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =112
3535 23:09:47.671414 DQ4 =114, DQ5 =128, DQ6 =124, DQ7 =112
3536 23:09:47.675036 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =100
3537 23:09:47.678137 DQ12 =120, DQ13 =118, DQ14 =122, DQ15 =120
3538 23:09:47.678637
3539 23:09:47.679004
3540 23:09:47.687957 [DQSOSCAuto] RK0, (LSB)MR18= 0xf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 410 ps
3541 23:09:47.688592 CH1 RK0: MR19=403, MR18=F4
3542 23:09:47.694857 CH1_RK0: MR19=0x403, MR18=0xF4, DQSOSC=410, MR23=63, INC=39, DEC=26
3543 23:09:47.695420
3544 23:09:47.697412 ----->DramcWriteLeveling(PI) begin...
3545 23:09:47.697891 ==
3546 23:09:47.700656 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 23:09:47.708052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 23:09:47.708782 ==
3549 23:09:47.710749 Write leveling (Byte 0): 26 => 26
3550 23:09:47.714428 Write leveling (Byte 1): 27 => 27
3551 23:09:47.714988 DramcWriteLeveling(PI) end<-----
3552 23:09:47.715350
3553 23:09:47.717332 ==
3554 23:09:47.720576 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 23:09:47.724051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 23:09:47.724851 ==
3557 23:09:47.727780 [Gating] SW mode calibration
3558 23:09:47.733810 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3559 23:09:47.736965 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3560 23:09:47.744013 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3561 23:09:47.746887 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3562 23:09:47.750536 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3563 23:09:47.756854 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3564 23:09:47.760002 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3565 23:09:47.763762 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3566 23:09:47.769853 0 15 24 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
3567 23:09:47.773188 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (1 0) (1 0)
3568 23:09:47.776555 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3569 23:09:47.783130 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3570 23:09:47.786652 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3571 23:09:47.789663 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3572 23:09:47.796395 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3573 23:09:47.799607 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3574 23:09:47.802880 1 0 24 | B1->B0 | 3737 2727 | 1 0 | (0 0) (0 0)
3575 23:09:47.809146 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3576 23:09:47.812330 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3577 23:09:47.815980 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3578 23:09:47.822301 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3579 23:09:47.825612 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3580 23:09:47.829099 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3581 23:09:47.836115 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3582 23:09:47.839029 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3583 23:09:47.842261 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3584 23:09:47.849057 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3585 23:09:47.852276 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3586 23:09:47.855782 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3587 23:09:47.862266 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3588 23:09:47.865495 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3589 23:09:47.869153 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3590 23:09:47.875241 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3591 23:09:47.878655 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3592 23:09:47.882166 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3593 23:09:47.888980 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3594 23:09:47.892013 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3595 23:09:47.895783 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3596 23:09:47.901917 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3597 23:09:47.905428 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3598 23:09:47.908481 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3599 23:09:47.915392 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3600 23:09:47.918936 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3601 23:09:47.921872 Total UI for P1: 0, mck2ui 16
3602 23:09:47.925203 best dqsien dly found for B0: ( 1, 3, 28)
3603 23:09:47.928194 Total UI for P1: 0, mck2ui 16
3604 23:09:47.932128 best dqsien dly found for B1: ( 1, 3, 28)
3605 23:09:47.935392 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3606 23:09:47.938262 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3607 23:09:47.938718
3608 23:09:47.941735 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3609 23:09:47.944639 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3610 23:09:47.948140 [Gating] SW calibration Done
3611 23:09:47.948598 ==
3612 23:09:47.951445 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 23:09:47.958068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 23:09:47.958629 ==
3615 23:09:47.958996 RX Vref Scan: 0
3616 23:09:47.959335
3617 23:09:47.961210 RX Vref 0 -> 0, step: 1
3618 23:09:47.961716
3619 23:09:47.964645 RX Delay -40 -> 252, step: 8
3620 23:09:47.967967 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3621 23:09:47.971062 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3622 23:09:47.975042 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3623 23:09:47.977697 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3624 23:09:47.984445 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3625 23:09:47.987941 iDelay=208, Bit 5, Center 123 (48 ~ 199) 152
3626 23:09:47.991481 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3627 23:09:47.994673 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3628 23:09:47.997608 iDelay=208, Bit 8, Center 99 (24 ~ 175) 152
3629 23:09:48.004999 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3630 23:09:48.007931 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3631 23:09:48.011302 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3632 23:09:48.014454 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3633 23:09:48.020939 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3634 23:09:48.024574 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3635 23:09:48.027345 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3636 23:09:48.027959 ==
3637 23:09:48.031183 Dram Type= 6, Freq= 0, CH_1, rank 1
3638 23:09:48.033908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3639 23:09:48.034385 ==
3640 23:09:48.037307 DQS Delay:
3641 23:09:48.037763 DQS0 = 0, DQS1 = 0
3642 23:09:48.040713 DQM Delay:
3643 23:09:48.041264 DQM0 = 116, DQM1 = 110
3644 23:09:48.041631 DQ Delay:
3645 23:09:48.047042 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3646 23:09:48.050663 DQ4 =115, DQ5 =123, DQ6 =131, DQ7 =115
3647 23:09:48.053826 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =103
3648 23:09:48.057293 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3649 23:09:48.057863
3650 23:09:48.058226
3651 23:09:48.058562 ==
3652 23:09:48.060667 Dram Type= 6, Freq= 0, CH_1, rank 1
3653 23:09:48.064014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3654 23:09:48.064476 ==
3655 23:09:48.064840
3656 23:09:48.065171
3657 23:09:48.067239 TX Vref Scan disable
3658 23:09:48.070328 == TX Byte 0 ==
3659 23:09:48.073247 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3660 23:09:48.077886 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3661 23:09:48.080090 == TX Byte 1 ==
3662 23:09:48.083258 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3663 23:09:48.086768 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3664 23:09:48.087319 ==
3665 23:09:48.090262 Dram Type= 6, Freq= 0, CH_1, rank 1
3666 23:09:48.096365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3667 23:09:48.096781 ==
3668 23:09:48.106937 TX Vref=22, minBit 8, minWin=25, winSum=425
3669 23:09:48.110364 TX Vref=24, minBit 3, minWin=26, winSum=429
3670 23:09:48.113835 TX Vref=26, minBit 9, minWin=26, winSum=431
3671 23:09:48.116944 TX Vref=28, minBit 9, minWin=26, winSum=430
3672 23:09:48.120508 TX Vref=30, minBit 9, minWin=26, winSum=431
3673 23:09:48.127108 TX Vref=32, minBit 9, minWin=25, winSum=428
3674 23:09:48.130387 [TxChooseVref] Worse bit 9, Min win 26, Win sum 431, Final Vref 26
3675 23:09:48.130910
3676 23:09:48.133737 Final TX Range 1 Vref 26
3677 23:09:48.134268
3678 23:09:48.134605 ==
3679 23:09:48.137292 Dram Type= 6, Freq= 0, CH_1, rank 1
3680 23:09:48.140132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3681 23:09:48.140650 ==
3682 23:09:48.143405
3683 23:09:48.143983
3684 23:09:48.144318 TX Vref Scan disable
3685 23:09:48.146498 == TX Byte 0 ==
3686 23:09:48.150763 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3687 23:09:48.156640 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3688 23:09:48.157173 == TX Byte 1 ==
3689 23:09:48.159818 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3690 23:09:48.166433 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3691 23:09:48.166849
3692 23:09:48.167179 [DATLAT]
3693 23:09:48.167487 Freq=1200, CH1 RK1
3694 23:09:48.167834
3695 23:09:48.169238 DATLAT Default: 0xd
3696 23:09:48.172687 0, 0xFFFF, sum = 0
3697 23:09:48.173112 1, 0xFFFF, sum = 0
3698 23:09:48.176364 2, 0xFFFF, sum = 0
3699 23:09:48.176867 3, 0xFFFF, sum = 0
3700 23:09:48.179532 4, 0xFFFF, sum = 0
3701 23:09:48.179988 5, 0xFFFF, sum = 0
3702 23:09:48.183790 6, 0xFFFF, sum = 0
3703 23:09:48.184315 7, 0xFFFF, sum = 0
3704 23:09:48.185886 8, 0xFFFF, sum = 0
3705 23:09:48.186309 9, 0xFFFF, sum = 0
3706 23:09:48.189735 10, 0xFFFF, sum = 0
3707 23:09:48.190349 11, 0xFFFF, sum = 0
3708 23:09:48.193195 12, 0x0, sum = 1
3709 23:09:48.193791 13, 0x0, sum = 2
3710 23:09:48.196184 14, 0x0, sum = 3
3711 23:09:48.196653 15, 0x0, sum = 4
3712 23:09:48.199052 best_step = 13
3713 23:09:48.199509
3714 23:09:48.199929 ==
3715 23:09:48.202787 Dram Type= 6, Freq= 0, CH_1, rank 1
3716 23:09:48.205467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3717 23:09:48.205881 ==
3718 23:09:48.209807 RX Vref Scan: 0
3719 23:09:48.210320
3720 23:09:48.210652 RX Vref 0 -> 0, step: 1
3721 23:09:48.210959
3722 23:09:48.211953 RX Delay -21 -> 252, step: 4
3723 23:09:48.219173 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3724 23:09:48.222649 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3725 23:09:48.225877 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3726 23:09:48.228805 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3727 23:09:48.232559 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3728 23:09:48.239337 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3729 23:09:48.242491 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3730 23:09:48.245551 iDelay=199, Bit 7, Center 114 (47 ~ 182) 136
3731 23:09:48.248780 iDelay=199, Bit 8, Center 100 (35 ~ 166) 132
3732 23:09:48.252208 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3733 23:09:48.258633 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3734 23:09:48.261814 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3735 23:09:48.265514 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3736 23:09:48.268353 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3737 23:09:48.275168 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3738 23:09:48.278680 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3739 23:09:48.279278 ==
3740 23:09:48.281480 Dram Type= 6, Freq= 0, CH_1, rank 1
3741 23:09:48.284830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3742 23:09:48.285290 ==
3743 23:09:48.288251 DQS Delay:
3744 23:09:48.288751 DQS0 = 0, DQS1 = 0
3745 23:09:48.289122 DQM Delay:
3746 23:09:48.291427 DQM0 = 116, DQM1 = 111
3747 23:09:48.292014 DQ Delay:
3748 23:09:48.294950 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =112
3749 23:09:48.299296 DQ4 =116, DQ5 =126, DQ6 =130, DQ7 =114
3750 23:09:48.304657 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =102
3751 23:09:48.308256 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =120
3752 23:09:48.308825
3753 23:09:48.309190
3754 23:09:48.315650 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6f1, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
3755 23:09:48.317889 CH1 RK1: MR19=303, MR18=F6F1
3756 23:09:48.324573 CH1_RK1: MR19=0x303, MR18=0xF6F1, DQSOSC=414, MR23=63, INC=38, DEC=25
3757 23:09:48.328149 [RxdqsGatingPostProcess] freq 1200
3758 23:09:48.334653 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3759 23:09:48.335220 best DQS0 dly(2T, 0.5T) = (0, 11)
3760 23:09:48.338284 best DQS1 dly(2T, 0.5T) = (0, 11)
3761 23:09:48.340833 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3762 23:09:48.344359 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3763 23:09:48.347318 best DQS0 dly(2T, 0.5T) = (0, 11)
3764 23:09:48.351465 best DQS1 dly(2T, 0.5T) = (0, 11)
3765 23:09:48.354112 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3766 23:09:48.356927 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3767 23:09:48.360830 Pre-setting of DQS Precalculation
3768 23:09:48.367049 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3769 23:09:48.373812 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3770 23:09:48.380054 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3771 23:09:48.380626
3772 23:09:48.380975
3773 23:09:48.383546 [Calibration Summary] 2400 Mbps
3774 23:09:48.384219 CH 0, Rank 0
3775 23:09:48.387084 SW Impedance : PASS
3776 23:09:48.390601 DUTY Scan : NO K
3777 23:09:48.391136 ZQ Calibration : PASS
3778 23:09:48.393893 Jitter Meter : NO K
3779 23:09:48.397302 CBT Training : PASS
3780 23:09:48.397718 Write leveling : PASS
3781 23:09:48.399966 RX DQS gating : PASS
3782 23:09:48.403619 RX DQ/DQS(RDDQC) : PASS
3783 23:09:48.404089 TX DQ/DQS : PASS
3784 23:09:48.407335 RX DATLAT : PASS
3785 23:09:48.410150 RX DQ/DQS(Engine): PASS
3786 23:09:48.410668 TX OE : NO K
3787 23:09:48.411000 All Pass.
3788 23:09:48.413796
3789 23:09:48.414316 CH 0, Rank 1
3790 23:09:48.417041 SW Impedance : PASS
3791 23:09:48.417564 DUTY Scan : NO K
3792 23:09:48.420253 ZQ Calibration : PASS
3793 23:09:48.423818 Jitter Meter : NO K
3794 23:09:48.424349 CBT Training : PASS
3795 23:09:48.426545 Write leveling : PASS
3796 23:09:48.427064 RX DQS gating : PASS
3797 23:09:48.430214 RX DQ/DQS(RDDQC) : PASS
3798 23:09:48.433134 TX DQ/DQS : PASS
3799 23:09:48.433557 RX DATLAT : PASS
3800 23:09:48.436385 RX DQ/DQS(Engine): PASS
3801 23:09:48.439832 TX OE : NO K
3802 23:09:48.440515 All Pass.
3803 23:09:48.440917
3804 23:09:48.441232 CH 1, Rank 0
3805 23:09:48.442864 SW Impedance : PASS
3806 23:09:48.446191 DUTY Scan : NO K
3807 23:09:48.446607 ZQ Calibration : PASS
3808 23:09:48.449637 Jitter Meter : NO K
3809 23:09:48.453307 CBT Training : PASS
3810 23:09:48.453838 Write leveling : PASS
3811 23:09:48.456161 RX DQS gating : PASS
3812 23:09:48.459835 RX DQ/DQS(RDDQC) : PASS
3813 23:09:48.460373 TX DQ/DQS : PASS
3814 23:09:48.463123 RX DATLAT : PASS
3815 23:09:48.465998 RX DQ/DQS(Engine): PASS
3816 23:09:48.466539 TX OE : NO K
3817 23:09:48.469213 All Pass.
3818 23:09:48.469634
3819 23:09:48.469964 CH 1, Rank 1
3820 23:09:48.472368 SW Impedance : PASS
3821 23:09:48.472800 DUTY Scan : NO K
3822 23:09:48.475775 ZQ Calibration : PASS
3823 23:09:48.479217 Jitter Meter : NO K
3824 23:09:48.479649 CBT Training : PASS
3825 23:09:48.482722 Write leveling : PASS
3826 23:09:48.485919 RX DQS gating : PASS
3827 23:09:48.486449 RX DQ/DQS(RDDQC) : PASS
3828 23:09:48.489814 TX DQ/DQS : PASS
3829 23:09:48.492743 RX DATLAT : PASS
3830 23:09:48.493160 RX DQ/DQS(Engine): PASS
3831 23:09:48.496089 TX OE : NO K
3832 23:09:48.496619 All Pass.
3833 23:09:48.496950
3834 23:09:48.499043 DramC Write-DBI off
3835 23:09:48.502011 PER_BANK_REFRESH: Hybrid Mode
3836 23:09:48.502429 TX_TRACKING: ON
3837 23:09:48.512398 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3838 23:09:48.515811 [FAST_K] Save calibration result to emmc
3839 23:09:48.519053 dramc_set_vcore_voltage set vcore to 650000
3840 23:09:48.522326 Read voltage for 600, 5
3841 23:09:48.522847 Vio18 = 0
3842 23:09:48.523180 Vcore = 650000
3843 23:09:48.525581 Vdram = 0
3844 23:09:48.526102 Vddq = 0
3845 23:09:48.526435 Vmddr = 0
3846 23:09:48.532706 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3847 23:09:48.535643 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3848 23:09:48.539553 MEM_TYPE=3, freq_sel=19
3849 23:09:48.542228 sv_algorithm_assistance_LP4_1600
3850 23:09:48.546073 ============ PULL DRAM RESETB DOWN ============
3851 23:09:48.548872 ========== PULL DRAM RESETB DOWN end =========
3852 23:09:48.555347 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3853 23:09:48.558981 ===================================
3854 23:09:48.559402 LPDDR4 DRAM CONFIGURATION
3855 23:09:48.562364 ===================================
3856 23:09:48.565534 EX_ROW_EN[0] = 0x0
3857 23:09:48.568765 EX_ROW_EN[1] = 0x0
3858 23:09:48.569233 LP4Y_EN = 0x0
3859 23:09:48.572264 WORK_FSP = 0x0
3860 23:09:48.572683 WL = 0x2
3861 23:09:48.575522 RL = 0x2
3862 23:09:48.575977 BL = 0x2
3863 23:09:48.578562 RPST = 0x0
3864 23:09:48.578993 RD_PRE = 0x0
3865 23:09:48.582162 WR_PRE = 0x1
3866 23:09:48.582580 WR_PST = 0x0
3867 23:09:48.584763 DBI_WR = 0x0
3868 23:09:48.585379 DBI_RD = 0x0
3869 23:09:48.588036 OTF = 0x1
3870 23:09:48.591570 ===================================
3871 23:09:48.595148 ===================================
3872 23:09:48.595567 ANA top config
3873 23:09:48.597897 ===================================
3874 23:09:48.601355 DLL_ASYNC_EN = 0
3875 23:09:48.604577 ALL_SLAVE_EN = 1
3876 23:09:48.608008 NEW_RANK_MODE = 1
3877 23:09:48.608430 DLL_IDLE_MODE = 1
3878 23:09:48.611428 LP45_APHY_COMB_EN = 1
3879 23:09:48.614769 TX_ODT_DIS = 1
3880 23:09:48.618258 NEW_8X_MODE = 1
3881 23:09:48.621522 ===================================
3882 23:09:48.624639 ===================================
3883 23:09:48.627537 data_rate = 1200
3884 23:09:48.630897 CKR = 1
3885 23:09:48.631317 DQ_P2S_RATIO = 8
3886 23:09:48.634635 ===================================
3887 23:09:48.637909 CA_P2S_RATIO = 8
3888 23:09:48.641168 DQ_CA_OPEN = 0
3889 23:09:48.644277 DQ_SEMI_OPEN = 0
3890 23:09:48.647735 CA_SEMI_OPEN = 0
3891 23:09:48.651568 CA_FULL_RATE = 0
3892 23:09:48.652146 DQ_CKDIV4_EN = 1
3893 23:09:48.654620 CA_CKDIV4_EN = 1
3894 23:09:48.657503 CA_PREDIV_EN = 0
3895 23:09:48.660766 PH8_DLY = 0
3896 23:09:48.664057 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3897 23:09:48.667694 DQ_AAMCK_DIV = 4
3898 23:09:48.668252 CA_AAMCK_DIV = 4
3899 23:09:48.671215 CA_ADMCK_DIV = 4
3900 23:09:48.673888 DQ_TRACK_CA_EN = 0
3901 23:09:48.677255 CA_PICK = 600
3902 23:09:48.680643 CA_MCKIO = 600
3903 23:09:48.684096 MCKIO_SEMI = 0
3904 23:09:48.687719 PLL_FREQ = 2288
3905 23:09:48.688149 DQ_UI_PI_RATIO = 32
3906 23:09:48.690298 CA_UI_PI_RATIO = 0
3907 23:09:48.693418 ===================================
3908 23:09:48.696708 ===================================
3909 23:09:48.700088 memory_type:LPDDR4
3910 23:09:48.704009 GP_NUM : 10
3911 23:09:48.704426 SRAM_EN : 1
3912 23:09:48.707261 MD32_EN : 0
3913 23:09:48.710193 ===================================
3914 23:09:48.713637 [ANA_INIT] >>>>>>>>>>>>>>
3915 23:09:48.713933 <<<<<< [CONFIGURE PHASE]: ANA_TX
3916 23:09:48.719750 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3917 23:09:48.719983 ===================================
3918 23:09:48.723038 data_rate = 1200,PCW = 0X5800
3919 23:09:48.726802 ===================================
3920 23:09:48.729786 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3921 23:09:48.736434 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3922 23:09:48.743143 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3923 23:09:48.746283 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3924 23:09:48.749539 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3925 23:09:48.752476 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3926 23:09:48.755725 [ANA_INIT] flow start
3927 23:09:48.759071 [ANA_INIT] PLL >>>>>>>>
3928 23:09:48.759321 [ANA_INIT] PLL <<<<<<<<
3929 23:09:48.762547 [ANA_INIT] MIDPI >>>>>>>>
3930 23:09:48.765834 [ANA_INIT] MIDPI <<<<<<<<
3931 23:09:48.766010 [ANA_INIT] DLL >>>>>>>>
3932 23:09:48.769053 [ANA_INIT] flow end
3933 23:09:48.772497 ============ LP4 DIFF to SE enter ============
3934 23:09:48.775262 ============ LP4 DIFF to SE exit ============
3935 23:09:48.778883 [ANA_INIT] <<<<<<<<<<<<<
3936 23:09:48.782131 [Flow] Enable top DCM control >>>>>
3937 23:09:48.785302 [Flow] Enable top DCM control <<<<<
3938 23:09:48.789010 Enable DLL master slave shuffle
3939 23:09:48.795199 ==============================================================
3940 23:09:48.795289 Gating Mode config
3941 23:09:48.802073 ==============================================================
3942 23:09:48.805826 Config description:
3943 23:09:48.812205 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3944 23:09:48.818610 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3945 23:09:48.825950 SELPH_MODE 0: By rank 1: By Phase
3946 23:09:48.832330 ==============================================================
3947 23:09:48.833037 GAT_TRACK_EN = 1
3948 23:09:48.835649 RX_GATING_MODE = 2
3949 23:09:48.838617 RX_GATING_TRACK_MODE = 2
3950 23:09:48.841603 SELPH_MODE = 1
3951 23:09:48.844797 PICG_EARLY_EN = 1
3952 23:09:48.848378 VALID_LAT_VALUE = 1
3953 23:09:48.855172 ==============================================================
3954 23:09:48.858295 Enter into Gating configuration >>>>
3955 23:09:48.861863 Exit from Gating configuration <<<<
3956 23:09:48.864785 Enter into DVFS_PRE_config >>>>>
3957 23:09:48.874251 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3958 23:09:48.877702 Exit from DVFS_PRE_config <<<<<
3959 23:09:48.881493 Enter into PICG configuration >>>>
3960 23:09:48.884306 Exit from PICG configuration <<<<
3961 23:09:48.887448 [RX_INPUT] configuration >>>>>
3962 23:09:48.891268 [RX_INPUT] configuration <<<<<
3963 23:09:48.893990 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3964 23:09:48.900635 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3965 23:09:48.907558 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3966 23:09:48.914025 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3967 23:09:48.917523 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3968 23:09:48.924355 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3969 23:09:48.930931 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3970 23:09:48.934293 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3971 23:09:48.937054 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3972 23:09:48.940566 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3973 23:09:48.947092 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3974 23:09:48.950628 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3975 23:09:48.953811 ===================================
3976 23:09:48.957212 LPDDR4 DRAM CONFIGURATION
3977 23:09:48.960292 ===================================
3978 23:09:48.960830 EX_ROW_EN[0] = 0x0
3979 23:09:48.964027 EX_ROW_EN[1] = 0x0
3980 23:09:48.964553 LP4Y_EN = 0x0
3981 23:09:48.967280 WORK_FSP = 0x0
3982 23:09:48.967721 WL = 0x2
3983 23:09:48.969970 RL = 0x2
3984 23:09:48.970394 BL = 0x2
3985 23:09:48.973738 RPST = 0x0
3986 23:09:48.974160 RD_PRE = 0x0
3987 23:09:48.977287 WR_PRE = 0x1
3988 23:09:48.980525 WR_PST = 0x0
3989 23:09:48.981071 DBI_WR = 0x0
3990 23:09:48.983104 DBI_RD = 0x0
3991 23:09:48.983543 OTF = 0x1
3992 23:09:48.986662 ===================================
3993 23:09:48.990425 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3994 23:09:48.996681 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3995 23:09:48.999937 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3996 23:09:49.003484 ===================================
3997 23:09:49.006590 LPDDR4 DRAM CONFIGURATION
3998 23:09:49.009887 ===================================
3999 23:09:49.010341 EX_ROW_EN[0] = 0x10
4000 23:09:49.013070 EX_ROW_EN[1] = 0x0
4001 23:09:49.013485 LP4Y_EN = 0x0
4002 23:09:49.016409 WORK_FSP = 0x0
4003 23:09:49.016820 WL = 0x2
4004 23:09:49.019897 RL = 0x2
4005 23:09:49.020436 BL = 0x2
4006 23:09:49.023224 RPST = 0x0
4007 23:09:49.026473 RD_PRE = 0x0
4008 23:09:49.026889 WR_PRE = 0x1
4009 23:09:49.030072 WR_PST = 0x0
4010 23:09:49.030599 DBI_WR = 0x0
4011 23:09:49.032861 DBI_RD = 0x0
4012 23:09:49.033274 OTF = 0x1
4013 23:09:49.036350 ===================================
4014 23:09:49.042472 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4015 23:09:49.046839 nWR fixed to 30
4016 23:09:49.050159 [ModeRegInit_LP4] CH0 RK0
4017 23:09:49.050664 [ModeRegInit_LP4] CH0 RK1
4018 23:09:49.053355 [ModeRegInit_LP4] CH1 RK0
4019 23:09:49.056275 [ModeRegInit_LP4] CH1 RK1
4020 23:09:49.056791 match AC timing 17
4021 23:09:49.063303 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4022 23:09:49.066228 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4023 23:09:49.069562 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4024 23:09:49.076398 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4025 23:09:49.079879 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4026 23:09:49.080301 ==
4027 23:09:49.083114 Dram Type= 6, Freq= 0, CH_0, rank 0
4028 23:09:49.086161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4029 23:09:49.086577 ==
4030 23:09:49.092774 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4031 23:09:49.100038 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4032 23:09:49.102740 [CA 0] Center 36 (6~66) winsize 61
4033 23:09:49.106357 [CA 1] Center 36 (6~66) winsize 61
4034 23:09:49.109805 [CA 2] Center 34 (4~65) winsize 62
4035 23:09:49.112744 [CA 3] Center 34 (3~65) winsize 63
4036 23:09:49.116199 [CA 4] Center 33 (3~64) winsize 62
4037 23:09:49.119601 [CA 5] Center 33 (3~64) winsize 62
4038 23:09:49.120172
4039 23:09:49.122947 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4040 23:09:49.123483
4041 23:09:49.125715 [CATrainingPosCal] consider 1 rank data
4042 23:09:49.129260 u2DelayCellTimex100 = 270/100 ps
4043 23:09:49.132143 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4044 23:09:49.135935 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4045 23:09:49.138977 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4046 23:09:49.145495 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4047 23:09:49.148669 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4048 23:09:49.152471 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4049 23:09:49.152885
4050 23:09:49.155405 CA PerBit enable=1, Macro0, CA PI delay=33
4051 23:09:49.155861
4052 23:09:49.158659 [CBTSetCACLKResult] CA Dly = 33
4053 23:09:49.159182 CS Dly: 5 (0~36)
4054 23:09:49.159599 ==
4055 23:09:49.162084 Dram Type= 6, Freq= 0, CH_0, rank 1
4056 23:09:49.168229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4057 23:09:49.168712 ==
4058 23:09:49.171788 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4059 23:09:49.177944 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4060 23:09:49.182453 [CA 0] Center 36 (6~66) winsize 61
4061 23:09:49.185688 [CA 1] Center 36 (6~66) winsize 61
4062 23:09:49.188191 [CA 2] Center 34 (3~65) winsize 63
4063 23:09:49.191595 [CA 3] Center 33 (3~64) winsize 62
4064 23:09:49.194959 [CA 4] Center 33 (3~64) winsize 62
4065 23:09:49.198453 [CA 5] Center 33 (3~64) winsize 62
4066 23:09:49.198875
4067 23:09:49.201815 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4068 23:09:49.202237
4069 23:09:49.205111 [CATrainingPosCal] consider 2 rank data
4070 23:09:49.208306 u2DelayCellTimex100 = 270/100 ps
4071 23:09:49.214501 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4072 23:09:49.218484 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4073 23:09:49.221421 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4074 23:09:49.224668 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4075 23:09:49.228251 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4076 23:09:49.230821 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4077 23:09:49.231329
4078 23:09:49.234662 CA PerBit enable=1, Macro0, CA PI delay=33
4079 23:09:49.235172
4080 23:09:49.237525 [CBTSetCACLKResult] CA Dly = 33
4081 23:09:49.241293 CS Dly: 6 (0~39)
4082 23:09:49.241712
4083 23:09:49.244181 ----->DramcWriteLeveling(PI) begin...
4084 23:09:49.244707 ==
4085 23:09:49.247364 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 23:09:49.251190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 23:09:49.251751 ==
4088 23:09:49.254217 Write leveling (Byte 0): 34 => 34
4089 23:09:49.257380 Write leveling (Byte 1): 30 => 30
4090 23:09:49.261100 DramcWriteLeveling(PI) end<-----
4091 23:09:49.261611
4092 23:09:49.261948 ==
4093 23:09:49.264519 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 23:09:49.267127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 23:09:49.267541 ==
4096 23:09:49.270590 [Gating] SW mode calibration
4097 23:09:49.276920 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4098 23:09:49.283762 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4099 23:09:49.286975 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4100 23:09:49.293366 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4101 23:09:49.297266 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4102 23:09:49.300158 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4103 23:09:49.306813 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4104 23:09:49.310551 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4105 23:09:49.314012 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4106 23:09:49.319599 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4107 23:09:49.323851 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4108 23:09:49.327309 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4109 23:09:49.333303 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4110 23:09:49.336566 0 10 12 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
4111 23:09:49.340049 0 10 16 | B1->B0 | 3434 4545 | 0 0 | (1 1) (0 0)
4112 23:09:49.343933 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4113 23:09:49.349701 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4114 23:09:49.353029 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4115 23:09:49.356186 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4116 23:09:49.363295 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4117 23:09:49.366157 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4118 23:09:49.369583 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4119 23:09:49.375915 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4120 23:09:49.379947 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4121 23:09:49.382495 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4122 23:09:49.389865 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4123 23:09:49.392906 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4124 23:09:49.396205 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4125 23:09:49.402517 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4126 23:09:49.406157 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4127 23:09:49.409216 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4128 23:09:49.415748 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4129 23:09:49.419008 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4130 23:09:49.423427 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4131 23:09:49.429432 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4132 23:09:49.432472 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4133 23:09:49.439846 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4134 23:09:49.442460 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4135 23:09:49.445690 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4136 23:09:49.448642 Total UI for P1: 0, mck2ui 16
4137 23:09:49.451966 best dqsien dly found for B0: ( 0, 13, 12)
4138 23:09:49.455143 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4139 23:09:49.458578 Total UI for P1: 0, mck2ui 16
4140 23:09:49.462006 best dqsien dly found for B1: ( 0, 13, 14)
4141 23:09:49.468420 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4142 23:09:49.471712 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4143 23:09:49.472127
4144 23:09:49.475197 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4145 23:09:49.478553 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4146 23:09:49.481963 [Gating] SW calibration Done
4147 23:09:49.482374 ==
4148 23:09:49.484810 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 23:09:49.488105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 23:09:49.488522 ==
4151 23:09:49.492139 RX Vref Scan: 0
4152 23:09:49.492550
4153 23:09:49.492877 RX Vref 0 -> 0, step: 1
4154 23:09:49.493182
4155 23:09:49.494665 RX Delay -230 -> 252, step: 16
4156 23:09:49.501778 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4157 23:09:49.504729 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4158 23:09:49.508434 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4159 23:09:49.511195 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4160 23:09:49.514653 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4161 23:09:49.521421 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4162 23:09:49.524452 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4163 23:09:49.527799 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4164 23:09:49.531370 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4165 23:09:49.537846 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4166 23:09:49.541459 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4167 23:09:49.544269 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4168 23:09:49.547721 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4169 23:09:49.554575 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4170 23:09:49.557945 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4171 23:09:49.560682 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4172 23:09:49.561096 ==
4173 23:09:49.563613 Dram Type= 6, Freq= 0, CH_0, rank 0
4174 23:09:49.567191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 23:09:49.570489 ==
4176 23:09:49.570897 DQS Delay:
4177 23:09:49.571228 DQS0 = 0, DQS1 = 0
4178 23:09:49.573822 DQM Delay:
4179 23:09:49.574347 DQM0 = 42, DQM1 = 30
4180 23:09:49.577247 DQ Delay:
4181 23:09:49.577747 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4182 23:09:49.580755 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4183 23:09:49.584274 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4184 23:09:49.587027 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4185 23:09:49.590416
4186 23:09:49.590821
4187 23:09:49.591146 ==
4188 23:09:49.594293 Dram Type= 6, Freq= 0, CH_0, rank 0
4189 23:09:49.597530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 23:09:49.597951 ==
4191 23:09:49.598281
4192 23:09:49.598582
4193 23:09:49.600422 TX Vref Scan disable
4194 23:09:49.600832 == TX Byte 0 ==
4195 23:09:49.606983 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4196 23:09:49.610194 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4197 23:09:49.610712 == TX Byte 1 ==
4198 23:09:49.616578 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4199 23:09:49.620481 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4200 23:09:49.621070 ==
4201 23:09:49.623600 Dram Type= 6, Freq= 0, CH_0, rank 0
4202 23:09:49.627118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 23:09:49.627640 ==
4204 23:09:49.628051
4205 23:09:49.628448
4206 23:09:49.630406 TX Vref Scan disable
4207 23:09:49.633188 == TX Byte 0 ==
4208 23:09:49.636429 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4209 23:09:49.643570 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4210 23:09:49.644157 == TX Byte 1 ==
4211 23:09:49.646351 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4212 23:09:49.652659 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4213 23:09:49.653074
4214 23:09:49.653400 [DATLAT]
4215 23:09:49.653706 Freq=600, CH0 RK0
4216 23:09:49.654002
4217 23:09:49.656551 DATLAT Default: 0x9
4218 23:09:49.659410 0, 0xFFFF, sum = 0
4219 23:09:49.659965 1, 0xFFFF, sum = 0
4220 23:09:49.662655 2, 0xFFFF, sum = 0
4221 23:09:49.663072 3, 0xFFFF, sum = 0
4222 23:09:49.666311 4, 0xFFFF, sum = 0
4223 23:09:49.666848 5, 0xFFFF, sum = 0
4224 23:09:49.669643 6, 0xFFFF, sum = 0
4225 23:09:49.670065 7, 0xFFFF, sum = 0
4226 23:09:49.672570 8, 0x0, sum = 1
4227 23:09:49.673094 9, 0x0, sum = 2
4228 23:09:49.676054 10, 0x0, sum = 3
4229 23:09:49.676628 11, 0x0, sum = 4
4230 23:09:49.677154 best_step = 9
4231 23:09:49.677625
4232 23:09:49.679361 ==
4233 23:09:49.682511 Dram Type= 6, Freq= 0, CH_0, rank 0
4234 23:09:49.685978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 23:09:49.686690 ==
4236 23:09:49.687196 RX Vref Scan: 1
4237 23:09:49.687549
4238 23:09:49.689456 RX Vref 0 -> 0, step: 1
4239 23:09:49.690157
4240 23:09:49.692747 RX Delay -195 -> 252, step: 8
4241 23:09:49.693180
4242 23:09:49.696118 Set Vref, RX VrefLevel [Byte0]: 61
4243 23:09:49.698993 [Byte1]: 48
4244 23:09:49.699541
4245 23:09:49.702808 Final RX Vref Byte 0 = 61 to rank0
4246 23:09:49.705744 Final RX Vref Byte 1 = 48 to rank0
4247 23:09:49.708953 Final RX Vref Byte 0 = 61 to rank1
4248 23:09:49.712780 Final RX Vref Byte 1 = 48 to rank1==
4249 23:09:49.715455 Dram Type= 6, Freq= 0, CH_0, rank 0
4250 23:09:49.719190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 23:09:49.722164 ==
4252 23:09:49.722584 DQS Delay:
4253 23:09:49.722920 DQS0 = 0, DQS1 = 0
4254 23:09:49.725662 DQM Delay:
4255 23:09:49.726081 DQM0 = 43, DQM1 = 32
4256 23:09:49.729156 DQ Delay:
4257 23:09:49.732068 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4258 23:09:49.732492 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =48
4259 23:09:49.735741 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4260 23:09:49.739022 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4261 23:09:49.742024
4262 23:09:49.742442
4263 23:09:49.748841 [DQSOSCAuto] RK0, (LSB)MR18= 0x6138, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
4264 23:09:49.752218 CH0 RK0: MR19=808, MR18=6138
4265 23:09:49.758619 CH0_RK0: MR19=0x808, MR18=0x6138, DQSOSC=391, MR23=63, INC=171, DEC=114
4266 23:09:49.759127
4267 23:09:49.762008 ----->DramcWriteLeveling(PI) begin...
4268 23:09:49.762437 ==
4269 23:09:49.765325 Dram Type= 6, Freq= 0, CH_0, rank 1
4270 23:09:49.768552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4271 23:09:49.768976 ==
4272 23:09:49.771951 Write leveling (Byte 0): 33 => 33
4273 23:09:49.775611 Write leveling (Byte 1): 31 => 31
4274 23:09:49.778806 DramcWriteLeveling(PI) end<-----
4275 23:09:49.779226
4276 23:09:49.779557 ==
4277 23:09:49.782216 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 23:09:49.785407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 23:09:49.785831 ==
4280 23:09:49.788156 [Gating] SW mode calibration
4281 23:09:49.794928 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4282 23:09:49.801565 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4283 23:09:49.805308 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4284 23:09:49.812155 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4285 23:09:49.814744 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4286 23:09:49.818083 0 9 12 | B1->B0 | 3232 3131 | 1 0 | (1 0) (0 0)
4287 23:09:49.825019 0 9 16 | B1->B0 | 2d2d 2626 | 0 0 | (0 0) (1 1)
4288 23:09:49.827933 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4289 23:09:49.831168 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4290 23:09:49.838470 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4291 23:09:49.841239 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4292 23:09:49.845071 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4293 23:09:49.851102 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4294 23:09:49.855001 0 10 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4295 23:09:49.857916 0 10 16 | B1->B0 | 3b3b 3f3f | 0 0 | (0 0) (0 0)
4296 23:09:49.864078 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4297 23:09:49.867398 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4298 23:09:49.870879 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4299 23:09:49.877393 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4300 23:09:49.880864 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4301 23:09:49.883784 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4302 23:09:49.890749 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4303 23:09:49.894051 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4304 23:09:49.897645 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 23:09:49.903920 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 23:09:49.906947 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 23:09:49.910601 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4308 23:09:49.917084 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 23:09:49.920126 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 23:09:49.923729 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 23:09:49.930782 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 23:09:49.933698 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 23:09:49.936924 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 23:09:49.943331 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 23:09:49.946669 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 23:09:49.950130 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 23:09:49.956811 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 23:09:49.960984 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4319 23:09:49.963478 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4320 23:09:49.966807 Total UI for P1: 0, mck2ui 16
4321 23:09:49.969577 best dqsien dly found for B0: ( 0, 13, 12)
4322 23:09:49.972920 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4323 23:09:49.976115 Total UI for P1: 0, mck2ui 16
4324 23:09:49.979830 best dqsien dly found for B1: ( 0, 13, 14)
4325 23:09:49.986558 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4326 23:09:49.989255 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4327 23:09:49.989668
4328 23:09:49.993384 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4329 23:09:49.996420 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4330 23:09:49.999390 [Gating] SW calibration Done
4331 23:09:49.999850 ==
4332 23:09:50.003425 Dram Type= 6, Freq= 0, CH_0, rank 1
4333 23:09:50.005982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 23:09:50.006396 ==
4335 23:09:50.009372 RX Vref Scan: 0
4336 23:09:50.009782
4337 23:09:50.010105 RX Vref 0 -> 0, step: 1
4338 23:09:50.010410
4339 23:09:50.012685 RX Delay -230 -> 252, step: 16
4340 23:09:50.019825 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4341 23:09:50.022905 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4342 23:09:50.026183 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4343 23:09:50.029239 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4344 23:09:50.032251 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4345 23:09:50.039175 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4346 23:09:50.042593 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4347 23:09:50.045561 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4348 23:09:50.048928 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4349 23:09:50.055224 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4350 23:09:50.059127 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4351 23:09:50.063391 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4352 23:09:50.066325 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4353 23:09:50.072569 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4354 23:09:50.075083 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4355 23:09:50.078792 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4356 23:09:50.079212 ==
4357 23:09:50.081769 Dram Type= 6, Freq= 0, CH_0, rank 1
4358 23:09:50.085476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4359 23:09:50.088283 ==
4360 23:09:50.088866 DQS Delay:
4361 23:09:50.089258 DQS0 = 0, DQS1 = 0
4362 23:09:50.091920 DQM Delay:
4363 23:09:50.092342 DQM0 = 45, DQM1 = 39
4364 23:09:50.094790 DQ Delay:
4365 23:09:50.095208 DQ0 =41, DQ1 =57, DQ2 =33, DQ3 =41
4366 23:09:50.098399 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =57
4367 23:09:50.102404 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4368 23:09:50.105146 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4369 23:09:50.105555
4370 23:09:50.108527
4371 23:09:50.108935 ==
4372 23:09:50.111601 Dram Type= 6, Freq= 0, CH_0, rank 1
4373 23:09:50.114727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 23:09:50.115019 ==
4375 23:09:50.115251
4376 23:09:50.115464
4377 23:09:50.118026 TX Vref Scan disable
4378 23:09:50.118318 == TX Byte 0 ==
4379 23:09:50.124934 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4380 23:09:50.127777 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4381 23:09:50.128069 == TX Byte 1 ==
4382 23:09:50.134480 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4383 23:09:50.137788 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4384 23:09:50.138082 ==
4385 23:09:50.140985 Dram Type= 6, Freq= 0, CH_0, rank 1
4386 23:09:50.144530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4387 23:09:50.144823 ==
4388 23:09:50.145052
4389 23:09:50.145263
4390 23:09:50.147635 TX Vref Scan disable
4391 23:09:50.151328 == TX Byte 0 ==
4392 23:09:50.154234 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4393 23:09:50.161304 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4394 23:09:50.161685 == TX Byte 1 ==
4395 23:09:50.164265 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4396 23:09:50.171029 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4397 23:09:50.171388
4398 23:09:50.171621 [DATLAT]
4399 23:09:50.171872 Freq=600, CH0 RK1
4400 23:09:50.172083
4401 23:09:50.174063 DATLAT Default: 0x9
4402 23:09:50.174352 0, 0xFFFF, sum = 0
4403 23:09:50.177776 1, 0xFFFF, sum = 0
4404 23:09:50.181732 2, 0xFFFF, sum = 0
4405 23:09:50.182175 3, 0xFFFF, sum = 0
4406 23:09:50.183833 4, 0xFFFF, sum = 0
4407 23:09:50.184215 5, 0xFFFF, sum = 0
4408 23:09:50.188262 6, 0xFFFF, sum = 0
4409 23:09:50.188988 7, 0xFFFF, sum = 0
4410 23:09:50.191244 8, 0x0, sum = 1
4411 23:09:50.191659 9, 0x0, sum = 2
4412 23:09:50.193923 10, 0x0, sum = 3
4413 23:09:50.194338 11, 0x0, sum = 4
4414 23:09:50.194667 best_step = 9
4415 23:09:50.194967
4416 23:09:50.197266 ==
4417 23:09:50.197675 Dram Type= 6, Freq= 0, CH_0, rank 1
4418 23:09:50.204323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4419 23:09:50.204829 ==
4420 23:09:50.205156 RX Vref Scan: 0
4421 23:09:50.205459
4422 23:09:50.208126 RX Vref 0 -> 0, step: 1
4423 23:09:50.208536
4424 23:09:50.210812 RX Delay -179 -> 252, step: 8
4425 23:09:50.217765 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4426 23:09:50.221270 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4427 23:09:50.224628 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4428 23:09:50.227329 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4429 23:09:50.230742 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4430 23:09:50.237443 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4431 23:09:50.240351 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4432 23:09:50.243514 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4433 23:09:50.246945 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4434 23:09:50.253567 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4435 23:09:50.256826 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4436 23:09:50.260418 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4437 23:09:50.263566 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4438 23:09:50.269791 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4439 23:09:50.273598 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4440 23:09:50.276490 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4441 23:09:50.276906 ==
4442 23:09:50.279878 Dram Type= 6, Freq= 0, CH_0, rank 1
4443 23:09:50.283084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 23:09:50.283500 ==
4445 23:09:50.286738 DQS Delay:
4446 23:09:50.287256 DQS0 = 0, DQS1 = 0
4447 23:09:50.289575 DQM Delay:
4448 23:09:50.289988 DQM0 = 42, DQM1 = 37
4449 23:09:50.290312 DQ Delay:
4450 23:09:50.293275 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4451 23:09:50.296437 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4452 23:09:50.299990 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4453 23:09:50.303411 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4454 23:09:50.303996
4455 23:09:50.304335
4456 23:09:50.312879 [DQSOSCAuto] RK1, (LSB)MR18= 0x6518, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 390 ps
4457 23:09:50.316253 CH0 RK1: MR19=808, MR18=6518
4458 23:09:50.323138 CH0_RK1: MR19=0x808, MR18=0x6518, DQSOSC=390, MR23=63, INC=172, DEC=114
4459 23:09:50.326611 [RxdqsGatingPostProcess] freq 600
4460 23:09:50.329307 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4461 23:09:50.333065 Pre-setting of DQS Precalculation
4462 23:09:50.339143 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4463 23:09:50.339666 ==
4464 23:09:50.342447 Dram Type= 6, Freq= 0, CH_1, rank 0
4465 23:09:50.346452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4466 23:09:50.346961 ==
4467 23:09:50.353460 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4468 23:09:50.355495 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4469 23:09:50.360422 [CA 0] Center 35 (5~66) winsize 62
4470 23:09:50.363308 [CA 1] Center 35 (5~66) winsize 62
4471 23:09:50.366528 [CA 2] Center 34 (4~65) winsize 62
4472 23:09:50.370311 [CA 3] Center 33 (3~64) winsize 62
4473 23:09:50.373828 [CA 4] Center 34 (4~65) winsize 62
4474 23:09:50.376683 [CA 5] Center 33 (3~64) winsize 62
4475 23:09:50.377178
4476 23:09:50.380236 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4477 23:09:50.380656
4478 23:09:50.383129 [CATrainingPosCal] consider 1 rank data
4479 23:09:50.386968 u2DelayCellTimex100 = 270/100 ps
4480 23:09:50.389409 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4481 23:09:50.396402 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4482 23:09:50.399668 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4483 23:09:50.403305 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4484 23:09:50.406509 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4485 23:09:50.410504 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4486 23:09:50.411071
4487 23:09:50.412988 CA PerBit enable=1, Macro0, CA PI delay=33
4488 23:09:50.413553
4489 23:09:50.416215 [CBTSetCACLKResult] CA Dly = 33
4490 23:09:50.419869 CS Dly: 3 (0~34)
4491 23:09:50.420430 ==
4492 23:09:50.422988 Dram Type= 6, Freq= 0, CH_1, rank 1
4493 23:09:50.426537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4494 23:09:50.427109 ==
4495 23:09:50.432874 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4496 23:09:50.436694 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4497 23:09:50.441067 [CA 0] Center 35 (5~66) winsize 62
4498 23:09:50.443590 [CA 1] Center 36 (6~66) winsize 61
4499 23:09:50.446993 [CA 2] Center 34 (4~65) winsize 62
4500 23:09:50.450146 [CA 3] Center 34 (3~65) winsize 63
4501 23:09:50.453533 [CA 4] Center 34 (3~65) winsize 63
4502 23:09:50.456492 [CA 5] Center 34 (3~65) winsize 63
4503 23:09:50.456918
4504 23:09:50.460247 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4505 23:09:50.460781
4506 23:09:50.463476 [CATrainingPosCal] consider 2 rank data
4507 23:09:50.466281 u2DelayCellTimex100 = 270/100 ps
4508 23:09:50.470155 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4509 23:09:50.476465 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4510 23:09:50.479500 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4511 23:09:50.483213 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4512 23:09:50.486596 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4513 23:09:50.490030 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4514 23:09:50.490700
4515 23:09:50.493113 CA PerBit enable=1, Macro0, CA PI delay=33
4516 23:09:50.493648
4517 23:09:50.496324 [CBTSetCACLKResult] CA Dly = 33
4518 23:09:50.499460 CS Dly: 4 (0~37)
4519 23:09:50.499906
4520 23:09:50.502895 ----->DramcWriteLeveling(PI) begin...
4521 23:09:50.503312 ==
4522 23:09:50.505783 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 23:09:50.509837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 23:09:50.510354 ==
4525 23:09:50.513459 Write leveling (Byte 0): 30 => 30
4526 23:09:50.516184 Write leveling (Byte 1): 31 => 31
4527 23:09:50.519009 DramcWriteLeveling(PI) end<-----
4528 23:09:50.519500
4529 23:09:50.519886 ==
4530 23:09:50.523284 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 23:09:50.525803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 23:09:50.526221 ==
4533 23:09:50.529295 [Gating] SW mode calibration
4534 23:09:50.535799 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4535 23:09:50.542213 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4536 23:09:50.545914 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4537 23:09:50.548708 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4538 23:09:50.555491 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4539 23:09:50.558974 0 9 12 | B1->B0 | 3131 2f2f | 1 1 | (0 1) (1 0)
4540 23:09:50.562266 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4541 23:09:50.568323 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4542 23:09:50.571897 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4543 23:09:50.575315 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4544 23:09:50.581451 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4545 23:09:50.584975 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4546 23:09:50.588233 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4547 23:09:50.595080 0 10 12 | B1->B0 | 3030 3939 | 0 1 | (0 0) (1 1)
4548 23:09:50.598331 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4549 23:09:50.601515 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4550 23:09:50.608219 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4551 23:09:50.611226 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4552 23:09:50.614983 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4553 23:09:50.621275 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4554 23:09:50.624225 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4555 23:09:50.627971 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4556 23:09:50.634573 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4557 23:09:50.637338 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4558 23:09:50.644418 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4559 23:09:50.647999 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4560 23:09:50.650934 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4561 23:09:50.657504 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4562 23:09:50.660446 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4563 23:09:50.663811 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4564 23:09:50.670545 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4565 23:09:50.673564 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4566 23:09:50.677257 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4567 23:09:50.684082 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4568 23:09:50.687201 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4569 23:09:50.690944 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4570 23:09:50.697007 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4571 23:09:50.700006 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4572 23:09:50.703509 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4573 23:09:50.706608 Total UI for P1: 0, mck2ui 16
4574 23:09:50.709872 best dqsien dly found for B0: ( 0, 13, 12)
4575 23:09:50.713347 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4576 23:09:50.716548 Total UI for P1: 0, mck2ui 16
4577 23:09:50.720054 best dqsien dly found for B1: ( 0, 13, 14)
4578 23:09:50.726403 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4579 23:09:50.730066 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4580 23:09:50.730493
4581 23:09:50.733298 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4582 23:09:50.736170 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4583 23:09:50.739510 [Gating] SW calibration Done
4584 23:09:50.739987 ==
4585 23:09:50.742746 Dram Type= 6, Freq= 0, CH_1, rank 0
4586 23:09:50.746192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 23:09:50.746622 ==
4588 23:09:50.750007 RX Vref Scan: 0
4589 23:09:50.750433
4590 23:09:50.750865 RX Vref 0 -> 0, step: 1
4591 23:09:50.751274
4592 23:09:50.753695 RX Delay -230 -> 252, step: 16
4593 23:09:50.759438 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4594 23:09:50.762951 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4595 23:09:50.765987 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4596 23:09:50.769216 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4597 23:09:50.772599 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4598 23:09:50.779739 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4599 23:09:50.782400 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4600 23:09:50.785791 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4601 23:09:50.789386 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4602 23:09:50.795448 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4603 23:09:50.799127 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4604 23:09:50.802403 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4605 23:09:50.805725 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4606 23:09:50.812547 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4607 23:09:50.815189 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4608 23:09:50.818866 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4609 23:09:50.819282 ==
4610 23:09:50.822176 Dram Type= 6, Freq= 0, CH_1, rank 0
4611 23:09:50.825955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 23:09:50.828782 ==
4613 23:09:50.829199 DQS Delay:
4614 23:09:50.829526 DQS0 = 0, DQS1 = 0
4615 23:09:50.832110 DQM Delay:
4616 23:09:50.832519 DQM0 = 46, DQM1 = 34
4617 23:09:50.835607 DQ Delay:
4618 23:09:50.838712 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4619 23:09:50.839125 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4620 23:09:50.842245 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4621 23:09:50.845349 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4622 23:09:50.849058
4623 23:09:50.849566
4624 23:09:50.849894 ==
4625 23:09:50.851735 Dram Type= 6, Freq= 0, CH_1, rank 0
4626 23:09:50.854976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 23:09:50.855493 ==
4628 23:09:50.855944
4629 23:09:50.856260
4630 23:09:50.859190 TX Vref Scan disable
4631 23:09:50.859744 == TX Byte 0 ==
4632 23:09:50.865711 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4633 23:09:50.868491 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4634 23:09:50.869010 == TX Byte 1 ==
4635 23:09:50.875038 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4636 23:09:50.878199 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4637 23:09:50.878614 ==
4638 23:09:50.881901 Dram Type= 6, Freq= 0, CH_1, rank 0
4639 23:09:50.885023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 23:09:50.885441 ==
4641 23:09:50.885770
4642 23:09:50.887982
4643 23:09:50.888497 TX Vref Scan disable
4644 23:09:50.891665 == TX Byte 0 ==
4645 23:09:50.895051 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4646 23:09:50.901976 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4647 23:09:50.902397 == TX Byte 1 ==
4648 23:09:50.904373 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4649 23:09:50.911208 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4650 23:09:50.911756
4651 23:09:50.912101 [DATLAT]
4652 23:09:50.912411 Freq=600, CH1 RK0
4653 23:09:50.912736
4654 23:09:50.914617 DATLAT Default: 0x9
4655 23:09:50.915237 0, 0xFFFF, sum = 0
4656 23:09:50.918343 1, 0xFFFF, sum = 0
4657 23:09:50.921337 2, 0xFFFF, sum = 0
4658 23:09:50.921860 3, 0xFFFF, sum = 0
4659 23:09:50.925203 4, 0xFFFF, sum = 0
4660 23:09:50.925728 5, 0xFFFF, sum = 0
4661 23:09:50.927643 6, 0xFFFF, sum = 0
4662 23:09:50.928106 7, 0xFFFF, sum = 0
4663 23:09:50.930995 8, 0x0, sum = 1
4664 23:09:50.931519 9, 0x0, sum = 2
4665 23:09:50.934425 10, 0x0, sum = 3
4666 23:09:50.935042 11, 0x0, sum = 4
4667 23:09:50.935382 best_step = 9
4668 23:09:50.935733
4669 23:09:50.938257 ==
4670 23:09:50.941177 Dram Type= 6, Freq= 0, CH_1, rank 0
4671 23:09:50.944666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 23:09:50.945187 ==
4673 23:09:50.945515 RX Vref Scan: 1
4674 23:09:50.945824
4675 23:09:50.947623 RX Vref 0 -> 0, step: 1
4676 23:09:50.948080
4677 23:09:50.950836 RX Delay -195 -> 252, step: 8
4678 23:09:50.951355
4679 23:09:50.954075 Set Vref, RX VrefLevel [Byte0]: 51
4680 23:09:50.957533 [Byte1]: 58
4681 23:09:50.958056
4682 23:09:50.960735 Final RX Vref Byte 0 = 51 to rank0
4683 23:09:50.963914 Final RX Vref Byte 1 = 58 to rank0
4684 23:09:50.966987 Final RX Vref Byte 0 = 51 to rank1
4685 23:09:50.970478 Final RX Vref Byte 1 = 58 to rank1==
4686 23:09:50.973629 Dram Type= 6, Freq= 0, CH_1, rank 0
4687 23:09:50.977548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4688 23:09:50.980469 ==
4689 23:09:50.980909 DQS Delay:
4690 23:09:50.981244 DQS0 = 0, DQS1 = 0
4691 23:09:50.983347 DQM Delay:
4692 23:09:50.983789 DQM0 = 48, DQM1 = 37
4693 23:09:50.987361 DQ Delay:
4694 23:09:50.991090 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4695 23:09:50.991505 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4696 23:09:50.994015 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4697 23:09:50.999907 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4698 23:09:51.000322
4699 23:09:51.000648
4700 23:09:51.006965 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b30, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4701 23:09:51.009886 CH1 RK0: MR19=808, MR18=4B30
4702 23:09:51.016636 CH1_RK0: MR19=0x808, MR18=0x4B30, DQSOSC=395, MR23=63, INC=168, DEC=112
4703 23:09:51.017101
4704 23:09:51.020074 ----->DramcWriteLeveling(PI) begin...
4705 23:09:51.020493 ==
4706 23:09:51.023581 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 23:09:51.026773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 23:09:51.027286 ==
4709 23:09:51.030456 Write leveling (Byte 0): 29 => 29
4710 23:09:51.033124 Write leveling (Byte 1): 29 => 29
4711 23:09:51.036607 DramcWriteLeveling(PI) end<-----
4712 23:09:51.037017
4713 23:09:51.037342 ==
4714 23:09:51.039776 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 23:09:51.042804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 23:09:51.043219 ==
4717 23:09:51.046744 [Gating] SW mode calibration
4718 23:09:51.053151 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4719 23:09:51.059421 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4720 23:09:51.063077 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4721 23:09:51.069333 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4722 23:09:51.072599 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4723 23:09:51.075757 0 9 12 | B1->B0 | 2f2f 3232 | 1 1 | (1 1) (1 1)
4724 23:09:51.082598 0 9 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4725 23:09:51.086194 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4726 23:09:51.089253 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4727 23:09:51.096207 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4728 23:09:51.099008 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4729 23:09:51.102465 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4730 23:09:51.109013 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4731 23:09:51.112230 0 10 12 | B1->B0 | 3737 2d2d | 0 0 | (0 0) (0 0)
4732 23:09:51.115793 0 10 16 | B1->B0 | 4646 3d3d | 0 0 | (0 0) (0 0)
4733 23:09:51.121954 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4734 23:09:51.125955 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4735 23:09:51.129272 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4736 23:09:51.134965 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4737 23:09:51.138873 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4738 23:09:51.141720 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4739 23:09:51.148266 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4740 23:09:51.151609 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4741 23:09:51.155553 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4742 23:09:51.162053 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4743 23:09:51.165205 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4744 23:09:51.168688 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4745 23:09:51.175122 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4746 23:09:51.178234 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4747 23:09:51.181424 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4748 23:09:51.188040 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4749 23:09:51.191161 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4750 23:09:51.194967 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4751 23:09:51.201438 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4752 23:09:51.204876 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4753 23:09:51.207789 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4754 23:09:51.214551 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4755 23:09:51.217843 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4756 23:09:51.221054 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4757 23:09:51.224610 Total UI for P1: 0, mck2ui 16
4758 23:09:51.227499 best dqsien dly found for B1: ( 0, 13, 14)
4759 23:09:51.234699 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4760 23:09:51.235217 Total UI for P1: 0, mck2ui 16
4761 23:09:51.240904 best dqsien dly found for B0: ( 0, 13, 14)
4762 23:09:51.244046 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4763 23:09:51.247524 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4764 23:09:51.248097
4765 23:09:51.250992 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4766 23:09:51.253707 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4767 23:09:51.257360 [Gating] SW calibration Done
4768 23:09:51.257772 ==
4769 23:09:51.260606 Dram Type= 6, Freq= 0, CH_1, rank 1
4770 23:09:51.263635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4771 23:09:51.264101 ==
4772 23:09:51.266906 RX Vref Scan: 0
4773 23:09:51.267488
4774 23:09:51.270246 RX Vref 0 -> 0, step: 1
4775 23:09:51.270659
4776 23:09:51.270981 RX Delay -230 -> 252, step: 16
4777 23:09:51.276949 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4778 23:09:51.280125 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4779 23:09:51.284111 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4780 23:09:51.286873 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4781 23:09:51.293953 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4782 23:09:51.296672 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4783 23:09:51.299867 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4784 23:09:51.303061 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4785 23:09:51.307058 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4786 23:09:51.313214 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4787 23:09:51.317226 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4788 23:09:51.320383 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4789 23:09:51.323497 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4790 23:09:51.329977 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4791 23:09:51.333281 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4792 23:09:51.336753 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4793 23:09:51.337421 ==
4794 23:09:51.339812 Dram Type= 6, Freq= 0, CH_1, rank 1
4795 23:09:51.342900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4796 23:09:51.346583 ==
4797 23:09:51.347143 DQS Delay:
4798 23:09:51.347512 DQS0 = 0, DQS1 = 0
4799 23:09:51.350036 DQM Delay:
4800 23:09:51.350554 DQM0 = 44, DQM1 = 35
4801 23:09:51.354058 DQ Delay:
4802 23:09:51.356552 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4803 23:09:51.357032 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =33
4804 23:09:51.360053 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4805 23:09:51.363211 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4806 23:09:51.366667
4807 23:09:51.367230
4808 23:09:51.367598 ==
4809 23:09:51.369896 Dram Type= 6, Freq= 0, CH_1, rank 1
4810 23:09:51.373107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4811 23:09:51.373666 ==
4812 23:09:51.374030
4813 23:09:51.374363
4814 23:09:51.376159 TX Vref Scan disable
4815 23:09:51.376616 == TX Byte 0 ==
4816 23:09:51.383309 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4817 23:09:51.386411 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4818 23:09:51.386970 == TX Byte 1 ==
4819 23:09:51.392485 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4820 23:09:51.395724 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4821 23:09:51.396189 ==
4822 23:09:51.399658 Dram Type= 6, Freq= 0, CH_1, rank 1
4823 23:09:51.402947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4824 23:09:51.403508 ==
4825 23:09:51.403926
4826 23:09:51.405918
4827 23:09:51.406375 TX Vref Scan disable
4828 23:09:51.409830 == TX Byte 0 ==
4829 23:09:51.412634 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4830 23:09:51.419578 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4831 23:09:51.420170 == TX Byte 1 ==
4832 23:09:51.422750 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4833 23:09:51.429137 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4834 23:09:51.429655
4835 23:09:51.430011 [DATLAT]
4836 23:09:51.430344 Freq=600, CH1 RK1
4837 23:09:51.430666
4838 23:09:51.432039 DATLAT Default: 0x9
4839 23:09:51.435702 0, 0xFFFF, sum = 0
4840 23:09:51.436234 1, 0xFFFF, sum = 0
4841 23:09:51.438958 2, 0xFFFF, sum = 0
4842 23:09:51.439378 3, 0xFFFF, sum = 0
4843 23:09:51.442478 4, 0xFFFF, sum = 0
4844 23:09:51.442899 5, 0xFFFF, sum = 0
4845 23:09:51.445503 6, 0xFFFF, sum = 0
4846 23:09:51.446022 7, 0xFFFF, sum = 0
4847 23:09:51.449312 8, 0x0, sum = 1
4848 23:09:51.449885 9, 0x0, sum = 2
4849 23:09:51.452008 10, 0x0, sum = 3
4850 23:09:51.452430 11, 0x0, sum = 4
4851 23:09:51.452761 best_step = 9
4852 23:09:51.453128
4853 23:09:51.455965 ==
4854 23:09:51.459006 Dram Type= 6, Freq= 0, CH_1, rank 1
4855 23:09:51.462791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4856 23:09:51.463308 ==
4857 23:09:51.463643 RX Vref Scan: 0
4858 23:09:51.464009
4859 23:09:51.465346 RX Vref 0 -> 0, step: 1
4860 23:09:51.465763
4861 23:09:51.468585 RX Delay -195 -> 252, step: 8
4862 23:09:51.475023 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4863 23:09:51.478688 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4864 23:09:51.481807 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4865 23:09:51.484800 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4866 23:09:51.488424 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4867 23:09:51.495221 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4868 23:09:51.498200 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4869 23:09:51.501698 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4870 23:09:51.505107 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4871 23:09:51.512012 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4872 23:09:51.514886 iDelay=213, Bit 10, Center 40 (-115 ~ 196) 312
4873 23:09:51.518305 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4874 23:09:51.521242 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4875 23:09:51.528238 iDelay=213, Bit 13, Center 48 (-107 ~ 204) 312
4876 23:09:51.531668 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4877 23:09:51.534334 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4878 23:09:51.534751 ==
4879 23:09:51.537933 Dram Type= 6, Freq= 0, CH_1, rank 1
4880 23:09:51.541174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4881 23:09:51.544313 ==
4882 23:09:51.544830 DQS Delay:
4883 23:09:51.545164 DQS0 = 0, DQS1 = 0
4884 23:09:51.547735 DQM Delay:
4885 23:09:51.548258 DQM0 = 45, DQM1 = 37
4886 23:09:51.551225 DQ Delay:
4887 23:09:51.551711 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4888 23:09:51.554381 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4889 23:09:51.558557 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4890 23:09:51.561490 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =48
4891 23:09:51.564393
4892 23:09:51.564922
4893 23:09:51.571301 [DQSOSCAuto] RK1, (LSB)MR18= 0x3228, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 400 ps
4894 23:09:51.573885 CH1 RK1: MR19=808, MR18=3228
4895 23:09:51.580699 CH1_RK1: MR19=0x808, MR18=0x3228, DQSOSC=400, MR23=63, INC=163, DEC=109
4896 23:09:51.584135 [RxdqsGatingPostProcess] freq 600
4897 23:09:51.587292 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4898 23:09:51.590748 Pre-setting of DQS Precalculation
4899 23:09:51.596965 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4900 23:09:51.603560 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4901 23:09:51.609969 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4902 23:09:51.610432
4903 23:09:51.610789
4904 23:09:51.613843 [Calibration Summary] 1200 Mbps
4905 23:09:51.614421 CH 0, Rank 0
4906 23:09:51.617121 SW Impedance : PASS
4907 23:09:51.620041 DUTY Scan : NO K
4908 23:09:51.620506 ZQ Calibration : PASS
4909 23:09:51.623830 Jitter Meter : NO K
4910 23:09:51.627003 CBT Training : PASS
4911 23:09:51.627559 Write leveling : PASS
4912 23:09:51.629867 RX DQS gating : PASS
4913 23:09:51.633140 RX DQ/DQS(RDDQC) : PASS
4914 23:09:51.633701 TX DQ/DQS : PASS
4915 23:09:51.636366 RX DATLAT : PASS
4916 23:09:51.640089 RX DQ/DQS(Engine): PASS
4917 23:09:51.640643 TX OE : NO K
4918 23:09:51.642804 All Pass.
4919 23:09:51.643361
4920 23:09:51.643770 CH 0, Rank 1
4921 23:09:51.646508 SW Impedance : PASS
4922 23:09:51.646965 DUTY Scan : NO K
4923 23:09:51.649737 ZQ Calibration : PASS
4924 23:09:51.653334 Jitter Meter : NO K
4925 23:09:51.653820 CBT Training : PASS
4926 23:09:51.656455 Write leveling : PASS
4927 23:09:51.659384 RX DQS gating : PASS
4928 23:09:51.659971 RX DQ/DQS(RDDQC) : PASS
4929 23:09:51.662813 TX DQ/DQS : PASS
4930 23:09:51.663292 RX DATLAT : PASS
4931 23:09:51.666358 RX DQ/DQS(Engine): PASS
4932 23:09:51.669264 TX OE : NO K
4933 23:09:51.669840 All Pass.
4934 23:09:51.670368
4935 23:09:51.670865 CH 1, Rank 0
4936 23:09:51.672759 SW Impedance : PASS
4937 23:09:51.676055 DUTY Scan : NO K
4938 23:09:51.676583 ZQ Calibration : PASS
4939 23:09:51.679360 Jitter Meter : NO K
4940 23:09:51.682373 CBT Training : PASS
4941 23:09:51.682794 Write leveling : PASS
4942 23:09:51.685986 RX DQS gating : PASS
4943 23:09:51.689825 RX DQ/DQS(RDDQC) : PASS
4944 23:09:51.690290 TX DQ/DQS : PASS
4945 23:09:51.692516 RX DATLAT : PASS
4946 23:09:51.695715 RX DQ/DQS(Engine): PASS
4947 23:09:51.696195 TX OE : NO K
4948 23:09:51.699326 All Pass.
4949 23:09:51.699946
4950 23:09:51.700345 CH 1, Rank 1
4951 23:09:51.702199 SW Impedance : PASS
4952 23:09:51.702616 DUTY Scan : NO K
4953 23:09:51.706527 ZQ Calibration : PASS
4954 23:09:51.709397 Jitter Meter : NO K
4955 23:09:51.709864 CBT Training : PASS
4956 23:09:51.712071 Write leveling : PASS
4957 23:09:51.715584 RX DQS gating : PASS
4958 23:09:51.716181 RX DQ/DQS(RDDQC) : PASS
4959 23:09:51.719299 TX DQ/DQS : PASS
4960 23:09:51.722310 RX DATLAT : PASS
4961 23:09:51.722870 RX DQ/DQS(Engine): PASS
4962 23:09:51.725962 TX OE : NO K
4963 23:09:51.726525 All Pass.
4964 23:09:51.726892
4965 23:09:51.728734 DramC Write-DBI off
4966 23:09:51.732629 PER_BANK_REFRESH: Hybrid Mode
4967 23:09:51.733193 TX_TRACKING: ON
4968 23:09:51.743169 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4969 23:09:51.745308 [FAST_K] Save calibration result to emmc
4970 23:09:51.749332 dramc_set_vcore_voltage set vcore to 662500
4971 23:09:51.752521 Read voltage for 933, 3
4972 23:09:51.753092 Vio18 = 0
4973 23:09:51.753458 Vcore = 662500
4974 23:09:51.755630 Vdram = 0
4975 23:09:51.756128 Vddq = 0
4976 23:09:51.756491 Vmddr = 0
4977 23:09:51.762125 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4978 23:09:51.765370 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4979 23:09:51.768610 MEM_TYPE=3, freq_sel=17
4980 23:09:51.771738 sv_algorithm_assistance_LP4_1600
4981 23:09:51.774891 ============ PULL DRAM RESETB DOWN ============
4982 23:09:51.778208 ========== PULL DRAM RESETB DOWN end =========
4983 23:09:51.784679 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4984 23:09:51.788633 ===================================
4985 23:09:51.791504 LPDDR4 DRAM CONFIGURATION
4986 23:09:51.794743 ===================================
4987 23:09:51.795202 EX_ROW_EN[0] = 0x0
4988 23:09:51.798734 EX_ROW_EN[1] = 0x0
4989 23:09:51.799188 LP4Y_EN = 0x0
4990 23:09:51.801404 WORK_FSP = 0x0
4991 23:09:51.801862 WL = 0x3
4992 23:09:51.804499 RL = 0x3
4993 23:09:51.804952 BL = 0x2
4994 23:09:51.807539 RPST = 0x0
4995 23:09:51.808009 RD_PRE = 0x0
4996 23:09:51.811479 WR_PRE = 0x1
4997 23:09:51.811937 WR_PST = 0x0
4998 23:09:51.814468 DBI_WR = 0x0
4999 23:09:51.817570 DBI_RD = 0x0
5000 23:09:51.818086 OTF = 0x1
5001 23:09:51.820649 ===================================
5002 23:09:51.824098 ===================================
5003 23:09:51.824514 ANA top config
5004 23:09:51.827367 ===================================
5005 23:09:51.831480 DLL_ASYNC_EN = 0
5006 23:09:51.834345 ALL_SLAVE_EN = 1
5007 23:09:51.837075 NEW_RANK_MODE = 1
5008 23:09:51.841034 DLL_IDLE_MODE = 1
5009 23:09:51.841549 LP45_APHY_COMB_EN = 1
5010 23:09:51.843736 TX_ODT_DIS = 1
5011 23:09:51.846892 NEW_8X_MODE = 1
5012 23:09:51.850494 ===================================
5013 23:09:51.853463 ===================================
5014 23:09:51.856855 data_rate = 1866
5015 23:09:51.860398 CKR = 1
5016 23:09:51.864020 DQ_P2S_RATIO = 8
5017 23:09:51.866604 ===================================
5018 23:09:51.867023 CA_P2S_RATIO = 8
5019 23:09:51.870340 DQ_CA_OPEN = 0
5020 23:09:51.873270 DQ_SEMI_OPEN = 0
5021 23:09:51.876608 CA_SEMI_OPEN = 0
5022 23:09:51.880525 CA_FULL_RATE = 0
5023 23:09:51.883562 DQ_CKDIV4_EN = 1
5024 23:09:51.884019 CA_CKDIV4_EN = 1
5025 23:09:51.886497 CA_PREDIV_EN = 0
5026 23:09:51.889794 PH8_DLY = 0
5027 23:09:51.893040 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5028 23:09:51.896248 DQ_AAMCK_DIV = 4
5029 23:09:51.899845 CA_AAMCK_DIV = 4
5030 23:09:51.900266 CA_ADMCK_DIV = 4
5031 23:09:51.903165 DQ_TRACK_CA_EN = 0
5032 23:09:51.906494 CA_PICK = 933
5033 23:09:51.909975 CA_MCKIO = 933
5034 23:09:51.912926 MCKIO_SEMI = 0
5035 23:09:51.916350 PLL_FREQ = 3732
5036 23:09:51.919571 DQ_UI_PI_RATIO = 32
5037 23:09:51.923064 CA_UI_PI_RATIO = 0
5038 23:09:51.926144 ===================================
5039 23:09:51.929448 ===================================
5040 23:09:51.930001 memory_type:LPDDR4
5041 23:09:51.932519 GP_NUM : 10
5042 23:09:51.932991 SRAM_EN : 1
5043 23:09:51.936788 MD32_EN : 0
5044 23:09:51.939746 ===================================
5045 23:09:51.942801 [ANA_INIT] >>>>>>>>>>>>>>
5046 23:09:51.946546 <<<<<< [CONFIGURE PHASE]: ANA_TX
5047 23:09:51.950075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5048 23:09:51.952805 ===================================
5049 23:09:51.955725 data_rate = 1866,PCW = 0X8f00
5050 23:09:51.959561 ===================================
5051 23:09:51.963114 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5052 23:09:51.966494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5053 23:09:51.972792 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5054 23:09:51.976082 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5055 23:09:51.979230 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5056 23:09:51.982601 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5057 23:09:51.985451 [ANA_INIT] flow start
5058 23:09:51.989123 [ANA_INIT] PLL >>>>>>>>
5059 23:09:51.989678 [ANA_INIT] PLL <<<<<<<<
5060 23:09:51.992416 [ANA_INIT] MIDPI >>>>>>>>
5061 23:09:51.995816 [ANA_INIT] MIDPI <<<<<<<<
5062 23:09:51.998947 [ANA_INIT] DLL >>>>>>>>
5063 23:09:51.999402 [ANA_INIT] flow end
5064 23:09:52.002065 ============ LP4 DIFF to SE enter ============
5065 23:09:52.008899 ============ LP4 DIFF to SE exit ============
5066 23:09:52.009453 [ANA_INIT] <<<<<<<<<<<<<
5067 23:09:52.012317 [Flow] Enable top DCM control >>>>>
5068 23:09:52.015665 [Flow] Enable top DCM control <<<<<
5069 23:09:52.018794 Enable DLL master slave shuffle
5070 23:09:52.025399 ==============================================================
5071 23:09:52.025864 Gating Mode config
5072 23:09:52.032132 ==============================================================
5073 23:09:52.035031 Config description:
5074 23:09:52.045073 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5075 23:09:52.051978 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5076 23:09:52.054736 SELPH_MODE 0: By rank 1: By Phase
5077 23:09:52.061650 ==============================================================
5078 23:09:52.064961 GAT_TRACK_EN = 1
5079 23:09:52.068464 RX_GATING_MODE = 2
5080 23:09:52.069023 RX_GATING_TRACK_MODE = 2
5081 23:09:52.071381 SELPH_MODE = 1
5082 23:09:52.074804 PICG_EARLY_EN = 1
5083 23:09:52.077787 VALID_LAT_VALUE = 1
5084 23:09:52.084493 ==============================================================
5085 23:09:52.088148 Enter into Gating configuration >>>>
5086 23:09:52.090894 Exit from Gating configuration <<<<
5087 23:09:52.094947 Enter into DVFS_PRE_config >>>>>
5088 23:09:52.104326 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5089 23:09:52.107382 Exit from DVFS_PRE_config <<<<<
5090 23:09:52.111059 Enter into PICG configuration >>>>
5091 23:09:52.114726 Exit from PICG configuration <<<<
5092 23:09:52.117646 [RX_INPUT] configuration >>>>>
5093 23:09:52.121041 [RX_INPUT] configuration <<<<<
5094 23:09:52.125225 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5095 23:09:52.130884 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5096 23:09:52.138041 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5097 23:09:52.143650 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5098 23:09:52.150672 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5099 23:09:52.153898 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5100 23:09:52.160575 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5101 23:09:52.163654 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5102 23:09:52.167250 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5103 23:09:52.170877 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5104 23:09:52.177357 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5105 23:09:52.180634 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5106 23:09:52.183402 ===================================
5107 23:09:52.187434 LPDDR4 DRAM CONFIGURATION
5108 23:09:52.190223 ===================================
5109 23:09:52.190641 EX_ROW_EN[0] = 0x0
5110 23:09:52.193412 EX_ROW_EN[1] = 0x0
5111 23:09:52.193890 LP4Y_EN = 0x0
5112 23:09:52.197124 WORK_FSP = 0x0
5113 23:09:52.197687 WL = 0x3
5114 23:09:52.199858 RL = 0x3
5115 23:09:52.200329 BL = 0x2
5116 23:09:52.203990 RPST = 0x0
5117 23:09:52.207543 RD_PRE = 0x0
5118 23:09:52.208150 WR_PRE = 0x1
5119 23:09:52.209679 WR_PST = 0x0
5120 23:09:52.210233 DBI_WR = 0x0
5121 23:09:52.212858 DBI_RD = 0x0
5122 23:09:52.213316 OTF = 0x1
5123 23:09:52.216649 ===================================
5124 23:09:52.220309 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5125 23:09:52.226567 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5126 23:09:52.229780 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5127 23:09:52.233475 ===================================
5128 23:09:52.236470 LPDDR4 DRAM CONFIGURATION
5129 23:09:52.239851 ===================================
5130 23:09:52.240309 EX_ROW_EN[0] = 0x10
5131 23:09:52.243380 EX_ROW_EN[1] = 0x0
5132 23:09:52.243974 LP4Y_EN = 0x0
5133 23:09:52.247026 WORK_FSP = 0x0
5134 23:09:52.247589 WL = 0x3
5135 23:09:52.250019 RL = 0x3
5136 23:09:52.250583 BL = 0x2
5137 23:09:52.253557 RPST = 0x0
5138 23:09:52.254012 RD_PRE = 0x0
5139 23:09:52.256705 WR_PRE = 0x1
5140 23:09:52.259841 WR_PST = 0x0
5141 23:09:52.260300 DBI_WR = 0x0
5142 23:09:52.262738 DBI_RD = 0x0
5143 23:09:52.263292 OTF = 0x1
5144 23:09:52.266786 ===================================
5145 23:09:52.273000 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5146 23:09:52.276608 nWR fixed to 30
5147 23:09:52.280263 [ModeRegInit_LP4] CH0 RK0
5148 23:09:52.280845 [ModeRegInit_LP4] CH0 RK1
5149 23:09:52.282990 [ModeRegInit_LP4] CH1 RK0
5150 23:09:52.286143 [ModeRegInit_LP4] CH1 RK1
5151 23:09:52.286598 match AC timing 9
5152 23:09:52.292884 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5153 23:09:52.296650 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5154 23:09:52.299707 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5155 23:09:52.308238 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5156 23:09:52.309606 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5157 23:09:52.310062 ==
5158 23:09:52.312993 Dram Type= 6, Freq= 0, CH_0, rank 0
5159 23:09:52.316271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5160 23:09:52.316731 ==
5161 23:09:52.322771 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5162 23:09:52.329293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5163 23:09:52.332517 [CA 0] Center 37 (7~68) winsize 62
5164 23:09:52.336357 [CA 1] Center 37 (7~68) winsize 62
5165 23:09:52.339429 [CA 2] Center 34 (4~65) winsize 62
5166 23:09:52.342236 [CA 3] Center 34 (4~65) winsize 62
5167 23:09:52.346017 [CA 4] Center 33 (3~64) winsize 62
5168 23:09:52.349781 [CA 5] Center 33 (3~64) winsize 62
5169 23:09:52.350303
5170 23:09:52.353462 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5171 23:09:52.353921
5172 23:09:52.355791 [CATrainingPosCal] consider 1 rank data
5173 23:09:52.359443 u2DelayCellTimex100 = 270/100 ps
5174 23:09:52.362723 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5175 23:09:52.366299 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5176 23:09:52.369065 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5177 23:09:52.372544 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5178 23:09:52.376053 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5179 23:09:52.382987 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5180 23:09:52.383554
5181 23:09:52.385524 CA PerBit enable=1, Macro0, CA PI delay=33
5182 23:09:52.385981
5183 23:09:52.389201 [CBTSetCACLKResult] CA Dly = 33
5184 23:09:52.389756 CS Dly: 7 (0~38)
5185 23:09:52.390122 ==
5186 23:09:52.393363 Dram Type= 6, Freq= 0, CH_0, rank 1
5187 23:09:52.395495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5188 23:09:52.399265 ==
5189 23:09:52.403167 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5190 23:09:52.408862 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5191 23:09:52.412064 [CA 0] Center 37 (7~68) winsize 62
5192 23:09:52.415734 [CA 1] Center 37 (7~68) winsize 62
5193 23:09:52.418783 [CA 2] Center 34 (4~65) winsize 62
5194 23:09:52.422381 [CA 3] Center 34 (4~65) winsize 62
5195 23:09:52.425521 [CA 4] Center 33 (3~64) winsize 62
5196 23:09:52.429021 [CA 5] Center 32 (2~63) winsize 62
5197 23:09:52.429575
5198 23:09:52.431950 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5199 23:09:52.432501
5200 23:09:52.435359 [CATrainingPosCal] consider 2 rank data
5201 23:09:52.438388 u2DelayCellTimex100 = 270/100 ps
5202 23:09:52.441791 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5203 23:09:52.444673 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5204 23:09:52.452129 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5205 23:09:52.454792 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5206 23:09:52.459522 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5207 23:09:52.462147 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5208 23:09:52.462705
5209 23:09:52.465346 CA PerBit enable=1, Macro0, CA PI delay=33
5210 23:09:52.465906
5211 23:09:52.468262 [CBTSetCACLKResult] CA Dly = 33
5212 23:09:52.468820 CS Dly: 7 (0~39)
5213 23:09:52.469185
5214 23:09:52.471509 ----->DramcWriteLeveling(PI) begin...
5215 23:09:52.474619 ==
5216 23:09:52.478150 Dram Type= 6, Freq= 0, CH_0, rank 0
5217 23:09:52.481372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5218 23:09:52.481839 ==
5219 23:09:52.484422 Write leveling (Byte 0): 33 => 33
5220 23:09:52.487850 Write leveling (Byte 1): 28 => 28
5221 23:09:52.491580 DramcWriteLeveling(PI) end<-----
5222 23:09:52.492190
5223 23:09:52.492556 ==
5224 23:09:52.494611 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 23:09:52.498081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 23:09:52.498648 ==
5227 23:09:52.501486 [Gating] SW mode calibration
5228 23:09:52.508029 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5229 23:09:52.514672 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5230 23:09:52.518187 0 14 0 | B1->B0 | 2323 3131 | 1 1 | (1 1) (1 1)
5231 23:09:52.520609 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5232 23:09:52.528070 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5233 23:09:52.530943 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5234 23:09:52.534363 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5235 23:09:52.540860 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5236 23:09:52.544501 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5237 23:09:52.547495 0 14 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
5238 23:09:52.553845 0 15 0 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
5239 23:09:52.557041 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5240 23:09:52.560315 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5241 23:09:52.567328 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5242 23:09:52.571064 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5243 23:09:52.573959 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5244 23:09:52.581031 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5245 23:09:52.584161 0 15 28 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5246 23:09:52.586922 1 0 0 | B1->B0 | 3434 4343 | 1 0 | (0 0) (1 1)
5247 23:09:52.592932 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5248 23:09:52.596338 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5249 23:09:52.599902 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5250 23:09:52.606930 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5251 23:09:52.609935 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5252 23:09:52.613426 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5253 23:09:52.620469 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5254 23:09:52.623445 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5255 23:09:52.626482 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5256 23:09:52.632957 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5257 23:09:52.636356 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5258 23:09:52.639718 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5259 23:09:52.646116 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5260 23:09:52.649415 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5261 23:09:52.652398 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5262 23:09:52.659158 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5263 23:09:52.662605 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5264 23:09:52.665691 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5265 23:09:52.672073 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5266 23:09:52.675659 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5267 23:09:52.678933 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5268 23:09:52.685737 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5269 23:09:52.689153 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5270 23:09:52.692534 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5271 23:09:52.695332 Total UI for P1: 0, mck2ui 16
5272 23:09:52.698849 best dqsien dly found for B0: ( 1, 2, 28)
5273 23:09:52.705608 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5274 23:09:52.708568 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5275 23:09:52.711398 Total UI for P1: 0, mck2ui 16
5276 23:09:52.714757 best dqsien dly found for B1: ( 1, 3, 0)
5277 23:09:52.718322 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5278 23:09:52.721357 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5279 23:09:52.721814
5280 23:09:52.725229 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5281 23:09:52.728293 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5282 23:09:52.731370 [Gating] SW calibration Done
5283 23:09:52.731990 ==
5284 23:09:52.735369 Dram Type= 6, Freq= 0, CH_0, rank 0
5285 23:09:52.741344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 23:09:52.741903 ==
5287 23:09:52.742271 RX Vref Scan: 0
5288 23:09:52.742609
5289 23:09:52.744410 RX Vref 0 -> 0, step: 1
5290 23:09:52.744869
5291 23:09:52.748115 RX Delay -80 -> 252, step: 8
5292 23:09:52.751868 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5293 23:09:52.754601 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5294 23:09:52.758475 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5295 23:09:52.761500 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5296 23:09:52.765299 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5297 23:09:52.771667 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5298 23:09:52.774966 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5299 23:09:52.777551 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5300 23:09:52.781462 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5301 23:09:52.784289 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5302 23:09:52.791008 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5303 23:09:52.794352 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5304 23:09:52.797742 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5305 23:09:52.801048 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5306 23:09:52.804285 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5307 23:09:52.810736 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5308 23:09:52.811354 ==
5309 23:09:52.814112 Dram Type= 6, Freq= 0, CH_0, rank 0
5310 23:09:52.817174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5311 23:09:52.817640 ==
5312 23:09:52.818007 DQS Delay:
5313 23:09:52.820674 DQS0 = 0, DQS1 = 0
5314 23:09:52.821133 DQM Delay:
5315 23:09:52.823885 DQM0 = 96, DQM1 = 84
5316 23:09:52.824452 DQ Delay:
5317 23:09:52.826940 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5318 23:09:52.830834 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =103
5319 23:09:52.833734 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =79
5320 23:09:52.837015 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5321 23:09:52.837587
5322 23:09:52.837956
5323 23:09:52.838294 ==
5324 23:09:52.840086 Dram Type= 6, Freq= 0, CH_0, rank 0
5325 23:09:52.847006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 23:09:52.847551 ==
5327 23:09:52.847950
5328 23:09:52.848290
5329 23:09:52.848614 TX Vref Scan disable
5330 23:09:52.850859 == TX Byte 0 ==
5331 23:09:52.853642 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5332 23:09:52.860427 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5333 23:09:52.860991 == TX Byte 1 ==
5334 23:09:52.863335 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5335 23:09:52.870091 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5336 23:09:52.870667 ==
5337 23:09:52.873262 Dram Type= 6, Freq= 0, CH_0, rank 0
5338 23:09:52.876428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5339 23:09:52.876890 ==
5340 23:09:52.877258
5341 23:09:52.877595
5342 23:09:52.879933 TX Vref Scan disable
5343 23:09:52.883280 == TX Byte 0 ==
5344 23:09:52.886302 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5345 23:09:52.889943 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5346 23:09:52.892889 == TX Byte 1 ==
5347 23:09:52.896599 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5348 23:09:52.899900 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5349 23:09:52.900454
5350 23:09:52.900812 [DATLAT]
5351 23:09:52.902719 Freq=933, CH0 RK0
5352 23:09:52.903178
5353 23:09:52.905784 DATLAT Default: 0xd
5354 23:09:52.906239 0, 0xFFFF, sum = 0
5355 23:09:52.909209 1, 0xFFFF, sum = 0
5356 23:09:52.909672 2, 0xFFFF, sum = 0
5357 23:09:52.912458 3, 0xFFFF, sum = 0
5358 23:09:52.912924 4, 0xFFFF, sum = 0
5359 23:09:52.916549 5, 0xFFFF, sum = 0
5360 23:09:52.917019 6, 0xFFFF, sum = 0
5361 23:09:52.919411 7, 0xFFFF, sum = 0
5362 23:09:52.919944 8, 0xFFFF, sum = 0
5363 23:09:52.922700 9, 0xFFFF, sum = 0
5364 23:09:52.923118 10, 0x0, sum = 1
5365 23:09:52.925862 11, 0x0, sum = 2
5366 23:09:52.926294 12, 0x0, sum = 3
5367 23:09:52.929998 13, 0x0, sum = 4
5368 23:09:52.930482 best_step = 11
5369 23:09:52.930949
5370 23:09:52.931269 ==
5371 23:09:52.931952 Dram Type= 6, Freq= 0, CH_0, rank 0
5372 23:09:52.935547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 23:09:52.938414 ==
5374 23:09:52.938708 RX Vref Scan: 1
5375 23:09:52.938939
5376 23:09:52.942652 RX Vref 0 -> 0, step: 1
5377 23:09:52.943065
5378 23:09:52.946349 RX Delay -69 -> 252, step: 4
5379 23:09:52.946940
5380 23:09:52.948554 Set Vref, RX VrefLevel [Byte0]: 61
5381 23:09:52.951798 [Byte1]: 48
5382 23:09:52.952213
5383 23:09:52.955712 Final RX Vref Byte 0 = 61 to rank0
5384 23:09:52.959435 Final RX Vref Byte 1 = 48 to rank0
5385 23:09:52.962145 Final RX Vref Byte 0 = 61 to rank1
5386 23:09:52.965674 Final RX Vref Byte 1 = 48 to rank1==
5387 23:09:52.968365 Dram Type= 6, Freq= 0, CH_0, rank 0
5388 23:09:52.972101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5389 23:09:52.972518 ==
5390 23:09:52.975824 DQS Delay:
5391 23:09:52.976236 DQS0 = 0, DQS1 = 0
5392 23:09:52.976562 DQM Delay:
5393 23:09:52.978505 DQM0 = 97, DQM1 = 85
5394 23:09:52.978918 DQ Delay:
5395 23:09:52.981681 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5396 23:09:52.985402 DQ4 =96, DQ5 =88, DQ6 =108, DQ7 =106
5397 23:09:52.988446 DQ8 =78, DQ9 =74, DQ10 =84, DQ11 =78
5398 23:09:52.991991 DQ12 =90, DQ13 =88, DQ14 =98, DQ15 =90
5399 23:09:52.992405
5400 23:09:52.992728
5401 23:09:53.001623 [DQSOSCAuto] RK0, (LSB)MR18= 0x290f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5402 23:09:53.005070 CH0 RK0: MR19=505, MR18=290F
5403 23:09:53.008451 CH0_RK0: MR19=0x505, MR18=0x290F, DQSOSC=408, MR23=63, INC=65, DEC=43
5404 23:09:53.008869
5405 23:09:53.015241 ----->DramcWriteLeveling(PI) begin...
5406 23:09:53.015660 ==
5407 23:09:53.018783 Dram Type= 6, Freq= 0, CH_0, rank 1
5408 23:09:53.021605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5409 23:09:53.022020 ==
5410 23:09:53.024955 Write leveling (Byte 0): 34 => 34
5411 23:09:53.028095 Write leveling (Byte 1): 28 => 28
5412 23:09:53.031627 DramcWriteLeveling(PI) end<-----
5413 23:09:53.032081
5414 23:09:53.032409 ==
5415 23:09:53.034868 Dram Type= 6, Freq= 0, CH_0, rank 1
5416 23:09:53.038055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5417 23:09:53.038472 ==
5418 23:09:53.041353 [Gating] SW mode calibration
5419 23:09:53.048588 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5420 23:09:53.054459 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5421 23:09:53.057684 0 14 0 | B1->B0 | 2929 3131 | 0 0 | (0 0) (0 0)
5422 23:09:53.061462 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5423 23:09:53.067821 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5424 23:09:53.071159 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5425 23:09:53.074574 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5426 23:09:53.080900 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5427 23:09:53.084233 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5428 23:09:53.088166 0 14 28 | B1->B0 | 3232 2d2d | 1 1 | (1 1) (1 0)
5429 23:09:53.094129 0 15 0 | B1->B0 | 2e2e 2525 | 1 1 | (1 0) (1 0)
5430 23:09:53.097315 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
5431 23:09:53.101211 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5432 23:09:53.107260 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5433 23:09:53.110997 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5434 23:09:53.113792 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5435 23:09:53.120662 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5436 23:09:53.124414 0 15 28 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5437 23:09:53.127165 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5438 23:09:53.134451 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5439 23:09:53.137111 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5440 23:09:53.140215 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5441 23:09:53.147532 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5442 23:09:53.150801 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5443 23:09:53.154208 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5444 23:09:53.160235 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5445 23:09:53.163476 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 23:09:53.167121 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 23:09:53.173804 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 23:09:53.177500 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 23:09:53.180461 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 23:09:53.187215 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 23:09:53.189735 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 23:09:53.193072 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 23:09:53.199568 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 23:09:53.203277 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5455 23:09:53.206719 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5456 23:09:53.213584 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5457 23:09:53.216494 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5458 23:09:53.219830 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5459 23:09:53.226874 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5460 23:09:53.230103 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5461 23:09:53.233372 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5462 23:09:53.236644 Total UI for P1: 0, mck2ui 16
5463 23:09:53.239999 best dqsien dly found for B0: ( 1, 2, 28)
5464 23:09:53.243431 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5465 23:09:53.246962 Total UI for P1: 0, mck2ui 16
5466 23:09:53.249474 best dqsien dly found for B1: ( 1, 3, 0)
5467 23:09:53.253080 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5468 23:09:53.259508 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5469 23:09:53.260116
5470 23:09:53.262922 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5471 23:09:53.266350 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5472 23:09:53.269759 [Gating] SW calibration Done
5473 23:09:53.270318 ==
5474 23:09:53.272989 Dram Type= 6, Freq= 0, CH_0, rank 1
5475 23:09:53.276067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 23:09:53.276529 ==
5477 23:09:53.279666 RX Vref Scan: 0
5478 23:09:53.280428
5479 23:09:53.280807 RX Vref 0 -> 0, step: 1
5480 23:09:53.281161
5481 23:09:53.282825 RX Delay -80 -> 252, step: 8
5482 23:09:53.285957 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5483 23:09:53.289467 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5484 23:09:53.295838 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5485 23:09:53.299219 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5486 23:09:53.302478 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5487 23:09:53.305816 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5488 23:09:53.308927 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5489 23:09:53.313324 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5490 23:09:53.318813 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5491 23:09:53.322089 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5492 23:09:53.325689 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5493 23:09:53.328968 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5494 23:09:53.332284 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5495 23:09:53.338787 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5496 23:09:53.341770 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5497 23:09:53.345422 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5498 23:09:53.345886 ==
5499 23:09:53.348342 Dram Type= 6, Freq= 0, CH_0, rank 1
5500 23:09:53.351773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5501 23:09:53.352229 ==
5502 23:09:53.355555 DQS Delay:
5503 23:09:53.356132 DQS0 = 0, DQS1 = 0
5504 23:09:53.358396 DQM Delay:
5505 23:09:53.358810 DQM0 = 97, DQM1 = 87
5506 23:09:53.359142 DQ Delay:
5507 23:09:53.362206 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5508 23:09:53.365080 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5509 23:09:53.368590 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5510 23:09:53.371821 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5511 23:09:53.372341
5512 23:09:53.375448
5513 23:09:53.376097 ==
5514 23:09:53.378250 Dram Type= 6, Freq= 0, CH_0, rank 1
5515 23:09:53.381514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 23:09:53.381932 ==
5517 23:09:53.382261
5518 23:09:53.382569
5519 23:09:53.385185 TX Vref Scan disable
5520 23:09:53.385600 == TX Byte 0 ==
5521 23:09:53.391957 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5522 23:09:53.394949 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5523 23:09:53.395462 == TX Byte 1 ==
5524 23:09:53.401088 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5525 23:09:53.404780 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5526 23:09:53.405403 ==
5527 23:09:53.407964 Dram Type= 6, Freq= 0, CH_0, rank 1
5528 23:09:53.411386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5529 23:09:53.411847 ==
5530 23:09:53.412237
5531 23:09:53.412565
5532 23:09:53.414222 TX Vref Scan disable
5533 23:09:53.417536 == TX Byte 0 ==
5534 23:09:53.421043 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5535 23:09:53.424663 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5536 23:09:53.428192 == TX Byte 1 ==
5537 23:09:53.431131 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5538 23:09:53.434718 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5539 23:09:53.437440
5540 23:09:53.437853 [DATLAT]
5541 23:09:53.438216 Freq=933, CH0 RK1
5542 23:09:53.438707
5543 23:09:53.441441 DATLAT Default: 0xb
5544 23:09:53.441974 0, 0xFFFF, sum = 0
5545 23:09:53.444306 1, 0xFFFF, sum = 0
5546 23:09:53.444728 2, 0xFFFF, sum = 0
5547 23:09:53.447972 3, 0xFFFF, sum = 0
5548 23:09:53.448501 4, 0xFFFF, sum = 0
5549 23:09:53.450903 5, 0xFFFF, sum = 0
5550 23:09:53.451328 6, 0xFFFF, sum = 0
5551 23:09:53.454532 7, 0xFFFF, sum = 0
5552 23:09:53.457353 8, 0xFFFF, sum = 0
5553 23:09:53.457775 9, 0xFFFF, sum = 0
5554 23:09:53.461063 10, 0x0, sum = 1
5555 23:09:53.461594 11, 0x0, sum = 2
5556 23:09:53.461932 12, 0x0, sum = 3
5557 23:09:53.464466 13, 0x0, sum = 4
5558 23:09:53.464890 best_step = 11
5559 23:09:53.465219
5560 23:09:53.465526 ==
5561 23:09:53.467696 Dram Type= 6, Freq= 0, CH_0, rank 1
5562 23:09:53.473757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 23:09:53.474273 ==
5564 23:09:53.474609 RX Vref Scan: 0
5565 23:09:53.474920
5566 23:09:53.477401 RX Vref 0 -> 0, step: 1
5567 23:09:53.477980
5568 23:09:53.480490 RX Delay -61 -> 252, step: 4
5569 23:09:53.484195 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5570 23:09:53.490540 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5571 23:09:53.493806 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5572 23:09:53.497680 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5573 23:09:53.500559 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5574 23:09:53.503623 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5575 23:09:53.507086 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5576 23:09:53.513285 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5577 23:09:53.517245 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5578 23:09:53.520616 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5579 23:09:53.523209 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5580 23:09:53.529984 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5581 23:09:53.533336 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5582 23:09:53.536640 iDelay=203, Bit 13, Center 94 (-1 ~ 190) 192
5583 23:09:53.540234 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5584 23:09:53.543448 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5585 23:09:53.544015 ==
5586 23:09:53.546403 Dram Type= 6, Freq= 0, CH_0, rank 1
5587 23:09:53.553381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5588 23:09:53.553910 ==
5589 23:09:53.554243 DQS Delay:
5590 23:09:53.556246 DQS0 = 0, DQS1 = 0
5591 23:09:53.556662 DQM Delay:
5592 23:09:53.556988 DQM0 = 95, DQM1 = 86
5593 23:09:53.559724 DQ Delay:
5594 23:09:53.563429 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94
5595 23:09:53.566767 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5596 23:09:53.569652 DQ8 =76, DQ9 =74, DQ10 =88, DQ11 =78
5597 23:09:53.572927 DQ12 =92, DQ13 =94, DQ14 =98, DQ15 =92
5598 23:09:53.573388
5599 23:09:53.573751
5600 23:09:53.579624 [DQSOSCAuto] RK1, (LSB)MR18= 0x27f7, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5601 23:09:53.582774 CH0 RK1: MR19=504, MR18=27F7
5602 23:09:53.589289 CH0_RK1: MR19=0x504, MR18=0x27F7, DQSOSC=409, MR23=63, INC=64, DEC=43
5603 23:09:53.592363 [RxdqsGatingPostProcess] freq 933
5604 23:09:53.598883 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5605 23:09:53.599302 best DQS0 dly(2T, 0.5T) = (0, 10)
5606 23:09:53.602195 best DQS1 dly(2T, 0.5T) = (0, 11)
5607 23:09:53.605871 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5608 23:09:53.609864 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5609 23:09:53.612689 best DQS0 dly(2T, 0.5T) = (0, 10)
5610 23:09:53.615704 best DQS1 dly(2T, 0.5T) = (0, 11)
5611 23:09:53.619033 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5612 23:09:53.622430 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5613 23:09:53.625620 Pre-setting of DQS Precalculation
5614 23:09:53.632329 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5615 23:09:53.632748 ==
5616 23:09:53.635476 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 23:09:53.639291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 23:09:53.639856 ==
5619 23:09:53.645421 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5620 23:09:53.648606 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5621 23:09:53.652939 [CA 0] Center 36 (6~67) winsize 62
5622 23:09:53.656280 [CA 1] Center 36 (6~67) winsize 62
5623 23:09:53.659011 [CA 2] Center 34 (4~65) winsize 62
5624 23:09:53.662608 [CA 3] Center 33 (3~64) winsize 62
5625 23:09:53.665568 [CA 4] Center 34 (4~64) winsize 61
5626 23:09:53.668733 [CA 5] Center 33 (3~64) winsize 62
5627 23:09:53.669152
5628 23:09:53.672100 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5629 23:09:53.672521
5630 23:09:53.678623 [CATrainingPosCal] consider 1 rank data
5631 23:09:53.679042 u2DelayCellTimex100 = 270/100 ps
5632 23:09:53.685682 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5633 23:09:53.688848 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5634 23:09:53.691805 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5635 23:09:53.695461 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5636 23:09:53.698690 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5637 23:09:53.701473 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5638 23:09:53.701895
5639 23:09:53.704920 CA PerBit enable=1, Macro0, CA PI delay=33
5640 23:09:53.705336
5641 23:09:53.708160 [CBTSetCACLKResult] CA Dly = 33
5642 23:09:53.712139 CS Dly: 6 (0~37)
5643 23:09:53.712570 ==
5644 23:09:53.715379 Dram Type= 6, Freq= 0, CH_1, rank 1
5645 23:09:53.718599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 23:09:53.719144 ==
5647 23:09:53.725241 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5648 23:09:53.731446 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5649 23:09:53.734541 [CA 0] Center 36 (6~67) winsize 62
5650 23:09:53.738437 [CA 1] Center 36 (6~67) winsize 62
5651 23:09:53.741534 [CA 2] Center 34 (4~65) winsize 62
5652 23:09:53.744288 [CA 3] Center 33 (3~64) winsize 62
5653 23:09:53.748479 [CA 4] Center 34 (3~65) winsize 63
5654 23:09:53.749066 [CA 5] Center 33 (3~64) winsize 62
5655 23:09:53.751844
5656 23:09:53.754573 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5657 23:09:53.754995
5658 23:09:53.757794 [CATrainingPosCal] consider 2 rank data
5659 23:09:53.760805 u2DelayCellTimex100 = 270/100 ps
5660 23:09:53.764205 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5661 23:09:53.767562 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5662 23:09:53.771246 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5663 23:09:53.774649 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5664 23:09:53.778162 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5665 23:09:53.781584 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5666 23:09:53.782057
5667 23:09:53.784116 CA PerBit enable=1, Macro0, CA PI delay=33
5668 23:09:53.787727
5669 23:09:53.788143 [CBTSetCACLKResult] CA Dly = 33
5670 23:09:53.790966 CS Dly: 7 (0~39)
5671 23:09:53.791415
5672 23:09:53.794231 ----->DramcWriteLeveling(PI) begin...
5673 23:09:53.794654 ==
5674 23:09:53.797256 Dram Type= 6, Freq= 0, CH_1, rank 0
5675 23:09:53.800492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5676 23:09:53.800907 ==
5677 23:09:53.804127 Write leveling (Byte 0): 27 => 27
5678 23:09:53.807212 Write leveling (Byte 1): 27 => 27
5679 23:09:53.810579 DramcWriteLeveling(PI) end<-----
5680 23:09:53.810994
5681 23:09:53.811322 ==
5682 23:09:53.814727 Dram Type= 6, Freq= 0, CH_1, rank 0
5683 23:09:53.820623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5684 23:09:53.821044 ==
5685 23:09:53.821379 [Gating] SW mode calibration
5686 23:09:53.830698 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5687 23:09:53.833777 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5688 23:09:53.840948 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5689 23:09:53.843655 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5690 23:09:53.847118 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5691 23:09:53.853391 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5692 23:09:53.856885 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5693 23:09:53.859816 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5694 23:09:53.866478 0 14 24 | B1->B0 | 3434 3333 | 0 1 | (0 0) (1 0)
5695 23:09:53.869572 0 14 28 | B1->B0 | 2e2e 2c2c | 1 0 | (1 0) (1 0)
5696 23:09:53.873018 0 15 0 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
5697 23:09:53.879363 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5698 23:09:53.883109 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5699 23:09:53.886132 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5700 23:09:53.892776 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5701 23:09:53.896054 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5702 23:09:53.899473 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5703 23:09:53.905987 0 15 28 | B1->B0 | 3737 3c3c | 0 0 | (0 0) (1 1)
5704 23:09:53.908779 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5705 23:09:53.912289 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5706 23:09:53.918909 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5707 23:09:53.922435 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5708 23:09:53.925734 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5709 23:09:53.932631 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5710 23:09:53.935840 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5711 23:09:53.939388 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5712 23:09:53.945609 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5713 23:09:53.948748 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5714 23:09:53.952380 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5715 23:09:53.958464 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5716 23:09:53.961978 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5717 23:09:53.965159 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5718 23:09:53.971914 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5719 23:09:53.974779 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5720 23:09:53.978701 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5721 23:09:53.984835 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5722 23:09:53.988096 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5723 23:09:53.991804 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5724 23:09:53.998010 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5725 23:09:54.001718 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5726 23:09:54.004678 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5727 23:09:54.008016 Total UI for P1: 0, mck2ui 16
5728 23:09:54.011503 best dqsien dly found for B0: ( 1, 2, 20)
5729 23:09:54.017981 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5730 23:09:54.021100 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5731 23:09:54.024505 Total UI for P1: 0, mck2ui 16
5732 23:09:54.027548 best dqsien dly found for B1: ( 1, 2, 26)
5733 23:09:54.030991 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5734 23:09:54.034590 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5735 23:09:54.035112
5736 23:09:54.037550 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5737 23:09:54.041090 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5738 23:09:54.044325 [Gating] SW calibration Done
5739 23:09:54.044741 ==
5740 23:09:54.047813 Dram Type= 6, Freq= 0, CH_1, rank 0
5741 23:09:54.050562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 23:09:54.054089 ==
5743 23:09:54.054761 RX Vref Scan: 0
5744 23:09:54.055357
5745 23:09:54.058302 RX Vref 0 -> 0, step: 1
5746 23:09:54.058956
5747 23:09:54.060662 RX Delay -80 -> 252, step: 8
5748 23:09:54.064405 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5749 23:09:54.066986 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5750 23:09:54.070581 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5751 23:09:54.073950 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5752 23:09:54.077018 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5753 23:09:54.084610 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5754 23:09:54.087376 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5755 23:09:54.090908 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5756 23:09:54.093928 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5757 23:09:54.097139 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5758 23:09:54.103710 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5759 23:09:54.107008 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5760 23:09:54.110972 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5761 23:09:54.113168 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5762 23:09:54.117114 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5763 23:09:54.119888 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5764 23:09:54.123549 ==
5765 23:09:54.127114 Dram Type= 6, Freq= 0, CH_1, rank 0
5766 23:09:54.130979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 23:09:54.131402 ==
5768 23:09:54.131785 DQS Delay:
5769 23:09:54.133747 DQS0 = 0, DQS1 = 0
5770 23:09:54.134167 DQM Delay:
5771 23:09:54.136677 DQM0 = 101, DQM1 = 91
5772 23:09:54.137102 DQ Delay:
5773 23:09:54.139711 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =95
5774 23:09:54.142850 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5775 23:09:54.146402 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5776 23:09:54.150136 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5777 23:09:54.150561
5778 23:09:54.150889
5779 23:09:54.151193 ==
5780 23:09:54.153865 Dram Type= 6, Freq= 0, CH_1, rank 0
5781 23:09:54.157648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 23:09:54.158101 ==
5783 23:09:54.159584
5784 23:09:54.160044
5785 23:09:54.160376 TX Vref Scan disable
5786 23:09:54.163584 == TX Byte 0 ==
5787 23:09:54.166650 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5788 23:09:54.169882 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5789 23:09:54.172972 == TX Byte 1 ==
5790 23:09:54.175989 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5791 23:09:54.179300 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5792 23:09:54.179924 ==
5793 23:09:54.182776 Dram Type= 6, Freq= 0, CH_1, rank 0
5794 23:09:54.189660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5795 23:09:54.190135 ==
5796 23:09:54.190494
5797 23:09:54.190806
5798 23:09:54.192673 TX Vref Scan disable
5799 23:09:54.193095 == TX Byte 0 ==
5800 23:09:54.199206 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5801 23:09:54.202379 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5802 23:09:54.202801 == TX Byte 1 ==
5803 23:09:54.208995 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5804 23:09:54.212949 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5805 23:09:54.213375
5806 23:09:54.213708 [DATLAT]
5807 23:09:54.216024 Freq=933, CH1 RK0
5808 23:09:54.216447
5809 23:09:54.216780 DATLAT Default: 0xd
5810 23:09:54.219199 0, 0xFFFF, sum = 0
5811 23:09:54.219826 1, 0xFFFF, sum = 0
5812 23:09:54.222738 2, 0xFFFF, sum = 0
5813 23:09:54.223267 3, 0xFFFF, sum = 0
5814 23:09:54.226077 4, 0xFFFF, sum = 0
5815 23:09:54.226765 5, 0xFFFF, sum = 0
5816 23:09:54.229412 6, 0xFFFF, sum = 0
5817 23:09:54.232785 7, 0xFFFF, sum = 0
5818 23:09:54.233320 8, 0xFFFF, sum = 0
5819 23:09:54.235758 9, 0xFFFF, sum = 0
5820 23:09:54.236297 10, 0x0, sum = 1
5821 23:09:54.236647 11, 0x0, sum = 2
5822 23:09:54.239418 12, 0x0, sum = 3
5823 23:09:54.240004 13, 0x0, sum = 4
5824 23:09:54.242269 best_step = 11
5825 23:09:54.242690
5826 23:09:54.243024 ==
5827 23:09:54.245380 Dram Type= 6, Freq= 0, CH_1, rank 0
5828 23:09:54.248800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 23:09:54.249227 ==
5830 23:09:54.252388 RX Vref Scan: 1
5831 23:09:54.252809
5832 23:09:54.253146 RX Vref 0 -> 0, step: 1
5833 23:09:54.255879
5834 23:09:54.256447 RX Delay -61 -> 252, step: 4
5835 23:09:54.256802
5836 23:09:54.258583 Set Vref, RX VrefLevel [Byte0]: 51
5837 23:09:54.262524 [Byte1]: 58
5838 23:09:54.266624
5839 23:09:54.267143 Final RX Vref Byte 0 = 51 to rank0
5840 23:09:54.269922 Final RX Vref Byte 1 = 58 to rank0
5841 23:09:54.273563 Final RX Vref Byte 0 = 51 to rank1
5842 23:09:54.276461 Final RX Vref Byte 1 = 58 to rank1==
5843 23:09:54.279955 Dram Type= 6, Freq= 0, CH_1, rank 0
5844 23:09:54.286838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5845 23:09:54.287449 ==
5846 23:09:54.287878 DQS Delay:
5847 23:09:54.288351 DQS0 = 0, DQS1 = 0
5848 23:09:54.289673 DQM Delay:
5849 23:09:54.290095 DQM0 = 101, DQM1 = 94
5850 23:09:54.293196 DQ Delay:
5851 23:09:54.296150 DQ0 =104, DQ1 =98, DQ2 =92, DQ3 =98
5852 23:09:54.299535 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =96
5853 23:09:54.303535 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =86
5854 23:09:54.305901 DQ12 =100, DQ13 =100, DQ14 =100, DQ15 =104
5855 23:09:54.306326
5856 23:09:54.306657
5857 23:09:54.312931 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5858 23:09:54.316154 CH1 RK0: MR19=505, MR18=1F0F
5859 23:09:54.322638 CH1_RK0: MR19=0x505, MR18=0x1F0F, DQSOSC=412, MR23=63, INC=63, DEC=42
5860 23:09:54.323206
5861 23:09:54.325820 ----->DramcWriteLeveling(PI) begin...
5862 23:09:54.326245 ==
5863 23:09:54.329050 Dram Type= 6, Freq= 0, CH_1, rank 1
5864 23:09:54.332125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5865 23:09:54.335659 ==
5866 23:09:54.336116 Write leveling (Byte 0): 27 => 27
5867 23:09:54.338811 Write leveling (Byte 1): 28 => 28
5868 23:09:54.342486 DramcWriteLeveling(PI) end<-----
5869 23:09:54.343014
5870 23:09:54.343345 ==
5871 23:09:54.345565 Dram Type= 6, Freq= 0, CH_1, rank 1
5872 23:09:54.352239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5873 23:09:54.352660 ==
5874 23:09:54.352988 [Gating] SW mode calibration
5875 23:09:54.362418 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5876 23:09:54.365985 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5877 23:09:54.372172 0 14 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5878 23:09:54.375092 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5879 23:09:54.379136 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5880 23:09:54.385453 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5881 23:09:54.388642 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5882 23:09:54.392045 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5883 23:09:54.398957 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5884 23:09:54.402024 0 14 28 | B1->B0 | 2e2e 3030 | 0 1 | (0 0) (1 0)
5885 23:09:54.404904 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5886 23:09:54.412154 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5887 23:09:54.415089 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5888 23:09:54.418533 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5889 23:09:54.421807 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5890 23:09:54.428374 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5891 23:09:54.431959 0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5892 23:09:54.438126 0 15 28 | B1->B0 | 3b3b 3838 | 0 1 | (0 0) (0 0)
5893 23:09:54.441642 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5894 23:09:54.444175 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5895 23:09:54.451596 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5896 23:09:54.454820 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5897 23:09:54.458534 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5898 23:09:54.465116 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5899 23:09:54.467711 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5900 23:09:54.471365 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5901 23:09:54.477333 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5902 23:09:54.481254 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5903 23:09:54.484668 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5904 23:09:54.490881 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5905 23:09:54.493822 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5906 23:09:54.497144 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5907 23:09:54.504244 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5908 23:09:54.507299 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5909 23:09:54.510775 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5910 23:09:54.516772 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5911 23:09:54.521068 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5912 23:09:54.523625 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5913 23:09:54.530823 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5914 23:09:54.534347 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5915 23:09:54.537522 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5916 23:09:54.544160 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5917 23:09:54.544622 Total UI for P1: 0, mck2ui 16
5918 23:09:54.547539 best dqsien dly found for B0: ( 1, 2, 26)
5919 23:09:54.550193 Total UI for P1: 0, mck2ui 16
5920 23:09:54.553665 best dqsien dly found for B1: ( 1, 2, 24)
5921 23:09:54.556943 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5922 23:09:54.563792 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5923 23:09:54.564361
5924 23:09:54.567068 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5925 23:09:54.570565 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5926 23:09:54.573257 [Gating] SW calibration Done
5927 23:09:54.573721 ==
5928 23:09:54.576491 Dram Type= 6, Freq= 0, CH_1, rank 1
5929 23:09:54.579740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5930 23:09:54.580221 ==
5931 23:09:54.583950 RX Vref Scan: 0
5932 23:09:54.584519
5933 23:09:54.584888 RX Vref 0 -> 0, step: 1
5934 23:09:54.585228
5935 23:09:54.586442 RX Delay -80 -> 252, step: 8
5936 23:09:54.590219 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5937 23:09:54.593180 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5938 23:09:54.599934 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5939 23:09:54.603096 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5940 23:09:54.606552 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5941 23:09:54.609452 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5942 23:09:54.613255 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5943 23:09:54.619360 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5944 23:09:54.623230 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5945 23:09:54.626312 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5946 23:09:54.629461 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5947 23:09:54.632509 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5948 23:09:54.639228 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5949 23:09:54.643410 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5950 23:09:54.646135 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5951 23:09:54.649019 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5952 23:09:54.649483 ==
5953 23:09:54.652581 Dram Type= 6, Freq= 0, CH_1, rank 1
5954 23:09:54.656400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5955 23:09:54.659164 ==
5956 23:09:54.659623 DQS Delay:
5957 23:09:54.660088 DQS0 = 0, DQS1 = 0
5958 23:09:54.662440 DQM Delay:
5959 23:09:54.662898 DQM0 = 100, DQM1 = 92
5960 23:09:54.665636 DQ Delay:
5961 23:09:54.669505 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =95
5962 23:09:54.672527 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =95
5963 23:09:54.675360 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =87
5964 23:09:54.679328 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =99
5965 23:09:54.679937
5966 23:09:54.680373
5967 23:09:54.680724 ==
5968 23:09:54.682043 Dram Type= 6, Freq= 0, CH_1, rank 1
5969 23:09:54.685495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5970 23:09:54.686069 ==
5971 23:09:54.686440
5972 23:09:54.686780
5973 23:09:54.688703 TX Vref Scan disable
5974 23:09:54.689164 == TX Byte 0 ==
5975 23:09:54.695988 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5976 23:09:54.699023 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5977 23:09:54.699586 == TX Byte 1 ==
5978 23:09:54.706102 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5979 23:09:54.708671 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5980 23:09:54.709275 ==
5981 23:09:54.712043 Dram Type= 6, Freq= 0, CH_1, rank 1
5982 23:09:54.715117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5983 23:09:54.715811 ==
5984 23:09:54.716206
5985 23:09:54.718776
5986 23:09:54.719233 TX Vref Scan disable
5987 23:09:54.722050 == TX Byte 0 ==
5988 23:09:54.725274 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5989 23:09:54.728588 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5990 23:09:54.731556 == TX Byte 1 ==
5991 23:09:54.734700 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5992 23:09:54.741292 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5993 23:09:54.741794
5994 23:09:54.742126 [DATLAT]
5995 23:09:54.742436 Freq=933, CH1 RK1
5996 23:09:54.742734
5997 23:09:54.745034 DATLAT Default: 0xb
5998 23:09:54.745483 0, 0xFFFF, sum = 0
5999 23:09:54.747645 1, 0xFFFF, sum = 0
6000 23:09:54.751142 2, 0xFFFF, sum = 0
6001 23:09:54.751565 3, 0xFFFF, sum = 0
6002 23:09:54.754493 4, 0xFFFF, sum = 0
6003 23:09:54.754914 5, 0xFFFF, sum = 0
6004 23:09:54.757941 6, 0xFFFF, sum = 0
6005 23:09:54.758365 7, 0xFFFF, sum = 0
6006 23:09:54.761095 8, 0xFFFF, sum = 0
6007 23:09:54.761520 9, 0xFFFF, sum = 0
6008 23:09:54.764652 10, 0x0, sum = 1
6009 23:09:54.765170 11, 0x0, sum = 2
6010 23:09:54.767966 12, 0x0, sum = 3
6011 23:09:54.768394 13, 0x0, sum = 4
6012 23:09:54.768733 best_step = 11
6013 23:09:54.770925
6014 23:09:54.771339 ==
6015 23:09:54.774790 Dram Type= 6, Freq= 0, CH_1, rank 1
6016 23:09:54.777494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6017 23:09:54.777912 ==
6018 23:09:54.778244 RX Vref Scan: 0
6019 23:09:54.778552
6020 23:09:54.781121 RX Vref 0 -> 0, step: 1
6021 23:09:54.781535
6022 23:09:54.784380 RX Delay -61 -> 252, step: 4
6023 23:09:54.791199 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
6024 23:09:54.794857 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
6025 23:09:54.797687 iDelay=207, Bit 2, Center 88 (-1 ~ 178) 180
6026 23:09:54.800893 iDelay=207, Bit 3, Center 100 (15 ~ 186) 172
6027 23:09:54.803757 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
6028 23:09:54.811189 iDelay=207, Bit 5, Center 110 (19 ~ 202) 184
6029 23:09:54.814471 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
6030 23:09:54.816993 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6031 23:09:54.820800 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
6032 23:09:54.824381 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6033 23:09:54.827134 iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188
6034 23:09:54.834361 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6035 23:09:54.837229 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6036 23:09:54.840310 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
6037 23:09:54.843712 iDelay=207, Bit 14, Center 102 (11 ~ 194) 184
6038 23:09:54.850436 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6039 23:09:54.851007 ==
6040 23:09:54.853779 Dram Type= 6, Freq= 0, CH_1, rank 1
6041 23:09:54.856723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6042 23:09:54.857193 ==
6043 23:09:54.857559 DQS Delay:
6044 23:09:54.859988 DQS0 = 0, DQS1 = 0
6045 23:09:54.860531 DQM Delay:
6046 23:09:54.864264 DQM0 = 101, DQM1 = 94
6047 23:09:54.864727 DQ Delay:
6048 23:09:54.866761 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =100
6049 23:09:54.870042 DQ4 =98, DQ5 =110, DQ6 =116, DQ7 =98
6050 23:09:54.873234 DQ8 =84, DQ9 =84, DQ10 =92, DQ11 =84
6051 23:09:54.876847 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =102
6052 23:09:54.877294
6053 23:09:54.877622
6054 23:09:54.886579 [DQSOSCAuto] RK1, (LSB)MR18= 0xc05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 418 ps
6055 23:09:54.887123 CH1 RK1: MR19=505, MR18=C05
6056 23:09:54.893630 CH1_RK1: MR19=0x505, MR18=0xC05, DQSOSC=418, MR23=63, INC=62, DEC=41
6057 23:09:54.896264 [RxdqsGatingPostProcess] freq 933
6058 23:09:54.902941 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6059 23:09:54.906284 best DQS0 dly(2T, 0.5T) = (0, 10)
6060 23:09:54.909778 best DQS1 dly(2T, 0.5T) = (0, 10)
6061 23:09:54.913014 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6062 23:09:54.915904 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6063 23:09:54.919197 best DQS0 dly(2T, 0.5T) = (0, 10)
6064 23:09:54.923257 best DQS1 dly(2T, 0.5T) = (0, 10)
6065 23:09:54.926099 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6066 23:09:54.929572 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6067 23:09:54.929993 Pre-setting of DQS Precalculation
6068 23:09:54.936202 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6069 23:09:54.942586 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6070 23:09:54.949221 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6071 23:09:54.949750
6072 23:09:54.950085
6073 23:09:54.952270 [Calibration Summary] 1866 Mbps
6074 23:09:54.955704 CH 0, Rank 0
6075 23:09:54.956131 SW Impedance : PASS
6076 23:09:54.958728 DUTY Scan : NO K
6077 23:09:54.961980 ZQ Calibration : PASS
6078 23:09:54.962402 Jitter Meter : NO K
6079 23:09:54.965984 CBT Training : PASS
6080 23:09:54.968547 Write leveling : PASS
6081 23:09:54.968969 RX DQS gating : PASS
6082 23:09:54.972536 RX DQ/DQS(RDDQC) : PASS
6083 23:09:54.975768 TX DQ/DQS : PASS
6084 23:09:54.976195 RX DATLAT : PASS
6085 23:09:54.979000 RX DQ/DQS(Engine): PASS
6086 23:09:54.979526 TX OE : NO K
6087 23:09:54.982126 All Pass.
6088 23:09:54.982549
6089 23:09:54.982882 CH 0, Rank 1
6090 23:09:54.984975 SW Impedance : PASS
6091 23:09:54.988841 DUTY Scan : NO K
6092 23:09:54.989281 ZQ Calibration : PASS
6093 23:09:54.991643 Jitter Meter : NO K
6094 23:09:54.992203 CBT Training : PASS
6095 23:09:54.995831 Write leveling : PASS
6096 23:09:54.998384 RX DQS gating : PASS
6097 23:09:54.998809 RX DQ/DQS(RDDQC) : PASS
6098 23:09:55.002216 TX DQ/DQS : PASS
6099 23:09:55.005162 RX DATLAT : PASS
6100 23:09:55.005582 RX DQ/DQS(Engine): PASS
6101 23:09:55.008271 TX OE : NO K
6102 23:09:55.008694 All Pass.
6103 23:09:55.009022
6104 23:09:55.011594 CH 1, Rank 0
6105 23:09:55.012056 SW Impedance : PASS
6106 23:09:55.014903 DUTY Scan : NO K
6107 23:09:55.018260 ZQ Calibration : PASS
6108 23:09:55.018677 Jitter Meter : NO K
6109 23:09:55.021895 CBT Training : PASS
6110 23:09:55.025048 Write leveling : PASS
6111 23:09:55.025638 RX DQS gating : PASS
6112 23:09:55.028540 RX DQ/DQS(RDDQC) : PASS
6113 23:09:55.031390 TX DQ/DQS : PASS
6114 23:09:55.031846 RX DATLAT : PASS
6115 23:09:55.034916 RX DQ/DQS(Engine): PASS
6116 23:09:55.039267 TX OE : NO K
6117 23:09:55.039827 All Pass.
6118 23:09:55.040170
6119 23:09:55.040475 CH 1, Rank 1
6120 23:09:55.041319 SW Impedance : PASS
6121 23:09:55.044686 DUTY Scan : NO K
6122 23:09:55.045229 ZQ Calibration : PASS
6123 23:09:55.048612 Jitter Meter : NO K
6124 23:09:55.049037 CBT Training : PASS
6125 23:09:55.051370 Write leveling : PASS
6126 23:09:55.055258 RX DQS gating : PASS
6127 23:09:55.055869 RX DQ/DQS(RDDQC) : PASS
6128 23:09:55.058819 TX DQ/DQS : PASS
6129 23:09:55.061255 RX DATLAT : PASS
6130 23:09:55.061724 RX DQ/DQS(Engine): PASS
6131 23:09:55.065055 TX OE : NO K
6132 23:09:55.065522 All Pass.
6133 23:09:55.065891
6134 23:09:55.068032 DramC Write-DBI off
6135 23:09:55.071494 PER_BANK_REFRESH: Hybrid Mode
6136 23:09:55.072062 TX_TRACKING: ON
6137 23:09:55.081109 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6138 23:09:55.084809 [FAST_K] Save calibration result to emmc
6139 23:09:55.088402 dramc_set_vcore_voltage set vcore to 650000
6140 23:09:55.091494 Read voltage for 400, 6
6141 23:09:55.092086 Vio18 = 0
6142 23:09:55.094596 Vcore = 650000
6143 23:09:55.095163 Vdram = 0
6144 23:09:55.095537 Vddq = 0
6145 23:09:55.095931 Vmddr = 0
6146 23:09:55.101997 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6147 23:09:55.107791 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6148 23:09:55.108394 MEM_TYPE=3, freq_sel=20
6149 23:09:55.111187 sv_algorithm_assistance_LP4_800
6150 23:09:55.114047 ============ PULL DRAM RESETB DOWN ============
6151 23:09:55.120667 ========== PULL DRAM RESETB DOWN end =========
6152 23:09:55.124223 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6153 23:09:55.127263 ===================================
6154 23:09:55.130839 LPDDR4 DRAM CONFIGURATION
6155 23:09:55.134131 ===================================
6156 23:09:55.134704 EX_ROW_EN[0] = 0x0
6157 23:09:55.137267 EX_ROW_EN[1] = 0x0
6158 23:09:55.137851 LP4Y_EN = 0x0
6159 23:09:55.140623 WORK_FSP = 0x0
6160 23:09:55.143656 WL = 0x2
6161 23:09:55.144182 RL = 0x2
6162 23:09:55.146730 BL = 0x2
6163 23:09:55.147189 RPST = 0x0
6164 23:09:55.150327 RD_PRE = 0x0
6165 23:09:55.150789 WR_PRE = 0x1
6166 23:09:55.154461 WR_PST = 0x0
6167 23:09:55.155074 DBI_WR = 0x0
6168 23:09:55.157486 DBI_RD = 0x0
6169 23:09:55.158056 OTF = 0x1
6170 23:09:55.160240 ===================================
6171 23:09:55.163424 ===================================
6172 23:09:55.167709 ANA top config
6173 23:09:55.170245 ===================================
6174 23:09:55.170811 DLL_ASYNC_EN = 0
6175 23:09:55.174014 ALL_SLAVE_EN = 1
6176 23:09:55.176664 NEW_RANK_MODE = 1
6177 23:09:55.180110 DLL_IDLE_MODE = 1
6178 23:09:55.183722 LP45_APHY_COMB_EN = 1
6179 23:09:55.184295 TX_ODT_DIS = 1
6180 23:09:55.186950 NEW_8X_MODE = 1
6181 23:09:55.189617 ===================================
6182 23:09:55.193424 ===================================
6183 23:09:55.196458 data_rate = 800
6184 23:09:55.200138 CKR = 1
6185 23:09:55.203652 DQ_P2S_RATIO = 4
6186 23:09:55.206083 ===================================
6187 23:09:55.209510 CA_P2S_RATIO = 4
6188 23:09:55.209989 DQ_CA_OPEN = 0
6189 23:09:55.212618 DQ_SEMI_OPEN = 1
6190 23:09:55.216396 CA_SEMI_OPEN = 1
6191 23:09:55.219933 CA_FULL_RATE = 0
6192 23:09:55.223319 DQ_CKDIV4_EN = 0
6193 23:09:55.226196 CA_CKDIV4_EN = 1
6194 23:09:55.226622 CA_PREDIV_EN = 0
6195 23:09:55.229021 PH8_DLY = 0
6196 23:09:55.232587 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6197 23:09:55.235618 DQ_AAMCK_DIV = 0
6198 23:09:55.239613 CA_AAMCK_DIV = 0
6199 23:09:55.242307 CA_ADMCK_DIV = 4
6200 23:09:55.242724 DQ_TRACK_CA_EN = 0
6201 23:09:55.246363 CA_PICK = 800
6202 23:09:55.249309 CA_MCKIO = 400
6203 23:09:55.252774 MCKIO_SEMI = 400
6204 23:09:55.255944 PLL_FREQ = 3016
6205 23:09:55.259381 DQ_UI_PI_RATIO = 32
6206 23:09:55.262136 CA_UI_PI_RATIO = 32
6207 23:09:55.265521 ===================================
6208 23:09:55.269073 ===================================
6209 23:09:55.269492 memory_type:LPDDR4
6210 23:09:55.272544 GP_NUM : 10
6211 23:09:55.275840 SRAM_EN : 1
6212 23:09:55.276267 MD32_EN : 0
6213 23:09:55.278733 ===================================
6214 23:09:55.281949 [ANA_INIT] >>>>>>>>>>>>>>
6215 23:09:55.285043 <<<<<< [CONFIGURE PHASE]: ANA_TX
6216 23:09:55.288942 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6217 23:09:55.292088 ===================================
6218 23:09:55.295171 data_rate = 800,PCW = 0X7400
6219 23:09:55.298525 ===================================
6220 23:09:55.301986 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6221 23:09:55.305657 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6222 23:09:55.318452 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6223 23:09:55.321482 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6224 23:09:55.324950 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6225 23:09:55.328297 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6226 23:09:55.332356 [ANA_INIT] flow start
6227 23:09:55.335806 [ANA_INIT] PLL >>>>>>>>
6228 23:09:55.336327 [ANA_INIT] PLL <<<<<<<<
6229 23:09:55.339020 [ANA_INIT] MIDPI >>>>>>>>
6230 23:09:55.341681 [ANA_INIT] MIDPI <<<<<<<<
6231 23:09:55.342148 [ANA_INIT] DLL >>>>>>>>
6232 23:09:55.345010 [ANA_INIT] flow end
6233 23:09:55.348558 ============ LP4 DIFF to SE enter ============
6234 23:09:55.355012 ============ LP4 DIFF to SE exit ============
6235 23:09:55.355594 [ANA_INIT] <<<<<<<<<<<<<
6236 23:09:55.359164 [Flow] Enable top DCM control >>>>>
6237 23:09:55.361263 [Flow] Enable top DCM control <<<<<
6238 23:09:55.364378 Enable DLL master slave shuffle
6239 23:09:55.371753 ==============================================================
6240 23:09:55.372317 Gating Mode config
6241 23:09:55.378055 ==============================================================
6242 23:09:55.381139 Config description:
6243 23:09:55.391209 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6244 23:09:55.397943 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6245 23:09:55.400690 SELPH_MODE 0: By rank 1: By Phase
6246 23:09:55.407644 ==============================================================
6247 23:09:55.410802 GAT_TRACK_EN = 0
6248 23:09:55.413728 RX_GATING_MODE = 2
6249 23:09:55.414194 RX_GATING_TRACK_MODE = 2
6250 23:09:55.417613 SELPH_MODE = 1
6251 23:09:55.420547 PICG_EARLY_EN = 1
6252 23:09:55.424008 VALID_LAT_VALUE = 1
6253 23:09:55.430965 ==============================================================
6254 23:09:55.434499 Enter into Gating configuration >>>>
6255 23:09:55.437381 Exit from Gating configuration <<<<
6256 23:09:55.440729 Enter into DVFS_PRE_config >>>>>
6257 23:09:55.450584 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6258 23:09:55.453653 Exit from DVFS_PRE_config <<<<<
6259 23:09:55.456987 Enter into PICG configuration >>>>
6260 23:09:55.460430 Exit from PICG configuration <<<<
6261 23:09:55.463920 [RX_INPUT] configuration >>>>>
6262 23:09:55.467522 [RX_INPUT] configuration <<<<<
6263 23:09:55.470300 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6264 23:09:55.477074 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6265 23:09:55.483338 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6266 23:09:55.489895 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6267 23:09:55.497128 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6268 23:09:55.500351 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6269 23:09:55.506911 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6270 23:09:55.509590 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6271 23:09:55.512879 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6272 23:09:55.516570 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6273 23:09:55.520437 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6274 23:09:55.526970 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6275 23:09:55.529420 ===================================
6276 23:09:55.533357 LPDDR4 DRAM CONFIGURATION
6277 23:09:55.536225 ===================================
6278 23:09:55.536694 EX_ROW_EN[0] = 0x0
6279 23:09:55.539761 EX_ROW_EN[1] = 0x0
6280 23:09:55.540364 LP4Y_EN = 0x0
6281 23:09:55.543063 WORK_FSP = 0x0
6282 23:09:55.543648 WL = 0x2
6283 23:09:55.546754 RL = 0x2
6284 23:09:55.547336 BL = 0x2
6285 23:09:55.549499 RPST = 0x0
6286 23:09:55.549965 RD_PRE = 0x0
6287 23:09:55.552670 WR_PRE = 0x1
6288 23:09:55.553138 WR_PST = 0x0
6289 23:09:55.556442 DBI_WR = 0x0
6290 23:09:55.559718 DBI_RD = 0x0
6291 23:09:55.560294 OTF = 0x1
6292 23:09:55.563006 ===================================
6293 23:09:55.566377 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6294 23:09:55.569489 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6295 23:09:55.575908 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6296 23:09:55.579583 ===================================
6297 23:09:55.582730 LPDDR4 DRAM CONFIGURATION
6298 23:09:55.586335 ===================================
6299 23:09:55.586892 EX_ROW_EN[0] = 0x10
6300 23:09:55.588733 EX_ROW_EN[1] = 0x0
6301 23:09:55.589193 LP4Y_EN = 0x0
6302 23:09:55.592775 WORK_FSP = 0x0
6303 23:09:55.593235 WL = 0x2
6304 23:09:55.595534 RL = 0x2
6305 23:09:55.596208 BL = 0x2
6306 23:09:55.599149 RPST = 0x0
6307 23:09:55.599752 RD_PRE = 0x0
6308 23:09:55.602104 WR_PRE = 0x1
6309 23:09:55.605578 WR_PST = 0x0
6310 23:09:55.606135 DBI_WR = 0x0
6311 23:09:55.609019 DBI_RD = 0x0
6312 23:09:55.609480 OTF = 0x1
6313 23:09:55.612203 ===================================
6314 23:09:55.618457 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6315 23:09:55.622298 nWR fixed to 30
6316 23:09:55.625936 [ModeRegInit_LP4] CH0 RK0
6317 23:09:55.626497 [ModeRegInit_LP4] CH0 RK1
6318 23:09:55.629988 [ModeRegInit_LP4] CH1 RK0
6319 23:09:55.632426 [ModeRegInit_LP4] CH1 RK1
6320 23:09:55.632888 match AC timing 19
6321 23:09:55.638860 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6322 23:09:55.642266 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6323 23:09:55.645983 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6324 23:09:55.652140 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6325 23:09:55.655526 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6326 23:09:55.656136 ==
6327 23:09:55.659136 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 23:09:55.662183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 23:09:55.662646 ==
6330 23:09:55.668474 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6331 23:09:55.675301 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6332 23:09:55.678303 [CA 0] Center 36 (8~64) winsize 57
6333 23:09:55.681393 [CA 1] Center 36 (8~64) winsize 57
6334 23:09:55.685050 [CA 2] Center 36 (8~64) winsize 57
6335 23:09:55.688382 [CA 3] Center 36 (8~64) winsize 57
6336 23:09:55.692074 [CA 4] Center 36 (8~64) winsize 57
6337 23:09:55.695257 [CA 5] Center 36 (8~64) winsize 57
6338 23:09:55.695859
6339 23:09:55.698584 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6340 23:09:55.699137
6341 23:09:55.701262 [CATrainingPosCal] consider 1 rank data
6342 23:09:55.704424 u2DelayCellTimex100 = 270/100 ps
6343 23:09:55.708001 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6344 23:09:55.710966 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6345 23:09:55.714303 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6346 23:09:55.717876 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6347 23:09:55.721083 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6348 23:09:55.724224 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6349 23:09:55.724933
6350 23:09:55.730840 CA PerBit enable=1, Macro0, CA PI delay=36
6351 23:09:55.731408
6352 23:09:55.734138 [CBTSetCACLKResult] CA Dly = 36
6353 23:09:55.734702 CS Dly: 1 (0~32)
6354 23:09:55.735074 ==
6355 23:09:55.737577 Dram Type= 6, Freq= 0, CH_0, rank 1
6356 23:09:55.741340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 23:09:55.741909 ==
6358 23:09:55.747816 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6359 23:09:55.754216 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6360 23:09:55.757108 [CA 0] Center 36 (8~64) winsize 57
6361 23:09:55.760651 [CA 1] Center 36 (8~64) winsize 57
6362 23:09:55.764250 [CA 2] Center 36 (8~64) winsize 57
6363 23:09:55.767424 [CA 3] Center 36 (8~64) winsize 57
6364 23:09:55.770967 [CA 4] Center 36 (8~64) winsize 57
6365 23:09:55.771388 [CA 5] Center 36 (8~64) winsize 57
6366 23:09:55.771764
6367 23:09:55.777498 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6368 23:09:55.778023
6369 23:09:55.781231 [CATrainingPosCal] consider 2 rank data
6370 23:09:55.783778 u2DelayCellTimex100 = 270/100 ps
6371 23:09:55.787542 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6372 23:09:55.790351 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6373 23:09:55.793395 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6374 23:09:55.796956 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6375 23:09:55.800656 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6376 23:09:55.803606 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6377 23:09:55.804067
6378 23:09:55.807256 CA PerBit enable=1, Macro0, CA PI delay=36
6379 23:09:55.807842
6380 23:09:55.810320 [CBTSetCACLKResult] CA Dly = 36
6381 23:09:55.813907 CS Dly: 1 (0~32)
6382 23:09:55.814379
6383 23:09:55.816926 ----->DramcWriteLeveling(PI) begin...
6384 23:09:55.817609 ==
6385 23:09:55.820404 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 23:09:55.823729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 23:09:55.824285 ==
6388 23:09:55.826683 Write leveling (Byte 0): 40 => 8
6389 23:09:55.830436 Write leveling (Byte 1): 32 => 0
6390 23:09:55.833483 DramcWriteLeveling(PI) end<-----
6391 23:09:55.834031
6392 23:09:55.834388 ==
6393 23:09:55.836921 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 23:09:55.840195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 23:09:55.840655 ==
6396 23:09:55.843247 [Gating] SW mode calibration
6397 23:09:55.850306 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6398 23:09:55.857070 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6399 23:09:55.860323 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6400 23:09:55.866522 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6401 23:09:55.870357 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6402 23:09:55.873636 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6403 23:09:55.879885 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6404 23:09:55.883121 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6405 23:09:55.886324 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6406 23:09:55.892943 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6407 23:09:55.895997 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6408 23:09:55.899378 Total UI for P1: 0, mck2ui 16
6409 23:09:55.902574 best dqsien dly found for B0: ( 0, 14, 24)
6410 23:09:55.906309 Total UI for P1: 0, mck2ui 16
6411 23:09:55.909178 best dqsien dly found for B1: ( 0, 14, 24)
6412 23:09:55.912778 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6413 23:09:55.916310 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6414 23:09:55.916943
6415 23:09:55.919184 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6416 23:09:55.922527 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6417 23:09:55.926080 [Gating] SW calibration Done
6418 23:09:55.926638 ==
6419 23:09:55.929335 Dram Type= 6, Freq= 0, CH_0, rank 0
6420 23:09:55.932532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 23:09:55.935820 ==
6422 23:09:55.936371 RX Vref Scan: 0
6423 23:09:55.936736
6424 23:09:55.939337 RX Vref 0 -> 0, step: 1
6425 23:09:55.939944
6426 23:09:55.942663 RX Delay -410 -> 252, step: 16
6427 23:09:55.945756 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6428 23:09:55.949293 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6429 23:09:55.952391 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6430 23:09:55.958941 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6431 23:09:55.961925 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6432 23:09:55.965140 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6433 23:09:55.969239 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6434 23:09:55.975697 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6435 23:09:55.978596 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6436 23:09:55.981869 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6437 23:09:55.989160 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6438 23:09:55.991566 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6439 23:09:55.995050 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6440 23:09:55.998370 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6441 23:09:56.005197 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6442 23:09:56.008117 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6443 23:09:56.008751 ==
6444 23:09:56.011934 Dram Type= 6, Freq= 0, CH_0, rank 0
6445 23:09:56.014699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 23:09:56.015320 ==
6447 23:09:56.017720 DQS Delay:
6448 23:09:56.018204 DQS0 = 43, DQS1 = 59
6449 23:09:56.021271 DQM Delay:
6450 23:09:56.021730 DQM0 = 10, DQM1 = 12
6451 23:09:56.022096 DQ Delay:
6452 23:09:56.025124 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6453 23:09:56.029164 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6454 23:09:56.031467 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6455 23:09:56.034844 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6456 23:09:56.035307
6457 23:09:56.035668
6458 23:09:56.036070 ==
6459 23:09:56.037692 Dram Type= 6, Freq= 0, CH_0, rank 0
6460 23:09:56.044218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 23:09:56.044774 ==
6462 23:09:56.045147
6463 23:09:56.045490
6464 23:09:56.045816 TX Vref Scan disable
6465 23:09:56.048073 == TX Byte 0 ==
6466 23:09:56.051588 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6467 23:09:56.054775 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6468 23:09:56.057749 == TX Byte 1 ==
6469 23:09:56.061699 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6470 23:09:56.064472 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6471 23:09:56.067640 ==
6472 23:09:56.068241 Dram Type= 6, Freq= 0, CH_0, rank 0
6473 23:09:56.074069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 23:09:56.074694 ==
6475 23:09:56.075068
6476 23:09:56.075411
6477 23:09:56.078059 TX Vref Scan disable
6478 23:09:56.078627 == TX Byte 0 ==
6479 23:09:56.080615 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6480 23:09:56.087342 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6481 23:09:56.087957 == TX Byte 1 ==
6482 23:09:56.090659 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6483 23:09:56.098068 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6484 23:09:56.098536
6485 23:09:56.098904 [DATLAT]
6486 23:09:56.099245 Freq=400, CH0 RK0
6487 23:09:56.099575
6488 23:09:56.100638 DATLAT Default: 0xf
6489 23:09:56.101104 0, 0xFFFF, sum = 0
6490 23:09:56.103826 1, 0xFFFF, sum = 0
6491 23:09:56.108280 2, 0xFFFF, sum = 0
6492 23:09:56.108852 3, 0xFFFF, sum = 0
6493 23:09:56.110265 4, 0xFFFF, sum = 0
6494 23:09:56.110737 5, 0xFFFF, sum = 0
6495 23:09:56.114009 6, 0xFFFF, sum = 0
6496 23:09:56.114672 7, 0xFFFF, sum = 0
6497 23:09:56.116841 8, 0xFFFF, sum = 0
6498 23:09:56.117315 9, 0xFFFF, sum = 0
6499 23:09:56.120364 10, 0xFFFF, sum = 0
6500 23:09:56.120837 11, 0xFFFF, sum = 0
6501 23:09:56.123587 12, 0xFFFF, sum = 0
6502 23:09:56.124172 13, 0x0, sum = 1
6503 23:09:56.126922 14, 0x0, sum = 2
6504 23:09:56.127465 15, 0x0, sum = 3
6505 23:09:56.130825 16, 0x0, sum = 4
6506 23:09:56.131293 best_step = 14
6507 23:09:56.131625
6508 23:09:56.131995 ==
6509 23:09:56.135107 Dram Type= 6, Freq= 0, CH_0, rank 0
6510 23:09:56.137519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 23:09:56.140811 ==
6512 23:09:56.141377 RX Vref Scan: 1
6513 23:09:56.141748
6514 23:09:56.143379 RX Vref 0 -> 0, step: 1
6515 23:09:56.143897
6516 23:09:56.147086 RX Delay -359 -> 252, step: 8
6517 23:09:56.147664
6518 23:09:56.150328 Set Vref, RX VrefLevel [Byte0]: 61
6519 23:09:56.153417 [Byte1]: 48
6520 23:09:56.153881
6521 23:09:56.156935 Final RX Vref Byte 0 = 61 to rank0
6522 23:09:56.160626 Final RX Vref Byte 1 = 48 to rank0
6523 23:09:56.163557 Final RX Vref Byte 0 = 61 to rank1
6524 23:09:56.167197 Final RX Vref Byte 1 = 48 to rank1==
6525 23:09:56.170751 Dram Type= 6, Freq= 0, CH_0, rank 0
6526 23:09:56.173802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 23:09:56.176598 ==
6528 23:09:56.177164 DQS Delay:
6529 23:09:56.177534 DQS0 = 48, DQS1 = 60
6530 23:09:56.180351 DQM Delay:
6531 23:09:56.180816 DQM0 = 11, DQM1 = 12
6532 23:09:56.183241 DQ Delay:
6533 23:09:56.183877 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6534 23:09:56.187150 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6535 23:09:56.189473 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6536 23:09:56.192976 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6537 23:09:56.193442
6538 23:09:56.193879
6539 23:09:56.203605 [DQSOSCAuto] RK0, (LSB)MR18= 0xb87a, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 386 ps
6540 23:09:56.206622 CH0 RK0: MR19=C0C, MR18=B87A
6541 23:09:56.213170 CH0_RK0: MR19=0xC0C, MR18=0xB87A, DQSOSC=386, MR23=63, INC=396, DEC=264
6542 23:09:56.213728 ==
6543 23:09:56.216224 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 23:09:56.219540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 23:09:56.220080 ==
6546 23:09:56.223234 [Gating] SW mode calibration
6547 23:09:56.229285 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6548 23:09:56.236000 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6549 23:09:56.239466 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6550 23:09:56.242954 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6551 23:09:56.248937 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6552 23:09:56.252303 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6553 23:09:56.255727 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6554 23:09:56.262238 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6555 23:09:56.266076 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6556 23:09:56.268973 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6557 23:09:56.276075 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6558 23:09:56.276644 Total UI for P1: 0, mck2ui 16
6559 23:09:56.279039 best dqsien dly found for B0: ( 0, 14, 24)
6560 23:09:56.283312 Total UI for P1: 0, mck2ui 16
6561 23:09:56.285560 best dqsien dly found for B1: ( 0, 14, 24)
6562 23:09:56.292157 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6563 23:09:56.295338 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6564 23:09:56.295945
6565 23:09:56.299366 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6566 23:09:56.302771 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6567 23:09:56.305040 [Gating] SW calibration Done
6568 23:09:56.305609 ==
6569 23:09:56.308447 Dram Type= 6, Freq= 0, CH_0, rank 1
6570 23:09:56.311811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 23:09:56.312287 ==
6572 23:09:56.315079 RX Vref Scan: 0
6573 23:09:56.315549
6574 23:09:56.315986 RX Vref 0 -> 0, step: 1
6575 23:09:56.316333
6576 23:09:56.318818 RX Delay -410 -> 252, step: 16
6577 23:09:56.325331 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6578 23:09:56.328848 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6579 23:09:56.331452 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6580 23:09:56.335122 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6581 23:09:56.341480 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6582 23:09:56.345131 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6583 23:09:56.348151 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6584 23:09:56.351170 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6585 23:09:56.358195 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6586 23:09:56.361243 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6587 23:09:56.364636 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6588 23:09:56.367640 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6589 23:09:56.374533 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6590 23:09:56.377776 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6591 23:09:56.381073 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6592 23:09:56.387851 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6593 23:09:56.388394 ==
6594 23:09:56.391058 Dram Type= 6, Freq= 0, CH_0, rank 1
6595 23:09:56.394430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6596 23:09:56.394980 ==
6597 23:09:56.395326 DQS Delay:
6598 23:09:56.397948 DQS0 = 35, DQS1 = 59
6599 23:09:56.398364 DQM Delay:
6600 23:09:56.400646 DQM0 = 3, DQM1 = 17
6601 23:09:56.401140 DQ Delay:
6602 23:09:56.404233 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6603 23:09:56.407762 DQ4 =0, DQ5 =0, DQ6 =8, DQ7 =8
6604 23:09:56.411276 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6605 23:09:56.414436 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6606 23:09:56.414848
6607 23:09:56.415176
6608 23:09:56.415486 ==
6609 23:09:56.417329 Dram Type= 6, Freq= 0, CH_0, rank 1
6610 23:09:56.420384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 23:09:56.420837 ==
6612 23:09:56.421173
6613 23:09:56.421540
6614 23:09:56.424475 TX Vref Scan disable
6615 23:09:56.424899 == TX Byte 0 ==
6616 23:09:56.430250 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6617 23:09:56.434393 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6618 23:09:56.434921 == TX Byte 1 ==
6619 23:09:56.440580 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6620 23:09:56.444073 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6621 23:09:56.444613 ==
6622 23:09:56.447470 Dram Type= 6, Freq= 0, CH_0, rank 1
6623 23:09:56.450559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6624 23:09:56.451140 ==
6625 23:09:56.451602
6626 23:09:56.452014
6627 23:09:56.453824 TX Vref Scan disable
6628 23:09:56.454288 == TX Byte 0 ==
6629 23:09:56.460479 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6630 23:09:56.463713 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6631 23:09:56.464218 == TX Byte 1 ==
6632 23:09:56.470824 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6633 23:09:56.473388 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6634 23:09:56.473955
6635 23:09:56.474325 [DATLAT]
6636 23:09:56.476597 Freq=400, CH0 RK1
6637 23:09:56.477062
6638 23:09:56.477435 DATLAT Default: 0xe
6639 23:09:56.480240 0, 0xFFFF, sum = 0
6640 23:09:56.480713 1, 0xFFFF, sum = 0
6641 23:09:56.483863 2, 0xFFFF, sum = 0
6642 23:09:56.484473 3, 0xFFFF, sum = 0
6643 23:09:56.486536 4, 0xFFFF, sum = 0
6644 23:09:56.490110 5, 0xFFFF, sum = 0
6645 23:09:56.490685 6, 0xFFFF, sum = 0
6646 23:09:56.493243 7, 0xFFFF, sum = 0
6647 23:09:56.493763 8, 0xFFFF, sum = 0
6648 23:09:56.496619 9, 0xFFFF, sum = 0
6649 23:09:56.497110 10, 0xFFFF, sum = 0
6650 23:09:56.500314 11, 0xFFFF, sum = 0
6651 23:09:56.500885 12, 0xFFFF, sum = 0
6652 23:09:56.503518 13, 0x0, sum = 1
6653 23:09:56.504124 14, 0x0, sum = 2
6654 23:09:56.506122 15, 0x0, sum = 3
6655 23:09:56.506593 16, 0x0, sum = 4
6656 23:09:56.509488 best_step = 14
6657 23:09:56.509954
6658 23:09:56.510323 ==
6659 23:09:56.513031 Dram Type= 6, Freq= 0, CH_0, rank 1
6660 23:09:56.516164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 23:09:56.516758 ==
6662 23:09:56.517137 RX Vref Scan: 0
6663 23:09:56.519435
6664 23:09:56.519938 RX Vref 0 -> 0, step: 1
6665 23:09:56.520309
6666 23:09:56.522832 RX Delay -359 -> 252, step: 8
6667 23:09:56.530964 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6668 23:09:56.533726 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6669 23:09:56.536623 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6670 23:09:56.543573 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6671 23:09:56.546948 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6672 23:09:56.550010 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6673 23:09:56.553456 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6674 23:09:56.560133 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6675 23:09:56.562845 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6676 23:09:56.566665 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6677 23:09:56.570226 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6678 23:09:56.576558 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6679 23:09:56.579468 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6680 23:09:56.582984 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6681 23:09:56.589422 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6682 23:09:56.593549 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6683 23:09:56.594038 ==
6684 23:09:56.596196 Dram Type= 6, Freq= 0, CH_0, rank 1
6685 23:09:56.599290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 23:09:56.599884 ==
6687 23:09:56.602927 DQS Delay:
6688 23:09:56.603489 DQS0 = 44, DQS1 = 60
6689 23:09:56.603893 DQM Delay:
6690 23:09:56.605881 DQM0 = 7, DQM1 = 14
6691 23:09:56.606446 DQ Delay:
6692 23:09:56.608936 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6693 23:09:56.612536 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6694 23:09:56.616291 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6695 23:09:56.619149 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =20
6696 23:09:56.619608
6697 23:09:56.620029
6698 23:09:56.629068 [DQSOSCAuto] RK1, (LSB)MR18= 0xb945, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6699 23:09:56.629646 CH0 RK1: MR19=C0C, MR18=B945
6700 23:09:56.635414 CH0_RK1: MR19=0xC0C, MR18=0xB945, DQSOSC=386, MR23=63, INC=396, DEC=264
6701 23:09:56.639357 [RxdqsGatingPostProcess] freq 400
6702 23:09:56.645936 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6703 23:09:56.648643 best DQS0 dly(2T, 0.5T) = (0, 10)
6704 23:09:56.652390 best DQS1 dly(2T, 0.5T) = (0, 10)
6705 23:09:56.655613 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6706 23:09:56.658841 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6707 23:09:56.662564 best DQS0 dly(2T, 0.5T) = (0, 10)
6708 23:09:56.663125 best DQS1 dly(2T, 0.5T) = (0, 10)
6709 23:09:56.665428 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6710 23:09:56.668326 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6711 23:09:56.671771 Pre-setting of DQS Precalculation
6712 23:09:56.678655 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6713 23:09:56.679121 ==
6714 23:09:56.682027 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 23:09:56.685407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 23:09:56.685933 ==
6717 23:09:56.692758 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6718 23:09:56.698369 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6719 23:09:56.702038 [CA 0] Center 36 (8~64) winsize 57
6720 23:09:56.705296 [CA 1] Center 36 (8~64) winsize 57
6721 23:09:56.708457 [CA 2] Center 36 (8~64) winsize 57
6722 23:09:56.708881 [CA 3] Center 36 (8~64) winsize 57
6723 23:09:56.711930 [CA 4] Center 36 (8~64) winsize 57
6724 23:09:56.714832 [CA 5] Center 36 (8~64) winsize 57
6725 23:09:56.715372
6726 23:09:56.721220 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6727 23:09:56.721642
6728 23:09:56.724494 [CATrainingPosCal] consider 1 rank data
6729 23:09:56.728562 u2DelayCellTimex100 = 270/100 ps
6730 23:09:56.731397 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6731 23:09:56.734839 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6732 23:09:56.738065 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6733 23:09:56.740919 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6734 23:09:56.744951 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6735 23:09:56.747937 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6736 23:09:56.748461
6737 23:09:56.751108 CA PerBit enable=1, Macro0, CA PI delay=36
6738 23:09:56.751529
6739 23:09:56.754763 [CBTSetCACLKResult] CA Dly = 36
6740 23:09:56.758466 CS Dly: 1 (0~32)
6741 23:09:56.758989 ==
6742 23:09:56.761375 Dram Type= 6, Freq= 0, CH_1, rank 1
6743 23:09:56.764150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 23:09:56.764664 ==
6745 23:09:56.771136 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6746 23:09:56.777474 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6747 23:09:56.781131 [CA 0] Center 36 (8~64) winsize 57
6748 23:09:56.781660 [CA 1] Center 36 (8~64) winsize 57
6749 23:09:56.784225 [CA 2] Center 36 (8~64) winsize 57
6750 23:09:56.787374 [CA 3] Center 36 (8~64) winsize 57
6751 23:09:56.790822 [CA 4] Center 36 (8~64) winsize 57
6752 23:09:56.793764 [CA 5] Center 36 (8~64) winsize 57
6753 23:09:56.794264
6754 23:09:56.797391 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6755 23:09:56.797916
6756 23:09:56.804004 [CATrainingPosCal] consider 2 rank data
6757 23:09:56.804533 u2DelayCellTimex100 = 270/100 ps
6758 23:09:56.807566 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6759 23:09:56.813626 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6760 23:09:56.817669 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6761 23:09:56.820223 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6762 23:09:56.823900 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6763 23:09:56.827018 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6764 23:09:56.827556
6765 23:09:56.831040 CA PerBit enable=1, Macro0, CA PI delay=36
6766 23:09:56.831562
6767 23:09:56.833946 [CBTSetCACLKResult] CA Dly = 36
6768 23:09:56.837371 CS Dly: 1 (0~32)
6769 23:09:56.837897
6770 23:09:56.840569 ----->DramcWriteLeveling(PI) begin...
6771 23:09:56.841014 ==
6772 23:09:56.843842 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 23:09:56.847136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 23:09:56.847714 ==
6775 23:09:56.850290 Write leveling (Byte 0): 40 => 8
6776 23:09:56.853005 Write leveling (Byte 1): 40 => 8
6777 23:09:56.857228 DramcWriteLeveling(PI) end<-----
6778 23:09:56.857754
6779 23:09:56.858086 ==
6780 23:09:56.860210 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 23:09:56.863295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 23:09:56.863879 ==
6783 23:09:56.867276 [Gating] SW mode calibration
6784 23:09:56.873109 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6785 23:09:56.880365 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6786 23:09:56.883341 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6787 23:09:56.886701 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6788 23:09:56.893101 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6789 23:09:56.896116 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6790 23:09:56.899466 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6791 23:09:56.906813 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6792 23:09:56.909389 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6793 23:09:56.912590 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6794 23:09:56.918805 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6795 23:09:56.923415 Total UI for P1: 0, mck2ui 16
6796 23:09:56.925679 best dqsien dly found for B0: ( 0, 14, 24)
6797 23:09:56.928941 Total UI for P1: 0, mck2ui 16
6798 23:09:56.932776 best dqsien dly found for B1: ( 0, 14, 24)
6799 23:09:56.936956 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6800 23:09:56.939624 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6801 23:09:56.940209
6802 23:09:56.942976 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6803 23:09:56.945727 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6804 23:09:56.949178 [Gating] SW calibration Done
6805 23:09:56.949715 ==
6806 23:09:56.952595 Dram Type= 6, Freq= 0, CH_1, rank 0
6807 23:09:56.955200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 23:09:56.958927 ==
6809 23:09:56.959457 RX Vref Scan: 0
6810 23:09:56.959856
6811 23:09:56.962421 RX Vref 0 -> 0, step: 1
6812 23:09:56.962948
6813 23:09:56.964976 RX Delay -410 -> 252, step: 16
6814 23:09:56.968543 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6815 23:09:56.972006 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6816 23:09:56.975379 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6817 23:09:56.981487 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6818 23:09:56.985484 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6819 23:09:56.988645 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6820 23:09:56.992011 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6821 23:09:56.998249 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6822 23:09:57.001724 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6823 23:09:57.004742 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6824 23:09:57.007813 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6825 23:09:57.015006 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6826 23:09:57.017605 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6827 23:09:57.021236 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6828 23:09:57.028015 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6829 23:09:57.030955 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6830 23:09:57.031380 ==
6831 23:09:57.034220 Dram Type= 6, Freq= 0, CH_1, rank 0
6832 23:09:57.037829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 23:09:57.038357 ==
6834 23:09:57.040602 DQS Delay:
6835 23:09:57.041040 DQS0 = 43, DQS1 = 51
6836 23:09:57.044244 DQM Delay:
6837 23:09:57.044682 DQM0 = 12, DQM1 = 14
6838 23:09:57.045201 DQ Delay:
6839 23:09:57.048143 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6840 23:09:57.050871 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6841 23:09:57.054818 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6842 23:09:57.059750 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6843 23:09:57.060274
6844 23:09:57.060614
6845 23:09:57.060925 ==
6846 23:09:57.061564 Dram Type= 6, Freq= 0, CH_1, rank 0
6847 23:09:57.067126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 23:09:57.067554 ==
6849 23:09:57.067937
6850 23:09:57.068250
6851 23:09:57.068550 TX Vref Scan disable
6852 23:09:57.070531 == TX Byte 0 ==
6853 23:09:57.073794 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6854 23:09:57.077013 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6855 23:09:57.080135 == TX Byte 1 ==
6856 23:09:57.083895 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6857 23:09:57.087609 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6858 23:09:57.088073 ==
6859 23:09:57.090168 Dram Type= 6, Freq= 0, CH_1, rank 0
6860 23:09:57.097201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 23:09:57.097727 ==
6862 23:09:57.098064
6863 23:09:57.098421
6864 23:09:57.098733 TX Vref Scan disable
6865 23:09:57.100025 == TX Byte 0 ==
6866 23:09:57.104131 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6867 23:09:57.106825 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6868 23:09:57.110341 == TX Byte 1 ==
6869 23:09:57.113837 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6870 23:09:57.116818 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6871 23:09:57.117241
6872 23:09:57.120243 [DATLAT]
6873 23:09:57.120660 Freq=400, CH1 RK0
6874 23:09:57.120994
6875 23:09:57.124403 DATLAT Default: 0xf
6876 23:09:57.124821 0, 0xFFFF, sum = 0
6877 23:09:57.126957 1, 0xFFFF, sum = 0
6878 23:09:57.127384 2, 0xFFFF, sum = 0
6879 23:09:57.130250 3, 0xFFFF, sum = 0
6880 23:09:57.130677 4, 0xFFFF, sum = 0
6881 23:09:57.133366 5, 0xFFFF, sum = 0
6882 23:09:57.133897 6, 0xFFFF, sum = 0
6883 23:09:57.136634 7, 0xFFFF, sum = 0
6884 23:09:57.137061 8, 0xFFFF, sum = 0
6885 23:09:57.139647 9, 0xFFFF, sum = 0
6886 23:09:57.143719 10, 0xFFFF, sum = 0
6887 23:09:57.144257 11, 0xFFFF, sum = 0
6888 23:09:57.146929 12, 0xFFFF, sum = 0
6889 23:09:57.147387 13, 0x0, sum = 1
6890 23:09:57.149954 14, 0x0, sum = 2
6891 23:09:57.150487 15, 0x0, sum = 3
6892 23:09:57.153395 16, 0x0, sum = 4
6893 23:09:57.153920 best_step = 14
6894 23:09:57.154261
6895 23:09:57.154578 ==
6896 23:09:57.157025 Dram Type= 6, Freq= 0, CH_1, rank 0
6897 23:09:57.159998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 23:09:57.160424 ==
6899 23:09:57.163265 RX Vref Scan: 1
6900 23:09:57.163718
6901 23:09:57.166572 RX Vref 0 -> 0, step: 1
6902 23:09:57.166991
6903 23:09:57.167319 RX Delay -343 -> 252, step: 8
6904 23:09:57.167627
6905 23:09:57.169937 Set Vref, RX VrefLevel [Byte0]: 51
6906 23:09:57.172943 [Byte1]: 58
6907 23:09:57.178698
6908 23:09:57.179236 Final RX Vref Byte 0 = 51 to rank0
6909 23:09:57.181690 Final RX Vref Byte 1 = 58 to rank0
6910 23:09:57.184823 Final RX Vref Byte 0 = 51 to rank1
6911 23:09:57.188437 Final RX Vref Byte 1 = 58 to rank1==
6912 23:09:57.191568 Dram Type= 6, Freq= 0, CH_1, rank 0
6913 23:09:57.198024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 23:09:57.198461 ==
6915 23:09:57.198833 DQS Delay:
6916 23:09:57.201284 DQS0 = 44, DQS1 = 56
6917 23:09:57.201778 DQM Delay:
6918 23:09:57.202116 DQM0 = 8, DQM1 = 12
6919 23:09:57.205100 DQ Delay:
6920 23:09:57.208448 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6921 23:09:57.208977 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6922 23:09:57.211759 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6923 23:09:57.215359 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =24
6924 23:09:57.215914
6925 23:09:57.217826
6926 23:09:57.224612 [DQSOSCAuto] RK0, (LSB)MR18= 0x9a71, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6927 23:09:57.227776 CH1 RK0: MR19=C0C, MR18=9A71
6928 23:09:57.234748 CH1_RK0: MR19=0xC0C, MR18=0x9A71, DQSOSC=390, MR23=63, INC=388, DEC=258
6929 23:09:57.235286 ==
6930 23:09:57.237661 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 23:09:57.241064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 23:09:57.241592 ==
6933 23:09:57.245320 [Gating] SW mode calibration
6934 23:09:57.251294 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6935 23:09:57.257839 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6936 23:09:57.260578 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6937 23:09:57.264546 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6938 23:09:57.271529 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6939 23:09:57.274202 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6940 23:09:57.277531 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6941 23:09:57.283819 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6942 23:09:57.286961 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6943 23:09:57.290090 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6944 23:09:57.296814 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6945 23:09:57.297238 Total UI for P1: 0, mck2ui 16
6946 23:09:57.303715 best dqsien dly found for B0: ( 0, 14, 24)
6947 23:09:57.304143 Total UI for P1: 0, mck2ui 16
6948 23:09:57.310237 best dqsien dly found for B1: ( 0, 14, 24)
6949 23:09:57.313656 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6950 23:09:57.316545 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6951 23:09:57.317077
6952 23:09:57.319773 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6953 23:09:57.323362 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6954 23:09:57.326517 [Gating] SW calibration Done
6955 23:09:57.326942 ==
6956 23:09:57.329763 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 23:09:57.333525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 23:09:57.334040 ==
6959 23:09:57.336565 RX Vref Scan: 0
6960 23:09:57.336981
6961 23:09:57.337311 RX Vref 0 -> 0, step: 1
6962 23:09:57.339756
6963 23:09:57.340171 RX Delay -410 -> 252, step: 16
6964 23:09:57.346912 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6965 23:09:57.349827 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6966 23:09:57.353335 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6967 23:09:57.357050 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6968 23:09:57.363233 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6969 23:09:57.366254 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6970 23:09:57.369811 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6971 23:09:57.373036 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6972 23:09:57.379638 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6973 23:09:57.383335 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6974 23:09:57.386059 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6975 23:09:57.392668 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6976 23:09:57.395792 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6977 23:09:57.399097 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6978 23:09:57.402875 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6979 23:09:57.409807 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6980 23:09:57.410377 ==
6981 23:09:57.412395 Dram Type= 6, Freq= 0, CH_1, rank 1
6982 23:09:57.416207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6983 23:09:57.416776 ==
6984 23:09:57.417149 DQS Delay:
6985 23:09:57.418891 DQS0 = 43, DQS1 = 59
6986 23:09:57.419352 DQM Delay:
6987 23:09:57.422215 DQM0 = 12, DQM1 = 21
6988 23:09:57.422679 DQ Delay:
6989 23:09:57.426220 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6990 23:09:57.428796 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6991 23:09:57.432177 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6992 23:09:57.435534 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6993 23:09:57.436050
6994 23:09:57.436387
6995 23:09:57.436700 ==
6996 23:09:57.438978 Dram Type= 6, Freq= 0, CH_1, rank 1
6997 23:09:57.442594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6998 23:09:57.443175 ==
6999 23:09:57.443513
7000 23:09:57.445372
7001 23:09:57.445791 TX Vref Scan disable
7002 23:09:57.448557 == TX Byte 0 ==
7003 23:09:57.452031 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
7004 23:09:57.455664 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
7005 23:09:57.458835 == TX Byte 1 ==
7006 23:09:57.461840 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
7007 23:09:57.465193 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
7008 23:09:57.465616 ==
7009 23:09:57.468935 Dram Type= 6, Freq= 0, CH_1, rank 1
7010 23:09:57.471870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7011 23:09:57.475249 ==
7012 23:09:57.475667
7013 23:09:57.476054
7014 23:09:57.476367 TX Vref Scan disable
7015 23:09:57.478376 == TX Byte 0 ==
7016 23:09:57.481861 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
7017 23:09:57.484947 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
7018 23:09:57.488004 == TX Byte 1 ==
7019 23:09:57.491610 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
7020 23:09:57.495418 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
7021 23:09:57.495973
7022 23:09:57.496313 [DATLAT]
7023 23:09:57.498175 Freq=400, CH1 RK1
7024 23:09:57.498596
7025 23:09:57.501672 DATLAT Default: 0xe
7026 23:09:57.502186 0, 0xFFFF, sum = 0
7027 23:09:57.505072 1, 0xFFFF, sum = 0
7028 23:09:57.505676 2, 0xFFFF, sum = 0
7029 23:09:57.508437 3, 0xFFFF, sum = 0
7030 23:09:57.508863 4, 0xFFFF, sum = 0
7031 23:09:57.511469 5, 0xFFFF, sum = 0
7032 23:09:57.511933 6, 0xFFFF, sum = 0
7033 23:09:57.514812 7, 0xFFFF, sum = 0
7034 23:09:57.515241 8, 0xFFFF, sum = 0
7035 23:09:57.518585 9, 0xFFFF, sum = 0
7036 23:09:57.519014 10, 0xFFFF, sum = 0
7037 23:09:57.521637 11, 0xFFFF, sum = 0
7038 23:09:57.522125 12, 0xFFFF, sum = 0
7039 23:09:57.524955 13, 0x0, sum = 1
7040 23:09:57.525382 14, 0x0, sum = 2
7041 23:09:57.527749 15, 0x0, sum = 3
7042 23:09:57.528184 16, 0x0, sum = 4
7043 23:09:57.531220 best_step = 14
7044 23:09:57.531639
7045 23:09:57.532025 ==
7046 23:09:57.535117 Dram Type= 6, Freq= 0, CH_1, rank 1
7047 23:09:57.537693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7048 23:09:57.538119 ==
7049 23:09:57.541487 RX Vref Scan: 0
7050 23:09:57.542016
7051 23:09:57.542352 RX Vref 0 -> 0, step: 1
7052 23:09:57.542664
7053 23:09:57.544348 RX Delay -359 -> 252, step: 8
7054 23:09:57.552746 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
7055 23:09:57.556085 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
7056 23:09:57.559181 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
7057 23:09:57.565514 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7058 23:09:57.569133 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
7059 23:09:57.572712 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7060 23:09:57.575634 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7061 23:09:57.582514 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7062 23:09:57.586094 iDelay=225, Bit 8, Center -60 (-311 ~ 192) 504
7063 23:09:57.589444 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7064 23:09:57.592285 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7065 23:09:57.598732 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7066 23:09:57.602354 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7067 23:09:57.605372 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7068 23:09:57.609276 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7069 23:09:57.615518 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7070 23:09:57.616165 ==
7071 23:09:57.618771 Dram Type= 6, Freq= 0, CH_1, rank 1
7072 23:09:57.622557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7073 23:09:57.623128 ==
7074 23:09:57.623502 DQS Delay:
7075 23:09:57.625534 DQS0 = 48, DQS1 = 60
7076 23:09:57.626073 DQM Delay:
7077 23:09:57.628707 DQM0 = 11, DQM1 = 14
7078 23:09:57.629173 DQ Delay:
7079 23:09:57.631861 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =8
7080 23:09:57.635626 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
7081 23:09:57.638198 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
7082 23:09:57.641494 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7083 23:09:57.641959
7084 23:09:57.642329
7085 23:09:57.648200 [DQSOSCAuto] RK1, (LSB)MR18= 0x6958, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7086 23:09:57.651910 CH1 RK1: MR19=C0C, MR18=6958
7087 23:09:57.658475 CH1_RK1: MR19=0xC0C, MR18=0x6958, DQSOSC=396, MR23=63, INC=376, DEC=251
7088 23:09:57.661574 [RxdqsGatingPostProcess] freq 400
7089 23:09:57.668566 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7090 23:09:57.671610 best DQS0 dly(2T, 0.5T) = (0, 10)
7091 23:09:57.675333 best DQS1 dly(2T, 0.5T) = (0, 10)
7092 23:09:57.678408 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7093 23:09:57.681396 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7094 23:09:57.681866 best DQS0 dly(2T, 0.5T) = (0, 10)
7095 23:09:57.684802 best DQS1 dly(2T, 0.5T) = (0, 10)
7096 23:09:57.688371 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7097 23:09:57.691641 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7098 23:09:57.696058 Pre-setting of DQS Precalculation
7099 23:09:57.701730 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7100 23:09:57.708600 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7101 23:09:57.714902 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7102 23:09:57.715462
7103 23:09:57.715859
7104 23:09:57.717776 [Calibration Summary] 800 Mbps
7105 23:09:57.718243 CH 0, Rank 0
7106 23:09:57.721406 SW Impedance : PASS
7107 23:09:57.724589 DUTY Scan : NO K
7108 23:09:57.725203 ZQ Calibration : PASS
7109 23:09:57.727717 Jitter Meter : NO K
7110 23:09:57.731081 CBT Training : PASS
7111 23:09:57.731546 Write leveling : PASS
7112 23:09:57.735221 RX DQS gating : PASS
7113 23:09:57.738028 RX DQ/DQS(RDDQC) : PASS
7114 23:09:57.738496 TX DQ/DQS : PASS
7115 23:09:57.741370 RX DATLAT : PASS
7116 23:09:57.744371 RX DQ/DQS(Engine): PASS
7117 23:09:57.744834 TX OE : NO K
7118 23:09:57.747832 All Pass.
7119 23:09:57.748301
7120 23:09:57.748669 CH 0, Rank 1
7121 23:09:57.750740 SW Impedance : PASS
7122 23:09:57.751202 DUTY Scan : NO K
7123 23:09:57.754417 ZQ Calibration : PASS
7124 23:09:57.757287 Jitter Meter : NO K
7125 23:09:57.757785 CBT Training : PASS
7126 23:09:57.760700 Write leveling : NO K
7127 23:09:57.761160 RX DQS gating : PASS
7128 23:09:57.764929 RX DQ/DQS(RDDQC) : PASS
7129 23:09:57.767328 TX DQ/DQS : PASS
7130 23:09:57.767823 RX DATLAT : PASS
7131 23:09:57.771107 RX DQ/DQS(Engine): PASS
7132 23:09:57.774975 TX OE : NO K
7133 23:09:57.775530 All Pass.
7134 23:09:57.775963
7135 23:09:57.776306 CH 1, Rank 0
7136 23:09:57.777184 SW Impedance : PASS
7137 23:09:57.780257 DUTY Scan : NO K
7138 23:09:57.780717 ZQ Calibration : PASS
7139 23:09:57.783896 Jitter Meter : NO K
7140 23:09:57.787226 CBT Training : PASS
7141 23:09:57.787899 Write leveling : PASS
7142 23:09:57.791131 RX DQS gating : PASS
7143 23:09:57.794376 RX DQ/DQS(RDDQC) : PASS
7144 23:09:57.794945 TX DQ/DQS : PASS
7145 23:09:57.797486 RX DATLAT : PASS
7146 23:09:57.800488 RX DQ/DQS(Engine): PASS
7147 23:09:57.800955 TX OE : NO K
7148 23:09:57.803793 All Pass.
7149 23:09:57.804360
7150 23:09:57.804731 CH 1, Rank 1
7151 23:09:57.806996 SW Impedance : PASS
7152 23:09:57.807557 DUTY Scan : NO K
7153 23:09:57.810703 ZQ Calibration : PASS
7154 23:09:57.813630 Jitter Meter : NO K
7155 23:09:57.814196 CBT Training : PASS
7156 23:09:57.817577 Write leveling : NO K
7157 23:09:57.820678 RX DQS gating : PASS
7158 23:09:57.821145 RX DQ/DQS(RDDQC) : PASS
7159 23:09:57.823377 TX DQ/DQS : PASS
7160 23:09:57.826849 RX DATLAT : PASS
7161 23:09:57.827441 RX DQ/DQS(Engine): PASS
7162 23:09:57.829925 TX OE : NO K
7163 23:09:57.830390 All Pass.
7164 23:09:57.830755
7165 23:09:57.833820 DramC Write-DBI off
7166 23:09:57.836509 PER_BANK_REFRESH: Hybrid Mode
7167 23:09:57.836974 TX_TRACKING: ON
7168 23:09:57.846888 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7169 23:09:57.850027 [FAST_K] Save calibration result to emmc
7170 23:09:57.852965 dramc_set_vcore_voltage set vcore to 725000
7171 23:09:57.856751 Read voltage for 1600, 0
7172 23:09:57.857217 Vio18 = 0
7173 23:09:57.857585 Vcore = 725000
7174 23:09:57.859425 Vdram = 0
7175 23:09:57.859942 Vddq = 0
7176 23:09:57.860312 Vmddr = 0
7177 23:09:57.866317 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7178 23:09:57.869747 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7179 23:09:57.873349 MEM_TYPE=3, freq_sel=13
7180 23:09:57.876595 sv_algorithm_assistance_LP4_3733
7181 23:09:57.879154 ============ PULL DRAM RESETB DOWN ============
7182 23:09:57.883401 ========== PULL DRAM RESETB DOWN end =========
7183 23:09:57.889726 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7184 23:09:57.892811 ===================================
7185 23:09:57.896454 LPDDR4 DRAM CONFIGURATION
7186 23:09:57.899479 ===================================
7187 23:09:57.900125 EX_ROW_EN[0] = 0x0
7188 23:09:57.903067 EX_ROW_EN[1] = 0x0
7189 23:09:57.903704 LP4Y_EN = 0x0
7190 23:09:57.905443 WORK_FSP = 0x1
7191 23:09:57.905909 WL = 0x5
7192 23:09:57.909095 RL = 0x5
7193 23:09:57.909659 BL = 0x2
7194 23:09:57.912728 RPST = 0x0
7195 23:09:57.913193 RD_PRE = 0x0
7196 23:09:57.915420 WR_PRE = 0x1
7197 23:09:57.918550 WR_PST = 0x1
7198 23:09:57.919015 DBI_WR = 0x0
7199 23:09:57.921910 DBI_RD = 0x0
7200 23:09:57.922373 OTF = 0x1
7201 23:09:57.925435 ===================================
7202 23:09:57.928686 ===================================
7203 23:09:57.931974 ANA top config
7204 23:09:57.935872 ===================================
7205 23:09:57.936443 DLL_ASYNC_EN = 0
7206 23:09:57.938658 ALL_SLAVE_EN = 0
7207 23:09:57.942043 NEW_RANK_MODE = 1
7208 23:09:57.945352 DLL_IDLE_MODE = 1
7209 23:09:57.945919 LP45_APHY_COMB_EN = 1
7210 23:09:57.948239 TX_ODT_DIS = 0
7211 23:09:57.951839 NEW_8X_MODE = 1
7212 23:09:57.955402 ===================================
7213 23:09:57.959050 ===================================
7214 23:09:57.962168 data_rate = 3200
7215 23:09:57.965180 CKR = 1
7216 23:09:57.968517 DQ_P2S_RATIO = 8
7217 23:09:57.972048 ===================================
7218 23:09:57.972617 CA_P2S_RATIO = 8
7219 23:09:57.974799 DQ_CA_OPEN = 0
7220 23:09:57.978443 DQ_SEMI_OPEN = 0
7221 23:09:57.982036 CA_SEMI_OPEN = 0
7222 23:09:57.985212 CA_FULL_RATE = 0
7223 23:09:57.988927 DQ_CKDIV4_EN = 0
7224 23:09:57.989393 CA_CKDIV4_EN = 0
7225 23:09:57.991849 CA_PREDIV_EN = 0
7226 23:09:57.994648 PH8_DLY = 12
7227 23:09:57.997988 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7228 23:09:58.001912 DQ_AAMCK_DIV = 4
7229 23:09:58.004371 CA_AAMCK_DIV = 4
7230 23:09:58.004833 CA_ADMCK_DIV = 4
7231 23:09:58.008563 DQ_TRACK_CA_EN = 0
7232 23:09:58.011545 CA_PICK = 1600
7233 23:09:58.015073 CA_MCKIO = 1600
7234 23:09:58.018201 MCKIO_SEMI = 0
7235 23:09:58.021192 PLL_FREQ = 3068
7236 23:09:58.024523 DQ_UI_PI_RATIO = 32
7237 23:09:58.028121 CA_UI_PI_RATIO = 0
7238 23:09:58.031177 ===================================
7239 23:09:58.034412 ===================================
7240 23:09:58.034972 memory_type:LPDDR4
7241 23:09:58.037478 GP_NUM : 10
7242 23:09:58.040748 SRAM_EN : 1
7243 23:09:58.041207 MD32_EN : 0
7244 23:09:58.044392 ===================================
7245 23:09:58.047865 [ANA_INIT] >>>>>>>>>>>>>>
7246 23:09:58.051380 <<<<<< [CONFIGURE PHASE]: ANA_TX
7247 23:09:58.054256 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7248 23:09:58.057411 ===================================
7249 23:09:58.061049 data_rate = 3200,PCW = 0X7600
7250 23:09:58.064319 ===================================
7251 23:09:58.068154 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7252 23:09:58.070549 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7253 23:09:58.077877 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7254 23:09:58.081009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7255 23:09:58.084445 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7256 23:09:58.087374 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7257 23:09:58.090844 [ANA_INIT] flow start
7258 23:09:58.094009 [ANA_INIT] PLL >>>>>>>>
7259 23:09:58.094472 [ANA_INIT] PLL <<<<<<<<
7260 23:09:58.096873 [ANA_INIT] MIDPI >>>>>>>>
7261 23:09:58.100336 [ANA_INIT] MIDPI <<<<<<<<
7262 23:09:58.100949 [ANA_INIT] DLL >>>>>>>>
7263 23:09:58.103885 [ANA_INIT] DLL <<<<<<<<
7264 23:09:58.107788 [ANA_INIT] flow end
7265 23:09:58.111029 ============ LP4 DIFF to SE enter ============
7266 23:09:58.114083 ============ LP4 DIFF to SE exit ============
7267 23:09:58.117048 [ANA_INIT] <<<<<<<<<<<<<
7268 23:09:58.120237 [Flow] Enable top DCM control >>>>>
7269 23:09:58.123427 [Flow] Enable top DCM control <<<<<
7270 23:09:58.127049 Enable DLL master slave shuffle
7271 23:09:58.133325 ==============================================================
7272 23:09:58.133795 Gating Mode config
7273 23:09:58.140425 ==============================================================
7274 23:09:58.140889 Config description:
7275 23:09:58.150370 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7276 23:09:58.156398 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7277 23:09:58.163986 SELPH_MODE 0: By rank 1: By Phase
7278 23:09:58.167105 ==============================================================
7279 23:09:58.170184 GAT_TRACK_EN = 1
7280 23:09:58.173364 RX_GATING_MODE = 2
7281 23:09:58.177073 RX_GATING_TRACK_MODE = 2
7282 23:09:58.179521 SELPH_MODE = 1
7283 23:09:58.183356 PICG_EARLY_EN = 1
7284 23:09:58.186771 VALID_LAT_VALUE = 1
7285 23:09:58.192834 ==============================================================
7286 23:09:58.196166 Enter into Gating configuration >>>>
7287 23:09:58.199432 Exit from Gating configuration <<<<
7288 23:09:58.202537 Enter into DVFS_PRE_config >>>>>
7289 23:09:58.212597 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7290 23:09:58.216012 Exit from DVFS_PRE_config <<<<<
7291 23:09:58.219424 Enter into PICG configuration >>>>
7292 23:09:58.222829 Exit from PICG configuration <<<<
7293 23:09:58.226011 [RX_INPUT] configuration >>>>>
7294 23:09:58.226478 [RX_INPUT] configuration <<<<<
7295 23:09:58.232854 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7296 23:09:58.238806 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7297 23:09:58.242635 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7298 23:09:58.248867 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7299 23:09:58.255584 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7300 23:09:58.262595 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7301 23:09:58.265403 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7302 23:09:58.268599 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7303 23:09:58.275419 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7304 23:09:58.278703 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7305 23:09:58.281794 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7306 23:09:58.288983 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7307 23:09:58.292311 ===================================
7308 23:09:58.292774 LPDDR4 DRAM CONFIGURATION
7309 23:09:58.295604 ===================================
7310 23:09:58.298433 EX_ROW_EN[0] = 0x0
7311 23:09:58.301669 EX_ROW_EN[1] = 0x0
7312 23:09:58.302133 LP4Y_EN = 0x0
7313 23:09:58.304977 WORK_FSP = 0x1
7314 23:09:58.305400 WL = 0x5
7315 23:09:58.308285 RL = 0x5
7316 23:09:58.308854 BL = 0x2
7317 23:09:58.311532 RPST = 0x0
7318 23:09:58.312090 RD_PRE = 0x0
7319 23:09:58.314830 WR_PRE = 0x1
7320 23:09:58.315458 WR_PST = 0x1
7321 23:09:58.318398 DBI_WR = 0x0
7322 23:09:58.318966 DBI_RD = 0x0
7323 23:09:58.321200 OTF = 0x1
7324 23:09:58.324931 ===================================
7325 23:09:58.328029 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7326 23:09:58.331375 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7327 23:09:58.338017 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7328 23:09:58.340887 ===================================
7329 23:09:58.341312 LPDDR4 DRAM CONFIGURATION
7330 23:09:58.344166 ===================================
7331 23:09:58.347945 EX_ROW_EN[0] = 0x10
7332 23:09:58.350783 EX_ROW_EN[1] = 0x0
7333 23:09:58.351311 LP4Y_EN = 0x0
7334 23:09:58.354553 WORK_FSP = 0x1
7335 23:09:58.354975 WL = 0x5
7336 23:09:58.357347 RL = 0x5
7337 23:09:58.357771 BL = 0x2
7338 23:09:58.360587 RPST = 0x0
7339 23:09:58.361007 RD_PRE = 0x0
7340 23:09:58.364362 WR_PRE = 0x1
7341 23:09:58.364784 WR_PST = 0x1
7342 23:09:58.367874 DBI_WR = 0x0
7343 23:09:58.368396 DBI_RD = 0x0
7344 23:09:58.370458 OTF = 0x1
7345 23:09:58.373702 ===================================
7346 23:09:58.380816 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7347 23:09:58.381425 ==
7348 23:09:58.383796 Dram Type= 6, Freq= 0, CH_0, rank 0
7349 23:09:58.387282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7350 23:09:58.387725 ==
7351 23:09:58.390687 [Duty_Offset_Calibration]
7352 23:09:58.391243 B0:1 B1:-1 CA:0
7353 23:09:58.391608
7354 23:09:58.393782 [DutyScan_Calibration_Flow] k_type=0
7355 23:09:58.405208
7356 23:09:58.405759 ==CLK 0==
7357 23:09:58.407995 Final CLK duty delay cell = 0
7358 23:09:58.411496 [0] MAX Duty = 5156%(X100), DQS PI = 22
7359 23:09:58.414651 [0] MIN Duty = 4907%(X100), DQS PI = 6
7360 23:09:58.417862 [0] AVG Duty = 5031%(X100)
7361 23:09:58.418316
7362 23:09:58.421335 CH0 CLK Duty spec in!! Max-Min= 249%
7363 23:09:58.424786 [DutyScan_Calibration_Flow] ====Done====
7364 23:09:58.425309
7365 23:09:58.427547 [DutyScan_Calibration_Flow] k_type=1
7366 23:09:58.444375
7367 23:09:58.444915 ==DQS 0 ==
7368 23:09:58.447006 Final DQS duty delay cell = -4
7369 23:09:58.450722 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7370 23:09:58.453636 [-4] MIN Duty = 4875%(X100), DQS PI = 10
7371 23:09:58.456931 [-4] AVG Duty = 4937%(X100)
7372 23:09:58.457352
7373 23:09:58.457674 ==DQS 1 ==
7374 23:09:58.460354 Final DQS duty delay cell = 0
7375 23:09:58.463608 [0] MAX Duty = 5187%(X100), DQS PI = 4
7376 23:09:58.466973 [0] MIN Duty = 5031%(X100), DQS PI = 16
7377 23:09:58.470646 [0] AVG Duty = 5109%(X100)
7378 23:09:58.471061
7379 23:09:58.473494 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7380 23:09:58.474019
7381 23:09:58.476524 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7382 23:09:58.479651 [DutyScan_Calibration_Flow] ====Done====
7383 23:09:58.480088
7384 23:09:58.483186 [DutyScan_Calibration_Flow] k_type=3
7385 23:09:58.501557
7386 23:09:58.502153 ==DQM 0 ==
7387 23:09:58.505397 Final DQM duty delay cell = 0
7388 23:09:58.508337 [0] MAX Duty = 5124%(X100), DQS PI = 20
7389 23:09:58.511414 [0] MIN Duty = 4907%(X100), DQS PI = 8
7390 23:09:58.512077 [0] AVG Duty = 5015%(X100)
7391 23:09:58.514896
7392 23:09:58.515349 ==DQM 1 ==
7393 23:09:58.518479 Final DQM duty delay cell = 0
7394 23:09:58.521326 [0] MAX Duty = 5031%(X100), DQS PI = 10
7395 23:09:58.525047 [0] MIN Duty = 4813%(X100), DQS PI = 20
7396 23:09:58.527888 [0] AVG Duty = 4922%(X100)
7397 23:09:58.528348
7398 23:09:58.531610 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7399 23:09:58.532114
7400 23:09:58.535043 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7401 23:09:58.537905 [DutyScan_Calibration_Flow] ====Done====
7402 23:09:58.538467
7403 23:09:58.541020 [DutyScan_Calibration_Flow] k_type=2
7404 23:09:58.558244
7405 23:09:58.558705 ==DQ 0 ==
7406 23:09:58.561909 Final DQ duty delay cell = -4
7407 23:09:58.564168 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7408 23:09:58.568177 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7409 23:09:58.571209 [-4] AVG Duty = 4953%(X100)
7410 23:09:58.571738
7411 23:09:58.572236 ==DQ 1 ==
7412 23:09:58.574119 Final DQ duty delay cell = 0
7413 23:09:58.577499 [0] MAX Duty = 5125%(X100), DQS PI = 48
7414 23:09:58.581291 [0] MIN Duty = 5000%(X100), DQS PI = 36
7415 23:09:58.584251 [0] AVG Duty = 5062%(X100)
7416 23:09:58.584709
7417 23:09:58.587059 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7418 23:09:58.587522
7419 23:09:58.590560 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7420 23:09:58.594440 [DutyScan_Calibration_Flow] ====Done====
7421 23:09:58.594996 ==
7422 23:09:58.597095 Dram Type= 6, Freq= 0, CH_1, rank 0
7423 23:09:58.600996 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7424 23:09:58.601456 ==
7425 23:09:58.603660 [Duty_Offset_Calibration]
7426 23:09:58.604148 B0:-1 B1:1 CA:2
7427 23:09:58.607206
7428 23:09:58.610282 [DutyScan_Calibration_Flow] k_type=0
7429 23:09:58.618677
7430 23:09:58.619187 ==CLK 0==
7431 23:09:58.621582 Final CLK duty delay cell = 0
7432 23:09:58.624759 [0] MAX Duty = 5187%(X100), DQS PI = 22
7433 23:09:58.628342 [0] MIN Duty = 5000%(X100), DQS PI = 0
7434 23:09:58.628755 [0] AVG Duty = 5093%(X100)
7435 23:09:58.632108
7436 23:09:58.635238 CH1 CLK Duty spec in!! Max-Min= 187%
7437 23:09:58.638135 [DutyScan_Calibration_Flow] ====Done====
7438 23:09:58.638546
7439 23:09:58.641559 [DutyScan_Calibration_Flow] k_type=1
7440 23:09:58.658270
7441 23:09:58.658775 ==DQS 0 ==
7442 23:09:58.661660 Final DQS duty delay cell = 0
7443 23:09:58.665164 [0] MAX Duty = 5124%(X100), DQS PI = 18
7444 23:09:58.668141 [0] MIN Duty = 4907%(X100), DQS PI = 10
7445 23:09:58.671968 [0] AVG Duty = 5015%(X100)
7446 23:09:58.672481
7447 23:09:58.672817 ==DQS 1 ==
7448 23:09:58.674519 Final DQS duty delay cell = 0
7449 23:09:58.678246 [0] MAX Duty = 5093%(X100), DQS PI = 26
7450 23:09:58.681834 [0] MIN Duty = 4969%(X100), DQS PI = 54
7451 23:09:58.684765 [0] AVG Duty = 5031%(X100)
7452 23:09:58.685185
7453 23:09:58.687909 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7454 23:09:58.688327
7455 23:09:58.690608 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7456 23:09:58.694278 [DutyScan_Calibration_Flow] ====Done====
7457 23:09:58.694785
7458 23:09:58.698119 [DutyScan_Calibration_Flow] k_type=3
7459 23:09:58.715345
7460 23:09:58.715942 ==DQM 0 ==
7461 23:09:58.717607 Final DQM duty delay cell = -4
7462 23:09:58.720966 [-4] MAX Duty = 5062%(X100), DQS PI = 20
7463 23:09:58.723941 [-4] MIN Duty = 4782%(X100), DQS PI = 10
7464 23:09:58.727592 [-4] AVG Duty = 4922%(X100)
7465 23:09:58.728295
7466 23:09:58.728680 ==DQM 1 ==
7467 23:09:58.730833 Final DQM duty delay cell = 0
7468 23:09:58.733665 [0] MAX Duty = 5187%(X100), DQS PI = 2
7469 23:09:58.737527 [0] MIN Duty = 4938%(X100), DQS PI = 36
7470 23:09:58.740608 [0] AVG Duty = 5062%(X100)
7471 23:09:58.741069
7472 23:09:58.743781 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7473 23:09:58.744336
7474 23:09:58.747122 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7475 23:09:58.750166 [DutyScan_Calibration_Flow] ====Done====
7476 23:09:58.750630
7477 23:09:58.754166 [DutyScan_Calibration_Flow] k_type=2
7478 23:09:58.771856
7479 23:09:58.772403 ==DQ 0 ==
7480 23:09:58.775337 Final DQ duty delay cell = 0
7481 23:09:58.778433 [0] MAX Duty = 5156%(X100), DQS PI = 28
7482 23:09:58.781454 [0] MIN Duty = 4906%(X100), DQS PI = 10
7483 23:09:58.782019 [0] AVG Duty = 5031%(X100)
7484 23:09:58.784829
7485 23:09:58.785286 ==DQ 1 ==
7486 23:09:58.788398 Final DQ duty delay cell = 0
7487 23:09:58.791515 [0] MAX Duty = 5156%(X100), DQS PI = 8
7488 23:09:58.794464 [0] MIN Duty = 4969%(X100), DQS PI = 56
7489 23:09:58.794928 [0] AVG Duty = 5062%(X100)
7490 23:09:58.797712
7491 23:09:58.801392 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7492 23:09:58.801855
7493 23:09:58.804708 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7494 23:09:58.807772 [DutyScan_Calibration_Flow] ====Done====
7495 23:09:58.810991 nWR fixed to 30
7496 23:09:58.811455 [ModeRegInit_LP4] CH0 RK0
7497 23:09:58.814601 [ModeRegInit_LP4] CH0 RK1
7498 23:09:58.818000 [ModeRegInit_LP4] CH1 RK0
7499 23:09:58.820891 [ModeRegInit_LP4] CH1 RK1
7500 23:09:58.821416 match AC timing 5
7501 23:09:58.827800 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7502 23:09:58.830991 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7503 23:09:58.834445 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7504 23:09:58.840803 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7505 23:09:58.844169 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7506 23:09:58.844591 [MiockJmeterHQA]
7507 23:09:58.844922
7508 23:09:58.847455 [DramcMiockJmeter] u1RxGatingPI = 0
7509 23:09:58.851012 0 : 4363, 4137
7510 23:09:58.851439 4 : 4252, 4026
7511 23:09:58.853842 8 : 4363, 4137
7512 23:09:58.854267 12 : 4253, 4026
7513 23:09:58.854605 16 : 4253, 4026
7514 23:09:58.857506 20 : 4362, 4137
7515 23:09:58.858059 24 : 4361, 4137
7516 23:09:58.860500 28 : 4252, 4027
7517 23:09:58.860921 32 : 4250, 4027
7518 23:09:58.864356 36 : 4250, 4027
7519 23:09:58.864780 40 : 4363, 4137
7520 23:09:58.867244 44 : 4250, 4027
7521 23:09:58.867700 48 : 4361, 4138
7522 23:09:58.868061 52 : 4253, 4026
7523 23:09:58.870480 56 : 4250, 4027
7524 23:09:58.871001 60 : 4249, 4027
7525 23:09:58.873846 64 : 4253, 4029
7526 23:09:58.874268 68 : 4360, 4137
7527 23:09:58.877116 72 : 4250, 4026
7528 23:09:58.877641 76 : 4360, 4138
7529 23:09:58.880650 80 : 4250, 4027
7530 23:09:58.881170 84 : 4250, 4027
7531 23:09:58.883765 88 : 4249, 4026
7532 23:09:58.884303 92 : 4360, 869
7533 23:09:58.884645 96 : 4253, 0
7534 23:09:58.887248 100 : 4252, 0
7535 23:09:58.887711 104 : 4361, 0
7536 23:09:58.888066 108 : 4361, 0
7537 23:09:58.890085 112 : 4363, 0
7538 23:09:58.890510 116 : 4250, 0
7539 23:09:58.893219 120 : 4250, 0
7540 23:09:58.893646 124 : 4363, 0
7541 23:09:58.893984 128 : 4250, 0
7542 23:09:58.897013 132 : 4253, 0
7543 23:09:58.897434 136 : 4250, 0
7544 23:09:58.900084 140 : 4253, 0
7545 23:09:58.900508 144 : 4360, 0
7546 23:09:58.900847 148 : 4250, 0
7547 23:09:58.903051 152 : 4250, 0
7548 23:09:58.903502 156 : 4250, 0
7549 23:09:58.906846 160 : 4360, 0
7550 23:09:58.907369 164 : 4250, 0
7551 23:09:58.907743 168 : 4250, 0
7552 23:09:58.909604 172 : 4360, 0
7553 23:09:58.910029 176 : 4249, 0
7554 23:09:58.913919 180 : 4250, 0
7555 23:09:58.914344 184 : 4250, 0
7556 23:09:58.914684 188 : 4250, 0
7557 23:09:58.916247 192 : 4252, 0
7558 23:09:58.916808 196 : 4360, 0
7559 23:09:58.919793 200 : 4250, 0
7560 23:09:58.920312 204 : 4250, 0
7561 23:09:58.920657 208 : 4250, 0
7562 23:09:58.923622 212 : 4360, 0
7563 23:09:58.924187 216 : 4250, 0
7564 23:09:58.926500 220 : 4250, 0
7565 23:09:58.926924 224 : 4249, 433
7566 23:09:58.927261 228 : 4253, 3200
7567 23:09:58.929573 232 : 4361, 4137
7568 23:09:58.929998 236 : 4252, 4029
7569 23:09:58.933022 240 : 4249, 4027
7570 23:09:58.933451 244 : 4250, 4026
7571 23:09:58.935789 248 : 4253, 4029
7572 23:09:58.936216 252 : 4250, 4027
7573 23:09:58.939233 256 : 4249, 4027
7574 23:09:58.939663 260 : 4250, 4026
7575 23:09:58.943059 264 : 4253, 4029
7576 23:09:58.943590 268 : 4250, 4027
7577 23:09:58.945923 272 : 4360, 4137
7578 23:09:58.946351 276 : 4360, 4137
7579 23:09:58.949249 280 : 4250, 4027
7580 23:09:58.949923 284 : 4363, 4140
7581 23:09:58.952499 288 : 4250, 4027
7582 23:09:58.952927 292 : 4250, 4027
7583 23:09:58.953263 296 : 4250, 4026
7584 23:09:58.956047 300 : 4253, 4029
7585 23:09:58.956496 304 : 4250, 4027
7586 23:09:58.958781 308 : 4250, 4027
7587 23:09:58.959211 312 : 4250, 4026
7588 23:09:58.962834 316 : 4253, 4029
7589 23:09:58.963367 320 : 4250, 4027
7590 23:09:58.965711 324 : 4361, 4138
7591 23:09:58.966318 328 : 4360, 4137
7592 23:09:58.968707 332 : 4250, 4027
7593 23:09:58.969179 336 : 4363, 3743
7594 23:09:58.972246 340 : 4250, 1887
7595 23:09:58.972719
7596 23:09:58.973089 MIOCK jitter meter ch=0
7597 23:09:58.973436
7598 23:09:58.975336 1T = (340-92) = 248 dly cells
7599 23:09:58.982369 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7600 23:09:58.982936 ==
7601 23:09:58.985707 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 23:09:58.988978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 23:09:58.989536 ==
7604 23:09:58.995324 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7605 23:09:58.998542 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7606 23:09:59.005375 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7607 23:09:59.008946 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7608 23:09:59.019250 [CA 0] Center 43 (13~74) winsize 62
7609 23:09:59.022331 [CA 1] Center 43 (13~74) winsize 62
7610 23:09:59.025421 [CA 2] Center 39 (10~69) winsize 60
7611 23:09:59.028954 [CA 3] Center 39 (10~69) winsize 60
7612 23:09:59.032709 [CA 4] Center 37 (8~66) winsize 59
7613 23:09:59.034936 [CA 5] Center 36 (7~66) winsize 60
7614 23:09:59.035610
7615 23:09:59.039110 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7616 23:09:59.039788
7617 23:09:59.045078 [CATrainingPosCal] consider 1 rank data
7618 23:09:59.045653 u2DelayCellTimex100 = 262/100 ps
7619 23:09:59.051850 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7620 23:09:59.055267 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7621 23:09:59.058010 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7622 23:09:59.061552 CA3 delay=39 (10~69),Diff = 3 PI (11 cell)
7623 23:09:59.064784 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7624 23:09:59.068629 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7625 23:09:59.069192
7626 23:09:59.071952 CA PerBit enable=1, Macro0, CA PI delay=36
7627 23:09:59.072517
7628 23:09:59.074677 [CBTSetCACLKResult] CA Dly = 36
7629 23:09:59.077936 CS Dly: 12 (0~43)
7630 23:09:59.081403 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7631 23:09:59.084608 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7632 23:09:59.085224 ==
7633 23:09:59.088243 Dram Type= 6, Freq= 0, CH_0, rank 1
7634 23:09:59.094495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7635 23:09:59.095121 ==
7636 23:09:59.098391 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7637 23:09:59.105060 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7638 23:09:59.107892 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7639 23:09:59.114075 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7640 23:09:59.122366 [CA 0] Center 42 (12~73) winsize 62
7641 23:09:59.125753 [CA 1] Center 43 (13~73) winsize 61
7642 23:09:59.129231 [CA 2] Center 37 (8~67) winsize 60
7643 23:09:59.133035 [CA 3] Center 37 (7~67) winsize 61
7644 23:09:59.136033 [CA 4] Center 35 (6~65) winsize 60
7645 23:09:59.138974 [CA 5] Center 35 (5~65) winsize 61
7646 23:09:59.139564
7647 23:09:59.142801 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7648 23:09:59.143369
7649 23:09:59.146195 [CATrainingPosCal] consider 2 rank data
7650 23:09:59.149048 u2DelayCellTimex100 = 262/100 ps
7651 23:09:59.155271 CA0 delay=43 (13~73),Diff = 7 PI (26 cell)
7652 23:09:59.158925 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7653 23:09:59.161686 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7654 23:09:59.164996 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7655 23:09:59.168595 CA4 delay=36 (8~65),Diff = 0 PI (0 cell)
7656 23:09:59.172044 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7657 23:09:59.172643
7658 23:09:59.176175 CA PerBit enable=1, Macro0, CA PI delay=36
7659 23:09:59.176644
7660 23:09:59.178816 [CBTSetCACLKResult] CA Dly = 36
7661 23:09:59.181853 CS Dly: 12 (0~44)
7662 23:09:59.185027 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7663 23:09:59.188977 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7664 23:09:59.189581
7665 23:09:59.191595 ----->DramcWriteLeveling(PI) begin...
7666 23:09:59.195503 ==
7667 23:09:59.196118 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 23:09:59.201362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7669 23:09:59.202001 ==
7670 23:09:59.205066 Write leveling (Byte 0): 34 => 34
7671 23:09:59.208152 Write leveling (Byte 1): 28 => 28
7672 23:09:59.211175 DramcWriteLeveling(PI) end<-----
7673 23:09:59.211768
7674 23:09:59.212148 ==
7675 23:09:59.214873 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 23:09:59.217858 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 23:09:59.218332 ==
7678 23:09:59.221270 [Gating] SW mode calibration
7679 23:09:59.227526 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7680 23:09:59.234771 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7681 23:09:59.238154 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7682 23:09:59.241372 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7683 23:09:59.247706 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7684 23:09:59.251769 1 4 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7685 23:09:59.254458 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7686 23:09:59.261111 1 4 20 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
7687 23:09:59.264309 1 4 24 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
7688 23:09:59.267496 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7689 23:09:59.273552 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7690 23:09:59.277377 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7691 23:09:59.281150 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7692 23:09:59.287338 1 5 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
7693 23:09:59.290510 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7694 23:09:59.294045 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
7695 23:09:59.300199 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
7696 23:09:59.303733 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7697 23:09:59.306759 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7698 23:09:59.313693 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7699 23:09:59.316829 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7700 23:09:59.320006 1 6 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7701 23:09:59.326586 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7702 23:09:59.330368 1 6 20 | B1->B0 | 2b2b 4646 | 1 0 | (0 0) (0 0)
7703 23:09:59.334052 1 6 24 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
7704 23:09:59.340230 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7705 23:09:59.343261 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7706 23:09:59.346138 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7707 23:09:59.352974 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7708 23:09:59.356299 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7709 23:09:59.360303 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7710 23:09:59.366220 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7711 23:09:59.369203 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7712 23:09:59.372883 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7713 23:09:59.379356 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7714 23:09:59.382573 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7715 23:09:59.385659 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7716 23:09:59.392506 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7717 23:09:59.395932 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7718 23:09:59.399221 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7719 23:09:59.405575 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7720 23:09:59.409305 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7721 23:09:59.412138 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7722 23:09:59.418546 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7723 23:09:59.421807 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7724 23:09:59.425406 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7725 23:09:59.431984 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7726 23:09:59.432562 Total UI for P1: 0, mck2ui 16
7727 23:09:59.438510 best dqsien dly found for B0: ( 1, 9, 12)
7728 23:09:59.441831 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7729 23:09:59.445350 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7730 23:09:59.451858 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7731 23:09:59.452407 Total UI for P1: 0, mck2ui 16
7732 23:09:59.458206 best dqsien dly found for B1: ( 1, 9, 20)
7733 23:09:59.461780 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7734 23:09:59.465463 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7735 23:09:59.466021
7736 23:09:59.468043 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7737 23:09:59.471739 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7738 23:09:59.475008 [Gating] SW calibration Done
7739 23:09:59.475562 ==
7740 23:09:59.478251 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 23:09:59.481570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 23:09:59.482176 ==
7743 23:09:59.485019 RX Vref Scan: 0
7744 23:09:59.485570
7745 23:09:59.486001 RX Vref 0 -> 0, step: 1
7746 23:09:59.487650
7747 23:09:59.488151 RX Delay 0 -> 252, step: 8
7748 23:09:59.494824 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7749 23:09:59.497662 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7750 23:09:59.500775 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7751 23:09:59.504209 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7752 23:09:59.507573 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7753 23:09:59.514196 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7754 23:09:59.517426 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7755 23:09:59.520973 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7756 23:09:59.524365 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7757 23:09:59.527220 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7758 23:09:59.534397 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7759 23:09:59.537005 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7760 23:09:59.540399 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7761 23:09:59.544192 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7762 23:09:59.547384 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7763 23:09:59.554103 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7764 23:09:59.554899 ==
7765 23:09:59.557274 Dram Type= 6, Freq= 0, CH_0, rank 0
7766 23:09:59.560291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7767 23:09:59.560764 ==
7768 23:09:59.561140 DQS Delay:
7769 23:09:59.564216 DQS0 = 0, DQS1 = 0
7770 23:09:59.564785 DQM Delay:
7771 23:09:59.567369 DQM0 = 134, DQM1 = 126
7772 23:09:59.567988 DQ Delay:
7773 23:09:59.570466 DQ0 =131, DQ1 =139, DQ2 =131, DQ3 =131
7774 23:09:59.574182 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =147
7775 23:09:59.577103 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7776 23:09:59.583590 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7777 23:09:59.584208
7778 23:09:59.584665
7779 23:09:59.585017 ==
7780 23:09:59.586564 Dram Type= 6, Freq= 0, CH_0, rank 0
7781 23:09:59.590003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7782 23:09:59.590622 ==
7783 23:09:59.591002
7784 23:09:59.591346
7785 23:09:59.593022 TX Vref Scan disable
7786 23:09:59.593485 == TX Byte 0 ==
7787 23:09:59.600267 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7788 23:09:59.603383 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7789 23:09:59.603885 == TX Byte 1 ==
7790 23:09:59.610906 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7791 23:09:59.613179 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7792 23:09:59.613649 ==
7793 23:09:59.616382 Dram Type= 6, Freq= 0, CH_0, rank 0
7794 23:09:59.619583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7795 23:09:59.620103 ==
7796 23:09:59.633780
7797 23:09:59.637080 TX Vref early break, caculate TX vref
7798 23:09:59.640094 TX Vref=16, minBit 4, minWin=22, winSum=376
7799 23:09:59.643799 TX Vref=18, minBit 4, minWin=23, winSum=383
7800 23:09:59.646873 TX Vref=20, minBit 3, minWin=24, winSum=395
7801 23:09:59.650279 TX Vref=22, minBit 6, minWin=23, winSum=397
7802 23:09:59.653909 TX Vref=24, minBit 2, minWin=25, winSum=412
7803 23:09:59.660387 TX Vref=26, minBit 1, minWin=25, winSum=419
7804 23:09:59.663331 TX Vref=28, minBit 0, minWin=25, winSum=418
7805 23:09:59.666721 TX Vref=30, minBit 4, minWin=24, winSum=411
7806 23:09:59.670103 TX Vref=32, minBit 0, minWin=24, winSum=407
7807 23:09:59.673027 TX Vref=34, minBit 4, minWin=23, winSum=391
7808 23:09:59.679591 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 26
7809 23:09:59.680055
7810 23:09:59.682924 Final TX Range 0 Vref 26
7811 23:09:59.683348
7812 23:09:59.683722 ==
7813 23:09:59.686286 Dram Type= 6, Freq= 0, CH_0, rank 0
7814 23:09:59.689526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7815 23:09:59.689968 ==
7816 23:09:59.690301
7817 23:09:59.693035
7818 23:09:59.693456 TX Vref Scan disable
7819 23:09:59.700076 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7820 23:09:59.700508 == TX Byte 0 ==
7821 23:09:59.702818 u2DelayCellOfst[0]=14 cells (4 PI)
7822 23:09:59.706355 u2DelayCellOfst[1]=18 cells (5 PI)
7823 23:09:59.710053 u2DelayCellOfst[2]=14 cells (4 PI)
7824 23:09:59.713280 u2DelayCellOfst[3]=14 cells (4 PI)
7825 23:09:59.716134 u2DelayCellOfst[4]=11 cells (3 PI)
7826 23:09:59.719266 u2DelayCellOfst[5]=0 cells (0 PI)
7827 23:09:59.722608 u2DelayCellOfst[6]=22 cells (6 PI)
7828 23:09:59.726369 u2DelayCellOfst[7]=18 cells (5 PI)
7829 23:09:59.729464 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7830 23:09:59.732363 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7831 23:09:59.735824 == TX Byte 1 ==
7832 23:09:59.739019 u2DelayCellOfst[8]=0 cells (0 PI)
7833 23:09:59.742997 u2DelayCellOfst[9]=0 cells (0 PI)
7834 23:09:59.745948 u2DelayCellOfst[10]=7 cells (2 PI)
7835 23:09:59.749435 u2DelayCellOfst[11]=0 cells (0 PI)
7836 23:09:59.749850 u2DelayCellOfst[12]=11 cells (3 PI)
7837 23:09:59.753229 u2DelayCellOfst[13]=11 cells (3 PI)
7838 23:09:59.756127 u2DelayCellOfst[14]=14 cells (4 PI)
7839 23:09:59.759157 u2DelayCellOfst[15]=11 cells (3 PI)
7840 23:09:59.766084 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7841 23:09:59.769945 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7842 23:09:59.770423 DramC Write-DBI on
7843 23:09:59.772119 ==
7844 23:09:59.775548 Dram Type= 6, Freq= 0, CH_0, rank 0
7845 23:09:59.779359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7846 23:09:59.779990 ==
7847 23:09:59.780367
7848 23:09:59.780707
7849 23:09:59.781815 TX Vref Scan disable
7850 23:09:59.782272 == TX Byte 0 ==
7851 23:09:59.788851 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7852 23:09:59.789311 == TX Byte 1 ==
7853 23:09:59.792383 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7854 23:09:59.795345 DramC Write-DBI off
7855 23:09:59.795966
7856 23:09:59.796333 [DATLAT]
7857 23:09:59.798496 Freq=1600, CH0 RK0
7858 23:09:59.799005
7859 23:09:59.799385 DATLAT Default: 0xf
7860 23:09:59.802125 0, 0xFFFF, sum = 0
7861 23:09:59.802589 1, 0xFFFF, sum = 0
7862 23:09:59.805778 2, 0xFFFF, sum = 0
7863 23:09:59.806342 3, 0xFFFF, sum = 0
7864 23:09:59.808853 4, 0xFFFF, sum = 0
7865 23:09:59.809420 5, 0xFFFF, sum = 0
7866 23:09:59.812526 6, 0xFFFF, sum = 0
7867 23:09:59.815836 7, 0xFFFF, sum = 0
7868 23:09:59.816404 8, 0xFFFF, sum = 0
7869 23:09:59.818552 9, 0xFFFF, sum = 0
7870 23:09:59.819118 10, 0xFFFF, sum = 0
7871 23:09:59.822573 11, 0xFFFF, sum = 0
7872 23:09:59.823142 12, 0xFFFF, sum = 0
7873 23:09:59.825061 13, 0xFFFF, sum = 0
7874 23:09:59.825577 14, 0x0, sum = 1
7875 23:09:59.828307 15, 0x0, sum = 2
7876 23:09:59.828846 16, 0x0, sum = 3
7877 23:09:59.832219 17, 0x0, sum = 4
7878 23:09:59.832788 best_step = 15
7879 23:09:59.833153
7880 23:09:59.833484 ==
7881 23:09:59.835310 Dram Type= 6, Freq= 0, CH_0, rank 0
7882 23:09:59.838699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7883 23:09:59.841754 ==
7884 23:09:59.842599 RX Vref Scan: 1
7885 23:09:59.842997
7886 23:09:59.844714 Set Vref Range= 24 -> 127
7887 23:09:59.845171
7888 23:09:59.847905 RX Vref 24 -> 127, step: 1
7889 23:09:59.848363
7890 23:09:59.848728 RX Delay 11 -> 252, step: 4
7891 23:09:59.849168
7892 23:09:59.851618 Set Vref, RX VrefLevel [Byte0]: 24
7893 23:09:59.855061 [Byte1]: 24
7894 23:09:59.858663
7895 23:09:59.859122 Set Vref, RX VrefLevel [Byte0]: 25
7896 23:09:59.862320 [Byte1]: 25
7897 23:09:59.866569
7898 23:09:59.867024 Set Vref, RX VrefLevel [Byte0]: 26
7899 23:09:59.869700 [Byte1]: 26
7900 23:09:59.873822
7901 23:09:59.874293 Set Vref, RX VrefLevel [Byte0]: 27
7902 23:09:59.877941 [Byte1]: 27
7903 23:09:59.881768
7904 23:09:59.882331 Set Vref, RX VrefLevel [Byte0]: 28
7905 23:09:59.884920 [Byte1]: 28
7906 23:09:59.888822
7907 23:09:59.889320 Set Vref, RX VrefLevel [Byte0]: 29
7908 23:09:59.892949 [Byte1]: 29
7909 23:09:59.897086
7910 23:09:59.897565 Set Vref, RX VrefLevel [Byte0]: 30
7911 23:09:59.899753 [Byte1]: 30
7912 23:09:59.904551
7913 23:09:59.905032 Set Vref, RX VrefLevel [Byte0]: 31
7914 23:09:59.907886 [Byte1]: 31
7915 23:09:59.911898
7916 23:09:59.912436 Set Vref, RX VrefLevel [Byte0]: 32
7917 23:09:59.915386 [Byte1]: 32
7918 23:09:59.919478
7919 23:09:59.920070 Set Vref, RX VrefLevel [Byte0]: 33
7920 23:09:59.923033 [Byte1]: 33
7921 23:09:59.927586
7922 23:09:59.928192 Set Vref, RX VrefLevel [Byte0]: 34
7923 23:09:59.930364 [Byte1]: 34
7924 23:09:59.935214
7925 23:09:59.935847 Set Vref, RX VrefLevel [Byte0]: 35
7926 23:09:59.938864 [Byte1]: 35
7927 23:09:59.942566
7928 23:09:59.943118 Set Vref, RX VrefLevel [Byte0]: 36
7929 23:09:59.946348 [Byte1]: 36
7930 23:09:59.951067
7931 23:09:59.951535 Set Vref, RX VrefLevel [Byte0]: 37
7932 23:09:59.953034 [Byte1]: 37
7933 23:09:59.957514
7934 23:09:59.958035 Set Vref, RX VrefLevel [Byte0]: 38
7935 23:09:59.960979 [Byte1]: 38
7936 23:09:59.965424
7937 23:09:59.965888 Set Vref, RX VrefLevel [Byte0]: 39
7938 23:09:59.969217 [Byte1]: 39
7939 23:09:59.972585
7940 23:09:59.973006 Set Vref, RX VrefLevel [Byte0]: 40
7941 23:09:59.975836 [Byte1]: 40
7942 23:09:59.980337
7943 23:09:59.980757 Set Vref, RX VrefLevel [Byte0]: 41
7944 23:09:59.984495 [Byte1]: 41
7945 23:09:59.988527
7946 23:09:59.989048 Set Vref, RX VrefLevel [Byte0]: 42
7947 23:09:59.991154 [Byte1]: 42
7948 23:09:59.995321
7949 23:09:59.995899 Set Vref, RX VrefLevel [Byte0]: 43
7950 23:09:59.998647 [Byte1]: 43
7951 23:10:00.003011
7952 23:10:00.003433 Set Vref, RX VrefLevel [Byte0]: 44
7953 23:10:00.006796 [Byte1]: 44
7954 23:10:00.010927
7955 23:10:00.011228 Set Vref, RX VrefLevel [Byte0]: 45
7956 23:10:00.014012 [Byte1]: 45
7957 23:10:00.018370
7958 23:10:00.018614 Set Vref, RX VrefLevel [Byte0]: 46
7959 23:10:00.021445 [Byte1]: 46
7960 23:10:00.025622
7961 23:10:00.025804 Set Vref, RX VrefLevel [Byte0]: 47
7962 23:10:00.029662 [Byte1]: 47
7963 23:10:00.033631
7964 23:10:00.033713 Set Vref, RX VrefLevel [Byte0]: 48
7965 23:10:00.036827 [Byte1]: 48
7966 23:10:00.040777
7967 23:10:00.040901 Set Vref, RX VrefLevel [Byte0]: 49
7968 23:10:00.044145 [Byte1]: 49
7969 23:10:00.048240
7970 23:10:00.048347 Set Vref, RX VrefLevel [Byte0]: 50
7971 23:10:00.052056 [Byte1]: 50
7972 23:10:00.056595
7973 23:10:00.056679 Set Vref, RX VrefLevel [Byte0]: 51
7974 23:10:00.059569 [Byte1]: 51
7975 23:10:00.063639
7976 23:10:00.063761 Set Vref, RX VrefLevel [Byte0]: 52
7977 23:10:00.067576 [Byte1]: 52
7978 23:10:00.071030
7979 23:10:00.071125 Set Vref, RX VrefLevel [Byte0]: 53
7980 23:10:00.075039 [Byte1]: 53
7981 23:10:00.079377
7982 23:10:00.079563 Set Vref, RX VrefLevel [Byte0]: 54
7983 23:10:00.082868 [Byte1]: 54
7984 23:10:00.086669
7985 23:10:00.086868 Set Vref, RX VrefLevel [Byte0]: 55
7986 23:10:00.090657 [Byte1]: 55
7987 23:10:00.094597
7988 23:10:00.094829 Set Vref, RX VrefLevel [Byte0]: 56
7989 23:10:00.097600 [Byte1]: 56
7990 23:10:00.102069
7991 23:10:00.102318 Set Vref, RX VrefLevel [Byte0]: 57
7992 23:10:00.105532 [Byte1]: 57
7993 23:10:00.109862
7994 23:10:00.110175 Set Vref, RX VrefLevel [Byte0]: 58
7995 23:10:00.112900 [Byte1]: 58
7996 23:10:00.117257
7997 23:10:00.117643 Set Vref, RX VrefLevel [Byte0]: 59
7998 23:10:00.120726 [Byte1]: 59
7999 23:10:00.124974
8000 23:10:00.125391 Set Vref, RX VrefLevel [Byte0]: 60
8001 23:10:00.128208 [Byte1]: 60
8002 23:10:00.132369
8003 23:10:00.132784 Set Vref, RX VrefLevel [Byte0]: 61
8004 23:10:00.135510 [Byte1]: 61
8005 23:10:00.140496
8006 23:10:00.140938 Set Vref, RX VrefLevel [Byte0]: 62
8007 23:10:00.143069 [Byte1]: 62
8008 23:10:00.147405
8009 23:10:00.148002 Set Vref, RX VrefLevel [Byte0]: 63
8010 23:10:00.150811 [Byte1]: 63
8011 23:10:00.155409
8012 23:10:00.155869 Set Vref, RX VrefLevel [Byte0]: 64
8013 23:10:00.158491 [Byte1]: 64
8014 23:10:00.162858
8015 23:10:00.163333 Set Vref, RX VrefLevel [Byte0]: 65
8016 23:10:00.166288 [Byte1]: 65
8017 23:10:00.170858
8018 23:10:00.171349 Set Vref, RX VrefLevel [Byte0]: 66
8019 23:10:00.173668 [Byte1]: 66
8020 23:10:00.177807
8021 23:10:00.178077 Set Vref, RX VrefLevel [Byte0]: 67
8022 23:10:00.181387 [Byte1]: 67
8023 23:10:00.185701
8024 23:10:00.185781 Set Vref, RX VrefLevel [Byte0]: 68
8025 23:10:00.188486 [Byte1]: 68
8026 23:10:00.192889
8027 23:10:00.192969 Set Vref, RX VrefLevel [Byte0]: 69
8028 23:10:00.196744 [Byte1]: 69
8029 23:10:00.200952
8030 23:10:00.201033 Set Vref, RX VrefLevel [Byte0]: 70
8031 23:10:00.204220 [Byte1]: 70
8032 23:10:00.208591
8033 23:10:00.208666 Set Vref, RX VrefLevel [Byte0]: 71
8034 23:10:00.211518 [Byte1]: 71
8035 23:10:00.216782
8036 23:10:00.216855 Set Vref, RX VrefLevel [Byte0]: 72
8037 23:10:00.219635 [Byte1]: 72
8038 23:10:00.223521
8039 23:10:00.223595 Set Vref, RX VrefLevel [Byte0]: 73
8040 23:10:00.227239 [Byte1]: 73
8041 23:10:00.231564
8042 23:10:00.232008 Set Vref, RX VrefLevel [Byte0]: 74
8043 23:10:00.234847 [Byte1]: 74
8044 23:10:00.239801
8045 23:10:00.240205 Set Vref, RX VrefLevel [Byte0]: 75
8046 23:10:00.242508 [Byte1]: 75
8047 23:10:00.246907
8048 23:10:00.247315 Set Vref, RX VrefLevel [Byte0]: 76
8049 23:10:00.250280 [Byte1]: 76
8050 23:10:00.254038
8051 23:10:00.254445 Set Vref, RX VrefLevel [Byte0]: 77
8052 23:10:00.258224 [Byte1]: 77
8053 23:10:00.262489
8054 23:10:00.262908 Set Vref, RX VrefLevel [Byte0]: 78
8055 23:10:00.265364 [Byte1]: 78
8056 23:10:00.269366
8057 23:10:00.269741 Set Vref, RX VrefLevel [Byte0]: 79
8058 23:10:00.272736 [Byte1]: 79
8059 23:10:00.276738
8060 23:10:00.277042 Final RX Vref Byte 0 = 67 to rank0
8061 23:10:00.280195 Final RX Vref Byte 1 = 57 to rank0
8062 23:10:00.283433 Final RX Vref Byte 0 = 67 to rank1
8063 23:10:00.287472 Final RX Vref Byte 1 = 57 to rank1==
8064 23:10:00.290100 Dram Type= 6, Freq= 0, CH_0, rank 0
8065 23:10:00.296308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8066 23:10:00.296568 ==
8067 23:10:00.296767 DQS Delay:
8068 23:10:00.300169 DQS0 = 0, DQS1 = 0
8069 23:10:00.300454 DQM Delay:
8070 23:10:00.300640 DQM0 = 133, DQM1 = 124
8071 23:10:00.303092 DQ Delay:
8072 23:10:00.306454 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
8073 23:10:00.310017 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8074 23:10:00.313186 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
8075 23:10:00.316160 DQ12 =130, DQ13 =128, DQ14 =136, DQ15 =130
8076 23:10:00.316373
8077 23:10:00.316578
8078 23:10:00.316753
8079 23:10:00.319901 [DramC_TX_OE_Calibration] TA2
8080 23:10:00.323001 Original DQ_B0 (3 6) =30, OEN = 27
8081 23:10:00.326294 Original DQ_B1 (3 6) =30, OEN = 27
8082 23:10:00.330125 24, 0x0, End_B0=24 End_B1=24
8083 23:10:00.333043 25, 0x0, End_B0=25 End_B1=25
8084 23:10:00.333247 26, 0x0, End_B0=26 End_B1=26
8085 23:10:00.336006 27, 0x0, End_B0=27 End_B1=27
8086 23:10:00.339269 28, 0x0, End_B0=28 End_B1=28
8087 23:10:00.342674 29, 0x0, End_B0=29 End_B1=29
8088 23:10:00.342901 30, 0x0, End_B0=30 End_B1=30
8089 23:10:00.346143 31, 0x4141, End_B0=30 End_B1=30
8090 23:10:00.349907 Byte0 end_step=30 best_step=27
8091 23:10:00.352821 Byte1 end_step=30 best_step=27
8092 23:10:00.356236 Byte0 TX OE(2T, 0.5T) = (3, 3)
8093 23:10:00.359319 Byte1 TX OE(2T, 0.5T) = (3, 3)
8094 23:10:00.359542
8095 23:10:00.359745
8096 23:10:00.365898 [DQSOSCAuto] RK0, (LSB)MR18= 0x2011, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
8097 23:10:00.369344 CH0 RK0: MR19=303, MR18=2011
8098 23:10:00.375855 CH0_RK0: MR19=0x303, MR18=0x2011, DQSOSC=393, MR23=63, INC=23, DEC=15
8099 23:10:00.376350
8100 23:10:00.378942 ----->DramcWriteLeveling(PI) begin...
8101 23:10:00.379298 ==
8102 23:10:00.382479 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 23:10:00.386142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 23:10:00.386494 ==
8105 23:10:00.389306 Write leveling (Byte 0): 37 => 37
8106 23:10:00.392748 Write leveling (Byte 1): 27 => 27
8107 23:10:00.396048 DramcWriteLeveling(PI) end<-----
8108 23:10:00.396421
8109 23:10:00.396707 ==
8110 23:10:00.399126 Dram Type= 6, Freq= 0, CH_0, rank 1
8111 23:10:00.405608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8112 23:10:00.405972 ==
8113 23:10:00.406258 [Gating] SW mode calibration
8114 23:10:00.415771 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8115 23:10:00.418545 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8116 23:10:00.426006 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8117 23:10:00.428772 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8118 23:10:00.431949 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8119 23:10:00.438597 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8120 23:10:00.441773 1 4 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
8121 23:10:00.445146 1 4 20 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
8122 23:10:00.452188 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8123 23:10:00.455286 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8124 23:10:00.458186 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8125 23:10:00.464861 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8126 23:10:00.468016 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8127 23:10:00.471533 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8128 23:10:00.478599 1 5 16 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 1)
8129 23:10:00.481632 1 5 20 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
8130 23:10:00.484834 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8131 23:10:00.491327 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8132 23:10:00.494797 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8133 23:10:00.498199 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8134 23:10:00.504901 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8135 23:10:00.507815 1 6 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8136 23:10:00.511929 1 6 16 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8137 23:10:00.518031 1 6 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
8138 23:10:00.521257 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8139 23:10:00.524149 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8140 23:10:00.530770 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8141 23:10:00.534545 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8142 23:10:00.537510 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8143 23:10:00.543983 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8144 23:10:00.547071 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8145 23:10:00.550650 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8146 23:10:00.556945 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8147 23:10:00.560762 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 23:10:00.563908 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 23:10:00.571261 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 23:10:00.574282 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 23:10:00.576727 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 23:10:00.583893 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 23:10:00.587399 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8154 23:10:00.589916 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 23:10:00.596713 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 23:10:00.599850 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8157 23:10:00.603476 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8158 23:10:00.609979 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8159 23:10:00.613416 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8160 23:10:00.616540 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8161 23:10:00.623994 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8162 23:10:00.624552 Total UI for P1: 0, mck2ui 16
8163 23:10:00.626335 best dqsien dly found for B0: ( 1, 9, 12)
8164 23:10:00.633217 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8165 23:10:00.637020 Total UI for P1: 0, mck2ui 16
8166 23:10:00.639611 best dqsien dly found for B1: ( 1, 9, 20)
8167 23:10:00.643088 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8168 23:10:00.646018 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8169 23:10:00.646476
8170 23:10:00.649793 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8171 23:10:00.653092 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8172 23:10:00.656581 [Gating] SW calibration Done
8173 23:10:00.657143 ==
8174 23:10:00.659620 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 23:10:00.663232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 23:10:00.665959 ==
8177 23:10:00.666522 RX Vref Scan: 0
8178 23:10:00.666893
8179 23:10:00.669312 RX Vref 0 -> 0, step: 1
8180 23:10:00.669774
8181 23:10:00.670137 RX Delay 0 -> 252, step: 8
8182 23:10:00.676193 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8183 23:10:00.679778 iDelay=200, Bit 1, Center 139 (80 ~ 199) 120
8184 23:10:00.682860 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8185 23:10:00.686592 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8186 23:10:00.692496 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8187 23:10:00.695390 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8188 23:10:00.699250 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8189 23:10:00.702001 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8190 23:10:00.706028 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8191 23:10:00.712306 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8192 23:10:00.715995 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8193 23:10:00.718829 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8194 23:10:00.721794 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8195 23:10:00.725438 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8196 23:10:00.732151 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8197 23:10:00.735388 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8198 23:10:00.736160 ==
8199 23:10:00.738555 Dram Type= 6, Freq= 0, CH_0, rank 1
8200 23:10:00.741756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8201 23:10:00.742225 ==
8202 23:10:00.745438 DQS Delay:
8203 23:10:00.746333 DQS0 = 0, DQS1 = 0
8204 23:10:00.746745 DQM Delay:
8205 23:10:00.748276 DQM0 = 133, DQM1 = 128
8206 23:10:00.748741 DQ Delay:
8207 23:10:00.751928 DQ0 =131, DQ1 =139, DQ2 =127, DQ3 =127
8208 23:10:00.758176 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8209 23:10:00.761800 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8210 23:10:00.764509 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8211 23:10:00.765001
8212 23:10:00.765370
8213 23:10:00.765793 ==
8214 23:10:00.768145 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 23:10:00.771440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 23:10:00.771955 ==
8217 23:10:00.772329
8218 23:10:00.772676
8219 23:10:00.774837 TX Vref Scan disable
8220 23:10:00.778181 == TX Byte 0 ==
8221 23:10:00.781256 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8222 23:10:00.784442 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8223 23:10:00.788525 == TX Byte 1 ==
8224 23:10:00.791249 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8225 23:10:00.794457 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8226 23:10:00.794878 ==
8227 23:10:00.797777 Dram Type= 6, Freq= 0, CH_0, rank 1
8228 23:10:00.801489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8229 23:10:00.804220 ==
8230 23:10:00.817213
8231 23:10:00.820149 TX Vref early break, caculate TX vref
8232 23:10:00.823276 TX Vref=16, minBit 0, minWin=23, winSum=377
8233 23:10:00.826740 TX Vref=18, minBit 1, minWin=22, winSum=384
8234 23:10:00.829608 TX Vref=20, minBit 1, minWin=23, winSum=394
8235 23:10:00.833022 TX Vref=22, minBit 1, minWin=24, winSum=403
8236 23:10:00.836975 TX Vref=24, minBit 3, minWin=24, winSum=410
8237 23:10:00.843652 TX Vref=26, minBit 4, minWin=24, winSum=411
8238 23:10:00.846540 TX Vref=28, minBit 4, minWin=24, winSum=408
8239 23:10:00.850073 TX Vref=30, minBit 2, minWin=24, winSum=403
8240 23:10:00.853650 TX Vref=32, minBit 0, minWin=24, winSum=393
8241 23:10:00.856597 TX Vref=34, minBit 12, minWin=23, winSum=389
8242 23:10:00.862844 [TxChooseVref] Worse bit 4, Min win 24, Win sum 411, Final Vref 26
8243 23:10:00.863361
8244 23:10:00.866607 Final TX Range 0 Vref 26
8245 23:10:00.867125
8246 23:10:00.867457 ==
8247 23:10:00.869724 Dram Type= 6, Freq= 0, CH_0, rank 1
8248 23:10:00.873108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8249 23:10:00.873532 ==
8250 23:10:00.873866
8251 23:10:00.874192
8252 23:10:00.876294 TX Vref Scan disable
8253 23:10:00.883041 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8254 23:10:00.883564 == TX Byte 0 ==
8255 23:10:00.886429 u2DelayCellOfst[0]=11 cells (3 PI)
8256 23:10:00.889560 u2DelayCellOfst[1]=14 cells (4 PI)
8257 23:10:00.892825 u2DelayCellOfst[2]=11 cells (3 PI)
8258 23:10:00.896234 u2DelayCellOfst[3]=11 cells (3 PI)
8259 23:10:00.899184 u2DelayCellOfst[4]=11 cells (3 PI)
8260 23:10:00.902515 u2DelayCellOfst[5]=0 cells (0 PI)
8261 23:10:00.906716 u2DelayCellOfst[6]=18 cells (5 PI)
8262 23:10:00.909612 u2DelayCellOfst[7]=18 cells (5 PI)
8263 23:10:00.912405 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8264 23:10:00.915934 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8265 23:10:00.919479 == TX Byte 1 ==
8266 23:10:00.922461 u2DelayCellOfst[8]=0 cells (0 PI)
8267 23:10:00.925449 u2DelayCellOfst[9]=3 cells (1 PI)
8268 23:10:00.929369 u2DelayCellOfst[10]=7 cells (2 PI)
8269 23:10:00.932320 u2DelayCellOfst[11]=3 cells (1 PI)
8270 23:10:00.932743 u2DelayCellOfst[12]=11 cells (3 PI)
8271 23:10:00.936033 u2DelayCellOfst[13]=11 cells (3 PI)
8272 23:10:00.938946 u2DelayCellOfst[14]=18 cells (5 PI)
8273 23:10:00.942334 u2DelayCellOfst[15]=11 cells (3 PI)
8274 23:10:00.949167 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8275 23:10:00.952308 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8276 23:10:00.952751 DramC Write-DBI on
8277 23:10:00.955757 ==
8278 23:10:00.959261 Dram Type= 6, Freq= 0, CH_0, rank 1
8279 23:10:00.961853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8280 23:10:00.962274 ==
8281 23:10:00.962608
8282 23:10:00.962915
8283 23:10:00.965179 TX Vref Scan disable
8284 23:10:00.965797 == TX Byte 0 ==
8285 23:10:00.972269 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8286 23:10:00.972793 == TX Byte 1 ==
8287 23:10:00.975108 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8288 23:10:00.978573 DramC Write-DBI off
8289 23:10:00.979137
8290 23:10:00.979506 [DATLAT]
8291 23:10:00.982588 Freq=1600, CH0 RK1
8292 23:10:00.983172
8293 23:10:00.983544 DATLAT Default: 0xf
8294 23:10:00.985077 0, 0xFFFF, sum = 0
8295 23:10:00.985548 1, 0xFFFF, sum = 0
8296 23:10:00.988253 2, 0xFFFF, sum = 0
8297 23:10:00.988736 3, 0xFFFF, sum = 0
8298 23:10:00.991791 4, 0xFFFF, sum = 0
8299 23:10:00.992281 5, 0xFFFF, sum = 0
8300 23:10:00.994855 6, 0xFFFF, sum = 0
8301 23:10:00.995324 7, 0xFFFF, sum = 0
8302 23:10:00.998425 8, 0xFFFF, sum = 0
8303 23:10:01.001677 9, 0xFFFF, sum = 0
8304 23:10:01.002104 10, 0xFFFF, sum = 0
8305 23:10:01.005179 11, 0xFFFF, sum = 0
8306 23:10:01.005605 12, 0xFFFF, sum = 0
8307 23:10:01.008039 13, 0xFFFF, sum = 0
8308 23:10:01.008468 14, 0x0, sum = 1
8309 23:10:01.011306 15, 0x0, sum = 2
8310 23:10:01.011777 16, 0x0, sum = 3
8311 23:10:01.014812 17, 0x0, sum = 4
8312 23:10:01.015236 best_step = 15
8313 23:10:01.015567
8314 23:10:01.015934 ==
8315 23:10:01.018670 Dram Type= 6, Freq= 0, CH_0, rank 1
8316 23:10:01.021619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 23:10:01.022041 ==
8318 23:10:01.024722 RX Vref Scan: 0
8319 23:10:01.025139
8320 23:10:01.028916 RX Vref 0 -> 0, step: 1
8321 23:10:01.029438
8322 23:10:01.029774 RX Delay 11 -> 252, step: 4
8323 23:10:01.035848 iDelay=195, Bit 0, Center 126 (75 ~ 178) 104
8324 23:10:01.038685 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8325 23:10:01.042439 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8326 23:10:01.045537 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8327 23:10:01.052086 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8328 23:10:01.054997 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8329 23:10:01.058243 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8330 23:10:01.061449 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8331 23:10:01.065257 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8332 23:10:01.071706 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8333 23:10:01.075015 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8334 23:10:01.078089 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8335 23:10:01.081473 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8336 23:10:01.085014 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8337 23:10:01.091441 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8338 23:10:01.094458 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8339 23:10:01.094886 ==
8340 23:10:01.098366 Dram Type= 6, Freq= 0, CH_0, rank 1
8341 23:10:01.100944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8342 23:10:01.101367 ==
8343 23:10:01.104682 DQS Delay:
8344 23:10:01.105100 DQS0 = 0, DQS1 = 0
8345 23:10:01.107913 DQM Delay:
8346 23:10:01.108433 DQM0 = 130, DQM1 = 125
8347 23:10:01.108773 DQ Delay:
8348 23:10:01.114418 DQ0 =126, DQ1 =134, DQ2 =124, DQ3 =128
8349 23:10:01.117669 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =140
8350 23:10:01.121334 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8351 23:10:01.124086 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8352 23:10:01.124504
8353 23:10:01.124834
8354 23:10:01.125141
8355 23:10:01.127773 [DramC_TX_OE_Calibration] TA2
8356 23:10:01.130782 Original DQ_B0 (3 6) =30, OEN = 27
8357 23:10:01.134541 Original DQ_B1 (3 6) =30, OEN = 27
8358 23:10:01.135072 24, 0x0, End_B0=24 End_B1=24
8359 23:10:01.137463 25, 0x0, End_B0=25 End_B1=25
8360 23:10:01.140726 26, 0x0, End_B0=26 End_B1=26
8361 23:10:01.143875 27, 0x0, End_B0=27 End_B1=27
8362 23:10:01.147743 28, 0x0, End_B0=28 End_B1=28
8363 23:10:01.148165 29, 0x0, End_B0=29 End_B1=29
8364 23:10:01.150528 30, 0x0, End_B0=30 End_B1=30
8365 23:10:01.154104 31, 0x5151, End_B0=30 End_B1=30
8366 23:10:01.157408 Byte0 end_step=30 best_step=27
8367 23:10:01.160904 Byte1 end_step=30 best_step=27
8368 23:10:01.163878 Byte0 TX OE(2T, 0.5T) = (3, 3)
8369 23:10:01.164401 Byte1 TX OE(2T, 0.5T) = (3, 3)
8370 23:10:01.164732
8371 23:10:01.165038
8372 23:10:01.173853 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e02, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8373 23:10:01.176838 CH0 RK1: MR19=303, MR18=1E02
8374 23:10:01.184432 CH0_RK1: MR19=0x303, MR18=0x1E02, DQSOSC=394, MR23=63, INC=23, DEC=15
8375 23:10:01.184998 [RxdqsGatingPostProcess] freq 1600
8376 23:10:01.190353 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8377 23:10:01.193625 best DQS0 dly(2T, 0.5T) = (1, 1)
8378 23:10:01.196599 best DQS1 dly(2T, 0.5T) = (1, 1)
8379 23:10:01.199886 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8380 23:10:01.204399 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8381 23:10:01.206851 best DQS0 dly(2T, 0.5T) = (1, 1)
8382 23:10:01.211379 best DQS1 dly(2T, 0.5T) = (1, 1)
8383 23:10:01.214541 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8384 23:10:01.217717 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8385 23:10:01.220450 Pre-setting of DQS Precalculation
8386 23:10:01.223204 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8387 23:10:01.223664 ==
8388 23:10:01.226882 Dram Type= 6, Freq= 0, CH_1, rank 0
8389 23:10:01.230045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8390 23:10:01.230616 ==
8391 23:10:01.236887 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8392 23:10:01.239953 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8393 23:10:01.246686 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8394 23:10:01.249474 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8395 23:10:01.259839 [CA 0] Center 42 (13~71) winsize 59
8396 23:10:01.263105 [CA 1] Center 42 (12~72) winsize 61
8397 23:10:01.266500 [CA 2] Center 37 (8~66) winsize 59
8398 23:10:01.269660 [CA 3] Center 35 (6~65) winsize 60
8399 23:10:01.272899 [CA 4] Center 37 (8~66) winsize 59
8400 23:10:01.276290 [CA 5] Center 36 (6~66) winsize 61
8401 23:10:01.276928
8402 23:10:01.279352 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8403 23:10:01.279880
8404 23:10:01.282612 [CATrainingPosCal] consider 1 rank data
8405 23:10:01.286598 u2DelayCellTimex100 = 262/100 ps
8406 23:10:01.292856 CA0 delay=42 (13~71),Diff = 7 PI (26 cell)
8407 23:10:01.296070 CA1 delay=42 (12~72),Diff = 7 PI (26 cell)
8408 23:10:01.299828 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8409 23:10:01.302984 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8410 23:10:01.305680 CA4 delay=37 (8~66),Diff = 2 PI (7 cell)
8411 23:10:01.309009 CA5 delay=36 (6~66),Diff = 1 PI (3 cell)
8412 23:10:01.309566
8413 23:10:01.312945 CA PerBit enable=1, Macro0, CA PI delay=35
8414 23:10:01.313500
8415 23:10:01.315411 [CBTSetCACLKResult] CA Dly = 35
8416 23:10:01.319053 CS Dly: 9 (0~40)
8417 23:10:01.322221 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8418 23:10:01.326584 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8419 23:10:01.327210 ==
8420 23:10:01.329122 Dram Type= 6, Freq= 0, CH_1, rank 1
8421 23:10:01.335474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 23:10:01.336083 ==
8423 23:10:01.338469 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8424 23:10:01.345479 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8425 23:10:01.348894 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8426 23:10:01.355469 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8427 23:10:01.362996 [CA 0] Center 41 (12~71) winsize 60
8428 23:10:01.367063 [CA 1] Center 42 (13~72) winsize 60
8429 23:10:01.369611 [CA 2] Center 37 (8~67) winsize 60
8430 23:10:01.372551 [CA 3] Center 37 (8~66) winsize 59
8431 23:10:01.376368 [CA 4] Center 37 (8~67) winsize 60
8432 23:10:01.379368 [CA 5] Center 36 (7~66) winsize 60
8433 23:10:01.379871
8434 23:10:01.382535 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8435 23:10:01.383002
8436 23:10:01.389509 [CATrainingPosCal] consider 2 rank data
8437 23:10:01.390072 u2DelayCellTimex100 = 262/100 ps
8438 23:10:01.395839 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8439 23:10:01.398950 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8440 23:10:01.402364 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8441 23:10:01.405683 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8442 23:10:01.408744 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8443 23:10:01.412186 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8444 23:10:01.412654
8445 23:10:01.415377 CA PerBit enable=1, Macro0, CA PI delay=36
8446 23:10:01.415985
8447 23:10:01.418568 [CBTSetCACLKResult] CA Dly = 36
8448 23:10:01.422179 CS Dly: 10 (0~43)
8449 23:10:01.425488 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8450 23:10:01.428679 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8451 23:10:01.429145
8452 23:10:01.432487 ----->DramcWriteLeveling(PI) begin...
8453 23:10:01.432959 ==
8454 23:10:01.435245 Dram Type= 6, Freq= 0, CH_1, rank 0
8455 23:10:01.441954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8456 23:10:01.442620 ==
8457 23:10:01.445454 Write leveling (Byte 0): 23 => 23
8458 23:10:01.448272 Write leveling (Byte 1): 28 => 28
8459 23:10:01.451789 DramcWriteLeveling(PI) end<-----
8460 23:10:01.452254
8461 23:10:01.452625 ==
8462 23:10:01.454854 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 23:10:01.458746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 23:10:01.459217 ==
8465 23:10:01.461602 [Gating] SW mode calibration
8466 23:10:01.468348 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8467 23:10:01.475035 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8468 23:10:01.478551 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8469 23:10:01.481448 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8470 23:10:01.488226 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8471 23:10:01.492142 1 4 12 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
8472 23:10:01.494253 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8473 23:10:01.501229 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8474 23:10:01.504253 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8475 23:10:01.507965 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8476 23:10:01.514206 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8477 23:10:01.518167 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8478 23:10:01.520496 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8479 23:10:01.527933 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8480 23:10:01.530932 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8481 23:10:01.534523 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8482 23:10:01.540605 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8483 23:10:01.544390 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8484 23:10:01.547117 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8485 23:10:01.553985 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8486 23:10:01.557258 1 6 8 | B1->B0 | 2424 4040 | 0 0 | (0 0) (0 0)
8487 23:10:01.560337 1 6 12 | B1->B0 | 3837 4646 | 1 0 | (1 1) (0 0)
8488 23:10:01.567184 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8489 23:10:01.569924 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8490 23:10:01.573669 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8491 23:10:01.579856 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8492 23:10:01.583171 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8493 23:10:01.586614 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8494 23:10:01.593513 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8495 23:10:01.596456 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8496 23:10:01.599828 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8497 23:10:01.606282 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8498 23:10:01.609234 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8499 23:10:01.613038 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 23:10:01.619487 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 23:10:01.622833 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 23:10:01.626390 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 23:10:01.632706 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 23:10:01.636357 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 23:10:01.639478 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 23:10:01.645745 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 23:10:01.649256 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 23:10:01.652215 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 23:10:01.658775 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 23:10:01.662321 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8511 23:10:01.665417 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8512 23:10:01.672242 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8513 23:10:01.672750 Total UI for P1: 0, mck2ui 16
8514 23:10:01.678943 best dqsien dly found for B0: ( 1, 9, 10)
8515 23:10:01.682492 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8516 23:10:01.685173 Total UI for P1: 0, mck2ui 16
8517 23:10:01.688931 best dqsien dly found for B1: ( 1, 9, 14)
8518 23:10:01.692139 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8519 23:10:01.695155 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8520 23:10:01.695618
8521 23:10:01.698676 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8522 23:10:01.701573 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8523 23:10:01.705227 [Gating] SW calibration Done
8524 23:10:01.705793 ==
8525 23:10:01.708480 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 23:10:01.715344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 23:10:01.715905 ==
8528 23:10:01.716254 RX Vref Scan: 0
8529 23:10:01.716567
8530 23:10:01.718635 RX Vref 0 -> 0, step: 1
8531 23:10:01.719197
8532 23:10:01.722320 RX Delay 0 -> 252, step: 8
8533 23:10:01.725644 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8534 23:10:01.728571 iDelay=208, Bit 1, Center 135 (88 ~ 183) 96
8535 23:10:01.732060 iDelay=208, Bit 2, Center 131 (80 ~ 183) 104
8536 23:10:01.735045 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8537 23:10:01.741629 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8538 23:10:01.745125 iDelay=208, Bit 5, Center 155 (104 ~ 207) 104
8539 23:10:01.748510 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8540 23:10:01.751727 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8541 23:10:01.754789 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8542 23:10:01.761151 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8543 23:10:01.764633 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8544 23:10:01.767957 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8545 23:10:01.771620 iDelay=208, Bit 12, Center 139 (88 ~ 191) 104
8546 23:10:01.777868 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8547 23:10:01.781255 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8548 23:10:01.784303 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8549 23:10:01.784769 ==
8550 23:10:01.787865 Dram Type= 6, Freq= 0, CH_1, rank 0
8551 23:10:01.791375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8552 23:10:01.792113 ==
8553 23:10:01.794190 DQS Delay:
8554 23:10:01.794776 DQS0 = 0, DQS1 = 0
8555 23:10:01.797781 DQM Delay:
8556 23:10:01.798334 DQM0 = 140, DQM1 = 130
8557 23:10:01.798703 DQ Delay:
8558 23:10:01.804604 DQ0 =143, DQ1 =135, DQ2 =131, DQ3 =139
8559 23:10:01.807517 DQ4 =135, DQ5 =155, DQ6 =147, DQ7 =135
8560 23:10:01.810937 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =123
8561 23:10:01.814410 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8562 23:10:01.814879
8563 23:10:01.815249
8564 23:10:01.815590 ==
8565 23:10:01.817602 Dram Type= 6, Freq= 0, CH_1, rank 0
8566 23:10:01.820453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8567 23:10:01.820927 ==
8568 23:10:01.821296
8569 23:10:01.821638
8570 23:10:01.823843 TX Vref Scan disable
8571 23:10:01.826989 == TX Byte 0 ==
8572 23:10:01.830508 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8573 23:10:01.833923 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8574 23:10:01.837417 == TX Byte 1 ==
8575 23:10:01.841228 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8576 23:10:01.843427 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8577 23:10:01.843900 ==
8578 23:10:01.847016 Dram Type= 6, Freq= 0, CH_1, rank 0
8579 23:10:01.853701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8580 23:10:01.854127 ==
8581 23:10:01.865085
8582 23:10:01.868638 TX Vref early break, caculate TX vref
8583 23:10:01.872344 TX Vref=16, minBit 0, minWin=22, winSum=373
8584 23:10:01.875100 TX Vref=18, minBit 0, minWin=23, winSum=385
8585 23:10:01.878159 TX Vref=20, minBit 0, minWin=23, winSum=392
8586 23:10:01.881876 TX Vref=22, minBit 0, minWin=23, winSum=402
8587 23:10:01.885141 TX Vref=24, minBit 0, minWin=24, winSum=409
8588 23:10:01.892149 TX Vref=26, minBit 5, minWin=24, winSum=415
8589 23:10:01.895177 TX Vref=28, minBit 1, minWin=24, winSum=419
8590 23:10:01.899384 TX Vref=30, minBit 0, minWin=24, winSum=411
8591 23:10:01.901808 TX Vref=32, minBit 0, minWin=23, winSum=401
8592 23:10:01.904862 TX Vref=34, minBit 1, minWin=22, winSum=392
8593 23:10:01.911555 [TxChooseVref] Worse bit 1, Min win 24, Win sum 419, Final Vref 28
8594 23:10:01.912048
8595 23:10:01.914658 Final TX Range 0 Vref 28
8596 23:10:01.915074
8597 23:10:01.915401 ==
8598 23:10:01.917876 Dram Type= 6, Freq= 0, CH_1, rank 0
8599 23:10:01.921831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8600 23:10:01.922259 ==
8601 23:10:01.922598
8602 23:10:01.922910
8603 23:10:01.924738 TX Vref Scan disable
8604 23:10:01.931018 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8605 23:10:01.931441 == TX Byte 0 ==
8606 23:10:01.934402 u2DelayCellOfst[0]=18 cells (5 PI)
8607 23:10:01.937697 u2DelayCellOfst[1]=11 cells (3 PI)
8608 23:10:01.940737 u2DelayCellOfst[2]=0 cells (0 PI)
8609 23:10:01.944182 u2DelayCellOfst[3]=3 cells (1 PI)
8610 23:10:01.947942 u2DelayCellOfst[4]=7 cells (2 PI)
8611 23:10:01.951475 u2DelayCellOfst[5]=18 cells (5 PI)
8612 23:10:01.954458 u2DelayCellOfst[6]=18 cells (5 PI)
8613 23:10:01.957493 u2DelayCellOfst[7]=3 cells (1 PI)
8614 23:10:01.960848 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8615 23:10:01.964075 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8616 23:10:01.967220 == TX Byte 1 ==
8617 23:10:01.970852 u2DelayCellOfst[8]=0 cells (0 PI)
8618 23:10:01.971277 u2DelayCellOfst[9]=3 cells (1 PI)
8619 23:10:01.974330 u2DelayCellOfst[10]=11 cells (3 PI)
8620 23:10:01.977392 u2DelayCellOfst[11]=3 cells (1 PI)
8621 23:10:01.980659 u2DelayCellOfst[12]=14 cells (4 PI)
8622 23:10:01.984403 u2DelayCellOfst[13]=18 cells (5 PI)
8623 23:10:01.987313 u2DelayCellOfst[14]=18 cells (5 PI)
8624 23:10:01.991121 u2DelayCellOfst[15]=18 cells (5 PI)
8625 23:10:01.997384 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8626 23:10:02.000385 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8627 23:10:02.000811 DramC Write-DBI on
8628 23:10:02.001186 ==
8629 23:10:02.003881 Dram Type= 6, Freq= 0, CH_1, rank 0
8630 23:10:02.010700 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8631 23:10:02.011124 ==
8632 23:10:02.011458
8633 23:10:02.011786
8634 23:10:02.012086 TX Vref Scan disable
8635 23:10:02.015052 == TX Byte 0 ==
8636 23:10:02.018265 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8637 23:10:02.021925 == TX Byte 1 ==
8638 23:10:02.024256 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8639 23:10:02.027497 DramC Write-DBI off
8640 23:10:02.027945
8641 23:10:02.028278 [DATLAT]
8642 23:10:02.028588 Freq=1600, CH1 RK0
8643 23:10:02.028887
8644 23:10:02.031148 DATLAT Default: 0xf
8645 23:10:02.031565 0, 0xFFFF, sum = 0
8646 23:10:02.034039 1, 0xFFFF, sum = 0
8647 23:10:02.037841 2, 0xFFFF, sum = 0
8648 23:10:02.038267 3, 0xFFFF, sum = 0
8649 23:10:02.040847 4, 0xFFFF, sum = 0
8650 23:10:02.041271 5, 0xFFFF, sum = 0
8651 23:10:02.044830 6, 0xFFFF, sum = 0
8652 23:10:02.045255 7, 0xFFFF, sum = 0
8653 23:10:02.047661 8, 0xFFFF, sum = 0
8654 23:10:02.048174 9, 0xFFFF, sum = 0
8655 23:10:02.050862 10, 0xFFFF, sum = 0
8656 23:10:02.051283 11, 0xFFFF, sum = 0
8657 23:10:02.054399 12, 0xFFFF, sum = 0
8658 23:10:02.054873 13, 0xFFFF, sum = 0
8659 23:10:02.057396 14, 0x0, sum = 1
8660 23:10:02.057932 15, 0x0, sum = 2
8661 23:10:02.060818 16, 0x0, sum = 3
8662 23:10:02.061244 17, 0x0, sum = 4
8663 23:10:02.064360 best_step = 15
8664 23:10:02.064778
8665 23:10:02.065111 ==
8666 23:10:02.067466 Dram Type= 6, Freq= 0, CH_1, rank 0
8667 23:10:02.070859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8668 23:10:02.071385 ==
8669 23:10:02.073951 RX Vref Scan: 1
8670 23:10:02.074536
8671 23:10:02.074870 Set Vref Range= 24 -> 127
8672 23:10:02.075178
8673 23:10:02.077106 RX Vref 24 -> 127, step: 1
8674 23:10:02.077510
8675 23:10:02.080277 RX Delay 19 -> 252, step: 4
8676 23:10:02.080693
8677 23:10:02.084009 Set Vref, RX VrefLevel [Byte0]: 24
8678 23:10:02.086900 [Byte1]: 24
8679 23:10:02.087488
8680 23:10:02.090321 Set Vref, RX VrefLevel [Byte0]: 25
8681 23:10:02.093581 [Byte1]: 25
8682 23:10:02.097244
8683 23:10:02.097771 Set Vref, RX VrefLevel [Byte0]: 26
8684 23:10:02.100888 [Byte1]: 26
8685 23:10:02.104726
8686 23:10:02.105394 Set Vref, RX VrefLevel [Byte0]: 27
8687 23:10:02.108177 [Byte1]: 27
8688 23:10:02.112578
8689 23:10:02.113144 Set Vref, RX VrefLevel [Byte0]: 28
8690 23:10:02.116062 [Byte1]: 28
8691 23:10:02.120171
8692 23:10:02.120733 Set Vref, RX VrefLevel [Byte0]: 29
8693 23:10:02.123190 [Byte1]: 29
8694 23:10:02.127887
8695 23:10:02.128352 Set Vref, RX VrefLevel [Byte0]: 30
8696 23:10:02.130930 [Byte1]: 30
8697 23:10:02.135097
8698 23:10:02.135562 Set Vref, RX VrefLevel [Byte0]: 31
8699 23:10:02.138419 [Byte1]: 31
8700 23:10:02.143170
8701 23:10:02.143595 Set Vref, RX VrefLevel [Byte0]: 32
8702 23:10:02.145971 [Byte1]: 32
8703 23:10:02.150559
8704 23:10:02.151054 Set Vref, RX VrefLevel [Byte0]: 33
8705 23:10:02.153988 [Byte1]: 33
8706 23:10:02.157655
8707 23:10:02.158076 Set Vref, RX VrefLevel [Byte0]: 34
8708 23:10:02.161264 [Byte1]: 34
8709 23:10:02.165705
8710 23:10:02.166236 Set Vref, RX VrefLevel [Byte0]: 35
8711 23:10:02.169200 [Byte1]: 35
8712 23:10:02.173115
8713 23:10:02.173600 Set Vref, RX VrefLevel [Byte0]: 36
8714 23:10:02.176433 [Byte1]: 36
8715 23:10:02.180752
8716 23:10:02.181171 Set Vref, RX VrefLevel [Byte0]: 37
8717 23:10:02.184040 [Byte1]: 37
8718 23:10:02.188636
8719 23:10:02.189057 Set Vref, RX VrefLevel [Byte0]: 38
8720 23:10:02.191336 [Byte1]: 38
8721 23:10:02.195737
8722 23:10:02.196162 Set Vref, RX VrefLevel [Byte0]: 39
8723 23:10:02.198997 [Byte1]: 39
8724 23:10:02.203472
8725 23:10:02.203943 Set Vref, RX VrefLevel [Byte0]: 40
8726 23:10:02.206898 [Byte1]: 40
8727 23:10:02.211151
8728 23:10:02.211746 Set Vref, RX VrefLevel [Byte0]: 41
8729 23:10:02.217322 [Byte1]: 41
8730 23:10:02.217870
8731 23:10:02.220573 Set Vref, RX VrefLevel [Byte0]: 42
8732 23:10:02.224118 [Byte1]: 42
8733 23:10:02.224555
8734 23:10:02.227454 Set Vref, RX VrefLevel [Byte0]: 43
8735 23:10:02.230148 [Byte1]: 43
8736 23:10:02.230570
8737 23:10:02.233398 Set Vref, RX VrefLevel [Byte0]: 44
8738 23:10:02.236904 [Byte1]: 44
8739 23:10:02.241674
8740 23:10:02.242197 Set Vref, RX VrefLevel [Byte0]: 45
8741 23:10:02.244252 [Byte1]: 45
8742 23:10:02.248830
8743 23:10:02.249249 Set Vref, RX VrefLevel [Byte0]: 46
8744 23:10:02.252187 [Byte1]: 46
8745 23:10:02.256303
8746 23:10:02.256723 Set Vref, RX VrefLevel [Byte0]: 47
8747 23:10:02.259218 [Byte1]: 47
8748 23:10:02.264027
8749 23:10:02.264451 Set Vref, RX VrefLevel [Byte0]: 48
8750 23:10:02.266933 [Byte1]: 48
8751 23:10:02.271571
8752 23:10:02.272098 Set Vref, RX VrefLevel [Byte0]: 49
8753 23:10:02.274671 [Byte1]: 49
8754 23:10:02.279765
8755 23:10:02.280282 Set Vref, RX VrefLevel [Byte0]: 50
8756 23:10:02.282119 [Byte1]: 50
8757 23:10:02.286469
8758 23:10:02.286882 Set Vref, RX VrefLevel [Byte0]: 51
8759 23:10:02.289761 [Byte1]: 51
8760 23:10:02.294359
8761 23:10:02.294790 Set Vref, RX VrefLevel [Byte0]: 52
8762 23:10:02.297049 [Byte1]: 52
8763 23:10:02.301803
8764 23:10:02.302221 Set Vref, RX VrefLevel [Byte0]: 53
8765 23:10:02.304937 [Byte1]: 53
8766 23:10:02.309382
8767 23:10:02.309816 Set Vref, RX VrefLevel [Byte0]: 54
8768 23:10:02.315985 [Byte1]: 54
8769 23:10:02.316514
8770 23:10:02.318672 Set Vref, RX VrefLevel [Byte0]: 55
8771 23:10:02.322424 [Byte1]: 55
8772 23:10:02.322885
8773 23:10:02.325328 Set Vref, RX VrefLevel [Byte0]: 56
8774 23:10:02.329301 [Byte1]: 56
8775 23:10:02.329944
8776 23:10:02.332359 Set Vref, RX VrefLevel [Byte0]: 57
8777 23:10:02.335850 [Byte1]: 57
8778 23:10:02.339887
8779 23:10:02.340358 Set Vref, RX VrefLevel [Byte0]: 58
8780 23:10:02.342960 [Byte1]: 58
8781 23:10:02.347129
8782 23:10:02.347811 Set Vref, RX VrefLevel [Byte0]: 59
8783 23:10:02.350139 [Byte1]: 59
8784 23:10:02.354414
8785 23:10:02.354850 Set Vref, RX VrefLevel [Byte0]: 60
8786 23:10:02.358742 [Byte1]: 60
8787 23:10:02.362681
8788 23:10:02.363142 Set Vref, RX VrefLevel [Byte0]: 61
8789 23:10:02.365805 [Byte1]: 61
8790 23:10:02.369714
8791 23:10:02.370187 Set Vref, RX VrefLevel [Byte0]: 62
8792 23:10:02.373371 [Byte1]: 62
8793 23:10:02.377314
8794 23:10:02.377730 Set Vref, RX VrefLevel [Byte0]: 63
8795 23:10:02.380724 [Byte1]: 63
8796 23:10:02.385459
8797 23:10:02.385944 Set Vref, RX VrefLevel [Byte0]: 64
8798 23:10:02.389066 [Byte1]: 64
8799 23:10:02.392580
8800 23:10:02.392996 Set Vref, RX VrefLevel [Byte0]: 65
8801 23:10:02.395873 [Byte1]: 65
8802 23:10:02.400236
8803 23:10:02.400650 Set Vref, RX VrefLevel [Byte0]: 66
8804 23:10:02.403404 [Byte1]: 66
8805 23:10:02.408006
8806 23:10:02.408425 Set Vref, RX VrefLevel [Byte0]: 67
8807 23:10:02.410831 [Byte1]: 67
8808 23:10:02.415375
8809 23:10:02.415962 Set Vref, RX VrefLevel [Byte0]: 68
8810 23:10:02.418321 [Byte1]: 68
8811 23:10:02.422749
8812 23:10:02.423169 Set Vref, RX VrefLevel [Byte0]: 69
8813 23:10:02.426255 [Byte1]: 69
8814 23:10:02.430550
8815 23:10:02.430980 Set Vref, RX VrefLevel [Byte0]: 70
8816 23:10:02.434029 [Byte1]: 70
8817 23:10:02.437740
8818 23:10:02.438171 Set Vref, RX VrefLevel [Byte0]: 71
8819 23:10:02.441189 [Byte1]: 71
8820 23:10:02.446305
8821 23:10:02.446825 Set Vref, RX VrefLevel [Byte0]: 72
8822 23:10:02.448763 [Byte1]: 72
8823 23:10:02.453164
8824 23:10:02.453740 Set Vref, RX VrefLevel [Byte0]: 73
8825 23:10:02.456549 [Byte1]: 73
8826 23:10:02.460794
8827 23:10:02.461209 Set Vref, RX VrefLevel [Byte0]: 74
8828 23:10:02.463794 [Byte1]: 74
8829 23:10:02.468043
8830 23:10:02.468461 Set Vref, RX VrefLevel [Byte0]: 75
8831 23:10:02.472177 [Byte1]: 75
8832 23:10:02.475721
8833 23:10:02.476184 Set Vref, RX VrefLevel [Byte0]: 76
8834 23:10:02.479056 [Byte1]: 76
8835 23:10:02.484229
8836 23:10:02.484789 Set Vref, RX VrefLevel [Byte0]: 77
8837 23:10:02.487196 [Byte1]: 77
8838 23:10:02.490735
8839 23:10:02.491194 Set Vref, RX VrefLevel [Byte0]: 78
8840 23:10:02.494730 [Byte1]: 78
8841 23:10:02.499095
8842 23:10:02.499653 Final RX Vref Byte 0 = 54 to rank0
8843 23:10:02.502249 Final RX Vref Byte 1 = 60 to rank0
8844 23:10:02.505258 Final RX Vref Byte 0 = 54 to rank1
8845 23:10:02.508241 Final RX Vref Byte 1 = 60 to rank1==
8846 23:10:02.512091 Dram Type= 6, Freq= 0, CH_1, rank 0
8847 23:10:02.518272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8848 23:10:02.518841 ==
8849 23:10:02.519209 DQS Delay:
8850 23:10:02.521879 DQS0 = 0, DQS1 = 0
8851 23:10:02.522447 DQM Delay:
8852 23:10:02.522833 DQM0 = 135, DQM1 = 128
8853 23:10:02.524927 DQ Delay:
8854 23:10:02.529334 DQ0 =142, DQ1 =128, DQ2 =126, DQ3 =132
8855 23:10:02.531345 DQ4 =132, DQ5 =148, DQ6 =146, DQ7 =130
8856 23:10:02.535136 DQ8 =116, DQ9 =116, DQ10 =130, DQ11 =116
8857 23:10:02.538305 DQ12 =138, DQ13 =136, DQ14 =138, DQ15 =138
8858 23:10:02.538871
8859 23:10:02.539234
8860 23:10:02.539572
8861 23:10:02.541860 [DramC_TX_OE_Calibration] TA2
8862 23:10:02.545107 Original DQ_B0 (3 6) =30, OEN = 27
8863 23:10:02.548615 Original DQ_B1 (3 6) =30, OEN = 27
8864 23:10:02.551551 24, 0x0, End_B0=24 End_B1=24
8865 23:10:02.554447 25, 0x0, End_B0=25 End_B1=25
8866 23:10:02.554917 26, 0x0, End_B0=26 End_B1=26
8867 23:10:02.558479 27, 0x0, End_B0=27 End_B1=27
8868 23:10:02.561101 28, 0x0, End_B0=28 End_B1=28
8869 23:10:02.564458 29, 0x0, End_B0=29 End_B1=29
8870 23:10:02.565033 30, 0x0, End_B0=30 End_B1=30
8871 23:10:02.567999 31, 0x4141, End_B0=30 End_B1=30
8872 23:10:02.571586 Byte0 end_step=30 best_step=27
8873 23:10:02.574689 Byte1 end_step=30 best_step=27
8874 23:10:02.578020 Byte0 TX OE(2T, 0.5T) = (3, 3)
8875 23:10:02.580904 Byte1 TX OE(2T, 0.5T) = (3, 3)
8876 23:10:02.581382
8877 23:10:02.581746
8878 23:10:02.588655 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
8879 23:10:02.592041 CH1 RK0: MR19=303, MR18=1A10
8880 23:10:02.597930 CH1_RK0: MR19=0x303, MR18=0x1A10, DQSOSC=396, MR23=63, INC=23, DEC=15
8881 23:10:02.598402
8882 23:10:02.601062 ----->DramcWriteLeveling(PI) begin...
8883 23:10:02.601634 ==
8884 23:10:02.604322 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 23:10:02.607301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 23:10:02.607814 ==
8887 23:10:02.611214 Write leveling (Byte 0): 23 => 23
8888 23:10:02.614491 Write leveling (Byte 1): 29 => 29
8889 23:10:02.617730 DramcWriteLeveling(PI) end<-----
8890 23:10:02.618294
8891 23:10:02.618662 ==
8892 23:10:02.621389 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 23:10:02.624302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 23:10:02.627571 ==
8895 23:10:02.628068 [Gating] SW mode calibration
8896 23:10:02.637352 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8897 23:10:02.640821 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8898 23:10:02.643945 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8899 23:10:02.650823 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8900 23:10:02.653860 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8901 23:10:02.657350 1 4 12 | B1->B0 | 3332 2424 | 1 0 | (0 0) (0 0)
8902 23:10:02.663438 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8903 23:10:02.666967 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8904 23:10:02.670587 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8905 23:10:02.677036 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8906 23:10:02.679981 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8907 23:10:02.683619 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8908 23:10:02.690377 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8909 23:10:02.693808 1 5 12 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 0)
8910 23:10:02.696682 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8911 23:10:02.703204 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8912 23:10:02.706027 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8913 23:10:02.709699 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8914 23:10:02.715799 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8915 23:10:02.719555 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8916 23:10:02.723634 1 6 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8917 23:10:02.729479 1 6 12 | B1->B0 | 4241 2f2f | 1 0 | (0 0) (0 0)
8918 23:10:02.732404 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8919 23:10:02.736191 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8920 23:10:02.742623 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8921 23:10:02.746020 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8922 23:10:02.752705 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8923 23:10:02.755547 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8924 23:10:02.758764 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8925 23:10:02.765154 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8926 23:10:02.768636 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8927 23:10:02.771579 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8928 23:10:02.778330 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8929 23:10:02.782063 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8930 23:10:02.785183 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8931 23:10:02.792022 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8932 23:10:02.795049 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8933 23:10:02.798289 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8934 23:10:02.804557 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8935 23:10:02.807898 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8936 23:10:02.811238 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8937 23:10:02.817673 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8938 23:10:02.821681 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8939 23:10:02.824894 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8940 23:10:02.831027 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8941 23:10:02.834587 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8942 23:10:02.837896 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8943 23:10:02.840721 Total UI for P1: 0, mck2ui 16
8944 23:10:02.844335 best dqsien dly found for B0: ( 1, 9, 10)
8945 23:10:02.847196 Total UI for P1: 0, mck2ui 16
8946 23:10:02.850394 best dqsien dly found for B1: ( 1, 9, 12)
8947 23:10:02.853847 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8948 23:10:02.857270 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8949 23:10:02.857401
8950 23:10:02.860370 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8951 23:10:02.867041 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8952 23:10:02.867144 [Gating] SW calibration Done
8953 23:10:02.870046 ==
8954 23:10:02.873662 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 23:10:02.876676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 23:10:02.876761 ==
8957 23:10:02.876828 RX Vref Scan: 0
8958 23:10:02.876890
8959 23:10:02.880099 RX Vref 0 -> 0, step: 1
8960 23:10:02.880181
8961 23:10:02.883373 RX Delay 0 -> 252, step: 8
8962 23:10:02.886524 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8963 23:10:02.889930 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8964 23:10:02.893165 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8965 23:10:02.900327 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8966 23:10:02.903255 iDelay=208, Bit 4, Center 135 (72 ~ 199) 128
8967 23:10:02.906822 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8968 23:10:02.910818 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8969 23:10:02.913056 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8970 23:10:02.919706 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8971 23:10:02.923046 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8972 23:10:02.926210 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8973 23:10:02.929633 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8974 23:10:02.936778 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8975 23:10:02.940284 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8976 23:10:02.943157 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8977 23:10:02.946566 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8978 23:10:02.946991 ==
8979 23:10:02.949873 Dram Type= 6, Freq= 0, CH_1, rank 1
8980 23:10:02.956757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8981 23:10:02.957184 ==
8982 23:10:02.957521 DQS Delay:
8983 23:10:02.959706 DQS0 = 0, DQS1 = 0
8984 23:10:02.960138 DQM Delay:
8985 23:10:02.960477 DQM0 = 137, DQM1 = 130
8986 23:10:02.962931 DQ Delay:
8987 23:10:02.966327 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8988 23:10:02.969563 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8989 23:10:02.972899 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =119
8990 23:10:02.976082 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8991 23:10:02.976500
8992 23:10:02.976826
8993 23:10:02.977131 ==
8994 23:10:02.979159 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 23:10:02.986149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 23:10:02.986608 ==
8997 23:10:02.986947
8998 23:10:02.987264
8999 23:10:02.987566 TX Vref Scan disable
9000 23:10:02.989391 == TX Byte 0 ==
9001 23:10:02.992381 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9002 23:10:02.999232 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
9003 23:10:02.999841 == TX Byte 1 ==
9004 23:10:03.002716 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
9005 23:10:03.009126 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9006 23:10:03.009578 ==
9007 23:10:03.012628 Dram Type= 6, Freq= 0, CH_1, rank 1
9008 23:10:03.015641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9009 23:10:03.016103 ==
9010 23:10:03.028682
9011 23:10:03.031583 TX Vref early break, caculate TX vref
9012 23:10:03.034863 TX Vref=16, minBit 0, minWin=23, winSum=381
9013 23:10:03.038321 TX Vref=18, minBit 0, minWin=23, winSum=389
9014 23:10:03.041967 TX Vref=20, minBit 5, minWin=23, winSum=396
9015 23:10:03.045133 TX Vref=22, minBit 0, minWin=24, winSum=406
9016 23:10:03.048135 TX Vref=24, minBit 0, minWin=25, winSum=415
9017 23:10:03.054755 TX Vref=26, minBit 0, minWin=25, winSum=419
9018 23:10:03.058584 TX Vref=28, minBit 0, minWin=25, winSum=420
9019 23:10:03.061954 TX Vref=30, minBit 0, minWin=24, winSum=416
9020 23:10:03.065372 TX Vref=32, minBit 0, minWin=23, winSum=407
9021 23:10:03.068120 TX Vref=34, minBit 0, minWin=23, winSum=398
9022 23:10:03.074648 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
9023 23:10:03.075183
9024 23:10:03.077808 Final TX Range 0 Vref 28
9025 23:10:03.078199
9026 23:10:03.078518 ==
9027 23:10:03.081439 Dram Type= 6, Freq= 0, CH_1, rank 1
9028 23:10:03.084671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9029 23:10:03.085097 ==
9030 23:10:03.085432
9031 23:10:03.085742
9032 23:10:03.087445 TX Vref Scan disable
9033 23:10:03.094929 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
9034 23:10:03.095351 == TX Byte 0 ==
9035 23:10:03.097798 u2DelayCellOfst[0]=22 cells (6 PI)
9036 23:10:03.100733 u2DelayCellOfst[1]=14 cells (4 PI)
9037 23:10:03.104457 u2DelayCellOfst[2]=0 cells (0 PI)
9038 23:10:03.107372 u2DelayCellOfst[3]=7 cells (2 PI)
9039 23:10:03.110910 u2DelayCellOfst[4]=11 cells (3 PI)
9040 23:10:03.114550 u2DelayCellOfst[5]=22 cells (6 PI)
9041 23:10:03.117600 u2DelayCellOfst[6]=22 cells (6 PI)
9042 23:10:03.120520 u2DelayCellOfst[7]=7 cells (2 PI)
9043 23:10:03.124018 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
9044 23:10:03.127598 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
9045 23:10:03.130643 == TX Byte 1 ==
9046 23:10:03.133772 u2DelayCellOfst[8]=0 cells (0 PI)
9047 23:10:03.137698 u2DelayCellOfst[9]=3 cells (1 PI)
9048 23:10:03.140439 u2DelayCellOfst[10]=14 cells (4 PI)
9049 23:10:03.140862 u2DelayCellOfst[11]=3 cells (1 PI)
9050 23:10:03.143916 u2DelayCellOfst[12]=18 cells (5 PI)
9051 23:10:03.147011 u2DelayCellOfst[13]=18 cells (5 PI)
9052 23:10:03.150447 u2DelayCellOfst[14]=18 cells (5 PI)
9053 23:10:03.153937 u2DelayCellOfst[15]=18 cells (5 PI)
9054 23:10:03.160331 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
9055 23:10:03.163793 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9056 23:10:03.164221 DramC Write-DBI on
9057 23:10:03.166964 ==
9058 23:10:03.170207 Dram Type= 6, Freq= 0, CH_1, rank 1
9059 23:10:03.173068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9060 23:10:03.173493 ==
9061 23:10:03.173827
9062 23:10:03.174136
9063 23:10:03.176539 TX Vref Scan disable
9064 23:10:03.176962 == TX Byte 0 ==
9065 23:10:03.182947 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9066 23:10:03.183371 == TX Byte 1 ==
9067 23:10:03.186412 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9068 23:10:03.189844 DramC Write-DBI off
9069 23:10:03.190264
9070 23:10:03.190597 [DATLAT]
9071 23:10:03.193665 Freq=1600, CH1 RK1
9072 23:10:03.194089
9073 23:10:03.194422 DATLAT Default: 0xf
9074 23:10:03.196233 0, 0xFFFF, sum = 0
9075 23:10:03.196708 1, 0xFFFF, sum = 0
9076 23:10:03.200242 2, 0xFFFF, sum = 0
9077 23:10:03.200663 3, 0xFFFF, sum = 0
9078 23:10:03.202971 4, 0xFFFF, sum = 0
9079 23:10:03.206723 5, 0xFFFF, sum = 0
9080 23:10:03.207141 6, 0xFFFF, sum = 0
9081 23:10:03.209440 7, 0xFFFF, sum = 0
9082 23:10:03.209861 8, 0xFFFF, sum = 0
9083 23:10:03.212903 9, 0xFFFF, sum = 0
9084 23:10:03.213345 10, 0xFFFF, sum = 0
9085 23:10:03.216362 11, 0xFFFF, sum = 0
9086 23:10:03.216802 12, 0xFFFF, sum = 0
9087 23:10:03.219234 13, 0xFFFF, sum = 0
9088 23:10:03.219664 14, 0x0, sum = 1
9089 23:10:03.222625 15, 0x0, sum = 2
9090 23:10:03.223054 16, 0x0, sum = 3
9091 23:10:03.226686 17, 0x0, sum = 4
9092 23:10:03.227118 best_step = 15
9093 23:10:03.227456
9094 23:10:03.227820 ==
9095 23:10:03.229520 Dram Type= 6, Freq= 0, CH_1, rank 1
9096 23:10:03.232762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9097 23:10:03.235780 ==
9098 23:10:03.236207 RX Vref Scan: 0
9099 23:10:03.236544
9100 23:10:03.239564 RX Vref 0 -> 0, step: 1
9101 23:10:03.240167
9102 23:10:03.243146 RX Delay 11 -> 252, step: 4
9103 23:10:03.246168 iDelay=203, Bit 0, Center 140 (87 ~ 194) 108
9104 23:10:03.248949 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9105 23:10:03.252148 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9106 23:10:03.259132 iDelay=203, Bit 3, Center 132 (83 ~ 182) 100
9107 23:10:03.262313 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9108 23:10:03.265669 iDelay=203, Bit 5, Center 146 (95 ~ 198) 104
9109 23:10:03.268831 iDelay=203, Bit 6, Center 148 (95 ~ 202) 108
9110 23:10:03.272355 iDelay=203, Bit 7, Center 132 (83 ~ 182) 100
9111 23:10:03.278706 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9112 23:10:03.282437 iDelay=203, Bit 9, Center 114 (59 ~ 170) 112
9113 23:10:03.285667 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9114 23:10:03.288518 iDelay=203, Bit 11, Center 118 (63 ~ 174) 112
9115 23:10:03.291995 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9116 23:10:03.298648 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9117 23:10:03.301887 iDelay=203, Bit 14, Center 132 (75 ~ 190) 116
9118 23:10:03.305218 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9119 23:10:03.305636 ==
9120 23:10:03.308961 Dram Type= 6, Freq= 0, CH_1, rank 1
9121 23:10:03.315240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9122 23:10:03.315739 ==
9123 23:10:03.316077 DQS Delay:
9124 23:10:03.316385 DQS0 = 0, DQS1 = 0
9125 23:10:03.318548 DQM Delay:
9126 23:10:03.318981 DQM0 = 135, DQM1 = 126
9127 23:10:03.321465 DQ Delay:
9128 23:10:03.324831 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =132
9129 23:10:03.327964 DQ4 =134, DQ5 =146, DQ6 =148, DQ7 =132
9130 23:10:03.331428 DQ8 =112, DQ9 =114, DQ10 =126, DQ11 =118
9131 23:10:03.335044 DQ12 =134, DQ13 =134, DQ14 =132, DQ15 =138
9132 23:10:03.335468
9133 23:10:03.335849
9134 23:10:03.336167
9135 23:10:03.338429 [DramC_TX_OE_Calibration] TA2
9136 23:10:03.341265 Original DQ_B0 (3 6) =30, OEN = 27
9137 23:10:03.344735 Original DQ_B1 (3 6) =30, OEN = 27
9138 23:10:03.348285 24, 0x0, End_B0=24 End_B1=24
9139 23:10:03.348716 25, 0x0, End_B0=25 End_B1=25
9140 23:10:03.351704 26, 0x0, End_B0=26 End_B1=26
9141 23:10:03.354722 27, 0x0, End_B0=27 End_B1=27
9142 23:10:03.357763 28, 0x0, End_B0=28 End_B1=28
9143 23:10:03.361415 29, 0x0, End_B0=29 End_B1=29
9144 23:10:03.361856 30, 0x0, End_B0=30 End_B1=30
9145 23:10:03.364221 31, 0x4141, End_B0=30 End_B1=30
9146 23:10:03.367788 Byte0 end_step=30 best_step=27
9147 23:10:03.371356 Byte1 end_step=30 best_step=27
9148 23:10:03.374221 Byte0 TX OE(2T, 0.5T) = (3, 3)
9149 23:10:03.377604 Byte1 TX OE(2T, 0.5T) = (3, 3)
9150 23:10:03.378099
9151 23:10:03.378443
9152 23:10:03.384311 [DQSOSCAuto] RK1, (LSB)MR18= 0xb07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9153 23:10:03.387795 CH1 RK1: MR19=303, MR18=B07
9154 23:10:03.394498 CH1_RK1: MR19=0x303, MR18=0xB07, DQSOSC=404, MR23=63, INC=22, DEC=15
9155 23:10:03.397593 [RxdqsGatingPostProcess] freq 1600
9156 23:10:03.401069 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9157 23:10:03.404014 best DQS0 dly(2T, 0.5T) = (1, 1)
9158 23:10:03.407625 best DQS1 dly(2T, 0.5T) = (1, 1)
9159 23:10:03.410859 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9160 23:10:03.413908 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9161 23:10:03.417625 best DQS0 dly(2T, 0.5T) = (1, 1)
9162 23:10:03.420475 best DQS1 dly(2T, 0.5T) = (1, 1)
9163 23:10:03.423770 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9164 23:10:03.427437 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9165 23:10:03.430885 Pre-setting of DQS Precalculation
9166 23:10:03.433916 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9167 23:10:03.440793 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9168 23:10:03.450519 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9169 23:10:03.450956
9170 23:10:03.451331
9171 23:10:03.454362 [Calibration Summary] 3200 Mbps
9172 23:10:03.454725 CH 0, Rank 0
9173 23:10:03.457466 SW Impedance : PASS
9174 23:10:03.457921 DUTY Scan : NO K
9175 23:10:03.460768 ZQ Calibration : PASS
9176 23:10:03.461250 Jitter Meter : NO K
9177 23:10:03.464064 CBT Training : PASS
9178 23:10:03.467312 Write leveling : PASS
9179 23:10:03.467861 RX DQS gating : PASS
9180 23:10:03.471533 RX DQ/DQS(RDDQC) : PASS
9181 23:10:03.473690 TX DQ/DQS : PASS
9182 23:10:03.474172 RX DATLAT : PASS
9183 23:10:03.477023 RX DQ/DQS(Engine): PASS
9184 23:10:03.480396 TX OE : PASS
9185 23:10:03.480866 All Pass.
9186 23:10:03.481244
9187 23:10:03.481652 CH 0, Rank 1
9188 23:10:03.483537 SW Impedance : PASS
9189 23:10:03.486922 DUTY Scan : NO K
9190 23:10:03.487376 ZQ Calibration : PASS
9191 23:10:03.489781 Jitter Meter : NO K
9192 23:10:03.493440 CBT Training : PASS
9193 23:10:03.493866 Write leveling : PASS
9194 23:10:03.496592 RX DQS gating : PASS
9195 23:10:03.499628 RX DQ/DQS(RDDQC) : PASS
9196 23:10:03.500133 TX DQ/DQS : PASS
9197 23:10:03.503472 RX DATLAT : PASS
9198 23:10:03.506378 RX DQ/DQS(Engine): PASS
9199 23:10:03.506867 TX OE : PASS
9200 23:10:03.509984 All Pass.
9201 23:10:03.510476
9202 23:10:03.510879 CH 1, Rank 0
9203 23:10:03.513068 SW Impedance : PASS
9204 23:10:03.513499 DUTY Scan : NO K
9205 23:10:03.516365 ZQ Calibration : PASS
9206 23:10:03.519879 Jitter Meter : NO K
9207 23:10:03.520425 CBT Training : PASS
9208 23:10:03.522668 Write leveling : PASS
9209 23:10:03.526237 RX DQS gating : PASS
9210 23:10:03.526731 RX DQ/DQS(RDDQC) : PASS
9211 23:10:03.529935 TX DQ/DQS : PASS
9212 23:10:03.530454 RX DATLAT : PASS
9213 23:10:03.532706 RX DQ/DQS(Engine): PASS
9214 23:10:03.536446 TX OE : PASS
9215 23:10:03.536942 All Pass.
9216 23:10:03.537320
9217 23:10:03.537698 CH 1, Rank 1
9218 23:10:03.539470 SW Impedance : PASS
9219 23:10:03.542953 DUTY Scan : NO K
9220 23:10:03.543561 ZQ Calibration : PASS
9221 23:10:03.546384 Jitter Meter : NO K
9222 23:10:03.549834 CBT Training : PASS
9223 23:10:03.550539 Write leveling : PASS
9224 23:10:03.552695 RX DQS gating : PASS
9225 23:10:03.556429 RX DQ/DQS(RDDQC) : PASS
9226 23:10:03.557079 TX DQ/DQS : PASS
9227 23:10:03.559191 RX DATLAT : PASS
9228 23:10:03.562540 RX DQ/DQS(Engine): PASS
9229 23:10:03.563003 TX OE : PASS
9230 23:10:03.565573 All Pass.
9231 23:10:03.565787
9232 23:10:03.565987 DramC Write-DBI on
9233 23:10:03.568921 PER_BANK_REFRESH: Hybrid Mode
9234 23:10:03.569149 TX_TRACKING: ON
9235 23:10:03.578905 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9236 23:10:03.589202 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9237 23:10:03.595807 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9238 23:10:03.599060 [FAST_K] Save calibration result to emmc
9239 23:10:03.602107 sync common calibartion params.
9240 23:10:03.602324 sync cbt_mode0:1, 1:1
9241 23:10:03.605545 dram_init: ddr_geometry: 2
9242 23:10:03.608683 dram_init: ddr_geometry: 2
9243 23:10:03.608952 dram_init: ddr_geometry: 2
9244 23:10:03.612520 0:dram_rank_size:100000000
9245 23:10:03.615648 1:dram_rank_size:100000000
9246 23:10:03.622273 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9247 23:10:03.622581 DFS_SHUFFLE_HW_MODE: ON
9248 23:10:03.625442 dramc_set_vcore_voltage set vcore to 725000
9249 23:10:03.628739 Read voltage for 1600, 0
9250 23:10:03.629034 Vio18 = 0
9251 23:10:03.632162 Vcore = 725000
9252 23:10:03.632506 Vdram = 0
9253 23:10:03.632780 Vddq = 0
9254 23:10:03.635056 Vmddr = 0
9255 23:10:03.635341 switch to 3200 Mbps bootup
9256 23:10:03.638524 [DramcRunTimeConfig]
9257 23:10:03.638859 PHYPLL
9258 23:10:03.641787 DPM_CONTROL_AFTERK: ON
9259 23:10:03.642059 PER_BANK_REFRESH: ON
9260 23:10:03.645350 REFRESH_OVERHEAD_REDUCTION: ON
9261 23:10:03.648193 CMD_PICG_NEW_MODE: OFF
9262 23:10:03.648407 XRTWTW_NEW_MODE: ON
9263 23:10:03.652026 XRTRTR_NEW_MODE: ON
9264 23:10:03.652329 TX_TRACKING: ON
9265 23:10:03.655735 RDSEL_TRACKING: OFF
9266 23:10:03.658366 DQS Precalculation for DVFS: ON
9267 23:10:03.658670 RX_TRACKING: OFF
9268 23:10:03.662330 HW_GATING DBG: ON
9269 23:10:03.662664 ZQCS_ENABLE_LP4: ON
9270 23:10:03.665579 RX_PICG_NEW_MODE: ON
9271 23:10:03.665827 TX_PICG_NEW_MODE: ON
9272 23:10:03.668214 ENABLE_RX_DCM_DPHY: ON
9273 23:10:03.671423 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9274 23:10:03.675416 DUMMY_READ_FOR_TRACKING: OFF
9275 23:10:03.678048 !!! SPM_CONTROL_AFTERK: OFF
9276 23:10:03.678297 !!! SPM could not control APHY
9277 23:10:03.681729 IMPEDANCE_TRACKING: ON
9278 23:10:03.681973 TEMP_SENSOR: ON
9279 23:10:03.684649 HW_SAVE_FOR_SR: OFF
9280 23:10:03.688103 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9281 23:10:03.691576 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9282 23:10:03.694490 Read ODT Tracking: ON
9283 23:10:03.694755 Refresh Rate DeBounce: ON
9284 23:10:03.697693 DFS_NO_QUEUE_FLUSH: ON
9285 23:10:03.701116 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9286 23:10:03.704345 ENABLE_DFS_RUNTIME_MRW: OFF
9287 23:10:03.704579 DDR_RESERVE_NEW_MODE: ON
9288 23:10:03.708063 MR_CBT_SWITCH_FREQ: ON
9289 23:10:03.711336 =========================
9290 23:10:03.729791 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9291 23:10:03.732557 dram_init: ddr_geometry: 2
9292 23:10:03.751078 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9293 23:10:03.754845 dram_init: dram init end (result: 0)
9294 23:10:03.760506 DRAM-K: Full calibration passed in 24706 msecs
9295 23:10:03.763946 MRC: failed to locate region type 0.
9296 23:10:03.764363 DRAM rank0 size:0x100000000,
9297 23:10:03.767562 DRAM rank1 size=0x100000000
9298 23:10:03.777138 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9299 23:10:03.784283 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9300 23:10:03.790591 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9301 23:10:03.797378 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9302 23:10:03.800137 DRAM rank0 size:0x100000000,
9303 23:10:03.803718 DRAM rank1 size=0x100000000
9304 23:10:03.804165 CBMEM:
9305 23:10:03.806643 IMD: root @ 0xfffff000 254 entries.
9306 23:10:03.810338 IMD: root @ 0xffffec00 62 entries.
9307 23:10:03.813567 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9308 23:10:03.819970 WARNING: RO_VPD is uninitialized or empty.
9309 23:10:03.823751 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9310 23:10:03.833727 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9311 23:10:03.843778 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9312 23:10:03.855363 BS: romstage times (exec / console): total (unknown) / 24188 ms
9313 23:10:03.855842
9314 23:10:03.856280
9315 23:10:03.865417 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9316 23:10:03.868313 ARM64: Exception handlers installed.
9317 23:10:03.871267 ARM64: Testing exception
9318 23:10:03.874691 ARM64: Done test exception
9319 23:10:03.875305 Enumerating buses...
9320 23:10:03.877988 Show all devs... Before device enumeration.
9321 23:10:03.881515 Root Device: enabled 1
9322 23:10:03.884836 CPU_CLUSTER: 0: enabled 1
9323 23:10:03.885298 CPU: 00: enabled 1
9324 23:10:03.887723 Compare with tree...
9325 23:10:03.888199 Root Device: enabled 1
9326 23:10:03.891211 CPU_CLUSTER: 0: enabled 1
9327 23:10:03.894051 CPU: 00: enabled 1
9328 23:10:03.894468 Root Device scanning...
9329 23:10:03.897809 scan_static_bus for Root Device
9330 23:10:03.901276 CPU_CLUSTER: 0 enabled
9331 23:10:03.904914 scan_static_bus for Root Device done
9332 23:10:03.907760 scan_bus: bus Root Device finished in 8 msecs
9333 23:10:03.908304 done
9334 23:10:03.914298 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9335 23:10:03.917469 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9336 23:10:03.924305 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9337 23:10:03.931073 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9338 23:10:03.931496 Allocating resources...
9339 23:10:03.934056 Reading resources...
9340 23:10:03.936992 Root Device read_resources bus 0 link: 0
9341 23:10:03.940770 DRAM rank0 size:0x100000000,
9342 23:10:03.941187 DRAM rank1 size=0x100000000
9343 23:10:03.946859 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9344 23:10:03.947276 CPU: 00 missing read_resources
9345 23:10:03.953603 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9346 23:10:03.956986 Root Device read_resources bus 0 link: 0 done
9347 23:10:03.960156 Done reading resources.
9348 23:10:03.963640 Show resources in subtree (Root Device)...After reading.
9349 23:10:03.967623 Root Device child on link 0 CPU_CLUSTER: 0
9350 23:10:03.970784 CPU_CLUSTER: 0 child on link 0 CPU: 00
9351 23:10:03.980159 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9352 23:10:03.980610 CPU: 00
9353 23:10:03.986828 Root Device assign_resources, bus 0 link: 0
9354 23:10:03.990270 CPU_CLUSTER: 0 missing set_resources
9355 23:10:03.993279 Root Device assign_resources, bus 0 link: 0 done
9356 23:10:03.993718 Done setting resources.
9357 23:10:03.999632 Show resources in subtree (Root Device)...After assigning values.
9358 23:10:04.003361 Root Device child on link 0 CPU_CLUSTER: 0
9359 23:10:04.006461 CPU_CLUSTER: 0 child on link 0 CPU: 00
9360 23:10:04.016856 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9361 23:10:04.017275 CPU: 00
9362 23:10:04.019797 Done allocating resources.
9363 23:10:04.026788 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9364 23:10:04.027208 Enabling resources...
9365 23:10:04.029633 done.
9366 23:10:04.033216 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9367 23:10:04.036371 Initializing devices...
9368 23:10:04.036782 Root Device init
9369 23:10:04.039839 init hardware done!
9370 23:10:04.040251 0x00000018: ctrlr->caps
9371 23:10:04.042783 52.000 MHz: ctrlr->f_max
9372 23:10:04.045874 0.400 MHz: ctrlr->f_min
9373 23:10:04.046291 0x40ff8080: ctrlr->voltages
9374 23:10:04.049431 sclk: 390625
9375 23:10:04.049839 Bus Width = 1
9376 23:10:04.052775 sclk: 390625
9377 23:10:04.053185 Bus Width = 1
9378 23:10:04.055769 Early init status = 3
9379 23:10:04.059534 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9380 23:10:04.063363 in-header: 03 fc 00 00 01 00 00 00
9381 23:10:04.066682 in-data: 00
9382 23:10:04.070068 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9383 23:10:04.076940 in-header: 03 fd 00 00 00 00 00 00
9384 23:10:04.080153 in-data:
9385 23:10:04.083644 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9386 23:10:04.087381 in-header: 03 fc 00 00 01 00 00 00
9387 23:10:04.090773 in-data: 00
9388 23:10:04.093843 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9389 23:10:04.099664 in-header: 03 fd 00 00 00 00 00 00
9390 23:10:04.102782 in-data:
9391 23:10:04.106044 [SSUSB] Setting up USB HOST controller...
9392 23:10:04.109684 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9393 23:10:04.113582 [SSUSB] phy power-on done.
9394 23:10:04.116007 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9395 23:10:04.122865 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9396 23:10:04.126130 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9397 23:10:04.133642 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9398 23:10:04.138911 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9399 23:10:04.145556 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9400 23:10:04.152622 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9401 23:10:04.158847 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9402 23:10:04.161892 SPM: binary array size = 0x9dc
9403 23:10:04.165794 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9404 23:10:04.172081 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9405 23:10:04.179001 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9406 23:10:04.184980 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9407 23:10:04.188206 configure_display: Starting display init
9408 23:10:04.223106 anx7625_power_on_init: Init interface.
9409 23:10:04.226085 anx7625_disable_pd_protocol: Disabled PD feature.
9410 23:10:04.229436 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9411 23:10:04.256968 anx7625_start_dp_work: Secure OCM version=00
9412 23:10:04.260058 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9413 23:10:04.275324 sp_tx_get_edid_block: EDID Block = 1
9414 23:10:04.377987 Extracted contents:
9415 23:10:04.381044 header: 00 ff ff ff ff ff ff 00
9416 23:10:04.384221 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9417 23:10:04.387612 version: 01 04
9418 23:10:04.391053 basic params: 95 1f 11 78 0a
9419 23:10:04.394529 chroma info: 76 90 94 55 54 90 27 21 50 54
9420 23:10:04.397736 established: 00 00 00
9421 23:10:04.404077 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9422 23:10:04.410549 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9423 23:10:04.413934 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9424 23:10:04.420753 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9425 23:10:04.426981 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9426 23:10:04.430406 extensions: 00
9427 23:10:04.430825 checksum: fb
9428 23:10:04.431173
9429 23:10:04.437068 Manufacturer: IVO Model 57d Serial Number 0
9430 23:10:04.437584 Made week 0 of 2020
9431 23:10:04.440729 EDID version: 1.4
9432 23:10:04.441149 Digital display
9433 23:10:04.443661 6 bits per primary color channel
9434 23:10:04.446635 DisplayPort interface
9435 23:10:04.447059 Maximum image size: 31 cm x 17 cm
9436 23:10:04.450235 Gamma: 220%
9437 23:10:04.450654 Check DPMS levels
9438 23:10:04.456671 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9439 23:10:04.460319 First detailed timing is preferred timing
9440 23:10:04.463441 Established timings supported:
9441 23:10:04.464063 Standard timings supported:
9442 23:10:04.466880 Detailed timings
9443 23:10:04.469896 Hex of detail: 383680a07038204018303c0035ae10000019
9444 23:10:04.476578 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9445 23:10:04.479532 0780 0798 07c8 0820 hborder 0
9446 23:10:04.482985 0438 043b 0447 0458 vborder 0
9447 23:10:04.486148 -hsync -vsync
9448 23:10:04.486590 Did detailed timing
9449 23:10:04.492995 Hex of detail: 000000000000000000000000000000000000
9450 23:10:04.496224 Manufacturer-specified data, tag 0
9451 23:10:04.499227 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9452 23:10:04.502449 ASCII string: InfoVision
9453 23:10:04.505675 Hex of detail: 000000fe00523134304e574635205248200a
9454 23:10:04.509340 ASCII string: R140NWF5 RH
9455 23:10:04.509995 Checksum
9456 23:10:04.512324 Checksum: 0xfb (valid)
9457 23:10:04.516279 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9458 23:10:04.519887 DSI data_rate: 832800000 bps
9459 23:10:04.525564 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9460 23:10:04.529046 anx7625_parse_edid: pixelclock(138800).
9461 23:10:04.532209 hactive(1920), hsync(48), hfp(24), hbp(88)
9462 23:10:04.535419 vactive(1080), vsync(12), vfp(3), vbp(17)
9463 23:10:04.538647 anx7625_dsi_config: config dsi.
9464 23:10:04.545499 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9465 23:10:04.559888 anx7625_dsi_config: success to config DSI
9466 23:10:04.563605 anx7625_dp_start: MIPI phy setup OK.
9467 23:10:04.567153 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9468 23:10:04.569986 mtk_ddp_mode_set invalid vrefresh 60
9469 23:10:04.573065 main_disp_path_setup
9470 23:10:04.573651 ovl_layer_smi_id_en
9471 23:10:04.576464 ovl_layer_smi_id_en
9472 23:10:04.577068 ccorr_config
9473 23:10:04.577548 aal_config
9474 23:10:04.579793 gamma_config
9475 23:10:04.580365 postmask_config
9476 23:10:04.583344 dither_config
9477 23:10:04.586452 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9478 23:10:04.593038 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9479 23:10:04.595887 Root Device init finished in 556 msecs
9480 23:10:04.599001 CPU_CLUSTER: 0 init
9481 23:10:04.606176 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9482 23:10:04.612663 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9483 23:10:04.613120 APU_MBOX 0x190000b0 = 0x10001
9484 23:10:04.615586 APU_MBOX 0x190001b0 = 0x10001
9485 23:10:04.618971 APU_MBOX 0x190005b0 = 0x10001
9486 23:10:04.622330 APU_MBOX 0x190006b0 = 0x10001
9487 23:10:04.629276 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9488 23:10:04.638617 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9489 23:10:04.651587 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9490 23:10:04.657378 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9491 23:10:04.669817 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9492 23:10:04.678574 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9493 23:10:04.681977 CPU_CLUSTER: 0 init finished in 81 msecs
9494 23:10:04.685577 Devices initialized
9495 23:10:04.688438 Show all devs... After init.
9496 23:10:04.688860 Root Device: enabled 1
9497 23:10:04.692014 CPU_CLUSTER: 0: enabled 1
9498 23:10:04.695341 CPU: 00: enabled 1
9499 23:10:04.698257 BS: BS_DEV_INIT run times (exec / console): 214 / 447 ms
9500 23:10:04.701882 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9501 23:10:04.705323 ELOG: NV offset 0x57f000 size 0x1000
9502 23:10:04.712031 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9503 23:10:04.718414 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9504 23:10:04.722194 ELOG: Event(17) added with size 13 at 2023-12-27 23:10:32 UTC
9505 23:10:04.728591 out: cmd=0x121: 03 db 21 01 00 00 00 00
9506 23:10:04.732195 in-header: 03 70 00 00 2c 00 00 00
9507 23:10:04.744801 in-data: ef 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9508 23:10:04.749230 ELOG: Event(A1) added with size 10 at 2023-12-27 23:10:32 UTC
9509 23:10:04.754557 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9510 23:10:04.761039 ELOG: Event(A0) added with size 9 at 2023-12-27 23:10:32 UTC
9511 23:10:04.764423 elog_add_boot_reason: Logged dev mode boot
9512 23:10:04.770980 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9513 23:10:04.771537 Finalize devices...
9514 23:10:04.774508 Devices finalized
9515 23:10:04.777598 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9516 23:10:04.781171 Writing coreboot table at 0xffe64000
9517 23:10:04.787612 0. 000000000010a000-0000000000113fff: RAMSTAGE
9518 23:10:04.792447 1. 0000000040000000-00000000400fffff: RAM
9519 23:10:04.794810 2. 0000000040100000-000000004032afff: RAMSTAGE
9520 23:10:04.797309 3. 000000004032b000-00000000545fffff: RAM
9521 23:10:04.801274 4. 0000000054600000-000000005465ffff: BL31
9522 23:10:04.804227 5. 0000000054660000-00000000ffe63fff: RAM
9523 23:10:04.810680 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9524 23:10:04.814303 7. 0000000100000000-000000023fffffff: RAM
9525 23:10:04.817454 Passing 5 GPIOs to payload:
9526 23:10:04.821256 NAME | PORT | POLARITY | VALUE
9527 23:10:04.827028 EC in RW | 0x000000aa | low | undefined
9528 23:10:04.830517 EC interrupt | 0x00000005 | low | undefined
9529 23:10:04.836857 TPM interrupt | 0x000000ab | high | undefined
9530 23:10:04.840215 SD card detect | 0x00000011 | high | undefined
9531 23:10:04.843866 speaker enable | 0x00000093 | high | undefined
9532 23:10:04.846862 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9533 23:10:04.850917 in-header: 03 f9 00 00 02 00 00 00
9534 23:10:04.853721 in-data: 02 00
9535 23:10:04.857207 ADC[4]: Raw value=903031 ID=7
9536 23:10:04.860434 ADC[3]: Raw value=213652 ID=1
9537 23:10:04.860930 RAM Code: 0x71
9538 23:10:04.863845 ADC[6]: Raw value=75036 ID=0
9539 23:10:04.867152 ADC[5]: Raw value=212543 ID=1
9540 23:10:04.867615 SKU Code: 0x1
9541 23:10:04.874004 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a1a9
9542 23:10:04.874481 coreboot table: 964 bytes.
9543 23:10:04.876997 IMD ROOT 0. 0xfffff000 0x00001000
9544 23:10:04.880372 IMD SMALL 1. 0xffffe000 0x00001000
9545 23:10:04.883329 RO MCACHE 2. 0xffffc000 0x00001104
9546 23:10:04.887078 CONSOLE 3. 0xfff7c000 0x00080000
9547 23:10:04.891138 FMAP 4. 0xfff7b000 0x00000452
9548 23:10:04.893982 TIME STAMP 5. 0xfff7a000 0x00000910
9549 23:10:04.896891 VBOOT WORK 6. 0xfff66000 0x00014000
9550 23:10:04.900084 RAMOOPS 7. 0xffe66000 0x00100000
9551 23:10:04.903146 COREBOOT 8. 0xffe64000 0x00002000
9552 23:10:04.906744 IMD small region:
9553 23:10:04.909860 IMD ROOT 0. 0xffffec00 0x00000400
9554 23:10:04.913267 VPD 1. 0xffffeb80 0x0000006c
9555 23:10:04.916605 MMC STATUS 2. 0xffffeb60 0x00000004
9556 23:10:04.923257 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9557 23:10:04.923823 Probing TPM: done!
9558 23:10:04.930012 Connected to device vid:did:rid of 1ae0:0028:00
9559 23:10:04.936622 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9560 23:10:04.940342 Initialized TPM device CR50 revision 0
9561 23:10:04.943231 Checking cr50 for pending updates
9562 23:10:04.948951 Reading cr50 TPM mode
9563 23:10:04.957842 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9564 23:10:04.964423 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9565 23:10:05.004514 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9566 23:10:05.007198 Checking segment from ROM address 0x40100000
9567 23:10:05.011061 Checking segment from ROM address 0x4010001c
9568 23:10:05.017649 Loading segment from ROM address 0x40100000
9569 23:10:05.018195 code (compression=0)
9570 23:10:05.027709 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9571 23:10:05.034118 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9572 23:10:05.034682 it's not compressed!
9573 23:10:05.040682 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9574 23:10:05.047227 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9575 23:10:05.065131 Loading segment from ROM address 0x4010001c
9576 23:10:05.065673 Entry Point 0x80000000
9577 23:10:05.067970 Loaded segments
9578 23:10:05.071419 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9579 23:10:05.078605 Jumping to boot code at 0x80000000(0xffe64000)
9580 23:10:05.084421 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9581 23:10:05.091187 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9582 23:10:05.098934 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9583 23:10:05.102467 Checking segment from ROM address 0x40100000
9584 23:10:05.106050 Checking segment from ROM address 0x4010001c
9585 23:10:05.112627 Loading segment from ROM address 0x40100000
9586 23:10:05.113094 code (compression=1)
9587 23:10:05.119013 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9588 23:10:05.128908 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9589 23:10:05.129371 using LZMA
9590 23:10:05.137617 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9591 23:10:05.144305 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9592 23:10:05.147331 Loading segment from ROM address 0x4010001c
9593 23:10:05.147812 Entry Point 0x54601000
9594 23:10:05.150459 Loaded segments
9595 23:10:05.153821 NOTICE: MT8192 bl31_setup
9596 23:10:05.160668 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9597 23:10:05.164121 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9598 23:10:05.167741 WARNING: region 0:
9599 23:10:05.170896 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9600 23:10:05.171369 WARNING: region 1:
9601 23:10:05.177707 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9602 23:10:05.180890 WARNING: region 2:
9603 23:10:05.183892 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9604 23:10:05.187912 WARNING: region 3:
9605 23:10:05.190936 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9606 23:10:05.193942 WARNING: region 4:
9607 23:10:05.200681 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9608 23:10:05.201162 WARNING: region 5:
9609 23:10:05.204296 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9610 23:10:05.207149 WARNING: region 6:
9611 23:10:05.210545 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9612 23:10:05.214137 WARNING: region 7:
9613 23:10:05.217990 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9614 23:10:05.224068 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9615 23:10:05.227227 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9616 23:10:05.230248 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9617 23:10:05.237486 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9618 23:10:05.240688 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9619 23:10:05.247218 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9620 23:10:05.250309 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9621 23:10:05.253494 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9622 23:10:05.260610 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9623 23:10:05.264091 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9624 23:10:05.267469 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9625 23:10:05.273748 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9626 23:10:05.276555 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9627 23:10:05.283881 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9628 23:10:05.287067 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9629 23:10:05.290826 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9630 23:10:05.296483 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9631 23:10:05.300353 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9632 23:10:05.306780 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9633 23:10:05.309719 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9634 23:10:05.313199 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9635 23:10:05.319905 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9636 23:10:05.323116 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9637 23:10:05.327227 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9638 23:10:05.333054 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9639 23:10:05.336425 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9640 23:10:05.343192 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9641 23:10:05.346622 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9642 23:10:05.350017 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9643 23:10:05.357040 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9644 23:10:05.359906 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9645 23:10:05.366829 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9646 23:10:05.369859 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9647 23:10:05.373229 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9648 23:10:05.376623 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9649 23:10:05.383244 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9650 23:10:05.387084 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9651 23:10:05.390162 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9652 23:10:05.392690 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9653 23:10:05.399907 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9654 23:10:05.403093 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9655 23:10:05.406280 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9656 23:10:05.409313 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9657 23:10:05.416205 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9658 23:10:05.419873 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9659 23:10:05.422842 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9660 23:10:05.426842 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9661 23:10:05.433481 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9662 23:10:05.436383 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9663 23:10:05.442790 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9664 23:10:05.446045 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9665 23:10:05.449648 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9666 23:10:05.456208 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9667 23:10:05.459210 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9668 23:10:05.466013 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9669 23:10:05.469521 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9670 23:10:05.476135 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9671 23:10:05.479083 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9672 23:10:05.482518 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9673 23:10:05.489755 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9674 23:10:05.492987 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9675 23:10:05.499205 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9676 23:10:05.502834 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9677 23:10:05.509696 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9678 23:10:05.512921 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9679 23:10:05.518967 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9680 23:10:05.522791 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9681 23:10:05.526027 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9682 23:10:05.532611 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9683 23:10:05.535796 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9684 23:10:05.542555 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9685 23:10:05.545971 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9686 23:10:05.552849 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9687 23:10:05.555895 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9688 23:10:05.559451 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9689 23:10:05.565463 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9690 23:10:05.568899 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9691 23:10:05.575642 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9692 23:10:05.578705 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9693 23:10:05.585192 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9694 23:10:05.588550 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9695 23:10:05.595799 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9696 23:10:05.598618 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9697 23:10:05.602355 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9698 23:10:05.608688 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9699 23:10:05.611936 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9700 23:10:05.618556 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9701 23:10:05.621987 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9702 23:10:05.628575 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9703 23:10:05.632361 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9704 23:10:05.635255 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9705 23:10:05.642129 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9706 23:10:05.644924 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9707 23:10:05.651761 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9708 23:10:05.656096 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9709 23:10:05.661551 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9710 23:10:05.664680 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9711 23:10:05.668027 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9712 23:10:05.674665 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9713 23:10:05.678066 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9714 23:10:05.681039 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9715 23:10:05.684813 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9716 23:10:05.690979 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9717 23:10:05.694369 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9718 23:10:05.701085 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9719 23:10:05.704306 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9720 23:10:05.708066 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9721 23:10:05.714946 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9722 23:10:05.717663 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9723 23:10:05.724878 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9724 23:10:05.727858 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9725 23:10:05.734672 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9726 23:10:05.737363 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9727 23:10:05.741140 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9728 23:10:05.747870 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9729 23:10:05.751066 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9730 23:10:05.754304 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9731 23:10:05.760485 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9732 23:10:05.763979 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9733 23:10:05.767515 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9734 23:10:05.774266 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9735 23:10:05.777280 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9736 23:10:05.780501 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9737 23:10:05.783585 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9738 23:10:05.790534 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9739 23:10:05.793668 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9740 23:10:05.796889 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9741 23:10:05.804664 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9742 23:10:05.807275 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9743 23:10:05.813768 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9744 23:10:05.817101 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9745 23:10:05.820583 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9746 23:10:05.827127 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9747 23:10:05.830539 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9748 23:10:05.837463 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9749 23:10:05.840573 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9750 23:10:05.843862 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9751 23:10:05.850414 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9752 23:10:05.854255 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9753 23:10:05.860231 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9754 23:10:05.863429 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9755 23:10:05.867036 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9756 23:10:05.873473 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9757 23:10:05.877029 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9758 23:10:05.883655 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9759 23:10:05.886557 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9760 23:10:05.889879 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9761 23:10:05.896325 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9762 23:10:05.899926 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9763 23:10:05.907509 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9764 23:10:05.909895 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9765 23:10:05.912780 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9766 23:10:05.919804 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9767 23:10:05.923491 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9768 23:10:05.929668 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9769 23:10:05.933123 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9770 23:10:05.936817 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9771 23:10:05.943326 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9772 23:10:05.946610 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9773 23:10:05.952964 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9774 23:10:05.956604 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9775 23:10:05.959263 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9776 23:10:05.965536 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9777 23:10:05.969518 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9778 23:10:05.975702 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9779 23:10:05.979399 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9780 23:10:05.982168 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9781 23:10:05.989483 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9782 23:10:05.991898 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9783 23:10:05.998643 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9784 23:10:06.002341 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9785 23:10:06.005541 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9786 23:10:06.011915 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9787 23:10:06.014935 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9788 23:10:06.021750 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9789 23:10:06.025471 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9790 23:10:06.028361 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9791 23:10:06.035334 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9792 23:10:06.038137 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9793 23:10:06.044798 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9794 23:10:06.048357 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9795 23:10:06.051580 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9796 23:10:06.058407 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9797 23:10:06.061606 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9798 23:10:06.067833 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9799 23:10:06.071119 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9800 23:10:06.074825 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9801 23:10:06.081080 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9802 23:10:06.084474 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9803 23:10:06.090682 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9804 23:10:06.094261 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9805 23:10:06.101554 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9806 23:10:06.104005 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9807 23:10:06.107116 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9808 23:10:06.113939 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9809 23:10:06.117266 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9810 23:10:06.124014 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9811 23:10:06.127253 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9812 23:10:06.133104 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9813 23:10:06.136907 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9814 23:10:06.140052 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9815 23:10:06.147045 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9816 23:10:06.150025 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9817 23:10:06.156409 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9818 23:10:06.159653 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9819 23:10:06.166616 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9820 23:10:06.169818 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9821 23:10:06.172771 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9822 23:10:06.179534 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9823 23:10:06.183103 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9824 23:10:06.189682 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9825 23:10:06.193087 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9826 23:10:06.199412 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9827 23:10:06.202399 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9828 23:10:06.205924 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9829 23:10:06.213087 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9830 23:10:06.217124 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9831 23:10:06.222956 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9832 23:10:06.226197 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9833 23:10:06.232490 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9834 23:10:06.235551 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9835 23:10:06.239413 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9836 23:10:06.245806 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9837 23:10:06.249210 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9838 23:10:06.255959 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9839 23:10:06.259370 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9840 23:10:06.265573 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9841 23:10:06.268652 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9842 23:10:06.271964 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9843 23:10:06.278955 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9844 23:10:06.281979 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9845 23:10:06.285643 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9846 23:10:06.288361 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9847 23:10:06.294938 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9848 23:10:06.298442 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9849 23:10:06.301902 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9850 23:10:06.307986 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9851 23:10:06.311495 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9852 23:10:06.315089 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9853 23:10:06.321130 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9854 23:10:06.324778 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9855 23:10:06.331477 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9856 23:10:06.334456 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9857 23:10:06.337796 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9858 23:10:06.344758 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9859 23:10:06.348266 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9860 23:10:06.354706 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9861 23:10:06.358185 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9862 23:10:06.361077 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9863 23:10:06.368095 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9864 23:10:06.370968 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9865 23:10:06.373859 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9866 23:10:06.380748 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9867 23:10:06.384305 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9868 23:10:06.387842 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9869 23:10:06.393921 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9870 23:10:06.396724 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9871 23:10:06.403911 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9872 23:10:06.407312 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9873 23:10:06.410494 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9874 23:10:06.417063 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9875 23:10:06.419961 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9876 23:10:06.426614 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9877 23:10:06.430297 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9878 23:10:06.433649 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9879 23:10:06.439652 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9880 23:10:06.443308 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9881 23:10:06.446336 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9882 23:10:06.453182 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9883 23:10:06.456282 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9884 23:10:06.459993 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9885 23:10:06.463241 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9886 23:10:06.469626 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9887 23:10:06.473694 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9888 23:10:06.475843 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9889 23:10:06.479665 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9890 23:10:06.485670 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9891 23:10:06.489245 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9892 23:10:06.492592 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9893 23:10:06.496162 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9894 23:10:06.502523 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9895 23:10:06.505949 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9896 23:10:06.509749 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9897 23:10:06.516530 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9898 23:10:06.519192 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9899 23:10:06.526317 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9900 23:10:06.529289 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9901 23:10:06.535750 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9902 23:10:06.539621 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9903 23:10:06.542730 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9904 23:10:06.549222 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9905 23:10:06.552807 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9906 23:10:06.559240 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9907 23:10:06.562355 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9908 23:10:06.565668 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9909 23:10:06.572195 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9910 23:10:06.575589 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9911 23:10:06.582292 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9912 23:10:06.586084 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9913 23:10:06.588956 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9914 23:10:06.595620 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9915 23:10:06.599592 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9916 23:10:06.605751 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9917 23:10:06.609019 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9918 23:10:06.615374 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9919 23:10:06.618606 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9920 23:10:06.622492 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9921 23:10:06.628826 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9922 23:10:06.631819 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9923 23:10:06.638538 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9924 23:10:06.641846 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9925 23:10:06.648620 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9926 23:10:06.652268 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9927 23:10:06.654898 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9928 23:10:06.662174 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9929 23:10:06.664992 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9930 23:10:06.668339 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9931 23:10:06.675141 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9932 23:10:06.678225 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9933 23:10:06.684864 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9934 23:10:06.688220 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9935 23:10:06.691645 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9936 23:10:06.698084 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9937 23:10:06.701461 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9938 23:10:06.707916 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9939 23:10:06.711312 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9940 23:10:06.717691 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9941 23:10:06.721294 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9942 23:10:06.728186 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9943 23:10:06.731051 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9944 23:10:06.734359 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9945 23:10:06.740924 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9946 23:10:06.744001 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9947 23:10:06.750844 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9948 23:10:06.754284 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9949 23:10:06.757591 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9950 23:10:06.764193 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9951 23:10:06.767653 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9952 23:10:06.773661 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9953 23:10:06.777104 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9954 23:10:06.780420 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9955 23:10:06.787317 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9956 23:10:06.790854 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9957 23:10:06.796957 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9958 23:10:06.800598 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9959 23:10:06.803621 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9960 23:10:06.810135 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9961 23:10:06.813932 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9962 23:10:06.820498 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9963 23:10:06.823429 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9964 23:10:06.830217 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9965 23:10:06.833743 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9966 23:10:06.839930 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9967 23:10:06.843144 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9968 23:10:06.846647 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9969 23:10:06.853010 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9970 23:10:06.856215 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9971 23:10:06.862656 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9972 23:10:06.866443 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9973 23:10:06.872268 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9974 23:10:06.876077 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9975 23:10:06.878846 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9976 23:10:06.886383 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9977 23:10:06.888808 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9978 23:10:06.895398 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9979 23:10:06.899807 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9980 23:10:06.905298 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9981 23:10:06.908790 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9982 23:10:06.915645 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9983 23:10:06.918884 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9984 23:10:06.921689 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9985 23:10:06.928680 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9986 23:10:06.931919 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9987 23:10:06.938879 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9988 23:10:06.941724 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9989 23:10:06.948161 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9990 23:10:06.951800 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9991 23:10:06.955263 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9992 23:10:06.961211 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9993 23:10:06.965322 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9994 23:10:06.971334 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9995 23:10:06.974523 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9996 23:10:06.981512 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9997 23:10:06.984522 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9998 23:10:06.991457 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9999 23:10:06.994129 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
10000 23:10:06.998121 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
10001 23:10:07.004846 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
10002 23:10:07.007863 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
10003 23:10:07.014105 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
10004 23:10:07.017496 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
10005 23:10:07.024778 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
10006 23:10:07.028107 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
10007 23:10:07.034005 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
10008 23:10:07.037879 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
10009 23:10:07.041420 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
10010 23:10:07.047503 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
10011 23:10:07.051204 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
10012 23:10:07.057165 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
10013 23:10:07.060448 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
10014 23:10:07.067893 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
10015 23:10:07.070713 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
10016 23:10:07.074063 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
10017 23:10:07.080541 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
10018 23:10:07.083612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
10019 23:10:07.090435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
10020 23:10:07.093597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
10021 23:10:07.100301 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
10022 23:10:07.103348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
10023 23:10:07.110644 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
10024 23:10:07.113779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
10025 23:10:07.120226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
10026 23:10:07.123743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10027 23:10:07.129734 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10028 23:10:07.133022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10029 23:10:07.139572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10030 23:10:07.143162 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10031 23:10:07.150558 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10032 23:10:07.153038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10033 23:10:07.159447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10034 23:10:07.163343 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10035 23:10:07.169814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10036 23:10:07.173240 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10037 23:10:07.179401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10038 23:10:07.182534 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10039 23:10:07.189280 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10040 23:10:07.192880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10041 23:10:07.199133 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10042 23:10:07.202646 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10043 23:10:07.209021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10044 23:10:07.212129 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10045 23:10:07.218545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10046 23:10:07.222501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10047 23:10:07.228631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10048 23:10:07.232384 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10049 23:10:07.235358 INFO: [APUAPC] vio 0
10050 23:10:07.238572 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10051 23:10:07.245431 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10052 23:10:07.249164 INFO: [APUAPC] D0_APC_0: 0x400510
10053 23:10:07.249241 INFO: [APUAPC] D0_APC_1: 0x0
10054 23:10:07.252578 INFO: [APUAPC] D0_APC_2: 0x1540
10055 23:10:07.255325 INFO: [APUAPC] D0_APC_3: 0x0
10056 23:10:07.258876 INFO: [APUAPC] D1_APC_0: 0xffffffff
10057 23:10:07.261606 INFO: [APUAPC] D1_APC_1: 0xffffffff
10058 23:10:07.265116 INFO: [APUAPC] D1_APC_2: 0x3fffff
10059 23:10:07.268156 INFO: [APUAPC] D1_APC_3: 0x0
10060 23:10:07.272293 INFO: [APUAPC] D2_APC_0: 0xffffffff
10061 23:10:07.275533 INFO: [APUAPC] D2_APC_1: 0xffffffff
10062 23:10:07.278446 INFO: [APUAPC] D2_APC_2: 0x3fffff
10063 23:10:07.281522 INFO: [APUAPC] D2_APC_3: 0x0
10064 23:10:07.284831 INFO: [APUAPC] D3_APC_0: 0xffffffff
10065 23:10:07.288142 INFO: [APUAPC] D3_APC_1: 0xffffffff
10066 23:10:07.291617 INFO: [APUAPC] D3_APC_2: 0x3fffff
10067 23:10:07.294942 INFO: [APUAPC] D3_APC_3: 0x0
10068 23:10:07.299207 INFO: [APUAPC] D4_APC_0: 0xffffffff
10069 23:10:07.301401 INFO: [APUAPC] D4_APC_1: 0xffffffff
10070 23:10:07.304695 INFO: [APUAPC] D4_APC_2: 0x3fffff
10071 23:10:07.308536 INFO: [APUAPC] D4_APC_3: 0x0
10072 23:10:07.311579 INFO: [APUAPC] D5_APC_0: 0xffffffff
10073 23:10:07.314395 INFO: [APUAPC] D5_APC_1: 0xffffffff
10074 23:10:07.318202 INFO: [APUAPC] D5_APC_2: 0x3fffff
10075 23:10:07.321201 INFO: [APUAPC] D5_APC_3: 0x0
10076 23:10:07.324490 INFO: [APUAPC] D6_APC_0: 0xffffffff
10077 23:10:07.327525 INFO: [APUAPC] D6_APC_1: 0xffffffff
10078 23:10:07.330823 INFO: [APUAPC] D6_APC_2: 0x3fffff
10079 23:10:07.334806 INFO: [APUAPC] D6_APC_3: 0x0
10080 23:10:07.337672 INFO: [APUAPC] D7_APC_0: 0xffffffff
10081 23:10:07.340868 INFO: [APUAPC] D7_APC_1: 0xffffffff
10082 23:10:07.344641 INFO: [APUAPC] D7_APC_2: 0x3fffff
10083 23:10:07.347572 INFO: [APUAPC] D7_APC_3: 0x0
10084 23:10:07.351253 INFO: [APUAPC] D8_APC_0: 0xffffffff
10085 23:10:07.354447 INFO: [APUAPC] D8_APC_1: 0xffffffff
10086 23:10:07.357334 INFO: [APUAPC] D8_APC_2: 0x3fffff
10087 23:10:07.360838 INFO: [APUAPC] D8_APC_3: 0x0
10088 23:10:07.363815 INFO: [APUAPC] D9_APC_0: 0xffffffff
10089 23:10:07.367329 INFO: [APUAPC] D9_APC_1: 0xffffffff
10090 23:10:07.370361 INFO: [APUAPC] D9_APC_2: 0x3fffff
10091 23:10:07.374171 INFO: [APUAPC] D9_APC_3: 0x0
10092 23:10:07.376964 INFO: [APUAPC] D10_APC_0: 0xffffffff
10093 23:10:07.380568 INFO: [APUAPC] D10_APC_1: 0xffffffff
10094 23:10:07.383654 INFO: [APUAPC] D10_APC_2: 0x3fffff
10095 23:10:07.387162 INFO: [APUAPC] D10_APC_3: 0x0
10096 23:10:07.390334 INFO: [APUAPC] D11_APC_0: 0xffffffff
10097 23:10:07.393881 INFO: [APUAPC] D11_APC_1: 0xffffffff
10098 23:10:07.397083 INFO: [APUAPC] D11_APC_2: 0x3fffff
10099 23:10:07.400549 INFO: [APUAPC] D11_APC_3: 0x0
10100 23:10:07.403459 INFO: [APUAPC] D12_APC_0: 0xffffffff
10101 23:10:07.406724 INFO: [APUAPC] D12_APC_1: 0xffffffff
10102 23:10:07.410347 INFO: [APUAPC] D12_APC_2: 0x3fffff
10103 23:10:07.413755 INFO: [APUAPC] D12_APC_3: 0x0
10104 23:10:07.416481 INFO: [APUAPC] D13_APC_0: 0xffffffff
10105 23:10:07.419916 INFO: [APUAPC] D13_APC_1: 0xffffffff
10106 23:10:07.423248 INFO: [APUAPC] D13_APC_2: 0x3fffff
10107 23:10:07.426984 INFO: [APUAPC] D13_APC_3: 0x0
10108 23:10:07.429859 INFO: [APUAPC] D14_APC_0: 0xffffffff
10109 23:10:07.433574 INFO: [APUAPC] D14_APC_1: 0xffffffff
10110 23:10:07.436971 INFO: [APUAPC] D14_APC_2: 0x3fffff
10111 23:10:07.440185 INFO: [APUAPC] D14_APC_3: 0x0
10112 23:10:07.443197 INFO: [APUAPC] D15_APC_0: 0xffffffff
10113 23:10:07.446445 INFO: [APUAPC] D15_APC_1: 0xffffffff
10114 23:10:07.449992 INFO: [APUAPC] D15_APC_2: 0x3fffff
10115 23:10:07.453065 INFO: [APUAPC] D15_APC_3: 0x0
10116 23:10:07.456671 INFO: [APUAPC] APC_CON: 0x4
10117 23:10:07.459807 INFO: [NOCDAPC] D0_APC_0: 0x0
10118 23:10:07.463116 INFO: [NOCDAPC] D0_APC_1: 0x0
10119 23:10:07.466347 INFO: [NOCDAPC] D1_APC_0: 0x0
10120 23:10:07.466428 INFO: [NOCDAPC] D1_APC_1: 0xfff
10121 23:10:07.469575 INFO: [NOCDAPC] D2_APC_0: 0x0
10122 23:10:07.473228 INFO: [NOCDAPC] D2_APC_1: 0xfff
10123 23:10:07.476085 INFO: [NOCDAPC] D3_APC_0: 0x0
10124 23:10:07.479826 INFO: [NOCDAPC] D3_APC_1: 0xfff
10125 23:10:07.483235 INFO: [NOCDAPC] D4_APC_0: 0x0
10126 23:10:07.486442 INFO: [NOCDAPC] D4_APC_1: 0xfff
10127 23:10:07.489199 INFO: [NOCDAPC] D5_APC_0: 0x0
10128 23:10:07.492732 INFO: [NOCDAPC] D5_APC_1: 0xfff
10129 23:10:07.496139 INFO: [NOCDAPC] D6_APC_0: 0x0
10130 23:10:07.499030 INFO: [NOCDAPC] D6_APC_1: 0xfff
10131 23:10:07.503100 INFO: [NOCDAPC] D7_APC_0: 0x0
10132 23:10:07.506044 INFO: [NOCDAPC] D7_APC_1: 0xfff
10133 23:10:07.506554 INFO: [NOCDAPC] D8_APC_0: 0x0
10134 23:10:07.509741 INFO: [NOCDAPC] D8_APC_1: 0xfff
10135 23:10:07.512832 INFO: [NOCDAPC] D9_APC_0: 0x0
10136 23:10:07.516168 INFO: [NOCDAPC] D9_APC_1: 0xfff
10137 23:10:07.520025 INFO: [NOCDAPC] D10_APC_0: 0x0
10138 23:10:07.522683 INFO: [NOCDAPC] D10_APC_1: 0xfff
10139 23:10:07.526075 INFO: [NOCDAPC] D11_APC_0: 0x0
10140 23:10:07.529099 INFO: [NOCDAPC] D11_APC_1: 0xfff
10141 23:10:07.532765 INFO: [NOCDAPC] D12_APC_0: 0x0
10142 23:10:07.536062 INFO: [NOCDAPC] D12_APC_1: 0xfff
10143 23:10:07.539806 INFO: [NOCDAPC] D13_APC_0: 0x0
10144 23:10:07.542876 INFO: [NOCDAPC] D13_APC_1: 0xfff
10145 23:10:07.546057 INFO: [NOCDAPC] D14_APC_0: 0x0
10146 23:10:07.549292 INFO: [NOCDAPC] D14_APC_1: 0xfff
10147 23:10:07.549696 INFO: [NOCDAPC] D15_APC_0: 0x0
10148 23:10:07.552956 INFO: [NOCDAPC] D15_APC_1: 0xfff
10149 23:10:07.555784 INFO: [NOCDAPC] APC_CON: 0x4
10150 23:10:07.558684 INFO: [APUAPC] set_apusys_apc done
10151 23:10:07.562254 INFO: [DEVAPC] devapc_init done
10152 23:10:07.568380 INFO: GICv3 without legacy support detected.
10153 23:10:07.572442 INFO: ARM GICv3 driver initialized in EL3
10154 23:10:07.575467 INFO: Maximum SPI INTID supported: 639
10155 23:10:07.578910 INFO: BL31: Initializing runtime services
10156 23:10:07.585281 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10157 23:10:07.588663 INFO: SPM: enable CPC mode
10158 23:10:07.591992 INFO: mcdi ready for mcusys-off-idle and system suspend
10159 23:10:07.598343 INFO: BL31: Preparing for EL3 exit to normal world
10160 23:10:07.601246 INFO: Entry point address = 0x80000000
10161 23:10:07.601557 INFO: SPSR = 0x8
10162 23:10:07.608529
10163 23:10:07.608708
10164 23:10:07.608858
10165 23:10:07.611958 Starting depthcharge on Spherion...
10166 23:10:07.612090
10167 23:10:07.612203 Wipe memory regions:
10168 23:10:07.612317
10169 23:10:07.613356 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10170 23:10:07.613547 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10171 23:10:07.613697 Setting prompt string to ['asurada:']
10172 23:10:07.613847 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10173 23:10:07.614896 [0x00000040000000, 0x00000054600000)
10174 23:10:07.737243
10175 23:10:07.737380 [0x00000054660000, 0x00000080000000)
10176 23:10:07.997718
10177 23:10:07.997868 [0x000000821a7280, 0x000000ffe64000)
10178 23:10:08.742616
10179 23:10:08.745990 [0x00000100000000, 0x00000240000000)
10180 23:10:10.633113
10181 23:10:10.636493 Initializing XHCI USB controller at 0x11200000.
10182 23:10:11.617237
10183 23:10:11.617760 R8152: Initializing
10184 23:10:11.618139
10185 23:10:11.620751 Version 9 (ocp_data = 6010)
10186 23:10:11.621170
10187 23:10:11.624209 R8152: Done initializing
10188 23:10:11.624606
10189 23:10:11.624957 Adding net device
10190 23:10:12.022847
10191 23:10:12.025837 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10192 23:10:12.025926
10193 23:10:12.025990
10194 23:10:12.026057
10195 23:10:12.026418 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10197 23:10:12.126865 asurada: tftpboot 192.168.201.1 12395371/tftp-deploy-3o67wms0/kernel/image.itb 12395371/tftp-deploy-3o67wms0/kernel/cmdline
10198 23:10:12.127013 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10199 23:10:12.127098 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10200 23:10:12.131872 tftpboot 192.168.201.1 12395371/tftp-deploy-3o67wms0/kernel/image.itp-deploy-3o67wms0/kernel/cmdline
10201 23:10:12.131956
10202 23:10:12.132021 Waiting for link
10203 23:10:12.333791
10204 23:10:12.333946 done.
10205 23:10:12.334016
10206 23:10:12.334077 MAC: f4:f5:e8:50:de:0a
10207 23:10:12.334135
10208 23:10:12.336710 Sending DHCP discover... done.
10209 23:10:12.336795
10210 23:10:12.340558 Waiting for reply... done.
10211 23:10:12.340639
10212 23:10:12.343308 Sending DHCP request... done.
10213 23:10:12.343389
10214 23:10:12.348352 Waiting for reply... done.
10215 23:10:12.348433
10216 23:10:12.348497 My ip is 192.168.201.14
10217 23:10:12.348556
10218 23:10:12.351472 The DHCP server ip is 192.168.201.1
10219 23:10:12.351553
10220 23:10:12.358128 TFTP server IP predefined by user: 192.168.201.1
10221 23:10:12.358210
10222 23:10:12.364713 Bootfile predefined by user: 12395371/tftp-deploy-3o67wms0/kernel/image.itb
10223 23:10:12.364795
10224 23:10:12.368382 Sending tftp read request... done.
10225 23:10:12.368463
10226 23:10:12.372249 Waiting for the transfer...
10227 23:10:12.372330
10228 23:10:12.707541 00000000 ################################################################
10229 23:10:12.707684
10230 23:10:13.037828 00080000 ################################################################
10231 23:10:13.037966
10232 23:10:13.311023 00100000 ################################################################
10233 23:10:13.311154
10234 23:10:13.553117 00180000 ################################################################
10235 23:10:13.553280
10236 23:10:13.811634 00200000 ################################################################
10237 23:10:13.811841
10238 23:10:14.082721 00280000 ################################################################
10239 23:10:14.082864
10240 23:10:14.336100 00300000 ################################################################
10241 23:10:14.336234
10242 23:10:14.665043 00380000 ################################################################
10243 23:10:14.665222
10244 23:10:15.007622 00400000 ################################################################
10245 23:10:15.007790
10246 23:10:15.351245 00480000 ################################################################
10247 23:10:15.351439
10248 23:10:15.642116 00500000 ################################################################
10249 23:10:15.642260
10250 23:10:15.918577 00580000 ################################################################
10251 23:10:15.918719
10252 23:10:16.186284 00600000 ################################################################
10253 23:10:16.186457
10254 23:10:16.458827 00680000 ################################################################
10255 23:10:16.458972
10256 23:10:16.721299 00700000 ################################################################
10257 23:10:16.721430
10258 23:10:16.971788 00780000 ################################################################
10259 23:10:16.971922
10260 23:10:17.213615 00800000 ################################################################
10261 23:10:17.213790
10262 23:10:17.478789 00880000 ################################################################
10263 23:10:17.478952
10264 23:10:17.714370 00900000 ################################################################
10265 23:10:17.714522
10266 23:10:17.949813 00980000 ################################################################
10267 23:10:17.949963
10268 23:10:18.203463 00a00000 ################################################################
10269 23:10:18.203636
10270 23:10:18.440652 00a80000 ################################################################
10271 23:10:18.440808
10272 23:10:18.676475 00b00000 ################################################################
10273 23:10:18.676608
10274 23:10:18.914183 00b80000 ################################################################
10275 23:10:18.914322
10276 23:10:19.145413 00c00000 ################################################################
10277 23:10:19.145545
10278 23:10:19.378976 00c80000 ################################################################
10279 23:10:19.379123
10280 23:10:19.641146 00d00000 ################################################################
10281 23:10:19.641287
10282 23:10:19.896373 00d80000 ################################################################
10283 23:10:19.896510
10284 23:10:20.159240 00e00000 ################################################################
10285 23:10:20.159375
10286 23:10:20.389480 00e80000 ################################################################
10287 23:10:20.389626
10288 23:10:20.649308 00f00000 ################################################################
10289 23:10:20.649462
10290 23:10:20.904997 00f80000 ################################################################
10291 23:10:20.905149
10292 23:10:21.161857 01000000 ################################################################
10293 23:10:21.162009
10294 23:10:21.425291 01080000 ################################################################
10295 23:10:21.425439
10296 23:10:21.719660 01100000 ################################################################
10297 23:10:21.719849
10298 23:10:22.011449 01180000 ################################################################
10299 23:10:22.011600
10300 23:10:22.263229 01200000 ################################################################
10301 23:10:22.263380
10302 23:10:22.524897 01280000 ################################################################
10303 23:10:22.525029
10304 23:10:22.782419 01300000 ################################################################
10305 23:10:22.782566
10306 23:10:23.042494 01380000 ################################################################
10307 23:10:23.042665
10308 23:10:23.305205 01400000 ################################################################
10309 23:10:23.305351
10310 23:10:23.570619 01480000 ################################################################
10311 23:10:23.570791
10312 23:10:23.843687 01500000 ################################################################
10313 23:10:23.843837
10314 23:10:24.101353 01580000 ################################################################
10315 23:10:24.101533
10316 23:10:24.366474 01600000 ################################################################
10317 23:10:24.366654
10318 23:10:24.639639 01680000 ################################################################
10319 23:10:24.639818
10320 23:10:24.892071 01700000 ################################################################
10321 23:10:24.892219
10322 23:10:25.181505 01780000 ################################################################
10323 23:10:25.181661
10324 23:10:25.471605 01800000 ################################################################
10325 23:10:25.471776
10326 23:10:25.783364 01880000 ################################################################
10327 23:10:25.783509
10328 23:10:26.088907 01900000 ################################################################
10329 23:10:26.089058
10330 23:10:26.372283 01980000 ################################################################
10331 23:10:26.372431
10332 23:10:26.641778 01a00000 ################################################################
10333 23:10:26.641927
10334 23:10:26.918963 01a80000 ################################################################
10335 23:10:26.919110
10336 23:10:27.194108 01b00000 ################################################################
10337 23:10:27.194259
10338 23:10:27.486877 01b80000 ############################################################# done.
10339 23:10:27.487029
10340 23:10:27.490252 The bootfile was 29330410 bytes long.
10341 23:10:27.490335
10342 23:10:27.493919 Sending tftp read request... done.
10343 23:10:27.494001
10344 23:10:27.496794 Waiting for the transfer...
10345 23:10:27.496876
10346 23:10:27.496940 00000000 # done.
10347 23:10:27.497002
10348 23:10:27.507190 Command line loaded dynamically from TFTP file: 12395371/tftp-deploy-3o67wms0/kernel/cmdline
10349 23:10:27.507277
10350 23:10:27.526542 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12395371/extract-nfsrootfs-1s5co7bz,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10351 23:10:27.526631
10352 23:10:27.530309 Loading FIT.
10353 23:10:27.530389
10354 23:10:27.533394 Image ramdisk-1 has 17800711 bytes.
10355 23:10:27.533475
10356 23:10:27.536394 Image fdt-1 has 47278 bytes.
10357 23:10:27.536475
10358 23:10:27.539809 Image kernel-1 has 11480388 bytes.
10359 23:10:27.539889
10360 23:10:27.546810 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10361 23:10:27.546895
10362 23:10:27.566342 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10363 23:10:27.566429
10364 23:10:27.569254 Choosing best match conf-1 for compat google,spherion-rev2.
10365 23:10:27.574666
10366 23:10:27.578397 Connected to device vid:did:rid of 1ae0:0028:00
10367 23:10:27.586122
10368 23:10:27.588920 tpm_get_response: command 0x17b, return code 0x0
10369 23:10:27.589001
10370 23:10:27.592437 ec_init: CrosEC protocol v3 supported (256, 248)
10371 23:10:27.596684
10372 23:10:27.599803 tpm_cleanup: add release locality here.
10373 23:10:27.599885
10374 23:10:27.599948 Shutting down all USB controllers.
10375 23:10:27.602964
10376 23:10:27.603044 Removing current net device
10377 23:10:27.603107
10378 23:10:27.609891 Exiting depthcharge with code 4 at timestamp: 49505219
10379 23:10:27.609973
10380 23:10:27.612776 LZMA decompressing kernel-1 to 0x821a6718
10381 23:10:27.612857
10382 23:10:27.616217 LZMA decompressing kernel-1 to 0x40000000
10383 23:10:29.052007
10384 23:10:29.052155 jumping to kernel
10385 23:10:29.052600 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
10386 23:10:29.052703 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10387 23:10:29.052779 Setting prompt string to ['Linux version [0-9]']
10388 23:10:29.052847 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10389 23:10:29.052914 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10390 23:10:29.135099
10391 23:10:29.139029 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10392 23:10:29.141998 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10393 23:10:29.142090 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10394 23:10:29.142161 Setting prompt string to []
10395 23:10:29.142236 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10396 23:10:29.142312 Using line separator: #'\n'#
10397 23:10:29.142372 No login prompt set.
10398 23:10:29.142435 Parsing kernel messages
10399 23:10:29.142491 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10400 23:10:29.142598 [login-action] Waiting for messages, (timeout 00:04:03)
10401 23:10:29.161874 [ 0.000000] Linux version 6.1.67-cip12-rt7 (KernelCI@build-j59954-arm64-gcc-10-defconfig-arm64-chromebook-nblph) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023
10402 23:10:29.164749 [ 0.000000] random: crng init done
10403 23:10:29.171282 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10404 23:10:29.174799 [ 0.000000] efi: UEFI not found.
10405 23:10:29.180787 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10406 23:10:29.190758 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10407 23:10:29.201270 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10408 23:10:29.207228 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10409 23:10:29.216984 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10410 23:10:29.220242 [ 0.000000] printk: bootconsole [mtk8250] enabled
10411 23:10:29.227566 [ 0.000000] NUMA: No NUMA configuration found
10412 23:10:29.234209 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10413 23:10:29.240397 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10414 23:10:29.240479 [ 0.000000] Zone ranges:
10415 23:10:29.247257 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10416 23:10:29.250157 [ 0.000000] DMA32 empty
10417 23:10:29.257131 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10418 23:10:29.260284 [ 0.000000] Movable zone start for each node
10419 23:10:29.263232 [ 0.000000] Early memory node ranges
10420 23:10:29.270409 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10421 23:10:29.276768 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10422 23:10:29.284125 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10423 23:10:29.289928 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10424 23:10:29.296884 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10425 23:10:29.302985 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10426 23:10:29.359593 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10427 23:10:29.366571 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10428 23:10:29.372912 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10429 23:10:29.375824 [ 0.000000] psci: probing for conduit method from DT.
10430 23:10:29.383377 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10431 23:10:29.386002 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10432 23:10:29.392904 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10433 23:10:29.395937 [ 0.000000] psci: SMC Calling Convention v1.2
10434 23:10:29.402671 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10435 23:10:29.405994 [ 0.000000] Detected VIPT I-cache on CPU0
10436 23:10:29.412286 [ 0.000000] CPU features: detected: GIC system register CPU interface
10437 23:10:29.418973 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10438 23:10:29.426121 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10439 23:10:29.432433 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10440 23:10:29.441991 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10441 23:10:29.448690 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10442 23:10:29.451884 [ 0.000000] alternatives: applying boot alternatives
10443 23:10:29.458606 [ 0.000000] Fallback order for Node 0: 0
10444 23:10:29.465330 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10445 23:10:29.468616 [ 0.000000] Policy zone: Normal
10446 23:10:29.491539 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12395371/extract-nfsrootfs-1s5co7bz,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10447 23:10:29.501616 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10448 23:10:29.512930 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10449 23:10:29.522545 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10450 23:10:29.529210 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10451 23:10:29.532185 <6>[ 0.000000] software IO TLB: area num 8.
10452 23:10:29.588893 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10453 23:10:29.738398 <6>[ 0.000000] Memory: 7951336K/8385536K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 401432K reserved, 32768K cma-reserved)
10454 23:10:29.745185 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10455 23:10:29.751235 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10456 23:10:29.754785 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10457 23:10:29.761416 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10458 23:10:29.768223 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10459 23:10:29.770926 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10460 23:10:29.780842 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10461 23:10:29.787301 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10462 23:10:29.794126 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10463 23:10:29.800586 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10464 23:10:29.803862 <6>[ 0.000000] GICv3: 608 SPIs implemented
10465 23:10:29.807165 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10466 23:10:29.813893 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10467 23:10:29.817026 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10468 23:10:29.823630 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10469 23:10:29.837161 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10470 23:10:29.849982 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10471 23:10:29.857739 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10472 23:10:29.864488 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10473 23:10:29.878176 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10474 23:10:29.884558 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10475 23:10:29.890982 <6>[ 0.009182] Console: colour dummy device 80x25
10476 23:10:29.901202 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10477 23:10:29.907977 <6>[ 0.024416] pid_max: default: 32768 minimum: 301
10478 23:10:29.910789 <6>[ 0.029289] LSM: Security Framework initializing
10479 23:10:29.917540 <6>[ 0.034226] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10480 23:10:29.927555 <6>[ 0.042041] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10481 23:10:29.937821 <6>[ 0.051459] cblist_init_generic: Setting adjustable number of callback queues.
10482 23:10:29.940924 <6>[ 0.058948] cblist_init_generic: Setting shift to 3 and lim to 1.
10483 23:10:29.950924 <6>[ 0.065286] cblist_init_generic: Setting adjustable number of callback queues.
10484 23:10:29.957155 <6>[ 0.072758] cblist_init_generic: Setting shift to 3 and lim to 1.
10485 23:10:29.960480 <6>[ 0.079198] rcu: Hierarchical SRCU implementation.
10486 23:10:29.967116 <6>[ 0.079200] rcu: Max phase no-delay instances is 1000.
10487 23:10:29.973552 <6>[ 0.079224] printk: bootconsole [mtk8250] printing thread started
10488 23:10:29.980510 <6>[ 0.097563] EFI services will not be available.
10489 23:10:29.983507 <6>[ 0.097761] smp: Bringing up secondary CPUs ...
10490 23:10:29.991100 <6>[ 0.098071] Detected VIPT I-cache on CPU1
10491 23:10:29.996758 <6>[ 0.098139] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10492 23:10:30.002590 <6>[ 0.098170] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10493 23:10:30.012454 <6>[ 0.126041] Detected VIPT I-cache on CPU2
10494 23:10:30.019278 <6>[ 0.126087] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10495 23:10:30.028905 <6>[ 0.126103] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10496 23:10:30.032216 <6>[ 0.126357] Detected VIPT I-cache on CPU3
10497 23:10:30.039040 <6>[ 0.126403] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10498 23:10:30.045434 <6>[ 0.126417] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10499 23:10:30.048622 <6>[ 0.126726] CPU features: detected: Spectre-v4
10500 23:10:30.055486 <6>[ 0.126732] CPU features: detected: Spectre-BHB
10501 23:10:30.059298 <6>[ 0.126736] Detected PIPT I-cache on CPU4
10502 23:10:30.065256 <6>[ 0.126795] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10503 23:10:30.071548 <6>[ 0.126811] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10504 23:10:30.078380 <6>[ 0.127102] Detected PIPT I-cache on CPU5
10505 23:10:30.085516 <6>[ 0.127162] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10506 23:10:30.091361 <6>[ 0.127178] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10507 23:10:30.094591 <6>[ 0.127451] Detected PIPT I-cache on CPU6
10508 23:10:30.105512 <6>[ 0.127513] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10509 23:10:30.111083 <6>[ 0.127529] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10510 23:10:30.115966 <6>[ 0.127824] Detected PIPT I-cache on CPU7
10511 23:10:30.121870 <6>[ 0.127887] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10512 23:10:30.127757 <6>[ 0.127903] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10513 23:10:30.131576 <6>[ 0.127949] smp: Brought up 1 node, 8 CPUs
10514 23:10:30.137486 <6>[ 0.127954] SMP: Total of 8 processors activated.
10515 23:10:30.144489 <6>[ 0.127957] CPU features: detected: 32-bit EL0 Support
10516 23:10:30.150939 <6>[ 0.127959] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10517 23:10:30.157549 <6>[ 0.127962] CPU features: detected: Common not Private translations
10518 23:10:30.164182 <6>[ 0.127963] CPU features: detected: CRC32 instructions
10519 23:10:30.170796 <6>[ 0.127966] CPU features: detected: RCpc load-acquire (LDAPR)
10520 23:10:30.174393 <6>[ 0.127967] CPU features: detected: LSE atomic instructions
10521 23:10:30.181094 <6>[ 0.127969] CPU features: detected: Privileged Access Never
10522 23:10:30.187612 <6>[ 0.127970] CPU features: detected: RAS Extension Support
10523 23:10:30.193967 <6>[ 0.127973] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10524 23:10:30.197669 <6>[ 0.128038] CPU: All CPU(s) started at EL2
10525 23:10:30.203804 <6>[ 0.128040] alternatives: applying system-wide alternatives
10526 23:10:30.233375 �Ӌ�er�r�j��<6>[ <0.348822] printk: console [ttyS0] printing thread started
10527 23:10:30.236171 6>[ <6>[ 0.348840] printk: console [ttyS0] enabled
10528 23:10:30.242846 0.225573] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10529 23:10:30.251448 <6>[ 0.348844] printk: bootconsole [mtk8250] disabled
10530 23:10:30.258096 <6>[ 0.366231] printk: bootconsole [mtk8250] printing thread stopped
10531 23:10:30.261261 <6>[ 0.367269] SuperH (H)SCI(F) driver initialized
10532 23:10:30.267649 <6>[ 0.367758] msm_serial: driver initialized
10533 23:10:30.274313 <6>[ 0.372324] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10534 23:10:30.284245 <6>[ 0.372352] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10535 23:10:30.291051 <6>[ 0.372381] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10536 23:10:30.304783 <6>[ 0.372411] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10537 23:10:30.314960 <6>[ 0.372432] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10538 23:10:30.323031 <6>[ 0.372461] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10539 23:10:30.343013 <6>[ 0.372489] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10540 23:10:30.344636 <6>[ 0.372601] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10541 23:10:30.345170 <6>[ 0.372630] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10542 23:10:30.348543 <6>[ 0.384236] loop: module loaded
10543 23:10:30.353183 <6>[ 0.386821] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10544 23:10:30.358979 <4>[ 0.403646] mtk-pmic-keys: Failed to locate of_node [id: -1]
10545 23:10:30.364677 <6>[ 0.404502] megasas: 07.719.03.00-rc1
10546 23:10:30.367906 <6>[ 0.416881] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10547 23:10:30.374599 <6>[ 0.420856] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10548 23:10:30.381215 <6>[ 0.432628] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10549 23:10:30.394685 <6>[ 0.491231] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10550 23:10:30.855523 <6>[ 0.971251] Freeing initrd memory: 17380K
10551 23:10:30.861911 <6>[ 0.977365] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10552 23:10:30.864857 <6>[ 0.982073] tun: Universal TUN/TAP device driver, 1.6
10553 23:10:30.868107 <6>[ 0.982816] thunder_xcv, ver 1.0
10554 23:10:30.871512 <6>[ 0.982833] thunder_bgx, ver 1.0
10555 23:10:30.874970 <6>[ 0.982849] nicpf, ver 1.0
10556 23:10:30.885214 <6>[ 0.983896] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10557 23:10:30.888259 <6>[ 0.983899] hns3: Copyright (c) 2017 Huawei Corporation.
10558 23:10:30.891492 <6>[ 0.983949] hclge is initializing
10559 23:10:30.898124 <6>[ 0.983964] e1000: Intel(R) PRO/1000 Network Driver
10560 23:10:30.905361 <6>[ 0.983966] e1000: Copyright (c) 1999-2006 Intel Corporation.
10561 23:10:30.908877 <6>[ 0.983983] e1000e: Intel(R) PRO/1000 Network Driver
10562 23:10:30.916206 <6>[ 0.983985] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10563 23:10:30.919244 <6>[ 0.984001] igb: Intel(R) Gigabit Ethernet Network Driver
10564 23:10:30.926077 <6>[ 0.984003] igb: Copyright (c) 2007-2014 Intel Corporation.
10565 23:10:30.933176 <6>[ 0.984016] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10566 23:10:30.939803 <6>[ 0.984018] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10567 23:10:30.943218 <6>[ 0.984310] sky2: driver version 1.30
10568 23:10:30.949680 <6>[ 0.985373] VFIO - User Level meta-driver version: 0.3
10569 23:10:30.956062 <6>[ 0.988188] usbcore: registered new interface driver usb-storage
10570 23:10:30.962821 <6>[ 0.988369] usbcore: registered new device driver onboard-usb-hub
10571 23:10:30.965829 <6>[ 0.991134] mt6397-rtc mt6359-rtc: registered as rtc0
10572 23:10:30.976396 <6>[ 0.991283] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-27T23:10:58 UTC (1703718658)
10573 23:10:30.980352 <6>[ 0.991897] i2c_dev: i2c /dev entries driver
10574 23:10:30.989954 <6>[ 0.999073] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10575 23:10:30.992855 <6>[ 1.014057] cpu cpu0: EM: created perf domain
10576 23:10:30.996722 <6>[ 1.014371] cpu cpu4: EM: created perf domain
10577 23:10:31.002727 <6>[ 1.015928] sdhci: Secure Digital Host Controller Interface driver
10578 23:10:31.009959 <6>[ 1.015929] sdhci: Copyright(c) Pierre Ossman
10579 23:10:31.016047 <6>[ 1.016281] Synopsys Designware Multimedia Card Interface Driver
10580 23:10:31.019821 <6>[ 1.016664] sdhci-pltfm: SDHCI platform and OF driver helper
10581 23:10:31.025761 <6>[ 1.020932] ledtrig-cpu: registered to indicate activity on CPUs
10582 23:10:31.028924 <6>[ 1.021551] mmc0: CQHCI version 5.10
10583 23:10:31.039132 <6>[ 1.021608] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10584 23:10:31.042390 <6>[ 1.021882] usbcore: registered new interface driver usbhid
10585 23:10:31.048549 <6>[ 1.021884] usbhid: USB HID core driver
10586 23:10:31.055885 <6>[ 1.022010] spi_master spi0: will run message pump with realtime priority
10587 23:10:31.065197 <6>[ 1.050840] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10588 23:10:31.079041 <6>[ 1.055247] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10589 23:10:31.085413 <6>[ 1.056228] cros-ec-spi spi0.0: Chrome EC device registered
10590 23:10:31.095319 <6>[ 1.068719] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10591 23:10:31.102738 <6>[ 1.069601] NET: Registered PF_PACKET protocol family
10592 23:10:31.105309 <6>[ 1.069672] 9pnet: Installing 9P2000 support
10593 23:10:31.108480 <5>[ 1.069710] Key type dns_resolver registered
10594 23:10:31.114854 <6>[ 1.070197] registered taskstats version 1
10595 23:10:31.118779 <5>[ 1.070214] Loading compiled-in X.509 certificates
10596 23:10:31.129098 <4>[ 1.086992] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10597 23:10:31.141617 <4>[ 1.087252] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10598 23:10:31.148581 <3>[ 1.087269] debugfs: File 'uA_load' in directory '/' already present!
10599 23:10:31.154462 <3>[ 1.087281] debugfs: File 'min_uV' in directory '/' already present!
10600 23:10:31.161253 <3>[ 1.087287] debugfs: File 'max_uV' in directory '/' already present!
10601 23:10:31.168014 <3>[ 1.087294] debugfs: File 'constraint_flags' in directory '/' already present!
10602 23:10:31.174765 <3>[ 1.090735] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10603 23:10:31.181142 <6>[ 1.103288] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10604 23:10:31.188088 <6>[ 1.103880] xhci-mtk 11200000.usb: xHCI Host Controller
10605 23:10:31.194120 <6>[ 1.103900] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10606 23:10:31.204525 <6>[ 1.104125] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10607 23:10:31.211203 <6>[ 1.104189] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10608 23:10:31.217850 <6>[ 1.104297] xhci-mtk 11200000.usb: xHCI Host Controller
10609 23:10:31.224237 <6>[ 1.104305] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10610 23:10:31.231352 <6>[ 1.104313] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10611 23:10:31.234491 <6>[ 1.104836] hub 1-0:1.0: USB hub found
10612 23:10:31.240796 <6>[ 1.104856] hub 1-0:1.0: 1 port detected
10613 23:10:31.247762 <6>[ 1.105072] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10614 23:10:31.251562 <6>[ 1.105454] hub 2-0:1.0: USB hub found
10615 23:10:31.257597 <6>[ 1.105471] hub 2-0:1.0: 1 port detected
10616 23:10:31.261629 <6>[ 1.108299] mtk-msdc 11f70000.mmc: Got CD GPIO
10617 23:10:31.264081 <6>[ 1.115870] mmc0: Command Queue Engine enabled
10618 23:10:31.271299 <6>[ 1.115881] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10619 23:10:31.277110 <6>[ 1.116357] mmcblk0: mmc0:0001 DA4128 116 GiB
10620 23:10:31.283726 <6>[ 1.119551] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10621 23:10:31.287208 <6>[ 1.120916] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10622 23:10:31.294086 <6>[ 1.121817] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10623 23:10:31.300735 <6>[ 1.123074] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10624 23:10:31.307593 <6>[ 1.126416] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10625 23:10:31.313635 <6>[ 1.126423] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10626 23:10:31.324052 <4>[ 1.126513] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10627 23:10:31.333202 <6>[ 1.127004] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10628 23:10:31.341245 <6>[ 1.127005] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10629 23:10:31.346827 <6>[ 1.127132] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10630 23:10:31.356818 <6>[ 1.127141] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10631 23:10:31.362915 <6>[ 1.127143] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10632 23:10:31.373484 <6>[ 1.127147] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10633 23:10:31.380255 <6>[ 1.128184] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10634 23:10:31.389434 <6>[ 1.128198] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10635 23:10:31.395935 <6>[ 1.128202] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10636 23:10:31.405994 <6>[ 1.128206] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10637 23:10:31.412587 <6>[ 1.128209] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10638 23:10:31.422634 <6>[ 1.128213] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10639 23:10:31.432661 <6>[ 1.128217] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10640 23:10:31.439040 <6>[ 1.128221] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10641 23:10:31.448708 <6>[ 1.128224] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10642 23:10:31.455891 <6>[ 1.128228] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10643 23:10:31.465394 <6>[ 1.128231] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10644 23:10:31.472699 <6>[ 1.128235] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10645 23:10:31.481904 <6>[ 1.128239] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10646 23:10:31.488608 <6>[ 1.128242] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10647 23:10:31.498484 <6>[ 1.128248] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10648 23:10:31.504960 <6>[ 1.128516] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10649 23:10:31.512040 <6>[ 1.129083] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10650 23:10:31.518195 <6>[ 1.129315] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10651 23:10:31.524962 <6>[ 1.129611] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10652 23:10:31.531562 <6>[ 1.129932] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10653 23:10:31.538370 <6>[ 1.130106] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10654 23:10:31.548121 <6>[ 1.130117] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10655 23:10:31.558249 <6>[ 1.130119] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10656 23:10:31.567744 <6>[ 1.130122] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10657 23:10:31.578592 <6>[ 1.130125] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10658 23:10:31.587731 <6>[ 1.130127] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10659 23:10:31.594584 <6>[ 1.130130] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10660 23:10:31.604051 <6>[ 1.130133] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10661 23:10:31.613954 <6>[ 1.130135] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10662 23:10:31.624273 <6>[ 1.130139] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10663 23:10:31.633745 <6>[ 1.130142] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10664 23:10:31.643390 <6>[ 1.131017] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10665 23:10:31.650223 <6>[ 1.145113] Trying to probe devices needed for running init ...
10666 23:10:31.656646 <6>[ 1.517528] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10667 23:10:31.660155 <6>[ 1.669861] hub 1-1:1.0: USB hub found
10668 23:10:31.663446 <6>[ 1.670237] hub 1-1:1.0: 4 ports detected
10669 23:10:31.667162 <6>[ 1.672953] hub 1-1:1.0: USB hub found
10670 23:10:31.673626 <6>[ 1.673220] hub 1-1:1.0: 4 ports detected
10671 23:10:31.686450 <6>[ 1.797724] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10672 23:10:31.707379 <6>[ 1.824208] hub 2-1:1.0: USB hub found
10673 23:10:31.711023 <6>[ 1.824702] hub 2-1:1.0: 3 ports detected
10674 23:10:31.713908 <6>[ 1.827699] hub 2-1:1.0: USB hub found
10675 23:10:31.720412 <6>[ 1.828130] hub 2-1:1.0: 3 ports detected
10676 23:10:31.874967 <6>[ 1.985748] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10677 23:10:31.995187 <6>[ 2.111129] hub 1-1.1:1.0: USB hub found
10678 23:10:31.998598 <6>[ 2.111187] hub 1-1.1:1.0: 4 ports detected
10679 23:10:32.106740 <6>[ 2.217527] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10680 23:10:32.227359 <6>[ 2.344531] hub 1-1.4:1.0: USB hub found
10681 23:10:32.230603 <6>[ 2.344851] hub 1-1.4:1.0: 2 ports detected
10682 23:10:32.233882 <6>[ 2.347896] hub 1-1.4:1.0: USB hub found
10683 23:10:32.240547 <6>[ 2.348209] hub 1-1.4:1.0: 2 ports detected
10684 23:10:32.310943 <6>[ 2.421722] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10685 23:10:32.526638 <6>[ 2.637731] usb 1-1.4.1: new high-speed USB device number 6 using xhci-mtk
10686 23:10:32.710783 <6>[ 2.821766] usb 1-1.4.2: new high-speed USB device number 7 using xhci-mtk
10687 23:10:43.324908 <6>[ 13.442759] ALSA device list:
10688 23:10:43.330867 <6>[ 13.442780] No soundcards found.
10689 23:10:43.334579 <6>[ 13.447134] Freeing unused kernel memory: 8448K
10690 23:10:43.337610 <6>[ 13.447284] Run /init as init process
10691 23:10:43.341676 Loading, please wait...
10692 23:10:43.357581 Starting version 247.3-7+deb11u2
10693 23:10:43.569667 <6>[ 13.682722] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10694 23:10:43.578252 <6>[ 13.694220] remoteproc remoteproc0: scp is available
10695 23:10:43.584736 <6>[ 13.694391] remoteproc remoteproc0: powering up scp
10696 23:10:43.591330 <6>[ 13.694398] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10697 23:10:43.597896 <6>[ 13.694465] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10698 23:10:43.604311 <6>[ 13.710693] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10699 23:10:43.614542 <6>[ 13.710753] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10700 23:10:43.621325 <6>[ 13.710769] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10701 23:10:43.630837 <4>[ 13.720190] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10702 23:10:43.637699 <4>[ 13.730051] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10703 23:10:43.644319 <3>[ 13.756167] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10704 23:10:43.654295 <3>[ 13.756180] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 23:10:43.660727 <3>[ 13.756184] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 23:10:43.667187 <6>[ 13.763154] mc: Linux media interface: v0.10
10707 23:10:43.673915 <6>[ 13.763299] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10708 23:10:43.683715 <3>[ 13.764871] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 23:10:43.690675 <3>[ 13.764910] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 23:10:43.697927 <3>[ 13.764917] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 23:10:43.707720 <3>[ 13.764924] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 23:10:43.713972 <3>[ 13.764928] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10713 23:10:43.721950 <3>[ 13.772090] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 23:10:43.731411 <3>[ 13.772265] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 23:10:43.738029 <3>[ 13.772269] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 23:10:43.747635 <3>[ 13.772272] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10717 23:10:43.754456 <3>[ 13.772349] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10718 23:10:43.764313 <3>[ 13.772351] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10719 23:10:43.771066 <3>[ 13.772354] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10720 23:10:43.780959 <3>[ 13.772359] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10721 23:10:43.787645 <3>[ 13.772361] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10722 23:10:43.794365 <3>[ 13.772376] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 23:10:43.801213 <6>[ 13.787864] videodev: Linux video capture interface: v2.00
10724 23:10:43.807643 <6>[ 13.790686] usbcore: registered new interface driver r8152
10725 23:10:43.816721 <4>[ 13.805106] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10726 23:10:43.821466 <4>[ 13.805106] Fallback method does not support PEC.
10727 23:10:43.831112 <6>[ 13.819832] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10728 23:10:43.837217 <6>[ 13.819832] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10729 23:10:43.844059 <6>[ 13.819846] remoteproc remoteproc0: remote processor scp is now up
10730 23:10:43.850174 <3>[ 13.820554] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10731 23:10:43.860293 <6>[ 13.832294] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10732 23:10:43.866876 <6>[ 13.833957] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10733 23:10:43.873134 <6>[ 13.838945] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10734 23:10:43.879820 <6>[ 13.838957] pci_bus 0000:00: root bus resource [bus 00-ff]
10735 23:10:43.887014 <6>[ 13.838964] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10736 23:10:43.896399 <6>[ 13.838970] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10737 23:10:43.903207 <6>[ 13.839004] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10738 23:10:43.909913 <6>[ 13.839024] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10739 23:10:43.915764 <6>[ 13.839100] pci 0000:00:00.0: supports D1 D2
10740 23:10:43.922669 <6>[ 13.839103] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10741 23:10:43.929587 <6>[ 13.840649] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10742 23:10:43.936167 <6>[ 13.840755] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10743 23:10:43.946108 <6>[ 13.840787] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10744 23:10:43.952418 <6>[ 13.840806] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10745 23:10:43.959201 <6>[ 13.840824] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10746 23:10:43.962492 <6>[ 13.840937] pci 0000:01:00.0: supports D1 D2
10747 23:10:43.972335 <6>[ 13.840940] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10748 23:10:43.978855 <3>[ 13.845299] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10749 23:10:43.988834 <6>[ 13.853744] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10750 23:10:43.995389 <6>[ 13.857541] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10751 23:10:44.005797 <6>[ 13.857572] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10752 23:10:44.011978 <6>[ 13.857577] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10753 23:10:44.019021 <6>[ 13.857590] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10754 23:10:44.028377 <6>[ 13.857606] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10755 23:10:44.035017 <6>[ 13.857621] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10756 23:10:44.041509 <6>[ 13.857638] pci 0000:00:00.0: PCI bridge to [bus 01]
10757 23:10:44.048353 <6>[ 13.857645] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10758 23:10:44.054951 <6>[ 13.857774] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10759 23:10:44.061066 <6>[ 13.858703] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10760 23:10:44.068739 <6>[ 13.859062] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10761 23:10:44.077968 <6>[ 13.882668] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10762 23:10:44.088422 <6>[ 13.883120] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10763 23:10:44.094631 <6>[ 13.890736] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10764 23:10:44.100861 <6>[ 13.904588] usbcore: registered new interface driver cdc_ether
10765 23:10:44.107960 <5>[ 13.908294] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10766 23:10:44.115281 <6>[ 13.913140] usbcore: registered new interface driver r8153_ecm
10767 23:10:44.121408 <5>[ 13.924320] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10768 23:10:44.131105 <4>[ 13.924389] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10769 23:10:44.133833 <6>[ 13.924397] cfg80211: failed to load regulatory.db
10770 23:10:44.137158 <6>[ 13.926461] Bluetooth: Core ver 2.22
10771 23:10:44.144409 <6>[ 13.926601] NET: Registered PF_BLUETOOTH protocol family
10772 23:10:44.150505 <6>[ 13.926608] Bluetooth: HCI device and connection manager initialized
10773 23:10:44.156820 <6>[ 13.926679] Bluetooth: HCI socket layer initialized
10774 23:10:44.161165 <6>[ 13.926698] Bluetooth: L2CAP socket layer initialized
10775 23:10:44.167066 <6>[ 13.926726] Bluetooth: SCO socket layer initialized
10776 23:10:44.173210 <6>[ 13.962522] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10777 23:10:44.186722 <6>[ 13.963778] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10778 23:10:44.189666 <6>[ 13.963943] usbcore: registered new interface driver uvcvideo
10779 23:10:44.196600 <6>[ 13.993056] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10780 23:10:44.203184 <6>[ 13.999904] usbcore: registered new interface driver btusb
10781 23:10:44.213036 <4>[ 14.001586] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10782 23:10:44.219939 <3>[ 14.001607] Bluetooth: hci0: Failed to load firmware file (-2)
10783 23:10:44.227302 <3>[ 14.001612] Bluetooth: hci0: Failed to set up firmware (-2)
10784 23:10:44.236347 <4>[ 14.001614] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10785 23:10:44.246164 <4>[ 14.005978] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10786 23:10:44.252978 <4>[ 14.005999] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10787 23:10:44.262465 <6>[ 14.026935] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10788 23:10:44.266164 <6>[ 14.027036] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10789 23:10:44.273143 <6>[ 14.045578] mt7921e 0000:01:00.0: ASIC revision: 79610010
10790 23:10:44.279553 <6>[ 14.057631] r8152 1-1.1.1:1.0 eth0: v1.12.13
10791 23:10:44.282182 <6>[ 14.072066] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10792 23:10:44.292470 <6>[ 14.140397] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10793 23:10:44.295818 <6>[ 14.140397]
10794 23:10:44.301998 <6>[ 14.396634] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10795 23:10:44.306170 Begin: Loading essential drivers ... done.
10796 23:10:44.312481 Begin: Running /scripts/init-premount ... done.
10797 23:10:44.319278 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10798 23:10:44.324986 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10799 23:10:44.331832 Device /sys/class/net/enxf4f5e850de0a found
10800 23:10:44.332384 done.
10801 23:10:44.373212 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10802 23:10:45.118238 <6>[ 15.233516] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10803 23:10:45.586248 <6>[ 15.702302] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10804 23:10:46.371303 IP-Config: no response after 2 secs - giving up
10805 23:10:46.418278 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:47 mtu 1500 DHCP
10806 23:10:47.156791 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10807 23:10:47.160118 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10808 23:10:47.166690 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10809 23:10:47.177159 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10810 23:10:47.183202 host : mt8192-asurada-spherion-r0-cbg-9
10811 23:10:47.190571 domain : lava-rack
10812 23:10:47.193253 rootserver: 192.168.201.1 rootpath:
10813 23:10:47.193810 filename :
10814 23:10:47.298922 done.
10815 23:10:47.306050 Begin: Running /scripts/nfs-bottom ... done.
10816 23:10:47.324912 Begin: Running /scripts/init-bottom ... done.
10817 23:10:48.525274 <6>[ 18.645315] NET: Registered PF_INET6 protocol family
10818 23:10:48.528133 <6>[ 18.647563] Segment Routing with IPv6
10819 23:10:48.535141 <6>[ 18.647575] In-situ OAM (IOAM) with IPv6
10820 23:10:48.641831 <30>[ 18.740055] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10821 23:10:48.644344 <30>[ 18.741057] systemd[1]: Detected architecture arm64.
10822 23:10:48.644765
10823 23:10:48.651218 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10824 23:10:48.651791
10825 23:10:48.669132 <30>[ 18.788181] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10826 23:10:49.568290 <30>[ 19.682668] systemd[1]: Queued start job for default target Graphical Interface.
10827 23:10:49.599664 [[0;32m OK [<30>[ 19.715987] systemd[1]: Created slice system-getty.slice.
10828 23:10:49.602964 0m] Created slice [0;1;39msystem-getty.slice[0m.
10829 23:10:49.622841 [[0;32m OK [0m] Created slic<30>[ 19.739131] systemd[1]: Created slice system-modprobe.slice.
10830 23:10:49.625797 e [0;1;39msystem-modprobe.slice[0m.
10831 23:10:49.646480 [[0;32m OK [0m] Created slic<30>[ 19.762923] systemd[1]: Created slice system-serial\x2dgetty.slice.
10832 23:10:49.652684 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10833 23:10:49.670110 [[0;32m OK [0m] Created slic<30>[ 19.786788] systemd[1]: Created slice User and Session Slice.
10834 23:10:49.673900 e [0;1;39mUser and Session Slice[0m.
10835 23:10:49.697475 [[0;32m OK [0m] Started [0;<30>[ 19.810525] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10836 23:10:49.700778 1;39mDispatch Password …ts to Console Directory Watch[0m.
10837 23:10:49.724603 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 19.837922] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10838 23:10:49.727969 sword R…uests to Wall Directory Watch[0m.
10839 23:10:49.751639 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 19.861857] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10840 23:10:49.758442 <30>[ 19.862039] systemd[1]: Reached target Local Encrypted Volumes.
10841 23:10:49.761631 l Encrypted Volumes[0m.
10842 23:10:49.781169 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 19.897830] systemd[1]: Reached target Paths.
10843 23:10:49.781932 s[0m.
10844 23:10:49.804331 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 19.917700] systemd[1]: Reached target Remote File Systems.
10845 23:10:49.804877 te File Systems[0m.
10846 23:10:49.825562 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 19.941693] systemd[1]: Reached target Slices.
10847 23:10:49.826163 es[0m.
10848 23:10:49.844918 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 19.961706] systemd[1]: Reached target Swap.
10849 23:10:49.845499 [0m.
10850 23:10:49.868912 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 19.982160] systemd[1]: Listening on initctl Compatibility Named Pipe.
10851 23:10:49.871923 l Compatibility Named Pipe[0m.
10852 23:10:49.881851 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.998320] systemd[1]: Listening on Journal Audit Socket.
10853 23:10:49.885425 l Audit Socket[0m.
10854 23:10:49.908218 [[0;32m OK [<30>[ 20.023925] systemd[1]: Listening on Journal Socket (/dev/log).
10855 23:10:49.910381 0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10856 23:10:49.930125 [[0;32m OK [0m] Listening on<30>[ 20.047017] systemd[1]: Listening on Journal Socket.
10857 23:10:49.933612 [0;1;39mJournal Socket[0m.
10858 23:10:49.951578 [[0;32m OK [0m] Listening on<30>[ 20.067548] systemd[1]: Listening on Network Service Netlink Socket.
10859 23:10:49.957167 [0;1;39mNetwork Service Netlink Socket[0m.
10860 23:10:49.977480 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 20.093939] systemd[1]: Listening on udev Control Socket.
10861 23:10:49.980406 ontrol Socket[0m.
10862 23:10:50.001348 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 20.118197] systemd[1]: Listening on udev Kernel Socket.
10863 23:10:50.004799 ernel Socket[0m.
10864 23:10:50.061414 Mounting [0;1;39mHuge Pages File Syste<30>[ 20.174267] systemd[1]: Mounting Huge Pages File System...
10865 23:10:50.061905 m[0m...
10866 23:10:50.078869 Mountin<30>[ 20.196053] systemd[1]: Mounting POSIX Message Queue File System...
10867 23:10:50.082268 g [0;1;39mPOSIX Message Queue File System[0m...
10868 23:10:50.108884 Mounting [0;1;39mKernel Debug File Sys<30>[ 20.221857] systemd[1]: Mounting Kernel Debug File System...
10869 23:10:50.109334 tem[0m...
10870 23:10:50.128754 <30>[ 20.242105] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10871 23:10:50.141407 Starting [0;1;39mCreate list of st…o<30>[ 20.249666] systemd[1]: Starting Create list of static device nodes for the current kernel...
10872 23:10:50.145236 des for the current kernel[0m...
10873 23:10:50.176953 Starting [0;1;39mLoad Kernel Module co<30>[ 20.290408] systemd[1]: Starting Load Kernel Module configfs...
10874 23:10:50.177403 nfigfs[0m...
10875 23:10:50.202609 Starting [0;1;39mLoad <30>[ 20.318839] systemd[1]: Starting Load Kernel Module drm...
10876 23:10:50.205211 Kernel Module drm[0m...
10877 23:10:50.230251 Starting [0;1;39mLoad <30>[ 20.346785] systemd[1]: Starting Load Kernel Module fuse...
10878 23:10:50.233147 Kernel Module fuse[0m...
10879 23:10:50.269798 <6>[ 20.387569] fuse: init (API version 7.37)
10880 23:10:50.279437 <30>[ 20.388870] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10881 23:10:50.329815 Starting [0;1;39mJournal Service[0m..<30>[ 20.446460] systemd[1]: Starting Journal Service...
10882 23:10:50.330386 .
10883 23:10:50.362388 Starting [0;1;39mLoad <30>[ 20.478994] systemd[1]: Starting Load Kernel Modules...
10884 23:10:50.365408 Kernel Modules[0m...
10885 23:10:50.388079 Starting [0;1;39mRemount Root and Kern<30>[ 20.501626] systemd[1]: Starting Remount Root and Kernel File Systems...
10886 23:10:50.391370 el File Systems[0m...
10887 23:10:50.414672 Starting [0;1;39mColdp<30>[ 20.531666] systemd[1]: Starting Coldplug All udev Devices...
10888 23:10:50.417810 lug All udev Devices[0m...
10889 23:10:50.442475 [[0;32m OK [0m] Mounted [0;<30>[ 20.559891] systemd[1]: Mounted Huge Pages File System.
10890 23:10:50.446175 1;39mHuge Pages File System[0m.
10891 23:10:50.468371 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Messa<30>[ 20.582153] systemd[1]: Mounted POSIX Message Queue File System.
10892 23:10:50.468613 ge Queue File System[0m.
10893 23:10:50.488942 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<30>[ 20.606386] systemd[1]: Mounted Kernel Debug File System.
10894 23:10:50.492383 g File System[0m.
10895 23:10:50.518544 [[0;32m OK [<30>[ 20.632481] systemd[1]: Finished Create list of static device nodes for the current kernel.
10896 23:10:50.529206 0m] Finished [0;1;39mCreate lis<3>[ 20.645003] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 23:10:50.532374 t of st… nodes for the current kernel[0m.
10898 23:10:50.554649 [[0;32m OK [0m] Finished [0<30>[ 20.670490] systemd[1]: modprobe@configfs.service: Succeeded.
10899 23:10:50.561420 ;1;39mLoad Kerne<30>[ 20.671203] systemd[1]: Finished Load Kernel Module configfs.
10900 23:10:50.564386 l Module configfs[0m.
10901 23:10:50.574975 <3>[ 20.687776] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 23:10:50.584639 [[0;32m OK [0m] Finished [0<30>[ 20.699454] systemd[1]: modprobe@drm.service: Succeeded.
10903 23:10:50.591149 ;1;39mLoad Kerne<30>[ 20.699959] systemd[1]: Finished Load Kernel Module drm.
10904 23:10:50.591621 l Module drm[0m.
10905 23:10:50.602217 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<30>[ 20.718219] systemd[1]: modprobe@fuse.service: Succeeded.
10906 23:10:50.612003 l Module fuse[0<30>[ 20.718663] systemd[1]: Finished Load Kernel Module fuse.
10907 23:10:50.612470 m.
10908 23:10:50.618330 <3>[ 20.726035] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 23:10:50.630913 [[0;32m OK [0m] Finished [0<30>[ 20.746907] systemd[1]: Finished Load Kernel Modules.
10910 23:10:50.634044 ;1;39mLoad Kernel Modules[0m.
10911 23:10:50.640698 <3>[ 20.756260] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10912 23:10:50.656962 [[0;32m OK [0m] Finished [0;1;39mRemount Ro<30>[ 20.769651] systemd[1]: Finished Remount Root and Kernel File Systems.
10913 23:10:50.660027 ot and Kernel File Systems[0m.
10914 23:10:50.670184 <3>[ 20.781728] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 23:10:50.692748 <3>[ 20.807532] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 23:10:50.702101 Mounting [0;1;39mFUSE Control File Sys<30>[ 20.818412] systemd[1]: Mounting FUSE Control File System...
10917 23:10:50.705815 tem[0m...
10918 23:10:50.712313 <3>[ 20.827754] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 23:10:50.729237 Mounting [0;1;39mKernel Configuration <30>[ 20.841660] systemd[1]: Mounting Kernel Configuration File System...
10920 23:10:50.738193 File System[0m.<3>[ 20.852406] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 23:10:50.738328 ..
10922 23:10:50.767643 Startin<3>[ 20.877573] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 23:10:50.774919 g [0;1;39mLoad/<30>[ 20.877880] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10924 23:10:50.784857 <30>[ 20.878074] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10925 23:10:50.794617 Save Random Seed<30>[ 20.881041] systemd[1]: Starting Load/Save Random Seed...
10926 23:10:50.795057 [0m...
10927 23:10:50.801231 <3>[ 20.898288] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10928 23:10:50.815545 Starting [0;1;39mApply<30>[ 20.931031] systemd[1]: Starting Apply Kernel Variables...
10929 23:10:50.818404 Kernel Variables[0m...
10930 23:10:50.833952 Starting [0;1;39mCreate System Users[0m...
10931 23:10:50.841085 <30>[ 20.953721] systemd[1]: Starting Create System Users...
10932 23:10:50.852517 [[0;32m OK [<30>[ 20.972702] systemd[1]: Started Journal Service.
10933 23:10:50.856020 0m] Started [0;1;39mJournal Service[0m.
10934 23:10:50.874861 <4>[ 20.984308] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10935 23:10:50.881539 <3>[ 20.984331] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10936 23:10:50.888646 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10937 23:10:50.913615 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10938 23:10:50.925770 See 'systemctl status systemd-udev-trigger.service' for details.
10939 23:10:50.942718 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10940 23:10:50.958737 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10941 23:10:50.975214 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10942 23:10:50.991151 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10943 23:10:51.034198 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10944 23:10:51.053544 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10945 23:10:51.108161 <46>[ 21.222971] systemd-journald[305]: Received client request to flush runtime journal.
10946 23:10:51.134948 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10947 23:10:51.149976 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10948 23:10:51.165618 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10949 23:10:51.233554 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10950 23:10:52.495609 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10951 23:10:52.537539 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10952 23:10:52.564044 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10953 23:10:52.586070 Starting [0;1;39mNetwork Service[0m...
10954 23:10:52.907163 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10955 23:10:52.928751 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10956 23:10:52.989058 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10957 23:10:53.255479 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10958 23:10:53.272983 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10959 23:10:53.294349 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10960 23:10:53.309363 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10961 23:10:53.374348 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10962 23:10:53.395761 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10963 23:10:53.458678 Starting [0;1;39mNetwork Name Resolution[0m...
10964 23:10:53.487050 Starting [0;1;39mNetwork Time Synchronization[0m...
10965 23:10:53.506793 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10966 23:10:53.522378 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10967 23:10:53.585694 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10968 23:10:53.923117 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10969 23:10:53.941652 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10970 23:10:53.960723 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10971 23:10:53.973511 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10972 23:10:53.988979 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10973 23:10:54.048237 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10974 23:10:54.098837 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10975 23:10:54.119098 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10976 23:10:54.658288 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10977 23:10:54.672730 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10978 23:10:54.837273 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10979 23:10:54.848732 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10980 23:10:54.865649 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10981 23:10:54.917831 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10982 23:10:55.225125 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10983 23:10:55.264138 Starting [0;1;39mUser Login Management[0m...
10984 23:10:55.282146 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10985 23:10:55.299520 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10986 23:10:55.316494 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10987 23:10:55.377519 Starting [0;1;39mPermit User Sessions[0m...
10988 23:10:55.479724 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10989 23:10:55.537105 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10990 23:10:55.556859 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10991 23:10:55.573515 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10992 23:10:55.598323 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10993 23:10:55.609309 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10994 23:10:55.627377 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10995 23:10:55.645500 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10996 23:10:55.702001 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10997 23:10:55.746459 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10998 23:10:55.827867
10999 23:10:55.828365
11000 23:10:55.830908 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11001 23:10:55.831343
11002 23:10:55.834348 debian-bullseye-arm64 login: root (automatic login)
11003 23:10:55.834788
11004 23:10:55.835225
11005 23:10:56.199231 Linux debian-bullseye-arm64 6.1.67-cip12-rt7 #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023 aarch64
11006 23:10:56.199823
11007 23:10:56.206021 The programs included with the Debian GNU/Linux system are free software;
11008 23:10:56.212639 the exact distribution terms for each program are described in the
11009 23:10:56.215358 individual files in /usr/share/doc/*/copyright.
11010 23:10:56.215813
11011 23:10:56.221968 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11012 23:10:56.225508 permitted by applicable law.
11013 23:10:57.140125 Matched prompt #10: / #
11015 23:10:57.141276 Setting prompt string to ['/ #']
11016 23:10:57.141716 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11018 23:10:57.142700 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11019 23:10:57.143140 start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
11020 23:10:57.143494 Setting prompt string to ['/ #']
11021 23:10:57.143861 Forcing a shell prompt, looking for ['/ #']
11023 23:10:57.194758 / #
11024 23:10:57.195392 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11025 23:10:57.195922 Waiting using forced prompt support (timeout 00:02:30)
11026 23:10:57.201543
11027 23:10:57.202476 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11028 23:10:57.202995 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
11030 23:10:57.304280 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12395371/extract-nfsrootfs-1s5co7bz'
11031 23:10:57.311429 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12395371/extract-nfsrootfs-1s5co7bz'
11033 23:10:57.413070 / # export NFS_SERVER_IP='192.168.201.1'
11034 23:10:57.419639 export NFS_SERVER_IP='192.168.201.1'
11035 23:10:57.420668 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11036 23:10:57.421217 end: 2.2 depthcharge-retry (duration 00:01:25) [common]
11037 23:10:57.421722 end: 2 depthcharge-action (duration 00:01:25) [common]
11038 23:10:57.422252 start: 3 lava-test-retry (timeout 00:07:54) [common]
11039 23:10:57.422769 start: 3.1 lava-test-shell (timeout 00:07:54) [common]
11040 23:10:57.423178 Using namespace: common
11042 23:10:57.524510 / # #
11043 23:10:57.525168 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11044 23:10:57.531504 #
11045 23:10:57.532435 Using /lava-12395371
11047 23:10:57.633797 / # export SHELL=/bin/bash
11048 23:10:57.640219 export SHELL=/bin/bash
11050 23:10:57.741896 / # . /lava-12395371/environment
11051 23:10:57.748195 . /lava-12395371/environment
11053 23:10:57.854910 / # /lava-12395371/bin/lava-test-runner /lava-12395371/0
11054 23:10:57.855557 Test shell timeout: 10s (minimum of the action and connection timeout)
11055 23:10:57.862080 /lava-12395371/bin/lava-test-runner /lava-12395371/0
11056 23:10:58.147204 + export TESTRUN_ID=0_timesync-off
11057 23:10:58.150390 + TESTRUN_ID=0_timesync-off
11058 23:10:58.153403 + cd /lava-12395371/0/tests/0_timesync-off
11059 23:10:58.157144 ++ cat uuid
11060 23:10:58.160630 + UUID=12395371_1.6.2.3.1
11061 23:10:58.161065 + set +x
11062 23:10:58.167572 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12395371_1.6.2.3.1>
11063 23:10:58.168301 Received signal: <STARTRUN> 0_timesync-off 12395371_1.6.2.3.1
11064 23:10:58.168700 Starting test lava.0_timesync-off (12395371_1.6.2.3.1)
11065 23:10:58.169152 Skipping test definition patterns.
11066 23:10:58.170556 + systemctl stop systemd-timesyncd
11067 23:10:58.242004 + set +x
11068 23:10:58.245576 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12395371_1.6.2.3.1>
11069 23:10:58.246251 Received signal: <ENDRUN> 0_timesync-off 12395371_1.6.2.3.1
11070 23:10:58.246654 Ending use of test pattern.
11071 23:10:58.246972 Ending test lava.0_timesync-off (12395371_1.6.2.3.1), duration 0.08
11073 23:10:58.326118 + export TESTRUN_ID=1_kselftest-tpm2
11074 23:10:58.329814 + TESTRUN_ID=1_kselftest-tpm2
11075 23:10:58.336572 + cd /lava-12395371/0/tests/1_kselftest-tpm2
11076 23:10:58.337000 ++ cat uuid
11077 23:10:58.343235 + UUID=12395371_1.6.2.3.5
11078 23:10:58.343656 + set +x
11079 23:10:58.349186 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 12395371_1.6.2.3.5>
11080 23:10:58.349862 Received signal: <STARTRUN> 1_kselftest-tpm2 12395371_1.6.2.3.5
11081 23:10:58.350212 Starting test lava.1_kselftest-tpm2 (12395371_1.6.2.3.5)
11082 23:10:58.350599 Skipping test definition patterns.
11083 23:10:58.352877 + cd ./automated/linux/kselftest/
11084 23:10:58.382155 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11085 23:10:58.425404 INFO: install_deps skipped
11086 23:10:58.543490 --2023-12-27 23:10:58-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11087 23:10:58.550900 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11088 23:10:58.680278 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11089 23:10:58.809733 HTTP request sent, awaiting response... 200 OK
11090 23:10:58.812297 Length: 2966456 (2.8M) [application/octet-stream]
11091 23:10:58.815749 Saving to: 'kselftest.tar.xz'
11092 23:10:58.816297
11093 23:10:58.816653
11094 23:10:59.068593 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11095 23:10:59.327906 kselftest.tar.xz 1%[ ] 43.57K 169KB/s
11096 23:10:59.634850 kselftest.tar.xz 7%[> ] 214.67K 415KB/s
11097 23:10:59.906545 kselftest.tar.xz 28%[====> ] 821.30K 997KB/s
11098 23:11:00.035010 kselftest.tar.xz 67%[============> ] 1.91M 1.74MB/s
11099 23:11:00.040691 kselftest.tar.xz 100%[===================>] 2.83M 2.31MB/s in 1.2s
11100 23:11:00.040778
11101 23:11:00.299564 2023-12-27 23:11:00 (2.31 MB/s) - 'kselftest.tar.xz' saved [2966456/2966456]
11102 23:11:00.299762
11103 23:11:05.840311 skiplist:
11104 23:11:05.843300 ========================================
11105 23:11:05.847026 ========================================
11106 23:11:05.895271 tpm2:test_smoke.sh
11107 23:11:05.898358 tpm2:test_space.sh
11108 23:11:05.915008 ============== Tests to run ===============
11109 23:11:05.918322 tpm2:test_smoke.sh
11110 23:11:05.918744 tpm2:test_space.sh
11111 23:11:05.921754 ===========End Tests to run ===============
11112 23:11:05.924760 shardfile-tpm2 pass
11113 23:11:06.035495 <12>[ 36.154116] kselftest: Running tests in tpm2
11114 23:11:06.041043 TAP version 13
11115 23:11:06.054533 1..2
11116 23:11:06.090446 # selftests: tpm2: test_smoke.sh
11117 23:11:07.568556 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
11118 23:11:07.571862 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
11119 23:11:07.578350 # Exception ignored in: <function Client.__del__ at 0xffffb16a7d30>
11120 23:11:07.581527 # Traceback (most recent call last):
11121 23:11:07.591984 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11122 23:11:07.592467 # if self.tpm:
11123 23:11:07.598346 # AttributeError: 'Client' object has no attribute 'tpm'
11124 23:11:07.601830 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
11125 23:11:07.608291 # Exception ignored in: <function Client.__del__ at 0xffffb16a7d30>
11126 23:11:07.611820 # Traceback (most recent call last):
11127 23:11:07.621895 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11128 23:11:07.624773 # if self.tpm:
11129 23:11:07.627882 # AttributeError: 'Client' object has no attribute 'tpm'
11130 23:11:07.634772 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
11131 23:11:07.641584 # Exception ignored in: <function Client.__del__ at 0xffffb16a7d30>
11132 23:11:07.644996 # Traceback (most recent call last):
11133 23:11:07.655126 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11134 23:11:07.655745 # if self.tpm:
11135 23:11:07.661326 # AttributeError: 'Client' object has no attribute 'tpm'
11136 23:11:07.664841 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
11137 23:11:07.671146 # Exception ignored in: <function Client.__del__ at 0xffffb16a7d30>
11138 23:11:07.674769 # Traceback (most recent call last):
11139 23:11:07.684076 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11140 23:11:07.687610 # if self.tpm:
11141 23:11:07.690588 # AttributeError: 'Client' object has no attribute 'tpm'
11142 23:11:07.697460 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
11143 23:11:07.700999 # Exception ignored in: <function Client.__del__ at 0xffffb16a7d30>
11144 23:11:07.704256 # Traceback (most recent call last):
11145 23:11:07.713798 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11146 23:11:07.717071 # if self.tpm:
11147 23:11:07.721041 # AttributeError: 'Client' object has no attribute 'tpm'
11148 23:11:07.727747 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
11149 23:11:07.734344 # Exception ignored in: <function Client.__del__ at 0xffffb16a7d30>
11150 23:11:07.737498 # Traceback (most recent call last):
11151 23:11:07.747036 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11152 23:11:07.747463 # if self.tpm:
11153 23:11:07.754021 # AttributeError: 'Client' object has no attribute 'tpm'
11154 23:11:07.757137 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
11155 23:11:07.764427 # Exception ignored in: <function Client.__del__ at 0xffffb16a7d30>
11156 23:11:07.767556 # Traceback (most recent call last):
11157 23:11:07.777322 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11158 23:11:07.780073 # if self.tpm:
11159 23:11:07.783531 # AttributeError: 'Client' object has no attribute 'tpm'
11160 23:11:07.790058 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
11161 23:11:07.797169 # Exception ignored in: <function Client.__del__ at 0xffffb16a7d30>
11162 23:11:07.800922 # Traceback (most recent call last):
11163 23:11:07.810502 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11164 23:11:07.811042 # if self.tpm:
11165 23:11:07.816654 # AttributeError: 'Client' object has no attribute 'tpm'
11166 23:11:07.817168 #
11167 23:11:07.823258 # ======================================================================
11168 23:11:07.826392 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
11169 23:11:07.833166 # ----------------------------------------------------------------------
11170 23:11:07.836339 # Traceback (most recent call last):
11171 23:11:07.846723 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11172 23:11:07.852787 # self.root_key = self.client.create_root_key()
11173 23:11:07.866703 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11174 23:11:07.869000 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11175 23:11:07.879776 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11176 23:11:07.883302 # raise ProtocolError(cc, rc)
11177 23:11:07.886203 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11178 23:11:07.886764 #
11179 23:11:07.892937 # ======================================================================
11180 23:11:07.899601 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
11181 23:11:07.906501 # ----------------------------------------------------------------------
11182 23:11:07.909371 # Traceback (most recent call last):
11183 23:11:07.919041 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11184 23:11:07.922498 # self.client = tpm2.Client()
11185 23:11:07.932911 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11186 23:11:07.936001 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11187 23:11:07.942411 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11188 23:11:07.942926 #
11189 23:11:07.949188 # ======================================================================
11190 23:11:07.952276 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
11191 23:11:07.959112 # ----------------------------------------------------------------------
11192 23:11:07.962160 # Traceback (most recent call last):
11193 23:11:07.972044 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11194 23:11:07.975397 # self.client = tpm2.Client()
11195 23:11:07.985115 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11196 23:11:07.992308 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11197 23:11:07.994989 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11198 23:11:07.995415 #
11199 23:11:08.002158 # ======================================================================
11200 23:11:08.008647 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
11201 23:11:08.015212 # ----------------------------------------------------------------------
11202 23:11:08.018345 # Traceback (most recent call last):
11203 23:11:08.028077 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11204 23:11:08.031293 # self.client = tpm2.Client()
11205 23:11:08.041373 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11206 23:11:08.044356 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11207 23:11:08.051655 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11208 23:11:08.052232 #
11209 23:11:08.057741 # ======================================================================
11210 23:11:08.061115 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
11211 23:11:08.068004 # ----------------------------------------------------------------------
11212 23:11:08.071361 # Traceback (most recent call last):
11213 23:11:08.081284 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11214 23:11:08.084510 # self.client = tpm2.Client()
11215 23:11:08.094268 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11216 23:11:08.101618 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11217 23:11:08.104202 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11218 23:11:08.104628 #
11219 23:11:08.111008 # ======================================================================
11220 23:11:08.117470 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
11221 23:11:08.124089 # ----------------------------------------------------------------------
11222 23:11:08.127712 # Traceback (most recent call last):
11223 23:11:08.137517 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11224 23:11:08.141126 # self.client = tpm2.Client()
11225 23:11:08.147531 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11226 23:11:08.154297 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11227 23:11:08.160901 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11228 23:11:08.161465 #
11229 23:11:08.167791 # ======================================================================
11230 23:11:08.170558 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
11231 23:11:08.177362 # ----------------------------------------------------------------------
11232 23:11:08.180746 # Traceback (most recent call last):
11233 23:11:08.190294 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11234 23:11:08.193415 # self.client = tpm2.Client()
11235 23:11:08.203628 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11236 23:11:08.206621 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11237 23:11:08.214428 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11238 23:11:08.214969 #
11239 23:11:08.220621 # ======================================================================
11240 23:11:08.224750 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
11241 23:11:08.231654 # ----------------------------------------------------------------------
11242 23:11:08.234957 # Traceback (most recent call last):
11243 23:11:08.248466 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11244 23:11:08.249032 # self.client = tpm2.Client()
11245 23:11:08.258707 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11246 23:11:08.262875 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11247 23:11:08.268645 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11248 23:11:08.269198 #
11249 23:11:08.276625 # ======================================================================
11250 23:11:08.283394 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11251 23:11:08.286523 # ----------------------------------------------------------------------
11252 23:11:08.289655 # Traceback (most recent call last):
11253 23:11:08.299574 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11254 23:11:08.303216 # self.client = tpm2.Client()
11255 23:11:08.312975 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11256 23:11:08.319168 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11257 23:11:08.322577 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11258 23:11:08.323040 #
11259 23:11:08.329544 # ----------------------------------------------------------------------
11260 23:11:08.332634 # Ran 9 tests in 0.042s
11261 23:11:08.333092 #
11262 23:11:08.335606 # FAILED (errors=9)
11263 23:11:08.339272 # test_async (tpm2_tests.AsyncTest) ... ok
11264 23:11:08.342680 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11265 23:11:08.343187 #
11266 23:11:08.349540 # ----------------------------------------------------------------------
11267 23:11:08.352808 # Ran 2 tests in 0.039s
11268 23:11:08.353271 #
11269 23:11:08.353637 # OK
11270 23:11:08.356275 ok 1 selftests: tpm2: test_smoke.sh
11271 23:11:08.359169 # selftests: tpm2: test_space.sh
11272 23:11:08.366330 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11273 23:11:08.368818 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11274 23:11:08.372532 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11275 23:11:08.378985 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11276 23:11:08.379549 #
11277 23:11:08.385855 # ======================================================================
11278 23:11:08.389045 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11279 23:11:08.395715 # ----------------------------------------------------------------------
11280 23:11:08.398313 # Traceback (most recent call last):
11281 23:11:08.411752 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11282 23:11:08.415346 # root1 = space1.create_root_key()
11283 23:11:08.425155 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11284 23:11:08.428355 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11285 23:11:08.438668 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11286 23:11:08.442239 # raise ProtocolError(cc, rc)
11287 23:11:08.448378 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11288 23:11:08.448948 #
11289 23:11:08.455714 # ======================================================================
11290 23:11:08.461507 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11291 23:11:08.465007 # ----------------------------------------------------------------------
11292 23:11:08.468287 # Traceback (most recent call last):
11293 23:11:08.481332 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11294 23:11:08.484492 # space1.create_root_key()
11295 23:11:08.494805 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11296 23:11:08.500983 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11297 23:11:08.511475 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11298 23:11:08.512084 # raise ProtocolError(cc, rc)
11299 23:11:08.517530 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11300 23:11:08.518143 #
11301 23:11:08.524213 # ======================================================================
11302 23:11:08.530843 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11303 23:11:08.533990 # ----------------------------------------------------------------------
11304 23:11:08.537601 # Traceback (most recent call last):
11305 23:11:08.551208 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11306 23:11:08.554259 # root1 = space1.create_root_key()
11307 23:11:08.564292 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11308 23:11:08.570828 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11309 23:11:08.580328 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11310 23:11:08.584055 # raise ProtocolError(cc, rc)
11311 23:11:08.587204 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11312 23:11:08.590698 #
11313 23:11:08.593537 # ======================================================================
11314 23:11:08.600302 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11315 23:11:08.607072 # ----------------------------------------------------------------------
11316 23:11:08.610467 # Traceback (most recent call last):
11317 23:11:08.620810 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11318 23:11:08.624131 # root1 = space1.create_root_key()
11319 23:11:08.637290 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11320 23:11:08.640790 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11321 23:11:08.650322 # File "/lava-12395371/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11322 23:11:08.653238 # raise ProtocolError(cc, rc)
11323 23:11:08.659811 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11324 23:11:08.660249 #
11325 23:11:08.666405 # ----------------------------------------------------------------------
11326 23:11:08.669922 # Ran 4 tests in 0.086s
11327 23:11:08.670481 #
11328 23:11:08.670970 # FAILED (errors=4)
11329 23:11:08.676440 not ok 2 selftests: tpm2: test_space.sh # exit=1
11330 23:11:08.749140 tpm2_test_smoke_sh pass
11331 23:11:08.752882 tpm2_test_space_sh fail
11332 23:11:08.766699 + ../../utils/send-to-lava.sh ./output/result.txt
11333 23:11:08.842038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11334 23:11:08.842936 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11336 23:11:08.896035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11337 23:11:08.896729 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11339 23:11:08.942820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11340 23:11:08.943651 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11342 23:11:08.945885 + set +x
11343 23:11:08.950174 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 12395371_1.6.2.3.5>
11344 23:11:08.950963 Received signal: <ENDRUN> 1_kselftest-tpm2 12395371_1.6.2.3.5
11345 23:11:08.951348 Ending use of test pattern.
11346 23:11:08.951848 Ending test lava.1_kselftest-tpm2 (12395371_1.6.2.3.5), duration 10.60
11348 23:11:08.952985 <LAVA_TEST_RUNNER EXIT>
11349 23:11:08.953584 ok: lava_test_shell seems to have completed
11350 23:11:08.954087 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11351 23:11:08.954493 end: 3.1 lava-test-shell (duration 00:00:12) [common]
11352 23:11:08.954890 end: 3 lava-test-retry (duration 00:00:12) [common]
11353 23:11:08.955325 start: 4 finalize (timeout 00:07:42) [common]
11354 23:11:08.955811 start: 4.1 power-off (timeout 00:00:30) [common]
11355 23:11:08.956547 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11356 23:11:09.082748 >> Command sent successfully.
11357 23:11:09.087582 Returned 0 in 0 seconds
11358 23:11:09.188681 end: 4.1 power-off (duration 00:00:00) [common]
11360 23:11:09.190270 start: 4.2 read-feedback (timeout 00:07:42) [common]
11361 23:11:09.191588 Listened to connection for namespace 'common' for up to 1s
11362 23:11:10.192084 Finalising connection for namespace 'common'
11363 23:11:10.192793 Disconnecting from shell: Finalise
11364 23:11:10.193263 / #
11365 23:11:10.294281 end: 4.2 read-feedback (duration 00:00:01) [common]
11366 23:11:10.294982 end: 4 finalize (duration 00:00:01) [common]
11367 23:11:10.295580 Cleaning after the job
11368 23:11:10.296156 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395371/tftp-deploy-3o67wms0/ramdisk
11369 23:11:10.310117 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395371/tftp-deploy-3o67wms0/kernel
11370 23:11:10.344685 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395371/tftp-deploy-3o67wms0/dtb
11371 23:11:10.344990 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395371/tftp-deploy-3o67wms0/nfsrootfs
11372 23:11:10.438132 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395371/tftp-deploy-3o67wms0/modules
11373 23:11:10.445436 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12395371
11374 23:11:11.067049 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12395371
11375 23:11:11.067248 Job finished correctly