Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 14
- Kernel Errors: 35
- Errors: 0
1 23:06:35.588827 lava-dispatcher, installed at version: 2023.10
2 23:06:35.589014 start: 0 validate
3 23:06:35.589139 Start time: 2023-12-27 23:06:35.589132+00:00 (UTC)
4 23:06:35.589254 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:06:35.589386 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 23:06:35.864927 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:06:35.865683 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:07:04.882291 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:07:04.883243 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:07:05.152142 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:07:05.152848 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:07:05.681478 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:07:05.682252 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:07:08.686154 validate duration: 33.10
16 23:07:08.686414 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:07:08.686513 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:07:08.686603 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:07:08.686739 Not decompressing ramdisk as can be used compressed.
20 23:07:08.686842 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/initrd.cpio.gz
21 23:07:08.686949 saving as /var/lib/lava/dispatcher/tmp/12395352/tftp-deploy-70s7j2a6/ramdisk/initrd.cpio.gz
22 23:07:08.687048 total size: 4665398 (4 MB)
23 23:07:08.953261 progress 0 % (0 MB)
24 23:07:08.955353 progress 5 % (0 MB)
25 23:07:08.957323 progress 10 % (0 MB)
26 23:07:08.959301 progress 15 % (0 MB)
27 23:07:08.961289 progress 20 % (0 MB)
28 23:07:08.963282 progress 25 % (1 MB)
29 23:07:08.965277 progress 30 % (1 MB)
30 23:07:08.967252 progress 35 % (1 MB)
31 23:07:08.969211 progress 40 % (1 MB)
32 23:07:08.971434 progress 45 % (2 MB)
33 23:07:08.973381 progress 50 % (2 MB)
34 23:07:08.975343 progress 55 % (2 MB)
35 23:07:08.977308 progress 60 % (2 MB)
36 23:07:08.979277 progress 65 % (2 MB)
37 23:07:08.981250 progress 70 % (3 MB)
38 23:07:08.983207 progress 75 % (3 MB)
39 23:07:08.985243 progress 80 % (3 MB)
40 23:07:08.987467 progress 85 % (3 MB)
41 23:07:08.989426 progress 90 % (4 MB)
42 23:07:08.991434 progress 95 % (4 MB)
43 23:07:08.993426 progress 100 % (4 MB)
44 23:07:08.993661 4 MB downloaded in 0.31 s (14.51 MB/s)
45 23:07:08.993883 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:07:08.994279 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:07:08.994414 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:07:08.994547 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:07:08.994741 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:07:08.994851 saving as /var/lib/lava/dispatcher/tmp/12395352/tftp-deploy-70s7j2a6/kernel/Image
52 23:07:08.994954 total size: 50024960 (47 MB)
53 23:07:08.995056 No compression specified
54 23:07:08.996647 progress 0 % (0 MB)
55 23:07:09.009865 progress 5 % (2 MB)
56 23:07:09.022821 progress 10 % (4 MB)
57 23:07:09.035603 progress 15 % (7 MB)
58 23:07:09.048709 progress 20 % (9 MB)
59 23:07:09.061182 progress 25 % (11 MB)
60 23:07:09.073647 progress 30 % (14 MB)
61 23:07:09.086372 progress 35 % (16 MB)
62 23:07:09.098997 progress 40 % (19 MB)
63 23:07:09.111582 progress 45 % (21 MB)
64 23:07:09.124619 progress 50 % (23 MB)
65 23:07:09.137606 progress 55 % (26 MB)
66 23:07:09.150454 progress 60 % (28 MB)
67 23:07:09.163152 progress 65 % (31 MB)
68 23:07:09.175626 progress 70 % (33 MB)
69 23:07:09.188238 progress 75 % (35 MB)
70 23:07:09.200789 progress 80 % (38 MB)
71 23:07:09.213219 progress 85 % (40 MB)
72 23:07:09.226227 progress 90 % (42 MB)
73 23:07:09.239013 progress 95 % (45 MB)
74 23:07:09.251470 progress 100 % (47 MB)
75 23:07:09.251733 47 MB downloaded in 0.26 s (185.79 MB/s)
76 23:07:09.251893 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:07:09.252129 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:07:09.252220 start: 1.3 download-retry (timeout 00:09:59) [common]
80 23:07:09.252307 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 23:07:09.252444 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:07:09.252515 saving as /var/lib/lava/dispatcher/tmp/12395352/tftp-deploy-70s7j2a6/dtb/mt8192-asurada-spherion-r0.dtb
83 23:07:09.252577 total size: 47278 (0 MB)
84 23:07:09.252639 No compression specified
85 23:07:09.253784 progress 69 % (0 MB)
86 23:07:09.254095 progress 100 % (0 MB)
87 23:07:09.254251 0 MB downloaded in 0.00 s (26.98 MB/s)
88 23:07:09.254375 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:07:09.254600 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:07:09.254688 start: 1.4 download-retry (timeout 00:09:59) [common]
92 23:07:09.254772 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 23:07:09.254883 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/full.rootfs.tar.xz
94 23:07:09.254951 saving as /var/lib/lava/dispatcher/tmp/12395352/tftp-deploy-70s7j2a6/nfsrootfs/full.rootfs.tar
95 23:07:09.255013 total size: 89451516 (85 MB)
96 23:07:09.255075 Using unxz to decompress xz
97 23:07:09.259446 progress 0 % (0 MB)
98 23:07:09.470089 progress 5 % (4 MB)
99 23:07:09.686248 progress 10 % (8 MB)
100 23:07:09.938842 progress 15 % (12 MB)
101 23:07:10.131806 progress 20 % (17 MB)
102 23:07:10.226264 progress 25 % (21 MB)
103 23:07:10.472627 progress 30 % (25 MB)
104 23:07:10.756728 progress 35 % (29 MB)
105 23:07:11.017480 progress 40 % (34 MB)
106 23:07:11.288732 progress 45 % (38 MB)
107 23:07:11.537887 progress 50 % (42 MB)
108 23:07:11.801391 progress 55 % (46 MB)
109 23:07:12.051969 progress 60 % (51 MB)
110 23:07:12.317503 progress 65 % (55 MB)
111 23:07:12.613635 progress 70 % (59 MB)
112 23:07:12.910293 progress 75 % (64 MB)
113 23:07:13.202888 progress 80 % (68 MB)
114 23:07:13.456841 progress 85 % (72 MB)
115 23:07:13.683106 progress 90 % (76 MB)
116 23:07:13.941746 progress 95 % (81 MB)
117 23:07:14.204337 progress 100 % (85 MB)
118 23:07:14.210616 85 MB downloaded in 4.96 s (17.21 MB/s)
119 23:07:14.210871 end: 1.4.1 http-download (duration 00:00:05) [common]
121 23:07:14.211150 end: 1.4 download-retry (duration 00:00:05) [common]
122 23:07:14.211273 start: 1.5 download-retry (timeout 00:09:54) [common]
123 23:07:14.211381 start: 1.5.1 http-download (timeout 00:09:54) [common]
124 23:07:14.211538 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:07:14.211613 saving as /var/lib/lava/dispatcher/tmp/12395352/tftp-deploy-70s7j2a6/modules/modules.tar
126 23:07:14.211678 total size: 8633892 (8 MB)
127 23:07:14.211774 Using unxz to decompress xz
128 23:07:14.215524 progress 0 % (0 MB)
129 23:07:14.237092 progress 5 % (0 MB)
130 23:07:14.260231 progress 10 % (0 MB)
131 23:07:14.283674 progress 15 % (1 MB)
132 23:07:14.307450 progress 20 % (1 MB)
133 23:07:14.331449 progress 25 % (2 MB)
134 23:07:14.358770 progress 30 % (2 MB)
135 23:07:14.382825 progress 35 % (2 MB)
136 23:07:14.406546 progress 40 % (3 MB)
137 23:07:14.430943 progress 45 % (3 MB)
138 23:07:14.456148 progress 50 % (4 MB)
139 23:07:14.480229 progress 55 % (4 MB)
140 23:07:14.506691 progress 60 % (4 MB)
141 23:07:14.532482 progress 65 % (5 MB)
142 23:07:14.557291 progress 70 % (5 MB)
143 23:07:14.580446 progress 75 % (6 MB)
144 23:07:14.607298 progress 80 % (6 MB)
145 23:07:14.633070 progress 85 % (7 MB)
146 23:07:14.659732 progress 90 % (7 MB)
147 23:07:14.689043 progress 95 % (7 MB)
148 23:07:14.716595 progress 100 % (8 MB)
149 23:07:14.722246 8 MB downloaded in 0.51 s (16.13 MB/s)
150 23:07:14.722503 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:07:14.722772 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:07:14.722865 start: 1.6 prepare-tftp-overlay (timeout 00:09:54) [common]
154 23:07:14.722965 start: 1.6.1 extract-nfsrootfs (timeout 00:09:54) [common]
155 23:07:16.339857 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12395352/extract-nfsrootfs-u4fj8z19
156 23:07:16.340068 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 23:07:16.340167 start: 1.6.2 lava-overlay (timeout 00:09:52) [common]
158 23:07:16.340333 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw
159 23:07:16.340456 makedir: /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin
160 23:07:16.340554 makedir: /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/tests
161 23:07:16.340673 makedir: /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/results
162 23:07:16.340790 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-add-keys
163 23:07:16.340927 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-add-sources
164 23:07:16.341050 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-background-process-start
165 23:07:16.341179 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-background-process-stop
166 23:07:16.341305 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-common-functions
167 23:07:16.341435 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-echo-ipv4
168 23:07:16.341554 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-install-packages
169 23:07:16.341671 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-installed-packages
170 23:07:16.341787 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-os-build
171 23:07:16.341904 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-probe-channel
172 23:07:16.342058 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-probe-ip
173 23:07:16.342176 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-target-ip
174 23:07:16.342291 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-target-mac
175 23:07:16.342408 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-target-storage
176 23:07:16.342528 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-test-case
177 23:07:16.342647 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-test-event
178 23:07:16.342779 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-test-feedback
179 23:07:16.342897 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-test-raise
180 23:07:16.343012 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-test-reference
181 23:07:16.343129 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-test-runner
182 23:07:16.343244 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-test-set
183 23:07:16.343359 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-test-shell
184 23:07:16.343490 Updating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-install-packages (oe)
185 23:07:16.343637 Updating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/bin/lava-installed-packages (oe)
186 23:07:16.343761 Creating /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/environment
187 23:07:16.343858 LAVA metadata
188 23:07:16.343928 - LAVA_JOB_ID=12395352
189 23:07:16.343991 - LAVA_DISPATCHER_IP=192.168.201.1
190 23:07:16.344098 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:52) [common]
191 23:07:16.344165 skipped lava-vland-overlay
192 23:07:16.344239 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 23:07:16.344317 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:52) [common]
194 23:07:16.344376 skipped lava-multinode-overlay
195 23:07:16.344447 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 23:07:16.344523 start: 1.6.2.3 test-definition (timeout 00:09:52) [common]
197 23:07:16.344597 Loading test definitions
198 23:07:16.344683 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:52) [common]
199 23:07:16.344752 Using /lava-12395352 at stage 0
200 23:07:16.345036 uuid=12395352_1.6.2.3.1 testdef=None
201 23:07:16.345124 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 23:07:16.345207 start: 1.6.2.3.2 test-overlay (timeout 00:09:52) [common]
203 23:07:16.345729 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 23:07:16.345978 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:52) [common]
206 23:07:16.346582 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 23:07:16.346810 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:52) [common]
209 23:07:16.347379 runner path: /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/0/tests/0_lc-compliance test_uuid 12395352_1.6.2.3.1
210 23:07:16.347573 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 23:07:16.347774 Creating lava-test-runner.conf files
213 23:07:16.347835 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12395352/lava-overlay-ibp0xqlw/lava-12395352/0 for stage 0
214 23:07:16.347920 - 0_lc-compliance
215 23:07:16.348012 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 23:07:16.348095 start: 1.6.2.4 compress-overlay (timeout 00:09:52) [common]
217 23:07:16.354192 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 23:07:16.354331 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:52) [common]
219 23:07:16.354416 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 23:07:16.354503 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 23:07:16.354587 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:52) [common]
222 23:07:16.468026 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 23:07:16.468398 start: 1.6.4 extract-modules (timeout 00:09:52) [common]
224 23:07:16.468526 extracting modules file /var/lib/lava/dispatcher/tmp/12395352/tftp-deploy-70s7j2a6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12395352/extract-nfsrootfs-u4fj8z19
225 23:07:16.682173 extracting modules file /var/lib/lava/dispatcher/tmp/12395352/tftp-deploy-70s7j2a6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12395352/extract-overlay-ramdisk-ku2ocawq/ramdisk
226 23:07:16.894519 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 23:07:16.894731 start: 1.6.5 apply-overlay-tftp (timeout 00:09:52) [common]
228 23:07:16.894916 [common] Applying overlay to NFS
229 23:07:16.895040 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12395352/compress-overlay-9rgws0o5/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12395352/extract-nfsrootfs-u4fj8z19
230 23:07:16.901251 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 23:07:16.901390 start: 1.6.6 configure-preseed-file (timeout 00:09:52) [common]
232 23:07:16.901485 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 23:07:16.901576 start: 1.6.7 compress-ramdisk (timeout 00:09:52) [common]
234 23:07:16.901661 Building ramdisk /var/lib/lava/dispatcher/tmp/12395352/extract-overlay-ramdisk-ku2ocawq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12395352/extract-overlay-ramdisk-ku2ocawq/ramdisk
235 23:07:17.197093 >> 119421 blocks
236 23:07:19.104259 rename /var/lib/lava/dispatcher/tmp/12395352/extract-overlay-ramdisk-ku2ocawq/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12395352/tftp-deploy-70s7j2a6/ramdisk/ramdisk.cpio.gz
237 23:07:19.104682 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 23:07:19.104798 start: 1.6.8 prepare-kernel (timeout 00:09:50) [common]
239 23:07:19.104905 start: 1.6.8.1 prepare-fit (timeout 00:09:50) [common]
240 23:07:19.105017 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12395352/tftp-deploy-70s7j2a6/kernel/Image'
241 23:07:31.823692 Returned 0 in 12 seconds
242 23:07:31.924296 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12395352/tftp-deploy-70s7j2a6/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12395352/tftp-deploy-70s7j2a6/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12395352/tftp-deploy-70s7j2a6/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12395352/tftp-deploy-70s7j2a6/kernel/image.itb
243 23:07:32.258360 output: FIT description: Kernel Image image with one or more FDT blobs
244 23:07:32.258721 output: Created: Wed Dec 27 23:07:32 2023
245 23:07:32.258799 output: Image 0 (kernel-1)
246 23:07:32.258902 output: Description:
247 23:07:32.258981 output: Created: Wed Dec 27 23:07:32 2023
248 23:07:32.259044 output: Type: Kernel Image
249 23:07:32.259105 output: Compression: lzma compressed
250 23:07:32.259167 output: Data Size: 11480388 Bytes = 11211.32 KiB = 10.95 MiB
251 23:07:32.259229 output: Architecture: AArch64
252 23:07:32.259291 output: OS: Linux
253 23:07:32.259406 output: Load Address: 0x00000000
254 23:07:32.259525 output: Entry Point: 0x00000000
255 23:07:32.259615 output: Hash algo: crc32
256 23:07:32.259672 output: Hash value: a55b2f0b
257 23:07:32.259730 output: Image 1 (fdt-1)
258 23:07:32.259785 output: Description: mt8192-asurada-spherion-r0
259 23:07:32.259839 output: Created: Wed Dec 27 23:07:32 2023
260 23:07:32.259893 output: Type: Flat Device Tree
261 23:07:32.259947 output: Compression: uncompressed
262 23:07:32.260000 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
263 23:07:32.260054 output: Architecture: AArch64
264 23:07:32.260108 output: Hash algo: crc32
265 23:07:32.260161 output: Hash value: cc4352de
266 23:07:32.260214 output: Image 2 (ramdisk-1)
267 23:07:32.260267 output: Description: unavailable
268 23:07:32.260320 output: Created: Wed Dec 27 23:07:32 2023
269 23:07:32.260375 output: Type: RAMDisk Image
270 23:07:32.260429 output: Compression: Unknown Compression
271 23:07:32.260483 output: Data Size: 17802928 Bytes = 17385.67 KiB = 16.98 MiB
272 23:07:32.260537 output: Architecture: AArch64
273 23:07:32.260590 output: OS: Linux
274 23:07:32.260643 output: Load Address: unavailable
275 23:07:32.260696 output: Entry Point: unavailable
276 23:07:32.260749 output: Hash algo: crc32
277 23:07:32.260803 output: Hash value: 39768309
278 23:07:32.260856 output: Default Configuration: 'conf-1'
279 23:07:32.260909 output: Configuration 0 (conf-1)
280 23:07:32.260962 output: Description: mt8192-asurada-spherion-r0
281 23:07:32.261016 output: Kernel: kernel-1
282 23:07:32.261070 output: Init Ramdisk: ramdisk-1
283 23:07:32.261122 output: FDT: fdt-1
284 23:07:32.261175 output: Loadables: kernel-1
285 23:07:32.261228 output:
286 23:07:32.261423 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
287 23:07:32.261521 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
288 23:07:32.261626 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 23:07:32.261718 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:36) [common]
290 23:07:32.261801 No LXC device requested
291 23:07:32.261880 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 23:07:32.261991 start: 1.8 deploy-device-env (timeout 00:09:36) [common]
293 23:07:32.262085 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 23:07:32.262153 Checking files for TFTP limit of 4294967296 bytes.
295 23:07:32.262629 end: 1 tftp-deploy (duration 00:00:24) [common]
296 23:07:32.262731 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 23:07:32.262822 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 23:07:32.262949 substitutions:
299 23:07:32.263015 - {DTB}: 12395352/tftp-deploy-70s7j2a6/dtb/mt8192-asurada-spherion-r0.dtb
300 23:07:32.263082 - {INITRD}: 12395352/tftp-deploy-70s7j2a6/ramdisk/ramdisk.cpio.gz
301 23:07:32.263143 - {KERNEL}: 12395352/tftp-deploy-70s7j2a6/kernel/Image
302 23:07:32.263200 - {LAVA_MAC}: None
303 23:07:32.263257 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12395352/extract-nfsrootfs-u4fj8z19
304 23:07:32.263345 - {NFS_SERVER_IP}: 192.168.201.1
305 23:07:32.263405 - {PRESEED_CONFIG}: None
306 23:07:32.263460 - {PRESEED_LOCAL}: None
307 23:07:32.263516 - {RAMDISK}: 12395352/tftp-deploy-70s7j2a6/ramdisk/ramdisk.cpio.gz
308 23:07:32.263571 - {ROOT_PART}: None
309 23:07:32.263625 - {ROOT}: None
310 23:07:32.263679 - {SERVER_IP}: 192.168.201.1
311 23:07:32.263733 - {TEE}: None
312 23:07:32.263787 Parsed boot commands:
313 23:07:32.263842 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 23:07:32.264014 Parsed boot commands: tftpboot 192.168.201.1 12395352/tftp-deploy-70s7j2a6/kernel/image.itb 12395352/tftp-deploy-70s7j2a6/kernel/cmdline
315 23:07:32.264103 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 23:07:32.264186 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 23:07:32.264277 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 23:07:32.264365 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 23:07:32.264439 Not connected, no need to disconnect.
320 23:07:32.264512 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 23:07:32.264595 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 23:07:32.264665 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
323 23:07:32.268133 Setting prompt string to ['lava-test: # ']
324 23:07:32.268473 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 23:07:32.268579 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 23:07:32.268681 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 23:07:32.268806 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 23:07:32.268993 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
329 23:07:37.400950 >> Command sent successfully.
330 23:07:37.403401 Returned 0 in 5 seconds
331 23:07:37.503825 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 23:07:37.504176 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 23:07:37.504275 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 23:07:37.504362 Setting prompt string to 'Starting depthcharge on Spherion...'
336 23:07:37.504430 Changing prompt to 'Starting depthcharge on Spherion...'
337 23:07:37.504498 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 23:07:37.504758 [Enter `^Ec?' for help]
339 23:07:37.676056
340 23:07:37.676251
341 23:07:37.676355 F0: 102B 0000
342 23:07:37.676455
343 23:07:37.676545 F3: 1001 0000 [0200]
344 23:07:37.679045
345 23:07:37.679132 F3: 1001 0000
346 23:07:37.679200
347 23:07:37.679264 F7: 102D 0000
348 23:07:37.679329
349 23:07:37.682534 F1: 0000 0000
350 23:07:37.682626
351 23:07:37.682694 V0: 0000 0000 [0001]
352 23:07:37.682757
353 23:07:37.686170 00: 0007 8000
354 23:07:37.686260
355 23:07:37.686334 01: 0000 0000
356 23:07:37.686401
357 23:07:37.689321 BP: 0C00 0209 [0000]
358 23:07:37.689408
359 23:07:37.689476 G0: 1182 0000
360 23:07:37.689539
361 23:07:37.692368 EC: 0000 0021 [4000]
362 23:07:37.692457
363 23:07:37.692526 S7: 0000 0000 [0000]
364 23:07:37.692590
365 23:07:37.695999 CC: 0000 0000 [0001]
366 23:07:37.696086
367 23:07:37.696156 T0: 0000 0040 [010F]
368 23:07:37.696221
369 23:07:37.698985 Jump to BL
370 23:07:37.699075
371 23:07:37.723518
372 23:07:37.723676
373 23:07:37.723749
374 23:07:37.731178 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 23:07:37.734710 ARM64: Exception handlers installed.
376 23:07:37.737932 ARM64: Testing exception
377 23:07:37.738052 ARM64: Done test exception
378 23:07:37.748028 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 23:07:37.758125 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 23:07:37.765685 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 23:07:37.775488 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 23:07:37.782050 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 23:07:37.788740 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 23:07:37.799374 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 23:07:37.806630 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 23:07:37.825725 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 23:07:37.829154 WDT: Last reset was cold boot
388 23:07:37.832216 SPI1(PAD0) initialized at 2873684 Hz
389 23:07:37.835556 SPI5(PAD0) initialized at 992727 Hz
390 23:07:37.839237 VBOOT: Loading verstage.
391 23:07:37.845930 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 23:07:37.849241 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 23:07:37.852316 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 23:07:37.855854 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 23:07:37.863229 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 23:07:37.869902 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 23:07:37.880739 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
398 23:07:37.880879
399 23:07:37.880956
400 23:07:37.890818 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 23:07:37.894241 ARM64: Exception handlers installed.
402 23:07:37.897340 ARM64: Testing exception
403 23:07:37.897433 ARM64: Done test exception
404 23:07:37.904013 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 23:07:37.907626 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 23:07:37.921875 Probing TPM: . done!
407 23:07:37.922057 TPM ready after 0 ms
408 23:07:37.928320 Connected to device vid:did:rid of 1ae0:0028:00
409 23:07:37.935501 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
410 23:07:37.991523 Initialized TPM device CR50 revision 0
411 23:07:38.003711 tlcl_send_startup: Startup return code is 0
412 23:07:38.003864 TPM: setup succeeded
413 23:07:38.015243 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 23:07:38.023780 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 23:07:38.033917 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 23:07:38.043372 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 23:07:38.046774 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 23:07:38.055296 in-header: 03 07 00 00 08 00 00 00
419 23:07:38.058921 in-data: aa e4 47 04 13 02 00 00
420 23:07:38.062578 Chrome EC: UHEPI supported
421 23:07:38.069810 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 23:07:38.073475 in-header: 03 ad 00 00 08 00 00 00
423 23:07:38.076821 in-data: 00 20 20 08 00 00 00 00
424 23:07:38.076947 Phase 1
425 23:07:38.080687 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 23:07:38.088142 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 23:07:38.091901 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 23:07:38.096570 Recovery requested (1009000e)
429 23:07:38.105448 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 23:07:38.110598 tlcl_extend: response is 0
431 23:07:38.120032 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 23:07:38.125892 tlcl_extend: response is 0
433 23:07:38.132771 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 23:07:38.153067 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
435 23:07:38.160051 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 23:07:38.160185
437 23:07:38.160262
438 23:07:38.170177 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 23:07:38.173240 ARM64: Exception handlers installed.
440 23:07:38.173342 ARM64: Testing exception
441 23:07:38.177000 ARM64: Done test exception
442 23:07:38.198286 pmic_efuse_setting: Set efuses in 11 msecs
443 23:07:38.201913 pmwrap_interface_init: Select PMIF_VLD_RDY
444 23:07:38.208653 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 23:07:38.212273 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 23:07:38.215501 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 23:07:38.222181 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 23:07:38.225246 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 23:07:38.232981 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 23:07:38.236964 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 23:07:38.240393 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 23:07:38.243976 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 23:07:38.251936 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 23:07:38.255486 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 23:07:38.259512 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 23:07:38.262671 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 23:07:38.269530 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 23:07:38.276547 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 23:07:38.283345 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 23:07:38.287171 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 23:07:38.294487 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 23:07:38.297931 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 23:07:38.304574 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 23:07:38.308239 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 23:07:38.315509 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 23:07:38.322307 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 23:07:38.325476 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 23:07:38.332448 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 23:07:38.339352 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 23:07:38.342286 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 23:07:38.348656 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 23:07:38.351978 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 23:07:38.355572 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 23:07:38.362414 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 23:07:38.365466 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 23:07:38.372084 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 23:07:38.375510 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 23:07:38.382548 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 23:07:38.385982 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 23:07:38.392436 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 23:07:38.395556 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 23:07:38.402628 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 23:07:38.406357 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 23:07:38.409736 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 23:07:38.413037 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 23:07:38.419655 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 23:07:38.423293 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 23:07:38.426659 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 23:07:38.433026 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 23:07:38.436782 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 23:07:38.440095 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 23:07:38.446488 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 23:07:38.450151 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 23:07:38.453252 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 23:07:38.460068 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 23:07:38.470115 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 23:07:38.473317 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 23:07:38.483375 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 23:07:38.489918 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 23:07:38.496868 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 23:07:38.499923 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 23:07:38.503261 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 23:07:38.510906 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x21
504 23:07:38.517247 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 23:07:38.520456 [RTC]rtc_osc_init,62: osc32con val = 0xde70
506 23:07:38.527406 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 23:07:38.535017 [RTC]rtc_get_frequency_meter,154: input=15, output=774
508 23:07:38.545126 [RTC]rtc_get_frequency_meter,154: input=23, output=957
509 23:07:38.554166 [RTC]rtc_get_frequency_meter,154: input=19, output=865
510 23:07:38.563993 [RTC]rtc_get_frequency_meter,154: input=17, output=818
511 23:07:38.573193 [RTC]rtc_get_frequency_meter,154: input=16, output=795
512 23:07:38.577038 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
513 23:07:38.583268 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
514 23:07:38.586827 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
515 23:07:38.589922 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
516 23:07:38.593467 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
517 23:07:38.597000 ADC[4]: Raw value=902507 ID=7
518 23:07:38.600716 ADC[3]: Raw value=213179 ID=1
519 23:07:38.600801 RAM Code: 0x71
520 23:07:38.606837 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
521 23:07:38.610490 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
522 23:07:38.621137 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
523 23:07:38.624785 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
524 23:07:38.628311 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
525 23:07:38.632295 in-header: 03 07 00 00 08 00 00 00
526 23:07:38.635844 in-data: aa e4 47 04 13 02 00 00
527 23:07:38.639679 Chrome EC: UHEPI supported
528 23:07:38.647032 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
529 23:07:38.650867 in-header: 03 ed 00 00 08 00 00 00
530 23:07:38.654157 in-data: 80 20 60 08 00 00 00 00
531 23:07:38.654248 MRC: failed to locate region type 0.
532 23:07:38.661831 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
533 23:07:38.665710 DRAM-K: Running full calibration
534 23:07:38.672848 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
535 23:07:38.673082 header.status = 0x0
536 23:07:38.676696 header.version = 0x6 (expected: 0x6)
537 23:07:38.680067 header.size = 0xd00 (expected: 0xd00)
538 23:07:38.680213 header.flags = 0x0
539 23:07:38.686552 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
540 23:07:38.705304 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
541 23:07:38.712054 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
542 23:07:38.715310 dram_init: ddr_geometry: 2
543 23:07:38.718898 [EMI] MDL number = 2
544 23:07:38.718994 [EMI] Get MDL freq = 0
545 23:07:38.721958 dram_init: ddr_type: 0
546 23:07:38.722068 is_discrete_lpddr4: 1
547 23:07:38.725323 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
548 23:07:38.725411
549 23:07:38.725479
550 23:07:38.728592 [Bian_co] ETT version 0.0.0.1
551 23:07:38.735901 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
552 23:07:38.736016
553 23:07:38.739923 dramc_set_vcore_voltage set vcore to 650000
554 23:07:38.740022 Read voltage for 800, 4
555 23:07:38.740125 Vio18 = 0
556 23:07:38.743228 Vcore = 650000
557 23:07:38.743349 Vdram = 0
558 23:07:38.743437 Vddq = 0
559 23:07:38.747493 Vmddr = 0
560 23:07:38.747613 dram_init: config_dvfs: 1
561 23:07:38.751159 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
562 23:07:38.758726 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
563 23:07:38.762126 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
564 23:07:38.765389 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
565 23:07:38.768837 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
566 23:07:38.772222 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
567 23:07:38.775447 MEM_TYPE=3, freq_sel=18
568 23:07:38.778940 sv_algorithm_assistance_LP4_1600
569 23:07:38.781936 ============ PULL DRAM RESETB DOWN ============
570 23:07:38.785563 ========== PULL DRAM RESETB DOWN end =========
571 23:07:38.792308 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
572 23:07:38.795672 ===================================
573 23:07:38.798829 LPDDR4 DRAM CONFIGURATION
574 23:07:38.802153 ===================================
575 23:07:38.802248 EX_ROW_EN[0] = 0x0
576 23:07:38.805855 EX_ROW_EN[1] = 0x0
577 23:07:38.805995 LP4Y_EN = 0x0
578 23:07:38.808849 WORK_FSP = 0x0
579 23:07:38.808952 WL = 0x2
580 23:07:38.812163 RL = 0x2
581 23:07:38.812253 BL = 0x2
582 23:07:38.815976 RPST = 0x0
583 23:07:38.816066 RD_PRE = 0x0
584 23:07:38.819239 WR_PRE = 0x1
585 23:07:38.819326 WR_PST = 0x0
586 23:07:38.822305 DBI_WR = 0x0
587 23:07:38.822394 DBI_RD = 0x0
588 23:07:38.825897 OTF = 0x1
589 23:07:38.829145 ===================================
590 23:07:38.832529 ===================================
591 23:07:38.832622 ANA top config
592 23:07:38.835667 ===================================
593 23:07:38.839151 DLL_ASYNC_EN = 0
594 23:07:38.842401 ALL_SLAVE_EN = 1
595 23:07:38.845637 NEW_RANK_MODE = 1
596 23:07:38.845733 DLL_IDLE_MODE = 1
597 23:07:38.849138 LP45_APHY_COMB_EN = 1
598 23:07:38.852598 TX_ODT_DIS = 1
599 23:07:38.855820 NEW_8X_MODE = 1
600 23:07:38.859142 ===================================
601 23:07:38.862779 ===================================
602 23:07:38.862875 data_rate = 1600
603 23:07:38.865833 CKR = 1
604 23:07:38.869355 DQ_P2S_RATIO = 8
605 23:07:38.872622 ===================================
606 23:07:38.876084 CA_P2S_RATIO = 8
607 23:07:38.879313 DQ_CA_OPEN = 0
608 23:07:38.882712 DQ_SEMI_OPEN = 0
609 23:07:38.882811 CA_SEMI_OPEN = 0
610 23:07:38.886207 CA_FULL_RATE = 0
611 23:07:38.889458 DQ_CKDIV4_EN = 1
612 23:07:38.892665 CA_CKDIV4_EN = 1
613 23:07:38.896258 CA_PREDIV_EN = 0
614 23:07:38.899541 PH8_DLY = 0
615 23:07:38.899627 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
616 23:07:38.902861 DQ_AAMCK_DIV = 4
617 23:07:38.905837 CA_AAMCK_DIV = 4
618 23:07:38.909704 CA_ADMCK_DIV = 4
619 23:07:38.913113 DQ_TRACK_CA_EN = 0
620 23:07:38.916146 CA_PICK = 800
621 23:07:38.916262 CA_MCKIO = 800
622 23:07:38.919673 MCKIO_SEMI = 0
623 23:07:38.922833 PLL_FREQ = 3068
624 23:07:38.926242 DQ_UI_PI_RATIO = 32
625 23:07:38.929779 CA_UI_PI_RATIO = 0
626 23:07:38.932779 ===================================
627 23:07:38.936014 ===================================
628 23:07:38.936106 memory_type:LPDDR4
629 23:07:38.939781 GP_NUM : 10
630 23:07:38.942614 SRAM_EN : 1
631 23:07:38.942696 MD32_EN : 0
632 23:07:38.946241 ===================================
633 23:07:38.950181 [ANA_INIT] >>>>>>>>>>>>>>
634 23:07:38.953626 <<<<<< [CONFIGURE PHASE]: ANA_TX
635 23:07:38.957441 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
636 23:07:38.961022 ===================================
637 23:07:38.961112 data_rate = 1600,PCW = 0X7600
638 23:07:38.964762 ===================================
639 23:07:38.968112 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
640 23:07:38.975163 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
641 23:07:38.978869 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
642 23:07:38.982443 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
643 23:07:38.986398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
644 23:07:38.990126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
645 23:07:38.993880 [ANA_INIT] flow start
646 23:07:38.994000 [ANA_INIT] PLL >>>>>>>>
647 23:07:38.997530 [ANA_INIT] PLL <<<<<<<<
648 23:07:39.001138 [ANA_INIT] MIDPI >>>>>>>>
649 23:07:39.001232 [ANA_INIT] MIDPI <<<<<<<<
650 23:07:39.004870 [ANA_INIT] DLL >>>>>>>>
651 23:07:39.008200 [ANA_INIT] flow end
652 23:07:39.011819 ============ LP4 DIFF to SE enter ============
653 23:07:39.015411 ============ LP4 DIFF to SE exit ============
654 23:07:39.015554 [ANA_INIT] <<<<<<<<<<<<<
655 23:07:39.018988 [Flow] Enable top DCM control >>>>>
656 23:07:39.023250 [Flow] Enable top DCM control <<<<<
657 23:07:39.026486 Enable DLL master slave shuffle
658 23:07:39.033829 ==============================================================
659 23:07:39.034009 Gating Mode config
660 23:07:39.041353 ==============================================================
661 23:07:39.041465 Config description:
662 23:07:39.053121 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
663 23:07:39.056477 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
664 23:07:39.064036 SELPH_MODE 0: By rank 1: By Phase
665 23:07:39.067567 ==============================================================
666 23:07:39.071673 GAT_TRACK_EN = 1
667 23:07:39.075350 RX_GATING_MODE = 2
668 23:07:39.078775 RX_GATING_TRACK_MODE = 2
669 23:07:39.078913 SELPH_MODE = 1
670 23:07:39.082238 PICG_EARLY_EN = 1
671 23:07:39.086345 VALID_LAT_VALUE = 1
672 23:07:39.090044 ==============================================================
673 23:07:39.094109 Enter into Gating configuration >>>>
674 23:07:39.097601 Exit from Gating configuration <<<<
675 23:07:39.101335 Enter into DVFS_PRE_config >>>>>
676 23:07:39.111701 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
677 23:07:39.115923 Exit from DVFS_PRE_config <<<<<
678 23:07:39.119348 Enter into PICG configuration >>>>
679 23:07:39.123052 Exit from PICG configuration <<<<
680 23:07:39.123145 [RX_INPUT] configuration >>>>>
681 23:07:39.126743 [RX_INPUT] configuration <<<<<
682 23:07:39.134499 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
683 23:07:39.137878 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
684 23:07:39.145413 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
685 23:07:39.149278 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
686 23:07:39.156459 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
687 23:07:39.163527 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
688 23:07:39.167215 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
689 23:07:39.170962 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
690 23:07:39.174760 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
691 23:07:39.178873 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
692 23:07:39.182490 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
693 23:07:39.186220 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
694 23:07:39.189963 ===================================
695 23:07:39.193314 LPDDR4 DRAM CONFIGURATION
696 23:07:39.196997 ===================================
697 23:07:39.197105 EX_ROW_EN[0] = 0x0
698 23:07:39.200883 EX_ROW_EN[1] = 0x0
699 23:07:39.200993 LP4Y_EN = 0x0
700 23:07:39.204647 WORK_FSP = 0x0
701 23:07:39.204754 WL = 0x2
702 23:07:39.208556 RL = 0x2
703 23:07:39.208670 BL = 0x2
704 23:07:39.211822 RPST = 0x0
705 23:07:39.211928 RD_PRE = 0x0
706 23:07:39.215525 WR_PRE = 0x1
707 23:07:39.215621 WR_PST = 0x0
708 23:07:39.219417 DBI_WR = 0x0
709 23:07:39.219525 DBI_RD = 0x0
710 23:07:39.219609 OTF = 0x1
711 23:07:39.223220 ===================================
712 23:07:39.226883 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
713 23:07:39.234534 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
714 23:07:39.238253 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
715 23:07:39.241878 ===================================
716 23:07:39.242013 LPDDR4 DRAM CONFIGURATION
717 23:07:39.245774 ===================================
718 23:07:39.249523 EX_ROW_EN[0] = 0x10
719 23:07:39.249626 EX_ROW_EN[1] = 0x0
720 23:07:39.253170 LP4Y_EN = 0x0
721 23:07:39.253301 WORK_FSP = 0x0
722 23:07:39.256349 WL = 0x2
723 23:07:39.256466 RL = 0x2
724 23:07:39.260211 BL = 0x2
725 23:07:39.260368 RPST = 0x0
726 23:07:39.263924 RD_PRE = 0x0
727 23:07:39.264018 WR_PRE = 0x1
728 23:07:39.264108 WR_PST = 0x0
729 23:07:39.267749 DBI_WR = 0x0
730 23:07:39.267839 DBI_RD = 0x0
731 23:07:39.270981 OTF = 0x1
732 23:07:39.274791 ===================================
733 23:07:39.278468 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
734 23:07:39.284556 nWR fixed to 40
735 23:07:39.287534 [ModeRegInit_LP4] CH0 RK0
736 23:07:39.287647 [ModeRegInit_LP4] CH0 RK1
737 23:07:39.291365 [ModeRegInit_LP4] CH1 RK0
738 23:07:39.295041 [ModeRegInit_LP4] CH1 RK1
739 23:07:39.295200 match AC timing 13
740 23:07:39.298359 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
741 23:07:39.301636 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
742 23:07:39.308155 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
743 23:07:39.311777 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
744 23:07:39.318362 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
745 23:07:39.318485 [EMI DOE] emi_dcm 0
746 23:07:39.321918 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
747 23:07:39.324882 ==
748 23:07:39.325006 Dram Type= 6, Freq= 0, CH_0, rank 0
749 23:07:39.332375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
750 23:07:39.332521 ==
751 23:07:39.335293 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
752 23:07:39.341648 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
753 23:07:39.351696 [CA 0] Center 38 (7~69) winsize 63
754 23:07:39.354840 [CA 1] Center 38 (7~69) winsize 63
755 23:07:39.358387 [CA 2] Center 35 (5~66) winsize 62
756 23:07:39.361385 [CA 3] Center 35 (5~66) winsize 62
757 23:07:39.364890 [CA 4] Center 34 (4~65) winsize 62
758 23:07:39.368192 [CA 5] Center 33 (3~64) winsize 62
759 23:07:39.368315
760 23:07:39.371645 [CmdBusTrainingLP45] Vref(ca) range 1: 32
761 23:07:39.371765
762 23:07:39.374942 [CATrainingPosCal] consider 1 rank data
763 23:07:39.378214 u2DelayCellTimex100 = 270/100 ps
764 23:07:39.381363 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
765 23:07:39.384717 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
766 23:07:39.391563 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
767 23:07:39.394974 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
768 23:07:39.398202 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
769 23:07:39.401624 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
770 23:07:39.401747
771 23:07:39.404910 CA PerBit enable=1, Macro0, CA PI delay=33
772 23:07:39.405000
773 23:07:39.408614 [CBTSetCACLKResult] CA Dly = 33
774 23:07:39.408704 CS Dly: 6 (0~37)
775 23:07:39.411674 ==
776 23:07:39.411763 Dram Type= 6, Freq= 0, CH_0, rank 1
777 23:07:39.418167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
778 23:07:39.418272 ==
779 23:07:39.421410 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
780 23:07:39.428319 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
781 23:07:39.437976 [CA 0] Center 38 (7~69) winsize 63
782 23:07:39.441499 [CA 1] Center 38 (7~69) winsize 63
783 23:07:39.445065 [CA 2] Center 36 (6~66) winsize 61
784 23:07:39.448211 [CA 3] Center 36 (5~67) winsize 63
785 23:07:39.451433 [CA 4] Center 35 (4~66) winsize 63
786 23:07:39.454584 [CA 5] Center 34 (4~65) winsize 62
787 23:07:39.454675
788 23:07:39.458081 [CmdBusTrainingLP45] Vref(ca) range 1: 32
789 23:07:39.458170
790 23:07:39.461670 [CATrainingPosCal] consider 2 rank data
791 23:07:39.464684 u2DelayCellTimex100 = 270/100 ps
792 23:07:39.468144 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
793 23:07:39.471524 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
794 23:07:39.478217 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
795 23:07:39.481596 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
796 23:07:39.485068 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
797 23:07:39.488349 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
798 23:07:39.488449
799 23:07:39.491414 CA PerBit enable=1, Macro0, CA PI delay=34
800 23:07:39.491505
801 23:07:39.495164 [CBTSetCACLKResult] CA Dly = 34
802 23:07:39.495254 CS Dly: 6 (0~38)
803 23:07:39.495325
804 23:07:39.498103 ----->DramcWriteLeveling(PI) begin...
805 23:07:39.498191 ==
806 23:07:39.501735 Dram Type= 6, Freq= 0, CH_0, rank 0
807 23:07:39.508149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 23:07:39.508258 ==
809 23:07:39.511405 Write leveling (Byte 0): 33 => 33
810 23:07:39.514900 Write leveling (Byte 1): 28 => 28
811 23:07:39.514991 DramcWriteLeveling(PI) end<-----
812 23:07:39.518437
813 23:07:39.518526 ==
814 23:07:39.521454 Dram Type= 6, Freq= 0, CH_0, rank 0
815 23:07:39.524795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
816 23:07:39.524891 ==
817 23:07:39.528440 [Gating] SW mode calibration
818 23:07:39.535572 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
819 23:07:39.539461 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
820 23:07:39.543449 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
821 23:07:39.546802 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
822 23:07:39.553486 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:07:39.557128 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:07:39.561003 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:07:39.564141 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:07:39.570741 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:07:39.574113 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 23:07:39.577382 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 23:07:39.584120 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 23:07:39.587655 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 23:07:39.591176 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 23:07:39.597641 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 23:07:39.601003 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 23:07:39.604708 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 23:07:39.611345 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 23:07:39.614654 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
837 23:07:39.617561 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
838 23:07:39.624236 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
839 23:07:39.627706 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 23:07:39.631004 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 23:07:39.637584 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 23:07:39.641110 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 23:07:39.644402 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 23:07:39.647656 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 23:07:39.654364 0 9 4 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
846 23:07:39.657428 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
847 23:07:39.661096 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
848 23:07:39.667718 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
849 23:07:39.670972 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
850 23:07:39.674349 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
851 23:07:39.681220 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 23:07:39.684186 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 23:07:39.687657 0 10 4 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
854 23:07:39.694887 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
855 23:07:39.697643 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 23:07:39.701165 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:07:39.707635 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:07:39.711301 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:07:39.714750 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:07:39.721414 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:07:39.724616 0 11 4 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
862 23:07:39.727958 0 11 8 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
863 23:07:39.731075 0 11 12 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
864 23:07:39.737841 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 23:07:39.741335 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 23:07:39.744401 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 23:07:39.751037 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 23:07:39.754865 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 23:07:39.758051 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
870 23:07:39.764690 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 23:07:39.767814 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 23:07:39.771223 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 23:07:39.777760 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 23:07:39.781242 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 23:07:39.784772 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 23:07:39.791393 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 23:07:39.794574 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 23:07:39.798048 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 23:07:39.804692 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 23:07:39.808277 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 23:07:39.811389 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 23:07:39.814761 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 23:07:39.821479 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 23:07:39.824595 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
885 23:07:39.828254 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
886 23:07:39.834770 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
887 23:07:39.834886 Total UI for P1: 0, mck2ui 16
888 23:07:39.841740 best dqsien dly found for B0: ( 0, 14, 2)
889 23:07:39.845232 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
890 23:07:39.848695 Total UI for P1: 0, mck2ui 16
891 23:07:39.851507 best dqsien dly found for B1: ( 0, 14, 6)
892 23:07:39.855184 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
893 23:07:39.858183 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
894 23:07:39.858279
895 23:07:39.861754 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
896 23:07:39.865232 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
897 23:07:39.868307 [Gating] SW calibration Done
898 23:07:39.868399 ==
899 23:07:39.871793 Dram Type= 6, Freq= 0, CH_0, rank 0
900 23:07:39.875057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 23:07:39.875154 ==
902 23:07:39.878286 RX Vref Scan: 0
903 23:07:39.878375
904 23:07:39.881457 RX Vref 0 -> 0, step: 1
905 23:07:39.881574
906 23:07:39.881674 RX Delay -130 -> 252, step: 16
907 23:07:39.888326 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
908 23:07:39.891431 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
909 23:07:39.894828 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
910 23:07:39.898228 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
911 23:07:39.901848 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
912 23:07:39.908408 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
913 23:07:39.911619 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
914 23:07:39.915333 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
915 23:07:39.918484 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
916 23:07:39.922253 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
917 23:07:39.928484 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
918 23:07:39.932127 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
919 23:07:39.935155 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
920 23:07:39.938648 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
921 23:07:39.941763 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
922 23:07:39.948507 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
923 23:07:39.948620 ==
924 23:07:39.951766 Dram Type= 6, Freq= 0, CH_0, rank 0
925 23:07:39.955048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
926 23:07:39.955128 ==
927 23:07:39.955201 DQS Delay:
928 23:07:39.958559 DQS0 = 0, DQS1 = 0
929 23:07:39.958641 DQM Delay:
930 23:07:39.961819 DQM0 = 90, DQM1 = 80
931 23:07:39.961894 DQ Delay:
932 23:07:39.965279 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
933 23:07:39.968655 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
934 23:07:39.971822 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
935 23:07:39.975433 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
936 23:07:39.975528
937 23:07:39.975604
938 23:07:39.975668 ==
939 23:07:39.978594 Dram Type= 6, Freq= 0, CH_0, rank 0
940 23:07:39.981823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
941 23:07:39.981964 ==
942 23:07:39.985299
943 23:07:39.985386
944 23:07:39.985454 TX Vref Scan disable
945 23:07:39.988837 == TX Byte 0 ==
946 23:07:39.991857 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
947 23:07:39.995420 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
948 23:07:39.998443 == TX Byte 1 ==
949 23:07:40.001777 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
950 23:07:40.005580 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
951 23:07:40.005701 ==
952 23:07:40.008613 Dram Type= 6, Freq= 0, CH_0, rank 0
953 23:07:40.014995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
954 23:07:40.015103 ==
955 23:07:40.027896 TX Vref=22, minBit 6, minWin=27, winSum=442
956 23:07:40.031059 TX Vref=24, minBit 6, minWin=27, winSum=444
957 23:07:40.034136 TX Vref=26, minBit 13, minWin=27, winSum=449
958 23:07:40.037758 TX Vref=28, minBit 0, minWin=28, winSum=452
959 23:07:40.041006 TX Vref=30, minBit 5, minWin=28, winSum=457
960 23:07:40.044316 TX Vref=32, minBit 5, minWin=28, winSum=455
961 23:07:40.050842 [TxChooseVref] Worse bit 5, Min win 28, Win sum 457, Final Vref 30
962 23:07:40.050950
963 23:07:40.054548 Final TX Range 1 Vref 30
964 23:07:40.054636
965 23:07:40.054721 ==
966 23:07:40.057850 Dram Type= 6, Freq= 0, CH_0, rank 0
967 23:07:40.060928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 23:07:40.061013 ==
969 23:07:40.061098
970 23:07:40.064073
971 23:07:40.064157 TX Vref Scan disable
972 23:07:40.067600 == TX Byte 0 ==
973 23:07:40.070980 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
974 23:07:40.074639 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
975 23:07:40.077601 == TX Byte 1 ==
976 23:07:40.080944 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
977 23:07:40.084067 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
978 23:07:40.087827
979 23:07:40.087945 [DATLAT]
980 23:07:40.088050 Freq=800, CH0 RK0
981 23:07:40.088152
982 23:07:40.091020 DATLAT Default: 0xa
983 23:07:40.091124 0, 0xFFFF, sum = 0
984 23:07:40.094231 1, 0xFFFF, sum = 0
985 23:07:40.094316 2, 0xFFFF, sum = 0
986 23:07:40.097800 3, 0xFFFF, sum = 0
987 23:07:40.097915 4, 0xFFFF, sum = 0
988 23:07:40.101279 5, 0xFFFF, sum = 0
989 23:07:40.101387 6, 0xFFFF, sum = 0
990 23:07:40.104619 7, 0xFFFF, sum = 0
991 23:07:40.104700 8, 0xFFFF, sum = 0
992 23:07:40.107779 9, 0x0, sum = 1
993 23:07:40.107861 10, 0x0, sum = 2
994 23:07:40.111220 11, 0x0, sum = 3
995 23:07:40.111302 12, 0x0, sum = 4
996 23:07:40.114623 best_step = 10
997 23:07:40.114704
998 23:07:40.114792 ==
999 23:07:40.118073 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 23:07:40.120916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 23:07:40.121022 ==
1002 23:07:40.124549 RX Vref Scan: 1
1003 23:07:40.124659
1004 23:07:40.124746 Set Vref Range= 32 -> 127
1005 23:07:40.124830
1006 23:07:40.127773 RX Vref 32 -> 127, step: 1
1007 23:07:40.127854
1008 23:07:40.131052 RX Delay -95 -> 252, step: 8
1009 23:07:40.131133
1010 23:07:40.134552 Set Vref, RX VrefLevel [Byte0]: 32
1011 23:07:40.137864 [Byte1]: 32
1012 23:07:40.137976
1013 23:07:40.141367 Set Vref, RX VrefLevel [Byte0]: 33
1014 23:07:40.144518 [Byte1]: 33
1015 23:07:40.148087
1016 23:07:40.148172 Set Vref, RX VrefLevel [Byte0]: 34
1017 23:07:40.151345 [Byte1]: 34
1018 23:07:40.155623
1019 23:07:40.155706 Set Vref, RX VrefLevel [Byte0]: 35
1020 23:07:40.159003 [Byte1]: 35
1021 23:07:40.163004
1022 23:07:40.163087 Set Vref, RX VrefLevel [Byte0]: 36
1023 23:07:40.166525 [Byte1]: 36
1024 23:07:40.170626
1025 23:07:40.170750 Set Vref, RX VrefLevel [Byte0]: 37
1026 23:07:40.173853 [Byte1]: 37
1027 23:07:40.178684
1028 23:07:40.178782 Set Vref, RX VrefLevel [Byte0]: 38
1029 23:07:40.182463 [Byte1]: 38
1030 23:07:40.185769
1031 23:07:40.185885 Set Vref, RX VrefLevel [Byte0]: 39
1032 23:07:40.189158 [Byte1]: 39
1033 23:07:40.193573
1034 23:07:40.193662 Set Vref, RX VrefLevel [Byte0]: 40
1035 23:07:40.197108 [Byte1]: 40
1036 23:07:40.201298
1037 23:07:40.201383 Set Vref, RX VrefLevel [Byte0]: 41
1038 23:07:40.204595 [Byte1]: 41
1039 23:07:40.208925
1040 23:07:40.209027 Set Vref, RX VrefLevel [Byte0]: 42
1041 23:07:40.212485 [Byte1]: 42
1042 23:07:40.216798
1043 23:07:40.216911 Set Vref, RX VrefLevel [Byte0]: 43
1044 23:07:40.220450 [Byte1]: 43
1045 23:07:40.224386
1046 23:07:40.224484 Set Vref, RX VrefLevel [Byte0]: 44
1047 23:07:40.227835 [Byte1]: 44
1048 23:07:40.232067
1049 23:07:40.232165 Set Vref, RX VrefLevel [Byte0]: 45
1050 23:07:40.235073 [Byte1]: 45
1051 23:07:40.239383
1052 23:07:40.239482 Set Vref, RX VrefLevel [Byte0]: 46
1053 23:07:40.242243 [Byte1]: 46
1054 23:07:40.246742
1055 23:07:40.246832 Set Vref, RX VrefLevel [Byte0]: 47
1056 23:07:40.249747 [Byte1]: 47
1057 23:07:40.254228
1058 23:07:40.254322 Set Vref, RX VrefLevel [Byte0]: 48
1059 23:07:40.257687 [Byte1]: 48
1060 23:07:40.262194
1061 23:07:40.262288 Set Vref, RX VrefLevel [Byte0]: 49
1062 23:07:40.265765 [Byte1]: 49
1063 23:07:40.269740
1064 23:07:40.269834 Set Vref, RX VrefLevel [Byte0]: 50
1065 23:07:40.272988 [Byte1]: 50
1066 23:07:40.277306
1067 23:07:40.277411 Set Vref, RX VrefLevel [Byte0]: 51
1068 23:07:40.280346 [Byte1]: 51
1069 23:07:40.284886
1070 23:07:40.284985 Set Vref, RX VrefLevel [Byte0]: 52
1071 23:07:40.288042 [Byte1]: 52
1072 23:07:40.292482
1073 23:07:40.292604 Set Vref, RX VrefLevel [Byte0]: 53
1074 23:07:40.295597 [Byte1]: 53
1075 23:07:40.299905
1076 23:07:40.300002 Set Vref, RX VrefLevel [Byte0]: 54
1077 23:07:40.303165 [Byte1]: 54
1078 23:07:40.307861
1079 23:07:40.307962 Set Vref, RX VrefLevel [Byte0]: 55
1080 23:07:40.311046 [Byte1]: 55
1081 23:07:40.315380
1082 23:07:40.315521 Set Vref, RX VrefLevel [Byte0]: 56
1083 23:07:40.318468 [Byte1]: 56
1084 23:07:40.322816
1085 23:07:40.322910 Set Vref, RX VrefLevel [Byte0]: 57
1086 23:07:40.325899 [Byte1]: 57
1087 23:07:40.330161
1088 23:07:40.330254 Set Vref, RX VrefLevel [Byte0]: 58
1089 23:07:40.333736 [Byte1]: 58
1090 23:07:40.337905
1091 23:07:40.338062 Set Vref, RX VrefLevel [Byte0]: 59
1092 23:07:40.341144 [Byte1]: 59
1093 23:07:40.345153
1094 23:07:40.348862 Set Vref, RX VrefLevel [Byte0]: 60
1095 23:07:40.348955 [Byte1]: 60
1096 23:07:40.352887
1097 23:07:40.353006 Set Vref, RX VrefLevel [Byte0]: 61
1098 23:07:40.356482 [Byte1]: 61
1099 23:07:40.360508
1100 23:07:40.360601 Set Vref, RX VrefLevel [Byte0]: 62
1101 23:07:40.364222 [Byte1]: 62
1102 23:07:40.368297
1103 23:07:40.368390 Set Vref, RX VrefLevel [Byte0]: 63
1104 23:07:40.371654 [Byte1]: 63
1105 23:07:40.375855
1106 23:07:40.375954 Set Vref, RX VrefLevel [Byte0]: 64
1107 23:07:40.379399 [Byte1]: 64
1108 23:07:40.383788
1109 23:07:40.383888 Set Vref, RX VrefLevel [Byte0]: 65
1110 23:07:40.386701 [Byte1]: 65
1111 23:07:40.391059
1112 23:07:40.391180 Set Vref, RX VrefLevel [Byte0]: 66
1113 23:07:40.394498 [Byte1]: 66
1114 23:07:40.398905
1115 23:07:40.399003 Set Vref, RX VrefLevel [Byte0]: 67
1116 23:07:40.401929 [Byte1]: 67
1117 23:07:40.406198
1118 23:07:40.406307 Set Vref, RX VrefLevel [Byte0]: 68
1119 23:07:40.409332 [Byte1]: 68
1120 23:07:40.413745
1121 23:07:40.413836 Set Vref, RX VrefLevel [Byte0]: 69
1122 23:07:40.417116 [Byte1]: 69
1123 23:07:40.421296
1124 23:07:40.421388 Set Vref, RX VrefLevel [Byte0]: 70
1125 23:07:40.424602 [Byte1]: 70
1126 23:07:40.429086
1127 23:07:40.429206 Set Vref, RX VrefLevel [Byte0]: 71
1128 23:07:40.432418 [Byte1]: 71
1129 23:07:40.436630
1130 23:07:40.436721 Set Vref, RX VrefLevel [Byte0]: 72
1131 23:07:40.439803 [Byte1]: 72
1132 23:07:40.444242
1133 23:07:40.447516 Set Vref, RX VrefLevel [Byte0]: 73
1134 23:07:40.450983 [Byte1]: 73
1135 23:07:40.451072
1136 23:07:40.454278 Set Vref, RX VrefLevel [Byte0]: 74
1137 23:07:40.457480 [Byte1]: 74
1138 23:07:40.457568
1139 23:07:40.460865 Set Vref, RX VrefLevel [Byte0]: 75
1140 23:07:40.464292 [Byte1]: 75
1141 23:07:40.464382
1142 23:07:40.467718 Set Vref, RX VrefLevel [Byte0]: 76
1143 23:07:40.470531 [Byte1]: 76
1144 23:07:40.474459
1145 23:07:40.474557 Final RX Vref Byte 0 = 62 to rank0
1146 23:07:40.478288 Final RX Vref Byte 1 = 63 to rank0
1147 23:07:40.481235 Final RX Vref Byte 0 = 62 to rank1
1148 23:07:40.485051 Final RX Vref Byte 1 = 63 to rank1==
1149 23:07:40.488101 Dram Type= 6, Freq= 0, CH_0, rank 0
1150 23:07:40.494632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 23:07:40.494742 ==
1152 23:07:40.494815 DQS Delay:
1153 23:07:40.494877 DQS0 = 0, DQS1 = 0
1154 23:07:40.497801 DQM Delay:
1155 23:07:40.497886 DQM0 = 93, DQM1 = 82
1156 23:07:40.501422 DQ Delay:
1157 23:07:40.504577 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1158 23:07:40.508085 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1159 23:07:40.511484 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1160 23:07:40.514778 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1161 23:07:40.514873
1162 23:07:40.514941
1163 23:07:40.521108 [DQSOSCAuto] RK0, (LSB)MR18= 0x403c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
1164 23:07:40.524442 CH0 RK0: MR19=606, MR18=403C
1165 23:07:40.531631 CH0_RK0: MR19=0x606, MR18=0x403C, DQSOSC=393, MR23=63, INC=95, DEC=63
1166 23:07:40.531750
1167 23:07:40.534696 ----->DramcWriteLeveling(PI) begin...
1168 23:07:40.534777 ==
1169 23:07:40.537885 Dram Type= 6, Freq= 0, CH_0, rank 1
1170 23:07:40.541548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1171 23:07:40.541636 ==
1172 23:07:40.544583 Write leveling (Byte 0): 35 => 35
1173 23:07:40.547842 Write leveling (Byte 1): 29 => 29
1174 23:07:40.551197 DramcWriteLeveling(PI) end<-----
1175 23:07:40.551272
1176 23:07:40.551335 ==
1177 23:07:40.554877 Dram Type= 6, Freq= 0, CH_0, rank 1
1178 23:07:40.558135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1179 23:07:40.558211 ==
1180 23:07:40.561352 [Gating] SW mode calibration
1181 23:07:40.568159 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1182 23:07:40.574644 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1183 23:07:40.577883 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1184 23:07:40.581265 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1185 23:07:40.588363 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 23:07:40.591332 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 23:07:40.594633 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 23:07:40.601645 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 23:07:40.645358 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 23:07:40.645707 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 23:07:40.645781 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 23:07:40.645846 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 23:07:40.646180 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 23:07:40.646677 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 23:07:40.646922 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 23:07:40.646986 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 23:07:40.647229 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 23:07:40.647500 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 23:07:40.664166 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 23:07:40.664494 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1201 23:07:40.664601 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1202 23:07:40.664704 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 23:07:40.667730 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 23:07:40.670994 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 23:07:40.674391 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 23:07:40.677606 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 23:07:40.684329 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 23:07:40.688011 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1209 23:07:40.690899 0 9 8 | B1->B0 | 2b2b 3130 | 1 1 | (1 1) (0 0)
1210 23:07:40.697817 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1211 23:07:40.701004 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1212 23:07:40.704686 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1213 23:07:40.711047 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1214 23:07:40.714231 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1215 23:07:40.718251 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1216 23:07:40.724273 0 10 4 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 1)
1217 23:07:40.727634 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1218 23:07:40.730907 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 23:07:40.737755 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 23:07:40.741010 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 23:07:40.744699 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 23:07:40.750937 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 23:07:40.754376 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 23:07:40.757772 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1225 23:07:40.764686 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1226 23:07:40.767924 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1227 23:07:40.770972 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1228 23:07:40.774269 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1229 23:07:40.781080 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1230 23:07:40.785348 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1231 23:07:40.788574 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1232 23:07:40.792551 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1233 23:07:40.799237 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1234 23:07:40.802879 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 23:07:40.806598 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 23:07:40.809758 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 23:07:40.816568 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 23:07:40.819711 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 23:07:40.823087 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 23:07:40.829845 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 23:07:40.833264 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 23:07:40.836374 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 23:07:40.843020 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 23:07:40.846573 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 23:07:40.849733 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 23:07:40.856816 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 23:07:40.859732 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 23:07:40.863266 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1249 23:07:40.866716 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 23:07:40.869864 Total UI for P1: 0, mck2ui 16
1251 23:07:40.873218 best dqsien dly found for B0: ( 0, 14, 4)
1252 23:07:40.876528 Total UI for P1: 0, mck2ui 16
1253 23:07:40.880216 best dqsien dly found for B1: ( 0, 14, 4)
1254 23:07:40.883244 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1255 23:07:40.886362 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1256 23:07:40.889881
1257 23:07:40.893246 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1258 23:07:40.896508 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1259 23:07:40.899945 [Gating] SW calibration Done
1260 23:07:40.900051 ==
1261 23:07:40.903088 Dram Type= 6, Freq= 0, CH_0, rank 1
1262 23:07:40.906763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1263 23:07:40.906873 ==
1264 23:07:40.906965 RX Vref Scan: 0
1265 23:07:40.907062
1266 23:07:40.909904 RX Vref 0 -> 0, step: 1
1267 23:07:40.910012
1268 23:07:40.913592 RX Delay -130 -> 252, step: 16
1269 23:07:40.916952 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1270 23:07:40.919887 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1271 23:07:40.926982 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1272 23:07:40.929924 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1273 23:07:40.933188 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1274 23:07:40.936559 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1275 23:07:40.939840 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1276 23:07:40.943370 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1277 23:07:40.949911 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1278 23:07:40.953101 iDelay=206, Bit 9, Center 69 (-34 ~ 173) 208
1279 23:07:40.956889 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1280 23:07:40.960413 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1281 23:07:40.963653 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1282 23:07:40.969984 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1283 23:07:40.973227 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1284 23:07:40.976577 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1285 23:07:40.976697 ==
1286 23:07:40.980187 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 23:07:40.983609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 23:07:40.983719 ==
1289 23:07:40.986632 DQS Delay:
1290 23:07:40.986740 DQS0 = 0, DQS1 = 0
1291 23:07:40.990061 DQM Delay:
1292 23:07:40.990137 DQM0 = 87, DQM1 = 78
1293 23:07:40.990199 DQ Delay:
1294 23:07:40.993669 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1295 23:07:40.996726 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1296 23:07:41.000338 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1297 23:07:41.003579 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1298 23:07:41.003686
1299 23:07:41.003780
1300 23:07:41.006975 ==
1301 23:07:41.007053 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 23:07:41.013616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 23:07:41.013736 ==
1304 23:07:41.013832
1305 23:07:41.013921
1306 23:07:41.017306 TX Vref Scan disable
1307 23:07:41.017382 == TX Byte 0 ==
1308 23:07:41.020073 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1309 23:07:41.026738 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1310 23:07:41.026866 == TX Byte 1 ==
1311 23:07:41.030316 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1312 23:07:41.036913 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1313 23:07:41.037013 ==
1314 23:07:41.040075 Dram Type= 6, Freq= 0, CH_0, rank 1
1315 23:07:41.043408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1316 23:07:41.043493 ==
1317 23:07:41.057457 TX Vref=22, minBit 0, minWin=27, winSum=442
1318 23:07:41.061024 TX Vref=24, minBit 3, minWin=27, winSum=445
1319 23:07:41.064122 TX Vref=26, minBit 8, minWin=27, winSum=449
1320 23:07:41.067739 TX Vref=28, minBit 8, minWin=27, winSum=452
1321 23:07:41.070913 TX Vref=30, minBit 8, minWin=27, winSum=455
1322 23:07:41.074273 TX Vref=32, minBit 8, minWin=27, winSum=455
1323 23:07:41.080909 [TxChooseVref] Worse bit 8, Min win 27, Win sum 455, Final Vref 30
1324 23:07:41.081045
1325 23:07:41.084482 Final TX Range 1 Vref 30
1326 23:07:41.084598
1327 23:07:41.084695 ==
1328 23:07:41.087439 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 23:07:41.091278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 23:07:41.091405 ==
1331 23:07:41.091475
1332 23:07:41.091537
1333 23:07:41.094445 TX Vref Scan disable
1334 23:07:41.097538 == TX Byte 0 ==
1335 23:07:41.101229 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1336 23:07:41.104412 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1337 23:07:41.107653 == TX Byte 1 ==
1338 23:07:41.111042 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1339 23:07:41.114614 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1340 23:07:41.114704
1341 23:07:41.117795 [DATLAT]
1342 23:07:41.117880 Freq=800, CH0 RK1
1343 23:07:41.117972
1344 23:07:41.121209 DATLAT Default: 0xa
1345 23:07:41.121293 0, 0xFFFF, sum = 0
1346 23:07:41.124566 1, 0xFFFF, sum = 0
1347 23:07:41.124681 2, 0xFFFF, sum = 0
1348 23:07:41.127797 3, 0xFFFF, sum = 0
1349 23:07:41.127884 4, 0xFFFF, sum = 0
1350 23:07:41.130857 5, 0xFFFF, sum = 0
1351 23:07:41.130944 6, 0xFFFF, sum = 0
1352 23:07:41.134335 7, 0xFFFF, sum = 0
1353 23:07:41.134422 8, 0xFFFF, sum = 0
1354 23:07:41.137439 9, 0x0, sum = 1
1355 23:07:41.137525 10, 0x0, sum = 2
1356 23:07:41.141249 11, 0x0, sum = 3
1357 23:07:41.141338 12, 0x0, sum = 4
1358 23:07:41.144419 best_step = 10
1359 23:07:41.144529
1360 23:07:41.144624 ==
1361 23:07:41.147620 Dram Type= 6, Freq= 0, CH_0, rank 1
1362 23:07:41.150863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1363 23:07:41.150951 ==
1364 23:07:41.154307 RX Vref Scan: 0
1365 23:07:41.154392
1366 23:07:41.154459 RX Vref 0 -> 0, step: 1
1367 23:07:41.154521
1368 23:07:41.157792 RX Delay -79 -> 252, step: 8
1369 23:07:41.164638 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1370 23:07:41.167612 iDelay=209, Bit 1, Center 96 (-15 ~ 208) 224
1371 23:07:41.171570 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1372 23:07:41.174188 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1373 23:07:41.177615 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1374 23:07:41.184266 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1375 23:07:41.187605 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1376 23:07:41.190932 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1377 23:07:41.194141 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1378 23:07:41.197908 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1379 23:07:41.200834 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1380 23:07:41.207881 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1381 23:07:41.211208 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1382 23:07:41.214396 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1383 23:07:41.217622 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1384 23:07:41.224405 iDelay=209, Bit 15, Center 84 (-23 ~ 192) 216
1385 23:07:41.224517 ==
1386 23:07:41.227639 Dram Type= 6, Freq= 0, CH_0, rank 1
1387 23:07:41.231206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1388 23:07:41.231298 ==
1389 23:07:41.231365 DQS Delay:
1390 23:07:41.234735 DQS0 = 0, DQS1 = 0
1391 23:07:41.234821 DQM Delay:
1392 23:07:41.237607 DQM0 = 91, DQM1 = 80
1393 23:07:41.237690 DQ Delay:
1394 23:07:41.241065 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =84
1395 23:07:41.244412 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1396 23:07:41.247923 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =76
1397 23:07:41.251294 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =84
1398 23:07:41.251383
1399 23:07:41.251448
1400 23:07:41.257930 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1401 23:07:41.261400 CH0 RK1: MR19=606, MR18=3F19
1402 23:07:41.268224 CH0_RK1: MR19=0x606, MR18=0x3F19, DQSOSC=393, MR23=63, INC=95, DEC=63
1403 23:07:41.271327 [RxdqsGatingPostProcess] freq 800
1404 23:07:41.275044 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1405 23:07:41.278315 Pre-setting of DQS Precalculation
1406 23:07:41.284808 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1407 23:07:41.284915 ==
1408 23:07:41.288479 Dram Type= 6, Freq= 0, CH_1, rank 0
1409 23:07:41.291399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 23:07:41.291490 ==
1411 23:07:41.298113 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1412 23:07:41.304973 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1413 23:07:41.312631 [CA 0] Center 36 (6~67) winsize 62
1414 23:07:41.315640 [CA 1] Center 36 (6~67) winsize 62
1415 23:07:41.319407 [CA 2] Center 34 (4~65) winsize 62
1416 23:07:41.322609 [CA 3] Center 34 (3~65) winsize 63
1417 23:07:41.326355 [CA 4] Center 34 (4~65) winsize 62
1418 23:07:41.329084 [CA 5] Center 34 (3~65) winsize 63
1419 23:07:41.329178
1420 23:07:41.332732 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1421 23:07:41.332820
1422 23:07:41.335829 [CATrainingPosCal] consider 1 rank data
1423 23:07:41.339286 u2DelayCellTimex100 = 270/100 ps
1424 23:07:41.342565 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1425 23:07:41.346102 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 23:07:41.349383 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1427 23:07:41.355789 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1428 23:07:41.359493 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 23:07:41.362505 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1430 23:07:41.362603
1431 23:07:41.365985 CA PerBit enable=1, Macro0, CA PI delay=34
1432 23:07:41.366089
1433 23:07:41.369505 [CBTSetCACLKResult] CA Dly = 34
1434 23:07:41.369598 CS Dly: 5 (0~36)
1435 23:07:41.369687 ==
1436 23:07:41.372775 Dram Type= 6, Freq= 0, CH_1, rank 1
1437 23:07:41.379190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 23:07:41.379357 ==
1439 23:07:41.382744 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1440 23:07:41.389174 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1441 23:07:41.398785 [CA 0] Center 36 (6~67) winsize 62
1442 23:07:41.401909 [CA 1] Center 37 (6~68) winsize 63
1443 23:07:41.405366 [CA 2] Center 35 (5~66) winsize 62
1444 23:07:41.408844 [CA 3] Center 34 (4~65) winsize 62
1445 23:07:41.411944 [CA 4] Center 34 (4~65) winsize 62
1446 23:07:41.415494 [CA 5] Center 34 (3~65) winsize 63
1447 23:07:41.415589
1448 23:07:41.418562 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1449 23:07:41.418652
1450 23:07:41.422201 [CATrainingPosCal] consider 2 rank data
1451 23:07:41.425472 u2DelayCellTimex100 = 270/100 ps
1452 23:07:41.428826 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1453 23:07:41.431932 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1454 23:07:41.438989 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1455 23:07:41.441955 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1456 23:07:41.445590 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1457 23:07:41.449475 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1458 23:07:41.449583
1459 23:07:41.453882 CA PerBit enable=1, Macro0, CA PI delay=34
1460 23:07:41.454003
1461 23:07:41.456889 [CBTSetCACLKResult] CA Dly = 34
1462 23:07:41.456980 CS Dly: 6 (0~38)
1463 23:07:41.457068
1464 23:07:41.460505 ----->DramcWriteLeveling(PI) begin...
1465 23:07:41.460598 ==
1466 23:07:41.464087 Dram Type= 6, Freq= 0, CH_1, rank 0
1467 23:07:41.467840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1468 23:07:41.467955 ==
1469 23:07:41.471543 Write leveling (Byte 0): 26 => 26
1470 23:07:41.475455 Write leveling (Byte 1): 29 => 29
1471 23:07:41.478719 DramcWriteLeveling(PI) end<-----
1472 23:07:41.478820
1473 23:07:41.478890 ==
1474 23:07:41.482386 Dram Type= 6, Freq= 0, CH_1, rank 0
1475 23:07:41.485569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1476 23:07:41.485680 ==
1477 23:07:41.488771 [Gating] SW mode calibration
1478 23:07:41.495532 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1479 23:07:41.499142 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1480 23:07:41.505775 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1481 23:07:41.508935 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1482 23:07:41.512715 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1483 23:07:41.519249 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 23:07:41.522577 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 23:07:41.525793 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 23:07:41.529581 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 23:07:41.535956 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 23:07:41.539434 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 23:07:41.542709 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 23:07:41.549604 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 23:07:41.552923 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 23:07:41.556318 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 23:07:41.563020 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 23:07:41.566483 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 23:07:41.569477 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 23:07:41.576217 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1497 23:07:41.579601 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1498 23:07:41.583090 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 23:07:41.586701 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 23:07:41.592869 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 23:07:41.596404 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 23:07:41.599755 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 23:07:41.606179 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 23:07:41.609581 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 23:07:41.613136 0 9 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1506 23:07:41.619613 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1507 23:07:41.623048 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1508 23:07:41.626311 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1509 23:07:41.632858 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1510 23:07:41.636497 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1511 23:07:41.639555 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1512 23:07:41.646548 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1513 23:07:41.649689 0 10 4 | B1->B0 | 2f2f 2e2e | 1 1 | (1 1) (1 0)
1514 23:07:41.653332 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 23:07:41.659600 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 23:07:41.662806 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 23:07:41.666398 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 23:07:41.672824 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 23:07:41.676229 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 23:07:41.680038 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 23:07:41.682940 0 11 4 | B1->B0 | 3232 3a3a | 1 0 | (0 0) (0 0)
1522 23:07:41.689729 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 23:07:41.693000 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1524 23:07:41.696667 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1525 23:07:41.703104 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1526 23:07:41.706466 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1527 23:07:41.709844 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1528 23:07:41.716569 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1529 23:07:41.720021 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1530 23:07:41.723383 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1531 23:07:41.729956 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 23:07:41.733104 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 23:07:41.736683 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 23:07:41.743419 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 23:07:41.747057 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 23:07:41.750209 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 23:07:41.753611 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 23:07:41.760127 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 23:07:41.763569 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 23:07:41.767127 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 23:07:41.773614 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 23:07:41.777206 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 23:07:41.780153 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 23:07:41.787088 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1545 23:07:41.790288 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1546 23:07:41.793576 Total UI for P1: 0, mck2ui 16
1547 23:07:41.796999 best dqsien dly found for B0: ( 0, 14, 0)
1548 23:07:41.800304 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1549 23:07:41.803617 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 23:07:41.807353 Total UI for P1: 0, mck2ui 16
1551 23:07:41.810774 best dqsien dly found for B1: ( 0, 14, 6)
1552 23:07:41.813805 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1553 23:07:41.817150 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1554 23:07:41.820228
1555 23:07:41.823851 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1556 23:07:41.827341 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1557 23:07:41.830576 [Gating] SW calibration Done
1558 23:07:41.830655 ==
1559 23:07:41.833794 Dram Type= 6, Freq= 0, CH_1, rank 0
1560 23:07:41.836962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1561 23:07:41.837036 ==
1562 23:07:41.837099 RX Vref Scan: 0
1563 23:07:41.837159
1564 23:07:41.840572 RX Vref 0 -> 0, step: 1
1565 23:07:41.840639
1566 23:07:41.844198 RX Delay -130 -> 252, step: 16
1567 23:07:41.847227 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1568 23:07:41.850444 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1569 23:07:41.857115 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1570 23:07:41.860534 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1571 23:07:41.864018 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1572 23:07:41.867489 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1573 23:07:41.870584 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1574 23:07:41.873711 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1575 23:07:41.880417 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1576 23:07:41.883922 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1577 23:07:41.887450 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1578 23:07:41.890999 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1579 23:07:41.894142 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1580 23:07:41.901084 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1581 23:07:41.904589 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1582 23:07:41.907315 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1583 23:07:41.907398 ==
1584 23:07:41.910696 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 23:07:41.914240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 23:07:41.914324 ==
1587 23:07:41.917652 DQS Delay:
1588 23:07:41.917735 DQS0 = 0, DQS1 = 0
1589 23:07:41.920908 DQM Delay:
1590 23:07:41.920991 DQM0 = 91, DQM1 = 80
1591 23:07:41.921057 DQ Delay:
1592 23:07:41.924025 DQ0 =101, DQ1 =77, DQ2 =77, DQ3 =93
1593 23:07:41.927448 DQ4 =85, DQ5 =101, DQ6 =109, DQ7 =85
1594 23:07:41.931061 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1595 23:07:41.934540 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1596 23:07:41.934623
1597 23:07:41.937648
1598 23:07:41.937730 ==
1599 23:07:41.941390 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 23:07:41.944298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 23:07:41.944374 ==
1602 23:07:41.944438
1603 23:07:41.944498
1604 23:07:41.947694 TX Vref Scan disable
1605 23:07:41.947766 == TX Byte 0 ==
1606 23:07:41.954226 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1607 23:07:41.957335 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1608 23:07:41.957408 == TX Byte 1 ==
1609 23:07:41.964232 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1610 23:07:41.967604 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1611 23:07:41.967676 ==
1612 23:07:41.970895 Dram Type= 6, Freq= 0, CH_1, rank 0
1613 23:07:41.973927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1614 23:07:41.974026 ==
1615 23:07:41.987733 TX Vref=22, minBit 15, minWin=26, winSum=447
1616 23:07:41.990850 TX Vref=24, minBit 15, minWin=27, winSum=453
1617 23:07:41.994578 TX Vref=26, minBit 15, minWin=27, winSum=455
1618 23:07:41.997714 TX Vref=28, minBit 15, minWin=27, winSum=456
1619 23:07:42.001216 TX Vref=30, minBit 15, minWin=27, winSum=460
1620 23:07:42.007591 TX Vref=32, minBit 13, minWin=27, winSum=456
1621 23:07:42.011287 [TxChooseVref] Worse bit 15, Min win 27, Win sum 460, Final Vref 30
1622 23:07:42.011361
1623 23:07:42.014659 Final TX Range 1 Vref 30
1624 23:07:42.014765
1625 23:07:42.014856 ==
1626 23:07:42.017857 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 23:07:42.020950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 23:07:42.024391 ==
1629 23:07:42.024498
1630 23:07:42.024590
1631 23:07:42.024678 TX Vref Scan disable
1632 23:07:42.028179 == TX Byte 0 ==
1633 23:07:42.031701 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1634 23:07:42.035453 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1635 23:07:42.038600 == TX Byte 1 ==
1636 23:07:42.042218 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1637 23:07:42.045282 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1638 23:07:42.045382
1639 23:07:42.048384 [DATLAT]
1640 23:07:42.048481 Freq=800, CH1 RK0
1641 23:07:42.048571
1642 23:07:42.052297 DATLAT Default: 0xa
1643 23:07:42.052396 0, 0xFFFF, sum = 0
1644 23:07:42.055056 1, 0xFFFF, sum = 0
1645 23:07:42.055157 2, 0xFFFF, sum = 0
1646 23:07:42.058385 3, 0xFFFF, sum = 0
1647 23:07:42.058490 4, 0xFFFF, sum = 0
1648 23:07:42.061836 5, 0xFFFF, sum = 0
1649 23:07:42.061937 6, 0xFFFF, sum = 0
1650 23:07:42.065420 7, 0xFFFF, sum = 0
1651 23:07:42.065527 8, 0xFFFF, sum = 0
1652 23:07:42.068553 9, 0x0, sum = 1
1653 23:07:42.068629 10, 0x0, sum = 2
1654 23:07:42.072240 11, 0x0, sum = 3
1655 23:07:42.072343 12, 0x0, sum = 4
1656 23:07:42.075156 best_step = 10
1657 23:07:42.075229
1658 23:07:42.075308 ==
1659 23:07:42.078418 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 23:07:42.081934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1661 23:07:42.082046 ==
1662 23:07:42.085425 RX Vref Scan: 1
1663 23:07:42.085524
1664 23:07:42.085614 Set Vref Range= 32 -> 127
1665 23:07:42.085706
1666 23:07:42.088651 RX Vref 32 -> 127, step: 1
1667 23:07:42.088745
1668 23:07:42.091760 RX Delay -95 -> 252, step: 8
1669 23:07:42.091855
1670 23:07:42.095175 Set Vref, RX VrefLevel [Byte0]: 32
1671 23:07:42.098560 [Byte1]: 32
1672 23:07:42.098669
1673 23:07:42.102154 Set Vref, RX VrefLevel [Byte0]: 33
1674 23:07:42.105014 [Byte1]: 33
1675 23:07:42.108587
1676 23:07:42.108686 Set Vref, RX VrefLevel [Byte0]: 34
1677 23:07:42.112201 [Byte1]: 34
1678 23:07:42.116046
1679 23:07:42.116144 Set Vref, RX VrefLevel [Byte0]: 35
1680 23:07:42.119231 [Byte1]: 35
1681 23:07:42.123629
1682 23:07:42.123701 Set Vref, RX VrefLevel [Byte0]: 36
1683 23:07:42.126923 [Byte1]: 36
1684 23:07:42.131407
1685 23:07:42.131510 Set Vref, RX VrefLevel [Byte0]: 37
1686 23:07:42.134804 [Byte1]: 37
1687 23:07:42.139078
1688 23:07:42.139152 Set Vref, RX VrefLevel [Byte0]: 38
1689 23:07:42.142370 [Byte1]: 38
1690 23:07:42.146550
1691 23:07:42.146627 Set Vref, RX VrefLevel [Byte0]: 39
1692 23:07:42.149766 [Byte1]: 39
1693 23:07:42.154087
1694 23:07:42.154163 Set Vref, RX VrefLevel [Byte0]: 40
1695 23:07:42.157371 [Byte1]: 40
1696 23:07:42.161544
1697 23:07:42.161624 Set Vref, RX VrefLevel [Byte0]: 41
1698 23:07:42.164985 [Byte1]: 41
1699 23:07:42.169100
1700 23:07:42.169202 Set Vref, RX VrefLevel [Byte0]: 42
1701 23:07:42.172659 [Byte1]: 42
1702 23:07:42.177077
1703 23:07:42.177176 Set Vref, RX VrefLevel [Byte0]: 43
1704 23:07:42.180321 [Byte1]: 43
1705 23:07:42.184562
1706 23:07:42.184665 Set Vref, RX VrefLevel [Byte0]: 44
1707 23:07:42.187658 [Byte1]: 44
1708 23:07:42.192036
1709 23:07:42.192140 Set Vref, RX VrefLevel [Byte0]: 45
1710 23:07:42.195565 [Byte1]: 45
1711 23:07:42.199942
1712 23:07:42.200047 Set Vref, RX VrefLevel [Byte0]: 46
1713 23:07:42.202872 [Byte1]: 46
1714 23:07:42.207125
1715 23:07:42.207212 Set Vref, RX VrefLevel [Byte0]: 47
1716 23:07:42.210839 [Byte1]: 47
1717 23:07:42.214643
1718 23:07:42.214719 Set Vref, RX VrefLevel [Byte0]: 48
1719 23:07:42.218380 [Byte1]: 48
1720 23:07:42.222765
1721 23:07:42.222858 Set Vref, RX VrefLevel [Byte0]: 49
1722 23:07:42.225706 [Byte1]: 49
1723 23:07:42.230209
1724 23:07:42.230313 Set Vref, RX VrefLevel [Byte0]: 50
1725 23:07:42.233284 [Byte1]: 50
1726 23:07:42.237851
1727 23:07:42.237970 Set Vref, RX VrefLevel [Byte0]: 51
1728 23:07:42.240884 [Byte1]: 51
1729 23:07:42.245428
1730 23:07:42.245515 Set Vref, RX VrefLevel [Byte0]: 52
1731 23:07:42.248480 [Byte1]: 52
1732 23:07:42.252795
1733 23:07:42.252900 Set Vref, RX VrefLevel [Byte0]: 53
1734 23:07:42.256649 [Byte1]: 53
1735 23:07:42.260390
1736 23:07:42.260464 Set Vref, RX VrefLevel [Byte0]: 54
1737 23:07:42.263591 [Byte1]: 54
1738 23:07:42.267907
1739 23:07:42.268009 Set Vref, RX VrefLevel [Byte0]: 55
1740 23:07:42.271119 [Byte1]: 55
1741 23:07:42.275678
1742 23:07:42.275751 Set Vref, RX VrefLevel [Byte0]: 56
1743 23:07:42.279045 [Byte1]: 56
1744 23:07:42.283294
1745 23:07:42.283375 Set Vref, RX VrefLevel [Byte0]: 57
1746 23:07:42.286903 [Byte1]: 57
1747 23:07:42.291062
1748 23:07:42.291167 Set Vref, RX VrefLevel [Byte0]: 58
1749 23:07:42.293918 [Byte1]: 58
1750 23:07:42.298545
1751 23:07:42.298620 Set Vref, RX VrefLevel [Byte0]: 59
1752 23:07:42.301556 [Byte1]: 59
1753 23:07:42.306155
1754 23:07:42.306238 Set Vref, RX VrefLevel [Byte0]: 60
1755 23:07:42.309503 [Byte1]: 60
1756 23:07:42.313555
1757 23:07:42.313669 Set Vref, RX VrefLevel [Byte0]: 61
1758 23:07:42.316886 [Byte1]: 61
1759 23:07:42.321154
1760 23:07:42.321253 Set Vref, RX VrefLevel [Byte0]: 62
1761 23:07:42.324304 [Byte1]: 62
1762 23:07:42.328757
1763 23:07:42.328862 Set Vref, RX VrefLevel [Byte0]: 63
1764 23:07:42.332184 [Byte1]: 63
1765 23:07:42.336568
1766 23:07:42.336657 Set Vref, RX VrefLevel [Byte0]: 64
1767 23:07:42.339519 [Byte1]: 64
1768 23:07:42.343926
1769 23:07:42.344053 Set Vref, RX VrefLevel [Byte0]: 65
1770 23:07:42.347158 [Byte1]: 65
1771 23:07:42.351442
1772 23:07:42.351542 Set Vref, RX VrefLevel [Byte0]: 66
1773 23:07:42.354856 [Byte1]: 66
1774 23:07:42.359172
1775 23:07:42.359253 Set Vref, RX VrefLevel [Byte0]: 67
1776 23:07:42.362322 [Byte1]: 67
1777 23:07:42.366866
1778 23:07:42.366942 Set Vref, RX VrefLevel [Byte0]: 68
1779 23:07:42.370277 [Byte1]: 68
1780 23:07:42.374547
1781 23:07:42.374654 Set Vref, RX VrefLevel [Byte0]: 69
1782 23:07:42.377871 [Byte1]: 69
1783 23:07:42.382053
1784 23:07:42.382150 Set Vref, RX VrefLevel [Byte0]: 70
1785 23:07:42.385265 [Byte1]: 70
1786 23:07:42.389720
1787 23:07:42.389863 Set Vref, RX VrefLevel [Byte0]: 71
1788 23:07:42.392933 [Byte1]: 71
1789 23:07:42.396902
1790 23:07:42.397011 Set Vref, RX VrefLevel [Byte0]: 72
1791 23:07:42.400673 [Byte1]: 72
1792 23:07:42.404771
1793 23:07:42.404909 Set Vref, RX VrefLevel [Byte0]: 73
1794 23:07:42.407816 [Byte1]: 73
1795 23:07:42.412262
1796 23:07:42.412338 Set Vref, RX VrefLevel [Byte0]: 74
1797 23:07:42.415947 [Byte1]: 74
1798 23:07:42.419810
1799 23:07:42.419882 Set Vref, RX VrefLevel [Byte0]: 75
1800 23:07:42.423091 [Byte1]: 75
1801 23:07:42.427732
1802 23:07:42.427811 Set Vref, RX VrefLevel [Byte0]: 76
1803 23:07:42.430797 [Byte1]: 76
1804 23:07:42.434929
1805 23:07:42.435003 Set Vref, RX VrefLevel [Byte0]: 77
1806 23:07:42.438608 [Byte1]: 77
1807 23:07:42.442822
1808 23:07:42.442923 Final RX Vref Byte 0 = 54 to rank0
1809 23:07:42.445877 Final RX Vref Byte 1 = 63 to rank0
1810 23:07:42.449326 Final RX Vref Byte 0 = 54 to rank1
1811 23:07:42.452664 Final RX Vref Byte 1 = 63 to rank1==
1812 23:07:42.456135 Dram Type= 6, Freq= 0, CH_1, rank 0
1813 23:07:42.459397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 23:07:42.462995 ==
1815 23:07:42.463084 DQS Delay:
1816 23:07:42.463166 DQS0 = 0, DQS1 = 0
1817 23:07:42.466347 DQM Delay:
1818 23:07:42.466423 DQM0 = 92, DQM1 = 82
1819 23:07:42.469485 DQ Delay:
1820 23:07:42.473260 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1821 23:07:42.473375 DQ4 =88, DQ5 =104, DQ6 =100, DQ7 =88
1822 23:07:42.476528 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1823 23:07:42.483009 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =88
1824 23:07:42.483131
1825 23:07:42.483201
1826 23:07:42.489501 [DQSOSCAuto] RK0, (LSB)MR18= 0x304d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1827 23:07:42.492695 CH1 RK0: MR19=606, MR18=304D
1828 23:07:42.499624 CH1_RK0: MR19=0x606, MR18=0x304D, DQSOSC=390, MR23=63, INC=97, DEC=64
1829 23:07:42.499785
1830 23:07:42.502776 ----->DramcWriteLeveling(PI) begin...
1831 23:07:42.502865 ==
1832 23:07:42.506583 Dram Type= 6, Freq= 0, CH_1, rank 1
1833 23:07:42.509422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 23:07:42.509504 ==
1835 23:07:42.512899 Write leveling (Byte 0): 29 => 29
1836 23:07:42.516266 Write leveling (Byte 1): 30 => 30
1837 23:07:42.519477 DramcWriteLeveling(PI) end<-----
1838 23:07:42.519562
1839 23:07:42.519625 ==
1840 23:07:42.522724 Dram Type= 6, Freq= 0, CH_1, rank 1
1841 23:07:42.526565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1842 23:07:42.526710 ==
1843 23:07:42.529420 [Gating] SW mode calibration
1844 23:07:42.536668 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1845 23:07:42.542812 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1846 23:07:42.546141 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1847 23:07:42.549697 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1848 23:07:42.556480 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 23:07:42.559599 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 23:07:42.562893 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 23:07:42.569769 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 23:07:42.572992 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 23:07:42.576414 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 23:07:42.579918 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 23:07:42.586383 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 23:07:42.589839 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 23:07:42.593355 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 23:07:42.599792 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 23:07:42.603043 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 23:07:42.606650 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 23:07:42.613165 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 23:07:42.616735 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1863 23:07:42.620183 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1864 23:07:42.626603 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1865 23:07:42.630145 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 23:07:42.633252 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 23:07:42.640211 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 23:07:42.643963 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 23:07:42.647022 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 23:07:42.650163 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 23:07:42.656606 0 9 4 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
1872 23:07:42.660006 0 9 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1873 23:07:42.663739 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 23:07:42.670201 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 23:07:42.673326 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1876 23:07:42.677020 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1877 23:07:42.683668 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1878 23:07:42.686907 0 10 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1879 23:07:42.690057 0 10 4 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
1880 23:07:42.697101 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:07:42.700078 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:07:42.703372 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:07:42.710083 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 23:07:42.713739 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 23:07:42.717029 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 23:07:42.723308 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 23:07:42.726656 0 11 4 | B1->B0 | 3232 2b2b | 0 0 | (1 1) (0 0)
1888 23:07:42.729969 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1889 23:07:42.733509 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 23:07:42.740278 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 23:07:42.743440 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 23:07:42.746673 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 23:07:42.753369 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 23:07:42.756945 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1895 23:07:42.759945 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1896 23:07:42.767213 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 23:07:42.770292 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 23:07:42.774095 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 23:07:42.780099 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 23:07:42.783660 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 23:07:42.786884 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 23:07:42.793682 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 23:07:42.796888 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 23:07:42.800326 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 23:07:42.806897 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 23:07:42.810919 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 23:07:42.813789 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 23:07:42.816984 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 23:07:42.823608 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 23:07:42.826946 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 23:07:42.830825 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1912 23:07:42.837121 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 23:07:42.840178 Total UI for P1: 0, mck2ui 16
1914 23:07:42.843802 best dqsien dly found for B0: ( 0, 14, 4)
1915 23:07:42.843877 Total UI for P1: 0, mck2ui 16
1916 23:07:42.850288 best dqsien dly found for B1: ( 0, 14, 4)
1917 23:07:42.853867 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1918 23:07:42.857351 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1919 23:07:42.857440
1920 23:07:42.860702 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1921 23:07:42.863833 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1922 23:07:42.867600 [Gating] SW calibration Done
1923 23:07:42.867673 ==
1924 23:07:42.870604 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 23:07:42.874048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 23:07:42.874127 ==
1927 23:07:42.877061 RX Vref Scan: 0
1928 23:07:42.877161
1929 23:07:42.877264 RX Vref 0 -> 0, step: 1
1930 23:07:42.877326
1931 23:07:42.880459 RX Delay -130 -> 252, step: 16
1932 23:07:42.883608 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1933 23:07:42.890499 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1934 23:07:42.893634 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1935 23:07:42.896902 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1936 23:07:42.900359 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1937 23:07:42.903618 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1938 23:07:42.910586 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1939 23:07:42.913867 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1940 23:07:42.917341 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1941 23:07:42.920633 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1942 23:07:42.923777 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1943 23:07:42.930492 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1944 23:07:42.934057 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1945 23:07:42.937616 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1946 23:07:42.940772 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1947 23:07:42.943644 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1948 23:07:42.943716 ==
1949 23:07:42.947079 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 23:07:42.953814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 23:07:42.953922 ==
1952 23:07:42.953999 DQS Delay:
1953 23:07:42.957348 DQS0 = 0, DQS1 = 0
1954 23:07:42.957421 DQM Delay:
1955 23:07:42.957484 DQM0 = 89, DQM1 = 80
1956 23:07:42.960582 DQ Delay:
1957 23:07:42.964199 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1958 23:07:42.967387 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1959 23:07:42.970752 DQ8 =61, DQ9 =69, DQ10 =85, DQ11 =69
1960 23:07:42.974069 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1961 23:07:42.974142
1962 23:07:42.974212
1963 23:07:42.974270 ==
1964 23:07:42.977408 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 23:07:42.980542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 23:07:42.980628 ==
1967 23:07:42.980696
1968 23:07:42.980757
1969 23:07:42.984139 TX Vref Scan disable
1970 23:07:42.984222 == TX Byte 0 ==
1971 23:07:42.990765 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1972 23:07:42.993915 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1973 23:07:42.994038 == TX Byte 1 ==
1974 23:07:43.000687 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1975 23:07:43.003990 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1976 23:07:43.004073 ==
1977 23:07:43.007382 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 23:07:43.010964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 23:07:43.011060 ==
1980 23:07:43.024683 TX Vref=22, minBit 13, minWin=27, winSum=449
1981 23:07:43.028298 TX Vref=24, minBit 13, minWin=27, winSum=456
1982 23:07:43.031174 TX Vref=26, minBit 13, minWin=27, winSum=458
1983 23:07:43.034698 TX Vref=28, minBit 8, minWin=28, winSum=457
1984 23:07:43.038138 TX Vref=30, minBit 2, minWin=28, winSum=456
1985 23:07:43.044553 TX Vref=32, minBit 15, minWin=27, winSum=457
1986 23:07:43.048145 [TxChooseVref] Worse bit 8, Min win 28, Win sum 457, Final Vref 28
1987 23:07:43.048220
1988 23:07:43.051412 Final TX Range 1 Vref 28
1989 23:07:43.051484
1990 23:07:43.051546 ==
1991 23:07:43.054672 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 23:07:43.058185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 23:07:43.058257 ==
1994 23:07:43.061198
1995 23:07:43.061300
1996 23:07:43.061390 TX Vref Scan disable
1997 23:07:43.064990 == TX Byte 0 ==
1998 23:07:43.068106 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1999 23:07:43.071379 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2000 23:07:43.074778 == TX Byte 1 ==
2001 23:07:43.078217 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2002 23:07:43.081399 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2003 23:07:43.081485
2004 23:07:43.084677 [DATLAT]
2005 23:07:43.084761 Freq=800, CH1 RK1
2006 23:07:43.084828
2007 23:07:43.088262 DATLAT Default: 0xa
2008 23:07:43.088353 0, 0xFFFF, sum = 0
2009 23:07:43.091620 1, 0xFFFF, sum = 0
2010 23:07:43.091706 2, 0xFFFF, sum = 0
2011 23:07:43.094801 3, 0xFFFF, sum = 0
2012 23:07:43.094919 4, 0xFFFF, sum = 0
2013 23:07:43.098173 5, 0xFFFF, sum = 0
2014 23:07:43.098250 6, 0xFFFF, sum = 0
2015 23:07:43.101446 7, 0xFFFF, sum = 0
2016 23:07:43.104670 8, 0xFFFF, sum = 0
2017 23:07:43.104776 9, 0x0, sum = 1
2018 23:07:43.104845 10, 0x0, sum = 2
2019 23:07:43.108235 11, 0x0, sum = 3
2020 23:07:43.108308 12, 0x0, sum = 4
2021 23:07:43.111652 best_step = 10
2022 23:07:43.111729
2023 23:07:43.111800 ==
2024 23:07:43.114969 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 23:07:43.118179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 23:07:43.118284 ==
2027 23:07:43.121970 RX Vref Scan: 0
2028 23:07:43.122059
2029 23:07:43.122123 RX Vref 0 -> 0, step: 1
2030 23:07:43.122184
2031 23:07:43.124916 RX Delay -95 -> 252, step: 8
2032 23:07:43.132141 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2033 23:07:43.135313 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2034 23:07:43.138689 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2035 23:07:43.141908 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2036 23:07:43.145286 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2037 23:07:43.148646 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2038 23:07:43.155159 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2039 23:07:43.158380 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2040 23:07:43.162170 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2041 23:07:43.165114 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2042 23:07:43.168474 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2043 23:07:43.175186 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2044 23:07:43.178368 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2045 23:07:43.181864 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2046 23:07:43.185429 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2047 23:07:43.188756 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2048 23:07:43.192139 ==
2049 23:07:43.195294 Dram Type= 6, Freq= 0, CH_1, rank 1
2050 23:07:43.198677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2051 23:07:43.198762 ==
2052 23:07:43.198828 DQS Delay:
2053 23:07:43.201967 DQS0 = 0, DQS1 = 0
2054 23:07:43.202063 DQM Delay:
2055 23:07:43.205204 DQM0 = 91, DQM1 = 82
2056 23:07:43.205291 DQ Delay:
2057 23:07:43.208581 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2058 23:07:43.211983 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2059 23:07:43.215421 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2060 23:07:43.218729 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2061 23:07:43.218813
2062 23:07:43.218893
2063 23:07:43.225095 [DQSOSCAuto] RK1, (LSB)MR18= 0x380e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2064 23:07:43.228539 CH1 RK1: MR19=606, MR18=380E
2065 23:07:43.235422 CH1_RK1: MR19=0x606, MR18=0x380E, DQSOSC=395, MR23=63, INC=94, DEC=63
2066 23:07:43.238547 [RxdqsGatingPostProcess] freq 800
2067 23:07:43.241951 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2068 23:07:43.245420 Pre-setting of DQS Precalculation
2069 23:07:43.251861 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2070 23:07:43.258714 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2071 23:07:43.265062 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2072 23:07:43.265148
2073 23:07:43.265212
2074 23:07:43.268381 [Calibration Summary] 1600 Mbps
2075 23:07:43.271959 CH 0, Rank 0
2076 23:07:43.272033 SW Impedance : PASS
2077 23:07:43.275586 DUTY Scan : NO K
2078 23:07:43.275689 ZQ Calibration : PASS
2079 23:07:43.278786 Jitter Meter : NO K
2080 23:07:43.282096 CBT Training : PASS
2081 23:07:43.282173 Write leveling : PASS
2082 23:07:43.285300 RX DQS gating : PASS
2083 23:07:43.288620 RX DQ/DQS(RDDQC) : PASS
2084 23:07:43.288742 TX DQ/DQS : PASS
2085 23:07:43.292075 RX DATLAT : PASS
2086 23:07:43.295408 RX DQ/DQS(Engine): PASS
2087 23:07:43.295511 TX OE : NO K
2088 23:07:43.298869 All Pass.
2089 23:07:43.298967
2090 23:07:43.299057 CH 0, Rank 1
2091 23:07:43.302050 SW Impedance : PASS
2092 23:07:43.302123 DUTY Scan : NO K
2093 23:07:43.305220 ZQ Calibration : PASS
2094 23:07:43.308701 Jitter Meter : NO K
2095 23:07:43.308799 CBT Training : PASS
2096 23:07:43.311920 Write leveling : PASS
2097 23:07:43.311993 RX DQS gating : PASS
2098 23:07:43.315365 RX DQ/DQS(RDDQC) : PASS
2099 23:07:43.318432 TX DQ/DQS : PASS
2100 23:07:43.318504 RX DATLAT : PASS
2101 23:07:43.321873 RX DQ/DQS(Engine): PASS
2102 23:07:43.325091 TX OE : NO K
2103 23:07:43.325190 All Pass.
2104 23:07:43.325287
2105 23:07:43.325388 CH 1, Rank 0
2106 23:07:43.328643 SW Impedance : PASS
2107 23:07:43.331836 DUTY Scan : NO K
2108 23:07:43.331910 ZQ Calibration : PASS
2109 23:07:43.335448 Jitter Meter : NO K
2110 23:07:43.338634 CBT Training : PASS
2111 23:07:43.338733 Write leveling : PASS
2112 23:07:43.342051 RX DQS gating : PASS
2113 23:07:43.345407 RX DQ/DQS(RDDQC) : PASS
2114 23:07:43.345532 TX DQ/DQS : PASS
2115 23:07:43.348668 RX DATLAT : PASS
2116 23:07:43.348747 RX DQ/DQS(Engine): PASS
2117 23:07:43.351870 TX OE : NO K
2118 23:07:43.351942 All Pass.
2119 23:07:43.352009
2120 23:07:43.355406 CH 1, Rank 1
2121 23:07:43.358709 SW Impedance : PASS
2122 23:07:43.358781 DUTY Scan : NO K
2123 23:07:43.361819 ZQ Calibration : PASS
2124 23:07:43.361915 Jitter Meter : NO K
2125 23:07:43.365321 CBT Training : PASS
2126 23:07:43.368786 Write leveling : PASS
2127 23:07:43.368859 RX DQS gating : PASS
2128 23:07:43.372233 RX DQ/DQS(RDDQC) : PASS
2129 23:07:43.375425 TX DQ/DQS : PASS
2130 23:07:43.375497 RX DATLAT : PASS
2131 23:07:43.378699 RX DQ/DQS(Engine): PASS
2132 23:07:43.381934 TX OE : NO K
2133 23:07:43.382063 All Pass.
2134 23:07:43.382128
2135 23:07:43.382189 DramC Write-DBI off
2136 23:07:43.385560 PER_BANK_REFRESH: Hybrid Mode
2137 23:07:43.388672 TX_TRACKING: ON
2138 23:07:43.392112 [GetDramInforAfterCalByMRR] Vendor 6.
2139 23:07:43.395178 [GetDramInforAfterCalByMRR] Revision 606.
2140 23:07:43.398663 [GetDramInforAfterCalByMRR] Revision 2 0.
2141 23:07:43.398745 MR0 0x3b3b
2142 23:07:43.401965 MR8 0x5151
2143 23:07:43.405483 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2144 23:07:43.405572
2145 23:07:43.405665 MR0 0x3b3b
2146 23:07:43.405769 MR8 0x5151
2147 23:07:43.408886 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2148 23:07:43.408986
2149 23:07:43.418703 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2150 23:07:43.422174 [FAST_K] Save calibration result to emmc
2151 23:07:43.425525 [FAST_K] Save calibration result to emmc
2152 23:07:43.429051 dram_init: config_dvfs: 1
2153 23:07:43.432223 dramc_set_vcore_voltage set vcore to 662500
2154 23:07:43.435737 Read voltage for 1200, 2
2155 23:07:43.435843 Vio18 = 0
2156 23:07:43.435936 Vcore = 662500
2157 23:07:43.438944 Vdram = 0
2158 23:07:43.439031 Vddq = 0
2159 23:07:43.439097 Vmddr = 0
2160 23:07:43.445400 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2161 23:07:43.449167 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2162 23:07:43.452432 MEM_TYPE=3, freq_sel=15
2163 23:07:43.455555 sv_algorithm_assistance_LP4_1600
2164 23:07:43.458818 ============ PULL DRAM RESETB DOWN ============
2165 23:07:43.462484 ========== PULL DRAM RESETB DOWN end =========
2166 23:07:43.468862 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2167 23:07:43.472520 ===================================
2168 23:07:43.475576 LPDDR4 DRAM CONFIGURATION
2169 23:07:43.478965 ===================================
2170 23:07:43.479046 EX_ROW_EN[0] = 0x0
2171 23:07:43.482305 EX_ROW_EN[1] = 0x0
2172 23:07:43.482380 LP4Y_EN = 0x0
2173 23:07:43.485775 WORK_FSP = 0x0
2174 23:07:43.485869 WL = 0x4
2175 23:07:43.489066 RL = 0x4
2176 23:07:43.489137 BL = 0x2
2177 23:07:43.492286 RPST = 0x0
2178 23:07:43.492381 RD_PRE = 0x0
2179 23:07:43.495707 WR_PRE = 0x1
2180 23:07:43.495803 WR_PST = 0x0
2181 23:07:43.499249 DBI_WR = 0x0
2182 23:07:43.499323 DBI_RD = 0x0
2183 23:07:43.502296 OTF = 0x1
2184 23:07:43.505838 ===================================
2185 23:07:43.509156 ===================================
2186 23:07:43.509226 ANA top config
2187 23:07:43.512533 ===================================
2188 23:07:43.516039 DLL_ASYNC_EN = 0
2189 23:07:43.519237 ALL_SLAVE_EN = 0
2190 23:07:43.522360 NEW_RANK_MODE = 1
2191 23:07:43.522459 DLL_IDLE_MODE = 1
2192 23:07:43.525765 LP45_APHY_COMB_EN = 1
2193 23:07:43.529329 TX_ODT_DIS = 1
2194 23:07:43.532350 NEW_8X_MODE = 1
2195 23:07:43.536045 ===================================
2196 23:07:43.539043 ===================================
2197 23:07:43.542716 data_rate = 2400
2198 23:07:43.542793 CKR = 1
2199 23:07:43.546239 DQ_P2S_RATIO = 8
2200 23:07:43.549238 ===================================
2201 23:07:43.552768 CA_P2S_RATIO = 8
2202 23:07:43.555777 DQ_CA_OPEN = 0
2203 23:07:43.559364 DQ_SEMI_OPEN = 0
2204 23:07:43.559452 CA_SEMI_OPEN = 0
2205 23:07:43.562805 CA_FULL_RATE = 0
2206 23:07:43.566131 DQ_CKDIV4_EN = 0
2207 23:07:43.569416 CA_CKDIV4_EN = 0
2208 23:07:43.572907 CA_PREDIV_EN = 0
2209 23:07:43.576271 PH8_DLY = 17
2210 23:07:43.576357 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2211 23:07:43.579532 DQ_AAMCK_DIV = 4
2212 23:07:43.582795 CA_AAMCK_DIV = 4
2213 23:07:43.586179 CA_ADMCK_DIV = 4
2214 23:07:43.589315 DQ_TRACK_CA_EN = 0
2215 23:07:43.592630 CA_PICK = 1200
2216 23:07:43.595996 CA_MCKIO = 1200
2217 23:07:43.596092 MCKIO_SEMI = 0
2218 23:07:43.599271 PLL_FREQ = 2366
2219 23:07:43.602844 DQ_UI_PI_RATIO = 32
2220 23:07:43.605988 CA_UI_PI_RATIO = 0
2221 23:07:43.609554 ===================================
2222 23:07:43.612864 ===================================
2223 23:07:43.615898 memory_type:LPDDR4
2224 23:07:43.615985 GP_NUM : 10
2225 23:07:43.619256 SRAM_EN : 1
2226 23:07:43.619343 MD32_EN : 0
2227 23:07:43.622496 ===================================
2228 23:07:43.626200 [ANA_INIT] >>>>>>>>>>>>>>
2229 23:07:43.629411 <<<<<< [CONFIGURE PHASE]: ANA_TX
2230 23:07:43.632757 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2231 23:07:43.636506 ===================================
2232 23:07:43.639691 data_rate = 2400,PCW = 0X5b00
2233 23:07:43.642532 ===================================
2234 23:07:43.646416 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2235 23:07:43.652494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2236 23:07:43.656117 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2237 23:07:43.662805 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2238 23:07:43.665972 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2239 23:07:43.669250 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2240 23:07:43.669338 [ANA_INIT] flow start
2241 23:07:43.672590 [ANA_INIT] PLL >>>>>>>>
2242 23:07:43.676155 [ANA_INIT] PLL <<<<<<<<
2243 23:07:43.676245 [ANA_INIT] MIDPI >>>>>>>>
2244 23:07:43.679244 [ANA_INIT] MIDPI <<<<<<<<
2245 23:07:43.682649 [ANA_INIT] DLL >>>>>>>>
2246 23:07:43.682736 [ANA_INIT] DLL <<<<<<<<
2247 23:07:43.686149 [ANA_INIT] flow end
2248 23:07:43.689579 ============ LP4 DIFF to SE enter ============
2249 23:07:43.692608 ============ LP4 DIFF to SE exit ============
2250 23:07:43.696300 [ANA_INIT] <<<<<<<<<<<<<
2251 23:07:43.699300 [Flow] Enable top DCM control >>>>>
2252 23:07:43.702545 [Flow] Enable top DCM control <<<<<
2253 23:07:43.706055 Enable DLL master slave shuffle
2254 23:07:43.712673 ==============================================================
2255 23:07:43.712764 Gating Mode config
2256 23:07:43.719429 ==============================================================
2257 23:07:43.719521 Config description:
2258 23:07:43.729211 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2259 23:07:43.736294 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2260 23:07:43.743032 SELPH_MODE 0: By rank 1: By Phase
2261 23:07:43.746418 ==============================================================
2262 23:07:43.749543 GAT_TRACK_EN = 1
2263 23:07:43.752811 RX_GATING_MODE = 2
2264 23:07:43.756283 RX_GATING_TRACK_MODE = 2
2265 23:07:43.759710 SELPH_MODE = 1
2266 23:07:43.762846 PICG_EARLY_EN = 1
2267 23:07:43.766501 VALID_LAT_VALUE = 1
2268 23:07:43.769722 ==============================================================
2269 23:07:43.773013 Enter into Gating configuration >>>>
2270 23:07:43.776117 Exit from Gating configuration <<<<
2271 23:07:43.779734 Enter into DVFS_PRE_config >>>>>
2272 23:07:43.792753 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2273 23:07:43.796095 Exit from DVFS_PRE_config <<<<<
2274 23:07:43.799914 Enter into PICG configuration >>>>
2275 23:07:43.800022 Exit from PICG configuration <<<<
2276 23:07:43.802665 [RX_INPUT] configuration >>>>>
2277 23:07:43.806328 [RX_INPUT] configuration <<<<<
2278 23:07:43.813024 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2279 23:07:43.816033 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2280 23:07:43.822810 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2281 23:07:43.829539 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2282 23:07:43.836102 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2283 23:07:43.842822 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2284 23:07:43.846225 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2285 23:07:43.849618 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2286 23:07:43.852903 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2287 23:07:43.859462 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2288 23:07:43.863043 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2289 23:07:43.866497 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2290 23:07:43.869663 ===================================
2291 23:07:43.872868 LPDDR4 DRAM CONFIGURATION
2292 23:07:43.876255 ===================================
2293 23:07:43.876357 EX_ROW_EN[0] = 0x0
2294 23:07:43.879485 EX_ROW_EN[1] = 0x0
2295 23:07:43.882947 LP4Y_EN = 0x0
2296 23:07:43.883024 WORK_FSP = 0x0
2297 23:07:43.886338 WL = 0x4
2298 23:07:43.886409 RL = 0x4
2299 23:07:43.889871 BL = 0x2
2300 23:07:43.889984 RPST = 0x0
2301 23:07:43.892788 RD_PRE = 0x0
2302 23:07:43.892881 WR_PRE = 0x1
2303 23:07:43.896724 WR_PST = 0x0
2304 23:07:43.896818 DBI_WR = 0x0
2305 23:07:43.899819 DBI_RD = 0x0
2306 23:07:43.899886 OTF = 0x1
2307 23:07:43.903031 ===================================
2308 23:07:43.906113 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2309 23:07:43.912864 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2310 23:07:43.916502 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2311 23:07:43.919948 ===================================
2312 23:07:43.923064 LPDDR4 DRAM CONFIGURATION
2313 23:07:43.926396 ===================================
2314 23:07:43.926496 EX_ROW_EN[0] = 0x10
2315 23:07:43.929587 EX_ROW_EN[1] = 0x0
2316 23:07:43.929666 LP4Y_EN = 0x0
2317 23:07:43.933022 WORK_FSP = 0x0
2318 23:07:43.933122 WL = 0x4
2319 23:07:43.936342 RL = 0x4
2320 23:07:43.936429 BL = 0x2
2321 23:07:43.939660 RPST = 0x0
2322 23:07:43.939746 RD_PRE = 0x0
2323 23:07:43.943384 WR_PRE = 0x1
2324 23:07:43.946577 WR_PST = 0x0
2325 23:07:43.946669 DBI_WR = 0x0
2326 23:07:43.949668 DBI_RD = 0x0
2327 23:07:43.949757 OTF = 0x1
2328 23:07:43.953091 ===================================
2329 23:07:43.959569 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2330 23:07:43.959680 ==
2331 23:07:43.963006 Dram Type= 6, Freq= 0, CH_0, rank 0
2332 23:07:43.966489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2333 23:07:43.966576 ==
2334 23:07:43.969806 [Duty_Offset_Calibration]
2335 23:07:43.969889 B0:2 B1:0 CA:1
2336 23:07:43.969980
2337 23:07:43.973023 [DutyScan_Calibration_Flow] k_type=0
2338 23:07:43.983165
2339 23:07:43.983275 ==CLK 0==
2340 23:07:43.986316 Final CLK duty delay cell = -4
2341 23:07:43.989836 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2342 23:07:43.993082 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2343 23:07:43.996460 [-4] AVG Duty = 4953%(X100)
2344 23:07:43.996544
2345 23:07:44.000160 CH0 CLK Duty spec in!! Max-Min= 156%
2346 23:07:44.003136 [DutyScan_Calibration_Flow] ====Done====
2347 23:07:44.003280
2348 23:07:44.006557 [DutyScan_Calibration_Flow] k_type=1
2349 23:07:44.021789
2350 23:07:44.021897 ==DQS 0 ==
2351 23:07:44.025469 Final DQS duty delay cell = 0
2352 23:07:44.028641 [0] MAX Duty = 5187%(X100), DQS PI = 30
2353 23:07:44.032052 [0] MIN Duty = 4938%(X100), DQS PI = 0
2354 23:07:44.032192 [0] AVG Duty = 5062%(X100)
2355 23:07:44.035193
2356 23:07:44.035277 ==DQS 1 ==
2357 23:07:44.038783 Final DQS duty delay cell = -4
2358 23:07:44.042127 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2359 23:07:44.045491 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2360 23:07:44.048748 [-4] AVG Duty = 5015%(X100)
2361 23:07:44.048833
2362 23:07:44.052394 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2363 23:07:44.052478
2364 23:07:44.055578 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2365 23:07:44.059163 [DutyScan_Calibration_Flow] ====Done====
2366 23:07:44.059246
2367 23:07:44.061873 [DutyScan_Calibration_Flow] k_type=3
2368 23:07:44.078778
2369 23:07:44.078906 ==DQM 0 ==
2370 23:07:44.082311 Final DQM duty delay cell = 0
2371 23:07:44.085402 [0] MAX Duty = 5062%(X100), DQS PI = 24
2372 23:07:44.088612 [0] MIN Duty = 4813%(X100), DQS PI = 0
2373 23:07:44.088696 [0] AVG Duty = 4937%(X100)
2374 23:07:44.092100
2375 23:07:44.092184 ==DQM 1 ==
2376 23:07:44.095746 Final DQM duty delay cell = 0
2377 23:07:44.099026 [0] MAX Duty = 5187%(X100), DQS PI = 32
2378 23:07:44.102605 [0] MIN Duty = 5000%(X100), DQS PI = 12
2379 23:07:44.102707 [0] AVG Duty = 5093%(X100)
2380 23:07:44.105633
2381 23:07:44.108742 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2382 23:07:44.108827
2383 23:07:44.112306 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2384 23:07:44.115755 [DutyScan_Calibration_Flow] ====Done====
2385 23:07:44.115840
2386 23:07:44.119323 [DutyScan_Calibration_Flow] k_type=2
2387 23:07:44.135501
2388 23:07:44.135631 ==DQ 0 ==
2389 23:07:44.138569 Final DQ duty delay cell = -4
2390 23:07:44.141833 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2391 23:07:44.145166 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2392 23:07:44.148736 [-4] AVG Duty = 4953%(X100)
2393 23:07:44.148822
2394 23:07:44.148888 ==DQ 1 ==
2395 23:07:44.152302 Final DQ duty delay cell = 4
2396 23:07:44.155171 [4] MAX Duty = 5124%(X100), DQS PI = 54
2397 23:07:44.158917 [4] MIN Duty = 5031%(X100), DQS PI = 2
2398 23:07:44.158996 [4] AVG Duty = 5077%(X100)
2399 23:07:44.159060
2400 23:07:44.162053 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2401 23:07:44.165449
2402 23:07:44.168993 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2403 23:07:44.172344 [DutyScan_Calibration_Flow] ====Done====
2404 23:07:44.172460 ==
2405 23:07:44.175372 Dram Type= 6, Freq= 0, CH_1, rank 0
2406 23:07:44.178716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2407 23:07:44.178802 ==
2408 23:07:44.182579 [Duty_Offset_Calibration]
2409 23:07:44.182670 B0:0 B1:-1 CA:2
2410 23:07:44.182738
2411 23:07:44.185655 [DutyScan_Calibration_Flow] k_type=0
2412 23:07:44.195507
2413 23:07:44.195620 ==CLK 0==
2414 23:07:44.198602 Final CLK duty delay cell = 0
2415 23:07:44.201974 [0] MAX Duty = 5156%(X100), DQS PI = 16
2416 23:07:44.205829 [0] MIN Duty = 4938%(X100), DQS PI = 44
2417 23:07:44.205914 [0] AVG Duty = 5047%(X100)
2418 23:07:44.209035
2419 23:07:44.211913 CH1 CLK Duty spec in!! Max-Min= 218%
2420 23:07:44.215480 [DutyScan_Calibration_Flow] ====Done====
2421 23:07:44.215564
2422 23:07:44.218603 [DutyScan_Calibration_Flow] k_type=1
2423 23:07:44.234808
2424 23:07:44.234941 ==DQS 0 ==
2425 23:07:44.238282 Final DQS duty delay cell = 0
2426 23:07:44.241479 [0] MAX Duty = 5093%(X100), DQS PI = 24
2427 23:07:44.244903 [0] MIN Duty = 4969%(X100), DQS PI = 0
2428 23:07:44.244980 [0] AVG Duty = 5031%(X100)
2429 23:07:44.245048
2430 23:07:44.248352 ==DQS 1 ==
2431 23:07:44.251989 Final DQS duty delay cell = 0
2432 23:07:44.255019 [0] MAX Duty = 5156%(X100), DQS PI = 0
2433 23:07:44.258441 [0] MIN Duty = 4844%(X100), DQS PI = 36
2434 23:07:44.258543 [0] AVG Duty = 5000%(X100)
2435 23:07:44.258681
2436 23:07:44.264937 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2437 23:07:44.265014
2438 23:07:44.268262 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2439 23:07:44.271728 [DutyScan_Calibration_Flow] ====Done====
2440 23:07:44.271805
2441 23:07:44.274817 [DutyScan_Calibration_Flow] k_type=3
2442 23:07:44.291975
2443 23:07:44.292110 ==DQM 0 ==
2444 23:07:44.295605 Final DQM duty delay cell = 4
2445 23:07:44.298905 [4] MAX Duty = 5093%(X100), DQS PI = 4
2446 23:07:44.302529 [4] MIN Duty = 4969%(X100), DQS PI = 28
2447 23:07:44.302615 [4] AVG Duty = 5031%(X100)
2448 23:07:44.305688
2449 23:07:44.305755 ==DQM 1 ==
2450 23:07:44.308821 Final DQM duty delay cell = 0
2451 23:07:44.312752 [0] MAX Duty = 5249%(X100), DQS PI = 0
2452 23:07:44.315462 [0] MIN Duty = 4907%(X100), DQS PI = 36
2453 23:07:44.315559 [0] AVG Duty = 5078%(X100)
2454 23:07:44.315638
2455 23:07:44.319004 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2456 23:07:44.322177
2457 23:07:44.325574 CH1 DQM 1 Duty spec in!! Max-Min= 342%
2458 23:07:44.328891 [DutyScan_Calibration_Flow] ====Done====
2459 23:07:44.328972
2460 23:07:44.332159 [DutyScan_Calibration_Flow] k_type=2
2461 23:07:44.348436
2462 23:07:44.348536 ==DQ 0 ==
2463 23:07:44.352007 Final DQ duty delay cell = 0
2464 23:07:44.355180 [0] MAX Duty = 5062%(X100), DQS PI = 20
2465 23:07:44.358857 [0] MIN Duty = 4938%(X100), DQS PI = 0
2466 23:07:44.358931 [0] AVG Duty = 5000%(X100)
2467 23:07:44.358994
2468 23:07:44.362079 ==DQ 1 ==
2469 23:07:44.365374 Final DQ duty delay cell = 0
2470 23:07:44.369087 [0] MAX Duty = 5031%(X100), DQS PI = 2
2471 23:07:44.371793 [0] MIN Duty = 4813%(X100), DQS PI = 36
2472 23:07:44.371863 [0] AVG Duty = 4922%(X100)
2473 23:07:44.371928
2474 23:07:44.375161 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2475 23:07:44.375232
2476 23:07:44.378572 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2477 23:07:44.385088 [DutyScan_Calibration_Flow] ====Done====
2478 23:07:44.388560 nWR fixed to 30
2479 23:07:44.388663 [ModeRegInit_LP4] CH0 RK0
2480 23:07:44.392345 [ModeRegInit_LP4] CH0 RK1
2481 23:07:44.395399 [ModeRegInit_LP4] CH1 RK0
2482 23:07:44.395477 [ModeRegInit_LP4] CH1 RK1
2483 23:07:44.398868 match AC timing 7
2484 23:07:44.401803 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2485 23:07:44.405097 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2486 23:07:44.412069 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2487 23:07:44.415552 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2488 23:07:44.422254 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2489 23:07:44.422335 ==
2490 23:07:44.425461 Dram Type= 6, Freq= 0, CH_0, rank 0
2491 23:07:44.428582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2492 23:07:44.428711 ==
2493 23:07:44.435436 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2494 23:07:44.438819 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2495 23:07:44.448374 [CA 0] Center 38 (7~69) winsize 63
2496 23:07:44.451699 [CA 1] Center 38 (8~69) winsize 62
2497 23:07:44.455277 [CA 2] Center 35 (4~66) winsize 63
2498 23:07:44.458662 [CA 3] Center 35 (4~66) winsize 63
2499 23:07:44.461468 [CA 4] Center 34 (4~65) winsize 62
2500 23:07:44.465205 [CA 5] Center 33 (3~64) winsize 62
2501 23:07:44.465277
2502 23:07:44.468176 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2503 23:07:44.468266
2504 23:07:44.471567 [CATrainingPosCal] consider 1 rank data
2505 23:07:44.474826 u2DelayCellTimex100 = 270/100 ps
2506 23:07:44.478552 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2507 23:07:44.481778 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2508 23:07:44.488156 CA2 delay=35 (4~66),Diff = 2 PI (9 cell)
2509 23:07:44.491584 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2510 23:07:44.495402 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2511 23:07:44.498306 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2512 23:07:44.498376
2513 23:07:44.501510 CA PerBit enable=1, Macro0, CA PI delay=33
2514 23:07:44.501584
2515 23:07:44.504986 [CBTSetCACLKResult] CA Dly = 33
2516 23:07:44.505055 CS Dly: 6 (0~37)
2517 23:07:44.505119 ==
2518 23:07:44.508251 Dram Type= 6, Freq= 0, CH_0, rank 1
2519 23:07:44.514848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 23:07:44.514926 ==
2521 23:07:44.518489 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2522 23:07:44.525210 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2523 23:07:44.534211 [CA 0] Center 39 (8~70) winsize 63
2524 23:07:44.537614 [CA 1] Center 38 (8~69) winsize 62
2525 23:07:44.541147 [CA 2] Center 35 (5~66) winsize 62
2526 23:07:44.544118 [CA 3] Center 35 (5~66) winsize 62
2527 23:07:44.547489 [CA 4] Center 34 (4~65) winsize 62
2528 23:07:44.551057 [CA 5] Center 34 (4~64) winsize 61
2529 23:07:44.551160
2530 23:07:44.554093 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2531 23:07:44.554178
2532 23:07:44.557382 [CATrainingPosCal] consider 2 rank data
2533 23:07:44.560933 u2DelayCellTimex100 = 270/100 ps
2534 23:07:44.564061 CA0 delay=38 (8~69),Diff = 4 PI (19 cell)
2535 23:07:44.567398 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
2536 23:07:44.574175 CA2 delay=35 (5~66),Diff = 1 PI (4 cell)
2537 23:07:44.577379 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2538 23:07:44.581058 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2539 23:07:44.584255 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2540 23:07:44.584343
2541 23:07:44.587664 CA PerBit enable=1, Macro0, CA PI delay=34
2542 23:07:44.587748
2543 23:07:44.591030 [CBTSetCACLKResult] CA Dly = 34
2544 23:07:44.591115 CS Dly: 7 (0~39)
2545 23:07:44.591183
2546 23:07:44.594454 ----->DramcWriteLeveling(PI) begin...
2547 23:07:44.594566 ==
2548 23:07:44.597760 Dram Type= 6, Freq= 0, CH_0, rank 0
2549 23:07:44.604235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2550 23:07:44.604320 ==
2551 23:07:44.607798 Write leveling (Byte 0): 34 => 34
2552 23:07:44.611349 Write leveling (Byte 1): 30 => 30
2553 23:07:44.611433 DramcWriteLeveling(PI) end<-----
2554 23:07:44.611500
2555 23:07:44.614642 ==
2556 23:07:44.617828 Dram Type= 6, Freq= 0, CH_0, rank 0
2557 23:07:44.621302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2558 23:07:44.621386 ==
2559 23:07:44.624634 [Gating] SW mode calibration
2560 23:07:44.630930 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2561 23:07:44.634188 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2562 23:07:44.640807 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2563 23:07:44.644367 0 15 4 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
2564 23:07:44.647357 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2565 23:07:44.654214 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2566 23:07:44.657438 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2567 23:07:44.660729 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2568 23:07:44.667346 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
2569 23:07:44.670638 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2570 23:07:44.674150 1 0 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
2571 23:07:44.680898 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2572 23:07:44.684112 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2573 23:07:44.687718 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 23:07:44.694011 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2575 23:07:44.697749 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2576 23:07:44.700814 1 0 24 | B1->B0 | 2323 3737 | 0 0 | (0 0) (1 1)
2577 23:07:44.707411 1 0 28 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2578 23:07:44.710837 1 1 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
2579 23:07:44.714124 1 1 4 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
2580 23:07:44.717685 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 23:07:44.724112 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 23:07:44.727653 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 23:07:44.730899 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 23:07:44.737715 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2585 23:07:44.741173 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2586 23:07:44.744247 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2587 23:07:44.751379 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2588 23:07:44.754099 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 23:07:44.757780 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 23:07:44.764262 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 23:07:44.767713 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 23:07:44.771017 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 23:07:44.777420 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 23:07:44.780849 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 23:07:44.784261 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 23:07:44.787620 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 23:07:44.794186 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 23:07:44.797724 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 23:07:44.801043 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 23:07:44.807694 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2601 23:07:44.810913 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2602 23:07:44.814097 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2603 23:07:44.817877 Total UI for P1: 0, mck2ui 16
2604 23:07:44.820973 best dqsien dly found for B0: ( 1, 3, 26)
2605 23:07:44.827539 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 23:07:44.827653 Total UI for P1: 0, mck2ui 16
2607 23:07:44.834487 best dqsien dly found for B1: ( 1, 3, 30)
2608 23:07:44.837632 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2609 23:07:44.841389 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2610 23:07:44.841474
2611 23:07:44.844418 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2612 23:07:44.848005 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2613 23:07:44.851202 [Gating] SW calibration Done
2614 23:07:44.851287 ==
2615 23:07:44.854738 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 23:07:44.857783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 23:07:44.857911 ==
2618 23:07:44.861003 RX Vref Scan: 0
2619 23:07:44.861087
2620 23:07:44.861154 RX Vref 0 -> 0, step: 1
2621 23:07:44.861217
2622 23:07:44.864756 RX Delay -40 -> 252, step: 8
2623 23:07:44.867993 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2624 23:07:44.874626 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2625 23:07:44.877787 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2626 23:07:44.881064 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2627 23:07:44.884427 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2628 23:07:44.887805 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2629 23:07:44.894551 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2630 23:07:44.897550 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2631 23:07:44.901619 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2632 23:07:44.904569 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2633 23:07:44.907934 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2634 23:07:44.911376 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2635 23:07:44.918277 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2636 23:07:44.921418 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2637 23:07:44.924530 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2638 23:07:44.928023 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2639 23:07:44.928114 ==
2640 23:07:44.931327 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 23:07:44.937946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 23:07:44.938097 ==
2643 23:07:44.938163 DQS Delay:
2644 23:07:44.938225 DQS0 = 0, DQS1 = 0
2645 23:07:44.941630 DQM Delay:
2646 23:07:44.941774 DQM0 = 122, DQM1 = 110
2647 23:07:44.944767 DQ Delay:
2648 23:07:44.948393 DQ0 =123, DQ1 =119, DQ2 =119, DQ3 =119
2649 23:07:44.951461 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2650 23:07:44.954672 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2651 23:07:44.957926 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2652 23:07:44.958068
2653 23:07:44.958193
2654 23:07:44.958314 ==
2655 23:07:44.961220 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 23:07:44.964772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 23:07:44.964879 ==
2658 23:07:44.967842
2659 23:07:44.967932
2660 23:07:44.968002 TX Vref Scan disable
2661 23:07:44.971181 == TX Byte 0 ==
2662 23:07:44.974607 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2663 23:07:44.977836 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2664 23:07:44.981298 == TX Byte 1 ==
2665 23:07:44.984841 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2666 23:07:44.987879 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2667 23:07:44.987984 ==
2668 23:07:44.991294 Dram Type= 6, Freq= 0, CH_0, rank 0
2669 23:07:44.998203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2670 23:07:44.998288 ==
2671 23:07:45.008568 TX Vref=22, minBit 1, minWin=24, winSum=411
2672 23:07:45.012045 TX Vref=24, minBit 7, minWin=24, winSum=415
2673 23:07:45.015143 TX Vref=26, minBit 7, minWin=24, winSum=418
2674 23:07:45.018575 TX Vref=28, minBit 5, minWin=25, winSum=422
2675 23:07:45.021838 TX Vref=30, minBit 3, minWin=25, winSum=426
2676 23:07:45.028332 TX Vref=32, minBit 1, minWin=25, winSum=418
2677 23:07:45.032137 [TxChooseVref] Worse bit 3, Min win 25, Win sum 426, Final Vref 30
2678 23:07:45.032217
2679 23:07:45.035194 Final TX Range 1 Vref 30
2680 23:07:45.035267
2681 23:07:45.035331 ==
2682 23:07:45.038531 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 23:07:45.041748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 23:07:45.041819 ==
2685 23:07:45.041894
2686 23:07:45.045270
2687 23:07:45.045340 TX Vref Scan disable
2688 23:07:45.048742 == TX Byte 0 ==
2689 23:07:45.051967 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2690 23:07:45.055118 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2691 23:07:45.058554 == TX Byte 1 ==
2692 23:07:45.061777 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2693 23:07:45.065307 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2694 23:07:45.065409
2695 23:07:45.068513 [DATLAT]
2696 23:07:45.068591 Freq=1200, CH0 RK0
2697 23:07:45.068658
2698 23:07:45.071714 DATLAT Default: 0xd
2699 23:07:45.071785 0, 0xFFFF, sum = 0
2700 23:07:45.075080 1, 0xFFFF, sum = 0
2701 23:07:45.075153 2, 0xFFFF, sum = 0
2702 23:07:45.078326 3, 0xFFFF, sum = 0
2703 23:07:45.078398 4, 0xFFFF, sum = 0
2704 23:07:45.081643 5, 0xFFFF, sum = 0
2705 23:07:45.081723 6, 0xFFFF, sum = 0
2706 23:07:45.085485 7, 0xFFFF, sum = 0
2707 23:07:45.088538 8, 0xFFFF, sum = 0
2708 23:07:45.088645 9, 0xFFFF, sum = 0
2709 23:07:45.092133 10, 0xFFFF, sum = 0
2710 23:07:45.092242 11, 0xFFFF, sum = 0
2711 23:07:45.095083 12, 0x0, sum = 1
2712 23:07:45.095186 13, 0x0, sum = 2
2713 23:07:45.098589 14, 0x0, sum = 3
2714 23:07:45.098680 15, 0x0, sum = 4
2715 23:07:45.098774 best_step = 13
2716 23:07:45.098863
2717 23:07:45.101857 ==
2718 23:07:45.101959 Dram Type= 6, Freq= 0, CH_0, rank 0
2719 23:07:45.108610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2720 23:07:45.108717 ==
2721 23:07:45.108810 RX Vref Scan: 1
2722 23:07:45.108902
2723 23:07:45.112075 Set Vref Range= 32 -> 127
2724 23:07:45.112172
2725 23:07:45.115301 RX Vref 32 -> 127, step: 1
2726 23:07:45.115409
2727 23:07:45.118738 RX Delay -13 -> 252, step: 4
2728 23:07:45.118838
2729 23:07:45.122410 Set Vref, RX VrefLevel [Byte0]: 32
2730 23:07:45.125184 [Byte1]: 32
2731 23:07:45.125255
2732 23:07:45.128587 Set Vref, RX VrefLevel [Byte0]: 33
2733 23:07:45.132017 [Byte1]: 33
2734 23:07:45.132094
2735 23:07:45.135474 Set Vref, RX VrefLevel [Byte0]: 34
2736 23:07:45.138667 [Byte1]: 34
2737 23:07:45.142737
2738 23:07:45.142812 Set Vref, RX VrefLevel [Byte0]: 35
2739 23:07:45.145892 [Byte1]: 35
2740 23:07:45.150720
2741 23:07:45.150793 Set Vref, RX VrefLevel [Byte0]: 36
2742 23:07:45.153751 [Byte1]: 36
2743 23:07:45.158587
2744 23:07:45.158662 Set Vref, RX VrefLevel [Byte0]: 37
2745 23:07:45.161804 [Byte1]: 37
2746 23:07:45.166207
2747 23:07:45.166279 Set Vref, RX VrefLevel [Byte0]: 38
2748 23:07:45.169533 [Byte1]: 38
2749 23:07:45.174376
2750 23:07:45.174481 Set Vref, RX VrefLevel [Byte0]: 39
2751 23:07:45.177597 [Byte1]: 39
2752 23:07:45.182182
2753 23:07:45.182295 Set Vref, RX VrefLevel [Byte0]: 40
2754 23:07:45.185687 [Byte1]: 40
2755 23:07:45.189957
2756 23:07:45.190038 Set Vref, RX VrefLevel [Byte0]: 41
2757 23:07:45.193559 [Byte1]: 41
2758 23:07:45.198067
2759 23:07:45.198151 Set Vref, RX VrefLevel [Byte0]: 42
2760 23:07:45.201070 [Byte1]: 42
2761 23:07:45.206081
2762 23:07:45.206155 Set Vref, RX VrefLevel [Byte0]: 43
2763 23:07:45.209216 [Byte1]: 43
2764 23:07:45.213726
2765 23:07:45.213829 Set Vref, RX VrefLevel [Byte0]: 44
2766 23:07:45.216870 [Byte1]: 44
2767 23:07:45.221374
2768 23:07:45.221448 Set Vref, RX VrefLevel [Byte0]: 45
2769 23:07:45.224794 [Byte1]: 45
2770 23:07:45.229215
2771 23:07:45.229318 Set Vref, RX VrefLevel [Byte0]: 46
2772 23:07:45.232582 [Byte1]: 46
2773 23:07:45.237271
2774 23:07:45.237377 Set Vref, RX VrefLevel [Byte0]: 47
2775 23:07:45.240694 [Byte1]: 47
2776 23:07:45.245149
2777 23:07:45.245223 Set Vref, RX VrefLevel [Byte0]: 48
2778 23:07:45.248479 [Byte1]: 48
2779 23:07:45.253275
2780 23:07:45.253351 Set Vref, RX VrefLevel [Byte0]: 49
2781 23:07:45.256277 [Byte1]: 49
2782 23:07:45.260952
2783 23:07:45.261027 Set Vref, RX VrefLevel [Byte0]: 50
2784 23:07:45.264120 [Byte1]: 50
2785 23:07:45.268742
2786 23:07:45.268846 Set Vref, RX VrefLevel [Byte0]: 51
2787 23:07:45.272285 [Byte1]: 51
2788 23:07:45.276773
2789 23:07:45.276874 Set Vref, RX VrefLevel [Byte0]: 52
2790 23:07:45.280053 [Byte1]: 52
2791 23:07:45.284917
2792 23:07:45.285025 Set Vref, RX VrefLevel [Byte0]: 53
2793 23:07:45.287933 [Byte1]: 53
2794 23:07:45.292606
2795 23:07:45.292716 Set Vref, RX VrefLevel [Byte0]: 54
2796 23:07:45.295969 [Byte1]: 54
2797 23:07:45.300637
2798 23:07:45.300741 Set Vref, RX VrefLevel [Byte0]: 55
2799 23:07:45.303557 [Byte1]: 55
2800 23:07:45.308420
2801 23:07:45.308520 Set Vref, RX VrefLevel [Byte0]: 56
2802 23:07:45.311885 [Byte1]: 56
2803 23:07:45.316099
2804 23:07:45.316199 Set Vref, RX VrefLevel [Byte0]: 57
2805 23:07:45.319336 [Byte1]: 57
2806 23:07:45.323967
2807 23:07:45.324069 Set Vref, RX VrefLevel [Byte0]: 58
2808 23:07:45.327329 [Byte1]: 58
2809 23:07:45.331933
2810 23:07:45.332040 Set Vref, RX VrefLevel [Byte0]: 59
2811 23:07:45.335103 [Byte1]: 59
2812 23:07:45.340070
2813 23:07:45.340171 Set Vref, RX VrefLevel [Byte0]: 60
2814 23:07:45.343296 [Byte1]: 60
2815 23:07:45.347608
2816 23:07:45.347714 Set Vref, RX VrefLevel [Byte0]: 61
2817 23:07:45.351338 [Byte1]: 61
2818 23:07:45.355566
2819 23:07:45.355668 Set Vref, RX VrefLevel [Byte0]: 62
2820 23:07:45.359134 [Byte1]: 62
2821 23:07:45.363440
2822 23:07:45.363536 Set Vref, RX VrefLevel [Byte0]: 63
2823 23:07:45.366875 [Byte1]: 63
2824 23:07:45.371253
2825 23:07:45.371352 Set Vref, RX VrefLevel [Byte0]: 64
2826 23:07:45.374801 [Byte1]: 64
2827 23:07:45.379245
2828 23:07:45.379343 Set Vref, RX VrefLevel [Byte0]: 65
2829 23:07:45.382450 [Byte1]: 65
2830 23:07:45.387184
2831 23:07:45.387260 Set Vref, RX VrefLevel [Byte0]: 66
2832 23:07:45.390460 [Byte1]: 66
2833 23:07:45.395007
2834 23:07:45.395089 Set Vref, RX VrefLevel [Byte0]: 67
2835 23:07:45.398612 [Byte1]: 67
2836 23:07:45.402983
2837 23:07:45.403055 Set Vref, RX VrefLevel [Byte0]: 68
2838 23:07:45.406772 [Byte1]: 68
2839 23:07:45.411034
2840 23:07:45.411206 Set Vref, RX VrefLevel [Byte0]: 69
2841 23:07:45.414112 [Byte1]: 69
2842 23:07:45.418766
2843 23:07:45.418865 Final RX Vref Byte 0 = 58 to rank0
2844 23:07:45.422124 Final RX Vref Byte 1 = 51 to rank0
2845 23:07:45.425833 Final RX Vref Byte 0 = 58 to rank1
2846 23:07:45.429123 Final RX Vref Byte 1 = 51 to rank1==
2847 23:07:45.432306 Dram Type= 6, Freq= 0, CH_0, rank 0
2848 23:07:45.439148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2849 23:07:45.439256 ==
2850 23:07:45.439350 DQS Delay:
2851 23:07:45.439441 DQS0 = 0, DQS1 = 0
2852 23:07:45.442429 DQM Delay:
2853 23:07:45.442502 DQM0 = 122, DQM1 = 109
2854 23:07:45.445686 DQ Delay:
2855 23:07:45.448857 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2856 23:07:45.452065 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2857 23:07:45.455706 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =104
2858 23:07:45.459131 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2859 23:07:45.459233
2860 23:07:45.459325
2861 23:07:45.465723 [DQSOSCAuto] RK0, (LSB)MR18= 0xb08, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2862 23:07:45.469181 CH0 RK0: MR19=404, MR18=B08
2863 23:07:45.475775 CH0_RK0: MR19=0x404, MR18=0xB08, DQSOSC=405, MR23=63, INC=39, DEC=26
2864 23:07:45.475894
2865 23:07:45.478928 ----->DramcWriteLeveling(PI) begin...
2866 23:07:45.479005 ==
2867 23:07:45.482580 Dram Type= 6, Freq= 0, CH_0, rank 1
2868 23:07:45.485927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2869 23:07:45.486020 ==
2870 23:07:45.488977 Write leveling (Byte 0): 35 => 35
2871 23:07:45.492657 Write leveling (Byte 1): 31 => 31
2872 23:07:45.496193 DramcWriteLeveling(PI) end<-----
2873 23:07:45.496302
2874 23:07:45.496396 ==
2875 23:07:45.499468 Dram Type= 6, Freq= 0, CH_0, rank 1
2876 23:07:45.502711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2877 23:07:45.502814 ==
2878 23:07:45.505776 [Gating] SW mode calibration
2879 23:07:45.512818 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2880 23:07:45.519215 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2881 23:07:45.522658 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2882 23:07:45.529480 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2883 23:07:45.532740 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2884 23:07:45.536039 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2885 23:07:45.542549 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 23:07:45.546475 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2887 23:07:45.549281 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2888 23:07:45.552684 0 15 28 | B1->B0 | 2e2e 2a2a | 1 0 | (1 0) (0 0)
2889 23:07:45.559461 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 23:07:45.562461 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2891 23:07:45.565964 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2892 23:07:45.572737 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 23:07:45.575756 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 23:07:45.579321 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 23:07:45.586094 1 0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2896 23:07:45.589264 1 0 28 | B1->B0 | 3d3d 3f3f | 0 0 | (0 0) (0 0)
2897 23:07:45.592461 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 23:07:45.599356 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 23:07:45.602754 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2900 23:07:45.606214 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 23:07:45.613009 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 23:07:45.615895 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 23:07:45.619250 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 23:07:45.625915 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2905 23:07:45.629173 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2906 23:07:45.632557 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 23:07:45.639256 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 23:07:45.642782 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 23:07:45.645972 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 23:07:45.649553 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 23:07:45.656398 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 23:07:45.659704 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 23:07:45.662917 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 23:07:45.669671 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 23:07:45.672885 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 23:07:45.676566 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 23:07:45.682864 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 23:07:45.686699 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 23:07:45.690016 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 23:07:45.696083 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2921 23:07:45.699660 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 23:07:45.703188 Total UI for P1: 0, mck2ui 16
2923 23:07:45.706524 best dqsien dly found for B0: ( 1, 3, 28)
2924 23:07:45.709717 Total UI for P1: 0, mck2ui 16
2925 23:07:45.713029 best dqsien dly found for B1: ( 1, 3, 28)
2926 23:07:45.716190 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2927 23:07:45.719481 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2928 23:07:45.719556
2929 23:07:45.723064 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2930 23:07:45.726350 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2931 23:07:45.729813 [Gating] SW calibration Done
2932 23:07:45.729919 ==
2933 23:07:45.733073 Dram Type= 6, Freq= 0, CH_0, rank 1
2934 23:07:45.736266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2935 23:07:45.736366 ==
2936 23:07:45.739833 RX Vref Scan: 0
2937 23:07:45.739916
2938 23:07:45.743327 RX Vref 0 -> 0, step: 1
2939 23:07:45.743411
2940 23:07:45.743488 RX Delay -40 -> 252, step: 8
2941 23:07:45.749642 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2942 23:07:45.753168 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2943 23:07:45.756345 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2944 23:07:45.759677 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2945 23:07:45.763156 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2946 23:07:45.769931 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2947 23:07:45.773327 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2948 23:07:45.776695 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2949 23:07:45.779733 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2950 23:07:45.783299 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2951 23:07:45.786444 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2952 23:07:45.793232 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2953 23:07:45.796508 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2954 23:07:45.799728 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2955 23:07:45.803093 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2956 23:07:45.806513 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2957 23:07:45.810082 ==
2958 23:07:45.813507 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 23:07:45.816667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 23:07:45.816772 ==
2961 23:07:45.816868 DQS Delay:
2962 23:07:45.819933 DQS0 = 0, DQS1 = 0
2963 23:07:45.820035 DQM Delay:
2964 23:07:45.823208 DQM0 = 120, DQM1 = 108
2965 23:07:45.823308 DQ Delay:
2966 23:07:45.826804 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2967 23:07:45.830057 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2968 23:07:45.833632 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2969 23:07:45.836801 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2970 23:07:45.836903
2971 23:07:45.836997
2972 23:07:45.837090 ==
2973 23:07:45.839904 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 23:07:45.843358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 23:07:45.846936 ==
2976 23:07:45.847038
2977 23:07:45.847130
2978 23:07:45.847223 TX Vref Scan disable
2979 23:07:45.850483 == TX Byte 0 ==
2980 23:07:45.853351 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2981 23:07:45.856622 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2982 23:07:45.860160 == TX Byte 1 ==
2983 23:07:45.863707 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2984 23:07:45.866833 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2985 23:07:45.866935 ==
2986 23:07:45.870243 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 23:07:45.876888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 23:07:45.877003 ==
2989 23:07:45.888235 TX Vref=22, minBit 1, minWin=24, winSum=414
2990 23:07:45.891674 TX Vref=24, minBit 0, minWin=24, winSum=415
2991 23:07:45.894932 TX Vref=26, minBit 3, minWin=24, winSum=415
2992 23:07:45.898119 TX Vref=28, minBit 3, minWin=25, winSum=422
2993 23:07:45.901324 TX Vref=30, minBit 4, minWin=25, winSum=423
2994 23:07:45.905203 TX Vref=32, minBit 0, minWin=25, winSum=420
2995 23:07:45.911645 [TxChooseVref] Worse bit 4, Min win 25, Win sum 423, Final Vref 30
2996 23:07:45.911732
2997 23:07:45.914689 Final TX Range 1 Vref 30
2998 23:07:45.914768
2999 23:07:45.914838 ==
3000 23:07:45.918457 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 23:07:45.921518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 23:07:45.921597 ==
3003 23:07:45.921663
3004 23:07:45.921727
3005 23:07:45.924788 TX Vref Scan disable
3006 23:07:45.928233 == TX Byte 0 ==
3007 23:07:45.931643 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3008 23:07:45.934785 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3009 23:07:45.938152 == TX Byte 1 ==
3010 23:07:45.941371 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3011 23:07:45.945114 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3012 23:07:45.945194
3013 23:07:45.948430 [DATLAT]
3014 23:07:45.948531 Freq=1200, CH0 RK1
3015 23:07:45.948624
3016 23:07:45.951693 DATLAT Default: 0xd
3017 23:07:45.951791 0, 0xFFFF, sum = 0
3018 23:07:45.954985 1, 0xFFFF, sum = 0
3019 23:07:45.955085 2, 0xFFFF, sum = 0
3020 23:07:45.958077 3, 0xFFFF, sum = 0
3021 23:07:45.958148 4, 0xFFFF, sum = 0
3022 23:07:45.961435 5, 0xFFFF, sum = 0
3023 23:07:45.961541 6, 0xFFFF, sum = 0
3024 23:07:45.964957 7, 0xFFFF, sum = 0
3025 23:07:45.965057 8, 0xFFFF, sum = 0
3026 23:07:45.968501 9, 0xFFFF, sum = 0
3027 23:07:45.968604 10, 0xFFFF, sum = 0
3028 23:07:45.971486 11, 0xFFFF, sum = 0
3029 23:07:45.971588 12, 0x0, sum = 1
3030 23:07:45.974732 13, 0x0, sum = 2
3031 23:07:45.974831 14, 0x0, sum = 3
3032 23:07:45.978603 15, 0x0, sum = 4
3033 23:07:45.978712 best_step = 13
3034 23:07:45.978806
3035 23:07:45.978895 ==
3036 23:07:45.981530 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 23:07:45.988238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 23:07:45.988372 ==
3039 23:07:45.988487 RX Vref Scan: 0
3040 23:07:45.988579
3041 23:07:45.991714 RX Vref 0 -> 0, step: 1
3042 23:07:45.991816
3043 23:07:45.995304 RX Delay -21 -> 252, step: 4
3044 23:07:45.998534 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3045 23:07:46.002082 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3046 23:07:46.008507 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3047 23:07:46.011864 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3048 23:07:46.015000 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3049 23:07:46.018502 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3050 23:07:46.021870 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3051 23:07:46.025107 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3052 23:07:46.031970 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3053 23:07:46.035188 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3054 23:07:46.038550 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3055 23:07:46.042086 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3056 23:07:46.045308 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3057 23:07:46.051989 iDelay=195, Bit 13, Center 112 (51 ~ 174) 124
3058 23:07:46.055066 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3059 23:07:46.058279 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3060 23:07:46.058371 ==
3061 23:07:46.061811 Dram Type= 6, Freq= 0, CH_0, rank 1
3062 23:07:46.065469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 23:07:46.065594 ==
3064 23:07:46.068327 DQS Delay:
3065 23:07:46.068399 DQS0 = 0, DQS1 = 0
3066 23:07:46.071692 DQM Delay:
3067 23:07:46.071774 DQM0 = 119, DQM1 = 108
3068 23:07:46.071839 DQ Delay:
3069 23:07:46.078479 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =112
3070 23:07:46.081871 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =124
3071 23:07:46.085228 DQ8 =98, DQ9 =96, DQ10 =108, DQ11 =104
3072 23:07:46.088742 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
3073 23:07:46.088852
3074 23:07:46.088944
3075 23:07:46.095397 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3076 23:07:46.098440 CH0 RK1: MR19=403, MR18=11F8
3077 23:07:46.105213 CH0_RK1: MR19=0x403, MR18=0x11F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3078 23:07:46.108952 [RxdqsGatingPostProcess] freq 1200
3079 23:07:46.115256 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3080 23:07:46.115382 best DQS0 dly(2T, 0.5T) = (0, 11)
3081 23:07:46.118556 best DQS1 dly(2T, 0.5T) = (0, 11)
3082 23:07:46.122197 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3083 23:07:46.125208 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3084 23:07:46.128513 best DQS0 dly(2T, 0.5T) = (0, 11)
3085 23:07:46.131998 best DQS1 dly(2T, 0.5T) = (0, 11)
3086 23:07:46.135278 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3087 23:07:46.138822 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3088 23:07:46.142054 Pre-setting of DQS Precalculation
3089 23:07:46.145328 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3090 23:07:46.145449 ==
3091 23:07:46.148626 Dram Type= 6, Freq= 0, CH_1, rank 0
3092 23:07:46.155541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 23:07:46.155637 ==
3094 23:07:46.158925 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3095 23:07:46.165209 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3096 23:07:46.174517 [CA 0] Center 37 (7~68) winsize 62
3097 23:07:46.177576 [CA 1] Center 37 (7~68) winsize 62
3098 23:07:46.181074 [CA 2] Center 35 (5~65) winsize 61
3099 23:07:46.184648 [CA 3] Center 34 (4~65) winsize 62
3100 23:07:46.187662 [CA 4] Center 34 (4~64) winsize 61
3101 23:07:46.190842 [CA 5] Center 33 (3~64) winsize 62
3102 23:07:46.190926
3103 23:07:46.194306 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3104 23:07:46.194397
3105 23:07:46.197736 [CATrainingPosCal] consider 1 rank data
3106 23:07:46.201077 u2DelayCellTimex100 = 270/100 ps
3107 23:07:46.204340 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3108 23:07:46.207771 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3109 23:07:46.211298 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3110 23:07:46.217876 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3111 23:07:46.221229 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3112 23:07:46.224467 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3113 23:07:46.224580
3114 23:07:46.228085 CA PerBit enable=1, Macro0, CA PI delay=33
3115 23:07:46.228169
3116 23:07:46.231189 [CBTSetCACLKResult] CA Dly = 33
3117 23:07:46.231272 CS Dly: 5 (0~36)
3118 23:07:46.231338 ==
3119 23:07:46.234459 Dram Type= 6, Freq= 0, CH_1, rank 1
3120 23:07:46.241367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 23:07:46.241454 ==
3122 23:07:46.244518 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3123 23:07:46.251253 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3124 23:07:46.260216 [CA 0] Center 38 (8~68) winsize 61
3125 23:07:46.263082 [CA 1] Center 38 (7~69) winsize 63
3126 23:07:46.266677 [CA 2] Center 35 (5~66) winsize 62
3127 23:07:46.269754 [CA 3] Center 35 (5~65) winsize 61
3128 23:07:46.273345 [CA 4] Center 34 (4~64) winsize 61
3129 23:07:46.276577 [CA 5] Center 34 (4~64) winsize 61
3130 23:07:46.276656
3131 23:07:46.280030 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3132 23:07:46.280104
3133 23:07:46.283056 [CATrainingPosCal] consider 2 rank data
3134 23:07:46.286774 u2DelayCellTimex100 = 270/100 ps
3135 23:07:46.290155 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3136 23:07:46.293313 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3137 23:07:46.300171 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3138 23:07:46.303418 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3139 23:07:46.306821 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3140 23:07:46.309827 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3141 23:07:46.309934
3142 23:07:46.313428 CA PerBit enable=1, Macro0, CA PI delay=34
3143 23:07:46.313534
3144 23:07:46.316733 [CBTSetCACLKResult] CA Dly = 34
3145 23:07:46.316837 CS Dly: 6 (0~39)
3146 23:07:46.316940
3147 23:07:46.320198 ----->DramcWriteLeveling(PI) begin...
3148 23:07:46.320277 ==
3149 23:07:46.323295 Dram Type= 6, Freq= 0, CH_1, rank 0
3150 23:07:46.330035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3151 23:07:46.330141 ==
3152 23:07:46.333408 Write leveling (Byte 0): 25 => 25
3153 23:07:46.337108 Write leveling (Byte 1): 28 => 28
3154 23:07:46.337212 DramcWriteLeveling(PI) end<-----
3155 23:07:46.337312
3156 23:07:46.340254 ==
3157 23:07:46.343612 Dram Type= 6, Freq= 0, CH_1, rank 0
3158 23:07:46.347473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3159 23:07:46.347559 ==
3160 23:07:46.350290 [Gating] SW mode calibration
3161 23:07:46.356795 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3162 23:07:46.360397 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3163 23:07:46.367348 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3164 23:07:46.370313 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3165 23:07:46.373858 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3166 23:07:46.380958 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3167 23:07:46.383797 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 23:07:46.387003 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 23:07:46.393838 0 15 24 | B1->B0 | 2d2d 2b2b | 0 0 | (0 0) (1 0)
3170 23:07:46.397305 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3171 23:07:46.400594 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 23:07:46.403931 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3173 23:07:46.410815 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3174 23:07:46.413816 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 23:07:46.417106 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 23:07:46.423733 1 0 20 | B1->B0 | 2525 2727 | 0 0 | (0 0) (0 0)
3177 23:07:46.427268 1 0 24 | B1->B0 | 3535 4343 | 0 0 | (0 0) (0 0)
3178 23:07:46.430512 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 23:07:46.437345 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 23:07:46.440608 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 23:07:46.444055 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 23:07:46.450853 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 23:07:46.454018 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 23:07:46.457619 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3185 23:07:46.463941 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3186 23:07:46.467615 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3187 23:07:46.470994 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 23:07:46.474064 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 23:07:46.480919 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 23:07:46.484357 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 23:07:46.487760 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 23:07:46.494206 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 23:07:46.497493 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 23:07:46.500932 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 23:07:46.507813 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 23:07:46.510731 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 23:07:46.514444 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 23:07:46.521140 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 23:07:46.524166 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 23:07:46.527453 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3201 23:07:46.534477 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3202 23:07:46.537685 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 23:07:46.540941 Total UI for P1: 0, mck2ui 16
3204 23:07:46.544388 best dqsien dly found for B0: ( 1, 3, 22)
3205 23:07:46.547796 Total UI for P1: 0, mck2ui 16
3206 23:07:46.550934 best dqsien dly found for B1: ( 1, 3, 24)
3207 23:07:46.554562 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3208 23:07:46.557790 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3209 23:07:46.557889
3210 23:07:46.561059 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3211 23:07:46.564620 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3212 23:07:46.568182 [Gating] SW calibration Done
3213 23:07:46.568280 ==
3214 23:07:46.571503 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 23:07:46.574565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 23:07:46.574665 ==
3217 23:07:46.577760 RX Vref Scan: 0
3218 23:07:46.577833
3219 23:07:46.577894 RX Vref 0 -> 0, step: 1
3220 23:07:46.577977
3221 23:07:46.581340 RX Delay -40 -> 252, step: 8
3222 23:07:46.587795 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3223 23:07:46.591523 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3224 23:07:46.594698 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3225 23:07:46.597753 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3226 23:07:46.601277 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3227 23:07:46.604747 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3228 23:07:46.611429 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3229 23:07:46.614611 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3230 23:07:46.618240 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3231 23:07:46.621520 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3232 23:07:46.624668 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3233 23:07:46.631190 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3234 23:07:46.634908 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3235 23:07:46.638073 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3236 23:07:46.641258 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3237 23:07:46.644579 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3238 23:07:46.644663 ==
3239 23:07:46.647874 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 23:07:46.654611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 23:07:46.654698 ==
3242 23:07:46.654765 DQS Delay:
3243 23:07:46.657875 DQS0 = 0, DQS1 = 0
3244 23:07:46.657999 DQM Delay:
3245 23:07:46.661397 DQM0 = 119, DQM1 = 112
3246 23:07:46.661480 DQ Delay:
3247 23:07:46.664536 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =119
3248 23:07:46.668201 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3249 23:07:46.671164 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3250 23:07:46.675036 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3251 23:07:46.675120
3252 23:07:46.675187
3253 23:07:46.675249 ==
3254 23:07:46.678137 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 23:07:46.684516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 23:07:46.684601 ==
3257 23:07:46.684669
3258 23:07:46.684730
3259 23:07:46.684790 TX Vref Scan disable
3260 23:07:46.688075 == TX Byte 0 ==
3261 23:07:46.691229 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3262 23:07:46.694586 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3263 23:07:46.697946 == TX Byte 1 ==
3264 23:07:46.701257 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3265 23:07:46.704429 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3266 23:07:46.708194 ==
3267 23:07:46.708278 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 23:07:46.714720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 23:07:46.714807 ==
3270 23:07:46.725393 TX Vref=22, minBit 1, minWin=24, winSum=406
3271 23:07:46.728584 TX Vref=24, minBit 1, minWin=25, winSum=408
3272 23:07:46.732413 TX Vref=26, minBit 3, minWin=25, winSum=414
3273 23:07:46.735811 TX Vref=28, minBit 10, minWin=25, winSum=422
3274 23:07:46.738877 TX Vref=30, minBit 11, minWin=25, winSum=423
3275 23:07:46.742526 TX Vref=32, minBit 9, minWin=25, winSum=423
3276 23:07:46.748988 [TxChooseVref] Worse bit 11, Min win 25, Win sum 423, Final Vref 30
3277 23:07:46.749079
3278 23:07:46.752451 Final TX Range 1 Vref 30
3279 23:07:46.752538
3280 23:07:46.752624 ==
3281 23:07:46.755652 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 23:07:46.758900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 23:07:46.758987 ==
3284 23:07:46.762295
3285 23:07:46.762381
3286 23:07:46.762468 TX Vref Scan disable
3287 23:07:46.765614 == TX Byte 0 ==
3288 23:07:46.769042 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3289 23:07:46.772259 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3290 23:07:46.775849 == TX Byte 1 ==
3291 23:07:46.778864 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3292 23:07:46.782329 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3293 23:07:46.782414
3294 23:07:46.785538 [DATLAT]
3295 23:07:46.785624 Freq=1200, CH1 RK0
3296 23:07:46.785729
3297 23:07:46.788897 DATLAT Default: 0xd
3298 23:07:46.788983 0, 0xFFFF, sum = 0
3299 23:07:46.792458 1, 0xFFFF, sum = 0
3300 23:07:46.792546 2, 0xFFFF, sum = 0
3301 23:07:46.795533 3, 0xFFFF, sum = 0
3302 23:07:46.795621 4, 0xFFFF, sum = 0
3303 23:07:46.799095 5, 0xFFFF, sum = 0
3304 23:07:46.799182 6, 0xFFFF, sum = 0
3305 23:07:46.802317 7, 0xFFFF, sum = 0
3306 23:07:46.805815 8, 0xFFFF, sum = 0
3307 23:07:46.805902 9, 0xFFFF, sum = 0
3308 23:07:46.809003 10, 0xFFFF, sum = 0
3309 23:07:46.809090 11, 0xFFFF, sum = 0
3310 23:07:46.811982 12, 0x0, sum = 1
3311 23:07:46.812094 13, 0x0, sum = 2
3312 23:07:46.815800 14, 0x0, sum = 3
3313 23:07:46.815887 15, 0x0, sum = 4
3314 23:07:46.815973 best_step = 13
3315 23:07:46.816053
3316 23:07:46.818950 ==
3317 23:07:46.822245 Dram Type= 6, Freq= 0, CH_1, rank 0
3318 23:07:46.825602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3319 23:07:46.825737 ==
3320 23:07:46.825857 RX Vref Scan: 1
3321 23:07:46.825977
3322 23:07:46.828884 Set Vref Range= 32 -> 127
3323 23:07:46.828969
3324 23:07:46.832194 RX Vref 32 -> 127, step: 1
3325 23:07:46.832296
3326 23:07:46.835512 RX Delay -13 -> 252, step: 4
3327 23:07:46.835598
3328 23:07:46.838928 Set Vref, RX VrefLevel [Byte0]: 32
3329 23:07:46.842326 [Byte1]: 32
3330 23:07:46.842439
3331 23:07:46.845664 Set Vref, RX VrefLevel [Byte0]: 33
3332 23:07:46.848830 [Byte1]: 33
3333 23:07:46.848914
3334 23:07:46.853199 Set Vref, RX VrefLevel [Byte0]: 34
3335 23:07:46.855622 [Byte1]: 34
3336 23:07:46.859853
3337 23:07:46.859935 Set Vref, RX VrefLevel [Byte0]: 35
3338 23:07:46.862894 [Byte1]: 35
3339 23:07:46.867913
3340 23:07:46.867995 Set Vref, RX VrefLevel [Byte0]: 36
3341 23:07:46.870885 [Byte1]: 36
3342 23:07:46.875677
3343 23:07:46.875759 Set Vref, RX VrefLevel [Byte0]: 37
3344 23:07:46.878996 [Byte1]: 37
3345 23:07:46.883600
3346 23:07:46.883682 Set Vref, RX VrefLevel [Byte0]: 38
3347 23:07:46.886673 [Byte1]: 38
3348 23:07:46.891427
3349 23:07:46.891506 Set Vref, RX VrefLevel [Byte0]: 39
3350 23:07:46.894492 [Byte1]: 39
3351 23:07:46.899502
3352 23:07:46.899581 Set Vref, RX VrefLevel [Byte0]: 40
3353 23:07:46.902647 [Byte1]: 40
3354 23:07:46.907237
3355 23:07:46.907317 Set Vref, RX VrefLevel [Byte0]: 41
3356 23:07:46.910268 [Byte1]: 41
3357 23:07:46.914892
3358 23:07:46.914968 Set Vref, RX VrefLevel [Byte0]: 42
3359 23:07:46.918320 [Byte1]: 42
3360 23:07:46.922803
3361 23:07:46.922874 Set Vref, RX VrefLevel [Byte0]: 43
3362 23:07:46.925996 [Byte1]: 43
3363 23:07:46.930619
3364 23:07:46.930696 Set Vref, RX VrefLevel [Byte0]: 44
3365 23:07:46.934662 [Byte1]: 44
3366 23:07:46.938506
3367 23:07:46.938581 Set Vref, RX VrefLevel [Byte0]: 45
3368 23:07:46.941969 [Byte1]: 45
3369 23:07:46.946659
3370 23:07:46.946738 Set Vref, RX VrefLevel [Byte0]: 46
3371 23:07:46.949891 [Byte1]: 46
3372 23:07:46.954531
3373 23:07:46.954630 Set Vref, RX VrefLevel [Byte0]: 47
3374 23:07:46.957782 [Byte1]: 47
3375 23:07:46.962154
3376 23:07:46.962225 Set Vref, RX VrefLevel [Byte0]: 48
3377 23:07:46.965566 [Byte1]: 48
3378 23:07:46.970189
3379 23:07:46.970261 Set Vref, RX VrefLevel [Byte0]: 49
3380 23:07:46.973601 [Byte1]: 49
3381 23:07:46.978360
3382 23:07:46.978436 Set Vref, RX VrefLevel [Byte0]: 50
3383 23:07:46.981327 [Byte1]: 50
3384 23:07:46.986063
3385 23:07:46.986138 Set Vref, RX VrefLevel [Byte0]: 51
3386 23:07:46.989345 [Byte1]: 51
3387 23:07:46.993935
3388 23:07:46.994047 Set Vref, RX VrefLevel [Byte0]: 52
3389 23:07:46.997303 [Byte1]: 52
3390 23:07:47.001639
3391 23:07:47.001740 Set Vref, RX VrefLevel [Byte0]: 53
3392 23:07:47.005408 [Byte1]: 53
3393 23:07:47.009718
3394 23:07:47.009802 Set Vref, RX VrefLevel [Byte0]: 54
3395 23:07:47.013004 [Byte1]: 54
3396 23:07:47.017722
3397 23:07:47.017801 Set Vref, RX VrefLevel [Byte0]: 55
3398 23:07:47.021035 [Byte1]: 55
3399 23:07:47.025172
3400 23:07:47.025268 Set Vref, RX VrefLevel [Byte0]: 56
3401 23:07:47.028530 [Byte1]: 56
3402 23:07:47.033267
3403 23:07:47.033340 Set Vref, RX VrefLevel [Byte0]: 57
3404 23:07:47.036803 [Byte1]: 57
3405 23:07:47.041495
3406 23:07:47.041573 Set Vref, RX VrefLevel [Byte0]: 58
3407 23:07:47.044575 [Byte1]: 58
3408 23:07:47.049025
3409 23:07:47.049101 Set Vref, RX VrefLevel [Byte0]: 59
3410 23:07:47.052552 [Byte1]: 59
3411 23:07:47.056919
3412 23:07:47.056993 Set Vref, RX VrefLevel [Byte0]: 60
3413 23:07:47.060285 [Byte1]: 60
3414 23:07:47.064708
3415 23:07:47.064785 Set Vref, RX VrefLevel [Byte0]: 61
3416 23:07:47.068280 [Byte1]: 61
3417 23:07:47.072763
3418 23:07:47.072862 Set Vref, RX VrefLevel [Byte0]: 62
3419 23:07:47.076107 [Byte1]: 62
3420 23:07:47.080358
3421 23:07:47.080437 Set Vref, RX VrefLevel [Byte0]: 63
3422 23:07:47.083672 [Byte1]: 63
3423 23:07:47.088627
3424 23:07:47.088728 Set Vref, RX VrefLevel [Byte0]: 64
3425 23:07:47.091631 [Byte1]: 64
3426 23:07:47.096569
3427 23:07:47.096672 Set Vref, RX VrefLevel [Byte0]: 65
3428 23:07:47.099594 [Byte1]: 65
3429 23:07:47.104098
3430 23:07:47.104202 Set Vref, RX VrefLevel [Byte0]: 66
3431 23:07:47.107666 [Byte1]: 66
3432 23:07:47.111990
3433 23:07:47.112092 Set Vref, RX VrefLevel [Byte0]: 67
3434 23:07:47.115425 [Byte1]: 67
3435 23:07:47.120414
3436 23:07:47.120530 Final RX Vref Byte 0 = 51 to rank0
3437 23:07:47.123444 Final RX Vref Byte 1 = 49 to rank0
3438 23:07:47.126907 Final RX Vref Byte 0 = 51 to rank1
3439 23:07:47.130153 Final RX Vref Byte 1 = 49 to rank1==
3440 23:07:47.133794 Dram Type= 6, Freq= 0, CH_1, rank 0
3441 23:07:47.140066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3442 23:07:47.140144 ==
3443 23:07:47.140244 DQS Delay:
3444 23:07:47.140374 DQS0 = 0, DQS1 = 0
3445 23:07:47.143913 DQM Delay:
3446 23:07:47.143984 DQM0 = 119, DQM1 = 111
3447 23:07:47.147338 DQ Delay:
3448 23:07:47.150315 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3449 23:07:47.153530 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =118
3450 23:07:47.156580 DQ8 =98, DQ9 =100, DQ10 =114, DQ11 =104
3451 23:07:47.159868 DQ12 =122, DQ13 =116, DQ14 =118, DQ15 =118
3452 23:07:47.159939
3453 23:07:47.160001
3454 23:07:47.166911 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3455 23:07:47.170411 CH1 RK0: MR19=404, MR18=114
3456 23:07:47.176815 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3457 23:07:47.176921
3458 23:07:47.180017 ----->DramcWriteLeveling(PI) begin...
3459 23:07:47.180118 ==
3460 23:07:47.183343 Dram Type= 6, Freq= 0, CH_1, rank 1
3461 23:07:47.186861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3462 23:07:47.186941 ==
3463 23:07:47.190139 Write leveling (Byte 0): 25 => 25
3464 23:07:47.193966 Write leveling (Byte 1): 29 => 29
3465 23:07:47.196902 DramcWriteLeveling(PI) end<-----
3466 23:07:47.197003
3467 23:07:47.197097 ==
3468 23:07:47.200343 Dram Type= 6, Freq= 0, CH_1, rank 1
3469 23:07:47.203734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3470 23:07:47.207200 ==
3471 23:07:47.207288 [Gating] SW mode calibration
3472 23:07:47.213649 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3473 23:07:47.220414 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3474 23:07:47.223814 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3475 23:07:47.230655 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3476 23:07:47.233848 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3477 23:07:47.237235 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3478 23:07:47.243887 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3479 23:07:47.247272 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3480 23:07:47.251016 0 15 24 | B1->B0 | 2727 3333 | 1 1 | (1 0) (1 0)
3481 23:07:47.253768 0 15 28 | B1->B0 | 2323 2b2b | 0 0 | (1 0) (1 0)
3482 23:07:47.260307 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3483 23:07:47.263831 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3484 23:07:47.267118 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3485 23:07:47.273847 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3486 23:07:47.277219 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3487 23:07:47.280651 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3488 23:07:47.287184 1 0 24 | B1->B0 | 3e3e 2626 | 0 0 | (1 1) (0 0)
3489 23:07:47.290561 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3490 23:07:47.293732 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3491 23:07:47.300823 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 23:07:47.303865 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3493 23:07:47.307324 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3494 23:07:47.314251 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3495 23:07:47.317502 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 23:07:47.320667 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3497 23:07:47.327520 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3498 23:07:47.330744 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 23:07:47.334216 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 23:07:47.337517 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 23:07:47.344276 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 23:07:47.347387 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 23:07:47.350525 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 23:07:47.357245 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 23:07:47.360582 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 23:07:47.364085 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 23:07:47.370527 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 23:07:47.373714 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 23:07:47.377776 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 23:07:47.383772 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 23:07:47.387180 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3512 23:07:47.390879 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3513 23:07:47.397582 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3514 23:07:47.400364 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 23:07:47.403614 Total UI for P1: 0, mck2ui 16
3516 23:07:47.407011 best dqsien dly found for B0: ( 1, 3, 24)
3517 23:07:47.410541 Total UI for P1: 0, mck2ui 16
3518 23:07:47.413742 best dqsien dly found for B1: ( 1, 3, 26)
3519 23:07:47.416876 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3520 23:07:47.420551 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3521 23:07:47.420691
3522 23:07:47.423771 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3523 23:07:47.427104 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3524 23:07:47.430311 [Gating] SW calibration Done
3525 23:07:47.430409 ==
3526 23:07:47.433899 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 23:07:47.437014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 23:07:47.440205 ==
3529 23:07:47.440308 RX Vref Scan: 0
3530 23:07:47.440378
3531 23:07:47.443927 RX Vref 0 -> 0, step: 1
3532 23:07:47.444025
3533 23:07:47.444095 RX Delay -40 -> 252, step: 8
3534 23:07:47.450566 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3535 23:07:47.454094 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3536 23:07:47.457454 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3537 23:07:47.460481 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3538 23:07:47.463839 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3539 23:07:47.470520 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3540 23:07:47.473900 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3541 23:07:47.476977 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3542 23:07:47.480484 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3543 23:07:47.484207 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3544 23:07:47.490517 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3545 23:07:47.493769 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3546 23:07:47.497079 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3547 23:07:47.500473 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3548 23:07:47.503558 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3549 23:07:47.510182 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3550 23:07:47.510306 ==
3551 23:07:47.513730 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 23:07:47.517069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 23:07:47.517173 ==
3554 23:07:47.517266 DQS Delay:
3555 23:07:47.520526 DQS0 = 0, DQS1 = 0
3556 23:07:47.520611 DQM Delay:
3557 23:07:47.523670 DQM0 = 119, DQM1 = 113
3558 23:07:47.523754 DQ Delay:
3559 23:07:47.526904 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3560 23:07:47.530219 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3561 23:07:47.533878 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3562 23:07:47.536870 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3563 23:07:47.536980
3564 23:07:47.540518
3565 23:07:47.540602 ==
3566 23:07:47.544129 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 23:07:47.547106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 23:07:47.547191 ==
3569 23:07:47.547259
3570 23:07:47.547321
3571 23:07:47.550600 TX Vref Scan disable
3572 23:07:47.550684 == TX Byte 0 ==
3573 23:07:47.554260 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3574 23:07:47.560333 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3575 23:07:47.560418 == TX Byte 1 ==
3576 23:07:47.563846 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3577 23:07:47.570211 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3578 23:07:47.570296 ==
3579 23:07:47.573635 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 23:07:47.576891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 23:07:47.576976 ==
3582 23:07:47.589143 TX Vref=22, minBit 1, minWin=25, winSum=419
3583 23:07:47.592275 TX Vref=24, minBit 1, minWin=25, winSum=417
3584 23:07:47.595709 TX Vref=26, minBit 1, minWin=25, winSum=427
3585 23:07:47.599260 TX Vref=28, minBit 0, minWin=26, winSum=427
3586 23:07:47.602300 TX Vref=30, minBit 7, minWin=26, winSum=432
3587 23:07:47.608979 TX Vref=32, minBit 0, minWin=26, winSum=428
3588 23:07:47.612449 [TxChooseVref] Worse bit 7, Min win 26, Win sum 432, Final Vref 30
3589 23:07:47.612564
3590 23:07:47.616050 Final TX Range 1 Vref 30
3591 23:07:47.616135
3592 23:07:47.616202 ==
3593 23:07:47.619029 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 23:07:47.622310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 23:07:47.622395 ==
3596 23:07:47.622463
3597 23:07:47.625878
3598 23:07:47.625996 TX Vref Scan disable
3599 23:07:47.629031 == TX Byte 0 ==
3600 23:07:47.632374 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3601 23:07:47.635608 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3602 23:07:47.638994 == TX Byte 1 ==
3603 23:07:47.642928 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3604 23:07:47.645599 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3605 23:07:47.648998
3606 23:07:47.649081 [DATLAT]
3607 23:07:47.649148 Freq=1200, CH1 RK1
3608 23:07:47.649211
3609 23:07:47.652684 DATLAT Default: 0xd
3610 23:07:47.652768 0, 0xFFFF, sum = 0
3611 23:07:47.655980 1, 0xFFFF, sum = 0
3612 23:07:47.656066 2, 0xFFFF, sum = 0
3613 23:07:47.659213 3, 0xFFFF, sum = 0
3614 23:07:47.659326 4, 0xFFFF, sum = 0
3615 23:07:47.662501 5, 0xFFFF, sum = 0
3616 23:07:47.665575 6, 0xFFFF, sum = 0
3617 23:07:47.665660 7, 0xFFFF, sum = 0
3618 23:07:47.668881 8, 0xFFFF, sum = 0
3619 23:07:47.668967 9, 0xFFFF, sum = 0
3620 23:07:47.672422 10, 0xFFFF, sum = 0
3621 23:07:47.672508 11, 0xFFFF, sum = 0
3622 23:07:47.675958 12, 0x0, sum = 1
3623 23:07:47.676044 13, 0x0, sum = 2
3624 23:07:47.678837 14, 0x0, sum = 3
3625 23:07:47.678922 15, 0x0, sum = 4
3626 23:07:47.678990 best_step = 13
3627 23:07:47.679092
3628 23:07:47.682087 ==
3629 23:07:47.685807 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 23:07:47.688892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 23:07:47.689034 ==
3632 23:07:47.689134 RX Vref Scan: 0
3633 23:07:47.689229
3634 23:07:47.692439 RX Vref 0 -> 0, step: 1
3635 23:07:47.692523
3636 23:07:47.695688 RX Delay -13 -> 252, step: 4
3637 23:07:47.699615 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3638 23:07:47.705550 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3639 23:07:47.708902 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3640 23:07:47.712316 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3641 23:07:47.715716 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3642 23:07:47.718741 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3643 23:07:47.722536 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3644 23:07:47.728937 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3645 23:07:47.732382 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3646 23:07:47.735555 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3647 23:07:47.738825 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3648 23:07:47.742172 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3649 23:07:47.749150 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3650 23:07:47.752325 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3651 23:07:47.755567 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3652 23:07:47.758868 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3653 23:07:47.758996 ==
3654 23:07:47.762028 Dram Type= 6, Freq= 0, CH_1, rank 1
3655 23:07:47.768735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3656 23:07:47.768840 ==
3657 23:07:47.768910 DQS Delay:
3658 23:07:47.772021 DQS0 = 0, DQS1 = 0
3659 23:07:47.772106 DQM Delay:
3660 23:07:47.772174 DQM0 = 119, DQM1 = 112
3661 23:07:47.775788 DQ Delay:
3662 23:07:47.779203 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3663 23:07:47.782320 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3664 23:07:47.785365 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3665 23:07:47.789273 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =120
3666 23:07:47.789352
3667 23:07:47.789417
3668 23:07:47.798794 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 405 ps
3669 23:07:47.798880 CH1 RK1: MR19=403, MR18=CF1
3670 23:07:47.805534 CH1_RK1: MR19=0x403, MR18=0xCF1, DQSOSC=405, MR23=63, INC=39, DEC=26
3671 23:07:47.808997 [RxdqsGatingPostProcess] freq 1200
3672 23:07:47.815575 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3673 23:07:47.819016 best DQS0 dly(2T, 0.5T) = (0, 11)
3674 23:07:47.822194 best DQS1 dly(2T, 0.5T) = (0, 11)
3675 23:07:47.825509 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3676 23:07:47.825593 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3677 23:07:47.828881 best DQS0 dly(2T, 0.5T) = (0, 11)
3678 23:07:47.832327 best DQS1 dly(2T, 0.5T) = (0, 11)
3679 23:07:47.835519 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3680 23:07:47.838900 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3681 23:07:47.842225 Pre-setting of DQS Precalculation
3682 23:07:47.848806 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3683 23:07:47.855463 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3684 23:07:47.862026 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3685 23:07:47.862099
3686 23:07:47.862164
3687 23:07:47.865589 [Calibration Summary] 2400 Mbps
3688 23:07:47.865656 CH 0, Rank 0
3689 23:07:47.868780 SW Impedance : PASS
3690 23:07:47.872207 DUTY Scan : NO K
3691 23:07:47.872300 ZQ Calibration : PASS
3692 23:07:47.875516 Jitter Meter : NO K
3693 23:07:47.878882 CBT Training : PASS
3694 23:07:47.878948 Write leveling : PASS
3695 23:07:47.882274 RX DQS gating : PASS
3696 23:07:47.885804 RX DQ/DQS(RDDQC) : PASS
3697 23:07:47.885923 TX DQ/DQS : PASS
3698 23:07:47.888822 RX DATLAT : PASS
3699 23:07:47.888919 RX DQ/DQS(Engine): PASS
3700 23:07:47.892155 TX OE : NO K
3701 23:07:47.892226 All Pass.
3702 23:07:47.892288
3703 23:07:47.895624 CH 0, Rank 1
3704 23:07:47.895699 SW Impedance : PASS
3705 23:07:47.898750 DUTY Scan : NO K
3706 23:07:47.901754 ZQ Calibration : PASS
3707 23:07:47.901847 Jitter Meter : NO K
3708 23:07:47.905229 CBT Training : PASS
3709 23:07:47.908587 Write leveling : PASS
3710 23:07:47.908671 RX DQS gating : PASS
3711 23:07:47.912083 RX DQ/DQS(RDDQC) : PASS
3712 23:07:47.915119 TX DQ/DQS : PASS
3713 23:07:47.915203 RX DATLAT : PASS
3714 23:07:47.918672 RX DQ/DQS(Engine): PASS
3715 23:07:47.921759 TX OE : NO K
3716 23:07:47.921842 All Pass.
3717 23:07:47.921908
3718 23:07:47.922008 CH 1, Rank 0
3719 23:07:47.925240 SW Impedance : PASS
3720 23:07:47.928377 DUTY Scan : NO K
3721 23:07:47.928459 ZQ Calibration : PASS
3722 23:07:47.932157 Jitter Meter : NO K
3723 23:07:47.935490 CBT Training : PASS
3724 23:07:47.935574 Write leveling : PASS
3725 23:07:47.938480 RX DQS gating : PASS
3726 23:07:47.938563 RX DQ/DQS(RDDQC) : PASS
3727 23:07:47.941852 TX DQ/DQS : PASS
3728 23:07:47.945056 RX DATLAT : PASS
3729 23:07:47.945139 RX DQ/DQS(Engine): PASS
3730 23:07:47.948341 TX OE : NO K
3731 23:07:47.948424 All Pass.
3732 23:07:47.948490
3733 23:07:47.951699 CH 1, Rank 1
3734 23:07:47.951782 SW Impedance : PASS
3735 23:07:47.955012 DUTY Scan : NO K
3736 23:07:47.958228 ZQ Calibration : PASS
3737 23:07:47.958311 Jitter Meter : NO K
3738 23:07:47.961548 CBT Training : PASS
3739 23:07:47.964850 Write leveling : PASS
3740 23:07:47.964933 RX DQS gating : PASS
3741 23:07:47.968193 RX DQ/DQS(RDDQC) : PASS
3742 23:07:47.971411 TX DQ/DQS : PASS
3743 23:07:47.971495 RX DATLAT : PASS
3744 23:07:47.974835 RX DQ/DQS(Engine): PASS
3745 23:07:47.978178 TX OE : NO K
3746 23:07:47.978261 All Pass.
3747 23:07:47.978327
3748 23:07:47.981449 DramC Write-DBI off
3749 23:07:47.981532 PER_BANK_REFRESH: Hybrid Mode
3750 23:07:47.984819 TX_TRACKING: ON
3751 23:07:47.991713 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3752 23:07:47.998222 [FAST_K] Save calibration result to emmc
3753 23:07:48.001635 dramc_set_vcore_voltage set vcore to 650000
3754 23:07:48.001718 Read voltage for 600, 5
3755 23:07:48.004938 Vio18 = 0
3756 23:07:48.005020 Vcore = 650000
3757 23:07:48.005086 Vdram = 0
3758 23:07:48.008201 Vddq = 0
3759 23:07:48.008283 Vmddr = 0
3760 23:07:48.011524 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3761 23:07:48.017932 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3762 23:07:48.021159 MEM_TYPE=3, freq_sel=19
3763 23:07:48.024470 sv_algorithm_assistance_LP4_1600
3764 23:07:48.027918 ============ PULL DRAM RESETB DOWN ============
3765 23:07:48.031300 ========== PULL DRAM RESETB DOWN end =========
3766 23:07:48.034422 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3767 23:07:48.037887 ===================================
3768 23:07:48.041077 LPDDR4 DRAM CONFIGURATION
3769 23:07:48.044339 ===================================
3770 23:07:48.047672 EX_ROW_EN[0] = 0x0
3771 23:07:48.047754 EX_ROW_EN[1] = 0x0
3772 23:07:48.051524 LP4Y_EN = 0x0
3773 23:07:48.051607 WORK_FSP = 0x0
3774 23:07:48.054257 WL = 0x2
3775 23:07:48.054340 RL = 0x2
3776 23:07:48.057883 BL = 0x2
3777 23:07:48.057971 RPST = 0x0
3778 23:07:48.061001 RD_PRE = 0x0
3779 23:07:48.064312 WR_PRE = 0x1
3780 23:07:48.064397 WR_PST = 0x0
3781 23:07:48.067700 DBI_WR = 0x0
3782 23:07:48.067783 DBI_RD = 0x0
3783 23:07:48.070930 OTF = 0x1
3784 23:07:48.074169 ===================================
3785 23:07:48.077531 ===================================
3786 23:07:48.077614 ANA top config
3787 23:07:48.080885 ===================================
3788 23:07:48.084155 DLL_ASYNC_EN = 0
3789 23:07:48.087929 ALL_SLAVE_EN = 1
3790 23:07:48.088013 NEW_RANK_MODE = 1
3791 23:07:48.091315 DLL_IDLE_MODE = 1
3792 23:07:48.094763 LP45_APHY_COMB_EN = 1
3793 23:07:48.097863 TX_ODT_DIS = 1
3794 23:07:48.097953 NEW_8X_MODE = 1
3795 23:07:48.101214 ===================================
3796 23:07:48.104194 ===================================
3797 23:07:48.107662 data_rate = 1200
3798 23:07:48.111032 CKR = 1
3799 23:07:48.114307 DQ_P2S_RATIO = 8
3800 23:07:48.117664 ===================================
3801 23:07:48.121319 CA_P2S_RATIO = 8
3802 23:07:48.124301 DQ_CA_OPEN = 0
3803 23:07:48.124384 DQ_SEMI_OPEN = 0
3804 23:07:48.127762 CA_SEMI_OPEN = 0
3805 23:07:48.131232 CA_FULL_RATE = 0
3806 23:07:48.134657 DQ_CKDIV4_EN = 1
3807 23:07:48.137892 CA_CKDIV4_EN = 1
3808 23:07:48.138011 CA_PREDIV_EN = 0
3809 23:07:48.141030 PH8_DLY = 0
3810 23:07:48.144581 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3811 23:07:48.147740 DQ_AAMCK_DIV = 4
3812 23:07:48.151006 CA_AAMCK_DIV = 4
3813 23:07:48.154346 CA_ADMCK_DIV = 4
3814 23:07:48.154429 DQ_TRACK_CA_EN = 0
3815 23:07:48.158096 CA_PICK = 600
3816 23:07:48.161189 CA_MCKIO = 600
3817 23:07:48.164800 MCKIO_SEMI = 0
3818 23:07:48.168102 PLL_FREQ = 2288
3819 23:07:48.171010 DQ_UI_PI_RATIO = 32
3820 23:07:48.174846 CA_UI_PI_RATIO = 0
3821 23:07:48.177720 ===================================
3822 23:07:48.180989 ===================================
3823 23:07:48.181072 memory_type:LPDDR4
3824 23:07:48.184340 GP_NUM : 10
3825 23:07:48.187789 SRAM_EN : 1
3826 23:07:48.187872 MD32_EN : 0
3827 23:07:48.191134 ===================================
3828 23:07:48.194315 [ANA_INIT] >>>>>>>>>>>>>>
3829 23:07:48.198008 <<<<<< [CONFIGURE PHASE]: ANA_TX
3830 23:07:48.201307 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3831 23:07:48.204602 ===================================
3832 23:07:48.207630 data_rate = 1200,PCW = 0X5800
3833 23:07:48.210993 ===================================
3834 23:07:48.214284 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3835 23:07:48.217848 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3836 23:07:48.224152 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3837 23:07:48.227670 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3838 23:07:48.231020 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3839 23:07:48.234232 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3840 23:07:48.237711 [ANA_INIT] flow start
3841 23:07:48.240838 [ANA_INIT] PLL >>>>>>>>
3842 23:07:48.240921 [ANA_INIT] PLL <<<<<<<<
3843 23:07:48.244229 [ANA_INIT] MIDPI >>>>>>>>
3844 23:07:48.247594 [ANA_INIT] MIDPI <<<<<<<<
3845 23:07:48.247678 [ANA_INIT] DLL >>>>>>>>
3846 23:07:48.250687 [ANA_INIT] flow end
3847 23:07:48.254095 ============ LP4 DIFF to SE enter ============
3848 23:07:48.260706 ============ LP4 DIFF to SE exit ============
3849 23:07:48.260789 [ANA_INIT] <<<<<<<<<<<<<
3850 23:07:48.264432 [Flow] Enable top DCM control >>>>>
3851 23:07:48.267258 [Flow] Enable top DCM control <<<<<
3852 23:07:48.270972 Enable DLL master slave shuffle
3853 23:07:48.277288 ==============================================================
3854 23:07:48.277371 Gating Mode config
3855 23:07:48.283889 ==============================================================
3856 23:07:48.287215 Config description:
3857 23:07:48.293985 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3858 23:07:48.300637 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3859 23:07:48.307691 SELPH_MODE 0: By rank 1: By Phase
3860 23:07:48.310731 ==============================================================
3861 23:07:48.314013 GAT_TRACK_EN = 1
3862 23:07:48.317439 RX_GATING_MODE = 2
3863 23:07:48.320659 RX_GATING_TRACK_MODE = 2
3864 23:07:48.324368 SELPH_MODE = 1
3865 23:07:48.327501 PICG_EARLY_EN = 1
3866 23:07:48.331129 VALID_LAT_VALUE = 1
3867 23:07:48.337541 ==============================================================
3868 23:07:48.340856 Enter into Gating configuration >>>>
3869 23:07:48.343875 Exit from Gating configuration <<<<
3870 23:07:48.347827 Enter into DVFS_PRE_config >>>>>
3871 23:07:48.357328 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3872 23:07:48.360693 Exit from DVFS_PRE_config <<<<<
3873 23:07:48.364347 Enter into PICG configuration >>>>
3874 23:07:48.367416 Exit from PICG configuration <<<<
3875 23:07:48.367500 [RX_INPUT] configuration >>>>>
3876 23:07:48.370693 [RX_INPUT] configuration <<<<<
3877 23:07:48.377297 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3878 23:07:48.380635 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3879 23:07:48.387301 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3880 23:07:48.394105 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3881 23:07:48.400547 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3882 23:07:48.407146 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3883 23:07:48.410472 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3884 23:07:48.414040 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3885 23:07:48.420552 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3886 23:07:48.423882 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3887 23:07:48.427293 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3888 23:07:48.433916 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3889 23:07:48.436743 ===================================
3890 23:07:48.436828 LPDDR4 DRAM CONFIGURATION
3891 23:07:48.440436 ===================================
3892 23:07:48.443832 EX_ROW_EN[0] = 0x0
3893 23:07:48.443924 EX_ROW_EN[1] = 0x0
3894 23:07:48.446919 LP4Y_EN = 0x0
3895 23:07:48.446989 WORK_FSP = 0x0
3896 23:07:48.450409 WL = 0x2
3897 23:07:48.450484 RL = 0x2
3898 23:07:48.453862 BL = 0x2
3899 23:07:48.457006 RPST = 0x0
3900 23:07:48.457074 RD_PRE = 0x0
3901 23:07:48.460125 WR_PRE = 0x1
3902 23:07:48.460192 WR_PST = 0x0
3903 23:07:48.463898 DBI_WR = 0x0
3904 23:07:48.463965 DBI_RD = 0x0
3905 23:07:48.467000 OTF = 0x1
3906 23:07:48.470226 ===================================
3907 23:07:48.473598 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3908 23:07:48.476902 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3909 23:07:48.480325 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3910 23:07:48.483541 ===================================
3911 23:07:48.486897 LPDDR4 DRAM CONFIGURATION
3912 23:07:48.490230 ===================================
3913 23:07:48.493498 EX_ROW_EN[0] = 0x10
3914 23:07:48.493571 EX_ROW_EN[1] = 0x0
3915 23:07:48.496840 LP4Y_EN = 0x0
3916 23:07:48.496913 WORK_FSP = 0x0
3917 23:07:48.500060 WL = 0x2
3918 23:07:48.500128 RL = 0x2
3919 23:07:48.503430 BL = 0x2
3920 23:07:48.503498 RPST = 0x0
3921 23:07:48.506809 RD_PRE = 0x0
3922 23:07:48.506875 WR_PRE = 0x1
3923 23:07:48.510046 WR_PST = 0x0
3924 23:07:48.513551 DBI_WR = 0x0
3925 23:07:48.513618 DBI_RD = 0x0
3926 23:07:48.516703 OTF = 0x1
3927 23:07:48.519994 ===================================
3928 23:07:48.523340 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3929 23:07:48.528627 nWR fixed to 30
3930 23:07:48.531789 [ModeRegInit_LP4] CH0 RK0
3931 23:07:48.531861 [ModeRegInit_LP4] CH0 RK1
3932 23:07:48.534928 [ModeRegInit_LP4] CH1 RK0
3933 23:07:48.538623 [ModeRegInit_LP4] CH1 RK1
3934 23:07:48.538694 match AC timing 17
3935 23:07:48.544984 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3936 23:07:48.548461 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3937 23:07:48.551980 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3938 23:07:48.558232 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3939 23:07:48.561565 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3940 23:07:48.561635 ==
3941 23:07:48.564810 Dram Type= 6, Freq= 0, CH_0, rank 0
3942 23:07:48.568222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3943 23:07:48.568308 ==
3944 23:07:48.574980 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3945 23:07:48.581749 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3946 23:07:48.584580 [CA 0] Center 36 (6~67) winsize 62
3947 23:07:48.587997 [CA 1] Center 36 (6~67) winsize 62
3948 23:07:48.591752 [CA 2] Center 34 (4~65) winsize 62
3949 23:07:48.595064 [CA 3] Center 34 (4~65) winsize 62
3950 23:07:48.597932 [CA 4] Center 34 (3~65) winsize 63
3951 23:07:48.601889 [CA 5] Center 33 (3~64) winsize 62
3952 23:07:48.601975
3953 23:07:48.604956 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3954 23:07:48.605027
3955 23:07:48.608292 [CATrainingPosCal] consider 1 rank data
3956 23:07:48.611631 u2DelayCellTimex100 = 270/100 ps
3957 23:07:48.614847 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3958 23:07:48.617935 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3959 23:07:48.621321 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3960 23:07:48.624789 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3961 23:07:48.628053 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3962 23:07:48.634677 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3963 23:07:48.634758
3964 23:07:48.638231 CA PerBit enable=1, Macro0, CA PI delay=33
3965 23:07:48.638301
3966 23:07:48.641498 [CBTSetCACLKResult] CA Dly = 33
3967 23:07:48.641575 CS Dly: 4 (0~35)
3968 23:07:48.641636 ==
3969 23:07:48.644880 Dram Type= 6, Freq= 0, CH_0, rank 1
3970 23:07:48.647824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 23:07:48.647911 ==
3972 23:07:48.654434 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3973 23:07:48.661250 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3974 23:07:48.664470 [CA 0] Center 36 (6~67) winsize 62
3975 23:07:48.668141 [CA 1] Center 36 (6~67) winsize 62
3976 23:07:48.671296 [CA 2] Center 34 (4~65) winsize 62
3977 23:07:48.674548 [CA 3] Center 34 (4~65) winsize 62
3978 23:07:48.678167 [CA 4] Center 34 (3~65) winsize 63
3979 23:07:48.681500 [CA 5] Center 33 (3~64) winsize 62
3980 23:07:48.681574
3981 23:07:48.684865 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3982 23:07:48.684933
3983 23:07:48.687873 [CATrainingPosCal] consider 2 rank data
3984 23:07:48.691668 u2DelayCellTimex100 = 270/100 ps
3985 23:07:48.694540 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3986 23:07:48.697867 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3987 23:07:48.701552 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3988 23:07:48.704825 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3989 23:07:48.711558 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3990 23:07:48.714726 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3991 23:07:48.714797
3992 23:07:48.717795 CA PerBit enable=1, Macro0, CA PI delay=33
3993 23:07:48.717891
3994 23:07:48.721119 [CBTSetCACLKResult] CA Dly = 33
3995 23:07:48.721188 CS Dly: 5 (0~38)
3996 23:07:48.721248
3997 23:07:48.724540 ----->DramcWriteLeveling(PI) begin...
3998 23:07:48.724609 ==
3999 23:07:48.727828 Dram Type= 6, Freq= 0, CH_0, rank 0
4000 23:07:48.734522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4001 23:07:48.734599 ==
4002 23:07:48.737945 Write leveling (Byte 0): 35 => 35
4003 23:07:48.738031 Write leveling (Byte 1): 31 => 31
4004 23:07:48.741008 DramcWriteLeveling(PI) end<-----
4005 23:07:48.741078
4006 23:07:48.744239 ==
4007 23:07:48.744312 Dram Type= 6, Freq= 0, CH_0, rank 0
4008 23:07:48.751015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4009 23:07:48.751087 ==
4010 23:07:48.754196 [Gating] SW mode calibration
4011 23:07:48.760775 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4012 23:07:48.764240 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4013 23:07:48.771199 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4014 23:07:48.774257 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4015 23:07:48.777778 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4016 23:07:48.784261 0 9 12 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 1)
4017 23:07:48.787607 0 9 16 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
4018 23:07:48.790789 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4019 23:07:48.797379 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4020 23:07:48.800684 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4021 23:07:48.804038 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4022 23:07:48.810976 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4023 23:07:48.814403 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4024 23:07:48.817297 0 10 12 | B1->B0 | 2828 3939 | 0 0 | (0 0) (1 1)
4025 23:07:48.821054 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
4026 23:07:48.827290 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 23:07:48.831031 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 23:07:48.834188 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4029 23:07:48.841012 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 23:07:48.844278 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4031 23:07:48.847444 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 23:07:48.854101 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4033 23:07:48.857434 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4034 23:07:48.860962 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 23:07:48.867568 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 23:07:48.870637 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 23:07:48.874231 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 23:07:48.880860 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 23:07:48.883892 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 23:07:48.887532 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 23:07:48.894000 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 23:07:48.897237 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 23:07:48.900736 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 23:07:48.907321 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 23:07:48.910613 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 23:07:48.913823 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 23:07:48.920534 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 23:07:48.924112 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4049 23:07:48.927481 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4050 23:07:48.930705 Total UI for P1: 0, mck2ui 16
4051 23:07:48.933887 best dqsien dly found for B0: ( 0, 13, 12)
4052 23:07:48.936981 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 23:07:48.940303 Total UI for P1: 0, mck2ui 16
4054 23:07:48.943964 best dqsien dly found for B1: ( 0, 13, 16)
4055 23:07:48.950535 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4056 23:07:48.953748 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4057 23:07:48.953833
4058 23:07:48.957199 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4059 23:07:48.960558 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4060 23:07:48.964004 [Gating] SW calibration Done
4061 23:07:48.964087 ==
4062 23:07:48.967138 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 23:07:48.970144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 23:07:48.970229 ==
4065 23:07:48.973558 RX Vref Scan: 0
4066 23:07:48.973642
4067 23:07:48.973709 RX Vref 0 -> 0, step: 1
4068 23:07:48.973772
4069 23:07:48.976794 RX Delay -230 -> 252, step: 16
4070 23:07:48.980256 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4071 23:07:48.986966 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4072 23:07:48.990505 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4073 23:07:48.993504 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4074 23:07:48.996868 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4075 23:07:49.003597 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4076 23:07:49.006972 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4077 23:07:49.009996 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4078 23:07:49.013293 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4079 23:07:49.016752 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4080 23:07:49.023239 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4081 23:07:49.026856 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4082 23:07:49.030133 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4083 23:07:49.033483 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4084 23:07:49.040114 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4085 23:07:49.043532 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4086 23:07:49.043617 ==
4087 23:07:49.046713 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 23:07:49.049722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 23:07:49.049807 ==
4090 23:07:49.053336 DQS Delay:
4091 23:07:49.053419 DQS0 = 0, DQS1 = 0
4092 23:07:49.053486 DQM Delay:
4093 23:07:49.056524 DQM0 = 53, DQM1 = 43
4094 23:07:49.056607 DQ Delay:
4095 23:07:49.059999 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4096 23:07:49.063347 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4097 23:07:49.066673 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4098 23:07:49.069923 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4099 23:07:49.070027
4100 23:07:49.070094
4101 23:07:49.070154 ==
4102 23:07:49.073249 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 23:07:49.079596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 23:07:49.079681 ==
4105 23:07:49.079748
4106 23:07:49.079812
4107 23:07:49.079872 TX Vref Scan disable
4108 23:07:49.083728 == TX Byte 0 ==
4109 23:07:49.086759 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4110 23:07:49.090268 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4111 23:07:49.093486 == TX Byte 1 ==
4112 23:07:49.096964 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4113 23:07:49.103610 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4114 23:07:49.103695 ==
4115 23:07:49.106732 Dram Type= 6, Freq= 0, CH_0, rank 0
4116 23:07:49.110128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4117 23:07:49.110212 ==
4118 23:07:49.110279
4119 23:07:49.110341
4120 23:07:49.113631 TX Vref Scan disable
4121 23:07:49.116526 == TX Byte 0 ==
4122 23:07:49.119907 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4123 23:07:49.123261 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4124 23:07:49.126970 == TX Byte 1 ==
4125 23:07:49.130255 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4126 23:07:49.133532 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4127 23:07:49.133617
4128 23:07:49.133683 [DATLAT]
4129 23:07:49.136864 Freq=600, CH0 RK0
4130 23:07:49.136948
4131 23:07:49.137015 DATLAT Default: 0x9
4132 23:07:49.140107 0, 0xFFFF, sum = 0
4133 23:07:49.143482 1, 0xFFFF, sum = 0
4134 23:07:49.143568 2, 0xFFFF, sum = 0
4135 23:07:49.146900 3, 0xFFFF, sum = 0
4136 23:07:49.146986 4, 0xFFFF, sum = 0
4137 23:07:49.150202 5, 0xFFFF, sum = 0
4138 23:07:49.150288 6, 0xFFFF, sum = 0
4139 23:07:49.153523 7, 0xFFFF, sum = 0
4140 23:07:49.153607 8, 0x0, sum = 1
4141 23:07:49.153675 9, 0x0, sum = 2
4142 23:07:49.156719 10, 0x0, sum = 3
4143 23:07:49.156803 11, 0x0, sum = 4
4144 23:07:49.160074 best_step = 9
4145 23:07:49.160158
4146 23:07:49.160225 ==
4147 23:07:49.163392 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 23:07:49.166617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 23:07:49.166702 ==
4150 23:07:49.169985 RX Vref Scan: 1
4151 23:07:49.170068
4152 23:07:49.170135 RX Vref 0 -> 0, step: 1
4153 23:07:49.170195
4154 23:07:49.173255 RX Delay -163 -> 252, step: 8
4155 23:07:49.173338
4156 23:07:49.176598 Set Vref, RX VrefLevel [Byte0]: 58
4157 23:07:49.179726 [Byte1]: 51
4158 23:07:49.183958
4159 23:07:49.184042 Final RX Vref Byte 0 = 58 to rank0
4160 23:07:49.187594 Final RX Vref Byte 1 = 51 to rank0
4161 23:07:49.190531 Final RX Vref Byte 0 = 58 to rank1
4162 23:07:49.193967 Final RX Vref Byte 1 = 51 to rank1==
4163 23:07:49.197296 Dram Type= 6, Freq= 0, CH_0, rank 0
4164 23:07:49.203937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4165 23:07:49.204022 ==
4166 23:07:49.204089 DQS Delay:
4167 23:07:49.207316 DQS0 = 0, DQS1 = 0
4168 23:07:49.207399 DQM Delay:
4169 23:07:49.207466 DQM0 = 51, DQM1 = 38
4170 23:07:49.210378 DQ Delay:
4171 23:07:49.213761 DQ0 =48, DQ1 =52, DQ2 =48, DQ3 =48
4172 23:07:49.217325 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =60
4173 23:07:49.220284 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =32
4174 23:07:49.223717 DQ12 =48, DQ13 =40, DQ14 =48, DQ15 =44
4175 23:07:49.223801
4176 23:07:49.223867
4177 23:07:49.230453 [DQSOSCAuto] RK0, (LSB)MR18= 0x5d57, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4178 23:07:49.233820 CH0 RK0: MR19=808, MR18=5D57
4179 23:07:49.240447 CH0_RK0: MR19=0x808, MR18=0x5D57, DQSOSC=392, MR23=63, INC=170, DEC=113
4180 23:07:49.240531
4181 23:07:49.243790 ----->DramcWriteLeveling(PI) begin...
4182 23:07:49.243875 ==
4183 23:07:49.247132 Dram Type= 6, Freq= 0, CH_0, rank 1
4184 23:07:49.250486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 23:07:49.250571 ==
4186 23:07:49.253433 Write leveling (Byte 0): 32 => 32
4187 23:07:49.256784 Write leveling (Byte 1): 32 => 32
4188 23:07:49.260069 DramcWriteLeveling(PI) end<-----
4189 23:07:49.260153
4190 23:07:49.260219 ==
4191 23:07:49.263773 Dram Type= 6, Freq= 0, CH_0, rank 1
4192 23:07:49.266996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4193 23:07:49.267080 ==
4194 23:07:49.270288 [Gating] SW mode calibration
4195 23:07:49.277152 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4196 23:07:49.283286 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4197 23:07:49.286656 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4198 23:07:49.293260 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4199 23:07:49.297017 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4200 23:07:49.299890 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (0 1) (0 1)
4201 23:07:49.303745 0 9 16 | B1->B0 | 2828 2525 | 0 0 | (1 1) (1 0)
4202 23:07:49.310134 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4203 23:07:49.313698 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4204 23:07:49.317115 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4205 23:07:49.323403 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4206 23:07:49.326628 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4207 23:07:49.329892 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 23:07:49.336904 0 10 12 | B1->B0 | 3030 3333 | 0 0 | (0 0) (0 0)
4209 23:07:49.340189 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4210 23:07:49.343496 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 23:07:49.350195 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4212 23:07:49.353406 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4213 23:07:49.356679 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4214 23:07:49.363403 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4215 23:07:49.367045 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 23:07:49.369889 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4217 23:07:49.376487 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 23:07:49.380124 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 23:07:49.382977 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 23:07:49.389843 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 23:07:49.393424 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 23:07:49.396590 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 23:07:49.403146 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 23:07:49.406272 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 23:07:49.409549 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 23:07:49.416542 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 23:07:49.419676 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 23:07:49.423205 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 23:07:49.429736 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 23:07:49.432964 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 23:07:49.436200 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 23:07:49.442985 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4233 23:07:49.446330 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4234 23:07:49.449780 Total UI for P1: 0, mck2ui 16
4235 23:07:49.452977 best dqsien dly found for B0: ( 0, 13, 14)
4236 23:07:49.456313 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 23:07:49.459215 Total UI for P1: 0, mck2ui 16
4238 23:07:49.462601 best dqsien dly found for B1: ( 0, 13, 14)
4239 23:07:49.465913 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4240 23:07:49.469568 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4241 23:07:49.469653
4242 23:07:49.472558 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4243 23:07:49.479153 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4244 23:07:49.479238 [Gating] SW calibration Done
4245 23:07:49.479305 ==
4246 23:07:49.482472 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 23:07:49.489640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 23:07:49.489725 ==
4249 23:07:49.489792 RX Vref Scan: 0
4250 23:07:49.489855
4251 23:07:49.492764 RX Vref 0 -> 0, step: 1
4252 23:07:49.492848
4253 23:07:49.496092 RX Delay -230 -> 252, step: 16
4254 23:07:49.498945 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4255 23:07:49.502226 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4256 23:07:49.509087 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4257 23:07:49.512340 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4258 23:07:49.515998 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4259 23:07:49.518880 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4260 23:07:49.522497 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4261 23:07:49.528931 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4262 23:07:49.532587 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4263 23:07:49.535522 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4264 23:07:49.539136 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4265 23:07:49.545673 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4266 23:07:49.549089 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4267 23:07:49.552379 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4268 23:07:49.555654 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4269 23:07:49.562143 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4270 23:07:49.562227 ==
4271 23:07:49.565395 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 23:07:49.568768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 23:07:49.568853 ==
4274 23:07:49.568920 DQS Delay:
4275 23:07:49.572088 DQS0 = 0, DQS1 = 0
4276 23:07:49.572172 DQM Delay:
4277 23:07:49.575903 DQM0 = 47, DQM1 = 41
4278 23:07:49.575987 DQ Delay:
4279 23:07:49.578968 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4280 23:07:49.582405 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4281 23:07:49.585564 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4282 23:07:49.588903 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4283 23:07:49.588987
4284 23:07:49.589053
4285 23:07:49.589115 ==
4286 23:07:49.592173 Dram Type= 6, Freq= 0, CH_0, rank 1
4287 23:07:49.595491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4288 23:07:49.595575 ==
4289 23:07:49.595642
4290 23:07:49.595704
4291 23:07:49.598676 TX Vref Scan disable
4292 23:07:49.601929 == TX Byte 0 ==
4293 23:07:49.605891 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4294 23:07:49.608834 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4295 23:07:49.611925 == TX Byte 1 ==
4296 23:07:49.615336 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4297 23:07:49.618654 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4298 23:07:49.618738 ==
4299 23:07:49.621843 Dram Type= 6, Freq= 0, CH_0, rank 1
4300 23:07:49.628796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4301 23:07:49.628880 ==
4302 23:07:49.628947
4303 23:07:49.629009
4304 23:07:49.629070 TX Vref Scan disable
4305 23:07:49.633148 == TX Byte 0 ==
4306 23:07:49.636590 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4307 23:07:49.639555 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4308 23:07:49.643004 == TX Byte 1 ==
4309 23:07:49.646317 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4310 23:07:49.649922 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4311 23:07:49.653244
4312 23:07:49.653327 [DATLAT]
4313 23:07:49.653394 Freq=600, CH0 RK1
4314 23:07:49.653461
4315 23:07:49.656275 DATLAT Default: 0x9
4316 23:07:49.656359 0, 0xFFFF, sum = 0
4317 23:07:49.660016 1, 0xFFFF, sum = 0
4318 23:07:49.660100 2, 0xFFFF, sum = 0
4319 23:07:49.663318 3, 0xFFFF, sum = 0
4320 23:07:49.663403 4, 0xFFFF, sum = 0
4321 23:07:49.666559 5, 0xFFFF, sum = 0
4322 23:07:49.666644 6, 0xFFFF, sum = 0
4323 23:07:49.669926 7, 0xFFFF, sum = 0
4324 23:07:49.670049 8, 0x0, sum = 1
4325 23:07:49.673203 9, 0x0, sum = 2
4326 23:07:49.673288 10, 0x0, sum = 3
4327 23:07:49.676394 11, 0x0, sum = 4
4328 23:07:49.676479 best_step = 9
4329 23:07:49.676546
4330 23:07:49.676607 ==
4331 23:07:49.680056 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 23:07:49.686241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 23:07:49.686324 ==
4334 23:07:49.686390 RX Vref Scan: 0
4335 23:07:49.686450
4336 23:07:49.689601 RX Vref 0 -> 0, step: 1
4337 23:07:49.689682
4338 23:07:49.692768 RX Delay -179 -> 252, step: 8
4339 23:07:49.696107 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4340 23:07:49.703117 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4341 23:07:49.706503 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4342 23:07:49.709762 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4343 23:07:49.712821 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4344 23:07:49.716590 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4345 23:07:49.719478 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4346 23:07:49.725955 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4347 23:07:49.729870 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4348 23:07:49.732874 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4349 23:07:49.736287 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4350 23:07:49.742676 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4351 23:07:49.746274 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4352 23:07:49.749416 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4353 23:07:49.752552 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4354 23:07:49.756004 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4355 23:07:49.759344 ==
4356 23:07:49.763153 Dram Type= 6, Freq= 0, CH_0, rank 1
4357 23:07:49.765988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4358 23:07:49.766072 ==
4359 23:07:49.766137 DQS Delay:
4360 23:07:49.769512 DQS0 = 0, DQS1 = 0
4361 23:07:49.769594 DQM Delay:
4362 23:07:49.772680 DQM0 = 48, DQM1 = 40
4363 23:07:49.772762 DQ Delay:
4364 23:07:49.775877 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4365 23:07:49.779529 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4366 23:07:49.782501 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4367 23:07:49.785926 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4368 23:07:49.786046
4369 23:07:49.786110
4370 23:07:49.792680 [DQSOSCAuto] RK1, (LSB)MR18= 0x6431, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
4371 23:07:49.795603 CH0 RK1: MR19=808, MR18=6431
4372 23:07:49.802662 CH0_RK1: MR19=0x808, MR18=0x6431, DQSOSC=391, MR23=63, INC=171, DEC=114
4373 23:07:49.805965 [RxdqsGatingPostProcess] freq 600
4374 23:07:49.812563 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4375 23:07:49.812645 Pre-setting of DQS Precalculation
4376 23:07:49.819359 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4377 23:07:49.819441 ==
4378 23:07:49.822647 Dram Type= 6, Freq= 0, CH_1, rank 0
4379 23:07:49.825984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 23:07:49.826067 ==
4381 23:07:49.832295 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4382 23:07:49.839246 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4383 23:07:49.842352 [CA 0] Center 35 (5~66) winsize 62
4384 23:07:49.845975 [CA 1] Center 35 (5~66) winsize 62
4385 23:07:49.849073 [CA 2] Center 34 (3~65) winsize 63
4386 23:07:49.852507 [CA 3] Center 33 (3~64) winsize 62
4387 23:07:49.855796 [CA 4] Center 34 (3~65) winsize 63
4388 23:07:49.858986 [CA 5] Center 33 (3~64) winsize 62
4389 23:07:49.859067
4390 23:07:49.862354 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4391 23:07:49.862435
4392 23:07:49.865623 [CATrainingPosCal] consider 1 rank data
4393 23:07:49.868860 u2DelayCellTimex100 = 270/100 ps
4394 23:07:49.872345 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4395 23:07:49.875536 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4396 23:07:49.878773 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4397 23:07:49.882075 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4398 23:07:49.885632 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4399 23:07:49.888924 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4400 23:07:49.889009
4401 23:07:49.895585 CA PerBit enable=1, Macro0, CA PI delay=33
4402 23:07:49.895669
4403 23:07:49.898927 [CBTSetCACLKResult] CA Dly = 33
4404 23:07:49.899011 CS Dly: 4 (0~35)
4405 23:07:49.899079 ==
4406 23:07:49.902211 Dram Type= 6, Freq= 0, CH_1, rank 1
4407 23:07:49.905583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 23:07:49.905668 ==
4409 23:07:49.912099 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4410 23:07:49.918876 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4411 23:07:49.922330 [CA 0] Center 35 (5~66) winsize 62
4412 23:07:49.925198 [CA 1] Center 35 (5~66) winsize 62
4413 23:07:49.928474 [CA 2] Center 34 (4~65) winsize 62
4414 23:07:49.931927 [CA 3] Center 34 (4~65) winsize 62
4415 23:07:49.935220 [CA 4] Center 34 (4~65) winsize 62
4416 23:07:49.938601 [CA 5] Center 33 (3~64) winsize 62
4417 23:07:49.938685
4418 23:07:49.941885 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4419 23:07:49.941978
4420 23:07:49.945469 [CATrainingPosCal] consider 2 rank data
4421 23:07:49.948539 u2DelayCellTimex100 = 270/100 ps
4422 23:07:49.952129 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4423 23:07:49.955289 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4424 23:07:49.958690 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4425 23:07:49.961783 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4426 23:07:49.965255 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4427 23:07:49.971840 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4428 23:07:49.971923
4429 23:07:49.975005 CA PerBit enable=1, Macro0, CA PI delay=33
4430 23:07:49.975089
4431 23:07:49.978556 [CBTSetCACLKResult] CA Dly = 33
4432 23:07:49.978640 CS Dly: 4 (0~36)
4433 23:07:49.978707
4434 23:07:49.981929 ----->DramcWriteLeveling(PI) begin...
4435 23:07:49.982020 ==
4436 23:07:49.985625 Dram Type= 6, Freq= 0, CH_1, rank 0
4437 23:07:49.991734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4438 23:07:49.991819 ==
4439 23:07:49.995136 Write leveling (Byte 0): 31 => 31
4440 23:07:49.995221 Write leveling (Byte 1): 31 => 31
4441 23:07:49.998397 DramcWriteLeveling(PI) end<-----
4442 23:07:49.998480
4443 23:07:49.998547 ==
4444 23:07:50.001738 Dram Type= 6, Freq= 0, CH_1, rank 0
4445 23:07:50.008413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4446 23:07:50.008497 ==
4447 23:07:50.011687 [Gating] SW mode calibration
4448 23:07:50.018150 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4449 23:07:50.021608 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4450 23:07:50.028257 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4451 23:07:50.031502 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4452 23:07:50.034762 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4453 23:07:50.041504 0 9 12 | B1->B0 | 2f2f 2b2b | 0 0 | (1 1) (0 1)
4454 23:07:50.044704 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4455 23:07:50.048309 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4456 23:07:50.051550 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4457 23:07:50.058513 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4458 23:07:50.061625 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4459 23:07:50.064758 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 23:07:50.071679 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
4461 23:07:50.074722 0 10 12 | B1->B0 | 3939 4141 | 0 0 | (1 1) (0 0)
4462 23:07:50.078501 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 23:07:50.084871 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4464 23:07:50.088209 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4465 23:07:50.091524 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4466 23:07:50.098174 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4467 23:07:50.101523 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4468 23:07:50.104890 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 23:07:50.111518 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4470 23:07:50.115013 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 23:07:50.118242 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 23:07:50.124874 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 23:07:50.128161 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 23:07:50.131412 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 23:07:50.138115 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 23:07:50.141486 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 23:07:50.144792 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 23:07:50.151437 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 23:07:50.154894 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 23:07:50.157812 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 23:07:50.161359 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 23:07:50.167885 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 23:07:50.171468 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 23:07:50.174574 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 23:07:50.181458 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4486 23:07:50.185018 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 23:07:50.188045 Total UI for P1: 0, mck2ui 16
4488 23:07:50.191570 best dqsien dly found for B0: ( 0, 13, 12)
4489 23:07:50.194411 Total UI for P1: 0, mck2ui 16
4490 23:07:50.198141 best dqsien dly found for B1: ( 0, 13, 12)
4491 23:07:50.201277 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4492 23:07:50.204659 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4493 23:07:50.204738
4494 23:07:50.208042 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4495 23:07:50.214759 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4496 23:07:50.214869 [Gating] SW calibration Done
4497 23:07:50.214973 ==
4498 23:07:50.218057 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 23:07:50.224729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 23:07:50.224870 ==
4501 23:07:50.225009 RX Vref Scan: 0
4502 23:07:50.225138
4503 23:07:50.227769 RX Vref 0 -> 0, step: 1
4504 23:07:50.227877
4505 23:07:50.231099 RX Delay -230 -> 252, step: 16
4506 23:07:50.234257 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4507 23:07:50.238061 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4508 23:07:50.240985 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4509 23:07:50.247614 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4510 23:07:50.250966 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4511 23:07:50.254113 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4512 23:07:50.257742 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4513 23:07:50.264683 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4514 23:07:50.267974 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4515 23:07:50.270897 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4516 23:07:50.274365 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4517 23:07:50.278064 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4518 23:07:50.284378 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4519 23:07:50.287784 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4520 23:07:50.291137 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4521 23:07:50.294242 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4522 23:07:50.294351 ==
4523 23:07:50.297726 Dram Type= 6, Freq= 0, CH_1, rank 0
4524 23:07:50.304166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4525 23:07:50.304259 ==
4526 23:07:50.304327 DQS Delay:
4527 23:07:50.307483 DQS0 = 0, DQS1 = 0
4528 23:07:50.307554 DQM Delay:
4529 23:07:50.310806 DQM0 = 50, DQM1 = 45
4530 23:07:50.310882 DQ Delay:
4531 23:07:50.314108 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4532 23:07:50.317466 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4533 23:07:50.320672 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4534 23:07:50.323991 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4535 23:07:50.324059
4536 23:07:50.324127
4537 23:07:50.324186 ==
4538 23:07:50.327317 Dram Type= 6, Freq= 0, CH_1, rank 0
4539 23:07:50.330657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4540 23:07:50.330731 ==
4541 23:07:50.330793
4542 23:07:50.330851
4543 23:07:50.333935 TX Vref Scan disable
4544 23:07:50.337597 == TX Byte 0 ==
4545 23:07:50.340933 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4546 23:07:50.344329 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4547 23:07:50.347527 == TX Byte 1 ==
4548 23:07:50.350549 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4549 23:07:50.353844 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4550 23:07:50.353911 ==
4551 23:07:50.357540 Dram Type= 6, Freq= 0, CH_1, rank 0
4552 23:07:50.360715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 23:07:50.363910 ==
4554 23:07:50.363978
4555 23:07:50.364038
4556 23:07:50.364096 TX Vref Scan disable
4557 23:07:50.367716 == TX Byte 0 ==
4558 23:07:50.371042 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4559 23:07:50.378318 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4560 23:07:50.378396 == TX Byte 1 ==
4561 23:07:50.381121 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4562 23:07:50.387875 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4563 23:07:50.387948
4564 23:07:50.388018 [DATLAT]
4565 23:07:50.388078 Freq=600, CH1 RK0
4566 23:07:50.388138
4567 23:07:50.391268 DATLAT Default: 0x9
4568 23:07:50.391340 0, 0xFFFF, sum = 0
4569 23:07:50.394220 1, 0xFFFF, sum = 0
4570 23:07:50.394292 2, 0xFFFF, sum = 0
4571 23:07:50.397793 3, 0xFFFF, sum = 0
4572 23:07:50.397863 4, 0xFFFF, sum = 0
4573 23:07:50.401217 5, 0xFFFF, sum = 0
4574 23:07:50.404204 6, 0xFFFF, sum = 0
4575 23:07:50.404274 7, 0xFFFF, sum = 0
4576 23:07:50.404343 8, 0x0, sum = 1
4577 23:07:50.407927 9, 0x0, sum = 2
4578 23:07:50.408001 10, 0x0, sum = 3
4579 23:07:50.411089 11, 0x0, sum = 4
4580 23:07:50.411163 best_step = 9
4581 23:07:50.411224
4582 23:07:50.411282 ==
4583 23:07:50.414632 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 23:07:50.420987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 23:07:50.421057 ==
4586 23:07:50.421124 RX Vref Scan: 1
4587 23:07:50.421184
4588 23:07:50.424384 RX Vref 0 -> 0, step: 1
4589 23:07:50.424455
4590 23:07:50.427653 RX Delay -179 -> 252, step: 8
4591 23:07:50.427729
4592 23:07:50.431211 Set Vref, RX VrefLevel [Byte0]: 51
4593 23:07:50.434480 [Byte1]: 49
4594 23:07:50.434552
4595 23:07:50.437849 Final RX Vref Byte 0 = 51 to rank0
4596 23:07:50.441069 Final RX Vref Byte 1 = 49 to rank0
4597 23:07:50.444276 Final RX Vref Byte 0 = 51 to rank1
4598 23:07:50.447431 Final RX Vref Byte 1 = 49 to rank1==
4599 23:07:50.451251 Dram Type= 6, Freq= 0, CH_1, rank 0
4600 23:07:50.454714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4601 23:07:50.454783 ==
4602 23:07:50.457570 DQS Delay:
4603 23:07:50.457636 DQS0 = 0, DQS1 = 0
4604 23:07:50.457697 DQM Delay:
4605 23:07:50.461069 DQM0 = 48, DQM1 = 40
4606 23:07:50.461141 DQ Delay:
4607 23:07:50.464108 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4608 23:07:50.467790 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4609 23:07:50.470968 DQ8 =28, DQ9 =28, DQ10 =40, DQ11 =32
4610 23:07:50.474399 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4611 23:07:50.474466
4612 23:07:50.474532
4613 23:07:50.484124 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b72, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4614 23:07:50.484203 CH1 RK0: MR19=808, MR18=4B72
4615 23:07:50.490948 CH1_RK0: MR19=0x808, MR18=0x4B72, DQSOSC=388, MR23=63, INC=174, DEC=116
4616 23:07:50.491025
4617 23:07:50.493931 ----->DramcWriteLeveling(PI) begin...
4618 23:07:50.497542 ==
4619 23:07:50.500830 Dram Type= 6, Freq= 0, CH_1, rank 1
4620 23:07:50.503910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4621 23:07:50.503985 ==
4622 23:07:50.507604 Write leveling (Byte 0): 29 => 29
4623 23:07:50.510555 Write leveling (Byte 1): 28 => 28
4624 23:07:50.514012 DramcWriteLeveling(PI) end<-----
4625 23:07:50.514094
4626 23:07:50.514170 ==
4627 23:07:50.517295 Dram Type= 6, Freq= 0, CH_1, rank 1
4628 23:07:50.520585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4629 23:07:50.520668 ==
4630 23:07:50.524051 [Gating] SW mode calibration
4631 23:07:50.530702 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4632 23:07:50.537109 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4633 23:07:50.540479 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4634 23:07:50.543773 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4635 23:07:50.547447 0 9 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
4636 23:07:50.553734 0 9 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 0)
4637 23:07:50.557415 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4638 23:07:50.560698 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4639 23:07:50.567275 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4640 23:07:50.570499 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4641 23:07:50.573801 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4642 23:07:50.580413 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4643 23:07:50.583744 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4644 23:07:50.587207 0 10 12 | B1->B0 | 4040 2f2f | 0 0 | (0 0) (0 0)
4645 23:07:50.593605 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 23:07:50.597057 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4647 23:07:50.600298 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4648 23:07:50.606839 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4649 23:07:50.610229 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4650 23:07:50.613560 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4651 23:07:50.620202 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4652 23:07:50.623600 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4653 23:07:50.626898 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 23:07:50.634150 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 23:07:50.636987 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 23:07:50.640287 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 23:07:50.646966 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 23:07:50.650238 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 23:07:50.653869 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 23:07:50.660374 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 23:07:50.663624 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 23:07:50.666894 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 23:07:50.673482 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 23:07:50.677172 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 23:07:50.680438 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 23:07:50.683742 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 23:07:50.690241 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 23:07:50.693810 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4669 23:07:50.696678 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 23:07:50.700255 Total UI for P1: 0, mck2ui 16
4671 23:07:50.704203 best dqsien dly found for B0: ( 0, 13, 12)
4672 23:07:50.706545 Total UI for P1: 0, mck2ui 16
4673 23:07:50.709876 best dqsien dly found for B1: ( 0, 13, 12)
4674 23:07:50.713280 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4675 23:07:50.716703 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4676 23:07:50.720221
4677 23:07:50.723299 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4678 23:07:50.726685 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4679 23:07:50.729997 [Gating] SW calibration Done
4680 23:07:50.730072 ==
4681 23:07:50.733344 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 23:07:50.736769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 23:07:50.736863 ==
4684 23:07:50.736931 RX Vref Scan: 0
4685 23:07:50.736994
4686 23:07:50.739925 RX Vref 0 -> 0, step: 1
4687 23:07:50.740008
4688 23:07:50.743549 RX Delay -230 -> 252, step: 16
4689 23:07:50.746945 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4690 23:07:50.750272 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4691 23:07:50.756671 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4692 23:07:50.759976 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4693 23:07:50.763292 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4694 23:07:50.766648 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4695 23:07:50.773146 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4696 23:07:50.776538 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4697 23:07:50.779673 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4698 23:07:50.782884 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4699 23:07:50.786633 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4700 23:07:50.792962 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4701 23:07:50.796504 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4702 23:07:50.799671 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4703 23:07:50.802888 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4704 23:07:50.809780 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4705 23:07:50.809854 ==
4706 23:07:50.812734 Dram Type= 6, Freq= 0, CH_1, rank 1
4707 23:07:50.816160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4708 23:07:50.816228 ==
4709 23:07:50.816290 DQS Delay:
4710 23:07:50.819404 DQS0 = 0, DQS1 = 0
4711 23:07:50.819473 DQM Delay:
4712 23:07:50.822995 DQM0 = 51, DQM1 = 46
4713 23:07:50.823065 DQ Delay:
4714 23:07:50.826145 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4715 23:07:50.829521 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4716 23:07:50.832824 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4717 23:07:50.836137 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4718 23:07:50.836239
4719 23:07:50.836329
4720 23:07:50.836417 ==
4721 23:07:50.839437 Dram Type= 6, Freq= 0, CH_1, rank 1
4722 23:07:50.842711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4723 23:07:50.846001 ==
4724 23:07:50.846070
4725 23:07:50.846131
4726 23:07:50.846190 TX Vref Scan disable
4727 23:07:50.849163 == TX Byte 0 ==
4728 23:07:50.852485 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4729 23:07:50.856259 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4730 23:07:50.859442 == TX Byte 1 ==
4731 23:07:50.862765 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4732 23:07:50.866161 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4733 23:07:50.869350 ==
4734 23:07:50.872724 Dram Type= 6, Freq= 0, CH_1, rank 1
4735 23:07:50.875953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4736 23:07:50.876022 ==
4737 23:07:50.876083
4738 23:07:50.876141
4739 23:07:50.879365 TX Vref Scan disable
4740 23:07:50.879431 == TX Byte 0 ==
4741 23:07:50.885744 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4742 23:07:50.889464 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4743 23:07:50.889537 == TX Byte 1 ==
4744 23:07:50.895736 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4745 23:07:50.899015 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4746 23:07:50.899087
4747 23:07:50.899148 [DATLAT]
4748 23:07:50.902358 Freq=600, CH1 RK1
4749 23:07:50.902433
4750 23:07:50.902503 DATLAT Default: 0x9
4751 23:07:50.905950 0, 0xFFFF, sum = 0
4752 23:07:50.906053 1, 0xFFFF, sum = 0
4753 23:07:50.909143 2, 0xFFFF, sum = 0
4754 23:07:50.909218 3, 0xFFFF, sum = 0
4755 23:07:50.912560 4, 0xFFFF, sum = 0
4756 23:07:50.912630 5, 0xFFFF, sum = 0
4757 23:07:50.915747 6, 0xFFFF, sum = 0
4758 23:07:50.919267 7, 0xFFFF, sum = 0
4759 23:07:50.919338 8, 0x0, sum = 1
4760 23:07:50.919400 9, 0x0, sum = 2
4761 23:07:50.922452 10, 0x0, sum = 3
4762 23:07:50.922520 11, 0x0, sum = 4
4763 23:07:50.925660 best_step = 9
4764 23:07:50.925773
4765 23:07:50.925895 ==
4766 23:07:50.929189 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 23:07:50.932206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 23:07:50.932286 ==
4769 23:07:50.935660 RX Vref Scan: 0
4770 23:07:50.935767
4771 23:07:50.935858 RX Vref 0 -> 0, step: 1
4772 23:07:50.935951
4773 23:07:50.939048 RX Delay -163 -> 252, step: 8
4774 23:07:50.946294 iDelay=205, Bit 0, Center 52 (-83 ~ 188) 272
4775 23:07:50.949527 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4776 23:07:50.952790 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4777 23:07:50.956109 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4778 23:07:50.959358 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4779 23:07:50.966225 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4780 23:07:50.969509 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4781 23:07:50.972798 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4782 23:07:50.976108 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4783 23:07:50.979424 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4784 23:07:50.986400 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4785 23:07:50.989488 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4786 23:07:50.992916 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4787 23:07:50.996301 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4788 23:07:51.002958 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4789 23:07:51.006176 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4790 23:07:51.006251 ==
4791 23:07:51.009559 Dram Type= 6, Freq= 0, CH_1, rank 1
4792 23:07:51.012626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4793 23:07:51.012724 ==
4794 23:07:51.016169 DQS Delay:
4795 23:07:51.016266 DQS0 = 0, DQS1 = 0
4796 23:07:51.016355 DQM Delay:
4797 23:07:51.019396 DQM0 = 48, DQM1 = 42
4798 23:07:51.019491 DQ Delay:
4799 23:07:51.022919 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =48
4800 23:07:51.026483 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4801 23:07:51.029497 DQ8 =32, DQ9 =36, DQ10 =40, DQ11 =36
4802 23:07:51.032725 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =52
4803 23:07:51.032797
4804 23:07:51.032858
4805 23:07:51.042806 [DQSOSCAuto] RK1, (LSB)MR18= 0x571d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4806 23:07:51.042888 CH1 RK1: MR19=808, MR18=571D
4807 23:07:51.049483 CH1_RK1: MR19=0x808, MR18=0x571D, DQSOSC=393, MR23=63, INC=169, DEC=113
4808 23:07:51.052873 [RxdqsGatingPostProcess] freq 600
4809 23:07:51.059971 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4810 23:07:51.063186 Pre-setting of DQS Precalculation
4811 23:07:51.066311 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4812 23:07:51.072828 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4813 23:07:51.079773 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4814 23:07:51.079860
4815 23:07:51.082948
4816 23:07:51.083033 [Calibration Summary] 1200 Mbps
4817 23:07:51.086170 CH 0, Rank 0
4818 23:07:51.086256 SW Impedance : PASS
4819 23:07:51.089841 DUTY Scan : NO K
4820 23:07:51.093065 ZQ Calibration : PASS
4821 23:07:51.093151 Jitter Meter : NO K
4822 23:07:51.096342 CBT Training : PASS
4823 23:07:51.099661 Write leveling : PASS
4824 23:07:51.099747 RX DQS gating : PASS
4825 23:07:51.102895 RX DQ/DQS(RDDQC) : PASS
4826 23:07:51.106315 TX DQ/DQS : PASS
4827 23:07:51.106403 RX DATLAT : PASS
4828 23:07:51.109706 RX DQ/DQS(Engine): PASS
4829 23:07:51.112951 TX OE : NO K
4830 23:07:51.113037 All Pass.
4831 23:07:51.113124
4832 23:07:51.113205 CH 0, Rank 1
4833 23:07:51.116360 SW Impedance : PASS
4834 23:07:51.116446 DUTY Scan : NO K
4835 23:07:51.119643 ZQ Calibration : PASS
4836 23:07:51.122905 Jitter Meter : NO K
4837 23:07:51.122992 CBT Training : PASS
4838 23:07:51.126433 Write leveling : PASS
4839 23:07:51.129445 RX DQS gating : PASS
4840 23:07:51.129530 RX DQ/DQS(RDDQC) : PASS
4841 23:07:51.132945 TX DQ/DQS : PASS
4842 23:07:51.136140 RX DATLAT : PASS
4843 23:07:51.136227 RX DQ/DQS(Engine): PASS
4844 23:07:51.139688 TX OE : NO K
4845 23:07:51.139775 All Pass.
4846 23:07:51.139862
4847 23:07:51.142651 CH 1, Rank 0
4848 23:07:51.142737 SW Impedance : PASS
4849 23:07:51.146534 DUTY Scan : NO K
4850 23:07:51.149484 ZQ Calibration : PASS
4851 23:07:51.149570 Jitter Meter : NO K
4852 23:07:51.152765 CBT Training : PASS
4853 23:07:51.156119 Write leveling : PASS
4854 23:07:51.156205 RX DQS gating : PASS
4855 23:07:51.159860 RX DQ/DQS(RDDQC) : PASS
4856 23:07:51.159946 TX DQ/DQS : PASS
4857 23:07:51.163241 RX DATLAT : PASS
4858 23:07:51.166076 RX DQ/DQS(Engine): PASS
4859 23:07:51.166161 TX OE : NO K
4860 23:07:51.169230 All Pass.
4861 23:07:51.169315
4862 23:07:51.169401 CH 1, Rank 1
4863 23:07:51.172603 SW Impedance : PASS
4864 23:07:51.172685 DUTY Scan : NO K
4865 23:07:51.175889 ZQ Calibration : PASS
4866 23:07:51.179444 Jitter Meter : NO K
4867 23:07:51.179551 CBT Training : PASS
4868 23:07:51.182652 Write leveling : PASS
4869 23:07:51.186052 RX DQS gating : PASS
4870 23:07:51.186138 RX DQ/DQS(RDDQC) : PASS
4871 23:07:51.189354 TX DQ/DQS : PASS
4872 23:07:51.192685 RX DATLAT : PASS
4873 23:07:51.192768 RX DQ/DQS(Engine): PASS
4874 23:07:51.196329 TX OE : NO K
4875 23:07:51.196413 All Pass.
4876 23:07:51.196479
4877 23:07:51.199271 DramC Write-DBI off
4878 23:07:51.202485 PER_BANK_REFRESH: Hybrid Mode
4879 23:07:51.202568 TX_TRACKING: ON
4880 23:07:51.212535 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4881 23:07:51.215695 [FAST_K] Save calibration result to emmc
4882 23:07:51.219049 dramc_set_vcore_voltage set vcore to 662500
4883 23:07:51.222329 Read voltage for 933, 3
4884 23:07:51.222412 Vio18 = 0
4885 23:07:51.222478 Vcore = 662500
4886 23:07:51.225700 Vdram = 0
4887 23:07:51.225783 Vddq = 0
4888 23:07:51.225849 Vmddr = 0
4889 23:07:51.232162 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4890 23:07:51.235434 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4891 23:07:51.239099 MEM_TYPE=3, freq_sel=17
4892 23:07:51.242264 sv_algorithm_assistance_LP4_1600
4893 23:07:51.245451 ============ PULL DRAM RESETB DOWN ============
4894 23:07:51.248772 ========== PULL DRAM RESETB DOWN end =========
4895 23:07:51.255435 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4896 23:07:51.258795 ===================================
4897 23:07:51.262106 LPDDR4 DRAM CONFIGURATION
4898 23:07:51.265347 ===================================
4899 23:07:51.265430 EX_ROW_EN[0] = 0x0
4900 23:07:51.268729 EX_ROW_EN[1] = 0x0
4901 23:07:51.268812 LP4Y_EN = 0x0
4902 23:07:51.272009 WORK_FSP = 0x0
4903 23:07:51.272092 WL = 0x3
4904 23:07:51.275566 RL = 0x3
4905 23:07:51.275648 BL = 0x2
4906 23:07:51.278852 RPST = 0x0
4907 23:07:51.278934 RD_PRE = 0x0
4908 23:07:51.282160 WR_PRE = 0x1
4909 23:07:51.282242 WR_PST = 0x0
4910 23:07:51.285482 DBI_WR = 0x0
4911 23:07:51.285565 DBI_RD = 0x0
4912 23:07:51.288780 OTF = 0x1
4913 23:07:51.291992 ===================================
4914 23:07:51.295304 ===================================
4915 23:07:51.295390 ANA top config
4916 23:07:51.298473 ===================================
4917 23:07:51.301811 DLL_ASYNC_EN = 0
4918 23:07:51.305074 ALL_SLAVE_EN = 1
4919 23:07:51.308454 NEW_RANK_MODE = 1
4920 23:07:51.308541 DLL_IDLE_MODE = 1
4921 23:07:51.311810 LP45_APHY_COMB_EN = 1
4922 23:07:51.315195 TX_ODT_DIS = 1
4923 23:07:51.318489 NEW_8X_MODE = 1
4924 23:07:51.321971 ===================================
4925 23:07:51.324934 ===================================
4926 23:07:51.328239 data_rate = 1866
4927 23:07:51.331867 CKR = 1
4928 23:07:51.331952 DQ_P2S_RATIO = 8
4929 23:07:51.334711 ===================================
4930 23:07:51.338281 CA_P2S_RATIO = 8
4931 23:07:51.341470 DQ_CA_OPEN = 0
4932 23:07:51.344736 DQ_SEMI_OPEN = 0
4933 23:07:51.348511 CA_SEMI_OPEN = 0
4934 23:07:51.351416 CA_FULL_RATE = 0
4935 23:07:51.351504 DQ_CKDIV4_EN = 1
4936 23:07:51.354704 CA_CKDIV4_EN = 1
4937 23:07:51.358330 CA_PREDIV_EN = 0
4938 23:07:51.361302 PH8_DLY = 0
4939 23:07:51.364685 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4940 23:07:51.368152 DQ_AAMCK_DIV = 4
4941 23:07:51.368234 CA_AAMCK_DIV = 4
4942 23:07:51.371390 CA_ADMCK_DIV = 4
4943 23:07:51.374677 DQ_TRACK_CA_EN = 0
4944 23:07:51.378280 CA_PICK = 933
4945 23:07:51.381495 CA_MCKIO = 933
4946 23:07:51.384391 MCKIO_SEMI = 0
4947 23:07:51.388038 PLL_FREQ = 3732
4948 23:07:51.388146 DQ_UI_PI_RATIO = 32
4949 23:07:51.391395 CA_UI_PI_RATIO = 0
4950 23:07:51.394895 ===================================
4951 23:07:51.398037 ===================================
4952 23:07:51.401275 memory_type:LPDDR4
4953 23:07:51.404504 GP_NUM : 10
4954 23:07:51.404612 SRAM_EN : 1
4955 23:07:51.407822 MD32_EN : 0
4956 23:07:51.411201 ===================================
4957 23:07:51.411296 [ANA_INIT] >>>>>>>>>>>>>>
4958 23:07:51.414529 <<<<<< [CONFIGURE PHASE]: ANA_TX
4959 23:07:51.417839 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4960 23:07:51.421067 ===================================
4961 23:07:51.424445 data_rate = 1866,PCW = 0X8f00
4962 23:07:51.427724 ===================================
4963 23:07:51.431091 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4964 23:07:51.437903 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4965 23:07:51.441246 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4966 23:07:51.447749 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4967 23:07:51.451333 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4968 23:07:51.454311 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4969 23:07:51.457810 [ANA_INIT] flow start
4970 23:07:51.457917 [ANA_INIT] PLL >>>>>>>>
4971 23:07:51.461224 [ANA_INIT] PLL <<<<<<<<
4972 23:07:51.464593 [ANA_INIT] MIDPI >>>>>>>>
4973 23:07:51.464700 [ANA_INIT] MIDPI <<<<<<<<
4974 23:07:51.467600 [ANA_INIT] DLL >>>>>>>>
4975 23:07:51.470908 [ANA_INIT] flow end
4976 23:07:51.474175 ============ LP4 DIFF to SE enter ============
4977 23:07:51.477919 ============ LP4 DIFF to SE exit ============
4978 23:07:51.480923 [ANA_INIT] <<<<<<<<<<<<<
4979 23:07:51.484235 [Flow] Enable top DCM control >>>>>
4980 23:07:51.487875 [Flow] Enable top DCM control <<<<<
4981 23:07:51.490757 Enable DLL master slave shuffle
4982 23:07:51.494091 ==============================================================
4983 23:07:51.497865 Gating Mode config
4984 23:07:51.504051 ==============================================================
4985 23:07:51.504134 Config description:
4986 23:07:51.514308 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4987 23:07:51.520907 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4988 23:07:51.523824 SELPH_MODE 0: By rank 1: By Phase
4989 23:07:51.530480 ==============================================================
4990 23:07:51.533895 GAT_TRACK_EN = 1
4991 23:07:51.537262 RX_GATING_MODE = 2
4992 23:07:51.540567 RX_GATING_TRACK_MODE = 2
4993 23:07:51.543876 SELPH_MODE = 1
4994 23:07:51.547402 PICG_EARLY_EN = 1
4995 23:07:51.550830 VALID_LAT_VALUE = 1
4996 23:07:51.554150 ==============================================================
4997 23:07:51.557197 Enter into Gating configuration >>>>
4998 23:07:51.560720 Exit from Gating configuration <<<<
4999 23:07:51.564151 Enter into DVFS_PRE_config >>>>>
5000 23:07:51.573876 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5001 23:07:51.577323 Exit from DVFS_PRE_config <<<<<
5002 23:07:51.580783 Enter into PICG configuration >>>>
5003 23:07:51.583987 Exit from PICG configuration <<<<
5004 23:07:51.587201 [RX_INPUT] configuration >>>>>
5005 23:07:51.590837 [RX_INPUT] configuration <<<<<
5006 23:07:51.597482 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5007 23:07:51.600797 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5008 23:07:51.607366 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5009 23:07:51.613855 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5010 23:07:51.620700 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5011 23:07:51.627285 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5012 23:07:51.630614 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5013 23:07:51.633885 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5014 23:07:51.637231 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5015 23:07:51.643799 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5016 23:07:51.647036 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5017 23:07:51.650724 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5018 23:07:51.653758 ===================================
5019 23:07:51.657048 LPDDR4 DRAM CONFIGURATION
5020 23:07:51.660102 ===================================
5021 23:07:51.660188 EX_ROW_EN[0] = 0x0
5022 23:07:51.663538 EX_ROW_EN[1] = 0x0
5023 23:07:51.667118 LP4Y_EN = 0x0
5024 23:07:51.667204 WORK_FSP = 0x0
5025 23:07:51.670261 WL = 0x3
5026 23:07:51.670348 RL = 0x3
5027 23:07:51.673491 BL = 0x2
5028 23:07:51.673578 RPST = 0x0
5029 23:07:51.676833 RD_PRE = 0x0
5030 23:07:51.676919 WR_PRE = 0x1
5031 23:07:51.680311 WR_PST = 0x0
5032 23:07:51.680396 DBI_WR = 0x0
5033 23:07:51.683483 DBI_RD = 0x0
5034 23:07:51.683569 OTF = 0x1
5035 23:07:51.687140 ===================================
5036 23:07:51.690419 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5037 23:07:51.696885 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5038 23:07:51.700231 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5039 23:07:51.703503 ===================================
5040 23:07:51.706847 LPDDR4 DRAM CONFIGURATION
5041 23:07:51.710109 ===================================
5042 23:07:51.710196 EX_ROW_EN[0] = 0x10
5043 23:07:51.713362 EX_ROW_EN[1] = 0x0
5044 23:07:51.713448 LP4Y_EN = 0x0
5045 23:07:51.716962 WORK_FSP = 0x0
5046 23:07:51.717048 WL = 0x3
5047 23:07:51.720222 RL = 0x3
5048 23:07:51.723488 BL = 0x2
5049 23:07:51.723574 RPST = 0x0
5050 23:07:51.726788 RD_PRE = 0x0
5051 23:07:51.726874 WR_PRE = 0x1
5052 23:07:51.730085 WR_PST = 0x0
5053 23:07:51.730172 DBI_WR = 0x0
5054 23:07:51.733352 DBI_RD = 0x0
5055 23:07:51.733437 OTF = 0x1
5056 23:07:51.737050 ===================================
5057 23:07:51.743653 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5058 23:07:51.747509 nWR fixed to 30
5059 23:07:51.750370 [ModeRegInit_LP4] CH0 RK0
5060 23:07:51.750457 [ModeRegInit_LP4] CH0 RK1
5061 23:07:51.753738 [ModeRegInit_LP4] CH1 RK0
5062 23:07:51.757450 [ModeRegInit_LP4] CH1 RK1
5063 23:07:51.757537 match AC timing 9
5064 23:07:51.763787 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5065 23:07:51.767181 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5066 23:07:51.770659 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5067 23:07:51.777180 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5068 23:07:51.780412 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5069 23:07:51.780498 ==
5070 23:07:51.783838 Dram Type= 6, Freq= 0, CH_0, rank 0
5071 23:07:51.787238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5072 23:07:51.787325 ==
5073 23:07:51.793839 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5074 23:07:51.800798 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5075 23:07:51.803987 [CA 0] Center 38 (7~69) winsize 63
5076 23:07:51.807498 [CA 1] Center 38 (8~69) winsize 62
5077 23:07:51.810697 [CA 2] Center 35 (5~66) winsize 62
5078 23:07:51.814024 [CA 3] Center 34 (4~65) winsize 62
5079 23:07:51.817219 [CA 4] Center 34 (4~64) winsize 61
5080 23:07:51.820323 [CA 5] Center 33 (3~64) winsize 62
5081 23:07:51.820409
5082 23:07:51.824101 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5083 23:07:51.824187
5084 23:07:51.827517 [CATrainingPosCal] consider 1 rank data
5085 23:07:51.830454 u2DelayCellTimex100 = 270/100 ps
5086 23:07:51.833622 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5087 23:07:51.837288 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5088 23:07:51.840636 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5089 23:07:51.844057 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5090 23:07:51.847412 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5091 23:07:51.850707 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5092 23:07:51.850793
5093 23:07:51.857249 CA PerBit enable=1, Macro0, CA PI delay=33
5094 23:07:51.857336
5095 23:07:51.857422 [CBTSetCACLKResult] CA Dly = 33
5096 23:07:51.860556 CS Dly: 6 (0~37)
5097 23:07:51.860642 ==
5098 23:07:51.863939 Dram Type= 6, Freq= 0, CH_0, rank 1
5099 23:07:51.867359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5100 23:07:51.867446 ==
5101 23:07:51.873924 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5102 23:07:51.880570 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5103 23:07:51.883924 [CA 0] Center 38 (8~69) winsize 62
5104 23:07:51.886968 [CA 1] Center 38 (8~69) winsize 62
5105 23:07:51.890449 [CA 2] Center 36 (6~66) winsize 61
5106 23:07:51.893675 [CA 3] Center 35 (5~66) winsize 62
5107 23:07:51.897040 [CA 4] Center 34 (4~65) winsize 62
5108 23:07:51.900618 [CA 5] Center 34 (4~64) winsize 61
5109 23:07:51.900704
5110 23:07:51.903955 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5111 23:07:51.904042
5112 23:07:51.907319 [CATrainingPosCal] consider 2 rank data
5113 23:07:51.910518 u2DelayCellTimex100 = 270/100 ps
5114 23:07:51.913793 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5115 23:07:51.917050 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5116 23:07:51.920368 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5117 23:07:51.923850 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5118 23:07:51.926964 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5119 23:07:51.930328 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5120 23:07:51.930414
5121 23:07:51.937008 CA PerBit enable=1, Macro0, CA PI delay=34
5122 23:07:51.937094
5123 23:07:51.940309 [CBTSetCACLKResult] CA Dly = 34
5124 23:07:51.940395 CS Dly: 7 (0~39)
5125 23:07:51.940481
5126 23:07:51.943635 ----->DramcWriteLeveling(PI) begin...
5127 23:07:51.943748 ==
5128 23:07:51.947045 Dram Type= 6, Freq= 0, CH_0, rank 0
5129 23:07:51.950322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5130 23:07:51.950409 ==
5131 23:07:51.953615 Write leveling (Byte 0): 34 => 34
5132 23:07:51.956878 Write leveling (Byte 1): 28 => 28
5133 23:07:51.960474 DramcWriteLeveling(PI) end<-----
5134 23:07:51.960560
5135 23:07:51.960646 ==
5136 23:07:51.963548 Dram Type= 6, Freq= 0, CH_0, rank 0
5137 23:07:51.970592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5138 23:07:51.970679 ==
5139 23:07:51.970765 [Gating] SW mode calibration
5140 23:07:51.980371 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5141 23:07:51.983475 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5142 23:07:51.986920 0 14 0 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
5143 23:07:51.993452 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5144 23:07:51.996956 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5145 23:07:51.999982 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5146 23:07:52.006734 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5147 23:07:52.010107 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5148 23:07:52.013526 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5149 23:07:52.020274 0 14 28 | B1->B0 | 3232 2424 | 0 0 | (1 0) (0 0)
5150 23:07:52.023432 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5151 23:07:52.026753 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5152 23:07:52.033299 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5153 23:07:52.036714 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5154 23:07:52.039901 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5155 23:07:52.046636 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5156 23:07:52.049883 0 15 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5157 23:07:52.053540 0 15 28 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
5158 23:07:52.059892 1 0 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5159 23:07:52.063227 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 23:07:52.066576 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5161 23:07:52.073288 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 23:07:52.076502 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5163 23:07:52.079716 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5164 23:07:52.086730 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5165 23:07:52.089783 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5166 23:07:52.093206 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5167 23:07:52.096506 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 23:07:52.103196 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 23:07:52.106337 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 23:07:52.109647 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 23:07:52.116372 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 23:07:52.119909 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5173 23:07:52.123212 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 23:07:52.129961 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 23:07:52.132948 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 23:07:52.136685 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 23:07:52.143161 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 23:07:52.146437 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 23:07:52.149870 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 23:07:52.156560 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5181 23:07:52.159909 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5182 23:07:52.163125 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 23:07:52.166493 Total UI for P1: 0, mck2ui 16
5184 23:07:52.170074 best dqsien dly found for B0: ( 1, 2, 26)
5185 23:07:52.173206 Total UI for P1: 0, mck2ui 16
5186 23:07:52.176536 best dqsien dly found for B1: ( 1, 2, 28)
5187 23:07:52.179938 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5188 23:07:52.183173 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5189 23:07:52.183259
5190 23:07:52.186340 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5191 23:07:52.193090 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5192 23:07:52.193177 [Gating] SW calibration Done
5193 23:07:52.193263 ==
5194 23:07:52.196604 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 23:07:52.202884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 23:07:52.202971 ==
5197 23:07:52.203056 RX Vref Scan: 0
5198 23:07:52.203138
5199 23:07:52.206552 RX Vref 0 -> 0, step: 1
5200 23:07:52.206638
5201 23:07:52.209760 RX Delay -80 -> 252, step: 8
5202 23:07:52.212900 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5203 23:07:52.216443 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5204 23:07:52.220013 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5205 23:07:52.226216 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5206 23:07:52.229450 iDelay=208, Bit 4, Center 111 (24 ~ 199) 176
5207 23:07:52.233146 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5208 23:07:52.236248 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5209 23:07:52.239480 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5210 23:07:52.242835 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5211 23:07:52.249524 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5212 23:07:52.252789 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5213 23:07:52.256129 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5214 23:07:52.259486 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5215 23:07:52.262914 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5216 23:07:52.266213 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5217 23:07:52.272851 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5218 23:07:52.272938 ==
5219 23:07:52.276166 Dram Type= 6, Freq= 0, CH_0, rank 0
5220 23:07:52.279472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5221 23:07:52.279559 ==
5222 23:07:52.279645 DQS Delay:
5223 23:07:52.282740 DQS0 = 0, DQS1 = 0
5224 23:07:52.282825 DQM Delay:
5225 23:07:52.286267 DQM0 = 106, DQM1 = 90
5226 23:07:52.286353 DQ Delay:
5227 23:07:52.289496 DQ0 =107, DQ1 =111, DQ2 =99, DQ3 =99
5228 23:07:52.292990 DQ4 =111, DQ5 =95, DQ6 =115, DQ7 =115
5229 23:07:52.296265 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5230 23:07:52.299546 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5231 23:07:52.299633
5232 23:07:52.299718
5233 23:07:52.299799 ==
5234 23:07:52.303258 Dram Type= 6, Freq= 0, CH_0, rank 0
5235 23:07:52.306235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5236 23:07:52.309461 ==
5237 23:07:52.309547
5238 23:07:52.309633
5239 23:07:52.309733 TX Vref Scan disable
5240 23:07:52.312980 == TX Byte 0 ==
5241 23:07:52.316084 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5242 23:07:52.319664 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5243 23:07:52.322730 == TX Byte 1 ==
5244 23:07:52.326209 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5245 23:07:52.329489 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5246 23:07:52.332585 ==
5247 23:07:52.332671 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 23:07:52.339496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 23:07:52.339604 ==
5250 23:07:52.339694
5251 23:07:52.339777
5252 23:07:52.342618 TX Vref Scan disable
5253 23:07:52.342705 == TX Byte 0 ==
5254 23:07:52.349236 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5255 23:07:52.352567 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5256 23:07:52.352654 == TX Byte 1 ==
5257 23:07:52.359224 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5258 23:07:52.362403 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5259 23:07:52.362490
5260 23:07:52.362576 [DATLAT]
5261 23:07:52.365889 Freq=933, CH0 RK0
5262 23:07:52.366027
5263 23:07:52.366114 DATLAT Default: 0xd
5264 23:07:52.369107 0, 0xFFFF, sum = 0
5265 23:07:52.369195 1, 0xFFFF, sum = 0
5266 23:07:52.372461 2, 0xFFFF, sum = 0
5267 23:07:52.372547 3, 0xFFFF, sum = 0
5268 23:07:52.375820 4, 0xFFFF, sum = 0
5269 23:07:52.375908 5, 0xFFFF, sum = 0
5270 23:07:52.379088 6, 0xFFFF, sum = 0
5271 23:07:52.382479 7, 0xFFFF, sum = 0
5272 23:07:52.382566 8, 0xFFFF, sum = 0
5273 23:07:52.385761 9, 0xFFFF, sum = 0
5274 23:07:52.385848 10, 0x0, sum = 1
5275 23:07:52.385961 11, 0x0, sum = 2
5276 23:07:52.389068 12, 0x0, sum = 3
5277 23:07:52.389155 13, 0x0, sum = 4
5278 23:07:52.392322 best_step = 11
5279 23:07:52.392444
5280 23:07:52.392543 ==
5281 23:07:52.395556 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 23:07:52.398916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 23:07:52.399001 ==
5284 23:07:52.402230 RX Vref Scan: 1
5285 23:07:52.402313
5286 23:07:52.402380 RX Vref 0 -> 0, step: 1
5287 23:07:52.405485
5288 23:07:52.405568 RX Delay -53 -> 252, step: 4
5289 23:07:52.405635
5290 23:07:52.408631 Set Vref, RX VrefLevel [Byte0]: 58
5291 23:07:52.412254 [Byte1]: 51
5292 23:07:52.416212
5293 23:07:52.416296 Final RX Vref Byte 0 = 58 to rank0
5294 23:07:52.419476 Final RX Vref Byte 1 = 51 to rank0
5295 23:07:52.422919 Final RX Vref Byte 0 = 58 to rank1
5296 23:07:52.426324 Final RX Vref Byte 1 = 51 to rank1==
5297 23:07:52.429548 Dram Type= 6, Freq= 0, CH_0, rank 0
5298 23:07:52.436335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5299 23:07:52.436420 ==
5300 23:07:52.436487 DQS Delay:
5301 23:07:52.436550 DQS0 = 0, DQS1 = 0
5302 23:07:52.439440 DQM Delay:
5303 23:07:52.439524 DQM0 = 108, DQM1 = 92
5304 23:07:52.443277 DQ Delay:
5305 23:07:52.446026 DQ0 =106, DQ1 =108, DQ2 =102, DQ3 =106
5306 23:07:52.449814 DQ4 =110, DQ5 =100, DQ6 =118, DQ7 =116
5307 23:07:52.453123 DQ8 =86, DQ9 =82, DQ10 =92, DQ11 =90
5308 23:07:52.456366 DQ12 =98, DQ13 =92, DQ14 =102, DQ15 =100
5309 23:07:52.456449
5310 23:07:52.456516
5311 23:07:52.462752 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
5312 23:07:52.466109 CH0 RK0: MR19=505, MR18=2521
5313 23:07:52.472848 CH0_RK0: MR19=0x505, MR18=0x2521, DQSOSC=410, MR23=63, INC=64, DEC=42
5314 23:07:52.472932
5315 23:07:52.476128 ----->DramcWriteLeveling(PI) begin...
5316 23:07:52.476213 ==
5317 23:07:52.479408 Dram Type= 6, Freq= 0, CH_0, rank 1
5318 23:07:52.482758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5319 23:07:52.482842 ==
5320 23:07:52.485923 Write leveling (Byte 0): 31 => 31
5321 23:07:52.489370 Write leveling (Byte 1): 31 => 31
5322 23:07:52.492609 DramcWriteLeveling(PI) end<-----
5323 23:07:52.492708
5324 23:07:52.492775 ==
5325 23:07:52.496151 Dram Type= 6, Freq= 0, CH_0, rank 1
5326 23:07:52.502725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 23:07:52.502810 ==
5328 23:07:52.502891 [Gating] SW mode calibration
5329 23:07:52.512824 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5330 23:07:52.516110 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5331 23:07:52.519105 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 23:07:52.525890 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 23:07:52.529020 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 23:07:52.532471 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 23:07:52.539020 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5336 23:07:52.542314 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5337 23:07:52.545783 0 14 24 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
5338 23:07:52.552257 0 14 28 | B1->B0 | 2828 2525 | 1 0 | (0 1) (1 0)
5339 23:07:52.555515 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 23:07:52.558966 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 23:07:52.565780 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 23:07:52.569155 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 23:07:52.572484 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5344 23:07:52.579201 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5345 23:07:52.582450 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5346 23:07:52.585703 0 15 28 | B1->B0 | 4141 4343 | 0 0 | (0 0) (0 0)
5347 23:07:52.592334 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 23:07:52.595647 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 23:07:52.598860 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 23:07:52.605451 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 23:07:52.608802 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5352 23:07:52.612171 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5353 23:07:54.027488 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5354 23:07:54.027999 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5355 23:07:54.028216 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 23:07:54.028351 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 23:07:54.028484 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 23:07:54.028601 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 23:07:54.028668 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 23:07:54.028749 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 23:07:54.028841 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 23:07:54.028933 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 23:07:54.029018 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 23:07:54.029107 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 23:07:54.029258 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 23:07:54.029441 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 23:07:54.029565 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 23:07:54.029653 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 23:07:54.029757 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 23:07:54.029845 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5371 23:07:54.029952 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 23:07:54.030029 Total UI for P1: 0, mck2ui 16
5373 23:07:54.030086 best dqsien dly found for B0: ( 1, 2, 28)
5374 23:07:54.030173 Total UI for P1: 0, mck2ui 16
5375 23:07:54.030242 best dqsien dly found for B1: ( 1, 2, 28)
5376 23:07:54.030298 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5377 23:07:54.030357 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5378 23:07:54.030412
5379 23:07:54.030468 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5380 23:07:54.030551 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5381 23:07:54.030610 [Gating] SW calibration Done
5382 23:07:54.030665 ==
5383 23:07:54.030772 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 23:07:54.030830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 23:07:54.030887 ==
5386 23:07:54.030957 RX Vref Scan: 0
5387 23:07:54.031015
5388 23:07:54.031071 RX Vref 0 -> 0, step: 1
5389 23:07:54.031160
5390 23:07:54.031245 RX Delay -80 -> 252, step: 8
5391 23:07:54.031324 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5392 23:07:54.031409 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5393 23:07:54.031503 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5394 23:07:54.031592 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5395 23:07:54.031678 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5396 23:07:54.031763 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5397 23:07:54.031881 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5398 23:07:54.031974 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5399 23:07:54.032066 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5400 23:07:54.032159 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5401 23:07:54.032252 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5402 23:07:54.032341 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5403 23:07:54.032446 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5404 23:07:54.032537 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5405 23:07:54.032640 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5406 23:07:54.032732 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5407 23:07:54.032824 ==
5408 23:07:54.032916 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 23:07:54.033019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 23:07:54.033111 ==
5411 23:07:54.033204 DQS Delay:
5412 23:07:54.033295 DQS0 = 0, DQS1 = 0
5413 23:07:54.033398 DQM Delay:
5414 23:07:54.033489 DQM0 = 104, DQM1 = 90
5415 23:07:54.033589 DQ Delay:
5416 23:07:54.033682 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5417 23:07:54.033775 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5418 23:07:54.033865 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5419 23:07:54.033969 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5420 23:07:54.034031
5421 23:07:54.034089
5422 23:07:54.034155 ==
5423 23:07:54.034248 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 23:07:54.034339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 23:07:54.034441 ==
5426 23:07:54.034535
5427 23:07:54.034624
5428 23:07:54.034714 TX Vref Scan disable
5429 23:07:54.034815 == TX Byte 0 ==
5430 23:07:54.034915 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5431 23:07:54.035002 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5432 23:07:54.035085 == TX Byte 1 ==
5433 23:07:54.035181 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5434 23:07:54.035267 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5435 23:07:54.035353 ==
5436 23:07:54.035437 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 23:07:54.035534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 23:07:54.035619 ==
5439 23:07:54.035706
5440 23:07:54.035790
5441 23:07:54.035879 TX Vref Scan disable
5442 23:07:54.035968 == TX Byte 0 ==
5443 23:07:54.036054 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5444 23:07:54.036175 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5445 23:07:54.036271 == TX Byte 1 ==
5446 23:07:54.036356 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5447 23:07:54.036444 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5448 23:07:54.036527
5449 23:07:54.036610 [DATLAT]
5450 23:07:54.036704 Freq=933, CH0 RK1
5451 23:07:54.036788
5452 23:07:54.036874 DATLAT Default: 0xb
5453 23:07:54.036959 0, 0xFFFF, sum = 0
5454 23:07:54.037055 1, 0xFFFF, sum = 0
5455 23:07:54.037141 2, 0xFFFF, sum = 0
5456 23:07:54.037239 3, 0xFFFF, sum = 0
5457 23:07:54.037325 4, 0xFFFF, sum = 0
5458 23:07:54.037413 5, 0xFFFF, sum = 0
5459 23:07:54.037499 6, 0xFFFF, sum = 0
5460 23:07:54.037592 7, 0xFFFF, sum = 0
5461 23:07:54.037686 8, 0xFFFF, sum = 0
5462 23:07:54.037773 9, 0xFFFF, sum = 0
5463 23:07:54.037857 10, 0x0, sum = 1
5464 23:07:54.037962 11, 0x0, sum = 2
5465 23:07:54.038090 12, 0x0, sum = 3
5466 23:07:54.038234 13, 0x0, sum = 4
5467 23:07:54.038329 best_step = 11
5468 23:07:54.038398
5469 23:07:54.038485 ==
5470 23:07:54.038573 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 23:07:54.038662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 23:07:54.038748 ==
5473 23:07:54.038850 RX Vref Scan: 0
5474 23:07:54.038940
5475 23:07:54.039048 RX Vref 0 -> 0, step: 1
5476 23:07:54.039140
5477 23:07:54.039232 RX Delay -53 -> 252, step: 4
5478 23:07:54.039322 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5479 23:07:54.039408 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5480 23:07:54.039508 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5481 23:07:54.039595 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5482 23:07:54.039683 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5483 23:07:54.039770 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5484 23:07:54.039878 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5485 23:07:54.039962 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5486 23:07:54.040056 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5487 23:07:54.040353 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5488 23:07:54.040449 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5489 23:07:54.040537 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5490 23:07:54.040635 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5491 23:07:54.040720 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5492 23:07:54.040808 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5493 23:07:54.040894 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5494 23:07:54.040985 ==
5495 23:07:54.041046 Dram Type= 6, Freq= 0, CH_0, rank 1
5496 23:07:54.041132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 23:07:54.041218 ==
5498 23:07:54.041302 DQS Delay:
5499 23:07:54.041400 DQS0 = 0, DQS1 = 0
5500 23:07:54.041484 DQM Delay:
5501 23:07:54.041570 DQM0 = 104, DQM1 = 92
5502 23:07:54.041655 DQ Delay:
5503 23:07:54.041746 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98
5504 23:07:54.041833 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =110
5505 23:07:54.041921 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5506 23:07:54.042023 DQ12 =98, DQ13 =94, DQ14 =100, DQ15 =98
5507 23:07:54.042079
5508 23:07:54.042134
5509 23:07:54.042231 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5510 23:07:54.042317 CH0 RK1: MR19=505, MR18=2A0B
5511 23:07:54.042405 CH0_RK1: MR19=0x505, MR18=0x2A0B, DQSOSC=408, MR23=63, INC=65, DEC=43
5512 23:07:54.042496 [RxdqsGatingPostProcess] freq 933
5513 23:07:54.042592 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5514 23:07:54.042678 best DQS0 dly(2T, 0.5T) = (0, 10)
5515 23:07:54.042764 best DQS1 dly(2T, 0.5T) = (0, 10)
5516 23:07:54.042848 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5517 23:07:54.042942 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5518 23:07:54.043069 best DQS0 dly(2T, 0.5T) = (0, 10)
5519 23:07:54.043160 best DQS1 dly(2T, 0.5T) = (0, 10)
5520 23:07:54.043244 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5521 23:07:54.043332 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5522 23:07:54.043415 Pre-setting of DQS Precalculation
5523 23:07:54.043510 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5524 23:07:54.043594 ==
5525 23:07:54.043683 Dram Type= 6, Freq= 0, CH_1, rank 0
5526 23:07:54.043767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5527 23:07:54.043860 ==
5528 23:07:54.043947 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5529 23:07:54.044034 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5530 23:07:54.044119 [CA 0] Center 37 (7~68) winsize 62
5531 23:07:54.044205 [CA 1] Center 37 (7~68) winsize 62
5532 23:07:54.044300 [CA 2] Center 35 (5~66) winsize 62
5533 23:07:54.044384 [CA 3] Center 34 (4~65) winsize 62
5534 23:07:54.044479 [CA 4] Center 35 (5~66) winsize 62
5535 23:07:54.044563 [CA 5] Center 34 (4~64) winsize 61
5536 23:07:54.044648
5537 23:07:54.044735 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5538 23:07:54.044827
5539 23:07:54.044912 [CATrainingPosCal] consider 1 rank data
5540 23:07:54.044998 u2DelayCellTimex100 = 270/100 ps
5541 23:07:54.045056 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5542 23:07:54.045110 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5543 23:07:54.045169 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5544 23:07:54.045265 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5545 23:07:54.045349 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5546 23:07:54.045437 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5547 23:07:54.045520
5548 23:07:54.045606 CA PerBit enable=1, Macro0, CA PI delay=34
5549 23:07:54.045689
5550 23:07:54.045783 [CBTSetCACLKResult] CA Dly = 34
5551 23:07:54.045869 CS Dly: 6 (0~37)
5552 23:07:54.045976 ==
5553 23:07:54.046059 Dram Type= 6, Freq= 0, CH_1, rank 1
5554 23:07:54.046114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 23:07:54.046198 ==
5556 23:07:54.046285 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5557 23:07:54.046381 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5558 23:07:54.046468 [CA 0] Center 38 (8~68) winsize 61
5559 23:07:54.046556 [CA 1] Center 38 (8~69) winsize 62
5560 23:07:54.046640 [CA 2] Center 36 (6~66) winsize 61
5561 23:07:54.046732 [CA 3] Center 35 (6~65) winsize 60
5562 23:07:54.046820 [CA 4] Center 35 (5~65) winsize 61
5563 23:07:54.046904 [CA 5] Center 35 (5~65) winsize 61
5564 23:07:54.046995
5565 23:07:54.047083 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5566 23:07:54.047178
5567 23:07:54.047263 [CATrainingPosCal] consider 2 rank data
5568 23:07:54.047352 u2DelayCellTimex100 = 270/100 ps
5569 23:07:54.047436 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5570 23:07:54.047532 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5571 23:07:54.047617 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5572 23:07:54.047709 CA3 delay=35 (6~65),Diff = 1 PI (6 cell)
5573 23:07:54.047796 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5574 23:07:54.047883 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
5575 23:07:54.047966
5576 23:07:54.048050 CA PerBit enable=1, Macro0, CA PI delay=34
5577 23:07:54.048144
5578 23:07:54.048227 [CBTSetCACLKResult] CA Dly = 34
5579 23:07:54.048313 CS Dly: 7 (0~39)
5580 23:07:54.048398
5581 23:07:54.048493 ----->DramcWriteLeveling(PI) begin...
5582 23:07:54.048578 ==
5583 23:07:54.048674 Dram Type= 6, Freq= 0, CH_1, rank 0
5584 23:07:54.048760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5585 23:07:54.048850 ==
5586 23:07:54.048940 Write leveling (Byte 0): 26 => 26
5587 23:07:54.049024 Write leveling (Byte 1): 26 => 26
5588 23:07:54.049090 DramcWriteLeveling(PI) end<-----
5589 23:07:54.049182
5590 23:07:54.049265 ==
5591 23:07:54.049352 Dram Type= 6, Freq= 0, CH_1, rank 0
5592 23:07:54.049438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 23:07:54.049533 ==
5594 23:07:54.049617 [Gating] SW mode calibration
5595 23:07:54.049706 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5596 23:07:54.049791 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5597 23:07:54.049882 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5598 23:07:54.050019 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5599 23:07:54.050078 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5600 23:07:54.050134 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5601 23:07:54.050223 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5602 23:07:54.050309 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5603 23:07:54.050408 0 14 24 | B1->B0 | 3030 2f2f | 0 0 | (0 1) (1 1)
5604 23:07:54.050496 0 14 28 | B1->B0 | 2929 2828 | 0 0 | (0 0) (0 0)
5605 23:07:54.050778 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 23:07:54.050872 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5607 23:07:54.050960 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5608 23:07:54.051059 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5609 23:07:54.051146 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5610 23:07:54.051236 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5611 23:07:54.051321 0 15 24 | B1->B0 | 2626 2d2d | 0 0 | (0 0) (0 0)
5612 23:07:54.051407 0 15 28 | B1->B0 | 3d3d 4343 | 0 0 | (0 0) (0 0)
5613 23:07:54.051495 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 23:07:54.051584 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 23:07:54.051678 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5616 23:07:54.051764 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5617 23:07:54.051862 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5618 23:07:54.051949 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5619 23:07:54.052036 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5620 23:07:54.052122 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5621 23:07:54.052207 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 23:07:54.052293 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 23:07:54.052377 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 23:07:54.052474 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 23:07:54.052560 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 23:07:54.052657 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 23:07:54.052741 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 23:07:54.052829 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 23:07:54.052917 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 23:07:54.053008 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 23:07:54.053098 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 23:07:54.053185 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 23:07:54.053269 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 23:07:54.053354 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 23:07:54.053450 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5636 23:07:54.053534 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5637 23:07:54.053629 Total UI for P1: 0, mck2ui 16
5638 23:07:54.053715 best dqsien dly found for B0: ( 1, 2, 24)
5639 23:07:54.053802 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 23:07:54.053888 Total UI for P1: 0, mck2ui 16
5641 23:07:54.053991 best dqsien dly found for B1: ( 1, 2, 28)
5642 23:07:54.054077 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5643 23:07:54.054164 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5644 23:07:54.054249
5645 23:07:54.054332 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5646 23:07:54.054429 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5647 23:07:54.054513 [Gating] SW calibration Done
5648 23:07:54.054599 ==
5649 23:07:54.054683 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 23:07:54.054771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 23:07:54.054855 ==
5652 23:07:54.054944 RX Vref Scan: 0
5653 23:07:54.055033
5654 23:07:54.055117 RX Vref 0 -> 0, step: 1
5655 23:07:54.055211
5656 23:07:54.055298 RX Delay -80 -> 252, step: 8
5657 23:07:54.055384 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5658 23:07:54.055467 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5659 23:07:54.055563 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5660 23:07:54.055648 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5661 23:07:54.055735 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5662 23:07:54.055820 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5663 23:07:54.055915 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5664 23:07:54.055999 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5665 23:07:54.056087 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5666 23:07:54.056171 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5667 23:07:54.056261 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5668 23:07:54.056350 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5669 23:07:54.056435 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5670 23:07:54.056521 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5671 23:07:54.056606 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5672 23:07:54.056701 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5673 23:07:54.056784 ==
5674 23:07:54.056876 Dram Type= 6, Freq= 0, CH_1, rank 0
5675 23:07:54.056962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5676 23:07:54.057055 ==
5677 23:07:54.057142 DQS Delay:
5678 23:07:54.057227 DQS0 = 0, DQS1 = 0
5679 23:07:54.057314 DQM Delay:
5680 23:07:54.057402 DQM0 = 101, DQM1 = 95
5681 23:07:54.057500 DQ Delay:
5682 23:07:54.057585 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5683 23:07:54.057680 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5684 23:07:54.057765 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5685 23:07:54.057851 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5686 23:07:54.057937
5687 23:07:54.058028
5688 23:07:54.058122 ==
5689 23:07:54.058209 Dram Type= 6, Freq= 0, CH_1, rank 0
5690 23:07:54.058296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5691 23:07:54.058379 ==
5692 23:07:54.058476
5693 23:07:54.058560
5694 23:07:54.058647 TX Vref Scan disable
5695 23:07:54.058732 == TX Byte 0 ==
5696 23:07:54.058822 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5697 23:07:54.058911 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5698 23:07:54.058996 == TX Byte 1 ==
5699 23:07:54.059083 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5700 23:07:54.059170 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5701 23:07:54.059263 ==
5702 23:07:54.059347 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 23:07:54.059446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 23:07:54.059533 ==
5705 23:07:54.059631
5706 23:07:54.059743
5707 23:07:54.059829 TX Vref Scan disable
5708 23:07:54.059912 == TX Byte 0 ==
5709 23:07:54.060007 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5710 23:07:54.060095 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5711 23:07:54.060181 == TX Byte 1 ==
5712 23:07:54.060274 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5713 23:07:54.060359 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5714 23:07:54.060448
5715 23:07:54.060532 [DATLAT]
5716 23:07:54.060619 Freq=933, CH1 RK0
5717 23:07:54.060711
5718 23:07:54.060798 DATLAT Default: 0xd
5719 23:07:54.060882 0, 0xFFFF, sum = 0
5720 23:07:54.060967 1, 0xFFFF, sum = 0
5721 23:07:54.061066 2, 0xFFFF, sum = 0
5722 23:07:54.061154 3, 0xFFFF, sum = 0
5723 23:07:54.061242 4, 0xFFFF, sum = 0
5724 23:07:54.061533 5, 0xFFFF, sum = 0
5725 23:07:54.061630 6, 0xFFFF, sum = 0
5726 23:07:54.061721 7, 0xFFFF, sum = 0
5727 23:07:54.061807 8, 0xFFFF, sum = 0
5728 23:07:54.061895 9, 0xFFFF, sum = 0
5729 23:07:54.061979 10, 0x0, sum = 1
5730 23:07:54.062037 11, 0x0, sum = 2
5731 23:07:54.062092 12, 0x0, sum = 3
5732 23:07:54.062150 13, 0x0, sum = 4
5733 23:07:54.062236 best_step = 11
5734 23:07:54.062319
5735 23:07:54.062401 ==
5736 23:07:54.062486 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 23:07:54.062570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 23:07:54.062653 ==
5739 23:07:54.062738 RX Vref Scan: 1
5740 23:07:54.062822
5741 23:07:54.062933 RX Vref 0 -> 0, step: 1
5742 23:07:54.063016
5743 23:07:54.063099 RX Delay -53 -> 252, step: 4
5744 23:07:54.063182
5745 23:07:54.063266 Set Vref, RX VrefLevel [Byte0]: 51
5746 23:07:54.063351 [Byte1]: 49
5747 23:07:54.063433
5748 23:07:54.063517 Final RX Vref Byte 0 = 51 to rank0
5749 23:07:54.063601 Final RX Vref Byte 1 = 49 to rank0
5750 23:07:54.063685 Final RX Vref Byte 0 = 51 to rank1
5751 23:07:54.063768 Final RX Vref Byte 1 = 49 to rank1==
5752 23:07:54.063854 Dram Type= 6, Freq= 0, CH_1, rank 0
5753 23:07:54.063938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5754 23:07:54.064021 ==
5755 23:07:54.064105 DQS Delay:
5756 23:07:54.064188 DQS0 = 0, DQS1 = 0
5757 23:07:54.064271 DQM Delay:
5758 23:07:54.064354 DQM0 = 104, DQM1 = 96
5759 23:07:54.064438 DQ Delay:
5760 23:07:54.064521 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =104
5761 23:07:54.064606 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =100
5762 23:07:54.064689 DQ8 =86, DQ9 =84, DQ10 =100, DQ11 =90
5763 23:07:54.064772 DQ12 =106, DQ13 =100, DQ14 =102, DQ15 =102
5764 23:07:54.064855
5765 23:07:54.064938
5766 23:07:54.065022 [DQSOSCAuto] RK0, (LSB)MR18= 0x1830, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5767 23:07:54.065106 CH1 RK0: MR19=505, MR18=1830
5768 23:07:54.065191 CH1_RK0: MR19=0x505, MR18=0x1830, DQSOSC=406, MR23=63, INC=65, DEC=43
5769 23:07:54.065274
5770 23:07:54.065358 ----->DramcWriteLeveling(PI) begin...
5771 23:07:54.065443 ==
5772 23:07:54.065527 Dram Type= 6, Freq= 0, CH_1, rank 1
5773 23:07:54.065611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5774 23:07:54.065694 ==
5775 23:07:54.065777 Write leveling (Byte 0): 28 => 28
5776 23:07:54.065860 Write leveling (Byte 1): 27 => 27
5777 23:07:54.065948 DramcWriteLeveling(PI) end<-----
5778 23:07:54.066006
5779 23:07:54.066060 ==
5780 23:07:54.066114 Dram Type= 6, Freq= 0, CH_1, rank 1
5781 23:07:54.066172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 23:07:54.066226 ==
5783 23:07:54.066279 [Gating] SW mode calibration
5784 23:07:54.066332 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5785 23:07:54.066386 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5786 23:07:54.066444 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5787 23:07:54.066498 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5788 23:07:54.066551 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5789 23:07:54.066604 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5790 23:07:54.066659 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5791 23:07:54.066713 0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5792 23:07:54.066765 0 14 24 | B1->B0 | 3030 3434 | 0 1 | (0 1) (1 0)
5793 23:07:54.066818 0 14 28 | B1->B0 | 2525 2929 | 0 0 | (1 0) (0 0)
5794 23:07:54.066870 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5795 23:07:54.066954 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5796 23:07:54.067038 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5797 23:07:54.067121 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5798 23:07:54.067206 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5799 23:07:54.067290 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5800 23:07:54.067373 0 15 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5801 23:07:54.067458 0 15 28 | B1->B0 | 4242 3434 | 0 0 | (0 0) (0 0)
5802 23:07:54.067544 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 23:07:54.067627 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 23:07:54.067712 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5805 23:07:54.067796 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5806 23:07:54.067879 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5807 23:07:54.067962 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5808 23:07:54.068048 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5809 23:07:54.068132 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5810 23:07:54.068215 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 23:07:54.068300 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 23:07:54.068383 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 23:07:54.068466 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 23:07:54.068551 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 23:07:54.068635 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 23:07:54.068718 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 23:07:54.068803 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 23:07:54.068887 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 23:07:54.068970 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 23:07:54.069047 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 23:07:54.069104 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 23:07:54.069159 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 23:07:54.069213 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 23:07:54.069271 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5825 23:07:54.069355 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 23:07:54.069437 Total UI for P1: 0, mck2ui 16
5827 23:07:54.069522 best dqsien dly found for B0: ( 1, 2, 26)
5828 23:07:54.069607 Total UI for P1: 0, mck2ui 16
5829 23:07:54.069690 best dqsien dly found for B1: ( 1, 2, 24)
5830 23:07:54.069773 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5831 23:07:54.069858 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5832 23:07:54.069944
5833 23:07:54.070042 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5834 23:07:54.070101 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5835 23:07:54.070157 [Gating] SW calibration Done
5836 23:07:54.070211 ==
5837 23:07:54.070265 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 23:07:54.070506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 23:07:54.070570 ==
5840 23:07:54.070641 RX Vref Scan: 0
5841 23:07:54.070726
5842 23:07:54.070809 RX Vref 0 -> 0, step: 1
5843 23:07:54.070893
5844 23:07:54.070976 RX Delay -80 -> 252, step: 8
5845 23:07:54.071059 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5846 23:07:54.071143 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5847 23:07:54.071229 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5848 23:07:54.071312 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5849 23:07:54.071396 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5850 23:07:54.071480 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5851 23:07:54.072744 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5852 23:07:54.079499 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5853 23:07:54.082834 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5854 23:07:54.086115 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5855 23:07:54.089560 iDelay=200, Bit 10, Center 95 (8 ~ 183) 176
5856 23:07:54.092865 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5857 23:07:54.096235 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5858 23:07:54.102720 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5859 23:07:54.106154 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5860 23:07:54.109206 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5861 23:07:54.109313 ==
5862 23:07:54.112637 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 23:07:54.116167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 23:07:54.116283 ==
5865 23:07:54.119358 DQS Delay:
5866 23:07:54.119488 DQS0 = 0, DQS1 = 0
5867 23:07:54.119600 DQM Delay:
5868 23:07:54.122946 DQM0 = 101, DQM1 = 94
5869 23:07:54.123086 DQ Delay:
5870 23:07:54.126388 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5871 23:07:54.129424 DQ4 =103, DQ5 =111, DQ6 =107, DQ7 =99
5872 23:07:54.132727 DQ8 =79, DQ9 =87, DQ10 =95, DQ11 =91
5873 23:07:54.135937 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =103
5874 23:07:54.136030
5875 23:07:54.136101
5876 23:07:54.139503 ==
5877 23:07:54.142443 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 23:07:54.145962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 23:07:54.146066 ==
5880 23:07:54.146133
5881 23:07:54.146195
5882 23:07:54.149157 TX Vref Scan disable
5883 23:07:54.149240 == TX Byte 0 ==
5884 23:07:54.152502 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5885 23:07:54.159217 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5886 23:07:54.159300 == TX Byte 1 ==
5887 23:07:54.162476 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5888 23:07:54.169372 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5889 23:07:54.169456 ==
5890 23:07:54.172733 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 23:07:54.175976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 23:07:54.176059 ==
5893 23:07:54.176126
5894 23:07:54.176187
5895 23:07:54.179267 TX Vref Scan disable
5896 23:07:54.182598 == TX Byte 0 ==
5897 23:07:54.185904 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5898 23:07:54.189331 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5899 23:07:54.192732 == TX Byte 1 ==
5900 23:07:54.196240 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5901 23:07:54.199192 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5902 23:07:54.199279
5903 23:07:54.199370 [DATLAT]
5904 23:07:54.202506 Freq=933, CH1 RK1
5905 23:07:54.202593
5906 23:07:54.205753 DATLAT Default: 0xb
5907 23:07:54.205889 0, 0xFFFF, sum = 0
5908 23:07:54.209652 1, 0xFFFF, sum = 0
5909 23:07:54.209744 2, 0xFFFF, sum = 0
5910 23:07:54.212878 3, 0xFFFF, sum = 0
5911 23:07:54.212969 4, 0xFFFF, sum = 0
5912 23:07:54.216124 5, 0xFFFF, sum = 0
5913 23:07:54.216242 6, 0xFFFF, sum = 0
5914 23:07:54.219661 7, 0xFFFF, sum = 0
5915 23:07:54.219747 8, 0xFFFF, sum = 0
5916 23:07:54.222682 9, 0xFFFF, sum = 0
5917 23:07:54.222773 10, 0x0, sum = 1
5918 23:07:54.225927 11, 0x0, sum = 2
5919 23:07:54.226055 12, 0x0, sum = 3
5920 23:07:54.229539 13, 0x0, sum = 4
5921 23:07:54.229629 best_step = 11
5922 23:07:54.229698
5923 23:07:54.229761 ==
5924 23:07:54.232596 Dram Type= 6, Freq= 0, CH_1, rank 1
5925 23:07:54.236200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5926 23:07:54.236277 ==
5927 23:07:54.239532 RX Vref Scan: 0
5928 23:07:54.239632
5929 23:07:54.242733 RX Vref 0 -> 0, step: 1
5930 23:07:54.242809
5931 23:07:54.242873 RX Delay -61 -> 252, step: 4
5932 23:07:54.250640 iDelay=199, Bit 0, Center 110 (35 ~ 186) 152
5933 23:07:54.253771 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5934 23:07:54.257032 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5935 23:07:54.260887 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5936 23:07:54.263618 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5937 23:07:54.270478 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5938 23:07:54.273813 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5939 23:07:54.277182 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5940 23:07:54.280480 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5941 23:07:54.283773 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5942 23:07:54.286906 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5943 23:07:54.293692 iDelay=199, Bit 11, Center 90 (3 ~ 178) 176
5944 23:07:54.296963 iDelay=199, Bit 12, Center 104 (19 ~ 190) 172
5945 23:07:54.300196 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5946 23:07:54.303637 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5947 23:07:54.310539 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5948 23:07:54.310644 ==
5949 23:07:54.313402 Dram Type= 6, Freq= 0, CH_1, rank 1
5950 23:07:54.316696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5951 23:07:54.316798 ==
5952 23:07:54.316895 DQS Delay:
5953 23:07:54.320185 DQS0 = 0, DQS1 = 0
5954 23:07:54.320271 DQM Delay:
5955 23:07:54.323474 DQM0 = 104, DQM1 = 96
5956 23:07:54.323559 DQ Delay:
5957 23:07:54.326835 DQ0 =110, DQ1 =98, DQ2 =94, DQ3 =102
5958 23:07:54.329951 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
5959 23:07:54.333730 DQ8 =82, DQ9 =86, DQ10 =98, DQ11 =90
5960 23:07:54.336827 DQ12 =104, DQ13 =102, DQ14 =102, DQ15 =106
5961 23:07:54.336911
5962 23:07:54.336977
5963 23:07:54.346577 [DQSOSCAuto] RK1, (LSB)MR18= 0x2401, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
5964 23:07:54.346666 CH1 RK1: MR19=505, MR18=2401
5965 23:07:54.353511 CH1_RK1: MR19=0x505, MR18=0x2401, DQSOSC=410, MR23=63, INC=64, DEC=42
5966 23:07:54.356887 [RxdqsGatingPostProcess] freq 933
5967 23:07:54.363356 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5968 23:07:54.366730 best DQS0 dly(2T, 0.5T) = (0, 10)
5969 23:07:54.370406 best DQS1 dly(2T, 0.5T) = (0, 10)
5970 23:07:54.373405 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5971 23:07:54.377003 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5972 23:07:54.379871 best DQS0 dly(2T, 0.5T) = (0, 10)
5973 23:07:54.380002 best DQS1 dly(2T, 0.5T) = (0, 10)
5974 23:07:54.383520 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5975 23:07:54.386933 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5976 23:07:54.390488 Pre-setting of DQS Precalculation
5977 23:07:54.396572 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5978 23:07:54.403246 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5979 23:07:54.409900 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5980 23:07:54.410096
5981 23:07:54.410200
5982 23:07:54.413243 [Calibration Summary] 1866 Mbps
5983 23:07:54.413359 CH 0, Rank 0
5984 23:07:54.416562 SW Impedance : PASS
5985 23:07:54.419842 DUTY Scan : NO K
5986 23:07:54.419967 ZQ Calibration : PASS
5987 23:07:54.423537 Jitter Meter : NO K
5988 23:07:54.427010 CBT Training : PASS
5989 23:07:54.427148 Write leveling : PASS
5990 23:07:54.430100 RX DQS gating : PASS
5991 23:07:54.433444 RX DQ/DQS(RDDQC) : PASS
5992 23:07:54.433576 TX DQ/DQS : PASS
5993 23:07:54.436616 RX DATLAT : PASS
5994 23:07:54.440218 RX DQ/DQS(Engine): PASS
5995 23:07:54.440361 TX OE : NO K
5996 23:07:54.443472 All Pass.
5997 23:07:54.443602
5998 23:07:54.443711 CH 0, Rank 1
5999 23:07:54.446648 SW Impedance : PASS
6000 23:07:54.446776 DUTY Scan : NO K
6001 23:07:54.450074 ZQ Calibration : PASS
6002 23:07:54.453504 Jitter Meter : NO K
6003 23:07:54.453605 CBT Training : PASS
6004 23:07:54.456506 Write leveling : PASS
6005 23:07:54.456610 RX DQS gating : PASS
6006 23:07:54.459998 RX DQ/DQS(RDDQC) : PASS
6007 23:07:54.463364 TX DQ/DQS : PASS
6008 23:07:54.463451 RX DATLAT : PASS
6009 23:07:54.467157 RX DQ/DQS(Engine): PASS
6010 23:07:54.470205 TX OE : NO K
6011 23:07:54.470291 All Pass.
6012 23:07:54.470359
6013 23:07:54.470422 CH 1, Rank 0
6014 23:07:54.473427 SW Impedance : PASS
6015 23:07:54.476620 DUTY Scan : NO K
6016 23:07:54.476706 ZQ Calibration : PASS
6017 23:07:54.479871 Jitter Meter : NO K
6018 23:07:54.483247 CBT Training : PASS
6019 23:07:54.483333 Write leveling : PASS
6020 23:07:54.486551 RX DQS gating : PASS
6021 23:07:54.489837 RX DQ/DQS(RDDQC) : PASS
6022 23:07:54.489923 TX DQ/DQS : PASS
6023 23:07:54.493095 RX DATLAT : PASS
6024 23:07:54.496415 RX DQ/DQS(Engine): PASS
6025 23:07:54.496501 TX OE : NO K
6026 23:07:54.496570 All Pass.
6027 23:07:54.499690
6028 23:07:54.499775 CH 1, Rank 1
6029 23:07:54.503425 SW Impedance : PASS
6030 23:07:54.503512 DUTY Scan : NO K
6031 23:07:54.506723 ZQ Calibration : PASS
6032 23:07:54.506818 Jitter Meter : NO K
6033 23:07:54.509912 CBT Training : PASS
6034 23:07:54.513214 Write leveling : PASS
6035 23:07:54.513310 RX DQS gating : PASS
6036 23:07:54.516394 RX DQ/DQS(RDDQC) : PASS
6037 23:07:54.519823 TX DQ/DQS : PASS
6038 23:07:54.519922 RX DATLAT : PASS
6039 23:07:54.523175 RX DQ/DQS(Engine): PASS
6040 23:07:54.526579 TX OE : NO K
6041 23:07:54.526675 All Pass.
6042 23:07:54.526743
6043 23:07:54.530137 DramC Write-DBI off
6044 23:07:54.530230 PER_BANK_REFRESH: Hybrid Mode
6045 23:07:54.533194 TX_TRACKING: ON
6046 23:07:54.543125 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6047 23:07:54.546248 [FAST_K] Save calibration result to emmc
6048 23:07:54.549637 dramc_set_vcore_voltage set vcore to 650000
6049 23:07:54.549725 Read voltage for 400, 6
6050 23:07:54.552641 Vio18 = 0
6051 23:07:54.552754 Vcore = 650000
6052 23:07:54.552850 Vdram = 0
6053 23:07:54.556161 Vddq = 0
6054 23:07:54.556247 Vmddr = 0
6055 23:07:54.559666 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6056 23:07:54.565917 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6057 23:07:54.569404 MEM_TYPE=3, freq_sel=20
6058 23:07:54.572442 sv_algorithm_assistance_LP4_800
6059 23:07:54.575965 ============ PULL DRAM RESETB DOWN ============
6060 23:07:54.579237 ========== PULL DRAM RESETB DOWN end =========
6061 23:07:54.585823 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6062 23:07:54.589205 ===================================
6063 23:07:54.589317 LPDDR4 DRAM CONFIGURATION
6064 23:07:54.592507 ===================================
6065 23:07:54.595639 EX_ROW_EN[0] = 0x0
6066 23:07:54.595760 EX_ROW_EN[1] = 0x0
6067 23:07:54.599458 LP4Y_EN = 0x0
6068 23:07:54.602701 WORK_FSP = 0x0
6069 23:07:54.602798 WL = 0x2
6070 23:07:54.605482 RL = 0x2
6071 23:07:54.605593 BL = 0x2
6072 23:07:54.608860 RPST = 0x0
6073 23:07:54.608966 RD_PRE = 0x0
6074 23:07:54.612206 WR_PRE = 0x1
6075 23:07:54.612310 WR_PST = 0x0
6076 23:07:54.615495 DBI_WR = 0x0
6077 23:07:54.615599 DBI_RD = 0x0
6078 23:07:54.618930 OTF = 0x1
6079 23:07:54.622137 ===================================
6080 23:07:54.625893 ===================================
6081 23:07:54.625989 ANA top config
6082 23:07:54.629083 ===================================
6083 23:07:54.632451 DLL_ASYNC_EN = 0
6084 23:07:54.635831 ALL_SLAVE_EN = 1
6085 23:07:54.635918 NEW_RANK_MODE = 1
6086 23:07:54.639065 DLL_IDLE_MODE = 1
6087 23:07:54.641913 LP45_APHY_COMB_EN = 1
6088 23:07:54.645378 TX_ODT_DIS = 1
6089 23:07:54.648747 NEW_8X_MODE = 1
6090 23:07:54.651873 ===================================
6091 23:07:54.655173 ===================================
6092 23:07:54.655286 data_rate = 800
6093 23:07:54.658431 CKR = 1
6094 23:07:54.661970 DQ_P2S_RATIO = 4
6095 23:07:54.665328 ===================================
6096 23:07:54.668733 CA_P2S_RATIO = 4
6097 23:07:54.671595 DQ_CA_OPEN = 0
6098 23:07:54.675019 DQ_SEMI_OPEN = 1
6099 23:07:54.675129 CA_SEMI_OPEN = 1
6100 23:07:54.678529 CA_FULL_RATE = 0
6101 23:07:54.681878 DQ_CKDIV4_EN = 0
6102 23:07:54.685227 CA_CKDIV4_EN = 1
6103 23:07:54.688270 CA_PREDIV_EN = 0
6104 23:07:54.691855 PH8_DLY = 0
6105 23:07:54.691949 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6106 23:07:54.695280 DQ_AAMCK_DIV = 0
6107 23:07:54.698213 CA_AAMCK_DIV = 0
6108 23:07:54.701822 CA_ADMCK_DIV = 4
6109 23:07:54.704875 DQ_TRACK_CA_EN = 0
6110 23:07:54.708260 CA_PICK = 800
6111 23:07:54.711489 CA_MCKIO = 400
6112 23:07:54.711574 MCKIO_SEMI = 400
6113 23:07:54.714789 PLL_FREQ = 3016
6114 23:07:54.718104 DQ_UI_PI_RATIO = 32
6115 23:07:54.721400 CA_UI_PI_RATIO = 32
6116 23:07:54.725095 ===================================
6117 23:07:54.728302 ===================================
6118 23:07:54.731572 memory_type:LPDDR4
6119 23:07:54.731657 GP_NUM : 10
6120 23:07:54.734999 SRAM_EN : 1
6121 23:07:54.737898 MD32_EN : 0
6122 23:07:54.741273 ===================================
6123 23:07:54.741357 [ANA_INIT] >>>>>>>>>>>>>>
6124 23:07:54.744689 <<<<<< [CONFIGURE PHASE]: ANA_TX
6125 23:07:54.747876 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6126 23:07:54.751313 ===================================
6127 23:07:54.754454 data_rate = 800,PCW = 0X7400
6128 23:07:54.757806 ===================================
6129 23:07:54.761309 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6130 23:07:54.767771 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6131 23:07:54.777630 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6132 23:07:54.784596 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6133 23:07:54.788003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6134 23:07:54.791126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6135 23:07:54.791276 [ANA_INIT] flow start
6136 23:07:54.794104 [ANA_INIT] PLL >>>>>>>>
6137 23:07:54.797921 [ANA_INIT] PLL <<<<<<<<
6138 23:07:54.798101 [ANA_INIT] MIDPI >>>>>>>>
6139 23:07:54.801237 [ANA_INIT] MIDPI <<<<<<<<
6140 23:07:54.804410 [ANA_INIT] DLL >>>>>>>>
6141 23:07:54.804554 [ANA_INIT] flow end
6142 23:07:54.810983 ============ LP4 DIFF to SE enter ============
6143 23:07:54.814329 ============ LP4 DIFF to SE exit ============
6144 23:07:54.817240 [ANA_INIT] <<<<<<<<<<<<<
6145 23:07:54.820789 [Flow] Enable top DCM control >>>>>
6146 23:07:54.824014 [Flow] Enable top DCM control <<<<<
6147 23:07:54.824113 Enable DLL master slave shuffle
6148 23:07:54.830691 ==============================================================
6149 23:07:54.834363 Gating Mode config
6150 23:07:54.837414 ==============================================================
6151 23:07:54.840755 Config description:
6152 23:07:54.851040 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6153 23:07:54.857330 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6154 23:07:54.860697 SELPH_MODE 0: By rank 1: By Phase
6155 23:07:54.867643 ==============================================================
6156 23:07:54.870812 GAT_TRACK_EN = 0
6157 23:07:54.874044 RX_GATING_MODE = 2
6158 23:07:54.877341 RX_GATING_TRACK_MODE = 2
6159 23:07:54.877449 SELPH_MODE = 1
6160 23:07:54.880844 PICG_EARLY_EN = 1
6161 23:07:54.883928 VALID_LAT_VALUE = 1
6162 23:07:54.890795 ==============================================================
6163 23:07:54.894448 Enter into Gating configuration >>>>
6164 23:07:54.897082 Exit from Gating configuration <<<<
6165 23:07:54.900726 Enter into DVFS_PRE_config >>>>>
6166 23:07:54.910731 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6167 23:07:54.914067 Exit from DVFS_PRE_config <<<<<
6168 23:07:54.917330 Enter into PICG configuration >>>>
6169 23:07:54.920255 Exit from PICG configuration <<<<
6170 23:07:54.924102 [RX_INPUT] configuration >>>>>
6171 23:07:54.926893 [RX_INPUT] configuration <<<<<
6172 23:07:54.930701 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6173 23:07:54.937190 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6174 23:07:54.943864 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6175 23:07:54.950444 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6176 23:07:54.957016 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6177 23:07:54.960276 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6178 23:07:54.967111 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6179 23:07:54.970280 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6180 23:07:54.973686 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6181 23:07:54.976819 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6182 23:07:54.980446 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6183 23:07:54.987010 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6184 23:07:54.990563 ===================================
6185 23:07:54.993602 LPDDR4 DRAM CONFIGURATION
6186 23:07:54.997235 ===================================
6187 23:07:54.997320 EX_ROW_EN[0] = 0x0
6188 23:07:55.000428 EX_ROW_EN[1] = 0x0
6189 23:07:55.000512 LP4Y_EN = 0x0
6190 23:07:55.003638 WORK_FSP = 0x0
6191 23:07:55.003721 WL = 0x2
6192 23:07:55.007007 RL = 0x2
6193 23:07:55.007091 BL = 0x2
6194 23:07:55.010248 RPST = 0x0
6195 23:07:55.010332 RD_PRE = 0x0
6196 23:07:55.013502 WR_PRE = 0x1
6197 23:07:55.013585 WR_PST = 0x0
6198 23:07:55.017327 DBI_WR = 0x0
6199 23:07:55.017410 DBI_RD = 0x0
6200 23:07:55.020307 OTF = 0x1
6201 23:07:55.023579 ===================================
6202 23:07:55.026909 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6203 23:07:55.030236 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6204 23:07:55.036931 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6205 23:07:55.040293 ===================================
6206 23:07:55.040394 LPDDR4 DRAM CONFIGURATION
6207 23:07:55.043651 ===================================
6208 23:07:55.046959 EX_ROW_EN[0] = 0x10
6209 23:07:55.050412 EX_ROW_EN[1] = 0x0
6210 23:07:55.050496 LP4Y_EN = 0x0
6211 23:07:55.053712 WORK_FSP = 0x0
6212 23:07:55.053795 WL = 0x2
6213 23:07:55.057022 RL = 0x2
6214 23:07:55.057105 BL = 0x2
6215 23:07:55.060694 RPST = 0x0
6216 23:07:55.060777 RD_PRE = 0x0
6217 23:07:55.063673 WR_PRE = 0x1
6218 23:07:55.063757 WR_PST = 0x0
6219 23:07:55.066937 DBI_WR = 0x0
6220 23:07:55.067020 DBI_RD = 0x0
6221 23:07:55.070343 OTF = 0x1
6222 23:07:55.073591 ===================================
6223 23:07:55.080479 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6224 23:07:55.083660 nWR fixed to 30
6225 23:07:55.083747 [ModeRegInit_LP4] CH0 RK0
6226 23:07:55.087438 [ModeRegInit_LP4] CH0 RK1
6227 23:07:55.090492 [ModeRegInit_LP4] CH1 RK0
6228 23:07:55.090575 [ModeRegInit_LP4] CH1 RK1
6229 23:07:55.094142 match AC timing 19
6230 23:07:55.097060 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6231 23:07:55.100213 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6232 23:07:55.107016 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6233 23:07:55.110435 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6234 23:07:55.116918 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6235 23:07:55.117005 ==
6236 23:07:55.120435 Dram Type= 6, Freq= 0, CH_0, rank 0
6237 23:07:55.123769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6238 23:07:55.123856 ==
6239 23:07:55.130369 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6240 23:07:55.133681 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6241 23:07:55.136771 [CA 0] Center 36 (8~64) winsize 57
6242 23:07:55.140168 [CA 1] Center 36 (8~64) winsize 57
6243 23:07:55.143457 [CA 2] Center 36 (8~64) winsize 57
6244 23:07:55.146879 [CA 3] Center 36 (8~64) winsize 57
6245 23:07:55.150251 [CA 4] Center 36 (8~64) winsize 57
6246 23:07:55.153591 [CA 5] Center 36 (8~64) winsize 57
6247 23:07:55.153676
6248 23:07:55.157003 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6249 23:07:55.157089
6250 23:07:55.160319 [CATrainingPosCal] consider 1 rank data
6251 23:07:55.163952 u2DelayCellTimex100 = 270/100 ps
6252 23:07:55.166951 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 23:07:55.170295 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 23:07:55.173872 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 23:07:55.180039 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 23:07:55.183645 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 23:07:55.187019 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 23:07:55.187106
6259 23:07:55.190282 CA PerBit enable=1, Macro0, CA PI delay=36
6260 23:07:55.190368
6261 23:07:55.193872 [CBTSetCACLKResult] CA Dly = 36
6262 23:07:55.193994 CS Dly: 1 (0~32)
6263 23:07:55.194081 ==
6264 23:07:55.196749 Dram Type= 6, Freq= 0, CH_0, rank 1
6265 23:07:55.203514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 23:07:55.203631 ==
6267 23:07:55.206877 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6268 23:07:55.213616 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6269 23:07:55.217017 [CA 0] Center 36 (8~64) winsize 57
6270 23:07:55.220339 [CA 1] Center 36 (8~64) winsize 57
6271 23:07:55.223585 [CA 2] Center 36 (8~64) winsize 57
6272 23:07:55.226831 [CA 3] Center 36 (8~64) winsize 57
6273 23:07:55.230112 [CA 4] Center 36 (8~64) winsize 57
6274 23:07:55.233505 [CA 5] Center 36 (8~64) winsize 57
6275 23:07:55.233592
6276 23:07:55.236760 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6277 23:07:55.236848
6278 23:07:55.240062 [CATrainingPosCal] consider 2 rank data
6279 23:07:55.243859 u2DelayCellTimex100 = 270/100 ps
6280 23:07:55.247125 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 23:07:55.250457 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 23:07:55.253809 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 23:07:55.257035 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 23:07:55.260355 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 23:07:55.263704 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 23:07:55.263790
6287 23:07:55.269848 CA PerBit enable=1, Macro0, CA PI delay=36
6288 23:07:55.269936
6289 23:07:55.273502 [CBTSetCACLKResult] CA Dly = 36
6290 23:07:55.273589 CS Dly: 1 (0~32)
6291 23:07:55.273675
6292 23:07:55.276840 ----->DramcWriteLeveling(PI) begin...
6293 23:07:55.276928 ==
6294 23:07:55.279884 Dram Type= 6, Freq= 0, CH_0, rank 0
6295 23:07:55.283491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 23:07:55.283578 ==
6297 23:07:55.286681 Write leveling (Byte 0): 40 => 8
6298 23:07:55.289718 Write leveling (Byte 1): 32 => 0
6299 23:07:55.293122 DramcWriteLeveling(PI) end<-----
6300 23:07:55.293208
6301 23:07:55.293294 ==
6302 23:07:55.296491 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 23:07:55.302999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 23:07:55.303088 ==
6305 23:07:55.303174 [Gating] SW mode calibration
6306 23:07:55.312882 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6307 23:07:55.316380 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6308 23:07:55.319422 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6309 23:07:55.326398 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6310 23:07:55.329412 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6311 23:07:55.332767 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6312 23:07:55.339514 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6313 23:07:55.342700 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6314 23:07:55.345913 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6315 23:07:55.352697 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6316 23:07:55.356500 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6317 23:07:55.359284 Total UI for P1: 0, mck2ui 16
6318 23:07:55.362632 best dqsien dly found for B0: ( 0, 14, 24)
6319 23:07:55.366341 Total UI for P1: 0, mck2ui 16
6320 23:07:55.369440 best dqsien dly found for B1: ( 0, 14, 24)
6321 23:07:55.373110 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6322 23:07:55.375900 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6323 23:07:55.375986
6324 23:07:55.379569 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6325 23:07:55.382837 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6326 23:07:55.386271 [Gating] SW calibration Done
6327 23:07:55.386356 ==
6328 23:07:55.389254 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 23:07:55.396014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 23:07:55.396100 ==
6331 23:07:55.396165 RX Vref Scan: 0
6332 23:07:55.396226
6333 23:07:55.399278 RX Vref 0 -> 0, step: 1
6334 23:07:55.399361
6335 23:07:55.402735 RX Delay -410 -> 252, step: 16
6336 23:07:55.405888 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6337 23:07:55.409447 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6338 23:07:55.412824 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6339 23:07:55.419371 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6340 23:07:55.422772 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6341 23:07:55.426191 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6342 23:07:55.429611 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6343 23:07:55.435773 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6344 23:07:55.439149 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6345 23:07:55.442889 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6346 23:07:55.445791 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6347 23:07:55.452507 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6348 23:07:55.455962 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6349 23:07:55.459272 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6350 23:07:55.462510 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6351 23:07:55.469248 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6352 23:07:55.469329 ==
6353 23:07:55.472507 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 23:07:55.475707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 23:07:55.475790 ==
6356 23:07:55.475855 DQS Delay:
6357 23:07:55.479360 DQS0 = 27, DQS1 = 43
6358 23:07:55.479441 DQM Delay:
6359 23:07:55.482801 DQM0 = 13, DQM1 = 13
6360 23:07:55.482882 DQ Delay:
6361 23:07:55.486049 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6362 23:07:55.488908 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6363 23:07:55.492500 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6364 23:07:55.495805 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6365 23:07:55.495887
6366 23:07:55.495952
6367 23:07:55.496011 ==
6368 23:07:55.498967 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 23:07:55.502883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 23:07:55.502967 ==
6371 23:07:55.503032
6372 23:07:55.503092
6373 23:07:55.505959 TX Vref Scan disable
6374 23:07:55.509484 == TX Byte 0 ==
6375 23:07:55.512577 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6376 23:07:55.515629 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6377 23:07:55.519062 == TX Byte 1 ==
6378 23:07:55.522325 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6379 23:07:55.525781 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6380 23:07:55.525862 ==
6381 23:07:55.529151 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 23:07:55.532619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 23:07:55.532701 ==
6384 23:07:55.535838
6385 23:07:55.535920
6386 23:07:55.535985 TX Vref Scan disable
6387 23:07:55.539170 == TX Byte 0 ==
6388 23:07:55.542264 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6389 23:07:55.545644 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6390 23:07:55.548885 == TX Byte 1 ==
6391 23:07:55.552328 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6392 23:07:55.555623 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6393 23:07:55.555721
6394 23:07:55.555812 [DATLAT]
6395 23:07:55.558902 Freq=400, CH0 RK0
6396 23:07:55.559003
6397 23:07:55.562673 DATLAT Default: 0xf
6398 23:07:55.562754 0, 0xFFFF, sum = 0
6399 23:07:55.565836 1, 0xFFFF, sum = 0
6400 23:07:55.565945 2, 0xFFFF, sum = 0
6401 23:07:55.569132 3, 0xFFFF, sum = 0
6402 23:07:55.569203 4, 0xFFFF, sum = 0
6403 23:07:55.572135 5, 0xFFFF, sum = 0
6404 23:07:55.572207 6, 0xFFFF, sum = 0
6405 23:07:55.575744 7, 0xFFFF, sum = 0
6406 23:07:55.575817 8, 0xFFFF, sum = 0
6407 23:07:55.579060 9, 0xFFFF, sum = 0
6408 23:07:55.579139 10, 0xFFFF, sum = 0
6409 23:07:55.582429 11, 0xFFFF, sum = 0
6410 23:07:55.582504 12, 0xFFFF, sum = 0
6411 23:07:55.585774 13, 0x0, sum = 1
6412 23:07:55.585852 14, 0x0, sum = 2
6413 23:07:55.588716 15, 0x0, sum = 3
6414 23:07:55.588799 16, 0x0, sum = 4
6415 23:07:55.592135 best_step = 14
6416 23:07:55.592224
6417 23:07:55.592287 ==
6418 23:07:55.595410 Dram Type= 6, Freq= 0, CH_0, rank 0
6419 23:07:55.598957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6420 23:07:55.599034 ==
6421 23:07:55.602189 RX Vref Scan: 1
6422 23:07:55.602261
6423 23:07:55.602331 RX Vref 0 -> 0, step: 1
6424 23:07:55.602390
6425 23:07:55.605582 RX Delay -327 -> 252, step: 8
6426 23:07:55.605681
6427 23:07:55.609008 Set Vref, RX VrefLevel [Byte0]: 58
6428 23:07:55.611770 [Byte1]: 51
6429 23:07:55.616429
6430 23:07:55.616539 Final RX Vref Byte 0 = 58 to rank0
6431 23:07:55.619834 Final RX Vref Byte 1 = 51 to rank0
6432 23:07:55.623577 Final RX Vref Byte 0 = 58 to rank1
6433 23:07:55.626531 Final RX Vref Byte 1 = 51 to rank1==
6434 23:07:55.629922 Dram Type= 6, Freq= 0, CH_0, rank 0
6435 23:07:55.636455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6436 23:07:55.636561 ==
6437 23:07:55.636656 DQS Delay:
6438 23:07:55.636747 DQS0 = 24, DQS1 = 48
6439 23:07:55.640086 DQM Delay:
6440 23:07:55.640187 DQM0 = 8, DQM1 = 15
6441 23:07:55.643210 DQ Delay:
6442 23:07:55.643287 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6443 23:07:55.646845 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6444 23:07:55.650075 DQ8 =12, DQ9 =0, DQ10 =12, DQ11 =8
6445 23:07:55.653473 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6446 23:07:55.653575
6447 23:07:55.653666
6448 23:07:55.663274 [DQSOSCAuto] RK0, (LSB)MR18= 0xb2ab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6449 23:07:55.666397 CH0 RK0: MR19=C0C, MR18=B2AB
6450 23:07:55.672917 CH0_RK0: MR19=0xC0C, MR18=0xB2AB, DQSOSC=387, MR23=63, INC=394, DEC=262
6451 23:07:55.673001 ==
6452 23:07:55.676428 Dram Type= 6, Freq= 0, CH_0, rank 1
6453 23:07:55.679686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 23:07:55.679770 ==
6455 23:07:55.683026 [Gating] SW mode calibration
6456 23:07:55.689657 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6457 23:07:55.693431 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6458 23:07:55.699592 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6459 23:07:55.703163 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6460 23:07:55.706527 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6461 23:07:55.713165 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6462 23:07:55.716408 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6463 23:07:55.719524 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6464 23:07:55.726179 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6465 23:07:55.729190 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6466 23:07:55.732689 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6467 23:07:55.736078 Total UI for P1: 0, mck2ui 16
6468 23:07:55.739655 best dqsien dly found for B0: ( 0, 14, 24)
6469 23:07:55.742858 Total UI for P1: 0, mck2ui 16
6470 23:07:55.745910 best dqsien dly found for B1: ( 0, 14, 24)
6471 23:07:55.749633 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6472 23:07:55.752624 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6473 23:07:55.752698
6474 23:07:55.759270 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6475 23:07:55.762527 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6476 23:07:55.766232 [Gating] SW calibration Done
6477 23:07:55.766305 ==
6478 23:07:55.769123 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 23:07:55.772519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 23:07:55.772588 ==
6481 23:07:55.772648 RX Vref Scan: 0
6482 23:07:55.772706
6483 23:07:55.775891 RX Vref 0 -> 0, step: 1
6484 23:07:55.775958
6485 23:07:55.779623 RX Delay -410 -> 252, step: 16
6486 23:07:55.782842 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6487 23:07:55.789456 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6488 23:07:55.792856 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6489 23:07:55.795685 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6490 23:07:55.799021 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6491 23:07:55.806108 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6492 23:07:55.809324 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6493 23:07:55.812616 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6494 23:07:55.815966 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6495 23:07:55.822668 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6496 23:07:55.825832 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6497 23:07:55.829212 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6498 23:07:55.832340 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6499 23:07:55.839171 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6500 23:07:55.842436 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6501 23:07:55.845646 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6502 23:07:55.845729 ==
6503 23:07:55.849046 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 23:07:55.852509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 23:07:55.856038 ==
6506 23:07:55.856122 DQS Delay:
6507 23:07:55.856188 DQS0 = 27, DQS1 = 43
6508 23:07:55.859545 DQM Delay:
6509 23:07:55.859653 DQM0 = 10, DQM1 = 15
6510 23:07:55.862394 DQ Delay:
6511 23:07:55.862478 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6512 23:07:55.865735 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6513 23:07:55.869084 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6514 23:07:55.872446 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6515 23:07:55.872529
6516 23:07:55.872595
6517 23:07:55.872656 ==
6518 23:07:55.875879 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 23:07:55.882405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 23:07:55.882489 ==
6521 23:07:55.882556
6522 23:07:55.882619
6523 23:07:55.882679 TX Vref Scan disable
6524 23:07:55.885705 == TX Byte 0 ==
6525 23:07:55.889065 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6526 23:07:55.892305 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6527 23:07:55.896135 == TX Byte 1 ==
6528 23:07:55.899042 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6529 23:07:55.902389 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6530 23:07:55.902473 ==
6531 23:07:55.905664 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 23:07:55.912587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 23:07:55.912688 ==
6534 23:07:55.912787
6535 23:07:55.912865
6536 23:07:55.912923 TX Vref Scan disable
6537 23:07:55.915700 == TX Byte 0 ==
6538 23:07:55.919288 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6539 23:07:55.922672 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6540 23:07:55.925642 == TX Byte 1 ==
6541 23:07:55.928989 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6542 23:07:55.932272 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6543 23:07:55.932355
6544 23:07:55.935854 [DATLAT]
6545 23:07:55.935963 Freq=400, CH0 RK1
6546 23:07:55.936064
6547 23:07:55.939102 DATLAT Default: 0xe
6548 23:07:55.939185 0, 0xFFFF, sum = 0
6549 23:07:55.942482 1, 0xFFFF, sum = 0
6550 23:07:55.942566 2, 0xFFFF, sum = 0
6551 23:07:55.945817 3, 0xFFFF, sum = 0
6552 23:07:55.945928 4, 0xFFFF, sum = 0
6553 23:07:55.949119 5, 0xFFFF, sum = 0
6554 23:07:55.949204 6, 0xFFFF, sum = 0
6555 23:07:55.952147 7, 0xFFFF, sum = 0
6556 23:07:55.952232 8, 0xFFFF, sum = 0
6557 23:07:55.955534 9, 0xFFFF, sum = 0
6558 23:07:55.955618 10, 0xFFFF, sum = 0
6559 23:07:55.958871 11, 0xFFFF, sum = 0
6560 23:07:55.962262 12, 0xFFFF, sum = 0
6561 23:07:55.962347 13, 0x0, sum = 1
6562 23:07:55.962414 14, 0x0, sum = 2
6563 23:07:55.965456 15, 0x0, sum = 3
6564 23:07:55.965540 16, 0x0, sum = 4
6565 23:07:55.968968 best_step = 14
6566 23:07:55.969051
6567 23:07:55.969117 ==
6568 23:07:55.972474 Dram Type= 6, Freq= 0, CH_0, rank 1
6569 23:07:55.975473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6570 23:07:55.975557 ==
6571 23:07:55.978761 RX Vref Scan: 0
6572 23:07:55.978843
6573 23:07:55.978910 RX Vref 0 -> 0, step: 1
6574 23:07:55.978971
6575 23:07:55.982283 RX Delay -327 -> 252, step: 8
6576 23:07:55.990418 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6577 23:07:55.993770 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6578 23:07:55.997086 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6579 23:07:56.000466 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6580 23:07:56.007009 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6581 23:07:56.010321 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6582 23:07:56.013867 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6583 23:07:56.016981 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6584 23:07:56.023725 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6585 23:07:56.027016 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6586 23:07:56.030256 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6587 23:07:56.033492 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6588 23:07:56.040164 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6589 23:07:56.043344 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6590 23:07:56.046907 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6591 23:07:56.053485 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6592 23:07:56.053568 ==
6593 23:07:56.056899 Dram Type= 6, Freq= 0, CH_0, rank 1
6594 23:07:56.059906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 23:07:56.059990 ==
6596 23:07:56.060057 DQS Delay:
6597 23:07:56.063429 DQS0 = 28, DQS1 = 44
6598 23:07:56.063513 DQM Delay:
6599 23:07:56.066406 DQM0 = 10, DQM1 = 15
6600 23:07:56.066489 DQ Delay:
6601 23:07:56.069867 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6602 23:07:56.073379 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6603 23:07:56.077015 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6604 23:07:56.079912 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =20
6605 23:07:56.079999
6606 23:07:56.080066
6607 23:07:56.086689 [DQSOSCAuto] RK1, (LSB)MR18= 0xba6e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6608 23:07:56.089975 CH0 RK1: MR19=C0C, MR18=BA6E
6609 23:07:56.096773 CH0_RK1: MR19=0xC0C, MR18=0xBA6E, DQSOSC=386, MR23=63, INC=396, DEC=264
6610 23:07:56.100066 [RxdqsGatingPostProcess] freq 400
6611 23:07:56.106647 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6612 23:07:56.106731 best DQS0 dly(2T, 0.5T) = (0, 10)
6613 23:07:56.110037 best DQS1 dly(2T, 0.5T) = (0, 10)
6614 23:07:56.113372 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6615 23:07:56.116661 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6616 23:07:56.120171 best DQS0 dly(2T, 0.5T) = (0, 10)
6617 23:07:56.123246 best DQS1 dly(2T, 0.5T) = (0, 10)
6618 23:07:56.126578 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6619 23:07:56.129918 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6620 23:07:56.133377 Pre-setting of DQS Precalculation
6621 23:07:56.139717 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6622 23:07:56.139800 ==
6623 23:07:56.143207 Dram Type= 6, Freq= 0, CH_1, rank 0
6624 23:07:56.146319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 23:07:56.146402 ==
6626 23:07:56.152939 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6627 23:07:56.156558 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6628 23:07:56.159621 [CA 0] Center 36 (8~64) winsize 57
6629 23:07:56.163059 [CA 1] Center 36 (8~64) winsize 57
6630 23:07:56.166202 [CA 2] Center 36 (8~64) winsize 57
6631 23:07:56.169766 [CA 3] Center 36 (8~64) winsize 57
6632 23:07:56.172955 [CA 4] Center 36 (8~64) winsize 57
6633 23:07:56.176214 [CA 5] Center 36 (8~64) winsize 57
6634 23:07:56.176299
6635 23:07:56.179470 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6636 23:07:56.179554
6637 23:07:56.182705 [CATrainingPosCal] consider 1 rank data
6638 23:07:56.186148 u2DelayCellTimex100 = 270/100 ps
6639 23:07:56.189644 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 23:07:56.193029 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 23:07:56.196383 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 23:07:56.202977 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 23:07:56.206282 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 23:07:56.209171 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 23:07:56.209246
6646 23:07:56.213005 CA PerBit enable=1, Macro0, CA PI delay=36
6647 23:07:56.213112
6648 23:07:56.216386 [CBTSetCACLKResult] CA Dly = 36
6649 23:07:56.216492 CS Dly: 1 (0~32)
6650 23:07:56.216589 ==
6651 23:07:56.219569 Dram Type= 6, Freq= 0, CH_1, rank 1
6652 23:07:56.225898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 23:07:56.226019 ==
6654 23:07:56.229370 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6655 23:07:56.235842 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6656 23:07:56.239157 [CA 0] Center 36 (8~64) winsize 57
6657 23:07:56.242417 [CA 1] Center 36 (8~64) winsize 57
6658 23:07:56.245828 [CA 2] Center 36 (8~64) winsize 57
6659 23:07:56.249168 [CA 3] Center 36 (8~64) winsize 57
6660 23:07:56.252429 [CA 4] Center 36 (8~64) winsize 57
6661 23:07:56.255778 [CA 5] Center 36 (8~64) winsize 57
6662 23:07:56.255889
6663 23:07:56.258986 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6664 23:07:56.259065
6665 23:07:56.262522 [CATrainingPosCal] consider 2 rank data
6666 23:07:56.265858 u2DelayCellTimex100 = 270/100 ps
6667 23:07:56.269029 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 23:07:56.272711 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 23:07:56.276079 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 23:07:56.279263 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 23:07:56.282726 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 23:07:56.285848 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 23:07:56.285933
6674 23:07:56.292764 CA PerBit enable=1, Macro0, CA PI delay=36
6675 23:07:56.292849
6676 23:07:56.296006 [CBTSetCACLKResult] CA Dly = 36
6677 23:07:56.296096 CS Dly: 1 (0~32)
6678 23:07:56.296198
6679 23:07:56.299054 ----->DramcWriteLeveling(PI) begin...
6680 23:07:56.299140 ==
6681 23:07:56.302435 Dram Type= 6, Freq= 0, CH_1, rank 0
6682 23:07:56.305782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 23:07:56.305891 ==
6684 23:07:56.309108 Write leveling (Byte 0): 40 => 8
6685 23:07:56.312546 Write leveling (Byte 1): 32 => 0
6686 23:07:56.315842 DramcWriteLeveling(PI) end<-----
6687 23:07:56.315926
6688 23:07:56.316010 ==
6689 23:07:56.319080 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 23:07:56.322461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 23:07:56.325672 ==
6692 23:07:56.325757 [Gating] SW mode calibration
6693 23:07:56.335820 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6694 23:07:56.339186 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6695 23:07:56.342486 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6696 23:07:56.349076 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6697 23:07:56.352336 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6698 23:07:56.355509 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6699 23:07:56.362255 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6700 23:07:56.365507 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6701 23:07:56.368981 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6702 23:07:56.375476 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6703 23:07:56.378897 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6704 23:07:56.382194 Total UI for P1: 0, mck2ui 16
6705 23:07:56.385730 best dqsien dly found for B0: ( 0, 14, 24)
6706 23:07:56.389162 Total UI for P1: 0, mck2ui 16
6707 23:07:56.392751 best dqsien dly found for B1: ( 0, 14, 24)
6708 23:07:56.395618 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6709 23:07:56.399076 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6710 23:07:56.399161
6711 23:07:56.402560 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6712 23:07:56.405484 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6713 23:07:56.408880 [Gating] SW calibration Done
6714 23:07:56.408963 ==
6715 23:07:56.412313 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 23:07:56.415461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 23:07:56.415544 ==
6718 23:07:56.418722 RX Vref Scan: 0
6719 23:07:56.418805
6720 23:07:56.422444 RX Vref 0 -> 0, step: 1
6721 23:07:56.422527
6722 23:07:56.425397 RX Delay -410 -> 252, step: 16
6723 23:07:56.428802 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6724 23:07:56.432151 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6725 23:07:56.435439 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6726 23:07:56.442030 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6727 23:07:56.445574 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6728 23:07:56.448908 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6729 23:07:56.452365 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6730 23:07:56.458784 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6731 23:07:56.462123 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6732 23:07:56.465492 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6733 23:07:56.468853 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6734 23:07:56.475550 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6735 23:07:56.478559 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6736 23:07:56.482151 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6737 23:07:56.485313 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6738 23:07:56.491858 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6739 23:07:56.491941 ==
6740 23:07:56.495293 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 23:07:56.499205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 23:07:56.499290 ==
6743 23:07:56.499357 DQS Delay:
6744 23:07:56.502054 DQS0 = 27, DQS1 = 43
6745 23:07:56.502138 DQM Delay:
6746 23:07:56.505545 DQM0 = 5, DQM1 = 16
6747 23:07:56.505627 DQ Delay:
6748 23:07:56.508713 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6749 23:07:56.512216 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6750 23:07:56.515599 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6751 23:07:56.518865 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6752 23:07:56.518949
6753 23:07:56.519015
6754 23:07:56.519074 ==
6755 23:07:56.522190 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 23:07:56.525510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 23:07:56.525594 ==
6758 23:07:56.525661
6759 23:07:56.525722
6760 23:07:56.528844 TX Vref Scan disable
6761 23:07:56.528927 == TX Byte 0 ==
6762 23:07:56.535511 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6763 23:07:56.538572 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6764 23:07:56.538655 == TX Byte 1 ==
6765 23:07:56.545135 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6766 23:07:56.548429 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6767 23:07:56.548512 ==
6768 23:07:56.551826 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 23:07:56.555642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 23:07:56.555726 ==
6771 23:07:56.555792
6772 23:07:56.555853
6773 23:07:56.558821 TX Vref Scan disable
6774 23:07:56.558903 == TX Byte 0 ==
6775 23:07:56.565667 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 23:07:56.568947 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 23:07:56.569030 == TX Byte 1 ==
6778 23:07:56.575222 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6779 23:07:56.578929 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6780 23:07:56.579011
6781 23:07:56.579077 [DATLAT]
6782 23:07:56.582068 Freq=400, CH1 RK0
6783 23:07:56.582151
6784 23:07:56.582217 DATLAT Default: 0xf
6785 23:07:56.585473 0, 0xFFFF, sum = 0
6786 23:07:56.585557 1, 0xFFFF, sum = 0
6787 23:07:56.588561 2, 0xFFFF, sum = 0
6788 23:07:56.588660 3, 0xFFFF, sum = 0
6789 23:07:56.592021 4, 0xFFFF, sum = 0
6790 23:07:56.595375 5, 0xFFFF, sum = 0
6791 23:07:56.595459 6, 0xFFFF, sum = 0
6792 23:07:56.599003 7, 0xFFFF, sum = 0
6793 23:07:56.599088 8, 0xFFFF, sum = 0
6794 23:07:56.601668 9, 0xFFFF, sum = 0
6795 23:07:56.601752 10, 0xFFFF, sum = 0
6796 23:07:56.605154 11, 0xFFFF, sum = 0
6797 23:07:56.605239 12, 0xFFFF, sum = 0
6798 23:07:56.608608 13, 0x0, sum = 1
6799 23:07:56.608692 14, 0x0, sum = 2
6800 23:07:56.611937 15, 0x0, sum = 3
6801 23:07:56.612022 16, 0x0, sum = 4
6802 23:07:56.615326 best_step = 14
6803 23:07:56.615409
6804 23:07:56.615475 ==
6805 23:07:56.618803 Dram Type= 6, Freq= 0, CH_1, rank 0
6806 23:07:56.621575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6807 23:07:56.621658 ==
6808 23:07:56.621725 RX Vref Scan: 1
6809 23:07:56.624890
6810 23:07:56.624974 RX Vref 0 -> 0, step: 1
6811 23:07:56.625041
6812 23:07:56.628167 RX Delay -327 -> 252, step: 8
6813 23:07:56.628250
6814 23:07:56.631521 Set Vref, RX VrefLevel [Byte0]: 51
6815 23:07:56.634854 [Byte1]: 49
6816 23:07:56.639130
6817 23:07:56.639214 Final RX Vref Byte 0 = 51 to rank0
6818 23:07:56.642486 Final RX Vref Byte 1 = 49 to rank0
6819 23:07:56.645626 Final RX Vref Byte 0 = 51 to rank1
6820 23:07:56.648917 Final RX Vref Byte 1 = 49 to rank1==
6821 23:07:56.652260 Dram Type= 6, Freq= 0, CH_1, rank 0
6822 23:07:56.658983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6823 23:07:56.659059 ==
6824 23:07:56.659124 DQS Delay:
6825 23:07:56.659186 DQS0 = 32, DQS1 = 40
6826 23:07:56.662195 DQM Delay:
6827 23:07:56.662265 DQM0 = 11, DQM1 = 11
6828 23:07:56.665828 DQ Delay:
6829 23:07:56.669035 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6830 23:07:56.669119 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6831 23:07:56.672326 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6832 23:07:56.675806 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6833 23:07:56.675889
6834 23:07:56.675956
6835 23:07:56.685426 [DQSOSCAuto] RK0, (LSB)MR18= 0x9dd7, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6836 23:07:56.688881 CH1 RK0: MR19=C0C, MR18=9DD7
6837 23:07:56.695419 CH1_RK0: MR19=0xC0C, MR18=0x9DD7, DQSOSC=383, MR23=63, INC=402, DEC=268
6838 23:07:56.695504 ==
6839 23:07:56.698912 Dram Type= 6, Freq= 0, CH_1, rank 1
6840 23:07:56.702190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 23:07:56.702277 ==
6842 23:07:56.705654 [Gating] SW mode calibration
6843 23:07:56.712312 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6844 23:07:56.715505 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6845 23:07:56.721893 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6846 23:07:56.725547 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6847 23:07:56.728863 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6848 23:07:56.735673 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6849 23:07:56.738771 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6850 23:07:56.742091 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6851 23:07:56.748907 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6852 23:07:56.752279 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6853 23:07:56.755174 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6854 23:07:56.758899 Total UI for P1: 0, mck2ui 16
6855 23:07:56.761799 best dqsien dly found for B0: ( 0, 14, 24)
6856 23:07:56.765225 Total UI for P1: 0, mck2ui 16
6857 23:07:56.768431 best dqsien dly found for B1: ( 0, 14, 24)
6858 23:07:56.772107 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6859 23:07:56.775359 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6860 23:07:56.778765
6861 23:07:56.782026 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6862 23:07:56.785478 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6863 23:07:56.788319 [Gating] SW calibration Done
6864 23:07:56.788403 ==
6865 23:07:56.791732 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 23:07:56.795302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 23:07:56.795386 ==
6868 23:07:56.795453 RX Vref Scan: 0
6869 23:07:56.795516
6870 23:07:56.798520 RX Vref 0 -> 0, step: 1
6871 23:07:56.798629
6872 23:07:56.801839 RX Delay -410 -> 252, step: 16
6873 23:07:56.805066 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6874 23:07:56.811866 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6875 23:07:56.815393 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6876 23:07:56.818686 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6877 23:07:56.821914 iDelay=230, Bit 4, Center -11 (-234 ~ 213) 448
6878 23:07:56.828625 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6879 23:07:56.831815 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6880 23:07:56.835011 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6881 23:07:56.838568 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6882 23:07:56.842038 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6883 23:07:56.848468 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6884 23:07:56.851795 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6885 23:07:56.855083 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6886 23:07:56.861837 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6887 23:07:56.865207 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6888 23:07:56.868576 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6889 23:07:56.868660 ==
6890 23:07:56.871932 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 23:07:56.875051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 23:07:56.875136 ==
6893 23:07:56.878357 DQS Delay:
6894 23:07:56.878441 DQS0 = 35, DQS1 = 43
6895 23:07:56.881664 DQM Delay:
6896 23:07:56.881748 DQM0 = 20, DQM1 = 21
6897 23:07:56.884933 DQ Delay:
6898 23:07:56.885016 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6899 23:07:56.888390 DQ4 =24, DQ5 =32, DQ6 =32, DQ7 =16
6900 23:07:56.891658 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6901 23:07:56.894999 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =40
6902 23:07:56.895083
6903 23:07:56.895149
6904 23:07:56.898609 ==
6905 23:07:56.898692 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 23:07:56.905050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 23:07:56.905134 ==
6908 23:07:56.905201
6909 23:07:56.905264
6910 23:07:56.908392 TX Vref Scan disable
6911 23:07:56.908476 == TX Byte 0 ==
6912 23:07:56.911848 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6913 23:07:56.915162 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6914 23:07:56.918218 == TX Byte 1 ==
6915 23:07:56.921550 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6916 23:07:56.924937 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6917 23:07:56.928501 ==
6918 23:07:56.928585 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 23:07:56.935176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 23:07:56.935260 ==
6921 23:07:56.935328
6922 23:07:56.935390
6923 23:07:56.938561 TX Vref Scan disable
6924 23:07:56.938646 == TX Byte 0 ==
6925 23:07:56.941422 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6926 23:07:56.948432 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6927 23:07:56.948516 == TX Byte 1 ==
6928 23:07:56.951641 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6929 23:07:56.954863 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6930 23:07:56.958147
6931 23:07:56.958230 [DATLAT]
6932 23:07:56.958297 Freq=400, CH1 RK1
6933 23:07:56.958360
6934 23:07:56.961462 DATLAT Default: 0xe
6935 23:07:56.961546 0, 0xFFFF, sum = 0
6936 23:07:56.964837 1, 0xFFFF, sum = 0
6937 23:07:56.964922 2, 0xFFFF, sum = 0
6938 23:07:56.968108 3, 0xFFFF, sum = 0
6939 23:07:56.968193 4, 0xFFFF, sum = 0
6940 23:07:56.971454 5, 0xFFFF, sum = 0
6941 23:07:56.974844 6, 0xFFFF, sum = 0
6942 23:07:56.974929 7, 0xFFFF, sum = 0
6943 23:07:56.977915 8, 0xFFFF, sum = 0
6944 23:07:56.978021 9, 0xFFFF, sum = 0
6945 23:07:56.981324 10, 0xFFFF, sum = 0
6946 23:07:56.981409 11, 0xFFFF, sum = 0
6947 23:07:56.985249 12, 0xFFFF, sum = 0
6948 23:07:56.985334 13, 0x0, sum = 1
6949 23:07:56.988098 14, 0x0, sum = 2
6950 23:07:56.988183 15, 0x0, sum = 3
6951 23:07:56.991477 16, 0x0, sum = 4
6952 23:07:56.991562 best_step = 14
6953 23:07:56.991629
6954 23:07:56.991692 ==
6955 23:07:56.994874 Dram Type= 6, Freq= 0, CH_1, rank 1
6956 23:07:56.998220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6957 23:07:56.998304 ==
6958 23:07:57.001817 RX Vref Scan: 0
6959 23:07:57.001900
6960 23:07:57.004895 RX Vref 0 -> 0, step: 1
6961 23:07:57.004979
6962 23:07:57.005046 RX Delay -327 -> 252, step: 8
6963 23:07:57.013489 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6964 23:07:57.016461 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6965 23:07:57.020053 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6966 23:07:57.023169 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6967 23:07:57.029910 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6968 23:07:57.033292 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6969 23:07:57.036460 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6970 23:07:57.040062 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6971 23:07:57.046449 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6972 23:07:57.049759 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6973 23:07:57.053032 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6974 23:07:57.056595 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6975 23:07:57.063176 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6976 23:07:57.066447 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6977 23:07:57.069664 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6978 23:07:57.076380 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6979 23:07:57.076463 ==
6980 23:07:57.079740 Dram Type= 6, Freq= 0, CH_1, rank 1
6981 23:07:57.082998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6982 23:07:57.083082 ==
6983 23:07:57.083150 DQS Delay:
6984 23:07:57.086424 DQS0 = 32, DQS1 = 36
6985 23:07:57.086507 DQM Delay:
6986 23:07:57.089732 DQM0 = 12, DQM1 = 11
6987 23:07:57.089815 DQ Delay:
6988 23:07:57.093032 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6989 23:07:57.096359 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =8
6990 23:07:57.099606 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6991 23:07:57.103020 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6992 23:07:57.103104
6993 23:07:57.103170
6994 23:07:57.109897 [DQSOSCAuto] RK1, (LSB)MR18= 0xad55, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6995 23:07:57.113245 CH1 RK1: MR19=C0C, MR18=AD55
6996 23:07:57.119639 CH1_RK1: MR19=0xC0C, MR18=0xAD55, DQSOSC=388, MR23=63, INC=392, DEC=261
6997 23:07:57.123199 [RxdqsGatingPostProcess] freq 400
6998 23:07:57.126519 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6999 23:07:57.129851 best DQS0 dly(2T, 0.5T) = (0, 10)
7000 23:07:57.132997 best DQS1 dly(2T, 0.5T) = (0, 10)
7001 23:07:57.136606 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7002 23:07:57.139772 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7003 23:07:57.142949 best DQS0 dly(2T, 0.5T) = (0, 10)
7004 23:07:57.146566 best DQS1 dly(2T, 0.5T) = (0, 10)
7005 23:07:57.149834 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7006 23:07:57.153033 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7007 23:07:57.156409 Pre-setting of DQS Precalculation
7008 23:07:57.159595 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7009 23:07:57.169925 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7010 23:07:57.176128 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7011 23:07:57.176212
7012 23:07:57.176278
7013 23:07:57.179502 [Calibration Summary] 800 Mbps
7014 23:07:57.179585 CH 0, Rank 0
7015 23:07:57.182876 SW Impedance : PASS
7016 23:07:57.182960 DUTY Scan : NO K
7017 23:07:57.186073 ZQ Calibration : PASS
7018 23:07:57.189877 Jitter Meter : NO K
7019 23:07:57.189998 CBT Training : PASS
7020 23:07:57.192688 Write leveling : PASS
7021 23:07:57.196465 RX DQS gating : PASS
7022 23:07:57.196549 RX DQ/DQS(RDDQC) : PASS
7023 23:07:57.199454 TX DQ/DQS : PASS
7024 23:07:57.203092 RX DATLAT : PASS
7025 23:07:57.203176 RX DQ/DQS(Engine): PASS
7026 23:07:57.206086 TX OE : NO K
7027 23:07:57.206170 All Pass.
7028 23:07:57.206238
7029 23:07:57.209722 CH 0, Rank 1
7030 23:07:57.209806 SW Impedance : PASS
7031 23:07:57.213019 DUTY Scan : NO K
7032 23:07:57.213103 ZQ Calibration : PASS
7033 23:07:57.216256 Jitter Meter : NO K
7034 23:07:57.219440 CBT Training : PASS
7035 23:07:57.219524 Write leveling : NO K
7036 23:07:57.223232 RX DQS gating : PASS
7037 23:07:57.226455 RX DQ/DQS(RDDQC) : PASS
7038 23:07:57.226539 TX DQ/DQS : PASS
7039 23:07:57.229683 RX DATLAT : PASS
7040 23:07:57.233124 RX DQ/DQS(Engine): PASS
7041 23:07:57.233208 TX OE : NO K
7042 23:07:57.236548 All Pass.
7043 23:07:57.236632
7044 23:07:57.236700 CH 1, Rank 0
7045 23:07:57.239453 SW Impedance : PASS
7046 23:07:57.239536 DUTY Scan : NO K
7047 23:07:57.242961 ZQ Calibration : PASS
7048 23:07:57.246449 Jitter Meter : NO K
7049 23:07:57.246533 CBT Training : PASS
7050 23:07:57.249550 Write leveling : PASS
7051 23:07:57.249633 RX DQS gating : PASS
7052 23:07:57.253188 RX DQ/DQS(RDDQC) : PASS
7053 23:07:57.256401 TX DQ/DQS : PASS
7054 23:07:57.256488 RX DATLAT : PASS
7055 23:07:57.259717 RX DQ/DQS(Engine): PASS
7056 23:07:57.262972 TX OE : NO K
7057 23:07:57.263080 All Pass.
7058 23:07:57.263160
7059 23:07:57.263223 CH 1, Rank 1
7060 23:07:57.266120 SW Impedance : PASS
7061 23:07:57.269512 DUTY Scan : NO K
7062 23:07:57.269595 ZQ Calibration : PASS
7063 23:07:57.272774 Jitter Meter : NO K
7064 23:07:57.276081 CBT Training : PASS
7065 23:07:57.276165 Write leveling : NO K
7066 23:07:57.279361 RX DQS gating : PASS
7067 23:07:57.283019 RX DQ/DQS(RDDQC) : PASS
7068 23:07:57.283105 TX DQ/DQS : PASS
7069 23:07:57.286403 RX DATLAT : PASS
7070 23:07:57.289613 RX DQ/DQS(Engine): PASS
7071 23:07:57.289698 TX OE : NO K
7072 23:07:57.289768 All Pass.
7073 23:07:57.292833
7074 23:07:57.292916 DramC Write-DBI off
7075 23:07:57.296126 PER_BANK_REFRESH: Hybrid Mode
7076 23:07:57.296209 TX_TRACKING: ON
7077 23:07:57.306137 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7078 23:07:57.309590 [FAST_K] Save calibration result to emmc
7079 23:07:57.312920 dramc_set_vcore_voltage set vcore to 725000
7080 23:07:57.316355 Read voltage for 1600, 0
7081 23:07:57.316442 Vio18 = 0
7082 23:07:57.319266 Vcore = 725000
7083 23:07:57.319350 Vdram = 0
7084 23:07:57.319418 Vddq = 0
7085 23:07:57.319481 Vmddr = 0
7086 23:07:57.326123 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7087 23:07:57.332604 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7088 23:07:57.332713 MEM_TYPE=3, freq_sel=13
7089 23:07:57.336292 sv_algorithm_assistance_LP4_3733
7090 23:07:57.339325 ============ PULL DRAM RESETB DOWN ============
7091 23:07:57.346162 ========== PULL DRAM RESETB DOWN end =========
7092 23:07:57.349115 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7093 23:07:57.352515 ===================================
7094 23:07:57.355789 LPDDR4 DRAM CONFIGURATION
7095 23:07:57.359383 ===================================
7096 23:07:57.359495 EX_ROW_EN[0] = 0x0
7097 23:07:57.362399 EX_ROW_EN[1] = 0x0
7098 23:07:57.362503 LP4Y_EN = 0x0
7099 23:07:57.365838 WORK_FSP = 0x1
7100 23:07:57.369001 WL = 0x5
7101 23:07:57.369103 RL = 0x5
7102 23:07:57.372318 BL = 0x2
7103 23:07:57.372423 RPST = 0x0
7104 23:07:57.375631 RD_PRE = 0x0
7105 23:07:57.375744 WR_PRE = 0x1
7106 23:07:57.378919 WR_PST = 0x1
7107 23:07:57.379026 DBI_WR = 0x0
7108 23:07:57.382257 DBI_RD = 0x0
7109 23:07:57.382340 OTF = 0x1
7110 23:07:57.385617 ===================================
7111 23:07:57.388950 ===================================
7112 23:07:57.392185 ANA top config
7113 23:07:57.395858 ===================================
7114 23:07:57.395969 DLL_ASYNC_EN = 0
7115 23:07:57.399118 ALL_SLAVE_EN = 0
7116 23:07:57.402467 NEW_RANK_MODE = 1
7117 23:07:57.405911 DLL_IDLE_MODE = 1
7118 23:07:57.406006 LP45_APHY_COMB_EN = 1
7119 23:07:57.409249 TX_ODT_DIS = 0
7120 23:07:57.412642 NEW_8X_MODE = 1
7121 23:07:57.415931 ===================================
7122 23:07:57.419161 ===================================
7123 23:07:57.422233 data_rate = 3200
7124 23:07:57.425581 CKR = 1
7125 23:07:57.429005 DQ_P2S_RATIO = 8
7126 23:07:57.432184 ===================================
7127 23:07:57.432295 CA_P2S_RATIO = 8
7128 23:07:57.435829 DQ_CA_OPEN = 0
7129 23:07:57.439192 DQ_SEMI_OPEN = 0
7130 23:07:57.442304 CA_SEMI_OPEN = 0
7131 23:07:57.445751 CA_FULL_RATE = 0
7132 23:07:57.445852 DQ_CKDIV4_EN = 0
7133 23:07:57.449056 CA_CKDIV4_EN = 0
7134 23:07:57.452646 CA_PREDIV_EN = 0
7135 23:07:57.455654 PH8_DLY = 12
7136 23:07:57.459438 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7137 23:07:57.462386 DQ_AAMCK_DIV = 4
7138 23:07:57.462469 CA_AAMCK_DIV = 4
7139 23:07:57.465771 CA_ADMCK_DIV = 4
7140 23:07:57.469318 DQ_TRACK_CA_EN = 0
7141 23:07:57.472592 CA_PICK = 1600
7142 23:07:57.475876 CA_MCKIO = 1600
7143 23:07:57.479272 MCKIO_SEMI = 0
7144 23:07:57.482497 PLL_FREQ = 3068
7145 23:07:57.485984 DQ_UI_PI_RATIO = 32
7146 23:07:57.486066 CA_UI_PI_RATIO = 0
7147 23:07:57.489032 ===================================
7148 23:07:57.492375 ===================================
7149 23:07:57.495521 memory_type:LPDDR4
7150 23:07:57.499165 GP_NUM : 10
7151 23:07:57.499247 SRAM_EN : 1
7152 23:07:57.502539 MD32_EN : 0
7153 23:07:57.505867 ===================================
7154 23:07:57.509163 [ANA_INIT] >>>>>>>>>>>>>>
7155 23:07:57.509245 <<<<<< [CONFIGURE PHASE]: ANA_TX
7156 23:07:57.515827 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7157 23:07:57.515909 ===================================
7158 23:07:57.519096 data_rate = 3200,PCW = 0X7600
7159 23:07:57.522264 ===================================
7160 23:07:57.526200 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7161 23:07:57.532595 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7162 23:07:57.538986 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7163 23:07:57.542764 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7164 23:07:57.545753 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7165 23:07:57.549052 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7166 23:07:57.552566 [ANA_INIT] flow start
7167 23:07:57.552648 [ANA_INIT] PLL >>>>>>>>
7168 23:07:57.555832 [ANA_INIT] PLL <<<<<<<<
7169 23:07:57.559171 [ANA_INIT] MIDPI >>>>>>>>
7170 23:07:57.559253 [ANA_INIT] MIDPI <<<<<<<<
7171 23:07:57.562419 [ANA_INIT] DLL >>>>>>>>
7172 23:07:57.565685 [ANA_INIT] DLL <<<<<<<<
7173 23:07:57.565797 [ANA_INIT] flow end
7174 23:07:57.572382 ============ LP4 DIFF to SE enter ============
7175 23:07:57.575947 ============ LP4 DIFF to SE exit ============
7176 23:07:57.579057 [ANA_INIT] <<<<<<<<<<<<<
7177 23:07:57.579139 [Flow] Enable top DCM control >>>>>
7178 23:07:57.582323 [Flow] Enable top DCM control <<<<<
7179 23:07:57.585636 Enable DLL master slave shuffle
7180 23:07:57.592482 ==============================================================
7181 23:07:57.595895 Gating Mode config
7182 23:07:57.599172 ==============================================================
7183 23:07:57.602432 Config description:
7184 23:07:57.612554 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7185 23:07:57.618913 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7186 23:07:57.622177 SELPH_MODE 0: By rank 1: By Phase
7187 23:07:57.629059 ==============================================================
7188 23:07:57.632361 GAT_TRACK_EN = 1
7189 23:07:57.635907 RX_GATING_MODE = 2
7190 23:07:57.639115 RX_GATING_TRACK_MODE = 2
7191 23:07:57.639197 SELPH_MODE = 1
7192 23:07:57.642517 PICG_EARLY_EN = 1
7193 23:07:57.645459 VALID_LAT_VALUE = 1
7194 23:07:57.652098 ==============================================================
7195 23:07:57.655526 Enter into Gating configuration >>>>
7196 23:07:57.659189 Exit from Gating configuration <<<<
7197 23:07:57.662140 Enter into DVFS_PRE_config >>>>>
7198 23:07:57.672173 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7199 23:07:57.675479 Exit from DVFS_PRE_config <<<<<
7200 23:07:57.679169 Enter into PICG configuration >>>>
7201 23:07:57.682543 Exit from PICG configuration <<<<
7202 23:07:57.685664 [RX_INPUT] configuration >>>>>
7203 23:07:57.689096 [RX_INPUT] configuration <<<<<
7204 23:07:57.692483 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7205 23:07:57.699147 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7206 23:07:57.705730 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7207 23:07:57.709536 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7208 23:07:57.715824 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7209 23:07:57.722518 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7210 23:07:57.725868 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7211 23:07:57.732511 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7212 23:07:57.735982 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7213 23:07:57.739090 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7214 23:07:57.742334 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7215 23:07:57.749031 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7216 23:07:57.752319 ===================================
7217 23:07:57.752403 LPDDR4 DRAM CONFIGURATION
7218 23:07:57.755619 ===================================
7219 23:07:57.759509 EX_ROW_EN[0] = 0x0
7220 23:07:57.762831 EX_ROW_EN[1] = 0x0
7221 23:07:57.762914 LP4Y_EN = 0x0
7222 23:07:57.765866 WORK_FSP = 0x1
7223 23:07:57.765970 WL = 0x5
7224 23:07:57.769019 RL = 0x5
7225 23:07:57.769102 BL = 0x2
7226 23:07:57.772706 RPST = 0x0
7227 23:07:57.772789 RD_PRE = 0x0
7228 23:07:57.775862 WR_PRE = 0x1
7229 23:07:57.775945 WR_PST = 0x1
7230 23:07:57.779225 DBI_WR = 0x0
7231 23:07:57.779308 DBI_RD = 0x0
7232 23:07:57.782285 OTF = 0x1
7233 23:07:57.785756 ===================================
7234 23:07:57.789308 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7235 23:07:57.792253 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7236 23:07:57.799144 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7237 23:07:57.799229 ===================================
7238 23:07:57.802383 LPDDR4 DRAM CONFIGURATION
7239 23:07:57.805881 ===================================
7240 23:07:57.808897 EX_ROW_EN[0] = 0x10
7241 23:07:57.808980 EX_ROW_EN[1] = 0x0
7242 23:07:57.812665 LP4Y_EN = 0x0
7243 23:07:57.812748 WORK_FSP = 0x1
7244 23:07:57.815566 WL = 0x5
7245 23:07:57.815649 RL = 0x5
7246 23:07:57.818839 BL = 0x2
7247 23:07:57.822098 RPST = 0x0
7248 23:07:57.822181 RD_PRE = 0x0
7249 23:07:57.825474 WR_PRE = 0x1
7250 23:07:57.825557 WR_PST = 0x1
7251 23:07:57.828703 DBI_WR = 0x0
7252 23:07:57.828787 DBI_RD = 0x0
7253 23:07:57.832458 OTF = 0x1
7254 23:07:57.835759 ===================================
7255 23:07:57.838901 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7256 23:07:57.842388 ==
7257 23:07:57.845680 Dram Type= 6, Freq= 0, CH_0, rank 0
7258 23:07:57.848983 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7259 23:07:57.849067 ==
7260 23:07:57.852306 [Duty_Offset_Calibration]
7261 23:07:57.852389 B0:2 B1:0 CA:1
7262 23:07:57.852456
7263 23:07:57.855671 [DutyScan_Calibration_Flow] k_type=0
7264 23:07:57.864504
7265 23:07:57.864588 ==CLK 0==
7266 23:07:57.868104 Final CLK duty delay cell = -4
7267 23:07:57.871597 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7268 23:07:57.874678 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7269 23:07:57.878154 [-4] AVG Duty = 4906%(X100)
7270 23:07:57.878238
7271 23:07:57.881157 CH0 CLK Duty spec in!! Max-Min= 187%
7272 23:07:57.884398 [DutyScan_Calibration_Flow] ====Done====
7273 23:07:57.884481
7274 23:07:57.887817 [DutyScan_Calibration_Flow] k_type=1
7275 23:07:57.904343
7276 23:07:57.904428 ==DQS 0 ==
7277 23:07:57.907222 Final DQS duty delay cell = 0
7278 23:07:57.910602 [0] MAX Duty = 5249%(X100), DQS PI = 32
7279 23:07:57.914223 [0] MIN Duty = 4969%(X100), DQS PI = 0
7280 23:07:57.914306 [0] AVG Duty = 5109%(X100)
7281 23:07:57.917496
7282 23:07:57.917596 ==DQS 1 ==
7283 23:07:57.920698 Final DQS duty delay cell = -4
7284 23:07:57.923914 [-4] MAX Duty = 5156%(X100), DQS PI = 46
7285 23:07:57.927354 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7286 23:07:57.930588 [-4] AVG Duty = 5000%(X100)
7287 23:07:57.930671
7288 23:07:57.934000 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7289 23:07:57.934113
7290 23:07:57.937248 CH0 DQS 1 Duty spec in!! Max-Min= 312%
7291 23:07:57.940533 [DutyScan_Calibration_Flow] ====Done====
7292 23:07:57.940646
7293 23:07:57.943811 [DutyScan_Calibration_Flow] k_type=3
7294 23:07:57.961783
7295 23:07:57.961866 ==DQM 0 ==
7296 23:07:57.964742 Final DQM duty delay cell = 0
7297 23:07:57.967995 [0] MAX Duty = 5093%(X100), DQS PI = 26
7298 23:07:57.971802 [0] MIN Duty = 4813%(X100), DQS PI = 50
7299 23:07:57.974745 [0] AVG Duty = 4953%(X100)
7300 23:07:57.974828
7301 23:07:57.974894 ==DQM 1 ==
7302 23:07:57.978200 Final DQM duty delay cell = 0
7303 23:07:57.981418 [0] MAX Duty = 5249%(X100), DQS PI = 30
7304 23:07:57.985073 [0] MIN Duty = 5000%(X100), DQS PI = 20
7305 23:07:57.987937 [0] AVG Duty = 5124%(X100)
7306 23:07:57.988048
7307 23:07:57.991421 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7308 23:07:57.991566
7309 23:07:57.994853 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7310 23:07:57.997956 [DutyScan_Calibration_Flow] ====Done====
7311 23:07:57.998052
7312 23:07:58.001652 [DutyScan_Calibration_Flow] k_type=2
7313 23:07:58.018840
7314 23:07:58.018951 ==DQ 0 ==
7315 23:07:58.022141 Final DQ duty delay cell = 0
7316 23:07:58.025342 [0] MAX Duty = 5156%(X100), DQS PI = 38
7317 23:07:58.028732 [0] MIN Duty = 5000%(X100), DQS PI = 0
7318 23:07:58.028815 [0] AVG Duty = 5078%(X100)
7319 23:07:58.032071
7320 23:07:58.032154 ==DQ 1 ==
7321 23:07:58.035391 Final DQ duty delay cell = 0
7322 23:07:58.038810 [0] MAX Duty = 4969%(X100), DQS PI = 28
7323 23:07:58.041770 [0] MIN Duty = 4875%(X100), DQS PI = 12
7324 23:07:58.041854 [0] AVG Duty = 4922%(X100)
7325 23:07:58.045248
7326 23:07:58.048502 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7327 23:07:58.048602
7328 23:07:58.051938 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7329 23:07:58.055457 [DutyScan_Calibration_Flow] ====Done====
7330 23:07:58.055539 ==
7331 23:07:58.058437 Dram Type= 6, Freq= 0, CH_1, rank 0
7332 23:07:58.061714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7333 23:07:58.061821 ==
7334 23:07:58.065043 [Duty_Offset_Calibration]
7335 23:07:58.065124 B0:0 B1:-1 CA:2
7336 23:07:58.065189
7337 23:07:58.068541 [DutyScan_Calibration_Flow] k_type=0
7338 23:07:58.078979
7339 23:07:58.079060 ==CLK 0==
7340 23:07:58.082405 Final CLK duty delay cell = 0
7341 23:07:58.085458 [0] MAX Duty = 5156%(X100), DQS PI = 10
7342 23:07:58.088798 [0] MIN Duty = 4906%(X100), DQS PI = 46
7343 23:07:58.088881 [0] AVG Duty = 5031%(X100)
7344 23:07:58.092189
7345 23:07:58.095456 CH1 CLK Duty spec in!! Max-Min= 250%
7346 23:07:58.098970 [DutyScan_Calibration_Flow] ====Done====
7347 23:07:58.099040
7348 23:07:58.102226 [DutyScan_Calibration_Flow] k_type=1
7349 23:07:58.118620
7350 23:07:58.118702 ==DQS 0 ==
7351 23:07:58.121893 Final DQS duty delay cell = 0
7352 23:07:58.125140 [0] MAX Duty = 5062%(X100), DQS PI = 22
7353 23:07:58.128452 [0] MIN Duty = 4969%(X100), DQS PI = 0
7354 23:07:58.131835 [0] AVG Duty = 5015%(X100)
7355 23:07:58.131906
7356 23:07:58.131967 ==DQS 1 ==
7357 23:07:58.135082 Final DQS duty delay cell = 0
7358 23:07:58.138492 [0] MAX Duty = 5187%(X100), DQS PI = 0
7359 23:07:58.141822 [0] MIN Duty = 4844%(X100), DQS PI = 32
7360 23:07:58.145023 [0] AVG Duty = 5015%(X100)
7361 23:07:58.145150
7362 23:07:58.148573 CH1 DQS 0 Duty spec in!! Max-Min= 93%
7363 23:07:58.148641
7364 23:07:58.151882 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7365 23:07:58.155288 [DutyScan_Calibration_Flow] ====Done====
7366 23:07:58.155354
7367 23:07:58.158566 [DutyScan_Calibration_Flow] k_type=3
7368 23:07:58.176326
7369 23:07:58.176393 ==DQM 0 ==
7370 23:07:58.179806 Final DQM duty delay cell = 4
7371 23:07:58.182972 [4] MAX Duty = 5125%(X100), DQS PI = 22
7372 23:07:58.186480 [4] MIN Duty = 5000%(X100), DQS PI = 30
7373 23:07:58.186554 [4] AVG Duty = 5062%(X100)
7374 23:07:58.189774
7375 23:07:58.189868 ==DQM 1 ==
7376 23:07:58.193124 Final DQM duty delay cell = 0
7377 23:07:58.196579 [0] MAX Duty = 5249%(X100), DQS PI = 60
7378 23:07:58.199494 [0] MIN Duty = 4844%(X100), DQS PI = 34
7379 23:07:58.199587 [0] AVG Duty = 5046%(X100)
7380 23:07:58.202952
7381 23:07:58.206512 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7382 23:07:58.206585
7383 23:07:58.209507 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7384 23:07:58.212871 [DutyScan_Calibration_Flow] ====Done====
7385 23:07:58.212947
7386 23:07:58.216365 [DutyScan_Calibration_Flow] k_type=2
7387 23:07:58.233121
7388 23:07:58.233198 ==DQ 0 ==
7389 23:07:58.236875 Final DQ duty delay cell = 0
7390 23:07:58.239739 [0] MAX Duty = 5093%(X100), DQS PI = 22
7391 23:07:58.242935 [0] MIN Duty = 4969%(X100), DQS PI = 46
7392 23:07:58.243007 [0] AVG Duty = 5031%(X100)
7393 23:07:58.246305
7394 23:07:58.246377 ==DQ 1 ==
7395 23:07:58.249768 Final DQ duty delay cell = 0
7396 23:07:58.253078 [0] MAX Duty = 5062%(X100), DQS PI = 2
7397 23:07:58.256458 [0] MIN Duty = 4813%(X100), DQS PI = 34
7398 23:07:58.256529 [0] AVG Duty = 4937%(X100)
7399 23:07:58.256590
7400 23:07:58.259796 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7401 23:07:58.263069
7402 23:07:58.266373 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7403 23:07:58.269646 [DutyScan_Calibration_Flow] ====Done====
7404 23:07:58.272971 nWR fixed to 30
7405 23:07:58.273042 [ModeRegInit_LP4] CH0 RK0
7406 23:07:58.276387 [ModeRegInit_LP4] CH0 RK1
7407 23:07:58.279786 [ModeRegInit_LP4] CH1 RK0
7408 23:07:58.282997 [ModeRegInit_LP4] CH1 RK1
7409 23:07:58.283069 match AC timing 5
7410 23:07:58.286477 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7411 23:07:58.292576 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7412 23:07:58.296016 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7413 23:07:58.302600 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7414 23:07:58.306044 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7415 23:07:58.306119 [MiockJmeterHQA]
7416 23:07:58.306183
7417 23:07:58.309147 [DramcMiockJmeter] u1RxGatingPI = 0
7418 23:07:58.312702 0 : 4363, 4138
7419 23:07:58.312778 4 : 4252, 4027
7420 23:07:58.315746 8 : 4252, 4027
7421 23:07:58.315821 12 : 4252, 4027
7422 23:07:58.315886 16 : 4253, 4027
7423 23:07:58.319040 20 : 4363, 4138
7424 23:07:58.319119 24 : 4252, 4027
7425 23:07:58.322627 28 : 4364, 4137
7426 23:07:58.322702 32 : 4253, 4026
7427 23:07:58.326222 36 : 4252, 4027
7428 23:07:58.326300 40 : 4252, 4027
7429 23:07:58.329191 44 : 4255, 4029
7430 23:07:58.329270 48 : 4363, 4138
7431 23:07:58.329335 52 : 4252, 4027
7432 23:07:58.332664 56 : 4360, 4138
7433 23:07:58.332740 60 : 4250, 4026
7434 23:07:58.335866 64 : 4250, 4027
7435 23:07:58.335941 68 : 4250, 4027
7436 23:07:58.338796 72 : 4361, 4138
7437 23:07:58.338868 76 : 4250, 4027
7438 23:07:58.342250 80 : 4361, 4138
7439 23:07:58.342317 84 : 4249, 4027
7440 23:07:58.342378 88 : 4250, 3549
7441 23:07:58.345663 92 : 4250, 0
7442 23:07:58.345733 96 : 4361, 0
7443 23:07:58.348986 100 : 4252, 0
7444 23:07:58.349054 104 : 4253, 0
7445 23:07:58.349114 108 : 4361, 0
7446 23:07:58.352028 112 : 4250, 0
7447 23:07:58.352098 116 : 4250, 0
7448 23:07:58.352158 120 : 4250, 0
7449 23:07:58.355389 124 : 4361, 0
7450 23:07:58.355455 128 : 4361, 0
7451 23:07:58.358855 132 : 4250, 0
7452 23:07:58.358923 136 : 4250, 0
7453 23:07:58.358986 140 : 4363, 0
7454 23:07:58.362079 144 : 4250, 0
7455 23:07:58.362147 148 : 4250, 0
7456 23:07:58.365415 152 : 4250, 0
7457 23:07:58.365481 156 : 4252, 0
7458 23:07:58.365540 160 : 4361, 0
7459 23:07:58.368703 164 : 4250, 0
7460 23:07:58.368769 168 : 4250, 0
7461 23:07:58.372038 172 : 4250, 0
7462 23:07:58.372103 176 : 4361, 0
7463 23:07:58.372163 180 : 4361, 0
7464 23:07:58.375345 184 : 4250, 0
7465 23:07:58.375410 188 : 4250, 0
7466 23:07:58.375470 192 : 4250, 0
7467 23:07:58.378986 196 : 4252, 0
7468 23:07:58.379056 200 : 4250, 0
7469 23:07:58.382226 204 : 4250, 2133
7470 23:07:58.382302 208 : 4253, 4029
7471 23:07:58.385423 212 : 4361, 4138
7472 23:07:58.385490 216 : 4250, 4027
7473 23:07:58.388865 220 : 4250, 4027
7474 23:07:58.388935 224 : 4361, 4137
7475 23:07:58.392138 228 : 4361, 4137
7476 23:07:58.392205 232 : 4250, 4027
7477 23:07:58.392265 236 : 4363, 4140
7478 23:07:58.395452 240 : 4250, 4027
7479 23:07:58.395518 244 : 4250, 4027
7480 23:07:58.398812 248 : 4250, 4027
7481 23:07:58.398882 252 : 4252, 4029
7482 23:07:58.402000 256 : 4250, 4027
7483 23:07:58.402077 260 : 4252, 4026
7484 23:07:58.405267 264 : 4250, 4027
7485 23:07:58.405337 268 : 4252, 4029
7486 23:07:58.408487 272 : 4250, 4027
7487 23:07:58.408562 276 : 4361, 4137
7488 23:07:58.412062 280 : 4361, 4138
7489 23:07:58.412132 284 : 4250, 4027
7490 23:07:58.415222 288 : 4363, 4140
7491 23:07:58.415296 292 : 4250, 4027
7492 23:07:58.415356 296 : 4250, 4026
7493 23:07:58.418354 300 : 4250, 4027
7494 23:07:58.418425 304 : 4252, 4029
7495 23:07:58.421883 308 : 4250, 4027
7496 23:07:58.422010 312 : 4250, 4010
7497 23:07:58.424955 316 : 4250, 2378
7498 23:07:58.425034 320 : 4252, 36
7499 23:07:58.425096
7500 23:07:58.428440 MIOCK jitter meter ch=0
7501 23:07:58.428509
7502 23:07:58.431819 1T = (320-92) = 228 dly cells
7503 23:07:58.438569 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7504 23:07:58.438645 ==
7505 23:07:58.441733 Dram Type= 6, Freq= 0, CH_0, rank 0
7506 23:07:58.445259 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7507 23:07:58.445361 ==
7508 23:07:58.448543 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7509 23:07:58.455046 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7510 23:07:58.458316 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7511 23:07:58.464864 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7512 23:07:58.473251 [CA 0] Center 42 (12~73) winsize 62
7513 23:07:58.476510 [CA 1] Center 43 (13~73) winsize 61
7514 23:07:58.479878 [CA 2] Center 38 (8~68) winsize 61
7515 23:07:58.483180 [CA 3] Center 37 (8~67) winsize 60
7516 23:07:58.486759 [CA 4] Center 36 (6~66) winsize 61
7517 23:07:58.489889 [CA 5] Center 35 (5~65) winsize 61
7518 23:07:58.489983
7519 23:07:58.493248 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7520 23:07:58.493318
7521 23:07:58.496550 [CATrainingPosCal] consider 1 rank data
7522 23:07:58.499870 u2DelayCellTimex100 = 285/100 ps
7523 23:07:58.503129 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7524 23:07:58.510048 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7525 23:07:58.513652 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7526 23:07:58.516710 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7527 23:07:58.519929 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7528 23:07:58.523124 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7529 23:07:58.523223
7530 23:07:58.526465 CA PerBit enable=1, Macro0, CA PI delay=35
7531 23:07:58.526535
7532 23:07:58.530246 [CBTSetCACLKResult] CA Dly = 35
7533 23:07:58.533048 CS Dly: 9 (0~40)
7534 23:07:58.536547 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7535 23:07:58.539875 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7536 23:07:58.539946 ==
7537 23:07:58.543004 Dram Type= 6, Freq= 0, CH_0, rank 1
7538 23:07:58.546444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 23:07:58.546523 ==
7540 23:07:58.553242 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7541 23:07:58.556457 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7542 23:07:58.563282 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7543 23:07:58.566578 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7544 23:07:58.577045 [CA 0] Center 43 (13~73) winsize 61
7545 23:07:58.579819 [CA 1] Center 43 (13~73) winsize 61
7546 23:07:58.583503 [CA 2] Center 37 (8~67) winsize 60
7547 23:07:58.586797 [CA 3] Center 38 (9~68) winsize 60
7548 23:07:58.589899 [CA 4] Center 36 (6~67) winsize 62
7549 23:07:58.593347 [CA 5] Center 36 (6~66) winsize 61
7550 23:07:58.593422
7551 23:07:58.596767 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7552 23:07:58.596836
7553 23:07:58.599804 [CATrainingPosCal] consider 2 rank data
7554 23:07:58.603128 u2DelayCellTimex100 = 285/100 ps
7555 23:07:58.609855 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7556 23:07:58.612860 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7557 23:07:58.616175 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7558 23:07:58.619931 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7559 23:07:58.623116 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7560 23:07:58.626411 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7561 23:07:58.626487
7562 23:07:58.629738 CA PerBit enable=1, Macro0, CA PI delay=35
7563 23:07:58.629811
7564 23:07:58.632885 [CBTSetCACLKResult] CA Dly = 35
7565 23:07:58.636284 CS Dly: 10 (0~43)
7566 23:07:58.639781 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7567 23:07:58.642943 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7568 23:07:58.643017
7569 23:07:58.646224 ----->DramcWriteLeveling(PI) begin...
7570 23:07:58.646302 ==
7571 23:07:58.649430 Dram Type= 6, Freq= 0, CH_0, rank 0
7572 23:07:58.656094 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 23:07:58.656173 ==
7574 23:07:58.659546 Write leveling (Byte 0): 37 => 37
7575 23:07:58.659620 Write leveling (Byte 1): 31 => 31
7576 23:07:58.662877 DramcWriteLeveling(PI) end<-----
7577 23:07:58.662946
7578 23:07:58.666472 ==
7579 23:07:58.666541 Dram Type= 6, Freq= 0, CH_0, rank 0
7580 23:07:58.672871 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7581 23:07:58.672947 ==
7582 23:07:58.676207 [Gating] SW mode calibration
7583 23:07:58.682762 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7584 23:07:58.686398 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7585 23:07:58.692420 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 23:07:58.696149 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 23:07:58.699456 1 4 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7588 23:07:58.705959 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7589 23:07:58.709308 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7590 23:07:58.712559 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 23:07:58.719333 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 23:07:58.722813 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 23:07:58.726000 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 23:07:58.732767 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 23:07:58.735762 1 5 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
7596 23:07:58.738940 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7597 23:07:58.745829 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7598 23:07:58.749005 1 5 20 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
7599 23:07:58.752497 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 23:07:58.758880 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 23:07:58.762376 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 23:07:58.765343 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7603 23:07:58.772049 1 6 8 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7604 23:07:58.775474 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7605 23:07:58.778800 1 6 16 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7606 23:07:58.782028 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 23:07:58.788660 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 23:07:58.791940 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 23:07:58.795612 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 23:07:58.802139 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 23:07:58.805295 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 23:07:58.808702 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7613 23:07:58.815232 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7614 23:07:58.818748 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7615 23:07:58.822046 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 23:07:58.828664 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 23:07:58.831758 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 23:07:58.835048 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 23:07:58.842057 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 23:07:58.845314 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 23:07:58.848767 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 23:07:58.855252 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 23:07:58.858742 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 23:07:58.861923 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 23:07:58.868656 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 23:07:58.871975 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 23:07:58.875061 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7628 23:07:58.881908 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7629 23:07:58.882014 Total UI for P1: 0, mck2ui 16
7630 23:07:58.888628 best dqsien dly found for B0: ( 1, 9, 8)
7631 23:07:58.891877 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7632 23:07:58.895118 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7633 23:07:58.898495 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7634 23:07:58.905488 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 23:07:58.908560 Total UI for P1: 0, mck2ui 16
7636 23:07:58.911891 best dqsien dly found for B1: ( 1, 9, 22)
7637 23:07:58.915121 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7638 23:07:58.918515 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7639 23:07:58.918599
7640 23:07:58.921584 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7641 23:07:58.924836 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7642 23:07:58.928567 [Gating] SW calibration Done
7643 23:07:58.928651 ==
7644 23:07:58.931885 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 23:07:58.934948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 23:07:58.935033 ==
7647 23:07:58.938313 RX Vref Scan: 0
7648 23:07:58.938397
7649 23:07:58.941605 RX Vref 0 -> 0, step: 1
7650 23:07:58.941688
7651 23:07:58.941756 RX Delay 0 -> 252, step: 8
7652 23:07:58.948182 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7653 23:07:58.951415 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7654 23:07:58.954677 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7655 23:07:58.958514 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7656 23:07:58.961653 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7657 23:07:58.964771 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7658 23:07:58.971574 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7659 23:07:58.974823 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7660 23:07:58.977889 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7661 23:07:58.981353 iDelay=200, Bit 9, Center 111 (64 ~ 159) 96
7662 23:07:58.984623 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7663 23:07:58.991393 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7664 23:07:58.994641 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7665 23:07:58.997897 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7666 23:07:59.001322 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7667 23:07:59.004933 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7668 23:07:59.008232 ==
7669 23:07:59.011507 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 23:07:59.014721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 23:07:59.014796 ==
7672 23:07:59.014867 DQS Delay:
7673 23:07:59.018044 DQS0 = 0, DQS1 = 0
7674 23:07:59.018118 DQM Delay:
7675 23:07:59.021434 DQM0 = 138, DQM1 = 126
7676 23:07:59.021506 DQ Delay:
7677 23:07:59.024701 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7678 23:07:59.027911 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7679 23:07:59.031533 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
7680 23:07:59.034820 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7681 23:07:59.034896
7682 23:07:59.034959
7683 23:07:59.035018 ==
7684 23:07:59.038012 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 23:07:59.044548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 23:07:59.044659 ==
7687 23:07:59.044754
7688 23:07:59.044849
7689 23:07:59.044938 TX Vref Scan disable
7690 23:07:59.048273 == TX Byte 0 ==
7691 23:07:59.051435 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7692 23:07:59.058454 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7693 23:07:59.058535 == TX Byte 1 ==
7694 23:07:59.061359 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7695 23:07:59.067994 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7696 23:07:59.068078 ==
7697 23:07:59.071620 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 23:07:59.074738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 23:07:59.074811 ==
7700 23:07:59.088712
7701 23:07:59.092163 TX Vref early break, caculate TX vref
7702 23:07:59.095380 TX Vref=16, minBit 0, minWin=23, winSum=378
7703 23:07:59.098746 TX Vref=18, minBit 6, minWin=23, winSum=386
7704 23:07:59.102012 TX Vref=20, minBit 12, minWin=23, winSum=396
7705 23:07:59.105373 TX Vref=22, minBit 2, minWin=24, winSum=408
7706 23:07:59.108684 TX Vref=24, minBit 0, minWin=25, winSum=418
7707 23:07:59.115361 TX Vref=26, minBit 4, minWin=25, winSum=422
7708 23:07:59.118558 TX Vref=28, minBit 0, minWin=26, winSum=425
7709 23:07:59.121989 TX Vref=30, minBit 0, minWin=26, winSum=423
7710 23:07:59.124857 TX Vref=32, minBit 0, minWin=25, winSum=414
7711 23:07:59.128522 TX Vref=34, minBit 7, minWin=24, winSum=404
7712 23:07:59.131866 TX Vref=36, minBit 0, minWin=24, winSum=390
7713 23:07:59.138444 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
7714 23:07:59.138521
7715 23:07:59.141341 Final TX Range 0 Vref 28
7716 23:07:59.141440
7717 23:07:59.141529 ==
7718 23:07:59.144930 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 23:07:59.148350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 23:07:59.148427 ==
7721 23:07:59.151586
7722 23:07:59.151664
7723 23:07:59.151727 TX Vref Scan disable
7724 23:07:59.157953 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7725 23:07:59.158033 == TX Byte 0 ==
7726 23:07:59.161249 u2DelayCellOfst[0]=10 cells (3 PI)
7727 23:07:59.164600 u2DelayCellOfst[1]=13 cells (4 PI)
7728 23:07:59.167926 u2DelayCellOfst[2]=10 cells (3 PI)
7729 23:07:59.171234 u2DelayCellOfst[3]=10 cells (3 PI)
7730 23:07:59.175007 u2DelayCellOfst[4]=6 cells (2 PI)
7731 23:07:59.177976 u2DelayCellOfst[5]=0 cells (0 PI)
7732 23:07:59.181219 u2DelayCellOfst[6]=17 cells (5 PI)
7733 23:07:59.184857 u2DelayCellOfst[7]=13 cells (4 PI)
7734 23:07:59.188064 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7735 23:07:59.191558 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7736 23:07:59.194445 == TX Byte 1 ==
7737 23:07:59.197662 u2DelayCellOfst[8]=0 cells (0 PI)
7738 23:07:59.200943 u2DelayCellOfst[9]=0 cells (0 PI)
7739 23:07:59.204561 u2DelayCellOfst[10]=6 cells (2 PI)
7740 23:07:59.207885 u2DelayCellOfst[11]=3 cells (1 PI)
7741 23:07:59.210775 u2DelayCellOfst[12]=13 cells (4 PI)
7742 23:07:59.210849 u2DelayCellOfst[13]=13 cells (4 PI)
7743 23:07:59.214247 u2DelayCellOfst[14]=13 cells (4 PI)
7744 23:07:59.217821 u2DelayCellOfst[15]=10 cells (3 PI)
7745 23:07:59.224516 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7746 23:07:59.227815 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7747 23:07:59.227918 DramC Write-DBI on
7748 23:07:59.230673 ==
7749 23:07:59.233818 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 23:07:59.237690 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 23:07:59.237788 ==
7752 23:07:59.237881
7753 23:07:59.238026
7754 23:07:59.240847 TX Vref Scan disable
7755 23:07:59.240943 == TX Byte 0 ==
7756 23:07:59.247417 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7757 23:07:59.247502 == TX Byte 1 ==
7758 23:07:59.250617 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7759 23:07:59.254304 DramC Write-DBI off
7760 23:07:59.254376
7761 23:07:59.254438 [DATLAT]
7762 23:07:59.257442 Freq=1600, CH0 RK0
7763 23:07:59.257542
7764 23:07:59.257632 DATLAT Default: 0xf
7765 23:07:59.260750 0, 0xFFFF, sum = 0
7766 23:07:59.260848 1, 0xFFFF, sum = 0
7767 23:07:59.264158 2, 0xFFFF, sum = 0
7768 23:07:59.264254 3, 0xFFFF, sum = 0
7769 23:07:59.267444 4, 0xFFFF, sum = 0
7770 23:07:59.267523 5, 0xFFFF, sum = 0
7771 23:07:59.270429 6, 0xFFFF, sum = 0
7772 23:07:59.274098 7, 0xFFFF, sum = 0
7773 23:07:59.274177 8, 0xFFFF, sum = 0
7774 23:07:59.277207 9, 0xFFFF, sum = 0
7775 23:07:59.277315 10, 0xFFFF, sum = 0
7776 23:07:59.280420 11, 0xFFFF, sum = 0
7777 23:07:59.280523 12, 0xFFFF, sum = 0
7778 23:07:59.284103 13, 0xFFFF, sum = 0
7779 23:07:59.284208 14, 0x0, sum = 1
7780 23:07:59.287739 15, 0x0, sum = 2
7781 23:07:59.287848 16, 0x0, sum = 3
7782 23:07:59.290680 17, 0x0, sum = 4
7783 23:07:59.290757 best_step = 15
7784 23:07:59.290823
7785 23:07:59.290883 ==
7786 23:07:59.294076 Dram Type= 6, Freq= 0, CH_0, rank 0
7787 23:07:59.297085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7788 23:07:59.297185 ==
7789 23:07:59.300614 RX Vref Scan: 1
7790 23:07:59.300714
7791 23:07:59.303616 Set Vref Range= 24 -> 127
7792 23:07:59.303716
7793 23:07:59.303807 RX Vref 24 -> 127, step: 1
7794 23:07:59.303916
7795 23:07:59.307051 RX Delay 19 -> 252, step: 4
7796 23:07:59.307146
7797 23:07:59.310721 Set Vref, RX VrefLevel [Byte0]: 24
7798 23:07:59.314030 [Byte1]: 24
7799 23:07:59.317300
7800 23:07:59.317381 Set Vref, RX VrefLevel [Byte0]: 25
7801 23:07:59.320782 [Byte1]: 25
7802 23:07:59.324935
7803 23:07:59.325018 Set Vref, RX VrefLevel [Byte0]: 26
7804 23:07:59.328292 [Byte1]: 26
7805 23:07:59.332586
7806 23:07:59.332668 Set Vref, RX VrefLevel [Byte0]: 27
7807 23:07:59.335727 [Byte1]: 27
7808 23:07:59.339894
7809 23:07:59.339980 Set Vref, RX VrefLevel [Byte0]: 28
7810 23:07:59.343074 [Byte1]: 28
7811 23:07:59.347383
7812 23:07:59.347465 Set Vref, RX VrefLevel [Byte0]: 29
7813 23:07:59.350989 [Byte1]: 29
7814 23:07:59.355075
7815 23:07:59.358315 Set Vref, RX VrefLevel [Byte0]: 30
7816 23:07:59.361460 [Byte1]: 30
7817 23:07:59.361542
7818 23:07:59.365105 Set Vref, RX VrefLevel [Byte0]: 31
7819 23:07:59.368402 [Byte1]: 31
7820 23:07:59.368495
7821 23:07:59.371643 Set Vref, RX VrefLevel [Byte0]: 32
7822 23:07:59.374851 [Byte1]: 32
7823 23:07:59.374926
7824 23:07:59.378193 Set Vref, RX VrefLevel [Byte0]: 33
7825 23:07:59.381804 [Byte1]: 33
7826 23:07:59.385179
7827 23:07:59.385276 Set Vref, RX VrefLevel [Byte0]: 34
7828 23:07:59.388531 [Byte1]: 34
7829 23:07:59.393277
7830 23:07:59.393360 Set Vref, RX VrefLevel [Byte0]: 35
7831 23:07:59.396316 [Byte1]: 35
7832 23:07:59.400462
7833 23:07:59.400545 Set Vref, RX VrefLevel [Byte0]: 36
7834 23:07:59.403886 [Byte1]: 36
7835 23:07:59.408071
7836 23:07:59.408171 Set Vref, RX VrefLevel [Byte0]: 37
7837 23:07:59.411517 [Byte1]: 37
7838 23:07:59.415679
7839 23:07:59.415780 Set Vref, RX VrefLevel [Byte0]: 38
7840 23:07:59.419038 [Byte1]: 38
7841 23:07:59.423240
7842 23:07:59.423312 Set Vref, RX VrefLevel [Byte0]: 39
7843 23:07:59.426406 [Byte1]: 39
7844 23:07:59.431065
7845 23:07:59.431147 Set Vref, RX VrefLevel [Byte0]: 40
7846 23:07:59.434307 [Byte1]: 40
7847 23:07:59.438169
7848 23:07:59.438268 Set Vref, RX VrefLevel [Byte0]: 41
7849 23:07:59.441577 [Byte1]: 41
7850 23:07:59.446046
7851 23:07:59.446119 Set Vref, RX VrefLevel [Byte0]: 42
7852 23:07:59.449497 [Byte1]: 42
7853 23:07:59.453645
7854 23:07:59.453771 Set Vref, RX VrefLevel [Byte0]: 43
7855 23:07:59.456855 [Byte1]: 43
7856 23:07:59.460984
7857 23:07:59.461080 Set Vref, RX VrefLevel [Byte0]: 44
7858 23:07:59.464336 [Byte1]: 44
7859 23:07:59.468532
7860 23:07:59.468629 Set Vref, RX VrefLevel [Byte0]: 45
7861 23:07:59.471885 [Byte1]: 45
7862 23:07:59.476078
7863 23:07:59.476146 Set Vref, RX VrefLevel [Byte0]: 46
7864 23:07:59.479457 [Byte1]: 46
7865 23:07:59.483753
7866 23:07:59.483835 Set Vref, RX VrefLevel [Byte0]: 47
7867 23:07:59.487009 [Byte1]: 47
7868 23:07:59.491312
7869 23:07:59.491394 Set Vref, RX VrefLevel [Byte0]: 48
7870 23:07:59.494863 [Byte1]: 48
7871 23:07:59.498952
7872 23:07:59.499034 Set Vref, RX VrefLevel [Byte0]: 49
7873 23:07:59.502246 [Byte1]: 49
7874 23:07:59.506513
7875 23:07:59.506596 Set Vref, RX VrefLevel [Byte0]: 50
7876 23:07:59.509767 [Byte1]: 50
7877 23:07:59.514102
7878 23:07:59.514202 Set Vref, RX VrefLevel [Byte0]: 51
7879 23:07:59.517241 [Byte1]: 51
7880 23:07:59.521664
7881 23:07:59.521746 Set Vref, RX VrefLevel [Byte0]: 52
7882 23:07:59.524933 [Byte1]: 52
7883 23:07:59.529371
7884 23:07:59.529453 Set Vref, RX VrefLevel [Byte0]: 53
7885 23:07:59.532698 [Byte1]: 53
7886 23:07:59.537026
7887 23:07:59.537109 Set Vref, RX VrefLevel [Byte0]: 54
7888 23:07:59.540363 [Byte1]: 54
7889 23:07:59.544574
7890 23:07:59.544656 Set Vref, RX VrefLevel [Byte0]: 55
7891 23:07:59.547673 [Byte1]: 55
7892 23:07:59.551808
7893 23:07:59.551911 Set Vref, RX VrefLevel [Byte0]: 56
7894 23:07:59.555521 [Byte1]: 56
7895 23:07:59.559742
7896 23:07:59.559815 Set Vref, RX VrefLevel [Byte0]: 57
7897 23:07:59.562999 [Byte1]: 57
7898 23:07:59.567213
7899 23:07:59.567287 Set Vref, RX VrefLevel [Byte0]: 58
7900 23:07:59.570398 [Byte1]: 58
7901 23:07:59.574699
7902 23:07:59.574769 Set Vref, RX VrefLevel [Byte0]: 59
7903 23:07:59.578010 [Byte1]: 59
7904 23:07:59.582332
7905 23:07:59.582398 Set Vref, RX VrefLevel [Byte0]: 60
7906 23:07:59.585896 [Byte1]: 60
7907 23:07:59.590091
7908 23:07:59.590165 Set Vref, RX VrefLevel [Byte0]: 61
7909 23:07:59.593328 [Byte1]: 61
7910 23:07:59.597795
7911 23:07:59.597877 Set Vref, RX VrefLevel [Byte0]: 62
7912 23:07:59.600893 [Byte1]: 62
7913 23:07:59.605186
7914 23:07:59.605269 Set Vref, RX VrefLevel [Byte0]: 63
7915 23:07:59.608558 [Byte1]: 63
7916 23:07:59.612757
7917 23:07:59.612840 Set Vref, RX VrefLevel [Byte0]: 64
7918 23:07:59.615827 [Byte1]: 64
7919 23:07:59.620294
7920 23:07:59.620377 Set Vref, RX VrefLevel [Byte0]: 65
7921 23:07:59.623577 [Byte1]: 65
7922 23:07:59.627521
7923 23:07:59.627603 Set Vref, RX VrefLevel [Byte0]: 66
7924 23:07:59.630969 [Byte1]: 66
7925 23:07:59.635110
7926 23:07:59.635192 Set Vref, RX VrefLevel [Byte0]: 67
7927 23:07:59.638475 [Byte1]: 67
7928 23:07:59.642639
7929 23:07:59.642722 Set Vref, RX VrefLevel [Byte0]: 68
7930 23:07:59.646003 [Byte1]: 68
7931 23:07:59.650585
7932 23:07:59.650668 Set Vref, RX VrefLevel [Byte0]: 69
7933 23:07:59.653686 [Byte1]: 69
7934 23:07:59.657800
7935 23:07:59.657883 Set Vref, RX VrefLevel [Byte0]: 70
7936 23:07:59.661074 [Byte1]: 70
7937 23:07:59.665497
7938 23:07:59.665580 Set Vref, RX VrefLevel [Byte0]: 71
7939 23:07:59.668750 [Byte1]: 71
7940 23:07:59.672979
7941 23:07:59.673062 Set Vref, RX VrefLevel [Byte0]: 72
7942 23:07:59.676242 [Byte1]: 72
7943 23:07:59.680507
7944 23:07:59.680606 Set Vref, RX VrefLevel [Byte0]: 73
7945 23:07:59.683832 [Byte1]: 73
7946 23:07:59.688125
7947 23:07:59.688208 Set Vref, RX VrefLevel [Byte0]: 74
7948 23:07:59.691716 [Byte1]: 74
7949 23:07:59.695901
7950 23:07:59.695984 Set Vref, RX VrefLevel [Byte0]: 75
7951 23:07:59.699271 [Byte1]: 75
7952 23:07:59.703505
7953 23:07:59.703589 Set Vref, RX VrefLevel [Byte0]: 76
7954 23:07:59.706813 [Byte1]: 76
7955 23:07:59.711186
7956 23:07:59.711303 Set Vref, RX VrefLevel [Byte0]: 77
7957 23:07:59.714537 [Byte1]: 77
7958 23:07:59.718804
7959 23:07:59.718900 Set Vref, RX VrefLevel [Byte0]: 78
7960 23:07:59.721914 [Byte1]: 78
7961 23:07:59.726295
7962 23:07:59.726379 Set Vref, RX VrefLevel [Byte0]: 79
7963 23:07:59.729729 [Byte1]: 79
7964 23:07:59.733855
7965 23:07:59.733945 Final RX Vref Byte 0 = 63 to rank0
7966 23:07:59.737124 Final RX Vref Byte 1 = 62 to rank0
7967 23:07:59.740106 Final RX Vref Byte 0 = 63 to rank1
7968 23:07:59.743494 Final RX Vref Byte 1 = 62 to rank1==
7969 23:07:59.746806 Dram Type= 6, Freq= 0, CH_0, rank 0
7970 23:07:59.753396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7971 23:07:59.753481 ==
7972 23:07:59.753548 DQS Delay:
7973 23:07:59.756766 DQS0 = 0, DQS1 = 0
7974 23:07:59.756849 DQM Delay:
7975 23:07:59.756917 DQM0 = 136, DQM1 = 124
7976 23:07:59.760274 DQ Delay:
7977 23:07:59.763670 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
7978 23:07:59.766486 DQ4 =138, DQ5 =126, DQ6 =144, DQ7 =142
7979 23:07:59.770161 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
7980 23:07:59.773517 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =132
7981 23:07:59.773601
7982 23:07:59.773667
7983 23:07:59.773727
7984 23:07:59.776739 [DramC_TX_OE_Calibration] TA2
7985 23:07:59.779986 Original DQ_B0 (3 6) =30, OEN = 27
7986 23:07:59.783261 Original DQ_B1 (3 6) =30, OEN = 27
7987 23:07:59.786517 24, 0x0, End_B0=24 End_B1=24
7988 23:07:59.786601 25, 0x0, End_B0=25 End_B1=25
7989 23:07:59.789896 26, 0x0, End_B0=26 End_B1=26
7990 23:07:59.793335 27, 0x0, End_B0=27 End_B1=27
7991 23:07:59.796798 28, 0x0, End_B0=28 End_B1=28
7992 23:07:59.800019 29, 0x0, End_B0=29 End_B1=29
7993 23:07:59.800104 30, 0x0, End_B0=30 End_B1=30
7994 23:07:59.803606 31, 0x4141, End_B0=30 End_B1=30
7995 23:07:59.806420 Byte0 end_step=30 best_step=27
7996 23:07:59.809768 Byte1 end_step=30 best_step=27
7997 23:07:59.813398 Byte0 TX OE(2T, 0.5T) = (3, 3)
7998 23:07:59.816896 Byte1 TX OE(2T, 0.5T) = (3, 3)
7999 23:07:59.816980
8000 23:07:59.817047
8001 23:07:59.823469 [DQSOSCAuto] RK0, (LSB)MR18= 0x201e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
8002 23:07:59.826628 CH0 RK0: MR19=303, MR18=201E
8003 23:07:59.833094 CH0_RK0: MR19=0x303, MR18=0x201E, DQSOSC=393, MR23=63, INC=23, DEC=15
8004 23:07:59.833178
8005 23:07:59.836612 ----->DramcWriteLeveling(PI) begin...
8006 23:07:59.836698 ==
8007 23:07:59.839965 Dram Type= 6, Freq= 0, CH_0, rank 1
8008 23:07:59.843015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8009 23:07:59.843100 ==
8010 23:07:59.846551 Write leveling (Byte 0): 37 => 37
8011 23:07:59.849695 Write leveling (Byte 1): 31 => 31
8012 23:07:59.852985 DramcWriteLeveling(PI) end<-----
8013 23:07:59.853069
8014 23:07:59.853137 ==
8015 23:07:59.856384 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 23:07:59.859758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 23:07:59.859846 ==
8018 23:07:59.862918 [Gating] SW mode calibration
8019 23:07:59.869666 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8020 23:07:59.876017 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8021 23:07:59.879739 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 23:07:59.886257 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 23:07:59.889602 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 23:07:59.892888 1 4 12 | B1->B0 | 2a2a 3232 | 1 1 | (0 0) (1 1)
8025 23:07:59.896279 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 23:07:59.902739 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 23:07:59.905874 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 23:07:59.909275 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8029 23:07:59.915885 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8030 23:07:59.919202 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8031 23:07:59.922645 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8032 23:07:59.929182 1 5 12 | B1->B0 | 3434 2929 | 1 1 | (0 1) (1 0)
8033 23:07:59.932761 1 5 16 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
8034 23:07:59.935733 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 23:07:59.942509 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 23:07:59.945836 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 23:07:59.949401 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8038 23:07:59.956048 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 23:07:59.959419 1 6 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
8040 23:07:59.962869 1 6 12 | B1->B0 | 3434 4545 | 0 0 | (0 0) (0 0)
8041 23:07:59.969147 1 6 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8042 23:07:59.972433 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 23:07:59.976134 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 23:07:59.982522 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 23:07:59.985748 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 23:07:59.988989 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 23:07:59.995630 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8048 23:07:59.998882 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8049 23:08:00.002231 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8050 23:08:00.009212 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 23:08:00.012244 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 23:08:00.015602 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 23:08:00.022307 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 23:08:00.025773 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 23:08:00.028984 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 23:08:00.035413 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 23:08:00.038796 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 23:08:00.041960 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 23:08:00.048552 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 23:08:00.051909 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 23:08:00.055534 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 23:08:00.058620 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 23:08:00.065446 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 23:08:00.069023 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8065 23:08:00.072171 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8066 23:08:00.075621 Total UI for P1: 0, mck2ui 16
8067 23:08:00.078921 best dqsien dly found for B0: ( 1, 9, 12)
8068 23:08:00.085457 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 23:08:00.085542 Total UI for P1: 0, mck2ui 16
8070 23:08:00.092271 best dqsien dly found for B1: ( 1, 9, 14)
8071 23:08:00.095545 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8072 23:08:00.098856 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8073 23:08:00.098939
8074 23:08:00.102201 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8075 23:08:00.105531 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8076 23:08:00.108695 [Gating] SW calibration Done
8077 23:08:00.108779 ==
8078 23:08:00.111709 Dram Type= 6, Freq= 0, CH_0, rank 1
8079 23:08:00.115403 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8080 23:08:00.115488 ==
8081 23:08:00.118775 RX Vref Scan: 0
8082 23:08:00.118858
8083 23:08:00.122004 RX Vref 0 -> 0, step: 1
8084 23:08:00.122089
8085 23:08:00.122157 RX Delay 0 -> 252, step: 8
8086 23:08:00.128670 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8087 23:08:00.132150 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8088 23:08:00.135304 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8089 23:08:00.138536 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8090 23:08:00.141782 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8091 23:08:00.144972 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8092 23:08:00.151895 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8093 23:08:00.154947 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8094 23:08:00.158446 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8095 23:08:00.161579 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8096 23:08:00.164873 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8097 23:08:00.171818 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8098 23:08:00.174914 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8099 23:08:00.178397 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8100 23:08:00.181829 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8101 23:08:00.188405 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8102 23:08:00.188488 ==
8103 23:08:00.191775 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 23:08:00.194878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 23:08:00.194963 ==
8106 23:08:00.195030 DQS Delay:
8107 23:08:00.198599 DQS0 = 0, DQS1 = 0
8108 23:08:00.198684 DQM Delay:
8109 23:08:00.202059 DQM0 = 136, DQM1 = 125
8110 23:08:00.202143 DQ Delay:
8111 23:08:00.205241 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8112 23:08:00.208699 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8113 23:08:00.211678 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8114 23:08:00.215069 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8115 23:08:00.215153
8116 23:08:00.215220
8117 23:08:00.215282 ==
8118 23:08:00.218486 Dram Type= 6, Freq= 0, CH_0, rank 1
8119 23:08:00.224906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8120 23:08:00.224990 ==
8121 23:08:00.225058
8122 23:08:00.225120
8123 23:08:00.228243 TX Vref Scan disable
8124 23:08:00.228327 == TX Byte 0 ==
8125 23:08:00.231460 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8126 23:08:00.238100 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8127 23:08:00.238184 == TX Byte 1 ==
8128 23:08:00.241779 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8129 23:08:00.248363 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8130 23:08:00.248448 ==
8131 23:08:00.251537 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 23:08:00.254927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 23:08:00.255012 ==
8134 23:08:00.268190
8135 23:08:00.272071 TX Vref early break, caculate TX vref
8136 23:08:00.275592 TX Vref=16, minBit 0, minWin=23, winSum=390
8137 23:08:00.278228 TX Vref=18, minBit 0, minWin=24, winSum=397
8138 23:08:00.281651 TX Vref=20, minBit 1, minWin=24, winSum=407
8139 23:08:00.285256 TX Vref=22, minBit 8, minWin=24, winSum=412
8140 23:08:00.288263 TX Vref=24, minBit 2, minWin=25, winSum=422
8141 23:08:00.294819 TX Vref=26, minBit 0, minWin=26, winSum=430
8142 23:08:00.298417 TX Vref=28, minBit 0, minWin=26, winSum=432
8143 23:08:00.301719 TX Vref=30, minBit 0, minWin=26, winSum=424
8144 23:08:00.305023 TX Vref=32, minBit 0, minWin=25, winSum=416
8145 23:08:00.308459 TX Vref=34, minBit 0, minWin=25, winSum=409
8146 23:08:00.315205 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
8147 23:08:00.315284
8148 23:08:00.318329 Final TX Range 0 Vref 28
8149 23:08:00.318412
8150 23:08:00.318476 ==
8151 23:08:00.321632 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 23:08:00.324842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 23:08:00.324920 ==
8154 23:08:00.324993
8155 23:08:00.325054
8156 23:08:00.328034 TX Vref Scan disable
8157 23:08:00.335070 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8158 23:08:00.335146 == TX Byte 0 ==
8159 23:08:00.338272 u2DelayCellOfst[0]=10 cells (3 PI)
8160 23:08:00.341636 u2DelayCellOfst[1]=17 cells (5 PI)
8161 23:08:00.344872 u2DelayCellOfst[2]=10 cells (3 PI)
8162 23:08:00.347971 u2DelayCellOfst[3]=10 cells (3 PI)
8163 23:08:00.351377 u2DelayCellOfst[4]=6 cells (2 PI)
8164 23:08:00.354747 u2DelayCellOfst[5]=0 cells (0 PI)
8165 23:08:00.358345 u2DelayCellOfst[6]=17 cells (5 PI)
8166 23:08:00.358428 u2DelayCellOfst[7]=17 cells (5 PI)
8167 23:08:00.364654 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8168 23:08:00.368092 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8169 23:08:00.368170 == TX Byte 1 ==
8170 23:08:00.371260 u2DelayCellOfst[8]=0 cells (0 PI)
8171 23:08:00.374729 u2DelayCellOfst[9]=0 cells (0 PI)
8172 23:08:00.378014 u2DelayCellOfst[10]=3 cells (1 PI)
8173 23:08:00.381241 u2DelayCellOfst[11]=0 cells (0 PI)
8174 23:08:00.385171 u2DelayCellOfst[12]=10 cells (3 PI)
8175 23:08:00.388250 u2DelayCellOfst[13]=10 cells (3 PI)
8176 23:08:00.391409 u2DelayCellOfst[14]=10 cells (3 PI)
8177 23:08:00.394557 u2DelayCellOfst[15]=6 cells (2 PI)
8178 23:08:00.397932 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8179 23:08:00.404792 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8180 23:08:00.404886 DramC Write-DBI on
8181 23:08:00.404981 ==
8182 23:08:00.408158 Dram Type= 6, Freq= 0, CH_0, rank 1
8183 23:08:00.411436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8184 23:08:00.411520 ==
8185 23:08:00.411586
8186 23:08:00.414778
8187 23:08:00.414875 TX Vref Scan disable
8188 23:08:00.418266 == TX Byte 0 ==
8189 23:08:00.421517 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8190 23:08:00.424700 == TX Byte 1 ==
8191 23:08:00.427953 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8192 23:08:00.428036 DramC Write-DBI off
8193 23:08:00.428102
8194 23:08:00.431203 [DATLAT]
8195 23:08:00.431285 Freq=1600, CH0 RK1
8196 23:08:00.431351
8197 23:08:00.434467 DATLAT Default: 0xf
8198 23:08:00.434550 0, 0xFFFF, sum = 0
8199 23:08:00.437682 1, 0xFFFF, sum = 0
8200 23:08:00.437792 2, 0xFFFF, sum = 0
8201 23:08:00.441420 3, 0xFFFF, sum = 0
8202 23:08:00.441504 4, 0xFFFF, sum = 0
8203 23:08:00.444705 5, 0xFFFF, sum = 0
8204 23:08:00.447988 6, 0xFFFF, sum = 0
8205 23:08:00.448071 7, 0xFFFF, sum = 0
8206 23:08:00.451195 8, 0xFFFF, sum = 0
8207 23:08:00.451279 9, 0xFFFF, sum = 0
8208 23:08:00.454672 10, 0xFFFF, sum = 0
8209 23:08:00.454756 11, 0xFFFF, sum = 0
8210 23:08:00.457928 12, 0xFFFF, sum = 0
8211 23:08:00.458020 13, 0xFFFF, sum = 0
8212 23:08:00.461229 14, 0x0, sum = 1
8213 23:08:00.461313 15, 0x0, sum = 2
8214 23:08:00.464703 16, 0x0, sum = 3
8215 23:08:00.464786 17, 0x0, sum = 4
8216 23:08:00.467941 best_step = 15
8217 23:08:00.468023
8218 23:08:00.468090 ==
8219 23:08:00.471176 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 23:08:00.474623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 23:08:00.474706 ==
8222 23:08:00.474772 RX Vref Scan: 0
8223 23:08:00.474834
8224 23:08:00.477933 RX Vref 0 -> 0, step: 1
8225 23:08:00.478021
8226 23:08:00.481302 RX Delay 11 -> 252, step: 4
8227 23:08:00.484531 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8228 23:08:00.491350 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8229 23:08:00.494335 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8230 23:08:00.497846 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8231 23:08:00.501244 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8232 23:08:00.504633 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8233 23:08:00.508057 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8234 23:08:00.514510 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8235 23:08:00.517819 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8236 23:08:00.521078 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8237 23:08:00.524347 iDelay=191, Bit 10, Center 126 (79 ~ 174) 96
8238 23:08:00.528001 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8239 23:08:00.534657 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8240 23:08:00.538068 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8241 23:08:00.540960 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8242 23:08:00.544316 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8243 23:08:00.544398 ==
8244 23:08:00.547699 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 23:08:00.554170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 23:08:00.554267 ==
8247 23:08:00.554346 DQS Delay:
8248 23:08:00.557736 DQS0 = 0, DQS1 = 0
8249 23:08:00.557818 DQM Delay:
8250 23:08:00.557894 DQM0 = 133, DQM1 = 123
8251 23:08:00.561077 DQ Delay:
8252 23:08:00.564311 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8253 23:08:00.567522 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8254 23:08:00.570864 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =120
8255 23:08:00.574609 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8256 23:08:00.574692
8257 23:08:00.574757
8258 23:08:00.574816
8259 23:08:00.577903 [DramC_TX_OE_Calibration] TA2
8260 23:08:00.581157 Original DQ_B0 (3 6) =30, OEN = 27
8261 23:08:00.584401 Original DQ_B1 (3 6) =30, OEN = 27
8262 23:08:00.587848 24, 0x0, End_B0=24 End_B1=24
8263 23:08:00.587932 25, 0x0, End_B0=25 End_B1=25
8264 23:08:00.590820 26, 0x0, End_B0=26 End_B1=26
8265 23:08:00.594544 27, 0x0, End_B0=27 End_B1=27
8266 23:08:00.597867 28, 0x0, End_B0=28 End_B1=28
8267 23:08:00.600918 29, 0x0, End_B0=29 End_B1=29
8268 23:08:00.601001 30, 0x0, End_B0=30 End_B1=30
8269 23:08:00.604351 31, 0x4141, End_B0=30 End_B1=30
8270 23:08:00.607665 Byte0 end_step=30 best_step=27
8271 23:08:00.611054 Byte1 end_step=30 best_step=27
8272 23:08:00.614481 Byte0 TX OE(2T, 0.5T) = (3, 3)
8273 23:08:00.617495 Byte1 TX OE(2T, 0.5T) = (3, 3)
8274 23:08:00.617577
8275 23:08:00.617643
8276 23:08:00.624148 [DQSOSCAuto] RK1, (LSB)MR18= 0x220f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8277 23:08:00.627444 CH0 RK1: MR19=303, MR18=220F
8278 23:08:00.634333 CH0_RK1: MR19=0x303, MR18=0x220F, DQSOSC=392, MR23=63, INC=24, DEC=16
8279 23:08:00.637666 [RxdqsGatingPostProcess] freq 1600
8280 23:08:00.641016 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8281 23:08:00.644363 best DQS0 dly(2T, 0.5T) = (1, 1)
8282 23:08:00.647668 best DQS1 dly(2T, 0.5T) = (1, 1)
8283 23:08:00.650980 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8284 23:08:00.654332 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8285 23:08:00.657480 best DQS0 dly(2T, 0.5T) = (1, 1)
8286 23:08:00.660965 best DQS1 dly(2T, 0.5T) = (1, 1)
8287 23:08:00.664584 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8288 23:08:00.667441 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8289 23:08:00.671081 Pre-setting of DQS Precalculation
8290 23:08:00.674410 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8291 23:08:00.674493 ==
8292 23:08:00.677792 Dram Type= 6, Freq= 0, CH_1, rank 0
8293 23:08:00.680821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 23:08:00.680908 ==
8295 23:08:00.687638 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8296 23:08:00.690874 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8297 23:08:00.697701 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8298 23:08:00.700858 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8299 23:08:00.710552 [CA 0] Center 42 (12~72) winsize 61
8300 23:08:00.714384 [CA 1] Center 42 (12~72) winsize 61
8301 23:08:00.717545 [CA 2] Center 38 (9~68) winsize 60
8302 23:08:00.720800 [CA 3] Center 37 (8~67) winsize 60
8303 23:08:00.723887 [CA 4] Center 37 (8~67) winsize 60
8304 23:08:00.727189 [CA 5] Center 37 (7~67) winsize 61
8305 23:08:00.727289
8306 23:08:00.730562 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8307 23:08:00.730654
8308 23:08:00.733861 [CATrainingPosCal] consider 1 rank data
8309 23:08:00.737344 u2DelayCellTimex100 = 285/100 ps
8310 23:08:00.740662 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8311 23:08:00.747280 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8312 23:08:00.750583 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8313 23:08:00.753856 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8314 23:08:00.757001 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8315 23:08:00.760568 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8316 23:08:00.760677
8317 23:08:00.763723 CA PerBit enable=1, Macro0, CA PI delay=37
8318 23:08:00.763797
8319 23:08:00.767093 [CBTSetCACLKResult] CA Dly = 37
8320 23:08:00.770358 CS Dly: 9 (0~40)
8321 23:08:00.773510 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8322 23:08:00.776954 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8323 23:08:00.777027 ==
8324 23:08:00.780242 Dram Type= 6, Freq= 0, CH_1, rank 1
8325 23:08:00.783530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 23:08:00.786768 ==
8327 23:08:00.790237 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8328 23:08:00.793554 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8329 23:08:00.800203 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8330 23:08:00.803583 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8331 23:08:00.813786 [CA 0] Center 41 (12~71) winsize 60
8332 23:08:00.816996 [CA 1] Center 41 (12~71) winsize 60
8333 23:08:00.820409 [CA 2] Center 37 (8~67) winsize 60
8334 23:08:00.823912 [CA 3] Center 37 (8~67) winsize 60
8335 23:08:00.826952 [CA 4] Center 37 (8~67) winsize 60
8336 23:08:00.830314 [CA 5] Center 37 (7~67) winsize 61
8337 23:08:00.830420
8338 23:08:00.833653 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8339 23:08:00.833726
8340 23:08:00.837082 [CATrainingPosCal] consider 2 rank data
8341 23:08:00.840471 u2DelayCellTimex100 = 285/100 ps
8342 23:08:00.843360 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8343 23:08:00.850312 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8344 23:08:00.853517 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8345 23:08:00.856873 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8346 23:08:00.860639 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8347 23:08:00.863922 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8348 23:08:00.864003
8349 23:08:00.867116 CA PerBit enable=1, Macro0, CA PI delay=37
8350 23:08:00.867196
8351 23:08:00.870485 [CBTSetCACLKResult] CA Dly = 37
8352 23:08:00.873404 CS Dly: 11 (0~44)
8353 23:08:00.877284 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8354 23:08:00.880179 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8355 23:08:00.880259
8356 23:08:00.883562 ----->DramcWriteLeveling(PI) begin...
8357 23:08:00.883644 ==
8358 23:08:00.886846 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 23:08:00.890592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 23:08:00.893798 ==
8361 23:08:00.893905 Write leveling (Byte 0): 24 => 24
8362 23:08:00.897008 Write leveling (Byte 1): 27 => 27
8363 23:08:00.900404 DramcWriteLeveling(PI) end<-----
8364 23:08:00.900484
8365 23:08:00.900548 ==
8366 23:08:00.903717 Dram Type= 6, Freq= 0, CH_1, rank 0
8367 23:08:00.910493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8368 23:08:00.910574 ==
8369 23:08:00.910637 [Gating] SW mode calibration
8370 23:08:00.920243 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8371 23:08:00.923523 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8372 23:08:00.929971 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 23:08:00.933333 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 23:08:00.936531 1 4 8 | B1->B0 | 2e2e 3333 | 1 1 | (0 0) (1 1)
8375 23:08:00.943160 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 23:08:00.946535 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 23:08:00.949878 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 23:08:00.953401 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 23:08:00.959981 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 23:08:00.963309 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 23:08:00.966966 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 23:08:00.973131 1 5 8 | B1->B0 | 2b2b 2828 | 0 0 | (0 0) (1 0)
8383 23:08:00.976796 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8384 23:08:00.980079 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 23:08:00.986428 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 23:08:00.990118 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 23:08:00.993145 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 23:08:00.999914 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 23:08:01.003187 1 6 4 | B1->B0 | 2424 2727 | 0 1 | (0 0) (0 0)
8390 23:08:01.006513 1 6 8 | B1->B0 | 3a3a 4040 | 0 0 | (0 0) (0 0)
8391 23:08:01.013186 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 23:08:01.016448 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 23:08:01.019838 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 23:08:01.026281 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 23:08:01.029635 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 23:08:01.032916 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 23:08:01.039576 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 23:08:01.042879 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8399 23:08:01.046431 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8400 23:08:01.052833 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8401 23:08:01.056451 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 23:08:01.059482 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 23:08:01.066426 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 23:08:01.069494 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 23:08:01.072888 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 23:08:01.076191 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 23:08:01.083392 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 23:08:01.086527 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 23:08:01.089580 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 23:08:01.096261 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 23:08:01.099536 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 23:08:01.103192 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 23:08:01.109468 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8414 23:08:01.112879 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8415 23:08:01.116079 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8416 23:08:01.119415 Total UI for P1: 0, mck2ui 16
8417 23:08:01.122901 best dqsien dly found for B0: ( 1, 9, 6)
8418 23:08:01.129305 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 23:08:01.129389 Total UI for P1: 0, mck2ui 16
8420 23:08:01.135917 best dqsien dly found for B1: ( 1, 9, 10)
8421 23:08:01.139539 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8422 23:08:01.143056 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8423 23:08:01.143139
8424 23:08:01.145992 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8425 23:08:01.149193 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8426 23:08:01.152937 [Gating] SW calibration Done
8427 23:08:01.153020 ==
8428 23:08:01.156115 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 23:08:01.159515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 23:08:01.159599 ==
8431 23:08:01.162672 RX Vref Scan: 0
8432 23:08:01.162755
8433 23:08:01.162821 RX Vref 0 -> 0, step: 1
8434 23:08:01.162883
8435 23:08:01.166065 RX Delay 0 -> 252, step: 8
8436 23:08:01.169652 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8437 23:08:01.176030 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8438 23:08:01.179337 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8439 23:08:01.182837 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8440 23:08:01.185937 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8441 23:08:01.189323 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8442 23:08:01.192930 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8443 23:08:01.199559 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8444 23:08:01.202653 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8445 23:08:01.205928 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8446 23:08:01.209365 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8447 23:08:01.212592 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8448 23:08:01.219262 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8449 23:08:01.222853 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8450 23:08:01.225846 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8451 23:08:01.229188 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8452 23:08:01.229272 ==
8453 23:08:01.232365 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 23:08:01.239012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 23:08:01.239096 ==
8456 23:08:01.239163 DQS Delay:
8457 23:08:01.242323 DQS0 = 0, DQS1 = 0
8458 23:08:01.242407 DQM Delay:
8459 23:08:01.246103 DQM0 = 136, DQM1 = 131
8460 23:08:01.246187 DQ Delay:
8461 23:08:01.249392 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =139
8462 23:08:01.252646 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8463 23:08:01.256025 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8464 23:08:01.259136 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8465 23:08:01.259220
8466 23:08:01.259287
8467 23:08:01.259347 ==
8468 23:08:01.262523 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 23:08:01.265912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 23:08:01.269229 ==
8471 23:08:01.269313
8472 23:08:01.269379
8473 23:08:01.269440 TX Vref Scan disable
8474 23:08:01.272468 == TX Byte 0 ==
8475 23:08:01.275812 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8476 23:08:01.279006 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8477 23:08:01.282448 == TX Byte 1 ==
8478 23:08:01.285617 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8479 23:08:01.289096 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8480 23:08:01.292471 ==
8481 23:08:01.295722 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 23:08:01.298924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 23:08:01.299008 ==
8484 23:08:01.310780
8485 23:08:01.313858 TX Vref early break, caculate TX vref
8486 23:08:01.317187 TX Vref=16, minBit 10, minWin=22, winSum=367
8487 23:08:01.320482 TX Vref=18, minBit 10, minWin=22, winSum=381
8488 23:08:01.323763 TX Vref=20, minBit 10, minWin=23, winSum=397
8489 23:08:01.327122 TX Vref=22, minBit 10, minWin=23, winSum=402
8490 23:08:01.333913 TX Vref=24, minBit 1, minWin=25, winSum=411
8491 23:08:01.337258 TX Vref=26, minBit 1, minWin=25, winSum=419
8492 23:08:01.340581 TX Vref=28, minBit 12, minWin=25, winSum=426
8493 23:08:01.343930 TX Vref=30, minBit 8, minWin=25, winSum=418
8494 23:08:01.347143 TX Vref=32, minBit 0, minWin=25, winSum=409
8495 23:08:01.350398 TX Vref=34, minBit 5, minWin=24, winSum=400
8496 23:08:01.357318 [TxChooseVref] Worse bit 12, Min win 25, Win sum 426, Final Vref 28
8497 23:08:01.357402
8498 23:08:01.360687 Final TX Range 0 Vref 28
8499 23:08:01.360771
8500 23:08:01.360839 ==
8501 23:08:01.363944 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 23:08:01.366884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 23:08:01.366969 ==
8504 23:08:01.367037
8505 23:08:01.367100
8506 23:08:01.370466 TX Vref Scan disable
8507 23:08:01.377204 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8508 23:08:01.377289 == TX Byte 0 ==
8509 23:08:01.380502 u2DelayCellOfst[0]=17 cells (5 PI)
8510 23:08:01.383917 u2DelayCellOfst[1]=10 cells (3 PI)
8511 23:08:01.387125 u2DelayCellOfst[2]=0 cells (0 PI)
8512 23:08:01.390611 u2DelayCellOfst[3]=6 cells (2 PI)
8513 23:08:01.393963 u2DelayCellOfst[4]=6 cells (2 PI)
8514 23:08:01.396838 u2DelayCellOfst[5]=17 cells (5 PI)
8515 23:08:01.400498 u2DelayCellOfst[6]=17 cells (5 PI)
8516 23:08:01.403923 u2DelayCellOfst[7]=6 cells (2 PI)
8517 23:08:01.407136 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8518 23:08:01.410334 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8519 23:08:01.413515 == TX Byte 1 ==
8520 23:08:01.416824 u2DelayCellOfst[8]=0 cells (0 PI)
8521 23:08:01.416908 u2DelayCellOfst[9]=3 cells (1 PI)
8522 23:08:01.420155 u2DelayCellOfst[10]=10 cells (3 PI)
8523 23:08:01.423468 u2DelayCellOfst[11]=3 cells (1 PI)
8524 23:08:01.426845 u2DelayCellOfst[12]=13 cells (4 PI)
8525 23:08:01.430067 u2DelayCellOfst[13]=17 cells (5 PI)
8526 23:08:01.433453 u2DelayCellOfst[14]=20 cells (6 PI)
8527 23:08:01.436753 u2DelayCellOfst[15]=17 cells (5 PI)
8528 23:08:01.440404 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8529 23:08:01.447365 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8530 23:08:01.447449 DramC Write-DBI on
8531 23:08:01.447516 ==
8532 23:08:01.450013 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 23:08:01.457108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 23:08:01.457193 ==
8535 23:08:01.457261
8536 23:08:01.457324
8537 23:08:01.457383 TX Vref Scan disable
8538 23:08:01.460429 == TX Byte 0 ==
8539 23:08:01.464019 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8540 23:08:01.466995 == TX Byte 1 ==
8541 23:08:01.470514 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8542 23:08:01.473876 DramC Write-DBI off
8543 23:08:01.473997
8544 23:08:01.474065 [DATLAT]
8545 23:08:01.474127 Freq=1600, CH1 RK0
8546 23:08:01.474188
8547 23:08:01.476964 DATLAT Default: 0xf
8548 23:08:01.477062 0, 0xFFFF, sum = 0
8549 23:08:01.480621 1, 0xFFFF, sum = 0
8550 23:08:01.480707 2, 0xFFFF, sum = 0
8551 23:08:01.483616 3, 0xFFFF, sum = 0
8552 23:08:01.487104 4, 0xFFFF, sum = 0
8553 23:08:01.487190 5, 0xFFFF, sum = 0
8554 23:08:01.490583 6, 0xFFFF, sum = 0
8555 23:08:01.490668 7, 0xFFFF, sum = 0
8556 23:08:01.494115 8, 0xFFFF, sum = 0
8557 23:08:01.494200 9, 0xFFFF, sum = 0
8558 23:08:01.497192 10, 0xFFFF, sum = 0
8559 23:08:01.497277 11, 0xFFFF, sum = 0
8560 23:08:01.500429 12, 0xFFFF, sum = 0
8561 23:08:01.500514 13, 0xFFFF, sum = 0
8562 23:08:01.503700 14, 0x0, sum = 1
8563 23:08:01.503785 15, 0x0, sum = 2
8564 23:08:01.506962 16, 0x0, sum = 3
8565 23:08:01.507048 17, 0x0, sum = 4
8566 23:08:01.510362 best_step = 15
8567 23:08:01.510445
8568 23:08:01.510513 ==
8569 23:08:01.513500 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 23:08:01.516845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 23:08:01.516930 ==
8572 23:08:01.516997 RX Vref Scan: 1
8573 23:08:01.520131
8574 23:08:01.520215 Set Vref Range= 24 -> 127
8575 23:08:01.520281
8576 23:08:01.523891 RX Vref 24 -> 127, step: 1
8577 23:08:01.523975
8578 23:08:01.526946 RX Delay 19 -> 252, step: 4
8579 23:08:01.527030
8580 23:08:01.530417 Set Vref, RX VrefLevel [Byte0]: 24
8581 23:08:01.533740 [Byte1]: 24
8582 23:08:01.533824
8583 23:08:01.536953 Set Vref, RX VrefLevel [Byte0]: 25
8584 23:08:01.540333 [Byte1]: 25
8585 23:08:01.540416
8586 23:08:01.543388 Set Vref, RX VrefLevel [Byte0]: 26
8587 23:08:01.546719 [Byte1]: 26
8588 23:08:01.550610
8589 23:08:01.550694 Set Vref, RX VrefLevel [Byte0]: 27
8590 23:08:01.554094 [Byte1]: 27
8591 23:08:01.558360
8592 23:08:01.558444 Set Vref, RX VrefLevel [Byte0]: 28
8593 23:08:01.561704 [Byte1]: 28
8594 23:08:01.565874
8595 23:08:01.565996 Set Vref, RX VrefLevel [Byte0]: 29
8596 23:08:01.569199 [Byte1]: 29
8597 23:08:01.573313
8598 23:08:01.573396 Set Vref, RX VrefLevel [Byte0]: 30
8599 23:08:01.576782 [Byte1]: 30
8600 23:08:01.581071
8601 23:08:01.581155 Set Vref, RX VrefLevel [Byte0]: 31
8602 23:08:01.584152 [Byte1]: 31
8603 23:08:01.588501
8604 23:08:01.588585 Set Vref, RX VrefLevel [Byte0]: 32
8605 23:08:01.592011 [Byte1]: 32
8606 23:08:01.596177
8607 23:08:01.596260 Set Vref, RX VrefLevel [Byte0]: 33
8608 23:08:01.599411 [Byte1]: 33
8609 23:08:01.603555
8610 23:08:01.603639 Set Vref, RX VrefLevel [Byte0]: 34
8611 23:08:01.607014 [Byte1]: 34
8612 23:08:01.611128
8613 23:08:01.611212 Set Vref, RX VrefLevel [Byte0]: 35
8614 23:08:01.614411 [Byte1]: 35
8615 23:08:01.619014
8616 23:08:01.619097 Set Vref, RX VrefLevel [Byte0]: 36
8617 23:08:01.622358 [Byte1]: 36
8618 23:08:01.626239
8619 23:08:01.626322 Set Vref, RX VrefLevel [Byte0]: 37
8620 23:08:01.629875 [Byte1]: 37
8621 23:08:01.634163
8622 23:08:01.634247 Set Vref, RX VrefLevel [Byte0]: 38
8623 23:08:01.637491 [Byte1]: 38
8624 23:08:01.641411
8625 23:08:01.641495 Set Vref, RX VrefLevel [Byte0]: 39
8626 23:08:01.644946 [Byte1]: 39
8627 23:08:01.649315
8628 23:08:01.649398 Set Vref, RX VrefLevel [Byte0]: 40
8629 23:08:01.652560 [Byte1]: 40
8630 23:08:01.656764
8631 23:08:01.656848 Set Vref, RX VrefLevel [Byte0]: 41
8632 23:08:01.660000 [Byte1]: 41
8633 23:08:01.664327
8634 23:08:01.664411 Set Vref, RX VrefLevel [Byte0]: 42
8635 23:08:01.667599 [Byte1]: 42
8636 23:08:01.671894
8637 23:08:01.671978 Set Vref, RX VrefLevel [Byte0]: 43
8638 23:08:01.675189 [Byte1]: 43
8639 23:08:01.679667
8640 23:08:01.679750 Set Vref, RX VrefLevel [Byte0]: 44
8641 23:08:01.682791 [Byte1]: 44
8642 23:08:01.687035
8643 23:08:01.687118 Set Vref, RX VrefLevel [Byte0]: 45
8644 23:08:01.690444 [Byte1]: 45
8645 23:08:01.694600
8646 23:08:01.694684 Set Vref, RX VrefLevel [Byte0]: 46
8647 23:08:01.697966 [Byte1]: 46
8648 23:08:01.702187
8649 23:08:01.702270 Set Vref, RX VrefLevel [Byte0]: 47
8650 23:08:01.705606 [Byte1]: 47
8651 23:08:01.709848
8652 23:08:01.709959 Set Vref, RX VrefLevel [Byte0]: 48
8653 23:08:01.713079 [Byte1]: 48
8654 23:08:01.717384
8655 23:08:01.717468 Set Vref, RX VrefLevel [Byte0]: 49
8656 23:08:01.720679 [Byte1]: 49
8657 23:08:01.725103
8658 23:08:01.725187 Set Vref, RX VrefLevel [Byte0]: 50
8659 23:08:01.728462 [Byte1]: 50
8660 23:08:01.732590
8661 23:08:01.732674 Set Vref, RX VrefLevel [Byte0]: 51
8662 23:08:01.736052 [Byte1]: 51
8663 23:08:01.739923
8664 23:08:01.740006 Set Vref, RX VrefLevel [Byte0]: 52
8665 23:08:01.743318 [Byte1]: 52
8666 23:08:01.747592
8667 23:08:01.747676 Set Vref, RX VrefLevel [Byte0]: 53
8668 23:08:01.750766 [Byte1]: 53
8669 23:08:01.755476
8670 23:08:01.755560 Set Vref, RX VrefLevel [Byte0]: 54
8671 23:08:01.758675 [Byte1]: 54
8672 23:08:01.762645
8673 23:08:01.762728 Set Vref, RX VrefLevel [Byte0]: 55
8674 23:08:01.765998 [Byte1]: 55
8675 23:08:01.770372
8676 23:08:01.770456 Set Vref, RX VrefLevel [Byte0]: 56
8677 23:08:01.773636 [Byte1]: 56
8678 23:08:01.777885
8679 23:08:01.778023 Set Vref, RX VrefLevel [Byte0]: 57
8680 23:08:01.781481 [Byte1]: 57
8681 23:08:01.785314
8682 23:08:01.785397 Set Vref, RX VrefLevel [Byte0]: 58
8683 23:08:01.788689 [Byte1]: 58
8684 23:08:01.792846
8685 23:08:01.792930 Set Vref, RX VrefLevel [Byte0]: 59
8686 23:08:01.796156 [Byte1]: 59
8687 23:08:01.800446
8688 23:08:01.800530 Set Vref, RX VrefLevel [Byte0]: 60
8689 23:08:01.803916 [Byte1]: 60
8690 23:08:01.808432
8691 23:08:01.808516 Set Vref, RX VrefLevel [Byte0]: 61
8692 23:08:01.811323 [Byte1]: 61
8693 23:08:01.815732
8694 23:08:01.815816 Set Vref, RX VrefLevel [Byte0]: 62
8695 23:08:01.819018 [Byte1]: 62
8696 23:08:01.823260
8697 23:08:01.823343 Set Vref, RX VrefLevel [Byte0]: 63
8698 23:08:01.826482 [Byte1]: 63
8699 23:08:01.831014
8700 23:08:01.831097 Set Vref, RX VrefLevel [Byte0]: 64
8701 23:08:01.834453 [Byte1]: 64
8702 23:08:01.838726
8703 23:08:01.838810 Set Vref, RX VrefLevel [Byte0]: 65
8704 23:08:01.841902 [Byte1]: 65
8705 23:08:01.845887
8706 23:08:01.846024 Set Vref, RX VrefLevel [Byte0]: 66
8707 23:08:01.849261 [Byte1]: 66
8708 23:08:01.853893
8709 23:08:01.854026 Set Vref, RX VrefLevel [Byte0]: 67
8710 23:08:01.857075 [Byte1]: 67
8711 23:08:01.861258
8712 23:08:01.861342 Set Vref, RX VrefLevel [Byte0]: 68
8713 23:08:01.864595 [Byte1]: 68
8714 23:08:01.869034
8715 23:08:01.869118 Set Vref, RX VrefLevel [Byte0]: 69
8716 23:08:01.871916 [Byte1]: 69
8717 23:08:01.876632
8718 23:08:01.876715 Set Vref, RX VrefLevel [Byte0]: 70
8719 23:08:01.879717 [Byte1]: 70
8720 23:08:01.884017
8721 23:08:01.884101 Set Vref, RX VrefLevel [Byte0]: 71
8722 23:08:01.887191 [Byte1]: 71
8723 23:08:01.891442
8724 23:08:01.891526 Set Vref, RX VrefLevel [Byte0]: 72
8725 23:08:01.894828 [Byte1]: 72
8726 23:08:01.899039
8727 23:08:01.899122 Set Vref, RX VrefLevel [Byte0]: 73
8728 23:08:01.902350 [Byte1]: 73
8729 23:08:01.906766
8730 23:08:01.909820 Set Vref, RX VrefLevel [Byte0]: 74
8731 23:08:01.912979 [Byte1]: 74
8732 23:08:01.913063
8733 23:08:01.916553 Set Vref, RX VrefLevel [Byte0]: 75
8734 23:08:01.919981 [Byte1]: 75
8735 23:08:01.920065
8736 23:08:01.923263 Set Vref, RX VrefLevel [Byte0]: 76
8737 23:08:01.926503 [Byte1]: 76
8738 23:08:01.926588
8739 23:08:01.929751 Set Vref, RX VrefLevel [Byte0]: 77
8740 23:08:01.933182 [Byte1]: 77
8741 23:08:01.936817
8742 23:08:01.936901 Set Vref, RX VrefLevel [Byte0]: 78
8743 23:08:01.940138 [Byte1]: 78
8744 23:08:01.944450
8745 23:08:01.944534 Final RX Vref Byte 0 = 57 to rank0
8746 23:08:01.947769 Final RX Vref Byte 1 = 62 to rank0
8747 23:08:01.951197 Final RX Vref Byte 0 = 57 to rank1
8748 23:08:01.954441 Final RX Vref Byte 1 = 62 to rank1==
8749 23:08:01.957680 Dram Type= 6, Freq= 0, CH_1, rank 0
8750 23:08:01.964371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8751 23:08:01.964456 ==
8752 23:08:01.964523 DQS Delay:
8753 23:08:01.964586 DQS0 = 0, DQS1 = 0
8754 23:08:01.967622 DQM Delay:
8755 23:08:01.967706 DQM0 = 133, DQM1 = 129
8756 23:08:01.970929 DQ Delay:
8757 23:08:01.974329 DQ0 =136, DQ1 =128, DQ2 =122, DQ3 =132
8758 23:08:01.977735 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
8759 23:08:01.981235 DQ8 =116, DQ9 =120, DQ10 =134, DQ11 =124
8760 23:08:01.984368 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8761 23:08:01.984452
8762 23:08:01.984518
8763 23:08:01.984581
8764 23:08:01.987656 [DramC_TX_OE_Calibration] TA2
8765 23:08:01.990965 Original DQ_B0 (3 6) =30, OEN = 27
8766 23:08:01.994237 Original DQ_B1 (3 6) =30, OEN = 27
8767 23:08:01.997498 24, 0x0, End_B0=24 End_B1=24
8768 23:08:01.997584 25, 0x0, End_B0=25 End_B1=25
8769 23:08:02.000983 26, 0x0, End_B0=26 End_B1=26
8770 23:08:02.004191 27, 0x0, End_B0=27 End_B1=27
8771 23:08:02.007876 28, 0x0, End_B0=28 End_B1=28
8772 23:08:02.010989 29, 0x0, End_B0=29 End_B1=29
8773 23:08:02.011075 30, 0x0, End_B0=30 End_B1=30
8774 23:08:02.014384 31, 0x5151, End_B0=30 End_B1=30
8775 23:08:02.017548 Byte0 end_step=30 best_step=27
8776 23:08:02.020643 Byte1 end_step=30 best_step=27
8777 23:08:02.023972 Byte0 TX OE(2T, 0.5T) = (3, 3)
8778 23:08:02.027486 Byte1 TX OE(2T, 0.5T) = (3, 3)
8779 23:08:02.027570
8780 23:08:02.027638
8781 23:08:02.034210 [DQSOSCAuto] RK0, (LSB)MR18= 0x1827, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8782 23:08:02.037478 CH1 RK0: MR19=303, MR18=1827
8783 23:08:02.044034 CH1_RK0: MR19=0x303, MR18=0x1827, DQSOSC=390, MR23=63, INC=24, DEC=16
8784 23:08:02.044118
8785 23:08:02.047400 ----->DramcWriteLeveling(PI) begin...
8786 23:08:02.047485 ==
8787 23:08:02.050652 Dram Type= 6, Freq= 0, CH_1, rank 1
8788 23:08:02.053879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8789 23:08:02.053983 ==
8790 23:08:02.057239 Write leveling (Byte 0): 24 => 24
8791 23:08:02.060617 Write leveling (Byte 1): 28 => 28
8792 23:08:02.063853 DramcWriteLeveling(PI) end<-----
8793 23:08:02.063937
8794 23:08:02.064004 ==
8795 23:08:02.067245 Dram Type= 6, Freq= 0, CH_1, rank 1
8796 23:08:02.070829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8797 23:08:02.070913 ==
8798 23:08:02.073887 [Gating] SW mode calibration
8799 23:08:02.080540 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8800 23:08:02.087343 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8801 23:08:02.090545 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 23:08:02.094028 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 23:08:02.100795 1 4 8 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
8804 23:08:02.103914 1 4 12 | B1->B0 | 3434 2a29 | 1 1 | (1 1) (0 0)
8805 23:08:02.107225 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 23:08:02.113822 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 23:08:02.117335 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8808 23:08:02.120493 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8809 23:08:02.127118 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8810 23:08:02.130732 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8811 23:08:02.134345 1 5 8 | B1->B0 | 2626 3434 | 1 1 | (1 0) (1 0)
8812 23:08:02.140380 1 5 12 | B1->B0 | 2323 2c2c | 0 0 | (1 0) (0 1)
8813 23:08:02.143662 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 23:08:02.147664 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 23:08:02.153884 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 23:08:02.157291 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 23:08:02.160630 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 23:08:02.167384 1 6 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8819 23:08:02.170731 1 6 8 | B1->B0 | 4141 2323 | 0 0 | (1 1) (0 0)
8820 23:08:02.173881 1 6 12 | B1->B0 | 4646 3636 | 0 0 | (0 0) (0 0)
8821 23:08:02.180514 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 23:08:02.183905 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 23:08:02.186974 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 23:08:02.193694 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 23:08:02.197062 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 23:08:02.200397 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 23:08:02.203682 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8828 23:08:02.210762 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8829 23:08:02.213781 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 23:08:02.217232 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 23:08:02.223786 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 23:08:02.227139 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 23:08:02.230258 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 23:08:02.236985 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 23:08:02.240170 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 23:08:02.243465 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 23:08:02.250492 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 23:08:02.253415 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 23:08:02.257130 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 23:08:02.263735 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 23:08:02.266935 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 23:08:02.269797 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 23:08:02.276463 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8844 23:08:02.279789 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8845 23:08:02.283421 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 23:08:02.286847 Total UI for P1: 0, mck2ui 16
8847 23:08:02.289805 best dqsien dly found for B0: ( 1, 9, 10)
8848 23:08:02.293143 Total UI for P1: 0, mck2ui 16
8849 23:08:02.296579 best dqsien dly found for B1: ( 1, 9, 10)
8850 23:08:02.299848 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8851 23:08:02.303216 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8852 23:08:02.303300
8853 23:08:02.309779 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8854 23:08:02.312900 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8855 23:08:02.316537 [Gating] SW calibration Done
8856 23:08:02.316620 ==
8857 23:08:02.319866 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 23:08:02.322900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 23:08:02.323009 ==
8860 23:08:02.323081 RX Vref Scan: 0
8861 23:08:02.323144
8862 23:08:02.326577 RX Vref 0 -> 0, step: 1
8863 23:08:02.326660
8864 23:08:02.329589 RX Delay 0 -> 252, step: 8
8865 23:08:02.332953 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8866 23:08:02.336004 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8867 23:08:02.342882 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8868 23:08:02.346236 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8869 23:08:02.349123 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8870 23:08:02.352512 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8871 23:08:02.355894 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8872 23:08:02.359184 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8873 23:08:02.365707 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8874 23:08:02.369311 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8875 23:08:02.372579 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8876 23:08:02.375875 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8877 23:08:02.382272 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8878 23:08:02.385643 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8879 23:08:02.388927 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8880 23:08:02.392518 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8881 23:08:02.392607 ==
8882 23:08:02.395614 Dram Type= 6, Freq= 0, CH_1, rank 1
8883 23:08:02.402207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8884 23:08:02.402294 ==
8885 23:08:02.402356 DQS Delay:
8886 23:08:02.405455 DQS0 = 0, DQS1 = 0
8887 23:08:02.405565 DQM Delay:
8888 23:08:02.405657 DQM0 = 136, DQM1 = 131
8889 23:08:02.408789 DQ Delay:
8890 23:08:02.412132 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8891 23:08:02.415401 DQ4 =135, DQ5 =147, DQ6 =139, DQ7 =135
8892 23:08:02.418671 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8893 23:08:02.422200 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =143
8894 23:08:02.422288
8895 23:08:02.422381
8896 23:08:02.422440 ==
8897 23:08:02.425840 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 23:08:02.428738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 23:08:02.432443 ==
8900 23:08:02.432543
8901 23:08:02.432637
8902 23:08:02.432725 TX Vref Scan disable
8903 23:08:02.435205 == TX Byte 0 ==
8904 23:08:02.438573 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8905 23:08:02.442056 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8906 23:08:02.445112 == TX Byte 1 ==
8907 23:08:02.448586 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8908 23:08:02.451718 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8909 23:08:02.455106 ==
8910 23:08:02.458498 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 23:08:02.461828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 23:08:02.461914 ==
8913 23:08:02.474217
8914 23:08:02.477436 TX Vref early break, caculate TX vref
8915 23:08:02.480733 TX Vref=16, minBit 9, minWin=22, winSum=382
8916 23:08:02.483916 TX Vref=18, minBit 9, minWin=21, winSum=389
8917 23:08:02.487247 TX Vref=20, minBit 9, minWin=23, winSum=394
8918 23:08:02.490633 TX Vref=22, minBit 9, minWin=24, winSum=407
8919 23:08:02.493911 TX Vref=24, minBit 9, minWin=24, winSum=408
8920 23:08:02.500653 TX Vref=26, minBit 10, minWin=24, winSum=422
8921 23:08:02.503966 TX Vref=28, minBit 10, minWin=25, winSum=419
8922 23:08:02.507472 TX Vref=30, minBit 9, minWin=24, winSum=416
8923 23:08:02.510663 TX Vref=32, minBit 9, minWin=24, winSum=409
8924 23:08:02.513644 TX Vref=34, minBit 0, minWin=24, winSum=399
8925 23:08:02.520719 [TxChooseVref] Worse bit 10, Min win 25, Win sum 419, Final Vref 28
8926 23:08:02.520820
8927 23:08:02.523958 Final TX Range 0 Vref 28
8928 23:08:02.524063
8929 23:08:02.524154 ==
8930 23:08:02.527271 Dram Type= 6, Freq= 0, CH_1, rank 1
8931 23:08:02.530395 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8932 23:08:02.530493 ==
8933 23:08:02.530584
8934 23:08:02.530681
8935 23:08:02.533873 TX Vref Scan disable
8936 23:08:02.540414 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8937 23:08:02.540520 == TX Byte 0 ==
8938 23:08:02.543627 u2DelayCellOfst[0]=13 cells (4 PI)
8939 23:08:02.546908 u2DelayCellOfst[1]=10 cells (3 PI)
8940 23:08:02.550244 u2DelayCellOfst[2]=0 cells (0 PI)
8941 23:08:02.553717 u2DelayCellOfst[3]=3 cells (1 PI)
8942 23:08:02.557085 u2DelayCellOfst[4]=6 cells (2 PI)
8943 23:08:02.560548 u2DelayCellOfst[5]=17 cells (5 PI)
8944 23:08:02.563754 u2DelayCellOfst[6]=17 cells (5 PI)
8945 23:08:02.566964 u2DelayCellOfst[7]=3 cells (1 PI)
8946 23:08:02.570344 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8947 23:08:02.573796 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8948 23:08:02.573893 == TX Byte 1 ==
8949 23:08:02.576996 u2DelayCellOfst[8]=0 cells (0 PI)
8950 23:08:02.580406 u2DelayCellOfst[9]=0 cells (0 PI)
8951 23:08:02.583670 u2DelayCellOfst[10]=10 cells (3 PI)
8952 23:08:02.586824 u2DelayCellOfst[11]=0 cells (0 PI)
8953 23:08:02.590603 u2DelayCellOfst[12]=10 cells (3 PI)
8954 23:08:02.593437 u2DelayCellOfst[13]=17 cells (5 PI)
8955 23:08:02.596829 u2DelayCellOfst[14]=17 cells (5 PI)
8956 23:08:02.600262 u2DelayCellOfst[15]=13 cells (4 PI)
8957 23:08:02.603584 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8958 23:08:02.609837 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8959 23:08:02.609991 DramC Write-DBI on
8960 23:08:02.610089 ==
8961 23:08:02.613766 Dram Type= 6, Freq= 0, CH_1, rank 1
8962 23:08:02.619866 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8963 23:08:02.619974 ==
8964 23:08:02.620068
8965 23:08:02.620162
8966 23:08:02.620253 TX Vref Scan disable
8967 23:08:02.623299 == TX Byte 0 ==
8968 23:08:02.626777 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8969 23:08:02.630364 == TX Byte 1 ==
8970 23:08:02.633207 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8971 23:08:02.636428 DramC Write-DBI off
8972 23:08:02.636533
8973 23:08:02.636627 [DATLAT]
8974 23:08:02.636724 Freq=1600, CH1 RK1
8975 23:08:02.636825
8976 23:08:02.639994 DATLAT Default: 0xf
8977 23:08:02.640098 0, 0xFFFF, sum = 0
8978 23:08:02.643922 1, 0xFFFF, sum = 0
8979 23:08:02.646428 2, 0xFFFF, sum = 0
8980 23:08:02.646532 3, 0xFFFF, sum = 0
8981 23:08:02.649877 4, 0xFFFF, sum = 0
8982 23:08:02.650033 5, 0xFFFF, sum = 0
8983 23:08:02.653327 6, 0xFFFF, sum = 0
8984 23:08:02.653408 7, 0xFFFF, sum = 0
8985 23:08:02.656713 8, 0xFFFF, sum = 0
8986 23:08:02.656796 9, 0xFFFF, sum = 0
8987 23:08:02.659851 10, 0xFFFF, sum = 0
8988 23:08:02.659933 11, 0xFFFF, sum = 0
8989 23:08:02.663278 12, 0xFFFF, sum = 0
8990 23:08:02.663352 13, 0xFFFF, sum = 0
8991 23:08:02.666557 14, 0x0, sum = 1
8992 23:08:02.666627 15, 0x0, sum = 2
8993 23:08:02.669696 16, 0x0, sum = 3
8994 23:08:02.669768 17, 0x0, sum = 4
8995 23:08:02.673061 best_step = 15
8996 23:08:02.673133
8997 23:08:02.673195 ==
8998 23:08:02.676378 Dram Type= 6, Freq= 0, CH_1, rank 1
8999 23:08:02.679776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9000 23:08:02.679845 ==
9001 23:08:02.682967 RX Vref Scan: 0
9002 23:08:02.683037
9003 23:08:02.683106 RX Vref 0 -> 0, step: 1
9004 23:08:02.683166
9005 23:08:02.686431 RX Delay 19 -> 252, step: 4
9006 23:08:02.689839 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
9007 23:08:02.696194 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9008 23:08:02.699655 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9009 23:08:02.702771 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9010 23:08:02.706005 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9011 23:08:02.709317 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
9012 23:08:02.716280 iDelay=195, Bit 6, Center 140 (91 ~ 190) 100
9013 23:08:02.719496 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9014 23:08:02.722799 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9015 23:08:02.726379 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9016 23:08:02.729600 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9017 23:08:02.736266 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9018 23:08:02.739503 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9019 23:08:02.742689 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9020 23:08:02.745862 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9021 23:08:02.749258 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9022 23:08:02.752866 ==
9023 23:08:02.755971 Dram Type= 6, Freq= 0, CH_1, rank 1
9024 23:08:02.759457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9025 23:08:02.759574 ==
9026 23:08:02.759708 DQS Delay:
9027 23:08:02.762783 DQS0 = 0, DQS1 = 0
9028 23:08:02.762866 DQM Delay:
9029 23:08:02.765880 DQM0 = 133, DQM1 = 129
9030 23:08:02.766002 DQ Delay:
9031 23:08:02.769046 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9032 23:08:02.772477 DQ4 =134, DQ5 =144, DQ6 =140, DQ7 =130
9033 23:08:02.775612 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =126
9034 23:08:02.778921 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =140
9035 23:08:02.779023
9036 23:08:02.779133
9037 23:08:02.779195
9038 23:08:02.782554 [DramC_TX_OE_Calibration] TA2
9039 23:08:02.785842 Original DQ_B0 (3 6) =30, OEN = 27
9040 23:08:02.789300 Original DQ_B1 (3 6) =30, OEN = 27
9041 23:08:02.792357 24, 0x0, End_B0=24 End_B1=24
9042 23:08:02.795634 25, 0x0, End_B0=25 End_B1=25
9043 23:08:02.795733 26, 0x0, End_B0=26 End_B1=26
9044 23:08:02.798874 27, 0x0, End_B0=27 End_B1=27
9045 23:08:02.802167 28, 0x0, End_B0=28 End_B1=28
9046 23:08:02.805482 29, 0x0, End_B0=29 End_B1=29
9047 23:08:02.808783 30, 0x0, End_B0=30 End_B1=30
9048 23:08:02.808869 31, 0x5151, End_B0=30 End_B1=30
9049 23:08:02.812088 Byte0 end_step=30 best_step=27
9050 23:08:02.815439 Byte1 end_step=30 best_step=27
9051 23:08:02.819031 Byte0 TX OE(2T, 0.5T) = (3, 3)
9052 23:08:02.822520 Byte1 TX OE(2T, 0.5T) = (3, 3)
9053 23:08:02.822603
9054 23:08:02.822670
9055 23:08:02.828990 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
9056 23:08:02.832429 CH1 RK1: MR19=303, MR18=1E09
9057 23:08:02.838859 CH1_RK1: MR19=0x303, MR18=0x1E09, DQSOSC=394, MR23=63, INC=23, DEC=15
9058 23:08:02.842166 [RxdqsGatingPostProcess] freq 1600
9059 23:08:02.848975 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9060 23:08:02.849060 best DQS0 dly(2T, 0.5T) = (1, 1)
9061 23:08:02.852363 best DQS1 dly(2T, 0.5T) = (1, 1)
9062 23:08:02.855587 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9063 23:08:02.859100 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9064 23:08:02.862030 best DQS0 dly(2T, 0.5T) = (1, 1)
9065 23:08:02.865414 best DQS1 dly(2T, 0.5T) = (1, 1)
9066 23:08:02.868885 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9067 23:08:02.872039 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9068 23:08:02.875531 Pre-setting of DQS Precalculation
9069 23:08:02.878962 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9070 23:08:02.885750 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9071 23:08:02.895333 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9072 23:08:02.895417
9073 23:08:02.895484
9074 23:08:02.898710 [Calibration Summary] 3200 Mbps
9075 23:08:02.898794 CH 0, Rank 0
9076 23:08:02.902211 SW Impedance : PASS
9077 23:08:02.902294 DUTY Scan : NO K
9078 23:08:02.905542 ZQ Calibration : PASS
9079 23:08:02.908850 Jitter Meter : NO K
9080 23:08:02.908949 CBT Training : PASS
9081 23:08:02.912240 Write leveling : PASS
9082 23:08:02.912323 RX DQS gating : PASS
9083 23:08:02.915562 RX DQ/DQS(RDDQC) : PASS
9084 23:08:02.918838 TX DQ/DQS : PASS
9085 23:08:02.918922 RX DATLAT : PASS
9086 23:08:02.922103 RX DQ/DQS(Engine): PASS
9087 23:08:02.925473 TX OE : PASS
9088 23:08:02.925556 All Pass.
9089 23:08:02.925623
9090 23:08:02.925685 CH 0, Rank 1
9091 23:08:02.928767 SW Impedance : PASS
9092 23:08:02.932034 DUTY Scan : NO K
9093 23:08:02.932118 ZQ Calibration : PASS
9094 23:08:02.935220 Jitter Meter : NO K
9095 23:08:02.938571 CBT Training : PASS
9096 23:08:02.938654 Write leveling : PASS
9097 23:08:02.942441 RX DQS gating : PASS
9098 23:08:02.945741 RX DQ/DQS(RDDQC) : PASS
9099 23:08:02.945825 TX DQ/DQS : PASS
9100 23:08:02.948926 RX DATLAT : PASS
9101 23:08:02.951957 RX DQ/DQS(Engine): PASS
9102 23:08:02.952040 TX OE : PASS
9103 23:08:02.952108 All Pass.
9104 23:08:02.955222
9105 23:08:02.955305 CH 1, Rank 0
9106 23:08:02.958499 SW Impedance : PASS
9107 23:08:02.958582 DUTY Scan : NO K
9108 23:08:02.962076 ZQ Calibration : PASS
9109 23:08:02.962174 Jitter Meter : NO K
9110 23:08:02.965218 CBT Training : PASS
9111 23:08:02.968599 Write leveling : PASS
9112 23:08:02.968685 RX DQS gating : PASS
9113 23:08:02.971852 RX DQ/DQS(RDDQC) : PASS
9114 23:08:02.975375 TX DQ/DQS : PASS
9115 23:08:02.975459 RX DATLAT : PASS
9116 23:08:02.978468 RX DQ/DQS(Engine): PASS
9117 23:08:02.981828 TX OE : PASS
9118 23:08:02.981937 All Pass.
9119 23:08:02.982053
9120 23:08:02.982116 CH 1, Rank 1
9121 23:08:02.985403 SW Impedance : PASS
9122 23:08:02.988606 DUTY Scan : NO K
9123 23:08:02.988732 ZQ Calibration : PASS
9124 23:08:02.991820 Jitter Meter : NO K
9125 23:08:02.995236 CBT Training : PASS
9126 23:08:02.995319 Write leveling : PASS
9127 23:08:02.998553 RX DQS gating : PASS
9128 23:08:03.001793 RX DQ/DQS(RDDQC) : PASS
9129 23:08:03.001903 TX DQ/DQS : PASS
9130 23:08:03.005208 RX DATLAT : PASS
9131 23:08:03.005292 RX DQ/DQS(Engine): PASS
9132 23:08:03.008421 TX OE : PASS
9133 23:08:03.008507 All Pass.
9134 23:08:03.008574
9135 23:08:03.011876 DramC Write-DBI on
9136 23:08:03.015221 PER_BANK_REFRESH: Hybrid Mode
9137 23:08:03.015320 TX_TRACKING: ON
9138 23:08:03.025373 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9139 23:08:03.032108 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9140 23:08:03.041627 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9141 23:08:03.044897 [FAST_K] Save calibration result to emmc
9142 23:08:03.044982 sync common calibartion params.
9143 23:08:03.048613 sync cbt_mode0:1, 1:1
9144 23:08:03.051921 dram_init: ddr_geometry: 2
9145 23:08:03.055163 dram_init: ddr_geometry: 2
9146 23:08:03.055246 dram_init: ddr_geometry: 2
9147 23:08:03.058277 0:dram_rank_size:100000000
9148 23:08:03.061797 1:dram_rank_size:100000000
9149 23:08:03.065173 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9150 23:08:03.068344 DFS_SHUFFLE_HW_MODE: ON
9151 23:08:03.071864 dramc_set_vcore_voltage set vcore to 725000
9152 23:08:03.074979 Read voltage for 1600, 0
9153 23:08:03.075063 Vio18 = 0
9154 23:08:03.078222 Vcore = 725000
9155 23:08:03.078307 Vdram = 0
9156 23:08:03.078374 Vddq = 0
9157 23:08:03.078437 Vmddr = 0
9158 23:08:03.081924 switch to 3200 Mbps bootup
9159 23:08:03.085269 [DramcRunTimeConfig]
9160 23:08:03.085368 PHYPLL
9161 23:08:03.088254 DPM_CONTROL_AFTERK: ON
9162 23:08:03.088338 PER_BANK_REFRESH: ON
9163 23:08:03.091603 REFRESH_OVERHEAD_REDUCTION: ON
9164 23:08:03.094858 CMD_PICG_NEW_MODE: OFF
9165 23:08:03.094942 XRTWTW_NEW_MODE: ON
9166 23:08:03.098148 XRTRTR_NEW_MODE: ON
9167 23:08:03.098233 TX_TRACKING: ON
9168 23:08:03.101801 RDSEL_TRACKING: OFF
9169 23:08:03.101917 DQS Precalculation for DVFS: ON
9170 23:08:03.104882 RX_TRACKING: OFF
9171 23:08:03.105036 HW_GATING DBG: ON
9172 23:08:03.108173 ZQCS_ENABLE_LP4: ON
9173 23:08:03.111439 RX_PICG_NEW_MODE: ON
9174 23:08:03.111524 TX_PICG_NEW_MODE: ON
9175 23:08:03.114995 ENABLE_RX_DCM_DPHY: ON
9176 23:08:03.118046 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9177 23:08:03.118142 DUMMY_READ_FOR_TRACKING: OFF
9178 23:08:03.121518 !!! SPM_CONTROL_AFTERK: OFF
9179 23:08:03.125439 !!! SPM could not control APHY
9180 23:08:03.128406 IMPEDANCE_TRACKING: ON
9181 23:08:03.128518 TEMP_SENSOR: ON
9182 23:08:03.132115 HW_SAVE_FOR_SR: OFF
9183 23:08:03.134721 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9184 23:08:03.137935 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9185 23:08:03.138054 Read ODT Tracking: ON
9186 23:08:03.141479 Refresh Rate DeBounce: ON
9187 23:08:03.144857 DFS_NO_QUEUE_FLUSH: ON
9188 23:08:03.148156 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9189 23:08:03.148249 ENABLE_DFS_RUNTIME_MRW: OFF
9190 23:08:03.151430 DDR_RESERVE_NEW_MODE: ON
9191 23:08:03.154742 MR_CBT_SWITCH_FREQ: ON
9192 23:08:03.154849 =========================
9193 23:08:03.174666 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9194 23:08:03.177826 dram_init: ddr_geometry: 2
9195 23:08:03.195933 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9196 23:08:03.199440 dram_init: dram init end (result: 0)
9197 23:08:03.206443 DRAM-K: Full calibration passed in 24529 msecs
9198 23:08:03.209318 MRC: failed to locate region type 0.
9199 23:08:03.209426 DRAM rank0 size:0x100000000,
9200 23:08:03.212884 DRAM rank1 size=0x100000000
9201 23:08:03.222532 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9202 23:08:03.229454 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9203 23:08:03.236239 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9204 23:08:03.242814 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9205 23:08:03.246132 DRAM rank0 size:0x100000000,
9206 23:08:03.249489 DRAM rank1 size=0x100000000
9207 23:08:03.249590 CBMEM:
9208 23:08:03.252875 IMD: root @ 0xfffff000 254 entries.
9209 23:08:03.256262 IMD: root @ 0xffffec00 62 entries.
9210 23:08:03.259584 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9211 23:08:03.262832 WARNING: RO_VPD is uninitialized or empty.
9212 23:08:03.269346 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9213 23:08:03.276009 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9214 23:08:03.288701 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9215 23:08:03.300379 BS: romstage times (exec / console): total (unknown) / 24024 ms
9216 23:08:03.300486
9217 23:08:03.300584
9218 23:08:03.310364 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9219 23:08:03.313461 ARM64: Exception handlers installed.
9220 23:08:03.316985 ARM64: Testing exception
9221 23:08:03.320289 ARM64: Done test exception
9222 23:08:03.320401 Enumerating buses...
9223 23:08:03.323435 Show all devs... Before device enumeration.
9224 23:08:03.326884 Root Device: enabled 1
9225 23:08:03.330026 CPU_CLUSTER: 0: enabled 1
9226 23:08:03.330113 CPU: 00: enabled 1
9227 23:08:03.333581 Compare with tree...
9228 23:08:03.333683 Root Device: enabled 1
9229 23:08:03.336845 CPU_CLUSTER: 0: enabled 1
9230 23:08:03.340203 CPU: 00: enabled 1
9231 23:08:03.340303 Root Device scanning...
9232 23:08:03.343464 scan_static_bus for Root Device
9233 23:08:03.346822 CPU_CLUSTER: 0 enabled
9234 23:08:03.350201 scan_static_bus for Root Device done
9235 23:08:03.353404 scan_bus: bus Root Device finished in 8 msecs
9236 23:08:03.353504 done
9237 23:08:03.360072 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9238 23:08:03.363389 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9239 23:08:03.370294 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9240 23:08:03.373634 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9241 23:08:03.377027 Allocating resources...
9242 23:08:03.377109 Reading resources...
9243 23:08:03.383409 Root Device read_resources bus 0 link: 0
9244 23:08:03.383492 DRAM rank0 size:0x100000000,
9245 23:08:03.386985 DRAM rank1 size=0x100000000
9246 23:08:03.390414 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9247 23:08:03.393403 CPU: 00 missing read_resources
9248 23:08:03.396779 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9249 23:08:03.403292 Root Device read_resources bus 0 link: 0 done
9250 23:08:03.403374 Done reading resources.
9251 23:08:03.410039 Show resources in subtree (Root Device)...After reading.
9252 23:08:03.413914 Root Device child on link 0 CPU_CLUSTER: 0
9253 23:08:03.416748 CPU_CLUSTER: 0 child on link 0 CPU: 00
9254 23:08:03.426392 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9255 23:08:03.426566 CPU: 00
9256 23:08:03.430395 Root Device assign_resources, bus 0 link: 0
9257 23:08:03.433245 CPU_CLUSTER: 0 missing set_resources
9258 23:08:03.439788 Root Device assign_resources, bus 0 link: 0 done
9259 23:08:03.440003 Done setting resources.
9260 23:08:03.446770 Show resources in subtree (Root Device)...After assigning values.
9261 23:08:03.450144 Root Device child on link 0 CPU_CLUSTER: 0
9262 23:08:03.453387 CPU_CLUSTER: 0 child on link 0 CPU: 00
9263 23:08:03.463266 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9264 23:08:03.463654 CPU: 00
9265 23:08:03.466871 Done allocating resources.
9266 23:08:03.470153 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9267 23:08:03.473344 Enabling resources...
9268 23:08:03.473915 done.
9269 23:08:03.479940 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9270 23:08:03.480508 Initializing devices...
9271 23:08:03.483257 Root Device init
9272 23:08:03.483820 init hardware done!
9273 23:08:03.486559 0x00000018: ctrlr->caps
9274 23:08:03.489804 52.000 MHz: ctrlr->f_max
9275 23:08:03.490436 0.400 MHz: ctrlr->f_min
9276 23:08:03.493358 0x40ff8080: ctrlr->voltages
9277 23:08:03.493835 sclk: 390625
9278 23:08:03.496561 Bus Width = 1
9279 23:08:03.497131 sclk: 390625
9280 23:08:03.499736 Bus Width = 1
9281 23:08:03.500310 Early init status = 3
9282 23:08:03.506459 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9283 23:08:03.509654 in-header: 03 fc 00 00 01 00 00 00
9284 23:08:03.512983 in-data: 00
9285 23:08:03.516095 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9286 23:08:03.521814 in-header: 03 fd 00 00 00 00 00 00
9287 23:08:03.525448 in-data:
9288 23:08:03.528325 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9289 23:08:03.532651 in-header: 03 fc 00 00 01 00 00 00
9290 23:08:03.536271 in-data: 00
9291 23:08:03.539175 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9292 23:08:03.545332 in-header: 03 fd 00 00 00 00 00 00
9293 23:08:03.548569 in-data:
9294 23:08:03.551669 [SSUSB] Setting up USB HOST controller...
9295 23:08:03.555096 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9296 23:08:03.558207 [SSUSB] phy power-on done.
9297 23:08:03.561722 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9298 23:08:03.568429 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9299 23:08:03.571689 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9300 23:08:03.578487 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9301 23:08:03.585106 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9302 23:08:03.591965 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9303 23:08:03.598522 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9304 23:08:03.605022 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9305 23:08:03.605608 SPM: binary array size = 0x9dc
9306 23:08:03.611301 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9307 23:08:03.618130 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9308 23:08:03.625063 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9309 23:08:03.628305 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9310 23:08:03.631386 configure_display: Starting display init
9311 23:08:03.668740 anx7625_power_on_init: Init interface.
9312 23:08:03.672025 anx7625_disable_pd_protocol: Disabled PD feature.
9313 23:08:03.674744 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9314 23:08:03.702863 anx7625_start_dp_work: Secure OCM version=00
9315 23:08:03.706012 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9316 23:08:03.720626 sp_tx_get_edid_block: EDID Block = 1
9317 23:08:03.823210 Extracted contents:
9318 23:08:03.826367 header: 00 ff ff ff ff ff ff 00
9319 23:08:03.829659 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9320 23:08:03.833182 version: 01 04
9321 23:08:03.836818 basic params: 95 1f 11 78 0a
9322 23:08:03.839716 chroma info: 76 90 94 55 54 90 27 21 50 54
9323 23:08:03.843139 established: 00 00 00
9324 23:08:03.849792 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9325 23:08:03.853014 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9326 23:08:03.859697 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9327 23:08:03.866451 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9328 23:08:03.873030 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9329 23:08:03.876057 extensions: 00
9330 23:08:03.876521 checksum: fb
9331 23:08:03.876891
9332 23:08:03.879386 Manufacturer: IVO Model 57d Serial Number 0
9333 23:08:03.882662 Made week 0 of 2020
9334 23:08:03.883125 EDID version: 1.4
9335 23:08:03.886421 Digital display
9336 23:08:03.889241 6 bits per primary color channel
9337 23:08:03.889711 DisplayPort interface
9338 23:08:03.892862 Maximum image size: 31 cm x 17 cm
9339 23:08:03.896354 Gamma: 220%
9340 23:08:03.896812 Check DPMS levels
9341 23:08:03.899258 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9342 23:08:03.903049 First detailed timing is preferred timing
9343 23:08:03.906477 Established timings supported:
9344 23:08:03.909434 Standard timings supported:
9345 23:08:03.913027 Detailed timings
9346 23:08:03.915913 Hex of detail: 383680a07038204018303c0035ae10000019
9347 23:08:03.919579 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9348 23:08:03.925990 0780 0798 07c8 0820 hborder 0
9349 23:08:03.929426 0438 043b 0447 0458 vborder 0
9350 23:08:03.932887 -hsync -vsync
9351 23:08:03.933344 Did detailed timing
9352 23:08:03.936661 Hex of detail: 000000000000000000000000000000000000
9353 23:08:03.939376 Manufacturer-specified data, tag 0
9354 23:08:03.945925 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9355 23:08:03.946498 ASCII string: InfoVision
9356 23:08:03.952916 Hex of detail: 000000fe00523134304e574635205248200a
9357 23:08:03.956318 ASCII string: R140NWF5 RH
9358 23:08:03.956909 Checksum
9359 23:08:03.957295 Checksum: 0xfb (valid)
9360 23:08:03.962880 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9361 23:08:03.966090 DSI data_rate: 832800000 bps
9362 23:08:03.972780 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9363 23:08:03.976252 anx7625_parse_edid: pixelclock(138800).
9364 23:08:03.979135 hactive(1920), hsync(48), hfp(24), hbp(88)
9365 23:08:03.982894 vactive(1080), vsync(12), vfp(3), vbp(17)
9366 23:08:03.986321 anx7625_dsi_config: config dsi.
9367 23:08:03.992627 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9368 23:08:04.005677 anx7625_dsi_config: success to config DSI
9369 23:08:04.008975 anx7625_dp_start: MIPI phy setup OK.
9370 23:08:04.012087 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9371 23:08:04.015408 mtk_ddp_mode_set invalid vrefresh 60
9372 23:08:04.018728 main_disp_path_setup
9373 23:08:04.019290 ovl_layer_smi_id_en
9374 23:08:04.022113 ovl_layer_smi_id_en
9375 23:08:04.022689 ccorr_config
9376 23:08:04.023054 aal_config
9377 23:08:04.025401 gamma_config
9378 23:08:04.025998 postmask_config
9379 23:08:04.028511 dither_config
9380 23:08:04.032091 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9381 23:08:04.038726 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9382 23:08:04.042126 Root Device init finished in 555 msecs
9383 23:08:04.042682 CPU_CLUSTER: 0 init
9384 23:08:04.051722 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9385 23:08:04.055324 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9386 23:08:04.058619 APU_MBOX 0x190000b0 = 0x10001
9387 23:08:04.061818 APU_MBOX 0x190001b0 = 0x10001
9388 23:08:04.065296 APU_MBOX 0x190005b0 = 0x10001
9389 23:08:04.068560 APU_MBOX 0x190006b0 = 0x10001
9390 23:08:04.072085 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9391 23:08:04.084732 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9392 23:08:04.096938 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9393 23:08:04.103556 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9394 23:08:04.115112 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9395 23:08:04.124066 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9396 23:08:04.127739 CPU_CLUSTER: 0 init finished in 81 msecs
9397 23:08:04.130845 Devices initialized
9398 23:08:04.134081 Show all devs... After init.
9399 23:08:04.134575 Root Device: enabled 1
9400 23:08:04.137500 CPU_CLUSTER: 0: enabled 1
9401 23:08:04.141200 CPU: 00: enabled 1
9402 23:08:04.144255 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9403 23:08:04.147405 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9404 23:08:04.150860 ELOG: NV offset 0x57f000 size 0x1000
9405 23:08:04.157529 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9406 23:08:04.163982 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9407 23:08:04.167265 ELOG: Event(17) added with size 13 at 2023-12-27 23:07:27 UTC
9408 23:08:04.170719 out: cmd=0x121: 03 db 21 01 00 00 00 00
9409 23:08:04.174422 in-header: 03 18 00 00 2c 00 00 00
9410 23:08:04.188007 in-data: 47 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9411 23:08:04.194390 ELOG: Event(A1) added with size 10 at 2023-12-27 23:07:27 UTC
9412 23:08:04.201149 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9413 23:08:04.207386 ELOG: Event(A0) added with size 9 at 2023-12-27 23:07:27 UTC
9414 23:08:04.210862 elog_add_boot_reason: Logged dev mode boot
9415 23:08:04.213877 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9416 23:08:04.217985 Finalize devices...
9417 23:08:04.218562 Devices finalized
9418 23:08:04.224495 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9419 23:08:04.227833 Writing coreboot table at 0xffe64000
9420 23:08:04.231008 0. 000000000010a000-0000000000113fff: RAMSTAGE
9421 23:08:04.234540 1. 0000000040000000-00000000400fffff: RAM
9422 23:08:04.237608 2. 0000000040100000-000000004032afff: RAMSTAGE
9423 23:08:04.244544 3. 000000004032b000-00000000545fffff: RAM
9424 23:08:04.247427 4. 0000000054600000-000000005465ffff: BL31
9425 23:08:04.250746 5. 0000000054660000-00000000ffe63fff: RAM
9426 23:08:04.257428 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9427 23:08:04.260778 7. 0000000100000000-000000023fffffff: RAM
9428 23:08:04.261246 Passing 5 GPIOs to payload:
9429 23:08:04.267340 NAME | PORT | POLARITY | VALUE
9430 23:08:04.270478 EC in RW | 0x000000aa | low | undefined
9431 23:08:04.277686 EC interrupt | 0x00000005 | low | undefined
9432 23:08:04.280617 TPM interrupt | 0x000000ab | high | undefined
9433 23:08:04.284000 SD card detect | 0x00000011 | high | undefined
9434 23:08:04.291102 speaker enable | 0x00000093 | high | undefined
9435 23:08:04.294301 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9436 23:08:04.297573 in-header: 03 f9 00 00 02 00 00 00
9437 23:08:04.298185 in-data: 02 00
9438 23:08:04.300413 ADC[4]: Raw value=901032 ID=7
9439 23:08:04.303928 ADC[3]: Raw value=212810 ID=1
9440 23:08:04.304403 RAM Code: 0x71
9441 23:08:04.307260 ADC[6]: Raw value=74502 ID=0
9442 23:08:04.310385 ADC[5]: Raw value=212441 ID=1
9443 23:08:04.310960 SKU Code: 0x1
9444 23:08:04.317379 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9532
9445 23:08:04.320663 coreboot table: 964 bytes.
9446 23:08:04.323805 IMD ROOT 0. 0xfffff000 0x00001000
9447 23:08:04.327195 IMD SMALL 1. 0xffffe000 0x00001000
9448 23:08:04.330607 RO MCACHE 2. 0xffffc000 0x00001104
9449 23:08:04.333859 CONSOLE 3. 0xfff7c000 0x00080000
9450 23:08:04.337163 FMAP 4. 0xfff7b000 0x00000452
9451 23:08:04.340746 TIME STAMP 5. 0xfff7a000 0x00000910
9452 23:08:04.344019 VBOOT WORK 6. 0xfff66000 0x00014000
9453 23:08:04.346876 RAMOOPS 7. 0xffe66000 0x00100000
9454 23:08:04.350296 COREBOOT 8. 0xffe64000 0x00002000
9455 23:08:04.350866 IMD small region:
9456 23:08:04.353612 IMD ROOT 0. 0xffffec00 0x00000400
9457 23:08:04.357065 VPD 1. 0xffffeb80 0x0000006c
9458 23:08:04.360234 MMC STATUS 2. 0xffffeb60 0x00000004
9459 23:08:04.366696 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9460 23:08:04.370125 Probing TPM: done!
9461 23:08:04.373597 Connected to device vid:did:rid of 1ae0:0028:00
9462 23:08:04.383680 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9463 23:08:04.387006 Initialized TPM device CR50 revision 0
9464 23:08:04.390922 Checking cr50 for pending updates
9465 23:08:04.394306 Reading cr50 TPM mode
9466 23:08:04.402800 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9467 23:08:04.409327 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9468 23:08:04.449521 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9469 23:08:04.452639 Checking segment from ROM address 0x40100000
9470 23:08:04.455848 Checking segment from ROM address 0x4010001c
9471 23:08:04.462746 Loading segment from ROM address 0x40100000
9472 23:08:04.463317 code (compression=0)
9473 23:08:04.469420 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9474 23:08:04.479371 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9475 23:08:04.479961 it's not compressed!
9476 23:08:04.486213 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9477 23:08:04.489385 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9478 23:08:04.509758 Loading segment from ROM address 0x4010001c
9479 23:08:04.510403 Entry Point 0x80000000
9480 23:08:04.513018 Loaded segments
9481 23:08:04.516304 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9482 23:08:04.520409 Jumping to boot code at 0x80000000(0xffe64000)
9483 23:08:04.530072 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9484 23:08:04.536572 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9485 23:08:04.544028 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9486 23:08:04.547428 Checking segment from ROM address 0x40100000
9487 23:08:04.550618 Checking segment from ROM address 0x4010001c
9488 23:08:04.557620 Loading segment from ROM address 0x40100000
9489 23:08:04.558262 code (compression=1)
9490 23:08:04.564187 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9491 23:08:04.574001 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9492 23:08:04.574586 using LZMA
9493 23:08:04.583151 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9494 23:08:04.589559 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9495 23:08:04.592773 Loading segment from ROM address 0x4010001c
9496 23:08:04.593339 Entry Point 0x54601000
9497 23:08:04.595923 Loaded segments
9498 23:08:04.598962 NOTICE: MT8192 bl31_setup
9499 23:08:04.606248 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9500 23:08:04.609753 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9501 23:08:04.612657 WARNING: region 0:
9502 23:08:04.615954 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9503 23:08:04.616422 WARNING: region 1:
9504 23:08:04.622682 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9505 23:08:04.626137 WARNING: region 2:
9506 23:08:04.629652 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9507 23:08:04.633208 WARNING: region 3:
9508 23:08:04.636437 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9509 23:08:04.639479 WARNING: region 4:
9510 23:08:04.642892 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9511 23:08:04.646385 WARNING: region 5:
9512 23:08:04.649577 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9513 23:08:04.652938 WARNING: region 6:
9514 23:08:04.656586 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9515 23:08:04.657161 WARNING: region 7:
9516 23:08:04.662965 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9517 23:08:04.669992 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9518 23:08:04.673011 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9519 23:08:04.676198 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9520 23:08:04.683052 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9521 23:08:04.686655 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9522 23:08:04.689569 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9523 23:08:04.696401 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9524 23:08:04.699580 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9525 23:08:04.702991 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9526 23:08:04.709470 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9527 23:08:04.712961 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9528 23:08:04.719282 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9529 23:08:04.722559 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9530 23:08:04.726099 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9531 23:08:04.732982 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9532 23:08:04.736411 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9533 23:08:04.739396 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9534 23:08:04.746358 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9535 23:08:04.749641 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9536 23:08:04.756144 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9537 23:08:04.759579 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9538 23:08:04.762680 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9539 23:08:04.769975 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9540 23:08:04.773222 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9541 23:08:04.779515 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9542 23:08:04.783155 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9543 23:08:04.786634 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9544 23:08:04.793225 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9545 23:08:04.796357 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9546 23:08:04.799781 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9547 23:08:04.806415 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9548 23:08:04.809970 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9549 23:08:04.813179 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9550 23:08:04.819609 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9551 23:08:04.822998 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9552 23:08:04.826480 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9553 23:08:04.829784 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9554 23:08:04.836622 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9555 23:08:04.839781 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9556 23:08:04.843089 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9557 23:08:04.846480 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9558 23:08:04.852865 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9559 23:08:04.856197 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9560 23:08:04.859602 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9561 23:08:04.862895 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9562 23:08:04.869882 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9563 23:08:04.873266 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9564 23:08:04.876577 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9565 23:08:04.883540 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9566 23:08:04.886672 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9567 23:08:04.890191 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9568 23:08:04.896773 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9569 23:08:04.900151 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9570 23:08:04.906618 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9571 23:08:04.909707 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9572 23:08:04.913296 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9573 23:08:04.920275 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9574 23:08:04.923869 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9575 23:08:04.930103 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9576 23:08:04.933803 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9577 23:08:04.940464 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9578 23:08:04.943604 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9579 23:08:04.950185 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9580 23:08:04.953379 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9581 23:08:04.957019 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9582 23:08:04.963354 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9583 23:08:04.966713 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9584 23:08:04.973607 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9585 23:08:04.976889 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9586 23:08:04.983519 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9587 23:08:04.986846 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9588 23:08:04.990315 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9589 23:08:04.997412 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9590 23:08:05.000459 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9591 23:08:05.006821 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9592 23:08:05.010280 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9593 23:08:05.016713 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9594 23:08:05.020493 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9595 23:08:05.023178 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9596 23:08:05.030252 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9597 23:08:05.033452 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9598 23:08:05.040083 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9599 23:08:05.043529 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9600 23:08:05.050277 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9601 23:08:05.053704 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9602 23:08:05.057013 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9603 23:08:05.063681 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9604 23:08:05.067131 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9605 23:08:05.073821 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9606 23:08:05.077136 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9607 23:08:05.083677 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9608 23:08:05.086857 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9609 23:08:05.090367 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9610 23:08:05.096898 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9611 23:08:05.100621 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9612 23:08:05.106719 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9613 23:08:05.110524 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9614 23:08:05.113614 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9615 23:08:05.116990 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9616 23:08:05.123822 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9617 23:08:05.127023 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9618 23:08:05.130253 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9619 23:08:05.136941 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9620 23:08:05.140302 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9621 23:08:05.146650 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9622 23:08:05.150100 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9623 23:08:05.153473 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9624 23:08:05.160369 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9625 23:08:05.163309 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9626 23:08:05.169659 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9627 23:08:05.173364 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9628 23:08:05.176713 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9629 23:08:05.183320 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9630 23:08:05.186724 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9631 23:08:05.189964 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9632 23:08:05.196816 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9633 23:08:05.199848 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9634 23:08:05.203364 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9635 23:08:05.210181 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9636 23:08:05.213103 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9637 23:08:05.216661 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9638 23:08:05.219801 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9639 23:08:05.226961 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9640 23:08:05.230159 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9641 23:08:05.233214 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9642 23:08:05.239940 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9643 23:08:05.243138 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9644 23:08:05.249892 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9645 23:08:05.253157 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9646 23:08:05.256453 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9647 23:08:05.263060 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9648 23:08:05.266709 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9649 23:08:05.269749 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9650 23:08:05.276703 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9651 23:08:05.279757 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9652 23:08:05.286702 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9653 23:08:05.289836 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9654 23:08:05.293207 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9655 23:08:05.300255 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9656 23:08:05.303364 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9657 23:08:05.306391 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9658 23:08:05.313554 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9659 23:08:05.316482 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9660 23:08:05.323190 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9661 23:08:05.326550 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9662 23:08:05.330113 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9663 23:08:05.336599 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9664 23:08:05.340292 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9665 23:08:05.346766 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9666 23:08:05.349868 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9667 23:08:05.353428 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9668 23:08:05.359816 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9669 23:08:05.363210 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9670 23:08:05.366615 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9671 23:08:05.373242 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9672 23:08:05.376743 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9673 23:08:05.383397 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9674 23:08:05.386593 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9675 23:08:05.389795 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9676 23:08:05.397216 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9677 23:08:05.400112 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9678 23:08:05.406773 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9679 23:08:05.409904 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9680 23:08:05.413313 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9681 23:08:05.420178 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9682 23:08:05.423406 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9683 23:08:05.426562 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9684 23:08:05.433254 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9685 23:08:05.436924 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9686 23:08:05.443200 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9687 23:08:05.446486 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9688 23:08:05.449887 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9689 23:08:05.456532 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9690 23:08:05.459861 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9691 23:08:05.466909 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9692 23:08:05.469864 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9693 23:08:05.473067 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9694 23:08:05.480194 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9695 23:08:05.483265 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9696 23:08:05.486316 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9697 23:08:05.493260 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9698 23:08:05.496649 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9699 23:08:05.503816 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9700 23:08:05.507154 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9701 23:08:05.509919 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9702 23:08:05.516456 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9703 23:08:05.519966 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9704 23:08:05.526718 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9705 23:08:05.530011 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9706 23:08:05.533377 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9707 23:08:05.540491 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9708 23:08:05.543406 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9709 23:08:05.550660 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9710 23:08:05.553567 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9711 23:08:05.560105 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9712 23:08:05.563671 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9713 23:08:05.566714 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9714 23:08:05.573441 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9715 23:08:05.576725 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9716 23:08:05.583486 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9717 23:08:05.586402 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9718 23:08:05.589860 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9719 23:08:05.596713 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9720 23:08:05.600351 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9721 23:08:05.606512 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9722 23:08:05.609657 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9723 23:08:05.615937 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9724 23:08:05.619731 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9725 23:08:05.622583 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9726 23:08:05.629491 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9727 23:08:05.632883 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9728 23:08:05.639222 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9729 23:08:05.642589 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9730 23:08:05.646304 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9731 23:08:05.652897 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9732 23:08:05.656298 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9733 23:08:05.663065 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9734 23:08:05.666401 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9735 23:08:05.673071 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9736 23:08:05.676088 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9737 23:08:05.679682 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9738 23:08:05.685978 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9739 23:08:05.689819 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9740 23:08:05.696299 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9741 23:08:05.699244 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9742 23:08:05.705506 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9743 23:08:05.709095 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9744 23:08:05.712310 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9745 23:08:05.718669 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9746 23:08:05.721990 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9747 23:08:05.725704 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9748 23:08:05.729086 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9749 23:08:05.735462 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9750 23:08:05.738976 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9751 23:08:05.742059 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9752 23:08:05.748877 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9753 23:08:05.752101 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9754 23:08:05.758919 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9755 23:08:05.761965 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9756 23:08:05.765183 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9757 23:08:05.771547 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9758 23:08:05.774985 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9759 23:08:05.778019 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9760 23:08:05.784936 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9761 23:08:05.788247 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9762 23:08:05.791460 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9763 23:08:05.798297 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9764 23:08:05.801951 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9765 23:08:05.805016 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9766 23:08:05.811766 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9767 23:08:05.814897 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9768 23:08:05.821562 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9769 23:08:05.824690 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9770 23:08:05.828186 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9771 23:08:05.835198 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9772 23:08:05.838537 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9773 23:08:05.842081 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9774 23:08:05.848078 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9775 23:08:05.851584 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9776 23:08:05.855204 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9777 23:08:05.861261 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9778 23:08:05.865018 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9779 23:08:05.871225 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9780 23:08:05.874737 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9781 23:08:05.877664 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9782 23:08:05.884441 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9783 23:08:05.887957 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9784 23:08:05.891007 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9785 23:08:05.897504 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9786 23:08:05.901214 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9787 23:08:05.904492 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9788 23:08:05.907788 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9789 23:08:05.914350 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9790 23:08:05.917679 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9791 23:08:05.920943 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9792 23:08:05.924438 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9793 23:08:05.930749 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9794 23:08:05.934541 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9795 23:08:05.937531 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9796 23:08:05.940919 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9797 23:08:05.947442 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9798 23:08:05.951117 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9799 23:08:05.954626 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9800 23:08:05.960921 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9801 23:08:05.964183 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9802 23:08:05.971083 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9803 23:08:05.973919 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9804 23:08:05.977291 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9805 23:08:05.983927 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9806 23:08:05.987583 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9807 23:08:05.994097 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9808 23:08:05.997162 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9809 23:08:06.000935 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9810 23:08:06.007475 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9811 23:08:06.011018 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9812 23:08:06.017478 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9813 23:08:06.020511 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9814 23:08:06.024157 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9815 23:08:06.030634 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9816 23:08:06.033854 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9817 23:08:06.040546 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9818 23:08:06.043934 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9819 23:08:06.050344 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9820 23:08:06.053836 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9821 23:08:06.057174 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9822 23:08:06.063611 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9823 23:08:06.067042 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9824 23:08:06.073692 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9825 23:08:06.077173 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9826 23:08:06.080487 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9827 23:08:06.086862 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9828 23:08:06.090681 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9829 23:08:06.097145 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9830 23:08:06.100587 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9831 23:08:06.103961 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9832 23:08:06.110303 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9833 23:08:06.113528 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9834 23:08:06.120143 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9835 23:08:06.123881 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9836 23:08:06.130541 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9837 23:08:06.133521 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9838 23:08:06.137007 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9839 23:08:06.143592 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9840 23:08:06.146513 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9841 23:08:06.153264 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9842 23:08:06.156551 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9843 23:08:06.159779 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9844 23:08:06.166726 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9845 23:08:06.170083 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9846 23:08:06.173370 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9847 23:08:06.179853 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9848 23:08:06.183379 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9849 23:08:06.190099 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9850 23:08:06.193319 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9851 23:08:06.200119 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9852 23:08:06.202991 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9853 23:08:06.206436 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9854 23:08:06.213143 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9855 23:08:06.216749 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9856 23:08:06.223312 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9857 23:08:06.226808 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9858 23:08:06.229825 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9859 23:08:06.236860 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9860 23:08:06.240027 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9861 23:08:06.246488 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9862 23:08:06.249874 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9863 23:08:06.253395 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9864 23:08:06.260310 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9865 23:08:06.263549 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9866 23:08:06.270307 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9867 23:08:06.273390 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9868 23:08:06.280601 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9869 23:08:06.283487 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9870 23:08:06.286849 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9871 23:08:06.293816 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9872 23:08:06.296948 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9873 23:08:06.303476 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9874 23:08:06.306887 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9875 23:08:06.313609 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9876 23:08:06.316513 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9877 23:08:06.319911 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9878 23:08:06.326618 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9879 23:08:06.329986 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9880 23:08:06.336833 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9881 23:08:06.339946 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9882 23:08:06.346700 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9883 23:08:06.349838 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9884 23:08:06.353270 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9885 23:08:06.359654 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9886 23:08:06.363197 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9887 23:08:06.370160 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9888 23:08:06.373457 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9889 23:08:06.379909 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9890 23:08:06.383444 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9891 23:08:06.386847 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9892 23:08:06.393523 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9893 23:08:06.396730 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9894 23:08:06.403081 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9895 23:08:06.406384 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9896 23:08:06.413198 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9897 23:08:06.416568 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9898 23:08:06.419547 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9899 23:08:06.426507 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9900 23:08:06.429770 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9901 23:08:06.436404 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9902 23:08:06.439850 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9903 23:08:06.446129 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9904 23:08:06.449422 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9905 23:08:06.452961 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9906 23:08:06.459535 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9907 23:08:06.462880 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9908 23:08:06.469776 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9909 23:08:06.473194 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9910 23:08:06.479714 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9911 23:08:06.483131 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9912 23:08:06.486348 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9913 23:08:06.493378 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9914 23:08:06.496199 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9915 23:08:06.502938 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9916 23:08:06.506601 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9917 23:08:06.512914 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9918 23:08:06.516413 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9919 23:08:06.519583 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9920 23:08:06.526434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9921 23:08:06.529427 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9922 23:08:06.536693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9923 23:08:06.539325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9924 23:08:06.545933 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9925 23:08:06.549694 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9926 23:08:06.556123 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9927 23:08:06.559369 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9928 23:08:06.566017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9929 23:08:06.569421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9930 23:08:06.572711 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9931 23:08:06.579466 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9932 23:08:06.582794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9933 23:08:06.589245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9934 23:08:06.592986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9935 23:08:06.599494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9936 23:08:06.602871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9937 23:08:06.609614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9938 23:08:06.612388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9939 23:08:06.619346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9940 23:08:06.622551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9941 23:08:06.629294 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9942 23:08:06.632818 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9943 23:08:06.639171 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9944 23:08:06.642695 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9945 23:08:06.649329 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9946 23:08:06.652676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9947 23:08:06.658968 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9948 23:08:06.662411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9949 23:08:06.669283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9950 23:08:06.672570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9951 23:08:06.679395 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9952 23:08:06.679966 INFO: [APUAPC] vio 0
9953 23:08:06.685701 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9954 23:08:06.689056 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9955 23:08:06.692339 INFO: [APUAPC] D0_APC_0: 0x400510
9956 23:08:06.695993 INFO: [APUAPC] D0_APC_1: 0x0
9957 23:08:06.698944 INFO: [APUAPC] D0_APC_2: 0x1540
9958 23:08:06.702626 INFO: [APUAPC] D0_APC_3: 0x0
9959 23:08:06.705895 INFO: [APUAPC] D1_APC_0: 0xffffffff
9960 23:08:06.709135 INFO: [APUAPC] D1_APC_1: 0xffffffff
9961 23:08:06.712506 INFO: [APUAPC] D1_APC_2: 0x3fffff
9962 23:08:06.715686 INFO: [APUAPC] D1_APC_3: 0x0
9963 23:08:06.718629 INFO: [APUAPC] D2_APC_0: 0xffffffff
9964 23:08:06.722050 INFO: [APUAPC] D2_APC_1: 0xffffffff
9965 23:08:06.726131 INFO: [APUAPC] D2_APC_2: 0x3fffff
9966 23:08:06.729439 INFO: [APUAPC] D2_APC_3: 0x0
9967 23:08:06.732620 INFO: [APUAPC] D3_APC_0: 0xffffffff
9968 23:08:06.735947 INFO: [APUAPC] D3_APC_1: 0xffffffff
9969 23:08:06.738956 INFO: [APUAPC] D3_APC_2: 0x3fffff
9970 23:08:06.739542 INFO: [APUAPC] D3_APC_3: 0x0
9971 23:08:06.745719 INFO: [APUAPC] D4_APC_0: 0xffffffff
9972 23:08:06.749124 INFO: [APUAPC] D4_APC_1: 0xffffffff
9973 23:08:06.752632 INFO: [APUAPC] D4_APC_2: 0x3fffff
9974 23:08:06.753206 INFO: [APUAPC] D4_APC_3: 0x0
9975 23:08:06.755940 INFO: [APUAPC] D5_APC_0: 0xffffffff
9976 23:08:06.758635 INFO: [APUAPC] D5_APC_1: 0xffffffff
9977 23:08:06.762249 INFO: [APUAPC] D5_APC_2: 0x3fffff
9978 23:08:06.765673 INFO: [APUAPC] D5_APC_3: 0x0
9979 23:08:06.768937 INFO: [APUAPC] D6_APC_0: 0xffffffff
9980 23:08:06.772244 INFO: [APUAPC] D6_APC_1: 0xffffffff
9981 23:08:06.775649 INFO: [APUAPC] D6_APC_2: 0x3fffff
9982 23:08:06.778858 INFO: [APUAPC] D6_APC_3: 0x0
9983 23:08:06.782593 INFO: [APUAPC] D7_APC_0: 0xffffffff
9984 23:08:06.785867 INFO: [APUAPC] D7_APC_1: 0xffffffff
9985 23:08:06.788758 INFO: [APUAPC] D7_APC_2: 0x3fffff
9986 23:08:06.792290 INFO: [APUAPC] D7_APC_3: 0x0
9987 23:08:06.795471 INFO: [APUAPC] D8_APC_0: 0xffffffff
9988 23:08:06.798874 INFO: [APUAPC] D8_APC_1: 0xffffffff
9989 23:08:06.802483 INFO: [APUAPC] D8_APC_2: 0x3fffff
9990 23:08:06.805735 INFO: [APUAPC] D8_APC_3: 0x0
9991 23:08:06.809117 INFO: [APUAPC] D9_APC_0: 0xffffffff
9992 23:08:06.812598 INFO: [APUAPC] D9_APC_1: 0xffffffff
9993 23:08:06.815940 INFO: [APUAPC] D9_APC_2: 0x3fffff
9994 23:08:06.818629 INFO: [APUAPC] D9_APC_3: 0x0
9995 23:08:06.821969 INFO: [APUAPC] D10_APC_0: 0xffffffff
9996 23:08:06.826116 INFO: [APUAPC] D10_APC_1: 0xffffffff
9997 23:08:06.829316 INFO: [APUAPC] D10_APC_2: 0x3fffff
9998 23:08:06.832620 INFO: [APUAPC] D10_APC_3: 0x0
9999 23:08:06.835480 INFO: [APUAPC] D11_APC_0: 0xffffffff
10000 23:08:06.838846 INFO: [APUAPC] D11_APC_1: 0xffffffff
10001 23:08:06.841919 INFO: [APUAPC] D11_APC_2: 0x3fffff
10002 23:08:06.845523 INFO: [APUAPC] D11_APC_3: 0x0
10003 23:08:06.848952 INFO: [APUAPC] D12_APC_0: 0xffffffff
10004 23:08:06.852269 INFO: [APUAPC] D12_APC_1: 0xffffffff
10005 23:08:06.855339 INFO: [APUAPC] D12_APC_2: 0x3fffff
10006 23:08:06.858567 INFO: [APUAPC] D12_APC_3: 0x0
10007 23:08:06.862080 INFO: [APUAPC] D13_APC_0: 0xffffffff
10008 23:08:06.865050 INFO: [APUAPC] D13_APC_1: 0xffffffff
10009 23:08:06.868618 INFO: [APUAPC] D13_APC_2: 0x3fffff
10010 23:08:06.871986 INFO: [APUAPC] D13_APC_3: 0x0
10011 23:08:06.875123 INFO: [APUAPC] D14_APC_0: 0xffffffff
10012 23:08:06.878683 INFO: [APUAPC] D14_APC_1: 0xffffffff
10013 23:08:06.882060 INFO: [APUAPC] D14_APC_2: 0x3fffff
10014 23:08:06.885313 INFO: [APUAPC] D14_APC_3: 0x0
10015 23:08:06.888405 INFO: [APUAPC] D15_APC_0: 0xffffffff
10016 23:08:06.891748 INFO: [APUAPC] D15_APC_1: 0xffffffff
10017 23:08:06.895315 INFO: [APUAPC] D15_APC_2: 0x3fffff
10018 23:08:06.898081 INFO: [APUAPC] D15_APC_3: 0x0
10019 23:08:06.901724 INFO: [APUAPC] APC_CON: 0x4
10020 23:08:06.904995 INFO: [NOCDAPC] D0_APC_0: 0x0
10021 23:08:06.908346 INFO: [NOCDAPC] D0_APC_1: 0x0
10022 23:08:06.911605 INFO: [NOCDAPC] D1_APC_0: 0x0
10023 23:08:06.914772 INFO: [NOCDAPC] D1_APC_1: 0xfff
10024 23:08:06.915256 INFO: [NOCDAPC] D2_APC_0: 0x0
10025 23:08:06.918187 INFO: [NOCDAPC] D2_APC_1: 0xfff
10026 23:08:06.921715 INFO: [NOCDAPC] D3_APC_0: 0x0
10027 23:08:06.924663 INFO: [NOCDAPC] D3_APC_1: 0xfff
10028 23:08:06.928221 INFO: [NOCDAPC] D4_APC_0: 0x0
10029 23:08:06.931328 INFO: [NOCDAPC] D4_APC_1: 0xfff
10030 23:08:06.934658 INFO: [NOCDAPC] D5_APC_0: 0x0
10031 23:08:06.938524 INFO: [NOCDAPC] D5_APC_1: 0xfff
10032 23:08:06.941801 INFO: [NOCDAPC] D6_APC_0: 0x0
10033 23:08:06.944403 INFO: [NOCDAPC] D6_APC_1: 0xfff
10034 23:08:06.947813 INFO: [NOCDAPC] D7_APC_0: 0x0
10035 23:08:06.951458 INFO: [NOCDAPC] D7_APC_1: 0xfff
10036 23:08:06.952027 INFO: [NOCDAPC] D8_APC_0: 0x0
10037 23:08:06.954629 INFO: [NOCDAPC] D8_APC_1: 0xfff
10038 23:08:06.957881 INFO: [NOCDAPC] D9_APC_0: 0x0
10039 23:08:06.961406 INFO: [NOCDAPC] D9_APC_1: 0xfff
10040 23:08:06.964130 INFO: [NOCDAPC] D10_APC_0: 0x0
10041 23:08:06.967680 INFO: [NOCDAPC] D10_APC_1: 0xfff
10042 23:08:06.970952 INFO: [NOCDAPC] D11_APC_0: 0x0
10043 23:08:06.974201 INFO: [NOCDAPC] D11_APC_1: 0xfff
10044 23:08:06.977680 INFO: [NOCDAPC] D12_APC_0: 0x0
10045 23:08:06.980796 INFO: [NOCDAPC] D12_APC_1: 0xfff
10046 23:08:06.984298 INFO: [NOCDAPC] D13_APC_0: 0x0
10047 23:08:06.987811 INFO: [NOCDAPC] D13_APC_1: 0xfff
10048 23:08:06.990677 INFO: [NOCDAPC] D14_APC_0: 0x0
10049 23:08:06.994104 INFO: [NOCDAPC] D14_APC_1: 0xfff
10050 23:08:06.994575 INFO: [NOCDAPC] D15_APC_0: 0x0
10051 23:08:06.997560 INFO: [NOCDAPC] D15_APC_1: 0xfff
10052 23:08:07.001155 INFO: [NOCDAPC] APC_CON: 0x4
10053 23:08:07.004114 INFO: [APUAPC] set_apusys_apc done
10054 23:08:07.007665 INFO: [DEVAPC] devapc_init done
10055 23:08:07.014005 INFO: GICv3 without legacy support detected.
10056 23:08:07.017437 INFO: ARM GICv3 driver initialized in EL3
10057 23:08:07.020316 INFO: Maximum SPI INTID supported: 639
10058 23:08:07.023711 INFO: BL31: Initializing runtime services
10059 23:08:07.030485 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10060 23:08:07.033698 INFO: SPM: enable CPC mode
10061 23:08:07.037241 INFO: mcdi ready for mcusys-off-idle and system suspend
10062 23:08:07.044121 INFO: BL31: Preparing for EL3 exit to normal world
10063 23:08:07.047166 INFO: Entry point address = 0x80000000
10064 23:08:07.047738 INFO: SPSR = 0x8
10065 23:08:07.053858
10066 23:08:07.054479
10067 23:08:07.054862
10068 23:08:07.057269 Starting depthcharge on Spherion...
10069 23:08:07.057775
10070 23:08:07.058201 Wipe memory regions:
10071 23:08:07.058618
10072 23:08:07.061131 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10073 23:08:07.061751 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10074 23:08:07.062263 Setting prompt string to ['asurada:']
10075 23:08:07.062725 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10076 23:08:07.063453 [0x00000040000000, 0x00000054600000)
10077 23:08:07.182953
10078 23:08:07.183517 [0x00000054660000, 0x00000080000000)
10079 23:08:07.443077
10080 23:08:07.443747 [0x000000821a7280, 0x000000ffe64000)
10081 23:08:08.187680
10082 23:08:08.187818 [0x00000100000000, 0x00000240000000)
10083 23:08:10.078007
10084 23:08:10.081344 Initializing XHCI USB controller at 0x11200000.
10085 23:08:11.119103
10086 23:08:11.122847 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10087 23:08:11.122948
10088 23:08:11.123016
10089 23:08:11.123078
10090 23:08:11.123359 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10092 23:08:11.223721 asurada: tftpboot 192.168.201.1 12395352/tftp-deploy-70s7j2a6/kernel/image.itb 12395352/tftp-deploy-70s7j2a6/kernel/cmdline
10093 23:08:11.223849 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10094 23:08:11.223933 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10095 23:08:11.228124 tftpboot 192.168.201.1 12395352/tftp-deploy-70s7j2a6/kernel/image.itp-deploy-70s7j2a6/kernel/cmdline
10096 23:08:11.228237
10097 23:08:11.228331 Waiting for link
10098 23:08:11.388672
10099 23:08:11.388787 R8152: Initializing
10100 23:08:11.388859
10101 23:08:11.391752 Version 9 (ocp_data = 6010)
10102 23:08:11.391836
10103 23:08:11.394915 R8152: Done initializing
10104 23:08:11.394999
10105 23:08:11.395065 Adding net device
10106 23:08:13.340465
10107 23:08:13.340613 done.
10108 23:08:13.340701
10109 23:08:13.340766 MAC: 00:e0:4c:72:2d:d6
10110 23:08:13.340827
10111 23:08:13.343678 Sending DHCP discover... done.
10112 23:08:13.343791
10113 23:08:13.347239 Waiting for reply... done.
10114 23:08:13.347324
10115 23:08:13.350315 Sending DHCP request... done.
10116 23:08:13.350388
10117 23:08:13.350451 Waiting for reply... done.
10118 23:08:13.350510
10119 23:08:13.353618 My ip is 192.168.201.21
10120 23:08:13.353687
10121 23:08:13.357376 The DHCP server ip is 192.168.201.1
10122 23:08:13.357448
10123 23:08:13.360420 TFTP server IP predefined by user: 192.168.201.1
10124 23:08:13.360494
10125 23:08:13.366869 Bootfile predefined by user: 12395352/tftp-deploy-70s7j2a6/kernel/image.itb
10126 23:08:13.366945
10127 23:08:13.370437 Sending tftp read request... done.
10128 23:08:13.370511
10129 23:08:13.373808 Waiting for the transfer...
10130 23:08:13.373884
10131 23:08:13.618822 00000000 ################################################################
10132 23:08:13.618953
10133 23:08:13.878405 00080000 ################################################################
10134 23:08:13.878541
10135 23:08:14.143644 00100000 ################################################################
10136 23:08:14.143802
10137 23:08:14.387161 00180000 ################################################################
10138 23:08:14.387319
10139 23:08:14.633393 00200000 ################################################################
10140 23:08:14.633539
10141 23:08:14.884033 00280000 ################################################################
10142 23:08:14.884172
10143 23:08:15.126699 00300000 ################################################################
10144 23:08:15.126842
10145 23:08:15.369376 00380000 ################################################################
10146 23:08:15.369568
10147 23:08:15.612759 00400000 ################################################################
10148 23:08:15.612894
10149 23:08:15.855412 00480000 ################################################################
10150 23:08:15.855550
10151 23:08:16.098484 00500000 ################################################################
10152 23:08:16.098623
10153 23:08:16.339658 00580000 ################################################################
10154 23:08:16.339838
10155 23:08:16.581700 00600000 ################################################################
10156 23:08:16.581849
10157 23:08:16.823308 00680000 ################################################################
10158 23:08:16.823455
10159 23:08:17.067766 00700000 ################################################################
10160 23:08:17.067907
10161 23:08:17.310663 00780000 ################################################################
10162 23:08:17.310798
10163 23:08:17.552249 00800000 ################################################################
10164 23:08:17.552380
10165 23:08:17.792966 00880000 ################################################################
10166 23:08:17.793130
10167 23:08:18.035244 00900000 ################################################################
10168 23:08:18.035375
10169 23:08:18.282355 00980000 ################################################################
10170 23:08:18.282497
10171 23:08:18.526293 00a00000 ################################################################
10172 23:08:18.526430
10173 23:08:18.767348 00a80000 ################################################################
10174 23:08:18.767481
10175 23:08:19.009508 00b00000 ################################################################
10176 23:08:19.009644
10177 23:08:19.251680 00b80000 ################################################################
10178 23:08:19.251812
10179 23:08:19.492711 00c00000 ################################################################
10180 23:08:19.492842
10181 23:08:19.734194 00c80000 ################################################################
10182 23:08:19.734330
10183 23:08:19.974711 00d00000 ################################################################
10184 23:08:19.974845
10185 23:08:20.215797 00d80000 ################################################################
10186 23:08:20.215932
10187 23:08:20.456512 00e00000 ################################################################
10188 23:08:20.456672
10189 23:08:20.698283 00e80000 ################################################################
10190 23:08:20.698418
10191 23:08:20.940243 00f00000 ################################################################
10192 23:08:20.940379
10193 23:08:21.184869 00f80000 ################################################################
10194 23:08:21.185016
10195 23:08:21.427999 01000000 ################################################################
10196 23:08:21.428140
10197 23:08:21.670369 01080000 ################################################################
10198 23:08:21.670539
10199 23:08:21.927790 01100000 ################################################################
10200 23:08:21.927925
10201 23:08:22.176944 01180000 ################################################################
10202 23:08:22.177075
10203 23:08:22.427685 01200000 ################################################################
10204 23:08:22.427851
10205 23:08:22.706130 01280000 ################################################################
10206 23:08:22.706267
10207 23:08:22.976413 01300000 ################################################################
10208 23:08:22.976595
10209 23:08:23.218163 01380000 ################################################################
10210 23:08:23.218338
10211 23:08:23.484340 01400000 ################################################################
10212 23:08:23.484493
10213 23:08:23.783145 01480000 ################################################################
10214 23:08:23.783276
10215 23:08:24.077597 01500000 ################################################################
10216 23:08:24.077720
10217 23:08:24.366437 01580000 ################################################################
10218 23:08:24.366571
10219 23:08:24.641267 01600000 ################################################################
10220 23:08:24.641434
10221 23:08:24.926653 01680000 ################################################################
10222 23:08:24.926782
10223 23:08:25.188883 01700000 ################################################################
10224 23:08:25.189012
10225 23:08:25.453052 01780000 ################################################################
10226 23:08:25.453189
10227 23:08:25.702764 01800000 ################################################################
10228 23:08:25.702894
10229 23:08:25.958515 01880000 ################################################################
10230 23:08:25.958646
10231 23:08:26.213833 01900000 ################################################################
10232 23:08:26.214004
10233 23:08:26.464929 01980000 ################################################################
10234 23:08:26.465061
10235 23:08:26.728313 01a00000 ################################################################
10236 23:08:26.728481
10237 23:08:26.995509 01a80000 ################################################################
10238 23:08:26.995664
10239 23:08:27.266466 01b00000 ################################################################
10240 23:08:27.266594
10241 23:08:27.529808 01b80000 ############################################################# done.
10242 23:08:27.529950
10243 23:08:27.533317 The bootfile was 29332626 bytes long.
10244 23:08:27.533402
10245 23:08:27.536801 Sending tftp read request... done.
10246 23:08:27.536970
10247 23:08:27.540691 Waiting for the transfer...
10248 23:08:27.540857
10249 23:08:27.543524 00000000 # done.
10250 23:08:27.543680
10251 23:08:27.550345 Command line loaded dynamically from TFTP file: 12395352/tftp-deploy-70s7j2a6/kernel/cmdline
10252 23:08:27.550544
10253 23:08:27.573419 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12395352/extract-nfsrootfs-u4fj8z19,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10254 23:08:27.573683
10255 23:08:27.573834 Loading FIT.
10256 23:08:27.573983
10257 23:08:27.577213 Image ramdisk-1 has 17802928 bytes.
10258 23:08:27.577506
10259 23:08:27.580076 Image fdt-1 has 47278 bytes.
10260 23:08:27.580410
10261 23:08:27.583276 Image kernel-1 has 11480388 bytes.
10262 23:08:27.583527
10263 23:08:27.590453 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10264 23:08:27.590936
10265 23:08:27.610117 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10266 23:08:27.610696
10267 23:08:27.613226 Choosing best match conf-1 for compat google,spherion-rev2.
10268 23:08:27.618718
10269 23:08:27.623173 Connected to device vid:did:rid of 1ae0:0028:00
10270 23:08:27.631328
10271 23:08:27.634828 tpm_get_response: command 0x17b, return code 0x0
10272 23:08:27.635404
10273 23:08:27.637907 ec_init: CrosEC protocol v3 supported (256, 248)
10274 23:08:27.642146
10275 23:08:27.645475 tpm_cleanup: add release locality here.
10276 23:08:27.645975
10277 23:08:27.646380 Shutting down all USB controllers.
10278 23:08:27.649028
10279 23:08:27.649495 Removing current net device
10280 23:08:27.649869
10281 23:08:27.655397 Exiting depthcharge with code 4 at timestamp: 49928722
10282 23:08:27.655872
10283 23:08:27.658940 LZMA decompressing kernel-1 to 0x821a6718
10284 23:08:27.659443
10285 23:08:27.662017 LZMA decompressing kernel-1 to 0x40000000
10286 23:08:29.097766
10287 23:08:29.098383 jumping to kernel
10288 23:08:29.100107 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10289 23:08:29.100654 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10290 23:08:29.101063 Setting prompt string to ['Linux version [0-9]']
10291 23:08:29.101447 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10292 23:08:29.101843 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10293 23:08:29.179304
10294 23:08:29.182489 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10295 23:08:29.186585 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10296 23:08:29.187100 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10297 23:08:29.187505 Setting prompt string to []
10298 23:08:29.187906 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10299 23:08:29.188303 Using line separator: #'\n'#
10300 23:08:29.188643 No login prompt set.
10301 23:08:29.188989 Parsing kernel messages
10302 23:08:29.189303 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10303 23:08:29.189868 [login-action] Waiting for messages, (timeout 00:04:03)
10304 23:08:29.205554 [ 0.000000] Linux version 6.1.67-cip12-rt7 (KernelCI@build-j59954-arm64-gcc-10-defconfig-arm64-chromebook-nblph) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023
10305 23:08:29.208823 [ 0.000000] random: crng init done
10306 23:08:29.215618 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10307 23:08:29.218914 [ 0.000000] efi: UEFI not found.
10308 23:08:29.225475 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10309 23:08:29.235750 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10310 23:08:29.242334 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10311 23:08:29.252451 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10312 23:08:29.259351 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10313 23:08:29.265788 [ 0.000000] printk: bootconsole [mtk8250] enabled
10314 23:08:29.272248 [ 0.000000] NUMA: No NUMA configuration found
10315 23:08:29.278732 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10316 23:08:29.282187 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10317 23:08:29.286100 [ 0.000000] Zone ranges:
10318 23:08:29.292406 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10319 23:08:29.295608 [ 0.000000] DMA32 empty
10320 23:08:29.302119 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10321 23:08:29.305557 [ 0.000000] Movable zone start for each node
10322 23:08:29.309229 [ 0.000000] Early memory node ranges
10323 23:08:29.315393 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10324 23:08:29.322315 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10325 23:08:29.328779 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10326 23:08:29.335482 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10327 23:08:29.341978 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10328 23:08:29.348296 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10329 23:08:29.404405 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10330 23:08:29.410696 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10331 23:08:29.417565 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10332 23:08:29.420954 [ 0.000000] psci: probing for conduit method from DT.
10333 23:08:29.427532 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10334 23:08:29.430876 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10335 23:08:29.437483 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10336 23:08:29.440767 [ 0.000000] psci: SMC Calling Convention v1.2
10337 23:08:29.447251 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10338 23:08:29.450413 [ 0.000000] Detected VIPT I-cache on CPU0
10339 23:08:29.457203 [ 0.000000] CPU features: detected: GIC system register CPU interface
10340 23:08:29.463909 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10341 23:08:29.470293 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10342 23:08:29.477375 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10343 23:08:29.486829 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10344 23:08:29.493623 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10345 23:08:29.496764 [ 0.000000] alternatives: applying boot alternatives
10346 23:08:29.503628 [ 0.000000] Fallback order for Node 0: 0
10347 23:08:29.510484 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10348 23:08:29.513400 [ 0.000000] Policy zone: Normal
10349 23:08:29.537161 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12395352/extract-nfsrootfs-u4fj8z19,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10350 23:08:29.546653 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10351 23:08:29.556985 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10352 23:08:29.567071 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10353 23:08:29.573967 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10354 23:08:29.577045 <6>[ 0.000000] software IO TLB: area num 8.
10355 23:08:29.634048 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10356 23:08:29.782704 <6>[ 0.000000] Memory: 7951336K/8385536K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 401432K reserved, 32768K cma-reserved)
10357 23:08:29.788990 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10358 23:08:29.795924 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10359 23:08:29.799115 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10360 23:08:29.805984 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10361 23:08:29.812740 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10362 23:08:29.816458 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10363 23:08:29.826040 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10364 23:08:29.832636 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10365 23:08:29.835833 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10366 23:08:29.843667 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10367 23:08:29.847020 <6>[ 0.000000] GICv3: 608 SPIs implemented
10368 23:08:29.853724 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10369 23:08:29.857043 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10370 23:08:29.860331 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10371 23:08:29.870312 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10372 23:08:29.879836 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10373 23:08:29.893315 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10374 23:08:29.899573 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10375 23:08:29.909513 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10376 23:08:29.922410 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10377 23:08:29.929241 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10378 23:08:29.935868 <6>[ 0.009185] Console: colour dummy device 80x25
10379 23:08:29.945520 <6>[ 0.013934] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10380 23:08:29.952454 <6>[ 0.024376] pid_max: default: 32768 minimum: 301
10381 23:08:29.955658 <6>[ 0.029249] LSM: Security Framework initializing
10382 23:08:29.962322 <6>[ 0.034187] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10383 23:08:29.972086 <6>[ 0.042000] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10384 23:08:29.978741 <6>[ 0.051378] cblist_init_generic: Setting adjustable number of callback queues.
10385 23:08:29.985246 <6>[ 0.058820] cblist_init_generic: Setting shift to 3 and lim to 1.
10386 23:08:29.995738 <6>[ 0.065159] cblist_init_generic: Setting adjustable number of callback queues.
10387 23:08:29.998684 <6>[ 0.072586] cblist_init_generic: Setting shift to 3 and lim to 1.
10388 23:08:30.005406 <6>[ 0.079025] rcu: Hierarchical SRCU implementation.
10389 23:08:30.012017 <6>[ 0.079027] rcu: Max phase no-delay instances is 1000.
10390 23:08:30.018820 <6>[ 0.079051] printk: bootconsole [mtk8250] printing thread started
10391 23:08:30.025413 <6>[ 0.097377] EFI services will not be available.
10392 23:08:30.028656 <6>[ 0.097577] smp: Bringing up secondary CPUs ...
10393 23:08:30.032057 <6>[ 0.097888] Detected VIPT I-cache on CPU1
10394 23:08:30.038685 <6>[ 0.097956] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10395 23:08:30.045433 <6>[ 0.097986] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10396 23:08:30.057335 <6>[ 0.125867] Detected VIPT I-cache on CPU2
10397 23:08:30.064217 <6>[ 0.125915] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10398 23:08:30.074082 <6>[ 0.125931] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10399 23:08:30.077526 <6>[ 0.126189] Detected VIPT I-cache on CPU3
10400 23:08:30.083873 <6>[ 0.126235] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10401 23:08:30.090425 <6>[ 0.126249] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10402 23:08:30.094181 <6>[ 0.126561] CPU features: detected: Spectre-v4
10403 23:08:30.100383 <6>[ 0.126567] CPU features: detected: Spectre-BHB
10404 23:08:30.103666 <6>[ 0.126572] Detected PIPT I-cache on CPU4
10405 23:08:30.110401 <6>[ 0.126630] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10406 23:08:30.117192 <6>[ 0.126646] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10407 23:08:30.123519 <6>[ 0.126938] Detected PIPT I-cache on CPU5
10408 23:08:30.129886 <6>[ 0.126998] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10409 23:08:30.136673 <6>[ 0.127014] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10410 23:08:30.140076 <6>[ 0.127291] Detected PIPT I-cache on CPU6
10411 23:08:30.146757 <6>[ 0.127354] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10412 23:08:30.153410 <6>[ 0.127370] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10413 23:08:30.160266 <6>[ 0.127663] Detected PIPT I-cache on CPU7
10414 23:08:30.166784 <6>[ 0.127726] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10415 23:08:30.173391 <6>[ 0.127742] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10416 23:08:30.176687 <6>[ 0.127788] smp: Brought up 1 node, 8 CPUs
10417 23:08:30.182793 <6>[ 0.127793] SMP: Total of 8 processors activated.
10418 23:08:30.186377 <6>[ 0.127795] CPU features: detected: 32-bit EL0 Support
10419 23:08:30.196123 <6>[ 0.127798] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10420 23:08:30.203052 <6>[ 0.127800] CPU features: detected: Common not Private translations
10421 23:08:30.209824 <6>[ 0.127802] CPU features: detected: CRC32 instructions
10422 23:08:30.213113 <6>[ 0.127804] CPU features: detected: RCpc load-acquire (LDAPR)
10423 23:08:30.219624 <6>[ 0.127806] CPU features: detected: LSE atomic instructions
10424 23:08:30.226142 <6>[ 0.127807] CPU features: detected: Privileged Access Never
10425 23:08:30.232647 <6>[ 0.127809] CPU features: detected: RAS Extension Support
10426 23:08:30.239412 <6>[ 0.127812] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10427 23:08:30.242885 <6>[ 0.127878] CPU: All CPU(s) started at EL2
10428 23:08:30.249294 <6>[ 0.127880] alternatives: applying system-wide alternatives
10429 23:08:30.277069 �;�}ٳ�r�jR�<6>[ <0.348803] printk: console [ttyS0] printing thread started
10430 23:08:30.284071 6>[ 0.225488] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10431 23:08:30.291567 <6>[ 0.348812] printk: console [ttyS0] enabled
10432 23:08:30.294727 <6>[ 0.348816] printk: bootconsole [mtk8250] disabled
10433 23:08:30.301972 <6>[ 0.361789] printk: bootconsole [mtk8250] printing thread stopped
10434 23:08:30.308273 <6>[ 0.362928] SuperH (H)SCI(F) driver initialized
10435 23:08:30.311690 <6>[ 0.363431] msm_serial: driver initialized
10436 23:08:30.321586 <6>[ 0.368094] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10437 23:08:30.328307 <6>[ 0.368133] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10438 23:08:30.344917 <6>[ 0.368163] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10439 23:08:30.351843 <6>[ 0.368192] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10440 23:08:30.355141 <6>[ 0.368214] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10441 23:08:30.380183 <6>[ 0.368242] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10442 23:08:30.381599 <6>[ 0.368270] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10443 23:08:30.385240 <6>[ 0.368379] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10444 23:08:30.392946 <6>[ 0.368408] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10445 23:08:30.398684 <6>[ 0.378524] loop: module loaded
10446 23:08:30.402578 <6>[ 0.381077] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10447 23:08:30.405818 <4>[ 0.398109] mtk-pmic-keys: Failed to locate of_node [id: -1]
10448 23:08:30.408926 <6>[ 0.399046] megasas: 07.719.03.00-rc1
10449 23:08:30.412771 <6>[ 0.408764] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10450 23:08:30.419122 <6>[ 0.416757] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10451 23:08:30.425724 <6>[ 0.428758] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10452 23:08:30.439080 <6>[ 0.480922] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10453 23:08:30.903591 <6>[ 0.973791] Freeing initrd memory: 17380K
10454 23:08:30.910014 <6>[ 0.980063] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10455 23:08:30.913652 <6>[ 0.984706] tun: Universal TUN/TAP device driver, 1.6
10456 23:08:30.917273 <6>[ 0.985465] thunder_xcv, ver 1.0
10457 23:08:30.920344 <6>[ 0.985484] thunder_bgx, ver 1.0
10458 23:08:30.923657 <6>[ 0.985498] nicpf, ver 1.0
10459 23:08:30.930244 <6>[ 0.986543] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10460 23:08:30.936845 <6>[ 0.986545] hns3: Copyright (c) 2017 Huawei Corporation.
10461 23:08:30.940226 <6>[ 0.986569] hclge is initializing
10462 23:08:30.946857 <6>[ 0.986582] e1000: Intel(R) PRO/1000 Network Driver
10463 23:08:30.950603 <6>[ 0.986584] e1000: Copyright (c) 1999-2006 Intel Corporation.
10464 23:08:30.957547 <6>[ 0.986603] e1000e: Intel(R) PRO/1000 Network Driver
10465 23:08:30.964947 <6>[ 0.986605] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10466 23:08:30.968365 <6>[ 0.986621] igb: Intel(R) Gigabit Ethernet Network Driver
10467 23:08:30.974754 <6>[ 0.986623] igb: Copyright (c) 2007-2014 Intel Corporation.
10468 23:08:30.982206 <6>[ 0.986636] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10469 23:08:30.989215 <6>[ 0.986638] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10470 23:08:30.992522 <6>[ 0.986928] sky2: driver version 1.30
10471 23:08:30.996080 <6>[ 0.987997] VFIO - User Level meta-driver version: 0.3
10472 23:08:31.002052 <6>[ 0.990830] usbcore: registered new interface driver usb-storage
10473 23:08:31.008977 <6>[ 0.991009] usbcore: registered new device driver onboard-usb-hub
10474 23:08:31.015920 <6>[ 0.993762] mt6397-rtc mt6359-rtc: registered as rtc0
10475 23:08:31.022303 <6>[ 0.993915] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-27T23:07:53 UTC (1703718473)
10476 23:08:31.028837 <6>[ 0.994523] i2c_dev: i2c /dev entries driver
10477 23:08:31.035654 <6>[ 1.001669] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10478 23:08:31.041809 <6>[ 1.016652] cpu cpu0: EM: created perf domain
10479 23:08:31.045566 <6>[ 1.016963] cpu cpu4: EM: created perf domain
10480 23:08:31.051811 <6>[ 1.019903] sdhci: Secure Digital Host Controller Interface driver
10481 23:08:31.055422 <6>[ 1.019904] sdhci: Copyright(c) Pierre Ossman
10482 23:08:31.062358 <6>[ 1.020273] Synopsys Designware Multimedia Card Interface Driver
10483 23:08:31.068882 <6>[ 1.020657] sdhci-pltfm: SDHCI platform and OF driver helper
10484 23:08:31.075477 <6>[ 1.024857] ledtrig-cpu: registered to indicate activity on CPUs
10485 23:08:31.078727 <6>[ 1.025445] mmc0: CQHCI version 5.10
10486 23:08:31.085624 <6>[ 1.025494] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10487 23:08:31.092228 <6>[ 1.025772] usbcore: registered new interface driver usbhid
10488 23:08:31.095197 <6>[ 1.025773] usbhid: USB HID core driver
10489 23:08:31.102307 <6>[ 1.025888] spi_master spi0: will run message pump with realtime priority
10490 23:08:31.115648 <6>[ 1.054146] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10491 23:08:31.128548 <6>[ 1.057138] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10492 23:08:31.135462 <6>[ 1.058130] cros-ec-spi spi0.0: Chrome EC device registered
10493 23:08:31.145347 <6>[ 1.069747] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10494 23:08:31.148314 <6>[ 1.070708] NET: Registered PF_PACKET protocol family
10495 23:08:31.152385 <6>[ 1.070776] 9pnet: Installing 9P2000 support
10496 23:08:31.158766 <5>[ 1.070810] Key type dns_resolver registered
10497 23:08:31.162048 <6>[ 1.071273] registered taskstats version 1
10498 23:08:31.168407 <5>[ 1.071291] Loading compiled-in X.509 certificates
10499 23:08:31.178654 <4>[ 1.087551] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10500 23:08:31.188387 <4>[ 1.087748] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10501 23:08:31.195161 <3>[ 1.087760] debugfs: File 'uA_load' in directory '/' already present!
10502 23:08:31.202036 <3>[ 1.087768] debugfs: File 'min_uV' in directory '/' already present!
10503 23:08:31.208502 <3>[ 1.087772] debugfs: File 'max_uV' in directory '/' already present!
10504 23:08:31.215401 <3>[ 1.087777] debugfs: File 'constraint_flags' in directory '/' already present!
10505 23:08:31.225243 <3>[ 1.090310] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10506 23:08:31.232044 <6>[ 1.098253] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10507 23:08:31.235163 <6>[ 1.098978] xhci-mtk 11200000.usb: xHCI Host Controller
10508 23:08:31.241867 <6>[ 1.098993] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10509 23:08:31.252301 <6>[ 1.099206] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10510 23:08:31.258837 <6>[ 1.099260] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10511 23:08:31.265077 <6>[ 1.099350] xhci-mtk 11200000.usb: xHCI Host Controller
10512 23:08:31.272079 <6>[ 1.099359] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10513 23:08:31.278783 <6>[ 1.099366] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10514 23:08:31.282148 <6>[ 1.099875] hub 1-0:1.0: USB hub found
10515 23:08:31.288756 <6>[ 1.099900] hub 1-0:1.0: 1 port detected
10516 23:08:31.295312 <6>[ 1.100112] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10517 23:08:31.298540 <6>[ 1.100359] hub 2-0:1.0: USB hub found
10518 23:08:31.305147 <6>[ 1.100378] hub 2-0:1.0: 1 port detected
10519 23:08:31.308324 <6>[ 1.103431] mtk-msdc 11f70000.mmc: Got CD GPIO
10520 23:08:31.314963 <6>[ 1.117481] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10521 23:08:31.324842 <6>[ 1.117494] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10522 23:08:31.335217 <4>[ 1.117695] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10523 23:08:31.341988 <6>[ 1.118326] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10524 23:08:31.348638 <6>[ 1.118329] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10525 23:08:31.358764 <6>[ 1.118446] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10526 23:08:31.365057 <6>[ 1.118461] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10527 23:08:31.371698 <6>[ 1.118465] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10528 23:08:31.381561 <6>[ 1.118470] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10529 23:08:31.388122 <6>[ 1.119704] mmc0: Command Queue Engine enabled
10530 23:08:31.394647 <6>[ 1.119715] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10531 23:08:31.401139 <6>[ 1.119937] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10532 23:08:31.411298 <6>[ 1.119961] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10533 23:08:31.417892 <6>[ 1.119968] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10534 23:08:31.428160 <6>[ 1.119976] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10535 23:08:31.434884 <6>[ 1.119982] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10536 23:08:31.444808 <6>[ 1.119989] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10537 23:08:31.451288 <6>[ 1.119995] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10538 23:08:31.461334 <6>[ 1.120001] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10539 23:08:31.467926 <6>[ 1.120008] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10540 23:08:31.478113 <6>[ 1.120014] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10541 23:08:31.484242 <6>[ 1.120020] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10542 23:08:31.493934 <6>[ 1.120027] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10543 23:08:31.500929 <6>[ 1.120034] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10544 23:08:31.510515 <6>[ 1.120040] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10545 23:08:31.517476 <6>[ 1.120046] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10546 23:08:31.524189 <6>[ 1.120235] mmcblk0: mmc0:0001 DA4128 116 GiB
10547 23:08:31.530815 <6>[ 1.120702] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10548 23:08:31.537350 <6>[ 1.121871] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10549 23:08:31.543889 <6>[ 1.122457] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10550 23:08:31.550653 <6>[ 1.123084] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10551 23:08:31.557170 <6>[ 1.123713] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10552 23:08:31.563529 <6>[ 1.123877] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10553 23:08:31.573442 <6>[ 1.123890] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10554 23:08:31.583605 <6>[ 1.123895] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10555 23:08:31.593090 <6>[ 1.123901] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10556 23:08:31.603733 <6>[ 1.123906] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10557 23:08:31.610277 <6>[ 1.123912] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10558 23:08:31.616907 <6>[ 1.123918] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10559 23:08:31.626392 <6>[ 1.123917] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10560 23:08:31.636631 <6>[ 1.123922] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10561 23:08:31.646619 <6>[ 1.123927] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10562 23:08:31.656204 <6>[ 1.123933] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10563 23:08:31.666472 <6>[ 1.123937] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10564 23:08:31.672828 <6>[ 1.124524] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10565 23:08:31.679716 <6>[ 1.125564] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10566 23:08:31.685776 <6>[ 1.126356] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10567 23:08:31.689035 <6>[ 1.127085] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10568 23:08:31.696052 <6>[ 1.137957] Trying to probe devices needed for running init ...
10569 23:08:31.702527 <6>[ 1.525560] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10570 23:08:31.709408 <6>[ 1.677553] hub 1-1:1.0: USB hub found
10571 23:08:31.712733 <6>[ 1.677950] hub 1-1:1.0: 4 ports detected
10572 23:08:31.715924 <6>[ 1.681417] hub 1-1:1.0: USB hub found
10573 23:08:31.718687 <6>[ 1.681808] hub 1-1:1.0: 4 ports detected
10574 23:08:31.739125 <6>[ 1.805801] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10575 23:08:31.759904 <6>[ 1.831540] hub 2-1:1.0: USB hub found
10576 23:08:31.763233 <6>[ 1.831976] hub 2-1:1.0: 3 ports detected
10577 23:08:31.766525 <6>[ 1.835609] hub 2-1:1.0: USB hub found
10578 23:08:31.769796 <6>[ 1.835981] hub 2-1:1.0: 3 ports detected
10579 23:08:31.927307 <6>[ 1.993671] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10580 23:08:32.051444 <6>[ 2.121405] hub 1-1.4:1.0: USB hub found
10581 23:08:32.054833 <6>[ 2.121844] hub 1-1.4:1.0: 2 ports detected
10582 23:08:32.058373 <6>[ 2.125217] hub 1-1.4:1.0: USB hub found
10583 23:08:32.064899 <6>[ 2.125556] hub 1-1.4:1.0: 2 ports detected
10584 23:08:32.131049 <6>[ 2.197897] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10585 23:08:32.347273 <6>[ 2.413651] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10586 23:08:32.530857 <6>[ 2.597655] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10587 23:08:43.335450 <6>[ 13.410730] ALSA device list:
10588 23:08:43.341792 <6>[ 13.410754] No soundcards found.
10589 23:08:43.344915 <6>[ 13.415330] Freeing unused kernel memory: 8448K
10590 23:08:43.348561 <6>[ 13.415594] Run /init as init process
10591 23:08:43.351692 Loading, please wait...
10592 23:08:43.374346 Starting version 247.3-7+deb11u2
10593 23:08:43.601579 <6>[ 13.671592] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10594 23:08:43.604900 <6>[ 13.675285] remoteproc remoteproc0: scp is available
10595 23:08:43.611469 <6>[ 13.675521] remoteproc remoteproc0: powering up scp
10596 23:08:43.617859 <6>[ 13.675532] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10597 23:08:43.624823 <6>[ 13.675562] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10598 23:08:43.631358 <6>[ 13.686882] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10599 23:08:43.640888 <6>[ 13.686921] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10600 23:08:43.650943 <6>[ 13.686926] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10601 23:08:43.657712 <4>[ 13.715387] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10602 23:08:43.664291 <4>[ 13.715530] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10603 23:08:43.674219 <3>[ 13.731196] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10604 23:08:43.680546 <3>[ 13.731218] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10605 23:08:43.687493 <3>[ 13.731225] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10606 23:08:43.697469 <3>[ 13.731316] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10607 23:08:43.703797 <3>[ 13.731323] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10608 23:08:43.714204 <3>[ 13.731330] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10609 23:08:43.721129 <3>[ 13.731339] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10610 23:08:43.728125 <3>[ 13.731346] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10611 23:08:43.737758 <3>[ 13.731392] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10612 23:08:43.744991 <3>[ 13.731445] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10613 23:08:43.754760 <3>[ 13.731452] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10614 23:08:43.761338 <3>[ 13.731459] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10615 23:08:43.771509 <3>[ 13.731511] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10616 23:08:43.777744 <3>[ 13.731518] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10617 23:08:43.784650 <3>[ 13.731525] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10618 23:08:43.794631 <3>[ 13.731532] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10619 23:08:43.801129 <3>[ 13.731538] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10620 23:08:43.810924 <3>[ 13.731574] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10621 23:08:43.814360 <6>[ 13.737951] mc: Linux media interface: v0.10
10622 23:08:43.821214 <6>[ 13.758180] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10623 23:08:43.827690 <6>[ 13.778087] videodev: Linux video capture interface: v2.00
10624 23:08:43.834630 <6>[ 13.778838] usbcore: registered new interface driver r8152
10625 23:08:43.844509 <4>[ 13.783466] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10626 23:08:43.847446 <4>[ 13.783466] Fallback method does not support PEC.
10627 23:08:43.857545 <3>[ 13.800171] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10628 23:08:43.864125 <6>[ 13.801146] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10629 23:08:43.870549 <6>[ 13.801251] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10630 23:08:43.877581 <6>[ 13.801258] remoteproc remoteproc0: remote processor scp is now up
10631 23:08:43.883947 <6>[ 13.810801] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10632 23:08:43.890604 <6>[ 13.810815] pci_bus 0000:00: root bus resource [bus 00-ff]
10633 23:08:43.897006 <6>[ 13.810822] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10634 23:08:43.907149 <6>[ 13.810827] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10635 23:08:43.914021 <6>[ 13.810864] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10636 23:08:43.920436 <6>[ 13.810891] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10637 23:08:43.926854 <6>[ 13.810987] pci 0000:00:00.0: supports D1 D2
10638 23:08:43.933572 <6>[ 13.810992] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10639 23:08:43.940151 <6>[ 13.813881] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10640 23:08:43.946943 <6>[ 13.814074] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10641 23:08:43.953240 <6>[ 13.814111] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10642 23:08:43.963282 <6>[ 13.814133] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10643 23:08:43.969854 <6>[ 13.814152] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10644 23:08:43.973405 <6>[ 13.814280] pci 0000:01:00.0: supports D1 D2
10645 23:08:43.979943 <6>[ 13.814283] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10646 23:08:43.989711 <6>[ 13.819417] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10647 23:08:43.996517 <6>[ 13.821030] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10648 23:08:44.006421 <3>[ 13.821270] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10649 23:08:44.013175 <6>[ 13.825443] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10650 23:08:44.022965 <6>[ 13.825483] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10651 23:08:44.029418 <6>[ 13.825491] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10652 23:08:44.036084 <6>[ 13.825505] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10653 23:08:44.046243 <6>[ 13.825522] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10654 23:08:44.052695 <6>[ 13.825539] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10655 23:08:44.059571 <6>[ 13.825556] pci 0000:00:00.0: PCI bridge to [bus 01]
10656 23:08:44.066028 <6>[ 13.825565] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10657 23:08:44.072841 <6>[ 13.825725] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10658 23:08:44.079162 <6>[ 13.826777] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10659 23:08:44.085890 <6>[ 13.827154] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10660 23:08:44.095792 <6>[ 13.835826] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10661 23:08:44.102724 <6>[ 13.862046] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10662 23:08:44.112369 <6>[ 13.874714] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10663 23:08:44.119081 <6>[ 13.875195] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10664 23:08:44.129330 <4>[ 13.888334] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10665 23:08:44.139260 <4>[ 13.888345] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10666 23:08:44.145700 <6>[ 13.891235] usbcore: registered new interface driver cdc_ether
10667 23:08:44.148924 <6>[ 13.896226] usbcore: registered new interface driver r8153_ecm
10668 23:08:44.159070 <5>[ 13.897844] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10669 23:08:44.165459 <5>[ 13.915944] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10670 23:08:44.172209 <4>[ 13.916043] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10671 23:08:44.178731 <6>[ 13.916052] cfg80211: failed to load regulatory.db
10672 23:08:44.181990 <6>[ 13.929014] Bluetooth: Core ver 2.22
10673 23:08:44.188640 <6>[ 13.929063] NET: Registered PF_BLUETOOTH protocol family
10674 23:08:44.195694 <6>[ 13.929065] Bluetooth: HCI device and connection manager initialized
10675 23:08:44.198689 <6>[ 13.929086] Bluetooth: HCI socket layer initialized
10676 23:08:44.205267 <6>[ 13.929091] Bluetooth: L2CAP socket layer initialized
10677 23:08:44.211363 <6>[ 13.929105] Bluetooth: SCO socket layer initialized
10678 23:08:44.214962 <6>[ 13.943918] r8152 2-1.3:1.0 eth0: v1.12.13
10679 23:08:44.221376 <6>[ 13.946018] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10680 23:08:44.234797 <6>[ 13.947464] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10681 23:08:44.241347 <6>[ 13.947576] usbcore: registered new interface driver uvcvideo
10682 23:08:44.245110 <6>[ 13.952237] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10683 23:08:44.251947 <6>[ 13.979445] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10684 23:08:44.257805 <6>[ 13.995052] usbcore: registered new interface driver btusb
10685 23:08:44.267831 <4>[ 13.996032] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10686 23:08:44.275049 <3>[ 13.996044] Bluetooth: hci0: Failed to load firmware file (-2)
10687 23:08:44.281535 <3>[ 13.996047] Bluetooth: hci0: Failed to set up firmware (-2)
10688 23:08:44.291495 <4>[ 13.996052] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10689 23:08:44.297877 <6>[ 14.236984] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10690 23:08:44.304668 <6>[ 14.237090] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10691 23:08:44.311162 <6>[ 14.257530] mt7921e 0000:01:00.0: ASIC revision: 79610010
10692 23:08:44.317743 <6>[ 14.352522] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10693 23:08:44.321448 <6>[ 14.352522]
10694 23:08:44.324436 Begin: Loading essential drivers ... done.
10695 23:08:44.327922 Begin: Running /scripts/init-premount ... done.
10696 23:08:44.334327 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10697 23:08:44.344193 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10698 23:08:44.347915 Device /sys/class/net/enx00e04c722dd6 found
10699 23:08:44.348424 done.
10700 23:08:44.405731 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10701 23:08:44.540652 <6>[ 14.609498] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10702 23:08:45.373646 <6>[ 15.446188] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10703 23:08:45.418471 IP-Config: no response after 2 secs - giving up
10704 23:08:45.477923 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:7b mtu 1500 DHCP
10705 23:08:45.530272 <6>[ 15.602174] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10706 23:08:46.201151 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10707 23:08:46.204870 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10708 23:08:46.210999 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10709 23:08:46.217909 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10710 23:08:46.224578 host : mt8192-asurada-spherion-r0-cbg-1
10711 23:08:46.230929 domain : lava-rack
10712 23:08:46.234311 rootserver: 192.168.201.1 rootpath:
10713 23:08:46.237764 filename :
10714 23:08:46.353812 done.
10715 23:08:46.360450 Begin: Running /scripts/nfs-bottom ... done.
10716 23:08:46.381373 Begin: Running /scripts/init-bottom ... done.
10717 23:08:47.565179 <6>[ 17.640487] NET: Registered PF_INET6 protocol family
10718 23:08:47.573389 <6>[ 17.647698] Segment Routing with IPv6
10719 23:08:47.576531 <6>[ 17.647715] In-situ OAM (IOAM) with IPv6
10720 23:08:47.685830 <30>[ 17.741511] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10721 23:08:47.692641 <30>[ 17.742536] systemd[1]: Detected architecture arm64.
10722 23:08:47.692737
10723 23:08:47.698965 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10724 23:08:47.699049
10725 23:08:47.721180 <30>[ 17.795890] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10726 23:08:48.545047 <30>[ 18.616201] systemd[1]: Queued start job for default target Graphical Interface.
10727 23:08:48.576038 [[0;32m OK [<30>[ 18.648231] systemd[1]: Created slice system-getty.slice.
10728 23:08:48.579235 0m] Created slice [0;1;39msystem-getty.slice[0m.
10729 23:08:48.598640 [[0;32m OK [0m] Created slic<30>[ 18.671142] systemd[1]: Created slice system-modprobe.slice.
10730 23:08:48.601627 e [0;1;39msystem-modprobe.slice[0m.
10731 23:08:48.622440 [[0;32m OK [0m] Created slic<30>[ 18.695103] systemd[1]: Created slice system-serial\x2dgetty.slice.
10732 23:08:48.629170 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10733 23:08:48.646399 [[0;32m OK [0m] Created slic<30>[ 18.718842] systemd[1]: Created slice User and Session Slice.
10734 23:08:48.649845 e [0;1;39mUser and Session Slice[0m.
10735 23:08:48.673120 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 18.741974] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10736 23:08:48.676663 ssword …ts to Console Directory Watch[0m.
10737 23:08:48.700447 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 18.769890] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10738 23:08:48.703983 sword R…uests to Wall Directory Watch[0m.
10739 23:08:48.727726 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 18.793809] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10740 23:08:48.738061 l Encrypted Volu<30>[ 18.794009] systemd[1]: Reached target Local Encrypted Volumes.
10741 23:08:48.738147 mes[0m.
10742 23:08:48.756728 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 18.829804] systemd[1]: Reached target Paths.
10743 23:08:48.756820 s[0m.
10744 23:08:48.780183 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 18.849683] systemd[1]: Reached target Remote File Systems.
10745 23:08:48.780275 te File Systems[0m.
10746 23:08:48.801294 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 18.874078] systemd[1]: Reached target Slices.
10747 23:08:48.801421 es[0m.
10748 23:08:48.821086 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 18.893693] systemd[1]: Reached target Swap.
10749 23:08:48.821172 [0m.
10750 23:08:48.844721 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 18.914170] systemd[1]: Listening on initctl Compatibility Named Pipe.
10751 23:08:48.848094 l Compatibility Named Pipe[0m.
10752 23:08:48.857923 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 18.930382] systemd[1]: Listening on Journal Audit Socket.
10753 23:08:48.861165 l Audit Socket[0m.
10754 23:08:48.882016 [[0;32m OK [0m] Listening on<30>[ 18.954919] systemd[1]: Listening on Journal Socket (/dev/log).
10755 23:08:48.885273 [0;1;39mJournal Socket (/dev/log)[0m.
10756 23:08:48.906223 [[0;32m OK [0m] Listening on<30>[ 18.979014] systemd[1]: Listening on Journal Socket.
10757 23:08:48.909465 [0;1;39mJournal Socket[0m.
10758 23:08:48.926523 [[0;32m OK [0m] Listening on<30>[ 18.999415] systemd[1]: Listening on Network Service Netlink Socket.
10759 23:08:48.933198 [0;1;39mNetwork Service Netlink Socket[0m.
10760 23:08:48.951527 [[0;32m OK [<30>[ 19.024476] systemd[1]: Listening on udev Control Socket.
10761 23:08:48.954940 0m] Listening on [0;1;39mudev Control Socket[0m.
10762 23:08:48.974103 [[0;32m OK [0m] Listening on<30>[ 19.046857] systemd[1]: Listening on udev Kernel Socket.
10763 23:08:48.977293 [0;1;39mudev Kernel Socket[0m.
10764 23:08:49.029468 Mounting [0;1;39mHuge Pages File Syste<30>[ 19.102113] systemd[1]: Mounting Huge Pages File System...
10765 23:08:49.032912 m[0m...
10766 23:08:49.051164 Mountin<30>[ 19.124131] systemd[1]: Mounting POSIX Message Queue File System...
10767 23:08:49.054493 g [0;1;39mPOSIX Message Queue File System[0m...
10768 23:08:49.075371 Mountin<30>[ 19.148398] systemd[1]: Mounting Kernel Debug File System...
10769 23:08:49.078865 g [0;1;39mKernel Debug File System[0m...
10770 23:08:49.100127 <30>[ 19.170092] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10771 23:08:49.120661 Starting [0;1;39mCreate list of st…o<30>[ 19.190206] systemd[1]: Starting Create list of static device nodes for the current kernel...
10772 23:08:49.123907 des for the current kernel[0m...
10773 23:08:49.156494 Starting [0;1;39mLoad Kernel Module co<30>[ 19.226070] systemd[1]: Starting Load Kernel Module configfs...
10774 23:08:49.156589 nfigfs[0m...
10775 23:08:49.178199 Starting [0;1;39mLoad <30>[ 19.250841] systemd[1]: Starting Load Kernel Module drm...
10776 23:08:49.181205 Kernel Module drm[0m...
10777 23:08:49.206655 Starting [0;1;39mLoad <30>[ 19.279187] systemd[1]: Starting Load Kernel Module fuse...
10778 23:08:49.209792 Kernel Module fuse[0m...
10779 23:08:49.241355 <6>[ 19.315016] fuse: init (API version 7.37)
10780 23:08:49.251097 <30>[ 19.316231] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10781 23:08:49.261729 Starting [0;1;39mJourn<30>[ 19.334548] systemd[1]: Starting Journal Service...
10782 23:08:49.261817 al Service[0m...
10783 23:08:49.286440 Starting [0;1;39mLoad <30>[ 19.359121] systemd[1]: Starting Load Kernel Modules...
10784 23:08:49.289444 Kernel Modules[0m...
10785 23:08:49.320529 Starting [0;1;39mRemount Root and Kern<30>[ 19.389558] systemd[1]: Starting Remount Root and Kernel File Systems...
10786 23:08:49.320664 el File Systems[0m...
10787 23:08:49.349759 Starting [0;1;39mColdp<30>[ 19.422355] systemd[1]: Starting Coldplug All udev Devices...
10788 23:08:49.353296 lug All udev Devices[0m...
10789 23:08:49.383564 [[0;32m OK [<30>[ 19.456515] systemd[1]: Mounted Huge Pages File System.
10790 23:08:49.387070 0m] Mounted [0;1;39mHuge Pages File System[0m.
10791 23:08:49.404543 <3>[ 19.475090] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10792 23:08:49.414469 [[0;32m OK [0m] Mounted [0;<30>[ 19.487267] systemd[1]: Mounted POSIX Message Queue File System.
10793 23:08:49.418145 1;39mPOSIX Message Queue File System[0m.
10794 23:08:49.428228 <3>[ 19.501063] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10795 23:08:49.441902 [[0;32m OK [0m] Mounted [0;<30>[ 19.514637] systemd[1]: Mounted Kernel Debug File System.
10796 23:08:49.444812 1;39mKernel Debug File System[0m.
10797 23:08:49.460848 <3>[ 19.530900] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10798 23:08:49.474560 [[0;32m OK [0m] Finished [0<30>[ 19.543231] systemd[1]: Finished Create list of static device nodes for the current kernel.
10799 23:08:49.484289 ;1;39mCreate lis<3>[ 19.553224] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10800 23:08:49.487617 t of st… nodes for the current kernel[0m.
10801 23:08:49.506939 [[0;32m OK [0m] Finished [0<30>[ 19.578541] systemd[1]: modprobe@configfs.service: Succeeded.
10802 23:08:49.513589 <30>[ 19.579059] systemd[1]: Finished Load Kernel Module configfs.
10803 23:08:49.523343 ;1;39mLoad Kerne<3>[ 19.587345] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10804 23:08:49.526938 l Module configfs[0m.
10805 23:08:49.549033 <3>[ 19.619115] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10806 23:08:49.555633 <30>[ 19.623645] systemd[1]: modprobe@drm.service: Succeeded.
10807 23:08:49.559315 <30>[ 19.624904] systemd[1]: Finished Load Kernel Module drm.
10808 23:08:49.569834 <3>[ 19.641551] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10809 23:08:49.575949 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10810 23:08:49.592540 <3>[ 19.661936] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10811 23:08:49.600888 [[0;32m OK [<30>[ 19.675311] systemd[1]: modprobe@fuse.service: Succeeded.
10812 23:08:49.611107 0m] Finished [0<30>[ 19.676175] systemd[1]: Finished Load Kernel Module fuse.
10813 23:08:49.620814 ;1;39mLoad Kerne<3>[ 19.684191] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10814 23:08:49.621266 l Module fuse[0m.
10815 23:08:49.632701 <3>[ 19.704293] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10816 23:08:49.647411 [[0;32m OK [0m] Finished [0<30>[ 19.718866] systemd[1]: Finished Load Kernel Modules.
10817 23:08:49.647978 ;1;39mLoad Kernel Modules[0m.
10818 23:08:49.667825 [[0;32m OK [0m] Finished [0<30>[ 19.739285] systemd[1]: Finished Remount Root and Kernel File Systems.
10819 23:08:49.670791 ;1;39mRemount Root and Kernel File Systems[0m.
10820 23:08:49.693370 [[0;32m OK [0m] Started [0;1;39mJournal Ser<30>[ 19.766139] systemd[1]: Started Journal Service.
10821 23:08:49.696924 vice[0m.
10822 23:08:49.746272 Mounting [0;1;39mFUSE Control File System[0m...
10823 23:08:49.766249 Mounting [0;1;39mKernel Configuration File System[0m...
10824 23:08:49.791701 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10825 23:08:49.814421 Starting [0;1;39mLoad/Save Random Seed[0m...
10826 23:08:49.836730 Startin<46>[ 19.905737] systemd-journald[308]: Received client request to flush runtime journal.
10827 23:08:49.839977 g [0;1;39mApply Kernel Variables[0m...
10828 23:08:49.895039 <4>[ 19.961120] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10829 23:08:49.904622 <3>[ 19.961137] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10830 23:08:49.981832 Starting [0;1;39mCreate System Users[0m...
10831 23:08:50.008867 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10832 23:08:50.021443 See 'systemctl status systemd-udev-trigger.service' for details.
10833 23:08:50.038028 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10834 23:08:50.053837 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10835 23:08:50.309379 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10836 23:08:50.580322 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10837 23:08:51.233423 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10838 23:08:51.268032 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10839 23:08:51.318548 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10840 23:08:51.393793 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10841 23:08:51.405367 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10842 23:08:51.421367 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10843 23:08:51.457779 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10844 23:08:51.486688 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10845 23:08:51.644958 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10846 23:08:51.699354 Starting [0;1;39mNetwork Service[0m...
10847 23:08:51.731416 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10848 23:08:51.820341 Starting [0;1;39mNetwork Time Synchronization[0m...
10849 23:08:51.841025 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10850 23:08:52.037952 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10851 23:08:52.062682 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10852 23:08:52.126706 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10853 23:08:52.377583 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10854 23:08:52.401065 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10855 23:08:52.446215 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10856 23:08:52.463224 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10857 23:08:52.483588 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10858 23:08:52.498112 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10859 23:08:52.514190 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10860 23:08:52.547751 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10861 23:08:52.566136 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10862 23:08:53.321689 Starting [0;1;39mNetwork Name Resolution[0m...
10863 23:08:53.343341 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10864 23:08:53.363500 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10865 23:08:53.650797 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10866 23:08:53.671550 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10867 23:08:53.692523 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10868 23:08:53.712706 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10869 23:08:53.728825 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10870 23:08:53.741403 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10871 23:08:53.762027 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10872 23:08:53.773484 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10873 23:08:53.789213 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10874 23:08:53.826133 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10875 23:08:53.921644 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10876 23:08:54.015439 Starting [0;1;39mUser Login Management[0m...
10877 23:08:54.308764 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10878 23:08:54.482530 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10879 23:08:54.643095 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10880 23:08:54.659348 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10881 23:08:54.677205 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10882 23:08:54.724335 Starting [0;1;39mPermit User Sessions[0m...
10883 23:08:54.758031 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10884 23:08:54.800097 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10885 23:08:54.822093 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10886 23:08:54.840634 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10887 23:08:54.862058 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10888 23:08:54.877796 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10889 23:08:54.923460 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10890 23:08:54.982927 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10891 23:08:55.047740
10892 23:08:55.047848
10893 23:08:55.050878 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10894 23:08:55.050962
10895 23:08:55.054075 debian-bullseye-arm64 login: root (automatic login)
10896 23:08:55.054158
10897 23:08:55.054223
10898 23:08:55.331082 Linux debian-bullseye-arm64 6.1.67-cip12-rt7 #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023 aarch64
10899 23:08:55.331219
10900 23:08:55.337723 The programs included with the Debian GNU/Linux system are free software;
10901 23:08:55.344606 the exact distribution terms for each program are described in the
10902 23:08:55.347750 individual files in /usr/share/doc/*/copyright.
10903 23:08:55.347841
10904 23:08:55.354448 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10905 23:08:55.357664 permitted by applicable law.
10906 23:08:55.415236 Matched prompt #10: / #
10908 23:08:55.415756 Setting prompt string to ['/ #']
10909 23:08:55.415958 end: 2.2.5.1 login-action (duration 00:00:26) [common]
10911 23:08:55.416454 end: 2.2.5 auto-login-action (duration 00:00:26) [common]
10912 23:08:55.416699 start: 2.2.6 expect-shell-connection (timeout 00:03:37) [common]
10913 23:08:55.416910 Setting prompt string to ['/ #']
10914 23:08:55.417079 Forcing a shell prompt, looking for ['/ #']
10916 23:08:55.467730 / #
10917 23:08:55.468396 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10918 23:08:55.468862 Waiting using forced prompt support (timeout 00:02:30)
10919 23:08:55.473906
10920 23:08:55.474756 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10921 23:08:55.475291 start: 2.2.7 export-device-env (timeout 00:03:37) [common]
10923 23:08:55.576677 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12395352/extract-nfsrootfs-u4fj8z19'
10924 23:08:55.582235 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12395352/extract-nfsrootfs-u4fj8z19'
10926 23:08:55.683159 / # export NFS_SERVER_IP='192.168.201.1'
10927 23:08:55.690068 export NFS_SERVER_IP='192.168.201.1'
10928 23:08:55.691016 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10929 23:08:55.691555 end: 2.2 depthcharge-retry (duration 00:01:23) [common]
10930 23:08:55.692046 end: 2 depthcharge-action (duration 00:01:23) [common]
10931 23:08:55.692538 start: 3 lava-test-retry (timeout 00:30:00) [common]
10932 23:08:55.693029 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
10933 23:08:55.693435 Using namespace: common
10935 23:08:55.794767 / # #
10936 23:08:55.795449 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
10937 23:08:55.801458 #
10938 23:08:55.802401 Using /lava-12395352
10940 23:08:55.903593 / # export SHELL=/bin/sh
10941 23:08:55.909052 export SHELL=/bin/sh
10943 23:08:56.010376 / # . /lava-12395352/environment
10944 23:08:56.015616 . /lava-12395352/environment
10946 23:08:56.122995 / # /lava-12395352/bin/lava-test-runner /lava-12395352/0
10947 23:08:56.123632 Test shell timeout: 10s (minimum of the action and connection timeout)
10948 23:08:56.130004 /lava-12395352/bin/lava-test-runner /lava-12395352/0
10949 23:08:56.352944 + export TESTRUN_ID=0_lc-compliance
10950 23:08:56.359419 + cd /lava-12395352/0/tests/0_lc-compliance
10951 23:08:56.359512 + cat uuid
10952 23:08:56.362715 + UUID=12395352_1.6.2.3.1
10953 23:08:56.362799 + set +x
10954 23:08:56.369359 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 12395352_1.6.2.3.1>
10955 23:08:56.369621 Received signal: <STARTRUN> 0_lc-compliance 12395352_1.6.2.3.1
10956 23:08:56.369696 Starting test lava.0_lc-compliance (12395352_1.6.2.3.1)
10957 23:08:56.369787 Skipping test definition patterns.
10958 23:08:56.372804 + /usr/bin/lc-compliance-parser.sh
10959 23:08:57.600757 [0:00:27.633936308] [412] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:297 [0mlibcamera v0.0.0+1-1f607da9
10960 23:08:57.604279 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
10961 23:08:57.617331 [0:00:27.650813923] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10962 23:08:57.668366 [==========] Running 120 tests from 1 test suite.
10963 23:08:57.678441 [0:00:27.712400846] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10964 23:08:57.725330 [----------] Global test environment set-up.
10965 23:08:57.734966 [0:00:27.770524846] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10966 23:08:57.777145 [----------] 120 tests from CaptureTests/SingleStream
10967 23:08:57.787002 [0:00:27.822996539] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10968 23:08:57.836999 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
10969 23:08:57.890609 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
10970 23:08:57.890923 Received signal: <TESTSET> START CaptureTests/SingleStream
10971 23:08:57.891017 Starting test_set CaptureTests/SingleStream
10972 23:08:57.893828 Camera needs 4 requests, can't test only 1
10973 23:08:57.948238 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10974 23:08:58.009267
10975 23:08:58.074823 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (61 ms)
10976 23:08:58.159857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
10977 23:08:58.160154 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
10979 23:08:58.176504 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
10980 23:08:58.217845 [0:00:28.251008847] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10981 23:08:58.228660 Camera needs 4 requests, can't test only 2
10982 23:08:58.312027 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10983 23:08:58.392260
10984 23:08:58.464338 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (59 ms)
10985 23:08:58.558788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
10986 23:08:58.559591 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
10988 23:08:58.577489 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
10989 23:08:58.635273 Camera needs 4 requests, can't test only 3
10990 23:08:58.710666 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
10991 23:08:58.748491 [0:00:28.781347385] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
10992 23:08:58.802324
10993 23:08:58.887627 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (52 ms)
10994 23:08:58.976614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
10995 23:08:58.977353 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
10997 23:08:58.991371 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
10998 23:08:59.039757 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (429 ms)
10999 23:08:59.123396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11000 23:08:59.123691 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11002 23:08:59.138183 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11003 23:08:59.185956 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (528 ms)
11004 23:08:59.256542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11005 23:08:59.256909 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11007 23:08:59.270171 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11008 23:08:59.373080 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (634 ms)
11009 23:08:59.383385 [0:00:29.415610924] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11010 23:08:59.454084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11011 23:08:59.454364 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11013 23:08:59.466186 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11014 23:09:00.271835 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (898 ms)
11015 23:09:00.281601 [0:00:30.314392616] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11016 23:09:00.366414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11017 23:09:00.367326 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11019 23:09:00.382459 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11020 23:09:01.668320 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1397 ms)
11021 23:09:01.678256 [0:00:31.710438077] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11022 23:09:01.740068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11023 23:09:01.740412 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11025 23:09:01.751299 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11026 23:09:03.763156 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2095 ms)
11027 23:09:03.773407 [0:00:33.805202155] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11028 23:09:03.860365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11029 23:09:03.861197 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11031 23:09:03.875974 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11032 23:09:06.991138 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3228 ms)
11033 23:09:07.000687 [0:00:37.033614155] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11034 23:09:07.051826 [0:00:37.086436539] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11035 23:09:07.078815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11036 23:09:07.079082 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11038 23:09:07.095292 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11039 23:09:07.108605 [0:00:37.142850847] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11040 23:09:07.145410 Camera needs 4 requests, can't test only 1
11041 23:09:07.163299 [0:00:37.197611616] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11042 23:09:07.219259 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11043 23:09:07.296429
11044 23:09:07.379685 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (54 ms)
11045 23:09:07.472044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11046 23:09:07.472828 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11048 23:09:07.489927 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11049 23:09:07.527873 [0:00:37.562275847] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11050 23:09:07.540169 Camera needs 4 requests, can't test only 2
11051 23:09:07.624916 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11052 23:09:07.708054
11053 23:09:07.784878 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (55 ms)
11054 23:09:07.874371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11055 23:09:07.875127 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11057 23:09:07.891924 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11058 23:09:07.948744 Camera needs 4 requests, can't test only 3
11059 23:09:08.021905 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11060 23:09:08.058437 [0:00:38.092767155] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11061 23:09:08.097265
11062 23:09:08.184748 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (54 ms)
11063 23:09:08.285238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11064 23:09:08.286092 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11066 23:09:08.302289 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11067 23:09:08.355694 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (365 ms)
11068 23:09:08.454117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11069 23:09:08.454402 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11071 23:09:08.469790 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11072 23:09:08.525696 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (529 ms)
11073 23:09:08.620394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11074 23:09:08.620710 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11076 23:09:08.635531 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11077 23:09:08.746460 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (697 ms)
11078 23:09:08.759403 [0:00:38.790142616] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11079 23:09:08.851642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11080 23:09:08.852517 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11082 23:09:08.870642 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11083 23:09:09.646832 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (901 ms)
11084 23:09:09.660372 [0:00:39.690360309] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11085 23:09:09.738060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11086 23:09:09.738822 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11088 23:09:09.756104 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11089 23:09:11.044010 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1397 ms)
11090 23:09:11.057039 [0:00:41.087319386] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11091 23:09:11.142811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11092 23:09:11.143579 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11094 23:09:11.162465 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11095 23:09:13.077882 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2034 ms)
11096 23:09:13.091048 [0:00:43.120835770] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11097 23:09:13.184146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11098 23:09:13.184966 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11100 23:09:13.201624 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11101 23:09:13.955252 <6>[ 44.033760] vpu: disabling
11102 23:09:13.958612 <6>[ 44.033896] vproc2: disabling
11103 23:09:13.962468 <6>[ 44.033955] vproc1: disabling
11104 23:09:13.965928 <6>[ 44.034014] vaud18: disabling
11105 23:09:13.972721 <6>[ 44.034285] vsram_others: disabling
11106 23:09:13.975949 <6>[ 44.034479] va09: disabling
11107 23:09:13.979636 <6>[ 44.034567] vsram_md: disabling
11108 23:09:13.982492 <6>[ 44.034708] Vgpu: disabling
11109 23:09:16.306829 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3229 ms)
11110 23:09:16.319714 [0:00:46.350660540] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11111 23:09:16.372554 [0:00:46.407513078] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11112 23:09:16.408383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11113 23:09:16.409081 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11115 23:09:16.428332 [0:00:46.463916694] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11116 23:09:16.431496 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11117 23:09:16.473194 Camera needs 4 requests, can't test only 1
11118 23:09:16.483351 [0:00:46.519015617] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11119 23:09:16.546089 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11120 23:09:16.618301
11121 23:09:16.696240 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (57 ms)
11122 23:09:16.768734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11123 23:09:16.769044 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11125 23:09:16.783043 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11126 23:09:16.826845 Camera needs 4 requests, can't test only 2
11127 23:09:16.893891 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11128 23:09:16.915492 [0:00:46.950968694] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11129 23:09:16.959256
11130 23:09:17.028873 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (57 ms)
11131 23:09:17.106727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11132 23:09:17.107057 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11134 23:09:17.121218 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11135 23:09:17.164533 Camera needs 4 requests, can't test only 3
11136 23:09:17.228476 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11137 23:09:17.284746
11138 23:09:17.345935 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (55 ms)
11139 23:09:17.380789 [0:00:47.416345386] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11140 23:09:17.411611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11141 23:09:17.411920 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11143 23:09:17.422918 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11144 23:09:17.457247 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (432 ms)
11145 23:09:17.521275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11146 23:09:17.521560 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11148 23:09:17.533974 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11149 23:09:17.578013 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (466 ms)
11150 23:09:17.644080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11151 23:09:17.644401 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11153 23:09:17.657877 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11154 23:09:18.067526 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (694 ms)
11155 23:09:18.080707 [0:00:48.113236002] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11156 23:09:18.147192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11157 23:09:18.147509 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11159 23:09:18.160822 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11160 23:09:19.066779 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (1000 ms)
11161 23:09:19.080062 [0:00:49.112749463] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11162 23:09:19.152168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11163 23:09:19.152493 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11165 23:09:19.165225 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11166 23:09:20.497971 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1431 ms)
11167 23:09:20.510971 [0:00:50.543854002] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11168 23:09:22.605964 [0:00:52.641890848] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11169 23:09:22.850231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11170 23:09:22.850584 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11172 23:09:22.865740 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11173 23:09:22.914567 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2099 ms)
11174 23:09:25.835834 [0:00:55.872264549] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11175 23:09:25.892415 [0:00:55.928998287] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11176 23:09:25.949433 [0:00:55.985716490] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11177 23:09:26.004943 [0:00:56.041450001] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11178 23:09:26.436775 [0:00:56.472869027] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11179 23:09:26.459327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11180 23:09:26.459612 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11182 23:09:26.476649 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11183 23:09:26.521097 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3230 ms)
11184 23:09:26.580746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11185 23:09:26.581047 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11187 23:09:26.592885 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11188 23:09:26.631435 Camera needs 4 requests, can't test only 1
11189 23:09:26.691862 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11190 23:09:26.755910
11191 23:09:26.822868 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (57 ms)
11192 23:09:26.891785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11193 23:09:26.892083 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11195 23:09:26.904812 [0:00:56.938470945] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11196 23:09:26.908207 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11197 23:09:26.947710 Camera needs 4 requests, can't test only 2
11198 23:09:27.006509 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11199 23:09:27.064008
11200 23:09:27.127087 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (56 ms)
11201 23:09:27.200838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11202 23:09:27.201159 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11204 23:09:27.212711 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11205 23:09:27.259927 Camera needs 4 requests, can't test only 3
11206 23:09:27.317812 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11207 23:09:27.379179
11208 23:09:27.447932 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (55 ms)
11209 23:09:27.520982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11210 23:09:27.521309 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11212 23:09:27.533871 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11213 23:09:27.572749 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (431 ms)
11214 23:09:27.597887 [0:00:57.634236967] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11215 23:09:27.646860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11216 23:09:27.647181 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11218 23:09:27.660572 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11219 23:09:27.701863 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (466 ms)
11220 23:09:27.765638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11221 23:09:27.765965 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11223 23:09:27.777516 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11224 23:09:27.809890 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (696 ms)
11225 23:09:27.873702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11226 23:09:27.874034 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11228 23:09:27.885869 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11229 23:09:28.486761 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (897 ms)
11230 23:09:28.500073 [0:00:58.532971514] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11231 23:09:28.565199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11232 23:09:28.565529 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11234 23:09:28.578809 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11235 23:09:29.884619 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1398 ms)
11236 23:09:29.897724 [0:00:59.930614537] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11237 23:09:29.970138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11238 23:09:29.970460 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11240 23:09:29.983301 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11241 23:09:31.983106 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2098 ms)
11242 23:09:31.996502 [0:01:02.029376889] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11243 23:09:32.060330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11244 23:09:32.060660 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11246 23:09:32.073358 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11247 23:09:35.213589 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3230 ms)
11248 23:09:35.226725 [0:01:05.259646478] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11249 23:09:35.281568 [0:01:05.317117612] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11250 23:09:35.305679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11251 23:09:35.305996 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11253 23:09:35.321172 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11254 23:09:35.340273 [0:01:05.375951259] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11255 23:09:35.371175 Camera needs 4 requests, can't test only 1
11256 23:09:35.399864 [0:01:05.436085273] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11257 23:09:35.444953 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11258 23:09:35.520085
11259 23:09:35.592309 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (58 ms)
11260 23:09:35.664535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11261 23:09:35.664852 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11263 23:09:35.674826 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11264 23:09:35.706199 Camera needs 4 requests, can't test only 2
11265 23:09:35.769047 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11266 23:09:35.836513
11267 23:09:35.915861 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (59 ms)
11268 23:09:36.004790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11269 23:09:36.005083 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11271 23:09:36.020459 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11272 23:09:36.065108 Camera needs 4 requests, can't test only 3
11273 23:09:36.132317 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11274 23:09:36.180615
11275 23:09:36.243878 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (60 ms)
11276 23:09:36.329806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11277 23:09:36.330091 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11279 23:09:36.343868 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11280 23:09:36.583925 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1193 ms)
11281 23:09:36.596696 [0:01:06.629437966] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11282 23:09:36.673527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11283 23:09:36.673816 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11285 23:09:36.689801 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11286 23:09:38.266238 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1682 ms)
11287 23:09:38.279329 [0:01:08.312470929] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11288 23:09:38.333870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11289 23:09:38.334198 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11291 23:09:38.345208 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11292 23:09:40.287817 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2021 ms)
11293 23:09:40.301213 [0:01:10.334393862] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11294 23:09:40.369036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11295 23:09:40.369361 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11297 23:09:40.381374 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11298 23:09:42.976575 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2689 ms)
11299 23:09:42.989599 [0:01:13.022252970] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11300 23:09:43.056473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11301 23:09:43.056802 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11303 23:09:43.072874 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11304 23:09:47.159254 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4183 ms)
11305 23:09:47.172527 [0:01:17.205933306] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11306 23:09:47.247556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11307 23:09:47.247901 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11309 23:09:47.260864 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11310 23:09:53.474823 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6316 ms)
11311 23:09:53.488172 [0:01:23.521728718] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11312 23:09:53.560150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11313 23:09:53.560481 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11315 23:09:53.574934 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11316 23:10:03.091738 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9617 ms)
11317 23:10:03.104553 [0:01:33.139273348] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11318 23:10:03.159273 [0:01:33.196526035] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11319 23:10:03.217065 [0:01:33.253987641] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11320 23:10:03.273021 [0:01:33.310126045] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11321 23:10:04.590429 [0:01:34.627779929] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11322 23:10:05.385767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11323 23:10:05.386147 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11325 23:10:05.402956 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11326 23:10:05.457606 Camera needs 4 requests, can't test only 1
11327 23:10:05.536967 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11328 23:10:05.617241
11329 23:10:05.702971 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (58 ms)
11330 23:10:06.271707 [0:01:36.309021057] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11331 23:10:08.677132 [0:01:38.328997010] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11332 23:10:08.678039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11333 23:10:08.678851 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11335 23:10:08.790022 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11336 23:10:08.843208 Camera needs 4 requests, can't test only 2
11337 23:10:08.925380 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11338 23:10:08.995083
11339 23:10:09.063555 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (57 ms)
11340 23:10:09.147208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11341 23:10:09.147950 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11343 23:10:09.158051 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11344 23:10:09.206792 Camera needs 4 requests, can't test only 3
11345 23:10:09.274939 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11346 23:10:09.340154
11347 23:10:09.417854 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (56 ms)
11348 23:10:09.483298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11349 23:10:09.483798 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11351 23:10:09.495630 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11352 23:10:09.547241 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1317 ms)
11353 23:10:09.621101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11354 23:10:09.621394 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11356 23:10:09.631091 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11357 23:10:09.676933 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1682 ms)
11358 23:10:09.743008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11359 23:10:09.743286 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11361 23:10:09.754706 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11362 23:10:09.797553 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2019 ms)
11363 23:10:09.861556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11364 23:10:09.861831 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11366 23:10:09.872915 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11367 23:10:10.972483 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2689 ms)
11368 23:10:10.982152 [0:01:41.017701332] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11369 23:10:11.050056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11370 23:10:11.050367 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11372 23:10:11.060108 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11373 23:10:15.156432 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4184 ms)
11374 23:10:15.166139 [0:01:45.202134675] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11375 23:10:15.230169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11376 23:10:15.230461 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11378 23:10:15.242791 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11379 23:10:21.471296 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6316 ms)
11380 23:10:21.480961 [0:01:51.517793852] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11381 23:10:21.549409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11382 23:10:21.549688 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11384 23:10:21.559761 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11385 23:10:31.152291 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9681 ms)
11386 23:10:31.162212 [0:02:01.199037196] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11387 23:10:31.216026 [0:02:01.255620731] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11388 23:10:31.265827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11389 23:10:31.266659 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11391 23:10:31.275227 [0:02:01.315072063] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11392 23:10:31.282028 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11393 23:10:31.331607 [0:02:01.371380361] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11394 23:10:31.334664 Camera needs 4 requests, can't test only 1
11395 23:10:31.413196 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11396 23:10:31.488076
11397 23:10:31.562265 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (58 ms)
11398 23:10:31.651119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11399 23:10:31.651935 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11401 23:10:31.664511 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11402 23:10:31.719250 Camera needs 4 requests, can't test only 2
11403 23:10:31.792601 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11404 23:10:31.869904
11405 23:10:31.964693 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (59 ms)
11406 23:10:32.055993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11407 23:10:32.056885 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11409 23:10:32.076761 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11410 23:10:32.122645 Camera needs 4 requests, can't test only 3
11411 23:10:32.193912 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11412 23:10:32.257682
11413 23:10:32.344684 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (57 ms)
11414 23:10:32.420766 [0:02:02.460959862] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11415 23:10:32.432919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11416 23:10:32.433201 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11418 23:10:32.443456 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11419 23:10:32.497882 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1090 ms)
11420 23:10:32.583946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11421 23:10:32.584666 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11423 23:10:32.596139 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11424 23:10:33.999046 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1582 ms)
11425 23:10:34.008442 [0:02:04.044887409] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11426 23:10:34.093202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11427 23:10:34.093996 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11429 23:10:34.109564 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11430 23:10:36.052553 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2053 ms)
11431 23:10:36.061782 [0:02:06.098315750] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11432 23:10:36.162604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11433 23:10:36.163399 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11435 23:10:36.179558 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11436 23:10:38.741374 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2689 ms)
11437 23:10:38.751118 [0:02:08.786574082] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11438 23:10:38.844846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11439 23:10:38.845165 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11441 23:10:38.857773 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11442 23:10:42.924955 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4183 ms)
11443 23:10:42.934353 [0:02:12.970262127] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11444 23:10:43.009932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11445 23:10:43.010240 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11447 23:10:43.019199 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11448 23:10:49.240015 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6315 ms)
11449 23:10:49.249852 [0:02:19.285091569] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11450 23:10:49.317683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11451 23:10:49.318013 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11453 23:10:49.328974 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11454 23:10:58.920404 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9680 ms)
11455 23:10:58.930272 [0:02:28.965514078] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11456 23:10:58.984960 [0:02:29.023172337] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11457 23:10:59.014548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11458 23:10:59.015242 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11460 23:10:59.025176 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11461 23:10:59.042936 [0:02:29.081248313] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11462 23:10:59.074376 Camera needs 4 requests, can't test only 1
11463 23:10:59.100673 [0:02:29.138912725] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11464 23:10:59.142159 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11465 23:10:59.210116
11466 23:10:59.274973 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (58 ms)
11467 23:10:59.336407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11468 23:10:59.336731 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11470 23:10:59.347166 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11471 23:10:59.388502 Camera needs 4 requests, can't test only 2
11472 23:10:59.445159 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11473 23:10:59.503923
11474 23:10:59.577770 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (59 ms)
11475 23:10:59.647650 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11477 23:10:59.650306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11478 23:10:59.660679 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11479 23:10:59.697729 Camera needs 4 requests, can't test only 3
11480 23:10:59.753025 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11481 23:10:59.812647
11482 23:10:59.884558 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (57 ms)
11483 23:10:59.950125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11484 23:10:59.950418 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11486 23:10:59.960058 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11487 23:11:00.346336 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1251 ms)
11488 23:11:00.356185 [0:02:30.391491565] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11489 23:11:00.442845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11490 23:11:00.443665 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11492 23:11:00.455489 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11493 23:11:01.932486 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1586 ms)
11494 23:11:01.942042 [0:02:31.977721593] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11495 23:11:02.013744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11496 23:11:02.014585 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11498 23:11:02.024527 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11499 23:11:03.987583 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2055 ms)
11500 23:11:03.997389 [0:02:34.032484877] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11501 23:11:04.070070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11502 23:11:04.070356 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11504 23:11:04.079897 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11505 23:11:06.675875 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2689 ms)
11506 23:11:06.685790 [0:02:36.721532576] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11507 23:11:06.758332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11508 23:11:06.758615 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11510 23:11:06.768616 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11511 23:11:10.927075 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4250 ms)
11512 23:11:10.936675 [0:02:40.971971476] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11513 23:11:11.026611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11514 23:11:11.027306 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11516 23:11:11.039192 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11517 23:11:17.209649 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6283 ms)
11518 23:11:17.219644 [0:02:47.254348409] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11519 23:11:17.316404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11520 23:11:17.317224 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11522 23:11:17.330569 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11523 23:11:26.889494 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9680 ms)
11524 23:11:26.899293 [0:02:56.934805561] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11525 23:11:26.986744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11526 23:11:26.987740 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11528 23:11:27.001412 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11529 23:11:27.185276 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (299 ms)
11530 23:11:27.195053 [0:02:57.234027004] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11531 23:11:27.269079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11532 23:11:27.269372 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11534 23:11:27.283909 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11535 23:11:27.518648 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (334 ms)
11536 23:11:27.531827 [0:02:57.567534648] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11537 23:11:27.613653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11538 23:11:27.613956 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11540 23:11:27.629102 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11541 23:11:27.918342 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (399 ms)
11542 23:11:27.927707 [0:02:57.966443851] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11543 23:11:28.006938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11544 23:11:28.007249 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11546 23:11:28.023520 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11547 23:11:28.287483 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (370 ms)
11548 23:11:28.300396 [0:02:58.336402534] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11549 23:11:28.381449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11550 23:11:28.381722 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11552 23:11:28.396243 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11553 23:11:28.757838 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (470 ms)
11554 23:11:28.770578 [0:02:58.806993607] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11555 23:11:28.837333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11556 23:11:28.837610 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11558 23:11:28.852460 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11559 23:11:29.489694 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (732 ms)
11560 23:11:29.503117 [0:02:59.539307031] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11561 23:11:29.587923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11562 23:11:29.588863 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11564 23:11:29.602878 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11565 23:11:30.392915 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (902 ms)
11566 23:11:30.406090 [0:03:00.442332456] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11567 23:11:30.486420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11568 23:11:30.487330 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11570 23:11:30.501635 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11571 23:11:31.792305 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1400 ms)
11572 23:11:31.805574 [0:03:01.841901527] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11573 23:11:31.901787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11574 23:11:31.902685 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11576 23:11:31.917347 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11577 23:11:33.892043 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2099 ms)
11578 23:11:33.904442 [0:03:03.940770341] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11579 23:11:33.990040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11580 23:11:33.990863 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11582 23:11:34.006419 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11583 23:11:37.122967 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3231 ms)
11584 23:11:37.136373 [0:03:07.172469688] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11585 23:11:37.223516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11586 23:11:37.224214 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11588 23:11:37.240762 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11589 23:11:37.363434 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (237 ms)
11590 23:11:37.372934 [0:03:07.409412178] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11591 23:11:37.473675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11592 23:11:37.474485 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11594 23:11:37.489087 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11595 23:11:37.633146 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (269 ms)
11596 23:11:37.642720 [0:03:07.678660266] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11597 23:11:37.740787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11598 23:11:37.741489 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11600 23:11:37.754401 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11601 23:11:37.933784 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (301 ms)
11602 23:11:37.943308 [0:03:07.979649717] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11603 23:11:38.018453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11604 23:11:38.018953 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11606 23:11:38.032615 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11607 23:11:38.366467 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (433 ms)
11608 23:11:38.376440 [0:03:08.413045798] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11609 23:11:38.475876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11610 23:11:38.476306 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11612 23:11:38.486676 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11613 23:11:38.900229 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (533 ms)
11614 23:11:38.909874 [0:03:08.945029513] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11615 23:11:38.991323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11616 23:11:38.992028 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11618 23:11:39.005085 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11619 23:11:39.597655 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (698 ms)
11620 23:11:39.607301 [0:03:09.643865731] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11621 23:11:39.694962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11622 23:11:39.695677 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11624 23:11:39.711289 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11625 23:11:40.499405 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (902 ms)
11626 23:11:40.509006 [0:03:10.545632861] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11627 23:11:40.600635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11628 23:11:40.601367 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11630 23:11:40.612246 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11631 23:11:41.897653 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1399 ms)
11632 23:11:41.907589 [0:03:11.944355253] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11633 23:11:41.991056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11634 23:11:41.991387 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11636 23:11:42.003423 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11637 23:11:43.996463 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2098 ms)
11638 23:11:44.006368 [0:03:14.043328671] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11639 23:11:44.102799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11640 23:11:44.103598 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11642 23:11:44.118280 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11643 23:11:47.228002 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3232 ms)
11644 23:11:47.237968 [0:03:17.274274546] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11645 23:11:47.327652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11646 23:11:47.328435 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11648 23:11:47.341331 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11649 23:11:47.526954 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (299 ms)
11650 23:11:47.536787 [0:03:17.573732801] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11651 23:11:47.625798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11652 23:11:47.626560 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11654 23:11:47.639340 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11655 23:11:47.893930 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (367 ms)
11656 23:11:47.903443 [0:03:17.940735796] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11657 23:11:47.995075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11658 23:11:47.995791 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11660 23:11:48.009251 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11661 23:11:48.197012 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (303 ms)
11662 23:11:48.206495 [0:03:18.243612612] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11663 23:11:48.300105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11664 23:11:48.300820 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11666 23:11:48.315146 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11667 23:11:48.630170 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (433 ms)
11668 23:11:48.639977 [0:03:18.676588158] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11669 23:11:48.734716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11670 23:11:48.735488 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11672 23:11:48.750390 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11673 23:11:49.163178 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (533 ms)
11674 23:11:49.172454 [0:03:19.209729657] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11675 23:11:49.265502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11676 23:11:49.266237 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11678 23:11:49.281491 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11679 23:11:49.862400 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (699 ms)
11680 23:11:49.872157 [0:03:19.909403484] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11681 23:11:49.957234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11682 23:11:49.957932 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11684 23:11:49.967801 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11685 23:11:50.763514 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (900 ms)
11686 23:11:50.772777 [0:03:20.809738088] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11687 23:11:50.859788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11688 23:11:50.860554 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11690 23:11:50.875840 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11691 23:11:52.161757 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1398 ms)
11692 23:11:52.171348 [0:03:22.208272202] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11693 23:11:52.263134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11694 23:11:52.263956 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11696 23:11:52.277091 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11697 23:11:54.260038 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2098 ms)
11698 23:11:54.269813 [0:03:24.306967156] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11699 23:11:54.359347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11700 23:11:54.359632 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11702 23:11:54.372272 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11703 23:11:57.490607 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3232 ms)
11704 23:11:57.500699 [0:03:27.538152520] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11705 23:11:57.579582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11706 23:11:57.579909 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11708 23:11:57.591782 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11709 23:11:57.790118 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (299 ms)
11710 23:11:57.799504 [0:03:27.837357416] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11711 23:11:57.868100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11712 23:11:57.868423 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11714 23:11:57.882918 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11715 23:11:58.122643 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (333 ms)
11716 23:11:58.132437 [0:03:28.170222472] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11717 23:11:58.209697 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11719 23:11:58.212550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11720 23:11:58.224022 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11721 23:11:58.423923 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (301 ms)
11722 23:11:58.433663 [0:03:28.471562760] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11723 23:11:58.501067 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11725 23:11:58.504130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11726 23:11:58.513251 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11727 23:11:58.889677 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (466 ms)
11728 23:11:58.899509 [0:03:28.937047296] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11729 23:11:58.974288 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11731 23:11:58.977190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11732 23:11:58.990186 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11733 23:11:59.455769 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (566 ms)
11734 23:11:59.465498 [0:03:29.503643638] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11735 23:11:59.532251 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11737 23:11:59.535049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11738 23:11:59.546222 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11739 23:12:00.155344 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (699 ms)
11740 23:12:00.165066 [0:03:30.203217620] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11741 23:12:00.234863 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11743 23:12:00.237943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11744 23:12:00.249933 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11745 23:12:01.055853 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (901 ms)
11746 23:12:01.065647 [0:03:31.103926501] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11747 23:12:01.140207 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11749 23:12:01.143400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11750 23:12:01.154668 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11751 23:12:02.454841 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1399 ms)
11752 23:12:02.464624 [0:03:32.502945897] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11753 23:12:02.536577 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11755 23:12:02.539795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11756 23:12:02.551768 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11757 23:12:04.553494 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2099 ms)
11758 23:12:04.563460 [0:03:34.601779363] [412] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11759 23:12:04.635252 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11761 23:12:04.637949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11762 23:12:04.648039 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11763 23:12:07.786095 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3233 ms)
11764 23:12:07.872292 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11766 23:12:07.875872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11767 23:12:07.886220 [----------] 120 tests from CaptureTests/SingleStream (190182 ms total)
11768 23:12:07.948738
11769 23:12:08.025509 [----------] Global test environment tear-down
11770 23:12:08.090790 [==========] 120 tests from 1 test suite ran. (190183 ms total)
11771 23:12:08.157925 <LAVA_SIGNAL_TESTSET STOP>
11772 23:12:08.158258 Received signal: <TESTSET> STOP
11773 23:12:08.158335 Closing test_set CaptureTests/SingleStream
11774 23:12:08.167577 + set +x
11775 23:12:08.170558 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 12395352_1.6.2.3.1>
11776 23:12:08.170812 Received signal: <ENDRUN> 0_lc-compliance 12395352_1.6.2.3.1
11777 23:12:08.170894 Ending use of test pattern.
11778 23:12:08.170982 Ending test lava.0_lc-compliance (12395352_1.6.2.3.1), duration 191.80
11780 23:12:08.174062 <LAVA_TEST_RUNNER EXIT>
11781 23:12:08.174328 ok: lava_test_shell seems to have completed
11782 23:12:08.176185 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11783 23:12:08.176362 end: 3.1 lava-test-shell (duration 00:03:12) [common]
11784 23:12:08.176448 end: 3 lava-test-retry (duration 00:03:12) [common]
11785 23:12:08.176536 start: 4 finalize (timeout 00:10:00) [common]
11786 23:12:08.176623 start: 4.1 power-off (timeout 00:00:30) [common]
11787 23:12:08.176773 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11788 23:12:08.254969 >> Command sent successfully.
11789 23:12:08.257488 Returned 0 in 0 seconds
11790 23:12:08.357929 end: 4.1 power-off (duration 00:00:00) [common]
11792 23:12:08.358318 start: 4.2 read-feedback (timeout 00:10:00) [common]
11793 23:12:08.358634 Listened to connection for namespace 'common' for up to 1s
11794 23:12:09.359171 Finalising connection for namespace 'common'
11795 23:12:09.359552 Disconnecting from shell: Finalise
11796 23:12:09.359769 / #
11797 23:12:09.460450 end: 4.2 read-feedback (duration 00:00:01) [common]
11798 23:12:09.461105 end: 4 finalize (duration 00:00:01) [common]
11799 23:12:09.461647 Cleaning after the job
11800 23:12:09.462144 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395352/tftp-deploy-70s7j2a6/ramdisk
11801 23:12:09.470902 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395352/tftp-deploy-70s7j2a6/kernel
11802 23:12:09.491546 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395352/tftp-deploy-70s7j2a6/dtb
11803 23:12:09.491838 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395352/tftp-deploy-70s7j2a6/nfsrootfs
11804 23:12:09.538830 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395352/tftp-deploy-70s7j2a6/modules
11805 23:12:09.544301 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12395352
11806 23:12:09.814439 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12395352
11807 23:12:09.814636 Job finished correctly