Boot log: mt8192-asurada-spherion-r0

    1 23:08:38.007639  lava-dispatcher, installed at version: 2023.10
    2 23:08:38.007864  start: 0 validate
    3 23:08:38.007997  Start time: 2023-12-27 23:08:38.007990+00:00 (UTC)
    4 23:08:38.008120  Using caching service: 'http://localhost/cache/?uri=%s'
    5 23:08:38.008251  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
    6 23:08:38.275425  Using caching service: 'http://localhost/cache/?uri=%s'
    7 23:08:38.275616  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
    8 23:08:38.532574  Using caching service: 'http://localhost/cache/?uri=%s'
    9 23:08:38.532840  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
   10 23:08:56.490410  Using caching service: 'http://localhost/cache/?uri=%s'
   11 23:08:56.490574  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
   12 23:08:57.002491  validate duration: 18.99
   14 23:08:57.002812  start: 1 tftp-deploy (timeout 00:10:00) [common]
   15 23:08:57.002947  start: 1.1 download-retry (timeout 00:10:00) [common]
   16 23:08:57.003038  start: 1.1.1 http-download (timeout 00:10:00) [common]
   17 23:08:57.003160  Not decompressing ramdisk as can be used compressed.
   18 23:08:57.003246  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
   19 23:08:57.003310  saving as /var/lib/lava/dispatcher/tmp/12395368/tftp-deploy-rxfkiwk3/ramdisk/rootfs.cpio.gz
   20 23:08:57.003377  total size: 84918747 (80 MB)
   21 23:09:02.780574  progress   0 % (0 MB)
   22 23:09:02.802664  progress   5 % (4 MB)
   23 23:09:02.824617  progress  10 % (8 MB)
   24 23:09:02.847110  progress  15 % (12 MB)
   25 23:09:02.873760  progress  20 % (16 MB)
   26 23:09:02.895776  progress  25 % (20 MB)
   27 23:09:02.925193  progress  30 % (24 MB)
   28 23:09:02.948550  progress  35 % (28 MB)
   29 23:09:02.971147  progress  40 % (32 MB)
   30 23:09:02.994564  progress  45 % (36 MB)
   31 23:09:03.016815  progress  50 % (40 MB)
   32 23:09:03.039112  progress  55 % (44 MB)
   33 23:09:03.061305  progress  60 % (48 MB)
   34 23:09:03.083684  progress  65 % (52 MB)
   35 23:09:03.106200  progress  70 % (56 MB)
   36 23:09:03.129190  progress  75 % (60 MB)
   37 23:09:03.151535  progress  80 % (64 MB)
   38 23:09:03.174018  progress  85 % (68 MB)
   39 23:09:03.196377  progress  90 % (72 MB)
   40 23:09:03.218805  progress  95 % (76 MB)
   41 23:09:03.241995  progress 100 % (80 MB)
   42 23:09:03.242276  80 MB downloaded in 6.24 s (12.98 MB/s)
   43 23:09:03.242490  end: 1.1.1 http-download (duration 00:00:06) [common]
   45 23:09:03.242877  end: 1.1 download-retry (duration 00:00:06) [common]
   46 23:09:03.242997  start: 1.2 download-retry (timeout 00:09:54) [common]
   47 23:09:03.243120  start: 1.2.1 http-download (timeout 00:09:54) [common]
   48 23:09:03.243293  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
   49 23:09:03.243390  saving as /var/lib/lava/dispatcher/tmp/12395368/tftp-deploy-rxfkiwk3/kernel/Image
   50 23:09:03.243486  total size: 50024960 (47 MB)
   51 23:09:03.243578  No compression specified
   52 23:09:03.245030  progress   0 % (0 MB)
   53 23:09:03.258684  progress   5 % (2 MB)
   54 23:09:03.273566  progress  10 % (4 MB)
   55 23:09:03.288755  progress  15 % (7 MB)
   56 23:09:03.302968  progress  20 % (9 MB)
   57 23:09:03.316618  progress  25 % (11 MB)
   58 23:09:03.330802  progress  30 % (14 MB)
   59 23:09:03.345587  progress  35 % (16 MB)
   60 23:09:03.360105  progress  40 % (19 MB)
   61 23:09:03.374375  progress  45 % (21 MB)
   62 23:09:03.388566  progress  50 % (23 MB)
   63 23:09:03.404333  progress  55 % (26 MB)
   64 23:09:03.419927  progress  60 % (28 MB)
   65 23:09:03.433306  progress  65 % (31 MB)
   66 23:09:03.446493  progress  70 % (33 MB)
   67 23:09:03.459580  progress  75 % (35 MB)
   68 23:09:03.472879  progress  80 % (38 MB)
   69 23:09:03.486111  progress  85 % (40 MB)
   70 23:09:03.503407  progress  90 % (42 MB)
   71 23:09:03.521860  progress  95 % (45 MB)
   72 23:09:03.540778  progress 100 % (47 MB)
   73 23:09:03.541155  47 MB downloaded in 0.30 s (160.27 MB/s)
   74 23:09:03.541437  end: 1.2.1 http-download (duration 00:00:00) [common]
   76 23:09:03.541850  end: 1.2 download-retry (duration 00:00:00) [common]
   77 23:09:03.542024  start: 1.3 download-retry (timeout 00:09:53) [common]
   78 23:09:03.542172  start: 1.3.1 http-download (timeout 00:09:53) [common]
   79 23:09:03.542382  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
   80 23:09:03.542502  saving as /var/lib/lava/dispatcher/tmp/12395368/tftp-deploy-rxfkiwk3/dtb/mt8192-asurada-spherion-r0.dtb
   81 23:09:03.542607  total size: 47278 (0 MB)
   82 23:09:03.542719  No compression specified
   83 23:09:03.544686  progress  69 % (0 MB)
   84 23:09:03.545113  progress 100 % (0 MB)
   85 23:09:03.545374  0 MB downloaded in 0.00 s (16.31 MB/s)
   86 23:09:03.545586  end: 1.3.1 http-download (duration 00:00:00) [common]
   88 23:09:03.546015  end: 1.3 download-retry (duration 00:00:00) [common]
   89 23:09:03.546214  start: 1.4 download-retry (timeout 00:09:53) [common]
   90 23:09:03.546375  start: 1.4.1 http-download (timeout 00:09:53) [common]
   91 23:09:03.546595  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
   92 23:09:03.546761  saving as /var/lib/lava/dispatcher/tmp/12395368/tftp-deploy-rxfkiwk3/modules/modules.tar
   93 23:09:03.546914  total size: 8633892 (8 MB)
   94 23:09:03.547053  Using unxz to decompress xz
   95 23:09:03.552855  progress   0 % (0 MB)
   96 23:09:03.575387  progress   5 % (0 MB)
   97 23:09:03.601069  progress  10 % (0 MB)
   98 23:09:03.625597  progress  15 % (1 MB)
   99 23:09:03.650625  progress  20 % (1 MB)
  100 23:09:03.676414  progress  25 % (2 MB)
  101 23:09:03.706685  progress  30 % (2 MB)
  102 23:09:03.733627  progress  35 % (2 MB)
  103 23:09:03.758743  progress  40 % (3 MB)
  104 23:09:03.784797  progress  45 % (3 MB)
  105 23:09:03.812473  progress  50 % (4 MB)
  106 23:09:03.838934  progress  55 % (4 MB)
  107 23:09:03.877365  progress  60 % (4 MB)
  108 23:09:03.904169  progress  65 % (5 MB)
  109 23:09:03.929693  progress  70 % (5 MB)
  110 23:09:03.953717  progress  75 % (6 MB)
  111 23:09:03.982561  progress  80 % (6 MB)
  112 23:09:04.015077  progress  85 % (7 MB)
  113 23:09:04.053944  progress  90 % (7 MB)
  114 23:09:04.095628  progress  95 % (7 MB)
  115 23:09:04.133048  progress 100 % (8 MB)
  116 23:09:04.141120  8 MB downloaded in 0.59 s (13.86 MB/s)
  117 23:09:04.141526  end: 1.4.1 http-download (duration 00:00:01) [common]
  119 23:09:04.142000  end: 1.4 download-retry (duration 00:00:01) [common]
  120 23:09:04.142153  start: 1.5 prepare-tftp-overlay (timeout 00:09:53) [common]
  121 23:09:04.142316  start: 1.5.1 extract-nfsrootfs (timeout 00:09:53) [common]
  122 23:09:04.142462  end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
  123 23:09:04.142611  start: 1.5.2 lava-overlay (timeout 00:09:53) [common]
  124 23:09:04.142934  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9
  125 23:09:04.143155  makedir: /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin
  126 23:09:04.143328  makedir: /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/tests
  127 23:09:04.143500  makedir: /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/results
  128 23:09:04.143689  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-add-keys
  129 23:09:04.143921  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-add-sources
  130 23:09:04.144134  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-background-process-start
  131 23:09:04.144347  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-background-process-stop
  132 23:09:04.144554  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-common-functions
  133 23:09:04.144763  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-echo-ipv4
  134 23:09:04.144969  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-install-packages
  135 23:09:04.145174  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-installed-packages
  136 23:09:04.145378  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-os-build
  137 23:09:04.145586  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-probe-channel
  138 23:09:04.145796  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-probe-ip
  139 23:09:04.146001  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-target-ip
  140 23:09:04.146205  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-target-mac
  141 23:09:04.146414  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-target-storage
  142 23:09:04.146629  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-test-case
  143 23:09:04.146831  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-test-event
  144 23:09:04.147041  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-test-feedback
  145 23:09:04.147250  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-test-raise
  146 23:09:04.147464  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-test-reference
  147 23:09:04.147675  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-test-runner
  148 23:09:04.147880  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-test-set
  149 23:09:04.148091  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-test-shell
  150 23:09:04.148310  Updating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-install-packages (oe)
  151 23:09:04.148561  Updating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/bin/lava-installed-packages (oe)
  152 23:09:04.148769  Creating /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/environment
  153 23:09:04.148939  LAVA metadata
  154 23:09:04.149066  - LAVA_JOB_ID=12395368
  155 23:09:04.149191  - LAVA_DISPATCHER_IP=192.168.201.1
  156 23:09:04.149373  start: 1.5.2.1 lava-vland-overlay (timeout 00:09:53) [common]
  157 23:09:04.149505  skipped lava-vland-overlay
  158 23:09:04.149644  end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
  159 23:09:04.149794  start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:53) [common]
  160 23:09:04.149916  skipped lava-multinode-overlay
  161 23:09:04.150057  end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
  162 23:09:04.150206  start: 1.5.2.3 test-definition (timeout 00:09:53) [common]
  163 23:09:04.150341  Loading test definitions
  164 23:09:04.150506  start: 1.5.2.3.1 git-repo-action (timeout 00:09:53) [common]
  165 23:09:04.150644  Using /lava-12395368 at stage 0
  166 23:09:04.150818  Fetching tests from https://github.com/kernelci/kernelci-core
  167 23:09:04.150964  Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/0/tests/0_sleep'
  168 23:09:04.791913  Removing '.git' directory in /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/0/tests/0_sleep
  169 23:09:04.794242  Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/0/tests/0_sleep/config/lava/sleep/sleep.yaml
  170 23:09:04.795049  uuid=12395368_1.5.2.3.1 testdef=None
  171 23:09:04.795323  end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
  173 23:09:04.795927  start: 1.5.2.3.2 test-overlay (timeout 00:09:52) [common]
  174 23:09:04.797198  end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
  176 23:09:04.797750  start: 1.5.2.3.3 test-install-overlay (timeout 00:09:52) [common]
  177 23:09:04.799357  end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
  179 23:09:04.799944  start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:52) [common]
  180 23:09:04.801499  runner path: /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/0/tests/0_sleep test_uuid 12395368_1.5.2.3.1
  181 23:09:04.801675  sleep_params='mem'
  182 23:09:04.801949  end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
  184 23:09:04.802503  Creating lava-test-runner.conf files
  185 23:09:04.802649  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12395368/lava-overlay-eruyelk9/lava-12395368/0 for stage 0
  186 23:09:04.802840  - 0_sleep
  187 23:09:04.803047  end: 1.5.2.3 test-definition (duration 00:00:01) [common]
  188 23:09:04.803242  start: 1.5.2.4 compress-overlay (timeout 00:09:52) [common]
  189 23:09:04.966705  end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
  190 23:09:04.966930  start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:52) [common]
  191 23:09:04.967084  end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
  192 23:09:04.967249  end: 1.5.2 lava-overlay (duration 00:00:01) [common]
  193 23:09:04.967393  start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:52) [common]
  194 23:09:07.746053  end: 1.5.3 extract-overlay-ramdisk (duration 00:00:03) [common]
  195 23:09:07.746572  start: 1.5.4 extract-modules (timeout 00:09:49) [common]
  196 23:09:07.746746  extracting modules file /var/lib/lava/dispatcher/tmp/12395368/tftp-deploy-rxfkiwk3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12395368/extract-overlay-ramdisk-7htkyrkb/ramdisk
  197 23:09:08.030135  end: 1.5.4 extract-modules (duration 00:00:00) [common]
  198 23:09:08.030318  start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
  199 23:09:08.030416  [common] Applying overlay /var/lib/lava/dispatcher/tmp/12395368/compress-overlay-mtdfijlu/overlay-1.5.2.4.tar.gz to ramdisk
  200 23:09:08.030489  [common] Applying overlay /var/lib/lava/dispatcher/tmp/12395368/compress-overlay-mtdfijlu/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12395368/extract-overlay-ramdisk-7htkyrkb/ramdisk
  201 23:09:08.133460  end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
  202 23:09:08.133633  start: 1.5.6 configure-preseed-file (timeout 00:09:49) [common]
  203 23:09:08.133725  end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
  204 23:09:08.133818  start: 1.5.7 compress-ramdisk (timeout 00:09:49) [common]
  205 23:09:08.133902  Building ramdisk /var/lib/lava/dispatcher/tmp/12395368/extract-overlay-ramdisk-7htkyrkb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12395368/extract-overlay-ramdisk-7htkyrkb/ramdisk
  206 23:09:09.890413  >> 563601 blocks

  207 23:09:20.681312  rename /var/lib/lava/dispatcher/tmp/12395368/extract-overlay-ramdisk-7htkyrkb/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12395368/tftp-deploy-rxfkiwk3/ramdisk/ramdisk.cpio.gz
  208 23:09:20.681953  end: 1.5.7 compress-ramdisk (duration 00:00:13) [common]
  209 23:09:20.682135  start: 1.5.8 prepare-kernel (timeout 00:09:36) [common]
  210 23:09:20.682286  start: 1.5.8.1 prepare-fit (timeout 00:09:36) [common]
  211 23:09:20.682455  Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12395368/tftp-deploy-rxfkiwk3/kernel/Image'
  212 23:09:34.389715  Returned 0 in 13 seconds
  213 23:09:34.490381  mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12395368/tftp-deploy-rxfkiwk3/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12395368/tftp-deploy-rxfkiwk3/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12395368/tftp-deploy-rxfkiwk3/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12395368/tftp-deploy-rxfkiwk3/kernel/image.itb
  214 23:09:35.826768  output: FIT description: Kernel Image image with one or more FDT blobs
  215 23:09:35.827157  output: Created:         Wed Dec 27 23:09:35 2023
  216 23:09:35.827236  output:  Image 0 (kernel-1)
  217 23:09:35.827330  output:   Description:  
  218 23:09:35.827430  output:   Created:      Wed Dec 27 23:09:35 2023
  219 23:09:35.827497  output:   Type:         Kernel Image
  220 23:09:35.827560  output:   Compression:  lzma compressed
  221 23:09:35.827626  output:   Data Size:    11480388 Bytes = 11211.32 KiB = 10.95 MiB
  222 23:09:35.827690  output:   Architecture: AArch64
  223 23:09:35.827755  output:   OS:           Linux
  224 23:09:35.827816  output:   Load Address: 0x00000000
  225 23:09:35.827879  output:   Entry Point:  0x00000000
  226 23:09:35.827940  output:   Hash algo:    crc32
  227 23:09:35.827999  output:   Hash value:   a55b2f0b
  228 23:09:35.828060  output:  Image 1 (fdt-1)
  229 23:09:35.828116  output:   Description:  mt8192-asurada-spherion-r0
  230 23:09:35.828172  output:   Created:      Wed Dec 27 23:09:35 2023
  231 23:09:35.828228  output:   Type:         Flat Device Tree
  232 23:09:35.828283  output:   Compression:  uncompressed
  233 23:09:35.828352  output:   Data Size:    47278 Bytes = 46.17 KiB = 0.05 MiB
  234 23:09:35.828408  output:   Architecture: AArch64
  235 23:09:35.828463  output:   Hash algo:    crc32
  236 23:09:35.828517  output:   Hash value:   cc4352de
  237 23:09:35.828572  output:  Image 2 (ramdisk-1)
  238 23:09:35.828627  output:   Description:  unavailable
  239 23:09:35.828682  output:   Created:      Wed Dec 27 23:09:35 2023
  240 23:09:35.828737  output:   Type:         RAMDisk Image
  241 23:09:35.828792  output:   Compression:  Unknown Compression
  242 23:09:35.828846  output:   Data Size:    98348930 Bytes = 96043.88 KiB = 93.79 MiB
  243 23:09:35.828902  output:   Architecture: AArch64
  244 23:09:35.828956  output:   OS:           Linux
  245 23:09:35.829011  output:   Load Address: unavailable
  246 23:09:35.829065  output:   Entry Point:  unavailable
  247 23:09:35.829119  output:   Hash algo:    crc32
  248 23:09:35.829173  output:   Hash value:   49274f90
  249 23:09:35.829228  output:  Default Configuration: 'conf-1'
  250 23:09:35.829283  output:  Configuration 0 (conf-1)
  251 23:09:35.829337  output:   Description:  mt8192-asurada-spherion-r0
  252 23:09:35.829392  output:   Kernel:       kernel-1
  253 23:09:35.829461  output:   Init Ramdisk: ramdisk-1
  254 23:09:35.829520  output:   FDT:          fdt-1
  255 23:09:35.829576  output:   Loadables:    kernel-1
  256 23:09:35.829644  output: 
  257 23:09:35.829861  end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
  258 23:09:35.829963  end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
  259 23:09:35.830080  end: 1.5 prepare-tftp-overlay (duration 00:00:32) [common]
  260 23:09:35.830179  start: 1.6 lxc-create-udev-rule-action (timeout 00:09:21) [common]
  261 23:09:35.830264  No LXC device requested
  262 23:09:35.830347  end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
  263 23:09:35.830435  start: 1.7 deploy-device-env (timeout 00:09:21) [common]
  264 23:09:35.830518  end: 1.7 deploy-device-env (duration 00:00:00) [common]
  265 23:09:35.830594  Checking files for TFTP limit of 4294967296 bytes.
  266 23:09:35.831117  end: 1 tftp-deploy (duration 00:00:39) [common]
  267 23:09:35.831232  start: 2 depthcharge-action (timeout 00:05:00) [common]
  268 23:09:35.831331  start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
  269 23:09:35.831460  substitutions:
  270 23:09:35.831531  - {DTB}: 12395368/tftp-deploy-rxfkiwk3/dtb/mt8192-asurada-spherion-r0.dtb
  271 23:09:35.831602  - {INITRD}: 12395368/tftp-deploy-rxfkiwk3/ramdisk/ramdisk.cpio.gz
  272 23:09:35.831664  - {KERNEL}: 12395368/tftp-deploy-rxfkiwk3/kernel/Image
  273 23:09:35.831725  - {LAVA_MAC}: None
  274 23:09:35.831784  - {PRESEED_CONFIG}: None
  275 23:09:35.831842  - {PRESEED_LOCAL}: None
  276 23:09:35.831900  - {RAMDISK}: 12395368/tftp-deploy-rxfkiwk3/ramdisk/ramdisk.cpio.gz
  277 23:09:35.831957  - {ROOT_PART}: None
  278 23:09:35.832014  - {ROOT}: None
  279 23:09:35.832071  - {SERVER_IP}: 192.168.201.1
  280 23:09:35.832127  - {TEE}: None
  281 23:09:35.832182  Parsed boot commands:
  282 23:09:35.832238  - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
  283 23:09:35.832444  Parsed boot commands: tftpboot 192.168.201.1 12395368/tftp-deploy-rxfkiwk3/kernel/image.itb 12395368/tftp-deploy-rxfkiwk3/kernel/cmdline 
  284 23:09:35.832540  end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
  285 23:09:35.832627  start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
  286 23:09:35.832723  start: 2.2.1 reset-connection (timeout 00:05:00) [common]
  287 23:09:35.832811  start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
  288 23:09:35.832885  Not connected, no need to disconnect.
  289 23:09:35.832962  end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
  290 23:09:35.833048  start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
  291 23:09:35.833117  [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
  292 23:09:35.837322  Setting prompt string to ['lava-test: # ']
  293 23:09:35.837730  end: 2.2.1.2 connect-device (duration 00:00:00) [common]
  294 23:09:35.837850  end: 2.2.1 reset-connection (duration 00:00:00) [common]
  295 23:09:35.837956  start: 2.2.2 reset-device (timeout 00:05:00) [common]
  296 23:09:35.838056  start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
  297 23:09:35.838269  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
  298 23:09:40.976601  >> Command sent successfully.

  299 23:09:40.980315  Returned 0 in 5 seconds
  300 23:09:41.080768  end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
  302 23:09:41.081297  end: 2.2.2 reset-device (duration 00:00:05) [common]
  303 23:09:41.081468  start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
  304 23:09:41.081623  Setting prompt string to 'Starting depthcharge on Spherion...'
  305 23:09:41.081748  Changing prompt to 'Starting depthcharge on Spherion...'
  306 23:09:41.081876  depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
  307 23:09:41.082319  [Enter `^Ec?' for help]

  308 23:09:41.253975  

  309 23:09:41.254159  

  310 23:09:41.254262  F0: 102B 0000

  311 23:09:41.254392  

  312 23:09:41.254482  F3: 1001 0000 [0200]

  313 23:09:41.254572  

  314 23:09:41.257601  F3: 1001 0000

  315 23:09:41.257687  

  316 23:09:41.257771  F7: 102D 0000

  317 23:09:41.257848  

  318 23:09:41.257908  F1: 0000 0000

  319 23:09:41.257967  

  320 23:09:41.261196  V0: 0000 0000 [0001]

  321 23:09:41.261338  

  322 23:09:41.261455  00: 0007 8000

  323 23:09:41.261576  

  324 23:09:41.265361  01: 0000 0000

  325 23:09:41.265490  

  326 23:09:41.265601  BP: 0C00 0209 [0000]

  327 23:09:41.265713  

  328 23:09:41.268151  G0: 1182 0000

  329 23:09:41.268257  

  330 23:09:41.268376  EC: 0000 0021 [4000]

  331 23:09:41.268468  

  332 23:09:41.271764  S7: 0000 0000 [0000]

  333 23:09:41.271872  

  334 23:09:41.271966  CC: 0000 0000 [0001]

  335 23:09:41.272057  

  336 23:09:41.275329  T0: 0000 0040 [010F]

  337 23:09:41.275420  

  338 23:09:41.275487  Jump to BL

  339 23:09:41.275550  

  340 23:09:41.300705  

  341 23:09:41.300883  

  342 23:09:41.300977  

  343 23:09:41.308177  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...

  344 23:09:41.312069  ARM64: Exception handlers installed.

  345 23:09:41.315796  ARM64: Testing exception

  346 23:09:41.319457  ARM64: Done test exception

  347 23:09:41.323311  Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000

  348 23:09:41.334628  Mapping address range [0x00000000:0x200000000) as     cacheable | read-write |     secure | device

  349 23:09:41.341982  Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000

  350 23:09:41.351853  Mapping address range [0x00100000:0x00120000) as     cacheable | read-write |     secure | normal

  351 23:09:41.358930  Backing address range [0x00000000:0x40000000) with new page table @0x0010f000

  352 23:09:41.365178  Backing address range [0x00000000:0x00200000) with new page table @0x00110000

  353 23:09:41.378514  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | normal

  354 23:09:41.384344  Backing address range [0x00200000:0x00400000) with new page table @0x00111000

  355 23:09:41.403271  Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write |     secure | normal

  356 23:09:41.406728  WDT: Last reset was cold boot

  357 23:09:41.409851  SPI1(PAD0) initialized at 2873684 Hz

  358 23:09:41.413490  SPI5(PAD0) initialized at 992727 Hz

  359 23:09:41.417062  VBOOT: Loading verstage.

  360 23:09:41.423835  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  361 23:09:41.426905  FMAP: Found "FLASH" version 1.1 at 0x20000.

  362 23:09:41.429847  FMAP: base = 0x0 size = 0x800000 #areas = 25

  363 23:09:41.433463  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  364 23:09:41.441010  CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes

  365 23:09:41.447726  CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150

  366 23:09:41.458566  read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps

  367 23:09:41.458741  

  368 23:09:41.458864  

  369 23:09:41.469123  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...

  370 23:09:41.472550  ARM64: Exception handlers installed.

  371 23:09:41.472692  ARM64: Testing exception

  372 23:09:41.476149  ARM64: Done test exception

  373 23:09:41.479233  FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)

  374 23:09:41.486169  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  375 23:09:41.499251  Probing TPM: . done!

  376 23:09:41.499421  TPM ready after 0 ms

  377 23:09:41.506743  Connected to device vid:did:rid of 1ae0:0028:00

  378 23:09:41.513408  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

  379 23:09:41.572709  Initialized TPM device CR50 revision 0

  380 23:09:41.584330  tlcl_send_startup: Startup return code is 0

  381 23:09:41.584553  TPM: setup succeeded

  382 23:09:41.595963  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0

  383 23:09:41.605184  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  384 23:09:41.617145  VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)

  385 23:09:41.627508  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  386 23:09:41.630751  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  387 23:09:41.634128  in-header: 03 07 00 00 08 00 00 00 

  388 23:09:41.638461  in-data: aa e4 47 04 13 02 00 00 

  389 23:09:41.642021  Chrome EC: UHEPI supported

  390 23:09:41.649299  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  391 23:09:41.652905  in-header: 03 95 00 00 08 00 00 00 

  392 23:09:41.653059  in-data: 18 20 20 08 00 00 00 00 

  393 23:09:41.656676  Phase 1

  394 23:09:41.660447  FMAP: area GBB found @ 3f5000 (12032 bytes)

  395 23:09:41.664018  VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7

  396 23:09:41.671990  VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7

  397 23:09:41.672175  Recovery requested (1009000e)

  398 23:09:41.682496  TPM: Extending digest for VBOOT: boot mode into PCR 0

  399 23:09:41.688537  tlcl_extend: response is 0

  400 23:09:41.697956  TPM: Extending digest for VBOOT: GBB HWID into PCR 1

  401 23:09:41.703405  tlcl_extend: response is 0

  402 23:09:41.710261  CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c

  403 23:09:41.730398  read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps

  404 23:09:41.737030  BS: bootblock times (exec / console): total (unknown) / 148 ms

  405 23:09:41.737157  

  406 23:09:41.737232  

  407 23:09:41.746559  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...

  408 23:09:41.750272  ARM64: Exception handlers installed.

  409 23:09:41.753236  ARM64: Testing exception

  410 23:09:41.753332  ARM64: Done test exception

  411 23:09:41.775541  pmic_efuse_setting: Set efuses in 11 msecs

  412 23:09:41.779360  pmwrap_interface_init: Select PMIF_VLD_RDY

  413 23:09:41.785620  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a

  414 23:09:41.789289  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a

  415 23:09:41.796423  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a

  416 23:09:41.800116  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a

  417 23:09:41.804067  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a

  418 23:09:41.807833  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a

  419 23:09:41.815214  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a

  420 23:09:41.818966  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a

  421 23:09:41.822552  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c

  422 23:09:41.826903  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a

  423 23:09:41.833743  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a

  424 23:09:41.837363  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c

  425 23:09:41.841786  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c

  426 23:09:41.848949  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a

  427 23:09:41.852967  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a

  428 23:09:41.860348  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a

  429 23:09:41.864013  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a

  430 23:09:41.871679  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a

  431 23:09:41.875612  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a

  432 23:09:41.883048  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a

  433 23:09:41.886919  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c

  434 23:09:41.894633  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a

  435 23:09:41.898266  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a

  436 23:09:41.905202  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c

  437 23:09:41.908726  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c

  438 23:09:41.916294  [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa

  439 23:09:41.920460  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92

  440 23:09:41.924180  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2

  441 23:09:41.931345  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82

  442 23:09:41.935148  [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10

  443 23:09:41.938958  [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425

  444 23:09:41.946326  [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010

  445 23:09:41.950115  [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f

  446 23:09:41.953685  [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000

  447 23:09:41.960177  [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8

  448 23:09:41.964092  [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb

  449 23:09:41.971669  [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698

  450 23:09:41.975355  [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3

  451 23:09:41.979040  [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92

  452 23:09:41.982870  [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a

  453 23:09:41.986446  [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2

  454 23:09:41.994256  [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a

  455 23:09:41.997792  [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a

  456 23:09:42.001350  [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a

  457 23:09:42.005004  [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a

  458 23:09:42.009101  [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82

  459 23:09:42.012911  [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c

  460 23:09:42.016209  [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a

  461 23:09:42.023511  [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a

  462 23:09:42.027307  [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c

  463 23:09:42.031381  [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c

  464 23:09:42.038595  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248

  465 23:09:42.045864  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1

  466 23:09:42.053378  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  467 23:09:42.060707  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248

  468 23:09:42.067919  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0

  469 23:09:42.071569  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  470 23:09:42.078994  [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  471 23:09:42.082857  [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  472 23:09:42.090116  [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0

  473 23:09:42.093192  [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2

  474 23:09:42.097209  [RTC]rtc_osc_init,62: osc32con val = 0xde70

  475 23:09:42.104170  [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a

  476 23:09:42.113454  [RTC]rtc_get_frequency_meter,154: input=15, output=759

  477 23:09:42.122914  [RTC]rtc_get_frequency_meter,154: input=23, output=942

  478 23:09:42.132129  [RTC]rtc_get_frequency_meter,154: input=19, output=852

  479 23:09:42.141846  [RTC]rtc_get_frequency_meter,154: input=17, output=805

  480 23:09:42.151045  [RTC]rtc_get_frequency_meter,154: input=16, output=781

  481 23:09:42.161133  [RTC]rtc_get_frequency_meter,154: input=16, output=782

  482 23:09:42.171078  [RTC]rtc_get_frequency_meter,154: input=17, output=805

  483 23:09:42.174722  [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17

  484 23:09:42.178490  [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70

  485 23:09:42.182274  [RTC]rtc_boot_common,202: RTC_STATE_REBOOT

  486 23:09:42.189695  [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486

  487 23:09:42.194111  [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1

  488 23:09:42.197075  [RTC]rtc_bbpu_power_on,300: done BBPU=0x81

  489 23:09:42.201184  ADC[4]: Raw value=905465 ID=7

  490 23:09:42.201313  ADC[3]: Raw value=213441 ID=1

  491 23:09:42.205062  RAM Code: 0x71

  492 23:09:42.209057  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  493 23:09:42.212584  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  494 23:09:42.219991  CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014

  495 23:09:42.227475  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  496 23:09:42.231057  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  497 23:09:42.234642  in-header: 03 07 00 00 08 00 00 00 

  498 23:09:42.238885  in-data: aa e4 47 04 13 02 00 00 

  499 23:09:42.242503  Chrome EC: UHEPI supported

  500 23:09:42.246000  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  501 23:09:42.250120  in-header: 03 95 00 00 08 00 00 00 

  502 23:09:42.253512  in-data: 18 20 20 08 00 00 00 00 

  503 23:09:42.257430  MRC: failed to locate region type 0.

  504 23:09:42.264840  DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)

  505 23:09:42.268496  DRAM-K: Running full calibration

  506 23:09:42.272961  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  507 23:09:42.276701  header.status = 0x0

  508 23:09:42.280042  header.version = 0x6 (expected: 0x6)

  509 23:09:42.280185  header.size = 0xd00 (expected: 0xd00)

  510 23:09:42.283633  header.flags = 0x0

  511 23:09:42.290449  CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40

  512 23:09:42.308111  read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps

  513 23:09:42.315162  dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6

  514 23:09:42.318840  dram_init: ddr_geometry: 2

  515 23:09:42.318987  [EMI] MDL number = 2

  516 23:09:42.322484  [EMI] Get MDL freq = 0

  517 23:09:42.322630  dram_init: ddr_type: 0

  518 23:09:42.326385  is_discrete_lpddr4: 1

  519 23:09:42.330110  [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0

  520 23:09:42.330254  

  521 23:09:42.330357  

  522 23:09:42.330451  [Bian_co] ETT version 0.0.0.1

  523 23:09:42.337975   dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6

  524 23:09:42.338101  

  525 23:09:42.341635  dramc_set_vcore_voltage set vcore to 650000

  526 23:09:42.341774  Read voltage for 800, 4

  527 23:09:42.341900  Vio18 = 0

  528 23:09:42.345491  Vcore = 650000

  529 23:09:42.345629  Vdram = 0

  530 23:09:42.345748  Vddq = 0

  531 23:09:42.349311  Vmddr = 0

  532 23:09:42.349449  dram_init: config_dvfs: 1

  533 23:09:42.357169  [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0

  534 23:09:42.360257  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

  535 23:09:42.363874  [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9

  536 23:09:42.368154  freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9

  537 23:09:42.371099  [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9

  538 23:09:42.374652  freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9

  539 23:09:42.378157  MEM_TYPE=3, freq_sel=18

  540 23:09:42.381349  sv_algorithm_assistance_LP4_1600 

  541 23:09:42.384330  ============ PULL DRAM RESETB DOWN ============

  542 23:09:42.388129  ========== PULL DRAM RESETB DOWN end =========

  543 23:09:42.395105  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  544 23:09:42.399036  =================================== 

  545 23:09:42.399177  LPDDR4 DRAM CONFIGURATION

  546 23:09:42.403226  =================================== 

  547 23:09:42.403355  EX_ROW_EN[0]    = 0x0

  548 23:09:42.406845  EX_ROW_EN[1]    = 0x0

  549 23:09:42.406980  LP4Y_EN      = 0x0

  550 23:09:42.410404  WORK_FSP     = 0x0

  551 23:09:42.410535  WL           = 0x2

  552 23:09:42.414085  RL           = 0x2

  553 23:09:42.414215  BL           = 0x2

  554 23:09:42.417198  RPST         = 0x0

  555 23:09:42.417335  RD_PRE       = 0x0

  556 23:09:42.420975  WR_PRE       = 0x1

  557 23:09:42.421144  WR_PST       = 0x0

  558 23:09:42.424274  DBI_WR       = 0x0

  559 23:09:42.424413  DBI_RD       = 0x0

  560 23:09:42.427561  OTF          = 0x1

  561 23:09:42.431059  =================================== 

  562 23:09:42.434330  =================================== 

  563 23:09:42.434446  ANA top config

  564 23:09:42.437946  =================================== 

  565 23:09:42.441584  DLL_ASYNC_EN            =  0

  566 23:09:42.445122  ALL_SLAVE_EN            =  1

  567 23:09:42.445307  NEW_RANK_MODE           =  1

  568 23:09:42.448305  DLL_IDLE_MODE           =  1

  569 23:09:42.451743  LP45_APHY_COMB_EN       =  1

  570 23:09:42.455281  TX_ODT_DIS              =  1

  571 23:09:42.455415  NEW_8X_MODE             =  1

  572 23:09:42.458873  =================================== 

  573 23:09:42.462762  =================================== 

  574 23:09:42.466261  data_rate                  = 1600

  575 23:09:42.469327  CKR                        = 1

  576 23:09:42.472488  DQ_P2S_RATIO               = 8

  577 23:09:42.476062  =================================== 

  578 23:09:42.476212  CA_P2S_RATIO               = 8

  579 23:09:42.479580  DQ_CA_OPEN                 = 0

  580 23:09:42.482823  DQ_SEMI_OPEN               = 0

  581 23:09:42.485999  CA_SEMI_OPEN               = 0

  582 23:09:42.489502  CA_FULL_RATE               = 0

  583 23:09:42.492429  DQ_CKDIV4_EN               = 1

  584 23:09:42.492577  CA_CKDIV4_EN               = 1

  585 23:09:42.495931  CA_PREDIV_EN               = 0

  586 23:09:42.499478  PH8_DLY                    = 0

  587 23:09:42.502756  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

  588 23:09:42.505795  DQ_AAMCK_DIV               = 4

  589 23:09:42.509305  CA_AAMCK_DIV               = 4

  590 23:09:42.509464  CA_ADMCK_DIV               = 4

  591 23:09:42.512721  DQ_TRACK_CA_EN             = 0

  592 23:09:42.515851  CA_PICK                    = 800

  593 23:09:42.519625  CA_MCKIO                   = 800

  594 23:09:42.523167  MCKIO_SEMI                 = 0

  595 23:09:42.526930  PLL_FREQ                   = 3068

  596 23:09:42.527069  DQ_UI_PI_RATIO             = 32

  597 23:09:42.531043  CA_UI_PI_RATIO             = 0

  598 23:09:42.534908  =================================== 

  599 23:09:42.538906  =================================== 

  600 23:09:42.539048  memory_type:LPDDR4         

  601 23:09:42.542387  GP_NUM     : 10       

  602 23:09:42.542488  SRAM_EN    : 1       

  603 23:09:42.545507  MD32_EN    : 0       

  604 23:09:42.549917  =================================== 

  605 23:09:42.550031  [ANA_INIT] >>>>>>>>>>>>>> 

  606 23:09:42.553549  <<<<<< [CONFIGURE PHASE]: ANA_TX

  607 23:09:42.557888  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

  608 23:09:42.560517  =================================== 

  609 23:09:42.564147  data_rate = 1600,PCW = 0X7600

  610 23:09:42.567174  =================================== 

  611 23:09:42.570914  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

  612 23:09:42.577239  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  613 23:09:42.580776  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  614 23:09:42.587414  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

  615 23:09:42.590538  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

  616 23:09:42.594182  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

  617 23:09:42.594321  [ANA_INIT] flow start 

  618 23:09:42.597178  [ANA_INIT] PLL >>>>>>>> 

  619 23:09:42.600662  [ANA_INIT] PLL <<<<<<<< 

  620 23:09:42.600797  [ANA_INIT] MIDPI >>>>>>>> 

  621 23:09:42.603977  [ANA_INIT] MIDPI <<<<<<<< 

  622 23:09:42.607585  [ANA_INIT] DLL >>>>>>>> 

  623 23:09:42.607708  [ANA_INIT] flow end 

  624 23:09:42.613945  ============ LP4 DIFF to SE enter ============

  625 23:09:42.617559  ============ LP4 DIFF to SE exit  ============

  626 23:09:42.617657  [ANA_INIT] <<<<<<<<<<<<< 

  627 23:09:42.620573  [Flow] Enable top DCM control >>>>> 

  628 23:09:42.624006  [Flow] Enable top DCM control <<<<< 

  629 23:09:42.627350  Enable DLL master slave shuffle 

  630 23:09:42.634080  ============================================================== 

  631 23:09:42.634249  Gating Mode config

  632 23:09:42.640754  ============================================================== 

  633 23:09:42.644023  Config description: 

  634 23:09:42.654379  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

  635 23:09:42.660578  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

  636 23:09:42.664260  SELPH_MODE            0: By rank         1: By Phase 

  637 23:09:42.670851  ============================================================== 

  638 23:09:42.674267  GAT_TRACK_EN                 =  1

  639 23:09:42.677452  RX_GATING_MODE               =  2

  640 23:09:42.677599  RX_GATING_TRACK_MODE         =  2

  641 23:09:42.680602  SELPH_MODE                   =  1

  642 23:09:42.684374  PICG_EARLY_EN                =  1

  643 23:09:42.687382  VALID_LAT_VALUE              =  1

  644 23:09:42.693981  ============================================================== 

  645 23:09:42.697607  Enter into Gating configuration >>>> 

  646 23:09:42.700627  Exit from Gating configuration <<<< 

  647 23:09:42.704103  Enter into  DVFS_PRE_config >>>>> 

  648 23:09:42.714076  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

  649 23:09:42.717806  Exit from  DVFS_PRE_config <<<<< 

  650 23:09:42.721354  Enter into PICG configuration >>>> 

  651 23:09:42.724154  Exit from PICG configuration <<<< 

  652 23:09:42.727652  [RX_INPUT] configuration >>>>> 

  653 23:09:42.730934  [RX_INPUT] configuration <<<<< 

  654 23:09:42.734546  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

  655 23:09:42.740917  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

  656 23:09:42.747699  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

  657 23:09:42.750676  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

  658 23:09:42.757420  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

  659 23:09:42.764400  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

  660 23:09:42.767488  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

  661 23:09:42.771238  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

  662 23:09:42.777313  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

  663 23:09:42.781169  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

  664 23:09:42.784127  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

  665 23:09:42.791385  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  666 23:09:42.791506  =================================== 

  667 23:09:42.794352  LPDDR4 DRAM CONFIGURATION

  668 23:09:42.797920  =================================== 

  669 23:09:42.800972  EX_ROW_EN[0]    = 0x0

  670 23:09:42.801110  EX_ROW_EN[1]    = 0x0

  671 23:09:42.804147  LP4Y_EN      = 0x0

  672 23:09:42.804265  WORK_FSP     = 0x0

  673 23:09:42.808125  WL           = 0x2

  674 23:09:42.808218  RL           = 0x2

  675 23:09:42.811199  BL           = 0x2

  676 23:09:42.811287  RPST         = 0x0

  677 23:09:42.814424  RD_PRE       = 0x0

  678 23:09:42.818109  WR_PRE       = 0x1

  679 23:09:42.818204  WR_PST       = 0x0

  680 23:09:42.821407  DBI_WR       = 0x0

  681 23:09:42.821496  DBI_RD       = 0x0

  682 23:09:42.824350  OTF          = 0x1

  683 23:09:42.827909  =================================== 

  684 23:09:42.831529  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

  685 23:09:42.834698  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

  686 23:09:42.837682  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  687 23:09:42.841525  =================================== 

  688 23:09:42.844443  LPDDR4 DRAM CONFIGURATION

  689 23:09:42.847977  =================================== 

  690 23:09:42.850986  EX_ROW_EN[0]    = 0x10

  691 23:09:42.851125  EX_ROW_EN[1]    = 0x0

  692 23:09:42.854494  LP4Y_EN      = 0x0

  693 23:09:42.854628  WORK_FSP     = 0x0

  694 23:09:42.858002  WL           = 0x2

  695 23:09:42.858127  RL           = 0x2

  696 23:09:42.861022  BL           = 0x2

  697 23:09:42.861131  RPST         = 0x0

  698 23:09:42.864535  RD_PRE       = 0x0

  699 23:09:42.864620  WR_PRE       = 0x1

  700 23:09:42.868057  WR_PST       = 0x0

  701 23:09:42.868172  DBI_WR       = 0x0

  702 23:09:42.871102  DBI_RD       = 0x0

  703 23:09:42.871238  OTF          = 0x1

  704 23:09:42.874487  =================================== 

  705 23:09:42.881329  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

  706 23:09:42.886063  nWR fixed to 40

  707 23:09:42.889485  [ModeRegInit_LP4] CH0 RK0

  708 23:09:42.889585  [ModeRegInit_LP4] CH0 RK1

  709 23:09:42.892513  [ModeRegInit_LP4] CH1 RK0

  710 23:09:42.896053  [ModeRegInit_LP4] CH1 RK1

  711 23:09:42.896187  match AC timing 13

  712 23:09:42.902533  dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1

  713 23:09:42.905941  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

  714 23:09:42.909350  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

  715 23:09:42.916096  [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17

  716 23:09:42.919251  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

  717 23:09:42.919342  [EMI DOE] emi_dcm 0

  718 23:09:42.926005  [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600

  719 23:09:42.926094  ==

  720 23:09:42.929860  Dram Type= 6, Freq= 0, CH_0, rank 0

  721 23:09:42.932827  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  722 23:09:42.932943  ==

  723 23:09:42.939365  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  724 23:09:42.943163  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  725 23:09:42.953396  [CA 0] Center 36 (6~67) winsize 62

  726 23:09:42.956454  [CA 1] Center 36 (6~67) winsize 62

  727 23:09:42.959593  [CA 2] Center 34 (4~65) winsize 62

  728 23:09:42.963346  [CA 3] Center 34 (4~64) winsize 61

  729 23:09:42.966547  [CA 4] Center 33 (3~64) winsize 62

  730 23:09:42.969474  [CA 5] Center 32 (2~62) winsize 61

  731 23:09:42.969575  

  732 23:09:42.972862  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  733 23:09:42.972946  

  734 23:09:42.976444  [CATrainingPosCal] consider 1 rank data

  735 23:09:42.979719  u2DelayCellTimex100 = 270/100 ps

  736 23:09:42.983300  CA0 delay=36 (6~67),Diff = 4 PI (28 cell)

  737 23:09:42.989606  CA1 delay=36 (6~67),Diff = 4 PI (28 cell)

  738 23:09:42.993009  CA2 delay=34 (4~65),Diff = 2 PI (14 cell)

  739 23:09:42.996453  CA3 delay=34 (4~64),Diff = 2 PI (14 cell)

  740 23:09:42.999597  CA4 delay=33 (3~64),Diff = 1 PI (7 cell)

  741 23:09:43.002877  CA5 delay=32 (2~62),Diff = 0 PI (0 cell)

  742 23:09:43.002988  

  743 23:09:43.006630  CA PerBit enable=1, Macro0, CA PI delay=32

  744 23:09:43.006744  

  745 23:09:43.010065  [CBTSetCACLKResult] CA Dly = 32

  746 23:09:43.010177  CS Dly: 4 (0~35)

  747 23:09:43.012936  ==

  748 23:09:43.016615  Dram Type= 6, Freq= 0, CH_0, rank 1

  749 23:09:43.019883  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  750 23:09:43.019995  ==

  751 23:09:43.022897  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  752 23:09:43.029745  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  753 23:09:43.039619  [CA 0] Center 36 (6~67) winsize 62

  754 23:09:43.043169  [CA 1] Center 36 (6~67) winsize 62

  755 23:09:43.046275  [CA 2] Center 34 (3~65) winsize 63

  756 23:09:43.049383  [CA 3] Center 34 (4~65) winsize 62

  757 23:09:43.052903  [CA 4] Center 32 (2~63) winsize 62

  758 23:09:43.056037  [CA 5] Center 32 (2~63) winsize 62

  759 23:09:43.056150  

  760 23:09:43.059697  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  761 23:09:43.059810  

  762 23:09:43.062702  [CATrainingPosCal] consider 2 rank data

  763 23:09:43.066570  u2DelayCellTimex100 = 270/100 ps

  764 23:09:43.069718  CA0 delay=36 (6~67),Diff = 4 PI (28 cell)

  765 23:09:43.072855  CA1 delay=36 (6~67),Diff = 4 PI (28 cell)

  766 23:09:43.079670  CA2 delay=34 (4~65),Diff = 2 PI (14 cell)

  767 23:09:43.082641  CA3 delay=34 (4~64),Diff = 2 PI (14 cell)

  768 23:09:43.086172  CA4 delay=33 (3~63),Diff = 1 PI (7 cell)

  769 23:09:43.089534  CA5 delay=32 (2~62),Diff = 0 PI (0 cell)

  770 23:09:43.089614  

  771 23:09:43.093027  CA PerBit enable=1, Macro0, CA PI delay=32

  772 23:09:43.093141  

  773 23:09:43.096044  [CBTSetCACLKResult] CA Dly = 32

  774 23:09:43.096156  CS Dly: 5 (0~37)

  775 23:09:43.096265  

  776 23:09:43.099536  ----->DramcWriteLeveling(PI) begin...

  777 23:09:43.103454  ==

  778 23:09:43.103549  Dram Type= 6, Freq= 0, CH_0, rank 0

  779 23:09:43.110844  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  780 23:09:43.110974  ==

  781 23:09:43.111081  Write leveling (Byte 0): 34 => 34

  782 23:09:43.114458  Write leveling (Byte 1): 31 => 31

  783 23:09:43.118732  DramcWriteLeveling(PI) end<-----

  784 23:09:43.118858  

  785 23:09:43.118987  ==

  786 23:09:43.122151  Dram Type= 6, Freq= 0, CH_0, rank 0

  787 23:09:43.125175  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  788 23:09:43.125295  ==

  789 23:09:43.128526  [Gating] SW mode calibration

  790 23:09:43.136183  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

  791 23:09:43.142962  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

  792 23:09:43.146439   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  793 23:09:43.149368   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

  794 23:09:43.152399   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

  795 23:09:43.159711   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  796 23:09:43.162648   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  797 23:09:43.165799   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  798 23:09:43.172665   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  799 23:09:43.175864   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  800 23:09:43.179544   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  801 23:09:43.185866   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  802 23:09:43.189023   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  803 23:09:43.192659   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  804 23:09:43.199550   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  805 23:09:43.202914   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  806 23:09:43.205876   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  807 23:09:43.212520   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  808 23:09:43.216071   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

  809 23:09:43.219395   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

  810 23:09:43.226122   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

  811 23:09:43.229678   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  812 23:09:43.232499   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  813 23:09:43.236047   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  814 23:09:43.243057   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  815 23:09:43.246070   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  816 23:09:43.249864   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  817 23:09:43.256328   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  818 23:09:43.259547   0  9  8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)

  819 23:09:43.262833   0  9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)

  820 23:09:43.270007   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  821 23:09:43.273103   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  822 23:09:43.276305   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  823 23:09:43.282942   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  824 23:09:43.286713   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  825 23:09:43.289936   0 10  4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)

  826 23:09:43.296672   0 10  8 | B1->B0 | 3030 2323 | 1 0 | (1 0) (1 0)

  827 23:09:43.299810   0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)

  828 23:09:43.302918   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  829 23:09:43.306393   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  830 23:09:43.312996   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  831 23:09:43.316530   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  832 23:09:43.319564   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  833 23:09:43.326165   0 11  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  834 23:09:43.329822   0 11  8 | B1->B0 | 2d2d 3f3f | 0 0 | (0 0) (0 0)

  835 23:09:43.333247   0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)

  836 23:09:43.339805   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  837 23:09:43.342989   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  838 23:09:43.346509   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  839 23:09:43.353418   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  840 23:09:43.356381   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  841 23:09:43.359975   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

  842 23:09:43.366379   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

  843 23:09:43.369832   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

  844 23:09:43.373409   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  845 23:09:43.379870   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  846 23:09:43.383062   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  847 23:09:43.386727   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  848 23:09:43.389823   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  849 23:09:43.396675   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  850 23:09:43.399828   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  851 23:09:43.403608   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  852 23:09:43.409809   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  853 23:09:43.413303   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  854 23:09:43.416935   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  855 23:09:43.423299   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  856 23:09:43.426370   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  857 23:09:43.429946   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

  858 23:09:43.436680   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

  859 23:09:43.439695   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  860 23:09:43.443463  Total UI for P1: 0, mck2ui 16

  861 23:09:43.446446  best dqsien dly found for B0: ( 0, 14,  6)

  862 23:09:43.449686  Total UI for P1: 0, mck2ui 16

  863 23:09:43.453486  best dqsien dly found for B1: ( 0, 14, 10)

  864 23:09:43.457270  best DQS0 dly(MCK, UI, PI) = (0, 14, 6)

  865 23:09:43.460549  best DQS1 dly(MCK, UI, PI) = (0, 14, 10)

  866 23:09:43.460637  

  867 23:09:43.464297  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)

  868 23:09:43.467415  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)

  869 23:09:43.471131  [Gating] SW calibration Done

  870 23:09:43.471244  ==

  871 23:09:43.474036  Dram Type= 6, Freq= 0, CH_0, rank 0

  872 23:09:43.477583  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  873 23:09:43.477701  ==

  874 23:09:43.480506  RX Vref Scan: 0

  875 23:09:43.480614  

  876 23:09:43.480724  RX Vref 0 -> 0, step: 1

  877 23:09:43.480822  

  878 23:09:43.484027  RX Delay -130 -> 252, step: 16

  879 23:09:43.487258  iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240

  880 23:09:43.494291  iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224

  881 23:09:43.497422  iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240

  882 23:09:43.500653  iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240

  883 23:09:43.503973  iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224

  884 23:09:43.507329  iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224

  885 23:09:43.514687  iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224

  886 23:09:43.517609  iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224

  887 23:09:43.521263  iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224

  888 23:09:43.524428  iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224

  889 23:09:43.527301  iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224

  890 23:09:43.534655  iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224

  891 23:09:43.537563  iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240

  892 23:09:43.541185  iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240

  893 23:09:43.544226  iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224

  894 23:09:43.547398  iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240

  895 23:09:43.547525  ==

  896 23:09:43.551146  Dram Type= 6, Freq= 0, CH_0, rank 0

  897 23:09:43.557617  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  898 23:09:43.557753  ==

  899 23:09:43.557868  DQS Delay:

  900 23:09:43.561109  DQS0 = 0, DQS1 = 0

  901 23:09:43.561236  DQM Delay:

  902 23:09:43.561349  DQM0 = 88, DQM1 = 82

  903 23:09:43.564156  DQ Delay:

  904 23:09:43.567446  DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85

  905 23:09:43.570787  DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93

  906 23:09:43.574417  DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77

  907 23:09:43.577343  DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85

  908 23:09:43.577473  

  909 23:09:43.577587  

  910 23:09:43.577696  ==

  911 23:09:43.581065  Dram Type= 6, Freq= 0, CH_0, rank 0

  912 23:09:43.584126  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  913 23:09:43.584256  ==

  914 23:09:43.584380  

  915 23:09:43.584489  

  916 23:09:43.587808  	TX Vref Scan disable

  917 23:09:43.587934   == TX Byte 0 ==

  918 23:09:43.594377  Update DQ  dly =585 (2 ,1, 41)  DQ  OEN =(1 ,6)

  919 23:09:43.597627  Update DQM dly =585 (2 ,1, 41)  DQM OEN =(1 ,6)

  920 23:09:43.597754   == TX Byte 1 ==

  921 23:09:43.604818  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

  922 23:09:43.607874  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

  923 23:09:43.608003  ==

  924 23:09:43.611399  Dram Type= 6, Freq= 0, CH_0, rank 0

  925 23:09:43.614252  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  926 23:09:43.614381  ==

  927 23:09:43.628994  TX Vref=22, minBit 8, minWin=27, winSum=446

  928 23:09:43.631990  TX Vref=24, minBit 10, minWin=27, winSum=451

  929 23:09:43.635495  TX Vref=26, minBit 9, minWin=27, winSum=452

  930 23:09:43.638923  TX Vref=28, minBit 5, minWin=28, winSum=455

  931 23:09:43.642243  TX Vref=30, minBit 5, minWin=28, winSum=459

  932 23:09:43.645475  TX Vref=32, minBit 2, minWin=28, winSum=452

  933 23:09:43.652340  [TxChooseVref] Worse bit 5, Min win 28, Win sum 459, Final Vref 30

  934 23:09:43.652472  

  935 23:09:43.655594  Final TX Range 1 Vref 30

  936 23:09:43.655718  

  937 23:09:43.655830  ==

  938 23:09:43.658570  Dram Type= 6, Freq= 0, CH_0, rank 0

  939 23:09:43.662287  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  940 23:09:43.662416  ==

  941 23:09:43.662530  

  942 23:09:43.665411  

  943 23:09:43.665534  	TX Vref Scan disable

  944 23:09:43.668931   == TX Byte 0 ==

  945 23:09:43.672475  Update DQ  dly =584 (2 ,1, 40)  DQ  OEN =(1 ,6)

  946 23:09:43.675230  Update DQM dly =584 (2 ,1, 40)  DQM OEN =(1 ,6)

  947 23:09:43.678567   == TX Byte 1 ==

  948 23:09:43.682043  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

  949 23:09:43.685606  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

  950 23:09:43.688653  

  951 23:09:43.688779  [DATLAT]

  952 23:09:43.688893  Freq=800, CH0 RK0

  953 23:09:43.689003  

  954 23:09:43.691709  DATLAT Default: 0xa

  955 23:09:43.691830  0, 0xFFFF, sum = 0

  956 23:09:43.695394  1, 0xFFFF, sum = 0

  957 23:09:43.695523  2, 0xFFFF, sum = 0

  958 23:09:43.698497  3, 0xFFFF, sum = 0

  959 23:09:43.702215  4, 0xFFFF, sum = 0

  960 23:09:43.702340  5, 0xFFFF, sum = 0

  961 23:09:43.705162  6, 0xFFFF, sum = 0

  962 23:09:43.705284  7, 0xFFFF, sum = 0

  963 23:09:43.708658  8, 0xFFFF, sum = 0

  964 23:09:43.708785  9, 0x0, sum = 1

  965 23:09:43.708896  10, 0x0, sum = 2

  966 23:09:43.712009  11, 0x0, sum = 3

  967 23:09:43.712139  12, 0x0, sum = 4

  968 23:09:43.715562  best_step = 10

  969 23:09:43.715686  

  970 23:09:43.715797  ==

  971 23:09:43.718772  Dram Type= 6, Freq= 0, CH_0, rank 0

  972 23:09:43.722214  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  973 23:09:43.722343  ==

  974 23:09:43.725413  RX Vref Scan: 1

  975 23:09:43.725538  

  976 23:09:43.725650  Set Vref Range= 32 -> 127

  977 23:09:43.728564  

  978 23:09:43.728689  RX Vref 32 -> 127, step: 1

  979 23:09:43.728801  

  980 23:09:43.731698  RX Delay -79 -> 252, step: 8

  981 23:09:43.731820  

  982 23:09:43.735180  Set Vref, RX VrefLevel [Byte0]: 32

  983 23:09:43.738838                           [Byte1]: 32

  984 23:09:43.738966  

  985 23:09:43.741871  Set Vref, RX VrefLevel [Byte0]: 33

  986 23:09:43.745483                           [Byte1]: 33

  987 23:09:43.749049  

  988 23:09:43.749175  Set Vref, RX VrefLevel [Byte0]: 34

  989 23:09:43.752495                           [Byte1]: 34

  990 23:09:43.756447  

  991 23:09:43.756574  Set Vref, RX VrefLevel [Byte0]: 35

  992 23:09:43.760215                           [Byte1]: 35

  993 23:09:43.764571  

  994 23:09:43.764702  Set Vref, RX VrefLevel [Byte0]: 36

  995 23:09:43.767616                           [Byte1]: 36

  996 23:09:43.771860  

  997 23:09:43.771993  Set Vref, RX VrefLevel [Byte0]: 37

  998 23:09:43.774875                           [Byte1]: 37

  999 23:09:43.780064  

 1000 23:09:43.780155  Set Vref, RX VrefLevel [Byte0]: 38

 1001 23:09:43.783038                           [Byte1]: 38

 1002 23:09:43.786823  

 1003 23:09:43.786957  Set Vref, RX VrefLevel [Byte0]: 39

 1004 23:09:43.790490                           [Byte1]: 39

 1005 23:09:43.794731  

 1006 23:09:43.794858  Set Vref, RX VrefLevel [Byte0]: 40

 1007 23:09:43.797636                           [Byte1]: 40

 1008 23:09:43.801876  

 1009 23:09:43.802003  Set Vref, RX VrefLevel [Byte0]: 41

 1010 23:09:43.805146                           [Byte1]: 41

 1011 23:09:43.809388  

 1012 23:09:43.809517  Set Vref, RX VrefLevel [Byte0]: 42

 1013 23:09:43.812617                           [Byte1]: 42

 1014 23:09:43.817167  

 1015 23:09:43.817297  Set Vref, RX VrefLevel [Byte0]: 43

 1016 23:09:43.820399                           [Byte1]: 43

 1017 23:09:43.824528  

 1018 23:09:43.824658  Set Vref, RX VrefLevel [Byte0]: 44

 1019 23:09:43.827551                           [Byte1]: 44

 1020 23:09:43.831887  

 1021 23:09:43.832014  Set Vref, RX VrefLevel [Byte0]: 45

 1022 23:09:43.835405                           [Byte1]: 45

 1023 23:09:43.839835  

 1024 23:09:43.839966  Set Vref, RX VrefLevel [Byte0]: 46

 1025 23:09:43.843129                           [Byte1]: 46

 1026 23:09:43.847217  

 1027 23:09:43.847333  Set Vref, RX VrefLevel [Byte0]: 47

 1028 23:09:43.850318                           [Byte1]: 47

 1029 23:09:43.854494  

 1030 23:09:43.854624  Set Vref, RX VrefLevel [Byte0]: 48

 1031 23:09:43.858017                           [Byte1]: 48

 1032 23:09:43.862078  

 1033 23:09:43.862253  Set Vref, RX VrefLevel [Byte0]: 49

 1034 23:09:43.865611                           [Byte1]: 49

 1035 23:09:43.870015  

 1036 23:09:43.870176  Set Vref, RX VrefLevel [Byte0]: 50

 1037 23:09:43.873036                           [Byte1]: 50

 1038 23:09:43.877486  

 1039 23:09:43.877665  Set Vref, RX VrefLevel [Byte0]: 51

 1040 23:09:43.880807                           [Byte1]: 51

 1041 23:09:43.884929  

 1042 23:09:43.885089  Set Vref, RX VrefLevel [Byte0]: 52

 1043 23:09:43.887894                           [Byte1]: 52

 1044 23:09:43.892611  

 1045 23:09:43.892783  Set Vref, RX VrefLevel [Byte0]: 53

 1046 23:09:43.895913                           [Byte1]: 53

 1047 23:09:43.899842  

 1048 23:09:43.900013  Set Vref, RX VrefLevel [Byte0]: 54

 1049 23:09:43.903511                           [Byte1]: 54

 1050 23:09:43.907281  

 1051 23:09:43.907445  Set Vref, RX VrefLevel [Byte0]: 55

 1052 23:09:43.911015                           [Byte1]: 55

 1053 23:09:43.914733  

 1054 23:09:43.914894  Set Vref, RX VrefLevel [Byte0]: 56

 1055 23:09:43.918399                           [Byte1]: 56

 1056 23:09:43.922817  

 1057 23:09:43.925845  Set Vref, RX VrefLevel [Byte0]: 57

 1058 23:09:43.925986                           [Byte1]: 57

 1059 23:09:43.929946  

 1060 23:09:43.930080  Set Vref, RX VrefLevel [Byte0]: 58

 1061 23:09:43.933631                           [Byte1]: 58

 1062 23:09:43.938088  

 1063 23:09:43.938229  Set Vref, RX VrefLevel [Byte0]: 59

 1064 23:09:43.941206                           [Byte1]: 59

 1065 23:09:43.945318  

 1066 23:09:43.945457  Set Vref, RX VrefLevel [Byte0]: 60

 1067 23:09:43.948264                           [Byte1]: 60

 1068 23:09:43.952874  

 1069 23:09:43.953011  Set Vref, RX VrefLevel [Byte0]: 61

 1070 23:09:43.956144                           [Byte1]: 61

 1071 23:09:43.960176  

 1072 23:09:43.960320  Set Vref, RX VrefLevel [Byte0]: 62

 1073 23:09:43.963378                           [Byte1]: 62

 1074 23:09:43.967815  

 1075 23:09:43.967958  Set Vref, RX VrefLevel [Byte0]: 63

 1076 23:09:43.971375                           [Byte1]: 63

 1077 23:09:43.975642  

 1078 23:09:43.975793  Set Vref, RX VrefLevel [Byte0]: 64

 1079 23:09:43.978746                           [Byte1]: 64

 1080 23:09:43.982894  

 1081 23:09:43.983035  Set Vref, RX VrefLevel [Byte0]: 65

 1082 23:09:43.986486                           [Byte1]: 65

 1083 23:09:43.990574  

 1084 23:09:43.990713  Set Vref, RX VrefLevel [Byte0]: 66

 1085 23:09:43.993879                           [Byte1]: 66

 1086 23:09:43.998337  

 1087 23:09:43.998470  Set Vref, RX VrefLevel [Byte0]: 67

 1088 23:09:44.001238                           [Byte1]: 67

 1089 23:09:44.006021  

 1090 23:09:44.006137  Set Vref, RX VrefLevel [Byte0]: 68

 1091 23:09:44.008849                           [Byte1]: 68

 1092 23:09:44.013075  

 1093 23:09:44.013258  Set Vref, RX VrefLevel [Byte0]: 69

 1094 23:09:44.016750                           [Byte1]: 69

 1095 23:09:44.020871  

 1096 23:09:44.021005  Set Vref, RX VrefLevel [Byte0]: 70

 1097 23:09:44.024357                           [Byte1]: 70

 1098 23:09:44.028691  

 1099 23:09:44.028829  Set Vref, RX VrefLevel [Byte0]: 71

 1100 23:09:44.031567                           [Byte1]: 71

 1101 23:09:44.035806  

 1102 23:09:44.035948  Set Vref, RX VrefLevel [Byte0]: 72

 1103 23:09:44.038872                           [Byte1]: 72

 1104 23:09:44.043195  

 1105 23:09:44.043333  Set Vref, RX VrefLevel [Byte0]: 73

 1106 23:09:44.046887                           [Byte1]: 73

 1107 23:09:44.051224  

 1108 23:09:44.051364  Set Vref, RX VrefLevel [Byte0]: 74

 1109 23:09:44.054310                           [Byte1]: 74

 1110 23:09:44.058703  

 1111 23:09:44.058845  Set Vref, RX VrefLevel [Byte0]: 75

 1112 23:09:44.061669                           [Byte1]: 75

 1113 23:09:44.065772  

 1114 23:09:44.065912  Set Vref, RX VrefLevel [Byte0]: 76

 1115 23:09:44.069005                           [Byte1]: 76

 1116 23:09:44.073395  

 1117 23:09:44.073591  Final RX Vref Byte 0 = 52 to rank0

 1118 23:09:44.077176  Final RX Vref Byte 1 = 57 to rank0

 1119 23:09:44.080082  Final RX Vref Byte 0 = 52 to rank1

 1120 23:09:44.083689  Final RX Vref Byte 1 = 57 to rank1==

 1121 23:09:44.087357  Dram Type= 6, Freq= 0, CH_0, rank 0

 1122 23:09:44.090450  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1123 23:09:44.093659  ==

 1124 23:09:44.093852  DQS Delay:

 1125 23:09:44.094017  DQS0 = 0, DQS1 = 0

 1126 23:09:44.096849  DQM Delay:

 1127 23:09:44.097000  DQM0 = 91, DQM1 = 85

 1128 23:09:44.100278  DQ Delay:

 1129 23:09:44.103886  DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88

 1130 23:09:44.104042  DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100

 1131 23:09:44.106948  DQ8 =72, DQ9 =76, DQ10 =88, DQ11 =76

 1132 23:09:44.110587  DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92

 1133 23:09:44.114073  

 1134 23:09:44.114218  

 1135 23:09:44.120534  [DQSOSCAuto] RK0, (LSB)MR18= 0x4b42, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps

 1136 23:09:44.123844  CH0 RK0: MR19=606, MR18=4B42

 1137 23:09:44.130405  CH0_RK0: MR19=0x606, MR18=0x4B42, DQSOSC=391, MR23=63, INC=96, DEC=64

 1138 23:09:44.130566  

 1139 23:09:44.134552  ----->DramcWriteLeveling(PI) begin...

 1140 23:09:44.134696  ==

 1141 23:09:44.137664  Dram Type= 6, Freq= 0, CH_0, rank 1

 1142 23:09:44.140488  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1143 23:09:44.140622  ==

 1144 23:09:44.143646  Write leveling (Byte 0): 35 => 35

 1145 23:09:44.147317  Write leveling (Byte 1): 29 => 29

 1146 23:09:44.150441  DramcWriteLeveling(PI) end<-----

 1147 23:09:44.150577  

 1148 23:09:44.150693  ==

 1149 23:09:44.154167  Dram Type= 6, Freq= 0, CH_0, rank 1

 1150 23:09:44.157373  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1151 23:09:44.157504  ==

 1152 23:09:44.160311  [Gating] SW mode calibration

 1153 23:09:44.167167  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1154 23:09:44.173942  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1155 23:09:44.218357   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1156 23:09:44.218779   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)

 1157 23:09:44.218914   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1158 23:09:44.219032   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1159 23:09:44.219161   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1160 23:09:44.219270   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1161 23:09:44.219402   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1162 23:09:44.219519   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1163 23:09:44.219648   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1164 23:09:44.219758   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1165 23:09:44.255227   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1166 23:09:44.255877   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1167 23:09:44.256009   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1168 23:09:44.256334   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1169 23:09:44.256460   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1170 23:09:44.256596   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1171 23:09:44.256710   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1172 23:09:44.256820   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1173 23:09:44.259684   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1174 23:09:44.263563   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1175 23:09:44.266603   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1176 23:09:44.269828   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1177 23:09:44.273516   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1178 23:09:44.276472   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1179 23:09:44.283206   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1180 23:09:44.286762   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1181 23:09:44.290049   0  9  8 | B1->B0 | 2b2b 2828 | 1 1 | (0 0) (0 0)

 1182 23:09:44.296545   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1183 23:09:44.300219   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1184 23:09:44.303346   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1185 23:09:44.310006   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1186 23:09:44.313502   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1187 23:09:44.316839   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1188 23:09:44.323059   0 10  4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)

 1189 23:09:44.326402   0 10  8 | B1->B0 | 2929 2929 | 0 1 | (0 0) (1 1)

 1190 23:09:44.329681   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1191 23:09:44.336476   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1192 23:09:44.340265   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1193 23:09:44.343466   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1194 23:09:44.347119   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1195 23:09:44.354974   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1196 23:09:44.359143   0 11  4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)

 1197 23:09:44.362310   0 11  8 | B1->B0 | 3f3f 3d3d | 0 0 | (0 0) (0 0)

 1198 23:09:44.366030   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1199 23:09:44.369113   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1200 23:09:44.373514   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1201 23:09:44.380191   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1202 23:09:44.383821   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1203 23:09:44.386813   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1204 23:09:44.393183   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1205 23:09:44.396905   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1206 23:09:44.400245   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1207 23:09:44.406526   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1208 23:09:44.410047   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1209 23:09:44.413817   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1210 23:09:44.420035   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1211 23:09:44.423667   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1212 23:09:44.426699   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1213 23:09:44.433303   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1214 23:09:44.436925   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1215 23:09:44.440302   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1216 23:09:44.446878   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1217 23:09:44.449790   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1218 23:09:44.453605   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1219 23:09:44.456951   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1220 23:09:44.463591   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1221 23:09:44.466860   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1222 23:09:44.470161   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 1223 23:09:44.473854  Total UI for P1: 0, mck2ui 16

 1224 23:09:44.477024  best dqsien dly found for B1: ( 0, 14,  8)

 1225 23:09:44.483713   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1226 23:09:44.483852  Total UI for P1: 0, mck2ui 16

 1227 23:09:44.490299  best dqsien dly found for B0: ( 0, 14, 10)

 1228 23:09:44.494009  best DQS0 dly(MCK, UI, PI) = (0, 14, 10)

 1229 23:09:44.497163  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

 1230 23:09:44.497255  

 1231 23:09:44.500304  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)

 1232 23:09:44.503976  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1233 23:09:44.507055  [Gating] SW calibration Done

 1234 23:09:44.507189  ==

 1235 23:09:44.510604  Dram Type= 6, Freq= 0, CH_0, rank 1

 1236 23:09:44.513495  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1237 23:09:44.513616  ==

 1238 23:09:44.516823  RX Vref Scan: 0

 1239 23:09:44.516921  

 1240 23:09:44.516993  RX Vref 0 -> 0, step: 1

 1241 23:09:44.517058  

 1242 23:09:44.520641  RX Delay -130 -> 252, step: 16

 1243 23:09:44.523572  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

 1244 23:09:44.530462  iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224

 1245 23:09:44.533363  iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240

 1246 23:09:44.536951  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

 1247 23:09:44.540694  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

 1248 23:09:44.543610  iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224

 1249 23:09:44.550604  iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224

 1250 23:09:44.554107  iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240

 1251 23:09:44.556934  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

 1252 23:09:44.560638  iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224

 1253 23:09:44.563644  iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224

 1254 23:09:44.570551  iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224

 1255 23:09:44.573666  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

 1256 23:09:44.576994  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

 1257 23:09:44.580563  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

 1258 23:09:44.583853  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

 1259 23:09:44.583974  ==

 1260 23:09:44.587485  Dram Type= 6, Freq= 0, CH_0, rank 1

 1261 23:09:44.593961  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1262 23:09:44.594110  ==

 1263 23:09:44.594234  DQS Delay:

 1264 23:09:44.597018  DQS0 = 0, DQS1 = 0

 1265 23:09:44.597141  DQM Delay:

 1266 23:09:44.597252  DQM0 = 89, DQM1 = 82

 1267 23:09:44.600871  DQ Delay:

 1268 23:09:44.603860  DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85

 1269 23:09:44.607554  DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101

 1270 23:09:44.610422  DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77

 1271 23:09:44.614138  DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85

 1272 23:09:44.614284  

 1273 23:09:44.614402  

 1274 23:09:44.614513  ==

 1275 23:09:44.617569  Dram Type= 6, Freq= 0, CH_0, rank 1

 1276 23:09:44.620459  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1277 23:09:44.620554  ==

 1278 23:09:44.620624  

 1279 23:09:44.620697  

 1280 23:09:44.624069  	TX Vref Scan disable

 1281 23:09:44.624204   == TX Byte 0 ==

 1282 23:09:44.630803  Update DQ  dly =586 (2 ,2, 10)  DQ  OEN =(1 ,7)

 1283 23:09:44.633890  Update DQM dly =586 (2 ,2, 10)  DQM OEN =(1 ,7)

 1284 23:09:44.634044   == TX Byte 1 ==

 1285 23:09:44.640669  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1286 23:09:44.643645  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1287 23:09:44.643796  ==

 1288 23:09:44.647391  Dram Type= 6, Freq= 0, CH_0, rank 1

 1289 23:09:44.650414  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1290 23:09:44.650561  ==

 1291 23:09:44.665393  TX Vref=22, minBit 8, minWin=27, winSum=446

 1292 23:09:44.668951  TX Vref=24, minBit 10, minWin=27, winSum=449

 1293 23:09:44.672107  TX Vref=26, minBit 1, minWin=28, winSum=454

 1294 23:09:44.675717  TX Vref=28, minBit 1, minWin=28, winSum=454

 1295 23:09:44.678543  TX Vref=30, minBit 1, minWin=28, winSum=457

 1296 23:09:44.681886  TX Vref=32, minBit 2, minWin=28, winSum=454

 1297 23:09:44.688507  [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 30

 1298 23:09:44.688620  

 1299 23:09:44.692110  Final TX Range 1 Vref 30

 1300 23:09:44.692243  

 1301 23:09:44.692353  ==

 1302 23:09:44.695460  Dram Type= 6, Freq= 0, CH_0, rank 1

 1303 23:09:44.698619  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1304 23:09:44.698750  ==

 1305 23:09:44.698869  

 1306 23:09:44.701873  

 1307 23:09:44.702001  	TX Vref Scan disable

 1308 23:09:44.705642   == TX Byte 0 ==

 1309 23:09:44.708894  Update DQ  dly =586 (2 ,2, 10)  DQ  OEN =(1 ,7)

 1310 23:09:44.715542  Update DQM dly =586 (2 ,2, 10)  DQM OEN =(1 ,7)

 1311 23:09:44.715646   == TX Byte 1 ==

 1312 23:09:44.719171  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1313 23:09:44.722034  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1314 23:09:44.725555  

 1315 23:09:44.725669  [DATLAT]

 1316 23:09:44.725739  Freq=800, CH0 RK1

 1317 23:09:44.725802  

 1318 23:09:44.728954  DATLAT Default: 0xa

 1319 23:09:44.729056  0, 0xFFFF, sum = 0

 1320 23:09:44.732109  1, 0xFFFF, sum = 0

 1321 23:09:44.732237  2, 0xFFFF, sum = 0

 1322 23:09:44.735775  3, 0xFFFF, sum = 0

 1323 23:09:44.735879  4, 0xFFFF, sum = 0

 1324 23:09:44.738780  5, 0xFFFF, sum = 0

 1325 23:09:44.738878  6, 0xFFFF, sum = 0

 1326 23:09:44.742445  7, 0xFFFF, sum = 0

 1327 23:09:44.742547  8, 0xFFFF, sum = 0

 1328 23:09:44.746101  9, 0x0, sum = 1

 1329 23:09:44.746197  10, 0x0, sum = 2

 1330 23:09:44.748954  11, 0x0, sum = 3

 1331 23:09:44.749043  12, 0x0, sum = 4

 1332 23:09:44.752555  best_step = 10

 1333 23:09:44.752671  

 1334 23:09:44.752766  ==

 1335 23:09:44.755668  Dram Type= 6, Freq= 0, CH_0, rank 1

 1336 23:09:44.758909  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1337 23:09:44.759046  ==

 1338 23:09:44.762493  RX Vref Scan: 0

 1339 23:09:44.762637  

 1340 23:09:44.762774  RX Vref 0 -> 0, step: 1

 1341 23:09:44.762890  

 1342 23:09:44.765600  RX Delay -79 -> 252, step: 8

 1343 23:09:44.772532  iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216

 1344 23:09:44.775892  iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208

 1345 23:09:44.778874  iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224

 1346 23:09:44.782651  iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216

 1347 23:09:44.786157  iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224

 1348 23:09:44.789012  iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216

 1349 23:09:44.796133  iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208

 1350 23:09:44.799318  iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216

 1351 23:09:44.802460  iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216

 1352 23:09:44.805979  iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208

 1353 23:09:44.809416  iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216

 1354 23:09:44.815938  iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216

 1355 23:09:44.819536  iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208

 1356 23:09:44.822808  iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224

 1357 23:09:44.826323  iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216

 1358 23:09:44.829292  iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224

 1359 23:09:44.833033  ==

 1360 23:09:44.833141  Dram Type= 6, Freq= 0, CH_0, rank 1

 1361 23:09:44.839274  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1362 23:09:44.839392  ==

 1363 23:09:44.839460  DQS Delay:

 1364 23:09:44.842792  DQS0 = 0, DQS1 = 0

 1365 23:09:44.842920  DQM Delay:

 1366 23:09:44.845926  DQM0 = 93, DQM1 = 83

 1367 23:09:44.846040  DQ Delay:

 1368 23:09:44.849652  DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92

 1369 23:09:44.852601  DQ4 =96, DQ5 =84, DQ6 =96, DQ7 =100

 1370 23:09:44.856146  DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76

 1371 23:09:44.859278  DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =88

 1372 23:09:44.859362  

 1373 23:09:44.859427  

 1374 23:09:44.865977  [DQSOSCAuto] RK1, (LSB)MR18= 0x4616, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps

 1375 23:09:44.869166  CH0 RK1: MR19=606, MR18=4616

 1376 23:09:44.875874  CH0_RK1: MR19=0x606, MR18=0x4616, DQSOSC=392, MR23=63, INC=96, DEC=64

 1377 23:09:44.879136  [RxdqsGatingPostProcess] freq 800

 1378 23:09:44.882835  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 1379 23:09:44.886101  Pre-setting of DQS Precalculation

 1380 23:09:44.892924  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 1381 23:09:44.893055  ==

 1382 23:09:44.895917  Dram Type= 6, Freq= 0, CH_1, rank 0

 1383 23:09:44.899511  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1384 23:09:44.899626  ==

 1385 23:09:44.906241  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1386 23:09:44.912510  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1387 23:09:44.920271  [CA 0] Center 36 (6~67) winsize 62

 1388 23:09:44.923884  [CA 1] Center 36 (6~67) winsize 62

 1389 23:09:44.927081  [CA 2] Center 34 (4~65) winsize 62

 1390 23:09:44.930586  [CA 3] Center 34 (4~65) winsize 62

 1391 23:09:44.933617  [CA 4] Center 34 (4~65) winsize 62

 1392 23:09:44.937344  [CA 5] Center 34 (4~64) winsize 61

 1393 23:09:44.937503  

 1394 23:09:44.940497  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1395 23:09:44.940647  

 1396 23:09:44.943457  [CATrainingPosCal] consider 1 rank data

 1397 23:09:44.946817  u2DelayCellTimex100 = 270/100 ps

 1398 23:09:44.950163  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1399 23:09:44.954053  CA1 delay=36 (6~67),Diff = 2 PI (14 cell)

 1400 23:09:44.957065  CA2 delay=34 (4~65),Diff = 0 PI (0 cell)

 1401 23:09:44.963644  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 1402 23:09:44.966792  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 1403 23:09:44.970354  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 1404 23:09:44.970533  

 1405 23:09:44.974143  CA PerBit enable=1, Macro0, CA PI delay=34

 1406 23:09:44.974329  

 1407 23:09:44.977155  [CBTSetCACLKResult] CA Dly = 34

 1408 23:09:44.977318  CS Dly: 6 (0~37)

 1409 23:09:44.977443  ==

 1410 23:09:44.980221  Dram Type= 6, Freq= 0, CH_1, rank 1

 1411 23:09:44.987637  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1412 23:09:44.987806  ==

 1413 23:09:44.990968  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1414 23:09:44.997048  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1415 23:09:45.006307  [CA 0] Center 36 (6~67) winsize 62

 1416 23:09:45.010288  [CA 1] Center 37 (6~68) winsize 63

 1417 23:09:45.013895  [CA 2] Center 35 (4~66) winsize 63

 1418 23:09:45.017543  [CA 3] Center 34 (4~65) winsize 62

 1419 23:09:45.021257  [CA 4] Center 35 (5~66) winsize 62

 1420 23:09:45.024421  [CA 5] Center 34 (4~65) winsize 62

 1421 23:09:45.024558  

 1422 23:09:45.028167  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1423 23:09:45.028318  

 1424 23:09:45.031784  [CATrainingPosCal] consider 2 rank data

 1425 23:09:45.035960  u2DelayCellTimex100 = 270/100 ps

 1426 23:09:45.039237  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1427 23:09:45.043333  CA1 delay=36 (6~67),Diff = 2 PI (14 cell)

 1428 23:09:45.043483  CA2 delay=34 (4~65),Diff = 0 PI (0 cell)

 1429 23:09:45.047253  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 1430 23:09:45.053892  CA4 delay=35 (5~65),Diff = 1 PI (7 cell)

 1431 23:09:45.056921  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 1432 23:09:45.057045  

 1433 23:09:45.060088  CA PerBit enable=1, Macro0, CA PI delay=34

 1434 23:09:45.060204  

 1435 23:09:45.063420  [CBTSetCACLKResult] CA Dly = 34

 1436 23:09:45.063543  CS Dly: 6 (0~38)

 1437 23:09:45.063643  

 1438 23:09:45.066789  ----->DramcWriteLeveling(PI) begin...

 1439 23:09:45.066885  ==

 1440 23:09:45.070075  Dram Type= 6, Freq= 0, CH_1, rank 0

 1441 23:09:45.077182  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1442 23:09:45.077318  ==

 1443 23:09:45.080408  Write leveling (Byte 0): 26 => 26

 1444 23:09:45.080565  Write leveling (Byte 1): 27 => 27

 1445 23:09:45.083447  DramcWriteLeveling(PI) end<-----

 1446 23:09:45.083611  

 1447 23:09:45.087120  ==

 1448 23:09:45.087271  Dram Type= 6, Freq= 0, CH_1, rank 0

 1449 23:09:45.093929  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1450 23:09:45.094114  ==

 1451 23:09:45.096892  [Gating] SW mode calibration

 1452 23:09:45.103837  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1453 23:09:45.106972  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1454 23:09:45.113740   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1455 23:09:45.117220   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)

 1456 23:09:45.120158   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1457 23:09:45.126976   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1458 23:09:45.130021   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1459 23:09:45.133733   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1460 23:09:45.140431   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1461 23:09:45.143475   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1462 23:09:45.147132   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1463 23:09:45.150545   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1464 23:09:45.156744   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1465 23:09:45.160022   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1466 23:09:45.163430   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1467 23:09:45.170379   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1468 23:09:45.173692   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1469 23:09:45.177232   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1470 23:09:45.183656   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

 1471 23:09:45.186891   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1472 23:09:45.190112   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1473 23:09:45.196845   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1474 23:09:45.200449   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1475 23:09:45.203546   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1476 23:09:45.210595   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1477 23:09:45.213763   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1478 23:09:45.216817   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1479 23:09:45.220321   0  9  4 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)

 1480 23:09:45.227352   0  9  8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)

 1481 23:09:45.230555   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1482 23:09:45.233585   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1483 23:09:45.240449   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1484 23:09:45.243969   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1485 23:09:45.247038   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1486 23:09:45.253944   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1487 23:09:45.256998   0 10  4 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (0 0)

 1488 23:09:45.260453   0 10  8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)

 1489 23:09:45.267263   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1490 23:09:45.270600   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1491 23:09:45.273880   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1492 23:09:45.280336   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1493 23:09:45.283905   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1494 23:09:45.287067   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1495 23:09:45.293913   0 11  4 | B1->B0 | 2b2b 3636 | 1 0 | (0 0) (1 1)

 1496 23:09:45.297360   0 11  8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)

 1497 23:09:45.300678   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1498 23:09:45.303984   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1499 23:09:45.310410   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1500 23:09:45.313969   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1501 23:09:45.317600   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1502 23:09:45.324094   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 1503 23:09:45.327239   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 1504 23:09:45.330792   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1505 23:09:45.337431   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1506 23:09:45.340489   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1507 23:09:45.343575   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1508 23:09:45.350364   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1509 23:09:45.354071   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1510 23:09:45.357084   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1511 23:09:45.363884   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1512 23:09:45.367537   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1513 23:09:45.370490   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1514 23:09:45.377539   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1515 23:09:45.380986   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1516 23:09:45.384301   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1517 23:09:45.390912   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1518 23:09:45.393813   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1519 23:09:45.397634   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1520 23:09:45.400583  Total UI for P1: 0, mck2ui 16

 1521 23:09:45.404106  best dqsien dly found for B0: ( 0, 14,  2)

 1522 23:09:45.407505  Total UI for P1: 0, mck2ui 16

 1523 23:09:45.410717  best dqsien dly found for B1: ( 0, 14,  2)

 1524 23:09:45.414477  best DQS0 dly(MCK, UI, PI) = (0, 14, 2)

 1525 23:09:45.417489  best DQS1 dly(MCK, UI, PI) = (0, 14, 2)

 1526 23:09:45.417620  

 1527 23:09:45.420579  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)

 1528 23:09:45.423898  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)

 1529 23:09:45.427674  [Gating] SW calibration Done

 1530 23:09:45.427822  ==

 1531 23:09:45.430735  Dram Type= 6, Freq= 0, CH_1, rank 0

 1532 23:09:45.434218  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1533 23:09:45.437233  ==

 1534 23:09:45.437363  RX Vref Scan: 0

 1535 23:09:45.437463  

 1536 23:09:45.440718  RX Vref 0 -> 0, step: 1

 1537 23:09:45.440837  

 1538 23:09:45.444404  RX Delay -130 -> 252, step: 16

 1539 23:09:45.447607  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

 1540 23:09:45.450509  iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208

 1541 23:09:45.454197  iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224

 1542 23:09:45.457307  iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224

 1543 23:09:45.464168  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

 1544 23:09:45.467471  iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224

 1545 23:09:45.471180  iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224

 1546 23:09:45.474273  iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224

 1547 23:09:45.477420  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

 1548 23:09:45.481077  iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224

 1549 23:09:45.487632  iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208

 1550 23:09:45.491021  iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208

 1551 23:09:45.494140  iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224

 1552 23:09:45.497516  iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224

 1553 23:09:45.504443  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

 1554 23:09:45.507262  iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224

 1555 23:09:45.507407  ==

 1556 23:09:45.510936  Dram Type= 6, Freq= 0, CH_1, rank 0

 1557 23:09:45.513987  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1558 23:09:45.514133  ==

 1559 23:09:45.517755  DQS Delay:

 1560 23:09:45.517850  DQS0 = 0, DQS1 = 0

 1561 23:09:45.517938  DQM Delay:

 1562 23:09:45.520722  DQM0 = 92, DQM1 = 87

 1563 23:09:45.520810  DQ Delay:

 1564 23:09:45.524134  DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93

 1565 23:09:45.527403  DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93

 1566 23:09:45.530826  DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85

 1567 23:09:45.534248  DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93

 1568 23:09:45.534336  

 1569 23:09:45.534402  

 1570 23:09:45.534464  ==

 1571 23:09:45.537702  Dram Type= 6, Freq= 0, CH_1, rank 0

 1572 23:09:45.540999  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1573 23:09:45.543946  ==

 1574 23:09:45.544063  

 1575 23:09:45.544159  

 1576 23:09:45.544251  	TX Vref Scan disable

 1577 23:09:45.547564   == TX Byte 0 ==

 1578 23:09:45.551045  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 1579 23:09:45.553992  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 1580 23:09:45.557676   == TX Byte 1 ==

 1581 23:09:45.560841  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 1582 23:09:45.564632  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 1583 23:09:45.567561  ==

 1584 23:09:45.567688  Dram Type= 6, Freq= 0, CH_1, rank 0

 1585 23:09:45.574321  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1586 23:09:45.574435  ==

 1587 23:09:45.586695  TX Vref=22, minBit 0, minWin=26, winSum=436

 1588 23:09:45.590213  TX Vref=24, minBit 1, minWin=26, winSum=438

 1589 23:09:45.594235  TX Vref=26, minBit 1, minWin=27, winSum=444

 1590 23:09:45.597118  TX Vref=28, minBit 1, minWin=27, winSum=447

 1591 23:09:45.600358  TX Vref=30, minBit 1, minWin=27, winSum=448

 1592 23:09:45.603910  TX Vref=32, minBit 2, minWin=26, winSum=446

 1593 23:09:45.610317  [TxChooseVref] Worse bit 1, Min win 27, Win sum 448, Final Vref 30

 1594 23:09:45.610464  

 1595 23:09:45.614295  Final TX Range 1 Vref 30

 1596 23:09:45.614422  

 1597 23:09:45.614539  ==

 1598 23:09:45.617455  Dram Type= 6, Freq= 0, CH_1, rank 0

 1599 23:09:45.620823  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1600 23:09:45.620912  ==

 1601 23:09:45.620987  

 1602 23:09:45.621060  

 1603 23:09:45.623799  	TX Vref Scan disable

 1604 23:09:45.627556   == TX Byte 0 ==

 1605 23:09:45.630469  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 1606 23:09:45.634033  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 1607 23:09:45.637075   == TX Byte 1 ==

 1608 23:09:45.640953  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 1609 23:09:45.644179  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 1610 23:09:45.644269  

 1611 23:09:45.644360  [DATLAT]

 1612 23:09:45.647596  Freq=800, CH1 RK0

 1613 23:09:45.647688  

 1614 23:09:45.650825  DATLAT Default: 0xa

 1615 23:09:45.650925  0, 0xFFFF, sum = 0

 1616 23:09:45.653839  1, 0xFFFF, sum = 0

 1617 23:09:45.653927  2, 0xFFFF, sum = 0

 1618 23:09:45.657640  3, 0xFFFF, sum = 0

 1619 23:09:45.657741  4, 0xFFFF, sum = 0

 1620 23:09:45.660740  5, 0xFFFF, sum = 0

 1621 23:09:45.660836  6, 0xFFFF, sum = 0

 1622 23:09:45.663838  7, 0xFFFF, sum = 0

 1623 23:09:45.663986  8, 0xFFFF, sum = 0

 1624 23:09:45.667094  9, 0x0, sum = 1

 1625 23:09:45.667233  10, 0x0, sum = 2

 1626 23:09:45.670739  11, 0x0, sum = 3

 1627 23:09:45.670884  12, 0x0, sum = 4

 1628 23:09:45.671002  best_step = 10

 1629 23:09:45.671118  

 1630 23:09:45.673915  ==

 1631 23:09:45.677569  Dram Type= 6, Freq= 0, CH_1, rank 0

 1632 23:09:45.680633  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1633 23:09:45.680765  ==

 1634 23:09:45.680898  RX Vref Scan: 1

 1635 23:09:45.681013  

 1636 23:09:45.684252  Set Vref Range= 32 -> 127

 1637 23:09:45.684400  

 1638 23:09:45.687318  RX Vref 32 -> 127, step: 1

 1639 23:09:45.687453  

 1640 23:09:45.691063  RX Delay -79 -> 252, step: 8

 1641 23:09:45.691178  

 1642 23:09:45.694109  Set Vref, RX VrefLevel [Byte0]: 32

 1643 23:09:45.697278                           [Byte1]: 32

 1644 23:09:45.697367  

 1645 23:09:45.700655  Set Vref, RX VrefLevel [Byte0]: 33

 1646 23:09:45.703924                           [Byte1]: 33

 1647 23:09:45.704035  

 1648 23:09:45.707669  Set Vref, RX VrefLevel [Byte0]: 34

 1649 23:09:45.710603                           [Byte1]: 34

 1650 23:09:45.713725  

 1651 23:09:45.713840  Set Vref, RX VrefLevel [Byte0]: 35

 1652 23:09:45.717487                           [Byte1]: 35

 1653 23:09:45.721916  

 1654 23:09:45.722008  Set Vref, RX VrefLevel [Byte0]: 36

 1655 23:09:45.724613                           [Byte1]: 36

 1656 23:09:45.729122  

 1657 23:09:45.729239  Set Vref, RX VrefLevel [Byte0]: 37

 1658 23:09:45.732224                           [Byte1]: 37

 1659 23:09:45.736882  

 1660 23:09:45.736979  Set Vref, RX VrefLevel [Byte0]: 38

 1661 23:09:45.739801                           [Byte1]: 38

 1662 23:09:45.743874  

 1663 23:09:45.744019  Set Vref, RX VrefLevel [Byte0]: 39

 1664 23:09:45.747567                           [Byte1]: 39

 1665 23:09:45.751939  

 1666 23:09:45.752058  Set Vref, RX VrefLevel [Byte0]: 40

 1667 23:09:45.755092                           [Byte1]: 40

 1668 23:09:45.759320  

 1669 23:09:45.759435  Set Vref, RX VrefLevel [Byte0]: 41

 1670 23:09:45.762850                           [Byte1]: 41

 1671 23:09:45.766698  

 1672 23:09:45.766832  Set Vref, RX VrefLevel [Byte0]: 42

 1673 23:09:45.769995                           [Byte1]: 42

 1674 23:09:45.774105  

 1675 23:09:45.774241  Set Vref, RX VrefLevel [Byte0]: 43

 1676 23:09:45.777647                           [Byte1]: 43

 1677 23:09:45.781923  

 1678 23:09:45.782057  Set Vref, RX VrefLevel [Byte0]: 44

 1679 23:09:45.785009                           [Byte1]: 44

 1680 23:09:45.789235  

 1681 23:09:45.789370  Set Vref, RX VrefLevel [Byte0]: 45

 1682 23:09:45.792989                           [Byte1]: 45

 1683 23:09:45.797326  

 1684 23:09:45.797455  Set Vref, RX VrefLevel [Byte0]: 46

 1685 23:09:45.800450                           [Byte1]: 46

 1686 23:09:45.804828  

 1687 23:09:45.804952  Set Vref, RX VrefLevel [Byte0]: 47

 1688 23:09:45.807894                           [Byte1]: 47

 1689 23:09:45.811836  

 1690 23:09:45.811948  Set Vref, RX VrefLevel [Byte0]: 48

 1691 23:09:45.815454                           [Byte1]: 48

 1692 23:09:45.819806  

 1693 23:09:45.819913  Set Vref, RX VrefLevel [Byte0]: 49

 1694 23:09:45.823301                           [Byte1]: 49

 1695 23:09:45.827465  

 1696 23:09:45.827593  Set Vref, RX VrefLevel [Byte0]: 50

 1697 23:09:45.830509                           [Byte1]: 50

 1698 23:09:45.835034  

 1699 23:09:45.835163  Set Vref, RX VrefLevel [Byte0]: 51

 1700 23:09:45.837875                           [Byte1]: 51

 1701 23:09:45.842215  

 1702 23:09:45.842350  Set Vref, RX VrefLevel [Byte0]: 52

 1703 23:09:45.845843                           [Byte1]: 52

 1704 23:09:45.849752  

 1705 23:09:45.849883  Set Vref, RX VrefLevel [Byte0]: 53

 1706 23:09:45.853539                           [Byte1]: 53

 1707 23:09:45.857138  

 1708 23:09:45.857375  Set Vref, RX VrefLevel [Byte0]: 54

 1709 23:09:45.860869                           [Byte1]: 54

 1710 23:09:45.864992  

 1711 23:09:45.865176  Set Vref, RX VrefLevel [Byte0]: 55

 1712 23:09:45.868082                           [Byte1]: 55

 1713 23:09:45.872403  

 1714 23:09:45.872574  Set Vref, RX VrefLevel [Byte0]: 56

 1715 23:09:45.875438                           [Byte1]: 56

 1716 23:09:45.880042  

 1717 23:09:45.880171  Set Vref, RX VrefLevel [Byte0]: 57

 1718 23:09:45.883330                           [Byte1]: 57

 1719 23:09:45.887494  

 1720 23:09:45.887587  Set Vref, RX VrefLevel [Byte0]: 58

 1721 23:09:45.890994                           [Byte1]: 58

 1722 23:09:45.894941  

 1723 23:09:45.895093  Set Vref, RX VrefLevel [Byte0]: 59

 1724 23:09:45.898629                           [Byte1]: 59

 1725 23:09:45.902744  

 1726 23:09:45.902871  Set Vref, RX VrefLevel [Byte0]: 60

 1727 23:09:45.905948                           [Byte1]: 60

 1728 23:09:45.910290  

 1729 23:09:45.910394  Set Vref, RX VrefLevel [Byte0]: 61

 1730 23:09:45.913820                           [Byte1]: 61

 1731 23:09:45.917604  

 1732 23:09:45.917735  Set Vref, RX VrefLevel [Byte0]: 62

 1733 23:09:45.921238                           [Byte1]: 62

 1734 23:09:45.925569  

 1735 23:09:45.925705  Set Vref, RX VrefLevel [Byte0]: 63

 1736 23:09:45.928529                           [Byte1]: 63

 1737 23:09:45.932737  

 1738 23:09:45.932872  Set Vref, RX VrefLevel [Byte0]: 64

 1739 23:09:45.936267                           [Byte1]: 64

 1740 23:09:45.940601  

 1741 23:09:45.940731  Set Vref, RX VrefLevel [Byte0]: 65

 1742 23:09:45.943474                           [Byte1]: 65

 1743 23:09:45.947824  

 1744 23:09:45.947956  Set Vref, RX VrefLevel [Byte0]: 66

 1745 23:09:45.951583                           [Byte1]: 66

 1746 23:09:45.955533  

 1747 23:09:45.955662  Set Vref, RX VrefLevel [Byte0]: 67

 1748 23:09:45.958917                           [Byte1]: 67

 1749 23:09:45.963063  

 1750 23:09:45.963174  Set Vref, RX VrefLevel [Byte0]: 68

 1751 23:09:45.966111                           [Byte1]: 68

 1752 23:09:45.970339  

 1753 23:09:45.970449  Set Vref, RX VrefLevel [Byte0]: 69

 1754 23:09:45.974077                           [Byte1]: 69

 1755 23:09:45.978496  

 1756 23:09:45.978585  Set Vref, RX VrefLevel [Byte0]: 70

 1757 23:09:45.981499                           [Byte1]: 70

 1758 23:09:45.985626  

 1759 23:09:45.985756  Set Vref, RX VrefLevel [Byte0]: 71

 1760 23:09:45.989116                           [Byte1]: 71

 1761 23:09:45.993330  

 1762 23:09:45.993494  Set Vref, RX VrefLevel [Byte0]: 72

 1763 23:09:45.996503                           [Byte1]: 72

 1764 23:09:46.000651  

 1765 23:09:46.000812  Final RX Vref Byte 0 = 57 to rank0

 1766 23:09:46.003999  Final RX Vref Byte 1 = 56 to rank0

 1767 23:09:46.007270  Final RX Vref Byte 0 = 57 to rank1

 1768 23:09:46.010570  Final RX Vref Byte 1 = 56 to rank1==

 1769 23:09:46.013784  Dram Type= 6, Freq= 0, CH_1, rank 0

 1770 23:09:46.020460  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1771 23:09:46.020626  ==

 1772 23:09:46.020774  DQS Delay:

 1773 23:09:46.020919  DQS0 = 0, DQS1 = 0

 1774 23:09:46.024141  DQM Delay:

 1775 23:09:46.024306  DQM0 = 96, DQM1 = 89

 1776 23:09:46.027086  DQ Delay:

 1777 23:09:46.031184  DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92

 1778 23:09:46.034046  DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =96

 1779 23:09:46.037558  DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84

 1780 23:09:46.040420  DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96

 1781 23:09:46.040586  

 1782 23:09:46.040735  

 1783 23:09:46.047630  [DQSOSCAuto] RK0, (LSB)MR18= 0x2c49, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps

 1784 23:09:46.050553  CH1 RK0: MR19=606, MR18=2C49

 1785 23:09:46.057364  CH1_RK0: MR19=0x606, MR18=0x2C49, DQSOSC=391, MR23=63, INC=96, DEC=64

 1786 23:09:46.057533  

 1787 23:09:46.060443  ----->DramcWriteLeveling(PI) begin...

 1788 23:09:46.060605  ==

 1789 23:09:46.063942  Dram Type= 6, Freq= 0, CH_1, rank 1

 1790 23:09:46.067353  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1791 23:09:46.067522  ==

 1792 23:09:46.070721  Write leveling (Byte 0): 27 => 27

 1793 23:09:46.074163  Write leveling (Byte 1): 28 => 28

 1794 23:09:46.077191  DramcWriteLeveling(PI) end<-----

 1795 23:09:46.077354  

 1796 23:09:46.077504  ==

 1797 23:09:46.080928  Dram Type= 6, Freq= 0, CH_1, rank 1

 1798 23:09:46.083897  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1799 23:09:46.084066  ==

 1800 23:09:46.087131  [Gating] SW mode calibration

 1801 23:09:46.093869  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1802 23:09:46.100424  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1803 23:09:46.104005   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1804 23:09:46.107635   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)

 1805 23:09:46.114252   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1806 23:09:46.117209   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1807 23:09:46.120598   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1808 23:09:46.127429   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1809 23:09:46.130804   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1810 23:09:46.134252   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1811 23:09:46.141100   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1812 23:09:46.144077   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1813 23:09:46.147561   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1814 23:09:46.154246   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1815 23:09:46.157231   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1816 23:09:46.160978   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1817 23:09:46.164071   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1818 23:09:46.170848   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)

 1819 23:09:46.173900   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1820 23:09:46.177321   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)

 1821 23:09:46.184057   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1822 23:09:46.187337   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1823 23:09:46.191026   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1824 23:09:46.197685   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1825 23:09:46.200680   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1826 23:09:46.204059   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1827 23:09:46.210713   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1828 23:09:46.214291   0  9  4 | B1->B0 | 2b2b 2323 | 1 0 | (0 0) (0 0)

 1829 23:09:46.217428   0  9  8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)

 1830 23:09:46.224261   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1831 23:09:46.227410   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1832 23:09:46.230986   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1833 23:09:46.237591   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1834 23:09:46.240859   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1835 23:09:46.243973   0 10  0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 1836 23:09:46.251127   0 10  4 | B1->B0 | 2f2f 3333 | 0 0 | (1 1) (1 0)

 1837 23:09:46.254126   0 10  8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 1838 23:09:46.257688   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1839 23:09:46.260893   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1840 23:09:46.267956   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1841 23:09:46.271075   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1842 23:09:46.274655   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1843 23:09:46.280977   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1844 23:09:46.284713   0 11  4 | B1->B0 | 3a3a 2d2d | 0 0 | (0 0) (0 0)

 1845 23:09:46.287543   0 11  8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)

 1846 23:09:46.294321   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1847 23:09:46.298171   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1848 23:09:46.301317   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1849 23:09:46.308139   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1850 23:09:46.311015   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1851 23:09:46.314375   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 1852 23:09:46.321007   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1853 23:09:46.324736   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1854 23:09:46.327864   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1855 23:09:46.334872   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1856 23:09:46.337962   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1857 23:09:46.341149   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1858 23:09:46.344109   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1859 23:09:46.351123   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1860 23:09:46.354441   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1861 23:09:46.357825   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1862 23:09:46.364519   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1863 23:09:46.367584   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1864 23:09:46.370811   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1865 23:09:46.377766   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1866 23:09:46.381006   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1867 23:09:46.384608   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1868 23:09:46.390880   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 1869 23:09:46.390967  Total UI for P1: 0, mck2ui 16

 1870 23:09:46.397930  best dqsien dly found for B1: ( 0, 14,  2)

 1871 23:09:46.401008   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1872 23:09:46.404220  Total UI for P1: 0, mck2ui 16

 1873 23:09:46.408008  best dqsien dly found for B0: ( 0, 14,  4)

 1874 23:09:46.411188  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1875 23:09:46.414431  best DQS1 dly(MCK, UI, PI) = (0, 14, 2)

 1876 23:09:46.414517  

 1877 23:09:46.418197  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1878 23:09:46.421032  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)

 1879 23:09:46.424280  [Gating] SW calibration Done

 1880 23:09:46.424375  ==

 1881 23:09:46.428079  Dram Type= 6, Freq= 0, CH_1, rank 1

 1882 23:09:46.431442  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1883 23:09:46.431531  ==

 1884 23:09:46.434675  RX Vref Scan: 0

 1885 23:09:46.434761  

 1886 23:09:46.437905  RX Vref 0 -> 0, step: 1

 1887 23:09:46.438019  

 1888 23:09:46.438115  RX Delay -130 -> 252, step: 16

 1889 23:09:46.444293  iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208

 1890 23:09:46.448126  iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208

 1891 23:09:46.451208  iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208

 1892 23:09:46.454311  iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208

 1893 23:09:46.458047  iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208

 1894 23:09:46.464120  iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224

 1895 23:09:46.467575  iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208

 1896 23:09:46.471064  iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224

 1897 23:09:46.474413  iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208

 1898 23:09:46.477880  iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208

 1899 23:09:46.484276  iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224

 1900 23:09:46.487937  iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208

 1901 23:09:46.491160  iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224

 1902 23:09:46.494609  iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208

 1903 23:09:46.497895  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

 1904 23:09:46.504257  iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208

 1905 23:09:46.504391  ==

 1906 23:09:46.507362  Dram Type= 6, Freq= 0, CH_1, rank 1

 1907 23:09:46.511161  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1908 23:09:46.511287  ==

 1909 23:09:46.511402  DQS Delay:

 1910 23:09:46.514339  DQS0 = 0, DQS1 = 0

 1911 23:09:46.514461  DQM Delay:

 1912 23:09:46.517489  DQM0 = 93, DQM1 = 92

 1913 23:09:46.517613  DQ Delay:

 1914 23:09:46.521301  DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85

 1915 23:09:46.524434  DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93

 1916 23:09:46.527483  DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85

 1917 23:09:46.531278  DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101

 1918 23:09:46.531403  

 1919 23:09:46.531514  

 1920 23:09:46.531623  ==

 1921 23:09:46.534907  Dram Type= 6, Freq= 0, CH_1, rank 1

 1922 23:09:46.537926  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1923 23:09:46.541403  ==

 1924 23:09:46.541528  

 1925 23:09:46.541641  

 1926 23:09:46.541752  	TX Vref Scan disable

 1927 23:09:46.544743   == TX Byte 0 ==

 1928 23:09:46.547925  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1929 23:09:46.551073  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1930 23:09:46.554254   == TX Byte 1 ==

 1931 23:09:46.558020  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1932 23:09:46.560987  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1933 23:09:46.561111  ==

 1934 23:09:46.564577  Dram Type= 6, Freq= 0, CH_1, rank 1

 1935 23:09:46.570929  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1936 23:09:46.571058  ==

 1937 23:09:46.582878  TX Vref=22, minBit 1, minWin=26, winSum=441

 1938 23:09:46.586352  TX Vref=24, minBit 0, minWin=27, winSum=445

 1939 23:09:46.589939  TX Vref=26, minBit 1, minWin=27, winSum=449

 1940 23:09:46.593016  TX Vref=28, minBit 1, minWin=27, winSum=451

 1941 23:09:46.596592  TX Vref=30, minBit 2, minWin=27, winSum=451

 1942 23:09:46.599489  TX Vref=32, minBit 2, minWin=27, winSum=448

 1943 23:09:46.606156  [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 28

 1944 23:09:46.606271  

 1945 23:09:46.609488  Final TX Range 1 Vref 28

 1946 23:09:46.609568  

 1947 23:09:46.609632  ==

 1948 23:09:46.613126  Dram Type= 6, Freq= 0, CH_1, rank 1

 1949 23:09:46.616917  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1950 23:09:46.617000  ==

 1951 23:09:46.617067  

 1952 23:09:46.617129  

 1953 23:09:46.619993  	TX Vref Scan disable

 1954 23:09:46.623145   == TX Byte 0 ==

 1955 23:09:46.626368  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1956 23:09:46.630227  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1957 23:09:46.633274   == TX Byte 1 ==

 1958 23:09:46.636421  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1959 23:09:46.640217  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1960 23:09:46.640304  

 1961 23:09:46.643128  [DATLAT]

 1962 23:09:46.643205  Freq=800, CH1 RK1

 1963 23:09:46.643276  

 1964 23:09:46.646630  DATLAT Default: 0xa

 1965 23:09:46.646740  0, 0xFFFF, sum = 0

 1966 23:09:46.650110  1, 0xFFFF, sum = 0

 1967 23:09:46.650240  2, 0xFFFF, sum = 0

 1968 23:09:46.653108  3, 0xFFFF, sum = 0

 1969 23:09:46.653231  4, 0xFFFF, sum = 0

 1970 23:09:46.656653  5, 0xFFFF, sum = 0

 1971 23:09:46.656780  6, 0xFFFF, sum = 0

 1972 23:09:46.659892  7, 0xFFFF, sum = 0

 1973 23:09:46.660017  8, 0xFFFF, sum = 0

 1974 23:09:46.663153  9, 0x0, sum = 1

 1975 23:09:46.663278  10, 0x0, sum = 2

 1976 23:09:46.666797  11, 0x0, sum = 3

 1977 23:09:46.666923  12, 0x0, sum = 4

 1978 23:09:46.669839  best_step = 10

 1979 23:09:46.669964  

 1980 23:09:46.670078  ==

 1981 23:09:46.673518  Dram Type= 6, Freq= 0, CH_1, rank 1

 1982 23:09:46.676575  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1983 23:09:46.676699  ==

 1984 23:09:46.679883  RX Vref Scan: 0

 1985 23:09:46.680006  

 1986 23:09:46.680117  RX Vref 0 -> 0, step: 1

 1987 23:09:46.680225  

 1988 23:09:46.683418  RX Delay -63 -> 252, step: 8

 1989 23:09:46.689720  iDelay=209, Bit 0, Center 104 (9 ~ 200) 192

 1990 23:09:46.693184  iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200

 1991 23:09:46.696640  iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200

 1992 23:09:46.699825  iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200

 1993 23:09:46.703054  iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200

 1994 23:09:46.706625  iDelay=209, Bit 5, Center 112 (17 ~ 208) 192

 1995 23:09:46.713374  iDelay=209, Bit 6, Center 108 (9 ~ 208) 200

 1996 23:09:46.716495  iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208

 1997 23:09:46.719981  iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208

 1998 23:09:46.723170  iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208

 1999 23:09:46.726490  iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208

 2000 23:09:46.730231  iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208

 2001 23:09:46.736486  iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216

 2002 23:09:46.740091  iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208

 2003 23:09:46.743293  iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208

 2004 23:09:46.746930  iDelay=209, Bit 15, Center 100 (-7 ~ 208) 216

 2005 23:09:46.747049  ==

 2006 23:09:46.749989  Dram Type= 6, Freq= 0, CH_1, rank 1

 2007 23:09:46.756415  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2008 23:09:46.756501  ==

 2009 23:09:46.756579  DQS Delay:

 2010 23:09:46.760052  DQS0 = 0, DQS1 = 0

 2011 23:09:46.760129  DQM Delay:

 2012 23:09:46.760192  DQM0 = 97, DQM1 = 92

 2013 23:09:46.763166  DQ Delay:

 2014 23:09:46.766931  DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92

 2015 23:09:46.769880  DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96

 2016 23:09:46.773309  DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88

 2017 23:09:46.776299  DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =100

 2018 23:09:46.776377  

 2019 23:09:46.776441  

 2020 23:09:46.783186  [DQSOSCAuto] RK1, (LSB)MR18= 0x4b14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps

 2021 23:09:46.786801  CH1 RK1: MR19=606, MR18=4B14

 2022 23:09:46.793608  CH1_RK1: MR19=0x606, MR18=0x4B14, DQSOSC=391, MR23=63, INC=96, DEC=64

 2023 23:09:46.796680  [RxdqsGatingPostProcess] freq 800

 2024 23:09:46.800366  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 2025 23:09:46.803384  Pre-setting of DQS Precalculation

 2026 23:09:46.810115  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 2027 23:09:46.816651  sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4

 2028 23:09:46.823328  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 2029 23:09:46.823437  

 2030 23:09:46.823532  

 2031 23:09:46.827006  [Calibration Summary] 1600 Mbps

 2032 23:09:46.827083  CH 0, Rank 0

 2033 23:09:46.830534  SW Impedance     : PASS

 2034 23:09:46.833490  DUTY Scan        : NO K

 2035 23:09:46.833597  ZQ Calibration   : PASS

 2036 23:09:46.837379  Jitter Meter     : NO K

 2037 23:09:46.840793  CBT Training     : PASS

 2038 23:09:46.840876  Write leveling   : PASS

 2039 23:09:46.843843  RX DQS gating    : PASS

 2040 23:09:46.843926  RX DQ/DQS(RDDQC) : PASS

 2041 23:09:46.846980  TX DQ/DQS        : PASS

 2042 23:09:46.850549  RX DATLAT        : PASS

 2043 23:09:46.850632  RX DQ/DQS(Engine): PASS

 2044 23:09:46.854046  TX OE            : NO K

 2045 23:09:46.854187  All Pass.

 2046 23:09:46.854310  

 2047 23:09:46.857257  CH 0, Rank 1

 2048 23:09:46.857385  SW Impedance     : PASS

 2049 23:09:46.860241  DUTY Scan        : NO K

 2050 23:09:46.863879  ZQ Calibration   : PASS

 2051 23:09:46.864002  Jitter Meter     : NO K

 2052 23:09:46.867415  CBT Training     : PASS

 2053 23:09:46.870527  Write leveling   : PASS

 2054 23:09:46.870648  RX DQS gating    : PASS

 2055 23:09:46.873670  RX DQ/DQS(RDDQC) : PASS

 2056 23:09:46.877328  TX DQ/DQS        : PASS

 2057 23:09:46.877450  RX DATLAT        : PASS

 2058 23:09:46.880693  RX DQ/DQS(Engine): PASS

 2059 23:09:46.880822  TX OE            : NO K

 2060 23:09:46.883616  All Pass.

 2061 23:09:46.883738  

 2062 23:09:46.883854  CH 1, Rank 0

 2063 23:09:46.887331  SW Impedance     : PASS

 2064 23:09:46.890529  DUTY Scan        : NO K

 2065 23:09:46.890635  ZQ Calibration   : PASS

 2066 23:09:46.893757  Jitter Meter     : NO K

 2067 23:09:46.893840  CBT Training     : PASS

 2068 23:09:46.896892  Write leveling   : PASS

 2069 23:09:46.900660  RX DQS gating    : PASS

 2070 23:09:46.900790  RX DQ/DQS(RDDQC) : PASS

 2071 23:09:46.903632  TX DQ/DQS        : PASS

 2072 23:09:46.907237  RX DATLAT        : PASS

 2073 23:09:46.907364  RX DQ/DQS(Engine): PASS

 2074 23:09:46.910235  TX OE            : NO K

 2075 23:09:46.910360  All Pass.

 2076 23:09:46.910475  

 2077 23:09:46.913966  CH 1, Rank 1

 2078 23:09:46.914085  SW Impedance     : PASS

 2079 23:09:46.917209  DUTY Scan        : NO K

 2080 23:09:46.920806  ZQ Calibration   : PASS

 2081 23:09:46.920936  Jitter Meter     : NO K

 2082 23:09:46.923733  CBT Training     : PASS

 2083 23:09:46.927250  Write leveling   : PASS

 2084 23:09:46.927376  RX DQS gating    : PASS

 2085 23:09:46.930243  RX DQ/DQS(RDDQC) : PASS

 2086 23:09:46.930341  TX DQ/DQS        : PASS

 2087 23:09:46.934009  RX DATLAT        : PASS

 2088 23:09:46.937147  RX DQ/DQS(Engine): PASS

 2089 23:09:46.937224  TX OE            : NO K

 2090 23:09:46.940842  All Pass.

 2091 23:09:46.940919  

 2092 23:09:46.940986  DramC Write-DBI off

 2093 23:09:46.943926  	PER_BANK_REFRESH: Hybrid Mode

 2094 23:09:46.947075  TX_TRACKING: ON

 2095 23:09:46.950325  [GetDramInforAfterCalByMRR] Vendor 6.

 2096 23:09:46.953676  [GetDramInforAfterCalByMRR] Revision 606.

 2097 23:09:46.957290  [GetDramInforAfterCalByMRR] Revision 2 0.

 2098 23:09:46.957365  MR0 0x3b3b

 2099 23:09:46.957427  MR8 0x5151

 2100 23:09:46.960326  RK0, DieNum 2, Density 16Gb, RKsize 32Gb.

 2101 23:09:46.963969  

 2102 23:09:46.964040  MR0 0x3b3b

 2103 23:09:46.964101  MR8 0x5151

 2104 23:09:46.967034  RK1, DieNum 2, Density 16Gb, RKsize 32Gb.

 2105 23:09:46.967104  

 2106 23:09:46.977417  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 2107 23:09:46.980593  [FAST_K] Save calibration result to emmc

 2108 23:09:46.983789  [FAST_K] Save calibration result to emmc

 2109 23:09:46.987449  dram_init: config_dvfs: 1

 2110 23:09:46.990382  dramc_set_vcore_voltage set vcore to 662500

 2111 23:09:46.994167  Read voltage for 1200, 2

 2112 23:09:46.994276  Vio18 = 0

 2113 23:09:46.994380  Vcore = 662500

 2114 23:09:46.997634  Vdram = 0

 2115 23:09:46.997753  Vddq = 0

 2116 23:09:46.997868  Vmddr = 0

 2117 23:09:47.004099  [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0

 2118 23:09:47.007169  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 2119 23:09:47.010831  MEM_TYPE=3, freq_sel=15

 2120 23:09:47.013960  sv_algorithm_assistance_LP4_1600 

 2121 23:09:47.017530  ============ PULL DRAM RESETB DOWN ============

 2122 23:09:47.020799  ========== PULL DRAM RESETB DOWN end =========

 2123 23:09:47.027624  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2124 23:09:47.030820  =================================== 

 2125 23:09:47.030950  LPDDR4 DRAM CONFIGURATION

 2126 23:09:47.034280  =================================== 

 2127 23:09:47.037249  EX_ROW_EN[0]    = 0x0

 2128 23:09:47.040795  EX_ROW_EN[1]    = 0x0

 2129 23:09:47.040924  LP4Y_EN      = 0x0

 2130 23:09:47.043955  WORK_FSP     = 0x0

 2131 23:09:47.044062  WL           = 0x4

 2132 23:09:47.047700  RL           = 0x4

 2133 23:09:47.047806  BL           = 0x2

 2134 23:09:47.050854  RPST         = 0x0

 2135 23:09:47.050954  RD_PRE       = 0x0

 2136 23:09:47.054127  WR_PRE       = 0x1

 2137 23:09:47.054214  WR_PST       = 0x0

 2138 23:09:47.057579  DBI_WR       = 0x0

 2139 23:09:47.057707  DBI_RD       = 0x0

 2140 23:09:47.061079  OTF          = 0x1

 2141 23:09:47.064440  =================================== 

 2142 23:09:47.067514  =================================== 

 2143 23:09:47.067639  ANA top config

 2144 23:09:47.071090  =================================== 

 2145 23:09:47.074400  DLL_ASYNC_EN            =  0

 2146 23:09:47.077843  ALL_SLAVE_EN            =  0

 2147 23:09:47.077970  NEW_RANK_MODE           =  1

 2148 23:09:47.080817  DLL_IDLE_MODE           =  1

 2149 23:09:47.084571  LP45_APHY_COMB_EN       =  1

 2150 23:09:47.087795  TX_ODT_DIS              =  1

 2151 23:09:47.087921  NEW_8X_MODE             =  1

 2152 23:09:47.091032  =================================== 

 2153 23:09:47.094676  =================================== 

 2154 23:09:47.097679  data_rate                  = 2400

 2155 23:09:47.101024  CKR                        = 1

 2156 23:09:47.104629  DQ_P2S_RATIO               = 8

 2157 23:09:47.107977  =================================== 

 2158 23:09:47.111210  CA_P2S_RATIO               = 8

 2159 23:09:47.114378  DQ_CA_OPEN                 = 0

 2160 23:09:47.114505  DQ_SEMI_OPEN               = 0

 2161 23:09:47.118089  CA_SEMI_OPEN               = 0

 2162 23:09:47.121065  CA_FULL_RATE               = 0

 2163 23:09:47.124766  DQ_CKDIV4_EN               = 0

 2164 23:09:47.127809  CA_CKDIV4_EN               = 0

 2165 23:09:47.131520  CA_PREDIV_EN               = 0

 2166 23:09:47.131642  PH8_DLY                    = 17

 2167 23:09:47.134512  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 2168 23:09:47.137757  DQ_AAMCK_DIV               = 4

 2169 23:09:47.141480  CA_AAMCK_DIV               = 4

 2170 23:09:47.144852  CA_ADMCK_DIV               = 4

 2171 23:09:47.144976  DQ_TRACK_CA_EN             = 0

 2172 23:09:47.147905  CA_PICK                    = 1200

 2173 23:09:47.151650  CA_MCKIO                   = 1200

 2174 23:09:47.154808  MCKIO_SEMI                 = 0

 2175 23:09:47.157866  PLL_FREQ                   = 2366

 2176 23:09:47.161094  DQ_UI_PI_RATIO             = 32

 2177 23:09:47.164893  CA_UI_PI_RATIO             = 0

 2178 23:09:47.167992  =================================== 

 2179 23:09:47.171195  =================================== 

 2180 23:09:47.171297  memory_type:LPDDR4         

 2181 23:09:47.174661  GP_NUM     : 10       

 2182 23:09:47.178087  SRAM_EN    : 1       

 2183 23:09:47.178187  MD32_EN    : 0       

 2184 23:09:47.181318  =================================== 

 2185 23:09:47.184461  [ANA_INIT] >>>>>>>>>>>>>> 

 2186 23:09:47.187936  <<<<<< [CONFIGURE PHASE]: ANA_TX

 2187 23:09:47.191519  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 2188 23:09:47.194844  =================================== 

 2189 23:09:47.198411  data_rate = 2400,PCW = 0X5b00

 2190 23:09:47.201498  =================================== 

 2191 23:09:47.204593  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 2192 23:09:47.208265  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2193 23:09:47.215049  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2194 23:09:47.218393  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 2195 23:09:47.221684  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 2196 23:09:47.225195  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 2197 23:09:47.228119  [ANA_INIT] flow start 

 2198 23:09:47.231660  [ANA_INIT] PLL >>>>>>>> 

 2199 23:09:47.231766  [ANA_INIT] PLL <<<<<<<< 

 2200 23:09:47.235311  [ANA_INIT] MIDPI >>>>>>>> 

 2201 23:09:47.238454  [ANA_INIT] MIDPI <<<<<<<< 

 2202 23:09:47.238536  [ANA_INIT] DLL >>>>>>>> 

 2203 23:09:47.241571  [ANA_INIT] DLL <<<<<<<< 

 2204 23:09:47.245414  [ANA_INIT] flow end 

 2205 23:09:47.248485  ============ LP4 DIFF to SE enter ============

 2206 23:09:47.251351  ============ LP4 DIFF to SE exit  ============

 2207 23:09:47.255104  [ANA_INIT] <<<<<<<<<<<<< 

 2208 23:09:47.258069  [Flow] Enable top DCM control >>>>> 

 2209 23:09:47.261737  [Flow] Enable top DCM control <<<<< 

 2210 23:09:47.264934  Enable DLL master slave shuffle 

 2211 23:09:47.268181  ============================================================== 

 2212 23:09:47.271926  Gating Mode config

 2213 23:09:47.278374  ============================================================== 

 2214 23:09:47.278487  Config description: 

 2215 23:09:47.288470  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 2216 23:09:47.295302  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 2217 23:09:47.298158  SELPH_MODE            0: By rank         1: By Phase 

 2218 23:09:47.305093  ============================================================== 

 2219 23:09:47.308274  GAT_TRACK_EN                 =  1

 2220 23:09:47.312074  RX_GATING_MODE               =  2

 2221 23:09:47.314813  RX_GATING_TRACK_MODE         =  2

 2222 23:09:47.318441  SELPH_MODE                   =  1

 2223 23:09:47.322051  PICG_EARLY_EN                =  1

 2224 23:09:47.322160  VALID_LAT_VALUE              =  1

 2225 23:09:47.328345  ============================================================== 

 2226 23:09:47.331616  Enter into Gating configuration >>>> 

 2227 23:09:47.335059  Exit from Gating configuration <<<< 

 2228 23:09:47.338168  Enter into  DVFS_PRE_config >>>>> 

 2229 23:09:47.348405  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 2230 23:09:47.351989  Exit from  DVFS_PRE_config <<<<< 

 2231 23:09:47.355295  Enter into PICG configuration >>>> 

 2232 23:09:47.358325  Exit from PICG configuration <<<< 

 2233 23:09:47.361815  [RX_INPUT] configuration >>>>> 

 2234 23:09:47.365291  [RX_INPUT] configuration <<<<< 

 2235 23:09:47.368527  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 2236 23:09:47.375460  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 2237 23:09:47.381770  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 2238 23:09:47.388669  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 2239 23:09:47.395093  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 2240 23:09:47.398262  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 2241 23:09:47.405054  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 2242 23:09:47.408639  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 2243 23:09:47.411673  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 2244 23:09:47.415344  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 2245 23:09:47.418323  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 2246 23:09:47.425250  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2247 23:09:47.428425  =================================== 

 2248 23:09:47.432005  LPDDR4 DRAM CONFIGURATION

 2249 23:09:47.435351  =================================== 

 2250 23:09:47.435459  EX_ROW_EN[0]    = 0x0

 2251 23:09:47.438733  EX_ROW_EN[1]    = 0x0

 2252 23:09:47.438839  LP4Y_EN      = 0x0

 2253 23:09:47.442101  WORK_FSP     = 0x0

 2254 23:09:47.442208  WL           = 0x4

 2255 23:09:47.445495  RL           = 0x4

 2256 23:09:47.445572  BL           = 0x2

 2257 23:09:47.448794  RPST         = 0x0

 2258 23:09:47.448894  RD_PRE       = 0x0

 2259 23:09:47.452087  WR_PRE       = 0x1

 2260 23:09:47.452191  WR_PST       = 0x0

 2261 23:09:47.455233  DBI_WR       = 0x0

 2262 23:09:47.455341  DBI_RD       = 0x0

 2263 23:09:47.458778  OTF          = 0x1

 2264 23:09:47.462386  =================================== 

 2265 23:09:47.465411  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 2266 23:09:47.468929  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 2267 23:09:47.475392  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2268 23:09:47.478747  =================================== 

 2269 23:09:47.478854  LPDDR4 DRAM CONFIGURATION

 2270 23:09:47.481917  =================================== 

 2271 23:09:47.485704  EX_ROW_EN[0]    = 0x10

 2272 23:09:47.488914  EX_ROW_EN[1]    = 0x0

 2273 23:09:47.488994  LP4Y_EN      = 0x0

 2274 23:09:47.492024  WORK_FSP     = 0x0

 2275 23:09:47.492099  WL           = 0x4

 2276 23:09:47.495199  RL           = 0x4

 2277 23:09:47.495270  BL           = 0x2

 2278 23:09:47.498885  RPST         = 0x0

 2279 23:09:47.498998  RD_PRE       = 0x0

 2280 23:09:47.501990  WR_PRE       = 0x1

 2281 23:09:47.502067  WR_PST       = 0x0

 2282 23:09:47.506125  DBI_WR       = 0x0

 2283 23:09:47.506252  DBI_RD       = 0x0

 2284 23:09:47.509136  OTF          = 0x1

 2285 23:09:47.512221  =================================== 

 2286 23:09:47.519020  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 2287 23:09:47.519107  ==

 2288 23:09:47.522136  Dram Type= 6, Freq= 0, CH_0, rank 0

 2289 23:09:47.525892  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2290 23:09:47.525978  ==

 2291 23:09:47.528845  [Duty_Offset_Calibration]

 2292 23:09:47.528939  	B0:2	B1:1	CA:1

 2293 23:09:47.529044  

 2294 23:09:47.532526  [DutyScan_Calibration_Flow] k_type=0

 2295 23:09:47.542064  

 2296 23:09:47.542152  ==CLK 0==

 2297 23:09:47.545265  Final CLK duty delay cell = 0

 2298 23:09:47.548745  [0] MAX Duty = 5218%(X100), DQS PI = 24

 2299 23:09:47.552006  [0] MIN Duty = 4844%(X100), DQS PI = 48

 2300 23:09:47.552084  [0] AVG Duty = 5031%(X100)

 2301 23:09:47.555461  

 2302 23:09:47.558528  CH0 CLK Duty spec in!! Max-Min= 374%

 2303 23:09:47.561932  [DutyScan_Calibration_Flow] ====Done====

 2304 23:09:47.562009  

 2305 23:09:47.565368  [DutyScan_Calibration_Flow] k_type=1

 2306 23:09:47.579646  

 2307 23:09:47.579778  ==DQS 0 ==

 2308 23:09:47.583004  Final DQS duty delay cell = -4

 2309 23:09:47.586166  [-4] MAX Duty = 5124%(X100), DQS PI = 22

 2310 23:09:47.589802  [-4] MIN Duty = 4782%(X100), DQS PI = 0

 2311 23:09:47.592958  [-4] AVG Duty = 4953%(X100)

 2312 23:09:47.593042  

 2313 23:09:47.593108  ==DQS 1 ==

 2314 23:09:47.596785  Final DQS duty delay cell = -4

 2315 23:09:47.599955  [-4] MAX Duty = 4969%(X100), DQS PI = 0

 2316 23:09:47.602974  [-4] MIN Duty = 4844%(X100), DQS PI = 32

 2317 23:09:47.606278  [-4] AVG Duty = 4906%(X100)

 2318 23:09:47.606391  

 2319 23:09:47.609490  CH0 DQS 0 Duty spec in!! Max-Min= 342%

 2320 23:09:47.609574  

 2321 23:09:47.613116  CH0 DQS 1 Duty spec in!! Max-Min= 125%

 2322 23:09:47.616235  [DutyScan_Calibration_Flow] ====Done====

 2323 23:09:47.616331  

 2324 23:09:47.619894  [DutyScan_Calibration_Flow] k_type=3

 2325 23:09:47.636652  

 2326 23:09:47.636737  ==DQM 0 ==

 2327 23:09:47.640360  Final DQM duty delay cell = 0

 2328 23:09:47.643650  [0] MAX Duty = 5187%(X100), DQS PI = 30

 2329 23:09:47.646875  [0] MIN Duty = 4906%(X100), DQS PI = 52

 2330 23:09:47.650032  [0] AVG Duty = 5046%(X100)

 2331 23:09:47.650117  

 2332 23:09:47.650182  ==DQM 1 ==

 2333 23:09:47.653512  Final DQM duty delay cell = 0

 2334 23:09:47.656628  [0] MAX Duty = 5093%(X100), DQS PI = 0

 2335 23:09:47.660156  [0] MIN Duty = 5031%(X100), DQS PI = 18

 2336 23:09:47.660240  [0] AVG Duty = 5062%(X100)

 2337 23:09:47.663308  

 2338 23:09:47.666764  CH0 DQM 0 Duty spec in!! Max-Min= 281%

 2339 23:09:47.666847  

 2340 23:09:47.670174  CH0 DQM 1 Duty spec in!! Max-Min= 62%

 2341 23:09:47.673521  [DutyScan_Calibration_Flow] ====Done====

 2342 23:09:47.673629  

 2343 23:09:47.677069  [DutyScan_Calibration_Flow] k_type=2

 2344 23:09:47.693598  

 2345 23:09:47.693733  ==DQ 0 ==

 2346 23:09:47.696878  Final DQ duty delay cell = 0

 2347 23:09:47.699713  [0] MAX Duty = 5031%(X100), DQS PI = 24

 2348 23:09:47.703180  [0] MIN Duty = 4875%(X100), DQS PI = 0

 2349 23:09:47.703291  [0] AVG Duty = 4953%(X100)

 2350 23:09:47.703386  

 2351 23:09:47.706682  ==DQ 1 ==

 2352 23:09:47.709872  Final DQ duty delay cell = 0

 2353 23:09:47.713384  [0] MAX Duty = 5093%(X100), DQS PI = 22

 2354 23:09:47.716497  [0] MIN Duty = 4938%(X100), DQS PI = 36

 2355 23:09:47.716625  [0] AVG Duty = 5015%(X100)

 2356 23:09:47.716742  

 2357 23:09:47.720196  CH0 DQ 0 Duty spec in!! Max-Min= 156%

 2358 23:09:47.720283  

 2359 23:09:47.723302  CH0 DQ 1 Duty spec in!! Max-Min= 155%

 2360 23:09:47.730238  [DutyScan_Calibration_Flow] ====Done====

 2361 23:09:47.730325  ==

 2362 23:09:47.733432  Dram Type= 6, Freq= 0, CH_1, rank 0

 2363 23:09:47.736503  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2364 23:09:47.736591  ==

 2365 23:09:47.740181  [Duty_Offset_Calibration]

 2366 23:09:47.740268  	B0:1	B1:0	CA:0

 2367 23:09:47.740366  

 2368 23:09:47.743138  [DutyScan_Calibration_Flow] k_type=0

 2369 23:09:47.752711  

 2370 23:09:47.752797  ==CLK 0==

 2371 23:09:47.755922  Final CLK duty delay cell = -4

 2372 23:09:47.758912  [-4] MAX Duty = 5031%(X100), DQS PI = 24

 2373 23:09:47.762486  [-4] MIN Duty = 4907%(X100), DQS PI = 50

 2374 23:09:47.765491  [-4] AVG Duty = 4969%(X100)

 2375 23:09:47.765599  

 2376 23:09:47.769236  CH1 CLK Duty spec in!! Max-Min= 124%

 2377 23:09:47.772247  [DutyScan_Calibration_Flow] ====Done====

 2378 23:09:47.772386  

 2379 23:09:47.775972  [DutyScan_Calibration_Flow] k_type=1

 2380 23:09:47.792479  

 2381 23:09:47.792610  ==DQS 0 ==

 2382 23:09:47.795627  Final DQS duty delay cell = 0

 2383 23:09:47.798941  [0] MAX Duty = 5094%(X100), DQS PI = 26

 2384 23:09:47.802130  [0] MIN Duty = 4875%(X100), DQS PI = 0

 2385 23:09:47.802259  [0] AVG Duty = 4984%(X100)

 2386 23:09:47.805881  

 2387 23:09:47.806005  ==DQS 1 ==

 2388 23:09:47.808762  Final DQS duty delay cell = 0

 2389 23:09:47.812172  [0] MAX Duty = 5218%(X100), DQS PI = 20

 2390 23:09:47.815912  [0] MIN Duty = 4969%(X100), DQS PI = 10

 2391 23:09:47.816040  [0] AVG Duty = 5093%(X100)

 2392 23:09:47.816153  

 2393 23:09:47.819286  CH1 DQS 0 Duty spec in!! Max-Min= 219%

 2394 23:09:47.822626  

 2395 23:09:47.825893  CH1 DQS 1 Duty spec in!! Max-Min= 249%

 2396 23:09:47.829439  [DutyScan_Calibration_Flow] ====Done====

 2397 23:09:47.829547  

 2398 23:09:47.832572  [DutyScan_Calibration_Flow] k_type=3

 2399 23:09:47.848732  

 2400 23:09:47.848821  ==DQM 0 ==

 2401 23:09:47.851982  Final DQM duty delay cell = 0

 2402 23:09:47.855754  [0] MAX Duty = 5156%(X100), DQS PI = 6

 2403 23:09:47.858991  [0] MIN Duty = 5031%(X100), DQS PI = 0

 2404 23:09:47.859076  [0] AVG Duty = 5093%(X100)

 2405 23:09:47.859142  

 2406 23:09:47.862481  ==DQM 1 ==

 2407 23:09:47.865572  Final DQM duty delay cell = 0

 2408 23:09:47.868648  [0] MAX Duty = 5031%(X100), DQS PI = 16

 2409 23:09:47.872482  [0] MIN Duty = 4907%(X100), DQS PI = 36

 2410 23:09:47.872568  [0] AVG Duty = 4969%(X100)

 2411 23:09:47.872634  

 2412 23:09:47.878781  CH1 DQM 0 Duty spec in!! Max-Min= 125%

 2413 23:09:47.878865  

 2414 23:09:47.881844  CH1 DQM 1 Duty spec in!! Max-Min= 124%

 2415 23:09:47.885613  [DutyScan_Calibration_Flow] ====Done====

 2416 23:09:47.885698  

 2417 23:09:47.888928  [DutyScan_Calibration_Flow] k_type=2

 2418 23:09:47.904856  

 2419 23:09:47.904941  ==DQ 0 ==

 2420 23:09:47.908216  Final DQ duty delay cell = -4

 2421 23:09:47.911082  [-4] MAX Duty = 5062%(X100), DQS PI = 8

 2422 23:09:47.914926  [-4] MIN Duty = 4906%(X100), DQS PI = 44

 2423 23:09:47.915033  [-4] AVG Duty = 4984%(X100)

 2424 23:09:47.917848  

 2425 23:09:47.917928  ==DQ 1 ==

 2426 23:09:47.921462  Final DQ duty delay cell = 0

 2427 23:09:47.924420  [0] MAX Duty = 5125%(X100), DQS PI = 20

 2428 23:09:47.928147  [0] MIN Duty = 4969%(X100), DQS PI = 12

 2429 23:09:47.928260  [0] AVG Duty = 5047%(X100)

 2430 23:09:47.928363  

 2431 23:09:47.931268  CH1 DQ 0 Duty spec in!! Max-Min= 156%

 2432 23:09:47.934463  

 2433 23:09:47.938192  CH1 DQ 1 Duty spec in!! Max-Min= 156%

 2434 23:09:47.941008  [DutyScan_Calibration_Flow] ====Done====

 2435 23:09:47.944503  nWR fixed to 30

 2436 23:09:47.944588  [ModeRegInit_LP4] CH0 RK0

 2437 23:09:47.947606  [ModeRegInit_LP4] CH0 RK1

 2438 23:09:47.951048  [ModeRegInit_LP4] CH1 RK0

 2439 23:09:47.954936  [ModeRegInit_LP4] CH1 RK1

 2440 23:09:47.955020  match AC timing 7

 2441 23:09:47.958090  dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1

 2442 23:09:47.964491  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 2443 23:09:47.967611  [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12

 2444 23:09:47.971392  [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25

 2445 23:09:47.977854  [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)

 2446 23:09:47.977941  ==

 2447 23:09:47.981053  Dram Type= 6, Freq= 0, CH_0, rank 0

 2448 23:09:47.984777  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2449 23:09:47.984862  ==

 2450 23:09:47.991466  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2451 23:09:47.997863  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2452 23:09:48.004746  [CA 0] Center 39 (8~70) winsize 63

 2453 23:09:48.007815  [CA 1] Center 39 (8~70) winsize 63

 2454 23:09:48.011550  [CA 2] Center 35 (5~66) winsize 62

 2455 23:09:48.014598  [CA 3] Center 34 (4~65) winsize 62

 2456 23:09:48.017917  [CA 4] Center 33 (3~64) winsize 62

 2457 23:09:48.021691  [CA 5] Center 32 (3~62) winsize 60

 2458 23:09:48.021778  

 2459 23:09:48.024670  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 2460 23:09:48.024758  

 2461 23:09:48.028182  [CATrainingPosCal] consider 1 rank data

 2462 23:09:48.031672  u2DelayCellTimex100 = 270/100 ps

 2463 23:09:48.034910  CA0 delay=39 (8~70),Diff = 7 PI (33 cell)

 2464 23:09:48.038023  CA1 delay=39 (8~70),Diff = 7 PI (33 cell)

 2465 23:09:48.045118  CA2 delay=35 (5~66),Diff = 3 PI (14 cell)

 2466 23:09:48.048170  CA3 delay=34 (4~65),Diff = 2 PI (9 cell)

 2467 23:09:48.051428  CA4 delay=33 (3~64),Diff = 1 PI (4 cell)

 2468 23:09:48.054533  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

 2469 23:09:48.054625  

 2470 23:09:48.058281  CA PerBit enable=1, Macro0, CA PI delay=32

 2471 23:09:48.058354  

 2472 23:09:48.061391  [CBTSetCACLKResult] CA Dly = 32

 2473 23:09:48.061475  CS Dly: 6 (0~37)

 2474 23:09:48.061541  ==

 2475 23:09:48.064815  Dram Type= 6, Freq= 0, CH_0, rank 1

 2476 23:09:48.071463  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2477 23:09:48.071549  ==

 2478 23:09:48.074765  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2479 23:09:48.081762  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2480 23:09:48.090362  [CA 0] Center 38 (8~69) winsize 62

 2481 23:09:48.094041  [CA 1] Center 38 (8~69) winsize 62

 2482 23:09:48.097359  [CA 2] Center 35 (4~66) winsize 63

 2483 23:09:48.100648  [CA 3] Center 34 (4~65) winsize 62

 2484 23:09:48.103714  [CA 4] Center 33 (3~64) winsize 62

 2485 23:09:48.106939  [CA 5] Center 32 (3~62) winsize 60

 2486 23:09:48.107024  

 2487 23:09:48.110574  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2488 23:09:48.110658  

 2489 23:09:48.113608  [CATrainingPosCal] consider 2 rank data

 2490 23:09:48.117564  u2DelayCellTimex100 = 270/100 ps

 2491 23:09:48.120694  CA0 delay=38 (8~69),Diff = 6 PI (28 cell)

 2492 23:09:48.123771  CA1 delay=38 (8~69),Diff = 6 PI (28 cell)

 2493 23:09:48.130292  CA2 delay=35 (5~66),Diff = 3 PI (14 cell)

 2494 23:09:48.133973  CA3 delay=34 (4~65),Diff = 2 PI (9 cell)

 2495 23:09:48.137037  CA4 delay=33 (3~64),Diff = 1 PI (4 cell)

 2496 23:09:48.140270  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

 2497 23:09:48.140403  

 2498 23:09:48.143809  CA PerBit enable=1, Macro0, CA PI delay=32

 2499 23:09:48.143940  

 2500 23:09:48.146934  [CBTSetCACLKResult] CA Dly = 32

 2501 23:09:48.147060  CS Dly: 6 (0~38)

 2502 23:09:48.147177  

 2503 23:09:48.150633  ----->DramcWriteLeveling(PI) begin...

 2504 23:09:48.153795  ==

 2505 23:09:48.153925  Dram Type= 6, Freq= 0, CH_0, rank 0

 2506 23:09:48.160679  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2507 23:09:48.160812  ==

 2508 23:09:48.163980  Write leveling (Byte 0): 33 => 33

 2509 23:09:48.167035  Write leveling (Byte 1): 28 => 28

 2510 23:09:48.170671  DramcWriteLeveling(PI) end<-----

 2511 23:09:48.170804  

 2512 23:09:48.170919  ==

 2513 23:09:48.173690  Dram Type= 6, Freq= 0, CH_0, rank 0

 2514 23:09:48.177314  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2515 23:09:48.177449  ==

 2516 23:09:48.180603  [Gating] SW mode calibration

 2517 23:09:48.187494  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2518 23:09:48.190448  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2519 23:09:48.197011   0 15  0 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)

 2520 23:09:48.200895   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2521 23:09:48.203869   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2522 23:09:48.210834   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2523 23:09:48.213753   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2524 23:09:48.217358   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2525 23:09:48.224055   0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)

 2526 23:09:48.227089   0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)

 2527 23:09:48.230698   1  0  0 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)

 2528 23:09:48.237109   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2529 23:09:48.240848   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2530 23:09:48.243751   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2531 23:09:48.250371   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2532 23:09:48.254022   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2533 23:09:48.261766   1  0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)

 2534 23:09:48.261881   1  0 28 | B1->B0 | 2929 4646 | 0 0 | (1 1) (0 0)

 2535 23:09:48.267765   1  1  0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)

 2536 23:09:48.270858   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2537 23:09:48.274000   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2538 23:09:48.280592   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2539 23:09:48.284545   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2540 23:09:48.287566   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2541 23:09:48.293993   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2542 23:09:48.297757   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2543 23:09:48.300993   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2544 23:09:48.307564   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2545 23:09:48.310678   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2546 23:09:48.314313   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2547 23:09:48.320640   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2548 23:09:48.324252   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2549 23:09:48.327599   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2550 23:09:48.334190   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2551 23:09:48.337672   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2552 23:09:48.340662   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2553 23:09:48.344487   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2554 23:09:48.350963   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2555 23:09:48.354001   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2556 23:09:48.357230   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2557 23:09:48.364428   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2558 23:09:48.367733   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 2559 23:09:48.370884   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2560 23:09:48.374332  Total UI for P1: 0, mck2ui 16

 2561 23:09:48.377569  best dqsien dly found for B0: ( 1,  3, 26)

 2562 23:09:48.384210   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2563 23:09:48.384346  Total UI for P1: 0, mck2ui 16

 2564 23:09:48.391057  best dqsien dly found for B1: ( 1,  3, 30)

 2565 23:09:48.394292  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 2566 23:09:48.397465  best DQS1 dly(MCK, UI, PI) = (1, 3, 30)

 2567 23:09:48.397552  

 2568 23:09:48.401254  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 2569 23:09:48.404497  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)

 2570 23:09:48.407727  [Gating] SW calibration Done

 2571 23:09:48.407838  ==

 2572 23:09:48.410708  Dram Type= 6, Freq= 0, CH_0, rank 0

 2573 23:09:48.414241  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2574 23:09:48.414325  ==

 2575 23:09:48.417992  RX Vref Scan: 0

 2576 23:09:48.418078  

 2577 23:09:48.418143  RX Vref 0 -> 0, step: 1

 2578 23:09:48.418204  

 2579 23:09:48.421095  RX Delay -40 -> 252, step: 8

 2580 23:09:48.424236  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 2581 23:09:48.431256  iDelay=200, Bit 1, Center 123 (48 ~ 199) 152

 2582 23:09:48.434420  iDelay=200, Bit 2, Center 119 (48 ~ 191) 144

 2583 23:09:48.437529  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 2584 23:09:48.441226  iDelay=200, Bit 4, Center 119 (48 ~ 191) 144

 2585 23:09:48.444278  iDelay=200, Bit 5, Center 115 (48 ~ 183) 136

 2586 23:09:48.451025  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 2587 23:09:48.454343  iDelay=200, Bit 7, Center 127 (56 ~ 199) 144

 2588 23:09:48.457395  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 2589 23:09:48.461144  iDelay=200, Bit 9, Center 107 (40 ~ 175) 136

 2590 23:09:48.463877  iDelay=200, Bit 10, Center 111 (48 ~ 175) 128

 2591 23:09:48.471119  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 2592 23:09:48.474269  iDelay=200, Bit 12, Center 119 (48 ~ 191) 144

 2593 23:09:48.477414  iDelay=200, Bit 13, Center 123 (56 ~ 191) 136

 2594 23:09:48.480732  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 2595 23:09:48.484636  iDelay=200, Bit 15, Center 119 (48 ~ 191) 144

 2596 23:09:48.484726  ==

 2597 23:09:48.487682  Dram Type= 6, Freq= 0, CH_0, rank 0

 2598 23:09:48.494181  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2599 23:09:48.494285  ==

 2600 23:09:48.494354  DQS Delay:

 2601 23:09:48.497849  DQS0 = 0, DQS1 = 0

 2602 23:09:48.497963  DQM Delay:

 2603 23:09:48.501155  DQM0 = 121, DQM1 = 113

 2604 23:09:48.501245  DQ Delay:

 2605 23:09:48.504765  DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119

 2606 23:09:48.507834  DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127

 2607 23:09:48.510957  DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107

 2608 23:09:48.514105  DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119

 2609 23:09:48.514213  

 2610 23:09:48.514313  

 2611 23:09:48.514413  ==

 2612 23:09:48.517821  Dram Type= 6, Freq= 0, CH_0, rank 0

 2613 23:09:48.520723  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2614 23:09:48.524508  ==

 2615 23:09:48.524629  

 2616 23:09:48.524729  

 2617 23:09:48.524824  	TX Vref Scan disable

 2618 23:09:48.527749   == TX Byte 0 ==

 2619 23:09:48.530963  Update DQ  dly =852 (3 ,2, 20)  DQ  OEN =(2 ,7)

 2620 23:09:48.534761  Update DQM dly =852 (3 ,2, 20)  DQM OEN =(2 ,7)

 2621 23:09:48.538050   == TX Byte 1 ==

 2622 23:09:48.541157  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 2623 23:09:48.544232  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 2624 23:09:48.548096  ==

 2625 23:09:48.548226  Dram Type= 6, Freq= 0, CH_0, rank 0

 2626 23:09:48.554403  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2627 23:09:48.554539  ==

 2628 23:09:48.565908  TX Vref=22, minBit 0, minWin=25, winSum=413

 2629 23:09:48.568963  TX Vref=24, minBit 1, minWin=25, winSum=418

 2630 23:09:48.572447  TX Vref=26, minBit 7, minWin=25, winSum=424

 2631 23:09:48.575898  TX Vref=28, minBit 1, minWin=26, winSum=427

 2632 23:09:48.578692  TX Vref=30, minBit 0, minWin=26, winSum=424

 2633 23:09:48.582162  TX Vref=32, minBit 0, minWin=26, winSum=425

 2634 23:09:48.588992  [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28

 2635 23:09:48.589135  

 2636 23:09:48.592118  Final TX Range 1 Vref 28

 2637 23:09:48.592236  

 2638 23:09:48.592343  ==

 2639 23:09:48.595673  Dram Type= 6, Freq= 0, CH_0, rank 0

 2640 23:09:48.598903  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2641 23:09:48.599028  ==

 2642 23:09:48.599127  

 2643 23:09:48.601943  

 2644 23:09:48.602055  	TX Vref Scan disable

 2645 23:09:48.605606   == TX Byte 0 ==

 2646 23:09:48.608922  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 2647 23:09:48.612063  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 2648 23:09:48.615664   == TX Byte 1 ==

 2649 23:09:48.618668  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 2650 23:09:48.622141  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 2651 23:09:48.622262  

 2652 23:09:48.625813  [DATLAT]

 2653 23:09:48.625928  Freq=1200, CH0 RK0

 2654 23:09:48.626025  

 2655 23:09:48.628921  DATLAT Default: 0xd

 2656 23:09:48.629033  0, 0xFFFF, sum = 0

 2657 23:09:48.632094  1, 0xFFFF, sum = 0

 2658 23:09:48.632206  2, 0xFFFF, sum = 0

 2659 23:09:48.635891  3, 0xFFFF, sum = 0

 2660 23:09:48.636006  4, 0xFFFF, sum = 0

 2661 23:09:48.639033  5, 0xFFFF, sum = 0

 2662 23:09:48.639149  6, 0xFFFF, sum = 0

 2663 23:09:48.642194  7, 0xFFFF, sum = 0

 2664 23:09:48.642308  8, 0xFFFF, sum = 0

 2665 23:09:48.645760  9, 0xFFFF, sum = 0

 2666 23:09:48.649011  10, 0xFFFF, sum = 0

 2667 23:09:48.649129  11, 0xFFFF, sum = 0

 2668 23:09:48.652219  12, 0x0, sum = 1

 2669 23:09:48.652342  13, 0x0, sum = 2

 2670 23:09:48.652441  14, 0x0, sum = 3

 2671 23:09:48.655403  15, 0x0, sum = 4

 2672 23:09:48.655512  best_step = 13

 2673 23:09:48.655607  

 2674 23:09:48.655701  ==

 2675 23:09:48.659068  Dram Type= 6, Freq= 0, CH_0, rank 0

 2676 23:09:48.665910  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2677 23:09:48.666042  ==

 2678 23:09:48.666142  RX Vref Scan: 1

 2679 23:09:48.666236  

 2680 23:09:48.668964  Set Vref Range= 32 -> 127

 2681 23:09:48.669074  

 2682 23:09:48.672791  RX Vref 32 -> 127, step: 1

 2683 23:09:48.672904  

 2684 23:09:48.675845  RX Delay -13 -> 252, step: 4

 2685 23:09:48.675956  

 2686 23:09:48.679015  Set Vref, RX VrefLevel [Byte0]: 32

 2687 23:09:48.679128                           [Byte1]: 32

 2688 23:09:48.683886  

 2689 23:09:48.684016  Set Vref, RX VrefLevel [Byte0]: 33

 2690 23:09:48.687131                           [Byte1]: 33

 2691 23:09:48.691583  

 2692 23:09:48.691699  Set Vref, RX VrefLevel [Byte0]: 34

 2693 23:09:48.694849                           [Byte1]: 34

 2694 23:09:48.699670  

 2695 23:09:48.699794  Set Vref, RX VrefLevel [Byte0]: 35

 2696 23:09:48.703005                           [Byte1]: 35

 2697 23:09:48.707285  

 2698 23:09:48.707407  Set Vref, RX VrefLevel [Byte0]: 36

 2699 23:09:48.711075                           [Byte1]: 36

 2700 23:09:48.715547  

 2701 23:09:48.715663  Set Vref, RX VrefLevel [Byte0]: 37

 2702 23:09:48.718636                           [Byte1]: 37

 2703 23:09:48.723206  

 2704 23:09:48.723325  Set Vref, RX VrefLevel [Byte0]: 38

 2705 23:09:48.726541                           [Byte1]: 38

 2706 23:09:48.730900  

 2707 23:09:48.731020  Set Vref, RX VrefLevel [Byte0]: 39

 2708 23:09:48.734204                           [Byte1]: 39

 2709 23:09:48.738971  

 2710 23:09:48.739089  Set Vref, RX VrefLevel [Byte0]: 40

 2711 23:09:48.742273                           [Byte1]: 40

 2712 23:09:48.746730  

 2713 23:09:48.746853  Set Vref, RX VrefLevel [Byte0]: 41

 2714 23:09:48.750362                           [Byte1]: 41

 2715 23:09:48.754703  

 2716 23:09:48.754824  Set Vref, RX VrefLevel [Byte0]: 42

 2717 23:09:48.757904                           [Byte1]: 42

 2718 23:09:48.762909  

 2719 23:09:48.763046  Set Vref, RX VrefLevel [Byte0]: 43

 2720 23:09:48.766004                           [Byte1]: 43

 2721 23:09:48.770356  

 2722 23:09:48.770474  Set Vref, RX VrefLevel [Byte0]: 44

 2723 23:09:48.773921                           [Byte1]: 44

 2724 23:09:48.778466  

 2725 23:09:48.778585  Set Vref, RX VrefLevel [Byte0]: 45

 2726 23:09:48.781572                           [Byte1]: 45

 2727 23:09:48.786577  

 2728 23:09:48.786704  Set Vref, RX VrefLevel [Byte0]: 46

 2729 23:09:48.789614                           [Byte1]: 46

 2730 23:09:48.794399  

 2731 23:09:48.794522  Set Vref, RX VrefLevel [Byte0]: 47

 2732 23:09:48.797495                           [Byte1]: 47

 2733 23:09:48.801998  

 2734 23:09:48.802114  Set Vref, RX VrefLevel [Byte0]: 48

 2735 23:09:48.808781                           [Byte1]: 48

 2736 23:09:48.808903  

 2737 23:09:48.812004  Set Vref, RX VrefLevel [Byte0]: 49

 2738 23:09:48.815192                           [Byte1]: 49

 2739 23:09:48.815286  

 2740 23:09:48.818845  Set Vref, RX VrefLevel [Byte0]: 50

 2741 23:09:48.822098                           [Byte1]: 50

 2742 23:09:48.826061  

 2743 23:09:48.826213  Set Vref, RX VrefLevel [Byte0]: 51

 2744 23:09:48.829064                           [Byte1]: 51

 2745 23:09:48.833772  

 2746 23:09:48.833867  Set Vref, RX VrefLevel [Byte0]: 52

 2747 23:09:48.837408                           [Byte1]: 52

 2748 23:09:48.841917  

 2749 23:09:48.842025  Set Vref, RX VrefLevel [Byte0]: 53

 2750 23:09:48.844723                           [Byte1]: 53

 2751 23:09:48.849367  

 2752 23:09:48.849461  Set Vref, RX VrefLevel [Byte0]: 54

 2753 23:09:48.852661                           [Byte1]: 54

 2754 23:09:48.857617  

 2755 23:09:48.857710  Set Vref, RX VrefLevel [Byte0]: 55

 2756 23:09:48.860590                           [Byte1]: 55

 2757 23:09:48.865330  

 2758 23:09:48.865492  Set Vref, RX VrefLevel [Byte0]: 56

 2759 23:09:48.868888                           [Byte1]: 56

 2760 23:09:48.873318  

 2761 23:09:48.873408  Set Vref, RX VrefLevel [Byte0]: 57

 2762 23:09:48.876207                           [Byte1]: 57

 2763 23:09:48.881215  

 2764 23:09:48.881357  Set Vref, RX VrefLevel [Byte0]: 58

 2765 23:09:48.884437                           [Byte1]: 58

 2766 23:09:48.888978  

 2767 23:09:48.889117  Set Vref, RX VrefLevel [Byte0]: 59

 2768 23:09:48.892127                           [Byte1]: 59

 2769 23:09:48.896931  

 2770 23:09:48.897112  Set Vref, RX VrefLevel [Byte0]: 60

 2771 23:09:48.899906                           [Byte1]: 60

 2772 23:09:48.904969  

 2773 23:09:48.905113  Set Vref, RX VrefLevel [Byte0]: 61

 2774 23:09:48.908082                           [Byte1]: 61

 2775 23:09:48.912465  

 2776 23:09:48.912657  Set Vref, RX VrefLevel [Byte0]: 62

 2777 23:09:48.916033                           [Byte1]: 62

 2778 23:09:48.920700  

 2779 23:09:48.920858  Set Vref, RX VrefLevel [Byte0]: 63

 2780 23:09:48.923606                           [Byte1]: 63

 2781 23:09:48.928405  

 2782 23:09:48.928593  Set Vref, RX VrefLevel [Byte0]: 64

 2783 23:09:48.931638                           [Byte1]: 64

 2784 23:09:48.936303  

 2785 23:09:48.936459  Set Vref, RX VrefLevel [Byte0]: 65

 2786 23:09:48.939942                           [Byte1]: 65

 2787 23:09:48.944391  

 2788 23:09:48.944489  Set Vref, RX VrefLevel [Byte0]: 66

 2789 23:09:48.947513                           [Byte1]: 66

 2790 23:09:48.951935  

 2791 23:09:48.952025  Set Vref, RX VrefLevel [Byte0]: 67

 2792 23:09:48.955081                           [Byte1]: 67

 2793 23:09:48.960006  

 2794 23:09:48.960099  Set Vref, RX VrefLevel [Byte0]: 68

 2795 23:09:48.963152                           [Byte1]: 68

 2796 23:09:48.967709  

 2797 23:09:48.967801  Set Vref, RX VrefLevel [Byte0]: 69

 2798 23:09:48.970862                           [Byte1]: 69

 2799 23:09:48.975530  

 2800 23:09:48.975675  Set Vref, RX VrefLevel [Byte0]: 70

 2801 23:09:48.979081                           [Byte1]: 70

 2802 23:09:48.983520  

 2803 23:09:48.983631  Final RX Vref Byte 0 = 61 to rank0

 2804 23:09:48.987064  Final RX Vref Byte 1 = 49 to rank0

 2805 23:09:48.990501  Final RX Vref Byte 0 = 61 to rank1

 2806 23:09:48.993795  Final RX Vref Byte 1 = 49 to rank1==

 2807 23:09:48.996900  Dram Type= 6, Freq= 0, CH_0, rank 0

 2808 23:09:49.000104  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2809 23:09:49.003727  ==

 2810 23:09:49.003870  DQS Delay:

 2811 23:09:49.003988  DQS0 = 0, DQS1 = 0

 2812 23:09:49.007523  DQM Delay:

 2813 23:09:49.007661  DQM0 = 121, DQM1 = 111

 2814 23:09:49.010614  DQ Delay:

 2815 23:09:49.013749  DQ0 =118, DQ1 =122, DQ2 =120, DQ3 =120

 2816 23:09:49.017007  DQ4 =122, DQ5 =116, DQ6 =124, DQ7 =126

 2817 23:09:49.020808  DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =106

 2818 23:09:49.023698  DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =122

 2819 23:09:49.023815  

 2820 23:09:49.023913  

 2821 23:09:49.030750  [DQSOSCAuto] RK0, (LSB)MR18= 0x1811, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 400 ps

 2822 23:09:49.033653  CH0 RK0: MR19=404, MR18=1811

 2823 23:09:49.040552  CH0_RK0: MR19=0x404, MR18=0x1811, DQSOSC=400, MR23=63, INC=40, DEC=27

 2824 23:09:49.040695  

 2825 23:09:49.043935  ----->DramcWriteLeveling(PI) begin...

 2826 23:09:49.044052  ==

 2827 23:09:49.047338  Dram Type= 6, Freq= 0, CH_0, rank 1

 2828 23:09:49.050515  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2829 23:09:49.050631  ==

 2830 23:09:49.053753  Write leveling (Byte 0): 34 => 34

 2831 23:09:49.056918  Write leveling (Byte 1): 29 => 29

 2832 23:09:49.060698  DramcWriteLeveling(PI) end<-----

 2833 23:09:49.060817  

 2834 23:09:49.060913  ==

 2835 23:09:49.063872  Dram Type= 6, Freq= 0, CH_0, rank 1

 2836 23:09:49.070223  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2837 23:09:49.070356  ==

 2838 23:09:49.070455  [Gating] SW mode calibration

 2839 23:09:49.080664  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2840 23:09:49.083704  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2841 23:09:49.087315   0 15  0 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)

 2842 23:09:49.093758   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2843 23:09:49.097088   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2844 23:09:49.100230   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2845 23:09:49.106841   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2846 23:09:49.110260   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2847 23:09:49.113760   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2848 23:09:49.120646   0 15 28 | B1->B0 | 3030 3030 | 0 1 | (0 1) (1 0)

 2849 23:09:49.123730   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2850 23:09:49.126933   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2851 23:09:49.133653   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2852 23:09:49.137413   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2853 23:09:49.140492   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2854 23:09:49.147271   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2855 23:09:49.150375   1  0 24 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)

 2856 23:09:49.154047   1  0 28 | B1->B0 | 4141 3c3c | 0 1 | (0 0) (0 0)

 2857 23:09:49.156966   1  1  0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)

 2858 23:09:49.163685   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2859 23:09:49.167605   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2860 23:09:49.170806   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2861 23:09:49.177618   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2862 23:09:49.180876   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2863 23:09:49.183890   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 2864 23:09:49.190982   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 2865 23:09:49.194114   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 2866 23:09:49.197323   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2867 23:09:49.204246   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2868 23:09:49.207353   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2869 23:09:49.210762   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2870 23:09:49.217376   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2871 23:09:49.220504   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2872 23:09:49.224092   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2873 23:09:49.230543   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2874 23:09:49.234034   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2875 23:09:49.237520   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2876 23:09:49.240656   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2877 23:09:49.247629   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2878 23:09:49.250609   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2879 23:09:49.254120   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 2880 23:09:49.261067   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 2881 23:09:49.264223   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 2882 23:09:49.267777  Total UI for P1: 0, mck2ui 16

 2883 23:09:49.270670  best dqsien dly found for B1: ( 1,  3, 26)

 2884 23:09:49.274007   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2885 23:09:49.277268  Total UI for P1: 0, mck2ui 16

 2886 23:09:49.280778  best dqsien dly found for B0: ( 1,  3, 30)

 2887 23:09:49.284554  best DQS0 dly(MCK, UI, PI) = (1, 3, 30)

 2888 23:09:49.287713  best DQS1 dly(MCK, UI, PI) = (1, 3, 26)

 2889 23:09:49.287846  

 2890 23:09:49.293891  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)

 2891 23:09:49.297396  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)

 2892 23:09:49.297516  [Gating] SW calibration Done

 2893 23:09:49.301013  ==

 2894 23:09:49.301150  Dram Type= 6, Freq= 0, CH_0, rank 1

 2895 23:09:49.307288  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2896 23:09:49.307423  ==

 2897 23:09:49.307525  RX Vref Scan: 0

 2898 23:09:49.307616  

 2899 23:09:49.310961  RX Vref 0 -> 0, step: 1

 2900 23:09:49.311079  

 2901 23:09:49.314474  RX Delay -40 -> 252, step: 8

 2902 23:09:49.317596  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 2903 23:09:49.320819  iDelay=200, Bit 1, Center 123 (56 ~ 191) 136

 2904 23:09:49.324372  iDelay=200, Bit 2, Center 123 (56 ~ 191) 136

 2905 23:09:49.331287  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 2906 23:09:49.334205  iDelay=200, Bit 4, Center 123 (56 ~ 191) 136

 2907 23:09:49.337551  iDelay=200, Bit 5, Center 115 (48 ~ 183) 136

 2908 23:09:49.340884  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 2909 23:09:49.344138  iDelay=200, Bit 7, Center 131 (64 ~ 199) 136

 2910 23:09:49.351099  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 2911 23:09:49.354495  iDelay=200, Bit 9, Center 103 (32 ~ 175) 144

 2912 23:09:49.357727  iDelay=200, Bit 10, Center 111 (48 ~ 175) 128

 2913 23:09:49.361093  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 2914 23:09:49.364543  iDelay=200, Bit 12, Center 115 (48 ~ 183) 136

 2915 23:09:49.370841  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 2916 23:09:49.374066  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 2917 23:09:49.377853  iDelay=200, Bit 15, Center 119 (56 ~ 183) 128

 2918 23:09:49.377973  ==

 2919 23:09:49.380771  Dram Type= 6, Freq= 0, CH_0, rank 1

 2920 23:09:49.384079  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2921 23:09:49.384199  ==

 2922 23:09:49.387585  DQS Delay:

 2923 23:09:49.387696  DQS0 = 0, DQS1 = 0

 2924 23:09:49.391131  DQM Delay:

 2925 23:09:49.391244  DQM0 = 122, DQM1 = 112

 2926 23:09:49.391339  DQ Delay:

 2927 23:09:49.394249  DQ0 =119, DQ1 =123, DQ2 =123, DQ3 =119

 2928 23:09:49.397309  DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =131

 2929 23:09:49.404577  DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107

 2930 23:09:49.407420  DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119

 2931 23:09:49.407541  

 2932 23:09:49.407636  

 2933 23:09:49.407726  ==

 2934 23:09:49.411144  Dram Type= 6, Freq= 0, CH_0, rank 1

 2935 23:09:49.414232  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2936 23:09:49.414347  ==

 2937 23:09:49.414442  

 2938 23:09:49.414534  

 2939 23:09:49.417857  	TX Vref Scan disable

 2940 23:09:49.417970   == TX Byte 0 ==

 2941 23:09:49.424326  Update DQ  dly =853 (3 ,2, 21)  DQ  OEN =(2 ,7)

 2942 23:09:49.427802  Update DQM dly =853 (3 ,2, 21)  DQM OEN =(2 ,7)

 2943 23:09:49.431019   == TX Byte 1 ==

 2944 23:09:49.434689  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 2945 23:09:49.437818  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 2946 23:09:49.437936  ==

 2947 23:09:49.440883  Dram Type= 6, Freq= 0, CH_0, rank 1

 2948 23:09:49.444062  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2949 23:09:49.444175  ==

 2950 23:09:49.457521  TX Vref=22, minBit 2, minWin=25, winSum=419

 2951 23:09:49.460892  TX Vref=24, minBit 1, minWin=25, winSum=421

 2952 23:09:49.464491  TX Vref=26, minBit 2, minWin=26, winSum=427

 2953 23:09:49.467490  TX Vref=28, minBit 1, minWin=26, winSum=432

 2954 23:09:49.471005  TX Vref=30, minBit 3, minWin=26, winSum=435

 2955 23:09:49.477418  TX Vref=32, minBit 0, minWin=26, winSum=427

 2956 23:09:49.480817  [TxChooseVref] Worse bit 3, Min win 26, Win sum 435, Final Vref 30

 2957 23:09:49.480942  

 2958 23:09:49.484472  Final TX Range 1 Vref 30

 2959 23:09:49.484595  

 2960 23:09:49.484690  ==

 2961 23:09:49.487459  Dram Type= 6, Freq= 0, CH_0, rank 1

 2962 23:09:49.491047  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2963 23:09:49.491185  ==

 2964 23:09:49.491274  

 2965 23:09:49.494435  

 2966 23:09:49.494569  	TX Vref Scan disable

 2967 23:09:49.497401   == TX Byte 0 ==

 2968 23:09:49.501241  Update DQ  dly =853 (3 ,2, 21)  DQ  OEN =(2 ,7)

 2969 23:09:49.504395  Update DQM dly =853 (3 ,2, 21)  DQM OEN =(2 ,7)

 2970 23:09:49.507591   == TX Byte 1 ==

 2971 23:09:49.511254  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 2972 23:09:49.514209  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 2973 23:09:49.517668  

 2974 23:09:49.517802  [DATLAT]

 2975 23:09:49.517915  Freq=1200, CH0 RK1

 2976 23:09:49.518029  

 2977 23:09:49.521199  DATLAT Default: 0xd

 2978 23:09:49.521337  0, 0xFFFF, sum = 0

 2979 23:09:49.524460  1, 0xFFFF, sum = 0

 2980 23:09:49.524591  2, 0xFFFF, sum = 0

 2981 23:09:49.527549  3, 0xFFFF, sum = 0

 2982 23:09:49.527676  4, 0xFFFF, sum = 0

 2983 23:09:49.531254  5, 0xFFFF, sum = 0

 2984 23:09:49.531386  6, 0xFFFF, sum = 0

 2985 23:09:49.534424  7, 0xFFFF, sum = 0

 2986 23:09:49.538165  8, 0xFFFF, sum = 0

 2987 23:09:49.538297  9, 0xFFFF, sum = 0

 2988 23:09:49.541163  10, 0xFFFF, sum = 0

 2989 23:09:49.541313  11, 0xFFFF, sum = 0

 2990 23:09:49.544211  12, 0x0, sum = 1

 2991 23:09:49.544344  13, 0x0, sum = 2

 2992 23:09:49.548055  14, 0x0, sum = 3

 2993 23:09:49.548186  15, 0x0, sum = 4

 2994 23:09:49.548308  best_step = 13

 2995 23:09:49.548422  

 2996 23:09:49.551085  ==

 2997 23:09:49.551210  Dram Type= 6, Freq= 0, CH_0, rank 1

 2998 23:09:49.558038  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2999 23:09:49.558185  ==

 3000 23:09:49.558300  RX Vref Scan: 0

 3001 23:09:49.558411  

 3002 23:09:49.561142  RX Vref 0 -> 0, step: 1

 3003 23:09:49.561282  

 3004 23:09:49.564447  RX Delay -13 -> 252, step: 4

 3005 23:09:49.568002  iDelay=195, Bit 0, Center 122 (55 ~ 190) 136

 3006 23:09:49.571008  iDelay=195, Bit 1, Center 122 (59 ~ 186) 128

 3007 23:09:49.577799  iDelay=195, Bit 2, Center 116 (51 ~ 182) 132

 3008 23:09:49.581464  iDelay=195, Bit 3, Center 120 (55 ~ 186) 132

 3009 23:09:49.584536  iDelay=195, Bit 4, Center 124 (59 ~ 190) 132

 3010 23:09:49.588093  iDelay=195, Bit 5, Center 116 (51 ~ 182) 132

 3011 23:09:49.591350  iDelay=195, Bit 6, Center 126 (59 ~ 194) 136

 3012 23:09:49.598319  iDelay=195, Bit 7, Center 126 (59 ~ 194) 136

 3013 23:09:49.601325  iDelay=195, Bit 8, Center 100 (35 ~ 166) 132

 3014 23:09:49.604833  iDelay=195, Bit 9, Center 98 (31 ~ 166) 136

 3015 23:09:49.607854  iDelay=195, Bit 10, Center 110 (47 ~ 174) 128

 3016 23:09:49.610974  iDelay=195, Bit 11, Center 102 (39 ~ 166) 128

 3017 23:09:49.617815  iDelay=195, Bit 12, Center 114 (51 ~ 178) 128

 3018 23:09:49.621461  iDelay=195, Bit 13, Center 116 (55 ~ 178) 124

 3019 23:09:49.624470  iDelay=195, Bit 14, Center 122 (59 ~ 186) 128

 3020 23:09:49.627769  iDelay=195, Bit 15, Center 120 (55 ~ 186) 132

 3021 23:09:49.627885  ==

 3022 23:09:49.631326  Dram Type= 6, Freq= 0, CH_0, rank 1

 3023 23:09:49.638075  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3024 23:09:49.638222  ==

 3025 23:09:49.638324  DQS Delay:

 3026 23:09:49.638417  DQS0 = 0, DQS1 = 0

 3027 23:09:49.641139  DQM Delay:

 3028 23:09:49.641248  DQM0 = 121, DQM1 = 110

 3029 23:09:49.644240  DQ Delay:

 3030 23:09:49.647960  DQ0 =122, DQ1 =122, DQ2 =116, DQ3 =120

 3031 23:09:49.651437  DQ4 =124, DQ5 =116, DQ6 =126, DQ7 =126

 3032 23:09:49.654683  DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102

 3033 23:09:49.657841  DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120

 3034 23:09:49.657963  

 3035 23:09:49.658058  

 3036 23:09:49.664872  [DQSOSCAuto] RK1, (LSB)MR18= 0x12f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps

 3037 23:09:49.668021  CH0 RK1: MR19=403, MR18=12F2

 3038 23:09:49.675010  CH0_RK1: MR19=0x403, MR18=0x12F2, DQSOSC=403, MR23=63, INC=40, DEC=26

 3039 23:09:49.678054  [RxdqsGatingPostProcess] freq 1200

 3040 23:09:49.684920  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3041 23:09:49.687934  best DQS0 dly(2T, 0.5T) = (0, 11)

 3042 23:09:49.688063  best DQS1 dly(2T, 0.5T) = (0, 11)

 3043 23:09:49.691655  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3044 23:09:49.694772  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3045 23:09:49.697877  best DQS0 dly(2T, 0.5T) = (0, 11)

 3046 23:09:49.701583  best DQS1 dly(2T, 0.5T) = (0, 11)

 3047 23:09:49.704583  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3048 23:09:49.708297  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3049 23:09:49.711239  Pre-setting of DQS Precalculation

 3050 23:09:49.718130  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3051 23:09:49.718286  ==

 3052 23:09:49.721501  Dram Type= 6, Freq= 0, CH_1, rank 0

 3053 23:09:49.724646  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3054 23:09:49.724766  ==

 3055 23:09:49.731279  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3056 23:09:49.734379  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3057 23:09:49.744076  [CA 0] Center 37 (7~68) winsize 62

 3058 23:09:49.747368  [CA 1] Center 37 (7~68) winsize 62

 3059 23:09:49.750694  [CA 2] Center 35 (5~65) winsize 61

 3060 23:09:49.754480  [CA 3] Center 34 (5~64) winsize 60

 3061 23:09:49.757535  [CA 4] Center 34 (4~64) winsize 61

 3062 23:09:49.760652  [CA 5] Center 33 (3~63) winsize 61

 3063 23:09:49.760768  

 3064 23:09:49.764532  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3065 23:09:49.764646  

 3066 23:09:49.767660  [CATrainingPosCal] consider 1 rank data

 3067 23:09:49.770746  u2DelayCellTimex100 = 270/100 ps

 3068 23:09:49.773873  CA0 delay=37 (7~68),Diff = 4 PI (19 cell)

 3069 23:09:49.777662  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3070 23:09:49.784078  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3071 23:09:49.787748  CA3 delay=34 (5~64),Diff = 1 PI (4 cell)

 3072 23:09:49.790502  CA4 delay=34 (4~64),Diff = 1 PI (4 cell)

 3073 23:09:49.793941  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 3074 23:09:49.794130  

 3075 23:09:49.797343  CA PerBit enable=1, Macro0, CA PI delay=33

 3076 23:09:49.797455  

 3077 23:09:49.800928  [CBTSetCACLKResult] CA Dly = 33

 3078 23:09:49.801048  CS Dly: 8 (0~39)

 3079 23:09:49.801143  ==

 3080 23:09:49.804177  Dram Type= 6, Freq= 0, CH_1, rank 1

 3081 23:09:49.811109  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3082 23:09:49.811249  ==

 3083 23:09:49.814219  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3084 23:09:49.820850  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3085 23:09:49.829614  [CA 0] Center 37 (7~68) winsize 62

 3086 23:09:49.833278  [CA 1] Center 38 (8~68) winsize 61

 3087 23:09:49.836514  [CA 2] Center 35 (5~65) winsize 61

 3088 23:09:49.839555  [CA 3] Center 34 (4~65) winsize 62

 3089 23:09:49.843079  [CA 4] Center 34 (4~65) winsize 62

 3090 23:09:49.846396  [CA 5] Center 34 (4~64) winsize 61

 3091 23:09:49.846513  

 3092 23:09:49.849574  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3093 23:09:49.849704  

 3094 23:09:49.853128  [CATrainingPosCal] consider 2 rank data

 3095 23:09:49.856560  u2DelayCellTimex100 = 270/100 ps

 3096 23:09:49.859711  CA0 delay=37 (7~68),Diff = 4 PI (19 cell)

 3097 23:09:49.863103  CA1 delay=38 (8~68),Diff = 5 PI (24 cell)

 3098 23:09:49.869923  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3099 23:09:49.873159  CA3 delay=34 (5~64),Diff = 1 PI (4 cell)

 3100 23:09:49.876208  CA4 delay=34 (4~64),Diff = 1 PI (4 cell)

 3101 23:09:49.880007  CA5 delay=33 (4~63),Diff = 0 PI (0 cell)

 3102 23:09:49.880129  

 3103 23:09:49.883104  CA PerBit enable=1, Macro0, CA PI delay=33

 3104 23:09:49.883214  

 3105 23:09:49.886963  [CBTSetCACLKResult] CA Dly = 33

 3106 23:09:49.887079  CS Dly: 9 (0~41)

 3107 23:09:49.887176  

 3108 23:09:49.890061  ----->DramcWriteLeveling(PI) begin...

 3109 23:09:49.890173  ==

 3110 23:09:49.893259  Dram Type= 6, Freq= 0, CH_1, rank 0

 3111 23:09:49.899941  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3112 23:09:49.900082  ==

 3113 23:09:49.903245  Write leveling (Byte 0): 26 => 26

 3114 23:09:49.906480  Write leveling (Byte 1): 27 => 27

 3115 23:09:49.906598  DramcWriteLeveling(PI) end<-----

 3116 23:09:49.906695  

 3117 23:09:49.910453  ==

 3118 23:09:49.913211  Dram Type= 6, Freq= 0, CH_1, rank 0

 3119 23:09:49.916847  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3120 23:09:49.916961  ==

 3121 23:09:49.920561  [Gating] SW mode calibration

 3122 23:09:49.926852  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3123 23:09:49.929972  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3124 23:09:49.936559   0 15  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3125 23:09:49.939872   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3126 23:09:49.943609   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3127 23:09:49.949954   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3128 23:09:49.953744   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3129 23:09:49.956877   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3130 23:09:49.963722   0 15 24 | B1->B0 | 3333 2e2e | 1 0 | (0 0) (0 0)

 3131 23:09:49.967214   0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)

 3132 23:09:49.970073   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3133 23:09:49.973639   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3134 23:09:49.980607   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3135 23:09:49.984141   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3136 23:09:49.986955   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3137 23:09:49.993750   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3138 23:09:49.997060   1  0 24 | B1->B0 | 3737 4444 | 0 0 | (0 0) (0 0)

 3139 23:09:50.000223   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3140 23:09:50.007368   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3141 23:09:50.010358   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3142 23:09:50.013761   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3143 23:09:50.020821   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3144 23:09:50.024126   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3145 23:09:50.027436   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 3146 23:09:50.033884   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3147 23:09:50.037074   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3148 23:09:50.040533   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3149 23:09:50.043709   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3150 23:09:50.050729   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3151 23:09:50.053814   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3152 23:09:50.057599   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3153 23:09:50.063861   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3154 23:09:50.067580   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3155 23:09:50.070440   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3156 23:09:50.077342   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3157 23:09:50.080877   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3158 23:09:50.084010   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3159 23:09:50.090678   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3160 23:09:50.094391   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3161 23:09:50.097457   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3162 23:09:50.104227   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3163 23:09:50.107597   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 3164 23:09:50.110909  Total UI for P1: 0, mck2ui 16

 3165 23:09:50.114405  best dqsien dly found for B0: ( 1,  3, 24)

 3166 23:09:50.117557   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3167 23:09:50.121072  Total UI for P1: 0, mck2ui 16

 3168 23:09:50.124204  best dqsien dly found for B1: ( 1,  3, 26)

 3169 23:09:50.127833  best DQS0 dly(MCK, UI, PI) = (1, 3, 24)

 3170 23:09:50.130820  best DQS1 dly(MCK, UI, PI) = (1, 3, 26)

 3171 23:09:50.130938  

 3172 23:09:50.134358  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)

 3173 23:09:50.137741  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3174 23:09:50.141127  [Gating] SW calibration Done

 3175 23:09:50.141248  ==

 3176 23:09:50.144658  Dram Type= 6, Freq= 0, CH_1, rank 0

 3177 23:09:50.150922  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3178 23:09:50.151060  ==

 3179 23:09:50.151160  RX Vref Scan: 0

 3180 23:09:50.151251  

 3181 23:09:50.154520  RX Vref 0 -> 0, step: 1

 3182 23:09:50.154630  

 3183 23:09:50.157733  RX Delay -40 -> 252, step: 8

 3184 23:09:50.160845  iDelay=200, Bit 0, Center 123 (56 ~ 191) 136

 3185 23:09:50.164678  iDelay=200, Bit 1, Center 115 (48 ~ 183) 136

 3186 23:09:50.167733  iDelay=200, Bit 2, Center 107 (40 ~ 175) 136

 3187 23:09:50.170901  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 3188 23:09:50.177718  iDelay=200, Bit 4, Center 119 (48 ~ 191) 144

 3189 23:09:50.181170  iDelay=200, Bit 5, Center 127 (56 ~ 199) 144

 3190 23:09:50.184726  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 3191 23:09:50.188119  iDelay=200, Bit 7, Center 119 (48 ~ 191) 144

 3192 23:09:50.191604  iDelay=200, Bit 8, Center 103 (40 ~ 167) 128

 3193 23:09:50.194373  iDelay=200, Bit 9, Center 107 (40 ~ 175) 136

 3194 23:09:50.201350  iDelay=200, Bit 10, Center 115 (48 ~ 183) 136

 3195 23:09:50.204626  iDelay=200, Bit 11, Center 111 (48 ~ 175) 128

 3196 23:09:50.208140  iDelay=200, Bit 12, Center 123 (56 ~ 191) 136

 3197 23:09:50.211122  iDelay=200, Bit 13, Center 127 (64 ~ 191) 128

 3198 23:09:50.218306  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 3199 23:09:50.221208  iDelay=200, Bit 15, Center 123 (56 ~ 191) 136

 3200 23:09:50.221338  ==

 3201 23:09:50.224898  Dram Type= 6, Freq= 0, CH_1, rank 0

 3202 23:09:50.228156  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3203 23:09:50.228339  ==

 3204 23:09:50.228414  DQS Delay:

 3205 23:09:50.231578  DQS0 = 0, DQS1 = 0

 3206 23:09:50.231670  DQM Delay:

 3207 23:09:50.234955  DQM0 = 119, DQM1 = 116

 3208 23:09:50.235040  DQ Delay:

 3209 23:09:50.238306  DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119

 3210 23:09:50.241377  DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119

 3211 23:09:50.244959  DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111

 3212 23:09:50.248426  DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123

 3213 23:09:50.248514  

 3214 23:09:50.251724  

 3215 23:09:50.251808  ==

 3216 23:09:50.255111  Dram Type= 6, Freq= 0, CH_1, rank 0

 3217 23:09:50.258404  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3218 23:09:50.258498  ==

 3219 23:09:50.258565  

 3220 23:09:50.258625  

 3221 23:09:50.261575  	TX Vref Scan disable

 3222 23:09:50.261659   == TX Byte 0 ==

 3223 23:09:50.265253  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3224 23:09:50.271663  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3225 23:09:50.271753   == TX Byte 1 ==

 3226 23:09:50.275001  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3227 23:09:50.281848  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3228 23:09:50.281983  ==

 3229 23:09:50.284885  Dram Type= 6, Freq= 0, CH_1, rank 0

 3230 23:09:50.287840  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3231 23:09:50.287954  ==

 3232 23:09:50.300552  TX Vref=22, minBit 1, minWin=25, winSum=412

 3233 23:09:50.303420  TX Vref=24, minBit 9, minWin=25, winSum=417

 3234 23:09:50.307035  TX Vref=26, minBit 9, minWin=25, winSum=423

 3235 23:09:50.310214  TX Vref=28, minBit 2, minWin=26, winSum=426

 3236 23:09:50.313345  TX Vref=30, minBit 2, minWin=26, winSum=429

 3237 23:09:50.316961  TX Vref=32, minBit 10, minWin=26, winSum=431

 3238 23:09:50.323420  [TxChooseVref] Worse bit 10, Min win 26, Win sum 431, Final Vref 32

 3239 23:09:50.323539  

 3240 23:09:50.326655  Final TX Range 1 Vref 32

 3241 23:09:50.326767  

 3242 23:09:50.326867  ==

 3243 23:09:50.330141  Dram Type= 6, Freq= 0, CH_1, rank 0

 3244 23:09:50.333583  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3245 23:09:50.333692  ==

 3246 23:09:50.333764  

 3247 23:09:50.336838  

 3248 23:09:50.336935  	TX Vref Scan disable

 3249 23:09:50.340089   == TX Byte 0 ==

 3250 23:09:50.343484  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3251 23:09:50.347008  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3252 23:09:50.350321   == TX Byte 1 ==

 3253 23:09:50.353388  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3254 23:09:50.356943  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3255 23:09:50.357051  

 3256 23:09:50.360393  [DATLAT]

 3257 23:09:50.360483  Freq=1200, CH1 RK0

 3258 23:09:50.360590  

 3259 23:09:50.363653  DATLAT Default: 0xd

 3260 23:09:50.363742  0, 0xFFFF, sum = 0

 3261 23:09:50.367061  1, 0xFFFF, sum = 0

 3262 23:09:50.367154  2, 0xFFFF, sum = 0

 3263 23:09:50.370133  3, 0xFFFF, sum = 0

 3264 23:09:50.370219  4, 0xFFFF, sum = 0

 3265 23:09:50.373950  5, 0xFFFF, sum = 0

 3266 23:09:50.374039  6, 0xFFFF, sum = 0

 3267 23:09:50.377209  7, 0xFFFF, sum = 0

 3268 23:09:50.377295  8, 0xFFFF, sum = 0

 3269 23:09:50.380381  9, 0xFFFF, sum = 0

 3270 23:09:50.380468  10, 0xFFFF, sum = 0

 3271 23:09:50.383561  11, 0xFFFF, sum = 0

 3272 23:09:50.383646  12, 0x0, sum = 1

 3273 23:09:50.386734  13, 0x0, sum = 2

 3274 23:09:50.386821  14, 0x0, sum = 3

 3275 23:09:50.390405  15, 0x0, sum = 4

 3276 23:09:50.390491  best_step = 13

 3277 23:09:50.390557  

 3278 23:09:50.390617  ==

 3279 23:09:50.393351  Dram Type= 6, Freq= 0, CH_1, rank 0

 3280 23:09:50.400157  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3281 23:09:50.400282  ==

 3282 23:09:50.400368  RX Vref Scan: 1

 3283 23:09:50.400432  

 3284 23:09:50.403787  Set Vref Range= 32 -> 127

 3285 23:09:50.403878  

 3286 23:09:50.406910  RX Vref 32 -> 127, step: 1

 3287 23:09:50.406998  

 3288 23:09:50.410441  RX Delay -5 -> 252, step: 4

 3289 23:09:50.410558  

 3290 23:09:50.413910  Set Vref, RX VrefLevel [Byte0]: 32

 3291 23:09:50.414001                           [Byte1]: 32

 3292 23:09:50.418344  

 3293 23:09:50.418437  Set Vref, RX VrefLevel [Byte0]: 33

 3294 23:09:50.421445                           [Byte1]: 33

 3295 23:09:50.426223  

 3296 23:09:50.426323  Set Vref, RX VrefLevel [Byte0]: 34

 3297 23:09:50.429542                           [Byte1]: 34

 3298 23:09:50.433872  

 3299 23:09:50.433973  Set Vref, RX VrefLevel [Byte0]: 35

 3300 23:09:50.437703                           [Byte1]: 35

 3301 23:09:50.442112  

 3302 23:09:50.442217  Set Vref, RX VrefLevel [Byte0]: 36

 3303 23:09:50.444864                           [Byte1]: 36

 3304 23:09:50.449529  

 3305 23:09:50.449651  Set Vref, RX VrefLevel [Byte0]: 37

 3306 23:09:50.453096                           [Byte1]: 37

 3307 23:09:50.457553  

 3308 23:09:50.457654  Set Vref, RX VrefLevel [Byte0]: 38

 3309 23:09:50.460981                           [Byte1]: 38

 3310 23:09:50.465092  

 3311 23:09:50.465191  Set Vref, RX VrefLevel [Byte0]: 39

 3312 23:09:50.468494                           [Byte1]: 39

 3313 23:09:50.473327  

 3314 23:09:50.473443  Set Vref, RX VrefLevel [Byte0]: 40

 3315 23:09:50.476482                           [Byte1]: 40

 3316 23:09:50.481036  

 3317 23:09:50.481141  Set Vref, RX VrefLevel [Byte0]: 41

 3318 23:09:50.484222                           [Byte1]: 41

 3319 23:09:50.488643  

 3320 23:09:50.488737  Set Vref, RX VrefLevel [Byte0]: 42

 3321 23:09:50.492442                           [Byte1]: 42

 3322 23:09:50.496918  

 3323 23:09:50.497014  Set Vref, RX VrefLevel [Byte0]: 43

 3324 23:09:50.499824                           [Byte1]: 43

 3325 23:09:50.504754  

 3326 23:09:50.504851  Set Vref, RX VrefLevel [Byte0]: 44

 3327 23:09:50.507838                           [Byte1]: 44

 3328 23:09:50.512676  

 3329 23:09:50.512796  Set Vref, RX VrefLevel [Byte0]: 45

 3330 23:09:50.515628                           [Byte1]: 45

 3331 23:09:50.520500  

 3332 23:09:50.520620  Set Vref, RX VrefLevel [Byte0]: 46

 3333 23:09:50.523783                           [Byte1]: 46

 3334 23:09:50.528213  

 3335 23:09:50.528337  Set Vref, RX VrefLevel [Byte0]: 47

 3336 23:09:50.531361                           [Byte1]: 47

 3337 23:09:50.535845  

 3338 23:09:50.535937  Set Vref, RX VrefLevel [Byte0]: 48

 3339 23:09:50.539489                           [Byte1]: 48

 3340 23:09:50.543834  

 3341 23:09:50.543932  Set Vref, RX VrefLevel [Byte0]: 49

 3342 23:09:50.546994                           [Byte1]: 49

 3343 23:09:50.551690  

 3344 23:09:50.551785  Set Vref, RX VrefLevel [Byte0]: 50

 3345 23:09:50.555127                           [Byte1]: 50

 3346 23:09:50.559276  

 3347 23:09:50.559386  Set Vref, RX VrefLevel [Byte0]: 51

 3348 23:09:50.562990                           [Byte1]: 51

 3349 23:09:50.567153  

 3350 23:09:50.567250  Set Vref, RX VrefLevel [Byte0]: 52

 3351 23:09:50.570709                           [Byte1]: 52

 3352 23:09:50.574995  

 3353 23:09:50.575126  Set Vref, RX VrefLevel [Byte0]: 53

 3354 23:09:50.578545                           [Byte1]: 53

 3355 23:09:50.583326  

 3356 23:09:50.583432  Set Vref, RX VrefLevel [Byte0]: 54

 3357 23:09:50.586163                           [Byte1]: 54

 3358 23:09:50.591074  

 3359 23:09:50.591182  Set Vref, RX VrefLevel [Byte0]: 55

 3360 23:09:50.594672                           [Byte1]: 55

 3361 23:09:50.599025  

 3362 23:09:50.599130  Set Vref, RX VrefLevel [Byte0]: 56

 3363 23:09:50.602176                           [Byte1]: 56

 3364 23:09:50.606918  

 3365 23:09:50.607020  Set Vref, RX VrefLevel [Byte0]: 57

 3366 23:09:50.610199                           [Byte1]: 57

 3367 23:09:50.614465  

 3368 23:09:50.614563  Set Vref, RX VrefLevel [Byte0]: 58

 3369 23:09:50.617997                           [Byte1]: 58

 3370 23:09:50.622190  

 3371 23:09:50.622316  Set Vref, RX VrefLevel [Byte0]: 59

 3372 23:09:50.625455                           [Byte1]: 59

 3373 23:09:50.629879  

 3374 23:09:50.629983  Set Vref, RX VrefLevel [Byte0]: 60

 3375 23:09:50.633616                           [Byte1]: 60

 3376 23:09:50.638203  

 3377 23:09:50.638302  Set Vref, RX VrefLevel [Byte0]: 61

 3378 23:09:50.641189                           [Byte1]: 61

 3379 23:09:50.645792  

 3380 23:09:50.645895  Set Vref, RX VrefLevel [Byte0]: 62

 3381 23:09:50.648911                           [Byte1]: 62

 3382 23:09:50.653905  

 3383 23:09:50.654005  Set Vref, RX VrefLevel [Byte0]: 63

 3384 23:09:50.656998                           [Byte1]: 63

 3385 23:09:50.661669  

 3386 23:09:50.661769  Set Vref, RX VrefLevel [Byte0]: 64

 3387 23:09:50.665163                           [Byte1]: 64

 3388 23:09:50.669376  

 3389 23:09:50.669548  Set Vref, RX VrefLevel [Byte0]: 65

 3390 23:09:50.673008                           [Byte1]: 65

 3391 23:09:50.677087  

 3392 23:09:50.677220  Set Vref, RX VrefLevel [Byte0]: 66

 3393 23:09:50.680552                           [Byte1]: 66

 3394 23:09:50.684967  

 3395 23:09:50.685066  Set Vref, RX VrefLevel [Byte0]: 67

 3396 23:09:50.688631                           [Byte1]: 67

 3397 23:09:50.692787  

 3398 23:09:50.692913  Set Vref, RX VrefLevel [Byte0]: 68

 3399 23:09:50.696314                           [Byte1]: 68

 3400 23:09:50.700772  

 3401 23:09:50.700872  Final RX Vref Byte 0 = 56 to rank0

 3402 23:09:50.704135  Final RX Vref Byte 1 = 54 to rank0

 3403 23:09:50.707244  Final RX Vref Byte 0 = 56 to rank1

 3404 23:09:50.710969  Final RX Vref Byte 1 = 54 to rank1==

 3405 23:09:50.714053  Dram Type= 6, Freq= 0, CH_1, rank 0

 3406 23:09:50.717427  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3407 23:09:50.720851  ==

 3408 23:09:50.720953  DQS Delay:

 3409 23:09:50.721024  DQS0 = 0, DQS1 = 0

 3410 23:09:50.724290  DQM Delay:

 3411 23:09:50.724431  DQM0 = 120, DQM1 = 117

 3412 23:09:50.727376  DQ Delay:

 3413 23:09:50.731117  DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118

 3414 23:09:50.734222  DQ4 =122, DQ5 =128, DQ6 =128, DQ7 =120

 3415 23:09:50.738058  DQ8 =104, DQ9 =108, DQ10 =118, DQ11 =112

 3416 23:09:50.741248  DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126

 3417 23:09:50.741358  

 3418 23:09:50.741425  

 3419 23:09:50.747885  [DQSOSCAuto] RK0, (LSB)MR18= 0xff12, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps

 3420 23:09:50.750815  CH1 RK0: MR19=304, MR18=FF12

 3421 23:09:50.757410  CH1_RK0: MR19=0x304, MR18=0xFF12, DQSOSC=403, MR23=63, INC=40, DEC=26

 3422 23:09:50.757589  

 3423 23:09:50.761134  ----->DramcWriteLeveling(PI) begin...

 3424 23:09:50.761273  ==

 3425 23:09:50.764268  Dram Type= 6, Freq= 0, CH_1, rank 1

 3426 23:09:50.767816  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3427 23:09:50.770871  ==

 3428 23:09:50.771007  Write leveling (Byte 0): 26 => 26

 3429 23:09:50.774559  Write leveling (Byte 1): 30 => 30

 3430 23:09:50.777667  DramcWriteLeveling(PI) end<-----

 3431 23:09:50.777808  

 3432 23:09:50.777925  ==

 3433 23:09:50.781243  Dram Type= 6, Freq= 0, CH_1, rank 1

 3434 23:09:50.787378  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3435 23:09:50.787601  ==

 3436 23:09:50.787723  [Gating] SW mode calibration

 3437 23:09:50.797882  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3438 23:09:50.800953  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3439 23:09:50.804503   0 15  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3440 23:09:50.811264   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3441 23:09:50.814772   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3442 23:09:50.817856   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3443 23:09:50.824682   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3444 23:09:50.828079   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3445 23:09:50.831728   0 15 24 | B1->B0 | 2e2e 3434 | 0 0 | (0 1) (0 0)

 3446 23:09:50.838401   0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)

 3447 23:09:50.841496   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3448 23:09:50.844686   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3449 23:09:50.847955   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3450 23:09:50.854865   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3451 23:09:50.857980   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3452 23:09:50.861687   1  0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)

 3453 23:09:50.868506   1  0 24 | B1->B0 | 4444 2c2c | 0 0 | (0 0) (0 0)

 3454 23:09:50.871494   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3455 23:09:50.874727   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3456 23:09:50.881374   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3457 23:09:50.884591   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3458 23:09:50.888192   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3459 23:09:50.894676   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3460 23:09:50.898027   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3461 23:09:50.901334   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3462 23:09:50.908033   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 3463 23:09:50.911801   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3464 23:09:50.914865   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3465 23:09:50.921607   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3466 23:09:50.925034   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3467 23:09:50.928241   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3468 23:09:50.931265   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3469 23:09:50.938081   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3470 23:09:50.941506   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3471 23:09:50.944832   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3472 23:09:50.951912   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3473 23:09:50.954935   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3474 23:09:50.958194   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3475 23:09:50.964520   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3476 23:09:50.968028   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 3477 23:09:50.971370   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3478 23:09:50.977758   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 3479 23:09:50.981438  Total UI for P1: 0, mck2ui 16

 3480 23:09:50.984685  best dqsien dly found for B1: ( 1,  3, 22)

 3481 23:09:50.987773   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3482 23:09:50.991298  Total UI for P1: 0, mck2ui 16

 3483 23:09:50.994483  best dqsien dly found for B0: ( 1,  3, 26)

 3484 23:09:50.998179  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 3485 23:09:51.001759  best DQS1 dly(MCK, UI, PI) = (1, 3, 22)

 3486 23:09:51.001888  

 3487 23:09:51.004512  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3488 23:09:51.007898  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)

 3489 23:09:51.011225  [Gating] SW calibration Done

 3490 23:09:51.011352  ==

 3491 23:09:51.014524  Dram Type= 6, Freq= 0, CH_1, rank 1

 3492 23:09:51.018308  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3493 23:09:51.021317  ==

 3494 23:09:51.021417  RX Vref Scan: 0

 3495 23:09:51.021485  

 3496 23:09:51.024407  RX Vref 0 -> 0, step: 1

 3497 23:09:51.024536  

 3498 23:09:51.027940  RX Delay -40 -> 252, step: 8

 3499 23:09:51.031176  iDelay=200, Bit 0, Center 123 (56 ~ 191) 136

 3500 23:09:51.034674  iDelay=200, Bit 1, Center 115 (48 ~ 183) 136

 3501 23:09:51.037568  iDelay=200, Bit 2, Center 107 (40 ~ 175) 136

 3502 23:09:51.041345  iDelay=200, Bit 3, Center 119 (56 ~ 183) 128

 3503 23:09:51.047442  iDelay=200, Bit 4, Center 115 (48 ~ 183) 136

 3504 23:09:51.050962  iDelay=200, Bit 5, Center 131 (64 ~ 199) 136

 3505 23:09:51.054481  iDelay=200, Bit 6, Center 131 (64 ~ 199) 136

 3506 23:09:51.057884  iDelay=200, Bit 7, Center 123 (56 ~ 191) 136

 3507 23:09:51.061240  iDelay=200, Bit 8, Center 107 (40 ~ 175) 136

 3508 23:09:51.067614  iDelay=200, Bit 9, Center 107 (40 ~ 175) 136

 3509 23:09:51.071364  iDelay=200, Bit 10, Center 119 (48 ~ 191) 144

 3510 23:09:51.074740  iDelay=200, Bit 11, Center 115 (48 ~ 183) 136

 3511 23:09:51.077591  iDelay=200, Bit 12, Center 127 (56 ~ 199) 144

 3512 23:09:51.081368  iDelay=200, Bit 13, Center 127 (64 ~ 191) 128

 3513 23:09:51.087677  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 3514 23:09:51.090861  iDelay=200, Bit 15, Center 123 (56 ~ 191) 136

 3515 23:09:51.090967  ==

 3516 23:09:51.094651  Dram Type= 6, Freq= 0, CH_1, rank 1

 3517 23:09:51.097649  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3518 23:09:51.097748  ==

 3519 23:09:51.101291  DQS Delay:

 3520 23:09:51.101382  DQS0 = 0, DQS1 = 0

 3521 23:09:51.101451  DQM Delay:

 3522 23:09:51.104553  DQM0 = 120, DQM1 = 118

 3523 23:09:51.104647  DQ Delay:

 3524 23:09:51.107882  DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119

 3525 23:09:51.110849  DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123

 3526 23:09:51.114743  DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115

 3527 23:09:51.120874  DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123

 3528 23:09:51.121018  

 3529 23:09:51.121122  

 3530 23:09:51.121223  ==

 3531 23:09:51.124203  Dram Type= 6, Freq= 0, CH_1, rank 1

 3532 23:09:51.127376  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3533 23:09:51.127492  ==

 3534 23:09:51.127589  

 3535 23:09:51.127679  

 3536 23:09:51.131200  	TX Vref Scan disable

 3537 23:09:51.131292   == TX Byte 0 ==

 3538 23:09:51.137827  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3539 23:09:51.141290  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3540 23:09:51.141416   == TX Byte 1 ==

 3541 23:09:51.147775  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3542 23:09:51.151491  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3543 23:09:51.151613  ==

 3544 23:09:51.154430  Dram Type= 6, Freq= 0, CH_1, rank 1

 3545 23:09:51.157562  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3546 23:09:51.157668  ==

 3547 23:09:51.170738  TX Vref=22, minBit 1, minWin=26, winSum=421

 3548 23:09:51.173511  TX Vref=24, minBit 9, minWin=25, winSum=424

 3549 23:09:51.177488  TX Vref=26, minBit 2, minWin=26, winSum=428

 3550 23:09:51.180451  TX Vref=28, minBit 9, minWin=26, winSum=434

 3551 23:09:51.183936  TX Vref=30, minBit 9, minWin=26, winSum=434

 3552 23:09:51.186850  TX Vref=32, minBit 0, minWin=27, winSum=436

 3553 23:09:51.193735  [TxChooseVref] Worse bit 0, Min win 27, Win sum 436, Final Vref 32

 3554 23:09:51.193860  

 3555 23:09:51.197303  Final TX Range 1 Vref 32

 3556 23:09:51.197441  

 3557 23:09:51.197566  ==

 3558 23:09:51.200482  Dram Type= 6, Freq= 0, CH_1, rank 1

 3559 23:09:51.203566  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3560 23:09:51.203698  ==

 3561 23:09:51.203798  

 3562 23:09:51.203889  

 3563 23:09:51.207310  	TX Vref Scan disable

 3564 23:09:51.210506   == TX Byte 0 ==

 3565 23:09:51.213882  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3566 23:09:51.217265  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3567 23:09:51.220802   == TX Byte 1 ==

 3568 23:09:51.223944  Update DQ  dly =847 (3 ,2, 15)  DQ  OEN =(2 ,7)

 3569 23:09:51.226903  Update DQM dly =847 (3 ,2, 15)  DQM OEN =(2 ,7)

 3570 23:09:51.227047  

 3571 23:09:51.230231  [DATLAT]

 3572 23:09:51.230372  Freq=1200, CH1 RK1

 3573 23:09:51.230491  

 3574 23:09:51.233550  DATLAT Default: 0xd

 3575 23:09:51.233671  0, 0xFFFF, sum = 0

 3576 23:09:51.236899  1, 0xFFFF, sum = 0

 3577 23:09:51.236997  2, 0xFFFF, sum = 0

 3578 23:09:51.240062  3, 0xFFFF, sum = 0

 3579 23:09:51.240184  4, 0xFFFF, sum = 0

 3580 23:09:51.243260  5, 0xFFFF, sum = 0

 3581 23:09:51.246910  6, 0xFFFF, sum = 0

 3582 23:09:51.247011  7, 0xFFFF, sum = 0

 3583 23:09:51.249905  8, 0xFFFF, sum = 0

 3584 23:09:51.250001  9, 0xFFFF, sum = 0

 3585 23:09:51.253305  10, 0xFFFF, sum = 0

 3586 23:09:51.253399  11, 0xFFFF, sum = 0

 3587 23:09:51.256424  12, 0x0, sum = 1

 3588 23:09:51.256529  13, 0x0, sum = 2

 3589 23:09:51.260072  14, 0x0, sum = 3

 3590 23:09:51.260195  15, 0x0, sum = 4

 3591 23:09:51.260318  best_step = 13

 3592 23:09:51.263329  

 3593 23:09:51.263448  ==

 3594 23:09:51.266885  Dram Type= 6, Freq= 0, CH_1, rank 1

 3595 23:09:51.270044  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3596 23:09:51.270144  ==

 3597 23:09:51.270235  RX Vref Scan: 0

 3598 23:09:51.270319  

 3599 23:09:51.273204  RX Vref 0 -> 0, step: 1

 3600 23:09:51.273318  

 3601 23:09:51.276810  RX Delay -5 -> 252, step: 4

 3602 23:09:51.279762  iDelay=195, Bit 0, Center 122 (59 ~ 186) 128

 3603 23:09:51.286616  iDelay=195, Bit 1, Center 116 (55 ~ 178) 124

 3604 23:09:51.289608  iDelay=195, Bit 2, Center 112 (51 ~ 174) 124

 3605 23:09:51.293180  iDelay=195, Bit 3, Center 116 (59 ~ 174) 116

 3606 23:09:51.296203  iDelay=195, Bit 4, Center 116 (55 ~ 178) 124

 3607 23:09:51.300023  iDelay=195, Bit 5, Center 130 (67 ~ 194) 128

 3608 23:09:51.306377  iDelay=195, Bit 6, Center 130 (67 ~ 194) 128

 3609 23:09:51.309581  iDelay=195, Bit 7, Center 120 (59 ~ 182) 124

 3610 23:09:51.313350  iDelay=195, Bit 8, Center 106 (47 ~ 166) 120

 3611 23:09:51.316499  iDelay=195, Bit 9, Center 108 (47 ~ 170) 124

 3612 23:09:51.319529  iDelay=195, Bit 10, Center 118 (55 ~ 182) 128

 3613 23:09:51.326068  iDelay=195, Bit 11, Center 112 (51 ~ 174) 124

 3614 23:09:51.329925  iDelay=195, Bit 12, Center 126 (63 ~ 190) 128

 3615 23:09:51.333396  iDelay=195, Bit 13, Center 124 (67 ~ 182) 116

 3616 23:09:51.336237  iDelay=195, Bit 14, Center 124 (67 ~ 182) 116

 3617 23:09:51.339371  iDelay=195, Bit 15, Center 128 (67 ~ 190) 124

 3618 23:09:51.343028  ==

 3619 23:09:51.346117  Dram Type= 6, Freq= 0, CH_1, rank 1

 3620 23:09:51.349405  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3621 23:09:51.349519  ==

 3622 23:09:51.349592  DQS Delay:

 3623 23:09:51.352597  DQS0 = 0, DQS1 = 0

 3624 23:09:51.352737  DQM Delay:

 3625 23:09:51.355858  DQM0 = 120, DQM1 = 118

 3626 23:09:51.355989  DQ Delay:

 3627 23:09:51.359890  DQ0 =122, DQ1 =116, DQ2 =112, DQ3 =116

 3628 23:09:51.363018  DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120

 3629 23:09:51.366387  DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112

 3630 23:09:51.369610  DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128

 3631 23:09:51.369717  

 3632 23:09:51.369805  

 3633 23:09:51.379879  [DQSOSCAuto] RK1, (LSB)MR18= 0x10ed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps

 3634 23:09:51.383046  CH1 RK1: MR19=403, MR18=10ED

 3635 23:09:51.386316  CH1_RK1: MR19=0x403, MR18=0x10ED, DQSOSC=403, MR23=63, INC=40, DEC=26

 3636 23:09:51.389705  [RxdqsGatingPostProcess] freq 1200

 3637 23:09:51.396147  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3638 23:09:51.399545  best DQS0 dly(2T, 0.5T) = (0, 11)

 3639 23:09:51.402989  best DQS1 dly(2T, 0.5T) = (0, 11)

 3640 23:09:51.406103  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3641 23:09:51.409502  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3642 23:09:51.412787  best DQS0 dly(2T, 0.5T) = (0, 11)

 3643 23:09:51.416004  best DQS1 dly(2T, 0.5T) = (0, 11)

 3644 23:09:51.419281  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3645 23:09:51.422504  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3646 23:09:51.425674  Pre-setting of DQS Precalculation

 3647 23:09:51.428940  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3648 23:09:51.435870  sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2

 3649 23:09:51.442520  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 3650 23:09:51.442671  

 3651 23:09:51.442770  

 3652 23:09:51.445755  [Calibration Summary] 2400 Mbps

 3653 23:09:51.449108  CH 0, Rank 0

 3654 23:09:51.449262  SW Impedance     : PASS

 3655 23:09:51.452361  DUTY Scan        : NO K

 3656 23:09:51.455550  ZQ Calibration   : PASS

 3657 23:09:51.455665  Jitter Meter     : NO K

 3658 23:09:51.458837  CBT Training     : PASS

 3659 23:09:51.462604  Write leveling   : PASS

 3660 23:09:51.462704  RX DQS gating    : PASS

 3661 23:09:51.465907  RX DQ/DQS(RDDQC) : PASS

 3662 23:09:51.469061  TX DQ/DQS        : PASS

 3663 23:09:51.469194  RX DATLAT        : PASS

 3664 23:09:51.472071  RX DQ/DQS(Engine): PASS

 3665 23:09:51.472186  TX OE            : NO K

 3666 23:09:51.475836  All Pass.

 3667 23:09:51.475955  

 3668 23:09:51.476050  CH 0, Rank 1

 3669 23:09:51.479403  SW Impedance     : PASS

 3670 23:09:51.479525  DUTY Scan        : NO K

 3671 23:09:51.482248  ZQ Calibration   : PASS

 3672 23:09:51.485581  Jitter Meter     : NO K

 3673 23:09:51.485698  CBT Training     : PASS

 3674 23:09:51.488933  Write leveling   : PASS

 3675 23:09:51.492106  RX DQS gating    : PASS

 3676 23:09:51.492238  RX DQ/DQS(RDDQC) : PASS

 3677 23:09:51.495990  TX DQ/DQS        : PASS

 3678 23:09:51.498879  RX DATLAT        : PASS

 3679 23:09:51.498975  RX DQ/DQS(Engine): PASS

 3680 23:09:51.501858  TX OE            : NO K

 3681 23:09:51.501952  All Pass.

 3682 23:09:51.502040  

 3683 23:09:51.505539  CH 1, Rank 0

 3684 23:09:51.505655  SW Impedance     : PASS

 3685 23:09:51.508883  DUTY Scan        : NO K

 3686 23:09:51.512622  ZQ Calibration   : PASS

 3687 23:09:51.512727  Jitter Meter     : NO K

 3688 23:09:51.515556  CBT Training     : PASS

 3689 23:09:51.519316  Write leveling   : PASS

 3690 23:09:51.519408  RX DQS gating    : PASS

 3691 23:09:51.522396  RX DQ/DQS(RDDQC) : PASS

 3692 23:09:51.522484  TX DQ/DQS        : PASS

 3693 23:09:51.525603  RX DATLAT        : PASS

 3694 23:09:51.528684  RX DQ/DQS(Engine): PASS

 3695 23:09:51.528768  TX OE            : NO K

 3696 23:09:51.532438  All Pass.

 3697 23:09:51.532532  

 3698 23:09:51.532599  CH 1, Rank 1

 3699 23:09:51.535668  SW Impedance     : PASS

 3700 23:09:51.535755  DUTY Scan        : NO K

 3701 23:09:51.538605  ZQ Calibration   : PASS

 3702 23:09:51.542289  Jitter Meter     : NO K

 3703 23:09:51.542390  CBT Training     : PASS

 3704 23:09:51.545132  Write leveling   : PASS

 3705 23:09:51.548987  RX DQS gating    : PASS

 3706 23:09:51.549089  RX DQ/DQS(RDDQC) : PASS

 3707 23:09:51.552405  TX DQ/DQS        : PASS

 3708 23:09:51.555540  RX DATLAT        : PASS

 3709 23:09:51.555630  RX DQ/DQS(Engine): PASS

 3710 23:09:51.559085  TX OE            : NO K

 3711 23:09:51.559178  All Pass.

 3712 23:09:51.559267  

 3713 23:09:51.561929  DramC Write-DBI off

 3714 23:09:51.565218  	PER_BANK_REFRESH: Hybrid Mode

 3715 23:09:51.565314  TX_TRACKING: ON

 3716 23:09:51.575111  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1

 3717 23:09:51.578908  [FAST_K] Save calibration result to emmc

 3718 23:09:51.582043  dramc_set_vcore_voltage set vcore to 650000

 3719 23:09:51.585194  Read voltage for 600, 5

 3720 23:09:51.585284  Vio18 = 0

 3721 23:09:51.585353  Vcore = 650000

 3722 23:09:51.588767  Vdram = 0

 3723 23:09:51.588856  Vddq = 0

 3724 23:09:51.588923  Vmddr = 0

 3725 23:09:51.595492  [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0

 3726 23:09:51.598923  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 3727 23:09:51.601991  MEM_TYPE=3, freq_sel=19

 3728 23:09:51.605089  sv_algorithm_assistance_LP4_1600 

 3729 23:09:51.608643  ============ PULL DRAM RESETB DOWN ============

 3730 23:09:51.611998  ========== PULL DRAM RESETB DOWN end =========

 3731 23:09:51.618559  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3732 23:09:51.621793  =================================== 

 3733 23:09:51.621915  LPDDR4 DRAM CONFIGURATION

 3734 23:09:51.625426  =================================== 

 3735 23:09:51.628581  EX_ROW_EN[0]    = 0x0

 3736 23:09:51.631722  EX_ROW_EN[1]    = 0x0

 3737 23:09:51.631802  LP4Y_EN      = 0x0

 3738 23:09:51.635445  WORK_FSP     = 0x0

 3739 23:09:51.635521  WL           = 0x2

 3740 23:09:51.638649  RL           = 0x2

 3741 23:09:51.638723  BL           = 0x2

 3742 23:09:51.641751  RPST         = 0x0

 3743 23:09:51.641828  RD_PRE       = 0x0

 3744 23:09:51.645563  WR_PRE       = 0x1

 3745 23:09:51.645645  WR_PST       = 0x0

 3746 23:09:51.648595  DBI_WR       = 0x0

 3747 23:09:51.648697  DBI_RD       = 0x0

 3748 23:09:51.652157  OTF          = 0x1

 3749 23:09:51.655354  =================================== 

 3750 23:09:51.658482  =================================== 

 3751 23:09:51.658563  ANA top config

 3752 23:09:51.662362  =================================== 

 3753 23:09:51.665379  DLL_ASYNC_EN            =  0

 3754 23:09:51.668601  ALL_SLAVE_EN            =  1

 3755 23:09:51.668678  NEW_RANK_MODE           =  1

 3756 23:09:51.672186  DLL_IDLE_MODE           =  1

 3757 23:09:51.675119  LP45_APHY_COMB_EN       =  1

 3758 23:09:51.678614  TX_ODT_DIS              =  1

 3759 23:09:51.681948  NEW_8X_MODE             =  1

 3760 23:09:51.685521  =================================== 

 3761 23:09:51.688581  =================================== 

 3762 23:09:51.688681  data_rate                  = 1200

 3763 23:09:51.692096  CKR                        = 1

 3764 23:09:51.695354  DQ_P2S_RATIO               = 8

 3765 23:09:51.698491  =================================== 

 3766 23:09:51.701715  CA_P2S_RATIO               = 8

 3767 23:09:51.704695  DQ_CA_OPEN                 = 0

 3768 23:09:51.708544  DQ_SEMI_OPEN               = 0

 3769 23:09:51.708730  CA_SEMI_OPEN               = 0

 3770 23:09:51.712186  CA_FULL_RATE               = 0

 3771 23:09:51.714832  DQ_CKDIV4_EN               = 1

 3772 23:09:51.718625  CA_CKDIV4_EN               = 1

 3773 23:09:51.721894  CA_PREDIV_EN               = 0

 3774 23:09:51.724797  PH8_DLY                    = 0

 3775 23:09:51.724975  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 3776 23:09:51.728264  DQ_AAMCK_DIV               = 4

 3777 23:09:51.731367  CA_AAMCK_DIV               = 4

 3778 23:09:51.734724  CA_ADMCK_DIV               = 4

 3779 23:09:51.738497  DQ_TRACK_CA_EN             = 0

 3780 23:09:51.741695  CA_PICK                    = 600

 3781 23:09:51.744695  CA_MCKIO                   = 600

 3782 23:09:51.744786  MCKIO_SEMI                 = 0

 3783 23:09:51.748164  PLL_FREQ                   = 2288

 3784 23:09:51.751369  DQ_UI_PI_RATIO             = 32

 3785 23:09:51.755046  CA_UI_PI_RATIO             = 0

 3786 23:09:51.757952  =================================== 

 3787 23:09:51.761676  =================================== 

 3788 23:09:51.764891  memory_type:LPDDR4         

 3789 23:09:51.764997  GP_NUM     : 10       

 3790 23:09:51.768057  SRAM_EN    : 1       

 3791 23:09:51.771174  MD32_EN    : 0       

 3792 23:09:51.774875  =================================== 

 3793 23:09:51.774969  [ANA_INIT] >>>>>>>>>>>>>> 

 3794 23:09:51.778099  <<<<<< [CONFIGURE PHASE]: ANA_TX

 3795 23:09:51.781327  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 3796 23:09:51.784929  =================================== 

 3797 23:09:51.787897  data_rate = 1200,PCW = 0X5800

 3798 23:09:51.791234  =================================== 

 3799 23:09:51.794419  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 3800 23:09:51.801510  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3801 23:09:51.804636  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3802 23:09:51.811440  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 3803 23:09:51.814669  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 3804 23:09:51.817784  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 3805 23:09:51.817917  [ANA_INIT] flow start 

 3806 23:09:51.821051  [ANA_INIT] PLL >>>>>>>> 

 3807 23:09:51.824758  [ANA_INIT] PLL <<<<<<<< 

 3808 23:09:51.824886  [ANA_INIT] MIDPI >>>>>>>> 

 3809 23:09:51.827717  [ANA_INIT] MIDPI <<<<<<<< 

 3810 23:09:51.831199  [ANA_INIT] DLL >>>>>>>> 

 3811 23:09:51.831344  [ANA_INIT] flow end 

 3812 23:09:51.837996  ============ LP4 DIFF to SE enter ============

 3813 23:09:51.840879  ============ LP4 DIFF to SE exit  ============

 3814 23:09:51.844561  [ANA_INIT] <<<<<<<<<<<<< 

 3815 23:09:51.847917  [Flow] Enable top DCM control >>>>> 

 3816 23:09:51.850724  [Flow] Enable top DCM control <<<<< 

 3817 23:09:51.854127  Enable DLL master slave shuffle 

 3818 23:09:51.857842  ============================================================== 

 3819 23:09:51.861134  Gating Mode config

 3820 23:09:51.864108  ============================================================== 

 3821 23:09:51.867298  Config description: 

 3822 23:09:51.877694  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 3823 23:09:51.884126  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 3824 23:09:51.887545  SELPH_MODE            0: By rank         1: By Phase 

 3825 23:09:51.893897  ============================================================== 

 3826 23:09:51.897420  GAT_TRACK_EN                 =  1

 3827 23:09:51.901031  RX_GATING_MODE               =  2

 3828 23:09:51.903934  RX_GATING_TRACK_MODE         =  2

 3829 23:09:51.907353  SELPH_MODE                   =  1

 3830 23:09:51.910609  PICG_EARLY_EN                =  1

 3831 23:09:51.910709  VALID_LAT_VALUE              =  1

 3832 23:09:51.917442  ============================================================== 

 3833 23:09:51.920557  Enter into Gating configuration >>>> 

 3834 23:09:51.924479  Exit from Gating configuration <<<< 

 3835 23:09:51.927546  Enter into  DVFS_PRE_config >>>>> 

 3836 23:09:51.937514  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 3837 23:09:51.940657  Exit from  DVFS_PRE_config <<<<< 

 3838 23:09:51.944184  Enter into PICG configuration >>>> 

 3839 23:09:51.947015  Exit from PICG configuration <<<< 

 3840 23:09:51.950943  [RX_INPUT] configuration >>>>> 

 3841 23:09:51.953711  [RX_INPUT] configuration <<<<< 

 3842 23:09:51.957276  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 3843 23:09:51.964182  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 3844 23:09:51.970476  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 3845 23:09:51.977308  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 3846 23:09:51.984005  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 3847 23:09:51.987192  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 3848 23:09:51.994092  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 3849 23:09:51.997293  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 3850 23:09:52.000455  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 3851 23:09:52.004051  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 3852 23:09:52.010528  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 3853 23:09:52.013629  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3854 23:09:52.017226  =================================== 

 3855 23:09:52.020611  LPDDR4 DRAM CONFIGURATION

 3856 23:09:52.023884  =================================== 

 3857 23:09:52.024019  EX_ROW_EN[0]    = 0x0

 3858 23:09:52.026984  EX_ROW_EN[1]    = 0x0

 3859 23:09:52.027112  LP4Y_EN      = 0x0

 3860 23:09:52.030245  WORK_FSP     = 0x0

 3861 23:09:52.030381  WL           = 0x2

 3862 23:09:52.034050  RL           = 0x2

 3863 23:09:52.034188  BL           = 0x2

 3864 23:09:52.037167  RPST         = 0x0

 3865 23:09:52.037297  RD_PRE       = 0x0

 3866 23:09:52.040408  WR_PRE       = 0x1

 3867 23:09:52.040500  WR_PST       = 0x0

 3868 23:09:52.044037  DBI_WR       = 0x0

 3869 23:09:52.047234  DBI_RD       = 0x0

 3870 23:09:52.047345  OTF          = 0x1

 3871 23:09:52.050372  =================================== 

 3872 23:09:52.053495  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 3873 23:09:52.057166  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 3874 23:09:52.063628  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3875 23:09:52.067146  =================================== 

 3876 23:09:52.070177  LPDDR4 DRAM CONFIGURATION

 3877 23:09:52.073615  =================================== 

 3878 23:09:52.073761  EX_ROW_EN[0]    = 0x10

 3879 23:09:52.076977  EX_ROW_EN[1]    = 0x0

 3880 23:09:52.077112  LP4Y_EN      = 0x0

 3881 23:09:52.079987  WORK_FSP     = 0x0

 3882 23:09:52.080119  WL           = 0x2

 3883 23:09:52.083385  RL           = 0x2

 3884 23:09:52.083516  BL           = 0x2

 3885 23:09:52.086709  RPST         = 0x0

 3886 23:09:52.086838  RD_PRE       = 0x0

 3887 23:09:52.090245  WR_PRE       = 0x1

 3888 23:09:52.090380  WR_PST       = 0x0

 3889 23:09:52.093464  DBI_WR       = 0x0

 3890 23:09:52.093594  DBI_RD       = 0x0

 3891 23:09:52.096572  OTF          = 0x1

 3892 23:09:52.100233  =================================== 

 3893 23:09:52.106439  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 3894 23:09:52.110133  nWR fixed to 30

 3895 23:09:52.113108  [ModeRegInit_LP4] CH0 RK0

 3896 23:09:52.113261  [ModeRegInit_LP4] CH0 RK1

 3897 23:09:52.116609  [ModeRegInit_LP4] CH1 RK0

 3898 23:09:52.119845  [ModeRegInit_LP4] CH1 RK1

 3899 23:09:52.119947  match AC timing 17

 3900 23:09:52.126953  dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1

 3901 23:09:52.129910  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 3902 23:09:52.133118  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 3903 23:09:52.140107  [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17

 3904 23:09:52.143391  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

 3905 23:09:52.143496  ==

 3906 23:09:52.146555  Dram Type= 6, Freq= 0, CH_0, rank 0

 3907 23:09:52.149809  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3908 23:09:52.149907  ==

 3909 23:09:52.156882  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3910 23:09:52.163523  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 3911 23:09:52.166445  [CA 0] Center 35 (5~66) winsize 62

 3912 23:09:52.169576  [CA 1] Center 35 (5~66) winsize 62

 3913 23:09:52.173087  [CA 2] Center 33 (3~64) winsize 62

 3914 23:09:52.176401  [CA 3] Center 33 (2~64) winsize 63

 3915 23:09:52.179815  [CA 4] Center 33 (2~64) winsize 63

 3916 23:09:52.183227  [CA 5] Center 32 (2~63) winsize 62

 3917 23:09:52.183374  

 3918 23:09:52.186628  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 3919 23:09:52.186766  

 3920 23:09:52.189545  [CATrainingPosCal] consider 1 rank data

 3921 23:09:52.193194  u2DelayCellTimex100 = 270/100 ps

 3922 23:09:52.196373  CA0 delay=35 (5~66),Diff = 3 PI (28 cell)

 3923 23:09:52.199693  CA1 delay=35 (5~66),Diff = 3 PI (28 cell)

 3924 23:09:52.203131  CA2 delay=33 (3~64),Diff = 1 PI (9 cell)

 3925 23:09:52.206148  CA3 delay=33 (2~64),Diff = 1 PI (9 cell)

 3926 23:09:52.209381  CA4 delay=33 (2~64),Diff = 1 PI (9 cell)

 3927 23:09:52.213083  CA5 delay=32 (2~63),Diff = 0 PI (0 cell)

 3928 23:09:52.216042  

 3929 23:09:52.219505  CA PerBit enable=1, Macro0, CA PI delay=32

 3930 23:09:52.219625  

 3931 23:09:52.222977  [CBTSetCACLKResult] CA Dly = 32

 3932 23:09:52.223059  CS Dly: 4 (0~35)

 3933 23:09:52.223123  ==

 3934 23:09:52.226020  Dram Type= 6, Freq= 0, CH_0, rank 1

 3935 23:09:52.229864  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3936 23:09:52.229964  ==

 3937 23:09:52.236249  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3938 23:09:52.242620  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 3939 23:09:52.245855  [CA 0] Center 35 (5~66) winsize 62

 3940 23:09:52.249081  [CA 1] Center 35 (5~66) winsize 62

 3941 23:09:52.252888  [CA 2] Center 34 (3~65) winsize 63

 3942 23:09:52.255965  [CA 3] Center 33 (2~64) winsize 63

 3943 23:09:52.259109  [CA 4] Center 32 (2~63) winsize 62

 3944 23:09:52.262343  [CA 5] Center 32 (2~63) winsize 62

 3945 23:09:52.262493  

 3946 23:09:52.266196  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3947 23:09:52.266318  

 3948 23:09:52.269394  [CATrainingPosCal] consider 2 rank data

 3949 23:09:52.272587  u2DelayCellTimex100 = 270/100 ps

 3950 23:09:52.275662  CA0 delay=35 (5~66),Diff = 3 PI (28 cell)

 3951 23:09:52.279200  CA1 delay=35 (5~66),Diff = 3 PI (28 cell)

 3952 23:09:52.282646  CA2 delay=33 (3~64),Diff = 1 PI (9 cell)

 3953 23:09:52.285646  CA3 delay=33 (2~64),Diff = 1 PI (9 cell)

 3954 23:09:52.292165  CA4 delay=32 (2~63),Diff = 0 PI (0 cell)

 3955 23:09:52.295544  CA5 delay=32 (2~63),Diff = 0 PI (0 cell)

 3956 23:09:52.295652  

 3957 23:09:52.299148  CA PerBit enable=1, Macro0, CA PI delay=32

 3958 23:09:52.299283  

 3959 23:09:52.302222  [CBTSetCACLKResult] CA Dly = 32

 3960 23:09:52.302312  CS Dly: 4 (0~36)

 3961 23:09:52.302379  

 3962 23:09:52.305726  ----->DramcWriteLeveling(PI) begin...

 3963 23:09:52.305818  ==

 3964 23:09:52.309087  Dram Type= 6, Freq= 0, CH_0, rank 0

 3965 23:09:52.315850  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3966 23:09:52.315968  ==

 3967 23:09:52.318818  Write leveling (Byte 0): 35 => 35

 3968 23:09:52.322485  Write leveling (Byte 1): 33 => 33

 3969 23:09:52.322601  DramcWriteLeveling(PI) end<-----

 3970 23:09:52.322702  

 3971 23:09:52.325462  ==

 3972 23:09:52.325553  Dram Type= 6, Freq= 0, CH_0, rank 0

 3973 23:09:52.332547  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3974 23:09:52.332660  ==

 3975 23:09:52.335693  [Gating] SW mode calibration

 3976 23:09:52.342442  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 3977 23:09:52.345611  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 3978 23:09:52.352469   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3979 23:09:52.355674   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3980 23:09:52.358833   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3981 23:09:52.365508   0  9 12 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 1)

 3982 23:09:52.368763   0  9 16 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)

 3983 23:09:52.372873   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3984 23:09:52.379139   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3985 23:09:52.382510   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3986 23:09:52.385356   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3987 23:09:52.392250   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3988 23:09:52.395397   0 10  8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 3989 23:09:52.398937   0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)

 3990 23:09:52.401932   0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)

 3991 23:09:52.408915   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3992 23:09:52.412245   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3993 23:09:52.415636   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3994 23:09:52.422618   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3995 23:09:52.425359   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3996 23:09:52.428883   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3997 23:09:52.435562   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3998 23:09:52.439035   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 3999 23:09:52.442269   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4000 23:09:52.448982   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4001 23:09:52.452251   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4002 23:09:52.455938   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4003 23:09:52.462218   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4004 23:09:52.465559   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4005 23:09:52.469401   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4006 23:09:52.475762   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4007 23:09:52.478890   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4008 23:09:52.482727   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4009 23:09:52.485930   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4010 23:09:52.492182   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4011 23:09:52.495942   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4012 23:09:52.499218   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4013 23:09:52.506021   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 4014 23:09:52.509141  Total UI for P1: 0, mck2ui 16

 4015 23:09:52.512160  best dqsien dly found for B0: ( 0, 13, 10)

 4016 23:09:52.515925   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4017 23:09:52.519150  Total UI for P1: 0, mck2ui 16

 4018 23:09:52.522401  best dqsien dly found for B1: ( 0, 13, 14)

 4019 23:09:52.525603  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4020 23:09:52.529391  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4021 23:09:52.529528  

 4022 23:09:52.532611  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4023 23:09:52.535600  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4024 23:09:52.539244  [Gating] SW calibration Done

 4025 23:09:52.539333  ==

 4026 23:09:52.542222  Dram Type= 6, Freq= 0, CH_0, rank 0

 4027 23:09:52.545630  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4028 23:09:52.549109  ==

 4029 23:09:52.549220  RX Vref Scan: 0

 4030 23:09:52.549312  

 4031 23:09:52.552696  RX Vref 0 -> 0, step: 1

 4032 23:09:52.552801  

 4033 23:09:52.555602  RX Delay -230 -> 252, step: 16

 4034 23:09:52.559207  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4035 23:09:52.562567  iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320

 4036 23:09:52.565618  iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304

 4037 23:09:52.572605  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4038 23:09:52.576144  iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320

 4039 23:09:52.579511  iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304

 4040 23:09:52.582570  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4041 23:09:52.585794  iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320

 4042 23:09:52.592947  iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288

 4043 23:09:52.595589  iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288

 4044 23:09:52.599151  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4045 23:09:52.602550  iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304

 4046 23:09:52.609185  iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304

 4047 23:09:52.612252  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4048 23:09:52.615956  iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320

 4049 23:09:52.618998  iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320

 4050 23:09:52.619101  ==

 4051 23:09:52.622241  Dram Type= 6, Freq= 0, CH_0, rank 0

 4052 23:09:52.629542  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4053 23:09:52.629660  ==

 4054 23:09:52.629754  DQS Delay:

 4055 23:09:52.629839  DQS0 = 0, DQS1 = 0

 4056 23:09:52.632561  DQM Delay:

 4057 23:09:52.632652  DQM0 = 53, DQM1 = 49

 4058 23:09:52.636163  DQ Delay:

 4059 23:09:52.639513  DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49

 4060 23:09:52.639615  DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57

 4061 23:09:52.642611  DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49

 4062 23:09:52.645958  DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57

 4063 23:09:52.649527  

 4064 23:09:52.649628  

 4065 23:09:52.649720  ==

 4066 23:09:52.652680  Dram Type= 6, Freq= 0, CH_0, rank 0

 4067 23:09:52.655867  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4068 23:09:52.655989  ==

 4069 23:09:52.656094  

 4070 23:09:52.656196  

 4071 23:09:52.659102  	TX Vref Scan disable

 4072 23:09:52.659217   == TX Byte 0 ==

 4073 23:09:52.665612  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 4074 23:09:52.669390  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 4075 23:09:52.669510   == TX Byte 1 ==

 4076 23:09:52.676010  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 4077 23:09:52.678909  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 4078 23:09:52.679012  ==

 4079 23:09:52.682408  Dram Type= 6, Freq= 0, CH_0, rank 0

 4080 23:09:52.686033  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4081 23:09:52.686139  ==

 4082 23:09:52.686231  

 4083 23:09:52.686315  

 4084 23:09:52.689223  	TX Vref Scan disable

 4085 23:09:52.692465   == TX Byte 0 ==

 4086 23:09:52.695582  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4087 23:09:52.699389  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4088 23:09:52.702606   == TX Byte 1 ==

 4089 23:09:52.705585  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 4090 23:09:52.709007  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 4091 23:09:52.712067  

 4092 23:09:52.712203  [DATLAT]

 4093 23:09:52.712313  Freq=600, CH0 RK0

 4094 23:09:52.712407  

 4095 23:09:52.715674  DATLAT Default: 0x9

 4096 23:09:52.715763  0, 0xFFFF, sum = 0

 4097 23:09:52.718888  1, 0xFFFF, sum = 0

 4098 23:09:52.718977  2, 0xFFFF, sum = 0

 4099 23:09:52.722431  3, 0xFFFF, sum = 0

 4100 23:09:52.722527  4, 0xFFFF, sum = 0

 4101 23:09:52.726158  5, 0xFFFF, sum = 0

 4102 23:09:52.726254  6, 0xFFFF, sum = 0

 4103 23:09:52.729337  7, 0xFFFF, sum = 0

 4104 23:09:52.729457  8, 0x0, sum = 1

 4105 23:09:52.732519  9, 0x0, sum = 2

 4106 23:09:52.732633  10, 0x0, sum = 3

 4107 23:09:52.735524  11, 0x0, sum = 4

 4108 23:09:52.735646  best_step = 9

 4109 23:09:52.735736  

 4110 23:09:52.735800  ==

 4111 23:09:52.739286  Dram Type= 6, Freq= 0, CH_0, rank 0

 4112 23:09:52.745668  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4113 23:09:52.745776  ==

 4114 23:09:52.745845  RX Vref Scan: 1

 4115 23:09:52.745907  

 4116 23:09:52.748904  RX Vref 0 -> 0, step: 1

 4117 23:09:52.749010  

 4118 23:09:52.752140  RX Delay -147 -> 252, step: 8

 4119 23:09:52.752251  

 4120 23:09:52.755702  Set Vref, RX VrefLevel [Byte0]: 61

 4121 23:09:52.758853                           [Byte1]: 49

 4122 23:09:52.758943  

 4123 23:09:52.762067  Final RX Vref Byte 0 = 61 to rank0

 4124 23:09:52.765200  Final RX Vref Byte 1 = 49 to rank0

 4125 23:09:52.769185  Final RX Vref Byte 0 = 61 to rank1

 4126 23:09:52.772261  Final RX Vref Byte 1 = 49 to rank1==

 4127 23:09:52.775432  Dram Type= 6, Freq= 0, CH_0, rank 0

 4128 23:09:52.778587  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4129 23:09:52.778675  ==

 4130 23:09:52.782259  DQS Delay:

 4131 23:09:52.782342  DQS0 = 0, DQS1 = 0

 4132 23:09:52.782405  DQM Delay:

 4133 23:09:52.785186  DQM0 = 52, DQM1 = 46

 4134 23:09:52.785287  DQ Delay:

 4135 23:09:52.788661  DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =52

 4136 23:09:52.791877  DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60

 4137 23:09:52.795434  DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40

 4138 23:09:52.798519  DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52

 4139 23:09:52.798675  

 4140 23:09:52.798796  

 4141 23:09:52.809033  [DQSOSCAuto] RK0, (LSB)MR18= 0x6e60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps

 4142 23:09:52.809188  CH0 RK0: MR19=808, MR18=6E60

 4143 23:09:52.815499  CH0_RK0: MR19=0x808, MR18=0x6E60, DQSOSC=389, MR23=63, INC=173, DEC=115

 4144 23:09:52.815615  

 4145 23:09:52.818885  ----->DramcWriteLeveling(PI) begin...

 4146 23:09:52.822176  ==

 4147 23:09:52.822276  Dram Type= 6, Freq= 0, CH_0, rank 1

 4148 23:09:52.828790  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4149 23:09:52.828932  ==

 4150 23:09:52.831928  Write leveling (Byte 0): 32 => 32

 4151 23:09:52.835224  Write leveling (Byte 1): 31 => 31

 4152 23:09:52.835328  DramcWriteLeveling(PI) end<-----

 4153 23:09:52.838536  

 4154 23:09:52.838658  ==

 4155 23:09:52.841673  Dram Type= 6, Freq= 0, CH_0, rank 1

 4156 23:09:52.845299  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4157 23:09:52.845403  ==

 4158 23:09:52.848551  [Gating] SW mode calibration

 4159 23:09:52.854947  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4160 23:09:52.858642  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4161 23:09:52.865378   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4162 23:09:52.868492   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4163 23:09:52.871860   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4164 23:09:52.878810   0  9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)

 4165 23:09:52.881865   0  9 16 | B1->B0 | 2b2b 2727 | 0 0 | (0 0) (0 0)

 4166 23:09:52.885089   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4167 23:09:52.891567   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4168 23:09:52.894832   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4169 23:09:52.898367   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4170 23:09:52.905276   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4171 23:09:52.908330   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4172 23:09:52.911712   0 10 12 | B1->B0 | 2727 2b2b | 0 0 | (0 0) (0 0)

 4173 23:09:52.918402   0 10 16 | B1->B0 | 3b3b 4343 | 0 0 | (1 1) (0 0)

 4174 23:09:52.921327   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4175 23:09:52.924663   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4176 23:09:52.931494   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4177 23:09:52.935101   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4178 23:09:52.938055   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4179 23:09:52.944881   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4180 23:09:52.948237   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4181 23:09:52.951396   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 4182 23:09:52.957869   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4183 23:09:52.961240   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4184 23:09:52.964988   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4185 23:09:52.971128   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4186 23:09:52.975065   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4187 23:09:52.978265   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4188 23:09:52.981421   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4189 23:09:52.987834   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4190 23:09:52.991214   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4191 23:09:52.995020   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4192 23:09:53.001550   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4193 23:09:53.004508   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4194 23:09:53.007870   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4195 23:09:53.014996   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4196 23:09:53.018147   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4197 23:09:53.021591   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4198 23:09:53.024869  Total UI for P1: 0, mck2ui 16

 4199 23:09:53.027884  best dqsien dly found for B0: ( 0, 13, 12)

 4200 23:09:53.031455  Total UI for P1: 0, mck2ui 16

 4201 23:09:53.034408  best dqsien dly found for B1: ( 0, 13, 14)

 4202 23:09:53.038079  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4203 23:09:53.041163  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4204 23:09:53.041263  

 4205 23:09:53.048132  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4206 23:09:53.051066  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4207 23:09:53.054510  [Gating] SW calibration Done

 4208 23:09:53.054615  ==

 4209 23:09:53.057709  Dram Type= 6, Freq= 0, CH_0, rank 1

 4210 23:09:53.061089  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4211 23:09:53.061197  ==

 4212 23:09:53.061287  RX Vref Scan: 0

 4213 23:09:53.061392  

 4214 23:09:53.064842  RX Vref 0 -> 0, step: 1

 4215 23:09:53.064937  

 4216 23:09:53.067938  RX Delay -230 -> 252, step: 16

 4217 23:09:53.071159  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4218 23:09:53.074432  iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304

 4219 23:09:53.081267  iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304

 4220 23:09:53.084858  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4221 23:09:53.087986  iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304

 4222 23:09:53.091008  iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320

 4223 23:09:53.098091  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4224 23:09:53.101435  iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320

 4225 23:09:53.104605  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4226 23:09:53.107625  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4227 23:09:53.111306  iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320

 4228 23:09:53.117748  iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304

 4229 23:09:53.120971  iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304

 4230 23:09:53.124210  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4231 23:09:53.128158  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4232 23:09:53.134247  iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304

 4233 23:09:53.134411  ==

 4234 23:09:53.137858  Dram Type= 6, Freq= 0, CH_0, rank 1

 4235 23:09:53.140880  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4236 23:09:53.141021  ==

 4237 23:09:53.141139  DQS Delay:

 4238 23:09:53.144434  DQS0 = 0, DQS1 = 0

 4239 23:09:53.144538  DQM Delay:

 4240 23:09:53.147585  DQM0 = 50, DQM1 = 42

 4241 23:09:53.147675  DQ Delay:

 4242 23:09:53.151316  DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49

 4243 23:09:53.154667  DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57

 4244 23:09:53.157886  DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33

 4245 23:09:53.161098  DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49

 4246 23:09:53.161192  

 4247 23:09:53.161258  

 4248 23:09:53.161337  ==

 4249 23:09:53.164229  Dram Type= 6, Freq= 0, CH_0, rank 1

 4250 23:09:53.167927  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4251 23:09:53.168031  ==

 4252 23:09:53.168103  

 4253 23:09:53.171103  

 4254 23:09:53.171223  	TX Vref Scan disable

 4255 23:09:53.174225   == TX Byte 0 ==

 4256 23:09:53.177642  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4257 23:09:53.181468  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4258 23:09:53.184375   == TX Byte 1 ==

 4259 23:09:53.187960  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4260 23:09:53.191320  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4261 23:09:53.191431  ==

 4262 23:09:53.194397  Dram Type= 6, Freq= 0, CH_0, rank 1

 4263 23:09:53.201059  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4264 23:09:53.201176  ==

 4265 23:09:53.201279  

 4266 23:09:53.201345  

 4267 23:09:53.201405  	TX Vref Scan disable

 4268 23:09:53.205352   == TX Byte 0 ==

 4269 23:09:53.209134  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4270 23:09:53.215372  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4271 23:09:53.215493   == TX Byte 1 ==

 4272 23:09:53.218481  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4273 23:09:53.225435  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4274 23:09:53.225553  

 4275 23:09:53.225622  [DATLAT]

 4276 23:09:53.225724  Freq=600, CH0 RK1

 4277 23:09:53.225808  

 4278 23:09:53.228615  DATLAT Default: 0x9

 4279 23:09:53.228703  0, 0xFFFF, sum = 0

 4280 23:09:53.231847  1, 0xFFFF, sum = 0

 4281 23:09:53.231938  2, 0xFFFF, sum = 0

 4282 23:09:53.235674  3, 0xFFFF, sum = 0

 4283 23:09:53.238745  4, 0xFFFF, sum = 0

 4284 23:09:53.238840  5, 0xFFFF, sum = 0

 4285 23:09:53.241716  6, 0xFFFF, sum = 0

 4286 23:09:53.241809  7, 0xFFFF, sum = 0

 4287 23:09:53.245300  8, 0x0, sum = 1

 4288 23:09:53.245394  9, 0x0, sum = 2

 4289 23:09:53.245462  10, 0x0, sum = 3

 4290 23:09:53.249246  11, 0x0, sum = 4

 4291 23:09:53.249340  best_step = 9

 4292 23:09:53.249407  

 4293 23:09:53.249468  ==

 4294 23:09:53.252126  Dram Type= 6, Freq= 0, CH_0, rank 1

 4295 23:09:53.258393  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4296 23:09:53.258538  ==

 4297 23:09:53.258644  RX Vref Scan: 0

 4298 23:09:53.258735  

 4299 23:09:53.262150  RX Vref 0 -> 0, step: 1

 4300 23:09:53.262276  

 4301 23:09:53.265635  RX Delay -163 -> 252, step: 8

 4302 23:09:53.268667  iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288

 4303 23:09:53.275490  iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280

 4304 23:09:53.278637  iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288

 4305 23:09:53.281789  iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288

 4306 23:09:53.285255  iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280

 4307 23:09:53.288355  iDelay=205, Bit 5, Center 48 (-91 ~ 188) 280

 4308 23:09:53.294906  iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288

 4309 23:09:53.298737  iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288

 4310 23:09:53.301730  iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288

 4311 23:09:53.305228  iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288

 4312 23:09:53.308545  iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280

 4313 23:09:53.314961  iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280

 4314 23:09:53.318370  iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288

 4315 23:09:53.321797  iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288

 4316 23:09:53.325140  iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280

 4317 23:09:53.328392  iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288

 4318 23:09:53.331526  ==

 4319 23:09:53.334918  Dram Type= 6, Freq= 0, CH_0, rank 1

 4320 23:09:53.337967  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4321 23:09:53.338093  ==

 4322 23:09:53.338171  DQS Delay:

 4323 23:09:53.341872  DQS0 = 0, DQS1 = 0

 4324 23:09:53.341997  DQM Delay:

 4325 23:09:53.345003  DQM0 = 54, DQM1 = 46

 4326 23:09:53.345122  DQ Delay:

 4327 23:09:53.348144  DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52

 4328 23:09:53.351416  DQ4 =56, DQ5 =48, DQ6 =60, DQ7 =60

 4329 23:09:53.355378  DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40

 4330 23:09:53.358262  DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52

 4331 23:09:53.358382  

 4332 23:09:53.358478  

 4333 23:09:53.365116  [DQSOSCAuto] RK1, (LSB)MR18= 0x6121, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps

 4334 23:09:53.368404  CH0 RK1: MR19=808, MR18=6121

 4335 23:09:53.375141  CH0_RK1: MR19=0x808, MR18=0x6121, DQSOSC=391, MR23=63, INC=171, DEC=114

 4336 23:09:53.378181  [RxdqsGatingPostProcess] freq 600

 4337 23:09:53.385036  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4338 23:09:53.385155  Pre-setting of DQS Precalculation

 4339 23:09:53.391490  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4340 23:09:53.391624  ==

 4341 23:09:53.394906  Dram Type= 6, Freq= 0, CH_1, rank 0

 4342 23:09:53.398089  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4343 23:09:53.398188  ==

 4344 23:09:53.404710  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4345 23:09:53.411187  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 4346 23:09:53.414969  [CA 0] Center 36 (5~67) winsize 63

 4347 23:09:53.418234  [CA 1] Center 36 (5~67) winsize 63

 4348 23:09:53.421252  [CA 2] Center 34 (4~65) winsize 62

 4349 23:09:53.424849  [CA 3] Center 34 (4~65) winsize 62

 4350 23:09:53.428239  [CA 4] Center 34 (4~65) winsize 62

 4351 23:09:53.431379  [CA 5] Center 34 (3~65) winsize 63

 4352 23:09:53.431503  

 4353 23:09:53.434499  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 4354 23:09:53.434593  

 4355 23:09:53.437957  [CATrainingPosCal] consider 1 rank data

 4356 23:09:53.440955  u2DelayCellTimex100 = 270/100 ps

 4357 23:09:53.444525  CA0 delay=36 (5~67),Diff = 2 PI (19 cell)

 4358 23:09:53.447822  CA1 delay=36 (5~67),Diff = 2 PI (19 cell)

 4359 23:09:53.451202  CA2 delay=34 (4~65),Diff = 0 PI (0 cell)

 4360 23:09:53.454534  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 4361 23:09:53.458047  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 4362 23:09:53.461586  CA5 delay=34 (3~65),Diff = 0 PI (0 cell)

 4363 23:09:53.461726  

 4364 23:09:53.467680  CA PerBit enable=1, Macro0, CA PI delay=34

 4365 23:09:53.467812  

 4366 23:09:53.467914  [CBTSetCACLKResult] CA Dly = 34

 4367 23:09:53.471001  CS Dly: 6 (0~37)

 4368 23:09:53.471113  ==

 4369 23:09:53.474785  Dram Type= 6, Freq= 0, CH_1, rank 1

 4370 23:09:53.477998  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4371 23:09:53.478110  ==

 4372 23:09:53.484224  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4373 23:09:53.491249  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 4374 23:09:53.494492  [CA 0] Center 36 (5~67) winsize 63

 4375 23:09:53.497699  [CA 1] Center 36 (5~67) winsize 63

 4376 23:09:53.500927  [CA 2] Center 34 (4~65) winsize 62

 4377 23:09:53.504456  [CA 3] Center 34 (4~65) winsize 62

 4378 23:09:53.507600  [CA 4] Center 35 (4~66) winsize 63

 4379 23:09:53.510883  [CA 5] Center 34 (4~65) winsize 62

 4380 23:09:53.511002  

 4381 23:09:53.514720  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 4382 23:09:53.514815  

 4383 23:09:53.517916  [CATrainingPosCal] consider 2 rank data

 4384 23:09:53.521150  u2DelayCellTimex100 = 270/100 ps

 4385 23:09:53.524325  CA0 delay=36 (5~67),Diff = 2 PI (19 cell)

 4386 23:09:53.528007  CA1 delay=36 (5~67),Diff = 2 PI (19 cell)

 4387 23:09:53.531208  CA2 delay=34 (4~65),Diff = 0 PI (0 cell)

 4388 23:09:53.534460  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 4389 23:09:53.537818  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 4390 23:09:53.544460  CA5 delay=34 (4~65),Diff = 0 PI (0 cell)

 4391 23:09:53.544620  

 4392 23:09:53.547397  CA PerBit enable=1, Macro0, CA PI delay=34

 4393 23:09:53.547537  

 4394 23:09:53.550961  [CBTSetCACLKResult] CA Dly = 34

 4395 23:09:53.551099  CS Dly: 6 (0~38)

 4396 23:09:53.551216  

 4397 23:09:53.554252  ----->DramcWriteLeveling(PI) begin...

 4398 23:09:53.554384  ==

 4399 23:09:53.557422  Dram Type= 6, Freq= 0, CH_1, rank 0

 4400 23:09:53.561131  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4401 23:09:53.563997  ==

 4402 23:09:53.564127  Write leveling (Byte 0): 29 => 29

 4403 23:09:53.567557  Write leveling (Byte 1): 31 => 31

 4404 23:09:53.571092  DramcWriteLeveling(PI) end<-----

 4405 23:09:53.571219  

 4406 23:09:53.571320  ==

 4407 23:09:53.573993  Dram Type= 6, Freq= 0, CH_1, rank 0

 4408 23:09:53.580804  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4409 23:09:53.580969  ==

 4410 23:09:53.581091  [Gating] SW mode calibration

 4411 23:09:53.590844  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4412 23:09:53.594008  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4413 23:09:53.597831   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4414 23:09:53.604073   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4415 23:09:53.607632   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4416 23:09:53.611254   0  9 12 | B1->B0 | 3030 2e2e | 0 0 | (0 1) (1 1)

 4417 23:09:53.617505   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4418 23:09:53.620681   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4419 23:09:53.624398   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4420 23:09:53.630616   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4421 23:09:53.634552   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4422 23:09:53.637686   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4423 23:09:53.643963   0 10  8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 4424 23:09:53.647615   0 10 12 | B1->B0 | 3737 3939 | 0 1 | (0 0) (0 0)

 4425 23:09:53.650723   0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4426 23:09:53.657788   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4427 23:09:53.660961   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4428 23:09:53.664169   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4429 23:09:53.670719   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4430 23:09:53.674025   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4431 23:09:53.677469   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4432 23:09:53.684210   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4433 23:09:53.687766   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4434 23:09:53.690632   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4435 23:09:53.694532   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4436 23:09:53.701114   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4437 23:09:53.704437   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4438 23:09:53.707476   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4439 23:09:53.714045   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4440 23:09:53.717687   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4441 23:09:53.720798   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4442 23:09:53.727540   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4443 23:09:53.731349   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4444 23:09:53.734559   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4445 23:09:53.740856   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4446 23:09:53.744050   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4447 23:09:53.747866   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4448 23:09:53.754124   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 4449 23:09:53.757843   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4450 23:09:53.761129  Total UI for P1: 0, mck2ui 16

 4451 23:09:53.764283  best dqsien dly found for B0: ( 0, 13, 14)

 4452 23:09:53.767430  Total UI for P1: 0, mck2ui 16

 4453 23:09:53.771259  best dqsien dly found for B1: ( 0, 13, 12)

 4454 23:09:53.774392  best DQS0 dly(MCK, UI, PI) = (0, 13, 14)

 4455 23:09:53.777296  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4456 23:09:53.777388  

 4457 23:09:53.780737  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4458 23:09:53.783872  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4459 23:09:53.787492  [Gating] SW calibration Done

 4460 23:09:53.787587  ==

 4461 23:09:53.791019  Dram Type= 6, Freq= 0, CH_1, rank 0

 4462 23:09:53.793968  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4463 23:09:53.797544  ==

 4464 23:09:53.797667  RX Vref Scan: 0

 4465 23:09:53.797765  

 4466 23:09:53.800755  RX Vref 0 -> 0, step: 1

 4467 23:09:53.800844  

 4468 23:09:53.804328  RX Delay -230 -> 252, step: 16

 4469 23:09:53.807516  iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320

 4470 23:09:53.810657  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4471 23:09:53.813858  iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320

 4472 23:09:53.817471  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4473 23:09:53.824790  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4474 23:09:53.827507  iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320

 4475 23:09:53.830706  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4476 23:09:53.834268  iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320

 4477 23:09:53.837412  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4478 23:09:53.843907  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4479 23:09:53.847720  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4480 23:09:53.850879  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4481 23:09:53.853950  iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320

 4482 23:09:53.860628  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4483 23:09:53.864300  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4484 23:09:53.867422  iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320

 4485 23:09:53.867573  ==

 4486 23:09:53.870637  Dram Type= 6, Freq= 0, CH_1, rank 0

 4487 23:09:53.874469  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4488 23:09:53.877539  ==

 4489 23:09:53.877678  DQS Delay:

 4490 23:09:53.877798  DQS0 = 0, DQS1 = 0

 4491 23:09:53.880805  DQM Delay:

 4492 23:09:53.880934  DQM0 = 47, DQM1 = 46

 4493 23:09:53.884121  DQ Delay:

 4494 23:09:53.884250  DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41

 4495 23:09:53.887515  DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41

 4496 23:09:53.890926  DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41

 4497 23:09:53.894135  DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57

 4498 23:09:53.897524  

 4499 23:09:53.897655  

 4500 23:09:53.897769  ==

 4501 23:09:53.900503  Dram Type= 6, Freq= 0, CH_1, rank 0

 4502 23:09:53.903870  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4503 23:09:53.903999  ==

 4504 23:09:53.904114  

 4505 23:09:53.904222  

 4506 23:09:53.907472  	TX Vref Scan disable

 4507 23:09:53.907597   == TX Byte 0 ==

 4508 23:09:53.914036  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4509 23:09:53.917249  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4510 23:09:53.917384   == TX Byte 1 ==

 4511 23:09:53.923901  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4512 23:09:53.927560  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4513 23:09:53.927707  ==

 4514 23:09:53.930716  Dram Type= 6, Freq= 0, CH_1, rank 0

 4515 23:09:53.933991  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4516 23:09:53.934124  ==

 4517 23:09:53.934237  

 4518 23:09:53.934349  

 4519 23:09:53.937549  	TX Vref Scan disable

 4520 23:09:53.940709   == TX Byte 0 ==

 4521 23:09:53.943691  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4522 23:09:53.947138  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4523 23:09:53.950390   == TX Byte 1 ==

 4524 23:09:53.953962  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4525 23:09:53.957144  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4526 23:09:53.957277  

 4527 23:09:53.960475  [DATLAT]

 4528 23:09:53.960598  Freq=600, CH1 RK0

 4529 23:09:53.960713  

 4530 23:09:53.963655  DATLAT Default: 0x9

 4531 23:09:53.963780  0, 0xFFFF, sum = 0

 4532 23:09:53.967313  1, 0xFFFF, sum = 0

 4533 23:09:53.967448  2, 0xFFFF, sum = 0

 4534 23:09:53.970532  3, 0xFFFF, sum = 0

 4535 23:09:53.970665  4, 0xFFFF, sum = 0

 4536 23:09:53.973830  5, 0xFFFF, sum = 0

 4537 23:09:53.973959  6, 0xFFFF, sum = 0

 4538 23:09:53.976935  7, 0xFFFF, sum = 0

 4539 23:09:53.977064  8, 0x0, sum = 1

 4540 23:09:53.980747  9, 0x0, sum = 2

 4541 23:09:53.980878  10, 0x0, sum = 3

 4542 23:09:53.983953  11, 0x0, sum = 4

 4543 23:09:53.984080  best_step = 9

 4544 23:09:53.984217  

 4545 23:09:53.984346  ==

 4546 23:09:53.987087  Dram Type= 6, Freq= 0, CH_1, rank 0

 4547 23:09:53.990702  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4548 23:09:53.993655  ==

 4549 23:09:53.993788  RX Vref Scan: 1

 4550 23:09:53.993903  

 4551 23:09:53.997127  RX Vref 0 -> 0, step: 1

 4552 23:09:53.997253  

 4553 23:09:54.000197  RX Delay -163 -> 252, step: 8

 4554 23:09:54.000346  

 4555 23:09:54.003921  Set Vref, RX VrefLevel [Byte0]: 56

 4556 23:09:54.006911                           [Byte1]: 54

 4557 23:09:54.007042  

 4558 23:09:54.010141  Final RX Vref Byte 0 = 56 to rank0

 4559 23:09:54.013635  Final RX Vref Byte 1 = 54 to rank0

 4560 23:09:54.017097  Final RX Vref Byte 0 = 56 to rank1

 4561 23:09:54.020225  Final RX Vref Byte 1 = 54 to rank1==

 4562 23:09:54.023607  Dram Type= 6, Freq= 0, CH_1, rank 0

 4563 23:09:54.027031  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4564 23:09:54.027170  ==

 4565 23:09:54.030691  DQS Delay:

 4566 23:09:54.030822  DQS0 = 0, DQS1 = 0

 4567 23:09:54.030935  DQM Delay:

 4568 23:09:54.033571  DQM0 = 48, DQM1 = 44

 4569 23:09:54.033694  DQ Delay:

 4570 23:09:54.036727  DQ0 =48, DQ1 =44, DQ2 =40, DQ3 =48

 4571 23:09:54.040524  DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48

 4572 23:09:54.043453  DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36

 4573 23:09:54.046636  DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52

 4574 23:09:54.046764  

 4575 23:09:54.046881  

 4576 23:09:54.056689  [DQSOSCAuto] RK0, (LSB)MR18= 0x486e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps

 4577 23:09:54.056867  CH1 RK0: MR19=808, MR18=486E

 4578 23:09:54.063675  CH1_RK0: MR19=0x808, MR18=0x486E, DQSOSC=389, MR23=63, INC=173, DEC=115

 4579 23:09:54.063820  

 4580 23:09:54.066719  ----->DramcWriteLeveling(PI) begin...

 4581 23:09:54.066845  ==

 4582 23:09:54.069992  Dram Type= 6, Freq= 0, CH_1, rank 1

 4583 23:09:54.077050  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4584 23:09:54.077211  ==

 4585 23:09:54.080267  Write leveling (Byte 0): 31 => 31

 4586 23:09:54.083328  Write leveling (Byte 1): 31 => 31

 4587 23:09:54.083460  DramcWriteLeveling(PI) end<-----

 4588 23:09:54.086556  

 4589 23:09:54.086683  ==

 4590 23:09:54.090271  Dram Type= 6, Freq= 0, CH_1, rank 1

 4591 23:09:54.093441  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4592 23:09:54.093576  ==

 4593 23:09:54.096487  [Gating] SW mode calibration

 4594 23:09:54.103545  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4595 23:09:54.106607  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4596 23:09:54.113306   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4597 23:09:54.116514   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4598 23:09:54.120240   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4599 23:09:54.126758   0  9 12 | B1->B0 | 2e2e 2e2e | 0 0 | (0 0) (0 0)

 4600 23:09:54.130065   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4601 23:09:54.133159   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4602 23:09:54.139813   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4603 23:09:54.143361   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4604 23:09:54.146359   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4605 23:09:54.153227   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4606 23:09:54.156380   0 10  8 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)

 4607 23:09:54.159581   0 10 12 | B1->B0 | 3939 3838 | 0 0 | (0 0) (0 0)

 4608 23:09:54.166462   0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4609 23:09:54.170081   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4610 23:09:54.173073   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4611 23:09:54.179939   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4612 23:09:54.183440   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4613 23:09:54.186588   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4614 23:09:54.189883   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 4615 23:09:54.196782   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 4616 23:09:54.199774   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4617 23:09:54.203507   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4618 23:09:54.209462   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4619 23:09:54.213098   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4620 23:09:54.216700   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4621 23:09:54.223021   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4622 23:09:54.226201   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4623 23:09:54.230037   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4624 23:09:54.236587   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4625 23:09:54.239550   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4626 23:09:54.242788   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4627 23:09:54.249470   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4628 23:09:54.252848   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4629 23:09:54.256531   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4630 23:09:54.263154   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4631 23:09:54.266133   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4632 23:09:54.269997  Total UI for P1: 0, mck2ui 16

 4633 23:09:54.273101  best dqsien dly found for B0: ( 0, 13, 10)

 4634 23:09:54.276549   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4635 23:09:54.279514  Total UI for P1: 0, mck2ui 16

 4636 23:09:54.282650  best dqsien dly found for B1: ( 0, 13, 12)

 4637 23:09:54.286515  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4638 23:09:54.289646  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4639 23:09:54.289737  

 4640 23:09:54.296213  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4641 23:09:54.299288  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4642 23:09:54.302629  [Gating] SW calibration Done

 4643 23:09:54.302721  ==

 4644 23:09:54.306348  Dram Type= 6, Freq= 0, CH_1, rank 1

 4645 23:09:54.309513  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4646 23:09:54.309653  ==

 4647 23:09:54.309786  RX Vref Scan: 0

 4648 23:09:54.309914  

 4649 23:09:54.312973  RX Vref 0 -> 0, step: 1

 4650 23:09:54.313101  

 4651 23:09:54.315923  RX Delay -230 -> 252, step: 16

 4652 23:09:54.319276  iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320

 4653 23:09:54.322875  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4654 23:09:54.329195  iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304

 4655 23:09:54.332491  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4656 23:09:54.336135  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4657 23:09:54.339180  iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320

 4658 23:09:54.346072  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4659 23:09:54.349139  iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320

 4660 23:09:54.353032  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4661 23:09:54.356177  iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320

 4662 23:09:54.359508  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4663 23:09:54.366195  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4664 23:09:54.369134  iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320

 4665 23:09:54.372710  iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320

 4666 23:09:54.375838  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4667 23:09:54.382467  iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320

 4668 23:09:54.382585  ==

 4669 23:09:54.386275  Dram Type= 6, Freq= 0, CH_1, rank 1

 4670 23:09:54.389136  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4671 23:09:54.389234  ==

 4672 23:09:54.389301  DQS Delay:

 4673 23:09:54.392809  DQS0 = 0, DQS1 = 0

 4674 23:09:54.392941  DQM Delay:

 4675 23:09:54.395946  DQM0 = 46, DQM1 = 48

 4676 23:09:54.396089  DQ Delay:

 4677 23:09:54.399581  DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41

 4678 23:09:54.402771  DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41

 4679 23:09:54.405914  DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41

 4680 23:09:54.408990  DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57

 4681 23:09:54.409122  

 4682 23:09:54.409238  

 4683 23:09:54.409342  ==

 4684 23:09:54.412631  Dram Type= 6, Freq= 0, CH_1, rank 1

 4685 23:09:54.415514  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4686 23:09:54.415646  ==

 4687 23:09:54.419250  

 4688 23:09:54.419376  

 4689 23:09:54.419486  	TX Vref Scan disable

 4690 23:09:54.422406   == TX Byte 0 ==

 4691 23:09:54.425411  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4692 23:09:54.428927  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4693 23:09:54.432125   == TX Byte 1 ==

 4694 23:09:54.435434  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4695 23:09:54.439051  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4696 23:09:54.439185  ==

 4697 23:09:54.442624  Dram Type= 6, Freq= 0, CH_1, rank 1

 4698 23:09:54.448815  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4699 23:09:54.448966  ==

 4700 23:09:54.449084  

 4701 23:09:54.449195  

 4702 23:09:54.449302  	TX Vref Scan disable

 4703 23:09:54.453281   == TX Byte 0 ==

 4704 23:09:54.457139  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4705 23:09:54.463619  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4706 23:09:54.463759   == TX Byte 1 ==

 4707 23:09:54.467100  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4708 23:09:54.473423  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4709 23:09:54.473576  

 4710 23:09:54.473693  [DATLAT]

 4711 23:09:54.473802  Freq=600, CH1 RK1

 4712 23:09:54.473909  

 4713 23:09:54.476557  DATLAT Default: 0x9

 4714 23:09:54.476683  0, 0xFFFF, sum = 0

 4715 23:09:54.480232  1, 0xFFFF, sum = 0

 4716 23:09:54.483192  2, 0xFFFF, sum = 0

 4717 23:09:54.483322  3, 0xFFFF, sum = 0

 4718 23:09:54.486779  4, 0xFFFF, sum = 0

 4719 23:09:54.486911  5, 0xFFFF, sum = 0

 4720 23:09:54.490069  6, 0xFFFF, sum = 0

 4721 23:09:54.490197  7, 0xFFFF, sum = 0

 4722 23:09:54.493338  8, 0x0, sum = 1

 4723 23:09:54.493468  9, 0x0, sum = 2

 4724 23:09:54.493585  10, 0x0, sum = 3

 4725 23:09:54.496720  11, 0x0, sum = 4

 4726 23:09:54.496847  best_step = 9

 4727 23:09:54.496960  

 4728 23:09:54.497069  ==

 4729 23:09:54.499785  Dram Type= 6, Freq= 0, CH_1, rank 1

 4730 23:09:54.506262  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4731 23:09:54.506421  ==

 4732 23:09:54.506539  RX Vref Scan: 0

 4733 23:09:54.506651  

 4734 23:09:54.509998  RX Vref 0 -> 0, step: 1

 4735 23:09:54.510124  

 4736 23:09:54.513156  RX Delay -163 -> 252, step: 8

 4737 23:09:54.516417  iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288

 4738 23:09:54.523345  iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288

 4739 23:09:54.526472  iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288

 4740 23:09:54.529539  iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288

 4741 23:09:54.533092  iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280

 4742 23:09:54.536462  iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288

 4743 23:09:54.543003  iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296

 4744 23:09:54.546003  iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296

 4745 23:09:54.549380  iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296

 4746 23:09:54.552919  iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296

 4747 23:09:54.555990  iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296

 4748 23:09:54.563098  iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296

 4749 23:09:54.566273  iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304

 4750 23:09:54.569380  iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288

 4751 23:09:54.572546  iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288

 4752 23:09:54.579488  iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296

 4753 23:09:54.579650  ==

 4754 23:09:54.582617  Dram Type= 6, Freq= 0, CH_1, rank 1

 4755 23:09:54.585850  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4756 23:09:54.585982  ==

 4757 23:09:54.586099  DQS Delay:

 4758 23:09:54.589011  DQS0 = 0, DQS1 = 0

 4759 23:09:54.589135  DQM Delay:

 4760 23:09:54.592894  DQM0 = 48, DQM1 = 45

 4761 23:09:54.593023  DQ Delay:

 4762 23:09:54.595771  DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44

 4763 23:09:54.599289  DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48

 4764 23:09:54.602519  DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40

 4765 23:09:54.606130  DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56

 4766 23:09:54.606216  

 4767 23:09:54.606282  

 4768 23:09:54.612752  [DQSOSCAuto] RK1, (LSB)MR18= 0x681f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps

 4769 23:09:54.615955  CH1 RK1: MR19=808, MR18=681F

 4770 23:09:54.623020  CH1_RK1: MR19=0x808, MR18=0x681F, DQSOSC=390, MR23=63, INC=172, DEC=114

 4771 23:09:54.626133  [RxdqsGatingPostProcess] freq 600

 4772 23:09:54.632548  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4773 23:09:54.636282  Pre-setting of DQS Precalculation

 4774 23:09:54.639480  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4775 23:09:54.646426  sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5

 4776 23:09:54.652558  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 4777 23:09:54.652660  

 4778 23:09:54.652725  

 4779 23:09:54.655656  [Calibration Summary] 1200 Mbps

 4780 23:09:54.659121  CH 0, Rank 0

 4781 23:09:54.659207  SW Impedance     : PASS

 4782 23:09:54.662526  DUTY Scan        : NO K

 4783 23:09:54.665456  ZQ Calibration   : PASS

 4784 23:09:54.665541  Jitter Meter     : NO K

 4785 23:09:54.669311  CBT Training     : PASS

 4786 23:09:54.672406  Write leveling   : PASS

 4787 23:09:54.672493  RX DQS gating    : PASS

 4788 23:09:54.675712  RX DQ/DQS(RDDQC) : PASS

 4789 23:09:54.679120  TX DQ/DQS        : PASS

 4790 23:09:54.679208  RX DATLAT        : PASS

 4791 23:09:54.682643  RX DQ/DQS(Engine): PASS

 4792 23:09:54.682729  TX OE            : NO K

 4793 23:09:54.685814  All Pass.

 4794 23:09:54.685897  

 4795 23:09:54.685981  CH 0, Rank 1

 4796 23:09:54.689204  SW Impedance     : PASS

 4797 23:09:54.689294  DUTY Scan        : NO K

 4798 23:09:54.692508  ZQ Calibration   : PASS

 4799 23:09:54.695650  Jitter Meter     : NO K

 4800 23:09:54.695737  CBT Training     : PASS

 4801 23:09:54.698914  Write leveling   : PASS

 4802 23:09:54.702392  RX DQS gating    : PASS

 4803 23:09:54.702497  RX DQ/DQS(RDDQC) : PASS

 4804 23:09:54.705215  TX DQ/DQS        : PASS

 4805 23:09:54.709040  RX DATLAT        : PASS

 4806 23:09:54.709133  RX DQ/DQS(Engine): PASS

 4807 23:09:54.712160  TX OE            : NO K

 4808 23:09:54.712251  All Pass.

 4809 23:09:54.712368  

 4810 23:09:54.715249  CH 1, Rank 0

 4811 23:09:54.715334  SW Impedance     : PASS

 4812 23:09:54.718777  DUTY Scan        : NO K

 4813 23:09:54.721806  ZQ Calibration   : PASS

 4814 23:09:54.721897  Jitter Meter     : NO K

 4815 23:09:54.725295  CBT Training     : PASS

 4816 23:09:54.728581  Write leveling   : PASS

 4817 23:09:54.728718  RX DQS gating    : PASS

 4818 23:09:54.732139  RX DQ/DQS(RDDQC) : PASS

 4819 23:09:54.735171  TX DQ/DQS        : PASS

 4820 23:09:54.735278  RX DATLAT        : PASS

 4821 23:09:54.738428  RX DQ/DQS(Engine): PASS

 4822 23:09:54.738512  TX OE            : NO K

 4823 23:09:54.741586  All Pass.

 4824 23:09:54.741669  

 4825 23:09:54.741763  CH 1, Rank 1

 4826 23:09:54.745266  SW Impedance     : PASS

 4827 23:09:54.745352  DUTY Scan        : NO K

 4828 23:09:54.748396  ZQ Calibration   : PASS

 4829 23:09:54.752095  Jitter Meter     : NO K

 4830 23:09:54.752228  CBT Training     : PASS

 4831 23:09:54.755266  Write leveling   : PASS

 4832 23:09:54.758488  RX DQS gating    : PASS

 4833 23:09:54.758618  RX DQ/DQS(RDDQC) : PASS

 4834 23:09:54.762157  TX DQ/DQS        : PASS

 4835 23:09:54.765064  RX DATLAT        : PASS

 4836 23:09:54.765190  RX DQ/DQS(Engine): PASS

 4837 23:09:54.768657  TX OE            : NO K

 4838 23:09:54.768787  All Pass.

 4839 23:09:54.768899  

 4840 23:09:54.771683  DramC Write-DBI off

 4841 23:09:54.775325  	PER_BANK_REFRESH: Hybrid Mode

 4842 23:09:54.775455  TX_TRACKING: ON

 4843 23:09:54.785447  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1

 4844 23:09:54.788519  [FAST_K] Save calibration result to emmc

 4845 23:09:54.791604  dramc_set_vcore_voltage set vcore to 662500

 4846 23:09:54.795033  Read voltage for 933, 3

 4847 23:09:54.795127  Vio18 = 0

 4848 23:09:54.795193  Vcore = 662500

 4849 23:09:54.798669  Vdram = 0

 4850 23:09:54.798763  Vddq = 0

 4851 23:09:54.798842  Vmddr = 0

 4852 23:09:54.805257  [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0

 4853 23:09:54.808489  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 4854 23:09:54.811985  MEM_TYPE=3, freq_sel=17

 4855 23:09:54.815149  sv_algorithm_assistance_LP4_1600 

 4856 23:09:54.818537  ============ PULL DRAM RESETB DOWN ============

 4857 23:09:54.821473  ========== PULL DRAM RESETB DOWN end =========

 4858 23:09:54.828248  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4859 23:09:54.832119  =================================== 

 4860 23:09:54.832239  LPDDR4 DRAM CONFIGURATION

 4861 23:09:54.835258  =================================== 

 4862 23:09:54.838075  EX_ROW_EN[0]    = 0x0

 4863 23:09:54.841622  EX_ROW_EN[1]    = 0x0

 4864 23:09:54.841709  LP4Y_EN      = 0x0

 4865 23:09:54.844864  WORK_FSP     = 0x0

 4866 23:09:54.844970  WL           = 0x3

 4867 23:09:54.848303  RL           = 0x3

 4868 23:09:54.848453  BL           = 0x2

 4869 23:09:54.851870  RPST         = 0x0

 4870 23:09:54.851959  RD_PRE       = 0x0

 4871 23:09:54.854986  WR_PRE       = 0x1

 4872 23:09:54.855073  WR_PST       = 0x0

 4873 23:09:54.858145  DBI_WR       = 0x0

 4874 23:09:54.858250  DBI_RD       = 0x0

 4875 23:09:54.861476  OTF          = 0x1

 4876 23:09:54.864678  =================================== 

 4877 23:09:54.867882  =================================== 

 4878 23:09:54.867994  ANA top config

 4879 23:09:54.871486  =================================== 

 4880 23:09:54.875094  DLL_ASYNC_EN            =  0

 4881 23:09:54.878336  ALL_SLAVE_EN            =  1

 4882 23:09:54.881370  NEW_RANK_MODE           =  1

 4883 23:09:54.881465  DLL_IDLE_MODE           =  1

 4884 23:09:54.884525  LP45_APHY_COMB_EN       =  1

 4885 23:09:54.888237  TX_ODT_DIS              =  1

 4886 23:09:54.891336  NEW_8X_MODE             =  1

 4887 23:09:54.894624  =================================== 

 4888 23:09:54.898472  =================================== 

 4889 23:09:54.901553  data_rate                  = 1866

 4890 23:09:54.901647  CKR                        = 1

 4891 23:09:54.904512  DQ_P2S_RATIO               = 8

 4892 23:09:54.908181  =================================== 

 4893 23:09:54.911550  CA_P2S_RATIO               = 8

 4894 23:09:54.914697  DQ_CA_OPEN                 = 0

 4895 23:09:54.918218  DQ_SEMI_OPEN               = 0

 4896 23:09:54.921131  CA_SEMI_OPEN               = 0

 4897 23:09:54.921260  CA_FULL_RATE               = 0

 4898 23:09:54.924908  DQ_CKDIV4_EN               = 1

 4899 23:09:54.927700  CA_CKDIV4_EN               = 1

 4900 23:09:54.931038  CA_PREDIV_EN               = 0

 4901 23:09:54.934584  PH8_DLY                    = 0

 4902 23:09:54.937889  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 4903 23:09:54.937982  DQ_AAMCK_DIV               = 4

 4904 23:09:54.941213  CA_AAMCK_DIV               = 4

 4905 23:09:54.944489  CA_ADMCK_DIV               = 4

 4906 23:09:54.948033  DQ_TRACK_CA_EN             = 0

 4907 23:09:54.951022  CA_PICK                    = 933

 4908 23:09:54.954528  CA_MCKIO                   = 933

 4909 23:09:54.954637  MCKIO_SEMI                 = 0

 4910 23:09:54.957708  PLL_FREQ                   = 3732

 4911 23:09:54.961268  DQ_UI_PI_RATIO             = 32

 4912 23:09:54.964095  CA_UI_PI_RATIO             = 0

 4913 23:09:54.967926  =================================== 

 4914 23:09:54.971136  =================================== 

 4915 23:09:54.974284  memory_type:LPDDR4         

 4916 23:09:54.974376  GP_NUM     : 10       

 4917 23:09:54.978040  SRAM_EN    : 1       

 4918 23:09:54.981007  MD32_EN    : 0       

 4919 23:09:54.984472  =================================== 

 4920 23:09:54.984564  [ANA_INIT] >>>>>>>>>>>>>> 

 4921 23:09:54.987648  <<<<<< [CONFIGURE PHASE]: ANA_TX

 4922 23:09:54.991087  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 4923 23:09:54.994196  =================================== 

 4924 23:09:54.997481  data_rate = 1866,PCW = 0X8f00

 4925 23:09:55.001261  =================================== 

 4926 23:09:55.004335  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 4927 23:09:55.011168  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4928 23:09:55.014400  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4929 23:09:55.020670  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 4930 23:09:55.024599  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 4931 23:09:55.027653  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 4932 23:09:55.027746  [ANA_INIT] flow start 

 4933 23:09:55.030733  [ANA_INIT] PLL >>>>>>>> 

 4934 23:09:55.033912  [ANA_INIT] PLL <<<<<<<< 

 4935 23:09:55.037667  [ANA_INIT] MIDPI >>>>>>>> 

 4936 23:09:55.037801  [ANA_INIT] MIDPI <<<<<<<< 

 4937 23:09:55.040983  [ANA_INIT] DLL >>>>>>>> 

 4938 23:09:55.041112  [ANA_INIT] flow end 

 4939 23:09:55.047525  ============ LP4 DIFF to SE enter ============

 4940 23:09:55.050910  ============ LP4 DIFF to SE exit  ============

 4941 23:09:55.054050  [ANA_INIT] <<<<<<<<<<<<< 

 4942 23:09:55.057314  [Flow] Enable top DCM control >>>>> 

 4943 23:09:55.060601  [Flow] Enable top DCM control <<<<< 

 4944 23:09:55.060736  Enable DLL master slave shuffle 

 4945 23:09:55.067468  ============================================================== 

 4946 23:09:55.071087  Gating Mode config

 4947 23:09:55.074005  ============================================================== 

 4948 23:09:55.077575  Config description: 

 4949 23:09:55.087455  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 4950 23:09:55.093891  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 4951 23:09:55.097416  SELPH_MODE            0: By rank         1: By Phase 

 4952 23:09:55.103949  ============================================================== 

 4953 23:09:55.107717  GAT_TRACK_EN                 =  1

 4954 23:09:55.110880  RX_GATING_MODE               =  2

 4955 23:09:55.113951  RX_GATING_TRACK_MODE         =  2

 4956 23:09:55.117697  SELPH_MODE                   =  1

 4957 23:09:55.117839  PICG_EARLY_EN                =  1

 4958 23:09:55.120887  VALID_LAT_VALUE              =  1

 4959 23:09:55.127237  ============================================================== 

 4960 23:09:55.131053  Enter into Gating configuration >>>> 

 4961 23:09:55.134239  Exit from Gating configuration <<<< 

 4962 23:09:55.137471  Enter into  DVFS_PRE_config >>>>> 

 4963 23:09:55.147579  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 4964 23:09:55.150911  Exit from  DVFS_PRE_config <<<<< 

 4965 23:09:55.154142  Enter into PICG configuration >>>> 

 4966 23:09:55.157309  Exit from PICG configuration <<<< 

 4967 23:09:55.160524  [RX_INPUT] configuration >>>>> 

 4968 23:09:55.164152  [RX_INPUT] configuration <<<<< 

 4969 23:09:55.166986  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 4970 23:09:55.174091  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 4971 23:09:55.180489  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 4972 23:09:55.186771  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 4973 23:09:55.193901  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 4974 23:09:55.196948  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 4975 23:09:55.203470  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 4976 23:09:55.206866  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 4977 23:09:55.210447  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 4978 23:09:55.213625  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 4979 23:09:55.220469  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 4980 23:09:55.223576  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4981 23:09:55.226946  =================================== 

 4982 23:09:55.230615  LPDDR4 DRAM CONFIGURATION

 4983 23:09:55.233860  =================================== 

 4984 23:09:55.233974  EX_ROW_EN[0]    = 0x0

 4985 23:09:55.236993  EX_ROW_EN[1]    = 0x0

 4986 23:09:55.237083  LP4Y_EN      = 0x0

 4987 23:09:55.240144  WORK_FSP     = 0x0

 4988 23:09:55.240233  WL           = 0x3

 4989 23:09:55.243982  RL           = 0x3

 4990 23:09:55.244072  BL           = 0x2

 4991 23:09:55.247069  RPST         = 0x0

 4992 23:09:55.247158  RD_PRE       = 0x0

 4993 23:09:55.250283  WR_PRE       = 0x1

 4994 23:09:55.250371  WR_PST       = 0x0

 4995 23:09:55.253909  DBI_WR       = 0x0

 4996 23:09:55.254001  DBI_RD       = 0x0

 4997 23:09:55.257137  OTF          = 0x1

 4998 23:09:55.260349  =================================== 

 4999 23:09:55.263537  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 5000 23:09:55.266653  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 5001 23:09:55.273348  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5002 23:09:55.276923  =================================== 

 5003 23:09:55.279993  LPDDR4 DRAM CONFIGURATION

 5004 23:09:55.280087  =================================== 

 5005 23:09:55.283515  EX_ROW_EN[0]    = 0x10

 5006 23:09:55.286485  EX_ROW_EN[1]    = 0x0

 5007 23:09:55.286601  LP4Y_EN      = 0x0

 5008 23:09:55.289992  WORK_FSP     = 0x0

 5009 23:09:55.290081  WL           = 0x3

 5010 23:09:55.293745  RL           = 0x3

 5011 23:09:55.293835  BL           = 0x2

 5012 23:09:55.296789  RPST         = 0x0

 5013 23:09:55.296876  RD_PRE       = 0x0

 5014 23:09:55.299939  WR_PRE       = 0x1

 5015 23:09:55.300025  WR_PST       = 0x0

 5016 23:09:55.303638  DBI_WR       = 0x0

 5017 23:09:55.303726  DBI_RD       = 0x0

 5018 23:09:55.306739  OTF          = 0x1

 5019 23:09:55.310345  =================================== 

 5020 23:09:55.316733  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 5021 23:09:55.320064  nWR fixed to 30

 5022 23:09:55.323250  [ModeRegInit_LP4] CH0 RK0

 5023 23:09:55.323341  [ModeRegInit_LP4] CH0 RK1

 5024 23:09:55.326806  [ModeRegInit_LP4] CH1 RK0

 5025 23:09:55.330353  [ModeRegInit_LP4] CH1 RK1

 5026 23:09:55.330464  match AC timing 9

 5027 23:09:55.336841  dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1

 5028 23:09:55.339891  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 5029 23:09:55.343252  [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10

 5030 23:09:55.349918  [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21

 5031 23:09:55.353267  [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)

 5032 23:09:55.353367  ==

 5033 23:09:55.356750  Dram Type= 6, Freq= 0, CH_0, rank 0

 5034 23:09:55.359934  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5035 23:09:55.360025  ==

 5036 23:09:55.366585  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5037 23:09:55.373558  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 5038 23:09:55.376709  [CA 0] Center 37 (6~68) winsize 63

 5039 23:09:55.379813  [CA 1] Center 37 (6~68) winsize 63

 5040 23:09:55.383278  [CA 2] Center 34 (4~65) winsize 62

 5041 23:09:55.386866  [CA 3] Center 34 (3~65) winsize 63

 5042 23:09:55.389829  [CA 4] Center 33 (3~64) winsize 62

 5043 23:09:55.393301  [CA 5] Center 32 (2~62) winsize 61

 5044 23:09:55.393395  

 5045 23:09:55.396837  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 5046 23:09:55.396958  

 5047 23:09:55.399881  [CATrainingPosCal] consider 1 rank data

 5048 23:09:55.403035  u2DelayCellTimex100 = 270/100 ps

 5049 23:09:55.406207  CA0 delay=37 (6~68),Diff = 5 PI (31 cell)

 5050 23:09:55.409981  CA1 delay=37 (6~68),Diff = 5 PI (31 cell)

 5051 23:09:55.412830  CA2 delay=34 (4~65),Diff = 2 PI (12 cell)

 5052 23:09:55.416618  CA3 delay=34 (3~65),Diff = 2 PI (12 cell)

 5053 23:09:55.419830  CA4 delay=33 (3~64),Diff = 1 PI (6 cell)

 5054 23:09:55.422952  CA5 delay=32 (2~62),Diff = 0 PI (0 cell)

 5055 23:09:55.423043  

 5056 23:09:55.429630  CA PerBit enable=1, Macro0, CA PI delay=32

 5057 23:09:55.429735  

 5058 23:09:55.429801  [CBTSetCACLKResult] CA Dly = 32

 5059 23:09:55.433321  CS Dly: 4 (0~35)

 5060 23:09:55.433429  ==

 5061 23:09:55.436493  Dram Type= 6, Freq= 0, CH_0, rank 1

 5062 23:09:55.439638  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5063 23:09:55.439770  ==

 5064 23:09:55.446581  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5065 23:09:55.452954  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5066 23:09:55.456581  [CA 0] Center 37 (6~68) winsize 63

 5067 23:09:55.459450  [CA 1] Center 37 (7~68) winsize 62

 5068 23:09:55.463002  [CA 2] Center 34 (4~65) winsize 62

 5069 23:09:55.466381  [CA 3] Center 34 (3~65) winsize 63

 5070 23:09:55.469754  [CA 4] Center 33 (3~63) winsize 61

 5071 23:09:55.473084  [CA 5] Center 32 (2~62) winsize 61

 5072 23:09:55.473179  

 5073 23:09:55.476021  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5074 23:09:55.476130  

 5075 23:09:55.479427  [CATrainingPosCal] consider 2 rank data

 5076 23:09:55.482917  u2DelayCellTimex100 = 270/100 ps

 5077 23:09:55.486228  CA0 delay=37 (6~68),Diff = 5 PI (31 cell)

 5078 23:09:55.489800  CA1 delay=37 (7~68),Diff = 5 PI (31 cell)

 5079 23:09:55.492863  CA2 delay=34 (4~65),Diff = 2 PI (12 cell)

 5080 23:09:55.495977  CA3 delay=34 (3~65),Diff = 2 PI (12 cell)

 5081 23:09:55.499235  CA4 delay=33 (3~63),Diff = 1 PI (6 cell)

 5082 23:09:55.502811  CA5 delay=32 (2~62),Diff = 0 PI (0 cell)

 5083 23:09:55.505912  

 5084 23:09:55.509192  CA PerBit enable=1, Macro0, CA PI delay=32

 5085 23:09:55.509283  

 5086 23:09:55.513015  [CBTSetCACLKResult] CA Dly = 32

 5087 23:09:55.513102  CS Dly: 5 (0~37)

 5088 23:09:55.513169  

 5089 23:09:55.515998  ----->DramcWriteLeveling(PI) begin...

 5090 23:09:55.516085  ==

 5091 23:09:55.519147  Dram Type= 6, Freq= 0, CH_0, rank 0

 5092 23:09:55.522917  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5093 23:09:55.526143  ==

 5094 23:09:55.526239  Write leveling (Byte 0): 30 => 30

 5095 23:09:55.529172  Write leveling (Byte 1): 30 => 30

 5096 23:09:55.532730  DramcWriteLeveling(PI) end<-----

 5097 23:09:55.532814  

 5098 23:09:55.532881  ==

 5099 23:09:55.536172  Dram Type= 6, Freq= 0, CH_0, rank 0

 5100 23:09:55.542681  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5101 23:09:55.542766  ==

 5102 23:09:55.542831  [Gating] SW mode calibration

 5103 23:09:55.552520  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5104 23:09:55.556251  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5105 23:09:55.559368   0 14  0 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)

 5106 23:09:55.565846   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5107 23:09:55.569040   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5108 23:09:55.572895   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5109 23:09:55.579188   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5110 23:09:55.582344   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5111 23:09:55.586060   0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)

 5112 23:09:55.592318   0 14 28 | B1->B0 | 3434 2828 | 0 0 | (0 0) (1 0)

 5113 23:09:55.595572   0 15  0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)

 5114 23:09:55.599128   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5115 23:09:55.605554   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5116 23:09:55.609292   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5117 23:09:55.612582   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5118 23:09:55.618985   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5119 23:09:55.622336   0 15 24 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)

 5120 23:09:55.625480   0 15 28 | B1->B0 | 2929 3d3d | 0 0 | (0 0) (0 0)

 5121 23:09:55.632133   1  0  0 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)

 5122 23:09:55.635755   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5123 23:09:55.638796   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5124 23:09:55.645826   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5125 23:09:55.649154   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5126 23:09:55.652219   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5127 23:09:55.659259   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5128 23:09:55.662211   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5129 23:09:55.665922   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5130 23:09:55.672412   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5131 23:09:55.675538   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5132 23:09:55.679266   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5133 23:09:55.685634   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5134 23:09:55.688763   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5135 23:09:55.691985   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5136 23:09:55.699031   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5137 23:09:55.702144   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5138 23:09:55.705715   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5139 23:09:55.708905   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5140 23:09:55.715373   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5141 23:09:55.718995   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5142 23:09:55.722060   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5143 23:09:55.728345   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5144 23:09:55.731919   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5145 23:09:55.735458   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5146 23:09:55.738465  Total UI for P1: 0, mck2ui 16

 5147 23:09:55.742032  best dqsien dly found for B0: ( 1,  2, 28)

 5148 23:09:55.748659   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5149 23:09:55.751737  Total UI for P1: 0, mck2ui 16

 5150 23:09:55.755171  best dqsien dly found for B1: ( 1,  2, 30)

 5151 23:09:55.758327  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5152 23:09:55.761829  best DQS1 dly(MCK, UI, PI) = (1, 2, 30)

 5153 23:09:55.761958  

 5154 23:09:55.765116  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5155 23:09:55.768476  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)

 5156 23:09:55.771727  [Gating] SW calibration Done

 5157 23:09:55.771856  ==

 5158 23:09:55.775308  Dram Type= 6, Freq= 0, CH_0, rank 0

 5159 23:09:55.778250  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5160 23:09:55.778380  ==

 5161 23:09:55.782082  RX Vref Scan: 0

 5162 23:09:55.782205  

 5163 23:09:55.782320  RX Vref 0 -> 0, step: 1

 5164 23:09:55.785271  

 5165 23:09:55.785396  RX Delay -80 -> 252, step: 8

 5166 23:09:55.792121  iDelay=208, Bit 0, Center 103 (8 ~ 199) 192

 5167 23:09:55.795194  iDelay=208, Bit 1, Center 107 (16 ~ 199) 184

 5168 23:09:55.798339  iDelay=208, Bit 2, Center 99 (8 ~ 191) 184

 5169 23:09:55.802149  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5170 23:09:55.805339  iDelay=208, Bit 4, Center 107 (16 ~ 199) 184

 5171 23:09:55.808443  iDelay=208, Bit 5, Center 95 (8 ~ 183) 176

 5172 23:09:55.812201  iDelay=208, Bit 6, Center 115 (24 ~ 207) 184

 5173 23:09:55.818501  iDelay=208, Bit 7, Center 115 (24 ~ 207) 184

 5174 23:09:55.822051  iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184

 5175 23:09:55.825071  iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184

 5176 23:09:55.828226  iDelay=208, Bit 10, Center 95 (8 ~ 183) 176

 5177 23:09:55.831988  iDelay=208, Bit 11, Center 95 (8 ~ 183) 176

 5178 23:09:55.835262  iDelay=208, Bit 12, Center 99 (8 ~ 191) 184

 5179 23:09:55.841674  iDelay=208, Bit 13, Center 99 (8 ~ 191) 184

 5180 23:09:55.844843  iDelay=208, Bit 14, Center 99 (8 ~ 191) 184

 5181 23:09:55.848582  iDelay=208, Bit 15, Center 99 (8 ~ 191) 184

 5182 23:09:55.848666  ==

 5183 23:09:55.852114  Dram Type= 6, Freq= 0, CH_0, rank 0

 5184 23:09:55.855222  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5185 23:09:55.855306  ==

 5186 23:09:55.858263  DQS Delay:

 5187 23:09:55.858350  DQS0 = 0, DQS1 = 0

 5188 23:09:55.861860  DQM Delay:

 5189 23:09:55.861942  DQM0 = 105, DQM1 = 94

 5190 23:09:55.862007  DQ Delay:

 5191 23:09:55.864896  DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99

 5192 23:09:55.868599  DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115

 5193 23:09:55.871687  DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =95

 5194 23:09:55.875203  DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99

 5195 23:09:55.875286  

 5196 23:09:55.878616  

 5197 23:09:55.878714  ==

 5198 23:09:55.881466  Dram Type= 6, Freq= 0, CH_0, rank 0

 5199 23:09:55.885279  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5200 23:09:55.885411  ==

 5201 23:09:55.885529  

 5202 23:09:55.885641  

 5203 23:09:55.888455  	TX Vref Scan disable

 5204 23:09:55.888580   == TX Byte 0 ==

 5205 23:09:55.894946  Update DQ  dly =714 (2 ,6, 10)  DQ  OEN =(2 ,3)

 5206 23:09:55.898194  Update DQM dly =714 (2 ,6, 10)  DQM OEN =(2 ,3)

 5207 23:09:55.898277   == TX Byte 1 ==

 5208 23:09:55.904857  Update DQ  dly =713 (2 ,5, 41)  DQ  OEN =(2 ,2)

 5209 23:09:55.907982  Update DQM dly =713 (2 ,5, 41)  DQM OEN =(2 ,2)

 5210 23:09:55.908065  ==

 5211 23:09:55.911598  Dram Type= 6, Freq= 0, CH_0, rank 0

 5212 23:09:55.914617  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5213 23:09:55.914741  ==

 5214 23:09:55.914855  

 5215 23:09:55.914967  

 5216 23:09:55.918451  	TX Vref Scan disable

 5217 23:09:55.921608   == TX Byte 0 ==

 5218 23:09:55.924603  Update DQ  dly =713 (2 ,5, 41)  DQ  OEN =(2 ,2)

 5219 23:09:55.928126  Update DQM dly =713 (2 ,5, 41)  DQM OEN =(2 ,2)

 5220 23:09:55.931219   == TX Byte 1 ==

 5221 23:09:55.934938  Update DQ  dly =713 (2 ,5, 41)  DQ  OEN =(2 ,2)

 5222 23:09:55.938260  Update DQM dly =713 (2 ,5, 41)  DQM OEN =(2 ,2)

 5223 23:09:55.938386  

 5224 23:09:55.941376  [DATLAT]

 5225 23:09:55.941500  Freq=933, CH0 RK0

 5226 23:09:55.941616  

 5227 23:09:55.944494  DATLAT Default: 0xd

 5228 23:09:55.944622  0, 0xFFFF, sum = 0

 5229 23:09:55.948217  1, 0xFFFF, sum = 0

 5230 23:09:55.948346  2, 0xFFFF, sum = 0

 5231 23:09:55.951504  3, 0xFFFF, sum = 0

 5232 23:09:55.951599  4, 0xFFFF, sum = 0

 5233 23:09:55.954485  5, 0xFFFF, sum = 0

 5234 23:09:55.954570  6, 0xFFFF, sum = 0

 5235 23:09:55.958066  7, 0xFFFF, sum = 0

 5236 23:09:55.958149  8, 0xFFFF, sum = 0

 5237 23:09:55.961167  9, 0xFFFF, sum = 0

 5238 23:09:55.961250  10, 0x0, sum = 1

 5239 23:09:55.964601  11, 0x0, sum = 2

 5240 23:09:55.964683  12, 0x0, sum = 3

 5241 23:09:55.967958  13, 0x0, sum = 4

 5242 23:09:55.968092  best_step = 11

 5243 23:09:55.968159  

 5244 23:09:55.968258  ==

 5245 23:09:55.971197  Dram Type= 6, Freq= 0, CH_0, rank 0

 5246 23:09:55.974962  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5247 23:09:55.978186  ==

 5248 23:09:55.978302  RX Vref Scan: 1

 5249 23:09:55.978395  

 5250 23:09:55.981254  RX Vref 0 -> 0, step: 1

 5251 23:09:55.981352  

 5252 23:09:55.984664  RX Delay -53 -> 252, step: 4

 5253 23:09:55.984746  

 5254 23:09:55.988221  Set Vref, RX VrefLevel [Byte0]: 61

 5255 23:09:55.991157                           [Byte1]: 49

 5256 23:09:55.991254  

 5257 23:09:55.994791  Final RX Vref Byte 0 = 61 to rank0

 5258 23:09:55.997857  Final RX Vref Byte 1 = 49 to rank0

 5259 23:09:56.000939  Final RX Vref Byte 0 = 61 to rank1

 5260 23:09:56.004808  Final RX Vref Byte 1 = 49 to rank1==

 5261 23:09:56.007803  Dram Type= 6, Freq= 0, CH_0, rank 0

 5262 23:09:56.011258  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5263 23:09:56.011383  ==

 5264 23:09:56.014618  DQS Delay:

 5265 23:09:56.014740  DQS0 = 0, DQS1 = 0

 5266 23:09:56.014856  DQM Delay:

 5267 23:09:56.017808  DQM0 = 105, DQM1 = 95

 5268 23:09:56.017893  DQ Delay:

 5269 23:09:56.021097  DQ0 =102, DQ1 =106, DQ2 =104, DQ3 =102

 5270 23:09:56.024770  DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112

 5271 23:09:56.027686  DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =92

 5272 23:09:56.031214  DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =102

 5273 23:09:56.031297  

 5274 23:09:56.034434  

 5275 23:09:56.041412  [DQSOSCAuto] RK0, (LSB)MR18= 0x3229, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps

 5276 23:09:56.044580  CH0 RK0: MR19=505, MR18=3229

 5277 23:09:56.051043  CH0_RK0: MR19=0x505, MR18=0x3229, DQSOSC=406, MR23=63, INC=65, DEC=43

 5278 23:09:56.051155  

 5279 23:09:56.054845  ----->DramcWriteLeveling(PI) begin...

 5280 23:09:56.054951  ==

 5281 23:09:56.058127  Dram Type= 6, Freq= 0, CH_0, rank 1

 5282 23:09:56.061140  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5283 23:09:56.061218  ==

 5284 23:09:56.064707  Write leveling (Byte 0): 34 => 34

 5285 23:09:56.067900  Write leveling (Byte 1): 32 => 32

 5286 23:09:56.070985  DramcWriteLeveling(PI) end<-----

 5287 23:09:56.071099  

 5288 23:09:56.071191  ==

 5289 23:09:56.074396  Dram Type= 6, Freq= 0, CH_0, rank 1

 5290 23:09:56.077911  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5291 23:09:56.078000  ==

 5292 23:09:56.080981  [Gating] SW mode calibration

 5293 23:09:56.087312  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5294 23:09:56.094290  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5295 23:09:56.097812   0 14  0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)

 5296 23:09:56.100982   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5297 23:09:56.107296   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5298 23:09:56.111121   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5299 23:09:56.114235   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5300 23:09:56.121053   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5301 23:09:56.124564   0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)

 5302 23:09:56.127615   0 14 28 | B1->B0 | 2727 2525 | 0 0 | (1 0) (1 0)

 5303 23:09:56.134495   0 15  0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)

 5304 23:09:56.137449   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5305 23:09:56.141130   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5306 23:09:56.147277   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5307 23:09:56.150686   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5308 23:09:56.154295   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5309 23:09:56.157856   0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 5310 23:09:56.164426   0 15 28 | B1->B0 | 3939 3333 | 1 0 | (0 0) (0 0)

 5311 23:09:56.167551   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5312 23:09:56.170951   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5313 23:09:56.177324   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5314 23:09:56.180899   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5315 23:09:56.183867   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5316 23:09:56.190860   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5317 23:09:56.194067   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5318 23:09:56.197099   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5319 23:09:56.203844   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5320 23:09:56.207073   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5321 23:09:56.210675   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5322 23:09:56.217052   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5323 23:09:56.220170   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5324 23:09:56.223937   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5325 23:09:56.230521   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5326 23:09:56.233528   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5327 23:09:56.237200   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5328 23:09:56.243344   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5329 23:09:56.247090   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5330 23:09:56.250145   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5331 23:09:56.257162   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5332 23:09:56.260315   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5333 23:09:56.263472   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5334 23:09:56.269995   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5335 23:09:56.270119  Total UI for P1: 0, mck2ui 16

 5336 23:09:56.276758  best dqsien dly found for B0: ( 1,  2, 24)

 5337 23:09:56.280197   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5338 23:09:56.283668  Total UI for P1: 0, mck2ui 16

 5339 23:09:56.286803  best dqsien dly found for B1: ( 1,  2, 26)

 5340 23:09:56.290152  best DQS0 dly(MCK, UI, PI) = (1, 2, 24)

 5341 23:09:56.293352  best DQS1 dly(MCK, UI, PI) = (1, 2, 26)

 5342 23:09:56.293430  

 5343 23:09:56.296971  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5344 23:09:56.300327  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5345 23:09:56.303285  [Gating] SW calibration Done

 5346 23:09:56.303381  ==

 5347 23:09:56.307029  Dram Type= 6, Freq= 0, CH_0, rank 1

 5348 23:09:56.310108  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5349 23:09:56.310187  ==

 5350 23:09:56.313460  RX Vref Scan: 0

 5351 23:09:56.313562  

 5352 23:09:56.316631  RX Vref 0 -> 0, step: 1

 5353 23:09:56.316741  

 5354 23:09:56.316837  RX Delay -80 -> 252, step: 8

 5355 23:09:56.323677  iDelay=208, Bit 0, Center 103 (8 ~ 199) 192

 5356 23:09:56.326828  iDelay=208, Bit 1, Center 107 (16 ~ 199) 184

 5357 23:09:56.329985  iDelay=208, Bit 2, Center 99 (8 ~ 191) 184

 5358 23:09:56.333701  iDelay=208, Bit 3, Center 103 (8 ~ 199) 192

 5359 23:09:56.336573  iDelay=208, Bit 4, Center 107 (16 ~ 199) 184

 5360 23:09:56.343349  iDelay=208, Bit 5, Center 99 (8 ~ 191) 184

 5361 23:09:56.347004  iDelay=208, Bit 6, Center 107 (16 ~ 199) 184

 5362 23:09:56.350183  iDelay=208, Bit 7, Center 115 (24 ~ 207) 184

 5363 23:09:56.353453  iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184

 5364 23:09:56.356522  iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184

 5365 23:09:56.360227  iDelay=208, Bit 10, Center 95 (8 ~ 183) 176

 5366 23:09:56.366559  iDelay=208, Bit 11, Center 87 (0 ~ 175) 176

 5367 23:09:56.369801  iDelay=208, Bit 12, Center 99 (8 ~ 191) 184

 5368 23:09:56.373476  iDelay=208, Bit 13, Center 99 (8 ~ 191) 184

 5369 23:09:56.376700  iDelay=208, Bit 14, Center 103 (16 ~ 191) 176

 5370 23:09:56.379845  iDelay=208, Bit 15, Center 99 (8 ~ 191) 184

 5371 23:09:56.379960  ==

 5372 23:09:56.383799  Dram Type= 6, Freq= 0, CH_0, rank 1

 5373 23:09:56.389873  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5374 23:09:56.389972  ==

 5375 23:09:56.390042  DQS Delay:

 5376 23:09:56.393368  DQS0 = 0, DQS1 = 0

 5377 23:09:56.393448  DQM Delay:

 5378 23:09:56.393513  DQM0 = 105, DQM1 = 93

 5379 23:09:56.396397  DQ Delay:

 5380 23:09:56.400202  DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =103

 5381 23:09:56.403625  DQ4 =107, DQ5 =99, DQ6 =107, DQ7 =115

 5382 23:09:56.406387  DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87

 5383 23:09:56.410111  DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99

 5384 23:09:56.410195  

 5385 23:09:56.410261  

 5386 23:09:56.410321  ==

 5387 23:09:56.413105  Dram Type= 6, Freq= 0, CH_0, rank 1

 5388 23:09:56.416455  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5389 23:09:56.416542  ==

 5390 23:09:56.416618  

 5391 23:09:56.416679  

 5392 23:09:56.419680  	TX Vref Scan disable

 5393 23:09:56.422944   == TX Byte 0 ==

 5394 23:09:56.426409  Update DQ  dly =718 (2 ,6, 14)  DQ  OEN =(2 ,3)

 5395 23:09:56.429644  Update DQM dly =718 (2 ,6, 14)  DQM OEN =(2 ,3)

 5396 23:09:56.433086   == TX Byte 1 ==

 5397 23:09:56.436135  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5398 23:09:56.439696  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5399 23:09:56.439802  ==

 5400 23:09:56.442986  Dram Type= 6, Freq= 0, CH_0, rank 1

 5401 23:09:56.449634  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5402 23:09:56.449763  ==

 5403 23:09:56.449833  

 5404 23:09:56.449895  

 5405 23:09:56.449972  	TX Vref Scan disable

 5406 23:09:56.453603   == TX Byte 0 ==

 5407 23:09:56.456657  Update DQ  dly =718 (2 ,6, 14)  DQ  OEN =(2 ,3)

 5408 23:09:56.463617  Update DQM dly =718 (2 ,6, 14)  DQM OEN =(2 ,3)

 5409 23:09:56.463742   == TX Byte 1 ==

 5410 23:09:56.466819  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5411 23:09:56.473161  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5412 23:09:56.473280  

 5413 23:09:56.473357  [DATLAT]

 5414 23:09:56.473419  Freq=933, CH0 RK1

 5415 23:09:56.473478  

 5416 23:09:56.477024  DATLAT Default: 0xb

 5417 23:09:56.477203  0, 0xFFFF, sum = 0

 5418 23:09:56.480207  1, 0xFFFF, sum = 0

 5419 23:09:56.480372  2, 0xFFFF, sum = 0

 5420 23:09:56.483318  3, 0xFFFF, sum = 0

 5421 23:09:56.486479  4, 0xFFFF, sum = 0

 5422 23:09:56.486632  5, 0xFFFF, sum = 0

 5423 23:09:56.490128  6, 0xFFFF, sum = 0

 5424 23:09:56.490258  7, 0xFFFF, sum = 0

 5425 23:09:56.493304  8, 0xFFFF, sum = 0

 5426 23:09:56.493401  9, 0xFFFF, sum = 0

 5427 23:09:56.496253  10, 0x0, sum = 1

 5428 23:09:56.496362  11, 0x0, sum = 2

 5429 23:09:56.499886  12, 0x0, sum = 3

 5430 23:09:56.500006  13, 0x0, sum = 4

 5431 23:09:56.500102  best_step = 11

 5432 23:09:56.500190  

 5433 23:09:56.503160  ==

 5434 23:09:56.506814  Dram Type= 6, Freq= 0, CH_0, rank 1

 5435 23:09:56.509888  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5436 23:09:56.509986  ==

 5437 23:09:56.510054  RX Vref Scan: 0

 5438 23:09:56.510116  

 5439 23:09:56.513081  RX Vref 0 -> 0, step: 1

 5440 23:09:56.513206  

 5441 23:09:56.516977  RX Delay -53 -> 252, step: 4

 5442 23:09:56.520104  iDelay=199, Bit 0, Center 104 (15 ~ 194) 180

 5443 23:09:56.526835  iDelay=199, Bit 1, Center 106 (23 ~ 190) 168

 5444 23:09:56.529772  iDelay=199, Bit 2, Center 102 (15 ~ 190) 176

 5445 23:09:56.533601  iDelay=199, Bit 3, Center 102 (15 ~ 190) 176

 5446 23:09:56.536911  iDelay=199, Bit 4, Center 106 (19 ~ 194) 176

 5447 23:09:56.539947  iDelay=199, Bit 5, Center 98 (11 ~ 186) 176

 5448 23:09:56.546734  iDelay=199, Bit 6, Center 110 (23 ~ 198) 176

 5449 23:09:56.550001  iDelay=199, Bit 7, Center 112 (27 ~ 198) 172

 5450 23:09:56.553150  iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172

 5451 23:09:56.556643  iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168

 5452 23:09:56.560139  iDelay=199, Bit 10, Center 94 (11 ~ 178) 168

 5453 23:09:56.563309  iDelay=199, Bit 11, Center 86 (3 ~ 170) 168

 5454 23:09:56.569663  iDelay=199, Bit 12, Center 100 (19 ~ 182) 164

 5455 23:09:56.572882  iDelay=199, Bit 13, Center 98 (15 ~ 182) 168

 5456 23:09:56.576485  iDelay=199, Bit 14, Center 102 (19 ~ 186) 168

 5457 23:09:56.579628  iDelay=199, Bit 15, Center 102 (19 ~ 186) 168

 5458 23:09:56.579743  ==

 5459 23:09:56.582979  Dram Type= 6, Freq= 0, CH_0, rank 1

 5460 23:09:56.589926  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5461 23:09:56.590017  ==

 5462 23:09:56.590085  DQS Delay:

 5463 23:09:56.592782  DQS0 = 0, DQS1 = 0

 5464 23:09:56.592866  DQM Delay:

 5465 23:09:56.592933  DQM0 = 105, DQM1 = 93

 5466 23:09:56.596641  DQ Delay:

 5467 23:09:56.599768  DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102

 5468 23:09:56.603258  DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112

 5469 23:09:56.606432  DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =86

 5470 23:09:56.609464  DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102

 5471 23:09:56.609548  

 5472 23:09:56.609614  

 5473 23:09:56.619085  [DQSOSCAuto] RK1, (LSB)MR18= 0x2901, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps

 5474 23:09:56.619177  CH0 RK1: MR19=505, MR18=2901

 5475 23:09:56.625987  CH0_RK1: MR19=0x505, MR18=0x2901, DQSOSC=408, MR23=63, INC=65, DEC=43

 5476 23:09:56.629320  [RxdqsGatingPostProcess] freq 933

 5477 23:09:56.636060  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5478 23:09:56.639068  best DQS0 dly(2T, 0.5T) = (0, 10)

 5479 23:09:56.642131  best DQS1 dly(2T, 0.5T) = (0, 10)

 5480 23:09:56.645816  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5481 23:09:56.649063  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5482 23:09:56.649140  best DQS0 dly(2T, 0.5T) = (0, 10)

 5483 23:09:56.652936  best DQS1 dly(2T, 0.5T) = (0, 10)

 5484 23:09:56.655675  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5485 23:09:56.659367  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5486 23:09:56.662578  Pre-setting of DQS Precalculation

 5487 23:09:56.669317  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5488 23:09:56.669408  ==

 5489 23:09:56.672536  Dram Type= 6, Freq= 0, CH_1, rank 0

 5490 23:09:56.675586  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5491 23:09:56.675671  ==

 5492 23:09:56.682448  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5493 23:09:56.688679  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5494 23:09:56.692045  [CA 0] Center 36 (6~67) winsize 62

 5495 23:09:56.695321  [CA 1] Center 37 (6~68) winsize 63

 5496 23:09:56.698856  [CA 2] Center 34 (4~65) winsize 62

 5497 23:09:56.702247  [CA 3] Center 34 (4~65) winsize 62

 5498 23:09:56.705313  [CA 4] Center 34 (4~64) winsize 61

 5499 23:09:56.705405  [CA 5] Center 33 (3~64) winsize 62

 5500 23:09:56.708905  

 5501 23:09:56.711888  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5502 23:09:56.711974  

 5503 23:09:56.715658  [CATrainingPosCal] consider 1 rank data

 5504 23:09:56.718728  u2DelayCellTimex100 = 270/100 ps

 5505 23:09:56.721848  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5506 23:09:56.725723  CA1 delay=37 (6~68),Diff = 4 PI (24 cell)

 5507 23:09:56.728949  CA2 delay=34 (4~65),Diff = 1 PI (6 cell)

 5508 23:09:56.732136  CA3 delay=34 (4~65),Diff = 1 PI (6 cell)

 5509 23:09:56.735339  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5510 23:09:56.738908  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5511 23:09:56.738989  

 5512 23:09:56.741953  CA PerBit enable=1, Macro0, CA PI delay=33

 5513 23:09:56.742029  

 5514 23:09:56.745591  [CBTSetCACLKResult] CA Dly = 33

 5515 23:09:56.748589  CS Dly: 6 (0~37)

 5516 23:09:56.748678  ==

 5517 23:09:56.752196  Dram Type= 6, Freq= 0, CH_1, rank 1

 5518 23:09:56.755462  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5519 23:09:56.755548  ==

 5520 23:09:56.762171  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5521 23:09:56.768923  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5522 23:09:56.771966  [CA 0] Center 36 (6~67) winsize 62

 5523 23:09:56.775202  [CA 1] Center 37 (7~68) winsize 62

 5524 23:09:56.779029  [CA 2] Center 35 (5~66) winsize 62

 5525 23:09:56.782237  [CA 3] Center 34 (4~65) winsize 62

 5526 23:09:56.785279  [CA 4] Center 34 (4~65) winsize 62

 5527 23:09:56.788562  [CA 5] Center 33 (3~64) winsize 62

 5528 23:09:56.788649  

 5529 23:09:56.792169  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5530 23:09:56.792280  

 5531 23:09:56.795292  [CATrainingPosCal] consider 2 rank data

 5532 23:09:56.799129  u2DelayCellTimex100 = 270/100 ps

 5533 23:09:56.802317  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5534 23:09:56.805311  CA1 delay=37 (7~68),Diff = 4 PI (24 cell)

 5535 23:09:56.808922  CA2 delay=35 (5~65),Diff = 2 PI (12 cell)

 5536 23:09:56.811983  CA3 delay=34 (4~65),Diff = 1 PI (6 cell)

 5537 23:09:56.815483  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5538 23:09:56.818701  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5539 23:09:56.818786  

 5540 23:09:56.821838  CA PerBit enable=1, Macro0, CA PI delay=33

 5541 23:09:56.821912  

 5542 23:09:56.825452  [CBTSetCACLKResult] CA Dly = 33

 5543 23:09:56.828678  CS Dly: 7 (0~40)

 5544 23:09:56.828782  

 5545 23:09:56.831865  ----->DramcWriteLeveling(PI) begin...

 5546 23:09:56.831951  ==

 5547 23:09:56.835350  Dram Type= 6, Freq= 0, CH_1, rank 0

 5548 23:09:56.838516  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5549 23:09:56.838606  ==

 5550 23:09:56.841851  Write leveling (Byte 0): 30 => 30

 5551 23:09:56.845445  Write leveling (Byte 1): 26 => 26

 5552 23:09:56.848701  DramcWriteLeveling(PI) end<-----

 5553 23:09:56.848815  

 5554 23:09:56.848904  ==

 5555 23:09:56.851676  Dram Type= 6, Freq= 0, CH_1, rank 0

 5556 23:09:56.855299  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5557 23:09:56.855386  ==

 5558 23:09:56.858377  [Gating] SW mode calibration

 5559 23:09:56.865277  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5560 23:09:56.871833  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5561 23:09:56.874970   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5562 23:09:56.881807   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5563 23:09:56.884979   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5564 23:09:56.888805   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5565 23:09:56.895060   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5566 23:09:56.898619   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5567 23:09:56.901923   0 14 24 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (1 0)

 5568 23:09:56.908211   0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)

 5569 23:09:56.911438   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5570 23:09:56.915283   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5571 23:09:56.921512   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5572 23:09:56.924636   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5573 23:09:56.928121   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5574 23:09:56.931672   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5575 23:09:56.937889   0 15 24 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)

 5576 23:09:56.941606   0 15 28 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)

 5577 23:09:56.944538   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5578 23:09:56.951749   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5579 23:09:56.954901   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5580 23:09:56.957865   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5581 23:09:56.964959   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5582 23:09:56.967949   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5583 23:09:56.971404   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5584 23:09:56.977766   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5585 23:09:56.981144   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5586 23:09:56.984427   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5587 23:09:56.991303   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5588 23:09:56.994421   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5589 23:09:56.997607   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5590 23:09:57.004533   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5591 23:09:57.007696   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5592 23:09:57.011528   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5593 23:09:57.017828   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5594 23:09:57.020905   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5595 23:09:57.024821   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5596 23:09:57.031029   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5597 23:09:57.034475   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5598 23:09:57.037632   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5599 23:09:57.043931   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5600 23:09:57.047639   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5601 23:09:57.051115   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5602 23:09:57.054404  Total UI for P1: 0, mck2ui 16

 5603 23:09:57.057610  best dqsien dly found for B0: ( 1,  2, 26)

 5604 23:09:57.060743  Total UI for P1: 0, mck2ui 16

 5605 23:09:57.064259  best dqsien dly found for B1: ( 1,  2, 26)

 5606 23:09:57.067174  best DQS0 dly(MCK, UI, PI) = (1, 2, 26)

 5607 23:09:57.070673  best DQS1 dly(MCK, UI, PI) = (1, 2, 26)

 5608 23:09:57.070782  

 5609 23:09:57.077655  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5610 23:09:57.080458  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5611 23:09:57.080570  [Gating] SW calibration Done

 5612 23:09:57.083856  ==

 5613 23:09:57.087132  Dram Type= 6, Freq= 0, CH_1, rank 0

 5614 23:09:57.090448  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5615 23:09:57.090555  ==

 5616 23:09:57.090646  RX Vref Scan: 0

 5617 23:09:57.090734  

 5618 23:09:57.094185  RX Vref 0 -> 0, step: 1

 5619 23:09:57.094290  

 5620 23:09:57.097591  RX Delay -80 -> 252, step: 8

 5621 23:09:57.100758  iDelay=208, Bit 0, Center 107 (16 ~ 199) 184

 5622 23:09:57.103947  iDelay=208, Bit 1, Center 95 (0 ~ 191) 192

 5623 23:09:57.107467  iDelay=208, Bit 2, Center 91 (0 ~ 183) 184

 5624 23:09:57.113825  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5625 23:09:57.116973  iDelay=208, Bit 4, Center 99 (8 ~ 191) 184

 5626 23:09:57.120844  iDelay=208, Bit 5, Center 111 (16 ~ 207) 192

 5627 23:09:57.124006  iDelay=208, Bit 6, Center 111 (16 ~ 207) 192

 5628 23:09:57.127211  iDelay=208, Bit 7, Center 103 (8 ~ 199) 192

 5629 23:09:57.130343  iDelay=208, Bit 8, Center 87 (0 ~ 175) 176

 5630 23:09:57.137234  iDelay=208, Bit 9, Center 87 (0 ~ 175) 176

 5631 23:09:57.140276  iDelay=208, Bit 10, Center 99 (8 ~ 191) 184

 5632 23:09:57.143875  iDelay=208, Bit 11, Center 91 (0 ~ 183) 184

 5633 23:09:57.147090  iDelay=208, Bit 12, Center 107 (16 ~ 199) 184

 5634 23:09:57.150932  iDelay=208, Bit 13, Center 103 (16 ~ 191) 176

 5635 23:09:57.154123  iDelay=208, Bit 14, Center 103 (16 ~ 191) 176

 5636 23:09:57.160332  iDelay=208, Bit 15, Center 107 (16 ~ 199) 184

 5637 23:09:57.160453  ==

 5638 23:09:57.163840  Dram Type= 6, Freq= 0, CH_1, rank 0

 5639 23:09:57.166973  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5640 23:09:57.167083  ==

 5641 23:09:57.167176  DQS Delay:

 5642 23:09:57.170481  DQS0 = 0, DQS1 = 0

 5643 23:09:57.170589  DQM Delay:

 5644 23:09:57.173901  DQM0 = 102, DQM1 = 98

 5645 23:09:57.174008  DQ Delay:

 5646 23:09:57.177229  DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99

 5647 23:09:57.180589  DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103

 5648 23:09:57.183956  DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91

 5649 23:09:57.186938  DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107

 5650 23:09:57.187048  

 5651 23:09:57.187141  

 5652 23:09:57.187229  ==

 5653 23:09:57.190104  Dram Type= 6, Freq= 0, CH_1, rank 0

 5654 23:09:57.197113  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5655 23:09:57.197229  ==

 5656 23:09:57.197322  

 5657 23:09:57.197410  

 5658 23:09:57.197498  	TX Vref Scan disable

 5659 23:09:57.200711   == TX Byte 0 ==

 5660 23:09:57.203914  Update DQ  dly =713 (2 ,5, 41)  DQ  OEN =(2 ,2)

 5661 23:09:57.207425  Update DQM dly =713 (2 ,5, 41)  DQM OEN =(2 ,2)

 5662 23:09:57.210690   == TX Byte 1 ==

 5663 23:09:57.213877  Update DQ  dly =708 (2 ,5, 36)  DQ  OEN =(2 ,2)

 5664 23:09:57.220253  Update DQM dly =708 (2 ,5, 36)  DQM OEN =(2 ,2)

 5665 23:09:57.220381  ==

 5666 23:09:57.224028  Dram Type= 6, Freq= 0, CH_1, rank 0

 5667 23:09:57.227395  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5668 23:09:57.227505  ==

 5669 23:09:57.227597  

 5670 23:09:57.227686  

 5671 23:09:57.230523  	TX Vref Scan disable

 5672 23:09:57.230626   == TX Byte 0 ==

 5673 23:09:57.237402  Update DQ  dly =713 (2 ,5, 41)  DQ  OEN =(2 ,2)

 5674 23:09:57.240535  Update DQM dly =713 (2 ,5, 41)  DQM OEN =(2 ,2)

 5675 23:09:57.240721   == TX Byte 1 ==

 5676 23:09:57.247124  Update DQ  dly =708 (2 ,5, 36)  DQ  OEN =(2 ,2)

 5677 23:09:57.250190  Update DQM dly =708 (2 ,5, 36)  DQM OEN =(2 ,2)

 5678 23:09:57.250300  

 5679 23:09:57.250394  [DATLAT]

 5680 23:09:57.253401  Freq=933, CH1 RK0

 5681 23:09:57.253508  

 5682 23:09:57.253600  DATLAT Default: 0xd

 5683 23:09:57.257261  0, 0xFFFF, sum = 0

 5684 23:09:57.257373  1, 0xFFFF, sum = 0

 5685 23:09:57.260517  2, 0xFFFF, sum = 0

 5686 23:09:57.260631  3, 0xFFFF, sum = 0

 5687 23:09:57.263669  4, 0xFFFF, sum = 0

 5688 23:09:57.266886  5, 0xFFFF, sum = 0

 5689 23:09:57.266998  6, 0xFFFF, sum = 0

 5690 23:09:57.270022  7, 0xFFFF, sum = 0

 5691 23:09:57.270137  8, 0xFFFF, sum = 0

 5692 23:09:57.273623  9, 0xFFFF, sum = 0

 5693 23:09:57.273734  10, 0x0, sum = 1

 5694 23:09:57.276986  11, 0x0, sum = 2

 5695 23:09:57.277099  12, 0x0, sum = 3

 5696 23:09:57.277200  13, 0x0, sum = 4

 5697 23:09:57.280425  best_step = 11

 5698 23:09:57.280535  

 5699 23:09:57.280632  ==

 5700 23:09:57.283905  Dram Type= 6, Freq= 0, CH_1, rank 0

 5701 23:09:57.286698  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5702 23:09:57.286812  ==

 5703 23:09:57.290043  RX Vref Scan: 1

 5704 23:09:57.290153  

 5705 23:09:57.290250  RX Vref 0 -> 0, step: 1

 5706 23:09:57.293713  

 5707 23:09:57.293825  RX Delay -45 -> 252, step: 4

 5708 23:09:57.293923  

 5709 23:09:57.296751  Set Vref, RX VrefLevel [Byte0]: 56

 5710 23:09:57.299891                           [Byte1]: 54

 5711 23:09:57.304821  

 5712 23:09:57.304943  Final RX Vref Byte 0 = 56 to rank0

 5713 23:09:57.307872  Final RX Vref Byte 1 = 54 to rank0

 5714 23:09:57.311007  Final RX Vref Byte 0 = 56 to rank1

 5715 23:09:57.314669  Final RX Vref Byte 1 = 54 to rank1==

 5716 23:09:57.317520  Dram Type= 6, Freq= 0, CH_1, rank 0

 5717 23:09:57.324276  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5718 23:09:57.324407  ==

 5719 23:09:57.324508  DQS Delay:

 5720 23:09:57.324604  DQS0 = 0, DQS1 = 0

 5721 23:09:57.327814  DQM Delay:

 5722 23:09:57.327926  DQM0 = 103, DQM1 = 101

 5723 23:09:57.331220  DQ Delay:

 5724 23:09:57.334167  DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102

 5725 23:09:57.337591  DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =104

 5726 23:09:57.341106  DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =94

 5727 23:09:57.344194  DQ12 =106, DQ13 =106, DQ14 =110, DQ15 =106

 5728 23:09:57.344313  

 5729 23:09:57.344411  

 5730 23:09:57.350881  [DQSOSCAuto] RK0, (LSB)MR18= 0x1a32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps

 5731 23:09:57.354377  CH1 RK0: MR19=505, MR18=1A32

 5732 23:09:57.360688  CH1_RK0: MR19=0x505, MR18=0x1A32, DQSOSC=406, MR23=63, INC=65, DEC=43

 5733 23:09:57.360814  

 5734 23:09:57.364486  ----->DramcWriteLeveling(PI) begin...

 5735 23:09:57.364600  ==

 5736 23:09:57.367625  Dram Type= 6, Freq= 0, CH_1, rank 1

 5737 23:09:57.370766  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5738 23:09:57.370878  ==

 5739 23:09:57.373937  Write leveling (Byte 0): 25 => 25

 5740 23:09:57.377738  Write leveling (Byte 1): 28 => 28

 5741 23:09:57.380637  DramcWriteLeveling(PI) end<-----

 5742 23:09:57.380751  

 5743 23:09:57.380849  ==

 5744 23:09:57.384256  Dram Type= 6, Freq= 0, CH_1, rank 1

 5745 23:09:57.390969  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5746 23:09:57.391089  ==

 5747 23:09:57.391192  [Gating] SW mode calibration

 5748 23:09:57.401017  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5749 23:09:57.404367  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5750 23:09:57.407205   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5751 23:09:57.414186   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5752 23:09:57.417917   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5753 23:09:57.420740   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5754 23:09:57.427483   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5755 23:09:57.430522   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5756 23:09:57.434024   0 14 24 | B1->B0 | 2a2a 3232 | 0 0 | (0 0) (0 1)

 5757 23:09:57.441014   0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 5758 23:09:57.444003   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5759 23:09:57.447302   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5760 23:09:57.453888   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5761 23:09:57.457630   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5762 23:09:57.460467   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5763 23:09:57.467427   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5764 23:09:57.470445   0 15 24 | B1->B0 | 3434 2c2c | 0 0 | (0 0) (0 0)

 5765 23:09:57.474294   0 15 28 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)

 5766 23:09:57.480569   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5767 23:09:57.484257   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5768 23:09:57.487227   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5769 23:09:57.493924   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5770 23:09:57.497574   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5771 23:09:57.500799   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5772 23:09:57.507060   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5773 23:09:57.510380   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 5774 23:09:57.514274   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 5775 23:09:57.517152   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5776 23:09:57.523715   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5777 23:09:57.527336   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5778 23:09:57.530836   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5779 23:09:57.537118   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5780 23:09:57.540934   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5781 23:09:57.543873   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5782 23:09:57.550856   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5783 23:09:57.553957   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5784 23:09:57.557265   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5785 23:09:57.563990   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5786 23:09:57.567522   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5787 23:09:57.570565   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5788 23:09:57.577086   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 5789 23:09:57.580884   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5790 23:09:57.584045  Total UI for P1: 0, mck2ui 16

 5791 23:09:57.587234  best dqsien dly found for B0: ( 1,  2, 26)

 5792 23:09:57.590953  Total UI for P1: 0, mck2ui 16

 5793 23:09:57.593933  best dqsien dly found for B1: ( 1,  2, 24)

 5794 23:09:57.596969  best DQS0 dly(MCK, UI, PI) = (1, 2, 26)

 5795 23:09:57.600650  best DQS1 dly(MCK, UI, PI) = (1, 2, 24)

 5796 23:09:57.600769  

 5797 23:09:57.603863  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5798 23:09:57.607047  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5799 23:09:57.610965  [Gating] SW calibration Done

 5800 23:09:57.611079  ==

 5801 23:09:57.614018  Dram Type= 6, Freq= 0, CH_1, rank 1

 5802 23:09:57.617044  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5803 23:09:57.617157  ==

 5804 23:09:57.620563  RX Vref Scan: 0

 5805 23:09:57.620676  

 5806 23:09:57.623880  RX Vref 0 -> 0, step: 1

 5807 23:09:57.623992  

 5808 23:09:57.624090  RX Delay -80 -> 252, step: 8

 5809 23:09:57.630712  iDelay=208, Bit 0, Center 107 (16 ~ 199) 184

 5810 23:09:57.634250  iDelay=208, Bit 1, Center 99 (8 ~ 191) 184

 5811 23:09:57.637078  iDelay=208, Bit 2, Center 95 (8 ~ 183) 176

 5812 23:09:57.640529  iDelay=208, Bit 3, Center 95 (8 ~ 183) 176

 5813 23:09:57.643941  iDelay=208, Bit 4, Center 95 (8 ~ 183) 176

 5814 23:09:57.647178  iDelay=208, Bit 5, Center 115 (24 ~ 207) 184

 5815 23:09:57.653960  iDelay=208, Bit 6, Center 115 (24 ~ 207) 184

 5816 23:09:57.657178  iDelay=208, Bit 7, Center 99 (8 ~ 191) 184

 5817 23:09:57.661053  iDelay=208, Bit 8, Center 87 (0 ~ 175) 176

 5818 23:09:57.663958  iDelay=208, Bit 9, Center 91 (0 ~ 183) 184

 5819 23:09:57.666965  iDelay=208, Bit 10, Center 99 (8 ~ 191) 184

 5820 23:09:57.670373  iDelay=208, Bit 11, Center 91 (0 ~ 183) 184

 5821 23:09:57.676947  iDelay=208, Bit 12, Center 107 (16 ~ 199) 184

 5822 23:09:57.680606  iDelay=208, Bit 13, Center 107 (16 ~ 199) 184

 5823 23:09:57.683848  iDelay=208, Bit 14, Center 103 (16 ~ 191) 176

 5824 23:09:57.687010  iDelay=208, Bit 15, Center 107 (16 ~ 199) 184

 5825 23:09:57.687137  ==

 5826 23:09:57.690318  Dram Type= 6, Freq= 0, CH_1, rank 1

 5827 23:09:57.696928  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5828 23:09:57.697022  ==

 5829 23:09:57.697090  DQS Delay:

 5830 23:09:57.697152  DQS0 = 0, DQS1 = 0

 5831 23:09:57.700565  DQM Delay:

 5832 23:09:57.700652  DQM0 = 102, DQM1 = 99

 5833 23:09:57.703554  DQ Delay:

 5834 23:09:57.707247  DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =95

 5835 23:09:57.710392  DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99

 5836 23:09:57.713614  DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91

 5837 23:09:57.716866  DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107

 5838 23:09:57.716952  

 5839 23:09:57.717019  

 5840 23:09:57.717080  ==

 5841 23:09:57.720583  Dram Type= 6, Freq= 0, CH_1, rank 1

 5842 23:09:57.723821  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5843 23:09:57.723908  ==

 5844 23:09:57.723975  

 5845 23:09:57.724036  

 5846 23:09:57.726841  	TX Vref Scan disable

 5847 23:09:57.730394   == TX Byte 0 ==

 5848 23:09:57.733678  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5849 23:09:57.737421  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5850 23:09:57.740149   == TX Byte 1 ==

 5851 23:09:57.743682  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5852 23:09:57.746886  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5853 23:09:57.747000  ==

 5854 23:09:57.750522  Dram Type= 6, Freq= 0, CH_1, rank 1

 5855 23:09:57.753370  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5856 23:09:57.756634  ==

 5857 23:09:57.756746  

 5858 23:09:57.756840  

 5859 23:09:57.756931  	TX Vref Scan disable

 5860 23:09:57.760275   == TX Byte 0 ==

 5861 23:09:57.763804  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5862 23:09:57.770636  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5863 23:09:57.770754   == TX Byte 1 ==

 5864 23:09:57.773837  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5865 23:09:57.780316  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5866 23:09:57.780433  

 5867 23:09:57.780529  [DATLAT]

 5868 23:09:57.780620  Freq=933, CH1 RK1

 5869 23:09:57.780712  

 5870 23:09:57.783599  DATLAT Default: 0xb

 5871 23:09:57.783705  0, 0xFFFF, sum = 0

 5872 23:09:57.786925  1, 0xFFFF, sum = 0

 5873 23:09:57.787035  2, 0xFFFF, sum = 0

 5874 23:09:57.790183  3, 0xFFFF, sum = 0

 5875 23:09:57.793470  4, 0xFFFF, sum = 0

 5876 23:09:57.793585  5, 0xFFFF, sum = 0

 5877 23:09:57.797026  6, 0xFFFF, sum = 0

 5878 23:09:57.797139  7, 0xFFFF, sum = 0

 5879 23:09:57.800590  8, 0xFFFF, sum = 0

 5880 23:09:57.800706  9, 0xFFFF, sum = 0

 5881 23:09:57.803623  10, 0x0, sum = 1

 5882 23:09:57.803736  11, 0x0, sum = 2

 5883 23:09:57.806641  12, 0x0, sum = 3

 5884 23:09:57.806756  13, 0x0, sum = 4

 5885 23:09:57.806856  best_step = 11

 5886 23:09:57.806952  

 5887 23:09:57.810262  ==

 5888 23:09:57.813410  Dram Type= 6, Freq= 0, CH_1, rank 1

 5889 23:09:57.817206  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5890 23:09:57.817321  ==

 5891 23:09:57.817419  RX Vref Scan: 0

 5892 23:09:57.817514  

 5893 23:09:57.820370  RX Vref 0 -> 0, step: 1

 5894 23:09:57.820483  

 5895 23:09:57.823499  RX Delay -45 -> 252, step: 4

 5896 23:09:57.826663  iDelay=203, Bit 0, Center 110 (27 ~ 194) 168

 5897 23:09:57.833446  iDelay=203, Bit 1, Center 102 (19 ~ 186) 168

 5898 23:09:57.836570  iDelay=203, Bit 2, Center 94 (11 ~ 178) 168

 5899 23:09:57.840059  iDelay=203, Bit 3, Center 98 (19 ~ 178) 160

 5900 23:09:57.843388  iDelay=203, Bit 4, Center 100 (19 ~ 182) 164

 5901 23:09:57.846873  iDelay=203, Bit 5, Center 116 (31 ~ 202) 172

 5902 23:09:57.853653  iDelay=203, Bit 6, Center 114 (31 ~ 198) 168

 5903 23:09:57.856611  iDelay=203, Bit 7, Center 104 (19 ~ 190) 172

 5904 23:09:57.859780  iDelay=203, Bit 8, Center 90 (7 ~ 174) 168

 5905 23:09:57.863509  iDelay=203, Bit 9, Center 92 (7 ~ 178) 172

 5906 23:09:57.866425  iDelay=203, Bit 10, Center 100 (15 ~ 186) 172

 5907 23:09:57.869797  iDelay=203, Bit 11, Center 94 (11 ~ 178) 168

 5908 23:09:57.876313  iDelay=203, Bit 12, Center 110 (23 ~ 198) 176

 5909 23:09:57.879629  iDelay=203, Bit 13, Center 106 (23 ~ 190) 168

 5910 23:09:57.883323  iDelay=203, Bit 14, Center 106 (23 ~ 190) 168

 5911 23:09:57.886489  iDelay=203, Bit 15, Center 108 (23 ~ 194) 172

 5912 23:09:57.889543  ==

 5913 23:09:57.889656  Dram Type= 6, Freq= 0, CH_1, rank 1

 5914 23:09:57.896572  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5915 23:09:57.896689  ==

 5916 23:09:57.896788  DQS Delay:

 5917 23:09:57.899366  DQS0 = 0, DQS1 = 0

 5918 23:09:57.899477  DQM Delay:

 5919 23:09:57.902953  DQM0 = 104, DQM1 = 100

 5920 23:09:57.903064  DQ Delay:

 5921 23:09:57.906086  DQ0 =110, DQ1 =102, DQ2 =94, DQ3 =98

 5922 23:09:57.909569  DQ4 =100, DQ5 =116, DQ6 =114, DQ7 =104

 5923 23:09:57.912827  DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =94

 5924 23:09:57.916454  DQ12 =110, DQ13 =106, DQ14 =106, DQ15 =108

 5925 23:09:57.916570  

 5926 23:09:57.916669  

 5927 23:09:57.925809  [DQSOSCAuto] RK1, (LSB)MR18= 0x2bfe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps

 5928 23:09:57.925946  CH1 RK1: MR19=504, MR18=2BFE

 5929 23:09:57.932917  CH1_RK1: MR19=0x504, MR18=0x2BFE, DQSOSC=408, MR23=63, INC=65, DEC=43

 5930 23:09:57.935994  [RxdqsGatingPostProcess] freq 933

 5931 23:09:57.942433  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5932 23:09:57.946074  best DQS0 dly(2T, 0.5T) = (0, 10)

 5933 23:09:57.949063  best DQS1 dly(2T, 0.5T) = (0, 10)

 5934 23:09:57.952657  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5935 23:09:57.956260  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5936 23:09:57.959246  best DQS0 dly(2T, 0.5T) = (0, 10)

 5937 23:09:57.959333  best DQS1 dly(2T, 0.5T) = (0, 10)

 5938 23:09:57.963017  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5939 23:09:57.966028  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5940 23:09:57.969347  Pre-setting of DQS Precalculation

 5941 23:09:57.976076  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5942 23:09:57.982431  sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3

 5943 23:09:57.989239  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 5944 23:09:57.989368  

 5945 23:09:57.989468  

 5946 23:09:57.992268  [Calibration Summary] 1866 Mbps

 5947 23:09:57.992388  CH 0, Rank 0

 5948 23:09:57.995863  SW Impedance     : PASS

 5949 23:09:57.999364  DUTY Scan        : NO K

 5950 23:09:57.999476  ZQ Calibration   : PASS

 5951 23:09:58.002492  Jitter Meter     : NO K

 5952 23:09:58.005635  CBT Training     : PASS

 5953 23:09:58.005746  Write leveling   : PASS

 5954 23:09:58.009265  RX DQS gating    : PASS

 5955 23:09:58.012683  RX DQ/DQS(RDDQC) : PASS

 5956 23:09:58.012796  TX DQ/DQS        : PASS

 5957 23:09:58.015908  RX DATLAT        : PASS

 5958 23:09:58.019023  RX DQ/DQS(Engine): PASS

 5959 23:09:58.019140  TX OE            : NO K

 5960 23:09:58.022328  All Pass.

 5961 23:09:58.022446  

 5962 23:09:58.022544  CH 0, Rank 1

 5963 23:09:58.025726  SW Impedance     : PASS

 5964 23:09:58.025839  DUTY Scan        : NO K

 5965 23:09:58.028706  ZQ Calibration   : PASS

 5966 23:09:58.032359  Jitter Meter     : NO K

 5967 23:09:58.032477  CBT Training     : PASS

 5968 23:09:58.035587  Write leveling   : PASS

 5969 23:09:58.038721  RX DQS gating    : PASS

 5970 23:09:58.038838  RX DQ/DQS(RDDQC) : PASS

 5971 23:09:58.042568  TX DQ/DQS        : PASS

 5972 23:09:58.042682  RX DATLAT        : PASS

 5973 23:09:58.045695  RX DQ/DQS(Engine): PASS

 5974 23:09:58.048853  TX OE            : NO K

 5975 23:09:58.048970  All Pass.

 5976 23:09:58.049069  

 5977 23:09:58.049164  CH 1, Rank 0

 5978 23:09:58.052536  SW Impedance     : PASS

 5979 23:09:58.055427  DUTY Scan        : NO K

 5980 23:09:58.055541  ZQ Calibration   : PASS

 5981 23:09:58.058552  Jitter Meter     : NO K

 5982 23:09:58.062349  CBT Training     : PASS

 5983 23:09:58.062468  Write leveling   : PASS

 5984 23:09:58.065385  RX DQS gating    : PASS

 5985 23:09:58.069030  RX DQ/DQS(RDDQC) : PASS

 5986 23:09:58.069145  TX DQ/DQS        : PASS

 5987 23:09:58.072429  RX DATLAT        : PASS

 5988 23:09:58.075812  RX DQ/DQS(Engine): PASS

 5989 23:09:58.075902  TX OE            : NO K

 5990 23:09:58.076009  All Pass.

 5991 23:09:58.079052  

 5992 23:09:58.079135  CH 1, Rank 1

 5993 23:09:58.082095  SW Impedance     : PASS

 5994 23:09:58.082185  DUTY Scan        : NO K

 5995 23:09:58.085588  ZQ Calibration   : PASS

 5996 23:09:58.085678  Jitter Meter     : NO K

 5997 23:09:58.089067  CBT Training     : PASS

 5998 23:09:58.092600  Write leveling   : PASS

 5999 23:09:58.092707  RX DQS gating    : PASS

 6000 23:09:58.095787  RX DQ/DQS(RDDQC) : PASS

 6001 23:09:58.099000  TX DQ/DQS        : PASS

 6002 23:09:58.099119  RX DATLAT        : PASS

 6003 23:09:58.102567  RX DQ/DQS(Engine): PASS

 6004 23:09:58.105475  TX OE            : NO K

 6005 23:09:58.105565  All Pass.

 6006 23:09:58.105631  

 6007 23:09:58.108623  DramC Write-DBI off

 6008 23:09:58.108715  	PER_BANK_REFRESH: Hybrid Mode

 6009 23:09:58.112258  TX_TRACKING: ON

 6010 23:09:58.118683  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0

 6011 23:09:58.125642  [FAST_K] Save calibration result to emmc

 6012 23:09:58.128600  dramc_set_vcore_voltage set vcore to 650000

 6013 23:09:58.128696  Read voltage for 400, 6

 6014 23:09:58.132061  Vio18 = 0

 6015 23:09:58.132147  Vcore = 650000

 6016 23:09:58.132214  Vdram = 0

 6017 23:09:58.135505  Vddq = 0

 6018 23:09:58.135625  Vmddr = 0

 6019 23:09:58.138409  [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0

 6020 23:09:58.145248  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 6021 23:09:58.148701  MEM_TYPE=3, freq_sel=20

 6022 23:09:58.151705  sv_algorithm_assistance_LP4_800 

 6023 23:09:58.154949  ============ PULL DRAM RESETB DOWN ============

 6024 23:09:58.158551  ========== PULL DRAM RESETB DOWN end =========

 6025 23:09:58.165138  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6026 23:09:58.168274  =================================== 

 6027 23:09:58.168375  LPDDR4 DRAM CONFIGURATION

 6028 23:09:58.171500  =================================== 

 6029 23:09:58.175293  EX_ROW_EN[0]    = 0x0

 6030 23:09:58.175417  EX_ROW_EN[1]    = 0x0

 6031 23:09:58.178388  LP4Y_EN      = 0x0

 6032 23:09:58.178479  WORK_FSP     = 0x0

 6033 23:09:58.181414  WL           = 0x2

 6034 23:09:58.184751  RL           = 0x2

 6035 23:09:58.184841  BL           = 0x2

 6036 23:09:58.187996  RPST         = 0x0

 6037 23:09:58.188083  RD_PRE       = 0x0

 6038 23:09:58.191710  WR_PRE       = 0x1

 6039 23:09:58.191800  WR_PST       = 0x0

 6040 23:09:58.194619  DBI_WR       = 0x0

 6041 23:09:58.194706  DBI_RD       = 0x0

 6042 23:09:58.197991  OTF          = 0x1

 6043 23:09:58.201283  =================================== 

 6044 23:09:58.204823  =================================== 

 6045 23:09:58.204922  ANA top config

 6046 23:09:58.207946  =================================== 

 6047 23:09:58.211583  DLL_ASYNC_EN            =  0

 6048 23:09:58.214688  ALL_SLAVE_EN            =  1

 6049 23:09:58.214778  NEW_RANK_MODE           =  1

 6050 23:09:58.217820  DLL_IDLE_MODE           =  1

 6051 23:09:58.221648  LP45_APHY_COMB_EN       =  1

 6052 23:09:58.224871  TX_ODT_DIS              =  1

 6053 23:09:58.228134  NEW_8X_MODE             =  1

 6054 23:09:58.231239  =================================== 

 6055 23:09:58.231332  =================================== 

 6056 23:09:58.234993  data_rate                  =  800

 6057 23:09:58.238163  CKR                        = 1

 6058 23:09:58.241366  DQ_P2S_RATIO               = 4

 6059 23:09:58.244511  =================================== 

 6060 23:09:58.248080  CA_P2S_RATIO               = 4

 6061 23:09:58.251239  DQ_CA_OPEN                 = 0

 6062 23:09:58.254700  DQ_SEMI_OPEN               = 1

 6063 23:09:58.254816  CA_SEMI_OPEN               = 1

 6064 23:09:58.258228  CA_FULL_RATE               = 0

 6065 23:09:58.261196  DQ_CKDIV4_EN               = 0

 6066 23:09:58.264727  CA_CKDIV4_EN               = 1

 6067 23:09:58.267960  CA_PREDIV_EN               = 0

 6068 23:09:58.268054  PH8_DLY                    = 0

 6069 23:09:58.271561  SEMI_OPEN_CA_PICK_MCK_RATIO= 4

 6070 23:09:58.274718  DQ_AAMCK_DIV               = 0

 6071 23:09:58.277798  CA_AAMCK_DIV               = 0

 6072 23:09:58.281417  CA_ADMCK_DIV               = 4

 6073 23:09:58.284567  DQ_TRACK_CA_EN             = 0

 6074 23:09:58.287786  CA_PICK                    = 800

 6075 23:09:58.287912  CA_MCKIO                   = 400

 6076 23:09:58.290984  MCKIO_SEMI                 = 400

 6077 23:09:58.294677  PLL_FREQ                   = 3016

 6078 23:09:58.298004  DQ_UI_PI_RATIO             = 32

 6079 23:09:58.301488  CA_UI_PI_RATIO             = 32

 6080 23:09:58.304607  =================================== 

 6081 23:09:58.307591  =================================== 

 6082 23:09:58.310833  memory_type:LPDDR4         

 6083 23:09:58.310968  GP_NUM     : 10       

 6084 23:09:58.314183  SRAM_EN    : 1       

 6085 23:09:58.314310  MD32_EN    : 0       

 6086 23:09:58.317548  =================================== 

 6087 23:09:58.320875  [ANA_INIT] >>>>>>>>>>>>>> 

 6088 23:09:58.324677  <<<<<< [CONFIGURE PHASE]: ANA_TX

 6089 23:09:58.328004  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 6090 23:09:58.331029  =================================== 

 6091 23:09:58.334154  data_rate = 800,PCW = 0X7400

 6092 23:09:58.337961  =================================== 

 6093 23:09:58.341071  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 6094 23:09:58.347382  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6095 23:09:58.357438  WARN: tr->DQ_AAMCK_DIV=  0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6096 23:09:58.360797  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 6097 23:09:58.364497  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 6098 23:09:58.367505  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 6099 23:09:58.370921  [ANA_INIT] flow start 

 6100 23:09:58.374393  [ANA_INIT] PLL >>>>>>>> 

 6101 23:09:58.374531  [ANA_INIT] PLL <<<<<<<< 

 6102 23:09:58.377352  [ANA_INIT] MIDPI >>>>>>>> 

 6103 23:09:58.380892  [ANA_INIT] MIDPI <<<<<<<< 

 6104 23:09:58.384098  [ANA_INIT] DLL >>>>>>>> 

 6105 23:09:58.384188  [ANA_INIT] flow end 

 6106 23:09:58.387409  ============ LP4 DIFF to SE enter ============

 6107 23:09:58.394143  ============ LP4 DIFF to SE exit  ============

 6108 23:09:58.394255  [ANA_INIT] <<<<<<<<<<<<< 

 6109 23:09:58.397904  [Flow] Enable top DCM control >>>>> 

 6110 23:09:58.401014  [Flow] Enable top DCM control <<<<< 

 6111 23:09:58.404258  Enable DLL master slave shuffle 

 6112 23:09:58.411007  ============================================================== 

 6113 23:09:58.411108  Gating Mode config

 6114 23:09:58.417279  ============================================================== 

 6115 23:09:58.420940  Config description: 

 6116 23:09:58.428072  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 6117 23:09:58.434064  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 6118 23:09:58.440893  SELPH_MODE            0: By rank         1: By Phase 

 6119 23:09:58.447348  ============================================================== 

 6120 23:09:58.447452  GAT_TRACK_EN                 =  0

 6121 23:09:58.450530  RX_GATING_MODE               =  2

 6122 23:09:58.454325  RX_GATING_TRACK_MODE         =  2

 6123 23:09:58.457284  SELPH_MODE                   =  1

 6124 23:09:58.461080  PICG_EARLY_EN                =  1

 6125 23:09:58.464268  VALID_LAT_VALUE              =  1

 6126 23:09:58.470670  ============================================================== 

 6127 23:09:58.473842  Enter into Gating configuration >>>> 

 6128 23:09:58.477504  Exit from Gating configuration <<<< 

 6129 23:09:58.480533  Enter into  DVFS_PRE_config >>>>> 

 6130 23:09:58.490622  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 6131 23:09:58.493963  Exit from  DVFS_PRE_config <<<<< 

 6132 23:09:58.497342  Enter into PICG configuration >>>> 

 6133 23:09:58.500755  Exit from PICG configuration <<<< 

 6134 23:09:58.504100  [RX_INPUT] configuration >>>>> 

 6135 23:09:58.504186  [RX_INPUT] configuration <<<<< 

 6136 23:09:58.510692  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 6137 23:09:58.517704  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 6138 23:09:58.520912  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 6139 23:09:58.527284  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 6140 23:09:58.533940  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 6141 23:09:58.540304  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 6142 23:09:58.543679  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 6143 23:09:58.547340  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 6144 23:09:58.553755  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 6145 23:09:58.557020  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 6146 23:09:58.560200  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 6147 23:09:58.566862  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6148 23:09:58.570116  =================================== 

 6149 23:09:58.570213  LPDDR4 DRAM CONFIGURATION

 6150 23:09:58.573781  =================================== 

 6151 23:09:58.576991  EX_ROW_EN[0]    = 0x0

 6152 23:09:58.577079  EX_ROW_EN[1]    = 0x0

 6153 23:09:58.580201  LP4Y_EN      = 0x0

 6154 23:09:58.580316  WORK_FSP     = 0x0

 6155 23:09:58.583941  WL           = 0x2

 6156 23:09:58.584051  RL           = 0x2

 6157 23:09:58.587024  BL           = 0x2

 6158 23:09:58.590374  RPST         = 0x0

 6159 23:09:58.590470  RD_PRE       = 0x0

 6160 23:09:58.593887  WR_PRE       = 0x1

 6161 23:09:58.593999  WR_PST       = 0x0

 6162 23:09:58.597091  DBI_WR       = 0x0

 6163 23:09:58.597176  DBI_RD       = 0x0

 6164 23:09:58.600622  OTF          = 0x1

 6165 23:09:58.603583  =================================== 

 6166 23:09:58.607280  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 6167 23:09:58.610362  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 6168 23:09:58.613772  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6169 23:09:58.617104  =================================== 

 6170 23:09:58.620226  LPDDR4 DRAM CONFIGURATION

 6171 23:09:58.623468  =================================== 

 6172 23:09:58.627213  EX_ROW_EN[0]    = 0x10

 6173 23:09:58.627335  EX_ROW_EN[1]    = 0x0

 6174 23:09:58.630393  LP4Y_EN      = 0x0

 6175 23:09:58.630496  WORK_FSP     = 0x0

 6176 23:09:58.633525  WL           = 0x2

 6177 23:09:58.633609  RL           = 0x2

 6178 23:09:58.636706  BL           = 0x2

 6179 23:09:58.636788  RPST         = 0x0

 6180 23:09:58.640525  RD_PRE       = 0x0

 6181 23:09:58.640635  WR_PRE       = 0x1

 6182 23:09:58.643704  WR_PST       = 0x0

 6183 23:09:58.646841  DBI_WR       = 0x0

 6184 23:09:58.646954  DBI_RD       = 0x0

 6185 23:09:58.649984  OTF          = 0x1

 6186 23:09:58.653747  =================================== 

 6187 23:09:58.656703  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 6188 23:09:58.661807  nWR fixed to 30

 6189 23:09:58.665005  [ModeRegInit_LP4] CH0 RK0

 6190 23:09:58.665117  [ModeRegInit_LP4] CH0 RK1

 6191 23:09:58.668481  [ModeRegInit_LP4] CH1 RK0

 6192 23:09:58.671714  [ModeRegInit_LP4] CH1 RK1

 6193 23:09:58.671827  match AC timing 19

 6194 23:09:58.678758  dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1

 6195 23:09:58.681854  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 6196 23:09:58.685042  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 6197 23:09:58.691592  [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17

 6198 23:09:58.695247  [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)

 6199 23:09:58.695332  ==

 6200 23:09:58.698743  Dram Type= 6, Freq= 0, CH_0, rank 0

 6201 23:09:58.701674  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6202 23:09:58.701761  ==

 6203 23:09:58.708305  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6204 23:09:58.715239  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 6205 23:09:58.718431  [CA 0] Center 36 (8~64) winsize 57

 6206 23:09:58.721843  [CA 1] Center 36 (8~64) winsize 57

 6207 23:09:58.725213  [CA 2] Center 36 (8~64) winsize 57

 6208 23:09:58.728273  [CA 3] Center 36 (8~64) winsize 57

 6209 23:09:58.728392  [CA 4] Center 36 (8~64) winsize 57

 6210 23:09:58.731900  [CA 5] Center 36 (8~64) winsize 57

 6211 23:09:58.731979  

 6212 23:09:58.738313  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 6213 23:09:58.738403  

 6214 23:09:58.741451  [CATrainingPosCal] consider 1 rank data

 6215 23:09:58.745224  u2DelayCellTimex100 = 270/100 ps

 6216 23:09:58.748402  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6217 23:09:58.751470  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6218 23:09:58.755241  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6219 23:09:58.758463  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6220 23:09:58.761675  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6221 23:09:58.764818  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6222 23:09:58.764902  

 6223 23:09:58.768266  CA PerBit enable=1, Macro0, CA PI delay=36

 6224 23:09:58.768361  

 6225 23:09:58.771859  [CBTSetCACLKResult] CA Dly = 36

 6226 23:09:58.774900  CS Dly: 1 (0~32)

 6227 23:09:58.774983  ==

 6228 23:09:58.778447  Dram Type= 6, Freq= 0, CH_0, rank 1

 6229 23:09:58.781506  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6230 23:09:58.781581  ==

 6231 23:09:58.788341  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6232 23:09:58.791799  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6233 23:09:58.794900  [CA 0] Center 36 (8~64) winsize 57

 6234 23:09:58.798288  [CA 1] Center 36 (8~64) winsize 57

 6235 23:09:58.801451  [CA 2] Center 36 (8~64) winsize 57

 6236 23:09:58.805105  [CA 3] Center 36 (8~64) winsize 57

 6237 23:09:58.808266  [CA 4] Center 36 (8~64) winsize 57

 6238 23:09:58.811338  [CA 5] Center 36 (8~64) winsize 57

 6239 23:09:58.811414  

 6240 23:09:58.814787  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6241 23:09:58.814866  

 6242 23:09:58.817884  [CATrainingPosCal] consider 2 rank data

 6243 23:09:58.821670  u2DelayCellTimex100 = 270/100 ps

 6244 23:09:58.824818  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6245 23:09:58.828559  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6246 23:09:58.831381  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6247 23:09:58.838117  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6248 23:09:58.841188  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6249 23:09:58.844991  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6250 23:09:58.845109  

 6251 23:09:58.848124  CA PerBit enable=1, Macro0, CA PI delay=36

 6252 23:09:58.848229  

 6253 23:09:58.851270  [CBTSetCACLKResult] CA Dly = 36

 6254 23:09:58.851384  CS Dly: 1 (0~32)

 6255 23:09:58.851477  

 6256 23:09:58.854451  ----->DramcWriteLeveling(PI) begin...

 6257 23:09:58.854556  ==

 6258 23:09:58.858143  Dram Type= 6, Freq= 0, CH_0, rank 0

 6259 23:09:58.864397  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6260 23:09:58.864511  ==

 6261 23:09:58.868120  Write leveling (Byte 0): 40 => 8

 6262 23:09:58.871348  Write leveling (Byte 1): 40 => 8

 6263 23:09:58.871426  DramcWriteLeveling(PI) end<-----

 6264 23:09:58.874383  

 6265 23:09:58.874461  ==

 6266 23:09:58.877838  Dram Type= 6, Freq= 0, CH_0, rank 0

 6267 23:09:58.881402  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6268 23:09:58.881510  ==

 6269 23:09:58.884416  [Gating] SW mode calibration

 6270 23:09:58.891255  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6271 23:09:58.894516  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6272 23:09:58.901137   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6273 23:09:58.904655   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6274 23:09:58.907569   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6275 23:09:58.914401   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6276 23:09:58.917560   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6277 23:09:58.921184   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6278 23:09:58.927547   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6279 23:09:58.930863   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6280 23:09:58.934462   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6281 23:09:58.937250  Total UI for P1: 0, mck2ui 16

 6282 23:09:58.941042  best dqsien dly found for B0: ( 0, 14, 24)

 6283 23:09:58.944139  Total UI for P1: 0, mck2ui 16

 6284 23:09:58.947353  best dqsien dly found for B1: ( 0, 14, 24)

 6285 23:09:58.950829  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6286 23:09:58.953790  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6287 23:09:58.953906  

 6288 23:09:58.960575  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6289 23:09:58.964304  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6290 23:09:58.967488  [Gating] SW calibration Done

 6291 23:09:58.967590  ==

 6292 23:09:58.970638  Dram Type= 6, Freq= 0, CH_0, rank 0

 6293 23:09:58.973778  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6294 23:09:58.973857  ==

 6295 23:09:58.973921  RX Vref Scan: 0

 6296 23:09:58.973986  

 6297 23:09:58.977511  RX Vref 0 -> 0, step: 1

 6298 23:09:58.977586  

 6299 23:09:58.980609  RX Delay -410 -> 252, step: 16

 6300 23:09:58.984025  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6301 23:09:58.990608  iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480

 6302 23:09:58.993711  iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480

 6303 23:09:58.997508  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6304 23:09:59.000645  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6305 23:09:59.006968  iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480

 6306 23:09:59.010647  iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464

 6307 23:09:59.013592  iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464

 6308 23:09:59.017432  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6309 23:09:59.020405  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6310 23:09:59.027534  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6311 23:09:59.030734  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6312 23:09:59.033923  iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464

 6313 23:09:59.040245  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6314 23:09:59.043840  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6315 23:09:59.047377  iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464

 6316 23:09:59.047460  ==

 6317 23:09:59.050275  Dram Type= 6, Freq= 0, CH_0, rank 0

 6318 23:09:59.053848  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6319 23:09:59.053957  ==

 6320 23:09:59.056802  DQS Delay:

 6321 23:09:59.056907  DQS0 = 27, DQS1 = 35

 6322 23:09:59.060086  DQM Delay:

 6323 23:09:59.060192  DQM0 = 11, DQM1 = 11

 6324 23:09:59.063718  DQ Delay:

 6325 23:09:59.063831  DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8

 6326 23:09:59.066716  DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24

 6327 23:09:59.070011  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6328 23:09:59.073695  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16

 6329 23:09:59.073773  

 6330 23:09:59.073842  

 6331 23:09:59.073907  ==

 6332 23:09:59.076912  Dram Type= 6, Freq= 0, CH_0, rank 0

 6333 23:09:59.083341  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6334 23:09:59.083433  ==

 6335 23:09:59.083508  

 6336 23:09:59.083574  

 6337 23:09:59.083665  	TX Vref Scan disable

 6338 23:09:59.086938   == TX Byte 0 ==

 6339 23:09:59.089900  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6340 23:09:59.093227  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6341 23:09:59.096833   == TX Byte 1 ==

 6342 23:09:59.099960  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6343 23:09:59.103169  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6344 23:09:59.106988  ==

 6345 23:09:59.107086  Dram Type= 6, Freq= 0, CH_0, rank 0

 6346 23:09:59.113272  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6347 23:09:59.113372  ==

 6348 23:09:59.113450  

 6349 23:09:59.113509  

 6350 23:09:59.116314  	TX Vref Scan disable

 6351 23:09:59.116385   == TX Byte 0 ==

 6352 23:09:59.119886  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6353 23:09:59.126810  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6354 23:09:59.126920   == TX Byte 1 ==

 6355 23:09:59.129974  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6356 23:09:59.133130  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6357 23:09:59.136357  

 6358 23:09:59.136447  [DATLAT]

 6359 23:09:59.136516  Freq=400, CH0 RK0

 6360 23:09:59.136576  

 6361 23:09:59.140215  DATLAT Default: 0xf

 6362 23:09:59.140320  0, 0xFFFF, sum = 0

 6363 23:09:59.143345  1, 0xFFFF, sum = 0

 6364 23:09:59.143421  2, 0xFFFF, sum = 0

 6365 23:09:59.146592  3, 0xFFFF, sum = 0

 6366 23:09:59.146692  4, 0xFFFF, sum = 0

 6367 23:09:59.149575  5, 0xFFFF, sum = 0

 6368 23:09:59.153126  6, 0xFFFF, sum = 0

 6369 23:09:59.153234  7, 0xFFFF, sum = 0

 6370 23:09:59.156364  8, 0xFFFF, sum = 0

 6371 23:09:59.156437  9, 0xFFFF, sum = 0

 6372 23:09:59.160195  10, 0xFFFF, sum = 0

 6373 23:09:59.160305  11, 0xFFFF, sum = 0

 6374 23:09:59.163450  12, 0xFFFF, sum = 0

 6375 23:09:59.163547  13, 0x0, sum = 1

 6376 23:09:59.166623  14, 0x0, sum = 2

 6377 23:09:59.166694  15, 0x0, sum = 3

 6378 23:09:59.169745  16, 0x0, sum = 4

 6379 23:09:59.169857  best_step = 14

 6380 23:09:59.169948  

 6381 23:09:59.170037  ==

 6382 23:09:59.173413  Dram Type= 6, Freq= 0, CH_0, rank 0

 6383 23:09:59.176498  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6384 23:09:59.176609  ==

 6385 23:09:59.179886  RX Vref Scan: 1

 6386 23:09:59.179989  

 6387 23:09:59.183200  RX Vref 0 -> 0, step: 1

 6388 23:09:59.183276  

 6389 23:09:59.183339  RX Delay -311 -> 252, step: 8

 6390 23:09:59.183401  

 6391 23:09:59.186486  Set Vref, RX VrefLevel [Byte0]: 61

 6392 23:09:59.189871                           [Byte1]: 49

 6393 23:09:59.195111  

 6394 23:09:59.195228  Final RX Vref Byte 0 = 61 to rank0

 6395 23:09:59.198325  Final RX Vref Byte 1 = 49 to rank0

 6396 23:09:59.201645  Final RX Vref Byte 0 = 61 to rank1

 6397 23:09:59.204901  Final RX Vref Byte 1 = 49 to rank1==

 6398 23:09:59.208347  Dram Type= 6, Freq= 0, CH_0, rank 0

 6399 23:09:59.215183  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6400 23:09:59.215327  ==

 6401 23:09:59.215443  DQS Delay:

 6402 23:09:59.218337  DQS0 = 24, DQS1 = 36

 6403 23:09:59.218460  DQM Delay:

 6404 23:09:59.218571  DQM0 = 7, DQM1 = 12

 6405 23:09:59.221335  DQ Delay:

 6406 23:09:59.224840  DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4

 6407 23:09:59.224926  DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16

 6408 23:09:59.228574  DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4

 6409 23:09:59.231515  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20

 6410 23:09:59.231644  

 6411 23:09:59.231763  

 6412 23:09:59.241443  [DQSOSCAuto] RK0, (LSB)MR18= 0xd2bf, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 383 ps

 6413 23:09:59.245217  CH0 RK0: MR19=C0C, MR18=D2BF

 6414 23:09:59.251704  CH0_RK0: MR19=0xC0C, MR18=0xD2BF, DQSOSC=383, MR23=63, INC=402, DEC=268

 6415 23:09:59.251846  ==

 6416 23:09:59.254716  Dram Type= 6, Freq= 0, CH_0, rank 1

 6417 23:09:59.258143  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6418 23:09:59.258250  ==

 6419 23:09:59.261867  [Gating] SW mode calibration

 6420 23:09:59.268371  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6421 23:09:59.271527  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6422 23:09:59.278479   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6423 23:09:59.281594   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6424 23:09:59.284899   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6425 23:09:59.291358   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6426 23:09:59.295144   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6427 23:09:59.298369   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6428 23:09:59.305140   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6429 23:09:59.307922   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6430 23:09:59.311488   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6431 23:09:59.314409  Total UI for P1: 0, mck2ui 16

 6432 23:09:59.317989  best dqsien dly found for B0: ( 0, 14, 24)

 6433 23:09:59.321558  Total UI for P1: 0, mck2ui 16

 6434 23:09:59.324475  best dqsien dly found for B1: ( 0, 14, 24)

 6435 23:09:59.327947  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6436 23:09:59.331514  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6437 23:09:59.331639  

 6438 23:09:59.337814  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6439 23:09:59.341065  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6440 23:09:59.344473  [Gating] SW calibration Done

 6441 23:09:59.344600  ==

 6442 23:09:59.347918  Dram Type= 6, Freq= 0, CH_0, rank 1

 6443 23:09:59.351743  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6444 23:09:59.351872  ==

 6445 23:09:59.351988  RX Vref Scan: 0

 6446 23:09:59.352099  

 6447 23:09:59.354230  RX Vref 0 -> 0, step: 1

 6448 23:09:59.354354  

 6449 23:09:59.357910  RX Delay -410 -> 252, step: 16

 6450 23:09:59.360786  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6451 23:09:59.367531  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6452 23:09:59.371405  iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464

 6453 23:09:59.374552  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6454 23:09:59.377598  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6455 23:09:59.384022  iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464

 6456 23:09:59.387777  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6457 23:09:59.390934  iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464

 6458 23:09:59.394051  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6459 23:09:59.400664  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6460 23:09:59.404510  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6461 23:09:59.407639  iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464

 6462 23:09:59.411020  iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464

 6463 23:09:59.417589  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6464 23:09:59.420593  iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448

 6465 23:09:59.423873  iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464

 6466 23:09:59.423954  ==

 6467 23:09:59.427563  Dram Type= 6, Freq= 0, CH_0, rank 1

 6468 23:09:59.430788  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6469 23:09:59.433926  ==

 6470 23:09:59.434003  DQS Delay:

 6471 23:09:59.434066  DQS0 = 19, DQS1 = 35

 6472 23:09:59.437516  DQM Delay:

 6473 23:09:59.437595  DQM0 = 3, DQM1 = 11

 6474 23:09:59.440639  DQ Delay:

 6475 23:09:59.440711  DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0

 6476 23:09:59.443691  DQ4 =0, DQ5 =0, DQ6 =8, DQ7 =16

 6477 23:09:59.447062  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0

 6478 23:09:59.450243  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16

 6479 23:09:59.450322  

 6480 23:09:59.450389  

 6481 23:09:59.450452  ==

 6482 23:09:59.453536  Dram Type= 6, Freq= 0, CH_0, rank 1

 6483 23:09:59.460364  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6484 23:09:59.460443  ==

 6485 23:09:59.460506  

 6486 23:09:59.460566  

 6487 23:09:59.460623  	TX Vref Scan disable

 6488 23:09:59.463794   == TX Byte 0 ==

 6489 23:09:59.467337  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6490 23:09:59.470432  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6491 23:09:59.473851   == TX Byte 1 ==

 6492 23:09:59.477007  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6493 23:09:59.480426  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6494 23:09:59.483696  ==

 6495 23:09:59.483823  Dram Type= 6, Freq= 0, CH_0, rank 1

 6496 23:09:59.490621  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6497 23:09:59.490744  ==

 6498 23:09:59.490858  

 6499 23:09:59.490969  

 6500 23:09:59.493553  	TX Vref Scan disable

 6501 23:09:59.493675   == TX Byte 0 ==

 6502 23:09:59.497153  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6503 23:09:59.500444  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6504 23:09:59.503865   == TX Byte 1 ==

 6505 23:09:59.507147  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6506 23:09:59.510309  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6507 23:09:59.510431  

 6508 23:09:59.513476  [DATLAT]

 6509 23:09:59.513604  Freq=400, CH0 RK1

 6510 23:09:59.513720  

 6511 23:09:59.517002  DATLAT Default: 0xe

 6512 23:09:59.517123  0, 0xFFFF, sum = 0

 6513 23:09:59.519959  1, 0xFFFF, sum = 0

 6514 23:09:59.520082  2, 0xFFFF, sum = 0

 6515 23:09:59.523591  3, 0xFFFF, sum = 0

 6516 23:09:59.523723  4, 0xFFFF, sum = 0

 6517 23:09:59.527098  5, 0xFFFF, sum = 0

 6518 23:09:59.527225  6, 0xFFFF, sum = 0

 6519 23:09:59.530338  7, 0xFFFF, sum = 0

 6520 23:09:59.533445  8, 0xFFFF, sum = 0

 6521 23:09:59.533571  9, 0xFFFF, sum = 0

 6522 23:09:59.536507  10, 0xFFFF, sum = 0

 6523 23:09:59.536615  11, 0xFFFF, sum = 0

 6524 23:09:59.539836  12, 0xFFFF, sum = 0

 6525 23:09:59.539961  13, 0x0, sum = 1

 6526 23:09:59.543586  14, 0x0, sum = 2

 6527 23:09:59.543708  15, 0x0, sum = 3

 6528 23:09:59.546702  16, 0x0, sum = 4

 6529 23:09:59.546835  best_step = 14

 6530 23:09:59.546951  

 6531 23:09:59.547060  ==

 6532 23:09:59.549920  Dram Type= 6, Freq= 0, CH_0, rank 1

 6533 23:09:59.553454  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6534 23:09:59.553544  ==

 6535 23:09:59.556599  RX Vref Scan: 0

 6536 23:09:59.556710  

 6537 23:09:59.559732  RX Vref 0 -> 0, step: 1

 6538 23:09:59.559818  

 6539 23:09:59.559921  RX Delay -311 -> 252, step: 8

 6540 23:09:59.568515  iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448

 6541 23:09:59.571942  iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440

 6542 23:09:59.575645  iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448

 6543 23:09:59.578828  iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448

 6544 23:09:59.585048  iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448

 6545 23:09:59.588466  iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448

 6546 23:09:59.592250  iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440

 6547 23:09:59.595287  iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448

 6548 23:09:59.602002  iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448

 6549 23:09:59.605465  iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448

 6550 23:09:59.608713  iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440

 6551 23:09:59.611792  iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448

 6552 23:09:59.618215  iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440

 6553 23:09:59.621922  iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440

 6554 23:09:59.625228  iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440

 6555 23:09:59.631878  iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448

 6556 23:09:59.631965  ==

 6557 23:09:59.634919  Dram Type= 6, Freq= 0, CH_0, rank 1

 6558 23:09:59.638699  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6559 23:09:59.638775  ==

 6560 23:09:59.638841  DQS Delay:

 6561 23:09:59.641890  DQS0 = 24, DQS1 = 32

 6562 23:09:59.641965  DQM Delay:

 6563 23:09:59.644965  DQM0 = 9, DQM1 = 9

 6564 23:09:59.645036  DQ Delay:

 6565 23:09:59.648797  DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8

 6566 23:09:59.651884  DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16

 6567 23:09:59.655038  DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0

 6568 23:09:59.658674  DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16

 6569 23:09:59.658755  

 6570 23:09:59.658818  

 6571 23:09:59.665059  [DQSOSCAuto] RK1, (LSB)MR18= 0xc061, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 386 ps

 6572 23:09:59.668076  CH0 RK1: MR19=C0C, MR18=C061

 6573 23:09:59.674817  CH0_RK1: MR19=0xC0C, MR18=0xC061, DQSOSC=386, MR23=63, INC=396, DEC=264

 6574 23:09:59.678309  [RxdqsGatingPostProcess] freq 400

 6575 23:09:59.681651  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6576 23:09:59.684727  best DQS0 dly(2T, 0.5T) = (0, 10)

 6577 23:09:59.688363  best DQS1 dly(2T, 0.5T) = (0, 10)

 6578 23:09:59.691537  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6579 23:09:59.694809  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6580 23:09:59.698505  best DQS0 dly(2T, 0.5T) = (0, 10)

 6581 23:09:59.701661  best DQS1 dly(2T, 0.5T) = (0, 10)

 6582 23:09:59.704796  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6583 23:09:59.708545  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6584 23:09:59.711452  Pre-setting of DQS Precalculation

 6585 23:09:59.714797  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6586 23:09:59.718086  ==

 6587 23:09:59.718197  Dram Type= 6, Freq= 0, CH_1, rank 0

 6588 23:09:59.724638  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6589 23:09:59.724727  ==

 6590 23:09:59.728270  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6591 23:09:59.734956  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6592 23:09:59.738308  [CA 0] Center 36 (8~64) winsize 57

 6593 23:09:59.741501  [CA 1] Center 36 (8~64) winsize 57

 6594 23:09:59.744854  [CA 2] Center 36 (8~64) winsize 57

 6595 23:09:59.748093  [CA 3] Center 36 (8~64) winsize 57

 6596 23:09:59.751159  [CA 4] Center 36 (8~64) winsize 57

 6597 23:09:59.754835  [CA 5] Center 36 (8~64) winsize 57

 6598 23:09:59.754951  

 6599 23:09:59.758091  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6600 23:09:59.758206  

 6601 23:09:59.761139  [CATrainingPosCal] consider 1 rank data

 6602 23:09:59.764923  u2DelayCellTimex100 = 270/100 ps

 6603 23:09:59.767963  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6604 23:09:59.771145  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6605 23:09:59.774859  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6606 23:09:59.777964  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6607 23:09:59.781158  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6608 23:09:59.788144  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6609 23:09:59.788264  

 6610 23:09:59.791354  CA PerBit enable=1, Macro0, CA PI delay=36

 6611 23:09:59.791461  

 6612 23:09:59.794531  [CBTSetCACLKResult] CA Dly = 36

 6613 23:09:59.794638  CS Dly: 1 (0~32)

 6614 23:09:59.794731  ==

 6615 23:09:59.797720  Dram Type= 6, Freq= 0, CH_1, rank 1

 6616 23:09:59.801544  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6617 23:09:59.801656  ==

 6618 23:09:59.807741  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6619 23:09:59.814817  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6620 23:09:59.817741  [CA 0] Center 36 (8~64) winsize 57

 6621 23:09:59.821393  [CA 1] Center 36 (8~64) winsize 57

 6622 23:09:59.824532  [CA 2] Center 36 (8~64) winsize 57

 6623 23:09:59.827789  [CA 3] Center 36 (8~64) winsize 57

 6624 23:09:59.831016  [CA 4] Center 36 (8~64) winsize 57

 6625 23:09:59.834600  [CA 5] Center 36 (8~64) winsize 57

 6626 23:09:59.834711  

 6627 23:09:59.837714  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6628 23:09:59.837824  

 6629 23:09:59.841232  [CATrainingPosCal] consider 2 rank data

 6630 23:09:59.844172  u2DelayCellTimex100 = 270/100 ps

 6631 23:09:59.847719  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6632 23:09:59.850761  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6633 23:09:59.854481  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6634 23:09:59.857562  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6635 23:09:59.861023  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6636 23:09:59.864047  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6637 23:09:59.864158  

 6638 23:09:59.867918  CA PerBit enable=1, Macro0, CA PI delay=36

 6639 23:09:59.868028  

 6640 23:09:59.871021  [CBTSetCACLKResult] CA Dly = 36

 6641 23:09:59.874087  CS Dly: 1 (0~32)

 6642 23:09:59.874198  

 6643 23:09:59.877587  ----->DramcWriteLeveling(PI) begin...

 6644 23:09:59.877703  ==

 6645 23:09:59.881192  Dram Type= 6, Freq= 0, CH_1, rank 0

 6646 23:09:59.884170  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6647 23:09:59.884281  ==

 6648 23:09:59.887427  Write leveling (Byte 0): 40 => 8

 6649 23:09:59.890500  Write leveling (Byte 1): 40 => 8

 6650 23:09:59.893944  DramcWriteLeveling(PI) end<-----

 6651 23:09:59.894055  

 6652 23:09:59.894150  ==

 6653 23:09:59.897419  Dram Type= 6, Freq= 0, CH_1, rank 0

 6654 23:09:59.900592  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6655 23:09:59.900703  ==

 6656 23:09:59.904230  [Gating] SW mode calibration

 6657 23:09:59.910663  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6658 23:09:59.917678  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6659 23:09:59.920646   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6660 23:09:59.927269   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6661 23:09:59.930413   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6662 23:09:59.934227   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6663 23:09:59.940474   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6664 23:09:59.943675   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6665 23:09:59.947419   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6666 23:09:59.950476   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6667 23:09:59.957177   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6668 23:09:59.960601  Total UI for P1: 0, mck2ui 16

 6669 23:09:59.963587  best dqsien dly found for B0: ( 0, 14, 24)

 6670 23:09:59.966903  Total UI for P1: 0, mck2ui 16

 6671 23:09:59.970526  best dqsien dly found for B1: ( 0, 14, 24)

 6672 23:09:59.974166  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6673 23:09:59.977116  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6674 23:09:59.977226  

 6675 23:09:59.980455  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6676 23:09:59.983710  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6677 23:09:59.987397  [Gating] SW calibration Done

 6678 23:09:59.987471  ==

 6679 23:09:59.990294  Dram Type= 6, Freq= 0, CH_1, rank 0

 6680 23:09:59.993880  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6681 23:09:59.994004  ==

 6682 23:09:59.997523  RX Vref Scan: 0

 6683 23:09:59.997647  

 6684 23:09:59.997758  RX Vref 0 -> 0, step: 1

 6685 23:10:00.000425  

 6686 23:10:00.000500  RX Delay -410 -> 252, step: 16

 6687 23:10:00.006965  iDelay=230, Bit 0, Center -3 (-234 ~ 229) 464

 6688 23:10:00.010317  iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480

 6689 23:10:00.013606  iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464

 6690 23:10:00.016935  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6691 23:10:00.023989  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6692 23:10:00.027027  iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464

 6693 23:10:00.030737  iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464

 6694 23:10:00.033921  iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464

 6695 23:10:00.040131  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6696 23:10:00.043956  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6697 23:10:00.047123  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6698 23:10:00.050250  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6699 23:10:00.057221  iDelay=230, Bit 12, Center -3 (-234 ~ 229) 464

 6700 23:10:00.060496  iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448

 6701 23:10:00.063703  iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448

 6702 23:10:00.067281  iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464

 6703 23:10:00.067397  ==

 6704 23:10:00.070160  Dram Type= 6, Freq= 0, CH_1, rank 0

 6705 23:10:00.077073  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6706 23:10:00.077191  ==

 6707 23:10:00.077288  DQS Delay:

 6708 23:10:00.080266  DQS0 = 35, DQS1 = 35

 6709 23:10:00.080383  DQM Delay:

 6710 23:10:00.084008  DQM0 = 19, DQM1 = 17

 6711 23:10:00.084115  DQ Delay:

 6712 23:10:00.087277  DQ0 =32, DQ1 =8, DQ2 =0, DQ3 =16

 6713 23:10:00.090336  DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16

 6714 23:10:00.093860  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6715 23:10:00.096742  DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32

 6716 23:10:00.096850  

 6717 23:10:00.096945  

 6718 23:10:00.097037  ==

 6719 23:10:00.100626  Dram Type= 6, Freq= 0, CH_1, rank 0

 6720 23:10:00.103514  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6721 23:10:00.103625  ==

 6722 23:10:00.103725  

 6723 23:10:00.103815  

 6724 23:10:00.107146  	TX Vref Scan disable

 6725 23:10:00.107256   == TX Byte 0 ==

 6726 23:10:00.113674  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6727 23:10:00.116616  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6728 23:10:00.116728   == TX Byte 1 ==

 6729 23:10:00.123436  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6730 23:10:00.126709  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6731 23:10:00.126819  ==

 6732 23:10:00.129837  Dram Type= 6, Freq= 0, CH_1, rank 0

 6733 23:10:00.133135  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6734 23:10:00.133241  ==

 6735 23:10:00.133338  

 6736 23:10:00.133427  

 6737 23:10:00.136553  	TX Vref Scan disable

 6738 23:10:00.136626   == TX Byte 0 ==

 6739 23:10:00.143242  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6740 23:10:00.146809  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6741 23:10:00.146925   == TX Byte 1 ==

 6742 23:10:00.153559  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6743 23:10:00.156917  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6744 23:10:00.157001  

 6745 23:10:00.157070  [DATLAT]

 6746 23:10:00.160081  Freq=400, CH1 RK0

 6747 23:10:00.160179  

 6748 23:10:00.160276  DATLAT Default: 0xf

 6749 23:10:00.163372  0, 0xFFFF, sum = 0

 6750 23:10:00.163472  1, 0xFFFF, sum = 0

 6751 23:10:00.166364  2, 0xFFFF, sum = 0

 6752 23:10:00.166491  3, 0xFFFF, sum = 0

 6753 23:10:00.170151  4, 0xFFFF, sum = 0

 6754 23:10:00.170282  5, 0xFFFF, sum = 0

 6755 23:10:00.173227  6, 0xFFFF, sum = 0

 6756 23:10:00.173355  7, 0xFFFF, sum = 0

 6757 23:10:00.176691  8, 0xFFFF, sum = 0

 6758 23:10:00.176823  9, 0xFFFF, sum = 0

 6759 23:10:00.180143  10, 0xFFFF, sum = 0

 6760 23:10:00.183301  11, 0xFFFF, sum = 0

 6761 23:10:00.183428  12, 0xFFFF, sum = 0

 6762 23:10:00.186620  13, 0x0, sum = 1

 6763 23:10:00.186745  14, 0x0, sum = 2

 6764 23:10:00.189563  15, 0x0, sum = 3

 6765 23:10:00.189687  16, 0x0, sum = 4

 6766 23:10:00.189808  best_step = 14

 6767 23:10:00.189918  

 6768 23:10:00.193353  ==

 6769 23:10:00.196483  Dram Type= 6, Freq= 0, CH_1, rank 0

 6770 23:10:00.199439  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6771 23:10:00.199556  ==

 6772 23:10:00.199673  RX Vref Scan: 1

 6773 23:10:00.199785  

 6774 23:10:00.203104  RX Vref 0 -> 0, step: 1

 6775 23:10:00.203226  

 6776 23:10:00.206599  RX Delay -311 -> 252, step: 8

 6777 23:10:00.206723  

 6778 23:10:00.209566  Set Vref, RX VrefLevel [Byte0]: 56

 6779 23:10:00.212931                           [Byte1]: 54

 6780 23:10:00.216470  

 6781 23:10:00.216597  Final RX Vref Byte 0 = 56 to rank0

 6782 23:10:00.220005  Final RX Vref Byte 1 = 54 to rank0

 6783 23:10:00.223188  Final RX Vref Byte 0 = 56 to rank1

 6784 23:10:00.226318  Final RX Vref Byte 1 = 54 to rank1==

 6785 23:10:00.229464  Dram Type= 6, Freq= 0, CH_1, rank 0

 6786 23:10:00.236221  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6787 23:10:00.236348  ==

 6788 23:10:00.236443  DQS Delay:

 6789 23:10:00.239832  DQS0 = 24, DQS1 = 32

 6790 23:10:00.239936  DQM Delay:

 6791 23:10:00.240031  DQM0 = 6, DQM1 = 9

 6792 23:10:00.242970  DQ Delay:

 6793 23:10:00.243085  DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4

 6794 23:10:00.246449  DQ4 =4, DQ5 =16, DQ6 =12, DQ7 =4

 6795 23:10:00.249878  DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4

 6796 23:10:00.252953  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16

 6797 23:10:00.253065  

 6798 23:10:00.253160  

 6799 23:10:00.262781  [DQSOSCAuto] RK0, (LSB)MR18= 0x8ec7, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps

 6800 23:10:00.266432  CH1 RK0: MR19=C0C, MR18=8EC7

 6801 23:10:00.269722  CH1_RK0: MR19=0xC0C, MR18=0x8EC7, DQSOSC=385, MR23=63, INC=398, DEC=265

 6802 23:10:00.272930  ==

 6803 23:10:00.276088  Dram Type= 6, Freq= 0, CH_1, rank 1

 6804 23:10:00.279873  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6805 23:10:00.279985  ==

 6806 23:10:00.282906  [Gating] SW mode calibration

 6807 23:10:00.289492  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6808 23:10:00.293188  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6809 23:10:00.299465   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6810 23:10:00.302687   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6811 23:10:00.306380   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6812 23:10:00.313188   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6813 23:10:00.316179   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6814 23:10:00.319692   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6815 23:10:00.326281   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6816 23:10:00.329185   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6817 23:10:00.332420   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6818 23:10:00.336121  Total UI for P1: 0, mck2ui 16

 6819 23:10:00.339266  best dqsien dly found for B0: ( 0, 14, 24)

 6820 23:10:00.342469  Total UI for P1: 0, mck2ui 16

 6821 23:10:00.346181  best dqsien dly found for B1: ( 0, 14, 24)

 6822 23:10:00.349315  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6823 23:10:00.352521  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6824 23:10:00.352632  

 6825 23:10:00.359306  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6826 23:10:00.362449  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6827 23:10:00.362562  [Gating] SW calibration Done

 6828 23:10:00.365999  ==

 6829 23:10:00.368979  Dram Type= 6, Freq= 0, CH_1, rank 1

 6830 23:10:00.372735  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6831 23:10:00.372845  ==

 6832 23:10:00.372940  RX Vref Scan: 0

 6833 23:10:00.373032  

 6834 23:10:00.375704  RX Vref 0 -> 0, step: 1

 6835 23:10:00.375811  

 6836 23:10:00.379005  RX Delay -410 -> 252, step: 16

 6837 23:10:00.382248  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6838 23:10:00.385953  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6839 23:10:00.392571  iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464

 6840 23:10:00.395426  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6841 23:10:00.399145  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6842 23:10:00.402306  iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464

 6843 23:10:00.409228  iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464

 6844 23:10:00.412199  iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464

 6845 23:10:00.415776  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6846 23:10:00.418837  iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480

 6847 23:10:00.425474  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6848 23:10:00.429186  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6849 23:10:00.432633  iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480

 6850 23:10:00.435475  iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480

 6851 23:10:00.442447  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6852 23:10:00.445624  iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480

 6853 23:10:00.445739  ==

 6854 23:10:00.449348  Dram Type= 6, Freq= 0, CH_1, rank 1

 6855 23:10:00.452473  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6856 23:10:00.452567  ==

 6857 23:10:00.455592  DQS Delay:

 6858 23:10:00.455667  DQS0 = 35, DQS1 = 35

 6859 23:10:00.459361  DQM Delay:

 6860 23:10:00.459461  DQM0 = 18, DQM1 = 15

 6861 23:10:00.459545  DQ Delay:

 6862 23:10:00.462329  DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16

 6863 23:10:00.465970  DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16

 6864 23:10:00.469169  DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8

 6865 23:10:00.472398  DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24

 6866 23:10:00.472481  

 6867 23:10:00.472553  

 6868 23:10:00.472614  ==

 6869 23:10:00.475555  Dram Type= 6, Freq= 0, CH_1, rank 1

 6870 23:10:00.482258  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6871 23:10:00.482364  ==

 6872 23:10:00.482456  

 6873 23:10:00.482548  

 6874 23:10:00.482636  	TX Vref Scan disable

 6875 23:10:00.485110   == TX Byte 0 ==

 6876 23:10:00.488657  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6877 23:10:00.492361  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6878 23:10:00.495199   == TX Byte 1 ==

 6879 23:10:00.498722  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6880 23:10:00.501901  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6881 23:10:00.505002  ==

 6882 23:10:00.508692  Dram Type= 6, Freq= 0, CH_1, rank 1

 6883 23:10:00.511942  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6884 23:10:00.512044  ==

 6885 23:10:00.512114  

 6886 23:10:00.512176  

 6887 23:10:00.515417  	TX Vref Scan disable

 6888 23:10:00.515533   == TX Byte 0 ==

 6889 23:10:00.518504  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6890 23:10:00.525101  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6891 23:10:00.525217   == TX Byte 1 ==

 6892 23:10:00.528117  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6893 23:10:00.531629  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6894 23:10:00.534794  

 6895 23:10:00.534899  [DATLAT]

 6896 23:10:00.535004  Freq=400, CH1 RK1

 6897 23:10:00.535100  

 6898 23:10:00.538510  DATLAT Default: 0xe

 6899 23:10:00.538626  0, 0xFFFF, sum = 0

 6900 23:10:00.541554  1, 0xFFFF, sum = 0

 6901 23:10:00.541661  2, 0xFFFF, sum = 0

 6902 23:10:00.545208  3, 0xFFFF, sum = 0

 6903 23:10:00.545302  4, 0xFFFF, sum = 0

 6904 23:10:00.548124  5, 0xFFFF, sum = 0

 6905 23:10:00.548227  6, 0xFFFF, sum = 0

 6906 23:10:00.551936  7, 0xFFFF, sum = 0

 6907 23:10:00.555039  8, 0xFFFF, sum = 0

 6908 23:10:00.555143  9, 0xFFFF, sum = 0

 6909 23:10:00.558263  10, 0xFFFF, sum = 0

 6910 23:10:00.558364  11, 0xFFFF, sum = 0

 6911 23:10:00.561511  12, 0xFFFF, sum = 0

 6912 23:10:00.561592  13, 0x0, sum = 1

 6913 23:10:00.565191  14, 0x0, sum = 2

 6914 23:10:00.565297  15, 0x0, sum = 3

 6915 23:10:00.568177  16, 0x0, sum = 4

 6916 23:10:00.568253  best_step = 14

 6917 23:10:00.568338  

 6918 23:10:00.568399  ==

 6919 23:10:00.571938  Dram Type= 6, Freq= 0, CH_1, rank 1

 6920 23:10:00.575063  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6921 23:10:00.575166  ==

 6922 23:10:00.578290  RX Vref Scan: 0

 6923 23:10:00.578366  

 6924 23:10:00.581495  RX Vref 0 -> 0, step: 1

 6925 23:10:00.581573  

 6926 23:10:00.581635  RX Delay -311 -> 252, step: 8

 6927 23:10:00.590296  iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448

 6928 23:10:00.593295  iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448

 6929 23:10:00.596668  iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440

 6930 23:10:00.603755  iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440

 6931 23:10:00.606858  iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440

 6932 23:10:00.609827  iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448

 6933 23:10:00.613196  iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448

 6934 23:10:00.616664  iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448

 6935 23:10:00.623172  iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456

 6936 23:10:00.626728  iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448

 6937 23:10:00.630366  iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456

 6938 23:10:00.633118  iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456

 6939 23:10:00.640079  iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456

 6940 23:10:00.643856  iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448

 6941 23:10:00.646758  iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448

 6942 23:10:00.650122  iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456

 6943 23:10:00.653259  ==

 6944 23:10:00.656822  Dram Type= 6, Freq= 0, CH_1, rank 1

 6945 23:10:00.659982  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6946 23:10:00.660093  ==

 6947 23:10:00.660189  DQS Delay:

 6948 23:10:00.663685  DQS0 = 28, DQS1 = 36

 6949 23:10:00.663794  DQM Delay:

 6950 23:10:00.666894  DQM0 = 10, DQM1 = 14

 6951 23:10:00.667005  DQ Delay:

 6952 23:10:00.670107  DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8

 6953 23:10:00.673542  DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12

 6954 23:10:00.676696  DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8

 6955 23:10:00.680429  DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24

 6956 23:10:00.680541  

 6957 23:10:00.680636  

 6958 23:10:00.686869  [DQSOSCAuto] RK1, (LSB)MR18= 0xc758, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps

 6959 23:10:00.690546  CH1 RK1: MR19=C0C, MR18=C758

 6960 23:10:00.696705  CH1_RK1: MR19=0xC0C, MR18=0xC758, DQSOSC=385, MR23=63, INC=398, DEC=265

 6961 23:10:00.700488  [RxdqsGatingPostProcess] freq 400

 6962 23:10:00.703417  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6963 23:10:00.706926  best DQS0 dly(2T, 0.5T) = (0, 10)

 6964 23:10:00.710095  best DQS1 dly(2T, 0.5T) = (0, 10)

 6965 23:10:00.713809  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6966 23:10:00.717004  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6967 23:10:00.719992  best DQS0 dly(2T, 0.5T) = (0, 10)

 6968 23:10:00.723596  best DQS1 dly(2T, 0.5T) = (0, 10)

 6969 23:10:00.726803  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6970 23:10:00.730051  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6971 23:10:00.733313  Pre-setting of DQS Precalculation

 6972 23:10:00.736931  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6973 23:10:00.747011  sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6

 6974 23:10:00.753511  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 6975 23:10:00.753630  

 6976 23:10:00.753730  

 6977 23:10:00.756814  [Calibration Summary] 800 Mbps

 6978 23:10:00.756927  CH 0, Rank 0

 6979 23:10:00.759923  SW Impedance     : PASS

 6980 23:10:00.760031  DUTY Scan        : NO K

 6981 23:10:00.763198  ZQ Calibration   : PASS

 6982 23:10:00.766772  Jitter Meter     : NO K

 6983 23:10:00.766885  CBT Training     : PASS

 6984 23:10:00.769924  Write leveling   : PASS

 6985 23:10:00.773530  RX DQS gating    : PASS

 6986 23:10:00.773639  RX DQ/DQS(RDDQC) : PASS

 6987 23:10:00.776637  TX DQ/DQS        : PASS

 6988 23:10:00.776747  RX DATLAT        : PASS

 6989 23:10:00.779937  RX DQ/DQS(Engine): PASS

 6990 23:10:00.783374  TX OE            : NO K

 6991 23:10:00.783488  All Pass.

 6992 23:10:00.783584  

 6993 23:10:00.783676  CH 0, Rank 1

 6994 23:10:00.786940  SW Impedance     : PASS

 6995 23:10:00.790152  DUTY Scan        : NO K

 6996 23:10:00.790260  ZQ Calibration   : PASS

 6997 23:10:00.793398  Jitter Meter     : NO K

 6998 23:10:00.796624  CBT Training     : PASS

 6999 23:10:00.796735  Write leveling   : NO K

 7000 23:10:00.800419  RX DQS gating    : PASS

 7001 23:10:00.803644  RX DQ/DQS(RDDQC) : PASS

 7002 23:10:00.803755  TX DQ/DQS        : PASS

 7003 23:10:00.806687  RX DATLAT        : PASS

 7004 23:10:00.810253  RX DQ/DQS(Engine): PASS

 7005 23:10:00.810371  TX OE            : NO K

 7006 23:10:00.810470  All Pass.

 7007 23:10:00.813636  

 7008 23:10:00.813746  CH 1, Rank 0

 7009 23:10:00.816728  SW Impedance     : PASS

 7010 23:10:00.816837  DUTY Scan        : NO K

 7011 23:10:00.819903  ZQ Calibration   : PASS

 7012 23:10:00.820011  Jitter Meter     : NO K

 7013 23:10:00.823551  CBT Training     : PASS

 7014 23:10:00.827005  Write leveling   : PASS

 7015 23:10:00.827115  RX DQS gating    : PASS

 7016 23:10:00.830022  RX DQ/DQS(RDDQC) : PASS

 7017 23:10:00.833215  TX DQ/DQS        : PASS

 7018 23:10:00.833300  RX DATLAT        : PASS

 7019 23:10:00.837040  RX DQ/DQS(Engine): PASS

 7020 23:10:00.840222  TX OE            : NO K

 7021 23:10:00.840347  All Pass.

 7022 23:10:00.840443  

 7023 23:10:00.840540  CH 1, Rank 1

 7024 23:10:00.843409  SW Impedance     : PASS

 7025 23:10:00.846501  DUTY Scan        : NO K

 7026 23:10:00.846609  ZQ Calibration   : PASS

 7027 23:10:00.849725  Jitter Meter     : NO K

 7028 23:10:00.853007  CBT Training     : PASS

 7029 23:10:00.853117  Write leveling   : NO K

 7030 23:10:00.856674  RX DQS gating    : PASS

 7031 23:10:00.859788  RX DQ/DQS(RDDQC) : PASS

 7032 23:10:00.859897  TX DQ/DQS        : PASS

 7033 23:10:00.863102  RX DATLAT        : PASS

 7034 23:10:00.866617  RX DQ/DQS(Engine): PASS

 7035 23:10:00.866727  TX OE            : NO K

 7036 23:10:00.866823  All Pass.

 7037 23:10:00.869805  

 7038 23:10:00.869891  DramC Write-DBI off

 7039 23:10:00.872799  	PER_BANK_REFRESH: Hybrid Mode

 7040 23:10:00.872875  TX_TRACKING: ON

 7041 23:10:00.883294  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 7042 23:10:00.886524  [FAST_K] Save calibration result to emmc

 7043 23:10:00.889992  dramc_set_vcore_voltage set vcore to 725000

 7044 23:10:00.893233  Read voltage for 1600, 0

 7045 23:10:00.893322  Vio18 = 0

 7046 23:10:00.896175  Vcore = 725000

 7047 23:10:00.896293  Vdram = 0

 7048 23:10:00.896364  Vddq = 0

 7049 23:10:00.896426  Vmddr = 0

 7050 23:10:00.903225  [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0

 7051 23:10:00.909432  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 7052 23:10:00.909531  MEM_TYPE=3, freq_sel=13

 7053 23:10:00.913306  sv_algorithm_assistance_LP4_3733 

 7054 23:10:00.916268  ============ PULL DRAM RESETB DOWN ============

 7055 23:10:00.923226  ========== PULL DRAM RESETB DOWN end =========

 7056 23:10:00.926454  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7057 23:10:00.929538  =================================== 

 7058 23:10:00.933099  LPDDR4 DRAM CONFIGURATION

 7059 23:10:00.936783  =================================== 

 7060 23:10:00.936869  EX_ROW_EN[0]    = 0x0

 7061 23:10:00.939903  EX_ROW_EN[1]    = 0x0

 7062 23:10:00.939989  LP4Y_EN      = 0x0

 7063 23:10:00.942968  WORK_FSP     = 0x1

 7064 23:10:00.943053  WL           = 0x5

 7065 23:10:00.946821  RL           = 0x5

 7066 23:10:00.946906  BL           = 0x2

 7067 23:10:00.949983  RPST         = 0x0

 7068 23:10:00.950094  RD_PRE       = 0x0

 7069 23:10:00.953077  WR_PRE       = 0x1

 7070 23:10:00.953162  WR_PST       = 0x1

 7071 23:10:00.956273  DBI_WR       = 0x0

 7072 23:10:00.960051  DBI_RD       = 0x0

 7073 23:10:00.960139  OTF          = 0x1

 7074 23:10:00.963298  =================================== 

 7075 23:10:00.966549  =================================== 

 7076 23:10:00.966637  ANA top config

 7077 23:10:00.969634  =================================== 

 7078 23:10:00.973372  DLL_ASYNC_EN            =  0

 7079 23:10:00.976412  ALL_SLAVE_EN            =  0

 7080 23:10:00.979966  NEW_RANK_MODE           =  1

 7081 23:10:00.980049  DLL_IDLE_MODE           =  1

 7082 23:10:00.983346  LP45_APHY_COMB_EN       =  1

 7083 23:10:00.986414  TX_ODT_DIS              =  0

 7084 23:10:00.989703  NEW_8X_MODE             =  1

 7085 23:10:00.993349  =================================== 

 7086 23:10:00.996440  =================================== 

 7087 23:10:00.999608  data_rate                  = 3200

 7088 23:10:01.003368  CKR                        = 1

 7089 23:10:01.003482  DQ_P2S_RATIO               = 8

 7090 23:10:01.006218  =================================== 

 7091 23:10:01.009575  CA_P2S_RATIO               = 8

 7092 23:10:01.013379  DQ_CA_OPEN                 = 0

 7093 23:10:01.016314  DQ_SEMI_OPEN               = 0

 7094 23:10:01.019874  CA_SEMI_OPEN               = 0

 7095 23:10:01.019986  CA_FULL_RATE               = 0

 7096 23:10:01.022856  DQ_CKDIV4_EN               = 0

 7097 23:10:01.026622  CA_CKDIV4_EN               = 0

 7098 23:10:01.029727  CA_PREDIV_EN               = 0

 7099 23:10:01.033117  PH8_DLY                    = 12

 7100 23:10:01.036211  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 7101 23:10:01.036333  DQ_AAMCK_DIV               = 4

 7102 23:10:01.039944  CA_AAMCK_DIV               = 4

 7103 23:10:01.045263  CA_ADMCK_DIV               = 4

 7104 23:10:01.046668  DQ_TRACK_CA_EN             = 0

 7105 23:10:01.049817  CA_PICK                    = 1600

 7106 23:10:01.053114  CA_MCKIO                   = 1600

 7107 23:10:01.056219  MCKIO_SEMI                 = 0

 7108 23:10:01.056346  PLL_FREQ                   = 3068

 7109 23:10:01.059468  DQ_UI_PI_RATIO             = 32

 7110 23:10:01.063221  CA_UI_PI_RATIO             = 0

 7111 23:10:01.066371  =================================== 

 7112 23:10:01.069588  =================================== 

 7113 23:10:01.073263  memory_type:LPDDR4         

 7114 23:10:01.076494  GP_NUM     : 10       

 7115 23:10:01.076602  SRAM_EN    : 1       

 7116 23:10:01.079638  MD32_EN    : 0       

 7117 23:10:01.082865  =================================== 

 7118 23:10:01.082976  [ANA_INIT] >>>>>>>>>>>>>> 

 7119 23:10:01.086583  <<<<<< [CONFIGURE PHASE]: ANA_TX

 7120 23:10:01.089561  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 7121 23:10:01.092956  =================================== 

 7122 23:10:01.096480  data_rate = 3200,PCW = 0X7600

 7123 23:10:01.099407  =================================== 

 7124 23:10:01.103287  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 7125 23:10:01.109647  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7126 23:10:01.112757  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7127 23:10:01.119494  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 7128 23:10:01.123159  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 7129 23:10:01.126547  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 7130 23:10:01.129397  [ANA_INIT] flow start 

 7131 23:10:01.129504  [ANA_INIT] PLL >>>>>>>> 

 7132 23:10:01.133165  [ANA_INIT] PLL <<<<<<<< 

 7133 23:10:01.136264  [ANA_INIT] MIDPI >>>>>>>> 

 7134 23:10:01.136387  [ANA_INIT] MIDPI <<<<<<<< 

 7135 23:10:01.139881  [ANA_INIT] DLL >>>>>>>> 

 7136 23:10:01.142730  [ANA_INIT] DLL <<<<<<<< 

 7137 23:10:01.142836  [ANA_INIT] flow end 

 7138 23:10:01.146039  ============ LP4 DIFF to SE enter ============

 7139 23:10:01.153021  ============ LP4 DIFF to SE exit  ============

 7140 23:10:01.153130  [ANA_INIT] <<<<<<<<<<<<< 

 7141 23:10:01.156131  [Flow] Enable top DCM control >>>>> 

 7142 23:10:01.159264  [Flow] Enable top DCM control <<<<< 

 7143 23:10:01.162500  Enable DLL master slave shuffle 

 7144 23:10:01.169176  ============================================================== 

 7145 23:10:01.172910  Gating Mode config

 7146 23:10:01.175949  ============================================================== 

 7147 23:10:01.179201  Config description: 

 7148 23:10:01.189267  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 7149 23:10:01.196351  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 7150 23:10:01.199300  SELPH_MODE            0: By rank         1: By Phase 

 7151 23:10:01.205976  ============================================================== 

 7152 23:10:01.209082  GAT_TRACK_EN                 =  1

 7153 23:10:01.212350  RX_GATING_MODE               =  2

 7154 23:10:01.212458  RX_GATING_TRACK_MODE         =  2

 7155 23:10:01.215652  SELPH_MODE                   =  1

 7156 23:10:01.219234  PICG_EARLY_EN                =  1

 7157 23:10:01.222366  VALID_LAT_VALUE              =  1

 7158 23:10:01.229206  ============================================================== 

 7159 23:10:01.232876  Enter into Gating configuration >>>> 

 7160 23:10:01.235916  Exit from Gating configuration <<<< 

 7161 23:10:01.239219  Enter into  DVFS_PRE_config >>>>> 

 7162 23:10:01.249452  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 7163 23:10:01.252449  Exit from  DVFS_PRE_config <<<<< 

 7164 23:10:01.256002  Enter into PICG configuration >>>> 

 7165 23:10:01.258862  Exit from PICG configuration <<<< 

 7166 23:10:01.262458  [RX_INPUT] configuration >>>>> 

 7167 23:10:01.265486  [RX_INPUT] configuration <<<<< 

 7168 23:10:01.269320  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 7169 23:10:01.275954  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 7170 23:10:01.282528  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 7171 23:10:01.288829  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 7172 23:10:01.292597  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 7173 23:10:01.299401  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 7174 23:10:01.302440  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 7175 23:10:01.308879  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 7176 23:10:01.312130  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 7177 23:10:01.315748  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 7178 23:10:01.319292  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 7179 23:10:01.325690  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7180 23:10:01.329236  =================================== 

 7181 23:10:01.329344  LPDDR4 DRAM CONFIGURATION

 7182 23:10:01.332341  =================================== 

 7183 23:10:01.335718  EX_ROW_EN[0]    = 0x0

 7184 23:10:01.339238  EX_ROW_EN[1]    = 0x0

 7185 23:10:01.339348  LP4Y_EN      = 0x0

 7186 23:10:01.342680  WORK_FSP     = 0x1

 7187 23:10:01.342790  WL           = 0x5

 7188 23:10:01.345587  RL           = 0x5

 7189 23:10:01.345693  BL           = 0x2

 7190 23:10:01.349223  RPST         = 0x0

 7191 23:10:01.349329  RD_PRE       = 0x0

 7192 23:10:01.352379  WR_PRE       = 0x1

 7193 23:10:01.352489  WR_PST       = 0x1

 7194 23:10:01.355525  DBI_WR       = 0x0

 7195 23:10:01.355628  DBI_RD       = 0x0

 7196 23:10:01.359352  OTF          = 0x1

 7197 23:10:01.362361  =================================== 

 7198 23:10:01.365760  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 7199 23:10:01.368923  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 7200 23:10:01.375698  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7201 23:10:01.378841  =================================== 

 7202 23:10:01.378945  LPDDR4 DRAM CONFIGURATION

 7203 23:10:01.382047  =================================== 

 7204 23:10:01.385300  EX_ROW_EN[0]    = 0x10

 7205 23:10:01.389030  EX_ROW_EN[1]    = 0x0

 7206 23:10:01.389136  LP4Y_EN      = 0x0

 7207 23:10:01.392033  WORK_FSP     = 0x1

 7208 23:10:01.392135  WL           = 0x5

 7209 23:10:01.395029  RL           = 0x5

 7210 23:10:01.395132  BL           = 0x2

 7211 23:10:01.398250  RPST         = 0x0

 7212 23:10:01.398352  RD_PRE       = 0x0

 7213 23:10:01.401843  WR_PRE       = 0x1

 7214 23:10:01.401948  WR_PST       = 0x1

 7215 23:10:01.404877  DBI_WR       = 0x0

 7216 23:10:01.404982  DBI_RD       = 0x0

 7217 23:10:01.408243  OTF          = 0x1

 7218 23:10:01.411802  =================================== 

 7219 23:10:01.418673  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 7220 23:10:01.418789  ==

 7221 23:10:01.421676  Dram Type= 6, Freq= 0, CH_0, rank 0

 7222 23:10:01.425215  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7223 23:10:01.425326  ==

 7224 23:10:01.428214  [Duty_Offset_Calibration]

 7225 23:10:01.428329  	B0:2	B1:1	CA:1

 7226 23:10:01.428426  

 7227 23:10:01.431827  [DutyScan_Calibration_Flow] k_type=0

 7228 23:10:01.442445  

 7229 23:10:01.442559  ==CLK 0==

 7230 23:10:01.445603  Final CLK duty delay cell = 0

 7231 23:10:01.448691  [0] MAX Duty = 5156%(X100), DQS PI = 22

 7232 23:10:01.452122  [0] MIN Duty = 4907%(X100), DQS PI = 0

 7233 23:10:01.452229  [0] AVG Duty = 5031%(X100)

 7234 23:10:01.455498  

 7235 23:10:01.455608  CH0 CLK Duty spec in!! Max-Min= 249%

 7236 23:10:01.462433  [DutyScan_Calibration_Flow] ====Done====

 7237 23:10:01.462542  

 7238 23:10:01.465539  [DutyScan_Calibration_Flow] k_type=1

 7239 23:10:01.481105  

 7240 23:10:01.481253  ==DQS 0 ==

 7241 23:10:01.484556  Final DQS duty delay cell = -4

 7242 23:10:01.488236  [-4] MAX Duty = 5125%(X100), DQS PI = 24

 7243 23:10:01.491490  [-4] MIN Duty = 4657%(X100), DQS PI = 0

 7244 23:10:01.494564  [-4] AVG Duty = 4891%(X100)

 7245 23:10:01.494678  

 7246 23:10:01.494769  ==DQS 1 ==

 7247 23:10:01.497788  Final DQS duty delay cell = 0

 7248 23:10:01.501534  [0] MAX Duty = 5218%(X100), DQS PI = 20

 7249 23:10:01.504806  [0] MIN Duty = 5062%(X100), DQS PI = 32

 7250 23:10:01.507907  [0] AVG Duty = 5140%(X100)

 7251 23:10:01.508012  

 7252 23:10:01.511462  CH0 DQS 0 Duty spec in!! Max-Min= 468%

 7253 23:10:01.511567  

 7254 23:10:01.514400  CH0 DQS 1 Duty spec in!! Max-Min= 156%

 7255 23:10:01.518072  [DutyScan_Calibration_Flow] ====Done====

 7256 23:10:01.518182  

 7257 23:10:01.521262  [DutyScan_Calibration_Flow] k_type=3

 7258 23:10:01.538084  

 7259 23:10:01.538247  ==DQM 0 ==

 7260 23:10:01.541247  Final DQM duty delay cell = 0

 7261 23:10:01.544741  [0] MAX Duty = 5218%(X100), DQS PI = 32

 7262 23:10:01.547688  [0] MIN Duty = 4907%(X100), DQS PI = 56

 7263 23:10:01.551695  [0] AVG Duty = 5062%(X100)

 7264 23:10:01.551814  

 7265 23:10:01.551910  ==DQM 1 ==

 7266 23:10:01.554531  Final DQM duty delay cell = -4

 7267 23:10:01.558209  [-4] MAX Duty = 5000%(X100), DQS PI = 22

 7268 23:10:01.561075  [-4] MIN Duty = 4813%(X100), DQS PI = 50

 7269 23:10:01.564626  [-4] AVG Duty = 4906%(X100)

 7270 23:10:01.564742  

 7271 23:10:01.567693  CH0 DQM 0 Duty spec in!! Max-Min= 311%

 7272 23:10:01.567805  

 7273 23:10:01.571430  CH0 DQM 1 Duty spec in!! Max-Min= 187%

 7274 23:10:01.574751  [DutyScan_Calibration_Flow] ====Done====

 7275 23:10:01.574849  

 7276 23:10:01.577842  [DutyScan_Calibration_Flow] k_type=2

 7277 23:10:01.595526  

 7278 23:10:01.595661  ==DQ 0 ==

 7279 23:10:01.599194  Final DQ duty delay cell = 0

 7280 23:10:01.602452  [0] MAX Duty = 5062%(X100), DQS PI = 24

 7281 23:10:01.605630  [0] MIN Duty = 4907%(X100), DQS PI = 0

 7282 23:10:01.605715  [0] AVG Duty = 4984%(X100)

 7283 23:10:01.605782  

 7284 23:10:01.609301  ==DQ 1 ==

 7285 23:10:01.612520  Final DQ duty delay cell = 0

 7286 23:10:01.615448  [0] MAX Duty = 5124%(X100), DQS PI = 22

 7287 23:10:01.618556  [0] MIN Duty = 4938%(X100), DQS PI = 32

 7288 23:10:01.618674  [0] AVG Duty = 5031%(X100)

 7289 23:10:01.618771  

 7290 23:10:01.622421  CH0 DQ 0 Duty spec in!! Max-Min= 155%

 7291 23:10:01.625513  

 7292 23:10:01.628720  CH0 DQ 1 Duty spec in!! Max-Min= 186%

 7293 23:10:01.632299  [DutyScan_Calibration_Flow] ====Done====

 7294 23:10:01.632411  ==

 7295 23:10:01.635578  Dram Type= 6, Freq= 0, CH_1, rank 0

 7296 23:10:01.638865  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7297 23:10:01.638970  ==

 7298 23:10:01.641978  [Duty_Offset_Calibration]

 7299 23:10:01.642092  	B0:1	B1:0	CA:0

 7300 23:10:01.642186  

 7301 23:10:01.645695  [DutyScan_Calibration_Flow] k_type=0

 7302 23:10:01.654794  

 7303 23:10:01.654883  ==CLK 0==

 7304 23:10:01.658476  Final CLK duty delay cell = -4

 7305 23:10:01.662177  [-4] MAX Duty = 5000%(X100), DQS PI = 22

 7306 23:10:01.665140  [-4] MIN Duty = 4844%(X100), DQS PI = 2

 7307 23:10:01.668643  [-4] AVG Duty = 4922%(X100)

 7308 23:10:01.668727  

 7309 23:10:01.671646  CH1 CLK Duty spec in!! Max-Min= 156%

 7310 23:10:01.675088  [DutyScan_Calibration_Flow] ====Done====

 7311 23:10:01.675216  

 7312 23:10:01.678120  [DutyScan_Calibration_Flow] k_type=1

 7313 23:10:01.695045  

 7314 23:10:01.695210  ==DQS 0 ==

 7315 23:10:01.698536  Final DQS duty delay cell = 0

 7316 23:10:01.701415  [0] MAX Duty = 5125%(X100), DQS PI = 30

 7317 23:10:01.705249  [0] MIN Duty = 4844%(X100), DQS PI = 50

 7318 23:10:01.708283  [0] AVG Duty = 4984%(X100)

 7319 23:10:01.708431  

 7320 23:10:01.708528  ==DQS 1 ==

 7321 23:10:01.711513  Final DQS duty delay cell = 0

 7322 23:10:01.714631  [0] MAX Duty = 5249%(X100), DQS PI = 16

 7323 23:10:01.718362  [0] MIN Duty = 4938%(X100), DQS PI = 8

 7324 23:10:01.721481  [0] AVG Duty = 5093%(X100)

 7325 23:10:01.721565  

 7326 23:10:01.724556  CH1 DQS 0 Duty spec in!! Max-Min= 281%

 7327 23:10:01.724641  

 7328 23:10:01.728314  CH1 DQS 1 Duty spec in!! Max-Min= 311%

 7329 23:10:01.731458  [DutyScan_Calibration_Flow] ====Done====

 7330 23:10:01.731556  

 7331 23:10:01.734696  [DutyScan_Calibration_Flow] k_type=3

 7332 23:10:01.751872  

 7333 23:10:01.752026  ==DQM 0 ==

 7334 23:10:01.755436  Final DQM duty delay cell = 0

 7335 23:10:01.758267  [0] MAX Duty = 5218%(X100), DQS PI = 18

 7336 23:10:01.761784  [0] MIN Duty = 4969%(X100), DQS PI = 48

 7337 23:10:01.761868  [0] AVG Duty = 5093%(X100)

 7338 23:10:01.765249  

 7339 23:10:01.765333  ==DQM 1 ==

 7340 23:10:01.768703  Final DQM duty delay cell = 0

 7341 23:10:01.771727  [0] MAX Duty = 5093%(X100), DQS PI = 42

 7342 23:10:01.775411  [0] MIN Duty = 4907%(X100), DQS PI = 34

 7343 23:10:01.778650  [0] AVG Duty = 5000%(X100)

 7344 23:10:01.778761  

 7345 23:10:01.782141  CH1 DQM 0 Duty spec in!! Max-Min= 249%

 7346 23:10:01.782226  

 7347 23:10:01.785284  CH1 DQM 1 Duty spec in!! Max-Min= 186%

 7348 23:10:01.788299  [DutyScan_Calibration_Flow] ====Done====

 7349 23:10:01.788418  

 7350 23:10:01.791542  [DutyScan_Calibration_Flow] k_type=2

 7351 23:10:01.807685  

 7352 23:10:01.807827  ==DQ 0 ==

 7353 23:10:01.811269  Final DQ duty delay cell = -4

 7354 23:10:01.814748  [-4] MAX Duty = 5062%(X100), DQS PI = 10

 7355 23:10:01.817913  [-4] MIN Duty = 4875%(X100), DQS PI = 46

 7356 23:10:01.821517  [-4] AVG Duty = 4968%(X100)

 7357 23:10:01.821627  

 7358 23:10:01.821723  ==DQ 1 ==

 7359 23:10:01.824658  Final DQ duty delay cell = 0

 7360 23:10:01.827899  [0] MAX Duty = 5156%(X100), DQS PI = 18

 7361 23:10:01.830969  [0] MIN Duty = 4938%(X100), DQS PI = 8

 7362 23:10:01.834597  [0] AVG Duty = 5047%(X100)

 7363 23:10:01.834701  

 7364 23:10:01.837782  CH1 DQ 0 Duty spec in!! Max-Min= 187%

 7365 23:10:01.837884  

 7366 23:10:01.841014  CH1 DQ 1 Duty spec in!! Max-Min= 218%

 7367 23:10:01.844813  [DutyScan_Calibration_Flow] ====Done====

 7368 23:10:01.847949  nWR fixed to 30

 7369 23:10:01.848059  [ModeRegInit_LP4] CH0 RK0

 7370 23:10:01.851065  [ModeRegInit_LP4] CH0 RK1

 7371 23:10:01.854695  [ModeRegInit_LP4] CH1 RK0

 7372 23:10:01.857624  [ModeRegInit_LP4] CH1 RK1

 7373 23:10:01.857729  match AC timing 5

 7374 23:10:01.864158  dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1

 7375 23:10:01.868123  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 7376 23:10:01.871216  [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14

 7377 23:10:01.877574  [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29

 7378 23:10:01.881186  [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)

 7379 23:10:01.881296  [MiockJmeterHQA]

 7380 23:10:01.881392  

 7381 23:10:01.884300  [DramcMiockJmeter] u1RxGatingPI = 0

 7382 23:10:01.887531  0 : 4255, 4027

 7383 23:10:01.887634  4 : 4252, 4027

 7384 23:10:01.891248  8 : 4363, 4138

 7385 23:10:01.891354  12 : 4252, 4027

 7386 23:10:01.891449  16 : 4364, 4137

 7387 23:10:01.894309  20 : 4253, 4027

 7388 23:10:01.894412  24 : 4253, 4026

 7389 23:10:01.897648  28 : 4252, 4027

 7390 23:10:01.897750  32 : 4254, 4029

 7391 23:10:01.901280  36 : 4253, 4026

 7392 23:10:01.901385  40 : 4363, 4138

 7393 23:10:01.904123  44 : 4363, 4137

 7394 23:10:01.904229  48 : 4252, 4027

 7395 23:10:01.904336  52 : 4252, 4027

 7396 23:10:01.907733  56 : 4252, 4027

 7397 23:10:01.907842  60 : 4253, 4029

 7398 23:10:01.910927  64 : 4254, 4029

 7399 23:10:01.911037  68 : 4361, 4137

 7400 23:10:01.914673  72 : 4250, 4027

 7401 23:10:01.914784  76 : 4250, 4027

 7402 23:10:01.914881  80 : 4250, 4027

 7403 23:10:01.917862  84 : 4252, 4027

 7404 23:10:01.917969  88 : 4250, 58

 7405 23:10:01.920906  92 : 4249, 0

 7406 23:10:01.921012  96 : 4253, 0

 7407 23:10:01.921119  100 : 4360, 0

 7408 23:10:01.924347  104 : 4361, 0

 7409 23:10:01.924426  108 : 4363, 0

 7410 23:10:01.927589  112 : 4361, 0

 7411 23:10:01.927700  116 : 4250, 0

 7412 23:10:01.927811  120 : 4250, 0

 7413 23:10:01.931069  124 : 4249, 0

 7414 23:10:01.931145  128 : 4250, 0

 7415 23:10:01.931209  132 : 4250, 0

 7416 23:10:01.934313  136 : 4252, 0

 7417 23:10:01.934420  140 : 4250, 0

 7418 23:10:01.937431  144 : 4250, 0

 7419 23:10:01.937544  148 : 4252, 0

 7420 23:10:01.937642  152 : 4250, 0

 7421 23:10:01.941309  156 : 4361, 0

 7422 23:10:01.941391  160 : 4360, 0

 7423 23:10:01.944399  164 : 4361, 0

 7424 23:10:01.944474  168 : 4250, 0

 7425 23:10:01.944543  172 : 4250, 0

 7426 23:10:01.947514  176 : 4249, 0

 7427 23:10:01.947588  180 : 4250, 0

 7428 23:10:01.950727  184 : 4250, 0

 7429 23:10:01.950833  188 : 4250, 0

 7430 23:10:01.950933  192 : 4250, 0

 7431 23:10:01.954535  196 : 4250, 0

 7432 23:10:01.954643  200 : 4252, 0

 7433 23:10:01.957819  204 : 4360, 1102

 7434 23:10:01.957924  208 : 4249, 3985

 7435 23:10:01.960831  212 : 4360, 4137

 7436 23:10:01.960908  216 : 4363, 4140

 7437 23:10:01.960978  220 : 4250, 4027

 7438 23:10:01.964430  224 : 4249, 4027

 7439 23:10:01.964529  228 : 4363, 4140

 7440 23:10:01.967440  232 : 4250, 4026

 7441 23:10:01.967549  236 : 4250, 4027

 7442 23:10:01.971057  240 : 4250, 4027

 7443 23:10:01.971168  244 : 4252, 4029

 7444 23:10:01.974219  248 : 4250, 4026

 7445 23:10:01.974321  252 : 4250, 4027

 7446 23:10:01.977824  256 : 4360, 4138

 7447 23:10:01.977932  260 : 4250, 4027

 7448 23:10:01.980837  264 : 4250, 4026

 7449 23:10:01.980926  268 : 4361, 4137

 7450 23:10:01.981020  272 : 4250, 4027

 7451 23:10:01.984215  276 : 4250, 4027

 7452 23:10:01.984339  280 : 4363, 4140

 7453 23:10:01.987476  284 : 4250, 4026

 7454 23:10:01.987551  288 : 4250, 4027

 7455 23:10:01.991222  292 : 4249, 4027

 7456 23:10:01.991329  296 : 4252, 4029

 7457 23:10:01.994399  300 : 4250, 4026

 7458 23:10:01.994507  304 : 4250, 4027

 7459 23:10:01.997499  308 : 4360, 4065

 7460 23:10:01.997575  312 : 4249, 1996

 7461 23:10:01.997639  

 7462 23:10:02.000679  	MIOCK jitter meter	ch=0

 7463 23:10:02.000777  

 7464 23:10:02.003920  1T = (312-88) = 224 dly cells

 7465 23:10:02.007594  Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps

 7466 23:10:02.010788  ==

 7467 23:10:02.014355  Dram Type= 6, Freq= 0, CH_0, rank 0

 7468 23:10:02.017192  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7469 23:10:02.017274  ==

 7470 23:10:02.021092  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7471 23:10:02.027507  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7472 23:10:02.030920  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7473 23:10:02.037392  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7474 23:10:02.045346  [CA 0] Center 43 (12~74) winsize 63

 7475 23:10:02.049184  [CA 1] Center 43 (13~74) winsize 62

 7476 23:10:02.052346  [CA 2] Center 38 (9~68) winsize 60

 7477 23:10:02.055435  [CA 3] Center 38 (8~68) winsize 61

 7478 23:10:02.058689  [CA 4] Center 37 (7~67) winsize 61

 7479 23:10:02.062470  [CA 5] Center 36 (7~65) winsize 59

 7480 23:10:02.062571  

 7481 23:10:02.065529  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7482 23:10:02.065634  

 7483 23:10:02.069090  [CATrainingPosCal] consider 1 rank data

 7484 23:10:02.072147  u2DelayCellTimex100 = 290/100 ps

 7485 23:10:02.075710  CA0 delay=43 (12~74),Diff = 7 PI (23 cell)

 7486 23:10:02.082515  CA1 delay=43 (13~74),Diff = 7 PI (23 cell)

 7487 23:10:02.085669  CA2 delay=38 (9~68),Diff = 2 PI (6 cell)

 7488 23:10:02.088821  CA3 delay=38 (8~68),Diff = 2 PI (6 cell)

 7489 23:10:02.092230  CA4 delay=37 (7~67),Diff = 1 PI (3 cell)

 7490 23:10:02.095494  CA5 delay=36 (7~65),Diff = 0 PI (0 cell)

 7491 23:10:02.095603  

 7492 23:10:02.098910  CA PerBit enable=1, Macro0, CA PI delay=36

 7493 23:10:02.099048  

 7494 23:10:02.102428  [CBTSetCACLKResult] CA Dly = 36

 7495 23:10:02.102537  CS Dly: 9 (0~40)

 7496 23:10:02.108604  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7497 23:10:02.112360  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7498 23:10:02.112457  ==

 7499 23:10:02.115620  Dram Type= 6, Freq= 0, CH_0, rank 1

 7500 23:10:02.118736  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7501 23:10:02.118847  ==

 7502 23:10:02.125983  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7503 23:10:02.129091  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7504 23:10:02.135604  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7505 23:10:02.138613  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7506 23:10:02.148659  [CA 0] Center 42 (12~73) winsize 62

 7507 23:10:02.151839  [CA 1] Center 42 (12~73) winsize 62

 7508 23:10:02.155041  [CA 2] Center 38 (8~68) winsize 61

 7509 23:10:02.158441  [CA 3] Center 37 (8~67) winsize 60

 7510 23:10:02.162056  [CA 4] Center 36 (6~66) winsize 61

 7511 23:10:02.165216  [CA 5] Center 35 (5~65) winsize 61

 7512 23:10:02.165318  

 7513 23:10:02.169061  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7514 23:10:02.169167  

 7515 23:10:02.172279  [CATrainingPosCal] consider 2 rank data

 7516 23:10:02.175360  u2DelayCellTimex100 = 290/100 ps

 7517 23:10:02.178402  CA0 delay=42 (12~73),Diff = 6 PI (20 cell)

 7518 23:10:02.184973  CA1 delay=43 (13~73),Diff = 7 PI (23 cell)

 7519 23:10:02.188169  CA2 delay=38 (9~68),Diff = 2 PI (6 cell)

 7520 23:10:02.192126  CA3 delay=37 (8~67),Diff = 1 PI (3 cell)

 7521 23:10:02.195279  CA4 delay=36 (7~66),Diff = 0 PI (0 cell)

 7522 23:10:02.198417  CA5 delay=36 (7~65),Diff = 0 PI (0 cell)

 7523 23:10:02.198520  

 7524 23:10:02.202135  CA PerBit enable=1, Macro0, CA PI delay=36

 7525 23:10:02.202241  

 7526 23:10:02.204872  [CBTSetCACLKResult] CA Dly = 36

 7527 23:10:02.208320  CS Dly: 10 (0~42)

 7528 23:10:02.211985  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7529 23:10:02.215077  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7530 23:10:02.215183  

 7531 23:10:02.218901  ----->DramcWriteLeveling(PI) begin...

 7532 23:10:02.219003  ==

 7533 23:10:02.222070  Dram Type= 6, Freq= 0, CH_0, rank 0

 7534 23:10:02.225201  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7535 23:10:02.228443  ==

 7536 23:10:02.228523  Write leveling (Byte 0): 36 => 36

 7537 23:10:02.231591  Write leveling (Byte 1): 29 => 29

 7538 23:10:02.234903  DramcWriteLeveling(PI) end<-----

 7539 23:10:02.235008  

 7540 23:10:02.235102  ==

 7541 23:10:02.238575  Dram Type= 6, Freq= 0, CH_0, rank 0

 7542 23:10:02.245000  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7543 23:10:02.245108  ==

 7544 23:10:02.248601  [Gating] SW mode calibration

 7545 23:10:02.255099  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7546 23:10:02.257997  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7547 23:10:02.265161   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7548 23:10:02.267983   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7549 23:10:02.271398   1  4  8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)

 7550 23:10:02.278512   1  4 12 | B1->B0 | 2323 3635 | 0 1 | (0 0) (0 0)

 7551 23:10:02.281557   1  4 16 | B1->B0 | 2424 3534 | 0 1 | (0 0) (1 1)

 7552 23:10:02.284711   1  4 20 | B1->B0 | 3333 3837 | 0 1 | (0 0) (1 1)

 7553 23:10:02.288241   1  4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)

 7554 23:10:02.294643   1  4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)

 7555 23:10:02.297937   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7556 23:10:02.301640   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7557 23:10:02.307912   1  5  8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)

 7558 23:10:02.311468   1  5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)

 7559 23:10:02.314540   1  5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)

 7560 23:10:02.321265   1  5 20 | B1->B0 | 2424 2424 | 0 0 | (1 0) (0 0)

 7561 23:10:02.325293   1  5 24 | B1->B0 | 2323 2727 | 0 0 | (1 0) (0 0)

 7562 23:10:02.327917   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7563 23:10:02.334993   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7564 23:10:02.338097   1  6  4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 7565 23:10:02.341412   1  6  8 | B1->B0 | 2323 3635 | 0 1 | (0 0) (0 0)

 7566 23:10:02.348158   1  6 12 | B1->B0 | 2323 4544 | 0 1 | (0 0) (0 0)

 7567 23:10:02.351290   1  6 16 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)

 7568 23:10:02.354903   1  6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)

 7569 23:10:02.361754   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7570 23:10:02.364890   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7571 23:10:02.368097   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7572 23:10:02.374996   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7573 23:10:02.377944   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7574 23:10:02.381534   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7575 23:10:02.387660   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7576 23:10:02.391310   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7577 23:10:02.394834   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7578 23:10:02.401314   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7579 23:10:02.404615   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7580 23:10:02.407738   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7581 23:10:02.414797   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7582 23:10:02.417797   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7583 23:10:02.421154   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7584 23:10:02.424500   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7585 23:10:02.431430   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7586 23:10:02.434499   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7587 23:10:02.437624   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7588 23:10:02.444652   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7589 23:10:02.447832   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7590 23:10:02.450822   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7591 23:10:02.457830   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 7592 23:10:02.460828  Total UI for P1: 0, mck2ui 16

 7593 23:10:02.464308  best dqsien dly found for B0: ( 1,  9, 10)

 7594 23:10:02.467542   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7595 23:10:02.470719   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7596 23:10:02.474604  Total UI for P1: 0, mck2ui 16

 7597 23:10:02.477528  best dqsien dly found for B1: ( 1,  9, 20)

 7598 23:10:02.481254  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 7599 23:10:02.484467  best DQS1 dly(MCK, UI, PI) = (1, 9, 20)

 7600 23:10:02.484566  

 7601 23:10:02.490948  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 7602 23:10:02.494594  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)

 7603 23:10:02.497405  [Gating] SW calibration Done

 7604 23:10:02.497506  ==

 7605 23:10:02.501512  Dram Type= 6, Freq= 0, CH_0, rank 0

 7606 23:10:02.504476  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7607 23:10:02.504576  ==

 7608 23:10:02.504669  RX Vref Scan: 0

 7609 23:10:02.504757  

 7610 23:10:02.507724  RX Vref 0 -> 0, step: 1

 7611 23:10:02.507827  

 7612 23:10:02.511116  RX Delay 0 -> 252, step: 8

 7613 23:10:02.514416  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 7614 23:10:02.517609  iDelay=200, Bit 1, Center 143 (88 ~ 199) 112

 7615 23:10:02.520898  iDelay=200, Bit 2, Center 135 (80 ~ 191) 112

 7616 23:10:02.527553  iDelay=200, Bit 3, Center 131 (80 ~ 183) 104

 7617 23:10:02.531301  iDelay=200, Bit 4, Center 139 (88 ~ 191) 104

 7618 23:10:02.534549  iDelay=200, Bit 5, Center 123 (72 ~ 175) 104

 7619 23:10:02.537479  iDelay=200, Bit 6, Center 147 (96 ~ 199) 104

 7620 23:10:02.541125  iDelay=200, Bit 7, Center 143 (96 ~ 191) 96

 7621 23:10:02.547381  iDelay=200, Bit 8, Center 119 (72 ~ 167) 96

 7622 23:10:02.551169  iDelay=200, Bit 9, Center 119 (64 ~ 175) 112

 7623 23:10:02.554187  iDelay=200, Bit 10, Center 131 (80 ~ 183) 104

 7624 23:10:02.557844  iDelay=200, Bit 11, Center 119 (64 ~ 175) 112

 7625 23:10:02.561083  iDelay=200, Bit 12, Center 135 (80 ~ 191) 112

 7626 23:10:02.567859  iDelay=200, Bit 13, Center 135 (80 ~ 191) 112

 7627 23:10:02.570821  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 7628 23:10:02.574424  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 7629 23:10:02.574522  ==

 7630 23:10:02.577713  Dram Type= 6, Freq= 0, CH_0, rank 0

 7631 23:10:02.580816  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7632 23:10:02.580938  ==

 7633 23:10:02.584504  DQS Delay:

 7634 23:10:02.584627  DQS0 = 0, DQS1 = 0

 7635 23:10:02.587766  DQM Delay:

 7636 23:10:02.587866  DQM0 = 137, DQM1 = 129

 7637 23:10:02.587964  DQ Delay:

 7638 23:10:02.594271  DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131

 7639 23:10:02.597616  DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143

 7640 23:10:02.600871  DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =119

 7641 23:10:02.603964  DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135

 7642 23:10:02.604067  

 7643 23:10:02.604185  

 7644 23:10:02.604277  ==

 7645 23:10:02.607114  Dram Type= 6, Freq= 0, CH_0, rank 0

 7646 23:10:02.610877  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7647 23:10:02.610977  ==

 7648 23:10:02.611068  

 7649 23:10:02.611156  

 7650 23:10:02.614284  	TX Vref Scan disable

 7651 23:10:02.617222   == TX Byte 0 ==

 7652 23:10:02.620571  Update DQ  dly =992 (3 ,6, 32)  DQ  OEN =(3 ,3)

 7653 23:10:02.623889  Update DQM dly =992 (3 ,6, 32)  DQM OEN =(3 ,3)

 7654 23:10:02.627115   == TX Byte 1 ==

 7655 23:10:02.630964  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 7656 23:10:02.633743  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 7657 23:10:02.633847  ==

 7658 23:10:02.637342  Dram Type= 6, Freq= 0, CH_0, rank 0

 7659 23:10:02.643830  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7660 23:10:02.643948  ==

 7661 23:10:02.655829  

 7662 23:10:02.659014  TX Vref early break, caculate TX vref

 7663 23:10:02.662599  TX Vref=16, minBit 4, minWin=22, winSum=375

 7664 23:10:02.665835  TX Vref=18, minBit 7, minWin=22, winSum=382

 7665 23:10:02.669118  TX Vref=20, minBit 3, minWin=24, winSum=398

 7666 23:10:02.672371  TX Vref=22, minBit 4, minWin=24, winSum=407

 7667 23:10:02.675924  TX Vref=24, minBit 2, minWin=24, winSum=418

 7668 23:10:02.682626  TX Vref=26, minBit 2, minWin=25, winSum=422

 7669 23:10:02.685750  TX Vref=28, minBit 2, minWin=25, winSum=423

 7670 23:10:02.688778  TX Vref=30, minBit 6, minWin=24, winSum=414

 7671 23:10:02.692498  TX Vref=32, minBit 6, minWin=23, winSum=401

 7672 23:10:02.695938  TX Vref=34, minBit 6, minWin=23, winSum=394

 7673 23:10:02.702221  [TxChooseVref] Worse bit 2, Min win 25, Win sum 423, Final Vref 28

 7674 23:10:02.702325  

 7675 23:10:02.705426  Final TX Range 0 Vref 28

 7676 23:10:02.705500  

 7677 23:10:02.705563  ==

 7678 23:10:02.708770  Dram Type= 6, Freq= 0, CH_0, rank 0

 7679 23:10:02.712039  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7680 23:10:02.712140  ==

 7681 23:10:02.712231  

 7682 23:10:02.712370  

 7683 23:10:02.715199  	TX Vref Scan disable

 7684 23:10:02.721918  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 7685 23:10:02.722006   == TX Byte 0 ==

 7686 23:10:02.725169  u2DelayCellOfst[0]=10 cells (3 PI)

 7687 23:10:02.728957  u2DelayCellOfst[1]=16 cells (5 PI)

 7688 23:10:02.731874  u2DelayCellOfst[2]=13 cells (4 PI)

 7689 23:10:02.735503  u2DelayCellOfst[3]=10 cells (3 PI)

 7690 23:10:02.738481  u2DelayCellOfst[4]=6 cells (2 PI)

 7691 23:10:02.741876  u2DelayCellOfst[5]=0 cells (0 PI)

 7692 23:10:02.745535  u2DelayCellOfst[6]=16 cells (5 PI)

 7693 23:10:02.748530  u2DelayCellOfst[7]=16 cells (5 PI)

 7694 23:10:02.751856  Update DQ  dly =990 (3 ,6, 30)  DQ  OEN =(3 ,3)

 7695 23:10:02.755064  Update DQM dly =992 (3 ,6, 32)  DQM OEN =(3 ,3)

 7696 23:10:02.758831   == TX Byte 1 ==

 7697 23:10:02.762092  u2DelayCellOfst[8]=0 cells (0 PI)

 7698 23:10:02.762217  u2DelayCellOfst[9]=0 cells (0 PI)

 7699 23:10:02.764931  u2DelayCellOfst[10]=10 cells (3 PI)

 7700 23:10:02.768296  u2DelayCellOfst[11]=6 cells (2 PI)

 7701 23:10:02.771677  u2DelayCellOfst[12]=10 cells (3 PI)

 7702 23:10:02.774986  u2DelayCellOfst[13]=10 cells (3 PI)

 7703 23:10:02.778803  u2DelayCellOfst[14]=13 cells (4 PI)

 7704 23:10:02.781835  u2DelayCellOfst[15]=10 cells (3 PI)

 7705 23:10:02.785030  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 7706 23:10:02.791969  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 7707 23:10:02.792068  DramC Write-DBI on

 7708 23:10:02.792169  ==

 7709 23:10:02.795219  Dram Type= 6, Freq= 0, CH_0, rank 0

 7710 23:10:02.798438  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7711 23:10:02.801612  ==

 7712 23:10:02.801698  

 7713 23:10:02.801786  

 7714 23:10:02.801869  	TX Vref Scan disable

 7715 23:10:02.805448   == TX Byte 0 ==

 7716 23:10:02.808731  Update DQM dly =736 (2 ,6, 32)  DQM OEN =(3 ,3)

 7717 23:10:02.811993   == TX Byte 1 ==

 7718 23:10:02.815241  Update DQM dly =724 (2 ,6, 20)  DQM OEN =(3 ,3)

 7719 23:10:02.818503  DramC Write-DBI off

 7720 23:10:02.818594  

 7721 23:10:02.818680  [DATLAT]

 7722 23:10:02.818762  Freq=1600, CH0 RK0

 7723 23:10:02.818843  

 7724 23:10:02.822317  DATLAT Default: 0xf

 7725 23:10:02.822403  0, 0xFFFF, sum = 0

 7726 23:10:02.825429  1, 0xFFFF, sum = 0

 7727 23:10:02.825517  2, 0xFFFF, sum = 0

 7728 23:10:02.828489  3, 0xFFFF, sum = 0

 7729 23:10:02.832460  4, 0xFFFF, sum = 0

 7730 23:10:02.832548  5, 0xFFFF, sum = 0

 7731 23:10:02.835640  6, 0xFFFF, sum = 0

 7732 23:10:02.835727  7, 0xFFFF, sum = 0

 7733 23:10:02.838791  8, 0xFFFF, sum = 0

 7734 23:10:02.838879  9, 0xFFFF, sum = 0

 7735 23:10:02.842028  10, 0xFFFF, sum = 0

 7736 23:10:02.842116  11, 0xFFFF, sum = 0

 7737 23:10:02.845122  12, 0xFFFF, sum = 0

 7738 23:10:02.845249  13, 0xFFFF, sum = 0

 7739 23:10:02.848915  14, 0x0, sum = 1

 7740 23:10:02.849042  15, 0x0, sum = 2

 7741 23:10:02.852020  16, 0x0, sum = 3

 7742 23:10:02.852107  17, 0x0, sum = 4

 7743 23:10:02.855079  best_step = 15

 7744 23:10:02.855205  

 7745 23:10:02.855321  ==

 7746 23:10:02.858523  Dram Type= 6, Freq= 0, CH_0, rank 0

 7747 23:10:02.862141  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7748 23:10:02.862262  ==

 7749 23:10:02.862375  RX Vref Scan: 1

 7750 23:10:02.865082  

 7751 23:10:02.865207  Set Vref Range= 24 -> 127

 7752 23:10:02.865318  

 7753 23:10:02.868342  RX Vref 24 -> 127, step: 1

 7754 23:10:02.868456  

 7755 23:10:02.872215  RX Delay 19 -> 252, step: 4

 7756 23:10:02.872344  

 7757 23:10:02.875087  Set Vref, RX VrefLevel [Byte0]: 24

 7758 23:10:02.878311                           [Byte1]: 24

 7759 23:10:02.878432  

 7760 23:10:02.881723  Set Vref, RX VrefLevel [Byte0]: 25

 7761 23:10:02.884673                           [Byte1]: 25

 7762 23:10:02.884792  

 7763 23:10:02.888564  Set Vref, RX VrefLevel [Byte0]: 26

 7764 23:10:02.891466                           [Byte1]: 26

 7765 23:10:02.895448  

 7766 23:10:02.895571  Set Vref, RX VrefLevel [Byte0]: 27

 7767 23:10:02.899287                           [Byte1]: 27

 7768 23:10:02.903378  

 7769 23:10:02.903527  Set Vref, RX VrefLevel [Byte0]: 28

 7770 23:10:02.906447                           [Byte1]: 28

 7771 23:10:02.910850  

 7772 23:10:02.910963  Set Vref, RX VrefLevel [Byte0]: 29

 7773 23:10:02.914106                           [Byte1]: 29

 7774 23:10:02.918640  

 7775 23:10:02.918727  Set Vref, RX VrefLevel [Byte0]: 30

 7776 23:10:02.921887                           [Byte1]: 30

 7777 23:10:02.926207  

 7778 23:10:02.926295  Set Vref, RX VrefLevel [Byte0]: 31

 7779 23:10:02.929395                           [Byte1]: 31

 7780 23:10:02.933434  

 7781 23:10:02.933518  Set Vref, RX VrefLevel [Byte0]: 32

 7782 23:10:02.936607                           [Byte1]: 32

 7783 23:10:02.941183  

 7784 23:10:02.941267  Set Vref, RX VrefLevel [Byte0]: 33

 7785 23:10:02.944071                           [Byte1]: 33

 7786 23:10:02.948451  

 7787 23:10:02.948552  Set Vref, RX VrefLevel [Byte0]: 34

 7788 23:10:02.951846                           [Byte1]: 34

 7789 23:10:02.956232  

 7790 23:10:02.956356  Set Vref, RX VrefLevel [Byte0]: 35

 7791 23:10:02.959477                           [Byte1]: 35

 7792 23:10:02.963736  

 7793 23:10:02.963837  Set Vref, RX VrefLevel [Byte0]: 36

 7794 23:10:02.967280                           [Byte1]: 36

 7795 23:10:02.971773  

 7796 23:10:02.971856  Set Vref, RX VrefLevel [Byte0]: 37

 7797 23:10:02.974960                           [Byte1]: 37

 7798 23:10:02.978824  

 7799 23:10:02.978908  Set Vref, RX VrefLevel [Byte0]: 38

 7800 23:10:02.982423                           [Byte1]: 38

 7801 23:10:02.986894  

 7802 23:10:02.986978  Set Vref, RX VrefLevel [Byte0]: 39

 7803 23:10:02.989661                           [Byte1]: 39

 7804 23:10:02.994103  

 7805 23:10:02.994188  Set Vref, RX VrefLevel [Byte0]: 40

 7806 23:10:02.997403                           [Byte1]: 40

 7807 23:10:03.001434  

 7808 23:10:03.001523  Set Vref, RX VrefLevel [Byte0]: 41

 7809 23:10:03.004928                           [Byte1]: 41

 7810 23:10:03.009495  

 7811 23:10:03.009580  Set Vref, RX VrefLevel [Byte0]: 42

 7812 23:10:03.012301                           [Byte1]: 42

 7813 23:10:03.017243  

 7814 23:10:03.017341  Set Vref, RX VrefLevel [Byte0]: 43

 7815 23:10:03.020270                           [Byte1]: 43

 7816 23:10:03.024253  

 7817 23:10:03.024370  Set Vref, RX VrefLevel [Byte0]: 44

 7818 23:10:03.027537                           [Byte1]: 44

 7819 23:10:03.031850  

 7820 23:10:03.031936  Set Vref, RX VrefLevel [Byte0]: 45

 7821 23:10:03.035273                           [Byte1]: 45

 7822 23:10:03.039546  

 7823 23:10:03.039630  Set Vref, RX VrefLevel [Byte0]: 46

 7824 23:10:03.042640                           [Byte1]: 46

 7825 23:10:03.047150  

 7826 23:10:03.047231  Set Vref, RX VrefLevel [Byte0]: 47

 7827 23:10:03.050367                           [Byte1]: 47

 7828 23:10:03.054703  

 7829 23:10:03.054785  Set Vref, RX VrefLevel [Byte0]: 48

 7830 23:10:03.057862                           [Byte1]: 48

 7831 23:10:03.062497  

 7832 23:10:03.062593  Set Vref, RX VrefLevel [Byte0]: 49

 7833 23:10:03.065706                           [Byte1]: 49

 7834 23:10:03.070121  

 7835 23:10:03.070203  Set Vref, RX VrefLevel [Byte0]: 50

 7836 23:10:03.073021                           [Byte1]: 50

 7837 23:10:03.077585  

 7838 23:10:03.077692  Set Vref, RX VrefLevel [Byte0]: 51

 7839 23:10:03.080693                           [Byte1]: 51

 7840 23:10:03.084830  

 7841 23:10:03.084918  Set Vref, RX VrefLevel [Byte0]: 52

 7842 23:10:03.088432                           [Byte1]: 52

 7843 23:10:03.092310  

 7844 23:10:03.092423  Set Vref, RX VrefLevel [Byte0]: 53

 7845 23:10:03.095902                           [Byte1]: 53

 7846 23:10:03.100086  

 7847 23:10:03.100186  Set Vref, RX VrefLevel [Byte0]: 54

 7848 23:10:03.103451                           [Byte1]: 54

 7849 23:10:03.107435  

 7850 23:10:03.107539  Set Vref, RX VrefLevel [Byte0]: 55

 7851 23:10:03.110906                           [Byte1]: 55

 7852 23:10:03.115068  

 7853 23:10:03.115143  Set Vref, RX VrefLevel [Byte0]: 56

 7854 23:10:03.118670                           [Byte1]: 56

 7855 23:10:03.122854  

 7856 23:10:03.122956  Set Vref, RX VrefLevel [Byte0]: 57

 7857 23:10:03.126216                           [Byte1]: 57

 7858 23:10:03.130778  

 7859 23:10:03.130912  Set Vref, RX VrefLevel [Byte0]: 58

 7860 23:10:03.134036                           [Byte1]: 58

 7861 23:10:03.137908  

 7862 23:10:03.138027  Set Vref, RX VrefLevel [Byte0]: 59

 7863 23:10:03.141194                           [Byte1]: 59

 7864 23:10:03.145387  

 7865 23:10:03.145503  Set Vref, RX VrefLevel [Byte0]: 60

 7866 23:10:03.149115                           [Byte1]: 60

 7867 23:10:03.152988  

 7868 23:10:03.153091  Set Vref, RX VrefLevel [Byte0]: 61

 7869 23:10:03.156092                           [Byte1]: 61

 7870 23:10:03.160471  

 7871 23:10:03.160580  Set Vref, RX VrefLevel [Byte0]: 62

 7872 23:10:03.164259                           [Byte1]: 62

 7873 23:10:03.168136  

 7874 23:10:03.168237  Set Vref, RX VrefLevel [Byte0]: 63

 7875 23:10:03.171389                           [Byte1]: 63

 7876 23:10:03.175699  

 7877 23:10:03.175792  Set Vref, RX VrefLevel [Byte0]: 64

 7878 23:10:03.179219                           [Byte1]: 64

 7879 23:10:03.183734  

 7880 23:10:03.183815  Set Vref, RX VrefLevel [Byte0]: 65

 7881 23:10:03.186921                           [Byte1]: 65

 7882 23:10:03.191340  

 7883 23:10:03.191421  Set Vref, RX VrefLevel [Byte0]: 66

 7884 23:10:03.194210                           [Byte1]: 66

 7885 23:10:03.198689  

 7886 23:10:03.198781  Set Vref, RX VrefLevel [Byte0]: 67

 7887 23:10:03.201940                           [Byte1]: 67

 7888 23:10:03.206262  

 7889 23:10:03.206350  Set Vref, RX VrefLevel [Byte0]: 68

 7890 23:10:03.209481                           [Byte1]: 68

 7891 23:10:03.213685  

 7892 23:10:03.213799  Set Vref, RX VrefLevel [Byte0]: 69

 7893 23:10:03.217232                           [Byte1]: 69

 7894 23:10:03.221232  

 7895 23:10:03.221313  Set Vref, RX VrefLevel [Byte0]: 70

 7896 23:10:03.224535                           [Byte1]: 70

 7897 23:10:03.228640  

 7898 23:10:03.228731  Set Vref, RX VrefLevel [Byte0]: 71

 7899 23:10:03.231996                           [Byte1]: 71

 7900 23:10:03.236492  

 7901 23:10:03.236574  Set Vref, RX VrefLevel [Byte0]: 72

 7902 23:10:03.239593                           [Byte1]: 72

 7903 23:10:03.243915  

 7904 23:10:03.244023  Set Vref, RX VrefLevel [Byte0]: 73

 7905 23:10:03.247144                           [Byte1]: 73

 7906 23:10:03.251489  

 7907 23:10:03.251571  Set Vref, RX VrefLevel [Byte0]: 74

 7908 23:10:03.254561                           [Byte1]: 74

 7909 23:10:03.259049  

 7910 23:10:03.259164  Set Vref, RX VrefLevel [Byte0]: 75

 7911 23:10:03.262183                           [Byte1]: 75

 7912 23:10:03.266628  

 7913 23:10:03.266724  Final RX Vref Byte 0 = 58 to rank0

 7914 23:10:03.269767  Final RX Vref Byte 1 = 55 to rank0

 7915 23:10:03.273565  Final RX Vref Byte 0 = 58 to rank1

 7916 23:10:03.276659  Final RX Vref Byte 1 = 55 to rank1==

 7917 23:10:03.279851  Dram Type= 6, Freq= 0, CH_0, rank 0

 7918 23:10:03.286473  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7919 23:10:03.286553  ==

 7920 23:10:03.286617  DQS Delay:

 7921 23:10:03.286682  DQS0 = 0, DQS1 = 0

 7922 23:10:03.290283  DQM Delay:

 7923 23:10:03.290370  DQM0 = 134, DQM1 = 127

 7924 23:10:03.293400  DQ Delay:

 7925 23:10:03.296570  DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132

 7926 23:10:03.299640  DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138

 7927 23:10:03.303371  DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120

 7928 23:10:03.306531  DQ12 =130, DQ13 =132, DQ14 =138, DQ15 =136

 7929 23:10:03.306619  

 7930 23:10:03.306756  

 7931 23:10:03.306818  

 7932 23:10:03.310077  [DramC_TX_OE_Calibration] TA2

 7933 23:10:03.313368  Original DQ_B0 (3 6) =30, OEN = 27

 7934 23:10:03.316464  Original DQ_B1 (3 6) =30, OEN = 27

 7935 23:10:03.319614  24, 0x0, End_B0=24 End_B1=24

 7936 23:10:03.319703  25, 0x0, End_B0=25 End_B1=25

 7937 23:10:03.323491  26, 0x0, End_B0=26 End_B1=26

 7938 23:10:03.326681  27, 0x0, End_B0=27 End_B1=27

 7939 23:10:03.330146  28, 0x0, End_B0=28 End_B1=28

 7940 23:10:03.330233  29, 0x0, End_B0=29 End_B1=29

 7941 23:10:03.333434  30, 0x0, End_B0=30 End_B1=30

 7942 23:10:03.336925  31, 0x4141, End_B0=30 End_B1=30

 7943 23:10:03.339718  Byte0 end_step=30  best_step=27

 7944 23:10:03.343319  Byte1 end_step=30  best_step=27

 7945 23:10:03.346347  Byte0 TX OE(2T, 0.5T) = (3, 3)

 7946 23:10:03.346473  Byte1 TX OE(2T, 0.5T) = (3, 3)

 7947 23:10:03.349860  

 7948 23:10:03.349959  

 7949 23:10:03.356136  [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps

 7950 23:10:03.359695  CH0 RK0: MR19=303, MR18=2521

 7951 23:10:03.366680  CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16

 7952 23:10:03.366791  

 7953 23:10:03.369613  ----->DramcWriteLeveling(PI) begin...

 7954 23:10:03.369688  ==

 7955 23:10:03.373123  Dram Type= 6, Freq= 0, CH_0, rank 1

 7956 23:10:03.376396  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7957 23:10:03.376480  ==

 7958 23:10:03.379572  Write leveling (Byte 0): 34 => 34

 7959 23:10:03.382842  Write leveling (Byte 1): 27 => 27

 7960 23:10:03.386836  DramcWriteLeveling(PI) end<-----

 7961 23:10:03.386950  

 7962 23:10:03.387014  ==

 7963 23:10:03.389710  Dram Type= 6, Freq= 0, CH_0, rank 1

 7964 23:10:03.393488  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7965 23:10:03.393571  ==

 7966 23:10:03.396469  [Gating] SW mode calibration

 7967 23:10:03.403373  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7968 23:10:03.409537  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7969 23:10:03.413281   1  4  0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 7970 23:10:03.416420   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7971 23:10:03.422833   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7972 23:10:03.426696   1  4 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)

 7973 23:10:03.429878   1  4 16 | B1->B0 | 3030 3535 | 0 1 | (0 0) (0 0)

 7974 23:10:03.436127   1  4 20 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)

 7975 23:10:03.439813   1  4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)

 7976 23:10:03.443265   1  4 28 | B1->B0 | 3434 3938 | 1 1 | (1 1) (0 0)

 7977 23:10:03.449460   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7978 23:10:03.452876   1  5  4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)

 7979 23:10:03.456232   1  5  8 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)

 7980 23:10:03.463254   1  5 12 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 0)

 7981 23:10:03.466459   1  5 16 | B1->B0 | 3030 2626 | 0 1 | (1 0) (1 0)

 7982 23:10:03.469556   1  5 20 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)

 7983 23:10:03.476032   1  5 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 7984 23:10:03.479744   1  5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 7985 23:10:03.482841   1  6  0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)

 7986 23:10:03.489968   1  6  4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 7987 23:10:03.493018   1  6  8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 7988 23:10:03.496555   1  6 12 | B1->B0 | 2323 3837 | 0 1 | (0 0) (0 0)

 7989 23:10:03.499372   1  6 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)

 7990 23:10:03.506155   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7991 23:10:03.509194   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7992 23:10:03.512874   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7993 23:10:03.519730   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7994 23:10:03.522894   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7995 23:10:03.526207   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7996 23:10:03.532750   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7997 23:10:03.535926   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 7998 23:10:03.539186   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7999 23:10:03.546313   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8000 23:10:03.549503   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8001 23:10:03.552530   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8002 23:10:03.559034   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8003 23:10:03.562385   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8004 23:10:03.565768   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8005 23:10:03.572498   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8006 23:10:03.576080   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8007 23:10:03.579347   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8008 23:10:03.585779   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8009 23:10:03.589006   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8010 23:10:03.592525   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8011 23:10:03.599567   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8012 23:10:03.602696   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8013 23:10:03.605738   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8014 23:10:03.609207  Total UI for P1: 0, mck2ui 16

 8015 23:10:03.612209  best dqsien dly found for B0: ( 1,  9, 12)

 8016 23:10:03.615984  Total UI for P1: 0, mck2ui 16

 8017 23:10:03.619057  best dqsien dly found for B1: ( 1,  9, 12)

 8018 23:10:03.622614  best DQS0 dly(MCK, UI, PI) = (1, 9, 12)

 8019 23:10:03.625583  best DQS1 dly(MCK, UI, PI) = (1, 9, 12)

 8020 23:10:03.625706  

 8021 23:10:03.628801  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)

 8022 23:10:03.635916  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)

 8023 23:10:03.636039  [Gating] SW calibration Done

 8024 23:10:03.636150  ==

 8025 23:10:03.639172  Dram Type= 6, Freq= 0, CH_0, rank 1

 8026 23:10:03.645726  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8027 23:10:03.645844  ==

 8028 23:10:03.645952  RX Vref Scan: 0

 8029 23:10:03.646061  

 8030 23:10:03.648991  RX Vref 0 -> 0, step: 1

 8031 23:10:03.649112  

 8032 23:10:03.652738  RX Delay 0 -> 252, step: 8

 8033 23:10:03.655802  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 8034 23:10:03.659262  iDelay=200, Bit 1, Center 139 (88 ~ 191) 104

 8035 23:10:03.662511  iDelay=200, Bit 2, Center 135 (80 ~ 191) 112

 8036 23:10:03.669199  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 8037 23:10:03.672126  iDelay=200, Bit 4, Center 139 (88 ~ 191) 104

 8038 23:10:03.675587  iDelay=200, Bit 5, Center 127 (72 ~ 183) 112

 8039 23:10:03.678869  iDelay=200, Bit 6, Center 143 (88 ~ 199) 112

 8040 23:10:03.682078  iDelay=200, Bit 7, Center 143 (88 ~ 199) 112

 8041 23:10:03.688604  iDelay=200, Bit 8, Center 119 (64 ~ 175) 112

 8042 23:10:03.692224  iDelay=200, Bit 9, Center 119 (64 ~ 175) 112

 8043 23:10:03.695877  iDelay=200, Bit 10, Center 127 (72 ~ 183) 112

 8044 23:10:03.698805  iDelay=200, Bit 11, Center 119 (64 ~ 175) 112

 8045 23:10:03.702279  iDelay=200, Bit 12, Center 135 (80 ~ 191) 112

 8046 23:10:03.709117  iDelay=200, Bit 13, Center 135 (80 ~ 191) 112

 8047 23:10:03.712273  iDelay=200, Bit 14, Center 135 (80 ~ 191) 112

 8048 23:10:03.715211  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 8049 23:10:03.715293  ==

 8050 23:10:03.718597  Dram Type= 6, Freq= 0, CH_0, rank 1

 8051 23:10:03.722265  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8052 23:10:03.722347  ==

 8053 23:10:03.725497  DQS Delay:

 8054 23:10:03.725579  DQS0 = 0, DQS1 = 0

 8055 23:10:03.728909  DQM Delay:

 8056 23:10:03.729002  DQM0 = 137, DQM1 = 128

 8057 23:10:03.731787  DQ Delay:

 8058 23:10:03.734901  DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135

 8059 23:10:03.738734  DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143

 8060 23:10:03.741936  DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119

 8061 23:10:03.745242  DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135

 8062 23:10:03.745362  

 8063 23:10:03.745465  

 8064 23:10:03.745597  ==

 8065 23:10:03.748439  Dram Type= 6, Freq= 0, CH_0, rank 1

 8066 23:10:03.751590  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8067 23:10:03.751672  ==

 8068 23:10:03.751772  

 8069 23:10:03.751872  

 8070 23:10:03.754873  	TX Vref Scan disable

 8071 23:10:03.758119   == TX Byte 0 ==

 8072 23:10:03.761900  Update DQ  dly =991 (3 ,6, 31)  DQ  OEN =(3 ,3)

 8073 23:10:03.764931  Update DQM dly =991 (3 ,6, 31)  DQM OEN =(3 ,3)

 8074 23:10:03.768085   == TX Byte 1 ==

 8075 23:10:03.771895  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8076 23:10:03.774920  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8077 23:10:03.775022  ==

 8078 23:10:03.778379  Dram Type= 6, Freq= 0, CH_0, rank 1

 8079 23:10:03.784594  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8080 23:10:03.784714  ==

 8081 23:10:03.798456  

 8082 23:10:03.801533  TX Vref early break, caculate TX vref

 8083 23:10:03.805270  TX Vref=16, minBit 1, minWin=22, winSum=389

 8084 23:10:03.808209  TX Vref=18, minBit 1, minWin=24, winSum=397

 8085 23:10:03.811669  TX Vref=20, minBit 1, minWin=24, winSum=410

 8086 23:10:03.815005  TX Vref=22, minBit 1, minWin=24, winSum=413

 8087 23:10:03.818111  TX Vref=24, minBit 1, minWin=25, winSum=425

 8088 23:10:03.824621  TX Vref=26, minBit 1, minWin=25, winSum=426

 8089 23:10:03.828113  TX Vref=28, minBit 6, minWin=25, winSum=425

 8090 23:10:03.831300  TX Vref=30, minBit 0, minWin=25, winSum=415

 8091 23:10:03.834967  TX Vref=32, minBit 0, minWin=25, winSum=410

 8092 23:10:03.837962  TX Vref=34, minBit 0, minWin=25, winSum=405

 8093 23:10:03.841454  TX Vref=36, minBit 0, minWin=23, winSum=392

 8094 23:10:03.848409  [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 26

 8095 23:10:03.848519  

 8096 23:10:03.851533  Final TX Range 0 Vref 26

 8097 23:10:03.851611  

 8098 23:10:03.851694  ==

 8099 23:10:03.854679  Dram Type= 6, Freq= 0, CH_0, rank 1

 8100 23:10:03.857871  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8101 23:10:03.857977  ==

 8102 23:10:03.858079  

 8103 23:10:03.861248  

 8104 23:10:03.861353  	TX Vref Scan disable

 8105 23:10:03.867926  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 8106 23:10:03.868034   == TX Byte 0 ==

 8107 23:10:03.871534  u2DelayCellOfst[0]=13 cells (4 PI)

 8108 23:10:03.874816  u2DelayCellOfst[1]=13 cells (4 PI)

 8109 23:10:03.878021  u2DelayCellOfst[2]=10 cells (3 PI)

 8110 23:10:03.881169  u2DelayCellOfst[3]=10 cells (3 PI)

 8111 23:10:03.884600  u2DelayCellOfst[4]=6 cells (2 PI)

 8112 23:10:03.888157  u2DelayCellOfst[5]=0 cells (0 PI)

 8113 23:10:03.891048  u2DelayCellOfst[6]=16 cells (5 PI)

 8114 23:10:03.894418  u2DelayCellOfst[7]=13 cells (4 PI)

 8115 23:10:03.898171  Update DQ  dly =989 (3 ,6, 29)  DQ  OEN =(3 ,3)

 8116 23:10:03.901182  Update DQM dly =991 (3 ,6, 31)  DQM OEN =(3 ,3)

 8117 23:10:03.904310   == TX Byte 1 ==

 8118 23:10:03.908032  u2DelayCellOfst[8]=3 cells (1 PI)

 8119 23:10:03.911139  u2DelayCellOfst[9]=0 cells (0 PI)

 8120 23:10:03.911243  u2DelayCellOfst[10]=6 cells (2 PI)

 8121 23:10:03.914277  u2DelayCellOfst[11]=3 cells (1 PI)

 8122 23:10:03.918089  u2DelayCellOfst[12]=10 cells (3 PI)

 8123 23:10:03.921218  u2DelayCellOfst[13]=10 cells (3 PI)

 8124 23:10:03.924637  u2DelayCellOfst[14]=13 cells (4 PI)

 8125 23:10:03.928020  u2DelayCellOfst[15]=10 cells (3 PI)

 8126 23:10:03.934394  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8127 23:10:03.937950  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8128 23:10:03.938060  DramC Write-DBI on

 8129 23:10:03.938163  ==

 8130 23:10:03.941226  Dram Type= 6, Freq= 0, CH_0, rank 1

 8131 23:10:03.947594  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8132 23:10:03.947676  ==

 8133 23:10:03.947781  

 8134 23:10:03.947882  

 8135 23:10:03.947981  	TX Vref Scan disable

 8136 23:10:03.952038   == TX Byte 0 ==

 8137 23:10:03.954988  Update DQM dly =735 (2 ,6, 31)  DQM OEN =(3 ,3)

 8138 23:10:03.958296   == TX Byte 1 ==

 8139 23:10:03.962106  Update DQM dly =722 (2 ,6, 18)  DQM OEN =(3 ,3)

 8140 23:10:03.965328  DramC Write-DBI off

 8141 23:10:03.965436  

 8142 23:10:03.965542  [DATLAT]

 8143 23:10:03.965632  Freq=1600, CH0 RK1

 8144 23:10:03.965727  

 8145 23:10:03.968512  DATLAT Default: 0xf

 8146 23:10:03.968607  0, 0xFFFF, sum = 0

 8147 23:10:03.971551  1, 0xFFFF, sum = 0

 8148 23:10:03.971626  2, 0xFFFF, sum = 0

 8149 23:10:03.975284  3, 0xFFFF, sum = 0

 8150 23:10:03.978253  4, 0xFFFF, sum = 0

 8151 23:10:03.978355  5, 0xFFFF, sum = 0

 8152 23:10:03.981495  6, 0xFFFF, sum = 0

 8153 23:10:03.981602  7, 0xFFFF, sum = 0

 8154 23:10:03.985393  8, 0xFFFF, sum = 0

 8155 23:10:03.985498  9, 0xFFFF, sum = 0

 8156 23:10:03.988617  10, 0xFFFF, sum = 0

 8157 23:10:03.988691  11, 0xFFFF, sum = 0

 8158 23:10:03.991730  12, 0xFFFF, sum = 0

 8159 23:10:03.991881  13, 0xFFFF, sum = 0

 8160 23:10:03.995486  14, 0x0, sum = 1

 8161 23:10:03.995583  15, 0x0, sum = 2

 8162 23:10:03.998474  16, 0x0, sum = 3

 8163 23:10:03.998581  17, 0x0, sum = 4

 8164 23:10:04.001920  best_step = 15

 8165 23:10:04.002000  

 8166 23:10:04.002068  ==

 8167 23:10:04.004908  Dram Type= 6, Freq= 0, CH_0, rank 1

 8168 23:10:04.008422  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8169 23:10:04.008502  ==

 8170 23:10:04.008566  RX Vref Scan: 0

 8171 23:10:04.011575  

 8172 23:10:04.011648  RX Vref 0 -> 0, step: 1

 8173 23:10:04.011709  

 8174 23:10:04.015187  RX Delay 19 -> 252, step: 4

 8175 23:10:04.018376  iDelay=191, Bit 0, Center 134 (83 ~ 186) 104

 8176 23:10:04.024807  iDelay=191, Bit 1, Center 138 (91 ~ 186) 96

 8177 23:10:04.028010  iDelay=191, Bit 2, Center 130 (79 ~ 182) 104

 8178 23:10:04.031218  iDelay=191, Bit 3, Center 134 (83 ~ 186) 104

 8179 23:10:04.034638  iDelay=191, Bit 4, Center 136 (87 ~ 186) 100

 8180 23:10:04.038095  iDelay=191, Bit 5, Center 128 (75 ~ 182) 108

 8181 23:10:04.044466  iDelay=191, Bit 6, Center 140 (91 ~ 190) 100

 8182 23:10:04.047824  iDelay=191, Bit 7, Center 140 (91 ~ 190) 100

 8183 23:10:04.051205  iDelay=191, Bit 8, Center 118 (67 ~ 170) 104

 8184 23:10:04.054862  iDelay=191, Bit 9, Center 116 (63 ~ 170) 108

 8185 23:10:04.057736  iDelay=191, Bit 10, Center 128 (79 ~ 178) 100

 8186 23:10:04.064461  iDelay=191, Bit 11, Center 118 (67 ~ 170) 104

 8187 23:10:04.067827  iDelay=191, Bit 12, Center 132 (83 ~ 182) 100

 8188 23:10:04.070947  iDelay=191, Bit 13, Center 132 (79 ~ 186) 108

 8189 23:10:04.074197  iDelay=191, Bit 14, Center 136 (83 ~ 190) 108

 8190 23:10:04.080838  iDelay=191, Bit 15, Center 134 (83 ~ 186) 104

 8191 23:10:04.080917  ==

 8192 23:10:04.084538  Dram Type= 6, Freq= 0, CH_0, rank 1

 8193 23:10:04.087784  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8194 23:10:04.087886  ==

 8195 23:10:04.087981  DQS Delay:

 8196 23:10:04.090947  DQS0 = 0, DQS1 = 0

 8197 23:10:04.091046  DQM Delay:

 8198 23:10:04.094138  DQM0 = 135, DQM1 = 126

 8199 23:10:04.094239  DQ Delay:

 8200 23:10:04.097868  DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134

 8201 23:10:04.106898  DQ4 =136, DQ5 =128, DQ6 =140, DQ7 =140

 8202 23:10:04.107068  DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118

 8203 23:10:04.108000  DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =134

 8204 23:10:04.108099  

 8205 23:10:04.108203  

 8206 23:10:04.108322  

 8207 23:10:04.110927  [DramC_TX_OE_Calibration] TA2

 8208 23:10:04.114379  Original DQ_B0 (3 6) =30, OEN = 27

 8209 23:10:04.117870  Original DQ_B1 (3 6) =30, OEN = 27

 8210 23:10:04.121262  24, 0x0, End_B0=24 End_B1=24

 8211 23:10:04.124216  25, 0x0, End_B0=25 End_B1=25

 8212 23:10:04.124336  26, 0x0, End_B0=26 End_B1=26

 8213 23:10:04.127557  27, 0x0, End_B0=27 End_B1=27

 8214 23:10:04.130804  28, 0x0, End_B0=28 End_B1=28

 8215 23:10:04.134663  29, 0x0, End_B0=29 End_B1=29

 8216 23:10:04.137791  30, 0x0, End_B0=30 End_B1=30

 8217 23:10:04.137895  31, 0x4141, End_B0=30 End_B1=30

 8218 23:10:04.141056  Byte0 end_step=30  best_step=27

 8219 23:10:04.144223  Byte1 end_step=30  best_step=27

 8220 23:10:04.147850  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8221 23:10:04.150761  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8222 23:10:04.150862  

 8223 23:10:04.150953  

 8224 23:10:04.157762  [DQSOSCAuto] RK1, (LSB)MR18= 0x1f08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps

 8225 23:10:04.161025  CH0 RK1: MR19=303, MR18=1F08

 8226 23:10:04.167246  CH0_RK1: MR19=0x303, MR18=0x1F08, DQSOSC=394, MR23=63, INC=23, DEC=15

 8227 23:10:04.170529  [RxdqsGatingPostProcess] freq 1600

 8228 23:10:04.177113  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 8229 23:10:04.177222  best DQS0 dly(2T, 0.5T) = (1, 1)

 8230 23:10:04.180352  best DQS1 dly(2T, 0.5T) = (1, 1)

 8231 23:10:04.184199  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8232 23:10:04.187224  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8233 23:10:04.190930  best DQS0 dly(2T, 0.5T) = (1, 1)

 8234 23:10:04.194236  best DQS1 dly(2T, 0.5T) = (1, 1)

 8235 23:10:04.197376  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8236 23:10:04.200469  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8237 23:10:04.203616  Pre-setting of DQS Precalculation

 8238 23:10:04.206935  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 8239 23:10:04.207041  ==

 8240 23:10:04.211044  Dram Type= 6, Freq= 0, CH_1, rank 0

 8241 23:10:04.217347  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8242 23:10:04.217452  ==

 8243 23:10:04.220350  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8244 23:10:04.227623  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8245 23:10:04.230876  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8246 23:10:04.237440  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8247 23:10:04.244572  [CA 0] Center 42 (13~72) winsize 60

 8248 23:10:04.248221  [CA 1] Center 42 (13~72) winsize 60

 8249 23:10:04.251505  [CA 2] Center 39 (10~68) winsize 59

 8250 23:10:04.254627  [CA 3] Center 38 (9~67) winsize 59

 8251 23:10:04.258260  [CA 4] Center 38 (9~68) winsize 60

 8252 23:10:04.261310  [CA 5] Center 37 (8~67) winsize 60

 8253 23:10:04.261429  

 8254 23:10:04.264433  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8255 23:10:04.264507  

 8256 23:10:04.268204  [CATrainingPosCal] consider 1 rank data

 8257 23:10:04.271198  u2DelayCellTimex100 = 290/100 ps

 8258 23:10:04.274684  CA0 delay=42 (13~72),Diff = 5 PI (16 cell)

 8259 23:10:04.281385  CA1 delay=42 (13~72),Diff = 5 PI (16 cell)

 8260 23:10:04.284633  CA2 delay=39 (10~68),Diff = 2 PI (6 cell)

 8261 23:10:04.288014  CA3 delay=38 (9~67),Diff = 1 PI (3 cell)

 8262 23:10:04.291506  CA4 delay=38 (9~68),Diff = 1 PI (3 cell)

 8263 23:10:04.294447  CA5 delay=37 (8~67),Diff = 0 PI (0 cell)

 8264 23:10:04.294549  

 8265 23:10:04.298070  CA PerBit enable=1, Macro0, CA PI delay=37

 8266 23:10:04.298189  

 8267 23:10:04.301582  [CBTSetCACLKResult] CA Dly = 37

 8268 23:10:04.304712  CS Dly: 11 (0~42)

 8269 23:10:04.308403  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8270 23:10:04.311588  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8271 23:10:04.311691  ==

 8272 23:10:04.314853  Dram Type= 6, Freq= 0, CH_1, rank 1

 8273 23:10:04.318009  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8274 23:10:04.321819  ==

 8275 23:10:04.324916  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8276 23:10:04.327882  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8277 23:10:04.334959  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8278 23:10:04.337916  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8279 23:10:04.348542  [CA 0] Center 42 (13~72) winsize 60

 8280 23:10:04.351732  [CA 1] Center 42 (13~72) winsize 60

 8281 23:10:04.354830  [CA 2] Center 39 (10~69) winsize 60

 8282 23:10:04.358034  [CA 3] Center 38 (9~68) winsize 60

 8283 23:10:04.361275  [CA 4] Center 39 (10~69) winsize 60

 8284 23:10:04.364952  [CA 5] Center 38 (9~68) winsize 60

 8285 23:10:04.365027  

 8286 23:10:04.367907  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 8287 23:10:04.368053  

 8288 23:10:04.374503  [CATrainingPosCal] consider 2 rank data

 8289 23:10:04.374632  u2DelayCellTimex100 = 290/100 ps

 8290 23:10:04.381277  CA0 delay=42 (13~72),Diff = 4 PI (13 cell)

 8291 23:10:04.384939  CA1 delay=42 (13~72),Diff = 4 PI (13 cell)

 8292 23:10:04.387980  CA2 delay=39 (10~68),Diff = 1 PI (3 cell)

 8293 23:10:04.391432  CA3 delay=38 (9~67),Diff = 0 PI (0 cell)

 8294 23:10:04.394573  CA4 delay=39 (10~68),Diff = 1 PI (3 cell)

 8295 23:10:04.398128  CA5 delay=38 (9~67),Diff = 0 PI (0 cell)

 8296 23:10:04.398234  

 8297 23:10:04.401204  CA PerBit enable=1, Macro0, CA PI delay=38

 8298 23:10:04.401280  

 8299 23:10:04.404581  [CBTSetCACLKResult] CA Dly = 38

 8300 23:10:04.407961  CS Dly: 12 (0~44)

 8301 23:10:04.411123  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8302 23:10:04.414562  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8303 23:10:04.414668  

 8304 23:10:04.417839  ----->DramcWriteLeveling(PI) begin...

 8305 23:10:04.417949  ==

 8306 23:10:04.421262  Dram Type= 6, Freq= 0, CH_1, rank 0

 8307 23:10:04.427766  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8308 23:10:04.427872  ==

 8309 23:10:04.430962  Write leveling (Byte 0): 26 => 26

 8310 23:10:04.434791  Write leveling (Byte 1): 27 => 27

 8311 23:10:04.434866  DramcWriteLeveling(PI) end<-----

 8312 23:10:04.434927  

 8313 23:10:04.437815  ==

 8314 23:10:04.441279  Dram Type= 6, Freq= 0, CH_1, rank 0

 8315 23:10:04.444461  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8316 23:10:04.444533  ==

 8317 23:10:04.448224  [Gating] SW mode calibration

 8318 23:10:04.454212  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8319 23:10:04.458109  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8320 23:10:04.464499   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8321 23:10:04.467854   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8322 23:10:04.470937   1  4  8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)

 8323 23:10:04.477568   1  4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)

 8324 23:10:04.480870   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8325 23:10:04.484488   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8326 23:10:04.490983   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8327 23:10:04.494116   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8328 23:10:04.497702   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8329 23:10:04.504087   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8330 23:10:04.507927   1  5  8 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)

 8331 23:10:04.511258   1  5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)

 8332 23:10:04.517660   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8333 23:10:04.520726   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8334 23:10:04.524340   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8335 23:10:04.530923   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8336 23:10:04.534262   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8337 23:10:04.537240   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8338 23:10:04.541061   1  6  8 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)

 8339 23:10:04.547221   1  6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8340 23:10:04.550619   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8341 23:10:04.553925   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8342 23:10:04.560645   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8343 23:10:04.563888   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8344 23:10:04.567561   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8345 23:10:04.574183   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8346 23:10:04.577210   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8347 23:10:04.580806   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8348 23:10:04.587605   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8349 23:10:04.590818   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8350 23:10:04.594141   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8351 23:10:04.600553   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8352 23:10:04.604218   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8353 23:10:04.607237   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8354 23:10:04.614022   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8355 23:10:04.617324   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8356 23:10:04.620492   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8357 23:10:04.627288   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8358 23:10:04.630387   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8359 23:10:04.634118   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8360 23:10:04.640818   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8361 23:10:04.643700   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8362 23:10:04.647098   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8363 23:10:04.653958   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8364 23:10:04.657428   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8365 23:10:04.661034  Total UI for P1: 0, mck2ui 16

 8366 23:10:04.664207  best dqsien dly found for B0: ( 1,  9, 10)

 8367 23:10:04.667515  Total UI for P1: 0, mck2ui 16

 8368 23:10:04.670948  best dqsien dly found for B1: ( 1,  9, 10)

 8369 23:10:04.673913  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 8370 23:10:04.677474  best DQS1 dly(MCK, UI, PI) = (1, 9, 10)

 8371 23:10:04.677581  

 8372 23:10:04.680261  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8373 23:10:04.683639  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8374 23:10:04.687064  [Gating] SW calibration Done

 8375 23:10:04.687181  ==

 8376 23:10:04.690365  Dram Type= 6, Freq= 0, CH_1, rank 0

 8377 23:10:04.693687  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8378 23:10:04.693770  ==

 8379 23:10:04.697427  RX Vref Scan: 0

 8380 23:10:04.697533  

 8381 23:10:04.700635  RX Vref 0 -> 0, step: 1

 8382 23:10:04.700741  

 8383 23:10:04.700827  RX Delay 0 -> 252, step: 8

 8384 23:10:04.706977  iDelay=200, Bit 0, Center 139 (88 ~ 191) 104

 8385 23:10:04.710687  iDelay=200, Bit 1, Center 131 (80 ~ 183) 104

 8386 23:10:04.713661  iDelay=200, Bit 2, Center 123 (72 ~ 175) 104

 8387 23:10:04.717337  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 8388 23:10:04.720496  iDelay=200, Bit 4, Center 131 (80 ~ 183) 104

 8389 23:10:04.723674  iDelay=200, Bit 5, Center 151 (104 ~ 199) 96

 8390 23:10:04.730359  iDelay=200, Bit 6, Center 147 (96 ~ 199) 104

 8391 23:10:04.734000  iDelay=200, Bit 7, Center 135 (80 ~ 191) 112

 8392 23:10:04.737241  iDelay=200, Bit 8, Center 119 (72 ~ 167) 96

 8393 23:10:04.741030  iDelay=200, Bit 9, Center 123 (72 ~ 175) 104

 8394 23:10:04.743644  iDelay=200, Bit 10, Center 131 (80 ~ 183) 104

 8395 23:10:04.750578  iDelay=200, Bit 11, Center 127 (80 ~ 175) 96

 8396 23:10:04.754058  iDelay=200, Bit 12, Center 143 (88 ~ 199) 112

 8397 23:10:04.757004  iDelay=200, Bit 13, Center 143 (88 ~ 199) 112

 8398 23:10:04.760498  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 8399 23:10:04.766957  iDelay=200, Bit 15, Center 139 (88 ~ 191) 104

 8400 23:10:04.767079  ==

 8401 23:10:04.770791  Dram Type= 6, Freq= 0, CH_1, rank 0

 8402 23:10:04.773849  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8403 23:10:04.773954  ==

 8404 23:10:04.774055  DQS Delay:

 8405 23:10:04.777207  DQS0 = 0, DQS1 = 0

 8406 23:10:04.777315  DQM Delay:

 8407 23:10:04.780490  DQM0 = 136, DQM1 = 133

 8408 23:10:04.780569  DQ Delay:

 8409 23:10:04.783787  DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135

 8410 23:10:04.786958  DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135

 8411 23:10:04.790285  DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127

 8412 23:10:04.793956  DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =139

 8413 23:10:04.794060  

 8414 23:10:04.794163  

 8415 23:10:04.794263  ==

 8416 23:10:04.796889  Dram Type= 6, Freq= 0, CH_1, rank 0

 8417 23:10:04.803470  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8418 23:10:04.803553  ==

 8419 23:10:04.803657  

 8420 23:10:04.803758  

 8421 23:10:04.803860  	TX Vref Scan disable

 8422 23:10:04.807388   == TX Byte 0 ==

 8423 23:10:04.810965  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8424 23:10:04.817687  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8425 23:10:04.817770   == TX Byte 1 ==

 8426 23:10:04.820750  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8427 23:10:04.827590  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8428 23:10:04.827701  ==

 8429 23:10:04.830836  Dram Type= 6, Freq= 0, CH_1, rank 0

 8430 23:10:04.833979  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8431 23:10:04.834089  ==

 8432 23:10:04.845873  

 8433 23:10:04.848962  TX Vref early break, caculate TX vref

 8434 23:10:04.852198  TX Vref=16, minBit 1, minWin=22, winSum=379

 8435 23:10:04.856134  TX Vref=18, minBit 0, minWin=23, winSum=387

 8436 23:10:04.859185  TX Vref=20, minBit 0, minWin=24, winSum=401

 8437 23:10:04.862674  TX Vref=22, minBit 0, minWin=24, winSum=404

 8438 23:10:04.865695  TX Vref=24, minBit 0, minWin=25, winSum=419

 8439 23:10:04.872676  TX Vref=26, minBit 0, minWin=25, winSum=425

 8440 23:10:04.876161  TX Vref=28, minBit 0, minWin=25, winSum=426

 8441 23:10:04.879395  TX Vref=30, minBit 0, minWin=25, winSum=418

 8442 23:10:04.882478  TX Vref=32, minBit 6, minWin=24, winSum=413

 8443 23:10:04.885676  TX Vref=34, minBit 0, minWin=24, winSum=402

 8444 23:10:04.892735  [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 28

 8445 23:10:04.892816  

 8446 23:10:04.895859  Final TX Range 0 Vref 28

 8447 23:10:04.895965  

 8448 23:10:04.896058  ==

 8449 23:10:04.898954  Dram Type= 6, Freq= 0, CH_1, rank 0

 8450 23:10:04.902718  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8451 23:10:04.902831  ==

 8452 23:10:04.902929  

 8453 23:10:04.903020  

 8454 23:10:04.905918  	TX Vref Scan disable

 8455 23:10:04.912340  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 8456 23:10:04.912420   == TX Byte 0 ==

 8457 23:10:04.916005  u2DelayCellOfst[0]=16 cells (5 PI)

 8458 23:10:04.918950  u2DelayCellOfst[1]=13 cells (4 PI)

 8459 23:10:04.922787  u2DelayCellOfst[2]=0 cells (0 PI)

 8460 23:10:04.926039  u2DelayCellOfst[3]=10 cells (3 PI)

 8461 23:10:04.929218  u2DelayCellOfst[4]=10 cells (3 PI)

 8462 23:10:04.932692  u2DelayCellOfst[5]=20 cells (6 PI)

 8463 23:10:04.932804  u2DelayCellOfst[6]=20 cells (6 PI)

 8464 23:10:04.935640  u2DelayCellOfst[7]=10 cells (3 PI)

 8465 23:10:04.942655  Update DQ  dly =978 (3 ,6, 18)  DQ  OEN =(3 ,3)

 8466 23:10:04.945628  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8467 23:10:04.945738   == TX Byte 1 ==

 8468 23:10:04.949108  u2DelayCellOfst[8]=0 cells (0 PI)

 8469 23:10:04.952624  u2DelayCellOfst[9]=3 cells (1 PI)

 8470 23:10:04.955893  u2DelayCellOfst[10]=13 cells (4 PI)

 8471 23:10:04.959023  u2DelayCellOfst[11]=3 cells (1 PI)

 8472 23:10:04.962324  u2DelayCellOfst[12]=13 cells (4 PI)

 8473 23:10:04.965453  u2DelayCellOfst[13]=16 cells (5 PI)

 8474 23:10:04.968963  u2DelayCellOfst[14]=16 cells (5 PI)

 8475 23:10:04.972377  u2DelayCellOfst[15]=16 cells (5 PI)

 8476 23:10:04.975524  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8477 23:10:04.979121  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8478 23:10:04.982618  DramC Write-DBI on

 8479 23:10:04.982723  ==

 8480 23:10:04.985918  Dram Type= 6, Freq= 0, CH_1, rank 0

 8481 23:10:04.989146  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8482 23:10:04.989256  ==

 8483 23:10:04.989351  

 8484 23:10:04.992380  

 8485 23:10:04.992458  	TX Vref Scan disable

 8486 23:10:04.995553   == TX Byte 0 ==

 8487 23:10:04.999449  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8488 23:10:05.002529   == TX Byte 1 ==

 8489 23:10:05.005629  Update DQM dly =722 (2 ,6, 18)  DQM OEN =(3 ,3)

 8490 23:10:05.005738  DramC Write-DBI off

 8491 23:10:05.005833  

 8492 23:10:05.009367  [DATLAT]

 8493 23:10:05.009446  Freq=1600, CH1 RK0

 8494 23:10:05.009515  

 8495 23:10:05.012579  DATLAT Default: 0xf

 8496 23:10:05.012658  0, 0xFFFF, sum = 0

 8497 23:10:05.015864  1, 0xFFFF, sum = 0

 8498 23:10:05.015971  2, 0xFFFF, sum = 0

 8499 23:10:05.019292  3, 0xFFFF, sum = 0

 8500 23:10:05.019397  4, 0xFFFF, sum = 0

 8501 23:10:05.022232  5, 0xFFFF, sum = 0

 8502 23:10:05.022338  6, 0xFFFF, sum = 0

 8503 23:10:05.026057  7, 0xFFFF, sum = 0

 8504 23:10:05.026192  8, 0xFFFF, sum = 0

 8505 23:10:05.029260  9, 0xFFFF, sum = 0

 8506 23:10:05.032459  10, 0xFFFF, sum = 0

 8507 23:10:05.032543  11, 0xFFFF, sum = 0

 8508 23:10:05.036010  12, 0xFFFF, sum = 0

 8509 23:10:05.036122  13, 0xFFFF, sum = 0

 8510 23:10:05.038842  14, 0x0, sum = 1

 8511 23:10:05.038948  15, 0x0, sum = 2

 8512 23:10:05.042148  16, 0x0, sum = 3

 8513 23:10:05.042253  17, 0x0, sum = 4

 8514 23:10:05.042356  best_step = 15

 8515 23:10:05.042457  

 8516 23:10:05.045985  ==

 8517 23:10:05.049015  Dram Type= 6, Freq= 0, CH_1, rank 0

 8518 23:10:05.052094  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8519 23:10:05.052198  ==

 8520 23:10:05.052310  RX Vref Scan: 1

 8521 23:10:05.052406  

 8522 23:10:05.055342  Set Vref Range= 24 -> 127

 8523 23:10:05.055413  

 8524 23:10:05.059041  RX Vref 24 -> 127, step: 1

 8525 23:10:05.059148  

 8526 23:10:05.061937  RX Delay 27 -> 252, step: 4

 8527 23:10:05.062054  

 8528 23:10:05.065637  Set Vref, RX VrefLevel [Byte0]: 24

 8529 23:10:05.068789                           [Byte1]: 24

 8530 23:10:05.068870  

 8531 23:10:05.071907  Set Vref, RX VrefLevel [Byte0]: 25

 8532 23:10:05.075626                           [Byte1]: 25

 8533 23:10:05.075706  

 8534 23:10:05.079019  Set Vref, RX VrefLevel [Byte0]: 26

 8535 23:10:05.082221                           [Byte1]: 26

 8536 23:10:05.085479  

 8537 23:10:05.085585  Set Vref, RX VrefLevel [Byte0]: 27

 8538 23:10:05.088541                           [Byte1]: 27

 8539 23:10:05.092749  

 8540 23:10:05.092852  Set Vref, RX VrefLevel [Byte0]: 28

 8541 23:10:05.096175                           [Byte1]: 28

 8542 23:10:05.100692  

 8543 23:10:05.100774  Set Vref, RX VrefLevel [Byte0]: 29

 8544 23:10:05.103830                           [Byte1]: 29

 8545 23:10:05.108256  

 8546 23:10:05.108371  Set Vref, RX VrefLevel [Byte0]: 30

 8547 23:10:05.111357                           [Byte1]: 30

 8548 23:10:05.115668  

 8549 23:10:05.115747  Set Vref, RX VrefLevel [Byte0]: 31

 8550 23:10:05.118896                           [Byte1]: 31

 8551 23:10:05.123306  

 8552 23:10:05.123412  Set Vref, RX VrefLevel [Byte0]: 32

 8553 23:10:05.126510                           [Byte1]: 32

 8554 23:10:05.130922  

 8555 23:10:05.131026  Set Vref, RX VrefLevel [Byte0]: 33

 8556 23:10:05.134066                           [Byte1]: 33

 8557 23:10:05.138606  

 8558 23:10:05.138712  Set Vref, RX VrefLevel [Byte0]: 34

 8559 23:10:05.141211                           [Byte1]: 34

 8560 23:10:05.145896  

 8561 23:10:05.146005  Set Vref, RX VrefLevel [Byte0]: 35

 8562 23:10:05.148988                           [Byte1]: 35

 8563 23:10:05.153196  

 8564 23:10:05.153278  Set Vref, RX VrefLevel [Byte0]: 36

 8565 23:10:05.156707                           [Byte1]: 36

 8566 23:10:05.160890  

 8567 23:10:05.160974  Set Vref, RX VrefLevel [Byte0]: 37

 8568 23:10:05.163950                           [Byte1]: 37

 8569 23:10:05.168516  

 8570 23:10:05.168597  Set Vref, RX VrefLevel [Byte0]: 38

 8571 23:10:05.171744                           [Byte1]: 38

 8572 23:10:05.175823  

 8573 23:10:05.175929  Set Vref, RX VrefLevel [Byte0]: 39

 8574 23:10:05.179233                           [Byte1]: 39

 8575 23:10:05.183191  

 8576 23:10:05.183296  Set Vref, RX VrefLevel [Byte0]: 40

 8577 23:10:05.186648                           [Byte1]: 40

 8578 23:10:05.190805  

 8579 23:10:05.190914  Set Vref, RX VrefLevel [Byte0]: 41

 8580 23:10:05.194055                           [Byte1]: 41

 8581 23:10:05.198456  

 8582 23:10:05.198531  Set Vref, RX VrefLevel [Byte0]: 42

 8583 23:10:05.201471                           [Byte1]: 42

 8584 23:10:05.206057  

 8585 23:10:05.206135  Set Vref, RX VrefLevel [Byte0]: 43

 8586 23:10:05.209414                           [Byte1]: 43

 8587 23:10:05.213283  

 8588 23:10:05.213370  Set Vref, RX VrefLevel [Byte0]: 44

 8589 23:10:05.217041                           [Byte1]: 44

 8590 23:10:05.221343  

 8591 23:10:05.221423  Set Vref, RX VrefLevel [Byte0]: 45

 8592 23:10:05.224593                           [Byte1]: 45

 8593 23:10:05.228869  

 8594 23:10:05.228972  Set Vref, RX VrefLevel [Byte0]: 46

 8595 23:10:05.232000                           [Byte1]: 46

 8596 23:10:05.235838  

 8597 23:10:05.235952  Set Vref, RX VrefLevel [Byte0]: 47

 8598 23:10:05.239637                           [Byte1]: 47

 8599 23:10:05.243566  

 8600 23:10:05.243645  Set Vref, RX VrefLevel [Byte0]: 48

 8601 23:10:05.246770                           [Byte1]: 48

 8602 23:10:05.251248  

 8603 23:10:05.251351  Set Vref, RX VrefLevel [Byte0]: 49

 8604 23:10:05.254428                           [Byte1]: 49

 8605 23:10:05.258531  

 8606 23:10:05.258637  Set Vref, RX VrefLevel [Byte0]: 50

 8607 23:10:05.262274                           [Byte1]: 50

 8608 23:10:05.265933  

 8609 23:10:05.266038  Set Vref, RX VrefLevel [Byte0]: 51

 8610 23:10:05.269794                           [Byte1]: 51

 8611 23:10:05.273790  

 8612 23:10:05.273909  Set Vref, RX VrefLevel [Byte0]: 52

 8613 23:10:05.277009                           [Byte1]: 52

 8614 23:10:05.281396  

 8615 23:10:05.281501  Set Vref, RX VrefLevel [Byte0]: 53

 8616 23:10:05.287376                           [Byte1]: 53

 8617 23:10:05.287490  

 8618 23:10:05.290770  Set Vref, RX VrefLevel [Byte0]: 54

 8619 23:10:05.294391                           [Byte1]: 54

 8620 23:10:05.294494  

 8621 23:10:05.297470  Set Vref, RX VrefLevel [Byte0]: 55

 8622 23:10:05.300827                           [Byte1]: 55

 8623 23:10:05.300931  

 8624 23:10:05.304133  Set Vref, RX VrefLevel [Byte0]: 56

 8625 23:10:05.307677                           [Byte1]: 56

 8626 23:10:05.311478  

 8627 23:10:05.311589  Set Vref, RX VrefLevel [Byte0]: 57

 8628 23:10:05.314552                           [Byte1]: 57

 8629 23:10:05.318745  

 8630 23:10:05.318875  Set Vref, RX VrefLevel [Byte0]: 58

 8631 23:10:05.322373                           [Byte1]: 58

 8632 23:10:05.326333  

 8633 23:10:05.326437  Set Vref, RX VrefLevel [Byte0]: 59

 8634 23:10:05.329856                           [Byte1]: 59

 8635 23:10:05.333966  

 8636 23:10:05.334048  Set Vref, RX VrefLevel [Byte0]: 60

 8637 23:10:05.337135                           [Byte1]: 60

 8638 23:10:05.341557  

 8639 23:10:05.341658  Set Vref, RX VrefLevel [Byte0]: 61

 8640 23:10:05.344900                           [Byte1]: 61

 8641 23:10:05.348734  

 8642 23:10:05.348839  Set Vref, RX VrefLevel [Byte0]: 62

 8643 23:10:05.352513                           [Byte1]: 62

 8644 23:10:05.356905  

 8645 23:10:05.357010  Set Vref, RX VrefLevel [Byte0]: 63

 8646 23:10:05.360038                           [Byte1]: 63

 8647 23:10:05.363734  

 8648 23:10:05.363837  Set Vref, RX VrefLevel [Byte0]: 64

 8649 23:10:05.367412                           [Byte1]: 64

 8650 23:10:05.371692  

 8651 23:10:05.371797  Set Vref, RX VrefLevel [Byte0]: 65

 8652 23:10:05.374931                           [Byte1]: 65

 8653 23:10:05.378904  

 8654 23:10:05.379021  Set Vref, RX VrefLevel [Byte0]: 66

 8655 23:10:05.382391                           [Byte1]: 66

 8656 23:10:05.386879  

 8657 23:10:05.386985  Set Vref, RX VrefLevel [Byte0]: 67

 8658 23:10:05.390245                           [Byte1]: 67

 8659 23:10:05.394259  

 8660 23:10:05.394358  Set Vref, RX VrefLevel [Byte0]: 68

 8661 23:10:05.397481                           [Byte1]: 68

 8662 23:10:05.401908  

 8663 23:10:05.402020  Set Vref, RX VrefLevel [Byte0]: 69

 8664 23:10:05.405148                           [Byte1]: 69

 8665 23:10:05.409012  

 8666 23:10:05.409114  Set Vref, RX VrefLevel [Byte0]: 70

 8667 23:10:05.412740                           [Byte1]: 70

 8668 23:10:05.416811  

 8669 23:10:05.416887  Set Vref, RX VrefLevel [Byte0]: 71

 8670 23:10:05.420180                           [Byte1]: 71

 8671 23:10:05.424509  

 8672 23:10:05.424614  Set Vref, RX VrefLevel [Byte0]: 72

 8673 23:10:05.427499                           [Byte1]: 72

 8674 23:10:05.431712  

 8675 23:10:05.431815  Set Vref, RX VrefLevel [Byte0]: 73

 8676 23:10:05.434906                           [Byte1]: 73

 8677 23:10:05.439471  

 8678 23:10:05.439575  Set Vref, RX VrefLevel [Byte0]: 74

 8679 23:10:05.442877                           [Byte1]: 74

 8680 23:10:05.446824  

 8681 23:10:05.446932  Final RX Vref Byte 0 = 58 to rank0

 8682 23:10:05.449895  Final RX Vref Byte 1 = 58 to rank0

 8683 23:10:05.453429  Final RX Vref Byte 0 = 58 to rank1

 8684 23:10:05.457335  Final RX Vref Byte 1 = 58 to rank1==

 8685 23:10:05.460266  Dram Type= 6, Freq= 0, CH_1, rank 0

 8686 23:10:05.466563  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8687 23:10:05.466668  ==

 8688 23:10:05.466775  DQS Delay:

 8689 23:10:05.470480  DQS0 = 0, DQS1 = 0

 8690 23:10:05.470596  DQM Delay:

 8691 23:10:05.470689  DQM0 = 134, DQM1 = 131

 8692 23:10:05.473482  DQ Delay:

 8693 23:10:05.476728  DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130

 8694 23:10:05.480308  DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132

 8695 23:10:05.483631  DQ8 =118, DQ9 =122, DQ10 =132, DQ11 =122

 8696 23:10:05.486912  DQ12 =140, DQ13 =138, DQ14 =140, DQ15 =140

 8697 23:10:05.487053  

 8698 23:10:05.487143  

 8699 23:10:05.487259  

 8700 23:10:05.490205  [DramC_TX_OE_Calibration] TA2

 8701 23:10:05.493457  Original DQ_B0 (3 6) =30, OEN = 27

 8702 23:10:05.496741  Original DQ_B1 (3 6) =30, OEN = 27

 8703 23:10:05.500587  24, 0x0, End_B0=24 End_B1=24

 8704 23:10:05.500664  25, 0x0, End_B0=25 End_B1=25

 8705 23:10:05.503705  26, 0x0, End_B0=26 End_B1=26

 8706 23:10:05.506881  27, 0x0, End_B0=27 End_B1=27

 8707 23:10:05.510134  28, 0x0, End_B0=28 End_B1=28

 8708 23:10:05.510219  29, 0x0, End_B0=29 End_B1=29

 8709 23:10:05.513425  30, 0x0, End_B0=30 End_B1=30

 8710 23:10:05.516654  31, 0x4141, End_B0=30 End_B1=30

 8711 23:10:05.519961  Byte0 end_step=30  best_step=27

 8712 23:10:05.523848  Byte1 end_step=30  best_step=27

 8713 23:10:05.526927  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8714 23:10:05.527056  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8715 23:10:05.529932  

 8716 23:10:05.530017  

 8717 23:10:05.537022  [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps

 8718 23:10:05.540179  CH1 RK0: MR19=303, MR18=1927

 8719 23:10:05.546628  CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16

 8720 23:10:05.546712  

 8721 23:10:05.550077  ----->DramcWriteLeveling(PI) begin...

 8722 23:10:05.550186  ==

 8723 23:10:05.553395  Dram Type= 6, Freq= 0, CH_1, rank 1

 8724 23:10:05.556784  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8725 23:10:05.556861  ==

 8726 23:10:05.559953  Write leveling (Byte 0): 25 => 25

 8727 23:10:05.563254  Write leveling (Byte 1): 28 => 28

 8728 23:10:05.566293  DramcWriteLeveling(PI) end<-----

 8729 23:10:05.566394  

 8730 23:10:05.566487  ==

 8731 23:10:05.569824  Dram Type= 6, Freq= 0, CH_1, rank 1

 8732 23:10:05.573034  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8733 23:10:05.573136  ==

 8734 23:10:05.576536  [Gating] SW mode calibration

 8735 23:10:05.583557  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8736 23:10:05.589928  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8737 23:10:05.593328   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8738 23:10:05.596811   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8739 23:10:05.603403   1  4  8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)

 8740 23:10:05.606603   1  4 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 8741 23:10:05.609616   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8742 23:10:05.616798   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8743 23:10:05.620166   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8744 23:10:05.623341   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8745 23:10:05.629835   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8746 23:10:05.633108   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)

 8747 23:10:05.636313   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)

 8748 23:10:05.642826   1  5 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)

 8749 23:10:05.646617   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8750 23:10:05.649578   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8751 23:10:05.656642   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8752 23:10:05.659669   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8753 23:10:05.663315   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8754 23:10:05.669524   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8755 23:10:05.673156   1  6  8 | B1->B0 | 3e3e 2424 | 1 0 | (0 0) (0 0)

 8756 23:10:05.676170   1  6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8757 23:10:05.679942   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8758 23:10:05.686117   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8759 23:10:05.689510   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8760 23:10:05.693296   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8761 23:10:05.699454   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8762 23:10:05.703072   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 8763 23:10:05.706164   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 8764 23:10:05.712618   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 8765 23:10:05.716091   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8766 23:10:05.719331   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8767 23:10:05.726326   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8768 23:10:05.729553   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8769 23:10:05.732914   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8770 23:10:05.739381   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8771 23:10:05.742573   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8772 23:10:05.746409   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8773 23:10:05.752847   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8774 23:10:05.755939   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8775 23:10:05.759321   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8776 23:10:05.766445   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8777 23:10:05.769541   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8778 23:10:05.773271   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 8779 23:10:05.779425   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 8780 23:10:05.783169   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 8781 23:10:05.786268  Total UI for P1: 0, mck2ui 16

 8782 23:10:05.789546  best dqsien dly found for B1: ( 1,  9,  6)

 8783 23:10:05.792597   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8784 23:10:05.796296  Total UI for P1: 0, mck2ui 16

 8785 23:10:05.799307  best dqsien dly found for B0: ( 1,  9, 12)

 8786 23:10:05.802942  best DQS0 dly(MCK, UI, PI) = (1, 9, 12)

 8787 23:10:05.805956  best DQS1 dly(MCK, UI, PI) = (1, 9, 6)

 8788 23:10:05.806064  

 8789 23:10:05.809700  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)

 8790 23:10:05.815894  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)

 8791 23:10:05.816006  [Gating] SW calibration Done

 8792 23:10:05.816102  ==

 8793 23:10:05.819441  Dram Type= 6, Freq= 0, CH_1, rank 1

 8794 23:10:05.826373  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8795 23:10:05.826483  ==

 8796 23:10:05.826580  RX Vref Scan: 0

 8797 23:10:05.826670  

 8798 23:10:05.829477  RX Vref 0 -> 0, step: 1

 8799 23:10:05.829577  

 8800 23:10:05.832386  RX Delay 0 -> 252, step: 8

 8801 23:10:05.835863  iDelay=208, Bit 0, Center 139 (88 ~ 191) 104

 8802 23:10:05.839207  iDelay=208, Bit 1, Center 135 (80 ~ 191) 112

 8803 23:10:05.842838  iDelay=208, Bit 2, Center 123 (72 ~ 175) 104

 8804 23:10:05.845940  iDelay=208, Bit 3, Center 131 (80 ~ 183) 104

 8805 23:10:05.852502  iDelay=208, Bit 4, Center 131 (80 ~ 183) 104

 8806 23:10:05.856193  iDelay=208, Bit 5, Center 151 (96 ~ 207) 112

 8807 23:10:05.859467  iDelay=208, Bit 6, Center 143 (88 ~ 199) 112

 8808 23:10:05.862669  iDelay=208, Bit 7, Center 135 (80 ~ 191) 112

 8809 23:10:05.866030  iDelay=208, Bit 8, Center 119 (64 ~ 175) 112

 8810 23:10:05.872899  iDelay=208, Bit 9, Center 119 (64 ~ 175) 112

 8811 23:10:05.875926  iDelay=208, Bit 10, Center 135 (80 ~ 191) 112

 8812 23:10:05.879128  iDelay=208, Bit 11, Center 127 (72 ~ 183) 112

 8813 23:10:05.882452  iDelay=208, Bit 12, Center 143 (88 ~ 199) 112

 8814 23:10:05.885980  iDelay=208, Bit 13, Center 143 (88 ~ 199) 112

 8815 23:10:05.892918  iDelay=208, Bit 14, Center 139 (88 ~ 191) 104

 8816 23:10:05.896189  iDelay=208, Bit 15, Center 143 (88 ~ 199) 112

 8817 23:10:05.896301  ==

 8818 23:10:05.899183  Dram Type= 6, Freq= 0, CH_1, rank 1

 8819 23:10:05.902593  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8820 23:10:05.902696  ==

 8821 23:10:05.906290  DQS Delay:

 8822 23:10:05.906396  DQS0 = 0, DQS1 = 0

 8823 23:10:05.906489  DQM Delay:

 8824 23:10:05.909336  DQM0 = 136, DQM1 = 133

 8825 23:10:05.909441  DQ Delay:

 8826 23:10:05.912470  DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131

 8827 23:10:05.916330  DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135

 8828 23:10:05.919495  DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127

 8829 23:10:05.926304  DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143

 8830 23:10:05.926414  

 8831 23:10:05.926512  

 8832 23:10:05.926609  ==

 8833 23:10:05.929436  Dram Type= 6, Freq= 0, CH_1, rank 1

 8834 23:10:05.932767  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8835 23:10:05.932872  ==

 8836 23:10:05.932966  

 8837 23:10:05.933060  

 8838 23:10:05.936014  	TX Vref Scan disable

 8839 23:10:05.936123   == TX Byte 0 ==

 8840 23:10:05.942454  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8841 23:10:05.946384  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8842 23:10:05.946510   == TX Byte 1 ==

 8843 23:10:05.952581  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8844 23:10:05.956031  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8845 23:10:05.956136  ==

 8846 23:10:05.959423  Dram Type= 6, Freq= 0, CH_1, rank 1

 8847 23:10:05.962366  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8848 23:10:05.962471  ==

 8849 23:10:05.977234  

 8850 23:10:05.980824  TX Vref early break, caculate TX vref

 8851 23:10:05.983768  TX Vref=16, minBit 0, minWin=23, winSum=383

 8852 23:10:05.987494  TX Vref=18, minBit 0, minWin=23, winSum=391

 8853 23:10:05.990647  TX Vref=20, minBit 0, minWin=24, winSum=399

 8854 23:10:05.994134  TX Vref=22, minBit 0, minWin=25, winSum=411

 8855 23:10:05.997401  TX Vref=24, minBit 0, minWin=24, winSum=418

 8856 23:10:06.003773  TX Vref=26, minBit 0, minWin=26, winSum=428

 8857 23:10:06.007518  TX Vref=28, minBit 0, minWin=25, winSum=426

 8858 23:10:06.010400  TX Vref=30, minBit 1, minWin=25, winSum=420

 8859 23:10:06.013995  TX Vref=32, minBit 0, minWin=24, winSum=413

 8860 23:10:06.016982  TX Vref=34, minBit 0, minWin=24, winSum=406

 8861 23:10:06.020740  TX Vref=36, minBit 0, minWin=23, winSum=399

 8862 23:10:06.027227  [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 26

 8863 23:10:06.027336  

 8864 23:10:06.030331  Final TX Range 0 Vref 26

 8865 23:10:06.030408  

 8866 23:10:06.030472  ==

 8867 23:10:06.034072  Dram Type= 6, Freq= 0, CH_1, rank 1

 8868 23:10:06.037297  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8869 23:10:06.037406  ==

 8870 23:10:06.037500  

 8871 23:10:06.037592  

 8872 23:10:06.040510  	TX Vref Scan disable

 8873 23:10:06.046958  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 8874 23:10:06.047079   == TX Byte 0 ==

 8875 23:10:06.050315  u2DelayCellOfst[0]=16 cells (5 PI)

 8876 23:10:06.053908  u2DelayCellOfst[1]=10 cells (3 PI)

 8877 23:10:06.057118  u2DelayCellOfst[2]=0 cells (0 PI)

 8878 23:10:06.060489  u2DelayCellOfst[3]=6 cells (2 PI)

 8879 23:10:06.063704  u2DelayCellOfst[4]=6 cells (2 PI)

 8880 23:10:06.067571  u2DelayCellOfst[5]=16 cells (5 PI)

 8881 23:10:06.070702  u2DelayCellOfst[6]=16 cells (5 PI)

 8882 23:10:06.073821  u2DelayCellOfst[7]=6 cells (2 PI)

 8883 23:10:06.077240  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8884 23:10:06.080825  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8885 23:10:06.083580   == TX Byte 1 ==

 8886 23:10:06.083684  u2DelayCellOfst[8]=0 cells (0 PI)

 8887 23:10:06.087592  u2DelayCellOfst[9]=3 cells (1 PI)

 8888 23:10:06.090495  u2DelayCellOfst[10]=10 cells (3 PI)

 8889 23:10:06.093623  u2DelayCellOfst[11]=3 cells (1 PI)

 8890 23:10:06.096933  u2DelayCellOfst[12]=13 cells (4 PI)

 8891 23:10:06.100488  u2DelayCellOfst[13]=13 cells (4 PI)

 8892 23:10:06.103842  u2DelayCellOfst[14]=13 cells (4 PI)

 8893 23:10:06.107070  u2DelayCellOfst[15]=16 cells (5 PI)

 8894 23:10:06.110468  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8895 23:10:06.117030  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8896 23:10:06.117130  DramC Write-DBI on

 8897 23:10:06.117243  ==

 8898 23:10:06.120500  Dram Type= 6, Freq= 0, CH_1, rank 1

 8899 23:10:06.123769  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8900 23:10:06.126830  ==

 8901 23:10:06.126946  

 8902 23:10:06.127077  

 8903 23:10:06.127202  	TX Vref Scan disable

 8904 23:10:06.130750   == TX Byte 0 ==

 8905 23:10:06.133794  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8906 23:10:06.137378   == TX Byte 1 ==

 8907 23:10:06.140471  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8908 23:10:06.143562  DramC Write-DBI off

 8909 23:10:06.143661  

 8910 23:10:06.143756  [DATLAT]

 8911 23:10:06.143830  Freq=1600, CH1 RK1

 8912 23:10:06.143904  

 8913 23:10:06.147480  DATLAT Default: 0xf

 8914 23:10:06.147564  0, 0xFFFF, sum = 0

 8915 23:10:06.150417  1, 0xFFFF, sum = 0

 8916 23:10:06.153643  2, 0xFFFF, sum = 0

 8917 23:10:06.153762  3, 0xFFFF, sum = 0

 8918 23:10:06.157318  4, 0xFFFF, sum = 0

 8919 23:10:06.157452  5, 0xFFFF, sum = 0

 8920 23:10:06.160306  6, 0xFFFF, sum = 0

 8921 23:10:06.160390  7, 0xFFFF, sum = 0

 8922 23:10:06.163689  8, 0xFFFF, sum = 0

 8923 23:10:06.163779  9, 0xFFFF, sum = 0

 8924 23:10:06.166939  10, 0xFFFF, sum = 0

 8925 23:10:06.167012  11, 0xFFFF, sum = 0

 8926 23:10:06.170146  12, 0xFFFF, sum = 0

 8927 23:10:06.170217  13, 0xFFFF, sum = 0

 8928 23:10:06.173368  14, 0x0, sum = 1

 8929 23:10:06.173462  15, 0x0, sum = 2

 8930 23:10:06.177170  16, 0x0, sum = 3

 8931 23:10:06.177261  17, 0x0, sum = 4

 8932 23:10:06.180298  best_step = 15

 8933 23:10:06.180406  

 8934 23:10:06.180468  ==

 8935 23:10:06.183639  Dram Type= 6, Freq= 0, CH_1, rank 1

 8936 23:10:06.186858  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8937 23:10:06.186959  ==

 8938 23:10:06.187048  RX Vref Scan: 0

 8939 23:10:06.190812  

 8940 23:10:06.190936  RX Vref 0 -> 0, step: 1

 8941 23:10:06.191025  

 8942 23:10:06.193976  RX Delay 19 -> 252, step: 4

 8943 23:10:06.196835  iDelay=195, Bit 0, Center 138 (91 ~ 186) 96

 8944 23:10:06.203500  iDelay=195, Bit 1, Center 128 (79 ~ 178) 100

 8945 23:10:06.207042  iDelay=195, Bit 2, Center 122 (71 ~ 174) 104

 8946 23:10:06.210525  iDelay=195, Bit 3, Center 130 (83 ~ 178) 96

 8947 23:10:06.213618  iDelay=195, Bit 4, Center 130 (83 ~ 178) 96

 8948 23:10:06.217011  iDelay=195, Bit 5, Center 146 (99 ~ 194) 96

 8949 23:10:06.220514  iDelay=195, Bit 6, Center 144 (95 ~ 194) 100

 8950 23:10:06.227148  iDelay=195, Bit 7, Center 134 (83 ~ 186) 104

 8951 23:10:06.230131  iDelay=195, Bit 8, Center 118 (67 ~ 170) 104

 8952 23:10:06.233741  iDelay=195, Bit 9, Center 118 (67 ~ 170) 104

 8953 23:10:06.237180  iDelay=195, Bit 10, Center 132 (83 ~ 182) 100

 8954 23:10:06.240503  iDelay=195, Bit 11, Center 124 (71 ~ 178) 108

 8955 23:10:06.246812  iDelay=195, Bit 12, Center 140 (87 ~ 194) 108

 8956 23:10:06.250031  iDelay=195, Bit 13, Center 138 (87 ~ 190) 104

 8957 23:10:06.253807  iDelay=195, Bit 14, Center 136 (87 ~ 186) 100

 8958 23:10:06.256840  iDelay=195, Bit 15, Center 140 (91 ~ 190) 100

 8959 23:10:06.256972  ==

 8960 23:10:06.260539  Dram Type= 6, Freq= 0, CH_1, rank 1

 8961 23:10:06.266915  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8962 23:10:06.267046  ==

 8963 23:10:06.267166  DQS Delay:

 8964 23:10:06.270079  DQS0 = 0, DQS1 = 0

 8965 23:10:06.270204  DQM Delay:

 8966 23:10:06.270323  DQM0 = 134, DQM1 = 130

 8967 23:10:06.273333  DQ Delay:

 8968 23:10:06.276554  DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130

 8969 23:10:06.279821  DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134

 8970 23:10:06.283713  DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124

 8971 23:10:06.286867  DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140

 8972 23:10:06.286973  

 8973 23:10:06.287084  

 8974 23:10:06.287189  

 8975 23:10:06.290230  [DramC_TX_OE_Calibration] TA2

 8976 23:10:06.293490  Original DQ_B0 (3 6) =30, OEN = 27

 8977 23:10:06.296630  Original DQ_B1 (3 6) =30, OEN = 27

 8978 23:10:06.299817  24, 0x0, End_B0=24 End_B1=24

 8979 23:10:06.299896  25, 0x0, End_B0=25 End_B1=25

 8980 23:10:06.303639  26, 0x0, End_B0=26 End_B1=26

 8981 23:10:06.306837  27, 0x0, End_B0=27 End_B1=27

 8982 23:10:06.309840  28, 0x0, End_B0=28 End_B1=28

 8983 23:10:06.313600  29, 0x0, End_B0=29 End_B1=29

 8984 23:10:06.313729  30, 0x0, End_B0=30 End_B1=30

 8985 23:10:06.316875  31, 0x4545, End_B0=30 End_B1=30

 8986 23:10:06.320141  Byte0 end_step=30  best_step=27

 8987 23:10:06.323425  Byte1 end_step=30  best_step=27

 8988 23:10:06.326429  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8989 23:10:06.329694  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8990 23:10:06.329823  

 8991 23:10:06.329938  

 8992 23:10:06.336631  [DQSOSCAuto] RK1, (LSB)MR18= 0x2207, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps

 8993 23:10:06.339568  CH1 RK1: MR19=303, MR18=2207

 8994 23:10:06.346340  CH1_RK1: MR19=0x303, MR18=0x2207, DQSOSC=392, MR23=63, INC=24, DEC=16

 8995 23:10:06.349899  [RxdqsGatingPostProcess] freq 1600

 8996 23:10:06.353475  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 8997 23:10:06.356363  best DQS0 dly(2T, 0.5T) = (1, 1)

 8998 23:10:06.359892  best DQS1 dly(2T, 0.5T) = (1, 1)

 8999 23:10:06.363004  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9000 23:10:06.366147  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9001 23:10:06.369778  best DQS0 dly(2T, 0.5T) = (1, 1)

 9002 23:10:06.373050  best DQS1 dly(2T, 0.5T) = (1, 1)

 9003 23:10:06.376200  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9004 23:10:06.379495  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9005 23:10:06.383018  Pre-setting of DQS Precalculation

 9006 23:10:06.386692  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 9007 23:10:06.393077  sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0

 9008 23:10:06.402813  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9009 23:10:06.402926  

 9010 23:10:06.403026  

 9011 23:10:06.403117  [Calibration Summary] 3200 Mbps

 9012 23:10:06.406295  CH 0, Rank 0

 9013 23:10:06.406378  SW Impedance     : PASS

 9014 23:10:06.409393  DUTY Scan        : NO K

 9015 23:10:06.412992  ZQ Calibration   : PASS

 9016 23:10:06.413066  Jitter Meter     : NO K

 9017 23:10:06.415972  CBT Training     : PASS

 9018 23:10:06.419801  Write leveling   : PASS

 9019 23:10:06.419879  RX DQS gating    : PASS

 9020 23:10:06.423091  RX DQ/DQS(RDDQC) : PASS

 9021 23:10:06.426374  TX DQ/DQS        : PASS

 9022 23:10:06.426475  RX DATLAT        : PASS

 9023 23:10:06.429328  RX DQ/DQS(Engine): PASS

 9024 23:10:06.433178  TX OE            : PASS

 9025 23:10:06.433252  All Pass.

 9026 23:10:06.433315  

 9027 23:10:06.433378  CH 0, Rank 1

 9028 23:10:06.436349  SW Impedance     : PASS

 9029 23:10:06.439614  DUTY Scan        : NO K

 9030 23:10:06.439694  ZQ Calibration   : PASS

 9031 23:10:06.442887  Jitter Meter     : NO K

 9032 23:10:06.446120  CBT Training     : PASS

 9033 23:10:06.446220  Write leveling   : PASS

 9034 23:10:06.449701  RX DQS gating    : PASS

 9035 23:10:06.449785  RX DQ/DQS(RDDQC) : PASS

 9036 23:10:06.452598  TX DQ/DQS        : PASS

 9037 23:10:06.455887  RX DATLAT        : PASS

 9038 23:10:06.455962  RX DQ/DQS(Engine): PASS

 9039 23:10:06.459400  TX OE            : PASS

 9040 23:10:06.459485  All Pass.

 9041 23:10:06.459551  

 9042 23:10:06.462831  CH 1, Rank 0

 9043 23:10:06.462917  SW Impedance     : PASS

 9044 23:10:06.466490  DUTY Scan        : NO K

 9045 23:10:06.469664  ZQ Calibration   : PASS

 9046 23:10:06.469749  Jitter Meter     : NO K

 9047 23:10:06.472901  CBT Training     : PASS

 9048 23:10:06.476213  Write leveling   : PASS

 9049 23:10:06.476306  RX DQS gating    : PASS

 9050 23:10:06.479304  RX DQ/DQS(RDDQC) : PASS

 9051 23:10:06.482777  TX DQ/DQS        : PASS

 9052 23:10:06.482862  RX DATLAT        : PASS

 9053 23:10:06.486158  RX DQ/DQS(Engine): PASS

 9054 23:10:06.489348  TX OE            : PASS

 9055 23:10:06.489433  All Pass.

 9056 23:10:06.489500  

 9057 23:10:06.489561  CH 1, Rank 1

 9058 23:10:06.492650  SW Impedance     : PASS

 9059 23:10:06.495900  DUTY Scan        : NO K

 9060 23:10:06.495984  ZQ Calibration   : PASS

 9061 23:10:06.499603  Jitter Meter     : NO K

 9062 23:10:06.502468  CBT Training     : PASS

 9063 23:10:06.502552  Write leveling   : PASS

 9064 23:10:06.506184  RX DQS gating    : PASS

 9065 23:10:06.506269  RX DQ/DQS(RDDQC) : PASS

 9066 23:10:06.509754  TX DQ/DQS        : PASS

 9067 23:10:06.512984  RX DATLAT        : PASS

 9068 23:10:06.513069  RX DQ/DQS(Engine): PASS

 9069 23:10:06.516169  TX OE            : PASS

 9070 23:10:06.516280  All Pass.

 9071 23:10:06.516359  

 9072 23:10:06.519195  DramC Write-DBI on

 9073 23:10:06.522722  	PER_BANK_REFRESH: Hybrid Mode

 9074 23:10:06.522807  TX_TRACKING: ON

 9075 23:10:06.532728  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0

 9076 23:10:06.539177  sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1

 9077 23:10:06.546192  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9078 23:10:06.552767  [FAST_K] Save calibration result to emmc

 9079 23:10:06.552853  sync common calibartion params.

 9080 23:10:06.555968  sync cbt_mode0:1, 1:1

 9081 23:10:06.559167  dram_init: ddr_geometry: 2

 9082 23:10:06.559263  dram_init: ddr_geometry: 2

 9083 23:10:06.562815  dram_init: ddr_geometry: 2

 9084 23:10:06.565720  0:dram_rank_size:100000000

 9085 23:10:06.569486  1:dram_rank_size:100000000

 9086 23:10:06.572354  sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000

 9087 23:10:06.575690  DFS_SHUFFLE_HW_MODE: ON

 9088 23:10:06.579327  dramc_set_vcore_voltage set vcore to 725000

 9089 23:10:06.582574  Read voltage for 1600, 0

 9090 23:10:06.582700  Vio18 = 0

 9091 23:10:06.582818  Vcore = 725000

 9092 23:10:06.586003  Vdram = 0

 9093 23:10:06.586129  Vddq = 0

 9094 23:10:06.586244  Vmddr = 0

 9095 23:10:06.589013  switch to 3200 Mbps bootup

 9096 23:10:06.592742  [DramcRunTimeConfig]

 9097 23:10:06.592867  PHYPLL

 9098 23:10:06.592982  DPM_CONTROL_AFTERK: ON

 9099 23:10:06.595680  PER_BANK_REFRESH: ON

 9100 23:10:06.599108  REFRESH_OVERHEAD_REDUCTION: ON

 9101 23:10:06.599234  CMD_PICG_NEW_MODE: OFF

 9102 23:10:06.602240  XRTWTW_NEW_MODE: ON

 9103 23:10:06.606039  XRTRTR_NEW_MODE: ON

 9104 23:10:06.606161  TX_TRACKING: ON

 9105 23:10:06.606277  RDSEL_TRACKING: OFF

 9106 23:10:06.608926  DQS Precalculation for DVFS: ON

 9107 23:10:06.612335  RX_TRACKING: OFF

 9108 23:10:06.612459  HW_GATING DBG: ON

 9109 23:10:06.615631  ZQCS_ENABLE_LP4: ON

 9110 23:10:06.615737  RX_PICG_NEW_MODE: ON

 9111 23:10:06.619025  TX_PICG_NEW_MODE: ON

 9112 23:10:06.622417  ENABLE_RX_DCM_DPHY: ON

 9113 23:10:06.625911  LOWPOWER_GOLDEN_SETTINGS(DCM): ON

 9114 23:10:06.626039  DUMMY_READ_FOR_TRACKING: OFF

 9115 23:10:06.629079  !!! SPM_CONTROL_AFTERK: OFF

 9116 23:10:06.632543  !!! SPM could not control APHY

 9117 23:10:06.635566  IMPEDANCE_TRACKING: ON

 9118 23:10:06.635691  TEMP_SENSOR: ON

 9119 23:10:06.635806  HW_SAVE_FOR_SR: OFF

 9120 23:10:06.638835  CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF

 9121 23:10:06.645845  PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF

 9122 23:10:06.645972  Read ODT Tracking: ON

 9123 23:10:06.648997  Refresh Rate DeBounce: ON

 9124 23:10:06.649124  DFS_NO_QUEUE_FLUSH: ON

 9125 23:10:06.652274  DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF

 9126 23:10:06.655453  ENABLE_DFS_RUNTIME_MRW: OFF

 9127 23:10:06.659322  DDR_RESERVE_NEW_MODE: ON

 9128 23:10:06.659428  MR_CBT_SWITCH_FREQ: ON

 9129 23:10:06.662408  =========================

 9130 23:10:06.681842  [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)

 9131 23:10:06.685137  dram_init: ddr_geometry: 2

 9132 23:10:06.703197  [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)

 9133 23:10:06.706565  dram_init: dram init end (result: 0)

 9134 23:10:06.713305  DRAM-K: Full calibration passed in 24434 msecs

 9135 23:10:06.716472  MRC: failed to locate region type 0.

 9136 23:10:06.716556  DRAM rank0 size:0x100000000,

 9137 23:10:06.720157  DRAM rank1 size=0x100000000

 9138 23:10:06.730046  Mapping address range [0x40000000:0x240000000) as     cacheable | read-write | non-secure | normal

 9139 23:10:06.736216  Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal

 9140 23:10:06.743354  Backing address range [0x40000000:0x80000000) with new page table @0x00112000

 9141 23:10:06.749499  Backing address range [0x40000000:0x40200000) with new page table @0x00113000

 9142 23:10:06.753348  DRAM rank0 size:0x100000000,

 9143 23:10:06.756488  DRAM rank1 size=0x100000000

 9144 23:10:06.756568  CBMEM:

 9145 23:10:06.759687  IMD: root @ 0xfffff000 254 entries.

 9146 23:10:06.763118  IMD: root @ 0xffffec00 62 entries.

 9147 23:10:06.766291  FMAP: area RO_VPD found @ 3f8000 (32768 bytes)

 9148 23:10:06.769509  WARNING: RO_VPD is uninitialized or empty.

 9149 23:10:06.776508  FMAP: area RW_VPD found @ 577000 (16384 bytes)

 9150 23:10:06.783448  CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80

 9151 23:10:06.796173  read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps

 9152 23:10:06.807753  BS: romstage times (exec / console): total (unknown) / 23968 ms

 9153 23:10:06.807871  

 9154 23:10:06.807967  

 9155 23:10:06.817754  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...

 9156 23:10:06.820520  ARM64: Exception handlers installed.

 9157 23:10:06.824237  ARM64: Testing exception

 9158 23:10:06.827331  ARM64: Done test exception

 9159 23:10:06.827435  Enumerating buses...

 9160 23:10:06.830988  Show all devs... Before device enumeration.

 9161 23:10:06.834225  Root Device: enabled 1

 9162 23:10:06.837398  CPU_CLUSTER: 0: enabled 1

 9163 23:10:06.837508  CPU: 00: enabled 1

 9164 23:10:06.841019  Compare with tree...

 9165 23:10:06.841126  Root Device: enabled 1

 9166 23:10:06.843934   CPU_CLUSTER: 0: enabled 1

 9167 23:10:06.847309    CPU: 00: enabled 1

 9168 23:10:06.847440  Root Device scanning...

 9169 23:10:06.851041  scan_static_bus for Root Device

 9170 23:10:06.854068  CPU_CLUSTER: 0 enabled

 9171 23:10:06.857407  scan_static_bus for Root Device done

 9172 23:10:06.860507  scan_bus: bus Root Device finished in 8 msecs

 9173 23:10:06.860634  done

 9174 23:10:06.867427  BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms

 9175 23:10:06.870514  FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)

 9176 23:10:06.877044  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

 9177 23:10:06.880946  BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms

 9178 23:10:06.884230  Allocating resources...

 9179 23:10:06.887166  Reading resources...

 9180 23:10:06.890885  Root Device read_resources bus 0 link: 0

 9181 23:10:06.890969  DRAM rank0 size:0x100000000,

 9182 23:10:06.893989  DRAM rank1 size=0x100000000

 9183 23:10:06.897240  CPU_CLUSTER: 0 read_resources bus 0 link: 0

 9184 23:10:06.900498  CPU: 00 missing read_resources

 9185 23:10:06.903639  CPU_CLUSTER: 0 read_resources bus 0 link: 0 done

 9186 23:10:06.910710  Root Device read_resources bus 0 link: 0 done

 9187 23:10:06.910795  Done reading resources.

 9188 23:10:06.917544  Show resources in subtree (Root Device)...After reading.

 9189 23:10:06.920642   Root Device child on link 0 CPU_CLUSTER: 0

 9190 23:10:06.923820    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9191 23:10:06.934117    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9192 23:10:06.934209     CPU: 00

 9193 23:10:06.936919  Root Device assign_resources, bus 0 link: 0

 9194 23:10:06.940592  CPU_CLUSTER: 0 missing set_resources

 9195 23:10:06.943822  Root Device assign_resources, bus 0 link: 0 done

 9196 23:10:06.947142  Done setting resources.

 9197 23:10:06.953955  Show resources in subtree (Root Device)...After assigning values.

 9198 23:10:06.956786   Root Device child on link 0 CPU_CLUSTER: 0

 9199 23:10:06.960239    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9200 23:10:06.970015    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9201 23:10:06.970104     CPU: 00

 9202 23:10:06.973538  Done allocating resources.

 9203 23:10:06.977170  BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms

 9204 23:10:06.980390  Enabling resources...

 9205 23:10:06.980475  done.

 9206 23:10:06.986741  BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms

 9207 23:10:06.986854  Initializing devices...

 9208 23:10:06.990492  Root Device init

 9209 23:10:06.990575  init hardware done!

 9210 23:10:06.993668  0x00000018: ctrlr->caps

 9211 23:10:06.996803  52.000 MHz: ctrlr->f_max

 9212 23:10:06.996890  0.400 MHz: ctrlr->f_min

 9213 23:10:07.000514  0x40ff8080: ctrlr->voltages

 9214 23:10:07.000627  sclk: 390625

 9215 23:10:07.003674  Bus Width = 1

 9216 23:10:07.003776  sclk: 390625

 9217 23:10:07.003868  Bus Width = 1

 9218 23:10:07.006938  Early init status = 3

 9219 23:10:07.010798  out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 

 9220 23:10:07.015246  in-header: 03 fc 00 00 01 00 00 00 

 9221 23:10:07.018330  in-data: 00 

 9222 23:10:07.021302  out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01 

 9223 23:10:07.026034  in-header: 03 fd 00 00 00 00 00 00 

 9224 23:10:07.029476  in-data: 

 9225 23:10:07.032961  out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 

 9226 23:10:07.035927  in-header: 03 fc 00 00 01 00 00 00 

 9227 23:10:07.039279  in-data: 00 

 9228 23:10:07.042732  out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01 

 9229 23:10:07.047315  in-header: 03 fd 00 00 00 00 00 00 

 9230 23:10:07.051001  in-data: 

 9231 23:10:07.054204  [SSUSB] Setting up USB HOST controller...

 9232 23:10:07.057479  [SSUSB] u3phy_ports_enable u2p:1, u3p:1

 9233 23:10:07.060706  [SSUSB] phy power-on done.

 9234 23:10:07.063911  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

 9235 23:10:07.070656  CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c

 9236 23:10:07.074195  mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)

 9237 23:10:07.080636  CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c

 9238 23:10:07.087208  read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps

 9239 23:10:07.094192  mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)

 9240 23:10:07.100756  CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204

 9241 23:10:07.106804  read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps

 9242 23:10:07.110073  SPM: binary array size = 0x9dc

 9243 23:10:07.113436  SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)

 9244 23:10:07.120520  spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18

 9245 23:10:07.126921  mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)

 9246 23:10:07.133802  SPM: spm_init done in 34 msecs, spm pc = 0x3f4

 9247 23:10:07.136956  configure_display: Starting display init

 9248 23:10:07.170887  anx7625_power_on_init: Init interface.

 9249 23:10:07.174052  anx7625_disable_pd_protocol: Disabled PD feature.

 9250 23:10:07.177266  anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.

 9251 23:10:07.205279  anx7625_start_dp_work: Secure OCM version=00

 9252 23:10:07.208125  anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91

 9253 23:10:07.223197  sp_tx_get_edid_block: EDID Block = 1

 9254 23:10:07.326091  Extracted contents:

 9255 23:10:07.328938  header:          00 ff ff ff ff ff ff 00

 9256 23:10:07.332496  serial number:   26 cf 7d 05 00 00 00 00 00 1e

 9257 23:10:07.335825  version:         01 04

 9258 23:10:07.338942  basic params:    95 1f 11 78 0a

 9259 23:10:07.342307  chroma info:     76 90 94 55 54 90 27 21 50 54

 9260 23:10:07.345489  established:     00 00 00

 9261 23:10:07.352236  standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01

 9262 23:10:07.355452  descriptor 1:    38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19

 9263 23:10:07.362351  descriptor 2:    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

 9264 23:10:07.369053  descriptor 3:    00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20

 9265 23:10:07.375820  descriptor 4:    00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a

 9266 23:10:07.378951  extensions:      00

 9267 23:10:07.379064  checksum:        fb

 9268 23:10:07.379169  

 9269 23:10:07.382313  Manufacturer: IVO Model 57d Serial Number 0

 9270 23:10:07.385409  Made week 0 of 2020

 9271 23:10:07.385489  EDID version: 1.4

 9272 23:10:07.388988  Digital display

 9273 23:10:07.392115  6 bits per primary color channel

 9274 23:10:07.392194  DisplayPort interface

 9275 23:10:07.395368  Maximum image size: 31 cm x 17 cm

 9276 23:10:07.398817  Gamma: 220%

 9277 23:10:07.398924  Check DPMS levels

 9278 23:10:07.401980  Supported color formats: RGB 4:4:4, YCrCb 4:2:2

 9279 23:10:07.405700  First detailed timing is preferred timing

 9280 23:10:07.408994  Established timings supported:

 9281 23:10:07.412155  Standard timings supported:

 9282 23:10:07.412274  Detailed timings

 9283 23:10:07.418661  Hex of detail: 383680a07038204018303c0035ae10000019

 9284 23:10:07.422283  Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm

 9285 23:10:07.428736                 0780 0798 07c8 0820 hborder 0

 9286 23:10:07.432053                 0438 043b 0447 0458 vborder 0

 9287 23:10:07.435618                 -hsync -vsync

 9288 23:10:07.435723  Did detailed timing

 9289 23:10:07.438475  Hex of detail: 000000000000000000000000000000000000

 9290 23:10:07.441935  Manufacturer-specified data, tag 0

 9291 23:10:07.448786  Hex of detail: 000000fe00496e666f566973696f6e0a2020

 9292 23:10:07.448904  ASCII string: InfoVision

 9293 23:10:07.455225  Hex of detail: 000000fe00523134304e574635205248200a

 9294 23:10:07.458905  ASCII string: R140NWF5 RH 

 9295 23:10:07.459026  Checksum

 9296 23:10:07.459122  Checksum: 0xfb (valid)

 9297 23:10:07.465514  configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz

 9298 23:10:07.468584  DSI data_rate: 832800000 bps

 9299 23:10:07.471836  anx7625_parse_edid: detected IVO panel, use k value 0x3b

 9300 23:10:07.478891  anx7625_parse_edid: pixelclock(138800).

 9301 23:10:07.482116   hactive(1920), hsync(48), hfp(24), hbp(88)

 9302 23:10:07.485352   vactive(1080), vsync(12), vfp(3), vbp(17)

 9303 23:10:07.488526  anx7625_dsi_config: config dsi.

 9304 23:10:07.495416  anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).

 9305 23:10:07.507736  anx7625_dsi_config: success to config DSI

 9306 23:10:07.510944  anx7625_dp_start: MIPI phy setup OK.

 9307 23:10:07.514660  mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4

 9308 23:10:07.517991  mtk_ddp_mode_set invalid vrefresh 60

 9309 23:10:07.521190  main_disp_path_setup

 9310 23:10:07.521318  ovl_layer_smi_id_en

 9311 23:10:07.524475  ovl_layer_smi_id_en

 9312 23:10:07.524601  ccorr_config

 9313 23:10:07.524712  aal_config

 9314 23:10:07.527778  gamma_config

 9315 23:10:07.527890  postmask_config

 9316 23:10:07.531004  dither_config

 9317 23:10:07.534679  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32

 9318 23:10:07.541030                     x_res x y_res: 1920 x 1080, size: 8294400 at 0x0

 9319 23:10:07.544541  Root Device init finished in 551 msecs

 9320 23:10:07.544622  CPU_CLUSTER: 0 init

 9321 23:10:07.554430  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | device

 9322 23:10:07.557653  INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff

 9323 23:10:07.561361  APU_MBOX 0x190000b0 = 0x10001

 9324 23:10:07.564491  APU_MBOX 0x190001b0 = 0x10001

 9325 23:10:07.567539  APU_MBOX 0x190005b0 = 0x10001

 9326 23:10:07.571264  APU_MBOX 0x190006b0 = 0x10001

 9327 23:10:07.574554  CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c

 9328 23:10:07.586814  read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps

 9329 23:10:07.598978  mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)

 9330 23:10:07.605679  CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0

 9331 23:10:07.617469  read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps

 9332 23:10:07.626802  mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)

 9333 23:10:07.630025  CPU_CLUSTER: 0 init finished in 81 msecs

 9334 23:10:07.633335  Devices initialized

 9335 23:10:07.636603  Show all devs... After init.

 9336 23:10:07.636728  Root Device: enabled 1

 9337 23:10:07.639951  CPU_CLUSTER: 0: enabled 1

 9338 23:10:07.643144  CPU: 00: enabled 1

 9339 23:10:07.646834  BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms

 9340 23:10:07.649756  FMAP: area RW_ELOG found @ 57f000 (4096 bytes)

 9341 23:10:07.653151  ELOG: NV offset 0x57f000 size 0x1000

 9342 23:10:07.660232  read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps

 9343 23:10:07.666549  ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024

 9344 23:10:07.670035  ELOG: Event(17) added with size 13 at 2023-12-27 23:07:36 UTC

 9345 23:10:07.673618  out: cmd=0x121: 03 db 21 01 00 00 00 00 

 9346 23:10:07.677186  in-header: 03 f5 00 00 2c 00 00 00 

 9347 23:10:07.690293  in-data: 6a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

 9348 23:10:07.697200  ELOG: Event(A1) added with size 10 at 2023-12-27 23:07:36 UTC

 9349 23:10:07.703799  elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b

 9350 23:10:07.710189  ELOG: Event(A0) added with size 9 at 2023-12-27 23:07:36 UTC

 9351 23:10:07.713320  elog_add_boot_reason: Logged dev mode boot

 9352 23:10:07.717075  BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms

 9353 23:10:07.720080  Finalize devices...

 9354 23:10:07.720189  Devices finalized

 9355 23:10:07.726834  BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms

 9356 23:10:07.729924  Writing coreboot table at 0xffe64000

 9357 23:10:07.733644   0. 000000000010a000-0000000000113fff: RAMSTAGE

 9358 23:10:07.736884   1. 0000000040000000-00000000400fffff: RAM

 9359 23:10:07.740159   2. 0000000040100000-000000004032afff: RAMSTAGE

 9360 23:10:07.746627   3. 000000004032b000-00000000545fffff: RAM

 9361 23:10:07.749927   4. 0000000054600000-000000005465ffff: BL31

 9362 23:10:07.753094   5. 0000000054660000-00000000ffe63fff: RAM

 9363 23:10:07.756340   6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES

 9364 23:10:07.763508   7. 0000000100000000-000000023fffffff: RAM

 9365 23:10:07.763627  Passing 5 GPIOs to payload:

 9366 23:10:07.769616              NAME |       PORT | POLARITY |     VALUE

 9367 23:10:07.773321          EC in RW | 0x000000aa |      low | undefined

 9368 23:10:07.779985      EC interrupt | 0x00000005 |      low | undefined

 9369 23:10:07.783329     TPM interrupt | 0x000000ab |     high | undefined

 9370 23:10:07.786672    SD card detect | 0x00000011 |     high | undefined

 9371 23:10:07.793204    speaker enable | 0x00000093 |     high | undefined

 9372 23:10:07.796175  out: cmd=0x6: 03 f7 06 00 00 00 00 00 

 9373 23:10:07.799859  in-header: 03 f9 00 00 02 00 00 00 

 9374 23:10:07.799976  in-data: 02 00 

 9375 23:10:07.803102  ADC[4]: Raw value=904726 ID=7

 9376 23:10:07.806285  ADC[3]: Raw value=213441 ID=1

 9377 23:10:07.806408  RAM Code: 0x71

 9378 23:10:07.809536  ADC[6]: Raw value=75701 ID=0

 9379 23:10:07.812822  ADC[5]: Raw value=212703 ID=1

 9380 23:10:07.812906  SKU Code: 0x1

 9381 23:10:07.819451  Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9315

 9382 23:10:07.822823  coreboot table: 964 bytes.

 9383 23:10:07.826627  IMD ROOT    0. 0xfffff000 0x00001000

 9384 23:10:07.829824  IMD SMALL   1. 0xffffe000 0x00001000

 9385 23:10:07.833065  RO MCACHE   2. 0xffffc000 0x00001104

 9386 23:10:07.836405  CONSOLE     3. 0xfff7c000 0x00080000

 9387 23:10:07.839715  FMAP        4. 0xfff7b000 0x00000452

 9388 23:10:07.842849  TIME STAMP  5. 0xfff7a000 0x00000910

 9389 23:10:07.846397  VBOOT WORK  6. 0xfff66000 0x00014000

 9390 23:10:07.849950  RAMOOPS     7. 0xffe66000 0x00100000

 9391 23:10:07.853222  COREBOOT    8. 0xffe64000 0x00002000

 9392 23:10:07.853330  IMD small region:

 9393 23:10:07.856494    IMD ROOT    0. 0xffffec00 0x00000400

 9394 23:10:07.859951    VPD         1. 0xffffeb80 0x0000006c

 9395 23:10:07.863164    MMC STATUS  2. 0xffffeb60 0x00000004

 9396 23:10:07.869681  BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms

 9397 23:10:07.869810  Probing TPM:  done!

 9398 23:10:07.876612  Connected to device vid:did:rid of 1ae0:0028:00

 9399 23:10:07.883562  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

 9400 23:10:07.890532  Initialized TPM device CR50 revision 0

 9401 23:10:07.890683  Checking cr50 for pending updates

 9402 23:10:07.896221  Reading cr50 TPM mode

 9403 23:10:07.905097  BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms

 9404 23:10:07.911314  CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098

 9405 23:10:07.951407  read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps

 9406 23:10:07.955339  Checking segment from ROM address 0x40100000

 9407 23:10:07.958552  Checking segment from ROM address 0x4010001c

 9408 23:10:07.965417  Loading segment from ROM address 0x40100000

 9409 23:10:07.965505    code (compression=0)

 9410 23:10:07.971830    New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178

 9411 23:10:07.981814  Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178

 9412 23:10:07.981947  it's not compressed!

 9413 23:10:07.988559  [ 0x80000000, 8004f178, 0x821a7280) <- 40100038

 9414 23:10:07.991546  Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108

 9415 23:10:08.012000  Loading segment from ROM address 0x4010001c

 9416 23:10:08.012089    Entry Point 0x80000000

 9417 23:10:08.015527  Loaded segments

 9418 23:10:08.018502  BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms

 9419 23:10:08.025246  Jumping to boot code at 0x80000000(0xffe64000)

 9420 23:10:08.032240  CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes

 9421 23:10:08.038558  CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290

 9422 23:10:08.046555  read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps

 9423 23:10:08.049816  Checking segment from ROM address 0x40100000

 9424 23:10:08.053092  Checking segment from ROM address 0x4010001c

 9425 23:10:08.060236  Loading segment from ROM address 0x40100000

 9426 23:10:08.060330    code (compression=1)

 9427 23:10:08.066366    New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470

 9428 23:10:08.076606  Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470

 9429 23:10:08.076697  using LZMA

 9430 23:10:08.085022  [ 0x54600000, 54614abc, 0x5462e000) <- 40100038

 9431 23:10:08.091843  Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544

 9432 23:10:08.094797  Loading segment from ROM address 0x4010001c

 9433 23:10:08.094880    Entry Point 0x54601000

 9434 23:10:08.098180  Loaded segments

 9435 23:10:08.101920  NOTICE:  MT8192 bl31_setup

 9436 23:10:08.108921  NOTICE:  BL31: v2.4(debug):v2.4-448-gce3ebc861

 9437 23:10:08.111902  NOTICE:  BL31: Built : Sat Sep 11 09:59:37 UTC 2021

 9438 23:10:08.114982  WARNING: region 0:

 9439 23:10:08.118182  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9440 23:10:08.118294  WARNING: region 1:

 9441 23:10:08.124664  WARNING: 	sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d

 9442 23:10:08.128299  WARNING: region 2:

 9443 23:10:08.131934  WARNING: 	sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d

 9444 23:10:08.134768  WARNING: region 3:

 9445 23:10:08.138216  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9446 23:10:08.141944  WARNING: region 4:

 9447 23:10:08.148472  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9448 23:10:08.148585  WARNING: region 5:

 9449 23:10:08.151715  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9450 23:10:08.155086  WARNING: region 6:

 9451 23:10:08.158203  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9452 23:10:08.161506  WARNING: region 7:

 9453 23:10:08.165401  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9454 23:10:08.171939  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000

 9455 23:10:08.175092  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0

 9456 23:10:08.178473  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff

 9457 23:10:08.185068  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff

 9458 23:10:08.188292  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff

 9459 23:10:08.191937  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00

 9460 23:10:08.198717  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff

 9461 23:10:08.201813  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff

 9462 23:10:08.208388  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff

 9463 23:10:08.212204  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff

 9464 23:10:08.214792  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff

 9465 23:10:08.221499  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff

 9466 23:10:08.225076  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff

 9467 23:10:08.228213  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff

 9468 23:10:08.235456  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff

 9469 23:10:08.238524  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff

 9470 23:10:08.241700  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff

 9471 23:10:08.248704  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff

 9472 23:10:08.251970  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff

 9473 23:10:08.258979  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff

 9474 23:10:08.262272  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff

 9475 23:10:08.265513  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff

 9476 23:10:08.271905  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff

 9477 23:10:08.275185  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff

 9478 23:10:08.281804  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff

 9479 23:10:08.285112  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff

 9480 23:10:08.288662  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff

 9481 23:10:08.295449  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff

 9482 23:10:08.298529  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff

 9483 23:10:08.302248  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff

 9484 23:10:08.308892  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff

 9485 23:10:08.311956  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff

 9486 23:10:08.315606  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0

 9487 23:10:08.322264  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0

 9488 23:10:08.325090  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0

 9489 23:10:08.329093  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0

 9490 23:10:08.332092  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0

 9491 23:10:08.338475  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0

 9492 23:10:08.341820  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0

 9493 23:10:08.345260  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0

 9494 23:10:08.349009  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0

 9495 23:10:08.355475  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0

 9496 23:10:08.358951  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0

 9497 23:10:08.362025  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0

 9498 23:10:08.365275  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0

 9499 23:10:08.371960  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0

 9500 23:10:08.375668  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0

 9501 23:10:08.378911  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0

 9502 23:10:08.385516  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff

 9503 23:10:08.388895  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff

 9504 23:10:08.392104  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff

 9505 23:10:08.398972  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff

 9506 23:10:08.402023  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff

 9507 23:10:08.409125  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff

 9508 23:10:08.412295  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff

 9509 23:10:08.418757  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff

 9510 23:10:08.422451  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff

 9511 23:10:08.425403  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff

 9512 23:10:08.431966  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff

 9513 23:10:08.435444  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff

 9514 23:10:08.442403  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff

 9515 23:10:08.445670  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff

 9516 23:10:08.452413  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff

 9517 23:10:08.455771  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff

 9518 23:10:08.458873  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff

 9519 23:10:08.465829  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff

 9520 23:10:08.469225  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff

 9521 23:10:08.475977  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff

 9522 23:10:08.479219  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff

 9523 23:10:08.485712  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff

 9524 23:10:08.488981  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff

 9525 23:10:08.492274  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff

 9526 23:10:08.499421  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff

 9527 23:10:08.502722  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff

 9528 23:10:08.509135  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff

 9529 23:10:08.512363  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff

 9530 23:10:08.519286  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff

 9531 23:10:08.522834  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff

 9532 23:10:08.525661  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff

 9533 23:10:08.532572  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff

 9534 23:10:08.535893  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff

 9535 23:10:08.542550  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff

 9536 23:10:08.545688  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff

 9537 23:10:08.552474  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff

 9538 23:10:08.555896  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff

 9539 23:10:08.559324  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff

 9540 23:10:08.565554  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff

 9541 23:10:08.569442  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff

 9542 23:10:08.575662  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff

 9543 23:10:08.579247  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff

 9544 23:10:08.586160  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff

 9545 23:10:08.589443  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff

 9546 23:10:08.592751  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff

 9547 23:10:08.599467  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff

 9548 23:10:08.602729  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff

 9549 23:10:08.609378  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff

 9550 23:10:08.612488  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0

 9551 23:10:08.616441  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0

 9552 23:10:08.619652  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0

 9553 23:10:08.626176  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0

 9554 23:10:08.629288  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0

 9555 23:10:08.632816  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff

 9556 23:10:08.639480  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff

 9557 23:10:08.643038  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff

 9558 23:10:08.649553  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff

 9559 23:10:08.652844  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff

 9560 23:10:08.656322  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff

 9561 23:10:08.663047  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff

 9562 23:10:08.666249  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff

 9563 23:10:08.672835  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff

 9564 23:10:08.676506  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff

 9565 23:10:08.679504  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff

 9566 23:10:08.686441  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff

 9567 23:10:08.689404  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff

 9568 23:10:08.696021  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff

 9569 23:10:08.699379  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff

 9570 23:10:08.703177  INFO:    [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18

 9571 23:10:08.706344  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000

 9572 23:10:08.712834  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004

 9573 23:10:08.716071  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0

 9574 23:10:08.719727  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0

 9575 23:10:08.722977  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0

 9576 23:10:08.729526  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0

 9577 23:10:08.732788  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000

 9578 23:10:08.736595  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff

 9579 23:10:08.743115  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff

 9580 23:10:08.746496  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff

 9581 23:10:08.749617  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff

 9582 23:10:08.756497  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff

 9583 23:10:08.760057  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff

 9584 23:10:08.766100  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff

 9585 23:10:08.769424  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc

 9586 23:10:08.773055  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff

 9587 23:10:08.779587  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf

 9588 23:10:08.783182  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff

 9589 23:10:08.789671  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc

 9590 23:10:08.792997  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff

 9591 23:10:08.796647  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff

 9592 23:10:08.803089  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff

 9593 23:10:08.806847  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff

 9594 23:10:08.810022  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff

 9595 23:10:08.816232  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff

 9596 23:10:08.820036  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff

 9597 23:10:08.826214  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff

 9598 23:10:08.829610  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff

 9599 23:10:08.832871  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff

 9600 23:10:08.839899  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff

 9601 23:10:08.843153  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff

 9602 23:10:08.849686  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff

 9603 23:10:08.853281  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff

 9604 23:10:08.856229  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff

 9605 23:10:08.863478  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff

 9606 23:10:08.866680  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff

 9607 23:10:08.869777  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff

 9608 23:10:08.876730  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff

 9609 23:10:08.880037  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff

 9610 23:10:08.886562  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff

 9611 23:10:08.889921  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff

 9612 23:10:08.893405  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff

 9613 23:10:08.900012  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff

 9614 23:10:08.903569  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff

 9615 23:10:08.906336  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff

 9616 23:10:08.913134  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff

 9617 23:10:08.916462  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff

 9618 23:10:08.923309  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff

 9619 23:10:08.926315  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff

 9620 23:10:08.929542  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff

 9621 23:10:08.936683  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff

 9622 23:10:08.940007  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff

 9623 23:10:08.946505  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff

 9624 23:10:08.949754  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff

 9625 23:10:08.952858  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff

 9626 23:10:08.959924  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff

 9627 23:10:08.963024  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff

 9628 23:10:08.969652  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff

 9629 23:10:08.972821  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff

 9630 23:10:08.976057  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff

 9631 23:10:08.983165  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff

 9632 23:10:08.986079  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff

 9633 23:10:08.989791  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff

 9634 23:10:08.996467  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff

 9635 23:10:08.999557  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff

 9636 23:10:09.006102  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff

 9637 23:10:09.009203  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff

 9638 23:10:09.012991  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff

 9639 23:10:09.019346  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff

 9640 23:10:09.022756  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff

 9641 23:10:09.029310  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff

 9642 23:10:09.032942  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff

 9643 23:10:09.036283  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff

 9644 23:10:09.042871  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff

 9645 23:10:09.046301  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff

 9646 23:10:09.053006  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff

 9647 23:10:09.056084  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff

 9648 23:10:09.059345  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff

 9649 23:10:09.066262  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff

 9650 23:10:09.069272  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff

 9651 23:10:09.075820  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff

 9652 23:10:09.079573  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff

 9653 23:10:09.086188  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff

 9654 23:10:09.089334  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff

 9655 23:10:09.092905  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff

 9656 23:10:09.099096  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff

 9657 23:10:09.102819  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff

 9658 23:10:09.109381  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff

 9659 23:10:09.112757  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff

 9660 23:10:09.119223  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff

 9661 23:10:09.122578  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff

 9662 23:10:09.125809  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff

 9663 23:10:09.132455  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff

 9664 23:10:09.135753  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff

 9665 23:10:09.142363  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff

 9666 23:10:09.145937  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff

 9667 23:10:09.149130  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff

 9668 23:10:09.155445  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff

 9669 23:10:09.158913  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff

 9670 23:10:09.165936  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff

 9671 23:10:09.169085  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff

 9672 23:10:09.175591  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff

 9673 23:10:09.179012  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff

 9674 23:10:09.182175  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff

 9675 23:10:09.188839  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff

 9676 23:10:09.191916  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff

 9677 23:10:09.198877  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff

 9678 23:10:09.202106  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff

 9679 23:10:09.205630  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff

 9680 23:10:09.211905  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff

 9681 23:10:09.215821  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff

 9682 23:10:09.221875  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff

 9683 23:10:09.225879  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0

 9684 23:10:09.228945  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0

 9685 23:10:09.232258  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0

 9686 23:10:09.235415  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0

 9687 23:10:09.241861  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0

 9688 23:10:09.245117  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff

 9689 23:10:09.252178  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff

 9690 23:10:09.255031  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff

 9691 23:10:09.258347  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff

 9692 23:10:09.265458  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf

 9693 23:10:09.268664  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff

 9694 23:10:09.271924  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff

 9695 23:10:09.278368  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff

 9696 23:10:09.282120  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff

 9697 23:10:09.285146  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf

 9698 23:10:09.292031  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff

 9699 23:10:09.295374  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff

 9700 23:10:09.301697  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff

 9701 23:10:09.305320  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff

 9702 23:10:09.308480  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf

 9703 23:10:09.315022  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff

 9704 23:10:09.318119  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff

 9705 23:10:09.321343  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff

 9706 23:10:09.328109  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff

 9707 23:10:09.331253  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf

 9708 23:10:09.335205  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff

 9709 23:10:09.341812  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff

 9710 23:10:09.344855  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff

 9711 23:10:09.351954  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff

 9712 23:10:09.355250  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf

 9713 23:10:09.358417  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff

 9714 23:10:09.365157  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff

 9715 23:10:09.368652  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff

 9716 23:10:09.371572  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff

 9717 23:10:09.378068  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf

 9718 23:10:09.381684  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff

 9719 23:10:09.384865  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff

 9720 23:10:09.391273  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff

 9721 23:10:09.395021  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff

 9722 23:10:09.397921  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf

 9723 23:10:09.404549  INFO:    [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0

 9724 23:10:09.407794  INFO:    [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3

 9725 23:10:09.411548  INFO:    [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3

 9726 23:10:09.414877  INFO:    [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3

 9727 23:10:09.417999  INFO:    [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0

 9728 23:10:09.424644  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400

 9729 23:10:09.428280  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0

 9730 23:10:09.431402  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0

 9731 23:10:09.437862  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0

 9732 23:10:09.441293  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0

 9733 23:10:09.444509  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0

 9734 23:10:09.447722  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000

 9735 23:10:09.454530  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0

 9736 23:10:09.457974  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff

 9737 23:10:09.464444  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff

 9738 23:10:09.467650  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff

 9739 23:10:09.471416  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff

 9740 23:10:09.477790  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff

 9741 23:10:09.481058  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff

 9742 23:10:09.487990  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff

 9743 23:10:09.490952  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f

 9744 23:10:09.494115  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3

 9745 23:10:09.501324  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff

 9746 23:10:09.504221  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff

 9747 23:10:09.510814  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff

 9748 23:10:09.514026  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff

 9749 23:10:09.520889  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff

 9750 23:10:09.524231  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff

 9751 23:10:09.527606  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f

 9752 23:10:09.534239  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff

 9753 23:10:09.537553  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff

 9754 23:10:09.541210  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff

 9755 23:10:09.547430  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff

 9756 23:10:09.550642  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff

 9757 23:10:09.557845  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff

 9758 23:10:09.560950  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff

 9759 23:10:09.564120  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f

 9760 23:10:09.570988  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff

 9761 23:10:09.574443  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff

 9762 23:10:09.580636  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff

 9763 23:10:09.583875  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff

 9764 23:10:09.590505  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff

 9765 23:10:09.594213  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff

 9766 23:10:09.597283  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff

 9767 23:10:09.604022  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f

 9768 23:10:09.607254  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff

 9769 23:10:09.613842  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff

 9770 23:10:09.617485  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff

 9771 23:10:09.620603  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff

 9772 23:10:09.626995  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff

 9773 23:10:09.630252  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff

 9774 23:10:09.637362  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff

 9775 23:10:09.640473  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f

 9776 23:10:09.643894  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff

 9777 23:10:09.650515  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff

 9778 23:10:09.653888  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff

 9779 23:10:09.660188  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff

 9780 23:10:09.663895  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff

 9781 23:10:09.670259  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff

 9782 23:10:09.673603  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff

 9783 23:10:09.677278  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f

 9784 23:10:09.683687  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff

 9785 23:10:09.686927  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff

 9786 23:10:09.693598  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff

 9787 23:10:09.697188  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff

 9788 23:10:09.700249  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff

 9789 23:10:09.706859  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff

 9790 23:10:09.710464  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff

 9791 23:10:09.713770  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f

 9792 23:10:09.720637  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff

 9793 23:10:09.723664  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff

 9794 23:10:09.730801  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff

 9795 23:10:09.733935  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff

 9796 23:10:09.740454  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff

 9797 23:10:09.743702  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff

 9798 23:10:09.747411  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff

 9799 23:10:09.753939  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f

 9800 23:10:09.756980  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff

 9801 23:10:09.763607  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff

 9802 23:10:09.766891  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff

 9803 23:10:09.770739  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff

 9804 23:10:09.777213  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff

 9805 23:10:09.780318  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff

 9806 23:10:09.787373  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff

 9807 23:10:09.790509  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f

 9808 23:10:09.793507  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff

 9809 23:10:09.800241  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff

 9810 23:10:09.803626  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff

 9811 23:10:09.809986  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff

 9812 23:10:09.813283  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff

 9813 23:10:09.819808  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff

 9814 23:10:09.823461  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff

 9815 23:10:09.826933  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f

 9816 23:10:09.833559  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff

 9817 23:10:09.836664  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff

 9818 23:10:09.843524  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff

 9819 23:10:09.846715  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff

 9820 23:10:09.853443  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff

 9821 23:10:09.856383  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff

 9822 23:10:09.863274  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff

 9823 23:10:09.866186  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f

 9824 23:10:09.869875  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff

 9825 23:10:09.876158  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff

 9826 23:10:09.879470  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff

 9827 23:10:09.886016  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff

 9828 23:10:09.889296  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff

 9829 23:10:09.896442  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff

 9830 23:10:09.899537  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff

 9831 23:10:09.902985  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f

 9832 23:10:09.909486  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff

 9833 23:10:09.912524  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff

 9834 23:10:09.919548  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff

 9835 23:10:09.922939  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff

 9836 23:10:09.929361  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff

 9837 23:10:09.932593  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff

 9838 23:10:09.939527  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff

 9839 23:10:09.942731  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f

 9840 23:10:09.945966  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff

 9841 23:10:09.952674  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff

 9842 23:10:09.955882  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff

 9843 23:10:09.962696  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff

 9844 23:10:09.966148  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff

 9845 23:10:09.972856  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff

 9846 23:10:09.975708  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff

 9847 23:10:09.979363  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f

 9848 23:10:09.985867  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff

 9849 23:10:09.989137  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff

 9850 23:10:09.995458  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff

 9851 23:10:09.999363  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff

 9852 23:10:10.005722  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff

 9853 23:10:10.009092  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff

 9854 23:10:10.015697  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff

 9855 23:10:10.019198  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f

 9856 23:10:10.022346  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0

 9857 23:10:10.028912  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000

 9858 23:10:10.032598  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff

 9859 23:10:10.039323  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff

 9860 23:10:10.042218  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3

 9861 23:10:10.048877  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff

 9862 23:10:10.052272  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff

 9863 23:10:10.055713  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff

 9864 23:10:10.061989  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff

 9865 23:10:10.065720  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff

 9866 23:10:10.072503  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff

 9867 23:10:10.075746  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff

 9868 23:10:10.082213  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff

 9869 23:10:10.085233  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff

 9870 23:10:10.092031  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff

 9871 23:10:10.095282  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff

 9872 23:10:10.101819  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff

 9873 23:10:10.105646  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff

 9874 23:10:10.111936  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff

 9875 23:10:10.115140  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff

 9876 23:10:10.122055  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff

 9877 23:10:10.125075  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff

 9878 23:10:10.132137  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff

 9879 23:10:10.135376  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff

 9880 23:10:10.141576  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff

 9881 23:10:10.145237  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff

 9882 23:10:10.152125  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff

 9883 23:10:10.154916  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff

 9884 23:10:10.161926  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff

 9885 23:10:10.164929  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff

 9886 23:10:10.171237  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff

 9887 23:10:10.174662  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff

 9888 23:10:10.181670  INFO:    [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0

 9889 23:10:10.181787  INFO:    [APUAPC] vio 0

 9890 23:10:10.188235  INFO:    [APUAPC] set_apusys_ao_apc - SUCCESS!

 9891 23:10:10.191640  INFO:    [APUAPC] set_apusys_noc_dapc - SUCCESS!

 9892 23:10:10.195311  INFO:    [APUAPC] D0_APC_0: 0x400510

 9893 23:10:10.198330  INFO:    [APUAPC] D0_APC_1: 0x0

 9894 23:10:10.202028  INFO:    [APUAPC] D0_APC_2: 0x1540

 9895 23:10:10.204947  INFO:    [APUAPC] D0_APC_3: 0x0

 9896 23:10:10.208130  INFO:    [APUAPC] D1_APC_0: 0xffffffff

 9897 23:10:10.211791  INFO:    [APUAPC] D1_APC_1: 0xffffffff

 9898 23:10:10.215108  INFO:    [APUAPC] D1_APC_2: 0x3fffff

 9899 23:10:10.218299  INFO:    [APUAPC] D1_APC_3: 0x0

 9900 23:10:10.221538  INFO:    [APUAPC] D2_APC_0: 0xffffffff

 9901 23:10:10.225385  INFO:    [APUAPC] D2_APC_1: 0xffffffff

 9902 23:10:10.228494  INFO:    [APUAPC] D2_APC_2: 0x3fffff

 9903 23:10:10.228577  INFO:    [APUAPC] D2_APC_3: 0x0

 9904 23:10:10.231607  INFO:    [APUAPC] D3_APC_0: 0xffffffff

 9905 23:10:10.238287  INFO:    [APUAPC] D3_APC_1: 0xffffffff

 9906 23:10:10.241997  INFO:    [APUAPC] D3_APC_2: 0x3fffff

 9907 23:10:10.242082  INFO:    [APUAPC] D3_APC_3: 0x0

 9908 23:10:10.245193  INFO:    [APUAPC] D4_APC_0: 0xffffffff

 9909 23:10:10.248271  INFO:    [APUAPC] D4_APC_1: 0xffffffff

 9910 23:10:10.252008  INFO:    [APUAPC] D4_APC_2: 0x3fffff

 9911 23:10:10.255297  INFO:    [APUAPC] D4_APC_3: 0x0

 9912 23:10:10.258352  INFO:    [APUAPC] D5_APC_0: 0xffffffff

 9913 23:10:10.261580  INFO:    [APUAPC] D5_APC_1: 0xffffffff

 9914 23:10:10.264821  INFO:    [APUAPC] D5_APC_2: 0x3fffff

 9915 23:10:10.268018  INFO:    [APUAPC] D5_APC_3: 0x0

 9916 23:10:10.271854  INFO:    [APUAPC] D6_APC_0: 0xffffffff

 9917 23:10:10.274970  INFO:    [APUAPC] D6_APC_1: 0xffffffff

 9918 23:10:10.278416  INFO:    [APUAPC] D6_APC_2: 0x3fffff

 9919 23:10:10.281444  INFO:    [APUAPC] D6_APC_3: 0x0

 9920 23:10:10.285035  INFO:    [APUAPC] D7_APC_0: 0xffffffff

 9921 23:10:10.287881  INFO:    [APUAPC] D7_APC_1: 0xffffffff

 9922 23:10:10.291503  INFO:    [APUAPC] D7_APC_2: 0x3fffff

 9923 23:10:10.294876  INFO:    [APUAPC] D7_APC_3: 0x0

 9924 23:10:10.297972  INFO:    [APUAPC] D8_APC_0: 0xffffffff

 9925 23:10:10.301618  INFO:    [APUAPC] D8_APC_1: 0xffffffff

 9926 23:10:10.304538  INFO:    [APUAPC] D8_APC_2: 0x3fffff

 9927 23:10:10.307792  INFO:    [APUAPC] D8_APC_3: 0x0

 9928 23:10:10.311444  INFO:    [APUAPC] D9_APC_0: 0xffffffff

 9929 23:10:10.314528  INFO:    [APUAPC] D9_APC_1: 0xffffffff

 9930 23:10:10.318000  INFO:    [APUAPC] D9_APC_2: 0x3fffff

 9931 23:10:10.321471  INFO:    [APUAPC] D9_APC_3: 0x0

 9932 23:10:10.324849  INFO:    [APUAPC] D10_APC_0: 0xffffffff

 9933 23:10:10.328021  INFO:    [APUAPC] D10_APC_1: 0xffffffff

 9934 23:10:10.331203  INFO:    [APUAPC] D10_APC_2: 0x3fffff

 9935 23:10:10.335079  INFO:    [APUAPC] D10_APC_3: 0x0

 9936 23:10:10.338064  INFO:    [APUAPC] D11_APC_0: 0xffffffff

 9937 23:10:10.341780  INFO:    [APUAPC] D11_APC_1: 0xffffffff

 9938 23:10:10.344783  INFO:    [APUAPC] D11_APC_2: 0x3fffff

 9939 23:10:10.348424  INFO:    [APUAPC] D11_APC_3: 0x0

 9940 23:10:10.351483  INFO:    [APUAPC] D12_APC_0: 0xffffffff

 9941 23:10:10.354595  INFO:    [APUAPC] D12_APC_1: 0xffffffff

 9942 23:10:10.357941  INFO:    [APUAPC] D12_APC_2: 0x3fffff

 9943 23:10:10.361649  INFO:    [APUAPC] D12_APC_3: 0x0

 9944 23:10:10.364642  INFO:    [APUAPC] D13_APC_0: 0xffffffff

 9945 23:10:10.368077  INFO:    [APUAPC] D13_APC_1: 0xffffffff

 9946 23:10:10.371260  INFO:    [APUAPC] D13_APC_2: 0x3fffff

 9947 23:10:10.375084  INFO:    [APUAPC] D13_APC_3: 0x0

 9948 23:10:10.378327  INFO:    [APUAPC] D14_APC_0: 0xffffffff

 9949 23:10:10.381374  INFO:    [APUAPC] D14_APC_1: 0xffffffff

 9950 23:10:10.385006  INFO:    [APUAPC] D14_APC_2: 0x3fffff

 9951 23:10:10.388098  INFO:    [APUAPC] D14_APC_3: 0x0

 9952 23:10:10.391644  INFO:    [APUAPC] D15_APC_0: 0xffffffff

 9953 23:10:10.394705  INFO:    [APUAPC] D15_APC_1: 0xffffffff

 9954 23:10:10.397864  INFO:    [APUAPC] D15_APC_2: 0x3fffff

 9955 23:10:10.400970  INFO:    [APUAPC] D15_APC_3: 0x0

 9956 23:10:10.404282  INFO:    [APUAPC] APC_CON: 0x4

 9957 23:10:10.407652  INFO:    [NOCDAPC] D0_APC_0: 0x0

 9958 23:10:10.411580  INFO:    [NOCDAPC] D0_APC_1: 0x0

 9959 23:10:10.411665  INFO:    [NOCDAPC] D1_APC_0: 0x0

 9960 23:10:10.414364  INFO:    [NOCDAPC] D1_APC_1: 0xfff

 9961 23:10:10.417970  INFO:    [NOCDAPC] D2_APC_0: 0x0

 9962 23:10:10.421057  INFO:    [NOCDAPC] D2_APC_1: 0xfff

 9963 23:10:10.424480  INFO:    [NOCDAPC] D3_APC_0: 0x0

 9964 23:10:10.427707  INFO:    [NOCDAPC] D3_APC_1: 0xfff

 9965 23:10:10.430818  INFO:    [NOCDAPC] D4_APC_0: 0x0

 9966 23:10:10.434537  INFO:    [NOCDAPC] D4_APC_1: 0xfff

 9967 23:10:10.437501  INFO:    [NOCDAPC] D5_APC_0: 0x0

 9968 23:10:10.441026  INFO:    [NOCDAPC] D5_APC_1: 0xfff

 9969 23:10:10.443960  INFO:    [NOCDAPC] D6_APC_0: 0x0

 9970 23:10:10.447927  INFO:    [NOCDAPC] D6_APC_1: 0xfff

 9971 23:10:10.448007  INFO:    [NOCDAPC] D7_APC_0: 0x0

 9972 23:10:10.450971  INFO:    [NOCDAPC] D7_APC_1: 0xfff

 9973 23:10:10.454043  INFO:    [NOCDAPC] D8_APC_0: 0x0

 9974 23:10:10.457462  INFO:    [NOCDAPC] D8_APC_1: 0xfff

 9975 23:10:10.461092  INFO:    [NOCDAPC] D9_APC_0: 0x0

 9976 23:10:10.463859  INFO:    [NOCDAPC] D9_APC_1: 0xfff

 9977 23:10:10.467667  INFO:    [NOCDAPC] D10_APC_0: 0x0

 9978 23:10:10.471006  INFO:    [NOCDAPC] D10_APC_1: 0xfff

 9979 23:10:10.473755  INFO:    [NOCDAPC] D11_APC_0: 0x0

 9980 23:10:10.477694  INFO:    [NOCDAPC] D11_APC_1: 0xfff

 9981 23:10:10.481055  INFO:    [NOCDAPC] D12_APC_0: 0x0

 9982 23:10:10.484273  INFO:    [NOCDAPC] D12_APC_1: 0xfff

 9983 23:10:10.487561  INFO:    [NOCDAPC] D13_APC_0: 0x0

 9984 23:10:10.487670  INFO:    [NOCDAPC] D13_APC_1: 0xfff

 9985 23:10:10.490596  INFO:    [NOCDAPC] D14_APC_0: 0x0

 9986 23:10:10.494086  INFO:    [NOCDAPC] D14_APC_1: 0xfff

 9987 23:10:10.497236  INFO:    [NOCDAPC] D15_APC_0: 0x0

 9988 23:10:10.500853  INFO:    [NOCDAPC] D15_APC_1: 0xfff

 9989 23:10:10.504227  INFO:    [NOCDAPC] APC_CON: 0x4

 9990 23:10:10.507300  INFO:    [APUAPC] set_apusys_apc done

 9991 23:10:10.510762  INFO:    [DEVAPC] devapc_init done

 9992 23:10:10.513918  INFO:    GICv3 without legacy support detected.

 9993 23:10:10.520270  INFO:    ARM GICv3 driver initialized in EL3

 9994 23:10:10.524149  INFO:    Maximum SPI INTID supported: 639

 9995 23:10:10.526875  INFO:    BL31: Initializing runtime services

 9996 23:10:10.534111  WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!

 9997 23:10:10.534205  INFO:    SPM: enable CPC mode

 9998 23:10:10.540558  INFO:    mcdi ready for mcusys-off-idle and system suspend

 9999 23:10:10.543572  INFO:    BL31: Preparing for EL3 exit to normal world

10000 23:10:10.547118  INFO:    Entry point address = 0x80000000

10001 23:10:10.550557  INFO:    SPSR = 0x8

10002 23:10:10.556473  

10003 23:10:10.556585  

10004 23:10:10.556654  

10005 23:10:10.559581  Starting depthcharge on Spherion...

10006 23:10:10.559665  

10007 23:10:10.559731  Wipe memory regions:

10008 23:10:10.559793  

10009 23:10:10.560552  end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10010 23:10:10.560660  start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10011 23:10:10.560745  Setting prompt string to ['asurada:']
10012 23:10:10.560827  bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10013 23:10:10.562823  	[0x00000040000000, 0x00000054600000)

10014 23:10:10.685053  

10015 23:10:10.685184  	[0x00000054660000, 0x00000080000000)

10016 23:10:10.946243  

10017 23:10:10.946393  	[0x000000821a7280, 0x000000ffe64000)

10018 23:10:11.690889  

10019 23:10:11.691029  	[0x00000100000000, 0x00000240000000)

10020 23:10:13.581082  

10021 23:10:13.584073  Initializing XHCI USB controller at 0x11200000.

10022 23:10:14.621776  

10023 23:10:14.625328  [firmware-asurada-13885.B-collabora] Dec  7 2021 09:38:38

10024 23:10:14.625476  

10025 23:10:14.625614  

10026 23:10:14.625742  

10027 23:10:14.626097  Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10029 23:10:14.726495  asurada: tftpboot 192.168.201.1 12395368/tftp-deploy-rxfkiwk3/kernel/image.itb 12395368/tftp-deploy-rxfkiwk3/kernel/cmdline 

10030 23:10:14.726636  Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10031 23:10:14.726727  bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10032 23:10:14.731335  tftpboot 192.168.201.1 12395368/tftp-deploy-rxfkiwk3/kernel/image.ittp-deploy-rxfkiwk3/kernel/cmdline 

10033 23:10:14.731447  

10034 23:10:14.731551  Waiting for link

10035 23:10:14.891574  

10036 23:10:14.891731  R8152: Initializing

10037 23:10:14.891852  

10038 23:10:14.894593  Version 9 (ocp_data = 6010)

10039 23:10:14.894703  

10040 23:10:14.898276  R8152: Done initializing

10041 23:10:14.898387  

10042 23:10:14.898487  Adding net device

10043 23:10:16.843677  

10044 23:10:16.843891  done.

10045 23:10:16.844002  

10046 23:10:16.844115  MAC: 00:e0:4c:78:7a:aa

10047 23:10:16.844207  

10048 23:10:16.847003  Sending DHCP discover... done.

10049 23:10:16.847143  

10050 23:10:20.029375  Waiting for reply... done.

10051 23:10:20.029531  

10052 23:10:20.029604  Sending DHCP request... done.

10053 23:10:20.031998  

10054 23:10:20.037722  Waiting for reply... done.

10055 23:10:20.037912  

10056 23:10:20.038006  My ip is 192.168.201.12

10057 23:10:20.038096  

10058 23:10:20.040826  The DHCP server ip is 192.168.201.1

10059 23:10:20.040910  

10060 23:10:20.047318  TFTP server IP predefined by user: 192.168.201.1

10061 23:10:20.047401  

10062 23:10:20.053874  Bootfile predefined by user: 12395368/tftp-deploy-rxfkiwk3/kernel/image.itb

10063 23:10:20.053961  

10064 23:10:20.057649  Sending tftp read request... done.

10065 23:10:20.057751  

10066 23:10:20.057883  Waiting for the transfer... 

10067 23:10:20.057972  

10068 23:10:20.318220  00000000 ################################################################

10069 23:10:20.318383  

10070 23:10:20.581401  00080000 ################################################################

10071 23:10:20.581580  

10072 23:10:20.832866  00100000 ################################################################

10073 23:10:20.833002  

10074 23:10:21.086236  00180000 ################################################################

10075 23:10:21.086396  

10076 23:10:21.340249  00200000 ################################################################

10077 23:10:21.340426  

10078 23:10:21.598446  00280000 ################################################################

10079 23:10:21.598607  

10080 23:10:21.853919  00300000 ################################################################

10081 23:10:21.854094  

10082 23:10:22.106848  00380000 ################################################################

10083 23:10:22.106985  

10084 23:10:22.359089  00400000 ################################################################

10085 23:10:22.359226  

10086 23:10:22.621666  00480000 ################################################################

10087 23:10:22.621833  

10088 23:10:22.876735  00500000 ################################################################

10089 23:10:22.876927  

10090 23:10:23.124559  00580000 ################################################################

10091 23:10:23.124724  

10092 23:10:23.376057  00600000 ################################################################

10093 23:10:23.376220  

10094 23:10:23.627674  00680000 ################################################################

10095 23:10:23.627840  

10096 23:10:23.880481  00700000 ################################################################

10097 23:10:23.880678  

10098 23:10:24.143354  00780000 ################################################################

10099 23:10:24.143496  

10100 23:10:24.426084  00800000 ################################################################

10101 23:10:24.426223  

10102 23:10:24.689055  00880000 ################################################################

10103 23:10:24.689252  

10104 23:10:24.955480  00900000 ################################################################

10105 23:10:24.955619  

10106 23:10:25.211881  00980000 ################################################################

10107 23:10:25.212145  

10108 23:10:25.473708  00a00000 ################################################################

10109 23:10:25.473884  

10110 23:10:25.730506  00a80000 ################################################################

10111 23:10:25.730703  

10112 23:10:25.983336  00b00000 ################################################################

10113 23:10:25.983532  

10114 23:10:26.248784  00b80000 ################################################################

10115 23:10:26.248922  

10116 23:10:26.510030  00c00000 ################################################################

10117 23:10:26.510167  

10118 23:10:26.765040  00c80000 ################################################################

10119 23:10:26.765237  

10120 23:10:27.027295  00d00000 ################################################################

10121 23:10:27.027489  

10122 23:10:27.318472  00d80000 ################################################################

10123 23:10:27.318679  

10124 23:10:27.591642  00e00000 ################################################################

10125 23:10:27.591846  

10126 23:10:27.869286  00e80000 ################################################################

10127 23:10:27.869494  

10128 23:10:28.129632  00f00000 ################################################################

10129 23:10:28.129850  

10130 23:10:28.398514  00f80000 ################################################################

10131 23:10:28.398654  

10132 23:10:28.660851  01000000 ################################################################

10133 23:10:28.660994  

10134 23:10:28.962854  01080000 ################################################################

10135 23:10:28.962995  

10136 23:10:29.238312  01100000 ################################################################

10137 23:10:29.238517  

10138 23:10:29.505673  01180000 ################################################################

10139 23:10:29.505833  

10140 23:10:29.769753  01200000 ################################################################

10141 23:10:29.769884  

10142 23:10:30.032339  01280000 ################################################################

10143 23:10:30.032472  

10144 23:10:30.293871  01300000 ################################################################

10145 23:10:30.294012  

10146 23:10:30.585642  01380000 ################################################################

10147 23:10:30.585773  

10148 23:10:30.856178  01400000 ################################################################

10149 23:10:30.856376  

10150 23:10:31.131366  01480000 ################################################################

10151 23:10:31.131511  

10152 23:10:31.411005  01500000 ################################################################

10153 23:10:31.411169  

10154 23:10:31.667230  01580000 ################################################################

10155 23:10:31.667390  

10156 23:10:31.928181  01600000 ################################################################

10157 23:10:31.928396  

10158 23:10:32.192143  01680000 ################################################################

10159 23:10:32.192279  

10160 23:10:32.468039  01700000 ################################################################

10161 23:10:32.468209  

10162 23:10:32.751462  01780000 ################################################################

10163 23:10:32.751657  

10164 23:10:33.042772  01800000 ################################################################

10165 23:10:33.042911  

10166 23:10:33.323588  01880000 ################################################################

10167 23:10:33.323796  

10168 23:10:33.574170  01900000 ################################################################

10169 23:10:33.574312  

10170 23:10:33.856942  01980000 ################################################################

10171 23:10:33.857106  

10172 23:10:34.116637  01a00000 ################################################################

10173 23:10:34.116793  

10174 23:10:34.384232  01a80000 ################################################################

10175 23:10:34.384474  

10176 23:10:34.641365  01b00000 ################################################################

10177 23:10:34.641498  

10178 23:10:34.907953  01b80000 ################################################################

10179 23:10:34.908115  

10180 23:10:35.167952  01c00000 ################################################################

10181 23:10:35.168087  

10182 23:10:35.426751  01c80000 ################################################################

10183 23:10:35.427041  

10184 23:10:35.699857  01d00000 ################################################################

10185 23:10:35.700046  

10186 23:10:35.978919  01d80000 ################################################################

10187 23:10:35.979067  

10188 23:10:36.243862  01e00000 ################################################################

10189 23:10:36.244009  

10190 23:10:36.503982  01e80000 ################################################################

10191 23:10:36.504187  

10192 23:10:36.768999  01f00000 ################################################################

10193 23:10:36.769134  

10194 23:10:37.030193  01f80000 ################################################################

10195 23:10:37.030385  

10196 23:10:37.297801  02000000 ################################################################

10197 23:10:37.297973  

10198 23:10:37.577018  02080000 ################################################################

10199 23:10:37.577212  

10200 23:10:37.835939  02100000 ################################################################

10201 23:10:37.836138  

10202 23:10:38.122961  02180000 ################################################################

10203 23:10:38.123163  

10204 23:10:38.407869  02200000 ################################################################

10205 23:10:38.408089  

10206 23:10:38.674125  02280000 ################################################################

10207 23:10:38.674278  

10208 23:10:38.944642  02300000 ################################################################

10209 23:10:38.944871  

10210 23:10:39.218861  02380000 ################################################################

10211 23:10:39.219078  

10212 23:10:39.476116  02400000 ################################################################

10213 23:10:39.476294  

10214 23:10:39.756037  02480000 ################################################################

10215 23:10:39.756175  

10216 23:10:40.017837  02500000 ################################################################

10217 23:10:40.017982  

10218 23:10:40.283922  02580000 ################################################################

10219 23:10:40.284153  

10220 23:10:40.541626  02600000 ################################################################

10221 23:10:40.541801  

10222 23:10:40.808492  02680000 ################################################################

10223 23:10:40.808630  

10224 23:10:41.076730  02700000 ################################################################

10225 23:10:41.076900  

10226 23:10:41.352646  02780000 ################################################################

10227 23:10:41.352843  

10228 23:10:41.611658  02800000 ################################################################

10229 23:10:41.611845  

10230 23:10:41.955859  02880000 ################################################################

10231 23:10:41.956019  

10232 23:10:42.313674  02900000 ################################################################

10233 23:10:42.313886  

10234 23:10:42.661531  02980000 ################################################################

10235 23:10:42.661728  

10236 23:10:42.997186  02a00000 ################################################################

10237 23:10:42.997328  

10238 23:10:43.267121  02a80000 ################################################################

10239 23:10:43.267259  

10240 23:10:43.548538  02b00000 ################################################################

10241 23:10:43.548685  

10242 23:10:43.831176  02b80000 ################################################################

10243 23:10:43.831371  

10244 23:10:44.134584  02c00000 ################################################################

10245 23:10:44.134741  

10246 23:10:44.417593  02c80000 ################################################################

10247 23:10:44.417730  

10248 23:10:44.697920  02d00000 ################################################################

10249 23:10:44.698119  

10250 23:10:44.987132  02d80000 ################################################################

10251 23:10:44.987296  

10252 23:10:45.272279  02e00000 ################################################################

10253 23:10:45.272474  

10254 23:10:45.558999  02e80000 ################################################################

10255 23:10:45.559169  

10256 23:10:45.829148  02f00000 ################################################################

10257 23:10:45.829282  

10258 23:10:46.101797  02f80000 ################################################################

10259 23:10:46.101992  

10260 23:10:46.388882  03000000 ################################################################

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10262 23:10:46.692182  03080000 ################################################################

10263 23:10:46.692374  

10264 23:10:46.977151  03100000 ################################################################

10265 23:10:46.977361  

10266 23:10:47.265760  03180000 ################################################################

10267 23:10:47.265927  

10268 23:10:47.543815  03200000 ################################################################

10269 23:10:47.543973  

10270 23:10:47.804894  03280000 ################################################################

10271 23:10:47.805046  

10272 23:10:48.090459  03300000 ################################################################

10273 23:10:48.090660  

10274 23:10:48.359509  03380000 ################################################################

10275 23:10:48.359646  

10276 23:10:48.612787  03400000 ################################################################

10277 23:10:48.612955  

10278 23:10:48.877614  03480000 ################################################################

10279 23:10:48.877762  

10280 23:10:49.141862  03500000 ################################################################

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10282 23:10:49.422403  03580000 ################################################################

10283 23:10:49.422601  

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10286 23:10:49.986111  03680000 ################################################################

10287 23:10:49.986253  

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10299 23:10:51.690206  

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10301 23:10:51.959416  

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10311 23:10:53.431702  

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10319 23:10:54.707537  

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10321 23:10:55.021807  

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10325 23:10:55.635505  

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10329 23:10:56.256986  

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10331 23:10:56.587560  

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10379 23:11:03.251945  

10380 23:11:03.514012  04e00000 ################################################################

10381 23:11:03.514159  

10382 23:11:03.775871  04e80000 ################################################################

10383 23:11:03.776020  

10384 23:11:04.049576  04f00000 ################################################################

10385 23:11:04.049721  

10386 23:11:04.323510  04f80000 ################################################################

10387 23:11:04.323652  

10388 23:11:04.596703  05000000 ################################################################

10389 23:11:04.596864  

10390 23:11:04.869925  05080000 ################################################################

10391 23:11:04.870133  

10392 23:11:05.153260  05100000 ################################################################

10393 23:11:05.153408  

10394 23:11:05.451139  05180000 ################################################################

10395 23:11:05.451287  

10396 23:11:05.744114  05200000 ################################################################

10397 23:11:05.744274  

10398 23:11:06.038819  05280000 ################################################################

10399 23:11:06.038996  

10400 23:11:06.335768  05300000 ################################################################

10401 23:11:06.335986  

10402 23:11:06.613074  05380000 ################################################################

10403 23:11:06.613215  

10404 23:11:06.907522  05400000 ################################################################

10405 23:11:06.907680  

10406 23:11:07.202453  05480000 ################################################################

10407 23:11:07.202599  

10408 23:11:07.502037  05500000 ################################################################

10409 23:11:07.502182  

10410 23:11:07.799798  05580000 ################################################################

10411 23:11:07.799947  

10412 23:11:08.093694  05600000 ################################################################

10413 23:11:08.093830  

10414 23:11:08.378724  05680000 ################################################################

10415 23:11:08.378938  

10416 23:11:08.670453  05700000 ################################################################

10417 23:11:08.670596  

10418 23:11:08.956869  05780000 ################################################################

10419 23:11:08.957072  

10420 23:11:09.239470  05800000 ################################################################

10421 23:11:09.239678  

10422 23:11:09.532513  05880000 ################################################################

10423 23:11:09.532664  

10424 23:11:09.831453  05900000 ################################################################

10425 23:11:09.831663  

10426 23:11:10.119781  05980000 ################################################################

10427 23:11:10.119927  

10428 23:11:10.404866  05a00000 ################################################################

10429 23:11:10.405011  

10430 23:11:10.705995  05a80000 ################################################################

10431 23:11:10.706159  

10432 23:11:10.989782  05b00000 ################################################################

10433 23:11:10.989925  

10434 23:11:11.276101  05b80000 ################################################################

10435 23:11:11.276242  

10436 23:11:11.566586  05c00000 ################################################################

10437 23:11:11.566762  

10438 23:11:11.861167  05c80000 ################################################################

10439 23:11:11.861307  

10440 23:11:12.155251  05d00000 ################################################################

10441 23:11:12.155397  

10442 23:11:12.450838  05d80000 ################################################################

10443 23:11:12.451050  

10444 23:11:12.735272  05e00000 ################################################################

10445 23:11:12.735478  

10446 23:11:13.034592  05e80000 ################################################################

10447 23:11:13.034798  

10448 23:11:13.331523  05f00000 ################################################################

10449 23:11:13.331697  

10450 23:11:13.620749  05f80000 ################################################################

10451 23:11:13.620895  

10452 23:11:13.908018  06000000 ################################################################

10453 23:11:13.908162  

10454 23:11:14.194821  06080000 ################################################################

10455 23:11:14.194967  

10456 23:11:14.477543  06100000 ################################################################

10457 23:11:14.477689  

10458 23:11:14.747573  06180000 ################################################################

10459 23:11:14.747783  

10460 23:11:15.019821  06200000 ################################################################

10461 23:11:15.019995  

10462 23:11:15.302897  06280000 ################################################################

10463 23:11:15.303113  

10464 23:11:15.584255  06300000 ################################################################

10465 23:11:15.584444  

10466 23:11:15.877844  06380000 ################################################################

10467 23:11:15.878051  

10468 23:11:16.164739  06400000 ################################################################

10469 23:11:16.164937  

10470 23:11:16.465886  06480000 ################################################################

10471 23:11:16.466032  

10472 23:11:16.749385  06500000 ################################################################

10473 23:11:16.749534  

10474 23:11:17.015563  06580000 ################################################################

10475 23:11:17.015760  

10476 23:11:17.301728  06600000 ################################################################

10477 23:11:17.301870  

10478 23:11:17.583877  06680000 ################################################################

10479 23:11:17.584020  

10480 23:11:17.850775  06700000 ################################################################

10481 23:11:17.850936  

10482 23:11:18.140356  06780000 ################################################################

10483 23:11:18.140511  

10484 23:11:18.414771  06800000 ################################################################

10485 23:11:18.414929  

10486 23:11:18.567843  06880000 ##################################### done.

10487 23:11:18.567979  

10488 23:11:18.571513  The bootfile was 109878630 bytes long.

10489 23:11:18.571598  

10490 23:11:18.574607  Sending tftp read request... done.

10491 23:11:18.574690  

10492 23:11:18.574756  Waiting for the transfer... 

10493 23:11:18.574817  

10494 23:11:18.578016  00000000 # done.

10495 23:11:18.578101  

10496 23:11:18.584660  Command line loaded dynamically from TFTP file: 12395368/tftp-deploy-rxfkiwk3/kernel/cmdline

10497 23:11:18.584769  

10498 23:11:18.597801  The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1

10499 23:11:18.597887  

10500 23:11:18.601282  Loading FIT.

10501 23:11:18.601415  

10502 23:11:18.604216  Image ramdisk-1 has 98348930 bytes.

10503 23:11:18.604357  

10504 23:11:18.608177  Image fdt-1 has 47278 bytes.

10505 23:11:18.608292  

10506 23:11:18.608394  Image kernel-1 has 11480388 bytes.

10507 23:11:18.608455  

10508 23:11:18.617625  Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion

10509 23:11:18.617709  

10510 23:11:18.634276  Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192

10511 23:11:18.634364  

10512 23:11:18.640923  Choosing best match conf-1 for compat google,spherion-rev2.

10513 23:11:18.645067  

10514 23:11:18.649680  Connected to device vid:did:rid of 1ae0:0028:00

10515 23:11:18.658187  

10516 23:11:18.661606  tpm_get_response: command 0x17b, return code 0x0

10517 23:11:18.661689  

10518 23:11:18.665020  ec_init: CrosEC protocol v3 supported (256, 248)

10519 23:11:18.669756  

10520 23:11:18.673065  tpm_cleanup: add release locality here.

10521 23:11:18.673148  

10522 23:11:18.673214  Shutting down all USB controllers.

10523 23:11:18.675962  

10524 23:11:18.676045  Removing current net device

10525 23:11:18.676110  

10526 23:11:18.682995  Exiting depthcharge with code 4 at timestamp: 97378204

10527 23:11:18.683103  

10528 23:11:18.686425  LZMA decompressing kernel-1 to 0x821a6718

10529 23:11:18.686507  

10530 23:11:18.689511  LZMA decompressing kernel-1 to 0x40000000

10531 23:11:20.126140  

10532 23:11:20.126295  jumping to kernel

10533 23:11:20.126855  end: 2.2.4 bootloader-commands (duration 00:01:10) [common]
10534 23:11:20.126958  start: 2.2.5 auto-login-action (timeout 00:03:16) [common]
10535 23:11:20.127036  Setting prompt string to ['Linux version [0-9]']
10536 23:11:20.127104  Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10537 23:11:20.127173  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10538 23:11:20.208680  

10539 23:11:20.212181  [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]

10540 23:11:20.215771  start: 2.2.5.1 login-action (timeout 00:03:16) [common]
10541 23:11:20.215861  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10542 23:11:20.215931  Setting prompt string to []
10543 23:11:20.216011  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10544 23:11:20.216085  Using line separator: #'\n'#
10545 23:11:20.216144  No login prompt set.
10546 23:11:20.216205  Parsing kernel messages
10547 23:11:20.216260  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10548 23:11:20.216409  [login-action] Waiting for messages, (timeout 00:03:16)
10549 23:11:20.235014  [    0.000000] Linux version 6.1.67-cip12-rt7 (KernelCI@build-j59954-arm64-gcc-10-defconfig-arm64-chromebook-nblph) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023

10550 23:11:20.238199  [    0.000000] random: crng init done

10551 23:11:20.244840  [    0.000000] Machine model: Google Spherion (rev0 - 3)

10552 23:11:20.248500  [    0.000000] efi: UEFI not found.

10553 23:11:20.254836  [    0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB

10554 23:11:20.265345  [    0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool

10555 23:11:20.274935  [    0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB

10556 23:11:20.281640  [    0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool

10557 23:11:20.288109  [    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')

10558 23:11:20.295011  [    0.000000] printk: bootconsole [mtk8250] enabled

10559 23:11:20.301259  [    0.000000] NUMA: No NUMA configuration found

10560 23:11:20.308120  [    0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]

10561 23:11:20.314642  [    0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]

10562 23:11:20.314724  [    0.000000] Zone ranges:

10563 23:11:20.321418  [    0.000000]   DMA      [mem 0x0000000040000000-0x00000000ffffffff]

10564 23:11:20.325012  [    0.000000]   DMA32    empty

10565 23:11:20.330870  [    0.000000]   Normal   [mem 0x0000000100000000-0x000000023fffffff]

10566 23:11:20.334401  [    0.000000] Movable zone start for each node

10567 23:11:20.337478  [    0.000000] Early memory node ranges

10568 23:11:20.344489  [    0.000000]   node   0: [mem 0x0000000040000000-0x000000004fffffff]

10569 23:11:20.350910  [    0.000000]   node   0: [mem 0x0000000050000000-0x00000000528fffff]

10570 23:11:20.357769  [    0.000000]   node   0: [mem 0x0000000052900000-0x00000000545fffff]

10571 23:11:20.364230  [    0.000000]   node   0: [mem 0x0000000054700000-0x00000000ffdfffff]

10572 23:11:20.370585  [    0.000000]   node   0: [mem 0x0000000100000000-0x000000023fffffff]

10573 23:11:20.377464  [    0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]

10574 23:11:20.433309  [    0.000000] On node 0, zone DMA: 256 pages in unavailable ranges

10575 23:11:20.439555  [    0.000000] On node 0, zone Normal: 512 pages in unavailable ranges

10576 23:11:20.446322  [    0.000000] cma: Reserved 32 MiB at 0x00000000fde00000

10577 23:11:20.449464  [    0.000000] psci: probing for conduit method from DT.

10578 23:11:20.456046  [    0.000000] psci: PSCIv1.1 detected in firmware.

10579 23:11:20.459872  [    0.000000] psci: Using standard PSCI v0.2 function IDs

10580 23:11:20.466244  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.

10581 23:11:20.469510  [    0.000000] psci: SMC Calling Convention v1.2

10582 23:11:20.475824  [    0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016

10583 23:11:20.479391  [    0.000000] Detected VIPT I-cache on CPU0

10584 23:11:20.485825  [    0.000000] CPU features: detected: GIC system register CPU interface

10585 23:11:20.492387  [    0.000000] CPU features: detected: Virtualization Host Extensions

10586 23:11:20.499033  [    0.000000] CPU features: kernel page table isolation forced ON by KASLR

10587 23:11:20.505743  [    0.000000] CPU features: detected: Kernel page table isolation (KPTI)

10588 23:11:20.515680  [    0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009

10589 23:11:20.522063  [    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923

10590 23:11:20.525673  [    0.000000] alternatives: applying boot alternatives

10591 23:11:20.532155  [    0.000000] Fallback order for Node 0: 0 

10592 23:11:20.539210  [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2063616

10593 23:11:20.542448  [    0.000000] Policy zone: Normal

10594 23:11:20.555609  [    0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1

10595 23:11:20.565617  <5>[    0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.

10596 23:11:20.577739  <6>[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)

10597 23:11:20.587630  <6>[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)

10598 23:11:20.594273  <6>[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off

10599 23:11:20.597815  <6>[    0.000000] software IO TLB: area num 8.

10600 23:11:20.654011  <6>[    0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)

10601 23:11:20.803735  <6>[    0.000000] Memory: 7872676K/8385536K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 480092K reserved, 32768K cma-reserved)

10602 23:11:20.809946  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1

10603 23:11:20.816813  <6>[    0.000000] rcu: Preemptible hierarchical RCU implementation.

10604 23:11:20.819816  <6>[    0.000000] rcu: 	RCU event tracing is enabled.

10605 23:11:20.826407  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.

10606 23:11:20.833169  <6>[    0.000000] 	Trampoline variant of Tasks RCU enabled.

10607 23:11:20.836626  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.

10608 23:11:20.846591  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.

10609 23:11:20.852885  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8

10610 23:11:20.859597  <6>[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0

10611 23:11:20.866304  <6>[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode

10612 23:11:20.869638  <6>[    0.000000] GICv3: 608 SPIs implemented

10613 23:11:20.872879  <6>[    0.000000] GICv3: 0 Extended SPIs implemented

10614 23:11:20.879641  <6>[    0.000000] Root IRQ handler: gic_handle_irq

10615 23:11:20.883214  <6>[    0.000000] GICv3: GICv3 features: 16 PPIs

10616 23:11:20.889397  <6>[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000

10617 23:11:20.902477  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }

10618 23:11:20.912834  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }

10619 23:11:20.922652  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.

10620 23:11:20.929911  <6>[    0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).

10621 23:11:20.943440  <6>[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns

10622 23:11:20.949636  <6>[    0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns

10623 23:11:20.956841  <6>[    0.009234] Console: colour dummy device 80x25

10624 23:11:20.966247  <6>[    0.013984] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)

10625 23:11:20.969863  <6>[    0.024426] pid_max: default: 32768 minimum: 301

10626 23:11:20.976455  <6>[    0.029299] LSM: Security Framework initializing

10627 23:11:20.983267  <6>[    0.034266] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10628 23:11:20.993055  <6>[    0.042080] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10629 23:11:20.999450  <6>[    0.051488] cblist_init_generic: Setting adjustable number of callback queues.

10630 23:11:21.006276  <6>[    0.058931] cblist_init_generic: Setting shift to 3 and lim to 1.

10631 23:11:21.016470  <6>[    0.065269] cblist_init_generic: Setting adjustable number of callback queues.

10632 23:11:21.019462  <6>[    0.072696] cblist_init_generic: Setting shift to 3 and lim to 1.

10633 23:11:21.026283  <6>[    0.079134] rcu: Hierarchical SRCU implementation.

10634 23:11:21.032832  <6>[    0.079136] rcu: 	Max phase no-delay instances is 1000.

10635 23:11:21.039522  <6>[    0.079160] printk: bootconsole [mtk8250] printing thread started

10636 23:11:21.046322  <6>[    0.097477] EFI services will not be available.

10637 23:11:21.049276  <6>[    0.097677] smp: Bringing up secondary CPUs ...

10638 23:11:21.052996  <6>[    0.097987] Detected VIPT I-cache on CPU1

10639 23:11:21.059669  <6>[    0.098056] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

10640 23:11:21.066186  <6>[    0.098086] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

10641 23:11:21.078060  <6>[    0.125912] Detected VIPT I-cache on CPU2

10642 23:11:21.084647  <6>[    0.125958] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

10643 23:11:21.094783  <6>[    0.125973] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

10644 23:11:21.097667  <6>[    0.126232] Detected VIPT I-cache on CPU3

10645 23:11:21.104658  <6>[    0.126277] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

10646 23:11:21.111150  <6>[    0.126292] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

10647 23:11:21.114751  <6>[    0.126608] CPU features: detected: Spectre-v4

10648 23:11:21.121290  <6>[    0.126614] CPU features: detected: Spectre-BHB

10649 23:11:21.124491  <6>[    0.126619] Detected PIPT I-cache on CPU4

10650 23:11:21.131575  <6>[    0.126680] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

10651 23:11:21.137588  <6>[    0.126697] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

10652 23:11:21.144460  <6>[    0.126990] Detected PIPT I-cache on CPU5

10653 23:11:21.151127  <6>[    0.127054] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

10654 23:11:21.158276  <6>[    0.127070] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

10655 23:11:21.161319  <6>[    0.127346] Detected PIPT I-cache on CPU6

10656 23:11:21.167893  <6>[    0.127412] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

10657 23:11:21.174466  <6>[    0.127428] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

10658 23:11:21.180932  <6>[    0.127721] Detected PIPT I-cache on CPU7

10659 23:11:21.187817  <6>[    0.127786] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

10660 23:11:21.194008  <6>[    0.127802] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

10661 23:11:21.197708  <6>[    0.127849] smp: Brought up 1 node, 8 CPUs

10662 23:11:21.204479  <6>[    0.127853] SMP: Total of 8 processors activated.

10663 23:11:21.207610  <6>[    0.127856] CPU features: detected: 32-bit EL0 Support

10664 23:11:21.217887  <6>[    0.127858] CPU features: detected: Data cache clean to the PoU not required for I/D coherence

10665 23:11:21.224363  <6>[    0.127860] CPU features: detected: Common not Private translations

10666 23:11:21.230598  <6>[    0.127862] CPU features: detected: CRC32 instructions

10667 23:11:21.233933  <6>[    0.127865] CPU features: detected: RCpc load-acquire (LDAPR)

10668 23:11:21.240633  <6>[    0.127866] CPU features: detected: LSE atomic instructions

10669 23:11:21.247215  <6>[    0.127868] CPU features: detected: Privileged Access Never

10670 23:11:21.254006  <6>[    0.127870] CPU features: detected: RAS Extension Support

10671 23:11:21.260541  <6>[    0.127873] CPU features: detected: Speculative Store Bypassing Safe (SSBS)

10672 23:11:21.263513  <6>[    0.127937] CPU: All CPU(s) started at EL2

10673 23:11:21.270722  <6>[    0.127939] alternatives: applying system-wide alternatives

10674 23:11:21.273789  <6>[    0.141023] devtmpfs: initialized

10675 23:11:21.283700  <6>[    0.147252] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns

10676 23:11:21.311803  � ������ѕɕ���}%9Q��ɽѽ����2�����5R�<6>[    0.36<4657] printk: console [ttyS0] printing thread started

10677 23:11:21.318457  6><6>[    0.364694] printk: console [ttyS0] enabled

10678 23:11:21.325051  [    0.228869] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)

10679 23:11:21.333053  <6>[    0.364699] printk: bootconsole [mtk8250] disabled

10680 23:11:21.339525  <6>[    0.382767] printk: bootconsole [mtk8250] printing thread stopped

10681 23:11:21.342947  <6>[    0.384064] SuperH (H)SCI(F) driver initialized

10682 23:11:21.349386  <6>[    0.384559] msm_serial: driver initialized

10683 23:11:21.355825  <6>[    0.389353] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000

10684 23:11:21.366000  <6>[    0.389383] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000

10685 23:11:21.372275  <6>[    0.389413] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000

10686 23:11:21.382396  <6>[    0.389443] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000

10687 23:11:21.400775  <6>[    0.389464] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000

10688 23:11:21.400879  <6>[    0.389495] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000

10689 23:11:21.417773  <6>[    0.389523] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000

10690 23:11:21.417860  <6>[    0.389647] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000

10691 23:11:21.431508  <6>[    0.389676] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000

10692 23:11:21.434965  <6>[    0.400477] loop: module loaded

10693 23:11:21.439791  <6>[    0.403089] vgpu11_sshub: Bringing 400000uV into 575000-575000uV

10694 23:11:21.443207  <4>[    0.419942] mtk-pmic-keys: Failed to locate of_node [id: -1]

10695 23:11:21.446565  <6>[    0.420831] megasas: 07.719.03.00-rc1

10696 23:11:21.452860  <6>[    0.432968] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2

10697 23:11:21.456445  <6>[    0.433045] spi-nor spi2.0: w25q64jwm (8192 Kbytes)

10698 23:11:21.462774  <6>[    0.444995] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)

10699 23:11:21.472569  <6>[    0.498902] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b

10700 23:11:25.208445  <6>[    4.259231] Freeing initrd memory: 96040K

10701 23:11:25.215246  <6>[    4.265502] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz

10702 23:11:25.218138  <6>[    4.270305] tun: Universal TUN/TAP device driver, 1.6

10703 23:11:25.221865  <6>[    4.271093] thunder_xcv, ver 1.0

10704 23:11:25.224972  <6>[    4.271110] thunder_bgx, ver 1.0

10705 23:11:25.228535  <6>[    4.271138] nicpf, ver 1.0

10706 23:11:25.237928  <6>[    4.272220] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version

10707 23:11:25.241538  <6>[    4.272224] hns3: Copyright (c) 2017 Huawei Corporation.

10708 23:11:25.244842  <6>[    4.272250] hclge is initializing

10709 23:11:25.251262  <6>[    4.272265] e1000: Intel(R) PRO/1000 Network Driver

10710 23:11:25.258288  <6>[    4.272267] e1000: Copyright (c) 1999-2006 Intel Corporation.

10711 23:11:25.261894  <6>[    4.272283] e1000e: Intel(R) PRO/1000 Network Driver

10712 23:11:25.269303  <6>[    4.272284] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.

10713 23:11:25.272927  <6>[    4.272302] igb: Intel(R) Gigabit Ethernet Network Driver

10714 23:11:25.279494  <6>[    4.272304] igb: Copyright (c) 2007-2014 Intel Corporation.

10715 23:11:25.286074  <6>[    4.272317] igbvf: Intel(R) Gigabit Virtual Function Network Driver

10716 23:11:25.293417  <6>[    4.272319] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.

10717 23:11:25.296984  <6>[    4.272617] sky2: driver version 1.30

10718 23:11:25.299962  <6>[    4.273749] VFIO - User Level meta-driver version: 0.3

10719 23:11:25.306533  <6>[    4.276695] usbcore: registered new interface driver usb-storage

10720 23:11:25.313053  <6>[    4.276877] usbcore: registered new device driver onboard-usb-hub

10721 23:11:25.319826  <6>[    4.279727] mt6397-rtc mt6359-rtc: registered as rtc0

10722 23:11:25.329753  <6>[    4.279881] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-27T23:08:54 UTC (1703718534)

10723 23:11:25.332860  <6>[    4.280513] i2c_dev: i2c /dev entries driver

10724 23:11:25.339451  <6>[    4.287897] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)

10725 23:11:25.346334  <6>[    4.303907] cpu cpu0: EM: created perf domain

10726 23:11:25.349888  <6>[    4.304229] cpu cpu4: EM: created perf domain

10727 23:11:25.356606  <6>[    4.309241] sdhci: Secure Digital Host Controller Interface driver

10728 23:11:25.359482  <6>[    4.309242] sdhci: Copyright(c) Pierre Ossman

10729 23:11:25.366530  <6>[    4.309609] Synopsys Designware Multimedia Card Interface Driver

10730 23:11:25.372882  <6>[    4.310026] sdhci-pltfm: SDHCI platform and OF driver helper

10731 23:11:25.379538  <6>[    4.315184] ledtrig-cpu: registered to indicate activity on CPUs

10732 23:11:25.383186  <6>[    4.315688] mmc0: CQHCI version 5.10

10733 23:11:25.389537  <6>[    4.316019] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000

10734 23:11:25.396187  <6>[    4.316306] usbcore: registered new interface driver usbhid

10735 23:11:25.399553  <6>[    4.316308] usbhid: USB HID core driver

10736 23:11:25.406204  <6>[    4.316436] spi_master spi0: will run message pump with realtime priority

10737 23:11:25.419845  <6>[    4.343640] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0

10738 23:11:25.432799  <6>[    4.346747] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1

10739 23:11:25.439559  <6>[    4.347815] cros-ec-spi spi0.0: Chrome EC device registered

10740 23:11:25.449248  <6>[    4.360187] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)

10741 23:11:25.452926  <6>[    4.361174] NET: Registered PF_PACKET protocol family

10742 23:11:25.459463  <6>[    4.361250] 9pnet: Installing 9P2000 support

10743 23:11:25.462559  <5>[    4.361285] Key type dns_resolver registered

10744 23:11:25.465610  <6>[    4.361583] registered taskstats version 1

10745 23:11:25.472834  <5>[    4.361598] Loading compiled-in X.509 certificates

10746 23:11:25.482495  <4>[    4.379285] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10747 23:11:25.492406  <4>[    4.379525] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10748 23:11:25.498997  <3>[    4.379549] debugfs: File 'uA_load' in directory '/' already present!

10749 23:11:25.505640  <3>[    4.379560] debugfs: File 'min_uV' in directory '/' already present!

10750 23:11:25.512159  <3>[    4.379566] debugfs: File 'max_uV' in directory '/' already present!

10751 23:11:25.519244  <3>[    4.379572] debugfs: File 'constraint_flags' in directory '/' already present!

10752 23:11:25.529200  <3>[    4.383079] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)

10753 23:11:25.535916  <6>[    4.391473] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102

10754 23:11:25.542073  <6>[    4.392158] xhci-mtk 11200000.usb: xHCI Host Controller

10755 23:11:25.548816  <6>[    4.392174] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1

10756 23:11:25.558842  <6>[    4.392367] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010

10757 23:11:25.561795  <6>[    4.392404] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000

10758 23:11:25.568559  <6>[    4.392481] xhci-mtk 11200000.usb: xHCI Host Controller

10759 23:11:25.575375  <6>[    4.392484] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2

10760 23:11:25.584941  <6>[    4.392488] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed

10761 23:11:25.588172  <6>[    4.392765] hub 1-0:1.0: USB hub found

10762 23:11:25.591680  <6>[    4.392774] hub 1-0:1.0: 1 port detected

10763 23:11:25.601355  <6>[    4.392864] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.

10764 23:11:25.604783  <6>[    4.392975] hub 2-0:1.0: USB hub found

10765 23:11:25.608237  <6>[    4.392980] hub 2-0:1.0: 1 port detected

10766 23:11:25.615041  <6>[    4.395260] mtk-msdc 11f70000.mmc: Got CD GPIO

10767 23:11:25.621483  <6>[    4.404230] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()

10768 23:11:25.628244  <6>[    4.404237] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()

10769 23:11:25.638333  <4>[    4.404309] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW

10770 23:11:25.644949  <6>[    4.404800] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()

10771 23:11:25.654717  <6>[    4.404801] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()

10772 23:11:25.661293  <6>[    4.404940] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()

10773 23:11:25.668543  <6>[    4.404952] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()

10774 23:11:25.678329  <6>[    4.404954] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()

10775 23:11:25.688185  <6>[    4.404955] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39

10776 23:11:25.694619  <6>[    4.406231] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)

10777 23:11:25.704561  <6>[    4.406246] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)

10778 23:11:25.711508  <6>[    4.406250] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)

10779 23:11:25.721072  <6>[    4.406253] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)

10780 23:11:25.727889  <6>[    4.406257] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)

10781 23:11:25.737505  <6>[    4.406261] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)

10782 23:11:25.744670  <6>[    4.406264] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)

10783 23:11:25.754442  <6>[    4.406268] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)

10784 23:11:25.760724  <6>[    4.406272] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)

10785 23:11:25.771038  <6>[    4.406276] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)

10786 23:11:25.777623  <6>[    4.406282] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)

10787 23:11:25.787523  <6>[    4.406286] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)

10788 23:11:25.794302  <6>[    4.406290] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)

10789 23:11:25.804274  <6>[    4.406293] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)

10790 23:11:25.810977  <6>[    4.406296] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)

10791 23:11:25.817449  <6>[    4.406605] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0

10792 23:11:25.824049  <6>[    4.407174] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0

10793 23:11:25.830739  <6>[    4.407404] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0

10794 23:11:25.837459  <6>[    4.407654] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0

10795 23:11:25.844142  <6>[    4.407902] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0

10796 23:11:25.854197  <6>[    4.408061] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)

10797 23:11:25.864172  <6>[    4.408070] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)

10798 23:11:25.870485  <6>[    4.408072] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)

10799 23:11:25.880564  <6>[    4.408075] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)

10800 23:11:25.890074  <6>[    4.408078] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)

10801 23:11:25.900469  <6>[    4.408081] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)

10802 23:11:25.910127  <6>[    4.408084] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)

10803 23:11:25.920516  <6>[    4.408087] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)

10804 23:11:25.926590  <6>[    4.408089] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)

10805 23:11:25.936480  <6>[    4.408093] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing

10806 23:11:25.950166  <6>[    4.408095] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing

10807 23:11:25.956882  <6>[    4.408799] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0

10808 23:11:25.959884  <6>[    4.415010] mmc0: Command Queue Engine enabled

10809 23:11:25.966584  <6>[    4.415022] mmc0: new HS400 Enhanced strobe MMC card at address 0001

10810 23:11:25.973122  <6>[    4.415519] mmcblk0: mmc0:0001 DA4128 116 GiB 

10811 23:11:25.979627  <6>[    4.418549]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12

10812 23:11:25.983193  <6>[    4.420002] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB 

10813 23:11:25.989640  <6>[    4.420545] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB 

10814 23:11:25.996122  <6>[    4.421050] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)

10815 23:11:26.002870  <6>[    4.773859] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk

10816 23:11:26.006043  <6>[    4.800494] hub 2-1:1.0: USB hub found

10817 23:11:26.009251  <6>[    4.800799] hub 2-1:1.0: 3 ports detected

10818 23:11:26.015820  <6>[    4.803180] hub 2-1:1.0: USB hub found

10819 23:11:26.019446  <6>[    4.803499] hub 2-1:1.0: 3 ports detected

10820 23:11:26.025781  <6>[    4.921646] usb 1-1: new high-speed USB device number 2 using xhci-mtk

10821 23:11:26.029391  <6>[    5.074678] hub 1-1:1.0: USB hub found

10822 23:11:26.032400  <6>[    5.075080] hub 1-1:1.0: 4 ports detected

10823 23:11:26.039362  <6>[    5.078442] hub 1-1:1.0: USB hub found

10824 23:11:26.042805  <6>[    5.078758] hub 1-1:1.0: 4 ports detected

10825 23:11:26.107427  <6>[    5.154092] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk

10826 23:11:26.343549  <6>[    5.389862] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk

10827 23:11:26.468349  <6>[    5.517646] hub 1-1.4:1.0: USB hub found

10828 23:11:26.471756  <6>[    5.518097] hub 1-1.4:1.0: 2 ports detected

10829 23:11:26.474618  <6>[    5.521852] hub 1-1.4:1.0: USB hub found

10830 23:11:26.481252  <6>[    5.522226] hub 1-1.4:1.0: 2 ports detected

10831 23:11:26.763206  <6>[    5.809852] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk

10832 23:11:26.947505  <6>[    5.993855] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk

10833 23:11:37.651973  <6>[   16.706855] ALSA device list:

10834 23:11:37.658358  <6>[   16.706877]   No soundcards found.

10835 23:11:37.661911  <6>[   16.711363] Freeing unused kernel memory: 8448K

10836 23:11:37.665066  <6>[   16.711575] Run /init as init process

10837 23:11:37.699012  <6>[   16.753312] NET: Registered PF_INET6 protocol family

10838 23:11:37.702010  <6>[   16.754490] Segment Routing with IPv6

10839 23:11:37.708714  <6>[   16.754506] In-situ OAM (IOAM) with IPv6

10840 23:11:37.738465  <30>[   16.772874] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)

10841 23:11:37.742206  <30>[   16.773429] systemd[1]: Detected architecture arm64.

10842 23:11:37.742290  

10843 23:11:37.748677  Welcome to Debian GNU/Linux 11 (bullseye)!

10844 23:11:37.748760  

10845 23:11:37.771186  <30>[   16.822043] systemd[1]: Set hostname to <debian-bullseye-arm64>.

10846 23:11:37.922228  <30>[   16.970864] systemd[1]: Queued start job for default target Graphical Interface.

10847 23:11:37.944060  [  OK  ] Created slic<30>[   16.994833] systemd[1]: Created slice system-getty.slice.

10848 23:11:37.947181  e system-getty.slice.

10849 23:11:37.970411  [  OK  ] Created slice syste<30>[   17.018442] systemd[1]: Created slice system-modprobe.slice.

10850 23:11:37.970496  m-modprobe.slice.

10851 23:11:37.994505  [  OK  ] Created slice syste<30>[   17.042683] systemd[1]: Created slice system-serial\x2dgetty.slice.

10852 23:11:37.998172  m-serial\x2dgetty.slice.

10853 23:11:38.015587  [  OK  ] Created slic<30>[   17.066768] systemd[1]: Created slice User and Session Slice.

10854 23:11:38.019061  e User and Session Slice.

10855 23:11:38.042742  [  OK  ] Started [0;<30>[   17.090637] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.

10856 23:11:38.046324  1;39mDispatch Password …ts to Console Directory Watch.

10857 23:11:38.070965  [  OK  ] Started Forward Pas<30>[   17.118584] systemd[1]: Started Forward Password Requests to Wall Directory Watch.

10858 23:11:38.074320  sword R…uests to Wall Directory Watch.

10859 23:11:38.102299  [  OK  ] Reached target Loca<30>[   17.146355] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.

10860 23:11:38.112154  l Encrypted Volu<30>[   17.146621] systemd[1]: Reached target Local Encrypted Volumes.

10861 23:11:38.112295  mes.

10862 23:11:38.131352  [  OK  ] Reached target Path<30>[   17.182389] systemd[1]: Reached target Paths.

10863 23:11:38.131480  s.

10864 23:11:38.153475  [  OK  ] Reached target Remo<30>[   17.201841] systemd[1]: Reached target Remote File Systems.

10865 23:11:38.153608  te File Systems.

10866 23:11:38.175206  [  OK  ] Reached target Slic<30>[   17.226235] systemd[1]: Reached target Slices.

10867 23:11:38.175315  es.

10868 23:11:38.194284  [  OK  ] Reached target Swap<30>[   17.245879] systemd[1]: Reached target Swap.

10869 23:11:38.194412  .

10870 23:11:38.218357  [  OK  ] Listening on initct<30>[   17.266319] systemd[1]: Listening on initctl Compatibility Named Pipe.

10871 23:11:38.221980  l Compatibility Named Pipe.

10872 23:11:38.228402  [  OK  [<30>[   17.281445] systemd[1]: Listening on Journal Audit Socket.

10873 23:11:38.235224  0m] Listening on Journal Audit Socket.

10874 23:11:38.254255  [  OK  ] Listening on Journa<30>[   17.302337] systemd[1]: Listening on Journal Socket (/dev/log).

10875 23:11:38.254382  l Socket (/dev/log).

10876 23:11:38.276097  [  OK  ] Listening on<30>[   17.327083] systemd[1]: Listening on Journal Socket.

10877 23:11:38.279134   Journal Socket.

10878 23:11:38.295077  [  OK  ] Listening on udev C<30>[   17.346428] systemd[1]: Listening on udev Control Socket.

10879 23:11:38.298518  ontrol Socket.

10880 23:11:38.319592  [  OK  ] Listening on<30>[   17.370880] systemd[1]: Listening on udev Kernel Socket.

10881 23:11:38.322663   udev Kernel Socket.

10882 23:11:38.382111           Mounting Huge Pages File Syste<30>[   17.430094] systemd[1]: Mounting Huge Pages File System...

10883 23:11:38.382198  m...

10884 23:11:38.400619           Mounting POSIX<30>[   17.451751] systemd[1]: Mounting POSIX Message Queue File System...

10885 23:11:38.403625   Message Queue File System...

10886 23:11:38.425642           Mountin<30>[   17.476535] systemd[1]: Mounting Kernel Debug File System...

10887 23:11:38.428677  g Kernel Debug File System...

10888 23:11:38.453039           Startin<30>[   17.498134] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.

10889 23:11:38.459769  <30>[   17.501012] systemd[1]: Starting Create list of static device nodes for the current kernel...

10890 23:11:38.466497  g Create list of st…odes for the current kernel...

10891 23:11:38.494606           Starting Load Kernel Module co<30>[   17.542188] systemd[1]: Starting Load Kernel Module configfs...

10892 23:11:38.494733  nfigfs...

10893 23:11:38.518353           Starting Load Kernel Module dr<30>[   17.566287] systemd[1]: Starting Load Kernel Module drm...

10894 23:11:38.518438  m...

10895 23:11:38.538208  <30>[   17.586359] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.

10896 23:11:38.552228           Starting Journ<30>[   17.603092] systemd[1]: Starting Journal Service...

10897 23:11:38.552371  al Service...

10898 23:11:38.575817           Starting Load <30>[   17.626822] systemd[1]: Starting Load Kernel Modules...

10899 23:11:38.578779  Kernel Modules...

10900 23:11:38.602928           Starting Remount Root and Kern<30>[   17.650501] systemd[1]: Starting Remount Root and Kernel File Systems...

10901 23:11:38.605819  el File Systems...

10902 23:11:38.630454           Starting Coldplug All udev Dev<30>[   17.678474] systemd[1]: Starting Coldplug All udev Devices...

10903 23:11:38.630538  ices...

10904 23:11:38.652227  [  OK  ] Started [0;<30>[   17.703566] systemd[1]: Started Journal Service.

10905 23:11:38.655747  1;39mJournal Service.

10906 23:11:38.671310  [  OK  ] Mounted Huge Pages File System.

10907 23:11:38.688587  [  OK  ] Mounted POSIX Message Queue File System.

10908 23:11:38.703849  [  OK  ] Mounted Kernel Debug File System.

10909 23:11:38.724935  [  OK  ] Finished Create list of st… nodes for the current kernel.

10910 23:11:38.746555  [  OK  ] Finished Load Kernel Module configfs.

10911 23:11:38.769439  [  OK  ] Finished Load Kernel Module drm.

10912 23:11:38.793626  [  OK  ] Finished Load Kernel Modules.

10913 23:11:38.817038  [FAILED] Failed to start Remount Root and Kernel File Systems.

10914 23:11:38.835300  See 'systemctl status systemd-remount-fs.service' for details.

10915 23:11:38.867825           Mounting Kernel Configuration File System...

10916 23:11:38.885675           Starting Flush Journal to Persistent Storage...

10917 23:11:38.906356  <46>[   17.955754] systemd-journald[191]: Received client request to flush runtime journal.

10918 23:11:38.914686           Starting Load/Save Random Seed...

10919 23:11:38.931627           Starting Apply Kernel Variables...

10920 23:11:38.952196           Starting Create System Users...

10921 23:11:38.971635  [  OK  ] Mounted Kernel Configuration File System.

10922 23:11:38.989570  [  OK  ] Finished Coldplug All udev Devices.

10923 23:11:39.012717  [  OK  ] Finished Flush Journal to Persistent Storage.

10924 23:11:39.029107  [  OK  ] Finished Load/Save Random Seed.

10925 23:11:39.048862  [  OK  ] Finished Apply Kernel Variables.

10926 23:11:39.065009  [  OK  ] Finished Create System Users.

10927 23:11:39.103406           Starting Create Static Device Nodes in /dev...

10928 23:11:39.127830  [  OK  ] Finished Create Static Device Nodes in /dev.

10929 23:11:39.139485  [  OK  ] Reached target Local File Systems (Pre).

10930 23:11:39.155343  [  OK  ] Reached target Local File Systems.

10931 23:11:39.195935           Starting Create Volatile Files and Directories...

10932 23:11:39.223094           Starting Rule-based Manage…for Device Events and Files...

10933 23:11:39.246272  [  OK  ] Started Rule-based Manager for Device Events and Files.

10934 23:11:39.270618  [  OK  ] Finished Create Volatile Files and Directories.

10935 23:11:39.333017           Starting Network Time Synchronization...

10936 23:11:39.358421           Starting Update UTMP about System Boot/Shutdown...

10937 23:11:39.392435  [  OK  ] Created slice system-systemd\x2dbacklight.slice.

10938 23:11:39.410022  <6>[   18.460547] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000

10939 23:11:39.430283  <6>[   18.480018] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:

10940 23:11:39.436626  <6>[   18.480132] mtk-pcie-gen3 11230000.pcie:      MEM 0x0012000000..0x00127fffff -> 0x0012000000

10941 23:11:39.446478  <6>[   18.480149] mtk-pcie-gen3 11230000.pcie:       IO 0x0012800000..0x0012ffffff -> 0x0012800000

10942 23:11:39.471113  <6>[   18.525158] remoteproc remoteproc0: scp is available

10943 23:11:39.477179  <6>[   18.525289] remoteproc remoteproc0: powering up scp

10944 23:11:39.483892  <6>[   18.525297] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164

10945 23:11:39.490707           Startin<6>[   18.525342] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0

10946 23:11:39.497483  g Load/Save Screen …of leds:white:kbd_backlight...

10947 23:11:39.513961  <3>[   18.564629] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10948 23:11:39.520677  <3>[   18.564650] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10949 23:11:39.534267  [  OK  ] Started Network Tim<3>[   18.564655] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10950 23:11:39.544004  e Synchronizatio<3>[   18.570607] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10951 23:11:39.550783  <3>[   18.570623] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10952 23:11:39.554190  n.

10953 23:11:39.560417  <3>[   18.570626] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10954 23:11:39.570340  <3>[   18.570631] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10955 23:11:39.577216  <3>[   18.570635] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10956 23:11:39.583995  <3>[   18.571526] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10957 23:11:39.593667  <4>[   18.573573] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator

10958 23:11:39.603467  [  OK  [<3>[   18.574579] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10959 23:11:39.610675  0m] Finished [0<3>[   18.574599] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10960 23:11:39.620231  ;1;39mUpdate UTM<3>[   18.574607] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10961 23:11:39.630528  P about System B<4>[   18.576126] elants_i2c 4-0010: supply vccio not found, using dummy regulator

10962 23:11:39.641017  oot/Shutdown<3>[   18.583545] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10963 23:11:39.641101  .

10964 23:11:39.647131  <3>[   18.583586] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10965 23:11:39.658051  <3>[   18.583593] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10966 23:11:39.665300  [  OK  [<3>[   18.583604] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10967 23:11:39.674811  0m] Finished [0<3>[   18.583612] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10968 23:11:39.685004  <3>[   18.605356] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10969 23:11:39.691222  ;1;39mLoad/Save <6>[   18.608851] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00

10970 23:11:39.697859  <6>[   18.608870] pci_bus 0000:00: root bus resource [bus 00-ff]

10971 23:11:39.704562  <6>[   18.608878] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]

10972 23:11:39.714855  <6>[   18.608884] pci_bus 0000:00: root bus resource [io  0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])

10973 23:11:39.721534  <6>[   18.608923] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400

10974 23:11:39.728651  <6>[   18.608964] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]

10975 23:11:39.735996  Screen …s of l<6>[   18.609064] pci 0000:00:00.0: supports D1 D2

10976 23:11:39.742170  eds:white:kbd_ba<6>[   18.609068] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10977 23:11:39.751919  <6>[   18.615470] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring

10978 23:11:39.755617  <6>[   18.633314] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000

10979 23:11:39.758763  cklight.

10980 23:11:39.765451  <6>[   18.633395] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]

10981 23:11:39.772177  <6>[   18.633421] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]

10982 23:11:39.782481  <6>[   18.633439] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]

10983 23:11:39.786051  [  OK  [<6>[   18.633625] pci 0000:01:00.0: supports D1 D2

10984 23:11:39.795996  0m] Found device<6>[   18.633628] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10985 23:11:39.802719  <6>[   18.651473] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01

10986 23:11:39.812599   /dev/t<6>[   18.651527] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]

10987 23:11:39.820267  <6>[   18.651534] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]

10988 23:11:39.820412  tyS0.

10989 23:11:39.829820  <6>[   18.651550] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]

10990 23:11:39.836426  <6>[   18.651566] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]

10991 23:11:39.842983  <6>[   18.651583] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]

10992 23:11:39.850682  <6>[   18.651599] pci 0000:00:00.0: PCI bridge to [bus 01]

10993 23:11:39.857623  <6>[   18.651607] pci 0000:00:00.0:   bridge window [mem 0x12000000-0x121fffff 64bit pref]

10994 23:11:39.863802  <6>[   18.652006] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered

10995 23:11:39.870980  <6>[   18.654103] pcieport 0000:00:00.0: enabling device (0000 -> 0002)

10996 23:11:39.880853  <6>[   18.661730] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e

10997 23:11:39.888281  <6>[   18.661740] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd

10998 23:11:39.895051  <6>[   18.661750] remoteproc remoteproc0: remote processor scp is now up

10999 23:11:39.901814  <4>[   18.680067] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.

11000 23:11:39.909327  <4>[   18.680067] Fallback method does not support PEC.

11001 23:11:39.919393  [  OK  ] Reached targ<3>[   18.695508] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11002 23:11:39.930047  et Syst<6>[   18.706184] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2

11003 23:11:39.933168  <6>[   18.709949] mc: Linux media interface: v0.10

11004 23:11:39.943340  em Initializatio<3>[   18.720233] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11005 23:11:39.946634  n.

11006 23:11:39.953950  <6>[   18.746380] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003

11007 23:11:39.963924  <6>[   18.747099] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3

11008 23:11:39.970321  <6>[   18.750485] usbcore: registered new interface driver r8152

11009 23:11:39.981229  [  OK  ] Started Daily Clean<6>[   18.772908] videodev: Linux video capture interface: v2.00

11010 23:11:39.988044  up of Temporary <6>[   18.779769] pcieport 0000:00:00.0: PME: Signaling with IRQ 282

11011 23:11:39.998497  Directories.<3>[   18.783535] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11012 23:11:39.998579  

11013 23:11:40.004813  <6>[   18.792869] pcieport 0000:00:00.0: AER: enabled with IRQ 282

11014 23:11:40.007940  <6>[   18.793207] usbcore: registered new interface driver cdc_ether

11015 23:11:40.015267  <6>[   18.834544] usbcore: registered new interface driver r8153_ecm

11016 23:11:40.025802  <3>[   18.845204] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11017 23:11:40.032925  <6>[   18.853446] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk

11018 23:11:40.038967  <6>[   18.869868] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)

11019 23:11:40.049258  <4>[   18.873334] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2

11020 23:11:40.052613  <6>[   18.873363] Bluetooth: Core ver 2.22

11021 23:11:40.059187  <4>[   18.873408] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)

11022 23:11:40.065624  <6>[   18.874897] NET: Registered PF_BLUETOOTH protocol family

11023 23:11:40.072418  <6>[   18.874908] Bluetooth: HCI device and connection manager initialized

11024 23:11:40.075702  <6>[   18.874932] Bluetooth: HCI socket layer initialized

11025 23:11:40.082339  <6>[   18.874937] Bluetooth: L2CAP socket layer initialized

11026 23:11:40.085702  <6>[   18.874956] Bluetooth: SCO socket layer initialized

11027 23:11:40.095840  <3>[   18.880254] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11028 23:11:40.108909  <6>[   18.880670] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4

11029 23:11:40.115697  [  OK  [<6>[   18.883356] usbcore: registered new interface driver uvcvideo

11030 23:11:40.125249  <5>[   18.914281] cfg80211: Loading compiled-in X.509 certificates for regulatory database

11031 23:11:40.132269  <3>[   18.917076] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11032 23:11:40.142015  <6>[   18.917496] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected

11033 23:11:40.148750  <6>[   18.927833] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered

11034 23:11:40.155485  <5>[   18.937183] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'

11035 23:11:40.165024  <4>[   18.937243] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2

11036 23:11:40.168653  <6>[   18.937249] cfg80211: failed to load regulatory.db

11037 23:11:40.175558  <6>[   18.937711] r8152 2-1.3:1.0 eth0: v1.12.13

11038 23:11:40.181948  <6>[   18.948605] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0

11039 23:11:40.188561  <3>[   18.953160] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11040 23:11:40.195527  <6>[   18.953901] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0

11041 23:11:40.205521  <3>[   18.953988] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6

11042 23:11:40.208474  <6>[   18.969896] usbcore: registered new interface driver btusb

11043 23:11:40.218492  <3>[   18.970431] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11044 23:11:40.228241  <4>[   18.971094] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2

11045 23:11:40.235334  <3>[   18.971122] Bluetooth: hci0: Failed to load firmware file (-2)

11046 23:11:40.241593  <3>[   18.971132] Bluetooth: hci0: Failed to set up firmware (-2)

11047 23:11:40.251383  <4>[   18.971139] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.

11048 23:11:40.261872  <3>[   18.997047] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

11049 23:11:40.268565  <6>[   19.251560] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000

11050 23:11:40.275071  <6>[   19.251663] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)

11051 23:11:40.278077  <6>[   19.269763] mt7921e 0000:01:00.0: ASIC revision: 79610010

11052 23:11:40.284828  0m] Reached target System Time Set.

11053 23:11:40.301144  [  OK  ] Reached target System Time Synchronized.

11054 23:11:40.320170  [  OK  ] Started Discard unused blocks once <6>[   19.366218] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a

11055 23:11:40.320281  <6>[   19.366218] 

11056 23:11:40.323729  a week.

11057 23:11:40.335345  [  OK  ] Reached target Timers.

11058 23:11:40.354821  [  OK  ] Listening on D-Bus System Message Bus Socket.

11059 23:11:40.371021  [  OK  ] Reached target Sockets.

11060 23:11:40.386705  [  OK  ] Reached target Basic System.

11061 23:11:40.407053  [  OK  ] Listening on Load/Save RF …itch Status /dev/rfkill Watch.

11062 23:11:40.444904  [  OK  ] Started D-Bus System Message Bus.

11063 23:11:40.471994           Starting User Login Management...

11064 23:11:40.489944           Starting Permit User Sessions...

11065 23:11:40.513814  [  OK  ] Finished Permit User Sessions.

11066 23:11:40.552674  [  OK  ] Reached target Bluetooth.

11067 23:11:40.578404  <6>[   19.626607] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959

11068 23:11:40.599889  [  OK  ] Started Getty on tty1.

11069 23:11:40.619854  [  OK  ] Started Serial Getty on ttyS0.

11070 23:11:40.635462  [  OK  ] Reached target Login Prompts.

11071 23:11:40.655081           Starting Load/Save RF Kill Switch Status...

11072 23:11:40.672785  [  OK  ] Started User Login Management.

11073 23:11:40.687938  [  OK  ] Started Load/Save RF Kill Switch Status.

11074 23:11:40.704686  [  OK  ] Reached target Multi-User System.

11075 23:11:40.719691  [  OK  ] Reached target Graphical Interface.

11076 23:11:40.780126           Starting Update UTMP about System Runlevel Changes...

11077 23:11:40.814347  [  OK  ] Finished Update UTMP about System Runlevel Changes.

11078 23:11:40.851645  

11079 23:11:40.851731  

11080 23:11:40.854559  Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0

11081 23:11:40.854641  

11082 23:11:40.858257  debian-bullseye-arm64 login: root (automatic login)

11083 23:11:40.858376  

11084 23:11:40.858469  

11085 23:11:40.875476  Linux debian-bullseye-arm64 6.1.67-cip12-rt7 #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023 aarch64

11086 23:11:40.875559  

11087 23:11:40.882044  The programs included with the Debian GNU/Linux system are free software;

11088 23:11:40.888210  the exact distribution terms for each program are described in the

11089 23:11:40.891934  individual files in /usr/share/doc/*/copyright.

11090 23:11:40.892040  

11091 23:11:40.898182  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent

11092 23:11:40.901828  permitted by applicable law.

11093 23:11:40.902194  Matched prompt #10: / #
11095 23:11:40.902451  Setting prompt string to ['/ #']
11096 23:11:40.902545  end: 2.2.5.1 login-action (duration 00:00:21) [common]
11098 23:11:40.902737  end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11099 23:11:40.902823  start: 2.2.6 expect-shell-connection (timeout 00:02:55) [common]
11100 23:11:40.902891  Setting prompt string to ['/ #']
11101 23:11:40.902950  Forcing a shell prompt, looking for ['/ #']
11103 23:11:40.953157  / # 

11104 23:11:40.953262  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11105 23:11:40.953337  Waiting using forced prompt support (timeout 00:02:30)
11106 23:11:40.957865  

11107 23:11:40.958134  end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11108 23:11:40.958227  start: 2.2.7 export-device-env (timeout 00:02:55) [common]
11109 23:11:40.958332  end: 2.2.7 export-device-env (duration 00:00:00) [common]
11110 23:11:40.958461  end: 2.2 depthcharge-retry (duration 00:02:05) [common]
11111 23:11:40.958546  end: 2 depthcharge-action (duration 00:02:05) [common]
11112 23:11:40.958630  start: 3 lava-test-retry (timeout 00:05:00) [common]
11113 23:11:40.958717  start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11114 23:11:40.958787  Using namespace: common
11116 23:11:41.059111  / # #

11117 23:11:41.059220  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11118 23:11:41.064593  #

11119 23:11:41.064860  Using /lava-12395368
11121 23:11:41.165153  / # export SHELL=/bin/sh

11122 23:11:41.170587  export SHELL=/bin/sh

11124 23:11:41.271132  / # . /lava-12395368/environment

11125 23:11:41.276075  . /lava-12395368/environment

11127 23:11:41.376607  / # /lava-12395368/bin/lava-test-runner /lava-12395368/0

11128 23:11:41.376715  Test shell timeout: 10s (minimum of the action and connection timeout)
11129 23:11:41.381597  /lava-12395368/bin/lava-test-runner /lava-12395368/0

11130 23:11:41.402667  + export TESTRUN_ID=0_sleep

11131 23:11:41.405641  + cd /lava-12395368/0/tests/0_sleep

11132 23:11:41.409181  + cat uuid

11133 23:11:41.409264  + UUID=12395368_1.5.2.3.1

11134 23:11:41.415629  + set +<6>[   20.468469] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0

11135 23:11:41.415713  x

11136 23:11:41.422250  <LAVA_SIGNAL_STARTRUN 0_sleep 12395368_1.5.2.3.1>

11137 23:11:41.422507  Received signal: <STARTRUN> 0_sleep 12395368_1.5.2.3.1
11138 23:11:41.422580  Starting test lava.0_sleep (12395368_1.5.2.3.1)
11139 23:11:41.422665  Skipping test definition patterns.
11140 23:11:41.425527  + ./config/lava/sleep/sleep.sh mem

11141 23:11:41.428920  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>

11142 23:11:41.429176  Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11144 23:11:41.435515  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>

11145 23:11:41.435766  Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11147 23:11:41.438579  rtcwake: assuming RTC uses UTC ...

11148 23:11:41.445285  rtcwake: wakeup from "mem" using rtc0 at Wed Dec 27 23:09:16 2023

11149 23:11:41.458628  <6>[   20.508122] PM: suspend entry (deep)

11150 23:11:41.461846  <6>[   20.508203] Filesystems sync: 0.000 seconds

11151 23:11:41.464914  <6>[   20.512841] Freezing user space processes

11152 23:11:41.475110  <6>[   20.515134] Freezing user space processes completed (elapsed 0.002 seconds)

11153 23:11:41.478520  <6>[   20.515149] OOM killer disabled.

11154 23:11:41.481968  <6>[   20.515152] Freezing remaining freezable tasks

11155 23:11:41.488256  <6>[   20.516575] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11156 23:11:41.498265  <6>[   20.516585] printk: Suspending console(s) (use no_console_suspend to debug)

11157 23:11:47.269050  <6>[   20.741317] Disabling non-boot CPUs ...

11158 23:11:47.272239  <4>[   20.742213] IRQ282: set affinity failed(-22).

11159 23:11:47.275815  <4>[   20.742228] IRQ284: set affinity failed(-22).

11160 23:11:47.282707  <6>[   20.742295] psci: CPU1 killed (polled 0 ms)

11161 23:11:47.286239  <4>[   20.743764] IRQ282: set affinity failed(-22).

11162 23:11:47.292833  <4>[   20.743773] IRQ284: set affinity failed(-22).

11163 23:11:47.295895  <6>[   20.744839] psci: CPU2 killed (polled 0 ms)

11164 23:11:47.299389  <4>[   20.746004] IRQ282: set affinity failed(-22).

11165 23:11:47.305764  <4>[   20.746013] IRQ284: set affinity failed(-22).

11166 23:11:47.309024  <6>[   20.747074] psci: CPU3 killed (polled 0 ms)

11167 23:11:47.312576  <4>[   20.747842] IRQ282: set affinity failed(-22).

11168 23:11:47.319319  <4>[   20.747848] IRQ284: set affinity failed(-22).

11169 23:11:47.322288  <6>[   20.747881] psci: CPU4 killed (polled 0 ms)

11170 23:11:47.329047  <4>[   20.748814] IRQ282: set affinity failed(-22).

11171 23:11:47.332454  <4>[   20.748821] IRQ284: set affinity failed(-22).

11172 23:11:47.335988  <6>[   20.748859] psci: CPU5 killed (polled 0 ms)

11173 23:11:47.342558  <6>[   20.749807] psci: CPU6 killed (polled 0 ms)

11174 23:11:47.345572  <6>[   20.751736] psci: CPU7 killed (polled 0 ms)

11175 23:11:47.349275  <6>[   20.752209] Enabling non-boot CPUs ...

11176 23:11:47.352265  <6>[   20.752437] Detected VIPT I-cache on CPU1

11177 23:11:47.362088  <6>[   20.752521] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

11178 23:11:47.369100  <6>[   20.752583] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

11179 23:11:47.369183  <6>[   20.753115] CPU1 is up

11180 23:11:47.375477  <6>[   20.753250] Detected VIPT I-cache on CPU2

11181 23:11:47.382593  <6>[   20.753302] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

11182 23:11:47.389269  <6>[   20.753339] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

11183 23:11:47.392251  <6>[   20.753801] CPU2 is up

11184 23:11:47.395784  <6>[   20.753936] Detected VIPT I-cache on CPU3

11185 23:11:47.402354  <6>[   20.753988] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

11186 23:11:47.409117  <6>[   20.754025] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

11187 23:11:47.412229  <6>[   20.754464] CPU3 is up

11188 23:11:47.419002  <6>[   20.754583] CPU features: detected: Hardware dirty bit management

11189 23:11:47.421990  <6>[   20.754606] Detected PIPT I-cache on CPU4

11190 23:11:47.428870  <6>[   20.754637] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

11191 23:11:47.435284  <6>[   20.754660] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

11192 23:11:47.438734  <6>[   20.755026] CPU4 is up

11193 23:11:47.445626  <6>[   20.755170] Detected PIPT I-cache on CPU5

11194 23:11:47.451916  <6>[   20.755205] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

11195 23:11:47.458665  <6>[   20.755227] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

11196 23:11:47.462315  <6>[   20.755554] CPU5 is up

11197 23:11:47.465441  <6>[   20.755689] Detected PIPT I-cache on CPU6

11198 23:11:47.471878  <6>[   20.755725] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

11199 23:11:47.478938  <6>[   20.755747] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

11200 23:11:47.482030  <6>[   20.756085] CPU6 is up

11201 23:11:47.485595  <6>[   20.756224] Detected PIPT I-cache on CPU7

11202 23:11:47.496590  <6>[   20.756259] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

11203 23:11:47.502955  <6>[   20.756282] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

11204 23:11:47.503038  <6>[   20.756634] CPU7 is up

11205 23:11:47.512970  <4>[   20.895205] typec port0-partner: PM: parent port0 should not be sleeping

11206 23:11:47.600862  <6>[   21.437825] OOM killer enabled.

11207 23:11:47.604551  <6>[   21.437834] Restarting tasks ... done.

11208 23:11:47.610914  <LAVA_SIGNAL_TES<5>[   21.439699] random: crng reseeded on system resumption

11209 23:11:47.611177  Received signal: <TES<5>[>   21.439699] random: crng reseeded on system resumption
<6
11210 23:11:47.614108  <6>[   21.442081] PM: suspend exit

11211 23:11:47.617671  TCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=pass>

11212 23:11:47.620848  rtcwake: assuming RTC uses UTC ...

11213 23:11:47.627588  rtcwake: wakeup from "mem" using rtc0 at Wed Dec 27 23:09:22 2023

11214 23:11:47.641121  <6>[   21.480073] PM: suspend entry (deep)

11215 23:11:47.644307  <6>[   21.480102] Filesystems sync: 0.000 seconds

11216 23:11:47.647637  <6>[   21.480399] Freezing user space processes

11217 23:11:47.657774  <6>[   21.481601] Freezing user space processes completed (elapsed 0.001 seconds)

11218 23:11:47.660902  <6>[   21.481605] OOM killer disabled.

11219 23:11:47.663958  <6>[   21.481607] Freezing remaining freezable tasks

11220 23:11:47.670714  <6>[   21.482768] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11221 23:11:47.677469  <6>[   21.482771] printk: Suspending console(s) (use no_console_suspend to debug)

11222 23:11:53.270410  <6>[   21.667563] Disabling non-boot CPUs ...

11223 23:11:53.273308  <6>[   21.669531] psci: CPU1 killed (polled 4 ms)

11224 23:11:53.276746  <6>[   21.670696] psci: CPU2 killed (polled 0 ms)

11225 23:11:53.283443  <6>[   21.671682] psci: CPU3 killed (polled 0 ms)

11226 23:11:53.286990  <6>[   21.672193] psci: CPU4 killed (polled 0 ms)

11227 23:11:53.290209  <6>[   21.672703] psci: CPU5 killed (polled 0 ms)

11228 23:11:53.296672  <6>[   21.673275] psci: CPU6 killed (polled 0 ms)

11229 23:11:53.299903  <6>[   21.673927] psci: CPU7 killed (polled 0 ms)

11230 23:11:53.303355  <6>[   21.674324] Enabling non-boot CPUs ...

11231 23:11:53.309943  <6>[   21.674552] Detected VIPT I-cache on CPU1

11232 23:11:53.316774  <6>[   21.674635] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

11233 23:11:53.323347  <6>[   21.674694] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

11234 23:11:53.326400  <6>[   21.675327] CPU1 is up

11235 23:11:53.330125  <6>[   21.675464] Detected VIPT I-cache on CPU2

11236 23:11:53.337052  <6>[   21.675518] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

11237 23:11:53.343244  <6>[   21.675554] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

11238 23:11:53.346946  <6>[   21.676060] CPU2 is up

11239 23:11:53.350034  <6>[   21.676191] Detected VIPT I-cache on CPU3

11240 23:11:53.357246  <6>[   21.676244] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

11241 23:11:53.363521  <6>[   21.676280] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

11242 23:11:53.366851  <6>[   21.676807] CPU3 is up

11243 23:11:53.370095  <6>[   21.676926] Detected PIPT I-cache on CPU4

11244 23:11:53.380125  <6>[   21.676946] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

11245 23:11:53.386396  <6>[   21.676958] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

11246 23:11:53.390824  <6>[   21.677205] CPU4 is up

11247 23:11:53.397521  <6>[   21.677323] Detected PIPT I-cache on CPU5

11248 23:11:53.404218  <6>[   21.677343] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

11249 23:11:53.410477  <6>[   21.677355] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

11250 23:11:53.414205  <6>[   21.677605] CPU5 is up

11251 23:11:53.417341  <6>[   21.677725] Detected PIPT I-cache on CPU6

11252 23:11:53.424232  <6>[   21.677745] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

11253 23:11:53.430448  <6>[   21.677757] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

11254 23:11:53.433962  <6>[   21.677986] CPU6 is up

11255 23:11:53.437242  <6>[   21.678102] Detected PIPT I-cache on CPU7

11256 23:11:53.444135  <6>[   21.678122] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

11257 23:11:53.450966  <6>[   21.678134] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

11258 23:11:53.453980  <6>[   21.678369] CPU7 is up

11259 23:11:53.501791  <6>[   22.261786] OOM killer enabled.

11260 23:11:53.505222  <6>[   22.261796] Restarting tasks ... done.

11261 23:11:53.512105  <5>[   22.265420] random: crng reseeded on system resumption

11262 23:11:53.512193  <6>[   22.269025] PM: suspend exit

11263 23:11:53.518801  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=pass>

11264 23:11:53.519068  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=pass
11266 23:11:53.521899  rtcwake: assuming RTC uses UTC ...

11267 23:11:53.528744  rtcwake: wakeup from "mem" using rtc0 at Wed Dec 27 23:09:28 2023

11268 23:11:53.542035  <6>[   22.303273] PM: suspend entry (deep)

11269 23:11:53.545514  <6>[   22.303304] Filesystems sync: 0.000 seconds

11270 23:11:53.548792  <6>[   22.303680] Freezing user space processes

11271 23:11:53.555128  <6>[   22.305049] Freezing user space processes completed (elapsed 0.001 seconds)

11272 23:11:53.558589  <6>[   22.305054] OOM killer disabled.

11273 23:11:53.565247  <6>[   22.305056] Freezing remaining freezable tasks

11274 23:11:53.572242  <6>[   22.306227] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11275 23:11:53.578512  <6>[   22.306232] printk: Suspending console(s) (use no_console_suspend to debug)

11276 23:11:59.271453  <6>[   22.483717] Disabling non-boot CPUs ...

11277 23:11:59.274686  <6>[   22.484721] psci: CPU1 killed (polled 0 ms)

11278 23:11:59.278453  <6>[   22.485916] psci: CPU2 killed (polled 0 ms)

11279 23:11:59.285320  <6>[   22.486855] psci: CPU3 killed (polled 0 ms)

11280 23:11:59.288317  <6>[   22.487483] psci: CPU4 killed (polled 0 ms)

11281 23:11:59.291862  <6>[   22.489050] psci: CPU5 killed (polled 0 ms)

11282 23:11:59.298559  <6>[   22.490769] psci: CPU6 killed (polled 0 ms)

11283 23:11:59.301469  <6>[   22.491411] psci: CPU7 killed (polled 0 ms)

11284 23:11:59.304981  <6>[   22.491855] Enabling non-boot CPUs ...

11285 23:11:59.311787  <6>[   22.492090] Detected VIPT I-cache on CPU1

11286 23:11:59.318574  <6>[   22.492177] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

11287 23:11:59.325196  <6>[   22.492241] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

11288 23:11:59.328282  <6>[   22.492895] CPU1 is up

11289 23:11:59.331808  <6>[   22.493038] Detected VIPT I-cache on CPU2

11290 23:11:59.338599  <6>[   22.493096] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

11291 23:11:59.345114  <6>[   22.493135] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

11292 23:11:59.348340  <6>[   22.493690] CPU2 is up

11293 23:11:59.351478  <6>[   22.493834] Detected VIPT I-cache on CPU3

11294 23:11:59.358277  <6>[   22.493892] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

11295 23:11:59.365036  <6>[   22.493930] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

11296 23:11:59.368170  <6>[   22.494465] CPU3 is up

11297 23:11:59.371887  <6>[   22.494597] Detected PIPT I-cache on CPU4

11298 23:11:59.381837  <6>[   22.494624] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

11299 23:11:59.388568  <6>[   22.494643] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

11300 23:11:59.391639  <6>[   22.494959] CPU4 is up

11301 23:11:59.395405  <6>[   22.495099] Detected PIPT I-cache on CPU5

11302 23:11:59.405279  <6>[   22.495127] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

11303 23:11:59.411662  <6>[   22.495145] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

11304 23:11:59.411746  <6>[   22.495434] CPU5 is up

11305 23:11:59.418472  <6>[   22.495563] Detected PIPT I-cache on CPU6

11306 23:11:59.424962  <6>[   22.495591] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

11307 23:11:59.431507  <6>[   22.495608] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

11308 23:11:59.434801  <6>[   22.495903] CPU6 is up

11309 23:11:59.438043  <6>[   22.496037] Detected PIPT I-cache on CPU7

11310 23:11:59.444943  <6>[   22.496065] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

11311 23:11:59.451659  <6>[   22.496083] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

11312 23:11:59.454645  <6>[   22.496407] CPU7 is up

11313 23:11:59.495839  <6>[   23.073731] OOM killer enabled.

11314 23:11:59.498963  <6>[   23.073740] Restarting tasks ... done.

11315 23:11:59.502036  <5>[   23.075304] random: crng reseeded on system resumption

11316 23:11:59.505679  <6>[   23.076640] PM: suspend exit

11317 23:11:59.512459  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=pass>

11318 23:11:59.512774  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=pass
11320 23:11:59.515518  rtcwake: assuming RTC uses UTC ...

11321 23:11:59.522228  rtcwake: wakeup from "mem" using rtc0 at Wed Dec 27 23:09:34 2023

11322 23:11:59.535585  <6>[   23.114501] PM: suspend entry (deep)

11323 23:11:59.538962  <6>[   23.114531] Filesystems sync: 0.000 seconds

11324 23:11:59.542514  <6>[   23.114841] Freezing user space processes

11325 23:11:59.549151  <6>[   23.116258] Freezing user space processes completed (elapsed 0.001 seconds)

11326 23:11:59.552218  <6>[   23.116266] OOM killer disabled.

11327 23:11:59.558733  <6>[   23.116268] Freezing remaining freezable tasks

11328 23:11:59.565476  <6>[   23.117565] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11329 23:11:59.572373  <6>[   23.117572] printk: Suspending console(s) (use no_console_suspend to debug)

11330 23:12:05.269517  <6>[   23.295400] Disabling non-boot CPUs ...

11331 23:12:05.273272  <6>[   23.296372] psci: CPU1 killed (polled 0 ms)

11332 23:12:05.276044  <6>[   23.297458] psci: CPU2 killed (polled 4 ms)

11333 23:12:05.282801  <6>[   23.298372] psci: CPU3 killed (polled 0 ms)

11334 23:12:05.285884  <6>[   23.298984] psci: CPU4 killed (polled 0 ms)

11335 23:12:05.289604  <6>[   23.299557] psci: CPU5 killed (polled 0 ms)

11336 23:12:05.296167  <6>[   23.300219] psci: CPU6 killed (polled 0 ms)

11337 23:12:05.299392  <6>[   23.300843] psci: CPU7 killed (polled 0 ms)

11338 23:12:05.302910  <6>[   23.301190] Enabling non-boot CPUs ...

11339 23:12:05.309555  <6>[   23.301419] Detected VIPT I-cache on CPU1

11340 23:12:05.316081  <6>[   23.301502] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

11341 23:12:05.322657  <6>[   23.301562] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

11342 23:12:05.326074  <6>[   23.302196] CPU1 is up

11343 23:12:05.329261  <6>[   23.302340] Detected VIPT I-cache on CPU2

11344 23:12:05.336062  <6>[   23.302395] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

11345 23:12:05.342931  <6>[   23.302433] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

11346 23:12:05.346116  <6>[   23.302947] CPU2 is up

11347 23:12:05.349142  <6>[   23.303085] Detected VIPT I-cache on CPU3

11348 23:12:05.355801  <6>[   23.303140] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

11349 23:12:05.362542  <6>[   23.303177] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

11350 23:12:05.366222  <6>[   23.303701] CPU3 is up

11351 23:12:05.369370  <6>[   23.303827] Detected PIPT I-cache on CPU4

11352 23:12:05.380674  <6>[   23.303851] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

11353 23:12:05.387548  <6>[   23.303866] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

11354 23:12:05.387672  <6>[   23.304141] CPU4 is up

11355 23:12:05.394454  <6>[   23.304265] Detected PIPT I-cache on CPU5

11356 23:12:05.401308  <6>[   23.304290] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

11357 23:12:05.408060  <6>[   23.304305] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

11358 23:12:05.411060  <6>[   23.304560] CPU5 is up

11359 23:12:05.414355  <6>[   23.304683] Detected PIPT I-cache on CPU6

11360 23:12:05.420858  <6>[   23.304706] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

11361 23:12:05.427364  <6>[   23.304721] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

11362 23:12:05.430757  <6>[   23.304978] CPU6 is up

11363 23:12:05.434311  <6>[   23.305107] Detected PIPT I-cache on CPU7

11364 23:12:05.441090  <6>[   23.305132] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

11365 23:12:05.450694  <6>[   23.305147] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

11366 23:12:05.450820  <6>[   23.305442] CPU7 is up

11367 23:12:05.485219  <6>[   23.873693] OOM killer enabled.

11368 23:12:05.488922  <6>[   23.873702] Restarting tasks ... done.

11369 23:12:05.495068  <5>[   23.877751] random: crng reseeded on system resumption

11370 23:12:05.495198  <6>[   23.880913] PM: suspend exit

11371 23:12:05.501620  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=pass>

11372 23:12:05.501939  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=pass
11374 23:12:05.505224  rtcwake: assuming RTC uses UTC ...

11375 23:12:05.512007  rtcwake: wakeup from "mem" using rtc0 at Wed Dec 27 23:09:40 2023

11376 23:12:05.525561  <6>[   23.915196] PM: suspend entry (deep)

11377 23:12:05.528578  <6>[   23.915229] Filesystems sync: 0.000 seconds

11378 23:12:05.532155  <6>[   23.915551] Freezing user space processes

11379 23:12:05.538893  <6>[   23.917041] Freezing user space processes completed (elapsed 0.001 seconds)

11380 23:12:05.541751  <6>[   23.917049] OOM killer disabled.

11381 23:12:05.548526  <6>[   23.917051] Freezing remaining freezable tasks

11382 23:12:05.555411  <6>[   23.918249] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11383 23:12:05.562173  <6>[   23.918254] printk: Suspending console(s) (use no_console_suspend to debug)

11384 23:12:11.272601  <6>[   24.095745] Disabling non-boot CPUs ...

11385 23:12:11.275614  <6>[   24.096707] psci: CPU1 killed (polled 0 ms)

11386 23:12:11.278677  <6>[   24.097881] psci: CPU2 killed (polled 0 ms)

11387 23:12:11.285505  <6>[   24.098800] psci: CPU3 killed (polled 0 ms)

11388 23:12:11.289064  <6>[   24.099300] psci: CPU4 killed (polled 0 ms)

11389 23:12:11.291978  <6>[   24.099807] psci: CPU5 killed (polled 0 ms)

11390 23:12:11.298766  <6>[   24.100476] psci: CPU6 killed (polled 0 ms)

11391 23:12:11.301946  <6>[   24.101135] psci: CPU7 killed (polled 0 ms)

11392 23:12:11.305746  <6>[   24.101582] Enabling non-boot CPUs ...

11393 23:12:11.311951  <6>[   24.101811] Detected VIPT I-cache on CPU1

11394 23:12:11.318581  <6>[   24.101898] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

11395 23:12:11.325086  <6>[   24.101958] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

11396 23:12:11.328717  <6>[   24.102609] CPU1 is up

11397 23:12:11.331787  <6>[   24.102748] Detected VIPT I-cache on CPU2

11398 23:12:11.338874  <6>[   24.102804] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

11399 23:12:11.345661  <6>[   24.102841] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

11400 23:12:11.348564  <6>[   24.103350] CPU2 is up

11401 23:12:11.351921  <6>[   24.103487] Detected VIPT I-cache on CPU3

11402 23:12:11.358778  <6>[   24.103542] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

11403 23:12:11.365491  <6>[   24.103579] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

11404 23:12:11.368797  <6>[   24.104101] CPU3 is up

11405 23:12:11.372250  <6>[   24.104226] Detected PIPT I-cache on CPU4

11406 23:12:11.381935  <6>[   24.104249] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

11407 23:12:11.388753  <6>[   24.104265] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

11408 23:12:11.391970  <6>[   24.104543] CPU4 is up

11409 23:12:11.395505  <6>[   24.104666] Detected PIPT I-cache on CPU5

11410 23:12:11.405808  <6>[   24.104691] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

11411 23:12:11.411992  <6>[   24.104706] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

11412 23:12:11.412113  <6>[   24.104960] CPU5 is up

11413 23:12:11.418922  <6>[   24.105083] Detected PIPT I-cache on CPU6

11414 23:12:11.425461  <6>[   24.105107] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

11415 23:12:11.431940  <6>[   24.105122] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

11416 23:12:11.435185  <6>[   24.105416] CPU6 is up

11417 23:12:11.438878  <6>[   24.105548] Detected PIPT I-cache on CPU7

11418 23:12:11.445653  <6>[   24.105572] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

11419 23:12:11.451649  <6>[   24.105587] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

11420 23:12:11.455243  <6>[   24.105862] CPU7 is up

11421 23:12:11.496231  <6>[   24.685606] OOM killer enabled.

11422 23:12:11.499596  <6>[   24.685615] Restarting tasks ... done.

11423 23:12:11.502526  <5>[   24.687895] random: crng reseeded on system resumption

11424 23:12:11.506155  <6>[   24.688596] PM: suspend exit

11425 23:12:11.512735  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=pass>

11426 23:12:11.513096  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=pass
11428 23:12:11.516086  rtcwake: assuming RTC uses UTC ...

11429 23:12:11.522513  rtcwake: wakeup from "mem" using rtc0 at Wed Dec 27 23:09:46 2023

11430 23:12:11.536317  <6>[   24.727254] PM: suspend entry (deep)

11431 23:12:11.539388  <6>[   24.727288] Filesystems sync: 0.000 seconds

11432 23:12:11.542472  <6>[   24.727622] Freezing user space processes

11433 23:12:11.549060  <6>[   24.729159] Freezing user space processes completed (elapsed 0.001 seconds)

11434 23:12:11.552594  <6>[   24.729168] OOM killer disabled.

11435 23:12:11.559215  <6>[   24.729170] Freezing remaining freezable tasks

11436 23:12:11.566205  <6>[   24.730420] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11437 23:12:11.572962  <6>[   24.730428] printk: Suspending console(s) (use no_console_suspend to debug)

11438 23:12:17.267330  <6>[   24.911439] Disabling non-boot CPUs ...

11439 23:12:17.270756  <6>[   24.912443] psci: CPU1 killed (polled 0 ms)

11440 23:12:17.273959  <6>[   24.913575] psci: CPU2 killed (polled 0 ms)

11441 23:12:17.280896  <6>[   24.914555] psci: CPU3 killed (polled 0 ms)

11442 23:12:17.284394  <6>[   24.915129] psci: CPU4 killed (polled 0 ms)

11443 23:12:17.287528  <6>[   24.915821] psci: CPU5 killed (polled 0 ms)

11444 23:12:17.294421  <6>[   24.916497] psci: CPU6 killed (polled 0 ms)

11445 23:12:17.297521  <6>[   24.917074] psci: CPU7 killed (polled 0 ms)

11446 23:12:17.300947  <6>[   24.917476] Enabling non-boot CPUs ...

11447 23:12:17.304360  <6>[   24.917709] Detected VIPT I-cache on CPU1

11448 23:12:17.314250  <6>[   24.917796] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

11449 23:12:17.321117  <6>[   24.917856] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

11450 23:12:17.321251  <6>[   24.918508] CPU1 is up

11451 23:12:17.327288  <6>[   24.918651] Detected VIPT I-cache on CPU2

11452 23:12:17.334010  <6>[   24.918706] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

11453 23:12:17.340904  <6>[   24.918744] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

11454 23:12:17.344129  <6>[   24.919266] CPU2 is up

11455 23:12:17.347260  <6>[   24.919406] Detected VIPT I-cache on CPU3

11456 23:12:17.354160  <6>[   24.919462] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

11457 23:12:17.360839  <6>[   24.919500] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

11458 23:12:17.363783  <6>[   24.920025] CPU3 is up

11459 23:12:17.367320  <6>[   24.920155] Detected PIPT I-cache on CPU4

11460 23:12:17.377606  <6>[   24.920181] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

11461 23:12:17.384078  <6>[   24.920198] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

11462 23:12:17.384178  <6>[   24.920500] CPU4 is up

11463 23:12:17.391331  <6>[   24.920627] Detected PIPT I-cache on CPU5

11464 23:12:17.398151  <6>[   24.920654] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

11465 23:12:17.404623  <6>[   24.920671] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

11466 23:12:17.407922  <6>[   24.920943] CPU5 is up

11467 23:12:17.411643  <6>[   24.921069] Detected PIPT I-cache on CPU6

11468 23:12:17.418150  <6>[   24.921096] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

11469 23:12:17.424772  <6>[   24.921113] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

11470 23:12:17.427780  <6>[   24.921476] CPU6 is up

11471 23:12:17.431526  <6>[   24.921613] Detected PIPT I-cache on CPU7

11472 23:12:17.441399  <6>[   24.921640] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

11473 23:12:17.447588  <6>[   24.921656] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

11474 23:12:17.447727  <6>[   24.921961] CPU7 is up

11475 23:12:17.499290  <6>[   25.505619] OOM killer enabled.

11476 23:12:17.502522  <6>[   25.505628] Restarting tasks ... done.

11477 23:12:17.506055  <5>[   25.507280] random: crng reseeded on system resumption

11478 23:12:17.509429  <6>[   25.508605] PM: suspend exit

11479 23:12:17.515851  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=pass>

11480 23:12:17.516141  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=pass
11482 23:12:17.519355  rtcwake: assuming RTC uses UTC ...

11483 23:12:17.525868  rtcwake: wakeup from "mem" using rtc0 at Wed Dec 27 23:09:52 2023

11484 23:12:17.539214  <6>[   25.547283] PM: suspend entry (deep)

11485 23:12:17.542894  <6>[   25.547311] Filesystems sync: 0.000 seconds

11486 23:12:17.545972  <6>[   25.547605] Freezing user space processes

11487 23:12:17.552793  <6>[   25.549049] Freezing user space processes completed (elapsed 0.001 seconds)

11488 23:12:17.555893  <6>[   25.549056] OOM killer disabled.

11489 23:12:17.562725  <6>[   25.549057] Freezing remaining freezable tasks

11490 23:12:17.569504  <6>[   25.550167] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11491 23:12:17.576250  <6>[   25.550170] printk: Suspending console(s) (use no_console_suspend to debug)

11492 23:12:23.270342  <6>[   25.743568] Disabling non-boot CPUs ...

11493 23:12:23.273802  <6>[   25.744513] psci: CPU1 killed (polled 0 ms)

11494 23:12:23.280653  <4>[   25.745648] migrate_one_irq: 76 callbacks suppressed

11495 23:12:23.283775  <4>[   25.745659] IRQ282: set affinity failed(-22).

11496 23:12:23.287553  <4>[   25.745667] IRQ284: set affinity failed(-22).

11497 23:12:23.293852  <6>[   25.745723] psci: CPU2 killed (polled 0 ms)

11498 23:12:23.297558  <4>[   25.746615] IRQ282: set affinity failed(-22).

11499 23:12:23.300520  <4>[   25.746626] IRQ284: set affinity failed(-22).

11500 23:12:23.307338  <6>[   25.746681] psci: CPU3 killed (polled 0 ms)

11501 23:12:23.311150  <4>[   25.747222] IRQ282: set affinity failed(-22).

11502 23:12:23.314153  <4>[   25.747226] IRQ284: set affinity failed(-22).

11503 23:12:23.320941  <6>[   25.747258] psci: CPU4 killed (polled 0 ms)

11504 23:12:23.324234  <4>[   25.747757] IRQ282: set affinity failed(-22).

11505 23:12:23.331035  <4>[   25.747763] IRQ284: set affinity failed(-22).

11506 23:12:23.334727  <6>[   25.747805] psci: CPU5 killed (polled 0 ms)

11507 23:12:23.337711  <4>[   25.748433] IRQ282: set affinity failed(-22).

11508 23:12:23.344077  <4>[   25.748439] IRQ284: set affinity failed(-22).

11509 23:12:23.347654  <6>[   25.748480] psci: CPU6 killed (polled 0 ms)

11510 23:12:23.351371  <6>[   25.749142] psci: CPU7 killed (polled 0 ms)

11511 23:12:23.354503  <6>[   25.749503] Enabling non-boot CPUs ...

11512 23:12:23.361165  <6>[   25.749732] Detected VIPT I-cache on CPU1

11513 23:12:23.367844  <6>[   25.749819] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

11514 23:12:23.374719  <6>[   25.749881] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

11515 23:12:23.377813  <6>[   25.750536] CPU1 is up

11516 23:12:23.381383  <6>[   25.750676] Detected VIPT I-cache on CPU2

11517 23:12:23.388012  <6>[   25.750730] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

11518 23:12:23.394762  <6>[   25.750768] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

11519 23:12:23.397974  <6>[   25.751280] CPU2 is up

11520 23:12:23.401143  <6>[   25.751417] Detected VIPT I-cache on CPU3

11521 23:12:23.411561  <6>[   25.751472] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

11522 23:12:23.417732  <6>[   25.751509] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

11523 23:12:23.417834  <6>[   25.752034] CPU3 is up

11524 23:12:23.424554  <6>[   25.752160] Detected PIPT I-cache on CPU4

11525 23:12:23.431334  <6>[   25.752184] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

11526 23:12:23.437888  <6>[   25.752200] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

11527 23:12:23.440977  <6>[   25.752485] CPU4 is up

11528 23:12:23.444343  <6>[   25.752608] Detected PIPT I-cache on CPU5

11529 23:12:23.451175  <6>[   25.752633] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

11530 23:12:23.457581  <6>[   25.752648] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

11531 23:12:23.460973  <6>[   25.752903] CPU5 is up

11532 23:12:23.464200  <6>[   25.753025] Detected PIPT I-cache on CPU6

11533 23:12:23.474582  <6>[   25.753049] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

11534 23:12:23.480904  <6>[   25.753065] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

11535 23:12:23.481028  <6>[   25.753347] CPU6 is up

11536 23:12:23.487908  <6>[   25.753479] Detected PIPT I-cache on CPU7

11537 23:12:23.494222  <6>[   25.753504] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

11538 23:12:23.500935  <6>[   25.753519] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

11539 23:12:23.504018  <6>[   25.753798] CPU7 is up

11540 23:12:23.507761  <6>[   26.350988] OOM killer enabled.

11541 23:12:23.514382  <LAVA_SIGNAL_TES<6>[   26.350997] Restarting tasks ... done.

11542 23:12:23.514699  Received signal: <TES<6>[>   26.350997] Restarting tasks ... done.
<5
11543 23:12:23.520684  <5>[   26.352594] random: crng reseeded on system resumption

11544 23:12:23.524422  <6>[   26.353360] PM: suspend exit

11545 23:12:23.527588  TCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=pass>

11546 23:12:23.530671  rtcwake: assuming RTC uses UTC ...

11547 23:12:23.533839  rtcwake: wakeup from "mem" using rtc0 at Wed Dec 27 23:09:58 2023

11548 23:12:23.550153  <6>[   26.390891] PM: suspend entry (deep)

11549 23:12:23.553519  <6>[   26.390916] Filesystems sync: 0.000 seconds

11550 23:12:23.557283  <6>[   26.391186] Freezing user space processes

11551 23:12:23.563888  <6>[   26.392587] Freezing user space processes completed (elapsed 0.001 seconds)

11552 23:12:23.566838  <6>[   26.392594] OOM killer disabled.

11553 23:12:23.573934  <6>[   26.392596] Freezing remaining freezable tasks

11554 23:12:23.580189  <6>[   26.393323] Freezing remaining freezable tasks completed (elapsed 0.000 seconds)

11555 23:12:23.587082  <6>[   26.393327] printk: Suspending console(s) (use no_console_suspend to debug)

11556 23:12:29.265796  <6>[   26.587473] Disabling non-boot CPUs ...

11557 23:12:29.269494  <6>[   26.588454] psci: CPU1 killed (polled 0 ms)

11558 23:12:29.272436  <6>[   26.589581] psci: CPU2 killed (polled 0 ms)

11559 23:12:29.279103  <6>[   26.590487] psci: CPU3 killed (polled 0 ms)

11560 23:12:29.282870  <6>[   26.590971] psci: CPU4 killed (polled 0 ms)

11561 23:12:29.285957  <6>[   26.591481] psci: CPU5 killed (polled 0 ms)

11562 23:12:29.292919  <6>[   26.592136] psci: CPU6 killed (polled 0 ms)

11563 23:12:29.295876  <6>[   26.592794] psci: CPU7 killed (polled 0 ms)

11564 23:12:29.299542  <6>[   26.593289] Enabling non-boot CPUs ...

11565 23:12:29.302602  <6>[   26.593515] Detected VIPT I-cache on CPU1

11566 23:12:29.312665  <6>[   26.593601] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

11567 23:12:29.319364  <6>[   26.593660] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

11568 23:12:29.319448  <6>[   26.594306] CPU1 is up

11569 23:12:29.325974  <6>[   26.594445] Detected VIPT I-cache on CPU2

11570 23:12:29.332412  <6>[   26.594500] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

11571 23:12:29.339179  <6>[   26.594537] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

11572 23:12:29.342953  <6>[   26.595056] CPU2 is up

11573 23:12:29.346236  <6>[   26.595190] Detected VIPT I-cache on CPU3

11574 23:12:29.352472  <6>[   26.595245] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

11575 23:12:29.359244  <6>[   26.595281] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

11576 23:12:29.362907  <6>[   26.595802] CPU3 is up

11577 23:12:29.365812  <6>[   26.595925] Detected PIPT I-cache on CPU4

11578 23:12:29.372695  <6>[   26.595947] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

11579 23:12:29.385315  <6>[   26.595962] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

11580 23:12:29.385399  <6>[   26.596231] CPU4 is up

11581 23:12:29.391992  <6>[   26.596352] Detected PIPT I-cache on CPU5

11582 23:12:29.398791  <6>[   26.596375] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

11583 23:12:29.405587  <6>[   26.596389] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

11584 23:12:29.408771  <6>[   26.596630] CPU5 is up

11585 23:12:29.411849  <6>[   26.596750] Detected PIPT I-cache on CPU6

11586 23:12:29.418733  <6>[   26.596772] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

11587 23:12:29.425254  <6>[   26.596787] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

11588 23:12:29.428130  <6>[   26.597042] CPU6 is up

11589 23:12:29.431689  <6>[   26.597162] Detected PIPT I-cache on CPU7

11590 23:12:29.438403  <6>[   26.597185] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

11591 23:12:29.445254  <6>[   26.597199] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

11592 23:12:29.448184  <6>[   26.597658] CPU7 is up

11593 23:12:29.489726  <6>[   27.173515] OOM killer enabled.

11594 23:12:29.493113  <6>[   27.173524] Restarting tasks ... done.

11595 23:12:29.499693  <LAVA_SIGNAL_TES<5>[   27.175366] random: crng reseeded on system resumption

11596 23:12:29.500044  Received signal: <TES<5>[>   27.175366] random: crng reseeded on system resumption
<6
11597 23:12:29.503180  <6>[   27.176116] PM: suspend exit

11598 23:12:29.507071  TCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=pass>

11599 23:12:29.509916  rtcwake: assuming RTC uses UTC ...

11600 23:12:29.516130  rtcwake: wakeup from "mem" using rtc0 at Wed Dec 27 23:10:04 2023

11601 23:12:29.529989  <6>[   27.214882] PM: suspend entry (deep)

11602 23:12:29.533371  <6>[   27.214913] Filesystems sync: 0.000 seconds

11603 23:12:29.536282  <6>[   27.215221] Freezing user space processes

11604 23:12:29.543247  <6>[   27.216707] Freezing user space processes completed (elapsed 0.001 seconds)

11605 23:12:29.546236  <6>[   27.216714] OOM killer disabled.

11606 23:12:29.552703  <6>[   27.216715] Freezing remaining freezable tasks

11607 23:12:29.559438  <6>[   27.217836] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11608 23:12:29.566401  <6>[   27.217840] printk: Suspending console(s) (use no_console_suspend to debug)

11609 23:12:35.265482  <6>[   27.395211] Disabling non-boot CPUs ...

11610 23:12:35.268708  <6>[   27.396160] psci: CPU1 killed (polled 0 ms)

11611 23:12:35.271808  <6>[   27.397287] psci: CPU2 killed (polled 0 ms)

11612 23:12:35.278684  <6>[   27.398162] psci: CPU3 killed (polled 0 ms)

11613 23:12:35.282161  <6>[   27.398660] psci: CPU4 killed (polled 0 ms)

11614 23:12:35.285275  <6>[   27.399172] psci: CPU5 killed (polled 0 ms)

11615 23:12:35.292197  <6>[   27.399789] psci: CPU6 killed (polled 0 ms)

11616 23:12:35.295500  <6>[   27.400391] psci: CPU7 killed (polled 0 ms)

11617 23:12:35.298550  <6>[   27.400753] Enabling non-boot CPUs ...

11618 23:12:35.305419  <6>[   27.400973] Detected VIPT I-cache on CPU1

11619 23:12:35.312210  <6>[   27.401056] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

11620 23:12:35.318624  <6>[   27.401114] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

11621 23:12:35.322275  <6>[   27.401840] CPU1 is up

11622 23:12:35.325351  <6>[   27.401975] Detected VIPT I-cache on CPU2

11623 23:12:35.332189  <6>[   27.402029] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

11624 23:12:35.338960  <6>[   27.402064] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

11625 23:12:35.342270  <6>[   27.402563] CPU2 is up

11626 23:12:35.345552  <6>[   27.402692] Detected VIPT I-cache on CPU3

11627 23:12:35.351769  <6>[   27.402746] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

11628 23:12:35.358603  <6>[   27.402781] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

11629 23:12:35.362137  <6>[   27.403291] CPU3 is up

11630 23:12:35.365434  <6>[   27.403407] Detected PIPT I-cache on CPU4

11631 23:12:35.375113  <6>[   27.403424] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

11632 23:12:35.382124  <6>[   27.403436] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

11633 23:12:35.382196  <6>[   27.403662] CPU4 is up

11634 23:12:35.389535  <6>[   27.403776] Detected PIPT I-cache on CPU5

11635 23:12:35.396061  <6>[   27.403794] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

11636 23:12:35.403023  <6>[   27.403805] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

11637 23:12:35.406201  <6>[   27.403999] CPU5 is up

11638 23:12:35.409309  <6>[   27.404111] Detected PIPT I-cache on CPU6

11639 23:12:35.415656  <6>[   27.404128] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

11640 23:12:35.422321  <6>[   27.404139] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

11641 23:12:35.425793  <6>[   27.404338] CPU6 is up

11642 23:12:35.429230  <6>[   27.404456] Detected PIPT I-cache on CPU7

11643 23:12:35.439092  <6>[   27.404474] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

11644 23:12:35.446039  <6>[   27.404484] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

11645 23:12:35.446117  <6>[   27.404697] CPU7 is up

11646 23:12:35.497177  <6>[   27.989471] OOM killer enabled.

11647 23:12:35.500823  <6>[   27.989480] Restarting tasks ... done.

11648 23:12:35.503792  <5>[   27.991376] random: crng reseeded on system resumption

11649 23:12:35.507388  <6>[   27.992169] PM: suspend exit

11650 23:12:35.513861  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=pass>

11651 23:12:35.514182  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=pass
11653 23:12:35.517076  rtcwake: assuming RTC uses UTC ...

11654 23:12:35.523721  rtcwake: wakeup from "mem" using rtc0 at Wed Dec 27 23:10:10 2023

11655 23:12:35.537061  <6>[   28.031137] PM: suspend entry (deep)

11656 23:12:35.540497  <6>[   28.031194] Filesystems sync: 0.000 seconds

11657 23:12:35.549340  <6>[   28.031892] Freezing user space processes

11658 23:12:35.556206  <6>[   28.033308] Freezing user space processes completed (elapsed 0.001 seconds)

11659 23:12:35.559319  <6>[   28.033319] OOM killer disabled.

11660 23:12:35.563000  <6>[   28.033321] Freezing remaining freezable tasks

11661 23:12:35.572749  <6>[   28.034592] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)

11662 23:12:35.579397  <6>[   28.034599] printk: Suspending console(s) (use no_console_suspend to debug)

11663 23:12:41.265077  <6>[   28.230595] Disabling non-boot CPUs ...

11664 23:12:41.268173  <6>[   28.231364] psci: CPU1 killed (polled 0 ms)

11665 23:12:41.271809  <6>[   28.232234] psci: CPU2 killed (polled 0 ms)

11666 23:12:41.278617  <6>[   28.232939] psci: CPU3 killed (polled 0 ms)

11667 23:12:41.281639  <6>[   28.233449] psci: CPU4 killed (polled 0 ms)

11668 23:12:41.285358  <6>[   28.234879] psci: CPU5 killed (polled 0 ms)

11669 23:12:41.291624  <6>[   28.235364] psci: CPU6 killed (polled 0 ms)

11670 23:12:41.295266  <6>[   28.235913] psci: CPU7 killed (polled 0 ms)

11671 23:12:41.298057  <6>[   28.236266] Enabling non-boot CPUs ...

11672 23:12:41.301409  <6>[   28.236460] Detected VIPT I-cache on CPU1

11673 23:12:41.311722  <6>[   28.236531] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

11674 23:12:41.318287  <6>[   28.236581] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

11675 23:12:41.322047  <6>[   28.237106] CPU1 is up

11676 23:12:41.325048  <6>[   28.237285] Detected VIPT I-cache on CPU2

11677 23:12:41.331676  <6>[   28.237325] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

11678 23:12:41.338545  <6>[   28.237352] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

11679 23:12:41.341593  <6>[   28.237726] CPU2 is up

11680 23:12:41.345342  <6>[   28.237834] Detected VIPT I-cache on CPU3

11681 23:12:41.351593  <6>[   28.237875] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

11682 23:12:41.358292  <6>[   28.237902] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

11683 23:12:41.361464  <6>[   28.238288] CPU3 is up

11684 23:12:41.365027  <6>[   28.238392] Detected PIPT I-cache on CPU4

11685 23:12:41.375159  <6>[   28.238410] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

11686 23:12:41.382118  <6>[   28.238422] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

11687 23:12:41.384931  <6>[   28.238646] CPU4 is up

11688 23:12:41.388649  <6>[   28.238747] Detected PIPT I-cache on CPU5

11689 23:12:41.398465  <6>[   28.238765] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

11690 23:12:41.404758  <6>[   28.238777] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

11691 23:12:41.404840  <6>[   28.238971] CPU5 is up

11692 23:12:41.411689  <6>[   28.239071] Detected PIPT I-cache on CPU6

11693 23:12:41.418565  <6>[   28.239090] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

11694 23:12:41.424951  <6>[   28.239101] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

11695 23:12:41.428143  <6>[   28.239300] CPU6 is up

11696 23:12:41.431641  <6>[   28.239406] Detected PIPT I-cache on CPU7

11697 23:12:41.438494  <6>[   28.239425] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

11698 23:12:41.445354  <6>[   28.239436] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

11699 23:12:41.448671  <6>[   28.239653] CPU7 is up

11700 23:12:41.489124  <6>[   28.817431] OOM killer enabled.

11701 23:12:41.492211  <6>[   28.817440] Restarting tasks ... done.

11702 23:12:41.495799  <5>[   28.821410] random: crng reseeded on system resumption

11703 23:12:41.498692  <6>[   28.824674] PM: suspend exit

11704 23:12:41.505801  <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=pass>

11705 23:12:41.505879  + set +x

11706 23:12:41.506132  Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=pass
11708 23:12:41.512139  <LAVA_SIGNAL_ENDRUN 0_sleep 12395368_1.5.2.3.1>

11709 23:12:41.512241  <LAVA_TEST_RUNNER EXIT>

11710 23:12:41.512514  Received signal: <ENDRUN> 0_sleep 12395368_1.5.2.3.1
11711 23:12:41.512593  Ending use of test pattern.
11712 23:12:41.512656  Ending test lava.0_sleep (12395368_1.5.2.3.1), duration 60.09
11714 23:12:41.512871  ok: lava_test_shell seems to have completed
11715 23:12:41.512995  rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-mem-10: pass
rtcwake-mem-2: pass
rtcwake-mem-3: pass
rtcwake-mem-4: pass
rtcwake-mem-5: pass
rtcwake-mem-6: pass
rtcwake-mem-9: pass

11716 23:12:41.513082  end: 3.1 lava-test-shell (duration 00:01:01) [common]
11717 23:12:41.513163  end: 3 lava-test-retry (duration 00:01:01) [common]
11718 23:12:41.513249  start: 4 finalize (timeout 00:06:15) [common]
11719 23:12:41.513332  start: 4.1 power-off (timeout 00:00:30) [common]
11720 23:12:41.513483  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11721 23:12:41.591296  >> Command sent successfully.

11722 23:12:41.594373  Returned 0 in 0 seconds
11723 23:12:41.694813  end: 4.1 power-off (duration 00:00:00) [common]
11725 23:12:41.695135  start: 4.2 read-feedback (timeout 00:06:15) [common]
11726 23:12:41.695402  Listened to connection for namespace 'common' for up to 1s
11727 23:12:42.696327  Finalising connection for namespace 'common'
11728 23:12:42.696508  Disconnecting from shell: Finalise
11729 23:12:42.696591  / # 
11730 23:12:42.796929  end: 4.2 read-feedback (duration 00:00:01) [common]
11731 23:12:42.797102  end: 4 finalize (duration 00:00:01) [common]
11732 23:12:42.797231  Cleaning after the job
11733 23:12:42.797348  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395368/tftp-deploy-rxfkiwk3/ramdisk
11734 23:12:42.811203  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395368/tftp-deploy-rxfkiwk3/kernel
11735 23:12:42.835535  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395368/tftp-deploy-rxfkiwk3/dtb
11736 23:12:42.835763  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395368/tftp-deploy-rxfkiwk3/modules
11737 23:12:42.843250  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12395368
11738 23:12:43.018889  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12395368
11739 23:12:43.019066  Job finished correctly