Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 13
- Kernel Errors: 29
- Errors: 1
1 23:09:24.027044 lava-dispatcher, installed at version: 2023.10
2 23:09:24.027260 start: 0 validate
3 23:09:24.027383 Start time: 2023-12-27 23:09:24.027376+00:00 (UTC)
4 23:09:24.027503 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:09:24.027636 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 23:09:24.297854 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:09:24.298596 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:09:24.562032 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:09:24.562784 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:09:24.834191 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:09:24.834986 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:09:25.096269 validate duration: 1.07
14 23:09:25.097698 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:09:25.098237 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:09:25.098736 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:09:25.099416 Not decompressing ramdisk as can be used compressed.
18 23:09:25.099947 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 23:09:25.100332 saving as /var/lib/lava/dispatcher/tmp/12395386/tftp-deploy-_crc1ad_/ramdisk/rootfs.cpio.gz
20 23:09:25.100688 total size: 26246609 (25 MB)
21 23:09:25.106586 progress 0 % (0 MB)
22 23:09:25.131771 progress 5 % (1 MB)
23 23:09:25.143394 progress 10 % (2 MB)
24 23:09:25.152292 progress 15 % (3 MB)
25 23:09:25.159765 progress 20 % (5 MB)
26 23:09:25.166784 progress 25 % (6 MB)
27 23:09:25.173579 progress 30 % (7 MB)
28 23:09:25.180374 progress 35 % (8 MB)
29 23:09:25.187195 progress 40 % (10 MB)
30 23:09:25.194050 progress 45 % (11 MB)
31 23:09:25.200939 progress 50 % (12 MB)
32 23:09:25.207819 progress 55 % (13 MB)
33 23:09:25.214681 progress 60 % (15 MB)
34 23:09:25.221592 progress 65 % (16 MB)
35 23:09:25.228473 progress 70 % (17 MB)
36 23:09:25.235311 progress 75 % (18 MB)
37 23:09:25.242199 progress 80 % (20 MB)
38 23:09:25.248972 progress 85 % (21 MB)
39 23:09:25.255696 progress 90 % (22 MB)
40 23:09:25.262483 progress 95 % (23 MB)
41 23:09:25.269139 progress 100 % (25 MB)
42 23:09:25.269386 25 MB downloaded in 0.17 s (148.36 MB/s)
43 23:09:25.269544 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:09:25.269792 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:09:25.269879 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:09:25.269962 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:09:25.270099 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:09:25.270168 saving as /var/lib/lava/dispatcher/tmp/12395386/tftp-deploy-_crc1ad_/kernel/Image
50 23:09:25.270228 total size: 50024960 (47 MB)
51 23:09:25.270289 No compression specified
52 23:09:25.271431 progress 0 % (0 MB)
53 23:09:25.284280 progress 5 % (2 MB)
54 23:09:25.297073 progress 10 % (4 MB)
55 23:09:25.310033 progress 15 % (7 MB)
56 23:09:25.323186 progress 20 % (9 MB)
57 23:09:25.336044 progress 25 % (11 MB)
58 23:09:25.348954 progress 30 % (14 MB)
59 23:09:25.362157 progress 35 % (16 MB)
60 23:09:25.375041 progress 40 % (19 MB)
61 23:09:25.387796 progress 45 % (21 MB)
62 23:09:25.400723 progress 50 % (23 MB)
63 23:09:25.413569 progress 55 % (26 MB)
64 23:09:25.426376 progress 60 % (28 MB)
65 23:09:25.439215 progress 65 % (31 MB)
66 23:09:25.451884 progress 70 % (33 MB)
67 23:09:25.464673 progress 75 % (35 MB)
68 23:09:25.477577 progress 80 % (38 MB)
69 23:09:25.490523 progress 85 % (40 MB)
70 23:09:25.503451 progress 90 % (42 MB)
71 23:09:25.516407 progress 95 % (45 MB)
72 23:09:25.529003 progress 100 % (47 MB)
73 23:09:25.529213 47 MB downloaded in 0.26 s (184.21 MB/s)
74 23:09:25.529379 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:09:25.529636 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:09:25.529742 start: 1.3 download-retry (timeout 00:10:00) [common]
78 23:09:25.529844 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 23:09:25.529998 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:09:25.530096 saving as /var/lib/lava/dispatcher/tmp/12395386/tftp-deploy-_crc1ad_/dtb/mt8192-asurada-spherion-r0.dtb
81 23:09:25.530194 total size: 47278 (0 MB)
82 23:09:25.530293 No compression specified
83 23:09:25.531977 progress 69 % (0 MB)
84 23:09:25.532279 progress 100 % (0 MB)
85 23:09:25.532470 0 MB downloaded in 0.00 s (19.83 MB/s)
86 23:09:25.532640 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:09:25.532972 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:09:25.533071 start: 1.4 download-retry (timeout 00:10:00) [common]
90 23:09:25.533169 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 23:09:25.533300 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:09:25.533372 saving as /var/lib/lava/dispatcher/tmp/12395386/tftp-deploy-_crc1ad_/modules/modules.tar
93 23:09:25.533470 total size: 8633892 (8 MB)
94 23:09:25.533570 Using unxz to decompress xz
95 23:09:25.538185 progress 0 % (0 MB)
96 23:09:25.558884 progress 5 % (0 MB)
97 23:09:25.582070 progress 10 % (0 MB)
98 23:09:25.605347 progress 15 % (1 MB)
99 23:09:25.628817 progress 20 % (1 MB)
100 23:09:25.652443 progress 25 % (2 MB)
101 23:09:25.679595 progress 30 % (2 MB)
102 23:09:25.703619 progress 35 % (2 MB)
103 23:09:25.726955 progress 40 % (3 MB)
104 23:09:25.750830 progress 45 % (3 MB)
105 23:09:25.775660 progress 50 % (4 MB)
106 23:09:25.799681 progress 55 % (4 MB)
107 23:09:25.826320 progress 60 % (4 MB)
108 23:09:25.851872 progress 65 % (5 MB)
109 23:09:25.876653 progress 70 % (5 MB)
110 23:09:25.899957 progress 75 % (6 MB)
111 23:09:25.927002 progress 80 % (6 MB)
112 23:09:25.952490 progress 85 % (7 MB)
113 23:09:25.978882 progress 90 % (7 MB)
114 23:09:26.008311 progress 95 % (7 MB)
115 23:09:26.036217 progress 100 % (8 MB)
116 23:09:26.041733 8 MB downloaded in 0.51 s (16.20 MB/s)
117 23:09:26.041989 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:09:26.042286 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:09:26.042395 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:09:26.042507 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:09:26.042602 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:09:26.042710 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:09:26.042961 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4
125 23:09:26.043138 makedir: /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin
126 23:09:26.043285 makedir: /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/tests
127 23:09:26.043425 makedir: /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/results
128 23:09:26.043557 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-add-keys
129 23:09:26.043725 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-add-sources
130 23:09:26.043873 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-background-process-start
131 23:09:26.044021 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-background-process-stop
132 23:09:26.044171 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-common-functions
133 23:09:26.044342 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-echo-ipv4
134 23:09:26.044516 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-install-packages
135 23:09:26.044687 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-installed-packages
136 23:09:26.044879 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-os-build
137 23:09:26.045023 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-probe-channel
138 23:09:26.045167 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-probe-ip
139 23:09:26.045311 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-target-ip
140 23:09:26.045455 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-target-mac
141 23:09:26.045601 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-target-storage
142 23:09:26.045776 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-test-case
143 23:09:26.045948 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-test-event
144 23:09:26.046114 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-test-feedback
145 23:09:26.046259 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-test-raise
146 23:09:26.046406 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-test-reference
147 23:09:26.046552 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-test-runner
148 23:09:26.046695 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-test-set
149 23:09:26.046839 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-test-shell
150 23:09:26.046989 Updating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-install-packages (oe)
151 23:09:26.047186 Updating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/bin/lava-installed-packages (oe)
152 23:09:26.047353 Creating /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/environment
153 23:09:26.047490 LAVA metadata
154 23:09:26.047573 - LAVA_JOB_ID=12395386
155 23:09:26.047653 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:09:26.047781 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:09:26.047859 skipped lava-vland-overlay
158 23:09:26.047979 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:09:26.048099 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:09:26.048201 skipped lava-multinode-overlay
161 23:09:26.048320 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:09:26.048449 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:09:26.048564 Loading test definitions
164 23:09:26.048699 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:09:26.048860 Using /lava-12395386 at stage 0
166 23:09:26.049286 uuid=12395386_1.5.2.3.1 testdef=None
167 23:09:26.049412 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:09:26.049538 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:09:26.050269 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:09:26.050544 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:09:26.051188 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:09:26.051448 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:09:26.052283 runner path: /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 12395386_1.5.2.3.1
176 23:09:26.052479 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:09:26.052712 Creating lava-test-runner.conf files
179 23:09:26.052813 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12395386/lava-overlay-uuf7udh4/lava-12395386/0 for stage 0
180 23:09:26.052949 - 0_v4l2-compliance-mtk-vcodec-enc
181 23:09:26.053085 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:09:26.053211 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 23:09:26.061410 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:09:26.061547 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 23:09:26.061648 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:09:26.061755 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:09:26.061860 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 23:09:26.768379 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 23:09:26.768796 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 23:09:26.768933 extracting modules file /var/lib/lava/dispatcher/tmp/12395386/tftp-deploy-_crc1ad_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12395386/extract-overlay-ramdisk-l8zuxi6j/ramdisk
191 23:09:26.997464 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:09:26.997628 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 23:09:26.997722 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12395386/compress-overlay-fv6xidt_/overlay-1.5.2.4.tar.gz to ramdisk
194 23:09:26.997793 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12395386/compress-overlay-fv6xidt_/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12395386/extract-overlay-ramdisk-l8zuxi6j/ramdisk
195 23:09:27.004337 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:09:27.004447 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 23:09:27.004535 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:09:27.004621 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 23:09:27.004697 Building ramdisk /var/lib/lava/dispatcher/tmp/12395386/extract-overlay-ramdisk-l8zuxi6j/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12395386/extract-overlay-ramdisk-l8zuxi6j/ramdisk
200 23:09:27.640238 >> 228450 blocks
201 23:09:31.608872 rename /var/lib/lava/dispatcher/tmp/12395386/extract-overlay-ramdisk-l8zuxi6j/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12395386/tftp-deploy-_crc1ad_/ramdisk/ramdisk.cpio.gz
202 23:09:31.609320 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 23:09:31.609451 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 23:09:31.609555 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 23:09:31.609662 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12395386/tftp-deploy-_crc1ad_/kernel/Image'
206 23:09:43.595158 Returned 0 in 11 seconds
207 23:09:43.696290 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12395386/tftp-deploy-_crc1ad_/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12395386/tftp-deploy-_crc1ad_/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12395386/tftp-deploy-_crc1ad_/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12395386/tftp-deploy-_crc1ad_/kernel/image.itb
208 23:09:44.335840 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:09:44.336226 output: Created: Wed Dec 27 23:09:44 2023
210 23:09:44.336302 output: Image 0 (kernel-1)
211 23:09:44.336365 output: Description:
212 23:09:44.336426 output: Created: Wed Dec 27 23:09:44 2023
213 23:09:44.336486 output: Type: Kernel Image
214 23:09:44.336547 output: Compression: lzma compressed
215 23:09:44.336605 output: Data Size: 11480388 Bytes = 11211.32 KiB = 10.95 MiB
216 23:09:44.336663 output: Architecture: AArch64
217 23:09:44.336733 output: OS: Linux
218 23:09:44.336793 output: Load Address: 0x00000000
219 23:09:44.336850 output: Entry Point: 0x00000000
220 23:09:44.336906 output: Hash algo: crc32
221 23:09:44.336961 output: Hash value: a55b2f0b
222 23:09:44.337019 output: Image 1 (fdt-1)
223 23:09:44.337073 output: Description: mt8192-asurada-spherion-r0
224 23:09:44.337124 output: Created: Wed Dec 27 23:09:44 2023
225 23:09:44.337176 output: Type: Flat Device Tree
226 23:09:44.337227 output: Compression: uncompressed
227 23:09:44.337279 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 23:09:44.337331 output: Architecture: AArch64
229 23:09:44.337382 output: Hash algo: crc32
230 23:09:44.337434 output: Hash value: cc4352de
231 23:09:44.337485 output: Image 2 (ramdisk-1)
232 23:09:44.337536 output: Description: unavailable
233 23:09:44.337587 output: Created: Wed Dec 27 23:09:44 2023
234 23:09:44.337639 output: Type: RAMDisk Image
235 23:09:44.337691 output: Compression: Unknown Compression
236 23:09:44.337742 output: Data Size: 39374984 Bytes = 38452.13 KiB = 37.55 MiB
237 23:09:44.337793 output: Architecture: AArch64
238 23:09:44.337845 output: OS: Linux
239 23:09:44.337895 output: Load Address: unavailable
240 23:09:44.337947 output: Entry Point: unavailable
241 23:09:44.337996 output: Hash algo: crc32
242 23:09:44.338047 output: Hash value: 5d38481c
243 23:09:44.338097 output: Default Configuration: 'conf-1'
244 23:09:44.338148 output: Configuration 0 (conf-1)
245 23:09:44.338199 output: Description: mt8192-asurada-spherion-r0
246 23:09:44.338250 output: Kernel: kernel-1
247 23:09:44.338301 output: Init Ramdisk: ramdisk-1
248 23:09:44.338352 output: FDT: fdt-1
249 23:09:44.338403 output: Loadables: kernel-1
250 23:09:44.338453 output:
251 23:09:44.338670 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 23:09:44.338797 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 23:09:44.338903 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 23:09:44.339001 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 23:09:44.339080 No LXC device requested
256 23:09:44.339161 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:09:44.339245 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 23:09:44.339322 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:09:44.339390 Checking files for TFTP limit of 4294967296 bytes.
260 23:09:44.339882 end: 1 tftp-deploy (duration 00:00:19) [common]
261 23:09:44.339986 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:09:44.340075 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:09:44.340202 substitutions:
264 23:09:44.340273 - {DTB}: 12395386/tftp-deploy-_crc1ad_/dtb/mt8192-asurada-spherion-r0.dtb
265 23:09:44.340337 - {INITRD}: 12395386/tftp-deploy-_crc1ad_/ramdisk/ramdisk.cpio.gz
266 23:09:44.340394 - {KERNEL}: 12395386/tftp-deploy-_crc1ad_/kernel/Image
267 23:09:44.340451 - {LAVA_MAC}: None
268 23:09:44.340521 - {PRESEED_CONFIG}: None
269 23:09:44.340592 - {PRESEED_LOCAL}: None
270 23:09:44.340680 - {RAMDISK}: 12395386/tftp-deploy-_crc1ad_/ramdisk/ramdisk.cpio.gz
271 23:09:44.340770 - {ROOT_PART}: None
272 23:09:44.340824 - {ROOT}: None
273 23:09:44.340878 - {SERVER_IP}: 192.168.201.1
274 23:09:44.340931 - {TEE}: None
275 23:09:44.340983 Parsed boot commands:
276 23:09:44.341035 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:09:44.341213 Parsed boot commands: tftpboot 192.168.201.1 12395386/tftp-deploy-_crc1ad_/kernel/image.itb 12395386/tftp-deploy-_crc1ad_/kernel/cmdline
278 23:09:44.341300 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:09:44.341388 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:09:44.341478 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:09:44.341565 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:09:44.341634 Not connected, no need to disconnect.
283 23:09:44.341706 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:09:44.341782 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:09:44.341846 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 23:09:44.345850 Setting prompt string to ['lava-test: # ']
287 23:09:44.346210 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:09:44.346317 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:09:44.346412 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:09:44.346505 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:09:44.346695 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
292 23:09:49.493502 >> Command sent successfully.
293 23:09:49.505086 Returned 0 in 5 seconds
294 23:09:49.606285 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:09:49.607798 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:09:49.608341 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:09:49.608869 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:09:49.609258 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:09:49.609650 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:09:49.610960 [Enter `^Ec?' for help]
302 23:09:49.778170
303 23:09:49.778748
304 23:09:49.779146 F0: 102B 0000
305 23:09:49.779518
306 23:09:49.779860 F3: 1001 0000 [0200]
307 23:09:49.781552
308 23:09:49.782089 F3: 1001 0000
309 23:09:49.782459
310 23:09:49.782798 F7: 102D 0000
311 23:09:49.783124
312 23:09:49.785263 F1: 0000 0000
313 23:09:49.785729
314 23:09:49.786090 V0: 0000 0000 [0001]
315 23:09:49.786493
316 23:09:49.786846 00: 0007 8000
317 23:09:49.787233
318 23:09:49.789307 01: 0000 0000
319 23:09:49.789780
320 23:09:49.790144 BP: 0C00 0209 [0000]
321 23:09:49.790528
322 23:09:49.792360 G0: 1182 0000
323 23:09:49.792931
324 23:09:49.793309 EC: 0000 0021 [4000]
325 23:09:49.793651
326 23:09:49.796867 S7: 0000 0000 [0000]
327 23:09:49.797329
328 23:09:49.797692 CC: 0000 0000 [0001]
329 23:09:49.798026
330 23:09:49.799736 T0: 0000 0040 [010F]
331 23:09:49.800203
332 23:09:49.800589 Jump to BL
333 23:09:49.800960
334 23:09:49.824810
335 23:09:49.825320
336 23:09:49.825649
337 23:09:49.831635 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 23:09:49.834941 ARM64: Exception handlers installed.
339 23:09:49.838655 ARM64: Testing exception
340 23:09:49.842197 ARM64: Done test exception
341 23:09:49.848652 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 23:09:49.858795 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 23:09:49.865968 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 23:09:49.875830 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 23:09:49.882579 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 23:09:49.892639 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 23:09:49.902519 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 23:09:49.909634 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 23:09:49.928219 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 23:09:49.931341 WDT: Last reset was cold boot
351 23:09:49.934427 SPI1(PAD0) initialized at 2873684 Hz
352 23:09:49.937577 SPI5(PAD0) initialized at 992727 Hz
353 23:09:49.941355 VBOOT: Loading verstage.
354 23:09:49.947938 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 23:09:49.951401 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 23:09:49.954425 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 23:09:49.958121 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 23:09:49.964908 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 23:09:49.971529 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 23:09:49.982936 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 23:09:49.983500
362 23:09:49.983861
363 23:09:49.992862 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 23:09:49.996121 ARM64: Exception handlers installed.
365 23:09:49.999903 ARM64: Testing exception
366 23:09:50.000484 ARM64: Done test exception
367 23:09:50.006186 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 23:09:50.009306 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 23:09:50.023927 Probing TPM: . done!
370 23:09:50.024497 TPM ready after 0 ms
371 23:09:50.030765 Connected to device vid:did:rid of 1ae0:0028:00
372 23:09:50.037387 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
373 23:09:50.041125 Initialized TPM device CR50 revision 0
374 23:09:50.091476 tlcl_send_startup: Startup return code is 0
375 23:09:50.092023 TPM: setup succeeded
376 23:09:50.102847 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 23:09:50.112116 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 23:09:50.121640 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 23:09:50.131075 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 23:09:50.134203 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 23:09:50.137606 in-header: 03 07 00 00 08 00 00 00
382 23:09:50.140850 in-data: aa e4 47 04 13 02 00 00
383 23:09:50.144236 Chrome EC: UHEPI supported
384 23:09:50.150988 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 23:09:50.154117 in-header: 03 9d 00 00 08 00 00 00
386 23:09:50.157278 in-data: 10 20 20 08 00 00 00 00
387 23:09:50.157920 Phase 1
388 23:09:50.160845 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 23:09:50.167756 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 23:09:50.174046 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 23:09:50.177318 Recovery requested (1009000e)
392 23:09:50.184192 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 23:09:50.189641 tlcl_extend: response is 0
394 23:09:50.197594 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 23:09:50.203403 tlcl_extend: response is 0
396 23:09:50.209702 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 23:09:50.230692 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 23:09:50.237054 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 23:09:50.237615
400 23:09:50.237985
401 23:09:50.246919 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 23:09:50.250395 ARM64: Exception handlers installed.
403 23:09:50.253651 ARM64: Testing exception
404 23:09:50.254242 ARM64: Done test exception
405 23:09:50.276124 pmic_efuse_setting: Set efuses in 11 msecs
406 23:09:50.279687 pmwrap_interface_init: Select PMIF_VLD_RDY
407 23:09:50.286180 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 23:09:50.289647 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 23:09:50.293523 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 23:09:50.300528 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 23:09:50.304424 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 23:09:50.308065 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 23:09:50.314932 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 23:09:50.318848 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 23:09:50.321818 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 23:09:50.328464 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 23:09:50.331704 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 23:09:50.338864 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 23:09:50.341713 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 23:09:50.347926 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 23:09:50.355136 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 23:09:50.358012 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 23:09:50.365245 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 23:09:50.372135 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 23:09:50.375933 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 23:09:50.382397 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 23:09:50.388922 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 23:09:50.392270 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 23:09:50.398734 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 23:09:50.405468 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 23:09:50.408859 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 23:09:50.415784 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 23:09:50.418583 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 23:09:50.425872 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 23:09:50.428872 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 23:09:50.435768 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 23:09:50.439051 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 23:09:50.445663 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 23:09:50.448827 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 23:09:50.455365 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 23:09:50.458880 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 23:09:50.465484 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 23:09:50.468847 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 23:09:50.475166 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 23:09:50.478435 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 23:09:50.482276 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 23:09:50.488758 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 23:09:50.492057 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 23:09:50.495531 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 23:09:50.501969 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 23:09:50.505188 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 23:09:50.508646 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 23:09:50.515547 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 23:09:50.518764 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 23:09:50.522194 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 23:09:50.525540 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 23:09:50.532176 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 23:09:50.539072 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 23:09:50.545672 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 23:09:50.552364 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 23:09:50.558970 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 23:09:50.569016 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 23:09:50.572409 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 23:09:50.579106 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:09:50.582214 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 23:09:50.588778 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 23:09:50.595552 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 23:09:50.599432 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 23:09:50.602406 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 23:09:50.613225 [RTC]rtc_get_frequency_meter,154: input=15, output=764
471 23:09:50.622732 [RTC]rtc_get_frequency_meter,154: input=23, output=949
472 23:09:50.632034 [RTC]rtc_get_frequency_meter,154: input=19, output=856
473 23:09:50.641578 [RTC]rtc_get_frequency_meter,154: input=17, output=810
474 23:09:50.651013 [RTC]rtc_get_frequency_meter,154: input=16, output=788
475 23:09:50.660436 [RTC]rtc_get_frequency_meter,154: input=16, output=787
476 23:09:50.670099 [RTC]rtc_get_frequency_meter,154: input=17, output=810
477 23:09:50.673419 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 23:09:50.680919 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 23:09:50.684095 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 23:09:50.687007 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 23:09:50.693749 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 23:09:50.697506 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 23:09:50.700663 ADC[4]: Raw value=669695 ID=5
484 23:09:50.701286 ADC[3]: Raw value=212549 ID=1
485 23:09:50.704190 RAM Code: 0x51
486 23:09:50.707201 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 23:09:50.714011 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 23:09:50.720873 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 23:09:50.727232 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 23:09:50.730638 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 23:09:50.733843 in-header: 03 07 00 00 08 00 00 00
492 23:09:50.737377 in-data: aa e4 47 04 13 02 00 00
493 23:09:50.740433 Chrome EC: UHEPI supported
494 23:09:50.746958 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 23:09:50.750738 in-header: 03 d5 00 00 08 00 00 00
496 23:09:50.753778 in-data: 98 20 60 08 00 00 00 00
497 23:09:50.757170 MRC: failed to locate region type 0.
498 23:09:50.763852 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 23:09:50.764412 DRAM-K: Running full calibration
500 23:09:50.771062 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 23:09:50.774079 header.status = 0x0
502 23:09:50.777361 header.version = 0x6 (expected: 0x6)
503 23:09:50.780632 header.size = 0xd00 (expected: 0xd00)
504 23:09:50.781272 header.flags = 0x0
505 23:09:50.787049 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 23:09:50.805394 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 23:09:50.812071 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 23:09:50.815369 dram_init: ddr_geometry: 0
509 23:09:50.818566 [EMI] MDL number = 0
510 23:09:50.819039 [EMI] Get MDL freq = 0
511 23:09:50.821887 dram_init: ddr_type: 0
512 23:09:50.822358 is_discrete_lpddr4: 1
513 23:09:50.825316 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 23:09:50.825784
515 23:09:50.826151
516 23:09:50.828940 [Bian_co] ETT version 0.0.0.1
517 23:09:50.833200 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 23:09:50.833789
519 23:09:50.840838 dramc_set_vcore_voltage set vcore to 650000
520 23:09:50.841413 Read voltage for 800, 4
521 23:09:50.843220 Vio18 = 0
522 23:09:50.843689 Vcore = 650000
523 23:09:50.844236 Vdram = 0
524 23:09:50.844686 Vddq = 0
525 23:09:50.846174 Vmddr = 0
526 23:09:50.846639 dram_init: config_dvfs: 1
527 23:09:50.852873 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 23:09:50.860017 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 23:09:50.862943 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 23:09:50.865978 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 23:09:50.869403 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 23:09:50.872917 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 23:09:50.875933 MEM_TYPE=3, freq_sel=18
534 23:09:50.879672 sv_algorithm_assistance_LP4_1600
535 23:09:50.883062 ============ PULL DRAM RESETB DOWN ============
536 23:09:50.885939 ========== PULL DRAM RESETB DOWN end =========
537 23:09:50.893094 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 23:09:50.896299 ===================================
539 23:09:50.896924 LPDDR4 DRAM CONFIGURATION
540 23:09:50.900068 ===================================
541 23:09:50.903287 EX_ROW_EN[0] = 0x0
542 23:09:50.903864 EX_ROW_EN[1] = 0x0
543 23:09:50.906137 LP4Y_EN = 0x0
544 23:09:50.906610 WORK_FSP = 0x0
545 23:09:50.909523 WL = 0x2
546 23:09:50.909995 RL = 0x2
547 23:09:50.913285 BL = 0x2
548 23:09:50.916348 RPST = 0x0
549 23:09:50.916979 RD_PRE = 0x0
550 23:09:50.919677 WR_PRE = 0x1
551 23:09:50.920249 WR_PST = 0x0
552 23:09:50.923114 DBI_WR = 0x0
553 23:09:50.923584 DBI_RD = 0x0
554 23:09:50.926636 OTF = 0x1
555 23:09:50.929572 ===================================
556 23:09:50.933191 ===================================
557 23:09:50.933767 ANA top config
558 23:09:50.936499 ===================================
559 23:09:50.939732 DLL_ASYNC_EN = 0
560 23:09:50.943064 ALL_SLAVE_EN = 1
561 23:09:50.943533 NEW_RANK_MODE = 1
562 23:09:50.946558 DLL_IDLE_MODE = 1
563 23:09:50.949532 LP45_APHY_COMB_EN = 1
564 23:09:50.953145 TX_ODT_DIS = 1
565 23:09:50.953710 NEW_8X_MODE = 1
566 23:09:50.956121 ===================================
567 23:09:50.959778 ===================================
568 23:09:50.962804 data_rate = 1600
569 23:09:50.966529 CKR = 1
570 23:09:50.969890 DQ_P2S_RATIO = 8
571 23:09:50.972755 ===================================
572 23:09:50.976085 CA_P2S_RATIO = 8
573 23:09:50.979385 DQ_CA_OPEN = 0
574 23:09:50.979854 DQ_SEMI_OPEN = 0
575 23:09:50.982643 CA_SEMI_OPEN = 0
576 23:09:50.986037 CA_FULL_RATE = 0
577 23:09:50.989379 DQ_CKDIV4_EN = 1
578 23:09:50.992881 CA_CKDIV4_EN = 1
579 23:09:50.995939 CA_PREDIV_EN = 0
580 23:09:50.996412 PH8_DLY = 0
581 23:09:50.999591 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 23:09:51.002497 DQ_AAMCK_DIV = 4
583 23:09:51.006135 CA_AAMCK_DIV = 4
584 23:09:51.009485 CA_ADMCK_DIV = 4
585 23:09:51.012888 DQ_TRACK_CA_EN = 0
586 23:09:51.013465 CA_PICK = 800
587 23:09:51.016087 CA_MCKIO = 800
588 23:09:51.019541 MCKIO_SEMI = 0
589 23:09:51.022554 PLL_FREQ = 3068
590 23:09:51.026154 DQ_UI_PI_RATIO = 32
591 23:09:51.029237 CA_UI_PI_RATIO = 0
592 23:09:51.032468 ===================================
593 23:09:51.036079 ===================================
594 23:09:51.036654 memory_type:LPDDR4
595 23:09:51.039298 GP_NUM : 10
596 23:09:51.042718 SRAM_EN : 1
597 23:09:51.043291 MD32_EN : 0
598 23:09:51.046364 ===================================
599 23:09:51.049644 [ANA_INIT] >>>>>>>>>>>>>>
600 23:09:51.052581 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 23:09:51.055886 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 23:09:51.059558 ===================================
603 23:09:51.062627 data_rate = 1600,PCW = 0X7600
604 23:09:51.066060 ===================================
605 23:09:51.069459 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 23:09:51.073115 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:09:51.079429 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 23:09:51.082403 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 23:09:51.085802 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:09:51.089027 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 23:09:51.092556 [ANA_INIT] flow start
612 23:09:51.096104 [ANA_INIT] PLL >>>>>>>>
613 23:09:51.096682 [ANA_INIT] PLL <<<<<<<<
614 23:09:51.099428 [ANA_INIT] MIDPI >>>>>>>>
615 23:09:51.102395 [ANA_INIT] MIDPI <<<<<<<<
616 23:09:51.105819 [ANA_INIT] DLL >>>>>>>>
617 23:09:51.106375 [ANA_INIT] flow end
618 23:09:51.109090 ============ LP4 DIFF to SE enter ============
619 23:09:51.116217 ============ LP4 DIFF to SE exit ============
620 23:09:51.116845 [ANA_INIT] <<<<<<<<<<<<<
621 23:09:51.119575 [Flow] Enable top DCM control >>>>>
622 23:09:51.122527 [Flow] Enable top DCM control <<<<<
623 23:09:51.125916 Enable DLL master slave shuffle
624 23:09:51.132793 ==============================================================
625 23:09:51.133400 Gating Mode config
626 23:09:51.139039 ==============================================================
627 23:09:51.142733 Config description:
628 23:09:51.149012 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 23:09:51.156071 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 23:09:51.162952 SELPH_MODE 0: By rank 1: By Phase
631 23:09:51.169175 ==============================================================
632 23:09:51.169932 GAT_TRACK_EN = 1
633 23:09:51.172982 RX_GATING_MODE = 2
634 23:09:51.175868 RX_GATING_TRACK_MODE = 2
635 23:09:51.179420 SELPH_MODE = 1
636 23:09:51.182970 PICG_EARLY_EN = 1
637 23:09:51.185821 VALID_LAT_VALUE = 1
638 23:09:51.192875 ==============================================================
639 23:09:51.195749 Enter into Gating configuration >>>>
640 23:09:51.199300 Exit from Gating configuration <<<<
641 23:09:51.202507 Enter into DVFS_PRE_config >>>>>
642 23:09:51.212656 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 23:09:51.215959 Exit from DVFS_PRE_config <<<<<
644 23:09:51.219489 Enter into PICG configuration >>>>
645 23:09:51.222609 Exit from PICG configuration <<<<
646 23:09:51.225893 [RX_INPUT] configuration >>>>>
647 23:09:51.226367 [RX_INPUT] configuration <<<<<
648 23:09:51.232537 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 23:09:51.239063 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 23:09:51.242540 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 23:09:51.249371 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 23:09:51.256013 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 23:09:51.262493 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 23:09:51.266047 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 23:09:51.269322 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 23:09:51.276089 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 23:09:51.279471 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 23:09:51.282954 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 23:09:51.285566 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 23:09:51.289073 ===================================
661 23:09:51.292562 LPDDR4 DRAM CONFIGURATION
662 23:09:51.295694 ===================================
663 23:09:51.299382 EX_ROW_EN[0] = 0x0
664 23:09:51.299961 EX_ROW_EN[1] = 0x0
665 23:09:51.302842 LP4Y_EN = 0x0
666 23:09:51.303316 WORK_FSP = 0x0
667 23:09:51.305881 WL = 0x2
668 23:09:51.306354 RL = 0x2
669 23:09:51.309250 BL = 0x2
670 23:09:51.309726 RPST = 0x0
671 23:09:51.312758 RD_PRE = 0x0
672 23:09:51.313356 WR_PRE = 0x1
673 23:09:51.316509 WR_PST = 0x0
674 23:09:51.319445 DBI_WR = 0x0
675 23:09:51.320021 DBI_RD = 0x0
676 23:09:51.322526 OTF = 0x1
677 23:09:51.325513 ===================================
678 23:09:51.329198 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 23:09:51.332858 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 23:09:51.336201 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 23:09:51.338957 ===================================
682 23:09:51.342410 LPDDR4 DRAM CONFIGURATION
683 23:09:51.345626 ===================================
684 23:09:51.348854 EX_ROW_EN[0] = 0x10
685 23:09:51.349426 EX_ROW_EN[1] = 0x0
686 23:09:51.352461 LP4Y_EN = 0x0
687 23:09:51.353104 WORK_FSP = 0x0
688 23:09:51.355443 WL = 0x2
689 23:09:51.355916 RL = 0x2
690 23:09:51.359396 BL = 0x2
691 23:09:51.359974 RPST = 0x0
692 23:09:51.362005 RD_PRE = 0x0
693 23:09:51.362482 WR_PRE = 0x1
694 23:09:51.365657 WR_PST = 0x0
695 23:09:51.366243 DBI_WR = 0x0
696 23:09:51.369123 DBI_RD = 0x0
697 23:09:51.369698 OTF = 0x1
698 23:09:51.372140 ===================================
699 23:09:51.379564 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 23:09:51.383648 nWR fixed to 40
701 23:09:51.387197 [ModeRegInit_LP4] CH0 RK0
702 23:09:51.387774 [ModeRegInit_LP4] CH0 RK1
703 23:09:51.390462 [ModeRegInit_LP4] CH1 RK0
704 23:09:51.393409 [ModeRegInit_LP4] CH1 RK1
705 23:09:51.393894 match AC timing 12
706 23:09:51.400882 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 23:09:51.403541 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 23:09:51.406982 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 23:09:51.413902 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 23:09:51.417248 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 23:09:51.417844 [EMI DOE] emi_dcm 0
712 23:09:51.423903 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 23:09:51.424485 ==
714 23:09:51.427098 Dram Type= 6, Freq= 0, CH_0, rank 0
715 23:09:51.430162 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 23:09:51.430645 ==
717 23:09:51.437177 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 23:09:51.443977 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 23:09:51.451075 [CA 0] Center 37 (7~68) winsize 62
720 23:09:51.454301 [CA 1] Center 37 (7~68) winsize 62
721 23:09:51.457474 [CA 2] Center 35 (4~66) winsize 63
722 23:09:51.460979 [CA 3] Center 35 (5~66) winsize 62
723 23:09:51.464518 [CA 4] Center 34 (4~65) winsize 62
724 23:09:51.467797 [CA 5] Center 33 (3~64) winsize 62
725 23:09:51.468379
726 23:09:51.470874 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 23:09:51.471603
728 23:09:51.474272 [CATrainingPosCal] consider 1 rank data
729 23:09:51.477571 u2DelayCellTimex100 = 270/100 ps
730 23:09:51.480862 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 23:09:51.487520 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
732 23:09:51.490963 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
733 23:09:51.493834 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
734 23:09:51.497681 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
735 23:09:51.500843 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 23:09:51.501422
737 23:09:51.504134 CA PerBit enable=1, Macro0, CA PI delay=33
738 23:09:51.504615
739 23:09:51.507447 [CBTSetCACLKResult] CA Dly = 33
740 23:09:51.507934 CS Dly: 5 (0~36)
741 23:09:51.510965 ==
742 23:09:51.513993 Dram Type= 6, Freq= 0, CH_0, rank 1
743 23:09:51.517399 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 23:09:51.517980 ==
745 23:09:51.520844 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 23:09:51.527480 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 23:09:51.537390 [CA 0] Center 37 (6~68) winsize 63
748 23:09:51.540281 [CA 1] Center 37 (6~68) winsize 63
749 23:09:51.543531 [CA 2] Center 35 (4~66) winsize 63
750 23:09:51.547413 [CA 3] Center 34 (4~65) winsize 62
751 23:09:51.550410 [CA 4] Center 33 (3~64) winsize 62
752 23:09:51.553631 [CA 5] Center 33 (3~64) winsize 62
753 23:09:51.554207
754 23:09:51.557117 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 23:09:51.557642
756 23:09:51.560499 [CATrainingPosCal] consider 2 rank data
757 23:09:51.563392 u2DelayCellTimex100 = 270/100 ps
758 23:09:51.567019 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 23:09:51.570254 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 23:09:51.577189 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
761 23:09:51.580604 CA3 delay=35 (5~65),Diff = 2 PI (14 cell)
762 23:09:51.584037 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
763 23:09:51.587038 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 23:09:51.587622
765 23:09:51.591193 CA PerBit enable=1, Macro0, CA PI delay=33
766 23:09:51.591771
767 23:09:51.593363 [CBTSetCACLKResult] CA Dly = 33
768 23:09:51.593943 CS Dly: 6 (0~38)
769 23:09:51.594463
770 23:09:51.597133 ----->DramcWriteLeveling(PI) begin...
771 23:09:51.600372 ==
772 23:09:51.603979 Dram Type= 6, Freq= 0, CH_0, rank 0
773 23:09:51.607114 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 23:09:51.607728 ==
775 23:09:51.610405 Write leveling (Byte 0): 28 => 28
776 23:09:51.613751 Write leveling (Byte 1): 29 => 29
777 23:09:51.617656 DramcWriteLeveling(PI) end<-----
778 23:09:51.618289
779 23:09:51.618634 ==
780 23:09:51.621247 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:09:51.623930 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 23:09:51.624468 ==
783 23:09:51.627245 [Gating] SW mode calibration
784 23:09:51.633963 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 23:09:51.637672 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 23:09:51.643551 0 6 0 | B1->B0 | 3232 2f2f | 1 1 | (1 0) (1 0)
787 23:09:51.647162 0 6 4 | B1->B0 | 2d2d 2424 | 0 0 | (1 1) (1 1)
788 23:09:51.650561 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 23:09:51.656931 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:09:51.660886 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:09:51.664061 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:09:51.670616 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:09:51.673661 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:09:51.676875 0 7 0 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
795 23:09:51.683574 0 7 4 | B1->B0 | 3b3b 4040 | 0 0 | (0 0) (0 0)
796 23:09:51.686933 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 23:09:51.690448 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 23:09:51.697527 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 23:09:51.700500 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 23:09:51.704030 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 23:09:51.709897 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 23:09:51.713417 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
803 23:09:51.716891 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
804 23:09:51.723873 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 23:09:51.727074 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 23:09:51.730039 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 23:09:51.736794 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 23:09:51.739860 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 23:09:51.743516 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 23:09:51.749954 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 23:09:51.753505 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 23:09:51.756813 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 23:09:51.760295 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 23:09:51.766602 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 23:09:51.770062 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 23:09:51.773620 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 23:09:51.779834 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 23:09:51.783539 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
819 23:09:51.786758 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
820 23:09:51.790052 Total UI for P1: 0, mck2ui 16
821 23:09:51.793226 best dqsien dly found for B0: ( 0, 10, 0)
822 23:09:51.796657 Total UI for P1: 0, mck2ui 16
823 23:09:51.800358 best dqsien dly found for B1: ( 0, 10, 0)
824 23:09:51.803276 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
825 23:09:51.806563 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
826 23:09:51.807112
827 23:09:51.813645 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
828 23:09:51.817079 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
829 23:09:51.817665 [Gating] SW calibration Done
830 23:09:51.820130 ==
831 23:09:51.823309 Dram Type= 6, Freq= 0, CH_0, rank 0
832 23:09:51.827304 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
833 23:09:51.827896 ==
834 23:09:51.828273 RX Vref Scan: 0
835 23:09:51.828675
836 23:09:51.830942 RX Vref 0 -> 0, step: 1
837 23:09:51.831551
838 23:09:51.834214 RX Delay -130 -> 252, step: 16
839 23:09:51.838074 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
840 23:09:51.840542 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
841 23:09:51.843932 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
842 23:09:51.847202 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
843 23:09:51.854472 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
844 23:09:51.857298 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
845 23:09:51.860438 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
846 23:09:51.864030 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
847 23:09:51.867177 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
848 23:09:51.873749 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
849 23:09:51.877626 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
850 23:09:51.880273 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
851 23:09:51.884166 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
852 23:09:51.887533 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
853 23:09:51.893585 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
854 23:09:51.897063 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
855 23:09:51.897490 ==
856 23:09:51.900853 Dram Type= 6, Freq= 0, CH_0, rank 0
857 23:09:51.903950 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
858 23:09:51.904513 ==
859 23:09:51.906976 DQS Delay:
860 23:09:51.907525 DQS0 = 0, DQS1 = 0
861 23:09:51.908088 DQM Delay:
862 23:09:51.910345 DQM0 = 82, DQM1 = 74
863 23:09:51.910772 DQ Delay:
864 23:09:51.914104 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
865 23:09:51.917410 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
866 23:09:51.920402 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
867 23:09:51.923960 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
868 23:09:51.924492
869 23:09:51.924887
870 23:09:51.925210 ==
871 23:09:51.927586 Dram Type= 6, Freq= 0, CH_0, rank 0
872 23:09:51.933706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
873 23:09:51.934247 ==
874 23:09:51.934587
875 23:09:51.934893
876 23:09:51.935234 TX Vref Scan disable
877 23:09:51.937613 == TX Byte 0 ==
878 23:09:51.940753 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
879 23:09:51.944405 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
880 23:09:51.947602 == TX Byte 1 ==
881 23:09:51.950678 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
882 23:09:51.957272 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
883 23:09:51.957766 ==
884 23:09:51.960913 Dram Type= 6, Freq= 0, CH_0, rank 0
885 23:09:51.964047 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
886 23:09:51.964585 ==
887 23:09:51.976342 TX Vref=22, minBit 2, minWin=27, winSum=443
888 23:09:51.979700 TX Vref=24, minBit 0, minWin=27, winSum=447
889 23:09:51.983317 TX Vref=26, minBit 4, minWin=27, winSum=450
890 23:09:51.986357 TX Vref=28, minBit 1, minWin=28, winSum=455
891 23:09:51.989728 TX Vref=30, minBit 1, minWin=28, winSum=455
892 23:09:51.992871 TX Vref=32, minBit 0, minWin=28, winSum=453
893 23:09:51.999712 [TxChooseVref] Worse bit 1, Min win 28, Win sum 455, Final Vref 28
894 23:09:52.000248
895 23:09:52.003083 Final TX Range 1 Vref 28
896 23:09:52.003634
897 23:09:52.003980 ==
898 23:09:52.006120 Dram Type= 6, Freq= 0, CH_0, rank 0
899 23:09:52.009602 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
900 23:09:52.010034 ==
901 23:09:52.012964
902 23:09:52.013489
903 23:09:52.013871 TX Vref Scan disable
904 23:09:52.016579 == TX Byte 0 ==
905 23:09:52.019591 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
906 23:09:52.026167 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
907 23:09:52.026714 == TX Byte 1 ==
908 23:09:52.029677 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
909 23:09:52.032870 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
910 23:09:52.036308
911 23:09:52.036886 [DATLAT]
912 23:09:52.037235 Freq=800, CH0 RK0
913 23:09:52.037555
914 23:09:52.039591 DATLAT Default: 0xa
915 23:09:52.040146 0, 0xFFFF, sum = 0
916 23:09:52.042678 1, 0xFFFF, sum = 0
917 23:09:52.043233 2, 0xFFFF, sum = 0
918 23:09:52.046369 3, 0xFFFF, sum = 0
919 23:09:52.046920 4, 0xFFFF, sum = 0
920 23:09:52.049421 5, 0xFFFF, sum = 0
921 23:09:52.052907 6, 0xFFFF, sum = 0
922 23:09:52.053447 7, 0xFFFF, sum = 0
923 23:09:52.053798 8, 0x0, sum = 1
924 23:09:52.056465 9, 0x0, sum = 2
925 23:09:52.057055 10, 0x0, sum = 3
926 23:09:52.059330 11, 0x0, sum = 4
927 23:09:52.059761 best_step = 9
928 23:09:52.060098
929 23:09:52.060410 ==
930 23:09:52.063103 Dram Type= 6, Freq= 0, CH_0, rank 0
931 23:09:52.069317 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
932 23:09:52.069878 ==
933 23:09:52.070229 RX Vref Scan: 1
934 23:09:52.070559
935 23:09:52.073048 Set Vref Range= 32 -> 127
936 23:09:52.073482
937 23:09:52.075932 RX Vref 32 -> 127, step: 1
938 23:09:52.076460
939 23:09:52.079467 RX Delay -111 -> 252, step: 8
940 23:09:52.080047
941 23:09:52.082638 Set Vref, RX VrefLevel [Byte0]: 32
942 23:09:52.083110 [Byte1]: 32
943 23:09:52.087154
944 23:09:52.087627 Set Vref, RX VrefLevel [Byte0]: 33
945 23:09:52.090559 [Byte1]: 33
946 23:09:52.095138
947 23:09:52.095712 Set Vref, RX VrefLevel [Byte0]: 34
948 23:09:52.098295 [Byte1]: 34
949 23:09:52.102236
950 23:09:52.102710 Set Vref, RX VrefLevel [Byte0]: 35
951 23:09:52.106145 [Byte1]: 35
952 23:09:52.110066
953 23:09:52.110582 Set Vref, RX VrefLevel [Byte0]: 36
954 23:09:52.113446 [Byte1]: 36
955 23:09:52.117906
956 23:09:52.118485 Set Vref, RX VrefLevel [Byte0]: 37
957 23:09:52.120961 [Byte1]: 37
958 23:09:52.125360
959 23:09:52.125934 Set Vref, RX VrefLevel [Byte0]: 38
960 23:09:52.128870 [Byte1]: 38
961 23:09:52.132817
962 23:09:52.133294 Set Vref, RX VrefLevel [Byte0]: 39
963 23:09:52.136576 [Byte1]: 39
964 23:09:52.140901
965 23:09:52.141473 Set Vref, RX VrefLevel [Byte0]: 40
966 23:09:52.144169 [Byte1]: 40
967 23:09:52.148447
968 23:09:52.149156 Set Vref, RX VrefLevel [Byte0]: 41
969 23:09:52.151683 [Byte1]: 41
970 23:09:52.156056
971 23:09:52.156632 Set Vref, RX VrefLevel [Byte0]: 42
972 23:09:52.159318 [Byte1]: 42
973 23:09:52.164025
974 23:09:52.164605 Set Vref, RX VrefLevel [Byte0]: 43
975 23:09:52.167473 [Byte1]: 43
976 23:09:52.171788
977 23:09:52.172361 Set Vref, RX VrefLevel [Byte0]: 44
978 23:09:52.174523 [Byte1]: 44
979 23:09:52.179369
980 23:09:52.179952 Set Vref, RX VrefLevel [Byte0]: 45
981 23:09:52.182078 [Byte1]: 45
982 23:09:52.186882
983 23:09:52.187457 Set Vref, RX VrefLevel [Byte0]: 46
984 23:09:52.189636 [Byte1]: 46
985 23:09:52.194033
986 23:09:52.197579 Set Vref, RX VrefLevel [Byte0]: 47
987 23:09:52.198152 [Byte1]: 47
988 23:09:52.201879
989 23:09:52.202449 Set Vref, RX VrefLevel [Byte0]: 48
990 23:09:52.205263 [Byte1]: 48
991 23:09:52.209601
992 23:09:52.210180 Set Vref, RX VrefLevel [Byte0]: 49
993 23:09:52.213296 [Byte1]: 49
994 23:09:52.217344
995 23:09:52.217916 Set Vref, RX VrefLevel [Byte0]: 50
996 23:09:52.220806 [Byte1]: 50
997 23:09:52.225036
998 23:09:52.225605 Set Vref, RX VrefLevel [Byte0]: 51
999 23:09:52.228238 [Byte1]: 51
1000 23:09:52.232318
1001 23:09:52.232826 Set Vref, RX VrefLevel [Byte0]: 52
1002 23:09:52.235743 [Byte1]: 52
1003 23:09:52.239877
1004 23:09:52.240451 Set Vref, RX VrefLevel [Byte0]: 53
1005 23:09:52.243382 [Byte1]: 53
1006 23:09:52.247879
1007 23:09:52.248453 Set Vref, RX VrefLevel [Byte0]: 54
1008 23:09:52.251058 [Byte1]: 54
1009 23:09:52.255393
1010 23:09:52.255866 Set Vref, RX VrefLevel [Byte0]: 55
1011 23:09:52.258677 [Byte1]: 55
1012 23:09:52.263119
1013 23:09:52.263701 Set Vref, RX VrefLevel [Byte0]: 56
1014 23:09:52.266322 [Byte1]: 56
1015 23:09:52.270844
1016 23:09:52.271415 Set Vref, RX VrefLevel [Byte0]: 57
1017 23:09:52.274202 [Byte1]: 57
1018 23:09:52.278767
1019 23:09:52.279337 Set Vref, RX VrefLevel [Byte0]: 58
1020 23:09:52.281560 [Byte1]: 58
1021 23:09:52.286545
1022 23:09:52.287121 Set Vref, RX VrefLevel [Byte0]: 59
1023 23:09:52.289146 [Byte1]: 59
1024 23:09:52.293680
1025 23:09:52.294297 Set Vref, RX VrefLevel [Byte0]: 60
1026 23:09:52.297467 [Byte1]: 60
1027 23:09:52.301360
1028 23:09:52.301920 Set Vref, RX VrefLevel [Byte0]: 61
1029 23:09:52.304642 [Byte1]: 61
1030 23:09:52.309076
1031 23:09:52.309647 Set Vref, RX VrefLevel [Byte0]: 62
1032 23:09:52.312395 [Byte1]: 62
1033 23:09:52.316399
1034 23:09:52.316894 Set Vref, RX VrefLevel [Byte0]: 63
1035 23:09:52.319534 [Byte1]: 63
1036 23:09:52.324106
1037 23:09:52.324669 Set Vref, RX VrefLevel [Byte0]: 64
1038 23:09:52.327506 [Byte1]: 64
1039 23:09:52.331830
1040 23:09:52.332393 Set Vref, RX VrefLevel [Byte0]: 65
1041 23:09:52.335230 [Byte1]: 65
1042 23:09:52.339706
1043 23:09:52.340270 Set Vref, RX VrefLevel [Byte0]: 66
1044 23:09:52.342753 [Byte1]: 66
1045 23:09:52.347095
1046 23:09:52.347652 Set Vref, RX VrefLevel [Byte0]: 67
1047 23:09:52.350474 [Byte1]: 67
1048 23:09:52.354805
1049 23:09:52.355371 Set Vref, RX VrefLevel [Byte0]: 68
1050 23:09:52.358019 [Byte1]: 68
1051 23:09:52.362639
1052 23:09:52.363197 Set Vref, RX VrefLevel [Byte0]: 69
1053 23:09:52.365613 [Byte1]: 69
1054 23:09:52.370248
1055 23:09:52.371040 Set Vref, RX VrefLevel [Byte0]: 70
1056 23:09:52.373463 [Byte1]: 70
1057 23:09:52.377744
1058 23:09:52.378361 Set Vref, RX VrefLevel [Byte0]: 71
1059 23:09:52.381051 [Byte1]: 71
1060 23:09:52.385034
1061 23:09:52.385499 Set Vref, RX VrefLevel [Byte0]: 72
1062 23:09:52.388796 [Byte1]: 72
1063 23:09:52.392955
1064 23:09:52.393503 Set Vref, RX VrefLevel [Byte0]: 73
1065 23:09:52.396562 [Byte1]: 73
1066 23:09:52.400872
1067 23:09:52.401421 Set Vref, RX VrefLevel [Byte0]: 74
1068 23:09:52.403984 [Byte1]: 74
1069 23:09:52.408446
1070 23:09:52.409072 Final RX Vref Byte 0 = 49 to rank0
1071 23:09:52.411355 Final RX Vref Byte 1 = 48 to rank0
1072 23:09:52.415062 Final RX Vref Byte 0 = 49 to rank1
1073 23:09:52.418379 Final RX Vref Byte 1 = 48 to rank1==
1074 23:09:52.421650 Dram Type= 6, Freq= 0, CH_0, rank 0
1075 23:09:52.425346 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1076 23:09:52.428526 ==
1077 23:09:52.429122 DQS Delay:
1078 23:09:52.429488 DQS0 = 0, DQS1 = 0
1079 23:09:52.431718 DQM Delay:
1080 23:09:52.432276 DQM0 = 83, DQM1 = 73
1081 23:09:52.434990 DQ Delay:
1082 23:09:52.435544 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1083 23:09:52.438854 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1084 23:09:52.441783 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1085 23:09:52.445380 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1086 23:09:52.445939
1087 23:09:52.448978
1088 23:09:52.455591 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e3e, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1089 23:09:52.458642 CH0 RK0: MR19=606, MR18=3E3E
1090 23:09:52.465316 CH0_RK0: MR19=0x606, MR18=0x3E3E, DQSOSC=394, MR23=63, INC=95, DEC=63
1091 23:09:52.465871
1092 23:09:52.468872 ----->DramcWriteLeveling(PI) begin...
1093 23:09:52.469435 ==
1094 23:09:52.471988 Dram Type= 6, Freq= 0, CH_0, rank 1
1095 23:09:52.475486 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1096 23:09:52.476048 ==
1097 23:09:52.478564 Write leveling (Byte 0): 31 => 31
1098 23:09:52.481689 Write leveling (Byte 1): 30 => 30
1099 23:09:52.485085 DramcWriteLeveling(PI) end<-----
1100 23:09:52.485544
1101 23:09:52.485899 ==
1102 23:09:52.488463 Dram Type= 6, Freq= 0, CH_0, rank 1
1103 23:09:52.492093 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1104 23:09:52.492652 ==
1105 23:09:52.495312 [Gating] SW mode calibration
1106 23:09:52.501660 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1107 23:09:52.508547 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1108 23:09:52.511778 0 6 0 | B1->B0 | 3333 3030 | 1 1 | (1 0) (1 0)
1109 23:09:52.515316 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1110 23:09:52.522380 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1111 23:09:52.525586 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1112 23:09:52.529408 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1113 23:09:52.535563 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1114 23:09:52.538890 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1115 23:09:52.541763 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1116 23:09:52.545462 0 7 0 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 0)
1117 23:09:52.552190 0 7 4 | B1->B0 | 4040 4545 | 0 0 | (1 1) (0 0)
1118 23:09:52.555710 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1119 23:09:52.558787 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1120 23:09:52.565701 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1121 23:09:52.568549 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1122 23:09:52.571576 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1123 23:09:52.578481 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1124 23:09:52.581480 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1125 23:09:52.584768 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1126 23:09:52.592109 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 23:09:52.595213 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 23:09:52.598553 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 23:09:52.604879 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 23:09:52.608698 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 23:09:52.611464 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 23:09:52.618477 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 23:09:52.621755 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 23:09:52.625416 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 23:09:52.631837 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 23:09:52.635475 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 23:09:52.638381 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 23:09:52.645090 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 23:09:52.648286 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 23:09:52.651969 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1141 23:09:52.655063 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1142 23:09:52.658637 Total UI for P1: 0, mck2ui 16
1143 23:09:52.661886 best dqsien dly found for B0: ( 0, 10, 0)
1144 23:09:52.668561 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1145 23:09:52.671709 Total UI for P1: 0, mck2ui 16
1146 23:09:52.674986 best dqsien dly found for B1: ( 0, 10, 2)
1147 23:09:52.678665 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1148 23:09:52.681855 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1149 23:09:52.682420
1150 23:09:52.684803 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1151 23:09:52.688353 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1152 23:09:52.691790 [Gating] SW calibration Done
1153 23:09:52.692340 ==
1154 23:09:52.694843 Dram Type= 6, Freq= 0, CH_0, rank 1
1155 23:09:52.698244 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1156 23:09:52.698801 ==
1157 23:09:52.701624 RX Vref Scan: 0
1158 23:09:52.702171
1159 23:09:52.702540 RX Vref 0 -> 0, step: 1
1160 23:09:52.745633
1161 23:09:52.746194 RX Delay -130 -> 252, step: 16
1162 23:09:52.746586 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1163 23:09:52.747001 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1164 23:09:52.747859 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1165 23:09:52.748395 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1166 23:09:52.748936 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1167 23:09:52.749430 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1168 23:09:52.749907 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1169 23:09:52.750381 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1170 23:09:52.750854 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1171 23:09:52.751324 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1172 23:09:52.755317 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1173 23:09:52.759085 iDelay=222, Bit 11, Center 61 (-50 ~ 173) 224
1174 23:09:52.759621 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1175 23:09:52.762199 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
1176 23:09:52.765886 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1177 23:09:52.769296 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
1178 23:09:52.771798 ==
1179 23:09:52.772262 Dram Type= 6, Freq= 0, CH_0, rank 1
1180 23:09:52.778893 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1181 23:09:52.779689 ==
1182 23:09:52.780076 DQS Delay:
1183 23:09:52.782245 DQS0 = 0, DQS1 = 0
1184 23:09:52.782803 DQM Delay:
1185 23:09:52.785307 DQM0 = 81, DQM1 = 70
1186 23:09:52.785776 DQ Delay:
1187 23:09:52.788808 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =69
1188 23:09:52.791961 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1189 23:09:52.795776 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1190 23:09:52.798856 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
1191 23:09:52.799415
1192 23:09:52.799782
1193 23:09:52.800120 ==
1194 23:09:52.802043 Dram Type= 6, Freq= 0, CH_0, rank 1
1195 23:09:52.805344 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1196 23:09:52.805811 ==
1197 23:09:52.806174
1198 23:09:52.806510
1199 23:09:52.808822 TX Vref Scan disable
1200 23:09:52.812105 == TX Byte 0 ==
1201 23:09:52.815791 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1202 23:09:52.818626 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1203 23:09:52.821703 == TX Byte 1 ==
1204 23:09:52.825855 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1205 23:09:52.828755 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1206 23:09:52.829319 ==
1207 23:09:52.831986 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 23:09:52.835480 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1209 23:09:52.836041 ==
1210 23:09:52.849943 TX Vref=22, minBit 0, minWin=28, winSum=453
1211 23:09:52.853124 TX Vref=24, minBit 0, minWin=28, winSum=452
1212 23:09:52.856681 TX Vref=26, minBit 2, minWin=28, winSum=456
1213 23:09:52.859927 TX Vref=28, minBit 2, minWin=28, winSum=459
1214 23:09:52.862833 TX Vref=30, minBit 2, minWin=28, winSum=457
1215 23:09:52.866257 TX Vref=32, minBit 0, minWin=28, winSum=457
1216 23:09:52.873100 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 28
1217 23:09:52.873906
1218 23:09:52.876465 Final TX Range 1 Vref 28
1219 23:09:52.877081
1220 23:09:52.877455 ==
1221 23:09:52.879766 Dram Type= 6, Freq= 0, CH_0, rank 1
1222 23:09:52.882769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1223 23:09:52.883424 ==
1224 23:09:52.885865
1225 23:09:52.886390
1226 23:09:52.886765 TX Vref Scan disable
1227 23:09:52.889537 == TX Byte 0 ==
1228 23:09:52.892949 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1229 23:09:52.899675 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1230 23:09:52.900276 == TX Byte 1 ==
1231 23:09:52.902796 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1232 23:09:52.906494 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1233 23:09:52.909582
1234 23:09:52.910046 [DATLAT]
1235 23:09:52.910411 Freq=800, CH0 RK1
1236 23:09:52.910773
1237 23:09:52.912486 DATLAT Default: 0x9
1238 23:09:52.913003 0, 0xFFFF, sum = 0
1239 23:09:52.916467 1, 0xFFFF, sum = 0
1240 23:09:52.917101 2, 0xFFFF, sum = 0
1241 23:09:52.919456 3, 0xFFFF, sum = 0
1242 23:09:52.919929 4, 0xFFFF, sum = 0
1243 23:09:52.922707 5, 0xFFFF, sum = 0
1244 23:09:52.926263 6, 0xFFFF, sum = 0
1245 23:09:52.926827 7, 0xFFFF, sum = 0
1246 23:09:52.929313 8, 0x0, sum = 1
1247 23:09:52.929778 9, 0x0, sum = 2
1248 23:09:52.930146 10, 0x0, sum = 3
1249 23:09:52.932440 11, 0x0, sum = 4
1250 23:09:52.932960 best_step = 9
1251 23:09:52.933333
1252 23:09:52.933671 ==
1253 23:09:52.935859 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 23:09:52.942609 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1255 23:09:52.943026 ==
1256 23:09:52.943406 RX Vref Scan: 0
1257 23:09:52.943745
1258 23:09:52.946371 RX Vref 0 -> 0, step: 1
1259 23:09:52.946912
1260 23:09:52.948945 RX Delay -111 -> 252, step: 8
1261 23:09:52.952308 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1262 23:09:52.955515 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1263 23:09:52.962462 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1264 23:09:52.965880 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1265 23:09:52.969199 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1266 23:09:52.972369 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1267 23:09:52.975721 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1268 23:09:52.982368 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1269 23:09:52.985613 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1270 23:09:52.989095 iDelay=217, Bit 9, Center 60 (-47 ~ 168) 216
1271 23:09:52.992907 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1272 23:09:52.995848 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1273 23:09:53.001996 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1274 23:09:53.005599 iDelay=217, Bit 13, Center 80 (-31 ~ 192) 224
1275 23:09:53.008931 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1276 23:09:53.012121 iDelay=217, Bit 15, Center 80 (-31 ~ 192) 224
1277 23:09:53.012594 ==
1278 23:09:53.015477 Dram Type= 6, Freq= 0, CH_0, rank 1
1279 23:09:53.022196 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1280 23:09:53.022617 ==
1281 23:09:53.022947 DQS Delay:
1282 23:09:53.025461 DQS0 = 0, DQS1 = 0
1283 23:09:53.025878 DQM Delay:
1284 23:09:53.026209 DQM0 = 86, DQM1 = 73
1285 23:09:53.028905 DQ Delay:
1286 23:09:53.032408 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1287 23:09:53.035426 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1288 23:09:53.038754 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1289 23:09:53.042077 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
1290 23:09:53.042563
1291 23:09:53.042900
1292 23:09:53.048807 [DQSOSCAuto] RK1, (LSB)MR18= 0x4343, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1293 23:09:53.052173 CH0 RK1: MR19=606, MR18=4343
1294 23:09:53.058666 CH0_RK1: MR19=0x606, MR18=0x4343, DQSOSC=393, MR23=63, INC=95, DEC=63
1295 23:09:53.062257 [RxdqsGatingPostProcess] freq 800
1296 23:09:53.065553 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1297 23:09:53.068816 Pre-setting of DQS Precalculation
1298 23:09:53.075629 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1299 23:09:53.076093 ==
1300 23:09:53.078894 Dram Type= 6, Freq= 0, CH_1, rank 0
1301 23:09:53.082322 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1302 23:09:53.082742 ==
1303 23:09:53.088818 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1304 23:09:53.091955 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1305 23:09:53.101833 [CA 0] Center 36 (6~67) winsize 62
1306 23:09:53.105728 [CA 1] Center 37 (6~68) winsize 63
1307 23:09:53.109052 [CA 2] Center 34 (4~65) winsize 62
1308 23:09:53.112045 [CA 3] Center 34 (4~65) winsize 62
1309 23:09:53.115786 [CA 4] Center 33 (3~64) winsize 62
1310 23:09:53.119103 [CA 5] Center 33 (3~64) winsize 62
1311 23:09:53.119613
1312 23:09:53.122589 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1313 23:09:53.123097
1314 23:09:53.125841 [CATrainingPosCal] consider 1 rank data
1315 23:09:53.128608 u2DelayCellTimex100 = 270/100 ps
1316 23:09:53.131958 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1317 23:09:53.135714 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1318 23:09:53.142388 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1319 23:09:53.145284 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1320 23:09:53.148941 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1321 23:09:53.151891 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1322 23:09:53.152277
1323 23:09:53.155554 CA PerBit enable=1, Macro0, CA PI delay=33
1324 23:09:53.156066
1325 23:09:53.158606 [CBTSetCACLKResult] CA Dly = 33
1326 23:09:53.159019 CS Dly: 4 (0~35)
1327 23:09:53.162051 ==
1328 23:09:53.162504 Dram Type= 6, Freq= 0, CH_1, rank 1
1329 23:09:53.168827 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1330 23:09:53.169340 ==
1331 23:09:53.172341 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1332 23:09:53.178868 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1333 23:09:53.188374 [CA 0] Center 36 (6~67) winsize 62
1334 23:09:53.191765 [CA 1] Center 37 (6~68) winsize 63
1335 23:09:53.195108 [CA 2] Center 34 (4~65) winsize 62
1336 23:09:53.198222 [CA 3] Center 34 (4~65) winsize 62
1337 23:09:53.201676 [CA 4] Center 33 (3~64) winsize 62
1338 23:09:53.204868 [CA 5] Center 33 (3~64) winsize 62
1339 23:09:53.205375
1340 23:09:53.208263 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1341 23:09:53.208677
1342 23:09:53.211131 [CATrainingPosCal] consider 2 rank data
1343 23:09:53.215024 u2DelayCellTimex100 = 270/100 ps
1344 23:09:53.218188 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1345 23:09:53.221560 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1346 23:09:53.227710 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1347 23:09:53.230934 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1348 23:09:53.234598 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1349 23:09:53.237671 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1350 23:09:53.238088
1351 23:09:53.241214 CA PerBit enable=1, Macro0, CA PI delay=33
1352 23:09:53.241727
1353 23:09:53.244244 [CBTSetCACLKResult] CA Dly = 33
1354 23:09:53.244654 CS Dly: 4 (0~36)
1355 23:09:53.245018
1356 23:09:53.247666 ----->DramcWriteLeveling(PI) begin...
1357 23:09:53.251346 ==
1358 23:09:53.254468 Dram Type= 6, Freq= 0, CH_1, rank 0
1359 23:09:53.258031 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1360 23:09:53.258453 ==
1361 23:09:53.261065 Write leveling (Byte 0): 25 => 25
1362 23:09:53.264973 Write leveling (Byte 1): 25 => 25
1363 23:09:53.267828 DramcWriteLeveling(PI) end<-----
1364 23:09:53.268341
1365 23:09:53.268669 ==
1366 23:09:53.271117 Dram Type= 6, Freq= 0, CH_1, rank 0
1367 23:09:53.274417 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1368 23:09:53.274837 ==
1369 23:09:53.277375 [Gating] SW mode calibration
1370 23:09:53.284796 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1371 23:09:53.287626 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1372 23:09:53.294544 0 6 0 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
1373 23:09:53.297748 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1374 23:09:53.301290 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1375 23:09:53.307750 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1376 23:09:53.310889 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1377 23:09:53.314449 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1378 23:09:53.321242 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1379 23:09:53.324558 0 6 28 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
1380 23:09:53.327778 0 7 0 | B1->B0 | 2c2c 3d3d | 0 0 | (0 0) (0 0)
1381 23:09:53.334710 0 7 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1382 23:09:53.338125 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1383 23:09:53.341288 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1384 23:09:53.348124 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1385 23:09:53.351221 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1386 23:09:53.354475 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1387 23:09:53.360978 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1388 23:09:53.364134 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1389 23:09:53.367722 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1390 23:09:53.374723 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 23:09:53.377363 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 23:09:53.381254 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 23:09:53.387756 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 23:09:53.390920 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 23:09:53.394101 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 23:09:53.397623 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 23:09:53.404564 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 23:09:53.407681 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 23:09:53.410950 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 23:09:53.417847 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 23:09:53.421370 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 23:09:53.424378 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1403 23:09:53.431300 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1404 23:09:53.434469 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1405 23:09:53.437501 Total UI for P1: 0, mck2ui 16
1406 23:09:53.441023 best dqsien dly found for B0: ( 0, 9, 30)
1407 23:09:53.444700 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1408 23:09:53.450939 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1409 23:09:53.451495 Total UI for P1: 0, mck2ui 16
1410 23:09:53.457677 best dqsien dly found for B1: ( 0, 10, 2)
1411 23:09:53.460919 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1412 23:09:53.464408 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1413 23:09:53.465020
1414 23:09:53.467602 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1415 23:09:53.470940 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1416 23:09:53.474966 [Gating] SW calibration Done
1417 23:09:53.475517 ==
1418 23:09:53.477442 Dram Type= 6, Freq= 0, CH_1, rank 0
1419 23:09:53.480947 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1420 23:09:53.481407 ==
1421 23:09:53.484104 RX Vref Scan: 0
1422 23:09:53.484559
1423 23:09:53.484964 RX Vref 0 -> 0, step: 1
1424 23:09:53.485313
1425 23:09:53.487244 RX Delay -130 -> 252, step: 16
1426 23:09:53.491091 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1427 23:09:53.497999 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1428 23:09:53.501379 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1429 23:09:53.504556 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1430 23:09:53.507484 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1431 23:09:53.510727 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1432 23:09:53.517304 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1433 23:09:53.520678 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1434 23:09:53.524502 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1435 23:09:53.527464 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1436 23:09:53.531204 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1437 23:09:53.537375 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1438 23:09:53.540776 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1439 23:09:53.544275 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1440 23:09:53.547480 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1441 23:09:53.550785 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1442 23:09:53.554153 ==
1443 23:09:53.557616 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 23:09:53.560834 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1445 23:09:53.561445 ==
1446 23:09:53.561804 DQS Delay:
1447 23:09:53.564292 DQS0 = 0, DQS1 = 0
1448 23:09:53.564847 DQM Delay:
1449 23:09:53.567379 DQM0 = 80, DQM1 = 74
1450 23:09:53.567793 DQ Delay:
1451 23:09:53.570799 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1452 23:09:53.574098 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1453 23:09:53.577157 DQ8 =53, DQ9 =69, DQ10 =77, DQ11 =69
1454 23:09:53.580636 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =85
1455 23:09:53.581199
1456 23:09:53.581535
1457 23:09:53.581841 ==
1458 23:09:53.583951 Dram Type= 6, Freq= 0, CH_1, rank 0
1459 23:09:53.587485 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1460 23:09:53.588004 ==
1461 23:09:53.588337
1462 23:09:53.588641
1463 23:09:53.590456 TX Vref Scan disable
1464 23:09:53.593989 == TX Byte 0 ==
1465 23:09:53.597468 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1466 23:09:53.600999 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1467 23:09:53.604011 == TX Byte 1 ==
1468 23:09:53.607433 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1469 23:09:53.610870 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1470 23:09:53.611385 ==
1471 23:09:53.614068 Dram Type= 6, Freq= 0, CH_1, rank 0
1472 23:09:53.617517 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1473 23:09:53.620660 ==
1474 23:09:53.631611 TX Vref=22, minBit 3, minWin=27, winSum=445
1475 23:09:53.634971 TX Vref=24, minBit 3, minWin=27, winSum=446
1476 23:09:53.638453 TX Vref=26, minBit 3, minWin=27, winSum=451
1477 23:09:53.641792 TX Vref=28, minBit 3, minWin=27, winSum=455
1478 23:09:53.644952 TX Vref=30, minBit 0, minWin=28, winSum=456
1479 23:09:53.648826 TX Vref=32, minBit 0, minWin=28, winSum=455
1480 23:09:53.655244 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
1481 23:09:53.655761
1482 23:09:53.658093 Final TX Range 1 Vref 30
1483 23:09:53.658512
1484 23:09:53.658839 ==
1485 23:09:53.661781 Dram Type= 6, Freq= 0, CH_1, rank 0
1486 23:09:53.665340 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1487 23:09:53.665856 ==
1488 23:09:53.666189
1489 23:09:53.668191
1490 23:09:53.668600 TX Vref Scan disable
1491 23:09:53.671490 == TX Byte 0 ==
1492 23:09:53.675319 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1493 23:09:53.678111 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1494 23:09:53.681984 == TX Byte 1 ==
1495 23:09:53.685547 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1496 23:09:53.688509 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1497 23:09:53.689075
1498 23:09:53.691833 [DATLAT]
1499 23:09:53.692249 Freq=800, CH1 RK0
1500 23:09:53.692574
1501 23:09:53.695522 DATLAT Default: 0xa
1502 23:09:53.696057 0, 0xFFFF, sum = 0
1503 23:09:53.698344 1, 0xFFFF, sum = 0
1504 23:09:53.698865 2, 0xFFFF, sum = 0
1505 23:09:53.702080 3, 0xFFFF, sum = 0
1506 23:09:53.702611 4, 0xFFFF, sum = 0
1507 23:09:53.705535 5, 0xFFFF, sum = 0
1508 23:09:53.705955 6, 0xFFFF, sum = 0
1509 23:09:53.708114 7, 0xFFFF, sum = 0
1510 23:09:53.708535 8, 0x0, sum = 1
1511 23:09:53.712176 9, 0x0, sum = 2
1512 23:09:53.712820 10, 0x0, sum = 3
1513 23:09:53.715276 11, 0x0, sum = 4
1514 23:09:53.715789 best_step = 9
1515 23:09:53.716113
1516 23:09:53.716416 ==
1517 23:09:53.718432 Dram Type= 6, Freq= 0, CH_1, rank 0
1518 23:09:53.721973 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1519 23:09:53.725260 ==
1520 23:09:53.725783 RX Vref Scan: 1
1521 23:09:53.726117
1522 23:09:53.728436 Set Vref Range= 32 -> 127
1523 23:09:53.728893
1524 23:09:53.732131 RX Vref 32 -> 127, step: 1
1525 23:09:53.732641
1526 23:09:53.733042 RX Delay -111 -> 252, step: 8
1527 23:09:53.733356
1528 23:09:53.735031 Set Vref, RX VrefLevel [Byte0]: 32
1529 23:09:53.738707 [Byte1]: 32
1530 23:09:53.742743
1531 23:09:53.743251 Set Vref, RX VrefLevel [Byte0]: 33
1532 23:09:53.745900 [Byte1]: 33
1533 23:09:53.750155
1534 23:09:53.750668 Set Vref, RX VrefLevel [Byte0]: 34
1535 23:09:53.753527 [Byte1]: 34
1536 23:09:53.757870
1537 23:09:53.758384 Set Vref, RX VrefLevel [Byte0]: 35
1538 23:09:53.760812 [Byte1]: 35
1539 23:09:53.765641
1540 23:09:53.766154 Set Vref, RX VrefLevel [Byte0]: 36
1541 23:09:53.768998 [Byte1]: 36
1542 23:09:53.772919
1543 23:09:53.773425 Set Vref, RX VrefLevel [Byte0]: 37
1544 23:09:53.776357 [Byte1]: 37
1545 23:09:53.780853
1546 23:09:53.781355 Set Vref, RX VrefLevel [Byte0]: 38
1547 23:09:53.784255 [Byte1]: 38
1548 23:09:53.788402
1549 23:09:53.788964 Set Vref, RX VrefLevel [Byte0]: 39
1550 23:09:53.791534 [Byte1]: 39
1551 23:09:53.796313
1552 23:09:53.796864 Set Vref, RX VrefLevel [Byte0]: 40
1553 23:09:53.799375 [Byte1]: 40
1554 23:09:53.803683
1555 23:09:53.804192 Set Vref, RX VrefLevel [Byte0]: 41
1556 23:09:53.806645 [Byte1]: 41
1557 23:09:53.811446
1558 23:09:53.811961 Set Vref, RX VrefLevel [Byte0]: 42
1559 23:09:53.814581 [Byte1]: 42
1560 23:09:53.818980
1561 23:09:53.819488 Set Vref, RX VrefLevel [Byte0]: 43
1562 23:09:53.822501 [Byte1]: 43
1563 23:09:53.826497
1564 23:09:53.827004 Set Vref, RX VrefLevel [Byte0]: 44
1565 23:09:53.829980 [Byte1]: 44
1566 23:09:53.834183
1567 23:09:53.834692 Set Vref, RX VrefLevel [Byte0]: 45
1568 23:09:53.837368 [Byte1]: 45
1569 23:09:53.842383
1570 23:09:53.842892 Set Vref, RX VrefLevel [Byte0]: 46
1571 23:09:53.845126 [Byte1]: 46
1572 23:09:53.849600
1573 23:09:53.850108 Set Vref, RX VrefLevel [Byte0]: 47
1574 23:09:53.853188 [Byte1]: 47
1575 23:09:53.857279
1576 23:09:53.857793 Set Vref, RX VrefLevel [Byte0]: 48
1577 23:09:53.860461 [Byte1]: 48
1578 23:09:53.864848
1579 23:09:53.865356 Set Vref, RX VrefLevel [Byte0]: 49
1580 23:09:53.868009 [Byte1]: 49
1581 23:09:53.872658
1582 23:09:53.873206 Set Vref, RX VrefLevel [Byte0]: 50
1583 23:09:53.875738 [Byte1]: 50
1584 23:09:53.879998
1585 23:09:53.880411 Set Vref, RX VrefLevel [Byte0]: 51
1586 23:09:53.883355 [Byte1]: 51
1587 23:09:53.888022
1588 23:09:53.888533 Set Vref, RX VrefLevel [Byte0]: 52
1589 23:09:53.890800 [Byte1]: 52
1590 23:09:53.895657
1591 23:09:53.896166 Set Vref, RX VrefLevel [Byte0]: 53
1592 23:09:53.898920 [Byte1]: 53
1593 23:09:53.902873
1594 23:09:53.903301 Set Vref, RX VrefLevel [Byte0]: 54
1595 23:09:53.906528 [Byte1]: 54
1596 23:09:53.910465
1597 23:09:53.910881 Set Vref, RX VrefLevel [Byte0]: 55
1598 23:09:53.913813 [Byte1]: 55
1599 23:09:53.918411
1600 23:09:53.918918 Set Vref, RX VrefLevel [Byte0]: 56
1601 23:09:53.921364 [Byte1]: 56
1602 23:09:53.926042
1603 23:09:53.926556 Set Vref, RX VrefLevel [Byte0]: 57
1604 23:09:53.928921 [Byte1]: 57
1605 23:09:53.933549
1606 23:09:53.933962 Set Vref, RX VrefLevel [Byte0]: 58
1607 23:09:53.936620 [Byte1]: 58
1608 23:09:53.941546
1609 23:09:53.942055 Set Vref, RX VrefLevel [Byte0]: 59
1610 23:09:53.944624 [Byte1]: 59
1611 23:09:53.949461
1612 23:09:53.949970 Set Vref, RX VrefLevel [Byte0]: 60
1613 23:09:53.952417 [Byte1]: 60
1614 23:09:53.956690
1615 23:09:53.957246 Set Vref, RX VrefLevel [Byte0]: 61
1616 23:09:53.960252 [Byte1]: 61
1617 23:09:53.964504
1618 23:09:53.965055 Set Vref, RX VrefLevel [Byte0]: 62
1619 23:09:53.967552 [Byte1]: 62
1620 23:09:53.971873
1621 23:09:53.972288 Set Vref, RX VrefLevel [Byte0]: 63
1622 23:09:53.975585 [Byte1]: 63
1623 23:09:53.979476
1624 23:09:53.979892 Set Vref, RX VrefLevel [Byte0]: 64
1625 23:09:53.982969 [Byte1]: 64
1626 23:09:53.987290
1627 23:09:53.987976 Set Vref, RX VrefLevel [Byte0]: 65
1628 23:09:53.990533 [Byte1]: 65
1629 23:09:53.994972
1630 23:09:53.995480 Set Vref, RX VrefLevel [Byte0]: 66
1631 23:09:53.998087 [Byte1]: 66
1632 23:09:54.002518
1633 23:09:54.003029 Set Vref, RX VrefLevel [Byte0]: 67
1634 23:09:54.005566 [Byte1]: 67
1635 23:09:54.010064
1636 23:09:54.010570 Set Vref, RX VrefLevel [Byte0]: 68
1637 23:09:54.013282 [Byte1]: 68
1638 23:09:54.017816
1639 23:09:54.018343 Set Vref, RX VrefLevel [Byte0]: 69
1640 23:09:54.021097 [Byte1]: 69
1641 23:09:54.025455
1642 23:09:54.025966 Set Vref, RX VrefLevel [Byte0]: 70
1643 23:09:54.028827 [Byte1]: 70
1644 23:09:54.032887
1645 23:09:54.033394 Set Vref, RX VrefLevel [Byte0]: 71
1646 23:09:54.036117 [Byte1]: 71
1647 23:09:54.040748
1648 23:09:54.041258 Set Vref, RX VrefLevel [Byte0]: 72
1649 23:09:54.044129 [Byte1]: 72
1650 23:09:54.048176
1651 23:09:54.048683 Set Vref, RX VrefLevel [Byte0]: 73
1652 23:09:54.051765 [Byte1]: 73
1653 23:09:54.056372
1654 23:09:54.056930 Set Vref, RX VrefLevel [Byte0]: 74
1655 23:09:54.059398 [Byte1]: 74
1656 23:09:54.063842
1657 23:09:54.064350 Set Vref, RX VrefLevel [Byte0]: 75
1658 23:09:54.067354 [Byte1]: 75
1659 23:09:54.071242
1660 23:09:54.071656 Set Vref, RX VrefLevel [Byte0]: 76
1661 23:09:54.074634 [Byte1]: 76
1662 23:09:54.078955
1663 23:09:54.079465 Set Vref, RX VrefLevel [Byte0]: 77
1664 23:09:54.082569 [Byte1]: 77
1665 23:09:54.086640
1666 23:09:54.087055 Set Vref, RX VrefLevel [Byte0]: 78
1667 23:09:54.089752 [Byte1]: 78
1668 23:09:54.094090
1669 23:09:54.094605 Final RX Vref Byte 0 = 60 to rank0
1670 23:09:54.097508 Final RX Vref Byte 1 = 56 to rank0
1671 23:09:54.100901 Final RX Vref Byte 0 = 60 to rank1
1672 23:09:54.104030 Final RX Vref Byte 1 = 56 to rank1==
1673 23:09:54.107618 Dram Type= 6, Freq= 0, CH_1, rank 0
1674 23:09:54.114081 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1675 23:09:54.114600 ==
1676 23:09:54.114939 DQS Delay:
1677 23:09:54.115271 DQS0 = 0, DQS1 = 0
1678 23:09:54.117407 DQM Delay:
1679 23:09:54.117824 DQM0 = 82, DQM1 = 74
1680 23:09:54.120839 DQ Delay:
1681 23:09:54.124203 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1682 23:09:54.127812 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =80
1683 23:09:54.128366 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1684 23:09:54.134621 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1685 23:09:54.135175
1686 23:09:54.135539
1687 23:09:54.140452 [DQSOSCAuto] RK0, (LSB)MR18= 0x5353, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1688 23:09:54.144089 CH1 RK0: MR19=606, MR18=5353
1689 23:09:54.150364 CH1_RK0: MR19=0x606, MR18=0x5353, DQSOSC=389, MR23=63, INC=97, DEC=65
1690 23:09:54.150905
1691 23:09:54.154211 ----->DramcWriteLeveling(PI) begin...
1692 23:09:54.154771 ==
1693 23:09:54.157622 Dram Type= 6, Freq= 0, CH_1, rank 1
1694 23:09:54.160826 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1695 23:09:54.161381 ==
1696 23:09:54.163827 Write leveling (Byte 0): 26 => 26
1697 23:09:54.167196 Write leveling (Byte 1): 25 => 25
1698 23:09:54.171006 DramcWriteLeveling(PI) end<-----
1699 23:09:54.171566
1700 23:09:54.171928 ==
1701 23:09:54.173973 Dram Type= 6, Freq= 0, CH_1, rank 1
1702 23:09:54.177554 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1703 23:09:54.178101 ==
1704 23:09:54.180406 [Gating] SW mode calibration
1705 23:09:54.187049 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1706 23:09:54.193937 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1707 23:09:54.197201 0 6 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (1 0)
1708 23:09:54.200803 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1709 23:09:54.206915 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1710 23:09:54.210595 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1711 23:09:54.213677 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1712 23:09:54.220910 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1713 23:09:54.223960 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1714 23:09:54.227147 0 6 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1715 23:09:54.233865 0 7 0 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
1716 23:09:54.236802 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1717 23:09:54.239996 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1718 23:09:54.246814 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1719 23:09:54.250123 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1720 23:09:54.253492 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1721 23:09:54.260502 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1722 23:09:54.263269 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1723 23:09:54.267217 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1724 23:09:54.273851 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1725 23:09:54.277382 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 23:09:54.280360 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 23:09:54.287095 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 23:09:54.290255 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1729 23:09:54.293527 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1730 23:09:54.300221 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1731 23:09:54.304100 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1732 23:09:54.306802 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1733 23:09:54.313563 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1734 23:09:54.316675 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1735 23:09:54.319796 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1736 23:09:54.323543 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1737 23:09:54.330062 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1738 23:09:54.333357 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1739 23:09:54.336755 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1740 23:09:54.339987 Total UI for P1: 0, mck2ui 16
1741 23:09:54.343365 best dqsien dly found for B0: ( 0, 9, 28)
1742 23:09:54.347088 Total UI for P1: 0, mck2ui 16
1743 23:09:54.349914 best dqsien dly found for B1: ( 0, 9, 30)
1744 23:09:54.353312 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1745 23:09:54.356807 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1746 23:09:54.357363
1747 23:09:54.363247 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1748 23:09:54.367259 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1749 23:09:54.370058 [Gating] SW calibration Done
1750 23:09:54.370609 ==
1751 23:09:54.373458 Dram Type= 6, Freq= 0, CH_1, rank 1
1752 23:09:54.376831 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1753 23:09:54.377392 ==
1754 23:09:54.377757 RX Vref Scan: 0
1755 23:09:54.378096
1756 23:09:54.380116 RX Vref 0 -> 0, step: 1
1757 23:09:54.380668
1758 23:09:54.383326 RX Delay -130 -> 252, step: 16
1759 23:09:54.386430 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1760 23:09:54.389689 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1761 23:09:54.396454 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1762 23:09:54.400009 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1763 23:09:54.403327 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1764 23:09:54.406557 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1765 23:09:54.409771 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1766 23:09:54.416676 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1767 23:09:54.419787 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1768 23:09:54.423392 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1769 23:09:54.426810 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1770 23:09:54.429874 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1771 23:09:54.436557 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1772 23:09:54.439970 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1773 23:09:54.443652 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1774 23:09:54.446482 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1775 23:09:54.446944 ==
1776 23:09:54.450212 Dram Type= 6, Freq= 0, CH_1, rank 1
1777 23:09:54.456360 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1778 23:09:54.456866 ==
1779 23:09:54.457241 DQS Delay:
1780 23:09:54.459782 DQS0 = 0, DQS1 = 0
1781 23:09:54.460425 DQM Delay:
1782 23:09:54.460855 DQM0 = 85, DQM1 = 73
1783 23:09:54.463308 DQ Delay:
1784 23:09:54.466556 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1785 23:09:54.470050 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1786 23:09:54.473008 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1787 23:09:54.476481 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1788 23:09:54.477068
1789 23:09:54.477438
1790 23:09:54.477774 ==
1791 23:09:54.479747 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 23:09:54.483171 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1793 23:09:54.483637 ==
1794 23:09:54.483998
1795 23:09:54.484332
1796 23:09:54.486440 TX Vref Scan disable
1797 23:09:54.486901 == TX Byte 0 ==
1798 23:09:54.492895 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1799 23:09:54.496347 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1800 23:09:54.496869 == TX Byte 1 ==
1801 23:09:54.503245 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1802 23:09:54.506458 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1803 23:09:54.507015 ==
1804 23:09:54.510199 Dram Type= 6, Freq= 0, CH_1, rank 1
1805 23:09:54.512924 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1806 23:09:54.513446 ==
1807 23:09:54.527207 TX Vref=22, minBit 0, minWin=27, winSum=448
1808 23:09:54.530415 TX Vref=24, minBit 0, minWin=27, winSum=449
1809 23:09:54.534359 TX Vref=26, minBit 0, minWin=28, winSum=455
1810 23:09:54.537052 TX Vref=28, minBit 9, minWin=27, winSum=453
1811 23:09:54.540636 TX Vref=30, minBit 0, minWin=28, winSum=457
1812 23:09:54.544116 TX Vref=32, minBit 9, minWin=27, winSum=453
1813 23:09:54.550432 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
1814 23:09:54.551016
1815 23:09:54.553538 Final TX Range 1 Vref 30
1816 23:09:54.554001
1817 23:09:54.554380 ==
1818 23:09:54.557167 Dram Type= 6, Freq= 0, CH_1, rank 1
1819 23:09:54.560395 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1820 23:09:54.561009 ==
1821 23:09:54.561385
1822 23:09:54.563434
1823 23:09:54.563945 TX Vref Scan disable
1824 23:09:54.567081 == TX Byte 0 ==
1825 23:09:54.570431 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1826 23:09:54.577031 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1827 23:09:54.577573 == TX Byte 1 ==
1828 23:09:54.580339 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1829 23:09:54.583852 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1830 23:09:54.586944
1831 23:09:54.587400 [DATLAT]
1832 23:09:54.587756 Freq=800, CH1 RK1
1833 23:09:54.588094
1834 23:09:54.590327 DATLAT Default: 0x9
1835 23:09:54.590785 0, 0xFFFF, sum = 0
1836 23:09:54.593427 1, 0xFFFF, sum = 0
1837 23:09:54.593891 2, 0xFFFF, sum = 0
1838 23:09:54.596903 3, 0xFFFF, sum = 0
1839 23:09:54.597371 4, 0xFFFF, sum = 0
1840 23:09:54.600582 5, 0xFFFF, sum = 0
1841 23:09:54.604039 6, 0xFFFF, sum = 0
1842 23:09:54.604602 7, 0xFFFF, sum = 0
1843 23:09:54.605053 8, 0x0, sum = 1
1844 23:09:54.607688 9, 0x0, sum = 2
1845 23:09:54.608246 10, 0x0, sum = 3
1846 23:09:54.610228 11, 0x0, sum = 4
1847 23:09:54.610696 best_step = 9
1848 23:09:54.611050
1849 23:09:54.611388 ==
1850 23:09:54.613421 Dram Type= 6, Freq= 0, CH_1, rank 1
1851 23:09:54.621115 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1852 23:09:54.621671 ==
1853 23:09:54.622036 RX Vref Scan: 0
1854 23:09:54.622372
1855 23:09:54.623380 RX Vref 0 -> 0, step: 1
1856 23:09:54.623844
1857 23:09:54.627237 RX Delay -111 -> 252, step: 8
1858 23:09:54.630574 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1859 23:09:54.633881 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
1860 23:09:54.640126 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1861 23:09:54.644010 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1862 23:09:54.646794 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1863 23:09:54.650197 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
1864 23:09:54.653441 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1865 23:09:54.660163 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1866 23:09:54.663590 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1867 23:09:54.667095 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
1868 23:09:54.670503 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1869 23:09:54.673725 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1870 23:09:54.680652 iDelay=209, Bit 12, Center 88 (-31 ~ 208) 240
1871 23:09:54.683943 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1872 23:09:54.687178 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1873 23:09:54.690203 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1874 23:09:54.690664 ==
1875 23:09:54.693270 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 23:09:54.700113 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1877 23:09:54.700665 ==
1878 23:09:54.701147 DQS Delay:
1879 23:09:54.701497 DQS0 = 0, DQS1 = 0
1880 23:09:54.703215 DQM Delay:
1881 23:09:54.703672 DQM0 = 83, DQM1 = 75
1882 23:09:54.706819 DQ Delay:
1883 23:09:54.709953 DQ0 =84, DQ1 =80, DQ2 =76, DQ3 =80
1884 23:09:54.710412 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =80
1885 23:09:54.713539 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1886 23:09:54.716703 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =84
1887 23:09:54.720550
1888 23:09:54.721193
1889 23:09:54.727011 [DQSOSCAuto] RK1, (LSB)MR18= 0x3838, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1890 23:09:54.730273 CH1 RK1: MR19=606, MR18=3838
1891 23:09:54.737100 CH1_RK1: MR19=0x606, MR18=0x3838, DQSOSC=395, MR23=63, INC=94, DEC=63
1892 23:09:54.740338 [RxdqsGatingPostProcess] freq 800
1893 23:09:54.743694 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1894 23:09:54.747078 Pre-setting of DQS Precalculation
1895 23:09:54.750069 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1896 23:09:54.760306 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1897 23:09:54.767169 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1898 23:09:54.767745
1899 23:09:54.768239
1900 23:09:54.770477 [Calibration Summary] 1600 Mbps
1901 23:09:54.771050 CH 0, Rank 0
1902 23:09:54.773463 SW Impedance : PASS
1903 23:09:54.774043 DUTY Scan : NO K
1904 23:09:54.776579 ZQ Calibration : PASS
1905 23:09:54.780465 Jitter Meter : NO K
1906 23:09:54.781096 CBT Training : PASS
1907 23:09:54.783191 Write leveling : PASS
1908 23:09:54.786657 RX DQS gating : PASS
1909 23:09:54.787235 RX DQ/DQS(RDDQC) : PASS
1910 23:09:54.789914 TX DQ/DQS : PASS
1911 23:09:54.793175 RX DATLAT : PASS
1912 23:09:54.793654 RX DQ/DQS(Engine): PASS
1913 23:09:54.796586 TX OE : NO K
1914 23:09:54.797106 All Pass.
1915 23:09:54.797585
1916 23:09:54.799935 CH 0, Rank 1
1917 23:09:54.800410 SW Impedance : PASS
1918 23:09:54.803127 DUTY Scan : NO K
1919 23:09:54.806431 ZQ Calibration : PASS
1920 23:09:54.806907 Jitter Meter : NO K
1921 23:09:54.809924 CBT Training : PASS
1922 23:09:54.810406 Write leveling : PASS
1923 23:09:54.813271 RX DQS gating : PASS
1924 23:09:54.816758 RX DQ/DQS(RDDQC) : PASS
1925 23:09:54.817221 TX DQ/DQS : PASS
1926 23:09:54.820143 RX DATLAT : PASS
1927 23:09:54.823497 RX DQ/DQS(Engine): PASS
1928 23:09:54.824009 TX OE : NO K
1929 23:09:54.826681 All Pass.
1930 23:09:54.827191
1931 23:09:54.827520 CH 1, Rank 0
1932 23:09:54.830152 SW Impedance : PASS
1933 23:09:54.830683 DUTY Scan : NO K
1934 23:09:54.833272 ZQ Calibration : PASS
1935 23:09:54.836574 Jitter Meter : NO K
1936 23:09:54.837024 CBT Training : PASS
1937 23:09:54.839622 Write leveling : PASS
1938 23:09:54.843766 RX DQS gating : PASS
1939 23:09:54.844279 RX DQ/DQS(RDDQC) : PASS
1940 23:09:54.846427 TX DQ/DQS : PASS
1941 23:09:54.850504 RX DATLAT : PASS
1942 23:09:54.851015 RX DQ/DQS(Engine): PASS
1943 23:09:54.853302 TX OE : NO K
1944 23:09:54.853849 All Pass.
1945 23:09:54.854186
1946 23:09:54.856869 CH 1, Rank 1
1947 23:09:54.857376 SW Impedance : PASS
1948 23:09:54.860186 DUTY Scan : NO K
1949 23:09:54.860692 ZQ Calibration : PASS
1950 23:09:54.863038 Jitter Meter : NO K
1951 23:09:54.866813 CBT Training : PASS
1952 23:09:54.867323 Write leveling : PASS
1953 23:09:54.869949 RX DQS gating : PASS
1954 23:09:54.873578 RX DQ/DQS(RDDQC) : PASS
1955 23:09:54.874085 TX DQ/DQS : PASS
1956 23:09:54.877120 RX DATLAT : PASS
1957 23:09:54.880481 RX DQ/DQS(Engine): PASS
1958 23:09:54.881042 TX OE : NO K
1959 23:09:54.883368 All Pass.
1960 23:09:54.883779
1961 23:09:54.884100 DramC Write-DBI off
1962 23:09:54.886967 PER_BANK_REFRESH: Hybrid Mode
1963 23:09:54.887483 TX_TRACKING: ON
1964 23:09:54.890083 [GetDramInforAfterCalByMRR] Vendor 6.
1965 23:09:54.896675 [GetDramInforAfterCalByMRR] Revision 606.
1966 23:09:54.899767 [GetDramInforAfterCalByMRR] Revision 2 0.
1967 23:09:54.900285 MR0 0x3939
1968 23:09:54.900613 MR8 0x1111
1969 23:09:54.903712 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1970 23:09:54.904128
1971 23:09:54.906950 MR0 0x3939
1972 23:09:54.907461 MR8 0x1111
1973 23:09:54.910304 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1974 23:09:54.910818
1975 23:09:54.920270 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1976 23:09:54.923343 [FAST_K] Save calibration result to emmc
1977 23:09:54.927095 [FAST_K] Save calibration result to emmc
1978 23:09:54.930171 dram_init: config_dvfs: 1
1979 23:09:54.933419 dramc_set_vcore_voltage set vcore to 662500
1980 23:09:54.936605 Read voltage for 1200, 2
1981 23:09:54.937054 Vio18 = 0
1982 23:09:54.937382 Vcore = 662500
1983 23:09:54.940457 Vdram = 0
1984 23:09:54.941061 Vddq = 0
1985 23:09:54.941404 Vmddr = 0
1986 23:09:54.946703 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1987 23:09:54.949978 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1988 23:09:54.953415 MEM_TYPE=3, freq_sel=15
1989 23:09:54.956743 sv_algorithm_assistance_LP4_1600
1990 23:09:54.960186 ============ PULL DRAM RESETB DOWN ============
1991 23:09:54.963147 ========== PULL DRAM RESETB DOWN end =========
1992 23:09:54.970040 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1993 23:09:54.973435 ===================================
1994 23:09:54.973947 LPDDR4 DRAM CONFIGURATION
1995 23:09:54.976974 ===================================
1996 23:09:54.980249 EX_ROW_EN[0] = 0x0
1997 23:09:54.983532 EX_ROW_EN[1] = 0x0
1998 23:09:54.984041 LP4Y_EN = 0x0
1999 23:09:54.986302 WORK_FSP = 0x0
2000 23:09:54.986715 WL = 0x4
2001 23:09:54.989827 RL = 0x4
2002 23:09:54.990239 BL = 0x2
2003 23:09:54.993221 RPST = 0x0
2004 23:09:54.993634 RD_PRE = 0x0
2005 23:09:54.996768 WR_PRE = 0x1
2006 23:09:54.997313 WR_PST = 0x0
2007 23:09:54.999873 DBI_WR = 0x0
2008 23:09:55.000284 DBI_RD = 0x0
2009 23:09:55.003605 OTF = 0x1
2010 23:09:55.006528 ===================================
2011 23:09:55.010385 ===================================
2012 23:09:55.010897 ANA top config
2013 23:09:55.013011 ===================================
2014 23:09:55.016311 DLL_ASYNC_EN = 0
2015 23:09:55.020095 ALL_SLAVE_EN = 0
2016 23:09:55.020609 NEW_RANK_MODE = 1
2017 23:09:55.023613 DLL_IDLE_MODE = 1
2018 23:09:55.026548 LP45_APHY_COMB_EN = 1
2019 23:09:55.030333 TX_ODT_DIS = 1
2020 23:09:55.033171 NEW_8X_MODE = 1
2021 23:09:55.036568 ===================================
2022 23:09:55.039907 ===================================
2023 23:09:55.040326 data_rate = 2400
2024 23:09:55.043487 CKR = 1
2025 23:09:55.046387 DQ_P2S_RATIO = 8
2026 23:09:55.049994 ===================================
2027 23:09:55.053406 CA_P2S_RATIO = 8
2028 23:09:55.056972 DQ_CA_OPEN = 0
2029 23:09:55.060227 DQ_SEMI_OPEN = 0
2030 23:09:55.060777 CA_SEMI_OPEN = 0
2031 23:09:55.063025 CA_FULL_RATE = 0
2032 23:09:55.066282 DQ_CKDIV4_EN = 0
2033 23:09:55.069849 CA_CKDIV4_EN = 0
2034 23:09:55.072949 CA_PREDIV_EN = 0
2035 23:09:55.076476 PH8_DLY = 17
2036 23:09:55.077051 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2037 23:09:55.079925 DQ_AAMCK_DIV = 4
2038 23:09:55.083472 CA_AAMCK_DIV = 4
2039 23:09:55.086141 CA_ADMCK_DIV = 4
2040 23:09:55.090033 DQ_TRACK_CA_EN = 0
2041 23:09:55.093275 CA_PICK = 1200
2042 23:09:55.096558 CA_MCKIO = 1200
2043 23:09:55.097147 MCKIO_SEMI = 0
2044 23:09:55.099498 PLL_FREQ = 2366
2045 23:09:55.102903 DQ_UI_PI_RATIO = 32
2046 23:09:55.106802 CA_UI_PI_RATIO = 0
2047 23:09:55.109875 ===================================
2048 23:09:55.112681 ===================================
2049 23:09:55.116146 memory_type:LPDDR4
2050 23:09:55.116562 GP_NUM : 10
2051 23:09:55.119943 SRAM_EN : 1
2052 23:09:55.120448 MD32_EN : 0
2053 23:09:55.123010 ===================================
2054 23:09:55.126379 [ANA_INIT] >>>>>>>>>>>>>>
2055 23:09:55.129663 <<<<<< [CONFIGURE PHASE]: ANA_TX
2056 23:09:55.133137 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2057 23:09:55.136175 ===================================
2058 23:09:55.139574 data_rate = 2400,PCW = 0X5b00
2059 23:09:55.143255 ===================================
2060 23:09:55.146029 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2061 23:09:55.153084 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2062 23:09:55.156138 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2063 23:09:55.162729 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2064 23:09:55.166590 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2065 23:09:55.169257 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2066 23:09:55.169677 [ANA_INIT] flow start
2067 23:09:55.172694 [ANA_INIT] PLL >>>>>>>>
2068 23:09:55.176213 [ANA_INIT] PLL <<<<<<<<
2069 23:09:55.176784 [ANA_INIT] MIDPI >>>>>>>>
2070 23:09:55.179514 [ANA_INIT] MIDPI <<<<<<<<
2071 23:09:55.182937 [ANA_INIT] DLL >>>>>>>>
2072 23:09:55.183478 [ANA_INIT] DLL <<<<<<<<
2073 23:09:55.186163 [ANA_INIT] flow end
2074 23:09:55.189315 ============ LP4 DIFF to SE enter ============
2075 23:09:55.192800 ============ LP4 DIFF to SE exit ============
2076 23:09:55.196217 [ANA_INIT] <<<<<<<<<<<<<
2077 23:09:55.199318 [Flow] Enable top DCM control >>>>>
2078 23:09:55.203042 [Flow] Enable top DCM control <<<<<
2079 23:09:55.206144 Enable DLL master slave shuffle
2080 23:09:55.212914 ==============================================================
2081 23:09:55.213464 Gating Mode config
2082 23:09:55.219755 ==============================================================
2083 23:09:55.220311 Config description:
2084 23:09:55.229784 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2085 23:09:55.236119 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2086 23:09:55.243054 SELPH_MODE 0: By rank 1: By Phase
2087 23:09:55.245992 ==============================================================
2088 23:09:55.249542 GAT_TRACK_EN = 1
2089 23:09:55.253089 RX_GATING_MODE = 2
2090 23:09:55.256357 RX_GATING_TRACK_MODE = 2
2091 23:09:55.259340 SELPH_MODE = 1
2092 23:09:55.262984 PICG_EARLY_EN = 1
2093 23:09:55.266351 VALID_LAT_VALUE = 1
2094 23:09:55.270146 ==============================================================
2095 23:09:55.272678 Enter into Gating configuration >>>>
2096 23:09:55.276447 Exit from Gating configuration <<<<
2097 23:09:55.279811 Enter into DVFS_PRE_config >>>>>
2098 23:09:55.293412 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2099 23:09:55.296448 Exit from DVFS_PRE_config <<<<<
2100 23:09:55.299471 Enter into PICG configuration >>>>
2101 23:09:55.303087 Exit from PICG configuration <<<<
2102 23:09:55.303502 [RX_INPUT] configuration >>>>>
2103 23:09:55.306577 [RX_INPUT] configuration <<<<<
2104 23:09:55.312968 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2105 23:09:55.316399 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2106 23:09:55.322943 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2107 23:09:55.329412 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2108 23:09:55.336403 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2109 23:09:55.342773 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2110 23:09:55.346409 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2111 23:09:55.349645 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2112 23:09:55.352875 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2113 23:09:55.359389 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2114 23:09:55.362522 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2115 23:09:55.366265 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2116 23:09:55.369437 ===================================
2117 23:09:55.372787 LPDDR4 DRAM CONFIGURATION
2118 23:09:55.375913 ===================================
2119 23:09:55.379232 EX_ROW_EN[0] = 0x0
2120 23:09:55.379689 EX_ROW_EN[1] = 0x0
2121 23:09:55.382876 LP4Y_EN = 0x0
2122 23:09:55.383386 WORK_FSP = 0x0
2123 23:09:55.385663 WL = 0x4
2124 23:09:55.386077 RL = 0x4
2125 23:09:55.389144 BL = 0x2
2126 23:09:55.389559 RPST = 0x0
2127 23:09:55.392455 RD_PRE = 0x0
2128 23:09:55.392902 WR_PRE = 0x1
2129 23:09:55.395980 WR_PST = 0x0
2130 23:09:55.396391 DBI_WR = 0x0
2131 23:09:55.399225 DBI_RD = 0x0
2132 23:09:55.399638 OTF = 0x1
2133 23:09:55.402731 ===================================
2134 23:09:55.409684 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2135 23:09:55.412308 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2136 23:09:55.416231 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2137 23:09:55.419189 ===================================
2138 23:09:55.422534 LPDDR4 DRAM CONFIGURATION
2139 23:09:55.425890 ===================================
2140 23:09:55.428869 EX_ROW_EN[0] = 0x10
2141 23:09:55.429283 EX_ROW_EN[1] = 0x0
2142 23:09:55.432498 LP4Y_EN = 0x0
2143 23:09:55.433069 WORK_FSP = 0x0
2144 23:09:55.435968 WL = 0x4
2145 23:09:55.436509 RL = 0x4
2146 23:09:55.438986 BL = 0x2
2147 23:09:55.439398 RPST = 0x0
2148 23:09:55.442584 RD_PRE = 0x0
2149 23:09:55.443095 WR_PRE = 0x1
2150 23:09:55.446233 WR_PST = 0x0
2151 23:09:55.446910 DBI_WR = 0x0
2152 23:09:55.449163 DBI_RD = 0x0
2153 23:09:55.449672 OTF = 0x1
2154 23:09:55.452580 ===================================
2155 23:09:55.459243 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2156 23:09:55.459791 ==
2157 23:09:55.462397 Dram Type= 6, Freq= 0, CH_0, rank 0
2158 23:09:55.469327 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2159 23:09:55.469888 ==
2160 23:09:55.470286 [Duty_Offset_Calibration]
2161 23:09:55.472332 B0:0 B1:2 CA:1
2162 23:09:55.472783
2163 23:09:55.475646 [DutyScan_Calibration_Flow] k_type=0
2164 23:09:55.484348
2165 23:09:55.484986 ==CLK 0==
2166 23:09:55.487553 Final CLK duty delay cell = 0
2167 23:09:55.491061 [0] MAX Duty = 5093%(X100), DQS PI = 12
2168 23:09:55.494512 [0] MIN Duty = 4938%(X100), DQS PI = 52
2169 23:09:55.494968 [0] AVG Duty = 5015%(X100)
2170 23:09:55.495337
2171 23:09:55.497496 CH0 CLK Duty spec in!! Max-Min= 155%
2172 23:09:55.504641 [DutyScan_Calibration_Flow] ====Done====
2173 23:09:55.505086
2174 23:09:55.507400 [DutyScan_Calibration_Flow] k_type=1
2175 23:09:55.523983
2176 23:09:55.524535 ==DQS 0 ==
2177 23:09:55.527133 Final DQS duty delay cell = 0
2178 23:09:55.530037 [0] MAX Duty = 5125%(X100), DQS PI = 30
2179 23:09:55.533632 [0] MIN Duty = 5031%(X100), DQS PI = 6
2180 23:09:55.534187 [0] AVG Duty = 5078%(X100)
2181 23:09:55.537018
2182 23:09:55.537569 ==DQS 1 ==
2183 23:09:55.540255 Final DQS duty delay cell = 0
2184 23:09:55.543729 [0] MAX Duty = 5062%(X100), DQS PI = 58
2185 23:09:55.546886 [0] MIN Duty = 4906%(X100), DQS PI = 14
2186 23:09:55.550105 [0] AVG Duty = 4984%(X100)
2187 23:09:55.550654
2188 23:09:55.553356 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2189 23:09:55.553855
2190 23:09:55.556665 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2191 23:09:55.560318 [DutyScan_Calibration_Flow] ====Done====
2192 23:09:55.560933
2193 23:09:55.563463 [DutyScan_Calibration_Flow] k_type=3
2194 23:09:55.580841
2195 23:09:55.581392 ==DQM 0 ==
2196 23:09:55.584197 Final DQM duty delay cell = 0
2197 23:09:55.587612 [0] MAX Duty = 5187%(X100), DQS PI = 20
2198 23:09:55.590753 [0] MIN Duty = 4969%(X100), DQS PI = 42
2199 23:09:55.594019 [0] AVG Duty = 5078%(X100)
2200 23:09:55.594477
2201 23:09:55.594832 ==DQM 1 ==
2202 23:09:55.597289 Final DQM duty delay cell = 4
2203 23:09:55.600633 [4] MAX Duty = 5187%(X100), DQS PI = 54
2204 23:09:55.603778 [4] MIN Duty = 5000%(X100), DQS PI = 18
2205 23:09:55.607569 [4] AVG Duty = 5093%(X100)
2206 23:09:55.608142
2207 23:09:55.610908 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2208 23:09:55.611455
2209 23:09:55.614040 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2210 23:09:55.617535 [DutyScan_Calibration_Flow] ====Done====
2211 23:09:55.617950
2212 23:09:55.620478 [DutyScan_Calibration_Flow] k_type=2
2213 23:09:55.635739
2214 23:09:55.636289 ==DQ 0 ==
2215 23:09:55.639196 Final DQ duty delay cell = -4
2216 23:09:55.642496 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2217 23:09:55.645846 [-4] MIN Duty = 4813%(X100), DQS PI = 54
2218 23:09:55.649053 [-4] AVG Duty = 4937%(X100)
2219 23:09:55.649613
2220 23:09:55.649970 ==DQ 1 ==
2221 23:09:55.652372 Final DQ duty delay cell = -4
2222 23:09:55.655991 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2223 23:09:55.658891 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2224 23:09:55.662380 [-4] AVG Duty = 4969%(X100)
2225 23:09:55.662929
2226 23:09:55.665737 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2227 23:09:55.666197
2228 23:09:55.669196 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2229 23:09:55.672445 [DutyScan_Calibration_Flow] ====Done====
2230 23:09:55.672962 ==
2231 23:09:55.675882 Dram Type= 6, Freq= 0, CH_1, rank 0
2232 23:09:55.678834 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2233 23:09:55.679301 ==
2234 23:09:55.682412 [Duty_Offset_Calibration]
2235 23:09:55.682958 B0:0 B1:5 CA:-5
2236 23:09:55.683324
2237 23:09:55.685425 [DutyScan_Calibration_Flow] k_type=0
2238 23:09:55.696547
2239 23:09:55.697152 ==CLK 0==
2240 23:09:55.699696 Final CLK duty delay cell = 0
2241 23:09:55.703315 [0] MAX Duty = 5094%(X100), DQS PI = 24
2242 23:09:55.706614 [0] MIN Duty = 4907%(X100), DQS PI = 44
2243 23:09:55.707167 [0] AVG Duty = 5000%(X100)
2244 23:09:55.709859
2245 23:09:55.712874 CH1 CLK Duty spec in!! Max-Min= 187%
2246 23:09:55.716391 [DutyScan_Calibration_Flow] ====Done====
2247 23:09:55.717038
2248 23:09:55.719523 [DutyScan_Calibration_Flow] k_type=1
2249 23:09:55.735012
2250 23:09:55.735562 ==DQS 0 ==
2251 23:09:55.738179 Final DQS duty delay cell = 0
2252 23:09:55.741295 [0] MAX Duty = 5125%(X100), DQS PI = 16
2253 23:09:55.744858 [0] MIN Duty = 4875%(X100), DQS PI = 40
2254 23:09:55.748448 [0] AVG Duty = 5000%(X100)
2255 23:09:55.749050
2256 23:09:55.749417 ==DQS 1 ==
2257 23:09:55.751594 Final DQS duty delay cell = -4
2258 23:09:55.754823 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2259 23:09:55.758139 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2260 23:09:55.761386 [-4] AVG Duty = 4969%(X100)
2261 23:09:55.761935
2262 23:09:55.764435 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2263 23:09:55.765103
2264 23:09:55.767890 CH1 DQS 1 Duty spec in!! Max-Min= 124%
2265 23:09:55.771492 [DutyScan_Calibration_Flow] ====Done====
2266 23:09:55.772050
2267 23:09:55.774807 [DutyScan_Calibration_Flow] k_type=3
2268 23:09:55.790071
2269 23:09:55.790700 ==DQM 0 ==
2270 23:09:55.793573 Final DQM duty delay cell = -4
2271 23:09:55.796766 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2272 23:09:55.800446 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2273 23:09:55.803272 [-4] AVG Duty = 4969%(X100)
2274 23:09:55.803739
2275 23:09:55.804092 ==DQM 1 ==
2276 23:09:55.806791 Final DQM duty delay cell = -4
2277 23:09:55.810432 [-4] MAX Duty = 5094%(X100), DQS PI = 20
2278 23:09:55.813451 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2279 23:09:55.816869 [-4] AVG Duty = 5000%(X100)
2280 23:09:55.817439
2281 23:09:55.819947 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2282 23:09:55.820404
2283 23:09:55.823472 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2284 23:09:55.826735 [DutyScan_Calibration_Flow] ====Done====
2285 23:09:55.827246
2286 23:09:55.829967 [DutyScan_Calibration_Flow] k_type=2
2287 23:09:55.847790
2288 23:09:55.848429 ==DQ 0 ==
2289 23:09:55.850995 Final DQ duty delay cell = 0
2290 23:09:55.853853 [0] MAX Duty = 5093%(X100), DQS PI = 2
2291 23:09:55.857471 [0] MIN Duty = 4969%(X100), DQS PI = 44
2292 23:09:55.858028 [0] AVG Duty = 5031%(X100)
2293 23:09:55.858389
2294 23:09:55.860623 ==DQ 1 ==
2295 23:09:55.863869 Final DQ duty delay cell = 0
2296 23:09:55.867003 [0] MAX Duty = 5031%(X100), DQS PI = 8
2297 23:09:55.870468 [0] MIN Duty = 4907%(X100), DQS PI = 0
2298 23:09:55.870923 [0] AVG Duty = 4969%(X100)
2299 23:09:55.871471
2300 23:09:55.873869 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2301 23:09:55.874281
2302 23:09:55.877180 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2303 23:09:55.883812 [DutyScan_Calibration_Flow] ====Done====
2304 23:09:55.887331 nWR fixed to 30
2305 23:09:55.887841 [ModeRegInit_LP4] CH0 RK0
2306 23:09:55.890394 [ModeRegInit_LP4] CH0 RK1
2307 23:09:55.893761 [ModeRegInit_LP4] CH1 RK0
2308 23:09:55.894172 [ModeRegInit_LP4] CH1 RK1
2309 23:09:55.897417 match AC timing 6
2310 23:09:55.900521 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2311 23:09:55.904036 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2312 23:09:55.910805 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2313 23:09:55.913593 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2314 23:09:55.920416 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2315 23:09:55.920906 ==
2316 23:09:55.924180 Dram Type= 6, Freq= 0, CH_0, rank 0
2317 23:09:55.927410 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2318 23:09:55.927826 ==
2319 23:09:55.934121 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2320 23:09:55.937136 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2321 23:09:55.947330 [CA 0] Center 39 (9~70) winsize 62
2322 23:09:55.950690 [CA 1] Center 39 (8~70) winsize 63
2323 23:09:55.953337 [CA 2] Center 36 (5~67) winsize 63
2324 23:09:55.957151 [CA 3] Center 35 (4~66) winsize 63
2325 23:09:55.960574 [CA 4] Center 34 (3~65) winsize 63
2326 23:09:55.963750 [CA 5] Center 33 (3~64) winsize 62
2327 23:09:55.964158
2328 23:09:55.966811 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2329 23:09:55.967262
2330 23:09:55.970646 [CATrainingPosCal] consider 1 rank data
2331 23:09:55.973883 u2DelayCellTimex100 = 270/100 ps
2332 23:09:55.977289 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2333 23:09:55.980416 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2334 23:09:55.987029 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2335 23:09:55.990165 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2336 23:09:55.993697 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2337 23:09:55.996754 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2338 23:09:55.997168
2339 23:09:56.000396 CA PerBit enable=1, Macro0, CA PI delay=33
2340 23:09:56.000953
2341 23:09:56.003343 [CBTSetCACLKResult] CA Dly = 33
2342 23:09:56.003753 CS Dly: 7 (0~38)
2343 23:09:56.007071 ==
2344 23:09:56.007575 Dram Type= 6, Freq= 0, CH_0, rank 1
2345 23:09:56.013417 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2346 23:09:56.013912 ==
2347 23:09:56.016995 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2348 23:09:56.023714 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2349 23:09:56.032571 [CA 0] Center 39 (8~70) winsize 63
2350 23:09:56.035956 [CA 1] Center 39 (8~70) winsize 63
2351 23:09:56.039159 [CA 2] Center 36 (5~67) winsize 63
2352 23:09:56.043017 [CA 3] Center 35 (4~66) winsize 63
2353 23:09:56.046090 [CA 4] Center 33 (3~64) winsize 62
2354 23:09:56.049129 [CA 5] Center 34 (3~65) winsize 63
2355 23:09:56.049690
2356 23:09:56.052504 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2357 23:09:56.053165
2358 23:09:56.055451 [CATrainingPosCal] consider 2 rank data
2359 23:09:56.059010 u2DelayCellTimex100 = 270/100 ps
2360 23:09:56.062208 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2361 23:09:56.069393 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2362 23:09:56.072323 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2363 23:09:56.075491 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2364 23:09:56.078612 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2365 23:09:56.082348 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2366 23:09:56.082917
2367 23:09:56.085599 CA PerBit enable=1, Macro0, CA PI delay=33
2368 23:09:56.086150
2369 23:09:56.089174 [CBTSetCACLKResult] CA Dly = 33
2370 23:09:56.089735 CS Dly: 7 (0~39)
2371 23:09:56.091984
2372 23:09:56.095682 ----->DramcWriteLeveling(PI) begin...
2373 23:09:56.096247 ==
2374 23:09:56.098763 Dram Type= 6, Freq= 0, CH_0, rank 0
2375 23:09:56.102227 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2376 23:09:56.102988 ==
2377 23:09:56.105419 Write leveling (Byte 0): 29 => 29
2378 23:09:56.109161 Write leveling (Byte 1): 26 => 26
2379 23:09:56.112417 DramcWriteLeveling(PI) end<-----
2380 23:09:56.113057
2381 23:09:56.113428 ==
2382 23:09:56.115579 Dram Type= 6, Freq= 0, CH_0, rank 0
2383 23:09:56.118631 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2384 23:09:56.119096 ==
2385 23:09:56.122008 [Gating] SW mode calibration
2386 23:09:56.129251 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2387 23:09:56.135472 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2388 23:09:56.139068 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2389 23:09:56.142062 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2390 23:09:56.149022 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2391 23:09:56.152321 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2392 23:09:56.155436 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2393 23:09:56.158789 0 11 20 | B1->B0 | 3131 2b2b | 1 1 | (1 0) (1 0)
2394 23:09:56.165591 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2395 23:09:56.168570 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2396 23:09:56.172131 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2397 23:09:56.178719 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2398 23:09:56.182315 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2399 23:09:56.185163 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2400 23:09:56.192056 0 12 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2401 23:09:56.195443 0 12 20 | B1->B0 | 3636 4040 | 0 0 | (0 0) (0 0)
2402 23:09:56.199014 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2403 23:09:56.205270 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2404 23:09:56.208774 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2405 23:09:56.212402 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2406 23:09:56.218529 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2407 23:09:56.222830 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2408 23:09:56.225442 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2409 23:09:56.232183 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2410 23:09:56.235614 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2411 23:09:56.238990 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 23:09:56.242109 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 23:09:56.248976 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 23:09:56.252430 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 23:09:56.255840 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2416 23:09:56.262492 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2417 23:09:56.265494 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2418 23:09:56.269022 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2419 23:09:56.276023 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2420 23:09:56.278739 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2421 23:09:56.282160 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2422 23:09:56.288701 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2423 23:09:56.292354 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2424 23:09:56.295299 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2425 23:09:56.302312 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2426 23:09:56.305298 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2427 23:09:56.309015 Total UI for P1: 0, mck2ui 16
2428 23:09:56.311822 best dqsien dly found for B0: ( 0, 15, 18)
2429 23:09:56.315396 Total UI for P1: 0, mck2ui 16
2430 23:09:56.318822 best dqsien dly found for B1: ( 0, 15, 20)
2431 23:09:56.322200 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2432 23:09:56.325629 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2433 23:09:56.326046
2434 23:09:56.328646 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2435 23:09:56.332204 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2436 23:09:56.335471 [Gating] SW calibration Done
2437 23:09:56.335986 ==
2438 23:09:56.338337 Dram Type= 6, Freq= 0, CH_0, rank 0
2439 23:09:56.341744 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2440 23:09:56.345521 ==
2441 23:09:56.346036 RX Vref Scan: 0
2442 23:09:56.346367
2443 23:09:56.348893 RX Vref 0 -> 0, step: 1
2444 23:09:56.349402
2445 23:09:56.352811 RX Delay -40 -> 252, step: 8
2446 23:09:56.355542 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2447 23:09:56.358793 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2448 23:09:56.362039 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2449 23:09:56.365296 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2450 23:09:56.372141 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2451 23:09:56.375368 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2452 23:09:56.378680 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2453 23:09:56.381927 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2454 23:09:56.385254 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2455 23:09:56.388494 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2456 23:09:56.395284 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2457 23:09:56.398502 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2458 23:09:56.401777 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2459 23:09:56.405383 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2460 23:09:56.411973 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2461 23:09:56.415575 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2462 23:09:56.416035 ==
2463 23:09:56.418468 Dram Type= 6, Freq= 0, CH_0, rank 0
2464 23:09:56.421425 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2465 23:09:56.421884 ==
2466 23:09:56.425079 DQS Delay:
2467 23:09:56.425534 DQS0 = 0, DQS1 = 0
2468 23:09:56.425891 DQM Delay:
2469 23:09:56.428086 DQM0 = 116, DQM1 = 106
2470 23:09:56.428541 DQ Delay:
2471 23:09:56.431420 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =115
2472 23:09:56.434969 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2473 23:09:56.438474 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2474 23:09:56.444876 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2475 23:09:56.445384
2476 23:09:56.445713
2477 23:09:56.446017 ==
2478 23:09:56.448293 Dram Type= 6, Freq= 0, CH_0, rank 0
2479 23:09:56.451513 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2480 23:09:56.452021 ==
2481 23:09:56.452352
2482 23:09:56.452654
2483 23:09:56.455026 TX Vref Scan disable
2484 23:09:56.455539 == TX Byte 0 ==
2485 23:09:56.461659 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2486 23:09:56.464985 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2487 23:09:56.465498 == TX Byte 1 ==
2488 23:09:56.471438 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2489 23:09:56.474829 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2490 23:09:56.475342 ==
2491 23:09:56.478299 Dram Type= 6, Freq= 0, CH_0, rank 0
2492 23:09:56.481366 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2493 23:09:56.481784 ==
2494 23:09:56.494173 TX Vref=22, minBit 9, minWin=25, winSum=412
2495 23:09:56.497409 TX Vref=24, minBit 9, minWin=25, winSum=417
2496 23:09:56.501025 TX Vref=26, minBit 8, minWin=26, winSum=430
2497 23:09:56.504324 TX Vref=28, minBit 15, minWin=25, winSum=430
2498 23:09:56.507503 TX Vref=30, minBit 10, minWin=26, winSum=436
2499 23:09:56.514308 TX Vref=32, minBit 9, minWin=26, winSum=430
2500 23:09:56.517215 [TxChooseVref] Worse bit 10, Min win 26, Win sum 436, Final Vref 30
2501 23:09:56.517633
2502 23:09:56.520486 Final TX Range 1 Vref 30
2503 23:09:56.521037
2504 23:09:56.521377 ==
2505 23:09:56.524420 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 23:09:56.527511 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2507 23:09:56.530592 ==
2508 23:09:56.531010
2509 23:09:56.531332
2510 23:09:56.531631 TX Vref Scan disable
2511 23:09:56.534173 == TX Byte 0 ==
2512 23:09:56.537267 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2513 23:09:56.541062 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2514 23:09:56.543779 == TX Byte 1 ==
2515 23:09:56.547647 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2516 23:09:56.553835 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2517 23:09:56.554347
2518 23:09:56.554676 [DATLAT]
2519 23:09:56.555084 Freq=1200, CH0 RK0
2520 23:09:56.555395
2521 23:09:56.556976 DATLAT Default: 0xd
2522 23:09:56.557391 0, 0xFFFF, sum = 0
2523 23:09:56.560433 1, 0xFFFF, sum = 0
2524 23:09:56.564048 2, 0xFFFF, sum = 0
2525 23:09:56.564560 3, 0xFFFF, sum = 0
2526 23:09:56.567347 4, 0xFFFF, sum = 0
2527 23:09:56.567787 5, 0xFFFF, sum = 0
2528 23:09:56.571049 6, 0xFFFF, sum = 0
2529 23:09:56.571566 7, 0xFFFF, sum = 0
2530 23:09:56.574229 8, 0xFFFF, sum = 0
2531 23:09:56.574743 9, 0xFFFF, sum = 0
2532 23:09:56.577174 10, 0xFFFF, sum = 0
2533 23:09:56.577697 11, 0x0, sum = 1
2534 23:09:56.580811 12, 0x0, sum = 2
2535 23:09:56.581322 13, 0x0, sum = 3
2536 23:09:56.584201 14, 0x0, sum = 4
2537 23:09:56.584758 best_step = 12
2538 23:09:56.585106
2539 23:09:56.585414 ==
2540 23:09:56.586998 Dram Type= 6, Freq= 0, CH_0, rank 0
2541 23:09:56.590507 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2542 23:09:56.590973 ==
2543 23:09:56.593781 RX Vref Scan: 1
2544 23:09:56.594345
2545 23:09:56.597389 Set Vref Range= 32 -> 127
2546 23:09:56.597943
2547 23:09:56.598306 RX Vref 32 -> 127, step: 1
2548 23:09:56.598638
2549 23:09:56.600335 RX Delay -21 -> 252, step: 4
2550 23:09:56.600835
2551 23:09:56.604177 Set Vref, RX VrefLevel [Byte0]: 32
2552 23:09:56.607019 [Byte1]: 32
2553 23:09:56.610981
2554 23:09:56.611534 Set Vref, RX VrefLevel [Byte0]: 33
2555 23:09:56.614167 [Byte1]: 33
2556 23:09:56.618839
2557 23:09:56.619358 Set Vref, RX VrefLevel [Byte0]: 34
2558 23:09:56.621911 [Byte1]: 34
2559 23:09:56.626666
2560 23:09:56.627214 Set Vref, RX VrefLevel [Byte0]: 35
2561 23:09:56.630139 [Byte1]: 35
2562 23:09:56.634766
2563 23:09:56.635317 Set Vref, RX VrefLevel [Byte0]: 36
2564 23:09:56.638004 [Byte1]: 36
2565 23:09:56.643314
2566 23:09:56.643868 Set Vref, RX VrefLevel [Byte0]: 37
2567 23:09:56.646018 [Byte1]: 37
2568 23:09:56.650440
2569 23:09:56.650992 Set Vref, RX VrefLevel [Byte0]: 38
2570 23:09:56.653671 [Byte1]: 38
2571 23:09:56.658584
2572 23:09:56.659135 Set Vref, RX VrefLevel [Byte0]: 39
2573 23:09:56.661970 [Byte1]: 39
2574 23:09:56.666276
2575 23:09:56.666840 Set Vref, RX VrefLevel [Byte0]: 40
2576 23:09:56.669354 [Byte1]: 40
2577 23:09:56.674150
2578 23:09:56.674711 Set Vref, RX VrefLevel [Byte0]: 41
2579 23:09:56.677564 [Byte1]: 41
2580 23:09:56.682505
2581 23:09:56.683056 Set Vref, RX VrefLevel [Byte0]: 42
2582 23:09:56.685549 [Byte1]: 42
2583 23:09:56.690382
2584 23:09:56.690941 Set Vref, RX VrefLevel [Byte0]: 43
2585 23:09:56.693607 [Byte1]: 43
2586 23:09:56.697901
2587 23:09:56.698430 Set Vref, RX VrefLevel [Byte0]: 44
2588 23:09:56.701462 [Byte1]: 44
2589 23:09:56.705957
2590 23:09:56.706532 Set Vref, RX VrefLevel [Byte0]: 45
2591 23:09:56.709126 [Byte1]: 45
2592 23:09:56.713944
2593 23:09:56.714499 Set Vref, RX VrefLevel [Byte0]: 46
2594 23:09:56.716826 [Byte1]: 46
2595 23:09:56.721732
2596 23:09:56.722286 Set Vref, RX VrefLevel [Byte0]: 47
2597 23:09:56.725367 [Byte1]: 47
2598 23:09:56.729720
2599 23:09:56.730273 Set Vref, RX VrefLevel [Byte0]: 48
2600 23:09:56.733208 [Byte1]: 48
2601 23:09:56.737368
2602 23:09:56.737822 Set Vref, RX VrefLevel [Byte0]: 49
2603 23:09:56.741345 [Byte1]: 49
2604 23:09:56.745617
2605 23:09:56.746098 Set Vref, RX VrefLevel [Byte0]: 50
2606 23:09:56.748757 [Byte1]: 50
2607 23:09:56.753447
2608 23:09:56.753997 Set Vref, RX VrefLevel [Byte0]: 51
2609 23:09:56.756512 [Byte1]: 51
2610 23:09:56.761653
2611 23:09:56.762168 Set Vref, RX VrefLevel [Byte0]: 52
2612 23:09:56.764862 [Byte1]: 52
2613 23:09:56.769314
2614 23:09:56.769772 Set Vref, RX VrefLevel [Byte0]: 53
2615 23:09:56.772866 [Byte1]: 53
2616 23:09:56.777336
2617 23:09:56.777887 Set Vref, RX VrefLevel [Byte0]: 54
2618 23:09:56.780483 [Byte1]: 54
2619 23:09:56.785221
2620 23:09:56.785762 Set Vref, RX VrefLevel [Byte0]: 55
2621 23:09:56.788641 [Byte1]: 55
2622 23:09:56.793071
2623 23:09:56.793621 Set Vref, RX VrefLevel [Byte0]: 56
2624 23:09:56.796150 [Byte1]: 56
2625 23:09:56.801151
2626 23:09:56.801699 Set Vref, RX VrefLevel [Byte0]: 57
2627 23:09:56.804973 [Byte1]: 57
2628 23:09:56.809408
2629 23:09:56.809868 Set Vref, RX VrefLevel [Byte0]: 58
2630 23:09:56.812473 [Byte1]: 58
2631 23:09:56.816877
2632 23:09:56.817439 Set Vref, RX VrefLevel [Byte0]: 59
2633 23:09:56.820229 [Byte1]: 59
2634 23:09:56.824420
2635 23:09:56.824920 Set Vref, RX VrefLevel [Byte0]: 60
2636 23:09:56.828238 [Byte1]: 60
2637 23:09:56.832893
2638 23:09:56.833455 Set Vref, RX VrefLevel [Byte0]: 61
2639 23:09:56.836175 [Byte1]: 61
2640 23:09:56.840891
2641 23:09:56.841439 Set Vref, RX VrefLevel [Byte0]: 62
2642 23:09:56.843904 [Byte1]: 62
2643 23:09:56.848615
2644 23:09:56.849210 Set Vref, RX VrefLevel [Byte0]: 63
2645 23:09:56.851891 [Byte1]: 63
2646 23:09:56.856307
2647 23:09:56.856895 Set Vref, RX VrefLevel [Byte0]: 64
2648 23:09:56.859694 [Byte1]: 64
2649 23:09:56.864403
2650 23:09:56.864998 Set Vref, RX VrefLevel [Byte0]: 65
2651 23:09:56.867607 [Byte1]: 65
2652 23:09:56.872368
2653 23:09:56.873013 Set Vref, RX VrefLevel [Byte0]: 66
2654 23:09:56.875551 [Byte1]: 66
2655 23:09:56.880159
2656 23:09:56.880746 Set Vref, RX VrefLevel [Byte0]: 67
2657 23:09:56.883726 [Byte1]: 67
2658 23:09:56.888177
2659 23:09:56.888760 Final RX Vref Byte 0 = 47 to rank0
2660 23:09:56.891413 Final RX Vref Byte 1 = 48 to rank0
2661 23:09:56.894772 Final RX Vref Byte 0 = 47 to rank1
2662 23:09:56.898627 Final RX Vref Byte 1 = 48 to rank1==
2663 23:09:56.901387 Dram Type= 6, Freq= 0, CH_0, rank 0
2664 23:09:56.908021 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2665 23:09:56.908557 ==
2666 23:09:56.908978 DQS Delay:
2667 23:09:56.909322 DQS0 = 0, DQS1 = 0
2668 23:09:56.911677 DQM Delay:
2669 23:09:56.912140 DQM0 = 113, DQM1 = 105
2670 23:09:56.914917 DQ Delay:
2671 23:09:56.918135 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2672 23:09:56.921185 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2673 23:09:56.924754 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2674 23:09:56.928461 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2675 23:09:56.929085
2676 23:09:56.929461
2677 23:09:56.934852 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
2678 23:09:56.938149 CH0 RK0: MR19=404, MR18=A0A
2679 23:09:56.945545 CH0_RK0: MR19=0x404, MR18=0xA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
2680 23:09:56.946102
2681 23:09:56.948115 ----->DramcWriteLeveling(PI) begin...
2682 23:09:56.948670 ==
2683 23:09:56.951181 Dram Type= 6, Freq= 0, CH_0, rank 1
2684 23:09:56.954891 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2685 23:09:56.955450 ==
2686 23:09:56.958183 Write leveling (Byte 0): 29 => 29
2687 23:09:56.961420 Write leveling (Byte 1): 25 => 25
2688 23:09:56.964679 DramcWriteLeveling(PI) end<-----
2689 23:09:56.965180
2690 23:09:56.965538 ==
2691 23:09:56.967860 Dram Type= 6, Freq= 0, CH_0, rank 1
2692 23:09:56.971997 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2693 23:09:56.975297 ==
2694 23:09:56.975841 [Gating] SW mode calibration
2695 23:09:56.981341 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2696 23:09:56.988183 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2697 23:09:56.991493 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2698 23:09:56.998283 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2699 23:09:57.001524 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2700 23:09:57.004855 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2701 23:09:57.012015 0 11 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2702 23:09:57.015015 0 11 20 | B1->B0 | 3030 2525 | 1 0 | (1 0) (0 0)
2703 23:09:57.017998 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2704 23:09:57.024619 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2705 23:09:57.028130 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2706 23:09:57.031537 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2707 23:09:57.038551 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2708 23:09:57.041420 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2709 23:09:57.044891 0 12 16 | B1->B0 | 2727 3939 | 0 0 | (0 0) (0 0)
2710 23:09:57.048147 0 12 20 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2711 23:09:57.054914 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2712 23:09:57.058150 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2713 23:09:57.061589 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2714 23:09:57.067984 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2715 23:09:57.071640 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2716 23:09:57.074628 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2717 23:09:57.081401 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2718 23:09:57.084635 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2719 23:09:57.087865 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2720 23:09:57.094704 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2721 23:09:57.098122 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2722 23:09:57.101384 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2723 23:09:57.108331 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2724 23:09:57.111550 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2725 23:09:57.114656 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2726 23:09:57.121316 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2727 23:09:57.124458 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2728 23:09:57.127717 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2729 23:09:57.134969 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2730 23:09:57.138066 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2731 23:09:57.141438 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2732 23:09:57.144753 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2733 23:09:57.151407 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2734 23:09:57.154647 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2735 23:09:57.158199 Total UI for P1: 0, mck2ui 16
2736 23:09:57.161211 best dqsien dly found for B0: ( 0, 15, 16)
2737 23:09:57.164960 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2738 23:09:57.168156 Total UI for P1: 0, mck2ui 16
2739 23:09:57.171502 best dqsien dly found for B1: ( 0, 15, 18)
2740 23:09:57.174904 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2741 23:09:57.178510 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2742 23:09:57.181621
2743 23:09:57.184983 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2744 23:09:57.188455 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2745 23:09:57.191639 [Gating] SW calibration Done
2746 23:09:57.192198 ==
2747 23:09:57.194694 Dram Type= 6, Freq= 0, CH_0, rank 1
2748 23:09:57.197860 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2749 23:09:57.198323 ==
2750 23:09:57.198684 RX Vref Scan: 0
2751 23:09:57.199019
2752 23:09:57.201510 RX Vref 0 -> 0, step: 1
2753 23:09:57.202059
2754 23:09:57.205078 RX Delay -40 -> 252, step: 8
2755 23:09:57.208242 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2756 23:09:57.211477 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2757 23:09:57.218105 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2758 23:09:57.221461 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2759 23:09:57.224444 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2760 23:09:57.227932 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2761 23:09:57.231148 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2762 23:09:57.237711 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2763 23:09:57.241333 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2764 23:09:57.244504 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2765 23:09:57.247851 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2766 23:09:57.251026 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2767 23:09:57.257772 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2768 23:09:57.261401 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2769 23:09:57.264453 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2770 23:09:57.267711 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2771 23:09:57.268169 ==
2772 23:09:57.270767 Dram Type= 6, Freq= 0, CH_0, rank 1
2773 23:09:57.277747 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2774 23:09:57.278302 ==
2775 23:09:57.278663 DQS Delay:
2776 23:09:57.279003 DQS0 = 0, DQS1 = 0
2777 23:09:57.281114 DQM Delay:
2778 23:09:57.281666 DQM0 = 115, DQM1 = 106
2779 23:09:57.284471 DQ Delay:
2780 23:09:57.287568 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2781 23:09:57.291002 DQ4 =119, DQ5 =107, DQ6 =123, DQ7 =123
2782 23:09:57.294732 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
2783 23:09:57.297635 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2784 23:09:57.298215
2785 23:09:57.298578
2786 23:09:57.298911 ==
2787 23:09:57.300893 Dram Type= 6, Freq= 0, CH_0, rank 1
2788 23:09:57.304229 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2789 23:09:57.304835 ==
2790 23:09:57.305211
2791 23:09:57.307487
2792 23:09:57.307936 TX Vref Scan disable
2793 23:09:57.310853 == TX Byte 0 ==
2794 23:09:57.314350 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2795 23:09:57.317509 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2796 23:09:57.321358 == TX Byte 1 ==
2797 23:09:57.324203 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2798 23:09:57.327855 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2799 23:09:57.328407 ==
2800 23:09:57.331096 Dram Type= 6, Freq= 0, CH_0, rank 1
2801 23:09:57.337716 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2802 23:09:57.338271 ==
2803 23:09:57.348227 TX Vref=22, minBit 8, minWin=25, winSum=418
2804 23:09:57.351706 TX Vref=24, minBit 8, minWin=25, winSum=424
2805 23:09:57.355243 TX Vref=26, minBit 8, minWin=26, winSum=427
2806 23:09:57.358573 TX Vref=28, minBit 9, minWin=26, winSum=433
2807 23:09:57.361909 TX Vref=30, minBit 9, minWin=26, winSum=436
2808 23:09:57.365097 TX Vref=32, minBit 10, minWin=26, winSum=434
2809 23:09:57.371651 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 30
2810 23:09:57.372210
2811 23:09:57.374937 Final TX Range 1 Vref 30
2812 23:09:57.375495
2813 23:09:57.375858 ==
2814 23:09:57.378065 Dram Type= 6, Freq= 0, CH_0, rank 1
2815 23:09:57.381988 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2816 23:09:57.382544 ==
2817 23:09:57.382904
2818 23:09:57.384752
2819 23:09:57.385381 TX Vref Scan disable
2820 23:09:57.388341 == TX Byte 0 ==
2821 23:09:57.391832 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2822 23:09:57.394940 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2823 23:09:57.398369 == TX Byte 1 ==
2824 23:09:57.401618 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2825 23:09:57.404944 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2826 23:09:57.408139
2827 23:09:57.408689 [DATLAT]
2828 23:09:57.409110 Freq=1200, CH0 RK1
2829 23:09:57.409454
2830 23:09:57.411314 DATLAT Default: 0xc
2831 23:09:57.411772 0, 0xFFFF, sum = 0
2832 23:09:57.414918 1, 0xFFFF, sum = 0
2833 23:09:57.415485 2, 0xFFFF, sum = 0
2834 23:09:57.417959 3, 0xFFFF, sum = 0
2835 23:09:57.418424 4, 0xFFFF, sum = 0
2836 23:09:57.421333 5, 0xFFFF, sum = 0
2837 23:09:57.424612 6, 0xFFFF, sum = 0
2838 23:09:57.425238 7, 0xFFFF, sum = 0
2839 23:09:57.427782 8, 0xFFFF, sum = 0
2840 23:09:57.428162 9, 0xFFFF, sum = 0
2841 23:09:57.431573 10, 0xFFFF, sum = 0
2842 23:09:57.432130 11, 0x0, sum = 1
2843 23:09:57.434947 12, 0x0, sum = 2
2844 23:09:57.435428 13, 0x0, sum = 3
2845 23:09:57.435794 14, 0x0, sum = 4
2846 23:09:57.437781 best_step = 12
2847 23:09:57.438229
2848 23:09:57.438586 ==
2849 23:09:57.441417 Dram Type= 6, Freq= 0, CH_0, rank 1
2850 23:09:57.444686 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2851 23:09:57.445136 ==
2852 23:09:57.448430 RX Vref Scan: 0
2853 23:09:57.448891
2854 23:09:57.449225 RX Vref 0 -> 0, step: 1
2855 23:09:57.451236
2856 23:09:57.451650 RX Delay -21 -> 252, step: 4
2857 23:09:57.458328 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2858 23:09:57.461641 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2859 23:09:57.465336 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2860 23:09:57.468918 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2861 23:09:57.471475 iDelay=199, Bit 4, Center 118 (47 ~ 190) 144
2862 23:09:57.478114 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2863 23:09:57.481460 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
2864 23:09:57.484967 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2865 23:09:57.488221 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2866 23:09:57.491826 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2867 23:09:57.498258 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2868 23:09:57.501557 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2869 23:09:57.504809 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
2870 23:09:57.508424 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2871 23:09:57.511407 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
2872 23:09:57.518062 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2873 23:09:57.518575 ==
2874 23:09:57.521417 Dram Type= 6, Freq= 0, CH_0, rank 1
2875 23:09:57.524813 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2876 23:09:57.525237 ==
2877 23:09:57.525568 DQS Delay:
2878 23:09:57.528193 DQS0 = 0, DQS1 = 0
2879 23:09:57.528629 DQM Delay:
2880 23:09:57.531876 DQM0 = 115, DQM1 = 105
2881 23:09:57.532400 DQ Delay:
2882 23:09:57.534970 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2883 23:09:57.537936 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =124
2884 23:09:57.541790 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2885 23:09:57.544807 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2886 23:09:57.545232
2887 23:09:57.545623
2888 23:09:57.554920 [DQSOSCAuto] RK1, (LSB)MR18= 0x1111, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 403 ps
2889 23:09:57.558400 CH0 RK1: MR19=404, MR18=1111
2890 23:09:57.561866 CH0_RK1: MR19=0x404, MR18=0x1111, DQSOSC=403, MR23=63, INC=40, DEC=26
2891 23:09:57.564969 [RxdqsGatingPostProcess] freq 1200
2892 23:09:57.571547 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2893 23:09:57.575115 Pre-setting of DQS Precalculation
2894 23:09:57.578491 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2895 23:09:57.581407 ==
2896 23:09:57.585185 Dram Type= 6, Freq= 0, CH_1, rank 0
2897 23:09:57.588182 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2898 23:09:57.588795 ==
2899 23:09:57.594604 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2900 23:09:57.598007 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2901 23:09:57.607188 [CA 0] Center 37 (7~68) winsize 62
2902 23:09:57.610559 [CA 1] Center 37 (7~68) winsize 62
2903 23:09:57.613642 [CA 2] Center 34 (4~65) winsize 62
2904 23:09:57.617307 [CA 3] Center 33 (3~64) winsize 62
2905 23:09:57.620983 [CA 4] Center 32 (2~63) winsize 62
2906 23:09:57.623800 [CA 5] Center 32 (2~63) winsize 62
2907 23:09:57.624269
2908 23:09:57.627570 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2909 23:09:57.628136
2910 23:09:57.630789 [CATrainingPosCal] consider 1 rank data
2911 23:09:57.634367 u2DelayCellTimex100 = 270/100 ps
2912 23:09:57.637506 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2913 23:09:57.640813 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2914 23:09:57.646955 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2915 23:09:57.650524 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2916 23:09:57.653948 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2917 23:09:57.657075 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2918 23:09:57.657649
2919 23:09:57.660335 CA PerBit enable=1, Macro0, CA PI delay=32
2920 23:09:57.660946
2921 23:09:57.663702 [CBTSetCACLKResult] CA Dly = 32
2922 23:09:57.664264 CS Dly: 5 (0~36)
2923 23:09:57.667268 ==
2924 23:09:57.667892 Dram Type= 6, Freq= 0, CH_1, rank 1
2925 23:09:57.673675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2926 23:09:57.674234 ==
2927 23:09:57.677363 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2928 23:09:57.684040 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2929 23:09:57.692869 [CA 0] Center 37 (7~68) winsize 62
2930 23:09:57.695898 [CA 1] Center 37 (6~68) winsize 63
2931 23:09:57.699428 [CA 2] Center 34 (3~65) winsize 63
2932 23:09:57.702589 [CA 3] Center 33 (3~64) winsize 62
2933 23:09:57.705782 [CA 4] Center 32 (2~63) winsize 62
2934 23:09:57.708792 [CA 5] Center 32 (1~63) winsize 63
2935 23:09:57.709268
2936 23:09:57.712180 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2937 23:09:57.712654
2938 23:09:57.715696 [CATrainingPosCal] consider 2 rank data
2939 23:09:57.718960 u2DelayCellTimex100 = 270/100 ps
2940 23:09:57.722258 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2941 23:09:57.728851 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2942 23:09:57.732558 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2943 23:09:57.735614 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2944 23:09:57.739086 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2945 23:09:57.742148 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2946 23:09:57.742721
2947 23:09:57.745515 CA PerBit enable=1, Macro0, CA PI delay=32
2948 23:09:57.745987
2949 23:09:57.748628 [CBTSetCACLKResult] CA Dly = 32
2950 23:09:57.749163 CS Dly: 6 (0~38)
2951 23:09:57.749638
2952 23:09:57.755704 ----->DramcWriteLeveling(PI) begin...
2953 23:09:57.756288 ==
2954 23:09:57.758843 Dram Type= 6, Freq= 0, CH_1, rank 0
2955 23:09:57.762407 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2956 23:09:57.762978 ==
2957 23:09:57.765555 Write leveling (Byte 0): 21 => 21
2958 23:09:57.768575 Write leveling (Byte 1): 21 => 21
2959 23:09:57.772145 DramcWriteLeveling(PI) end<-----
2960 23:09:57.772617
2961 23:09:57.773166 ==
2962 23:09:57.775721 Dram Type= 6, Freq= 0, CH_1, rank 0
2963 23:09:57.779312 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2964 23:09:57.779958 ==
2965 23:09:57.782339 [Gating] SW mode calibration
2966 23:09:57.789152 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2967 23:09:57.792600 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2968 23:09:57.798989 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2969 23:09:57.802287 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2970 23:09:57.808795 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2971 23:09:57.812393 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2972 23:09:57.815663 0 11 16 | B1->B0 | 3232 2828 | 0 0 | (0 1) (1 0)
2973 23:09:57.818867 0 11 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2974 23:09:57.825246 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2975 23:09:57.829081 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2976 23:09:57.832109 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2977 23:09:57.838896 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2978 23:09:57.842017 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2979 23:09:57.845396 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2980 23:09:57.852231 0 12 16 | B1->B0 | 3838 4545 | 1 0 | (0 0) (0 0)
2981 23:09:57.855355 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2982 23:09:57.858498 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2983 23:09:57.865196 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2984 23:09:57.868752 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2985 23:09:57.872137 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2986 23:09:57.878768 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2987 23:09:57.881843 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2988 23:09:57.885407 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2989 23:09:57.892139 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2990 23:09:57.895761 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 23:09:57.898938 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 23:09:57.901870 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 23:09:57.908797 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 23:09:57.912076 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 23:09:57.915502 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 23:09:57.922060 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 23:09:57.925217 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2998 23:09:57.928587 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 23:09:57.935317 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3000 23:09:57.938585 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3001 23:09:57.942328 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3002 23:09:57.948682 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3003 23:09:57.952050 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3004 23:09:57.955313 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3005 23:09:57.962375 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3006 23:09:57.962936 Total UI for P1: 0, mck2ui 16
3007 23:09:57.968561 best dqsien dly found for B0: ( 0, 15, 14)
3008 23:09:57.971899 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3009 23:09:57.975549 Total UI for P1: 0, mck2ui 16
3010 23:09:57.979044 best dqsien dly found for B1: ( 0, 15, 18)
3011 23:09:57.982343 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3012 23:09:57.985627 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3013 23:09:57.986184
3014 23:09:57.989386 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3015 23:09:57.992315 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3016 23:09:57.995521 [Gating] SW calibration Done
3017 23:09:57.996073 ==
3018 23:09:57.999197 Dram Type= 6, Freq= 0, CH_1, rank 0
3019 23:09:58.001950 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3020 23:09:58.005367 ==
3021 23:09:58.005829 RX Vref Scan: 0
3022 23:09:58.006189
3023 23:09:58.008466 RX Vref 0 -> 0, step: 1
3024 23:09:58.008969
3025 23:09:58.009330 RX Delay -40 -> 252, step: 8
3026 23:09:58.015226 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3027 23:09:58.018832 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3028 23:09:58.021900 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3029 23:09:58.025379 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3030 23:09:58.028793 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3031 23:09:58.035563 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3032 23:09:58.039006 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3033 23:09:58.042131 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3034 23:09:58.045444 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3035 23:09:58.049347 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3036 23:09:58.056237 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3037 23:09:58.058767 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3038 23:09:58.062712 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3039 23:09:58.065812 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3040 23:09:58.069012 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3041 23:09:58.075837 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3042 23:09:58.076405 ==
3043 23:09:58.078803 Dram Type= 6, Freq= 0, CH_1, rank 0
3044 23:09:58.082250 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3045 23:09:58.082805 ==
3046 23:09:58.083170 DQS Delay:
3047 23:09:58.085604 DQS0 = 0, DQS1 = 0
3048 23:09:58.086159 DQM Delay:
3049 23:09:58.089331 DQM0 = 116, DQM1 = 108
3050 23:09:58.089883 DQ Delay:
3051 23:09:58.091931 DQ0 =123, DQ1 =107, DQ2 =107, DQ3 =115
3052 23:09:58.095732 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3053 23:09:58.099015 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3054 23:09:58.102608 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3055 23:09:58.103162
3056 23:09:58.103526
3057 23:09:58.103860 ==
3058 23:09:58.105300 Dram Type= 6, Freq= 0, CH_1, rank 0
3059 23:09:58.112493 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3060 23:09:58.113106 ==
3061 23:09:58.113477
3062 23:09:58.113833
3063 23:09:58.114290 TX Vref Scan disable
3064 23:09:58.115917 == TX Byte 0 ==
3065 23:09:58.119189 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3066 23:09:58.125571 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3067 23:09:58.126067 == TX Byte 1 ==
3068 23:09:58.129051 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3069 23:09:58.132504 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3070 23:09:58.135863 ==
3071 23:09:58.139337 Dram Type= 6, Freq= 0, CH_1, rank 0
3072 23:09:58.142536 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3073 23:09:58.143111 ==
3074 23:09:58.153568 TX Vref=22, minBit 3, minWin=24, winSum=412
3075 23:09:58.157002 TX Vref=24, minBit 3, minWin=24, winSum=420
3076 23:09:58.160090 TX Vref=26, minBit 3, minWin=25, winSum=424
3077 23:09:58.163703 TX Vref=28, minBit 3, minWin=26, winSum=429
3078 23:09:58.166958 TX Vref=30, minBit 1, minWin=26, winSum=431
3079 23:09:58.173628 TX Vref=32, minBit 9, minWin=26, winSum=429
3080 23:09:58.176983 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
3081 23:09:58.177555
3082 23:09:58.179856 Final TX Range 1 Vref 30
3083 23:09:58.180329
3084 23:09:58.180912 ==
3085 23:09:58.183552 Dram Type= 6, Freq= 0, CH_1, rank 0
3086 23:09:58.186833 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3087 23:09:58.187406 ==
3088 23:09:58.187891
3089 23:09:58.190010
3090 23:09:58.190477 TX Vref Scan disable
3091 23:09:58.193366 == TX Byte 0 ==
3092 23:09:58.196699 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3093 23:09:58.200194 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3094 23:09:58.203463 == TX Byte 1 ==
3095 23:09:58.206780 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3096 23:09:58.210102 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3097 23:09:58.210676
3098 23:09:58.213268 [DATLAT]
3099 23:09:58.213741 Freq=1200, CH1 RK0
3100 23:09:58.214221
3101 23:09:58.216674 DATLAT Default: 0xd
3102 23:09:58.217182 0, 0xFFFF, sum = 0
3103 23:09:58.219834 1, 0xFFFF, sum = 0
3104 23:09:58.220317 2, 0xFFFF, sum = 0
3105 23:09:58.223291 3, 0xFFFF, sum = 0
3106 23:09:58.223770 4, 0xFFFF, sum = 0
3107 23:09:58.226577 5, 0xFFFF, sum = 0
3108 23:09:58.227060 6, 0xFFFF, sum = 0
3109 23:09:58.230084 7, 0xFFFF, sum = 0
3110 23:09:58.230665 8, 0xFFFF, sum = 0
3111 23:09:58.233456 9, 0xFFFF, sum = 0
3112 23:09:58.236654 10, 0xFFFF, sum = 0
3113 23:09:58.237270 11, 0x0, sum = 1
3114 23:09:58.237769 12, 0x0, sum = 2
3115 23:09:58.240082 13, 0x0, sum = 3
3116 23:09:58.240661 14, 0x0, sum = 4
3117 23:09:58.243534 best_step = 12
3118 23:09:58.244099
3119 23:09:58.244586 ==
3120 23:09:58.246595 Dram Type= 6, Freq= 0, CH_1, rank 0
3121 23:09:58.250049 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3122 23:09:58.250620 ==
3123 23:09:58.253338 RX Vref Scan: 1
3124 23:09:58.253902
3125 23:09:58.254384 Set Vref Range= 32 -> 127
3126 23:09:58.256875
3127 23:09:58.257442 RX Vref 32 -> 127, step: 1
3128 23:09:58.257929
3129 23:09:58.259901 RX Delay -29 -> 252, step: 4
3130 23:09:58.260468
3131 23:09:58.263227 Set Vref, RX VrefLevel [Byte0]: 32
3132 23:09:58.266791 [Byte1]: 32
3133 23:09:58.269727
3134 23:09:58.270205 Set Vref, RX VrefLevel [Byte0]: 33
3135 23:09:58.273290 [Byte1]: 33
3136 23:09:58.277939
3137 23:09:58.278508 Set Vref, RX VrefLevel [Byte0]: 34
3138 23:09:58.281100 [Byte1]: 34
3139 23:09:58.286024
3140 23:09:58.286590 Set Vref, RX VrefLevel [Byte0]: 35
3141 23:09:58.289037 [Byte1]: 35
3142 23:09:58.293598
3143 23:09:58.294166 Set Vref, RX VrefLevel [Byte0]: 36
3144 23:09:58.297101 [Byte1]: 36
3145 23:09:58.301873
3146 23:09:58.302442 Set Vref, RX VrefLevel [Byte0]: 37
3147 23:09:58.304829 [Byte1]: 37
3148 23:09:58.309421
3149 23:09:58.309891 Set Vref, RX VrefLevel [Byte0]: 38
3150 23:09:58.312999 [Byte1]: 38
3151 23:09:58.317417
3152 23:09:58.317889 Set Vref, RX VrefLevel [Byte0]: 39
3153 23:09:58.320882 [Byte1]: 39
3154 23:09:58.325967
3155 23:09:58.326437 Set Vref, RX VrefLevel [Byte0]: 40
3156 23:09:58.328842 [Byte1]: 40
3157 23:09:58.333690
3158 23:09:58.334252 Set Vref, RX VrefLevel [Byte0]: 41
3159 23:09:58.336807 [Byte1]: 41
3160 23:09:58.341490
3161 23:09:58.342061 Set Vref, RX VrefLevel [Byte0]: 42
3162 23:09:58.344966 [Byte1]: 42
3163 23:09:58.349453
3164 23:09:58.350044 Set Vref, RX VrefLevel [Byte0]: 43
3165 23:09:58.352397 [Byte1]: 43
3166 23:09:58.357366
3167 23:09:58.357940 Set Vref, RX VrefLevel [Byte0]: 44
3168 23:09:58.361029 [Byte1]: 44
3169 23:09:58.365752
3170 23:09:58.366325 Set Vref, RX VrefLevel [Byte0]: 45
3171 23:09:58.369010 [Byte1]: 45
3172 23:09:58.373211
3173 23:09:58.373684 Set Vref, RX VrefLevel [Byte0]: 46
3174 23:09:58.376639 [Byte1]: 46
3175 23:09:58.381413
3176 23:09:58.381990 Set Vref, RX VrefLevel [Byte0]: 47
3177 23:09:58.384644 [Byte1]: 47
3178 23:09:58.389413
3179 23:09:58.389982 Set Vref, RX VrefLevel [Byte0]: 48
3180 23:09:58.392749 [Byte1]: 48
3181 23:09:58.397337
3182 23:09:58.397902 Set Vref, RX VrefLevel [Byte0]: 49
3183 23:09:58.403600 [Byte1]: 49
3184 23:09:58.404183
3185 23:09:58.406876 Set Vref, RX VrefLevel [Byte0]: 50
3186 23:09:58.410040 [Byte1]: 50
3187 23:09:58.410513
3188 23:09:58.413408 Set Vref, RX VrefLevel [Byte0]: 51
3189 23:09:58.416662 [Byte1]: 51
3190 23:09:58.420974
3191 23:09:58.421535 Set Vref, RX VrefLevel [Byte0]: 52
3192 23:09:58.424338 [Byte1]: 52
3193 23:09:58.429340
3194 23:09:58.429915 Set Vref, RX VrefLevel [Byte0]: 53
3195 23:09:58.432665 [Byte1]: 53
3196 23:09:58.437284
3197 23:09:58.437846 Set Vref, RX VrefLevel [Byte0]: 54
3198 23:09:58.440268 [Byte1]: 54
3199 23:09:58.445056
3200 23:09:58.445619 Set Vref, RX VrefLevel [Byte0]: 55
3201 23:09:58.447932 [Byte1]: 55
3202 23:09:58.452833
3203 23:09:58.453416 Set Vref, RX VrefLevel [Byte0]: 56
3204 23:09:58.456363 [Byte1]: 56
3205 23:09:58.460953
3206 23:09:58.461515 Set Vref, RX VrefLevel [Byte0]: 57
3207 23:09:58.463854 [Byte1]: 57
3208 23:09:58.468795
3209 23:09:58.469357 Set Vref, RX VrefLevel [Byte0]: 58
3210 23:09:58.472065 [Byte1]: 58
3211 23:09:58.477011
3212 23:09:58.477573 Set Vref, RX VrefLevel [Byte0]: 59
3213 23:09:58.479769 [Byte1]: 59
3214 23:09:58.484783
3215 23:09:58.485258 Set Vref, RX VrefLevel [Byte0]: 60
3216 23:09:58.487664 [Byte1]: 60
3217 23:09:58.492653
3218 23:09:58.493268 Set Vref, RX VrefLevel [Byte0]: 61
3219 23:09:58.496395 [Byte1]: 61
3220 23:09:58.500916
3221 23:09:58.501478 Set Vref, RX VrefLevel [Byte0]: 62
3222 23:09:58.503949 [Byte1]: 62
3223 23:09:58.508337
3224 23:09:58.508954 Set Vref, RX VrefLevel [Byte0]: 63
3225 23:09:58.511757 [Byte1]: 63
3226 23:09:58.516687
3227 23:09:58.517296 Set Vref, RX VrefLevel [Byte0]: 64
3228 23:09:58.519845 [Byte1]: 64
3229 23:09:58.524269
3230 23:09:58.524881 Set Vref, RX VrefLevel [Byte0]: 65
3231 23:09:58.527571 [Byte1]: 65
3232 23:09:58.532357
3233 23:09:58.532967 Set Vref, RX VrefLevel [Byte0]: 66
3234 23:09:58.536175 [Byte1]: 66
3235 23:09:58.540475
3236 23:09:58.541221 Final RX Vref Byte 0 = 56 to rank0
3237 23:09:58.543702 Final RX Vref Byte 1 = 48 to rank0
3238 23:09:58.547136 Final RX Vref Byte 0 = 56 to rank1
3239 23:09:58.550390 Final RX Vref Byte 1 = 48 to rank1==
3240 23:09:58.553496 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 23:09:58.560685 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3242 23:09:58.561275 ==
3243 23:09:58.561643 DQS Delay:
3244 23:09:58.561984 DQS0 = 0, DQS1 = 0
3245 23:09:58.563307 DQM Delay:
3246 23:09:58.563768 DQM0 = 115, DQM1 = 104
3247 23:09:58.566877 DQ Delay:
3248 23:09:58.570093 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3249 23:09:58.573862 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3250 23:09:58.577161 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3251 23:09:58.581164 DQ12 =112, DQ13 =116, DQ14 =112, DQ15 =114
3252 23:09:58.581764
3253 23:09:58.582251
3254 23:09:58.586944 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
3255 23:09:58.590459 CH1 RK0: MR19=404, MR18=1515
3256 23:09:58.597142 CH1_RK0: MR19=0x404, MR18=0x1515, DQSOSC=401, MR23=63, INC=40, DEC=27
3257 23:09:58.597731
3258 23:09:58.600581 ----->DramcWriteLeveling(PI) begin...
3259 23:09:58.601228 ==
3260 23:09:58.603630 Dram Type= 6, Freq= 0, CH_1, rank 1
3261 23:09:58.607403 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3262 23:09:58.607990 ==
3263 23:09:58.610239 Write leveling (Byte 0): 21 => 21
3264 23:09:58.613497 Write leveling (Byte 1): 20 => 20
3265 23:09:58.617006 DramcWriteLeveling(PI) end<-----
3266 23:09:58.617483
3267 23:09:58.617958 ==
3268 23:09:58.620426 Dram Type= 6, Freq= 0, CH_1, rank 1
3269 23:09:58.627011 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3270 23:09:58.627549 ==
3271 23:09:58.627910 [Gating] SW mode calibration
3272 23:09:58.637709 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3273 23:09:58.640553 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3274 23:09:58.643764 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3275 23:09:58.650769 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3276 23:09:58.653655 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3277 23:09:58.657371 0 11 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
3278 23:09:58.664389 0 11 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
3279 23:09:58.667316 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3280 23:09:58.670912 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3281 23:09:58.677615 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3282 23:09:58.680578 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3283 23:09:58.684197 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3284 23:09:58.690679 0 12 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3285 23:09:58.694157 0 12 12 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
3286 23:09:58.696882 0 12 16 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
3287 23:09:58.703844 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3288 23:09:58.707153 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3289 23:09:58.710318 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3290 23:09:58.717148 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3291 23:09:58.720263 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3292 23:09:58.723604 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3293 23:09:58.729896 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3294 23:09:58.733439 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3295 23:09:58.736600 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3296 23:09:58.743495 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3297 23:09:58.746583 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3298 23:09:58.749833 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3299 23:09:58.753384 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3300 23:09:58.759947 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3301 23:09:58.763208 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3302 23:09:58.766116 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3303 23:09:58.773114 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3304 23:09:58.776566 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3305 23:09:58.779749 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3306 23:09:58.786374 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3307 23:09:58.789595 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3308 23:09:58.793097 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3309 23:09:58.799474 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3310 23:09:58.803023 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3311 23:09:58.806167 Total UI for P1: 0, mck2ui 16
3312 23:09:58.809971 best dqsien dly found for B0: ( 0, 15, 12)
3313 23:09:58.813090 Total UI for P1: 0, mck2ui 16
3314 23:09:58.816558 best dqsien dly found for B1: ( 0, 15, 14)
3315 23:09:58.819670 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3316 23:09:58.823072 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3317 23:09:58.823620
3318 23:09:58.826216 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3319 23:09:58.833026 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3320 23:09:58.833482 [Gating] SW calibration Done
3321 23:09:58.833840 ==
3322 23:09:58.835872 Dram Type= 6, Freq= 0, CH_1, rank 1
3323 23:09:58.842709 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3324 23:09:58.843246 ==
3325 23:09:58.843603 RX Vref Scan: 0
3326 23:09:58.843939
3327 23:09:58.846011 RX Vref 0 -> 0, step: 1
3328 23:09:58.846462
3329 23:09:58.849520 RX Delay -40 -> 252, step: 8
3330 23:09:58.852585 iDelay=208, Bit 0, Center 115 (40 ~ 191) 152
3331 23:09:58.856005 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3332 23:09:58.859810 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3333 23:09:58.862695 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3334 23:09:58.869741 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3335 23:09:58.872932 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3336 23:09:58.876189 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3337 23:09:58.879691 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3338 23:09:58.882686 iDelay=208, Bit 8, Center 91 (16 ~ 167) 152
3339 23:09:58.889576 iDelay=208, Bit 9, Center 91 (16 ~ 167) 152
3340 23:09:58.892891 iDelay=208, Bit 10, Center 107 (32 ~ 183) 152
3341 23:09:58.895949 iDelay=208, Bit 11, Center 99 (24 ~ 175) 152
3342 23:09:58.899225 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3343 23:09:58.902966 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3344 23:09:58.909287 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3345 23:09:58.912561 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3346 23:09:58.913170 ==
3347 23:09:58.916539 Dram Type= 6, Freq= 0, CH_1, rank 1
3348 23:09:58.920703 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3349 23:09:58.921215 ==
3350 23:09:58.922294 DQS Delay:
3351 23:09:58.922748 DQS0 = 0, DQS1 = 0
3352 23:09:58.923104 DQM Delay:
3353 23:09:58.925870 DQM0 = 116, DQM1 = 105
3354 23:09:58.926343 DQ Delay:
3355 23:09:58.929225 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
3356 23:09:58.932494 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3357 23:09:58.936151 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3358 23:09:58.942774 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3359 23:09:58.943347
3360 23:09:58.943709
3361 23:09:58.944040 ==
3362 23:09:58.946147 Dram Type= 6, Freq= 0, CH_1, rank 1
3363 23:09:58.949000 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3364 23:09:58.949534 ==
3365 23:09:58.949899
3366 23:09:58.950237
3367 23:09:58.952538 TX Vref Scan disable
3368 23:09:58.953161 == TX Byte 0 ==
3369 23:09:58.959427 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3370 23:09:58.962987 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3371 23:09:58.963543 == TX Byte 1 ==
3372 23:09:58.969620 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3373 23:09:58.972769 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3374 23:09:58.973234 ==
3375 23:09:58.976380 Dram Type= 6, Freq= 0, CH_1, rank 1
3376 23:09:58.979496 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3377 23:09:58.980055 ==
3378 23:09:58.992041 TX Vref=22, minBit 0, minWin=25, winSum=423
3379 23:09:58.995022 TX Vref=24, minBit 9, minWin=25, winSum=425
3380 23:09:58.998044 TX Vref=26, minBit 3, minWin=26, winSum=431
3381 23:09:59.001593 TX Vref=28, minBit 3, minWin=26, winSum=428
3382 23:09:59.004913 TX Vref=30, minBit 9, minWin=26, winSum=433
3383 23:09:59.012027 TX Vref=32, minBit 0, minWin=26, winSum=432
3384 23:09:59.014695 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3385 23:09:59.015251
3386 23:09:59.018223 Final TX Range 1 Vref 30
3387 23:09:59.019012
3388 23:09:59.019404 ==
3389 23:09:59.021199 Dram Type= 6, Freq= 0, CH_1, rank 1
3390 23:09:59.025163 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3391 23:09:59.025719 ==
3392 23:09:59.028000
3393 23:09:59.028456
3394 23:09:59.028864 TX Vref Scan disable
3395 23:09:59.031065 == TX Byte 0 ==
3396 23:09:59.035090 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3397 23:09:59.038396 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3398 23:09:59.041088 == TX Byte 1 ==
3399 23:09:59.044760 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3400 23:09:59.048088 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3401 23:09:59.051666
3402 23:09:59.052229 [DATLAT]
3403 23:09:59.052833 Freq=1200, CH1 RK1
3404 23:09:59.053295
3405 23:09:59.054473 DATLAT Default: 0xc
3406 23:09:59.054946 0, 0xFFFF, sum = 0
3407 23:09:59.058071 1, 0xFFFF, sum = 0
3408 23:09:59.058648 2, 0xFFFF, sum = 0
3409 23:09:59.061668 3, 0xFFFF, sum = 0
3410 23:09:59.062243 4, 0xFFFF, sum = 0
3411 23:09:59.065084 5, 0xFFFF, sum = 0
3412 23:09:59.065698 6, 0xFFFF, sum = 0
3413 23:09:59.068009 7, 0xFFFF, sum = 0
3414 23:09:59.071107 8, 0xFFFF, sum = 0
3415 23:09:59.071590 9, 0xFFFF, sum = 0
3416 23:09:59.074561 10, 0xFFFF, sum = 0
3417 23:09:59.075138 11, 0x0, sum = 1
3418 23:09:59.078088 12, 0x0, sum = 2
3419 23:09:59.078670 13, 0x0, sum = 3
3420 23:09:59.079161 14, 0x0, sum = 4
3421 23:09:59.081016 best_step = 12
3422 23:09:59.081484
3423 23:09:59.081974 ==
3424 23:09:59.084673 Dram Type= 6, Freq= 0, CH_1, rank 1
3425 23:09:59.088135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3426 23:09:59.088744 ==
3427 23:09:59.091539 RX Vref Scan: 0
3428 23:09:59.092108
3429 23:09:59.092596 RX Vref 0 -> 0, step: 1
3430 23:09:59.093095
3431 23:09:59.094477 RX Delay -29 -> 252, step: 4
3432 23:09:59.101619 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3433 23:09:59.104741 iDelay=199, Bit 1, Center 110 (39 ~ 182) 144
3434 23:09:59.108220 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3435 23:09:59.111523 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3436 23:09:59.115221 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3437 23:09:59.121582 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3438 23:09:59.124770 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3439 23:09:59.128336 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3440 23:09:59.131735 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3441 23:09:59.135234 iDelay=199, Bit 9, Center 90 (23 ~ 158) 136
3442 23:09:59.141534 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3443 23:09:59.145163 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3444 23:09:59.148502 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3445 23:09:59.151752 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3446 23:09:59.155303 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3447 23:09:59.161555 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3448 23:09:59.162109 ==
3449 23:09:59.165082 Dram Type= 6, Freq= 0, CH_1, rank 1
3450 23:09:59.168138 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3451 23:09:59.168596 ==
3452 23:09:59.168992 DQS Delay:
3453 23:09:59.171642 DQS0 = 0, DQS1 = 0
3454 23:09:59.172093 DQM Delay:
3455 23:09:59.175169 DQM0 = 114, DQM1 = 103
3456 23:09:59.175727 DQ Delay:
3457 23:09:59.178484 DQ0 =114, DQ1 =110, DQ2 =108, DQ3 =112
3458 23:09:59.181647 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3459 23:09:59.185100 DQ8 =86, DQ9 =90, DQ10 =106, DQ11 =98
3460 23:09:59.188363 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =110
3461 23:09:59.188965
3462 23:09:59.189329
3463 23:09:59.198417 [DQSOSCAuto] RK1, (LSB)MR18= 0xa0a, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
3464 23:09:59.201488 CH1 RK1: MR19=404, MR18=A0A
3465 23:09:59.205587 CH1_RK1: MR19=0x404, MR18=0xA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3466 23:09:59.208061 [RxdqsGatingPostProcess] freq 1200
3467 23:09:59.214927 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3468 23:09:59.218463 Pre-setting of DQS Precalculation
3469 23:09:59.221744 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3470 23:09:59.232224 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3471 23:09:59.238577 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3472 23:09:59.239149
3473 23:09:59.239739
3474 23:09:59.242103 [Calibration Summary] 2400 Mbps
3475 23:09:59.242661 CH 0, Rank 0
3476 23:09:59.244973 SW Impedance : PASS
3477 23:09:59.245431 DUTY Scan : NO K
3478 23:09:59.248591 ZQ Calibration : PASS
3479 23:09:59.251752 Jitter Meter : NO K
3480 23:09:59.252210 CBT Training : PASS
3481 23:09:59.255255 Write leveling : PASS
3482 23:09:59.258745 RX DQS gating : PASS
3483 23:09:59.259301 RX DQ/DQS(RDDQC) : PASS
3484 23:09:59.262102 TX DQ/DQS : PASS
3485 23:09:59.262656 RX DATLAT : PASS
3486 23:09:59.265226 RX DQ/DQS(Engine): PASS
3487 23:09:59.269063 TX OE : NO K
3488 23:09:59.269621 All Pass.
3489 23:09:59.269982
3490 23:09:59.270317 CH 0, Rank 1
3491 23:09:59.271935 SW Impedance : PASS
3492 23:09:59.275288 DUTY Scan : NO K
3493 23:09:59.275842 ZQ Calibration : PASS
3494 23:09:59.278675 Jitter Meter : NO K
3495 23:09:59.282114 CBT Training : PASS
3496 23:09:59.282575 Write leveling : PASS
3497 23:09:59.285480 RX DQS gating : PASS
3498 23:09:59.288799 RX DQ/DQS(RDDQC) : PASS
3499 23:09:59.289440 TX DQ/DQS : PASS
3500 23:09:59.292189 RX DATLAT : PASS
3501 23:09:59.292770 RX DQ/DQS(Engine): PASS
3502 23:09:59.295694 TX OE : NO K
3503 23:09:59.296255 All Pass.
3504 23:09:59.296618
3505 23:09:59.298737 CH 1, Rank 0
3506 23:09:59.299290 SW Impedance : PASS
3507 23:09:59.302078 DUTY Scan : NO K
3508 23:09:59.305578 ZQ Calibration : PASS
3509 23:09:59.306133 Jitter Meter : NO K
3510 23:09:59.308832 CBT Training : PASS
3511 23:09:59.312177 Write leveling : PASS
3512 23:09:59.312769 RX DQS gating : PASS
3513 23:09:59.315044 RX DQ/DQS(RDDQC) : PASS
3514 23:09:59.318824 TX DQ/DQS : PASS
3515 23:09:59.319378 RX DATLAT : PASS
3516 23:09:59.321951 RX DQ/DQS(Engine): PASS
3517 23:09:59.325158 TX OE : NO K
3518 23:09:59.325634 All Pass.
3519 23:09:59.325995
3520 23:09:59.326326 CH 1, Rank 1
3521 23:09:59.328818 SW Impedance : PASS
3522 23:09:59.331990 DUTY Scan : NO K
3523 23:09:59.332448 ZQ Calibration : PASS
3524 23:09:59.335312 Jitter Meter : NO K
3525 23:09:59.338708 CBT Training : PASS
3526 23:09:59.339267 Write leveling : PASS
3527 23:09:59.341657 RX DQS gating : PASS
3528 23:09:59.342114 RX DQ/DQS(RDDQC) : PASS
3529 23:09:59.345093 TX DQ/DQS : PASS
3530 23:09:59.348447 RX DATLAT : PASS
3531 23:09:59.348956 RX DQ/DQS(Engine): PASS
3532 23:09:59.351572 TX OE : NO K
3533 23:09:59.352032 All Pass.
3534 23:09:59.352390
3535 23:09:59.355306 DramC Write-DBI off
3536 23:09:59.358591 PER_BANK_REFRESH: Hybrid Mode
3537 23:09:59.359049 TX_TRACKING: ON
3538 23:09:59.368544 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3539 23:09:59.371819 [FAST_K] Save calibration result to emmc
3540 23:09:59.375099 dramc_set_vcore_voltage set vcore to 650000
3541 23:09:59.378258 Read voltage for 600, 5
3542 23:09:59.378712 Vio18 = 0
3543 23:09:59.379073 Vcore = 650000
3544 23:09:59.381562 Vdram = 0
3545 23:09:59.382017 Vddq = 0
3546 23:09:59.382376 Vmddr = 0
3547 23:09:59.388949 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3548 23:09:59.392128 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3549 23:09:59.395206 MEM_TYPE=3, freq_sel=19
3550 23:09:59.398427 sv_algorithm_assistance_LP4_1600
3551 23:09:59.401429 ============ PULL DRAM RESETB DOWN ============
3552 23:09:59.408702 ========== PULL DRAM RESETB DOWN end =========
3553 23:09:59.411644 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3554 23:09:59.414722 ===================================
3555 23:09:59.418665 LPDDR4 DRAM CONFIGURATION
3556 23:09:59.421304 ===================================
3557 23:09:59.421766 EX_ROW_EN[0] = 0x0
3558 23:09:59.424945 EX_ROW_EN[1] = 0x0
3559 23:09:59.425404 LP4Y_EN = 0x0
3560 23:09:59.428039 WORK_FSP = 0x0
3561 23:09:59.428497 WL = 0x2
3562 23:09:59.431391 RL = 0x2
3563 23:09:59.431942 BL = 0x2
3564 23:09:59.434774 RPST = 0x0
3565 23:09:59.435326 RD_PRE = 0x0
3566 23:09:59.438261 WR_PRE = 0x1
3567 23:09:59.438811 WR_PST = 0x0
3568 23:09:59.441238 DBI_WR = 0x0
3569 23:09:59.445185 DBI_RD = 0x0
3570 23:09:59.445735 OTF = 0x1
3571 23:09:59.448113 ===================================
3572 23:09:59.451153 ===================================
3573 23:09:59.451616 ANA top config
3574 23:09:59.454721 ===================================
3575 23:09:59.457595 DLL_ASYNC_EN = 0
3576 23:09:59.461084 ALL_SLAVE_EN = 1
3577 23:09:59.465022 NEW_RANK_MODE = 1
3578 23:09:59.467699 DLL_IDLE_MODE = 1
3579 23:09:59.468249 LP45_APHY_COMB_EN = 1
3580 23:09:59.471461 TX_ODT_DIS = 1
3581 23:09:59.474098 NEW_8X_MODE = 1
3582 23:09:59.477579 ===================================
3583 23:09:59.481298 ===================================
3584 23:09:59.484231 data_rate = 1200
3585 23:09:59.487683 CKR = 1
3586 23:09:59.488144 DQ_P2S_RATIO = 8
3587 23:09:59.490879 ===================================
3588 23:09:59.494704 CA_P2S_RATIO = 8
3589 23:09:59.497894 DQ_CA_OPEN = 0
3590 23:09:59.500844 DQ_SEMI_OPEN = 0
3591 23:09:59.504290 CA_SEMI_OPEN = 0
3592 23:09:59.507648 CA_FULL_RATE = 0
3593 23:09:59.508206 DQ_CKDIV4_EN = 1
3594 23:09:59.510779 CA_CKDIV4_EN = 1
3595 23:09:59.513960 CA_PREDIV_EN = 0
3596 23:09:59.517201 PH8_DLY = 0
3597 23:09:59.521145 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3598 23:09:59.524061 DQ_AAMCK_DIV = 4
3599 23:09:59.524522 CA_AAMCK_DIV = 4
3600 23:09:59.527519 CA_ADMCK_DIV = 4
3601 23:09:59.530624 DQ_TRACK_CA_EN = 0
3602 23:09:59.534518 CA_PICK = 600
3603 23:09:59.537664 CA_MCKIO = 600
3604 23:09:59.541182 MCKIO_SEMI = 0
3605 23:09:59.544289 PLL_FREQ = 2288
3606 23:09:59.544894 DQ_UI_PI_RATIO = 32
3607 23:09:59.547764 CA_UI_PI_RATIO = 0
3608 23:09:59.550637 ===================================
3609 23:09:59.554386 ===================================
3610 23:09:59.557416 memory_type:LPDDR4
3611 23:09:59.560967 GP_NUM : 10
3612 23:09:59.561528 SRAM_EN : 1
3613 23:09:59.563817 MD32_EN : 0
3614 23:09:59.567686 ===================================
3615 23:09:59.570552 [ANA_INIT] >>>>>>>>>>>>>>
3616 23:09:59.571018 <<<<<< [CONFIGURE PHASE]: ANA_TX
3617 23:09:59.573989 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3618 23:09:59.577070 ===================================
3619 23:09:59.580447 data_rate = 1200,PCW = 0X5800
3620 23:09:59.583658 ===================================
3621 23:09:59.587113 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3622 23:09:59.593389 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3623 23:09:59.600197 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3624 23:09:59.603167 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3625 23:09:59.606626 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3626 23:09:59.609823 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3627 23:09:59.613200 [ANA_INIT] flow start
3628 23:09:59.613357 [ANA_INIT] PLL >>>>>>>>
3629 23:09:59.616785 [ANA_INIT] PLL <<<<<<<<
3630 23:09:59.619893 [ANA_INIT] MIDPI >>>>>>>>
3631 23:09:59.623367 [ANA_INIT] MIDPI <<<<<<<<
3632 23:09:59.623864 [ANA_INIT] DLL >>>>>>>>
3633 23:09:59.626716 [ANA_INIT] flow end
3634 23:09:59.630435 ============ LP4 DIFF to SE enter ============
3635 23:09:59.633260 ============ LP4 DIFF to SE exit ============
3636 23:09:59.636767 [ANA_INIT] <<<<<<<<<<<<<
3637 23:09:59.639879 [Flow] Enable top DCM control >>>>>
3638 23:09:59.643384 [Flow] Enable top DCM control <<<<<
3639 23:09:59.646312 Enable DLL master slave shuffle
3640 23:09:59.652993 ==============================================================
3641 23:09:59.653173 Gating Mode config
3642 23:09:59.659435 ==============================================================
3643 23:09:59.659587 Config description:
3644 23:09:59.669407 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3645 23:09:59.676064 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3646 23:09:59.682805 SELPH_MODE 0: By rank 1: By Phase
3647 23:09:59.686134 ==============================================================
3648 23:09:59.689534 GAT_TRACK_EN = 1
3649 23:09:59.692520 RX_GATING_MODE = 2
3650 23:09:59.695996 RX_GATING_TRACK_MODE = 2
3651 23:09:59.699369 SELPH_MODE = 1
3652 23:09:59.702585 PICG_EARLY_EN = 1
3653 23:09:59.705912 VALID_LAT_VALUE = 1
3654 23:09:59.709089 ==============================================================
3655 23:09:59.712290 Enter into Gating configuration >>>>
3656 23:09:59.716071 Exit from Gating configuration <<<<
3657 23:09:59.719356 Enter into DVFS_PRE_config >>>>>
3658 23:09:59.732543 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3659 23:09:59.735969 Exit from DVFS_PRE_config <<<<<
3660 23:09:59.739375 Enter into PICG configuration >>>>
3661 23:09:59.742758 Exit from PICG configuration <<<<
3662 23:09:59.743175 [RX_INPUT] configuration >>>>>
3663 23:09:59.745915 [RX_INPUT] configuration <<<<<
3664 23:09:59.751992 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3665 23:09:59.755377 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3666 23:09:59.761928 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3667 23:09:59.768854 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3668 23:09:59.774994 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3669 23:09:59.782071 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3670 23:09:59.785353 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3671 23:09:59.788585 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3672 23:09:59.795480 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3673 23:09:59.798530 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3674 23:09:59.802116 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3675 23:09:59.808568 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3676 23:09:59.811757 ===================================
3677 23:09:59.811990 LPDDR4 DRAM CONFIGURATION
3678 23:09:59.815298 ===================================
3679 23:09:59.818705 EX_ROW_EN[0] = 0x0
3680 23:09:59.818978 EX_ROW_EN[1] = 0x0
3681 23:09:59.822021 LP4Y_EN = 0x0
3682 23:09:59.822248 WORK_FSP = 0x0
3683 23:09:59.824842 WL = 0x2
3684 23:09:59.825065 RL = 0x2
3685 23:09:59.829057 BL = 0x2
3686 23:09:59.832094 RPST = 0x0
3687 23:09:59.832552 RD_PRE = 0x0
3688 23:09:59.835126 WR_PRE = 0x1
3689 23:09:59.835583 WR_PST = 0x0
3690 23:09:59.838961 DBI_WR = 0x0
3691 23:09:59.839513 DBI_RD = 0x0
3692 23:09:59.841981 OTF = 0x1
3693 23:09:59.845273 ===================================
3694 23:09:59.848368 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3695 23:09:59.852291 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3696 23:09:59.855308 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3697 23:09:59.858208 ===================================
3698 23:09:59.861535 LPDDR4 DRAM CONFIGURATION
3699 23:09:59.864766 ===================================
3700 23:09:59.868405 EX_ROW_EN[0] = 0x10
3701 23:09:59.869006 EX_ROW_EN[1] = 0x0
3702 23:09:59.871668 LP4Y_EN = 0x0
3703 23:09:59.872127 WORK_FSP = 0x0
3704 23:09:59.874954 WL = 0x2
3705 23:09:59.875409 RL = 0x2
3706 23:09:59.878610 BL = 0x2
3707 23:09:59.879164 RPST = 0x0
3708 23:09:59.881682 RD_PRE = 0x0
3709 23:09:59.885349 WR_PRE = 0x1
3710 23:09:59.885901 WR_PST = 0x0
3711 23:09:59.888024 DBI_WR = 0x0
3712 23:09:59.888478 DBI_RD = 0x0
3713 23:09:59.891857 OTF = 0x1
3714 23:09:59.894773 ===================================
3715 23:09:59.897967 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3716 23:09:59.903503 nWR fixed to 30
3717 23:09:59.907046 [ModeRegInit_LP4] CH0 RK0
3718 23:09:59.907603 [ModeRegInit_LP4] CH0 RK1
3719 23:09:59.910049 [ModeRegInit_LP4] CH1 RK0
3720 23:09:59.913268 [ModeRegInit_LP4] CH1 RK1
3721 23:09:59.913725 match AC timing 16
3722 23:09:59.920793 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3723 23:09:59.923434 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3724 23:09:59.926444 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3725 23:09:59.933670 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3726 23:09:59.936620 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3727 23:09:59.937130 ==
3728 23:09:59.940130 Dram Type= 6, Freq= 0, CH_0, rank 0
3729 23:09:59.943163 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3730 23:09:59.943625 ==
3731 23:09:59.950190 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3732 23:09:59.956842 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3733 23:09:59.959805 [CA 0] Center 36 (6~66) winsize 61
3734 23:09:59.963516 [CA 1] Center 35 (5~66) winsize 62
3735 23:09:59.966883 [CA 2] Center 34 (4~65) winsize 62
3736 23:09:59.969974 [CA 3] Center 34 (3~65) winsize 63
3737 23:09:59.973176 [CA 4] Center 33 (3~64) winsize 62
3738 23:09:59.977094 [CA 5] Center 33 (3~64) winsize 62
3739 23:09:59.977668
3740 23:09:59.979835 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3741 23:09:59.980393
3742 23:09:59.982994 [CATrainingPosCal] consider 1 rank data
3743 23:09:59.986135 u2DelayCellTimex100 = 270/100 ps
3744 23:09:59.989700 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3745 23:09:59.993073 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3746 23:09:59.996294 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3747 23:09:59.999800 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3748 23:10:00.002764 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3749 23:10:00.010076 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3750 23:10:00.010629
3751 23:10:00.012861 CA PerBit enable=1, Macro0, CA PI delay=33
3752 23:10:00.013325
3753 23:10:00.015956 [CBTSetCACLKResult] CA Dly = 33
3754 23:10:00.016409 CS Dly: 6 (0~37)
3755 23:10:00.016820 ==
3756 23:10:00.019364 Dram Type= 6, Freq= 0, CH_0, rank 1
3757 23:10:00.022773 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3758 23:10:00.025927 ==
3759 23:10:00.029452 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3760 23:10:00.036577 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3761 23:10:00.039349 [CA 0] Center 35 (5~66) winsize 62
3762 23:10:00.042999 [CA 1] Center 35 (5~66) winsize 62
3763 23:10:00.046302 [CA 2] Center 34 (4~65) winsize 62
3764 23:10:00.049145 [CA 3] Center 34 (4~65) winsize 62
3765 23:10:00.052459 [CA 4] Center 33 (3~64) winsize 62
3766 23:10:00.056373 [CA 5] Center 33 (3~64) winsize 62
3767 23:10:00.056964
3768 23:10:00.059184 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3769 23:10:00.059732
3770 23:10:00.062533 [CATrainingPosCal] consider 2 rank data
3771 23:10:00.066454 u2DelayCellTimex100 = 270/100 ps
3772 23:10:00.069290 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3773 23:10:00.072262 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3774 23:10:00.075614 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3775 23:10:00.082488 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3776 23:10:00.085697 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3777 23:10:00.088933 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3778 23:10:00.089394
3779 23:10:00.092159 CA PerBit enable=1, Macro0, CA PI delay=33
3780 23:10:00.092616
3781 23:10:00.095588 [CBTSetCACLKResult] CA Dly = 33
3782 23:10:00.096044 CS Dly: 6 (0~37)
3783 23:10:00.096423
3784 23:10:00.098891 ----->DramcWriteLeveling(PI) begin...
3785 23:10:00.099366 ==
3786 23:10:00.102371 Dram Type= 6, Freq= 0, CH_0, rank 0
3787 23:10:00.109125 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3788 23:10:00.109680 ==
3789 23:10:00.112202 Write leveling (Byte 0): 30 => 30
3790 23:10:00.115386 Write leveling (Byte 1): 30 => 30
3791 23:10:00.118923 DramcWriteLeveling(PI) end<-----
3792 23:10:00.119381
3793 23:10:00.119741 ==
3794 23:10:00.122641 Dram Type= 6, Freq= 0, CH_0, rank 0
3795 23:10:00.125504 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3796 23:10:00.125972 ==
3797 23:10:00.128574 [Gating] SW mode calibration
3798 23:10:00.135480 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3799 23:10:00.139048 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3800 23:10:00.145484 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3801 23:10:00.149012 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3802 23:10:00.152306 0 5 8 | B1->B0 | 3333 3030 | 1 1 | (0 0) (0 0)
3803 23:10:00.158746 0 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3804 23:10:00.162285 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3805 23:10:00.165415 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3806 23:10:00.172053 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3807 23:10:00.175125 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3808 23:10:00.178747 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3809 23:10:00.185214 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3810 23:10:00.188816 0 6 8 | B1->B0 | 3030 3333 | 0 0 | (0 0) (0 0)
3811 23:10:00.191797 0 6 12 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
3812 23:10:00.198395 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3813 23:10:00.201385 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3814 23:10:00.205218 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3815 23:10:00.211852 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3816 23:10:00.215193 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3817 23:10:00.218294 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3818 23:10:00.225179 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3819 23:10:00.228641 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 23:10:00.231421 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 23:10:00.238102 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 23:10:00.241415 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 23:10:00.244691 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3824 23:10:00.251528 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3825 23:10:00.254640 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3826 23:10:00.257987 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3827 23:10:00.264461 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3828 23:10:00.267918 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3829 23:10:00.271210 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3830 23:10:00.277996 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3831 23:10:00.281058 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3832 23:10:00.284255 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3833 23:10:00.291084 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3834 23:10:00.294424 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3835 23:10:00.297482 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3836 23:10:00.300782 Total UI for P1: 0, mck2ui 16
3837 23:10:00.304219 best dqsien dly found for B0: ( 0, 9, 10)
3838 23:10:00.308026 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3839 23:10:00.310879 Total UI for P1: 0, mck2ui 16
3840 23:10:00.314185 best dqsien dly found for B1: ( 0, 9, 12)
3841 23:10:00.320704 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3842 23:10:00.324378 best DQS1 dly(MCK, UI, PI) = (0, 9, 12)
3843 23:10:00.324979
3844 23:10:00.327159 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3845 23:10:00.330896 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 12)
3846 23:10:00.334566 [Gating] SW calibration Done
3847 23:10:00.335116 ==
3848 23:10:00.337581 Dram Type= 6, Freq= 0, CH_0, rank 0
3849 23:10:00.340524 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3850 23:10:00.341033 ==
3851 23:10:00.344295 RX Vref Scan: 0
3852 23:10:00.344897
3853 23:10:00.345270 RX Vref 0 -> 0, step: 1
3854 23:10:00.345608
3855 23:10:00.346907 RX Delay -230 -> 252, step: 16
3856 23:10:00.353952 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3857 23:10:00.356875 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3858 23:10:00.360573 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3859 23:10:00.363934 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3860 23:10:00.367019 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
3861 23:10:00.373694 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3862 23:10:00.377025 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3863 23:10:00.380603 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3864 23:10:00.383731 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3865 23:10:00.387683 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3866 23:10:00.393668 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3867 23:10:00.397173 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3868 23:10:00.400198 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3869 23:10:00.403852 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3870 23:10:00.410076 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3871 23:10:00.413539 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3872 23:10:00.414108 ==
3873 23:10:00.417077 Dram Type= 6, Freq= 0, CH_0, rank 0
3874 23:10:00.420558 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3875 23:10:00.421167 ==
3876 23:10:00.423370 DQS Delay:
3877 23:10:00.423918 DQS0 = 0, DQS1 = 0
3878 23:10:00.426604 DQM Delay:
3879 23:10:00.427063 DQM0 = 37, DQM1 = 33
3880 23:10:00.427424 DQ Delay:
3881 23:10:00.430283 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3882 23:10:00.433160 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
3883 23:10:00.437173 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3884 23:10:00.440037 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3885 23:10:00.440496
3886 23:10:00.440894
3887 23:10:00.443325 ==
3888 23:10:00.443873 Dram Type= 6, Freq= 0, CH_0, rank 0
3889 23:10:00.450288 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3890 23:10:00.450839 ==
3891 23:10:00.451202
3892 23:10:00.451538
3893 23:10:00.453198 TX Vref Scan disable
3894 23:10:00.453654 == TX Byte 0 ==
3895 23:10:00.456445 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3896 23:10:00.463099 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3897 23:10:00.463656 == TX Byte 1 ==
3898 23:10:00.466523 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3899 23:10:00.473387 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3900 23:10:00.473938 ==
3901 23:10:00.476422 Dram Type= 6, Freq= 0, CH_0, rank 0
3902 23:10:00.479667 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3903 23:10:00.480126 ==
3904 23:10:00.480482
3905 23:10:00.480864
3906 23:10:00.483094 TX Vref Scan disable
3907 23:10:00.486315 == TX Byte 0 ==
3908 23:10:00.489663 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3909 23:10:00.492676 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3910 23:10:00.496070 == TX Byte 1 ==
3911 23:10:00.499720 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3912 23:10:00.503431 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3913 23:10:00.503990
3914 23:10:00.506561 [DATLAT]
3915 23:10:00.507112 Freq=600, CH0 RK0
3916 23:10:00.507479
3917 23:10:00.509637 DATLAT Default: 0x9
3918 23:10:00.510092 0, 0xFFFF, sum = 0
3919 23:10:00.513183 1, 0xFFFF, sum = 0
3920 23:10:00.513743 2, 0xFFFF, sum = 0
3921 23:10:00.516313 3, 0xFFFF, sum = 0
3922 23:10:00.516912 4, 0xFFFF, sum = 0
3923 23:10:00.519483 5, 0xFFFF, sum = 0
3924 23:10:00.519946 6, 0xFFFF, sum = 0
3925 23:10:00.522967 7, 0x0, sum = 1
3926 23:10:00.523474 8, 0x0, sum = 2
3927 23:10:00.526224 9, 0x0, sum = 3
3928 23:10:00.526692 10, 0x0, sum = 4
3929 23:10:00.529398 best_step = 8
3930 23:10:00.529875
3931 23:10:00.530333 ==
3932 23:10:00.532880 Dram Type= 6, Freq= 0, CH_0, rank 0
3933 23:10:00.536303 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3934 23:10:00.536909 ==
3935 23:10:00.537281 RX Vref Scan: 1
3936 23:10:00.537620
3937 23:10:00.539885 RX Vref 0 -> 0, step: 1
3938 23:10:00.540432
3939 23:10:00.542967 RX Delay -195 -> 252, step: 8
3940 23:10:00.543519
3941 23:10:00.546102 Set Vref, RX VrefLevel [Byte0]: 47
3942 23:10:00.549703 [Byte1]: 48
3943 23:10:00.550258
3944 23:10:00.552866 Final RX Vref Byte 0 = 47 to rank0
3945 23:10:00.556631 Final RX Vref Byte 1 = 48 to rank0
3946 23:10:00.559634 Final RX Vref Byte 0 = 47 to rank1
3947 23:10:00.563108 Final RX Vref Byte 1 = 48 to rank1==
3948 23:10:00.566143 Dram Type= 6, Freq= 0, CH_0, rank 0
3949 23:10:00.573126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3950 23:10:00.573680 ==
3951 23:10:00.574046 DQS Delay:
3952 23:10:00.574379 DQS0 = 0, DQS1 = 0
3953 23:10:00.575697 DQM Delay:
3954 23:10:00.576153 DQM0 = 40, DQM1 = 30
3955 23:10:00.579272 DQ Delay:
3956 23:10:00.582463 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
3957 23:10:00.585918 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
3958 23:10:00.586395 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
3959 23:10:00.592681 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
3960 23:10:00.593266
3961 23:10:00.593630
3962 23:10:00.599272 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
3963 23:10:00.602765 CH0 RK0: MR19=808, MR18=5C5C
3964 23:10:00.609007 CH0_RK0: MR19=0x808, MR18=0x5C5C, DQSOSC=392, MR23=63, INC=170, DEC=113
3965 23:10:00.609565
3966 23:10:00.612419 ----->DramcWriteLeveling(PI) begin...
3967 23:10:00.613011 ==
3968 23:10:00.615647 Dram Type= 6, Freq= 0, CH_0, rank 1
3969 23:10:00.618726 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3970 23:10:00.619279 ==
3971 23:10:00.622191 Write leveling (Byte 0): 32 => 32
3972 23:10:00.625422 Write leveling (Byte 1): 28 => 28
3973 23:10:00.628864 DramcWriteLeveling(PI) end<-----
3974 23:10:00.629324
3975 23:10:00.629696 ==
3976 23:10:00.632419 Dram Type= 6, Freq= 0, CH_0, rank 1
3977 23:10:00.635580 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3978 23:10:00.636139 ==
3979 23:10:00.639023 [Gating] SW mode calibration
3980 23:10:00.645276 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3981 23:10:00.652069 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3982 23:10:00.655547 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 23:10:00.662057 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3984 23:10:00.665175 0 5 8 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
3985 23:10:00.668539 0 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
3986 23:10:00.675010 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 23:10:00.678847 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 23:10:00.681874 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 23:10:00.688382 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 23:10:00.691782 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 23:10:00.695086 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 23:10:00.702128 0 6 8 | B1->B0 | 2e2e 3535 | 0 0 | (0 0) (0 0)
3993 23:10:00.705106 0 6 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
3994 23:10:00.708136 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 23:10:00.714945 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 23:10:00.718082 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 23:10:00.721383 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 23:10:00.725121 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 23:10:00.731380 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 23:10:00.735185 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4001 23:10:00.738053 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 23:10:00.744550 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 23:10:00.747980 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 23:10:00.751222 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 23:10:00.758118 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 23:10:00.761077 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 23:10:00.765015 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 23:10:00.771145 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 23:10:00.774666 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 23:10:00.777389 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 23:10:00.784508 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 23:10:00.787506 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 23:10:00.790863 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 23:10:00.797529 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 23:10:00.800991 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 23:10:00.804099 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4017 23:10:00.810729 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 23:10:00.814140 Total UI for P1: 0, mck2ui 16
4019 23:10:00.817247 best dqsien dly found for B0: ( 0, 9, 8)
4020 23:10:00.820846 Total UI for P1: 0, mck2ui 16
4021 23:10:00.823929 best dqsien dly found for B1: ( 0, 9, 10)
4022 23:10:00.827139 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4023 23:10:00.830489 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4024 23:10:00.831035
4025 23:10:00.833681 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4026 23:10:00.837367 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4027 23:10:00.841035 [Gating] SW calibration Done
4028 23:10:00.841587 ==
4029 23:10:00.843806 Dram Type= 6, Freq= 0, CH_0, rank 1
4030 23:10:00.847392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4031 23:10:00.847950 ==
4032 23:10:00.850274 RX Vref Scan: 0
4033 23:10:00.850733
4034 23:10:00.851089 RX Vref 0 -> 0, step: 1
4035 23:10:00.853612
4036 23:10:00.854069 RX Delay -230 -> 252, step: 16
4037 23:10:00.860489 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4038 23:10:00.863803 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4039 23:10:00.867095 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4040 23:10:00.870445 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4041 23:10:00.876996 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4042 23:10:00.880054 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4043 23:10:00.883714 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4044 23:10:00.887087 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4045 23:10:00.890387 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4046 23:10:00.897002 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4047 23:10:00.900503 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4048 23:10:00.903803 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4049 23:10:00.907135 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4050 23:10:00.913452 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4051 23:10:00.916962 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4052 23:10:00.920569 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4053 23:10:00.921201 ==
4054 23:10:00.923578 Dram Type= 6, Freq= 0, CH_0, rank 1
4055 23:10:00.926537 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4056 23:10:00.930184 ==
4057 23:10:00.930643 DQS Delay:
4058 23:10:00.931069 DQS0 = 0, DQS1 = 0
4059 23:10:00.933312 DQM Delay:
4060 23:10:00.933769 DQM0 = 41, DQM1 = 33
4061 23:10:00.936524 DQ Delay:
4062 23:10:00.937023 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4063 23:10:00.939870 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4064 23:10:00.943426 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4065 23:10:00.946768 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4066 23:10:00.947328
4067 23:10:00.950029
4068 23:10:00.950579 ==
4069 23:10:00.953484 Dram Type= 6, Freq= 0, CH_0, rank 1
4070 23:10:00.956375 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4071 23:10:00.956872 ==
4072 23:10:00.957238
4073 23:10:00.957574
4074 23:10:00.959880 TX Vref Scan disable
4075 23:10:00.960334 == TX Byte 0 ==
4076 23:10:00.966834 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4077 23:10:00.969587 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4078 23:10:00.970047 == TX Byte 1 ==
4079 23:10:00.976765 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4080 23:10:00.979986 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4081 23:10:00.980446 ==
4082 23:10:00.983135 Dram Type= 6, Freq= 0, CH_0, rank 1
4083 23:10:00.986342 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4084 23:10:00.986820 ==
4085 23:10:00.987180
4086 23:10:00.987535
4087 23:10:00.989917 TX Vref Scan disable
4088 23:10:00.993102 == TX Byte 0 ==
4089 23:10:00.996496 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4090 23:10:00.999643 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4091 23:10:01.002938 == TX Byte 1 ==
4092 23:10:01.006679 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4093 23:10:01.009790 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4094 23:10:01.012879
4095 23:10:01.013342 [DATLAT]
4096 23:10:01.013707 Freq=600, CH0 RK1
4097 23:10:01.014050
4098 23:10:01.016160 DATLAT Default: 0x8
4099 23:10:01.016760 0, 0xFFFF, sum = 0
4100 23:10:01.019767 1, 0xFFFF, sum = 0
4101 23:10:01.020338 2, 0xFFFF, sum = 0
4102 23:10:01.022677 3, 0xFFFF, sum = 0
4103 23:10:01.023147 4, 0xFFFF, sum = 0
4104 23:10:01.026041 5, 0xFFFF, sum = 0
4105 23:10:01.029448 6, 0xFFFF, sum = 0
4106 23:10:01.030112 7, 0x0, sum = 1
4107 23:10:01.030494 8, 0x0, sum = 2
4108 23:10:01.032587 9, 0x0, sum = 3
4109 23:10:01.033106 10, 0x0, sum = 4
4110 23:10:01.036206 best_step = 8
4111 23:10:01.036819
4112 23:10:01.037199 ==
4113 23:10:01.039353 Dram Type= 6, Freq= 0, CH_0, rank 1
4114 23:10:01.042686 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4115 23:10:01.043244 ==
4116 23:10:01.045977 RX Vref Scan: 0
4117 23:10:01.046436
4118 23:10:01.046796 RX Vref 0 -> 0, step: 1
4119 23:10:01.047131
4120 23:10:01.049200 RX Delay -195 -> 252, step: 8
4121 23:10:01.056554 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4122 23:10:01.059913 iDelay=205, Bit 1, Center 44 (-115 ~ 204) 320
4123 23:10:01.063527 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4124 23:10:01.066771 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4125 23:10:01.072851 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4126 23:10:01.076464 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4127 23:10:01.079691 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4128 23:10:01.083051 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4129 23:10:01.089639 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4130 23:10:01.093101 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4131 23:10:01.096175 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4132 23:10:01.099590 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4133 23:10:01.102863 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4134 23:10:01.109225 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4135 23:10:01.113097 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4136 23:10:01.116183 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4137 23:10:01.116808 ==
4138 23:10:01.119078 Dram Type= 6, Freq= 0, CH_0, rank 1
4139 23:10:01.125940 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4140 23:10:01.126400 ==
4141 23:10:01.126759 DQS Delay:
4142 23:10:01.127093 DQS0 = 0, DQS1 = 0
4143 23:10:01.129677 DQM Delay:
4144 23:10:01.130326 DQM0 = 40, DQM1 = 31
4145 23:10:01.132862 DQ Delay:
4146 23:10:01.136346 DQ0 =36, DQ1 =44, DQ2 =40, DQ3 =36
4147 23:10:01.139518 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
4148 23:10:01.143120 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4149 23:10:01.146010 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
4150 23:10:01.146564
4151 23:10:01.146925
4152 23:10:01.152303 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f6f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4153 23:10:01.156132 CH0 RK1: MR19=808, MR18=6F6F
4154 23:10:01.163047 CH0_RK1: MR19=0x808, MR18=0x6F6F, DQSOSC=389, MR23=63, INC=173, DEC=115
4155 23:10:01.165846 [RxdqsGatingPostProcess] freq 600
4156 23:10:01.169525 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4157 23:10:01.172457 Pre-setting of DQS Precalculation
4158 23:10:01.179438 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4159 23:10:01.180164 ==
4160 23:10:01.182358 Dram Type= 6, Freq= 0, CH_1, rank 0
4161 23:10:01.185967 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4162 23:10:01.186522 ==
4163 23:10:01.192559 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4164 23:10:01.195462 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4165 23:10:01.200141 [CA 0] Center 35 (5~66) winsize 62
4166 23:10:01.203547 [CA 1] Center 35 (5~66) winsize 62
4167 23:10:01.206614 [CA 2] Center 33 (3~64) winsize 62
4168 23:10:01.210208 [CA 3] Center 33 (3~64) winsize 62
4169 23:10:01.213165 [CA 4] Center 33 (2~64) winsize 63
4170 23:10:01.216518 [CA 5] Center 33 (2~64) winsize 63
4171 23:10:01.217122
4172 23:10:01.219666 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4173 23:10:01.220123
4174 23:10:01.223347 [CATrainingPosCal] consider 1 rank data
4175 23:10:01.226628 u2DelayCellTimex100 = 270/100 ps
4176 23:10:01.230014 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4177 23:10:01.233081 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4178 23:10:01.240064 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4179 23:10:01.243250 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4180 23:10:01.246666 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4181 23:10:01.250073 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4182 23:10:01.250629
4183 23:10:01.252887 CA PerBit enable=1, Macro0, CA PI delay=33
4184 23:10:01.253348
4185 23:10:01.256474 [CBTSetCACLKResult] CA Dly = 33
4186 23:10:01.256965 CS Dly: 4 (0~35)
4187 23:10:01.259945 ==
4188 23:10:01.260493 Dram Type= 6, Freq= 0, CH_1, rank 1
4189 23:10:01.266470 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4190 23:10:01.267027 ==
4191 23:10:01.269772 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4192 23:10:01.276244 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4193 23:10:01.280175 [CA 0] Center 35 (5~66) winsize 62
4194 23:10:01.283496 [CA 1] Center 34 (4~65) winsize 62
4195 23:10:01.286894 [CA 2] Center 33 (3~64) winsize 62
4196 23:10:01.290420 [CA 3] Center 33 (3~64) winsize 62
4197 23:10:01.293804 [CA 4] Center 32 (2~63) winsize 62
4198 23:10:01.296506 [CA 5] Center 32 (2~63) winsize 62
4199 23:10:01.297001
4200 23:10:01.299760 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4201 23:10:01.300217
4202 23:10:01.303467 [CATrainingPosCal] consider 2 rank data
4203 23:10:01.306560 u2DelayCellTimex100 = 270/100 ps
4204 23:10:01.310633 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4205 23:10:01.316235 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4206 23:10:01.320035 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4207 23:10:01.323286 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4208 23:10:01.326191 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4209 23:10:01.329624 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4210 23:10:01.330082
4211 23:10:01.333261 CA PerBit enable=1, Macro0, CA PI delay=32
4212 23:10:01.333716
4213 23:10:01.336257 [CBTSetCACLKResult] CA Dly = 32
4214 23:10:01.336751 CS Dly: 4 (0~36)
4215 23:10:01.339611
4216 23:10:01.343104 ----->DramcWriteLeveling(PI) begin...
4217 23:10:01.343661 ==
4218 23:10:01.346806 Dram Type= 6, Freq= 0, CH_1, rank 0
4219 23:10:01.349460 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4220 23:10:01.349922 ==
4221 23:10:01.353219 Write leveling (Byte 0): 28 => 28
4222 23:10:01.356095 Write leveling (Byte 1): 29 => 29
4223 23:10:01.359520 DramcWriteLeveling(PI) end<-----
4224 23:10:01.359977
4225 23:10:01.360331 ==
4226 23:10:01.363045 Dram Type= 6, Freq= 0, CH_1, rank 0
4227 23:10:01.366165 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4228 23:10:01.366721 ==
4229 23:10:01.369713 [Gating] SW mode calibration
4230 23:10:01.376468 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4231 23:10:01.382671 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4232 23:10:01.385916 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4233 23:10:01.389084 0 5 4 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 1)
4234 23:10:01.396215 0 5 8 | B1->B0 | 3131 2323 | 1 0 | (1 1) (1 0)
4235 23:10:01.399346 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 23:10:01.402625 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 23:10:01.409461 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 23:10:01.412380 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 23:10:01.415982 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 23:10:01.422536 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 23:10:01.425793 0 6 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4242 23:10:01.429053 0 6 8 | B1->B0 | 3131 4545 | 0 0 | (0 0) (0 0)
4243 23:10:01.435747 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 23:10:01.439118 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 23:10:01.442460 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 23:10:01.449006 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 23:10:01.452312 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 23:10:01.455602 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 23:10:01.459656 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4250 23:10:01.465691 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4251 23:10:01.468595 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 23:10:01.472294 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 23:10:01.478584 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 23:10:01.482346 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 23:10:01.485649 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 23:10:01.492093 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 23:10:01.495372 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 23:10:01.498733 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 23:10:01.505467 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 23:10:01.508816 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 23:10:01.511932 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 23:10:01.518537 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 23:10:01.521952 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 23:10:01.525274 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 23:10:01.531665 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4266 23:10:01.535533 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4267 23:10:01.538503 Total UI for P1: 0, mck2ui 16
4268 23:10:01.541569 best dqsien dly found for B0: ( 0, 9, 4)
4269 23:10:01.544835 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4270 23:10:01.548374 Total UI for P1: 0, mck2ui 16
4271 23:10:01.551758 best dqsien dly found for B1: ( 0, 9, 8)
4272 23:10:01.554976 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4273 23:10:01.558400 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4274 23:10:01.558954
4275 23:10:01.564885 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4276 23:10:01.568060 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4277 23:10:01.568519 [Gating] SW calibration Done
4278 23:10:01.571529 ==
4279 23:10:01.575080 Dram Type= 6, Freq= 0, CH_1, rank 0
4280 23:10:01.578268 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4281 23:10:01.578730 ==
4282 23:10:01.579090 RX Vref Scan: 0
4283 23:10:01.579426
4284 23:10:01.581358 RX Vref 0 -> 0, step: 1
4285 23:10:01.581813
4286 23:10:01.585080 RX Delay -230 -> 252, step: 16
4287 23:10:01.587827 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4288 23:10:01.591568 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4289 23:10:01.598041 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4290 23:10:01.601205 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4291 23:10:01.604824 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4292 23:10:01.607681 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4293 23:10:01.614633 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4294 23:10:01.617730 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4295 23:10:01.621005 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4296 23:10:01.624316 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4297 23:10:01.627785 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4298 23:10:01.634383 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4299 23:10:01.637349 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4300 23:10:01.641090 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4301 23:10:01.644226 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4302 23:10:01.650966 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4303 23:10:01.651366 ==
4304 23:10:01.654184 Dram Type= 6, Freq= 0, CH_1, rank 0
4305 23:10:01.657421 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4306 23:10:01.657747 ==
4307 23:10:01.657998 DQS Delay:
4308 23:10:01.660920 DQS0 = 0, DQS1 = 0
4309 23:10:01.661238 DQM Delay:
4310 23:10:01.663766 DQM0 = 39, DQM1 = 32
4311 23:10:01.664082 DQ Delay:
4312 23:10:01.667141 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4313 23:10:01.670505 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4314 23:10:01.674093 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4315 23:10:01.677428 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4316 23:10:01.677945
4317 23:10:01.678275
4318 23:10:01.678618 ==
4319 23:10:01.680649 Dram Type= 6, Freq= 0, CH_1, rank 0
4320 23:10:01.684588 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4321 23:10:01.687538 ==
4322 23:10:01.688096
4323 23:10:01.688461
4324 23:10:01.688838 TX Vref Scan disable
4325 23:10:01.690583 == TX Byte 0 ==
4326 23:10:01.694291 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4327 23:10:01.701085 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4328 23:10:01.701647 == TX Byte 1 ==
4329 23:10:01.704104 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4330 23:10:01.710507 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4331 23:10:01.711070 ==
4332 23:10:01.713640 Dram Type= 6, Freq= 0, CH_1, rank 0
4333 23:10:01.717109 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4334 23:10:01.717677 ==
4335 23:10:01.718041
4336 23:10:01.718375
4337 23:10:01.720490 TX Vref Scan disable
4338 23:10:01.723693 == TX Byte 0 ==
4339 23:10:01.726970 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4340 23:10:01.730332 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4341 23:10:01.733210 == TX Byte 1 ==
4342 23:10:01.736994 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4343 23:10:01.740585 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4344 23:10:01.741189
4345 23:10:01.741553 [DATLAT]
4346 23:10:01.743603 Freq=600, CH1 RK0
4347 23:10:01.744271
4348 23:10:01.746749 DATLAT Default: 0x9
4349 23:10:01.747300 0, 0xFFFF, sum = 0
4350 23:10:01.750163 1, 0xFFFF, sum = 0
4351 23:10:01.750716 2, 0xFFFF, sum = 0
4352 23:10:01.753149 3, 0xFFFF, sum = 0
4353 23:10:01.753610 4, 0xFFFF, sum = 0
4354 23:10:01.756442 5, 0xFFFF, sum = 0
4355 23:10:01.757093 6, 0xFFFF, sum = 0
4356 23:10:01.760127 7, 0x0, sum = 1
4357 23:10:01.760682 8, 0x0, sum = 2
4358 23:10:01.761112 9, 0x0, sum = 3
4359 23:10:01.763530 10, 0x0, sum = 4
4360 23:10:01.764092 best_step = 8
4361 23:10:01.764451
4362 23:10:01.766349 ==
4363 23:10:01.766806 Dram Type= 6, Freq= 0, CH_1, rank 0
4364 23:10:01.773610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4365 23:10:01.774170 ==
4366 23:10:01.774531 RX Vref Scan: 1
4367 23:10:01.774863
4368 23:10:01.776543 RX Vref 0 -> 0, step: 1
4369 23:10:01.777045
4370 23:10:01.779877 RX Delay -195 -> 252, step: 8
4371 23:10:01.780426
4372 23:10:01.783547 Set Vref, RX VrefLevel [Byte0]: 56
4373 23:10:01.786410 [Byte1]: 48
4374 23:10:01.786961
4375 23:10:01.789561 Final RX Vref Byte 0 = 56 to rank0
4376 23:10:01.793148 Final RX Vref Byte 1 = 48 to rank0
4377 23:10:01.796617 Final RX Vref Byte 0 = 56 to rank1
4378 23:10:01.799910 Final RX Vref Byte 1 = 48 to rank1==
4379 23:10:01.803337 Dram Type= 6, Freq= 0, CH_1, rank 0
4380 23:10:01.806407 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4381 23:10:01.806960 ==
4382 23:10:01.809753 DQS Delay:
4383 23:10:01.810281 DQS0 = 0, DQS1 = 0
4384 23:10:01.813156 DQM Delay:
4385 23:10:01.813703 DQM0 = 38, DQM1 = 31
4386 23:10:01.816868 DQ Delay:
4387 23:10:01.817420 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4388 23:10:01.819579 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4389 23:10:01.822627 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4390 23:10:01.826176 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4391 23:10:01.826725
4392 23:10:01.829413
4393 23:10:01.835897 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e6e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4394 23:10:01.839878 CH1 RK0: MR19=808, MR18=6E6E
4395 23:10:01.846068 CH1_RK0: MR19=0x808, MR18=0x6E6E, DQSOSC=389, MR23=63, INC=173, DEC=115
4396 23:10:01.846667
4397 23:10:01.849471 ----->DramcWriteLeveling(PI) begin...
4398 23:10:01.850025 ==
4399 23:10:01.852513 Dram Type= 6, Freq= 0, CH_1, rank 1
4400 23:10:01.856147 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4401 23:10:01.856698 ==
4402 23:10:01.859283 Write leveling (Byte 0): 29 => 29
4403 23:10:01.862462 Write leveling (Byte 1): 28 => 28
4404 23:10:01.865684 DramcWriteLeveling(PI) end<-----
4405 23:10:01.866136
4406 23:10:01.866497 ==
4407 23:10:01.869221 Dram Type= 6, Freq= 0, CH_1, rank 1
4408 23:10:01.872618 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4409 23:10:01.873218 ==
4410 23:10:01.875835 [Gating] SW mode calibration
4411 23:10:01.882834 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4412 23:10:01.889277 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4413 23:10:01.892110 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 23:10:01.895673 0 5 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4415 23:10:01.902621 0 5 8 | B1->B0 | 2f2f 2424 | 0 0 | (1 1) (0 0)
4416 23:10:01.905940 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 23:10:01.909129 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 23:10:01.915494 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 23:10:01.919085 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 23:10:01.922072 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 23:10:01.928842 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 23:10:01.932348 0 6 4 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
4423 23:10:01.935455 0 6 8 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
4424 23:10:01.942188 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 23:10:01.945632 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 23:10:01.948983 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 23:10:01.955589 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 23:10:01.958775 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 23:10:01.962333 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4430 23:10:01.968697 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4431 23:10:01.972277 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 23:10:01.975452 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 23:10:01.982224 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 23:10:01.985164 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 23:10:01.988653 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 23:10:01.995153 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 23:10:01.998476 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 23:10:02.001924 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 23:10:02.008342 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 23:10:02.011870 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 23:10:02.015109 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 23:10:02.021550 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 23:10:02.025414 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 23:10:02.028541 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 23:10:02.031829 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 23:10:02.038528 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4447 23:10:02.041680 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4448 23:10:02.045173 Total UI for P1: 0, mck2ui 16
4449 23:10:02.048413 best dqsien dly found for B0: ( 0, 9, 4)
4450 23:10:02.052140 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 23:10:02.054944 Total UI for P1: 0, mck2ui 16
4452 23:10:02.058203 best dqsien dly found for B1: ( 0, 9, 8)
4453 23:10:02.061700 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4454 23:10:02.064988 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4455 23:10:02.065552
4456 23:10:02.071981 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4457 23:10:02.075131 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4458 23:10:02.077884 [Gating] SW calibration Done
4459 23:10:02.078563 ==
4460 23:10:02.081401 Dram Type= 6, Freq= 0, CH_1, rank 1
4461 23:10:02.084897 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4462 23:10:02.085455 ==
4463 23:10:02.085822 RX Vref Scan: 0
4464 23:10:02.086162
4465 23:10:02.088165 RX Vref 0 -> 0, step: 1
4466 23:10:02.088763
4467 23:10:02.091526 RX Delay -230 -> 252, step: 16
4468 23:10:02.095089 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4469 23:10:02.101479 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4470 23:10:02.104643 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4471 23:10:02.107983 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4472 23:10:02.111182 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4473 23:10:02.115142 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4474 23:10:02.121112 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4475 23:10:02.124528 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4476 23:10:02.128267 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4477 23:10:02.131142 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4478 23:10:02.134514 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4479 23:10:02.141492 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4480 23:10:02.144673 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4481 23:10:02.148304 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4482 23:10:02.151333 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4483 23:10:02.157549 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4484 23:10:02.158088 ==
4485 23:10:02.160907 Dram Type= 6, Freq= 0, CH_1, rank 1
4486 23:10:02.164508 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4487 23:10:02.164670 ==
4488 23:10:02.164800 DQS Delay:
4489 23:10:02.167598 DQS0 = 0, DQS1 = 0
4490 23:10:02.167759 DQM Delay:
4491 23:10:02.171259 DQM0 = 42, DQM1 = 34
4492 23:10:02.171425 DQ Delay:
4493 23:10:02.174571 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4494 23:10:02.177249 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4495 23:10:02.181114 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4496 23:10:02.184185 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4497 23:10:02.184366
4498 23:10:02.184458
4499 23:10:02.184542 ==
4500 23:10:02.187601 Dram Type= 6, Freq= 0, CH_1, rank 1
4501 23:10:02.190744 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4502 23:10:02.193956 ==
4503 23:10:02.194157
4504 23:10:02.194266
4505 23:10:02.194362 TX Vref Scan disable
4506 23:10:02.197283 == TX Byte 0 ==
4507 23:10:02.200878 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4508 23:10:02.204367 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4509 23:10:02.207771 == TX Byte 1 ==
4510 23:10:02.211052 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4511 23:10:02.217699 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4512 23:10:02.218269 ==
4513 23:10:02.220964 Dram Type= 6, Freq= 0, CH_1, rank 1
4514 23:10:02.223893 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4515 23:10:02.224359 ==
4516 23:10:02.224760
4517 23:10:02.225111
4518 23:10:02.227327 TX Vref Scan disable
4519 23:10:02.230432 == TX Byte 0 ==
4520 23:10:02.233740 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4521 23:10:02.237071 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4522 23:10:02.240663 == TX Byte 1 ==
4523 23:10:02.243960 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4524 23:10:02.247316 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4525 23:10:02.247895
4526 23:10:02.248264 [DATLAT]
4527 23:10:02.250571 Freq=600, CH1 RK1
4528 23:10:02.251141
4529 23:10:02.251512 DATLAT Default: 0x8
4530 23:10:02.253427 0, 0xFFFF, sum = 0
4531 23:10:02.256918 1, 0xFFFF, sum = 0
4532 23:10:02.257512 2, 0xFFFF, sum = 0
4533 23:10:02.260337 3, 0xFFFF, sum = 0
4534 23:10:02.260963 4, 0xFFFF, sum = 0
4535 23:10:02.263352 5, 0xFFFF, sum = 0
4536 23:10:02.263830 6, 0xFFFF, sum = 0
4537 23:10:02.267031 7, 0x0, sum = 1
4538 23:10:02.267501 8, 0x0, sum = 2
4539 23:10:02.267874 9, 0x0, sum = 3
4540 23:10:02.270245 10, 0x0, sum = 4
4541 23:10:02.270810 best_step = 8
4542 23:10:02.271176
4543 23:10:02.271517 ==
4544 23:10:02.273338 Dram Type= 6, Freq= 0, CH_1, rank 1
4545 23:10:02.279965 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4546 23:10:02.280515 ==
4547 23:10:02.280924 RX Vref Scan: 0
4548 23:10:02.281273
4549 23:10:02.283363 RX Vref 0 -> 0, step: 1
4550 23:10:02.283924
4551 23:10:02.286767 RX Delay -195 -> 252, step: 8
4552 23:10:02.293416 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4553 23:10:02.296873 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4554 23:10:02.300044 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4555 23:10:02.303368 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4556 23:10:02.306732 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4557 23:10:02.313153 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4558 23:10:02.316804 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4559 23:10:02.320475 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4560 23:10:02.323314 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4561 23:10:02.329773 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4562 23:10:02.333185 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4563 23:10:02.336079 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4564 23:10:02.339312 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4565 23:10:02.346190 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4566 23:10:02.349406 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4567 23:10:02.352880 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4568 23:10:02.353442 ==
4569 23:10:02.356447 Dram Type= 6, Freq= 0, CH_1, rank 1
4570 23:10:02.359488 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4571 23:10:02.360051 ==
4572 23:10:02.362711 DQS Delay:
4573 23:10:02.363274 DQS0 = 0, DQS1 = 0
4574 23:10:02.366104 DQM Delay:
4575 23:10:02.366670 DQM0 = 36, DQM1 = 30
4576 23:10:02.369013 DQ Delay:
4577 23:10:02.369470 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4578 23:10:02.372296 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4579 23:10:02.375893 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =20
4580 23:10:02.379087 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4581 23:10:02.379580
4582 23:10:02.382677
4583 23:10:02.389411 [DQSOSCAuto] RK1, (LSB)MR18= 0x6161, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4584 23:10:02.392503 CH1 RK1: MR19=808, MR18=6161
4585 23:10:02.399308 CH1_RK1: MR19=0x808, MR18=0x6161, DQSOSC=391, MR23=63, INC=171, DEC=114
4586 23:10:02.402417 [RxdqsGatingPostProcess] freq 600
4587 23:10:02.405857 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4588 23:10:02.409320 Pre-setting of DQS Precalculation
4589 23:10:02.412857 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4590 23:10:02.422321 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4591 23:10:02.428808 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4592 23:10:02.429357
4593 23:10:02.429716
4594 23:10:02.432059 [Calibration Summary] 1200 Mbps
4595 23:10:02.432516 CH 0, Rank 0
4596 23:10:02.435721 SW Impedance : PASS
4597 23:10:02.438779 DUTY Scan : NO K
4598 23:10:02.439235 ZQ Calibration : PASS
4599 23:10:02.442115 Jitter Meter : NO K
4600 23:10:02.442664 CBT Training : PASS
4601 23:10:02.445278 Write leveling : PASS
4602 23:10:02.449005 RX DQS gating : PASS
4603 23:10:02.449563 RX DQ/DQS(RDDQC) : PASS
4604 23:10:02.452418 TX DQ/DQS : PASS
4605 23:10:02.455264 RX DATLAT : PASS
4606 23:10:02.455816 RX DQ/DQS(Engine): PASS
4607 23:10:02.458424 TX OE : NO K
4608 23:10:02.458894 All Pass.
4609 23:10:02.459258
4610 23:10:02.461922 CH 0, Rank 1
4611 23:10:02.462385 SW Impedance : PASS
4612 23:10:02.465258 DUTY Scan : NO K
4613 23:10:02.468664 ZQ Calibration : PASS
4614 23:10:02.469275 Jitter Meter : NO K
4615 23:10:02.471753 CBT Training : PASS
4616 23:10:02.475340 Write leveling : PASS
4617 23:10:02.475906 RX DQS gating : PASS
4618 23:10:02.478187 RX DQ/DQS(RDDQC) : PASS
4619 23:10:02.481490 TX DQ/DQS : PASS
4620 23:10:02.481958 RX DATLAT : PASS
4621 23:10:02.485265 RX DQ/DQS(Engine): PASS
4622 23:10:02.488490 TX OE : NO K
4623 23:10:02.489118 All Pass.
4624 23:10:02.489493
4625 23:10:02.489830 CH 1, Rank 0
4626 23:10:02.491457 SW Impedance : PASS
4627 23:10:02.495081 DUTY Scan : NO K
4628 23:10:02.495651 ZQ Calibration : PASS
4629 23:10:02.498124 Jitter Meter : NO K
4630 23:10:02.501525 CBT Training : PASS
4631 23:10:02.502094 Write leveling : PASS
4632 23:10:02.504881 RX DQS gating : PASS
4633 23:10:02.505347 RX DQ/DQS(RDDQC) : PASS
4634 23:10:02.508331 TX DQ/DQS : PASS
4635 23:10:02.511786 RX DATLAT : PASS
4636 23:10:02.512347 RX DQ/DQS(Engine): PASS
4637 23:10:02.515053 TX OE : NO K
4638 23:10:02.515516 All Pass.
4639 23:10:02.515882
4640 23:10:02.518510 CH 1, Rank 1
4641 23:10:02.519155 SW Impedance : PASS
4642 23:10:02.521486 DUTY Scan : NO K
4643 23:10:02.525191 ZQ Calibration : PASS
4644 23:10:02.525793 Jitter Meter : NO K
4645 23:10:02.528128 CBT Training : PASS
4646 23:10:02.531230 Write leveling : PASS
4647 23:10:02.531934 RX DQS gating : PASS
4648 23:10:02.534593 RX DQ/DQS(RDDQC) : PASS
4649 23:10:02.538418 TX DQ/DQS : PASS
4650 23:10:02.538888 RX DATLAT : PASS
4651 23:10:02.541216 RX DQ/DQS(Engine): PASS
4652 23:10:02.544758 TX OE : NO K
4653 23:10:02.545328 All Pass.
4654 23:10:02.545695
4655 23:10:02.546035 DramC Write-DBI off
4656 23:10:02.548035 PER_BANK_REFRESH: Hybrid Mode
4657 23:10:02.551477 TX_TRACKING: ON
4658 23:10:02.557980 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4659 23:10:02.561310 [FAST_K] Save calibration result to emmc
4660 23:10:02.567945 dramc_set_vcore_voltage set vcore to 662500
4661 23:10:02.568506 Read voltage for 933, 3
4662 23:10:02.570942 Vio18 = 0
4663 23:10:02.571503 Vcore = 662500
4664 23:10:02.571872 Vdram = 0
4665 23:10:02.574605 Vddq = 0
4666 23:10:02.575172 Vmddr = 0
4667 23:10:02.577710 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4668 23:10:02.584574 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4669 23:10:02.587674 MEM_TYPE=3, freq_sel=17
4670 23:10:02.591037 sv_algorithm_assistance_LP4_1600
4671 23:10:02.594687 ============ PULL DRAM RESETB DOWN ============
4672 23:10:02.597331 ========== PULL DRAM RESETB DOWN end =========
4673 23:10:02.604057 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4674 23:10:02.604636 ===================================
4675 23:10:02.607769 LPDDR4 DRAM CONFIGURATION
4676 23:10:02.610700 ===================================
4677 23:10:02.613934 EX_ROW_EN[0] = 0x0
4678 23:10:02.614401 EX_ROW_EN[1] = 0x0
4679 23:10:02.617121 LP4Y_EN = 0x0
4680 23:10:02.617586 WORK_FSP = 0x0
4681 23:10:02.620334 WL = 0x3
4682 23:10:02.620842 RL = 0x3
4683 23:10:02.624235 BL = 0x2
4684 23:10:02.627047 RPST = 0x0
4685 23:10:02.627509 RD_PRE = 0x0
4686 23:10:02.630245 WR_PRE = 0x1
4687 23:10:02.630708 WR_PST = 0x0
4688 23:10:02.633447 DBI_WR = 0x0
4689 23:10:02.633930 DBI_RD = 0x0
4690 23:10:02.636824 OTF = 0x1
4691 23:10:02.640072 ===================================
4692 23:10:02.643815 ===================================
4693 23:10:02.644434 ANA top config
4694 23:10:02.647013 ===================================
4695 23:10:02.650101 DLL_ASYNC_EN = 0
4696 23:10:02.653672 ALL_SLAVE_EN = 1
4697 23:10:02.654208 NEW_RANK_MODE = 1
4698 23:10:02.656878 DLL_IDLE_MODE = 1
4699 23:10:02.660270 LP45_APHY_COMB_EN = 1
4700 23:10:02.663330 TX_ODT_DIS = 1
4701 23:10:02.667197 NEW_8X_MODE = 1
4702 23:10:02.669763 ===================================
4703 23:10:02.673249 ===================================
4704 23:10:02.676533 data_rate = 1866
4705 23:10:02.677142 CKR = 1
4706 23:10:02.679740 DQ_P2S_RATIO = 8
4707 23:10:02.683354 ===================================
4708 23:10:02.686554 CA_P2S_RATIO = 8
4709 23:10:02.689922 DQ_CA_OPEN = 0
4710 23:10:02.692823 DQ_SEMI_OPEN = 0
4711 23:10:02.696062 CA_SEMI_OPEN = 0
4712 23:10:02.696861 CA_FULL_RATE = 0
4713 23:10:02.699575 DQ_CKDIV4_EN = 1
4714 23:10:02.703010 CA_CKDIV4_EN = 1
4715 23:10:02.706151 CA_PREDIV_EN = 0
4716 23:10:02.709388 PH8_DLY = 0
4717 23:10:02.712698 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4718 23:10:02.713283 DQ_AAMCK_DIV = 4
4719 23:10:02.716016 CA_AAMCK_DIV = 4
4720 23:10:02.719483 CA_ADMCK_DIV = 4
4721 23:10:02.722650 DQ_TRACK_CA_EN = 0
4722 23:10:02.725865 CA_PICK = 933
4723 23:10:02.729183 CA_MCKIO = 933
4724 23:10:02.729736 MCKIO_SEMI = 0
4725 23:10:02.732383 PLL_FREQ = 3732
4726 23:10:02.735685 DQ_UI_PI_RATIO = 32
4727 23:10:02.738915 CA_UI_PI_RATIO = 0
4728 23:10:02.742371 ===================================
4729 23:10:02.746192 ===================================
4730 23:10:02.748666 memory_type:LPDDR4
4731 23:10:02.749193 GP_NUM : 10
4732 23:10:02.752313 SRAM_EN : 1
4733 23:10:02.755678 MD32_EN : 0
4734 23:10:02.758657 ===================================
4735 23:10:02.759133 [ANA_INIT] >>>>>>>>>>>>>>
4736 23:10:02.762685 <<<<<< [CONFIGURE PHASE]: ANA_TX
4737 23:10:02.765660 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4738 23:10:02.769213 ===================================
4739 23:10:02.771845 data_rate = 1866,PCW = 0X8f00
4740 23:10:02.775420 ===================================
4741 23:10:02.778577 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4742 23:10:02.785372 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4743 23:10:02.788959 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4744 23:10:02.795439 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4745 23:10:02.798732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4746 23:10:02.802047 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4747 23:10:02.805250 [ANA_INIT] flow start
4748 23:10:02.805806 [ANA_INIT] PLL >>>>>>>>
4749 23:10:02.808661 [ANA_INIT] PLL <<<<<<<<
4750 23:10:02.811980 [ANA_INIT] MIDPI >>>>>>>>
4751 23:10:02.812532 [ANA_INIT] MIDPI <<<<<<<<
4752 23:10:02.815119 [ANA_INIT] DLL >>>>>>>>
4753 23:10:02.818286 [ANA_INIT] flow end
4754 23:10:02.822081 ============ LP4 DIFF to SE enter ============
4755 23:10:02.825097 ============ LP4 DIFF to SE exit ============
4756 23:10:02.828134 [ANA_INIT] <<<<<<<<<<<<<
4757 23:10:02.831579 [Flow] Enable top DCM control >>>>>
4758 23:10:02.834920 [Flow] Enable top DCM control <<<<<
4759 23:10:02.838027 Enable DLL master slave shuffle
4760 23:10:02.841364 ==============================================================
4761 23:10:02.844873 Gating Mode config
4762 23:10:02.851489 ==============================================================
4763 23:10:02.852033 Config description:
4764 23:10:02.861346 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4765 23:10:02.868272 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4766 23:10:02.874844 SELPH_MODE 0: By rank 1: By Phase
4767 23:10:02.877908 ==============================================================
4768 23:10:02.881199 GAT_TRACK_EN = 1
4769 23:10:02.884856 RX_GATING_MODE = 2
4770 23:10:02.888005 RX_GATING_TRACK_MODE = 2
4771 23:10:02.891020 SELPH_MODE = 1
4772 23:10:02.894748 PICG_EARLY_EN = 1
4773 23:10:02.897895 VALID_LAT_VALUE = 1
4774 23:10:02.901406 ==============================================================
4775 23:10:02.904791 Enter into Gating configuration >>>>
4776 23:10:02.907890 Exit from Gating configuration <<<<
4777 23:10:02.911026 Enter into DVFS_PRE_config >>>>>
4778 23:10:02.924457 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4779 23:10:02.927433 Exit from DVFS_PRE_config <<<<<
4780 23:10:02.931047 Enter into PICG configuration >>>>
4781 23:10:02.931561 Exit from PICG configuration <<<<
4782 23:10:02.934126 [RX_INPUT] configuration >>>>>
4783 23:10:02.937412 [RX_INPUT] configuration <<<<<
4784 23:10:02.944681 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4785 23:10:02.947517 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4786 23:10:02.954782 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4787 23:10:02.960698 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4788 23:10:02.967779 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4789 23:10:02.973975 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4790 23:10:02.977493 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4791 23:10:02.980802 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4792 23:10:02.987256 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4793 23:10:02.990281 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4794 23:10:02.994174 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4795 23:10:02.997147 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4796 23:10:03.000589 ===================================
4797 23:10:03.003528 LPDDR4 DRAM CONFIGURATION
4798 23:10:03.006629 ===================================
4799 23:10:03.010321 EX_ROW_EN[0] = 0x0
4800 23:10:03.010873 EX_ROW_EN[1] = 0x0
4801 23:10:03.013691 LP4Y_EN = 0x0
4802 23:10:03.014540 WORK_FSP = 0x0
4803 23:10:03.016815 WL = 0x3
4804 23:10:03.017366 RL = 0x3
4805 23:10:03.020093 BL = 0x2
4806 23:10:03.020553 RPST = 0x0
4807 23:10:03.023613 RD_PRE = 0x0
4808 23:10:03.024161 WR_PRE = 0x1
4809 23:10:03.026529 WR_PST = 0x0
4810 23:10:03.030041 DBI_WR = 0x0
4811 23:10:03.030499 DBI_RD = 0x0
4812 23:10:03.033466 OTF = 0x1
4813 23:10:03.036678 ===================================
4814 23:10:03.040107 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4815 23:10:03.043332 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4816 23:10:03.046559 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4817 23:10:03.049764 ===================================
4818 23:10:03.053076 LPDDR4 DRAM CONFIGURATION
4819 23:10:03.056501 ===================================
4820 23:10:03.059988 EX_ROW_EN[0] = 0x10
4821 23:10:03.060559 EX_ROW_EN[1] = 0x0
4822 23:10:03.062971 LP4Y_EN = 0x0
4823 23:10:03.063435 WORK_FSP = 0x0
4824 23:10:03.066352 WL = 0x3
4825 23:10:03.066814 RL = 0x3
4826 23:10:03.070214 BL = 0x2
4827 23:10:03.070775 RPST = 0x0
4828 23:10:03.073244 RD_PRE = 0x0
4829 23:10:03.073705 WR_PRE = 0x1
4830 23:10:03.076467 WR_PST = 0x0
4831 23:10:03.077075 DBI_WR = 0x0
4832 23:10:03.079881 DBI_RD = 0x0
4833 23:10:03.083067 OTF = 0x1
4834 23:10:03.083636 ===================================
4835 23:10:03.089376 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4836 23:10:03.094810 nWR fixed to 30
4837 23:10:03.098460 [ModeRegInit_LP4] CH0 RK0
4838 23:10:03.099018 [ModeRegInit_LP4] CH0 RK1
4839 23:10:03.101112 [ModeRegInit_LP4] CH1 RK0
4840 23:10:03.104642 [ModeRegInit_LP4] CH1 RK1
4841 23:10:03.105257 match AC timing 8
4842 23:10:03.111514 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4843 23:10:03.114224 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4844 23:10:03.118335 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4845 23:10:03.124393 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4846 23:10:03.127769 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4847 23:10:03.128342 ==
4848 23:10:03.131305 Dram Type= 6, Freq= 0, CH_0, rank 0
4849 23:10:03.134221 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4850 23:10:03.134702 ==
4851 23:10:03.140832 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4852 23:10:03.147883 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4853 23:10:03.150984 [CA 0] Center 38 (8~69) winsize 62
4854 23:10:03.154737 [CA 1] Center 38 (8~69) winsize 62
4855 23:10:03.157393 [CA 2] Center 36 (6~67) winsize 62
4856 23:10:03.160761 [CA 3] Center 35 (5~66) winsize 62
4857 23:10:03.164310 [CA 4] Center 34 (4~65) winsize 62
4858 23:10:03.167806 [CA 5] Center 34 (4~65) winsize 62
4859 23:10:03.168364
4860 23:10:03.171094 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4861 23:10:03.171649
4862 23:10:03.174469 [CATrainingPosCal] consider 1 rank data
4863 23:10:03.177881 u2DelayCellTimex100 = 270/100 ps
4864 23:10:03.180998 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4865 23:10:03.184356 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4866 23:10:03.187697 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4867 23:10:03.191151 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4868 23:10:03.194136 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4869 23:10:03.197315 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4870 23:10:03.200865
4871 23:10:03.204299 CA PerBit enable=1, Macro0, CA PI delay=34
4872 23:10:03.204894
4873 23:10:03.207490 [CBTSetCACLKResult] CA Dly = 34
4874 23:10:03.208043 CS Dly: 7 (0~38)
4875 23:10:03.208430 ==
4876 23:10:03.210651 Dram Type= 6, Freq= 0, CH_0, rank 1
4877 23:10:03.214471 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4878 23:10:03.215028 ==
4879 23:10:03.220696 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4880 23:10:03.227496 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4881 23:10:03.230556 [CA 0] Center 38 (8~69) winsize 62
4882 23:10:03.233957 [CA 1] Center 38 (7~69) winsize 63
4883 23:10:03.237223 [CA 2] Center 36 (6~67) winsize 62
4884 23:10:03.240979 [CA 3] Center 35 (5~66) winsize 62
4885 23:10:03.243966 [CA 4] Center 34 (4~65) winsize 62
4886 23:10:03.248003 [CA 5] Center 34 (4~65) winsize 62
4887 23:10:03.248568
4888 23:10:03.250719 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4889 23:10:03.251286
4890 23:10:03.253963 [CATrainingPosCal] consider 2 rank data
4891 23:10:03.257354 u2DelayCellTimex100 = 270/100 ps
4892 23:10:03.260677 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4893 23:10:03.263864 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4894 23:10:03.266816 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4895 23:10:03.270752 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4896 23:10:03.277236 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4897 23:10:03.280394 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4898 23:10:03.281092
4899 23:10:03.284168 CA PerBit enable=1, Macro0, CA PI delay=34
4900 23:10:03.284787
4901 23:10:03.286821 [CBTSetCACLKResult] CA Dly = 34
4902 23:10:03.287290 CS Dly: 7 (0~39)
4903 23:10:03.287659
4904 23:10:03.290296 ----->DramcWriteLeveling(PI) begin...
4905 23:10:03.290883 ==
4906 23:10:03.293755 Dram Type= 6, Freq= 0, CH_0, rank 0
4907 23:10:03.300521 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4908 23:10:03.301124 ==
4909 23:10:03.303759 Write leveling (Byte 0): 28 => 28
4910 23:10:03.306805 Write leveling (Byte 1): 29 => 29
4911 23:10:03.307270 DramcWriteLeveling(PI) end<-----
4912 23:10:03.307631
4913 23:10:03.309996 ==
4914 23:10:03.313504 Dram Type= 6, Freq= 0, CH_0, rank 0
4915 23:10:03.317170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4916 23:10:03.317745 ==
4917 23:10:03.320794 [Gating] SW mode calibration
4918 23:10:03.327278 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4919 23:10:03.330228 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4920 23:10:03.336886 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4921 23:10:03.339969 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4922 23:10:03.343513 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4923 23:10:03.350169 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4924 23:10:03.353711 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4925 23:10:03.356670 0 10 20 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
4926 23:10:03.363317 0 10 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
4927 23:10:03.366558 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4928 23:10:03.369821 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4929 23:10:03.376469 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4930 23:10:03.380043 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4931 23:10:03.383448 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4932 23:10:03.390286 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4933 23:10:03.393175 0 11 20 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
4934 23:10:03.396821 0 11 24 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
4935 23:10:03.403150 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4936 23:10:03.406220 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4937 23:10:03.409449 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4938 23:10:03.416393 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4939 23:10:03.419320 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4940 23:10:03.423232 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4941 23:10:03.429366 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4942 23:10:03.432961 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 23:10:03.436032 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 23:10:03.442402 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 23:10:03.445954 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4946 23:10:03.449074 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4947 23:10:03.455694 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4948 23:10:03.459271 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4949 23:10:03.462450 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4950 23:10:03.469346 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4951 23:10:03.472529 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4952 23:10:03.476040 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4953 23:10:03.478888 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4954 23:10:03.485633 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4955 23:10:03.489363 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4956 23:10:03.495671 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4957 23:10:03.498844 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4958 23:10:03.502188 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4959 23:10:03.505582 Total UI for P1: 0, mck2ui 16
4960 23:10:03.508600 best dqsien dly found for B0: ( 0, 14, 22)
4961 23:10:03.512606 Total UI for P1: 0, mck2ui 16
4962 23:10:03.515231 best dqsien dly found for B1: ( 0, 14, 20)
4963 23:10:03.518832 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
4964 23:10:03.522214 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4965 23:10:03.522791
4966 23:10:03.525157 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
4967 23:10:03.531737 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
4968 23:10:03.532298 [Gating] SW calibration Done
4969 23:10:03.532673 ==
4970 23:10:03.534859 Dram Type= 6, Freq= 0, CH_0, rank 0
4971 23:10:03.541666 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4972 23:10:03.542172 ==
4973 23:10:03.542543 RX Vref Scan: 0
4974 23:10:03.542886
4975 23:10:03.545791 RX Vref 0 -> 0, step: 1
4976 23:10:03.546257
4977 23:10:03.548518 RX Delay -80 -> 252, step: 8
4978 23:10:03.551618 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4979 23:10:03.555004 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4980 23:10:03.558501 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4981 23:10:03.564583 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4982 23:10:03.568300 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4983 23:10:03.571414 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4984 23:10:03.575010 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
4985 23:10:03.577870 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4986 23:10:03.580998 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
4987 23:10:03.588398 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4988 23:10:03.591492 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
4989 23:10:03.594408 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
4990 23:10:03.597753 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
4991 23:10:03.601133 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4992 23:10:03.607645 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4993 23:10:03.611022 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
4994 23:10:03.611571 ==
4995 23:10:03.614299 Dram Type= 6, Freq= 0, CH_0, rank 0
4996 23:10:03.617539 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4997 23:10:03.618108 ==
4998 23:10:03.618476 DQS Delay:
4999 23:10:03.620949 DQS0 = 0, DQS1 = 0
5000 23:10:03.621510 DQM Delay:
5001 23:10:03.624329 DQM0 = 95, DQM1 = 88
5002 23:10:03.624934 DQ Delay:
5003 23:10:03.628225 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5004 23:10:03.630960 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5005 23:10:03.633994 DQ8 =83, DQ9 =71, DQ10 =87, DQ11 =83
5006 23:10:03.637501 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5007 23:10:03.638132
5008 23:10:03.638508
5009 23:10:03.638851 ==
5010 23:10:03.640943 Dram Type= 6, Freq= 0, CH_0, rank 0
5011 23:10:03.644297 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5012 23:10:03.647586 ==
5013 23:10:03.648184
5014 23:10:03.648553
5015 23:10:03.648958 TX Vref Scan disable
5016 23:10:03.650817 == TX Byte 0 ==
5017 23:10:03.654059 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5018 23:10:03.657771 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5019 23:10:03.660880 == TX Byte 1 ==
5020 23:10:03.664065 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5021 23:10:03.670492 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5022 23:10:03.670958 ==
5023 23:10:03.674268 Dram Type= 6, Freq= 0, CH_0, rank 0
5024 23:10:03.677092 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5025 23:10:03.677557 ==
5026 23:10:03.677931
5027 23:10:03.678269
5028 23:10:03.680831 TX Vref Scan disable
5029 23:10:03.681309 == TX Byte 0 ==
5030 23:10:03.687104 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5031 23:10:03.690470 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5032 23:10:03.691056 == TX Byte 1 ==
5033 23:10:03.697208 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5034 23:10:03.700364 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5035 23:10:03.700980
5036 23:10:03.701356 [DATLAT]
5037 23:10:03.703631 Freq=933, CH0 RK0
5038 23:10:03.704196
5039 23:10:03.704566 DATLAT Default: 0xd
5040 23:10:03.707102 0, 0xFFFF, sum = 0
5041 23:10:03.707680 1, 0xFFFF, sum = 0
5042 23:10:03.710340 2, 0xFFFF, sum = 0
5043 23:10:03.710914 3, 0xFFFF, sum = 0
5044 23:10:03.713679 4, 0xFFFF, sum = 0
5045 23:10:03.717171 5, 0xFFFF, sum = 0
5046 23:10:03.717745 6, 0xFFFF, sum = 0
5047 23:10:03.720005 7, 0xFFFF, sum = 0
5048 23:10:03.720473 8, 0xFFFF, sum = 0
5049 23:10:03.723462 9, 0xFFFF, sum = 0
5050 23:10:03.723934 10, 0x0, sum = 1
5051 23:10:03.726842 11, 0x0, sum = 2
5052 23:10:03.727415 12, 0x0, sum = 3
5053 23:10:03.729813 13, 0x0, sum = 4
5054 23:10:03.730285 best_step = 11
5055 23:10:03.730650
5056 23:10:03.730993 ==
5057 23:10:03.733462 Dram Type= 6, Freq= 0, CH_0, rank 0
5058 23:10:03.736254 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5059 23:10:03.736769 ==
5060 23:10:03.739846 RX Vref Scan: 1
5061 23:10:03.740309
5062 23:10:03.743374 RX Vref 0 -> 0, step: 1
5063 23:10:03.743955
5064 23:10:03.744327 RX Delay -69 -> 252, step: 4
5065 23:10:03.744671
5066 23:10:03.746574 Set Vref, RX VrefLevel [Byte0]: 47
5067 23:10:03.749709 [Byte1]: 48
5068 23:10:03.754762
5069 23:10:03.755326 Final RX Vref Byte 0 = 47 to rank0
5070 23:10:03.757844 Final RX Vref Byte 1 = 48 to rank0
5071 23:10:03.761044 Final RX Vref Byte 0 = 47 to rank1
5072 23:10:03.764696 Final RX Vref Byte 1 = 48 to rank1==
5073 23:10:03.767978 Dram Type= 6, Freq= 0, CH_0, rank 0
5074 23:10:03.774338 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5075 23:10:03.774900 ==
5076 23:10:03.775430 DQS Delay:
5077 23:10:03.777418 DQS0 = 0, DQS1 = 0
5078 23:10:03.777880 DQM Delay:
5079 23:10:03.778248 DQM0 = 97, DQM1 = 86
5080 23:10:03.780805 DQ Delay:
5081 23:10:03.784378 DQ0 =94, DQ1 =102, DQ2 =96, DQ3 =94
5082 23:10:03.787479 DQ4 =100, DQ5 =86, DQ6 =104, DQ7 =104
5083 23:10:03.791213 DQ8 =76, DQ9 =70, DQ10 =84, DQ11 =80
5084 23:10:03.794114 DQ12 =94, DQ13 =94, DQ14 =96, DQ15 =96
5085 23:10:03.794687
5086 23:10:03.795061
5087 23:10:03.800949 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 413 ps
5088 23:10:03.804328 CH0 RK0: MR19=505, MR18=1B1B
5089 23:10:03.810781 CH0_RK0: MR19=0x505, MR18=0x1B1B, DQSOSC=413, MR23=63, INC=63, DEC=42
5090 23:10:03.811348
5091 23:10:03.814115 ----->DramcWriteLeveling(PI) begin...
5092 23:10:03.814682 ==
5093 23:10:03.817502 Dram Type= 6, Freq= 0, CH_0, rank 1
5094 23:10:03.820796 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5095 23:10:03.821365 ==
5096 23:10:03.823768 Write leveling (Byte 0): 28 => 28
5097 23:10:03.827229 Write leveling (Byte 1): 28 => 28
5098 23:10:03.830625 DramcWriteLeveling(PI) end<-----
5099 23:10:03.831190
5100 23:10:03.831561 ==
5101 23:10:03.834255 Dram Type= 6, Freq= 0, CH_0, rank 1
5102 23:10:03.837253 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5103 23:10:03.840553 ==
5104 23:10:03.841094 [Gating] SW mode calibration
5105 23:10:03.850491 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5106 23:10:03.853982 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5107 23:10:03.857001 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 23:10:03.864144 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 23:10:03.867095 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 23:10:03.870099 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 23:10:03.877406 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5112 23:10:03.880673 0 10 20 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 1)
5113 23:10:03.883407 0 10 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5114 23:10:03.890211 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 23:10:03.893592 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 23:10:03.896864 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 23:10:03.903624 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 23:10:03.906830 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 23:10:03.910344 0 11 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5120 23:10:03.916513 0 11 20 | B1->B0 | 2e2e 3a3a | 0 0 | (0 0) (0 0)
5121 23:10:03.920091 0 11 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5122 23:10:03.923549 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 23:10:03.930152 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 23:10:03.933404 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 23:10:03.936342 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 23:10:03.943312 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 23:10:03.946312 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5128 23:10:03.949958 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 23:10:03.956910 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5130 23:10:03.959890 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 23:10:03.962924 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 23:10:03.969925 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 23:10:03.973196 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 23:10:03.976476 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 23:10:03.983364 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 23:10:03.986216 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 23:10:03.989470 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 23:10:03.993346 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 23:10:03.999670 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 23:10:04.002956 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 23:10:04.009429 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 23:10:04.013291 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 23:10:04.015840 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 23:10:04.019501 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5145 23:10:04.025993 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5146 23:10:04.029551 Total UI for P1: 0, mck2ui 16
5147 23:10:04.032903 best dqsien dly found for B0: ( 0, 14, 20)
5148 23:10:04.035924 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 23:10:04.038927 Total UI for P1: 0, mck2ui 16
5150 23:10:04.042621 best dqsien dly found for B1: ( 0, 14, 22)
5151 23:10:04.045703 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5152 23:10:04.049245 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5153 23:10:04.049813
5154 23:10:04.052429 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5155 23:10:04.059225 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5156 23:10:04.059795 [Gating] SW calibration Done
5157 23:10:04.060169 ==
5158 23:10:04.062144 Dram Type= 6, Freq= 0, CH_0, rank 1
5159 23:10:04.069172 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5160 23:10:04.069742 ==
5161 23:10:04.070112 RX Vref Scan: 0
5162 23:10:04.070457
5163 23:10:04.072614 RX Vref 0 -> 0, step: 1
5164 23:10:04.073337
5165 23:10:04.075331 RX Delay -80 -> 252, step: 8
5166 23:10:04.078763 iDelay=200, Bit 0, Center 91 (-8 ~ 191) 200
5167 23:10:04.082442 iDelay=200, Bit 1, Center 95 (-8 ~ 199) 208
5168 23:10:04.085563 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5169 23:10:04.089154 iDelay=200, Bit 3, Center 87 (-8 ~ 183) 192
5170 23:10:04.095499 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5171 23:10:04.098775 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5172 23:10:04.102311 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5173 23:10:04.105521 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5174 23:10:04.108799 iDelay=200, Bit 8, Center 79 (-8 ~ 167) 176
5175 23:10:04.115637 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5176 23:10:04.119087 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5177 23:10:04.121900 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5178 23:10:04.125443 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5179 23:10:04.128415 iDelay=200, Bit 13, Center 91 (-8 ~ 191) 200
5180 23:10:04.132085 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5181 23:10:04.138332 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5182 23:10:04.138813 ==
5183 23:10:04.141651 Dram Type= 6, Freq= 0, CH_0, rank 1
5184 23:10:04.144900 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5185 23:10:04.145362 ==
5186 23:10:04.145726 DQS Delay:
5187 23:10:04.148332 DQS0 = 0, DQS1 = 0
5188 23:10:04.148859 DQM Delay:
5189 23:10:04.151891 DQM0 = 95, DQM1 = 87
5190 23:10:04.152456 DQ Delay:
5191 23:10:04.155738 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5192 23:10:04.158655 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5193 23:10:04.161995 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =83
5194 23:10:04.165196 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5195 23:10:04.165661
5196 23:10:04.166028
5197 23:10:04.166366 ==
5198 23:10:04.168437 Dram Type= 6, Freq= 0, CH_0, rank 1
5199 23:10:04.171515 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5200 23:10:04.174965 ==
5201 23:10:04.175532
5202 23:10:04.175897
5203 23:10:04.176235 TX Vref Scan disable
5204 23:10:04.178455 == TX Byte 0 ==
5205 23:10:04.181846 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5206 23:10:04.184509 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5207 23:10:04.187784 == TX Byte 1 ==
5208 23:10:04.191421 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5209 23:10:04.197956 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5210 23:10:04.198499 ==
5211 23:10:04.201411 Dram Type= 6, Freq= 0, CH_0, rank 1
5212 23:10:04.204802 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5213 23:10:04.205372 ==
5214 23:10:04.205750
5215 23:10:04.206091
5216 23:10:04.207972 TX Vref Scan disable
5217 23:10:04.208541 == TX Byte 0 ==
5218 23:10:04.214558 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5219 23:10:04.218157 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5220 23:10:04.218727 == TX Byte 1 ==
5221 23:10:04.224757 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5222 23:10:04.227404 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5223 23:10:04.227875
5224 23:10:04.228236 [DATLAT]
5225 23:10:04.230836 Freq=933, CH0 RK1
5226 23:10:04.231399
5227 23:10:04.231766 DATLAT Default: 0xb
5228 23:10:04.234113 0, 0xFFFF, sum = 0
5229 23:10:04.234587 1, 0xFFFF, sum = 0
5230 23:10:04.237711 2, 0xFFFF, sum = 0
5231 23:10:04.240653 3, 0xFFFF, sum = 0
5232 23:10:04.241327 4, 0xFFFF, sum = 0
5233 23:10:04.244231 5, 0xFFFF, sum = 0
5234 23:10:04.244860 6, 0xFFFF, sum = 0
5235 23:10:04.247672 7, 0xFFFF, sum = 0
5236 23:10:04.248241 8, 0xFFFF, sum = 0
5237 23:10:04.250919 9, 0xFFFF, sum = 0
5238 23:10:04.251491 10, 0x0, sum = 1
5239 23:10:04.254247 11, 0x0, sum = 2
5240 23:10:04.254821 12, 0x0, sum = 3
5241 23:10:04.257407 13, 0x0, sum = 4
5242 23:10:04.257878 best_step = 11
5243 23:10:04.258242
5244 23:10:04.258584 ==
5245 23:10:04.260426 Dram Type= 6, Freq= 0, CH_0, rank 1
5246 23:10:04.264187 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5247 23:10:04.264653 ==
5248 23:10:04.267391 RX Vref Scan: 0
5249 23:10:04.267953
5250 23:10:04.270742 RX Vref 0 -> 0, step: 1
5251 23:10:04.271319
5252 23:10:04.271692 RX Delay -69 -> 252, step: 4
5253 23:10:04.278220 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5254 23:10:04.281519 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5255 23:10:04.285116 iDelay=199, Bit 2, Center 96 (3 ~ 190) 188
5256 23:10:04.288400 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5257 23:10:04.292002 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5258 23:10:04.294974 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5259 23:10:04.301514 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5260 23:10:04.304760 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5261 23:10:04.308130 iDelay=199, Bit 8, Center 78 (-9 ~ 166) 176
5262 23:10:04.311351 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5263 23:10:04.314773 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5264 23:10:04.321091 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5265 23:10:04.324564 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5266 23:10:04.327818 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5267 23:10:04.331447 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5268 23:10:04.334404 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5269 23:10:04.337636 ==
5270 23:10:04.338101 Dram Type= 6, Freq= 0, CH_0, rank 1
5271 23:10:04.344503 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5272 23:10:04.345128 ==
5273 23:10:04.345511 DQS Delay:
5274 23:10:04.348036 DQS0 = 0, DQS1 = 0
5275 23:10:04.348599 DQM Delay:
5276 23:10:04.350969 DQM0 = 97, DQM1 = 87
5277 23:10:04.351531 DQ Delay:
5278 23:10:04.354393 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =92
5279 23:10:04.357970 DQ4 =102, DQ5 =88, DQ6 =102, DQ7 =106
5280 23:10:04.361029 DQ8 =78, DQ9 =72, DQ10 =90, DQ11 =80
5281 23:10:04.364048 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =94
5282 23:10:04.364525
5283 23:10:04.364959
5284 23:10:04.370904 [DQSOSCAuto] RK1, (LSB)MR18= 0x2828, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5285 23:10:04.374094 CH0 RK1: MR19=505, MR18=2828
5286 23:10:04.380639 CH0_RK1: MR19=0x505, MR18=0x2828, DQSOSC=409, MR23=63, INC=64, DEC=43
5287 23:10:04.383569 [RxdqsGatingPostProcess] freq 933
5288 23:10:04.390729 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5289 23:10:04.393717 Pre-setting of DQS Precalculation
5290 23:10:04.397258 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5291 23:10:04.397821 ==
5292 23:10:04.400673 Dram Type= 6, Freq= 0, CH_1, rank 0
5293 23:10:04.403570 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5294 23:10:04.404031 ==
5295 23:10:04.410451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5296 23:10:04.417181 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5297 23:10:04.420442 [CA 0] Center 37 (7~68) winsize 62
5298 23:10:04.423739 [CA 1] Center 37 (6~68) winsize 63
5299 23:10:04.427185 [CA 2] Center 34 (4~65) winsize 62
5300 23:10:04.430860 [CA 3] Center 34 (4~65) winsize 62
5301 23:10:04.433721 [CA 4] Center 33 (2~64) winsize 63
5302 23:10:04.436820 [CA 5] Center 33 (3~64) winsize 62
5303 23:10:04.437427
5304 23:10:04.440129 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5305 23:10:04.440587
5306 23:10:04.443505 [CATrainingPosCal] consider 1 rank data
5307 23:10:04.446597 u2DelayCellTimex100 = 270/100 ps
5308 23:10:04.450246 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5309 23:10:04.453595 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5310 23:10:04.457327 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5311 23:10:04.460230 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5312 23:10:04.463245 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5313 23:10:04.469983 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5314 23:10:04.470478
5315 23:10:04.473434 CA PerBit enable=1, Macro0, CA PI delay=33
5316 23:10:04.473897
5317 23:10:04.476750 [CBTSetCACLKResult] CA Dly = 33
5318 23:10:04.477314 CS Dly: 5 (0~36)
5319 23:10:04.477680 ==
5320 23:10:04.480000 Dram Type= 6, Freq= 0, CH_1, rank 1
5321 23:10:04.483081 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5322 23:10:04.486830 ==
5323 23:10:04.490066 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5324 23:10:04.496551 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5325 23:10:04.499844 [CA 0] Center 37 (6~68) winsize 63
5326 23:10:04.503220 [CA 1] Center 37 (6~68) winsize 63
5327 23:10:04.506890 [CA 2] Center 34 (4~65) winsize 62
5328 23:10:04.510274 [CA 3] Center 33 (3~64) winsize 62
5329 23:10:04.513154 [CA 4] Center 33 (3~64) winsize 62
5330 23:10:04.516632 [CA 5] Center 33 (3~64) winsize 62
5331 23:10:04.517301
5332 23:10:04.519578 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5333 23:10:04.520160
5334 23:10:04.523104 [CATrainingPosCal] consider 2 rank data
5335 23:10:04.526391 u2DelayCellTimex100 = 270/100 ps
5336 23:10:04.529440 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5337 23:10:04.533159 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5338 23:10:04.535909 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5339 23:10:04.539288 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5340 23:10:04.546241 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5341 23:10:04.549389 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5342 23:10:04.549851
5343 23:10:04.552682 CA PerBit enable=1, Macro0, CA PI delay=33
5344 23:10:04.553176
5345 23:10:04.556099 [CBTSetCACLKResult] CA Dly = 33
5346 23:10:04.556665 CS Dly: 5 (0~37)
5347 23:10:04.557076
5348 23:10:04.559026 ----->DramcWriteLeveling(PI) begin...
5349 23:10:04.559492 ==
5350 23:10:04.562563 Dram Type= 6, Freq= 0, CH_1, rank 0
5351 23:10:04.569042 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5352 23:10:04.569591 ==
5353 23:10:04.572223 Write leveling (Byte 0): 21 => 21
5354 23:10:04.575671 Write leveling (Byte 1): 23 => 23
5355 23:10:04.579060 DramcWriteLeveling(PI) end<-----
5356 23:10:04.579620
5357 23:10:04.579983 ==
5358 23:10:04.582580 Dram Type= 6, Freq= 0, CH_1, rank 0
5359 23:10:04.585356 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5360 23:10:04.585818 ==
5361 23:10:04.588734 [Gating] SW mode calibration
5362 23:10:04.595240 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5363 23:10:04.602287 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5364 23:10:04.605448 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 23:10:04.608909 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 23:10:04.615347 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 23:10:04.618399 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5368 23:10:04.622051 0 10 16 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5369 23:10:04.625458 0 10 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (1 0)
5370 23:10:04.632194 0 10 24 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
5371 23:10:04.635520 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 23:10:04.638491 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 23:10:04.645538 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 23:10:04.648487 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 23:10:04.651597 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 23:10:04.658192 0 11 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5377 23:10:04.661423 0 11 20 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
5378 23:10:04.664640 0 11 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5379 23:10:04.671413 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 23:10:04.674970 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 23:10:04.678731 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 23:10:04.684689 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 23:10:04.687959 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 23:10:04.691269 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5385 23:10:04.697662 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5386 23:10:04.701424 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 23:10:04.704423 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 23:10:04.710980 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 23:10:04.714558 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 23:10:04.717599 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 23:10:04.724678 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 23:10:04.728028 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 23:10:04.730967 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 23:10:04.737621 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 23:10:04.741133 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 23:10:04.744168 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 23:10:04.750805 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 23:10:04.754528 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 23:10:04.757433 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 23:10:04.764276 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5401 23:10:04.768044 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5402 23:10:04.771087 Total UI for P1: 0, mck2ui 16
5403 23:10:04.773956 best dqsien dly found for B0: ( 0, 14, 16)
5404 23:10:04.776937 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 23:10:04.780475 Total UI for P1: 0, mck2ui 16
5406 23:10:04.784047 best dqsien dly found for B1: ( 0, 14, 20)
5407 23:10:04.787504 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5408 23:10:04.790583 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5409 23:10:04.794143
5410 23:10:04.797264 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5411 23:10:04.800436 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5412 23:10:04.804075 [Gating] SW calibration Done
5413 23:10:04.804639 ==
5414 23:10:04.806981 Dram Type= 6, Freq= 0, CH_1, rank 0
5415 23:10:04.810100 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5416 23:10:04.810570 ==
5417 23:10:04.810936 RX Vref Scan: 0
5418 23:10:04.813594
5419 23:10:04.814158 RX Vref 0 -> 0, step: 1
5420 23:10:04.814527
5421 23:10:04.817107 RX Delay -80 -> 252, step: 8
5422 23:10:04.820388 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5423 23:10:04.823776 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5424 23:10:04.830243 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5425 23:10:04.833411 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5426 23:10:04.837266 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5427 23:10:04.839995 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5428 23:10:04.843117 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5429 23:10:04.846748 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5430 23:10:04.853441 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5431 23:10:04.856662 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5432 23:10:04.859647 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5433 23:10:04.863600 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5434 23:10:04.866731 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5435 23:10:04.872949 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5436 23:10:04.876281 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5437 23:10:04.879857 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5438 23:10:04.880422 ==
5439 23:10:04.882688 Dram Type= 6, Freq= 0, CH_1, rank 0
5440 23:10:04.886437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5441 23:10:04.887007 ==
5442 23:10:04.889658 DQS Delay:
5443 23:10:04.890226 DQS0 = 0, DQS1 = 0
5444 23:10:04.893239 DQM Delay:
5445 23:10:04.893804 DQM0 = 95, DQM1 = 87
5446 23:10:04.894178 DQ Delay:
5447 23:10:04.896360 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5448 23:10:04.899816 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5449 23:10:04.903048 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =79
5450 23:10:04.906074 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5451 23:10:04.906635
5452 23:10:04.907004
5453 23:10:04.909938 ==
5454 23:10:04.912745 Dram Type= 6, Freq= 0, CH_1, rank 0
5455 23:10:04.916104 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5456 23:10:04.916678 ==
5457 23:10:04.917094
5458 23:10:04.917436
5459 23:10:04.919241 TX Vref Scan disable
5460 23:10:04.919802 == TX Byte 0 ==
5461 23:10:04.926083 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5462 23:10:04.929590 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5463 23:10:04.930162 == TX Byte 1 ==
5464 23:10:04.936062 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5465 23:10:04.938867 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5466 23:10:04.939383 ==
5467 23:10:04.942403 Dram Type= 6, Freq= 0, CH_1, rank 0
5468 23:10:04.945523 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5469 23:10:04.945996 ==
5470 23:10:04.946358
5471 23:10:04.946695
5472 23:10:04.949036 TX Vref Scan disable
5473 23:10:04.952156 == TX Byte 0 ==
5474 23:10:04.955483 Update DQ dly =703 (2 ,5, 31) DQ OEN =(2 ,2)
5475 23:10:04.958831 Update DQM dly =703 (2 ,5, 31) DQM OEN =(2 ,2)
5476 23:10:04.962446 == TX Byte 1 ==
5477 23:10:04.965551 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5478 23:10:04.969022 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5479 23:10:04.969588
5480 23:10:04.972090 [DATLAT]
5481 23:10:04.972551 Freq=933, CH1 RK0
5482 23:10:04.972977
5483 23:10:04.976014 DATLAT Default: 0xd
5484 23:10:04.976574 0, 0xFFFF, sum = 0
5485 23:10:04.978857 1, 0xFFFF, sum = 0
5486 23:10:04.979431 2, 0xFFFF, sum = 0
5487 23:10:04.982073 3, 0xFFFF, sum = 0
5488 23:10:04.982542 4, 0xFFFF, sum = 0
5489 23:10:04.985384 5, 0xFFFF, sum = 0
5490 23:10:04.985856 6, 0xFFFF, sum = 0
5491 23:10:04.988957 7, 0xFFFF, sum = 0
5492 23:10:04.989527 8, 0xFFFF, sum = 0
5493 23:10:04.992693 9, 0xFFFF, sum = 0
5494 23:10:04.993302 10, 0x0, sum = 1
5495 23:10:04.995561 11, 0x0, sum = 2
5496 23:10:04.996134 12, 0x0, sum = 3
5497 23:10:04.998899 13, 0x0, sum = 4
5498 23:10:04.999471 best_step = 11
5499 23:10:04.999837
5500 23:10:05.000174 ==
5501 23:10:05.001766 Dram Type= 6, Freq= 0, CH_1, rank 0
5502 23:10:05.008761 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5503 23:10:05.009338 ==
5504 23:10:05.009709 RX Vref Scan: 1
5505 23:10:05.010050
5506 23:10:05.012269 RX Vref 0 -> 0, step: 1
5507 23:10:05.012875
5508 23:10:05.015170 RX Delay -69 -> 252, step: 4
5509 23:10:05.015752
5510 23:10:05.018325 Set Vref, RX VrefLevel [Byte0]: 56
5511 23:10:05.022039 [Byte1]: 48
5512 23:10:05.022603
5513 23:10:05.025218 Final RX Vref Byte 0 = 56 to rank0
5514 23:10:05.028440 Final RX Vref Byte 1 = 48 to rank0
5515 23:10:05.031891 Final RX Vref Byte 0 = 56 to rank1
5516 23:10:05.034806 Final RX Vref Byte 1 = 48 to rank1==
5517 23:10:05.038190 Dram Type= 6, Freq= 0, CH_1, rank 0
5518 23:10:05.041464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5519 23:10:05.041932 ==
5520 23:10:05.044648 DQS Delay:
5521 23:10:05.045160 DQS0 = 0, DQS1 = 0
5522 23:10:05.048336 DQM Delay:
5523 23:10:05.048956 DQM0 = 93, DQM1 = 88
5524 23:10:05.049330 DQ Delay:
5525 23:10:05.051673 DQ0 =96, DQ1 =90, DQ2 =84, DQ3 =92
5526 23:10:05.054780 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5527 23:10:05.058326 DQ8 =72, DQ9 =78, DQ10 =88, DQ11 =80
5528 23:10:05.061256 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5529 23:10:05.061720
5530 23:10:05.062082
5531 23:10:05.071377 [DQSOSCAuto] RK0, (LSB)MR18= 0x3131, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5532 23:10:05.074556 CH1 RK0: MR19=505, MR18=3131
5533 23:10:05.081333 CH1_RK0: MR19=0x505, MR18=0x3131, DQSOSC=406, MR23=63, INC=65, DEC=43
5534 23:10:05.081898
5535 23:10:05.084319 ----->DramcWriteLeveling(PI) begin...
5536 23:10:05.084955 ==
5537 23:10:05.087853 Dram Type= 6, Freq= 0, CH_1, rank 1
5538 23:10:05.091170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5539 23:10:05.091734 ==
5540 23:10:05.094244 Write leveling (Byte 0): 23 => 23
5541 23:10:05.097699 Write leveling (Byte 1): 22 => 22
5542 23:10:05.101164 DramcWriteLeveling(PI) end<-----
5543 23:10:05.101627
5544 23:10:05.101987 ==
5545 23:10:05.104399 Dram Type= 6, Freq= 0, CH_1, rank 1
5546 23:10:05.107756 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5547 23:10:05.108324 ==
5548 23:10:05.110983 [Gating] SW mode calibration
5549 23:10:05.117901 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5550 23:10:05.125012 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5551 23:10:05.127504 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 23:10:05.131062 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5553 23:10:05.137811 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5554 23:10:05.140806 0 10 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5555 23:10:05.144155 0 10 16 | B1->B0 | 3333 2525 | 0 0 | (0 1) (1 0)
5556 23:10:05.150814 0 10 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5557 23:10:05.153851 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 23:10:05.157625 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 23:10:05.164015 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 23:10:05.167131 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5561 23:10:05.170638 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5562 23:10:05.177067 0 11 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5563 23:10:05.180513 0 11 16 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
5564 23:10:05.183662 0 11 20 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5565 23:10:05.190566 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 23:10:05.193407 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 23:10:05.196779 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 23:10:05.203410 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5569 23:10:05.206645 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5570 23:10:05.210234 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5571 23:10:05.216804 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5572 23:10:05.219827 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 23:10:05.223746 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5574 23:10:05.230609 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 23:10:05.233603 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 23:10:05.236520 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 23:10:05.243088 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 23:10:05.246532 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 23:10:05.249517 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 23:10:05.256557 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 23:10:05.260010 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 23:10:05.263352 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 23:10:05.269606 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 23:10:05.272968 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 23:10:05.276435 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 23:10:05.282922 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 23:10:05.286062 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5588 23:10:05.289708 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5589 23:10:05.293002 Total UI for P1: 0, mck2ui 16
5590 23:10:05.296451 best dqsien dly found for B0: ( 0, 14, 16)
5591 23:10:05.302787 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 23:10:05.303345 Total UI for P1: 0, mck2ui 16
5593 23:10:05.306352 best dqsien dly found for B1: ( 0, 14, 18)
5594 23:10:05.312874 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5595 23:10:05.316069 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5596 23:10:05.316626
5597 23:10:05.319608 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5598 23:10:05.322699 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5599 23:10:05.325935 [Gating] SW calibration Done
5600 23:10:05.326486 ==
5601 23:10:05.329655 Dram Type= 6, Freq= 0, CH_1, rank 1
5602 23:10:05.332642 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5603 23:10:05.333253 ==
5604 23:10:05.336272 RX Vref Scan: 0
5605 23:10:05.336909
5606 23:10:05.337309 RX Vref 0 -> 0, step: 1
5607 23:10:05.337657
5608 23:10:05.339461 RX Delay -80 -> 252, step: 8
5609 23:10:05.342427 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5610 23:10:05.348955 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5611 23:10:05.353056 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5612 23:10:05.355744 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5613 23:10:05.359230 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5614 23:10:05.362583 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5615 23:10:05.365943 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5616 23:10:05.369591 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5617 23:10:05.375729 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5618 23:10:05.378869 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5619 23:10:05.382303 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5620 23:10:05.385462 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5621 23:10:05.388897 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5622 23:10:05.395498 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5623 23:10:05.398601 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5624 23:10:05.402067 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5625 23:10:05.402620 ==
5626 23:10:05.405573 Dram Type= 6, Freq= 0, CH_1, rank 1
5627 23:10:05.408871 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5628 23:10:05.409427 ==
5629 23:10:05.412039 DQS Delay:
5630 23:10:05.412592 DQS0 = 0, DQS1 = 0
5631 23:10:05.415426 DQM Delay:
5632 23:10:05.415975 DQM0 = 98, DQM1 = 87
5633 23:10:05.416340 DQ Delay:
5634 23:10:05.418827 DQ0 =99, DQ1 =95, DQ2 =91, DQ3 =95
5635 23:10:05.422015 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5636 23:10:05.425650 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =79
5637 23:10:05.428501 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5638 23:10:05.429104
5639 23:10:05.429476
5640 23:10:05.431964 ==
5641 23:10:05.432517 Dram Type= 6, Freq= 0, CH_1, rank 1
5642 23:10:05.438542 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5643 23:10:05.439094 ==
5644 23:10:05.439457
5645 23:10:05.439794
5646 23:10:05.441570 TX Vref Scan disable
5647 23:10:05.442094 == TX Byte 0 ==
5648 23:10:05.444939 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5649 23:10:05.452190 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5650 23:10:05.452982 == TX Byte 1 ==
5651 23:10:05.455403 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5652 23:10:05.461671 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5653 23:10:05.462378 ==
5654 23:10:05.464928 Dram Type= 6, Freq= 0, CH_1, rank 1
5655 23:10:05.468305 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5656 23:10:05.468802 ==
5657 23:10:05.469173
5658 23:10:05.469510
5659 23:10:05.471933 TX Vref Scan disable
5660 23:10:05.474548 == TX Byte 0 ==
5661 23:10:05.478388 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5662 23:10:05.481218 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5663 23:10:05.484944 == TX Byte 1 ==
5664 23:10:05.488097 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5665 23:10:05.491630 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5666 23:10:05.492192
5667 23:10:05.494861 [DATLAT]
5668 23:10:05.495412 Freq=933, CH1 RK1
5669 23:10:05.495782
5670 23:10:05.498076 DATLAT Default: 0xb
5671 23:10:05.498539 0, 0xFFFF, sum = 0
5672 23:10:05.501460 1, 0xFFFF, sum = 0
5673 23:10:05.502052 2, 0xFFFF, sum = 0
5674 23:10:05.504463 3, 0xFFFF, sum = 0
5675 23:10:05.505071 4, 0xFFFF, sum = 0
5676 23:10:05.508288 5, 0xFFFF, sum = 0
5677 23:10:05.508898 6, 0xFFFF, sum = 0
5678 23:10:05.511220 7, 0xFFFF, sum = 0
5679 23:10:05.511800 8, 0xFFFF, sum = 0
5680 23:10:05.514566 9, 0xFFFF, sum = 0
5681 23:10:05.515140 10, 0x0, sum = 1
5682 23:10:05.517911 11, 0x0, sum = 2
5683 23:10:05.518483 12, 0x0, sum = 3
5684 23:10:05.521288 13, 0x0, sum = 4
5685 23:10:05.521860 best_step = 11
5686 23:10:05.522230
5687 23:10:05.522569 ==
5688 23:10:05.524595 Dram Type= 6, Freq= 0, CH_1, rank 1
5689 23:10:05.530925 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5690 23:10:05.531492 ==
5691 23:10:05.531860 RX Vref Scan: 0
5692 23:10:05.532199
5693 23:10:05.534335 RX Vref 0 -> 0, step: 1
5694 23:10:05.534795
5695 23:10:05.537405 RX Delay -69 -> 252, step: 4
5696 23:10:05.541179 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5697 23:10:05.544255 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5698 23:10:05.551170 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5699 23:10:05.553840 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5700 23:10:05.557411 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5701 23:10:05.560863 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5702 23:10:05.564073 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5703 23:10:05.566992 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5704 23:10:05.573699 iDelay=203, Bit 8, Center 72 (-17 ~ 162) 180
5705 23:10:05.577119 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5706 23:10:05.580739 iDelay=203, Bit 10, Center 86 (-5 ~ 178) 184
5707 23:10:05.584026 iDelay=203, Bit 11, Center 80 (-9 ~ 170) 180
5708 23:10:05.587290 iDelay=203, Bit 12, Center 96 (7 ~ 186) 180
5709 23:10:05.593696 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5710 23:10:05.597108 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5711 23:10:05.600224 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5712 23:10:05.600685 ==
5713 23:10:05.603485 Dram Type= 6, Freq= 0, CH_1, rank 1
5714 23:10:05.607063 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5715 23:10:05.607528 ==
5716 23:10:05.610335 DQS Delay:
5717 23:10:05.610793 DQS0 = 0, DQS1 = 0
5718 23:10:05.611153 DQM Delay:
5719 23:10:05.613552 DQM0 = 96, DQM1 = 87
5720 23:10:05.614014 DQ Delay:
5721 23:10:05.616958 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =92
5722 23:10:05.620524 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5723 23:10:05.623683 DQ8 =72, DQ9 =74, DQ10 =86, DQ11 =80
5724 23:10:05.626968 DQ12 =96, DQ13 =96, DQ14 =98, DQ15 =96
5725 23:10:05.627428
5726 23:10:05.627793
5727 23:10:05.636993 [DQSOSCAuto] RK1, (LSB)MR18= 0x2525, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5728 23:10:05.639993 CH1 RK1: MR19=505, MR18=2525
5729 23:10:05.643418 CH1_RK1: MR19=0x505, MR18=0x2525, DQSOSC=410, MR23=63, INC=64, DEC=42
5730 23:10:05.647349 [RxdqsGatingPostProcess] freq 933
5731 23:10:05.653694 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5732 23:10:05.656649 Pre-setting of DQS Precalculation
5733 23:10:05.660270 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5734 23:10:05.670491 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5735 23:10:05.676931 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5736 23:10:05.677474
5737 23:10:05.677839
5738 23:10:05.680295 [Calibration Summary] 1866 Mbps
5739 23:10:05.680880 CH 0, Rank 0
5740 23:10:05.683321 SW Impedance : PASS
5741 23:10:05.683783 DUTY Scan : NO K
5742 23:10:05.686887 ZQ Calibration : PASS
5743 23:10:05.690073 Jitter Meter : NO K
5744 23:10:05.690641 CBT Training : PASS
5745 23:10:05.693212 Write leveling : PASS
5746 23:10:05.697111 RX DQS gating : PASS
5747 23:10:05.697675 RX DQ/DQS(RDDQC) : PASS
5748 23:10:05.700382 TX DQ/DQS : PASS
5749 23:10:05.703511 RX DATLAT : PASS
5750 23:10:05.704066 RX DQ/DQS(Engine): PASS
5751 23:10:05.707043 TX OE : NO K
5752 23:10:05.707578 All Pass.
5753 23:10:05.707941
5754 23:10:05.709945 CH 0, Rank 1
5755 23:10:05.710403 SW Impedance : PASS
5756 23:10:05.713037 DUTY Scan : NO K
5757 23:10:05.717175 ZQ Calibration : PASS
5758 23:10:05.717724 Jitter Meter : NO K
5759 23:10:05.719860 CBT Training : PASS
5760 23:10:05.720322 Write leveling : PASS
5761 23:10:05.723307 RX DQS gating : PASS
5762 23:10:05.727008 RX DQ/DQS(RDDQC) : PASS
5763 23:10:05.727560 TX DQ/DQS : PASS
5764 23:10:05.729812 RX DATLAT : PASS
5765 23:10:05.733113 RX DQ/DQS(Engine): PASS
5766 23:10:05.733578 TX OE : NO K
5767 23:10:05.737133 All Pass.
5768 23:10:05.737668
5769 23:10:05.738031 CH 1, Rank 0
5770 23:10:05.739920 SW Impedance : PASS
5771 23:10:05.740380 DUTY Scan : NO K
5772 23:10:05.743073 ZQ Calibration : PASS
5773 23:10:05.746520 Jitter Meter : NO K
5774 23:10:05.747009 CBT Training : PASS
5775 23:10:05.750182 Write leveling : PASS
5776 23:10:05.753455 RX DQS gating : PASS
5777 23:10:05.753909 RX DQ/DQS(RDDQC) : PASS
5778 23:10:05.756192 TX DQ/DQS : PASS
5779 23:10:05.759674 RX DATLAT : PASS
5780 23:10:05.760238 RX DQ/DQS(Engine): PASS
5781 23:10:05.763578 TX OE : NO K
5782 23:10:05.764107 All Pass.
5783 23:10:05.764469
5784 23:10:05.766227 CH 1, Rank 1
5785 23:10:05.766682 SW Impedance : PASS
5786 23:10:05.769577 DUTY Scan : NO K
5787 23:10:05.773329 ZQ Calibration : PASS
5788 23:10:05.773792 Jitter Meter : NO K
5789 23:10:05.776263 CBT Training : PASS
5790 23:10:05.776897 Write leveling : PASS
5791 23:10:05.779742 RX DQS gating : PASS
5792 23:10:05.782900 RX DQ/DQS(RDDQC) : PASS
5793 23:10:05.783467 TX DQ/DQS : PASS
5794 23:10:05.786308 RX DATLAT : PASS
5795 23:10:05.789441 RX DQ/DQS(Engine): PASS
5796 23:10:05.789913 TX OE : NO K
5797 23:10:05.792796 All Pass.
5798 23:10:05.793348
5799 23:10:05.793708 DramC Write-DBI off
5800 23:10:05.796500 PER_BANK_REFRESH: Hybrid Mode
5801 23:10:05.799377 TX_TRACKING: ON
5802 23:10:05.806225 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5803 23:10:05.809320 [FAST_K] Save calibration result to emmc
5804 23:10:05.816542 dramc_set_vcore_voltage set vcore to 650000
5805 23:10:05.817205 Read voltage for 400, 6
5806 23:10:05.817599 Vio18 = 0
5807 23:10:05.818900 Vcore = 650000
5808 23:10:05.819410 Vdram = 0
5809 23:10:05.819781 Vddq = 0
5810 23:10:05.822511 Vmddr = 0
5811 23:10:05.825545 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5812 23:10:05.832302 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5813 23:10:05.835791 MEM_TYPE=3, freq_sel=20
5814 23:10:05.836346 sv_algorithm_assistance_LP4_800
5815 23:10:05.842252 ============ PULL DRAM RESETB DOWN ============
5816 23:10:05.845553 ========== PULL DRAM RESETB DOWN end =========
5817 23:10:05.848796 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5818 23:10:05.852232 ===================================
5819 23:10:05.855522 LPDDR4 DRAM CONFIGURATION
5820 23:10:05.858828 ===================================
5821 23:10:05.862384 EX_ROW_EN[0] = 0x0
5822 23:10:05.862953 EX_ROW_EN[1] = 0x0
5823 23:10:05.865547 LP4Y_EN = 0x0
5824 23:10:05.866019 WORK_FSP = 0x0
5825 23:10:05.868760 WL = 0x2
5826 23:10:05.869239 RL = 0x2
5827 23:10:05.872581 BL = 0x2
5828 23:10:05.873207 RPST = 0x0
5829 23:10:05.875521 RD_PRE = 0x0
5830 23:10:05.876087 WR_PRE = 0x1
5831 23:10:05.878835 WR_PST = 0x0
5832 23:10:05.879416 DBI_WR = 0x0
5833 23:10:05.882578 DBI_RD = 0x0
5834 23:10:05.883141 OTF = 0x1
5835 23:10:05.886231 ===================================
5836 23:10:05.889049 ===================================
5837 23:10:05.892181 ANA top config
5838 23:10:05.895600 ===================================
5839 23:10:05.898776 DLL_ASYNC_EN = 0
5840 23:10:05.899237 ALL_SLAVE_EN = 1
5841 23:10:05.902127 NEW_RANK_MODE = 1
5842 23:10:05.905675 DLL_IDLE_MODE = 1
5843 23:10:05.908979 LP45_APHY_COMB_EN = 1
5844 23:10:05.909532 TX_ODT_DIS = 1
5845 23:10:05.912314 NEW_8X_MODE = 1
5846 23:10:05.915312 ===================================
5847 23:10:05.918743 ===================================
5848 23:10:05.922446 data_rate = 800
5849 23:10:05.925141 CKR = 1
5850 23:10:05.928553 DQ_P2S_RATIO = 4
5851 23:10:05.932170 ===================================
5852 23:10:05.935547 CA_P2S_RATIO = 4
5853 23:10:05.936320 DQ_CA_OPEN = 0
5854 23:10:05.938696 DQ_SEMI_OPEN = 1
5855 23:10:05.941457 CA_SEMI_OPEN = 1
5856 23:10:05.944887 CA_FULL_RATE = 0
5857 23:10:05.948216 DQ_CKDIV4_EN = 0
5858 23:10:05.952121 CA_CKDIV4_EN = 1
5859 23:10:05.952786 CA_PREDIV_EN = 0
5860 23:10:05.955359 PH8_DLY = 0
5861 23:10:05.958360 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5862 23:10:05.961639 DQ_AAMCK_DIV = 0
5863 23:10:05.964931 CA_AAMCK_DIV = 0
5864 23:10:05.968278 CA_ADMCK_DIV = 4
5865 23:10:05.968778 DQ_TRACK_CA_EN = 0
5866 23:10:05.971557 CA_PICK = 800
5867 23:10:05.974759 CA_MCKIO = 400
5868 23:10:05.978334 MCKIO_SEMI = 400
5869 23:10:05.981233 PLL_FREQ = 3016
5870 23:10:05.984515 DQ_UI_PI_RATIO = 32
5871 23:10:05.988137 CA_UI_PI_RATIO = 32
5872 23:10:05.991703 ===================================
5873 23:10:05.994794 ===================================
5874 23:10:05.995362 memory_type:LPDDR4
5875 23:10:05.998066 GP_NUM : 10
5876 23:10:06.001566 SRAM_EN : 1
5877 23:10:06.002136 MD32_EN : 0
5878 23:10:06.004874 ===================================
5879 23:10:06.008273 [ANA_INIT] >>>>>>>>>>>>>>
5880 23:10:06.011426 <<<<<< [CONFIGURE PHASE]: ANA_TX
5881 23:10:06.014577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5882 23:10:06.017794 ===================================
5883 23:10:06.021546 data_rate = 800,PCW = 0X7400
5884 23:10:06.024646 ===================================
5885 23:10:06.027886 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5886 23:10:06.031720 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5887 23:10:06.044287 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5888 23:10:06.047578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5889 23:10:06.051043 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5890 23:10:06.053904 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5891 23:10:06.057426 [ANA_INIT] flow start
5892 23:10:06.060691 [ANA_INIT] PLL >>>>>>>>
5893 23:10:06.061199 [ANA_INIT] PLL <<<<<<<<
5894 23:10:06.064303 [ANA_INIT] MIDPI >>>>>>>>
5895 23:10:06.067425 [ANA_INIT] MIDPI <<<<<<<<
5896 23:10:06.067891 [ANA_INIT] DLL >>>>>>>>
5897 23:10:06.070703 [ANA_INIT] flow end
5898 23:10:06.074018 ============ LP4 DIFF to SE enter ============
5899 23:10:06.081038 ============ LP4 DIFF to SE exit ============
5900 23:10:06.081602 [ANA_INIT] <<<<<<<<<<<<<
5901 23:10:06.084009 [Flow] Enable top DCM control >>>>>
5902 23:10:06.087306 [Flow] Enable top DCM control <<<<<
5903 23:10:06.090530 Enable DLL master slave shuffle
5904 23:10:06.097428 ==============================================================
5905 23:10:06.097967 Gating Mode config
5906 23:10:06.104267 ==============================================================
5907 23:10:06.107227 Config description:
5908 23:10:06.113987 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5909 23:10:06.120586 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5910 23:10:06.127134 SELPH_MODE 0: By rank 1: By Phase
5911 23:10:06.133650 ==============================================================
5912 23:10:06.137477 GAT_TRACK_EN = 0
5913 23:10:06.138046 RX_GATING_MODE = 2
5914 23:10:06.140187 RX_GATING_TRACK_MODE = 2
5915 23:10:06.143772 SELPH_MODE = 1
5916 23:10:06.147197 PICG_EARLY_EN = 1
5917 23:10:06.150108 VALID_LAT_VALUE = 1
5918 23:10:06.156702 ==============================================================
5919 23:10:06.160229 Enter into Gating configuration >>>>
5920 23:10:06.163357 Exit from Gating configuration <<<<
5921 23:10:06.166373 Enter into DVFS_PRE_config >>>>>
5922 23:10:06.176347 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5923 23:10:06.180061 Exit from DVFS_PRE_config <<<<<
5924 23:10:06.183551 Enter into PICG configuration >>>>
5925 23:10:06.186355 Exit from PICG configuration <<<<
5926 23:10:06.189831 [RX_INPUT] configuration >>>>>
5927 23:10:06.193012 [RX_INPUT] configuration <<<<<
5928 23:10:06.196157 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5929 23:10:06.203125 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5930 23:10:06.209602 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5931 23:10:06.216159 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5932 23:10:06.219709 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5933 23:10:06.225948 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5934 23:10:06.229391 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5935 23:10:06.236234 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5936 23:10:06.239349 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5937 23:10:06.242585 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5938 23:10:06.245681 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5939 23:10:06.252459 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5940 23:10:06.256061 ===================================
5941 23:10:06.258767 LPDDR4 DRAM CONFIGURATION
5942 23:10:06.262420 ===================================
5943 23:10:06.262882 EX_ROW_EN[0] = 0x0
5944 23:10:06.265405 EX_ROW_EN[1] = 0x0
5945 23:10:06.265862 LP4Y_EN = 0x0
5946 23:10:06.268787 WORK_FSP = 0x0
5947 23:10:06.269246 WL = 0x2
5948 23:10:06.272305 RL = 0x2
5949 23:10:06.272820 BL = 0x2
5950 23:10:06.275537 RPST = 0x0
5951 23:10:06.276056 RD_PRE = 0x0
5952 23:10:06.278891 WR_PRE = 0x1
5953 23:10:06.279476 WR_PST = 0x0
5954 23:10:06.282150 DBI_WR = 0x0
5955 23:10:06.282608 DBI_RD = 0x0
5956 23:10:06.285642 OTF = 0x1
5957 23:10:06.288960 ===================================
5958 23:10:06.292443 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5959 23:10:06.295366 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5960 23:10:06.302456 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5961 23:10:06.305703 ===================================
5962 23:10:06.308700 LPDDR4 DRAM CONFIGURATION
5963 23:10:06.311852 ===================================
5964 23:10:06.312312 EX_ROW_EN[0] = 0x10
5965 23:10:06.315479 EX_ROW_EN[1] = 0x0
5966 23:10:06.315941 LP4Y_EN = 0x0
5967 23:10:06.318424 WORK_FSP = 0x0
5968 23:10:06.318882 WL = 0x2
5969 23:10:06.321734 RL = 0x2
5970 23:10:06.322189 BL = 0x2
5971 23:10:06.325567 RPST = 0x0
5972 23:10:06.326116 RD_PRE = 0x0
5973 23:10:06.328583 WR_PRE = 0x1
5974 23:10:06.329182 WR_PST = 0x0
5975 23:10:06.331693 DBI_WR = 0x0
5976 23:10:06.334963 DBI_RD = 0x0
5977 23:10:06.335517 OTF = 0x1
5978 23:10:06.338264 ===================================
5979 23:10:06.344754 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5980 23:10:06.348211 nWR fixed to 30
5981 23:10:06.351589 [ModeRegInit_LP4] CH0 RK0
5982 23:10:06.352047 [ModeRegInit_LP4] CH0 RK1
5983 23:10:06.355330 [ModeRegInit_LP4] CH1 RK0
5984 23:10:06.358077 [ModeRegInit_LP4] CH1 RK1
5985 23:10:06.358533 match AC timing 18
5986 23:10:06.364827 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5987 23:10:06.368553 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5988 23:10:06.371360 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5989 23:10:06.377835 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5990 23:10:06.381445 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5991 23:10:06.382007 ==
5992 23:10:06.384497 Dram Type= 6, Freq= 0, CH_0, rank 0
5993 23:10:06.387728 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5994 23:10:06.388182 ==
5995 23:10:06.394715 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5996 23:10:06.401229 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5997 23:10:06.404373 [CA 0] Center 36 (8~64) winsize 57
5998 23:10:06.407550 [CA 1] Center 36 (8~64) winsize 57
5999 23:10:06.411095 [CA 2] Center 36 (8~64) winsize 57
6000 23:10:06.414276 [CA 3] Center 36 (8~64) winsize 57
6001 23:10:06.417395 [CA 4] Center 36 (8~64) winsize 57
6002 23:10:06.417852 [CA 5] Center 36 (8~64) winsize 57
6003 23:10:06.421037
6004 23:10:06.424167 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6005 23:10:06.424762
6006 23:10:06.427632 [CATrainingPosCal] consider 1 rank data
6007 23:10:06.430830 u2DelayCellTimex100 = 270/100 ps
6008 23:10:06.434087 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6009 23:10:06.437270 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6010 23:10:06.440662 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6011 23:10:06.444163 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6012 23:10:06.447218 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6013 23:10:06.450676 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6014 23:10:06.451231
6015 23:10:06.454357 CA PerBit enable=1, Macro0, CA PI delay=36
6016 23:10:06.457094
6017 23:10:06.457545 [CBTSetCACLKResult] CA Dly = 36
6018 23:10:06.460817 CS Dly: 1 (0~32)
6019 23:10:06.461386 ==
6020 23:10:06.464101 Dram Type= 6, Freq= 0, CH_0, rank 1
6021 23:10:06.467231 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6022 23:10:06.467785 ==
6023 23:10:06.473679 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6024 23:10:06.480369 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6025 23:10:06.483892 [CA 0] Center 36 (8~64) winsize 57
6026 23:10:06.486989 [CA 1] Center 36 (8~64) winsize 57
6027 23:10:06.490504 [CA 2] Center 36 (8~64) winsize 57
6028 23:10:06.491050 [CA 3] Center 36 (8~64) winsize 57
6029 23:10:06.493397 [CA 4] Center 36 (8~64) winsize 57
6030 23:10:06.497049 [CA 5] Center 36 (8~64) winsize 57
6031 23:10:06.497595
6032 23:10:06.503894 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6033 23:10:06.504447
6034 23:10:06.507041 [CATrainingPosCal] consider 2 rank data
6035 23:10:06.510185 u2DelayCellTimex100 = 270/100 ps
6036 23:10:06.513591 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6037 23:10:06.516616 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6038 23:10:06.519807 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6039 23:10:06.522981 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6040 23:10:06.526365 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6041 23:10:06.530022 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6042 23:10:06.530539
6043 23:10:06.533554 CA PerBit enable=1, Macro0, CA PI delay=36
6044 23:10:06.534107
6045 23:10:06.536665 [CBTSetCACLKResult] CA Dly = 36
6046 23:10:06.539773 CS Dly: 1 (0~32)
6047 23:10:06.540241
6048 23:10:06.543161 ----->DramcWriteLeveling(PI) begin...
6049 23:10:06.543622 ==
6050 23:10:06.546552 Dram Type= 6, Freq= 0, CH_0, rank 0
6051 23:10:06.550329 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6052 23:10:06.550946 ==
6053 23:10:06.553251 Write leveling (Byte 0): 32 => 0
6054 23:10:06.556120 Write leveling (Byte 1): 32 => 0
6055 23:10:06.559627 DramcWriteLeveling(PI) end<-----
6056 23:10:06.560083
6057 23:10:06.560440 ==
6058 23:10:06.562747 Dram Type= 6, Freq= 0, CH_0, rank 0
6059 23:10:06.566201 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6060 23:10:06.566656 ==
6061 23:10:06.569284 [Gating] SW mode calibration
6062 23:10:06.576083 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6063 23:10:06.582714 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6064 23:10:06.586105 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6065 23:10:06.589173 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6066 23:10:06.596112 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6067 23:10:06.599566 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6068 23:10:06.602780 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6069 23:10:06.609222 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6070 23:10:06.612364 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6071 23:10:06.615794 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6072 23:10:06.622419 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6073 23:10:06.625371 Total UI for P1: 0, mck2ui 16
6074 23:10:06.628658 best dqsien dly found for B0: ( 0, 10, 16)
6075 23:10:06.632418 Total UI for P1: 0, mck2ui 16
6076 23:10:06.635400 best dqsien dly found for B1: ( 0, 10, 16)
6077 23:10:06.638892 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6078 23:10:06.642326 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6079 23:10:06.642834
6080 23:10:06.645102 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6081 23:10:06.648514 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6082 23:10:06.651743 [Gating] SW calibration Done
6083 23:10:06.652200 ==
6084 23:10:06.655233 Dram Type= 6, Freq= 0, CH_0, rank 0
6085 23:10:06.659091 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6086 23:10:06.662143 ==
6087 23:10:06.662726 RX Vref Scan: 0
6088 23:10:06.663094
6089 23:10:06.665211 RX Vref 0 -> 0, step: 1
6090 23:10:06.665663
6091 23:10:06.668682 RX Delay -410 -> 252, step: 16
6092 23:10:06.672010 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6093 23:10:06.675324 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6094 23:10:06.678709 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6095 23:10:06.684899 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6096 23:10:06.688533 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6097 23:10:06.691671 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6098 23:10:06.695137 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6099 23:10:06.701605 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6100 23:10:06.704787 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6101 23:10:06.708498 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6102 23:10:06.711519 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6103 23:10:06.718301 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6104 23:10:06.721416 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6105 23:10:06.724861 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6106 23:10:06.731526 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6107 23:10:06.734633 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6108 23:10:06.735185 ==
6109 23:10:06.737576 Dram Type= 6, Freq= 0, CH_0, rank 0
6110 23:10:06.741383 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6111 23:10:06.742071 ==
6112 23:10:06.744409 DQS Delay:
6113 23:10:06.744926 DQS0 = 43, DQS1 = 59
6114 23:10:06.745378 DQM Delay:
6115 23:10:06.747743 DQM0 = 5, DQM1 = 14
6116 23:10:06.748405 DQ Delay:
6117 23:10:06.751070 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6118 23:10:06.754194 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6119 23:10:06.758019 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6120 23:10:06.761279 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6121 23:10:06.761737
6122 23:10:06.762092
6123 23:10:06.762433 ==
6124 23:10:06.764230 Dram Type= 6, Freq= 0, CH_0, rank 0
6125 23:10:06.767492 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6126 23:10:06.771171 ==
6127 23:10:06.771724
6128 23:10:06.772079
6129 23:10:06.772409 TX Vref Scan disable
6130 23:10:06.774017 == TX Byte 0 ==
6131 23:10:06.777357 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6132 23:10:06.781235 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6133 23:10:06.784066 == TX Byte 1 ==
6134 23:10:06.787259 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6135 23:10:06.790717 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6136 23:10:06.791275 ==
6137 23:10:06.794348 Dram Type= 6, Freq= 0, CH_0, rank 0
6138 23:10:06.800767 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6139 23:10:06.801322 ==
6140 23:10:06.801678
6141 23:10:06.802012
6142 23:10:06.802324 TX Vref Scan disable
6143 23:10:06.804130 == TX Byte 0 ==
6144 23:10:06.807404 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6145 23:10:06.810704 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6146 23:10:06.813790 == TX Byte 1 ==
6147 23:10:06.817363 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6148 23:10:06.821065 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6149 23:10:06.823551
6150 23:10:06.824001 [DATLAT]
6151 23:10:06.824358 Freq=400, CH0 RK0
6152 23:10:06.824693
6153 23:10:06.827182 DATLAT Default: 0xf
6154 23:10:06.827795 0, 0xFFFF, sum = 0
6155 23:10:06.830630 1, 0xFFFF, sum = 0
6156 23:10:06.831221 2, 0xFFFF, sum = 0
6157 23:10:06.833540 3, 0xFFFF, sum = 0
6158 23:10:06.833997 4, 0xFFFF, sum = 0
6159 23:10:06.837501 5, 0xFFFF, sum = 0
6160 23:10:06.840289 6, 0xFFFF, sum = 0
6161 23:10:06.840799 7, 0xFFFF, sum = 0
6162 23:10:06.843484 8, 0xFFFF, sum = 0
6163 23:10:06.843949 9, 0xFFFF, sum = 0
6164 23:10:06.846826 10, 0xFFFF, sum = 0
6165 23:10:06.847287 11, 0xFFFF, sum = 0
6166 23:10:06.849918 12, 0x0, sum = 1
6167 23:10:06.850380 13, 0x0, sum = 2
6168 23:10:06.853672 14, 0x0, sum = 3
6169 23:10:06.854259 15, 0x0, sum = 4
6170 23:10:06.854873 best_step = 13
6171 23:10:06.856577
6172 23:10:06.857095 ==
6173 23:10:06.860289 Dram Type= 6, Freq= 0, CH_0, rank 0
6174 23:10:06.863450 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6175 23:10:06.864001 ==
6176 23:10:06.864367 RX Vref Scan: 1
6177 23:10:06.864698
6178 23:10:06.866998 RX Vref 0 -> 0, step: 1
6179 23:10:06.867552
6180 23:10:06.869902 RX Delay -359 -> 252, step: 8
6181 23:10:06.870356
6182 23:10:06.873273 Set Vref, RX VrefLevel [Byte0]: 47
6183 23:10:06.876536 [Byte1]: 48
6184 23:10:06.880483
6185 23:10:06.880982 Final RX Vref Byte 0 = 47 to rank0
6186 23:10:06.884161 Final RX Vref Byte 1 = 48 to rank0
6187 23:10:06.886963 Final RX Vref Byte 0 = 47 to rank1
6188 23:10:06.890691 Final RX Vref Byte 1 = 48 to rank1==
6189 23:10:06.893547 Dram Type= 6, Freq= 0, CH_0, rank 0
6190 23:10:06.900981 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6191 23:10:06.901540 ==
6192 23:10:06.901940 DQS Delay:
6193 23:10:06.904025 DQS0 = 52, DQS1 = 68
6194 23:10:06.904479 DQM Delay:
6195 23:10:06.904907 DQM0 = 10, DQM1 = 17
6196 23:10:06.906942 DQ Delay:
6197 23:10:06.910583 DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =4
6198 23:10:06.913589 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6199 23:10:06.914120 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6200 23:10:06.917451 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6201 23:10:06.920351
6202 23:10:06.920847
6203 23:10:06.927089 [DQSOSCAuto] RK0, (LSB)MR18= 0xaaaa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6204 23:10:06.930111 CH0 RK0: MR19=C0C, MR18=AAAA
6205 23:10:06.936845 CH0_RK0: MR19=0xC0C, MR18=0xAAAA, DQSOSC=388, MR23=63, INC=392, DEC=261
6206 23:10:06.937576 ==
6207 23:10:06.940112 Dram Type= 6, Freq= 0, CH_0, rank 1
6208 23:10:06.943224 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6209 23:10:06.943768 ==
6210 23:10:06.947128 [Gating] SW mode calibration
6211 23:10:06.953241 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6212 23:10:06.960438 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6213 23:10:06.963261 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6214 23:10:06.967035 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6215 23:10:06.973487 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6216 23:10:06.976758 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
6217 23:10:06.980011 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6218 23:10:06.986589 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6219 23:10:06.989567 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6220 23:10:06.993476 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6221 23:10:06.999598 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6222 23:10:07.000135 Total UI for P1: 0, mck2ui 16
6223 23:10:07.003186 best dqsien dly found for B0: ( 0, 10, 16)
6224 23:10:07.006731 Total UI for P1: 0, mck2ui 16
6225 23:10:07.009685 best dqsien dly found for B1: ( 0, 10, 16)
6226 23:10:07.016406 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6227 23:10:07.019823 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6228 23:10:07.020374
6229 23:10:07.023099 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6230 23:10:07.026426 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6231 23:10:07.029546 [Gating] SW calibration Done
6232 23:10:07.030098 ==
6233 23:10:07.032792 Dram Type= 6, Freq= 0, CH_0, rank 1
6234 23:10:07.036392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6235 23:10:07.037254 ==
6236 23:10:07.039582 RX Vref Scan: 0
6237 23:10:07.040134
6238 23:10:07.040491 RX Vref 0 -> 0, step: 1
6239 23:10:07.040970
6240 23:10:07.042711 RX Delay -410 -> 252, step: 16
6241 23:10:07.049475 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6242 23:10:07.052924 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6243 23:10:07.055921 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6244 23:10:07.059523 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6245 23:10:07.065736 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6246 23:10:07.069422 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6247 23:10:07.072652 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6248 23:10:07.076014 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6249 23:10:07.082816 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6250 23:10:07.085451 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6251 23:10:07.088911 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6252 23:10:07.092450 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6253 23:10:07.098995 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6254 23:10:07.102389 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6255 23:10:07.105632 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6256 23:10:07.112295 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6257 23:10:07.112882 ==
6258 23:10:07.115664 Dram Type= 6, Freq= 0, CH_0, rank 1
6259 23:10:07.118910 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6260 23:10:07.119468 ==
6261 23:10:07.119829 DQS Delay:
6262 23:10:07.122103 DQS0 = 43, DQS1 = 59
6263 23:10:07.122556 DQM Delay:
6264 23:10:07.125657 DQM0 = 6, DQM1 = 15
6265 23:10:07.126206 DQ Delay:
6266 23:10:07.128912 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6267 23:10:07.132271 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6268 23:10:07.135783 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6269 23:10:07.139052 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6270 23:10:07.139734
6271 23:10:07.140095
6272 23:10:07.140423 ==
6273 23:10:07.142454 Dram Type= 6, Freq= 0, CH_0, rank 1
6274 23:10:07.145553 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6275 23:10:07.146010 ==
6276 23:10:07.146459
6277 23:10:07.146805
6278 23:10:07.148537 TX Vref Scan disable
6279 23:10:07.149073 == TX Byte 0 ==
6280 23:10:07.155585 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6281 23:10:07.158837 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6282 23:10:07.159450 == TX Byte 1 ==
6283 23:10:07.161796 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6284 23:10:07.168813 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6285 23:10:07.169394 ==
6286 23:10:07.172123 Dram Type= 6, Freq= 0, CH_0, rank 1
6287 23:10:07.175354 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6288 23:10:07.175812 ==
6289 23:10:07.176172
6290 23:10:07.176502
6291 23:10:07.178763 TX Vref Scan disable
6292 23:10:07.179340 == TX Byte 0 ==
6293 23:10:07.185418 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6294 23:10:07.188399 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6295 23:10:07.189025 == TX Byte 1 ==
6296 23:10:07.195678 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6297 23:10:07.198445 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6298 23:10:07.198867
6299 23:10:07.199225 [DATLAT]
6300 23:10:07.201892 Freq=400, CH0 RK1
6301 23:10:07.202298
6302 23:10:07.202618 DATLAT Default: 0xd
6303 23:10:07.205109 0, 0xFFFF, sum = 0
6304 23:10:07.205521 1, 0xFFFF, sum = 0
6305 23:10:07.208865 2, 0xFFFF, sum = 0
6306 23:10:07.209377 3, 0xFFFF, sum = 0
6307 23:10:07.212084 4, 0xFFFF, sum = 0
6308 23:10:07.212609 5, 0xFFFF, sum = 0
6309 23:10:07.215125 6, 0xFFFF, sum = 0
6310 23:10:07.215700 7, 0xFFFF, sum = 0
6311 23:10:07.218951 8, 0xFFFF, sum = 0
6312 23:10:07.219476 9, 0xFFFF, sum = 0
6313 23:10:07.221440 10, 0xFFFF, sum = 0
6314 23:10:07.224605 11, 0xFFFF, sum = 0
6315 23:10:07.225066 12, 0x0, sum = 1
6316 23:10:07.225401 13, 0x0, sum = 2
6317 23:10:07.228315 14, 0x0, sum = 3
6318 23:10:07.228868 15, 0x0, sum = 4
6319 23:10:07.231286 best_step = 13
6320 23:10:07.231806
6321 23:10:07.232128 ==
6322 23:10:07.235358 Dram Type= 6, Freq= 0, CH_0, rank 1
6323 23:10:07.237703 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6324 23:10:07.238198 ==
6325 23:10:07.241154 RX Vref Scan: 0
6326 23:10:07.241562
6327 23:10:07.241879 RX Vref 0 -> 0, step: 1
6328 23:10:07.244596
6329 23:10:07.245160 RX Delay -359 -> 252, step: 8
6330 23:10:07.252844 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6331 23:10:07.256265 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6332 23:10:07.259821 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6333 23:10:07.263284 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6334 23:10:07.269914 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6335 23:10:07.273182 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6336 23:10:07.276053 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6337 23:10:07.279940 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6338 23:10:07.286240 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6339 23:10:07.289386 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6340 23:10:07.292904 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6341 23:10:07.299561 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6342 23:10:07.302522 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6343 23:10:07.305901 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6344 23:10:07.309098 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6345 23:10:07.315666 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6346 23:10:07.316183 ==
6347 23:10:07.318989 Dram Type= 6, Freq= 0, CH_0, rank 1
6348 23:10:07.322323 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6349 23:10:07.322870 ==
6350 23:10:07.323230 DQS Delay:
6351 23:10:07.326066 DQS0 = 52, DQS1 = 60
6352 23:10:07.326615 DQM Delay:
6353 23:10:07.329096 DQM0 = 10, DQM1 = 9
6354 23:10:07.329642 DQ Delay:
6355 23:10:07.332175 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6356 23:10:07.335478 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6357 23:10:07.339394 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6358 23:10:07.342152 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =16
6359 23:10:07.342677
6360 23:10:07.343037
6361 23:10:07.348435 [DQSOSCAuto] RK1, (LSB)MR18= 0xb6b6, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6362 23:10:07.352063 CH0 RK1: MR19=C0C, MR18=B6B6
6363 23:10:07.358596 CH0_RK1: MR19=0xC0C, MR18=0xB6B6, DQSOSC=387, MR23=63, INC=394, DEC=262
6364 23:10:07.362622 [RxdqsGatingPostProcess] freq 400
6365 23:10:07.368426 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6366 23:10:07.371850 Pre-setting of DQS Precalculation
6367 23:10:07.375262 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6368 23:10:07.375803 ==
6369 23:10:07.378686 Dram Type= 6, Freq= 0, CH_1, rank 0
6370 23:10:07.382403 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6371 23:10:07.385337 ==
6372 23:10:07.388603 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6373 23:10:07.395179 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6374 23:10:07.398193 [CA 0] Center 36 (8~64) winsize 57
6375 23:10:07.401836 [CA 1] Center 36 (8~64) winsize 57
6376 23:10:07.405152 [CA 2] Center 36 (8~64) winsize 57
6377 23:10:07.408331 [CA 3] Center 36 (8~64) winsize 57
6378 23:10:07.411620 [CA 4] Center 36 (8~64) winsize 57
6379 23:10:07.414954 [CA 5] Center 36 (8~64) winsize 57
6380 23:10:07.415364
6381 23:10:07.418087 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6382 23:10:07.418498
6383 23:10:07.421425 [CATrainingPosCal] consider 1 rank data
6384 23:10:07.424852 u2DelayCellTimex100 = 270/100 ps
6385 23:10:07.427868 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6386 23:10:07.431590 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6387 23:10:07.434365 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6388 23:10:07.438005 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6389 23:10:07.441573 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6390 23:10:07.444813 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6391 23:10:07.445230
6392 23:10:07.451173 CA PerBit enable=1, Macro0, CA PI delay=36
6393 23:10:07.451588
6394 23:10:07.451911 [CBTSetCACLKResult] CA Dly = 36
6395 23:10:07.454421 CS Dly: 1 (0~32)
6396 23:10:07.454832 ==
6397 23:10:07.457661 Dram Type= 6, Freq= 0, CH_1, rank 1
6398 23:10:07.460985 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6399 23:10:07.461400 ==
6400 23:10:07.467866 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6401 23:10:07.474308 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6402 23:10:07.477789 [CA 0] Center 36 (8~64) winsize 57
6403 23:10:07.481250 [CA 1] Center 36 (8~64) winsize 57
6404 23:10:07.484329 [CA 2] Center 36 (8~64) winsize 57
6405 23:10:07.487762 [CA 3] Center 36 (8~64) winsize 57
6406 23:10:07.488319 [CA 4] Center 36 (8~64) winsize 57
6407 23:10:07.490708 [CA 5] Center 36 (8~64) winsize 57
6408 23:10:07.491162
6409 23:10:07.497457 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6410 23:10:07.498046
6411 23:10:07.500569 [CATrainingPosCal] consider 2 rank data
6412 23:10:07.504095 u2DelayCellTimex100 = 270/100 ps
6413 23:10:07.507663 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6414 23:10:07.510796 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6415 23:10:07.514090 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6416 23:10:07.517102 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6417 23:10:07.520493 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6418 23:10:07.523812 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6419 23:10:07.524274
6420 23:10:07.526890 CA PerBit enable=1, Macro0, CA PI delay=36
6421 23:10:07.527300
6422 23:10:07.530452 [CBTSetCACLKResult] CA Dly = 36
6423 23:10:07.534155 CS Dly: 1 (0~32)
6424 23:10:07.534709
6425 23:10:07.537090 ----->DramcWriteLeveling(PI) begin...
6426 23:10:07.537667 ==
6427 23:10:07.540374 Dram Type= 6, Freq= 0, CH_1, rank 0
6428 23:10:07.543482 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6429 23:10:07.543942 ==
6430 23:10:07.546370 Write leveling (Byte 0): 32 => 0
6431 23:10:07.550187 Write leveling (Byte 1): 32 => 0
6432 23:10:07.553379 DramcWriteLeveling(PI) end<-----
6433 23:10:07.553835
6434 23:10:07.554190 ==
6435 23:10:07.556846 Dram Type= 6, Freq= 0, CH_1, rank 0
6436 23:10:07.560029 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6437 23:10:07.560584 ==
6438 23:10:07.563338 [Gating] SW mode calibration
6439 23:10:07.570023 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6440 23:10:07.576434 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6441 23:10:07.580194 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6442 23:10:07.586949 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6443 23:10:07.590060 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6444 23:10:07.593431 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6445 23:10:07.599968 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6446 23:10:07.603561 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6447 23:10:07.606664 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6448 23:10:07.613121 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6449 23:10:07.616304 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6450 23:10:07.619565 Total UI for P1: 0, mck2ui 16
6451 23:10:07.622973 best dqsien dly found for B0: ( 0, 10, 16)
6452 23:10:07.626451 Total UI for P1: 0, mck2ui 16
6453 23:10:07.629581 best dqsien dly found for B1: ( 0, 10, 16)
6454 23:10:07.633099 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6455 23:10:07.636503 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6456 23:10:07.637089
6457 23:10:07.639458 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6458 23:10:07.642931 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6459 23:10:07.646059 [Gating] SW calibration Done
6460 23:10:07.646558 ==
6461 23:10:07.649193 Dram Type= 6, Freq= 0, CH_1, rank 0
6462 23:10:07.656433 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6463 23:10:07.657151 ==
6464 23:10:07.657525 RX Vref Scan: 0
6465 23:10:07.657858
6466 23:10:07.658976 RX Vref 0 -> 0, step: 1
6467 23:10:07.659430
6468 23:10:07.662362 RX Delay -410 -> 252, step: 16
6469 23:10:07.665571 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6470 23:10:07.669200 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6471 23:10:07.675745 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6472 23:10:07.678644 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6473 23:10:07.682348 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6474 23:10:07.685361 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6475 23:10:07.691972 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6476 23:10:07.695775 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6477 23:10:07.699150 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6478 23:10:07.702374 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6479 23:10:07.708774 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6480 23:10:07.711754 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6481 23:10:07.715382 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6482 23:10:07.718868 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6483 23:10:07.725350 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6484 23:10:07.728965 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6485 23:10:07.729538 ==
6486 23:10:07.731825 Dram Type= 6, Freq= 0, CH_1, rank 0
6487 23:10:07.735276 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6488 23:10:07.735973 ==
6489 23:10:07.739003 DQS Delay:
6490 23:10:07.739555 DQS0 = 43, DQS1 = 59
6491 23:10:07.741695 DQM Delay:
6492 23:10:07.742147 DQM0 = 6, DQM1 = 15
6493 23:10:07.742505 DQ Delay:
6494 23:10:07.745329 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6495 23:10:07.748075 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6496 23:10:07.752133 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6497 23:10:07.754792 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6498 23:10:07.755248
6499 23:10:07.755606
6500 23:10:07.755932 ==
6501 23:10:07.758665 Dram Type= 6, Freq= 0, CH_1, rank 0
6502 23:10:07.761710 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6503 23:10:07.765509 ==
6504 23:10:07.766062
6505 23:10:07.766424
6506 23:10:07.766757 TX Vref Scan disable
6507 23:10:07.767952 == TX Byte 0 ==
6508 23:10:07.771413 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6509 23:10:07.775046 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6510 23:10:07.777967 == TX Byte 1 ==
6511 23:10:07.781091 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6512 23:10:07.784950 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6513 23:10:07.785503 ==
6514 23:10:07.788241 Dram Type= 6, Freq= 0, CH_1, rank 0
6515 23:10:07.794928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6516 23:10:07.795488 ==
6517 23:10:07.795874
6518 23:10:07.796368
6519 23:10:07.796831 TX Vref Scan disable
6520 23:10:07.798129 == TX Byte 0 ==
6521 23:10:07.801607 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6522 23:10:07.808029 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6523 23:10:07.808595 == TX Byte 1 ==
6524 23:10:07.811549 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6525 23:10:07.818368 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6526 23:10:07.818903
6527 23:10:07.819265 [DATLAT]
6528 23:10:07.819599 Freq=400, CH1 RK0
6529 23:10:07.819921
6530 23:10:07.821198 DATLAT Default: 0xf
6531 23:10:07.821652 0, 0xFFFF, sum = 0
6532 23:10:07.824837 1, 0xFFFF, sum = 0
6533 23:10:07.825380 2, 0xFFFF, sum = 0
6534 23:10:07.828116 3, 0xFFFF, sum = 0
6535 23:10:07.831419 4, 0xFFFF, sum = 0
6536 23:10:07.831989 5, 0xFFFF, sum = 0
6537 23:10:07.834373 6, 0xFFFF, sum = 0
6538 23:10:07.834833 7, 0xFFFF, sum = 0
6539 23:10:07.837648 8, 0xFFFF, sum = 0
6540 23:10:07.838108 9, 0xFFFF, sum = 0
6541 23:10:07.841108 10, 0xFFFF, sum = 0
6542 23:10:07.841627 11, 0xFFFF, sum = 0
6543 23:10:07.844151 12, 0x0, sum = 1
6544 23:10:07.844611 13, 0x0, sum = 2
6545 23:10:07.847976 14, 0x0, sum = 3
6546 23:10:07.848439 15, 0x0, sum = 4
6547 23:10:07.848853 best_step = 13
6548 23:10:07.851377
6549 23:10:07.851875 ==
6550 23:10:07.854382 Dram Type= 6, Freq= 0, CH_1, rank 0
6551 23:10:07.857820 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6552 23:10:07.858301 ==
6553 23:10:07.858657 RX Vref Scan: 1
6554 23:10:07.858990
6555 23:10:07.861238 RX Vref 0 -> 0, step: 1
6556 23:10:07.861695
6557 23:10:07.864377 RX Delay -359 -> 252, step: 8
6558 23:10:07.864831
6559 23:10:07.867627 Set Vref, RX VrefLevel [Byte0]: 56
6560 23:10:07.870676 [Byte1]: 48
6561 23:10:07.874780
6562 23:10:07.875192 Final RX Vref Byte 0 = 56 to rank0
6563 23:10:07.878134 Final RX Vref Byte 1 = 48 to rank0
6564 23:10:07.881389 Final RX Vref Byte 0 = 56 to rank1
6565 23:10:07.884735 Final RX Vref Byte 1 = 48 to rank1==
6566 23:10:07.888007 Dram Type= 6, Freq= 0, CH_1, rank 0
6567 23:10:07.894670 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6568 23:10:07.895228 ==
6569 23:10:07.895595 DQS Delay:
6570 23:10:07.898084 DQS0 = 52, DQS1 = 68
6571 23:10:07.898587 DQM Delay:
6572 23:10:07.898921 DQM0 = 10, DQM1 = 19
6573 23:10:07.901421 DQ Delay:
6574 23:10:07.904555 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6575 23:10:07.905014 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6576 23:10:07.907991 DQ8 =0, DQ9 =12, DQ10 =20, DQ11 =12
6577 23:10:07.911356 DQ12 =28, DQ13 =28, DQ14 =28, DQ15 =28
6578 23:10:07.914546
6579 23:10:07.914956
6580 23:10:07.921095 [DQSOSCAuto] RK0, (LSB)MR18= 0xe1e1, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6581 23:10:07.924270 CH1 RK0: MR19=C0C, MR18=E1E1
6582 23:10:07.931108 CH1_RK0: MR19=0xC0C, MR18=0xE1E1, DQSOSC=382, MR23=63, INC=404, DEC=269
6583 23:10:07.931601 ==
6584 23:10:07.934057 Dram Type= 6, Freq= 0, CH_1, rank 1
6585 23:10:07.937449 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6586 23:10:07.937866 ==
6587 23:10:07.940940 [Gating] SW mode calibration
6588 23:10:07.947420 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6589 23:10:07.954466 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6590 23:10:07.957142 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6591 23:10:07.960586 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6592 23:10:07.967479 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6593 23:10:07.970791 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6594 23:10:07.974107 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6595 23:10:07.980817 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6596 23:10:07.983970 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6597 23:10:07.987490 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6598 23:10:07.994121 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6599 23:10:07.994599 Total UI for P1: 0, mck2ui 16
6600 23:10:07.997676 best dqsien dly found for B0: ( 0, 10, 16)
6601 23:10:08.001013 Total UI for P1: 0, mck2ui 16
6602 23:10:08.003966 best dqsien dly found for B1: ( 0, 10, 16)
6603 23:10:08.007429 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6604 23:10:08.014184 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6605 23:10:08.014703
6606 23:10:08.017367 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6607 23:10:08.020891 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6608 23:10:08.024315 [Gating] SW calibration Done
6609 23:10:08.024871 ==
6610 23:10:08.027813 Dram Type= 6, Freq= 0, CH_1, rank 1
6611 23:10:08.031005 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6612 23:10:08.031539 ==
6613 23:10:08.034032 RX Vref Scan: 0
6614 23:10:08.034494
6615 23:10:08.034852 RX Vref 0 -> 0, step: 1
6616 23:10:08.035191
6617 23:10:08.037347 RX Delay -410 -> 252, step: 16
6618 23:10:08.043811 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6619 23:10:08.047179 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6620 23:10:08.050418 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6621 23:10:08.054187 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6622 23:10:08.060550 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6623 23:10:08.063948 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6624 23:10:08.067182 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6625 23:10:08.070390 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6626 23:10:08.073696 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6627 23:10:08.080209 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6628 23:10:08.083536 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6629 23:10:08.087046 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6630 23:10:08.093726 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6631 23:10:08.096887 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6632 23:10:08.100045 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6633 23:10:08.103700 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6634 23:10:08.107150 ==
6635 23:10:08.107820 Dram Type= 6, Freq= 0, CH_1, rank 1
6636 23:10:08.113480 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6637 23:10:08.114141 ==
6638 23:10:08.114638 DQS Delay:
6639 23:10:08.116663 DQS0 = 43, DQS1 = 59
6640 23:10:08.117220 DQM Delay:
6641 23:10:08.120073 DQM0 = 9, DQM1 = 18
6642 23:10:08.120471 DQ Delay:
6643 23:10:08.123415 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6644 23:10:08.126946 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6645 23:10:08.130397 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6646 23:10:08.132976 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6647 23:10:08.133405
6648 23:10:08.133911
6649 23:10:08.134402 ==
6650 23:10:08.136927 Dram Type= 6, Freq= 0, CH_1, rank 1
6651 23:10:08.140148 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6652 23:10:08.140858 ==
6653 23:10:08.141361
6654 23:10:08.141681
6655 23:10:08.143403 TX Vref Scan disable
6656 23:10:08.143944 == TX Byte 0 ==
6657 23:10:08.149484 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6658 23:10:08.152888 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6659 23:10:08.153271 == TX Byte 1 ==
6660 23:10:08.156417 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6661 23:10:08.163482 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6662 23:10:08.164002 ==
6663 23:10:08.166210 Dram Type= 6, Freq= 0, CH_1, rank 1
6664 23:10:08.169708 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6665 23:10:08.170213 ==
6666 23:10:08.170544
6667 23:10:08.170845
6668 23:10:08.172974 TX Vref Scan disable
6669 23:10:08.173401 == TX Byte 0 ==
6670 23:10:08.179453 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6671 23:10:08.183407 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6672 23:10:08.183960 == TX Byte 1 ==
6673 23:10:08.189868 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6674 23:10:08.192820 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6675 23:10:08.193279
6676 23:10:08.193668 [DATLAT]
6677 23:10:08.196349 Freq=400, CH1 RK1
6678 23:10:08.196949
6679 23:10:08.197318 DATLAT Default: 0xd
6680 23:10:08.199539 0, 0xFFFF, sum = 0
6681 23:10:08.200025 1, 0xFFFF, sum = 0
6682 23:10:08.202974 2, 0xFFFF, sum = 0
6683 23:10:08.203441 3, 0xFFFF, sum = 0
6684 23:10:08.206387 4, 0xFFFF, sum = 0
6685 23:10:08.206944 5, 0xFFFF, sum = 0
6686 23:10:08.209298 6, 0xFFFF, sum = 0
6687 23:10:08.209908 7, 0xFFFF, sum = 0
6688 23:10:08.212564 8, 0xFFFF, sum = 0
6689 23:10:08.213088 9, 0xFFFF, sum = 0
6690 23:10:08.216008 10, 0xFFFF, sum = 0
6691 23:10:08.219215 11, 0xFFFF, sum = 0
6692 23:10:08.219637 12, 0x0, sum = 1
6693 23:10:08.219966 13, 0x0, sum = 2
6694 23:10:08.222816 14, 0x0, sum = 3
6695 23:10:08.223352 15, 0x0, sum = 4
6696 23:10:08.225859 best_step = 13
6697 23:10:08.226289
6698 23:10:08.226613 ==
6699 23:10:08.229357 Dram Type= 6, Freq= 0, CH_1, rank 1
6700 23:10:08.232523 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6701 23:10:08.233108 ==
6702 23:10:08.236160 RX Vref Scan: 0
6703 23:10:08.236755
6704 23:10:08.237125 RX Vref 0 -> 0, step: 1
6705 23:10:08.237460
6706 23:10:08.239207 RX Delay -359 -> 252, step: 8
6707 23:10:08.247341 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6708 23:10:08.250580 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6709 23:10:08.254080 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6710 23:10:08.260350 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6711 23:10:08.263672 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6712 23:10:08.267153 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6713 23:10:08.270370 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6714 23:10:08.276845 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6715 23:10:08.280772 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6716 23:10:08.283488 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6717 23:10:08.287367 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6718 23:10:08.293545 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6719 23:10:08.296883 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6720 23:10:08.300113 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6721 23:10:08.303618 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6722 23:10:08.310099 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6723 23:10:08.310577 ==
6724 23:10:08.313680 Dram Type= 6, Freq= 0, CH_1, rank 1
6725 23:10:08.316682 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6726 23:10:08.317218 ==
6727 23:10:08.317544 DQS Delay:
6728 23:10:08.320495 DQS0 = 48, DQS1 = 64
6729 23:10:08.320960 DQM Delay:
6730 23:10:08.323360 DQM0 = 9, DQM1 = 15
6731 23:10:08.323772 DQ Delay:
6732 23:10:08.327036 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6733 23:10:08.330143 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6734 23:10:08.333368 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6735 23:10:08.336672 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6736 23:10:08.337238
6737 23:10:08.337563
6738 23:10:08.343376 [DQSOSCAuto] RK1, (LSB)MR18= 0xadad, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
6739 23:10:08.346534 CH1 RK1: MR19=C0C, MR18=ADAD
6740 23:10:08.353196 CH1_RK1: MR19=0xC0C, MR18=0xADAD, DQSOSC=388, MR23=63, INC=392, DEC=261
6741 23:10:08.356742 [RxdqsGatingPostProcess] freq 400
6742 23:10:08.363240 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6743 23:10:08.363718 Pre-setting of DQS Precalculation
6744 23:10:08.369870 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6745 23:10:08.376437 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6746 23:10:08.383358 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6747 23:10:08.383834
6748 23:10:08.384157
6749 23:10:08.386795 [Calibration Summary] 800 Mbps
6750 23:10:08.389575 CH 0, Rank 0
6751 23:10:08.389985 SW Impedance : PASS
6752 23:10:08.393455 DUTY Scan : NO K
6753 23:10:08.396463 ZQ Calibration : PASS
6754 23:10:08.397009 Jitter Meter : NO K
6755 23:10:08.399741 CBT Training : PASS
6756 23:10:08.403162 Write leveling : PASS
6757 23:10:08.403658 RX DQS gating : PASS
6758 23:10:08.406279 RX DQ/DQS(RDDQC) : PASS
6759 23:10:08.409707 TX DQ/DQS : PASS
6760 23:10:08.410188 RX DATLAT : PASS
6761 23:10:08.412903 RX DQ/DQS(Engine): PASS
6762 23:10:08.413459 TX OE : NO K
6763 23:10:08.416095 All Pass.
6764 23:10:08.416639
6765 23:10:08.417060 CH 0, Rank 1
6766 23:10:08.419503 SW Impedance : PASS
6767 23:10:08.420049 DUTY Scan : NO K
6768 23:10:08.422635 ZQ Calibration : PASS
6769 23:10:08.426401 Jitter Meter : NO K
6770 23:10:08.426960 CBT Training : PASS
6771 23:10:08.429425 Write leveling : NO K
6772 23:10:08.432643 RX DQS gating : PASS
6773 23:10:08.433221 RX DQ/DQS(RDDQC) : PASS
6774 23:10:08.436399 TX DQ/DQS : PASS
6775 23:10:08.439469 RX DATLAT : PASS
6776 23:10:08.439974 RX DQ/DQS(Engine): PASS
6777 23:10:08.442356 TX OE : NO K
6778 23:10:08.442882 All Pass.
6779 23:10:08.443319
6780 23:10:08.446097 CH 1, Rank 0
6781 23:10:08.446547 SW Impedance : PASS
6782 23:10:08.449308 DUTY Scan : NO K
6783 23:10:08.452383 ZQ Calibration : PASS
6784 23:10:08.452826 Jitter Meter : NO K
6785 23:10:08.455824 CBT Training : PASS
6786 23:10:08.459339 Write leveling : PASS
6787 23:10:08.459847 RX DQS gating : PASS
6788 23:10:08.462452 RX DQ/DQS(RDDQC) : PASS
6789 23:10:08.465682 TX DQ/DQS : PASS
6790 23:10:08.466095 RX DATLAT : PASS
6791 23:10:08.469053 RX DQ/DQS(Engine): PASS
6792 23:10:08.469481 TX OE : NO K
6793 23:10:08.472210 All Pass.
6794 23:10:08.472624
6795 23:10:08.472999 CH 1, Rank 1
6796 23:10:08.475577 SW Impedance : PASS
6797 23:10:08.475985 DUTY Scan : NO K
6798 23:10:08.479143 ZQ Calibration : PASS
6799 23:10:08.482369 Jitter Meter : NO K
6800 23:10:08.482954 CBT Training : PASS
6801 23:10:08.485610 Write leveling : NO K
6802 23:10:08.489034 RX DQS gating : PASS
6803 23:10:08.489462 RX DQ/DQS(RDDQC) : PASS
6804 23:10:08.492557 TX DQ/DQS : PASS
6805 23:10:08.495770 RX DATLAT : PASS
6806 23:10:08.496181 RX DQ/DQS(Engine): PASS
6807 23:10:08.498943 TX OE : NO K
6808 23:10:08.499392 All Pass.
6809 23:10:08.499719
6810 23:10:08.502389 DramC Write-DBI off
6811 23:10:08.505745 PER_BANK_REFRESH: Hybrid Mode
6812 23:10:08.506250 TX_TRACKING: ON
6813 23:10:08.515666 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6814 23:10:08.518527 [FAST_K] Save calibration result to emmc
6815 23:10:08.522124 dramc_set_vcore_voltage set vcore to 725000
6816 23:10:08.525408 Read voltage for 1600, 0
6817 23:10:08.525904 Vio18 = 0
6818 23:10:08.526230 Vcore = 725000
6819 23:10:08.528591 Vdram = 0
6820 23:10:08.529155 Vddq = 0
6821 23:10:08.529486 Vmddr = 0
6822 23:10:08.535423 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6823 23:10:08.538519 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6824 23:10:08.542175 MEM_TYPE=3, freq_sel=13
6825 23:10:08.545197 sv_algorithm_assistance_LP4_3733
6826 23:10:08.548546 ============ PULL DRAM RESETB DOWN ============
6827 23:10:08.555003 ========== PULL DRAM RESETB DOWN end =========
6828 23:10:08.558494 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6829 23:10:08.561639 ===================================
6830 23:10:08.565194 LPDDR4 DRAM CONFIGURATION
6831 23:10:08.568392 ===================================
6832 23:10:08.568854 EX_ROW_EN[0] = 0x0
6833 23:10:08.571695 EX_ROW_EN[1] = 0x0
6834 23:10:08.572121 LP4Y_EN = 0x0
6835 23:10:08.574972 WORK_FSP = 0x1
6836 23:10:08.575387 WL = 0x5
6837 23:10:08.578282 RL = 0x5
6838 23:10:08.578694 BL = 0x2
6839 23:10:08.581472 RPST = 0x0
6840 23:10:08.581883 RD_PRE = 0x0
6841 23:10:08.584759 WR_PRE = 0x1
6842 23:10:08.588565 WR_PST = 0x1
6843 23:10:08.589137 DBI_WR = 0x0
6844 23:10:08.591537 DBI_RD = 0x0
6845 23:10:08.591982 OTF = 0x1
6846 23:10:08.595099 ===================================
6847 23:10:08.598494 ===================================
6848 23:10:08.598993 ANA top config
6849 23:10:08.601337 ===================================
6850 23:10:08.604926 DLL_ASYNC_EN = 0
6851 23:10:08.608520 ALL_SLAVE_EN = 0
6852 23:10:08.611603 NEW_RANK_MODE = 1
6853 23:10:08.614848 DLL_IDLE_MODE = 1
6854 23:10:08.615362 LP45_APHY_COMB_EN = 1
6855 23:10:08.618317 TX_ODT_DIS = 0
6856 23:10:08.621472 NEW_8X_MODE = 1
6857 23:10:08.625197 ===================================
6858 23:10:08.628407 ===================================
6859 23:10:08.631422 data_rate = 3200
6860 23:10:08.634649 CKR = 1
6861 23:10:08.635162 DQ_P2S_RATIO = 8
6862 23:10:08.637973 ===================================
6863 23:10:08.641599 CA_P2S_RATIO = 8
6864 23:10:08.644640 DQ_CA_OPEN = 0
6865 23:10:08.647778 DQ_SEMI_OPEN = 0
6866 23:10:08.651305 CA_SEMI_OPEN = 0
6867 23:10:08.654537 CA_FULL_RATE = 0
6868 23:10:08.655069 DQ_CKDIV4_EN = 0
6869 23:10:08.657805 CA_CKDIV4_EN = 0
6870 23:10:08.661007 CA_PREDIV_EN = 0
6871 23:10:08.664114 PH8_DLY = 12
6872 23:10:08.667321 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6873 23:10:08.670921 DQ_AAMCK_DIV = 4
6874 23:10:08.674100 CA_AAMCK_DIV = 4
6875 23:10:08.674606 CA_ADMCK_DIV = 4
6876 23:10:08.677593 DQ_TRACK_CA_EN = 0
6877 23:10:08.680643 CA_PICK = 1600
6878 23:10:08.684425 CA_MCKIO = 1600
6879 23:10:08.687360 MCKIO_SEMI = 0
6880 23:10:08.690615 PLL_FREQ = 3068
6881 23:10:08.694067 DQ_UI_PI_RATIO = 32
6882 23:10:08.694605 CA_UI_PI_RATIO = 0
6883 23:10:08.697342 ===================================
6884 23:10:08.700569 ===================================
6885 23:10:08.704035 memory_type:LPDDR4
6886 23:10:08.707100 GP_NUM : 10
6887 23:10:08.707576 SRAM_EN : 1
6888 23:10:08.710571 MD32_EN : 0
6889 23:10:08.713813 ===================================
6890 23:10:08.717372 [ANA_INIT] >>>>>>>>>>>>>>
6891 23:10:08.720672 <<<<<< [CONFIGURE PHASE]: ANA_TX
6892 23:10:08.723819 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6893 23:10:08.727198 ===================================
6894 23:10:08.727654 data_rate = 3200,PCW = 0X7600
6895 23:10:08.730549 ===================================
6896 23:10:08.734039 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6897 23:10:08.740338 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6898 23:10:08.746943 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6899 23:10:08.750190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6900 23:10:08.753533 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6901 23:10:08.756836 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6902 23:10:08.760406 [ANA_INIT] flow start
6903 23:10:08.763627 [ANA_INIT] PLL >>>>>>>>
6904 23:10:08.764144 [ANA_INIT] PLL <<<<<<<<
6905 23:10:08.766790 [ANA_INIT] MIDPI >>>>>>>>
6906 23:10:08.770047 [ANA_INIT] MIDPI <<<<<<<<
6907 23:10:08.770504 [ANA_INIT] DLL >>>>>>>>
6908 23:10:08.773623 [ANA_INIT] DLL <<<<<<<<
6909 23:10:08.776630 [ANA_INIT] flow end
6910 23:10:08.779822 ============ LP4 DIFF to SE enter ============
6911 23:10:08.783728 ============ LP4 DIFF to SE exit ============
6912 23:10:08.786915 [ANA_INIT] <<<<<<<<<<<<<
6913 23:10:08.789947 [Flow] Enable top DCM control >>>>>
6914 23:10:08.793203 [Flow] Enable top DCM control <<<<<
6915 23:10:08.796833 Enable DLL master slave shuffle
6916 23:10:08.799981 ==============================================================
6917 23:10:08.803324 Gating Mode config
6918 23:10:08.809936 ==============================================================
6919 23:10:08.810483 Config description:
6920 23:10:08.819767 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6921 23:10:08.826496 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6922 23:10:08.830106 SELPH_MODE 0: By rank 1: By Phase
6923 23:10:08.836330 ==============================================================
6924 23:10:08.839579 GAT_TRACK_EN = 1
6925 23:10:08.842950 RX_GATING_MODE = 2
6926 23:10:08.846230 RX_GATING_TRACK_MODE = 2
6927 23:10:08.849655 SELPH_MODE = 1
6928 23:10:08.852787 PICG_EARLY_EN = 1
6929 23:10:08.856126 VALID_LAT_VALUE = 1
6930 23:10:08.859642 ==============================================================
6931 23:10:08.862796 Enter into Gating configuration >>>>
6932 23:10:08.866067 Exit from Gating configuration <<<<
6933 23:10:08.869399 Enter into DVFS_PRE_config >>>>>
6934 23:10:08.882517 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6935 23:10:08.885739 Exit from DVFS_PRE_config <<<<<
6936 23:10:08.889262 Enter into PICG configuration >>>>
6937 23:10:08.889676 Exit from PICG configuration <<<<
6938 23:10:08.892657 [RX_INPUT] configuration >>>>>
6939 23:10:08.895874 [RX_INPUT] configuration <<<<<
6940 23:10:08.902947 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6941 23:10:08.905886 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6942 23:10:08.912384 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6943 23:10:08.918928 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6944 23:10:08.926309 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6945 23:10:08.932232 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6946 23:10:08.935450 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6947 23:10:08.938841 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6948 23:10:08.945757 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6949 23:10:08.949050 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6950 23:10:08.951881 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6951 23:10:08.955571 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6952 23:10:08.958939 ===================================
6953 23:10:08.961884 LPDDR4 DRAM CONFIGURATION
6954 23:10:08.965603 ===================================
6955 23:10:08.968473 EX_ROW_EN[0] = 0x0
6956 23:10:08.968919 EX_ROW_EN[1] = 0x0
6957 23:10:08.971687 LP4Y_EN = 0x0
6958 23:10:08.972094 WORK_FSP = 0x1
6959 23:10:08.975025 WL = 0x5
6960 23:10:08.975433 RL = 0x5
6961 23:10:08.978508 BL = 0x2
6962 23:10:08.978916 RPST = 0x0
6963 23:10:08.981683 RD_PRE = 0x0
6964 23:10:08.982172 WR_PRE = 0x1
6965 23:10:08.985061 WR_PST = 0x1
6966 23:10:08.985472 DBI_WR = 0x0
6967 23:10:08.988899 DBI_RD = 0x0
6968 23:10:08.991606 OTF = 0x1
6969 23:10:08.994887 ===================================
6970 23:10:08.998664 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6971 23:10:09.001699 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6972 23:10:09.005123 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6973 23:10:09.008364 ===================================
6974 23:10:09.011786 LPDDR4 DRAM CONFIGURATION
6975 23:10:09.015061 ===================================
6976 23:10:09.018373 EX_ROW_EN[0] = 0x10
6977 23:10:09.018863 EX_ROW_EN[1] = 0x0
6978 23:10:09.022009 LP4Y_EN = 0x0
6979 23:10:09.022420 WORK_FSP = 0x1
6980 23:10:09.024849 WL = 0x5
6981 23:10:09.025330 RL = 0x5
6982 23:10:09.028540 BL = 0x2
6983 23:10:09.028985 RPST = 0x0
6984 23:10:09.031598 RD_PRE = 0x0
6985 23:10:09.032080 WR_PRE = 0x1
6986 23:10:09.035057 WR_PST = 0x1
6987 23:10:09.035469 DBI_WR = 0x0
6988 23:10:09.038599 DBI_RD = 0x0
6989 23:10:09.039010 OTF = 0x1
6990 23:10:09.041626 ===================================
6991 23:10:09.048115 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6992 23:10:09.048654 ==
6993 23:10:09.051733 Dram Type= 6, Freq= 0, CH_0, rank 0
6994 23:10:09.058542 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6995 23:10:09.059028 ==
6996 23:10:09.059354 [Duty_Offset_Calibration]
6997 23:10:09.061274 B0:0 B1:2 CA:1
6998 23:10:09.061680
6999 23:10:09.064637 [DutyScan_Calibration_Flow] k_type=0
7000 23:10:09.074080
7001 23:10:09.074693 ==CLK 0==
7002 23:10:09.077343 Final CLK duty delay cell = 0
7003 23:10:09.081037 [0] MAX Duty = 5187%(X100), DQS PI = 24
7004 23:10:09.084400 [0] MIN Duty = 4938%(X100), DQS PI = 54
7005 23:10:09.087595 [0] AVG Duty = 5062%(X100)
7006 23:10:09.088143
7007 23:10:09.090952 CH0 CLK Duty spec in!! Max-Min= 249%
7008 23:10:09.093772 [DutyScan_Calibration_Flow] ====Done====
7009 23:10:09.094230
7010 23:10:09.097474 [DutyScan_Calibration_Flow] k_type=1
7011 23:10:09.114116
7012 23:10:09.114659 ==DQS 0 ==
7013 23:10:09.117336 Final DQS duty delay cell = 0
7014 23:10:09.120867 [0] MAX Duty = 5125%(X100), DQS PI = 22
7015 23:10:09.124401 [0] MIN Duty = 5031%(X100), DQS PI = 8
7016 23:10:09.127703 [0] AVG Duty = 5078%(X100)
7017 23:10:09.128253
7018 23:10:09.128611 ==DQS 1 ==
7019 23:10:09.131083 Final DQS duty delay cell = 0
7020 23:10:09.134415 [0] MAX Duty = 5031%(X100), DQS PI = 6
7021 23:10:09.137514 [0] MIN Duty = 4876%(X100), DQS PI = 16
7022 23:10:09.140836 [0] AVG Duty = 4953%(X100)
7023 23:10:09.141410
7024 23:10:09.144069 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7025 23:10:09.144598
7026 23:10:09.147165 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7027 23:10:09.150774 [DutyScan_Calibration_Flow] ====Done====
7028 23:10:09.151273
7029 23:10:09.153509 [DutyScan_Calibration_Flow] k_type=3
7030 23:10:09.171348
7031 23:10:09.171865 ==DQM 0 ==
7032 23:10:09.174768 Final DQM duty delay cell = 0
7033 23:10:09.177688 [0] MAX Duty = 5187%(X100), DQS PI = 20
7034 23:10:09.181237 [0] MIN Duty = 4907%(X100), DQS PI = 58
7035 23:10:09.184206 [0] AVG Duty = 5047%(X100)
7036 23:10:09.184661
7037 23:10:09.185083 ==DQM 1 ==
7038 23:10:09.187733 Final DQM duty delay cell = 0
7039 23:10:09.191040 [0] MAX Duty = 5031%(X100), DQS PI = 4
7040 23:10:09.194581 [0] MIN Duty = 4813%(X100), DQS PI = 14
7041 23:10:09.197814 [0] AVG Duty = 4922%(X100)
7042 23:10:09.198265
7043 23:10:09.201029 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7044 23:10:09.201482
7045 23:10:09.204324 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7046 23:10:09.207475 [DutyScan_Calibration_Flow] ====Done====
7047 23:10:09.207958
7048 23:10:09.210856 [DutyScan_Calibration_Flow] k_type=2
7049 23:10:09.227571
7050 23:10:09.228046 ==DQ 0 ==
7051 23:10:09.230943 Final DQ duty delay cell = 0
7052 23:10:09.234564 [0] MAX Duty = 5218%(X100), DQS PI = 18
7053 23:10:09.237479 [0] MIN Duty = 4938%(X100), DQS PI = 56
7054 23:10:09.237892 [0] AVG Duty = 5078%(X100)
7055 23:10:09.241120
7056 23:10:09.241600 ==DQ 1 ==
7057 23:10:09.243919 Final DQ duty delay cell = -4
7058 23:10:09.247484 [-4] MAX Duty = 5094%(X100), DQS PI = 4
7059 23:10:09.250395 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7060 23:10:09.253694 [-4] AVG Duty = 4969%(X100)
7061 23:10:09.254109
7062 23:10:09.256953 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7063 23:10:09.257444
7064 23:10:09.260249 CH0 DQ 1 Duty spec in!! Max-Min= 250%
7065 23:10:09.263544 [DutyScan_Calibration_Flow] ====Done====
7066 23:10:09.264066 ==
7067 23:10:09.267026 Dram Type= 6, Freq= 0, CH_1, rank 0
7068 23:10:09.270243 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7069 23:10:09.270736 ==
7070 23:10:09.273598 [Duty_Offset_Calibration]
7071 23:10:09.274159 B0:0 B1:4 CA:-5
7072 23:10:09.274510
7073 23:10:09.276736 [DutyScan_Calibration_Flow] k_type=0
7074 23:10:09.287820
7075 23:10:09.288298 ==CLK 0==
7076 23:10:09.291491 Final CLK duty delay cell = 0
7077 23:10:09.294596 [0] MAX Duty = 5187%(X100), DQS PI = 22
7078 23:10:09.298115 [0] MIN Duty = 4906%(X100), DQS PI = 52
7079 23:10:09.298634 [0] AVG Duty = 5046%(X100)
7080 23:10:09.301252
7081 23:10:09.304865 CH1 CLK Duty spec in!! Max-Min= 281%
7082 23:10:09.307784 [DutyScan_Calibration_Flow] ====Done====
7083 23:10:09.308193
7084 23:10:09.311460 [DutyScan_Calibration_Flow] k_type=1
7085 23:10:09.326773
7086 23:10:09.327315 ==DQS 0 ==
7087 23:10:09.330277 Final DQS duty delay cell = 0
7088 23:10:09.333737 [0] MAX Duty = 5187%(X100), DQS PI = 20
7089 23:10:09.336857 [0] MIN Duty = 4907%(X100), DQS PI = 42
7090 23:10:09.340430 [0] AVG Duty = 5047%(X100)
7091 23:10:09.341033
7092 23:10:09.341394 ==DQS 1 ==
7093 23:10:09.343380 Final DQS duty delay cell = -4
7094 23:10:09.347073 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7095 23:10:09.350278 [-4] MIN Duty = 4844%(X100), DQS PI = 42
7096 23:10:09.353168 [-4] AVG Duty = 4922%(X100)
7097 23:10:09.353621
7098 23:10:09.356872 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7099 23:10:09.357397
7100 23:10:09.359717 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7101 23:10:09.363376 [DutyScan_Calibration_Flow] ====Done====
7102 23:10:09.363832
7103 23:10:09.366661 [DutyScan_Calibration_Flow] k_type=3
7104 23:10:09.382598
7105 23:10:09.383109 ==DQM 0 ==
7106 23:10:09.385791 Final DQM duty delay cell = -4
7107 23:10:09.389479 [-4] MAX Duty = 5062%(X100), DQS PI = 32
7108 23:10:09.392414 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7109 23:10:09.396033 [-4] AVG Duty = 4937%(X100)
7110 23:10:09.396587
7111 23:10:09.397019 ==DQM 1 ==
7112 23:10:09.399406 Final DQM duty delay cell = -4
7113 23:10:09.402823 [-4] MAX Duty = 5093%(X100), DQS PI = 16
7114 23:10:09.405815 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7115 23:10:09.409011 [-4] AVG Duty = 5000%(X100)
7116 23:10:09.409559
7117 23:10:09.412523 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7118 23:10:09.413145
7119 23:10:09.415632 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7120 23:10:09.419153 [DutyScan_Calibration_Flow] ====Done====
7121 23:10:09.419611
7122 23:10:09.422211 [DutyScan_Calibration_Flow] k_type=2
7123 23:10:09.440380
7124 23:10:09.440944 ==DQ 0 ==
7125 23:10:09.443548 Final DQ duty delay cell = 0
7126 23:10:09.447285 [0] MAX Duty = 5093%(X100), DQS PI = 34
7127 23:10:09.450257 [0] MIN Duty = 4969%(X100), DQS PI = 46
7128 23:10:09.450717 [0] AVG Duty = 5031%(X100)
7129 23:10:09.453776
7130 23:10:09.454259 ==DQ 1 ==
7131 23:10:09.457443 Final DQ duty delay cell = 0
7132 23:10:09.460581 [0] MAX Duty = 5031%(X100), DQS PI = 4
7133 23:10:09.463624 [0] MIN Duty = 4876%(X100), DQS PI = 28
7134 23:10:09.464097 [0] AVG Duty = 4953%(X100)
7135 23:10:09.464456
7136 23:10:09.467058 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7137 23:10:09.470116
7138 23:10:09.473538 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7139 23:10:09.476868 [DutyScan_Calibration_Flow] ====Done====
7140 23:10:09.479871 nWR fixed to 30
7141 23:10:09.480328 [ModeRegInit_LP4] CH0 RK0
7142 23:10:09.483512 [ModeRegInit_LP4] CH0 RK1
7143 23:10:09.486862 [ModeRegInit_LP4] CH1 RK0
7144 23:10:09.490124 [ModeRegInit_LP4] CH1 RK1
7145 23:10:09.490579 match AC timing 4
7146 23:10:09.496665 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7147 23:10:09.499763 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7148 23:10:09.503072 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7149 23:10:09.509543 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7150 23:10:09.512923 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7151 23:10:09.513379 [MiockJmeterHQA]
7152 23:10:09.513736
7153 23:10:09.516052 [DramcMiockJmeter] u1RxGatingPI = 0
7154 23:10:09.520004 0 : 4253, 4027
7155 23:10:09.520578 4 : 4254, 4029
7156 23:10:09.523012 8 : 4363, 4137
7157 23:10:09.523474 12 : 4364, 4137
7158 23:10:09.526575 16 : 4366, 4140
7159 23:10:09.527171 20 : 4253, 4026
7160 23:10:09.527544 24 : 4253, 4026
7161 23:10:09.529874 28 : 4252, 4027
7162 23:10:09.530447 32 : 4364, 4137
7163 23:10:09.532668 36 : 4253, 4026
7164 23:10:09.533182 40 : 4363, 4138
7165 23:10:09.535942 44 : 4252, 4027
7166 23:10:09.536402 48 : 4253, 4027
7167 23:10:09.536804 52 : 4253, 4027
7168 23:10:09.539463 56 : 4255, 4030
7169 23:10:09.540033 60 : 4361, 4137
7170 23:10:09.543083 64 : 4250, 4026
7171 23:10:09.543649 68 : 4360, 4138
7172 23:10:09.546167 72 : 4250, 4027
7173 23:10:09.546628 76 : 4250, 4026
7174 23:10:09.549487 80 : 4250, 4027
7175 23:10:09.549955 84 : 4360, 4137
7176 23:10:09.550321 88 : 4250, 4026
7177 23:10:09.552682 92 : 4361, 4137
7178 23:10:09.553197 96 : 4250, 4026
7179 23:10:09.556066 100 : 4250, 2583
7180 23:10:09.556800 104 : 4361, 0
7181 23:10:09.559142 108 : 4253, 0
7182 23:10:09.559603 112 : 4253, 0
7183 23:10:09.560099 116 : 4250, 0
7184 23:10:09.562707 120 : 4250, 0
7185 23:10:09.563187 124 : 4253, 0
7186 23:10:09.565678 128 : 4250, 0
7187 23:10:09.566137 132 : 4250, 0
7188 23:10:09.566499 136 : 4253, 0
7189 23:10:09.569437 140 : 4360, 0
7190 23:10:09.569895 144 : 4249, 0
7191 23:10:09.572289 148 : 4250, 0
7192 23:10:09.572794 152 : 4250, 0
7193 23:10:09.573169 156 : 4361, 0
7194 23:10:09.575781 160 : 4361, 0
7195 23:10:09.576242 164 : 4250, 0
7196 23:10:09.576623 168 : 4251, 0
7197 23:10:09.579335 172 : 4250, 0
7198 23:10:09.579795 176 : 4253, 0
7199 23:10:09.582523 180 : 4250, 0
7200 23:10:09.582984 184 : 4250, 0
7201 23:10:09.583350 188 : 4253, 0
7202 23:10:09.586062 192 : 4250, 0
7203 23:10:09.586869 196 : 4250, 0
7204 23:10:09.588877 200 : 4252, 0
7205 23:10:09.589338 204 : 4250, 0
7206 23:10:09.589708 208 : 4361, 0
7207 23:10:09.592619 212 : 4361, 0
7208 23:10:09.593092 216 : 4250, 0
7209 23:10:09.595498 220 : 4250, 386
7210 23:10:09.595912 224 : 4253, 3966
7211 23:10:09.596238 228 : 4361, 4137
7212 23:10:09.599142 232 : 4250, 4027
7213 23:10:09.599561 236 : 4251, 4027
7214 23:10:09.602496 240 : 4250, 4026
7215 23:10:09.602912 244 : 4253, 4029
7216 23:10:09.605404 248 : 4250, 4027
7217 23:10:09.605821 252 : 4250, 4027
7218 23:10:09.608899 256 : 4250, 4026
7219 23:10:09.609318 260 : 4253, 4029
7220 23:10:09.612330 264 : 4250, 4027
7221 23:10:09.612782 268 : 4361, 4138
7222 23:10:09.615430 272 : 4360, 4137
7223 23:10:09.615848 276 : 4250, 4026
7224 23:10:09.618905 280 : 4363, 4140
7225 23:10:09.619321 284 : 4250, 4027
7226 23:10:09.621916 288 : 4251, 4027
7227 23:10:09.622379 292 : 4250, 4026
7228 23:10:09.622711 296 : 4253, 4029
7229 23:10:09.626107 300 : 4250, 4027
7230 23:10:09.626800 304 : 4250, 4027
7231 23:10:09.629206 308 : 4250, 4026
7232 23:10:09.629621 312 : 4253, 4029
7233 23:10:09.631993 316 : 4250, 4027
7234 23:10:09.632410 320 : 4361, 4138
7235 23:10:09.635597 324 : 4360, 4137
7236 23:10:09.636112 328 : 4250, 4026
7237 23:10:09.638715 332 : 4363, 4140
7238 23:10:09.639130 336 : 4250, 3956
7239 23:10:09.642473 340 : 4250, 2045
7240 23:10:09.642991
7241 23:10:09.643319 MIOCK jitter meter ch=0
7242 23:10:09.643621
7243 23:10:09.646090 1T = (340-104) = 236 dly cells
7244 23:10:09.651936 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7245 23:10:09.652385 ==
7246 23:10:09.655139 Dram Type= 6, Freq= 0, CH_0, rank 0
7247 23:10:09.658818 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7248 23:10:09.659334 ==
7249 23:10:09.665321 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7250 23:10:09.668542 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7251 23:10:09.671662 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7252 23:10:09.678646 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7253 23:10:09.687306 [CA 0] Center 41 (11~72) winsize 62
7254 23:10:09.690710 [CA 1] Center 41 (11~72) winsize 62
7255 23:10:09.693967 [CA 2] Center 37 (7~68) winsize 62
7256 23:10:09.697126 [CA 3] Center 37 (7~67) winsize 61
7257 23:10:09.700819 [CA 4] Center 35 (5~66) winsize 62
7258 23:10:09.704110 [CA 5] Center 35 (5~65) winsize 61
7259 23:10:09.704638
7260 23:10:09.707141 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7261 23:10:09.707553
7262 23:10:09.710585 [CATrainingPosCal] consider 1 rank data
7263 23:10:09.714108 u2DelayCellTimex100 = 275/100 ps
7264 23:10:09.720434 CA0 delay=41 (11~72),Diff = 6 PI (21 cell)
7265 23:10:09.723841 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7266 23:10:09.727234 CA2 delay=37 (7~68),Diff = 2 PI (7 cell)
7267 23:10:09.730804 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7268 23:10:09.733891 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7269 23:10:09.737434 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7270 23:10:09.737959
7271 23:10:09.740476 CA PerBit enable=1, Macro0, CA PI delay=35
7272 23:10:09.741031
7273 23:10:09.743969 [CBTSetCACLKResult] CA Dly = 35
7274 23:10:09.747388 CS Dly: 11 (0~42)
7275 23:10:09.750397 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7276 23:10:09.753691 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7277 23:10:09.754104 ==
7278 23:10:09.757187 Dram Type= 6, Freq= 0, CH_0, rank 1
7279 23:10:09.760587 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7280 23:10:09.763540 ==
7281 23:10:09.767337 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7282 23:10:09.770114 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7283 23:10:09.776669 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7284 23:10:09.783428 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7285 23:10:09.790430 [CA 0] Center 42 (12~73) winsize 62
7286 23:10:09.793273 [CA 1] Center 42 (12~73) winsize 62
7287 23:10:09.796992 [CA 2] Center 38 (9~68) winsize 60
7288 23:10:09.800172 [CA 3] Center 37 (8~67) winsize 60
7289 23:10:09.803708 [CA 4] Center 36 (6~66) winsize 61
7290 23:10:09.806666 [CA 5] Center 36 (6~66) winsize 61
7291 23:10:09.807086
7292 23:10:09.810276 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7293 23:10:09.810687
7294 23:10:09.813114 [CATrainingPosCal] consider 2 rank data
7295 23:10:09.816445 u2DelayCellTimex100 = 275/100 ps
7296 23:10:09.819918 CA0 delay=42 (12~72),Diff = 7 PI (24 cell)
7297 23:10:09.826572 CA1 delay=42 (12~72),Diff = 7 PI (24 cell)
7298 23:10:09.829552 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7299 23:10:09.833649 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7300 23:10:09.836402 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7301 23:10:09.839862 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7302 23:10:09.840379
7303 23:10:09.843285 CA PerBit enable=1, Macro0, CA PI delay=35
7304 23:10:09.843799
7305 23:10:09.846887 [CBTSetCACLKResult] CA Dly = 35
7306 23:10:09.849764 CS Dly: 11 (0~42)
7307 23:10:09.852733 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7308 23:10:09.856639 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7309 23:10:09.857204
7310 23:10:09.859737 ----->DramcWriteLeveling(PI) begin...
7311 23:10:09.860258 ==
7312 23:10:09.862974 Dram Type= 6, Freq= 0, CH_0, rank 0
7313 23:10:09.869398 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7314 23:10:09.869808 ==
7315 23:10:09.872784 Write leveling (Byte 0): 30 => 30
7316 23:10:09.876054 Write leveling (Byte 1): 27 => 27
7317 23:10:09.876482 DramcWriteLeveling(PI) end<-----
7318 23:10:09.876849
7319 23:10:09.879552 ==
7320 23:10:09.882559 Dram Type= 6, Freq= 0, CH_0, rank 0
7321 23:10:09.886155 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7322 23:10:09.886668 ==
7323 23:10:09.889629 [Gating] SW mode calibration
7324 23:10:09.895997 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7325 23:10:09.899562 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7326 23:10:09.906113 0 12 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7327 23:10:09.909523 0 12 4 | B1->B0 | 2b2a 3434 | 1 1 | (0 0) (1 1)
7328 23:10:09.913085 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7329 23:10:09.919395 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7330 23:10:09.922799 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7331 23:10:09.926097 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7332 23:10:09.932662 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7333 23:10:09.936157 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7334 23:10:09.939389 0 13 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7335 23:10:09.945826 0 13 4 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
7336 23:10:09.949186 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7337 23:10:09.952309 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7338 23:10:09.959234 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7339 23:10:09.962632 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7340 23:10:09.965869 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7341 23:10:09.972216 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7342 23:10:09.975756 0 14 0 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
7343 23:10:09.978923 0 14 4 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7344 23:10:09.985717 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7345 23:10:09.988912 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7346 23:10:09.992796 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7347 23:10:09.995503 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7348 23:10:10.002289 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7349 23:10:10.005704 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7350 23:10:10.009284 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7351 23:10:10.015552 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7352 23:10:10.018776 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7353 23:10:10.022660 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7354 23:10:10.028873 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7355 23:10:10.032043 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7356 23:10:10.035429 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7357 23:10:10.041871 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7358 23:10:10.045253 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7359 23:10:10.048560 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7360 23:10:10.055017 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7361 23:10:10.058275 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7362 23:10:10.061879 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7363 23:10:10.068656 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7364 23:10:10.071839 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7365 23:10:10.075050 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7366 23:10:10.081401 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7367 23:10:10.085298 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7368 23:10:10.088413 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7369 23:10:10.091722 Total UI for P1: 0, mck2ui 16
7370 23:10:10.094997 best dqsien dly found for B0: ( 1, 1, 2)
7371 23:10:10.101701 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7372 23:10:10.102277 Total UI for P1: 0, mck2ui 16
7373 23:10:10.108298 best dqsien dly found for B1: ( 1, 1, 6)
7374 23:10:10.111465 best DQS0 dly(MCK, UI, PI) = (1, 1, 2)
7375 23:10:10.115216 best DQS1 dly(MCK, UI, PI) = (1, 1, 6)
7376 23:10:10.115794
7377 23:10:10.117769 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 2)
7378 23:10:10.121372 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 6)
7379 23:10:10.124534 [Gating] SW calibration Done
7380 23:10:10.125122 ==
7381 23:10:10.127650 Dram Type= 6, Freq= 0, CH_0, rank 0
7382 23:10:10.131787 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7383 23:10:10.132378 ==
7384 23:10:10.134661 RX Vref Scan: 0
7385 23:10:10.135237
7386 23:10:10.135613 RX Vref 0 -> 0, step: 1
7387 23:10:10.135959
7388 23:10:10.137905 RX Delay 0 -> 252, step: 8
7389 23:10:10.141006 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7390 23:10:10.147951 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7391 23:10:10.151011 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7392 23:10:10.154328 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7393 23:10:10.157605 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7394 23:10:10.160966 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7395 23:10:10.167445 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7396 23:10:10.170628 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7397 23:10:10.173968 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7398 23:10:10.177375 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7399 23:10:10.180588 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7400 23:10:10.187620 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7401 23:10:10.190869 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7402 23:10:10.193814 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7403 23:10:10.197384 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7404 23:10:10.204155 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7405 23:10:10.204822 ==
7406 23:10:10.207325 Dram Type= 6, Freq= 0, CH_0, rank 0
7407 23:10:10.211105 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7408 23:10:10.211681 ==
7409 23:10:10.212052 DQS Delay:
7410 23:10:10.214140 DQS0 = 0, DQS1 = 0
7411 23:10:10.214707 DQM Delay:
7412 23:10:10.217297 DQM0 = 130, DQM1 = 123
7413 23:10:10.217858 DQ Delay:
7414 23:10:10.220304 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7415 23:10:10.223644 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7416 23:10:10.227230 DQ8 =115, DQ9 =107, DQ10 =119, DQ11 =115
7417 23:10:10.230895 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7418 23:10:10.231468
7419 23:10:10.231841
7420 23:10:10.232175 ==
7421 23:10:10.233647 Dram Type= 6, Freq= 0, CH_0, rank 0
7422 23:10:10.240553 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7423 23:10:10.241164 ==
7424 23:10:10.241536
7425 23:10:10.241876
7426 23:10:10.243598 TX Vref Scan disable
7427 23:10:10.244057 == TX Byte 0 ==
7428 23:10:10.247154 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7429 23:10:10.253739 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7430 23:10:10.254288 == TX Byte 1 ==
7431 23:10:10.256919 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7432 23:10:10.263713 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7433 23:10:10.264322 ==
7434 23:10:10.266924 Dram Type= 6, Freq= 0, CH_0, rank 0
7435 23:10:10.270665 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7436 23:10:10.271246 ==
7437 23:10:10.283083
7438 23:10:10.286455 TX Vref early break, caculate TX vref
7439 23:10:10.289892 TX Vref=16, minBit 8, minWin=22, winSum=372
7440 23:10:10.293108 TX Vref=18, minBit 8, minWin=22, winSum=378
7441 23:10:10.296632 TX Vref=20, minBit 8, minWin=23, winSum=392
7442 23:10:10.299713 TX Vref=22, minBit 8, minWin=24, winSum=398
7443 23:10:10.303363 TX Vref=24, minBit 8, minWin=24, winSum=406
7444 23:10:10.309599 TX Vref=26, minBit 3, minWin=25, winSum=411
7445 23:10:10.312969 TX Vref=28, minBit 9, minWin=24, winSum=413
7446 23:10:10.315994 TX Vref=30, minBit 0, minWin=25, winSum=413
7447 23:10:10.319538 TX Vref=32, minBit 2, minWin=24, winSum=398
7448 23:10:10.322753 TX Vref=34, minBit 8, minWin=23, winSum=391
7449 23:10:10.329472 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 30
7450 23:10:10.329990
7451 23:10:10.332766 Final TX Range 0 Vref 30
7452 23:10:10.333224
7453 23:10:10.333582 ==
7454 23:10:10.336324 Dram Type= 6, Freq= 0, CH_0, rank 0
7455 23:10:10.339289 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7456 23:10:10.339747 ==
7457 23:10:10.340107
7458 23:10:10.340435
7459 23:10:10.342556 TX Vref Scan disable
7460 23:10:10.349132 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7461 23:10:10.349795 == TX Byte 0 ==
7462 23:10:10.352355 u2DelayCellOfst[0]=14 cells (4 PI)
7463 23:10:10.355750 u2DelayCellOfst[1]=21 cells (6 PI)
7464 23:10:10.359007 u2DelayCellOfst[2]=14 cells (4 PI)
7465 23:10:10.362540 u2DelayCellOfst[3]=14 cells (4 PI)
7466 23:10:10.365710 u2DelayCellOfst[4]=7 cells (2 PI)
7467 23:10:10.369013 u2DelayCellOfst[5]=0 cells (0 PI)
7468 23:10:10.372296 u2DelayCellOfst[6]=17 cells (5 PI)
7469 23:10:10.375786 u2DelayCellOfst[7]=17 cells (5 PI)
7470 23:10:10.379132 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7471 23:10:10.382125 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7472 23:10:10.385748 == TX Byte 1 ==
7473 23:10:10.388690 u2DelayCellOfst[8]=0 cells (0 PI)
7474 23:10:10.389187 u2DelayCellOfst[9]=0 cells (0 PI)
7475 23:10:10.392234 u2DelayCellOfst[10]=7 cells (2 PI)
7476 23:10:10.395397 u2DelayCellOfst[11]=0 cells (0 PI)
7477 23:10:10.398773 u2DelayCellOfst[12]=10 cells (3 PI)
7478 23:10:10.401977 u2DelayCellOfst[13]=14 cells (4 PI)
7479 23:10:10.405414 u2DelayCellOfst[14]=17 cells (5 PI)
7480 23:10:10.408867 u2DelayCellOfst[15]=14 cells (4 PI)
7481 23:10:10.412446 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7482 23:10:10.418803 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7483 23:10:10.419345 DramC Write-DBI on
7484 23:10:10.419710 ==
7485 23:10:10.422154 Dram Type= 6, Freq= 0, CH_0, rank 0
7486 23:10:10.429124 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7487 23:10:10.429720 ==
7488 23:10:10.430093
7489 23:10:10.430433
7490 23:10:10.430754 TX Vref Scan disable
7491 23:10:10.432945 == TX Byte 0 ==
7492 23:10:10.436031 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7493 23:10:10.438942 == TX Byte 1 ==
7494 23:10:10.442519 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7495 23:10:10.445919 DramC Write-DBI off
7496 23:10:10.446484
7497 23:10:10.446939 [DATLAT]
7498 23:10:10.447286 Freq=1600, CH0 RK0
7499 23:10:10.447621
7500 23:10:10.448887 DATLAT Default: 0xf
7501 23:10:10.449347 0, 0xFFFF, sum = 0
7502 23:10:10.452897 1, 0xFFFF, sum = 0
7503 23:10:10.455736 2, 0xFFFF, sum = 0
7504 23:10:10.456205 3, 0xFFFF, sum = 0
7505 23:10:10.459343 4, 0xFFFF, sum = 0
7506 23:10:10.459919 5, 0xFFFF, sum = 0
7507 23:10:10.462006 6, 0xFFFF, sum = 0
7508 23:10:10.462475 7, 0xFFFF, sum = 0
7509 23:10:10.465897 8, 0xFFFF, sum = 0
7510 23:10:10.466364 9, 0xFFFF, sum = 0
7511 23:10:10.468805 10, 0xFFFF, sum = 0
7512 23:10:10.469316 11, 0xFFFF, sum = 0
7513 23:10:10.472174 12, 0xBFF, sum = 0
7514 23:10:10.472638 13, 0x0, sum = 1
7515 23:10:10.475508 14, 0x0, sum = 2
7516 23:10:10.475980 15, 0x0, sum = 3
7517 23:10:10.478804 16, 0x0, sum = 4
7518 23:10:10.479272 best_step = 14
7519 23:10:10.479636
7520 23:10:10.479974 ==
7521 23:10:10.482107 Dram Type= 6, Freq= 0, CH_0, rank 0
7522 23:10:10.485529 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7523 23:10:10.488873 ==
7524 23:10:10.489414 RX Vref Scan: 1
7525 23:10:10.489779
7526 23:10:10.492164 Set Vref Range= 24 -> 127
7527 23:10:10.492811
7528 23:10:10.495807 RX Vref 24 -> 127, step: 1
7529 23:10:10.496287
7530 23:10:10.496671 RX Delay 11 -> 252, step: 4
7531 23:10:10.497120
7532 23:10:10.498628 Set Vref, RX VrefLevel [Byte0]: 24
7533 23:10:10.501931 [Byte1]: 24
7534 23:10:10.505645
7535 23:10:10.506102 Set Vref, RX VrefLevel [Byte0]: 25
7536 23:10:10.509138 [Byte1]: 25
7537 23:10:10.513405
7538 23:10:10.513862 Set Vref, RX VrefLevel [Byte0]: 26
7539 23:10:10.516845 [Byte1]: 26
7540 23:10:10.520897
7541 23:10:10.521430 Set Vref, RX VrefLevel [Byte0]: 27
7542 23:10:10.524289 [Byte1]: 27
7543 23:10:10.528590
7544 23:10:10.529166 Set Vref, RX VrefLevel [Byte0]: 28
7545 23:10:10.531939 [Byte1]: 28
7546 23:10:10.536436
7547 23:10:10.537041 Set Vref, RX VrefLevel [Byte0]: 29
7548 23:10:10.539713 [Byte1]: 29
7549 23:10:10.543874
7550 23:10:10.544429 Set Vref, RX VrefLevel [Byte0]: 30
7551 23:10:10.547451 [Byte1]: 30
7552 23:10:10.551319
7553 23:10:10.551814 Set Vref, RX VrefLevel [Byte0]: 31
7554 23:10:10.554441 [Byte1]: 31
7555 23:10:10.559219
7556 23:10:10.559782 Set Vref, RX VrefLevel [Byte0]: 32
7557 23:10:10.562725 [Byte1]: 32
7558 23:10:10.567100
7559 23:10:10.567654 Set Vref, RX VrefLevel [Byte0]: 33
7560 23:10:10.570068 [Byte1]: 33
7561 23:10:10.574155
7562 23:10:10.574626 Set Vref, RX VrefLevel [Byte0]: 34
7563 23:10:10.577661 [Byte1]: 34
7564 23:10:10.581995
7565 23:10:10.582449 Set Vref, RX VrefLevel [Byte0]: 35
7566 23:10:10.584887 [Byte1]: 35
7567 23:10:10.589451
7568 23:10:10.589907 Set Vref, RX VrefLevel [Byte0]: 36
7569 23:10:10.592754 [Byte1]: 36
7570 23:10:10.596779
7571 23:10:10.597208 Set Vref, RX VrefLevel [Byte0]: 37
7572 23:10:10.600250 [Byte1]: 37
7573 23:10:10.604802
7574 23:10:10.605179 Set Vref, RX VrefLevel [Byte0]: 38
7575 23:10:10.608082 [Byte1]: 38
7576 23:10:10.612091
7577 23:10:10.612482 Set Vref, RX VrefLevel [Byte0]: 39
7578 23:10:10.615468 [Byte1]: 39
7579 23:10:10.620122
7580 23:10:10.620642 Set Vref, RX VrefLevel [Byte0]: 40
7581 23:10:10.623194 [Byte1]: 40
7582 23:10:10.627405
7583 23:10:10.627812 Set Vref, RX VrefLevel [Byte0]: 41
7584 23:10:10.630698 [Byte1]: 41
7585 23:10:10.634872
7586 23:10:10.635193 Set Vref, RX VrefLevel [Byte0]: 42
7587 23:10:10.638306 [Byte1]: 42
7588 23:10:10.642994
7589 23:10:10.643446 Set Vref, RX VrefLevel [Byte0]: 43
7590 23:10:10.646091 [Byte1]: 43
7591 23:10:10.650281
7592 23:10:10.650617 Set Vref, RX VrefLevel [Byte0]: 44
7593 23:10:10.653601 [Byte1]: 44
7594 23:10:10.657750
7595 23:10:10.658072 Set Vref, RX VrefLevel [Byte0]: 45
7596 23:10:10.661203 [Byte1]: 45
7597 23:10:10.665636
7598 23:10:10.666053 Set Vref, RX VrefLevel [Byte0]: 46
7599 23:10:10.668906 [Byte1]: 46
7600 23:10:10.672819
7601 23:10:10.673277 Set Vref, RX VrefLevel [Byte0]: 47
7602 23:10:10.676428 [Byte1]: 47
7603 23:10:10.680757
7604 23:10:10.681227 Set Vref, RX VrefLevel [Byte0]: 48
7605 23:10:10.684135 [Byte1]: 48
7606 23:10:10.688383
7607 23:10:10.688900 Set Vref, RX VrefLevel [Byte0]: 49
7608 23:10:10.691822 [Byte1]: 49
7609 23:10:10.695873
7610 23:10:10.696345 Set Vref, RX VrefLevel [Byte0]: 50
7611 23:10:10.699622 [Byte1]: 50
7612 23:10:10.703717
7613 23:10:10.704260 Set Vref, RX VrefLevel [Byte0]: 51
7614 23:10:10.706833 [Byte1]: 51
7615 23:10:10.711287
7616 23:10:10.711818 Set Vref, RX VrefLevel [Byte0]: 52
7617 23:10:10.714603 [Byte1]: 52
7618 23:10:10.719139
7619 23:10:10.719704 Set Vref, RX VrefLevel [Byte0]: 53
7620 23:10:10.722064 [Byte1]: 53
7621 23:10:10.726607
7622 23:10:10.727066 Set Vref, RX VrefLevel [Byte0]: 54
7623 23:10:10.730365 [Byte1]: 54
7624 23:10:10.734164
7625 23:10:10.734634 Set Vref, RX VrefLevel [Byte0]: 55
7626 23:10:10.737431 [Byte1]: 55
7627 23:10:10.741600
7628 23:10:10.742064 Set Vref, RX VrefLevel [Byte0]: 56
7629 23:10:10.744893 [Byte1]: 56
7630 23:10:10.749373
7631 23:10:10.749902 Set Vref, RX VrefLevel [Byte0]: 57
7632 23:10:10.752412 [Byte1]: 57
7633 23:10:10.757046
7634 23:10:10.757566 Set Vref, RX VrefLevel [Byte0]: 58
7635 23:10:10.760615 [Byte1]: 58
7636 23:10:10.764778
7637 23:10:10.765299 Set Vref, RX VrefLevel [Byte0]: 59
7638 23:10:10.767703 [Byte1]: 59
7639 23:10:10.772158
7640 23:10:10.772759 Set Vref, RX VrefLevel [Byte0]: 60
7641 23:10:10.775411 [Byte1]: 60
7642 23:10:10.779709
7643 23:10:10.780163 Set Vref, RX VrefLevel [Byte0]: 61
7644 23:10:10.782979 [Byte1]: 61
7645 23:10:10.787471
7646 23:10:10.788022 Set Vref, RX VrefLevel [Byte0]: 62
7647 23:10:10.791171 [Byte1]: 62
7648 23:10:10.795006
7649 23:10:10.795466 Set Vref, RX VrefLevel [Byte0]: 63
7650 23:10:10.798220 [Byte1]: 63
7651 23:10:10.803135
7652 23:10:10.803669 Set Vref, RX VrefLevel [Byte0]: 64
7653 23:10:10.805674 [Byte1]: 64
7654 23:10:10.810271
7655 23:10:10.810814 Set Vref, RX VrefLevel [Byte0]: 65
7656 23:10:10.813423 [Byte1]: 65
7657 23:10:10.818052
7658 23:10:10.818649 Set Vref, RX VrefLevel [Byte0]: 66
7659 23:10:10.821806 [Byte1]: 66
7660 23:10:10.825521
7661 23:10:10.825975 Set Vref, RX VrefLevel [Byte0]: 67
7662 23:10:10.828817 [Byte1]: 67
7663 23:10:10.833340
7664 23:10:10.833960 Set Vref, RX VrefLevel [Byte0]: 68
7665 23:10:10.836364 [Byte1]: 68
7666 23:10:10.840776
7667 23:10:10.841315 Set Vref, RX VrefLevel [Byte0]: 69
7668 23:10:10.843985 [Byte1]: 69
7669 23:10:10.848646
7670 23:10:10.849225 Set Vref, RX VrefLevel [Byte0]: 70
7671 23:10:10.851483 [Byte1]: 70
7672 23:10:10.856025
7673 23:10:10.856483 Set Vref, RX VrefLevel [Byte0]: 71
7674 23:10:10.859336 [Byte1]: 71
7675 23:10:10.863610
7676 23:10:10.864163 Set Vref, RX VrefLevel [Byte0]: 72
7677 23:10:10.866859 [Byte1]: 72
7678 23:10:10.871010
7679 23:10:10.871603 Final RX Vref Byte 0 = 53 to rank0
7680 23:10:10.874422 Final RX Vref Byte 1 = 56 to rank0
7681 23:10:10.877983 Final RX Vref Byte 0 = 53 to rank1
7682 23:10:10.881186 Final RX Vref Byte 1 = 56 to rank1==
7683 23:10:10.884651 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 23:10:10.891528 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7685 23:10:10.892083 ==
7686 23:10:10.892450 DQS Delay:
7687 23:10:10.894703 DQS0 = 0, DQS1 = 0
7688 23:10:10.895249 DQM Delay:
7689 23:10:10.895614 DQM0 = 127, DQM1 = 121
7690 23:10:10.897593 DQ Delay:
7691 23:10:10.901043 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =124
7692 23:10:10.904069 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7693 23:10:10.907825 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7694 23:10:10.910782 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7695 23:10:10.911477
7696 23:10:10.911968
7697 23:10:10.912418
7698 23:10:10.914014 [DramC_TX_OE_Calibration] TA2
7699 23:10:10.917715 Original DQ_B0 (3 6) =30, OEN = 27
7700 23:10:10.920638 Original DQ_B1 (3 6) =30, OEN = 27
7701 23:10:10.923748 24, 0x0, End_B0=24 End_B1=24
7702 23:10:10.927857 25, 0x0, End_B0=25 End_B1=25
7703 23:10:10.928610 26, 0x0, End_B0=26 End_B1=26
7704 23:10:10.930883 27, 0x0, End_B0=27 End_B1=27
7705 23:10:10.934112 28, 0x0, End_B0=28 End_B1=28
7706 23:10:10.937187 29, 0x0, End_B0=29 End_B1=29
7707 23:10:10.937658 30, 0x0, End_B0=30 End_B1=30
7708 23:10:10.940999 31, 0x4141, End_B0=30 End_B1=30
7709 23:10:10.944018 Byte0 end_step=30 best_step=27
7710 23:10:10.946928 Byte1 end_step=30 best_step=27
7711 23:10:10.950346 Byte0 TX OE(2T, 0.5T) = (3, 3)
7712 23:10:10.953359 Byte1 TX OE(2T, 0.5T) = (3, 3)
7713 23:10:10.953817
7714 23:10:10.954428
7715 23:10:10.960415 [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
7716 23:10:10.963450 CH0 RK0: MR19=303, MR18=1919
7717 23:10:10.970410 CH0_RK0: MR19=0x303, MR18=0x1919, DQSOSC=397, MR23=63, INC=23, DEC=15
7718 23:10:10.971078
7719 23:10:10.973180 ----->DramcWriteLeveling(PI) begin...
7720 23:10:10.973639 ==
7721 23:10:10.976762 Dram Type= 6, Freq= 0, CH_0, rank 1
7722 23:10:10.979799 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7723 23:10:10.980376 ==
7724 23:10:10.983443 Write leveling (Byte 0): 29 => 29
7725 23:10:10.986409 Write leveling (Byte 1): 27 => 27
7726 23:10:10.989968 DramcWriteLeveling(PI) end<-----
7727 23:10:10.990529
7728 23:10:10.990895 ==
7729 23:10:10.992914 Dram Type= 6, Freq= 0, CH_0, rank 1
7730 23:10:10.996743 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7731 23:10:10.999934 ==
7732 23:10:11.000482 [Gating] SW mode calibration
7733 23:10:11.009462 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7734 23:10:11.012941 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7735 23:10:11.016645 0 12 0 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
7736 23:10:11.022757 0 12 4 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7737 23:10:11.026465 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7738 23:10:11.029497 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7739 23:10:11.036117 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7740 23:10:11.039714 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7741 23:10:11.043074 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7742 23:10:11.049515 0 12 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7743 23:10:11.052647 0 13 0 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
7744 23:10:11.056094 0 13 4 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
7745 23:10:11.063320 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7746 23:10:11.065798 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7747 23:10:11.069394 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7748 23:10:11.075748 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7749 23:10:11.079068 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7750 23:10:11.082466 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7751 23:10:11.088913 0 14 0 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
7752 23:10:11.092121 0 14 4 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
7753 23:10:11.095994 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7754 23:10:11.102448 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7755 23:10:11.105522 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7756 23:10:11.109176 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7757 23:10:11.115503 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7758 23:10:11.118892 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7759 23:10:11.121915 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7760 23:10:11.128807 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7761 23:10:11.131744 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7762 23:10:11.135345 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7763 23:10:11.142712 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7764 23:10:11.145062 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7765 23:10:11.148649 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7766 23:10:11.155122 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7767 23:10:11.158642 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7768 23:10:11.161491 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7769 23:10:11.168298 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7770 23:10:11.171577 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7771 23:10:11.174749 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7772 23:10:11.181605 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7773 23:10:11.184646 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7774 23:10:11.188046 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7775 23:10:11.194396 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7776 23:10:11.197808 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7777 23:10:11.201093 Total UI for P1: 0, mck2ui 16
7778 23:10:11.204471 best dqsien dly found for B0: ( 1, 0, 28)
7779 23:10:11.207732 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7780 23:10:11.211108 Total UI for P1: 0, mck2ui 16
7781 23:10:11.214575 best dqsien dly found for B1: ( 1, 1, 2)
7782 23:10:11.217637 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7783 23:10:11.220825 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7784 23:10:11.221382
7785 23:10:11.227664 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7786 23:10:11.231067 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7787 23:10:11.231606 [Gating] SW calibration Done
7788 23:10:11.234284 ==
7789 23:10:11.234818 Dram Type= 6, Freq= 0, CH_0, rank 1
7790 23:10:11.240794 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7791 23:10:11.241336 ==
7792 23:10:11.241704 RX Vref Scan: 0
7793 23:10:11.242044
7794 23:10:11.244159 RX Vref 0 -> 0, step: 1
7795 23:10:11.244669
7796 23:10:11.247503 RX Delay 0 -> 252, step: 8
7797 23:10:11.250979 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7798 23:10:11.253776 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7799 23:10:11.257261 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7800 23:10:11.263845 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7801 23:10:11.267388 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7802 23:10:11.270531 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7803 23:10:11.273726 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7804 23:10:11.277149 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7805 23:10:11.283835 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7806 23:10:11.287137 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7807 23:10:11.290286 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7808 23:10:11.293620 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
7809 23:10:11.300217 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7810 23:10:11.303727 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7811 23:10:11.306866 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7812 23:10:11.310498 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7813 23:10:11.310959 ==
7814 23:10:11.313411 Dram Type= 6, Freq= 0, CH_0, rank 1
7815 23:10:11.319999 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7816 23:10:11.320534 ==
7817 23:10:11.320963 DQS Delay:
7818 23:10:11.321306 DQS0 = 0, DQS1 = 0
7819 23:10:11.323611 DQM Delay:
7820 23:10:11.324064 DQM0 = 132, DQM1 = 124
7821 23:10:11.326319 DQ Delay:
7822 23:10:11.330071 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
7823 23:10:11.333410 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =143
7824 23:10:11.336691 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7825 23:10:11.340106 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7826 23:10:11.340652
7827 23:10:11.341059
7828 23:10:11.341392 ==
7829 23:10:11.343314 Dram Type= 6, Freq= 0, CH_0, rank 1
7830 23:10:11.346603 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7831 23:10:11.349709 ==
7832 23:10:11.350230
7833 23:10:11.350593
7834 23:10:11.350927 TX Vref Scan disable
7835 23:10:11.353029 == TX Byte 0 ==
7836 23:10:11.356428 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7837 23:10:11.359796 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7838 23:10:11.363293 == TX Byte 1 ==
7839 23:10:11.366592 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7840 23:10:11.369444 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7841 23:10:11.372828 ==
7842 23:10:11.376352 Dram Type= 6, Freq= 0, CH_0, rank 1
7843 23:10:11.379358 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7844 23:10:11.379914 ==
7845 23:10:11.392866
7846 23:10:11.396340 TX Vref early break, caculate TX vref
7847 23:10:11.399134 TX Vref=16, minBit 1, minWin=22, winSum=373
7848 23:10:11.402858 TX Vref=18, minBit 11, minWin=22, winSum=382
7849 23:10:11.406484 TX Vref=20, minBit 1, minWin=23, winSum=394
7850 23:10:11.409288 TX Vref=22, minBit 1, minWin=24, winSum=400
7851 23:10:11.413472 TX Vref=24, minBit 8, minWin=23, winSum=402
7852 23:10:11.419429 TX Vref=26, minBit 8, minWin=24, winSum=415
7853 23:10:11.422664 TX Vref=28, minBit 1, minWin=25, winSum=416
7854 23:10:11.425505 TX Vref=30, minBit 7, minWin=24, winSum=416
7855 23:10:11.428892 TX Vref=32, minBit 11, minWin=24, winSum=404
7856 23:10:11.432306 TX Vref=34, minBit 1, minWin=24, winSum=400
7857 23:10:11.439090 TX Vref=36, minBit 8, minWin=23, winSum=389
7858 23:10:11.442231 [TxChooseVref] Worse bit 1, Min win 25, Win sum 416, Final Vref 28
7859 23:10:11.442825
7860 23:10:11.445704 Final TX Range 0 Vref 28
7861 23:10:11.446394
7862 23:10:11.446885 ==
7863 23:10:11.448898 Dram Type= 6, Freq= 0, CH_0, rank 1
7864 23:10:11.452041 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7865 23:10:11.452512 ==
7866 23:10:11.455250
7867 23:10:11.455720
7868 23:10:11.456193 TX Vref Scan disable
7869 23:10:11.462318 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7870 23:10:11.462921 == TX Byte 0 ==
7871 23:10:11.465455 u2DelayCellOfst[0]=14 cells (4 PI)
7872 23:10:11.468882 u2DelayCellOfst[1]=17 cells (5 PI)
7873 23:10:11.472219 u2DelayCellOfst[2]=14 cells (4 PI)
7874 23:10:11.475224 u2DelayCellOfst[3]=14 cells (4 PI)
7875 23:10:11.478745 u2DelayCellOfst[4]=10 cells (3 PI)
7876 23:10:11.481527 u2DelayCellOfst[5]=0 cells (0 PI)
7877 23:10:11.485057 u2DelayCellOfst[6]=17 cells (5 PI)
7878 23:10:11.488367 u2DelayCellOfst[7]=17 cells (5 PI)
7879 23:10:11.491679 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7880 23:10:11.494975 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7881 23:10:11.498090 == TX Byte 1 ==
7882 23:10:11.501457 u2DelayCellOfst[8]=3 cells (1 PI)
7883 23:10:11.504861 u2DelayCellOfst[9]=0 cells (0 PI)
7884 23:10:11.508089 u2DelayCellOfst[10]=10 cells (3 PI)
7885 23:10:11.511400 u2DelayCellOfst[11]=7 cells (2 PI)
7886 23:10:11.514750 u2DelayCellOfst[12]=14 cells (4 PI)
7887 23:10:11.518377 u2DelayCellOfst[13]=14 cells (4 PI)
7888 23:10:11.521436 u2DelayCellOfst[14]=17 cells (5 PI)
7889 23:10:11.524662 u2DelayCellOfst[15]=14 cells (4 PI)
7890 23:10:11.528678 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7891 23:10:11.531468 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7892 23:10:11.534847 DramC Write-DBI on
7893 23:10:11.535409 ==
7894 23:10:11.538165 Dram Type= 6, Freq= 0, CH_0, rank 1
7895 23:10:11.541200 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7896 23:10:11.541668 ==
7897 23:10:11.542031
7898 23:10:11.542367
7899 23:10:11.544785 TX Vref Scan disable
7900 23:10:11.545343 == TX Byte 0 ==
7901 23:10:11.551263 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7902 23:10:11.551835 == TX Byte 1 ==
7903 23:10:11.557643 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7904 23:10:11.558108 DramC Write-DBI off
7905 23:10:11.558469
7906 23:10:11.558812 [DATLAT]
7907 23:10:11.560933 Freq=1600, CH0 RK1
7908 23:10:11.561394
7909 23:10:11.561760 DATLAT Default: 0xe
7910 23:10:11.564283 0, 0xFFFF, sum = 0
7911 23:10:11.567505 1, 0xFFFF, sum = 0
7912 23:10:11.567971 2, 0xFFFF, sum = 0
7913 23:10:11.571182 3, 0xFFFF, sum = 0
7914 23:10:11.571747 4, 0xFFFF, sum = 0
7915 23:10:11.574055 5, 0xFFFF, sum = 0
7916 23:10:11.574525 6, 0xFFFF, sum = 0
7917 23:10:11.577461 7, 0xFFFF, sum = 0
7918 23:10:11.577925 8, 0xFFFF, sum = 0
7919 23:10:11.580740 9, 0xFFFF, sum = 0
7920 23:10:11.581227 10, 0xFFFF, sum = 0
7921 23:10:11.584473 11, 0xFFFF, sum = 0
7922 23:10:11.585003 12, 0x8FFF, sum = 0
7923 23:10:11.587357 13, 0x0, sum = 1
7924 23:10:11.587827 14, 0x0, sum = 2
7925 23:10:11.590951 15, 0x0, sum = 3
7926 23:10:11.591519 16, 0x0, sum = 4
7927 23:10:11.593788 best_step = 14
7928 23:10:11.594243
7929 23:10:11.594603 ==
7930 23:10:11.597199 Dram Type= 6, Freq= 0, CH_0, rank 1
7931 23:10:11.600575 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7932 23:10:11.601129 ==
7933 23:10:11.603988 RX Vref Scan: 0
7934 23:10:11.604444
7935 23:10:11.604845 RX Vref 0 -> 0, step: 1
7936 23:10:11.605198
7937 23:10:11.606923 RX Delay 11 -> 252, step: 4
7938 23:10:11.614121 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7939 23:10:11.616978 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7940 23:10:11.620388 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7941 23:10:11.623756 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7942 23:10:11.627349 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7943 23:10:11.633537 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7944 23:10:11.637050 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7945 23:10:11.640310 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7946 23:10:11.643402 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7947 23:10:11.647254 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7948 23:10:11.653657 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7949 23:10:11.656786 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7950 23:10:11.660066 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7951 23:10:11.663432 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7952 23:10:11.666928 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7953 23:10:11.673132 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7954 23:10:11.673665 ==
7955 23:10:11.676565 Dram Type= 6, Freq= 0, CH_0, rank 1
7956 23:10:11.679827 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7957 23:10:11.680292 ==
7958 23:10:11.680653 DQS Delay:
7959 23:10:11.683314 DQS0 = 0, DQS1 = 0
7960 23:10:11.683784 DQM Delay:
7961 23:10:11.686498 DQM0 = 128, DQM1 = 120
7962 23:10:11.686959 DQ Delay:
7963 23:10:11.689917 DQ0 =122, DQ1 =130, DQ2 =126, DQ3 =124
7964 23:10:11.693227 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
7965 23:10:11.696428 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7966 23:10:11.702935 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
7967 23:10:11.703456
7968 23:10:11.703821
7969 23:10:11.704159
7970 23:10:11.704479 [DramC_TX_OE_Calibration] TA2
7971 23:10:11.706105 Original DQ_B0 (3 6) =30, OEN = 27
7972 23:10:11.709918 Original DQ_B1 (3 6) =30, OEN = 27
7973 23:10:11.713040 24, 0x0, End_B0=24 End_B1=24
7974 23:10:11.716492 25, 0x0, End_B0=25 End_B1=25
7975 23:10:11.719312 26, 0x0, End_B0=26 End_B1=26
7976 23:10:11.722466 27, 0x0, End_B0=27 End_B1=27
7977 23:10:11.723091 28, 0x0, End_B0=28 End_B1=28
7978 23:10:11.726644 29, 0x0, End_B0=29 End_B1=29
7979 23:10:11.729251 30, 0x0, End_B0=30 End_B1=30
7980 23:10:11.732623 31, 0x5151, End_B0=30 End_B1=30
7981 23:10:11.736171 Byte0 end_step=30 best_step=27
7982 23:10:11.736701 Byte1 end_step=30 best_step=27
7983 23:10:11.739246 Byte0 TX OE(2T, 0.5T) = (3, 3)
7984 23:10:11.742461 Byte1 TX OE(2T, 0.5T) = (3, 3)
7985 23:10:11.743013
7986 23:10:11.743384
7987 23:10:11.752785 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
7988 23:10:11.753397 CH0 RK1: MR19=303, MR18=1E1E
7989 23:10:11.758880 CH0_RK1: MR19=0x303, MR18=0x1E1E, DQSOSC=394, MR23=63, INC=23, DEC=15
7990 23:10:11.762682 [RxdqsGatingPostProcess] freq 1600
7991 23:10:11.769012 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7992 23:10:11.771913 Pre-setting of DQS Precalculation
7993 23:10:11.775651 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7994 23:10:11.776112 ==
7995 23:10:11.778803 Dram Type= 6, Freq= 0, CH_1, rank 0
7996 23:10:11.785378 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7997 23:10:11.786022 ==
7998 23:10:11.788525 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7999 23:10:11.795825 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8000 23:10:11.798663 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8001 23:10:11.805714 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8002 23:10:11.812363 [CA 0] Center 41 (11~71) winsize 61
8003 23:10:11.815750 [CA 1] Center 40 (10~71) winsize 62
8004 23:10:11.818773 [CA 2] Center 36 (6~66) winsize 61
8005 23:10:11.822142 [CA 3] Center 35 (6~65) winsize 60
8006 23:10:11.825279 [CA 4] Center 33 (4~63) winsize 60
8007 23:10:11.829120 [CA 5] Center 33 (4~63) winsize 60
8008 23:10:11.829667
8009 23:10:11.832331 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8010 23:10:11.832874
8011 23:10:11.835675 [CATrainingPosCal] consider 1 rank data
8012 23:10:11.838963 u2DelayCellTimex100 = 275/100 ps
8013 23:10:11.842217 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8014 23:10:11.848844 CA1 delay=40 (10~71),Diff = 7 PI (24 cell)
8015 23:10:11.852129 CA2 delay=36 (6~66),Diff = 3 PI (10 cell)
8016 23:10:11.855380 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8017 23:10:11.858596 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8018 23:10:11.861993 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8019 23:10:11.862556
8020 23:10:11.865183 CA PerBit enable=1, Macro0, CA PI delay=33
8021 23:10:11.865729
8022 23:10:11.868669 [CBTSetCACLKResult] CA Dly = 33
8023 23:10:11.871788 CS Dly: 9 (0~40)
8024 23:10:11.875202 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8025 23:10:11.878598 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8026 23:10:11.879159 ==
8027 23:10:11.881697 Dram Type= 6, Freq= 0, CH_1, rank 1
8028 23:10:11.885057 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8029 23:10:11.888315 ==
8030 23:10:11.891703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8031 23:10:11.895139 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8032 23:10:11.901475 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8033 23:10:11.908571 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8034 23:10:11.914566 [CA 0] Center 41 (11~71) winsize 61
8035 23:10:11.918457 [CA 1] Center 41 (11~71) winsize 61
8036 23:10:11.921283 [CA 2] Center 36 (7~66) winsize 60
8037 23:10:11.924445 [CA 3] Center 36 (7~65) winsize 59
8038 23:10:11.928306 [CA 4] Center 34 (5~64) winsize 60
8039 23:10:11.931482 [CA 5] Center 34 (5~64) winsize 60
8040 23:10:11.932052
8041 23:10:11.934784 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8042 23:10:11.935349
8043 23:10:11.937702 [CATrainingPosCal] consider 2 rank data
8044 23:10:11.941549 u2DelayCellTimex100 = 275/100 ps
8045 23:10:11.948113 CA0 delay=41 (11~71),Diff = 7 PI (24 cell)
8046 23:10:11.951267 CA1 delay=41 (11~71),Diff = 7 PI (24 cell)
8047 23:10:11.954454 CA2 delay=36 (7~66),Diff = 2 PI (7 cell)
8048 23:10:11.957634 CA3 delay=36 (7~65),Diff = 2 PI (7 cell)
8049 23:10:11.960827 CA4 delay=34 (5~63),Diff = 0 PI (0 cell)
8050 23:10:11.964951 CA5 delay=34 (5~63),Diff = 0 PI (0 cell)
8051 23:10:11.965506
8052 23:10:11.967819 CA PerBit enable=1, Macro0, CA PI delay=34
8053 23:10:11.968380
8054 23:10:11.971085 [CBTSetCACLKResult] CA Dly = 34
8055 23:10:11.974535 CS Dly: 9 (0~41)
8056 23:10:11.977444 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8057 23:10:11.981174 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8058 23:10:11.981659
8059 23:10:11.984103 ----->DramcWriteLeveling(PI) begin...
8060 23:10:11.984581 ==
8061 23:10:11.987419 Dram Type= 6, Freq= 0, CH_1, rank 0
8062 23:10:11.994275 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8063 23:10:11.994834 ==
8064 23:10:11.997435 Write leveling (Byte 0): 23 => 23
8065 23:10:11.997890 Write leveling (Byte 1): 23 => 23
8066 23:10:12.000692 DramcWriteLeveling(PI) end<-----
8067 23:10:12.001200
8068 23:10:12.004270 ==
8069 23:10:12.007369 Dram Type= 6, Freq= 0, CH_1, rank 0
8070 23:10:12.010807 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8071 23:10:12.011428 ==
8072 23:10:12.013952 [Gating] SW mode calibration
8073 23:10:12.020752 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8074 23:10:12.023803 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8075 23:10:12.030603 0 12 0 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
8076 23:10:12.033686 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8077 23:10:12.036991 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8078 23:10:12.043678 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8079 23:10:12.046555 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8080 23:10:12.049780 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8081 23:10:12.056431 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8082 23:10:12.059920 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8083 23:10:12.063342 0 13 0 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
8084 23:10:12.069442 0 13 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8085 23:10:12.073012 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8086 23:10:12.076755 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8087 23:10:12.082733 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8088 23:10:12.086125 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8089 23:10:12.090194 0 13 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8090 23:10:12.096238 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8091 23:10:12.099757 0 14 0 | B1->B0 | 3030 4646 | 1 0 | (0 0) (0 0)
8092 23:10:12.102761 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8093 23:10:12.110094 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8094 23:10:12.112875 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8095 23:10:12.116308 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8096 23:10:12.122463 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8097 23:10:12.125725 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8098 23:10:12.129114 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8099 23:10:12.135751 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8100 23:10:12.139030 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8101 23:10:12.142191 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 23:10:12.148963 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 23:10:12.152065 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 23:10:12.155579 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 23:10:12.162010 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 23:10:12.165554 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 23:10:12.168954 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 23:10:12.175228 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 23:10:12.178488 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 23:10:12.182075 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 23:10:12.188496 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 23:10:12.191589 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 23:10:12.195080 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8114 23:10:12.201730 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8115 23:10:12.205364 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8116 23:10:12.208519 Total UI for P1: 0, mck2ui 16
8117 23:10:12.211721 best dqsien dly found for B0: ( 1, 0, 26)
8118 23:10:12.215098 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8119 23:10:12.221705 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8120 23:10:12.224960 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8121 23:10:12.228139 Total UI for P1: 0, mck2ui 16
8122 23:10:12.231383 best dqsien dly found for B1: ( 1, 1, 4)
8123 23:10:12.234978 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8124 23:10:12.237840 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
8125 23:10:12.238313
8126 23:10:12.241345 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8127 23:10:12.244632 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
8128 23:10:12.248044 [Gating] SW calibration Done
8129 23:10:12.248576 ==
8130 23:10:12.252002 Dram Type= 6, Freq= 0, CH_1, rank 0
8131 23:10:12.255103 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8132 23:10:12.257804 ==
8133 23:10:12.258446 RX Vref Scan: 0
8134 23:10:12.258827
8135 23:10:12.261270 RX Vref 0 -> 0, step: 1
8136 23:10:12.261727
8137 23:10:12.262085 RX Delay 0 -> 252, step: 8
8138 23:10:12.268246 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8139 23:10:12.271138 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8140 23:10:12.274518 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8141 23:10:12.277457 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8142 23:10:12.281074 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8143 23:10:12.287510 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8144 23:10:12.291180 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8145 23:10:12.294255 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8146 23:10:12.297313 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8147 23:10:12.303992 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8148 23:10:12.307425 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8149 23:10:12.310797 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8150 23:10:12.314291 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8151 23:10:12.317227 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8152 23:10:12.323970 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8153 23:10:12.327537 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8154 23:10:12.328073 ==
8155 23:10:12.330816 Dram Type= 6, Freq= 0, CH_1, rank 0
8156 23:10:12.333761 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8157 23:10:12.334226 ==
8158 23:10:12.337336 DQS Delay:
8159 23:10:12.337794 DQS0 = 0, DQS1 = 0
8160 23:10:12.338155 DQM Delay:
8161 23:10:12.340406 DQM0 = 130, DQM1 = 125
8162 23:10:12.340885 DQ Delay:
8163 23:10:12.343782 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8164 23:10:12.346932 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8165 23:10:12.353634 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8166 23:10:12.356978 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8167 23:10:12.357435
8168 23:10:12.357793
8169 23:10:12.358126 ==
8170 23:10:12.360665 Dram Type= 6, Freq= 0, CH_1, rank 0
8171 23:10:12.363598 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8172 23:10:12.364129 ==
8173 23:10:12.364498
8174 23:10:12.364912
8175 23:10:12.366747 TX Vref Scan disable
8176 23:10:12.370031 == TX Byte 0 ==
8177 23:10:12.373482 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8178 23:10:12.376903 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8179 23:10:12.379996 == TX Byte 1 ==
8180 23:10:12.383555 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8181 23:10:12.386872 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8182 23:10:12.387428 ==
8183 23:10:12.390256 Dram Type= 6, Freq= 0, CH_1, rank 0
8184 23:10:12.393524 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8185 23:10:12.396441 ==
8186 23:10:12.407283
8187 23:10:12.410331 TX Vref early break, caculate TX vref
8188 23:10:12.413477 TX Vref=16, minBit 0, minWin=21, winSum=361
8189 23:10:12.416898 TX Vref=18, minBit 3, minWin=22, winSum=372
8190 23:10:12.420409 TX Vref=20, minBit 0, minWin=23, winSum=380
8191 23:10:12.423593 TX Vref=22, minBit 3, minWin=23, winSum=392
8192 23:10:12.427042 TX Vref=24, minBit 3, minWin=23, winSum=399
8193 23:10:12.433867 TX Vref=26, minBit 0, minWin=24, winSum=403
8194 23:10:12.436839 TX Vref=28, minBit 3, minWin=24, winSum=411
8195 23:10:12.440115 TX Vref=30, minBit 0, minWin=24, winSum=404
8196 23:10:12.443687 TX Vref=32, minBit 1, minWin=23, winSum=395
8197 23:10:12.446629 TX Vref=34, minBit 1, minWin=23, winSum=385
8198 23:10:12.453656 [TxChooseVref] Worse bit 3, Min win 24, Win sum 411, Final Vref 28
8199 23:10:12.454208
8200 23:10:12.456434 Final TX Range 0 Vref 28
8201 23:10:12.456964
8202 23:10:12.457414 ==
8203 23:10:12.459978 Dram Type= 6, Freq= 0, CH_1, rank 0
8204 23:10:12.463253 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8205 23:10:12.463893 ==
8206 23:10:12.464278
8207 23:10:12.464618
8208 23:10:12.466517 TX Vref Scan disable
8209 23:10:12.473570 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8210 23:10:12.474123 == TX Byte 0 ==
8211 23:10:12.476702 u2DelayCellOfst[0]=14 cells (4 PI)
8212 23:10:12.479948 u2DelayCellOfst[1]=10 cells (3 PI)
8213 23:10:12.483043 u2DelayCellOfst[2]=0 cells (0 PI)
8214 23:10:12.486354 u2DelayCellOfst[3]=7 cells (2 PI)
8215 23:10:12.489618 u2DelayCellOfst[4]=7 cells (2 PI)
8216 23:10:12.493081 u2DelayCellOfst[5]=14 cells (4 PI)
8217 23:10:12.496305 u2DelayCellOfst[6]=14 cells (4 PI)
8218 23:10:12.496814 u2DelayCellOfst[7]=7 cells (2 PI)
8219 23:10:12.503147 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8220 23:10:12.506480 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8221 23:10:12.509396 == TX Byte 1 ==
8222 23:10:12.509859 u2DelayCellOfst[8]=0 cells (0 PI)
8223 23:10:12.512925 u2DelayCellOfst[9]=7 cells (2 PI)
8224 23:10:12.516181 u2DelayCellOfst[10]=10 cells (3 PI)
8225 23:10:12.519746 u2DelayCellOfst[11]=3 cells (1 PI)
8226 23:10:12.522970 u2DelayCellOfst[12]=17 cells (5 PI)
8227 23:10:12.526533 u2DelayCellOfst[13]=21 cells (6 PI)
8228 23:10:12.529543 u2DelayCellOfst[14]=21 cells (6 PI)
8229 23:10:12.533120 u2DelayCellOfst[15]=21 cells (6 PI)
8230 23:10:12.536402 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8231 23:10:12.542845 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8232 23:10:12.543380 DramC Write-DBI on
8233 23:10:12.543748 ==
8234 23:10:12.546208 Dram Type= 6, Freq= 0, CH_1, rank 0
8235 23:10:12.549261 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8236 23:10:12.552952 ==
8237 23:10:12.553508
8238 23:10:12.553873
8239 23:10:12.554211 TX Vref Scan disable
8240 23:10:12.556161 == TX Byte 0 ==
8241 23:10:12.559869 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8242 23:10:12.562597 == TX Byte 1 ==
8243 23:10:12.566184 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8244 23:10:12.569665 DramC Write-DBI off
8245 23:10:12.570245
8246 23:10:12.570618 [DATLAT]
8247 23:10:12.570951 Freq=1600, CH1 RK0
8248 23:10:12.571275
8249 23:10:12.573126 DATLAT Default: 0xf
8250 23:10:12.573615 0, 0xFFFF, sum = 0
8251 23:10:12.576536 1, 0xFFFF, sum = 0
8252 23:10:12.577168 2, 0xFFFF, sum = 0
8253 23:10:12.579610 3, 0xFFFF, sum = 0
8254 23:10:12.582767 4, 0xFFFF, sum = 0
8255 23:10:12.583296 5, 0xFFFF, sum = 0
8256 23:10:12.585970 6, 0xFFFF, sum = 0
8257 23:10:12.586491 7, 0xFFFF, sum = 0
8258 23:10:12.589469 8, 0xFFFF, sum = 0
8259 23:10:12.589947 9, 0xFFFF, sum = 0
8260 23:10:12.593199 10, 0xFFFF, sum = 0
8261 23:10:12.593680 11, 0xFFFF, sum = 0
8262 23:10:12.595953 12, 0xF7F, sum = 0
8263 23:10:12.596432 13, 0x0, sum = 1
8264 23:10:12.599227 14, 0x0, sum = 2
8265 23:10:12.599848 15, 0x0, sum = 3
8266 23:10:12.602389 16, 0x0, sum = 4
8267 23:10:12.602866 best_step = 14
8268 23:10:12.603342
8269 23:10:12.603791 ==
8270 23:10:12.606097 Dram Type= 6, Freq= 0, CH_1, rank 0
8271 23:10:12.609404 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8272 23:10:12.612514 ==
8273 23:10:12.613040 RX Vref Scan: 1
8274 23:10:12.613516
8275 23:10:12.615811 Set Vref Range= 24 -> 127
8276 23:10:12.616281
8277 23:10:12.616801 RX Vref 24 -> 127, step: 1
8278 23:10:12.619125
8279 23:10:12.619593 RX Delay 3 -> 252, step: 4
8280 23:10:12.620072
8281 23:10:12.622832 Set Vref, RX VrefLevel [Byte0]: 24
8282 23:10:12.625557 [Byte1]: 24
8283 23:10:12.629622
8284 23:10:12.630177 Set Vref, RX VrefLevel [Byte0]: 25
8285 23:10:12.632550 [Byte1]: 25
8286 23:10:12.637236
8287 23:10:12.637705 Set Vref, RX VrefLevel [Byte0]: 26
8288 23:10:12.640814 [Byte1]: 26
8289 23:10:12.645010
8290 23:10:12.645552 Set Vref, RX VrefLevel [Byte0]: 27
8291 23:10:12.647824 [Byte1]: 27
8292 23:10:12.652747
8293 23:10:12.653226 Set Vref, RX VrefLevel [Byte0]: 28
8294 23:10:12.655606 [Byte1]: 28
8295 23:10:12.660433
8296 23:10:12.660880 Set Vref, RX VrefLevel [Byte0]: 29
8297 23:10:12.663345 [Byte1]: 29
8298 23:10:12.667720
8299 23:10:12.668239 Set Vref, RX VrefLevel [Byte0]: 30
8300 23:10:12.670804 [Byte1]: 30
8301 23:10:12.675571
8302 23:10:12.676130 Set Vref, RX VrefLevel [Byte0]: 31
8303 23:10:12.678546 [Byte1]: 31
8304 23:10:12.683019
8305 23:10:12.683542 Set Vref, RX VrefLevel [Byte0]: 32
8306 23:10:12.686493 [Byte1]: 32
8307 23:10:12.690513
8308 23:10:12.690934 Set Vref, RX VrefLevel [Byte0]: 33
8309 23:10:12.693748 [Byte1]: 33
8310 23:10:12.698226
8311 23:10:12.698637 Set Vref, RX VrefLevel [Byte0]: 34
8312 23:10:12.701386 [Byte1]: 34
8313 23:10:12.705902
8314 23:10:12.706433 Set Vref, RX VrefLevel [Byte0]: 35
8315 23:10:12.709134 [Byte1]: 35
8316 23:10:12.713518
8317 23:10:12.713968 Set Vref, RX VrefLevel [Byte0]: 36
8318 23:10:12.716816 [Byte1]: 36
8319 23:10:12.721686
8320 23:10:12.722228 Set Vref, RX VrefLevel [Byte0]: 37
8321 23:10:12.724389 [Byte1]: 37
8322 23:10:12.729151
8323 23:10:12.729701 Set Vref, RX VrefLevel [Byte0]: 38
8324 23:10:12.732234 [Byte1]: 38
8325 23:10:12.736390
8326 23:10:12.736877 Set Vref, RX VrefLevel [Byte0]: 39
8327 23:10:12.740013 [Byte1]: 39
8328 23:10:12.744419
8329 23:10:12.744998 Set Vref, RX VrefLevel [Byte0]: 40
8330 23:10:12.747406 [Byte1]: 40
8331 23:10:12.751962
8332 23:10:12.752481 Set Vref, RX VrefLevel [Byte0]: 41
8333 23:10:12.754900 [Byte1]: 41
8334 23:10:12.759562
8335 23:10:12.760017 Set Vref, RX VrefLevel [Byte0]: 42
8336 23:10:12.762769 [Byte1]: 42
8337 23:10:12.767318
8338 23:10:12.767858 Set Vref, RX VrefLevel [Byte0]: 43
8339 23:10:12.770654 [Byte1]: 43
8340 23:10:12.775174
8341 23:10:12.775768 Set Vref, RX VrefLevel [Byte0]: 44
8342 23:10:12.777971 [Byte1]: 44
8343 23:10:12.782418
8344 23:10:12.782865 Set Vref, RX VrefLevel [Byte0]: 45
8345 23:10:12.785569 [Byte1]: 45
8346 23:10:12.790044
8347 23:10:12.790496 Set Vref, RX VrefLevel [Byte0]: 46
8348 23:10:12.793190 [Byte1]: 46
8349 23:10:12.797687
8350 23:10:12.798138 Set Vref, RX VrefLevel [Byte0]: 47
8351 23:10:12.801218 [Byte1]: 47
8352 23:10:12.805898
8353 23:10:12.806447 Set Vref, RX VrefLevel [Byte0]: 48
8354 23:10:12.808801 [Byte1]: 48
8355 23:10:12.813231
8356 23:10:12.813684 Set Vref, RX VrefLevel [Byte0]: 49
8357 23:10:12.816339 [Byte1]: 49
8358 23:10:12.820604
8359 23:10:12.821196 Set Vref, RX VrefLevel [Byte0]: 50
8360 23:10:12.823795 [Byte1]: 50
8361 23:10:12.828513
8362 23:10:12.829024 Set Vref, RX VrefLevel [Byte0]: 51
8363 23:10:12.831453 [Byte1]: 51
8364 23:10:12.836221
8365 23:10:12.836677 Set Vref, RX VrefLevel [Byte0]: 52
8366 23:10:12.839447 [Byte1]: 52
8367 23:10:12.843676
8368 23:10:12.844080 Set Vref, RX VrefLevel [Byte0]: 53
8369 23:10:12.846797 [Byte1]: 53
8370 23:10:12.851693
8371 23:10:12.852261 Set Vref, RX VrefLevel [Byte0]: 54
8372 23:10:12.854635 [Byte1]: 54
8373 23:10:12.858946
8374 23:10:12.859483 Set Vref, RX VrefLevel [Byte0]: 55
8375 23:10:12.862164 [Byte1]: 55
8376 23:10:12.866686
8377 23:10:12.867197 Set Vref, RX VrefLevel [Byte0]: 56
8378 23:10:12.869963 [Byte1]: 56
8379 23:10:12.874922
8380 23:10:12.875484 Set Vref, RX VrefLevel [Byte0]: 57
8381 23:10:12.877294 [Byte1]: 57
8382 23:10:12.882111
8383 23:10:12.882612 Set Vref, RX VrefLevel [Byte0]: 58
8384 23:10:12.885370 [Byte1]: 58
8385 23:10:12.889413
8386 23:10:12.889824 Set Vref, RX VrefLevel [Byte0]: 59
8387 23:10:12.892808 [Byte1]: 59
8388 23:10:12.897627
8389 23:10:12.898035 Set Vref, RX VrefLevel [Byte0]: 60
8390 23:10:12.900748 [Byte1]: 60
8391 23:10:12.904905
8392 23:10:12.905473 Set Vref, RX VrefLevel [Byte0]: 61
8393 23:10:12.908116 [Byte1]: 61
8394 23:10:12.912381
8395 23:10:12.912832 Set Vref, RX VrefLevel [Byte0]: 62
8396 23:10:12.915990 [Byte1]: 62
8397 23:10:12.920091
8398 23:10:12.920506 Set Vref, RX VrefLevel [Byte0]: 63
8399 23:10:12.923328 [Byte1]: 63
8400 23:10:12.927688
8401 23:10:12.931361 Set Vref, RX VrefLevel [Byte0]: 64
8402 23:10:12.931940 [Byte1]: 64
8403 23:10:12.935633
8404 23:10:12.936194 Set Vref, RX VrefLevel [Byte0]: 65
8405 23:10:12.939205 [Byte1]: 65
8406 23:10:12.943325
8407 23:10:12.943865 Set Vref, RX VrefLevel [Byte0]: 66
8408 23:10:12.946508 [Byte1]: 66
8409 23:10:12.951210
8410 23:10:12.951830 Set Vref, RX VrefLevel [Byte0]: 67
8411 23:10:12.953964 [Byte1]: 67
8412 23:10:12.958891
8413 23:10:12.959345 Set Vref, RX VrefLevel [Byte0]: 68
8414 23:10:12.961776 [Byte1]: 68
8415 23:10:12.965925
8416 23:10:12.966381 Set Vref, RX VrefLevel [Byte0]: 69
8417 23:10:12.969724 [Byte1]: 69
8418 23:10:12.973839
8419 23:10:12.974295 Set Vref, RX VrefLevel [Byte0]: 70
8420 23:10:12.977228 [Byte1]: 70
8421 23:10:12.981239
8422 23:10:12.981826 Set Vref, RX VrefLevel [Byte0]: 71
8423 23:10:12.984611 [Byte1]: 71
8424 23:10:12.988915
8425 23:10:12.989369 Set Vref, RX VrefLevel [Byte0]: 72
8426 23:10:12.992402 [Byte1]: 72
8427 23:10:12.996541
8428 23:10:12.997071 Set Vref, RX VrefLevel [Byte0]: 73
8429 23:10:13.000108 [Byte1]: 73
8430 23:10:13.004646
8431 23:10:13.005166 Set Vref, RX VrefLevel [Byte0]: 74
8432 23:10:13.007898 [Byte1]: 74
8433 23:10:13.011764
8434 23:10:13.012236 Final RX Vref Byte 0 = 60 to rank0
8435 23:10:13.015231 Final RX Vref Byte 1 = 53 to rank0
8436 23:10:13.018616 Final RX Vref Byte 0 = 60 to rank1
8437 23:10:13.022194 Final RX Vref Byte 1 = 53 to rank1==
8438 23:10:13.025402 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 23:10:13.032380 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8440 23:10:13.032995 ==
8441 23:10:13.033484 DQS Delay:
8442 23:10:13.033937 DQS0 = 0, DQS1 = 0
8443 23:10:13.035553 DQM Delay:
8444 23:10:13.036026 DQM0 = 129, DQM1 = 123
8445 23:10:13.038644 DQ Delay:
8446 23:10:13.042040 DQ0 =134, DQ1 =122, DQ2 =118, DQ3 =126
8447 23:10:13.045087 DQ4 =130, DQ5 =138, DQ6 =138, DQ7 =126
8448 23:10:13.048513 DQ8 =104, DQ9 =114, DQ10 =124, DQ11 =112
8449 23:10:13.052082 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =132
8450 23:10:13.052658
8451 23:10:13.053191
8452 23:10:13.053642
8453 23:10:13.054999 [DramC_TX_OE_Calibration] TA2
8454 23:10:13.058389 Original DQ_B0 (3 6) =30, OEN = 27
8455 23:10:13.061775 Original DQ_B1 (3 6) =30, OEN = 27
8456 23:10:13.065086 24, 0x0, End_B0=24 End_B1=24
8457 23:10:13.065570 25, 0x0, End_B0=25 End_B1=25
8458 23:10:13.068544 26, 0x0, End_B0=26 End_B1=26
8459 23:10:13.071814 27, 0x0, End_B0=27 End_B1=27
8460 23:10:13.075445 28, 0x0, End_B0=28 End_B1=28
8461 23:10:13.077951 29, 0x0, End_B0=29 End_B1=29
8462 23:10:13.078435 30, 0x0, End_B0=30 End_B1=30
8463 23:10:13.081686 31, 0x4545, End_B0=30 End_B1=30
8464 23:10:13.084914 Byte0 end_step=30 best_step=27
8465 23:10:13.088086 Byte1 end_step=30 best_step=27
8466 23:10:13.091330 Byte0 TX OE(2T, 0.5T) = (3, 3)
8467 23:10:13.094639 Byte1 TX OE(2T, 0.5T) = (3, 3)
8468 23:10:13.095112
8469 23:10:13.095594
8470 23:10:13.101479 [DQSOSCAuto] RK0, (LSB)MR18= 0x2828, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8471 23:10:13.104563 CH1 RK0: MR19=303, MR18=2828
8472 23:10:13.111298 CH1_RK0: MR19=0x303, MR18=0x2828, DQSOSC=389, MR23=63, INC=24, DEC=16
8473 23:10:13.111870
8474 23:10:13.114282 ----->DramcWriteLeveling(PI) begin...
8475 23:10:13.114761 ==
8476 23:10:13.118105 Dram Type= 6, Freq= 0, CH_1, rank 1
8477 23:10:13.121120 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8478 23:10:13.121596 ==
8479 23:10:13.124581 Write leveling (Byte 0): 23 => 23
8480 23:10:13.127996 Write leveling (Byte 1): 20 => 20
8481 23:10:13.131517 DramcWriteLeveling(PI) end<-----
8482 23:10:13.132081
8483 23:10:13.132448 ==
8484 23:10:13.134472 Dram Type= 6, Freq= 0, CH_1, rank 1
8485 23:10:13.138049 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8486 23:10:13.138616 ==
8487 23:10:13.141037 [Gating] SW mode calibration
8488 23:10:13.147893 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8489 23:10:13.154236 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8490 23:10:13.157380 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8491 23:10:13.164541 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8492 23:10:13.167310 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8493 23:10:13.171165 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8494 23:10:13.177364 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8495 23:10:13.180333 0 12 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8496 23:10:13.183735 0 12 24 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
8497 23:10:13.190303 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8498 23:10:13.193775 0 13 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
8499 23:10:13.197006 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8500 23:10:13.203546 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8501 23:10:13.207138 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8502 23:10:13.210400 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8503 23:10:13.217026 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8504 23:10:13.220670 0 13 24 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
8505 23:10:13.224067 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8506 23:10:13.230106 0 14 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8507 23:10:13.233337 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8508 23:10:13.236949 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8509 23:10:13.243966 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8510 23:10:13.246614 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8511 23:10:13.249974 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8512 23:10:13.256484 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8513 23:10:13.259750 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8514 23:10:13.263136 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8515 23:10:13.270123 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8516 23:10:13.273799 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8517 23:10:13.276820 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8518 23:10:13.282971 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8519 23:10:13.286347 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8520 23:10:13.289731 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8521 23:10:13.296143 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8522 23:10:13.299499 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8523 23:10:13.302957 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8524 23:10:13.306184 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8525 23:10:13.313090 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8526 23:10:13.316035 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8527 23:10:13.319513 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8528 23:10:13.326064 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8529 23:10:13.329165 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8530 23:10:13.332687 Total UI for P1: 0, mck2ui 16
8531 23:10:13.336087 best dqsien dly found for B0: ( 1, 0, 24)
8532 23:10:13.339137 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8533 23:10:13.345995 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8534 23:10:13.349024 Total UI for P1: 0, mck2ui 16
8535 23:10:13.352465 best dqsien dly found for B1: ( 1, 0, 30)
8536 23:10:13.355728 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8537 23:10:13.359174 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8538 23:10:13.359631
8539 23:10:13.362217 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8540 23:10:13.365646 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8541 23:10:13.368781 [Gating] SW calibration Done
8542 23:10:13.369240 ==
8543 23:10:13.372510 Dram Type= 6, Freq= 0, CH_1, rank 1
8544 23:10:13.375552 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8545 23:10:13.376014 ==
8546 23:10:13.379146 RX Vref Scan: 0
8547 23:10:13.379680
8548 23:10:13.382488 RX Vref 0 -> 0, step: 1
8549 23:10:13.382943
8550 23:10:13.383299 RX Delay 0 -> 252, step: 8
8551 23:10:13.388788 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8552 23:10:13.392297 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8553 23:10:13.395880 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8554 23:10:13.398782 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8555 23:10:13.402142 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8556 23:10:13.409066 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8557 23:10:13.412167 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8558 23:10:13.415693 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8559 23:10:13.418443 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8560 23:10:13.421952 iDelay=200, Bit 9, Center 111 (48 ~ 175) 128
8561 23:10:13.428602 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8562 23:10:13.432553 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8563 23:10:13.435729 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8564 23:10:13.438963 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8565 23:10:13.441741 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8566 23:10:13.448623 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8567 23:10:13.449240 ==
8568 23:10:13.452170 Dram Type= 6, Freq= 0, CH_1, rank 1
8569 23:10:13.455363 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8570 23:10:13.455927 ==
8571 23:10:13.456409 DQS Delay:
8572 23:10:13.458375 DQS0 = 0, DQS1 = 0
8573 23:10:13.459075 DQM Delay:
8574 23:10:13.461579 DQM0 = 131, DQM1 = 124
8575 23:10:13.462039 DQ Delay:
8576 23:10:13.465118 DQ0 =131, DQ1 =127, DQ2 =119, DQ3 =131
8577 23:10:13.468835 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8578 23:10:13.472008 DQ8 =107, DQ9 =111, DQ10 =127, DQ11 =115
8579 23:10:13.475065 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8580 23:10:13.478740
8581 23:10:13.479291
8582 23:10:13.479652 ==
8583 23:10:13.481337 Dram Type= 6, Freq= 0, CH_1, rank 1
8584 23:10:13.484827 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8585 23:10:13.485406 ==
8586 23:10:13.485785
8587 23:10:13.486121
8588 23:10:13.488359 TX Vref Scan disable
8589 23:10:13.488871 == TX Byte 0 ==
8590 23:10:13.494648 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8591 23:10:13.498035 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8592 23:10:13.498570 == TX Byte 1 ==
8593 23:10:13.504614 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8594 23:10:13.508679 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8595 23:10:13.509273 ==
8596 23:10:13.511447 Dram Type= 6, Freq= 0, CH_1, rank 1
8597 23:10:13.514590 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8598 23:10:13.515057 ==
8599 23:10:13.528270
8600 23:10:13.531954 TX Vref early break, caculate TX vref
8601 23:10:13.534989 TX Vref=16, minBit 0, minWin=22, winSum=379
8602 23:10:13.538286 TX Vref=18, minBit 0, minWin=23, winSum=389
8603 23:10:13.541754 TX Vref=20, minBit 0, minWin=22, winSum=394
8604 23:10:13.545186 TX Vref=22, minBit 0, minWin=23, winSum=404
8605 23:10:13.548498 TX Vref=24, minBit 0, minWin=23, winSum=413
8606 23:10:13.555129 TX Vref=26, minBit 0, minWin=24, winSum=420
8607 23:10:13.558168 TX Vref=28, minBit 0, minWin=24, winSum=419
8608 23:10:13.561878 TX Vref=30, minBit 0, minWin=23, winSum=411
8609 23:10:13.564743 TX Vref=32, minBit 0, minWin=24, winSum=406
8610 23:10:13.568124 TX Vref=34, minBit 0, minWin=21, winSum=397
8611 23:10:13.575174 [TxChooseVref] Worse bit 0, Min win 24, Win sum 420, Final Vref 26
8612 23:10:13.575718
8613 23:10:13.577871 Final TX Range 0 Vref 26
8614 23:10:13.578352
8615 23:10:13.578828 ==
8616 23:10:13.581604 Dram Type= 6, Freq= 0, CH_1, rank 1
8617 23:10:13.584811 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8618 23:10:13.585389 ==
8619 23:10:13.585875
8620 23:10:13.586219
8621 23:10:13.588175 TX Vref Scan disable
8622 23:10:13.594552 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8623 23:10:13.595255 == TX Byte 0 ==
8624 23:10:13.597686 u2DelayCellOfst[0]=17 cells (5 PI)
8625 23:10:13.601467 u2DelayCellOfst[1]=7 cells (2 PI)
8626 23:10:13.604462 u2DelayCellOfst[2]=0 cells (0 PI)
8627 23:10:13.608263 u2DelayCellOfst[3]=7 cells (2 PI)
8628 23:10:13.611398 u2DelayCellOfst[4]=7 cells (2 PI)
8629 23:10:13.614805 u2DelayCellOfst[5]=14 cells (4 PI)
8630 23:10:13.617804 u2DelayCellOfst[6]=14 cells (4 PI)
8631 23:10:13.618255 u2DelayCellOfst[7]=3 cells (1 PI)
8632 23:10:13.624419 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8633 23:10:13.627440 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8634 23:10:13.627883 == TX Byte 1 ==
8635 23:10:13.631135 u2DelayCellOfst[8]=0 cells (0 PI)
8636 23:10:13.634219 u2DelayCellOfst[9]=7 cells (2 PI)
8637 23:10:13.638139 u2DelayCellOfst[10]=10 cells (3 PI)
8638 23:10:13.641116 u2DelayCellOfst[11]=3 cells (1 PI)
8639 23:10:13.644530 u2DelayCellOfst[12]=14 cells (4 PI)
8640 23:10:13.647613 u2DelayCellOfst[13]=17 cells (5 PI)
8641 23:10:13.650981 u2DelayCellOfst[14]=17 cells (5 PI)
8642 23:10:13.654285 u2DelayCellOfst[15]=14 cells (4 PI)
8643 23:10:13.657404 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8644 23:10:13.664058 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8645 23:10:13.664639 DramC Write-DBI on
8646 23:10:13.665166 ==
8647 23:10:13.667337 Dram Type= 6, Freq= 0, CH_1, rank 1
8648 23:10:13.670919 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8649 23:10:13.674072 ==
8650 23:10:13.674529
8651 23:10:13.674889
8652 23:10:13.675219 TX Vref Scan disable
8653 23:10:13.677332 == TX Byte 0 ==
8654 23:10:13.680648 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8655 23:10:13.684105 == TX Byte 1 ==
8656 23:10:13.687348 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8657 23:10:13.690327 DramC Write-DBI off
8658 23:10:13.690808
8659 23:10:13.691295 [DATLAT]
8660 23:10:13.691750 Freq=1600, CH1 RK1
8661 23:10:13.692195
8662 23:10:13.693908 DATLAT Default: 0xe
8663 23:10:13.697235 0, 0xFFFF, sum = 0
8664 23:10:13.697867 1, 0xFFFF, sum = 0
8665 23:10:13.700299 2, 0xFFFF, sum = 0
8666 23:10:13.700972 3, 0xFFFF, sum = 0
8667 23:10:13.703766 4, 0xFFFF, sum = 0
8668 23:10:13.704227 5, 0xFFFF, sum = 0
8669 23:10:13.707411 6, 0xFFFF, sum = 0
8670 23:10:13.707966 7, 0xFFFF, sum = 0
8671 23:10:13.710564 8, 0xFFFF, sum = 0
8672 23:10:13.711118 9, 0xFFFF, sum = 0
8673 23:10:13.713409 10, 0xFFFF, sum = 0
8674 23:10:13.713872 11, 0xFFFF, sum = 0
8675 23:10:13.717483 12, 0xFFF, sum = 0
8676 23:10:13.717947 13, 0x0, sum = 1
8677 23:10:13.720392 14, 0x0, sum = 2
8678 23:10:13.721000 15, 0x0, sum = 3
8679 23:10:13.724083 16, 0x0, sum = 4
8680 23:10:13.724642 best_step = 14
8681 23:10:13.725041
8682 23:10:13.725376 ==
8683 23:10:13.727253 Dram Type= 6, Freq= 0, CH_1, rank 1
8684 23:10:13.730541 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8685 23:10:13.733436 ==
8686 23:10:13.733895 RX Vref Scan: 0
8687 23:10:13.734252
8688 23:10:13.736838 RX Vref 0 -> 0, step: 1
8689 23:10:13.737316
8690 23:10:13.740299 RX Delay 3 -> 252, step: 4
8691 23:10:13.743529 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8692 23:10:13.746865 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8693 23:10:13.750088 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8694 23:10:13.757111 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8695 23:10:13.760048 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8696 23:10:13.763187 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8697 23:10:13.766728 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8698 23:10:13.769953 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8699 23:10:13.776492 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8700 23:10:13.780066 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8701 23:10:13.783116 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8702 23:10:13.786593 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8703 23:10:13.789868 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8704 23:10:13.796639 iDelay=195, Bit 13, Center 130 (79 ~ 182) 104
8705 23:10:13.799661 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8706 23:10:13.802884 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8707 23:10:13.803338 ==
8708 23:10:13.806258 Dram Type= 6, Freq= 0, CH_1, rank 1
8709 23:10:13.810024 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8710 23:10:13.813100 ==
8711 23:10:13.813582 DQS Delay:
8712 23:10:13.814148 DQS0 = 0, DQS1 = 0
8713 23:10:13.816446 DQM Delay:
8714 23:10:13.817084 DQM0 = 127, DQM1 = 122
8715 23:10:13.819446 DQ Delay:
8716 23:10:13.823094 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124
8717 23:10:13.826085 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8718 23:10:13.829515 DQ8 =104, DQ9 =110, DQ10 =124, DQ11 =114
8719 23:10:13.832555 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =132
8720 23:10:13.833123
8721 23:10:13.833699
8722 23:10:13.834067
8723 23:10:13.836152 [DramC_TX_OE_Calibration] TA2
8724 23:10:13.839683 Original DQ_B0 (3 6) =30, OEN = 27
8725 23:10:13.843076 Original DQ_B1 (3 6) =30, OEN = 27
8726 23:10:13.843787 24, 0x0, End_B0=24 End_B1=24
8727 23:10:13.846166 25, 0x0, End_B0=25 End_B1=25
8728 23:10:13.849625 26, 0x0, End_B0=26 End_B1=26
8729 23:10:13.852826 27, 0x0, End_B0=27 End_B1=27
8730 23:10:13.855850 28, 0x0, End_B0=28 End_B1=28
8731 23:10:13.856312 29, 0x0, End_B0=29 End_B1=29
8732 23:10:13.859178 30, 0x0, End_B0=30 End_B1=30
8733 23:10:13.862504 31, 0x4141, End_B0=30 End_B1=30
8734 23:10:13.865573 Byte0 end_step=30 best_step=27
8735 23:10:13.869318 Byte1 end_step=30 best_step=27
8736 23:10:13.872590 Byte0 TX OE(2T, 0.5T) = (3, 3)
8737 23:10:13.873057 Byte1 TX OE(2T, 0.5T) = (3, 3)
8738 23:10:13.873384
8739 23:10:13.876226
8740 23:10:13.882210 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8741 23:10:13.885371 CH1 RK1: MR19=303, MR18=1C1C
8742 23:10:13.892134 CH1_RK1: MR19=0x303, MR18=0x1C1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8743 23:10:13.895648 [RxdqsGatingPostProcess] freq 1600
8744 23:10:13.898727 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8745 23:10:13.901829 Pre-setting of DQS Precalculation
8746 23:10:13.908805 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8747 23:10:13.915602 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8748 23:10:13.922005 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8749 23:10:13.922523
8750 23:10:13.922849
8751 23:10:13.926204 [Calibration Summary] 3200 Mbps
8752 23:10:13.926736 CH 0, Rank 0
8753 23:10:13.928447 SW Impedance : PASS
8754 23:10:13.931914 DUTY Scan : NO K
8755 23:10:13.932320 ZQ Calibration : PASS
8756 23:10:13.935485 Jitter Meter : NO K
8757 23:10:13.938684 CBT Training : PASS
8758 23:10:13.939194 Write leveling : PASS
8759 23:10:13.941672 RX DQS gating : PASS
8760 23:10:13.945026 RX DQ/DQS(RDDQC) : PASS
8761 23:10:13.945438 TX DQ/DQS : PASS
8762 23:10:13.948839 RX DATLAT : PASS
8763 23:10:13.952078 RX DQ/DQS(Engine): PASS
8764 23:10:13.952597 TX OE : PASS
8765 23:10:13.952970 All Pass.
8766 23:10:13.955378
8767 23:10:13.955901 CH 0, Rank 1
8768 23:10:13.958249 SW Impedance : PASS
8769 23:10:13.958664 DUTY Scan : NO K
8770 23:10:13.961725 ZQ Calibration : PASS
8771 23:10:13.964963 Jitter Meter : NO K
8772 23:10:13.965372 CBT Training : PASS
8773 23:10:13.968398 Write leveling : PASS
8774 23:10:13.968968 RX DQS gating : PASS
8775 23:10:13.972091 RX DQ/DQS(RDDQC) : PASS
8776 23:10:13.974686 TX DQ/DQS : PASS
8777 23:10:13.975102 RX DATLAT : PASS
8778 23:10:13.978041 RX DQ/DQS(Engine): PASS
8779 23:10:13.981492 TX OE : PASS
8780 23:10:13.981901 All Pass.
8781 23:10:13.982224
8782 23:10:13.982521 CH 1, Rank 0
8783 23:10:13.984449 SW Impedance : PASS
8784 23:10:13.987788 DUTY Scan : NO K
8785 23:10:13.988201 ZQ Calibration : PASS
8786 23:10:13.991337 Jitter Meter : NO K
8787 23:10:13.994644 CBT Training : PASS
8788 23:10:13.995102 Write leveling : PASS
8789 23:10:13.997794 RX DQS gating : PASS
8790 23:10:14.001256 RX DQ/DQS(RDDQC) : PASS
8791 23:10:14.001669 TX DQ/DQS : PASS
8792 23:10:14.004776 RX DATLAT : PASS
8793 23:10:14.008166 RX DQ/DQS(Engine): PASS
8794 23:10:14.008774 TX OE : PASS
8795 23:10:14.011245 All Pass.
8796 23:10:14.011761
8797 23:10:14.012091 CH 1, Rank 1
8798 23:10:14.014259 SW Impedance : PASS
8799 23:10:14.014672 DUTY Scan : NO K
8800 23:10:14.017527 ZQ Calibration : PASS
8801 23:10:14.021097 Jitter Meter : NO K
8802 23:10:14.021508 CBT Training : PASS
8803 23:10:14.024763 Write leveling : PASS
8804 23:10:14.027442 RX DQS gating : PASS
8805 23:10:14.027906 RX DQ/DQS(RDDQC) : PASS
8806 23:10:14.031111 TX DQ/DQS : PASS
8807 23:10:14.031630 RX DATLAT : PASS
8808 23:10:14.034230 RX DQ/DQS(Engine): PASS
8809 23:10:14.037334 TX OE : PASS
8810 23:10:14.037749 All Pass.
8811 23:10:14.038071
8812 23:10:14.041335 DramC Write-DBI on
8813 23:10:14.041850 PER_BANK_REFRESH: Hybrid Mode
8814 23:10:14.044154 TX_TRACKING: ON
8815 23:10:14.054093 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8816 23:10:14.060818 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8817 23:10:14.067201 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8818 23:10:14.071019 [FAST_K] Save calibration result to emmc
8819 23:10:14.074230 sync common calibartion params.
8820 23:10:14.077998 sync cbt_mode0:0, 1:0
8821 23:10:14.078515 dram_init: ddr_geometry: 0
8822 23:10:14.081187 dram_init: ddr_geometry: 0
8823 23:10:14.084123 dram_init: ddr_geometry: 0
8824 23:10:14.086929 0:dram_rank_size:80000000
8825 23:10:14.087417 1:dram_rank_size:80000000
8826 23:10:14.093908 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8827 23:10:14.097064 DFS_SHUFFLE_HW_MODE: ON
8828 23:10:14.100275 dramc_set_vcore_voltage set vcore to 725000
8829 23:10:14.100687 Read voltage for 1600, 0
8830 23:10:14.103926 Vio18 = 0
8831 23:10:14.104335 Vcore = 725000
8832 23:10:14.104653 Vdram = 0
8833 23:10:14.107527 Vddq = 0
8834 23:10:14.107937 Vmddr = 0
8835 23:10:14.110428 switch to 3200 Mbps bootup
8836 23:10:14.110843 [DramcRunTimeConfig]
8837 23:10:14.111167 PHYPLL
8838 23:10:14.113947 DPM_CONTROL_AFTERK: ON
8839 23:10:14.117005 PER_BANK_REFRESH: ON
8840 23:10:14.120744 REFRESH_OVERHEAD_REDUCTION: ON
8841 23:10:14.121157 CMD_PICG_NEW_MODE: OFF
8842 23:10:14.123720 XRTWTW_NEW_MODE: ON
8843 23:10:14.124141 XRTRTR_NEW_MODE: ON
8844 23:10:14.127138 TX_TRACKING: ON
8845 23:10:14.127547 RDSEL_TRACKING: OFF
8846 23:10:14.130746 DQS Precalculation for DVFS: ON
8847 23:10:14.134111 RX_TRACKING: OFF
8848 23:10:14.134620 HW_GATING DBG: ON
8849 23:10:14.137205 ZQCS_ENABLE_LP4: ON
8850 23:10:14.137613 RX_PICG_NEW_MODE: ON
8851 23:10:14.140448 TX_PICG_NEW_MODE: ON
8852 23:10:14.140994 ENABLE_RX_DCM_DPHY: ON
8853 23:10:14.143532 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8854 23:10:14.146776 DUMMY_READ_FOR_TRACKING: OFF
8855 23:10:14.150127 !!! SPM_CONTROL_AFTERK: OFF
8856 23:10:14.153448 !!! SPM could not control APHY
8857 23:10:14.153860 IMPEDANCE_TRACKING: ON
8858 23:10:14.156866 TEMP_SENSOR: ON
8859 23:10:14.157284 HW_SAVE_FOR_SR: OFF
8860 23:10:14.159976 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8861 23:10:14.163226 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8862 23:10:14.166790 Read ODT Tracking: ON
8863 23:10:14.170332 Refresh Rate DeBounce: ON
8864 23:10:14.170842 DFS_NO_QUEUE_FLUSH: ON
8865 23:10:14.173343 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8866 23:10:14.177022 ENABLE_DFS_RUNTIME_MRW: OFF
8867 23:10:14.179867 DDR_RESERVE_NEW_MODE: ON
8868 23:10:14.180347 MR_CBT_SWITCH_FREQ: ON
8869 23:10:14.183118 =========================
8870 23:10:14.201554 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8871 23:10:14.205039 dram_init: ddr_geometry: 0
8872 23:10:14.223347 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8873 23:10:14.226345 dram_init: dram init end (result: 0)
8874 23:10:14.233184 DRAM-K: Full calibration passed in 23456 msecs
8875 23:10:14.236532 MRC: failed to locate region type 0.
8876 23:10:14.237060 DRAM rank0 size:0x80000000,
8877 23:10:14.239710 DRAM rank1 size=0x80000000
8878 23:10:14.250044 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8879 23:10:14.256589 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8880 23:10:14.263119 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8881 23:10:14.269501 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8882 23:10:14.272961 DRAM rank0 size:0x80000000,
8883 23:10:14.276091 DRAM rank1 size=0x80000000
8884 23:10:14.276504 CBMEM:
8885 23:10:14.279661 IMD: root @ 0xfffff000 254 entries.
8886 23:10:14.282874 IMD: root @ 0xffffec00 62 entries.
8887 23:10:14.286214 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8888 23:10:14.289493 WARNING: RO_VPD is uninitialized or empty.
8889 23:10:14.296082 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8890 23:10:14.302611 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8891 23:10:14.315478 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8892 23:10:14.327168 BS: romstage times (exec / console): total (unknown) / 22990 ms
8893 23:10:14.327648
8894 23:10:14.327973
8895 23:10:14.336688 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8896 23:10:14.340011 ARM64: Exception handlers installed.
8897 23:10:14.343364 ARM64: Testing exception
8898 23:10:14.346618 ARM64: Done test exception
8899 23:10:14.347032 Enumerating buses...
8900 23:10:14.350835 Show all devs... Before device enumeration.
8901 23:10:14.353358 Root Device: enabled 1
8902 23:10:14.356938 CPU_CLUSTER: 0: enabled 1
8903 23:10:14.357455 CPU: 00: enabled 1
8904 23:10:14.360165 Compare with tree...
8905 23:10:14.360657 Root Device: enabled 1
8906 23:10:14.363355 CPU_CLUSTER: 0: enabled 1
8907 23:10:14.366473 CPU: 00: enabled 1
8908 23:10:14.366885 Root Device scanning...
8909 23:10:14.369922 scan_static_bus for Root Device
8910 23:10:14.373577 CPU_CLUSTER: 0 enabled
8911 23:10:14.377015 scan_static_bus for Root Device done
8912 23:10:14.379681 scan_bus: bus Root Device finished in 8 msecs
8913 23:10:14.380099 done
8914 23:10:14.386437 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8915 23:10:14.389980 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8916 23:10:14.396599 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8917 23:10:14.399902 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8918 23:10:14.403147 Allocating resources...
8919 23:10:14.406361 Reading resources...
8920 23:10:14.409616 Root Device read_resources bus 0 link: 0
8921 23:10:14.410101 DRAM rank0 size:0x80000000,
8922 23:10:14.413402 DRAM rank1 size=0x80000000
8923 23:10:14.416281 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8924 23:10:14.420041 CPU: 00 missing read_resources
8925 23:10:14.423136 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8926 23:10:14.429689 Root Device read_resources bus 0 link: 0 done
8927 23:10:14.430108 Done reading resources.
8928 23:10:14.436099 Show resources in subtree (Root Device)...After reading.
8929 23:10:14.439552 Root Device child on link 0 CPU_CLUSTER: 0
8930 23:10:14.442719 CPU_CLUSTER: 0 child on link 0 CPU: 00
8931 23:10:14.453139 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8932 23:10:14.453659 CPU: 00
8933 23:10:14.456171 Root Device assign_resources, bus 0 link: 0
8934 23:10:14.459321 CPU_CLUSTER: 0 missing set_resources
8935 23:10:14.466095 Root Device assign_resources, bus 0 link: 0 done
8936 23:10:14.466509 Done setting resources.
8937 23:10:14.472585 Show resources in subtree (Root Device)...After assigning values.
8938 23:10:14.475817 Root Device child on link 0 CPU_CLUSTER: 0
8939 23:10:14.479088 CPU_CLUSTER: 0 child on link 0 CPU: 00
8940 23:10:14.489081 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8941 23:10:14.489583 CPU: 00
8942 23:10:14.492920 Done allocating resources.
8943 23:10:14.495640 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8944 23:10:14.499103 Enabling resources...
8945 23:10:14.499510 done.
8946 23:10:14.505511 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8947 23:10:14.505924 Initializing devices...
8948 23:10:14.509070 Root Device init
8949 23:10:14.509561 init hardware done!
8950 23:10:14.512129 0x00000018: ctrlr->caps
8951 23:10:14.515964 52.000 MHz: ctrlr->f_max
8952 23:10:14.516456 0.400 MHz: ctrlr->f_min
8953 23:10:14.519453 0x40ff8080: ctrlr->voltages
8954 23:10:14.522193 sclk: 390625
8955 23:10:14.522682 Bus Width = 1
8956 23:10:14.523010 sclk: 390625
8957 23:10:14.525411 Bus Width = 1
8958 23:10:14.525820 Early init status = 3
8959 23:10:14.532188 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8960 23:10:14.535687 in-header: 03 fc 00 00 01 00 00 00
8961 23:10:14.538793 in-data: 00
8962 23:10:14.541890 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8963 23:10:14.546052 in-header: 03 fd 00 00 00 00 00 00
8964 23:10:14.549354 in-data:
8965 23:10:14.552425 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8966 23:10:14.556862 in-header: 03 fc 00 00 01 00 00 00
8967 23:10:14.559931 in-data: 00
8968 23:10:14.562941 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8969 23:10:14.568418 in-header: 03 fd 00 00 00 00 00 00
8970 23:10:14.571566 in-data:
8971 23:10:14.574594 [SSUSB] Setting up USB HOST controller...
8972 23:10:14.578254 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8973 23:10:14.581234 [SSUSB] phy power-on done.
8974 23:10:14.584856 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8975 23:10:14.591097 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8976 23:10:14.594319 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8977 23:10:14.600839 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8978 23:10:14.607282 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8979 23:10:14.614162 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8980 23:10:14.621327 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8981 23:10:14.627339 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8982 23:10:14.630878 SPM: binary array size = 0x9dc
8983 23:10:14.634419 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8984 23:10:14.640574 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8985 23:10:14.647590 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8986 23:10:14.654314 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8987 23:10:14.657205 configure_display: Starting display init
8988 23:10:14.691213 anx7625_power_on_init: Init interface.
8989 23:10:14.694696 anx7625_disable_pd_protocol: Disabled PD feature.
8990 23:10:14.697718 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8991 23:10:14.725512 anx7625_start_dp_work: Secure OCM version=00
8992 23:10:14.728778 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8993 23:10:14.744315 sp_tx_get_edid_block: EDID Block = 1
8994 23:10:14.847185 Extracted contents:
8995 23:10:14.849732 header: 00 ff ff ff ff ff ff 00
8996 23:10:14.853405 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8997 23:10:14.856487 version: 01 04
8998 23:10:14.859938 basic params: 95 1f 11 78 0a
8999 23:10:14.862652 chroma info: 76 90 94 55 54 90 27 21 50 54
9000 23:10:14.866205 established: 00 00 00
9001 23:10:14.873218 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9002 23:10:14.879494 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9003 23:10:14.882740 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9004 23:10:14.889378 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9005 23:10:14.895614 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9006 23:10:14.899115 extensions: 00
9007 23:10:14.899672 checksum: fb
9008 23:10:14.900042
9009 23:10:14.902489 Manufacturer: IVO Model 57d Serial Number 0
9010 23:10:14.905651 Made week 0 of 2020
9011 23:10:14.909319 EDID version: 1.4
9012 23:10:14.909777 Digital display
9013 23:10:14.912328 6 bits per primary color channel
9014 23:10:14.912943 DisplayPort interface
9015 23:10:14.915672 Maximum image size: 31 cm x 17 cm
9016 23:10:14.918616 Gamma: 220%
9017 23:10:14.919081 Check DPMS levels
9018 23:10:14.922126 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9019 23:10:14.928905 First detailed timing is preferred timing
9020 23:10:14.929373 Established timings supported:
9021 23:10:14.932020 Standard timings supported:
9022 23:10:14.935331 Detailed timings
9023 23:10:14.938441 Hex of detail: 383680a07038204018303c0035ae10000019
9024 23:10:14.945299 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9025 23:10:14.948341 0780 0798 07c8 0820 hborder 0
9026 23:10:14.952128 0438 043b 0447 0458 vborder 0
9027 23:10:14.955200 -hsync -vsync
9028 23:10:14.955629 Did detailed timing
9029 23:10:14.961529 Hex of detail: 000000000000000000000000000000000000
9030 23:10:14.964832 Manufacturer-specified data, tag 0
9031 23:10:14.968442 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9032 23:10:14.971461 ASCII string: InfoVision
9033 23:10:14.975110 Hex of detail: 000000fe00523134304e574635205248200a
9034 23:10:14.978087 ASCII string: R140NWF5 RH
9035 23:10:14.978503 Checksum
9036 23:10:14.981971 Checksum: 0xfb (valid)
9037 23:10:14.984878 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9038 23:10:14.987956 DSI data_rate: 832800000 bps
9039 23:10:14.994534 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9040 23:10:14.997936 anx7625_parse_edid: pixelclock(138800).
9041 23:10:15.001175 hactive(1920), hsync(48), hfp(24), hbp(88)
9042 23:10:15.004396 vactive(1080), vsync(12), vfp(3), vbp(17)
9043 23:10:15.007993 anx7625_dsi_config: config dsi.
9044 23:10:15.014344 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9045 23:10:15.028203 anx7625_dsi_config: success to config DSI
9046 23:10:15.031873 anx7625_dp_start: MIPI phy setup OK.
9047 23:10:15.035145 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9048 23:10:15.038069 mtk_ddp_mode_set invalid vrefresh 60
9049 23:10:15.041983 main_disp_path_setup
9050 23:10:15.042398 ovl_layer_smi_id_en
9051 23:10:15.044783 ovl_layer_smi_id_en
9052 23:10:15.045208 ccorr_config
9053 23:10:15.045540 aal_config
9054 23:10:15.048059 gamma_config
9055 23:10:15.048531 postmask_config
9056 23:10:15.051188 dither_config
9057 23:10:15.054922 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9058 23:10:15.061515 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9059 23:10:15.064537 Root Device init finished in 552 msecs
9060 23:10:15.068047 CPU_CLUSTER: 0 init
9061 23:10:15.074388 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9062 23:10:15.077807 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9063 23:10:15.081370 APU_MBOX 0x190000b0 = 0x10001
9064 23:10:15.084775 APU_MBOX 0x190001b0 = 0x10001
9065 23:10:15.087954 APU_MBOX 0x190005b0 = 0x10001
9066 23:10:15.091038 APU_MBOX 0x190006b0 = 0x10001
9067 23:10:15.094338 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9068 23:10:15.107143 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9069 23:10:15.119874 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9070 23:10:15.126357 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9071 23:10:15.138629 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9072 23:10:15.147162 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9073 23:10:15.150185 CPU_CLUSTER: 0 init finished in 81 msecs
9074 23:10:15.153872 Devices initialized
9075 23:10:15.156828 Show all devs... After init.
9076 23:10:15.157473 Root Device: enabled 1
9077 23:10:15.160199 CPU_CLUSTER: 0: enabled 1
9078 23:10:15.163634 CPU: 00: enabled 1
9079 23:10:15.166749 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9080 23:10:15.170036 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9081 23:10:15.173739 ELOG: NV offset 0x57f000 size 0x1000
9082 23:10:15.180206 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9083 23:10:15.186673 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9084 23:10:15.190283 ELOG: Event(17) added with size 13 at 2023-12-27 23:10:33 UTC
9085 23:10:15.196842 out: cmd=0x121: 03 db 21 01 00 00 00 00
9086 23:10:15.199876 in-header: 03 dd 00 00 2c 00 00 00
9087 23:10:15.209795 in-data: 86 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9088 23:10:15.216568 ELOG: Event(A1) added with size 10 at 2023-12-27 23:10:33 UTC
9089 23:10:15.223028 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9090 23:10:15.229457 ELOG: Event(A0) added with size 9 at 2023-12-27 23:10:33 UTC
9091 23:10:15.233030 elog_add_boot_reason: Logged dev mode boot
9092 23:10:15.239779 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9093 23:10:15.240078 Finalize devices...
9094 23:10:15.243013 Devices finalized
9095 23:10:15.246129 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9096 23:10:15.249794 Writing coreboot table at 0xffe64000
9097 23:10:15.253239 0. 000000000010a000-0000000000113fff: RAMSTAGE
9098 23:10:15.256401 1. 0000000040000000-00000000400fffff: RAM
9099 23:10:15.262855 2. 0000000040100000-000000004032afff: RAMSTAGE
9100 23:10:15.266008 3. 000000004032b000-00000000545fffff: RAM
9101 23:10:15.269526 4. 0000000054600000-000000005465ffff: BL31
9102 23:10:15.273143 5. 0000000054660000-00000000ffe63fff: RAM
9103 23:10:15.279603 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9104 23:10:15.282576 7. 0000000100000000-000000013fffffff: RAM
9105 23:10:15.286260 Passing 5 GPIOs to payload:
9106 23:10:15.289328 NAME | PORT | POLARITY | VALUE
9107 23:10:15.295825 EC in RW | 0x000000aa | low | undefined
9108 23:10:15.299497 EC interrupt | 0x00000005 | low | undefined
9109 23:10:15.302452 TPM interrupt | 0x000000ab | high | undefined
9110 23:10:15.309496 SD card detect | 0x00000011 | high | undefined
9111 23:10:15.312955 speaker enable | 0x00000093 | high | undefined
9112 23:10:15.315784 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9113 23:10:15.319525 in-header: 03 f8 00 00 02 00 00 00
9114 23:10:15.322713 in-data: 03 00
9115 23:10:15.326304 ADC[4]: Raw value=668958 ID=5
9116 23:10:15.326859 ADC[3]: Raw value=212917 ID=1
9117 23:10:15.329115 RAM Code: 0x51
9118 23:10:15.332817 ADC[6]: Raw value=74410 ID=0
9119 23:10:15.333367 ADC[5]: Raw value=211444 ID=1
9120 23:10:15.335753 SKU Code: 0x1
9121 23:10:15.339107 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum bca2
9122 23:10:15.342280 coreboot table: 964 bytes.
9123 23:10:15.345636 IMD ROOT 0. 0xfffff000 0x00001000
9124 23:10:15.349039 IMD SMALL 1. 0xffffe000 0x00001000
9125 23:10:15.352320 RO MCACHE 2. 0xffffc000 0x00001104
9126 23:10:15.355801 CONSOLE 3. 0xfff7c000 0x00080000
9127 23:10:15.359083 FMAP 4. 0xfff7b000 0x00000452
9128 23:10:15.362172 TIME STAMP 5. 0xfff7a000 0x00000910
9129 23:10:15.365523 VBOOT WORK 6. 0xfff66000 0x00014000
9130 23:10:15.368967 RAMOOPS 7. 0xffe66000 0x00100000
9131 23:10:15.372575 COREBOOT 8. 0xffe64000 0x00002000
9132 23:10:15.375846 IMD small region:
9133 23:10:15.378911 IMD ROOT 0. 0xffffec00 0x00000400
9134 23:10:15.382116 VPD 1. 0xffffeb80 0x0000006c
9135 23:10:15.385515 MMC STATUS 2. 0xffffeb60 0x00000004
9136 23:10:15.388691 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9137 23:10:15.392213 Probing TPM: done!
9138 23:10:15.395747 Connected to device vid:did:rid of 1ae0:0028:00
9139 23:10:15.405754 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9140 23:10:15.409274 Initialized TPM device CR50 revision 0
9141 23:10:15.412744 Checking cr50 for pending updates
9142 23:10:15.416601 Reading cr50 TPM mode
9143 23:10:15.425247 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9144 23:10:15.431981 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9145 23:10:15.471938 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9146 23:10:15.475434 Checking segment from ROM address 0x40100000
9147 23:10:15.478789 Checking segment from ROM address 0x4010001c
9148 23:10:15.485451 Loading segment from ROM address 0x40100000
9149 23:10:15.486042 code (compression=0)
9150 23:10:15.494968 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9151 23:10:15.501578 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9152 23:10:15.502060 it's not compressed!
9153 23:10:15.508552 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9154 23:10:15.515160 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9155 23:10:15.532492 Loading segment from ROM address 0x4010001c
9156 23:10:15.533087 Entry Point 0x80000000
9157 23:10:15.535922 Loaded segments
9158 23:10:15.539419 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9159 23:10:15.546004 Jumping to boot code at 0x80000000(0xffe64000)
9160 23:10:15.552272 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9161 23:10:15.558973 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9162 23:10:15.567532 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9163 23:10:15.570220 Checking segment from ROM address 0x40100000
9164 23:10:15.573771 Checking segment from ROM address 0x4010001c
9165 23:10:15.579799 Loading segment from ROM address 0x40100000
9166 23:10:15.580442 code (compression=1)
9167 23:10:15.586868 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9168 23:10:15.596416 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9169 23:10:15.596883 using LZMA
9170 23:10:15.604815 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9171 23:10:15.611499 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9172 23:10:15.615005 Loading segment from ROM address 0x4010001c
9173 23:10:15.615260 Entry Point 0x54601000
9174 23:10:15.618267 Loaded segments
9175 23:10:15.621603 NOTICE: MT8192 bl31_setup
9176 23:10:15.628668 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9177 23:10:15.632021 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9178 23:10:15.635181 WARNING: region 0:
9179 23:10:15.638604 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9180 23:10:15.638923 WARNING: region 1:
9181 23:10:15.645159 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9182 23:10:15.648496 WARNING: region 2:
9183 23:10:15.652168 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9184 23:10:15.655709 WARNING: region 3:
9185 23:10:15.658858 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9186 23:10:15.662190 WARNING: region 4:
9187 23:10:15.668776 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9188 23:10:15.669384 WARNING: region 5:
9189 23:10:15.672206 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9190 23:10:15.675293 WARNING: region 6:
9191 23:10:15.679166 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9192 23:10:15.679862 WARNING: region 7:
9193 23:10:15.685603 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9194 23:10:15.692299 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9195 23:10:15.695783 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9196 23:10:15.699222 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9197 23:10:15.705449 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9198 23:10:15.708930 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9199 23:10:15.712364 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9200 23:10:15.719102 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9201 23:10:15.722229 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9202 23:10:15.728854 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9203 23:10:15.732218 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9204 23:10:15.735722 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9205 23:10:15.742462 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9206 23:10:15.745402 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9207 23:10:15.749049 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9208 23:10:15.755660 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9209 23:10:15.758762 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9210 23:10:15.762211 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9211 23:10:15.768692 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9212 23:10:15.772291 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9213 23:10:15.778947 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9214 23:10:15.782440 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9215 23:10:15.785711 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9216 23:10:15.791988 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9217 23:10:15.795868 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9218 23:10:15.802139 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9219 23:10:15.805445 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9220 23:10:15.808744 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9221 23:10:15.815541 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9222 23:10:15.818778 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9223 23:10:15.822167 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9224 23:10:15.829085 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9225 23:10:15.832556 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9226 23:10:15.835576 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9227 23:10:15.842108 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9228 23:10:15.845470 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9229 23:10:15.849124 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9230 23:10:15.852147 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9231 23:10:15.858767 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9232 23:10:15.862166 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9233 23:10:15.865349 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9234 23:10:15.868858 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9235 23:10:15.875078 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9236 23:10:15.878562 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9237 23:10:15.882100 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9238 23:10:15.889095 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9239 23:10:15.891861 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9240 23:10:15.895119 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9241 23:10:15.898397 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9242 23:10:15.905465 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9243 23:10:15.908497 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9244 23:10:15.915281 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9245 23:10:15.918793 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9246 23:10:15.922163 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9247 23:10:15.928652 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9248 23:10:15.932303 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9249 23:10:15.938559 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9250 23:10:15.941720 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9251 23:10:15.948619 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9252 23:10:15.952035 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9253 23:10:15.958681 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9254 23:10:15.962178 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9255 23:10:15.965140 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9256 23:10:15.971636 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9257 23:10:15.975388 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9258 23:10:15.981579 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9259 23:10:15.985240 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9260 23:10:15.991873 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9261 23:10:15.995372 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9262 23:10:15.998552 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9263 23:10:16.005258 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9264 23:10:16.008177 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9265 23:10:16.015395 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9266 23:10:16.018207 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9267 23:10:16.025409 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9268 23:10:16.028254 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9269 23:10:16.032223 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9270 23:10:16.038579 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9271 23:10:16.041412 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9272 23:10:16.048327 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9273 23:10:16.051961 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9274 23:10:16.058697 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9275 23:10:16.061702 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9276 23:10:16.064785 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9277 23:10:16.071521 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9278 23:10:16.075357 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9279 23:10:16.081377 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9280 23:10:16.085106 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9281 23:10:16.091399 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9282 23:10:16.094780 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9283 23:10:16.098195 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9284 23:10:16.104675 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9285 23:10:16.108151 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9286 23:10:16.114559 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9287 23:10:16.118035 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9288 23:10:16.124501 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9289 23:10:16.128227 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9290 23:10:16.131209 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9291 23:10:16.138358 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9292 23:10:16.140952 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9293 23:10:16.144604 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9294 23:10:16.148100 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9295 23:10:16.154456 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9296 23:10:16.157743 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9297 23:10:16.164140 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9298 23:10:16.167672 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9299 23:10:16.171051 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9300 23:10:16.177579 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9301 23:10:16.180762 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9302 23:10:16.187573 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9303 23:10:16.190698 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9304 23:10:16.194335 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9305 23:10:16.200807 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9306 23:10:16.204358 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9307 23:10:16.210834 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9308 23:10:16.214558 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9309 23:10:16.218312 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9310 23:10:16.224410 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9311 23:10:16.227454 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9312 23:10:16.231178 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9313 23:10:16.237850 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9314 23:10:16.240776 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9315 23:10:16.244477 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9316 23:10:16.247579 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9317 23:10:16.254191 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9318 23:10:16.258131 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9319 23:10:16.260974 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9320 23:10:16.267294 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9321 23:10:16.270610 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9322 23:10:16.277692 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9323 23:10:16.281101 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9324 23:10:16.284325 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9325 23:10:16.291096 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9326 23:10:16.294335 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9327 23:10:16.297482 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9328 23:10:16.303989 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9329 23:10:16.307396 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9330 23:10:16.314031 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9331 23:10:16.317484 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9332 23:10:16.320641 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9333 23:10:16.327675 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9334 23:10:16.331076 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9335 23:10:16.337567 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9336 23:10:16.340494 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9337 23:10:16.343841 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9338 23:10:16.351281 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9339 23:10:16.354269 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9340 23:10:16.360544 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9341 23:10:16.363908 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9342 23:10:16.367377 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9343 23:10:16.374164 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9344 23:10:16.377873 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9345 23:10:16.380440 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9346 23:10:16.387562 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9347 23:10:16.391200 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9348 23:10:16.397288 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9349 23:10:16.400498 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9350 23:10:16.404110 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9351 23:10:16.410483 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9352 23:10:16.413943 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9353 23:10:16.420596 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9354 23:10:16.423838 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9355 23:10:16.427117 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9356 23:10:16.433609 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9357 23:10:16.437331 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9358 23:10:16.443771 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9359 23:10:16.447195 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9360 23:10:16.450553 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9361 23:10:16.457060 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9362 23:10:16.460629 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9363 23:10:16.467098 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9364 23:10:16.470143 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9365 23:10:16.474033 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9366 23:10:16.480192 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9367 23:10:16.483238 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9368 23:10:16.486887 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9369 23:10:16.493905 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9370 23:10:16.497120 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9371 23:10:16.503389 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9372 23:10:16.506657 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9373 23:10:16.510237 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9374 23:10:16.516535 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9375 23:10:16.520014 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9376 23:10:16.526441 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9377 23:10:16.529902 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9378 23:10:16.533109 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9379 23:10:16.540238 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9380 23:10:16.543220 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9381 23:10:16.549799 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9382 23:10:16.553265 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9383 23:10:16.556516 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9384 23:10:16.563317 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9385 23:10:16.566378 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9386 23:10:16.573065 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9387 23:10:16.576637 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9388 23:10:16.579572 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9389 23:10:16.586279 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9390 23:10:16.590057 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9391 23:10:16.596215 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9392 23:10:16.599451 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9393 23:10:16.606209 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9394 23:10:16.609774 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9395 23:10:16.612687 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9396 23:10:16.619762 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9397 23:10:16.622730 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9398 23:10:16.629422 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9399 23:10:16.632628 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9400 23:10:16.639213 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9401 23:10:16.642382 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9402 23:10:16.645618 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9403 23:10:16.652538 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9404 23:10:16.656007 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9405 23:10:16.662360 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9406 23:10:16.665736 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9407 23:10:16.672310 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9408 23:10:16.676082 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9409 23:10:16.679270 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9410 23:10:16.685571 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9411 23:10:16.688828 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9412 23:10:16.695435 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9413 23:10:16.699039 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9414 23:10:16.702040 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9415 23:10:16.708943 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9416 23:10:16.712125 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9417 23:10:16.718340 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9418 23:10:16.721816 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9419 23:10:16.728793 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9420 23:10:16.732046 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9421 23:10:16.735655 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9422 23:10:16.741954 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9423 23:10:16.745017 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9424 23:10:16.748326 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9425 23:10:16.752002 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9426 23:10:16.758568 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9427 23:10:16.761823 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9428 23:10:16.765195 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9429 23:10:16.771763 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9430 23:10:16.775097 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9431 23:10:16.781472 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9432 23:10:16.784856 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9433 23:10:16.788185 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9434 23:10:16.794965 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9435 23:10:16.798148 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9436 23:10:16.801583 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9437 23:10:16.808202 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9438 23:10:16.811241 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9439 23:10:16.814436 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9440 23:10:16.821455 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9441 23:10:16.824545 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9442 23:10:16.827708 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9443 23:10:16.834482 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9444 23:10:16.838101 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9445 23:10:16.844523 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9446 23:10:16.847679 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9447 23:10:16.850853 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9448 23:10:16.857392 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9449 23:10:16.860896 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9450 23:10:16.867380 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9451 23:10:16.870824 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9452 23:10:16.874105 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9453 23:10:16.880895 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9454 23:10:16.884087 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9455 23:10:16.887266 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9456 23:10:16.894130 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9457 23:10:16.897655 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9458 23:10:16.900567 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9459 23:10:16.907234 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9460 23:10:16.910520 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9461 23:10:16.917193 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9462 23:10:16.920586 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9463 23:10:16.923680 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9464 23:10:16.927495 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9465 23:10:16.933733 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9466 23:10:16.936872 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9467 23:10:16.940171 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9468 23:10:16.943638 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9469 23:10:16.947150 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9470 23:10:16.953359 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9471 23:10:16.957056 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9472 23:10:16.960247 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9473 23:10:16.966502 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9474 23:10:16.970436 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9475 23:10:16.973243 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9476 23:10:16.979760 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9477 23:10:16.983336 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9478 23:10:16.986449 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9479 23:10:16.993065 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9480 23:10:16.996580 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9481 23:10:17.003153 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9482 23:10:17.006537 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9483 23:10:17.009832 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9484 23:10:17.016510 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9485 23:10:17.019884 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9486 23:10:17.026094 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9487 23:10:17.029608 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9488 23:10:17.036166 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9489 23:10:17.039855 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9490 23:10:17.042740 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9491 23:10:17.049985 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9492 23:10:17.053106 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9493 23:10:17.059487 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9494 23:10:17.062852 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9495 23:10:17.066365 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9496 23:10:17.072601 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9497 23:10:17.076053 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9498 23:10:17.082612 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9499 23:10:17.085921 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9500 23:10:17.089337 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9501 23:10:17.095808 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9502 23:10:17.099333 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9503 23:10:17.105753 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9504 23:10:17.109168 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9505 23:10:17.115655 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9506 23:10:17.118924 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9507 23:10:17.122280 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9508 23:10:17.129294 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9509 23:10:17.132409 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9510 23:10:17.139128 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9511 23:10:17.142527 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9512 23:10:17.145418 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9513 23:10:17.152173 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9514 23:10:17.155514 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9515 23:10:17.162214 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9516 23:10:17.165632 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9517 23:10:17.168769 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9518 23:10:17.175458 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9519 23:10:17.178493 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9520 23:10:17.185273 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9521 23:10:17.188889 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9522 23:10:17.195698 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9523 23:10:17.198602 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9524 23:10:17.201804 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9525 23:10:17.208509 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9526 23:10:17.211897 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9527 23:10:17.218549 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9528 23:10:17.221877 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9529 23:10:17.225065 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9530 23:10:17.231743 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9531 23:10:17.235158 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9532 23:10:17.241713 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9533 23:10:17.244914 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9534 23:10:17.248273 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9535 23:10:17.254857 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9536 23:10:17.258443 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9537 23:10:17.264768 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9538 23:10:17.268148 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9539 23:10:17.271489 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9540 23:10:17.278476 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9541 23:10:17.281525 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9542 23:10:17.288068 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9543 23:10:17.291379 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9544 23:10:17.298056 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9545 23:10:17.301201 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9546 23:10:17.304524 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9547 23:10:17.311255 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9548 23:10:17.314527 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9549 23:10:17.320865 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9550 23:10:17.324450 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9551 23:10:17.331305 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9552 23:10:17.334115 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9553 23:10:17.341469 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9554 23:10:17.344469 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9555 23:10:17.347327 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9556 23:10:17.354019 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9557 23:10:17.357863 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9558 23:10:17.364385 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9559 23:10:17.367124 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9560 23:10:17.373950 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9561 23:10:17.377325 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9562 23:10:17.384007 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9563 23:10:17.387133 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9564 23:10:17.390801 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9565 23:10:17.397372 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9566 23:10:17.400406 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9567 23:10:17.406998 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9568 23:10:17.410343 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9569 23:10:17.416908 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9570 23:10:17.420303 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9571 23:10:17.423703 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9572 23:10:17.430272 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9573 23:10:17.433457 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9574 23:10:17.440168 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9575 23:10:17.443556 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9576 23:10:17.450110 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9577 23:10:17.453300 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9578 23:10:17.456791 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9579 23:10:17.463419 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9580 23:10:17.466722 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9581 23:10:17.473526 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9582 23:10:17.476753 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9583 23:10:17.483136 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9584 23:10:17.487033 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9585 23:10:17.493304 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9586 23:10:17.496388 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9587 23:10:17.499747 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9588 23:10:17.506637 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9589 23:10:17.509747 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9590 23:10:17.515931 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9591 23:10:17.519599 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9592 23:10:17.526297 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9593 23:10:17.529491 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9594 23:10:17.536287 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9595 23:10:17.539696 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9596 23:10:17.542945 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9597 23:10:17.549671 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9598 23:10:17.553245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9599 23:10:17.559404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9600 23:10:17.562631 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9601 23:10:17.569348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9602 23:10:17.572552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9603 23:10:17.579276 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9604 23:10:17.582451 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9605 23:10:17.589066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9606 23:10:17.591923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9607 23:10:17.595389 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9608 23:10:17.602527 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9609 23:10:17.605303 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9610 23:10:17.611762 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9611 23:10:17.615073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9612 23:10:17.621625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9613 23:10:17.624994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9614 23:10:17.631745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9615 23:10:17.635134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9616 23:10:17.642098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9617 23:10:17.645023 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9618 23:10:17.651916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9619 23:10:17.654967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9620 23:10:17.662004 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9621 23:10:17.665341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9622 23:10:17.671428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9623 23:10:17.675443 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9624 23:10:17.681660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9625 23:10:17.685484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9626 23:10:17.691330 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9627 23:10:17.697946 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9628 23:10:17.701644 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9629 23:10:17.702266 INFO: [APUAPC] vio 0
9630 23:10:17.708663 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9631 23:10:17.711618 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9632 23:10:17.714903 INFO: [APUAPC] D0_APC_0: 0x400510
9633 23:10:17.718520 INFO: [APUAPC] D0_APC_1: 0x0
9634 23:10:17.721770 INFO: [APUAPC] D0_APC_2: 0x1540
9635 23:10:17.725202 INFO: [APUAPC] D0_APC_3: 0x0
9636 23:10:17.728332 INFO: [APUAPC] D1_APC_0: 0xffffffff
9637 23:10:17.732314 INFO: [APUAPC] D1_APC_1: 0xffffffff
9638 23:10:17.734802 INFO: [APUAPC] D1_APC_2: 0x3fffff
9639 23:10:17.738572 INFO: [APUAPC] D1_APC_3: 0x0
9640 23:10:17.741412 INFO: [APUAPC] D2_APC_0: 0xffffffff
9641 23:10:17.745255 INFO: [APUAPC] D2_APC_1: 0xffffffff
9642 23:10:17.748059 INFO: [APUAPC] D2_APC_2: 0x3fffff
9643 23:10:17.752151 INFO: [APUAPC] D2_APC_3: 0x0
9644 23:10:17.755321 INFO: [APUAPC] D3_APC_0: 0xffffffff
9645 23:10:17.758528 INFO: [APUAPC] D3_APC_1: 0xffffffff
9646 23:10:17.761872 INFO: [APUAPC] D3_APC_2: 0x3fffff
9647 23:10:17.765055 INFO: [APUAPC] D3_APC_3: 0x0
9648 23:10:17.768439 INFO: [APUAPC] D4_APC_0: 0xffffffff
9649 23:10:17.771434 INFO: [APUAPC] D4_APC_1: 0xffffffff
9650 23:10:17.774843 INFO: [APUAPC] D4_APC_2: 0x3fffff
9651 23:10:17.775316 INFO: [APUAPC] D4_APC_3: 0x0
9652 23:10:17.781740 INFO: [APUAPC] D5_APC_0: 0xffffffff
9653 23:10:17.784990 INFO: [APUAPC] D5_APC_1: 0xffffffff
9654 23:10:17.788360 INFO: [APUAPC] D5_APC_2: 0x3fffff
9655 23:10:17.789128 INFO: [APUAPC] D5_APC_3: 0x0
9656 23:10:17.791493 INFO: [APUAPC] D6_APC_0: 0xffffffff
9657 23:10:17.794672 INFO: [APUAPC] D6_APC_1: 0xffffffff
9658 23:10:17.798139 INFO: [APUAPC] D6_APC_2: 0x3fffff
9659 23:10:17.801321 INFO: [APUAPC] D6_APC_3: 0x0
9660 23:10:17.804770 INFO: [APUAPC] D7_APC_0: 0xffffffff
9661 23:10:17.808105 INFO: [APUAPC] D7_APC_1: 0xffffffff
9662 23:10:17.811352 INFO: [APUAPC] D7_APC_2: 0x3fffff
9663 23:10:17.814431 INFO: [APUAPC] D7_APC_3: 0x0
9664 23:10:17.817636 INFO: [APUAPC] D8_APC_0: 0xffffffff
9665 23:10:17.821272 INFO: [APUAPC] D8_APC_1: 0xffffffff
9666 23:10:17.824449 INFO: [APUAPC] D8_APC_2: 0x3fffff
9667 23:10:17.828326 INFO: [APUAPC] D8_APC_3: 0x0
9668 23:10:17.831594 INFO: [APUAPC] D9_APC_0: 0xffffffff
9669 23:10:17.834512 INFO: [APUAPC] D9_APC_1: 0xffffffff
9670 23:10:17.837514 INFO: [APUAPC] D9_APC_2: 0x3fffff
9671 23:10:17.841352 INFO: [APUAPC] D9_APC_3: 0x0
9672 23:10:17.844130 INFO: [APUAPC] D10_APC_0: 0xffffffff
9673 23:10:17.847798 INFO: [APUAPC] D10_APC_1: 0xffffffff
9674 23:10:17.851303 INFO: [APUAPC] D10_APC_2: 0x3fffff
9675 23:10:17.854640 INFO: [APUAPC] D10_APC_3: 0x0
9676 23:10:17.857533 INFO: [APUAPC] D11_APC_0: 0xffffffff
9677 23:10:17.861371 INFO: [APUAPC] D11_APC_1: 0xffffffff
9678 23:10:17.864521 INFO: [APUAPC] D11_APC_2: 0x3fffff
9679 23:10:17.867583 INFO: [APUAPC] D11_APC_3: 0x0
9680 23:10:17.871061 INFO: [APUAPC] D12_APC_0: 0xffffffff
9681 23:10:17.874249 INFO: [APUAPC] D12_APC_1: 0xffffffff
9682 23:10:17.877711 INFO: [APUAPC] D12_APC_2: 0x3fffff
9683 23:10:17.881323 INFO: [APUAPC] D12_APC_3: 0x0
9684 23:10:17.884197 INFO: [APUAPC] D13_APC_0: 0xffffffff
9685 23:10:17.887839 INFO: [APUAPC] D13_APC_1: 0xffffffff
9686 23:10:17.890974 INFO: [APUAPC] D13_APC_2: 0x3fffff
9687 23:10:17.894309 INFO: [APUAPC] D13_APC_3: 0x0
9688 23:10:17.897286 INFO: [APUAPC] D14_APC_0: 0xffffffff
9689 23:10:17.900887 INFO: [APUAPC] D14_APC_1: 0xffffffff
9690 23:10:17.903899 INFO: [APUAPC] D14_APC_2: 0x3fffff
9691 23:10:17.907147 INFO: [APUAPC] D14_APC_3: 0x0
9692 23:10:17.910430 INFO: [APUAPC] D15_APC_0: 0xffffffff
9693 23:10:17.913987 INFO: [APUAPC] D15_APC_1: 0xffffffff
9694 23:10:17.917268 INFO: [APUAPC] D15_APC_2: 0x3fffff
9695 23:10:17.920412 INFO: [APUAPC] D15_APC_3: 0x0
9696 23:10:17.923754 INFO: [APUAPC] APC_CON: 0x4
9697 23:10:17.927249 INFO: [NOCDAPC] D0_APC_0: 0x0
9698 23:10:17.930385 INFO: [NOCDAPC] D0_APC_1: 0x0
9699 23:10:17.933524 INFO: [NOCDAPC] D1_APC_0: 0x0
9700 23:10:17.937093 INFO: [NOCDAPC] D1_APC_1: 0xfff
9701 23:10:17.940409 INFO: [NOCDAPC] D2_APC_0: 0x0
9702 23:10:17.943903 INFO: [NOCDAPC] D2_APC_1: 0xfff
9703 23:10:17.944466 INFO: [NOCDAPC] D3_APC_0: 0x0
9704 23:10:17.947441 INFO: [NOCDAPC] D3_APC_1: 0xfff
9705 23:10:17.950594 INFO: [NOCDAPC] D4_APC_0: 0x0
9706 23:10:17.953619 INFO: [NOCDAPC] D4_APC_1: 0xfff
9707 23:10:17.956788 INFO: [NOCDAPC] D5_APC_0: 0x0
9708 23:10:17.959949 INFO: [NOCDAPC] D5_APC_1: 0xfff
9709 23:10:17.963547 INFO: [NOCDAPC] D6_APC_0: 0x0
9710 23:10:17.966911 INFO: [NOCDAPC] D6_APC_1: 0xfff
9711 23:10:17.970151 INFO: [NOCDAPC] D7_APC_0: 0x0
9712 23:10:17.973489 INFO: [NOCDAPC] D7_APC_1: 0xfff
9713 23:10:17.976729 INFO: [NOCDAPC] D8_APC_0: 0x0
9714 23:10:17.979920 INFO: [NOCDAPC] D8_APC_1: 0xfff
9715 23:10:17.980413 INFO: [NOCDAPC] D9_APC_0: 0x0
9716 23:10:17.983846 INFO: [NOCDAPC] D9_APC_1: 0xfff
9717 23:10:17.986495 INFO: [NOCDAPC] D10_APC_0: 0x0
9718 23:10:17.990451 INFO: [NOCDAPC] D10_APC_1: 0xfff
9719 23:10:17.993604 INFO: [NOCDAPC] D11_APC_0: 0x0
9720 23:10:17.996867 INFO: [NOCDAPC] D11_APC_1: 0xfff
9721 23:10:18.000143 INFO: [NOCDAPC] D12_APC_0: 0x0
9722 23:10:18.003404 INFO: [NOCDAPC] D12_APC_1: 0xfff
9723 23:10:18.006671 INFO: [NOCDAPC] D13_APC_0: 0x0
9724 23:10:18.009526 INFO: [NOCDAPC] D13_APC_1: 0xfff
9725 23:10:18.012871 INFO: [NOCDAPC] D14_APC_0: 0x0
9726 23:10:18.016611 INFO: [NOCDAPC] D14_APC_1: 0xfff
9727 23:10:18.019966 INFO: [NOCDAPC] D15_APC_0: 0x0
9728 23:10:18.023501 INFO: [NOCDAPC] D15_APC_1: 0xfff
9729 23:10:18.024079 INFO: [NOCDAPC] APC_CON: 0x4
9730 23:10:18.026309 INFO: [APUAPC] set_apusys_apc done
9731 23:10:18.030047 INFO: [DEVAPC] devapc_init done
9732 23:10:18.036379 INFO: GICv3 without legacy support detected.
9733 23:10:18.039389 INFO: ARM GICv3 driver initialized in EL3
9734 23:10:18.043155 INFO: Maximum SPI INTID supported: 639
9735 23:10:18.046194 INFO: BL31: Initializing runtime services
9736 23:10:18.052865 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9737 23:10:18.056132 INFO: SPM: enable CPC mode
9738 23:10:18.059652 INFO: mcdi ready for mcusys-off-idle and system suspend
9739 23:10:18.065652 INFO: BL31: Preparing for EL3 exit to normal world
9740 23:10:18.068955 INFO: Entry point address = 0x80000000
9741 23:10:18.069417 INFO: SPSR = 0x8
9742 23:10:18.076356
9743 23:10:18.076900
9744 23:10:18.077268
9745 23:10:18.080009 Starting depthcharge on Spherion...
9746 23:10:18.080564
9747 23:10:18.080968 Wipe memory regions:
9748 23:10:18.081308
9749 23:10:18.083967 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9750 23:10:18.084517 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9751 23:10:18.084994 Setting prompt string to ['asurada:']
9752 23:10:18.085403 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9753 23:10:18.086139 [0x00000040000000, 0x00000054600000)
9754 23:10:18.205937
9755 23:10:18.206549 [0x00000054660000, 0x00000080000000)
9756 23:10:18.466042
9757 23:10:18.466560 [0x000000821a7280, 0x000000ffe64000)
9758 23:10:19.210778
9759 23:10:19.211321 [0x00000100000000, 0x00000140000000)
9760 23:10:19.591968
9761 23:10:19.595531 Initializing XHCI USB controller at 0x11200000.
9762 23:10:20.633033
9763 23:10:20.636311 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9764 23:10:20.636614
9765 23:10:20.636887
9766 23:10:20.637124
9767 23:10:20.637692 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9769 23:10:20.738875 asurada: tftpboot 192.168.201.1 12395386/tftp-deploy-_crc1ad_/kernel/image.itb 12395386/tftp-deploy-_crc1ad_/kernel/cmdline
9770 23:10:20.739527 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9771 23:10:20.740034 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9772 23:10:20.744296 tftpboot 192.168.201.1 12395386/tftp-deploy-_crc1ad_/kernel/image.ittp-deploy-_crc1ad_/kernel/cmdline
9773 23:10:20.744805
9774 23:10:20.745175 Waiting for link
9775 23:10:20.904986
9776 23:10:20.905529 R8152: Initializing
9777 23:10:20.905892
9778 23:10:20.908036 Version 9 (ocp_data = 6010)
9779 23:10:20.908588
9780 23:10:20.911330 R8152: Done initializing
9781 23:10:20.911885
9782 23:10:20.912247 Adding net device
9783 23:10:22.851171
9784 23:10:22.851696 done.
9785 23:10:22.852054
9786 23:10:22.852415 MAC: 00:e0:4c:68:03:bd
9787 23:10:22.852765
9788 23:10:22.854378 Sending DHCP discover... done.
9789 23:10:22.854827
9790 23:10:22.857586 Waiting for reply... done.
9791 23:10:22.858101
9792 23:10:22.860996 Sending DHCP request... done.
9793 23:10:22.861500
9794 23:10:22.867766 Waiting for reply... done.
9795 23:10:22.868218
9796 23:10:22.868642 My ip is 192.168.201.16
9797 23:10:22.869019
9798 23:10:22.871038 The DHCP server ip is 192.168.201.1
9799 23:10:22.871488
9800 23:10:22.878276 TFTP server IP predefined by user: 192.168.201.1
9801 23:10:22.878760
9802 23:10:22.884548 Bootfile predefined by user: 12395386/tftp-deploy-_crc1ad_/kernel/image.itb
9803 23:10:22.885183
9804 23:10:22.887910 Sending tftp read request... done.
9805 23:10:22.888364
9806 23:10:22.894390 Waiting for the transfer...
9807 23:10:22.894847
9808 23:10:23.230079 00000000 ################################################################
9809 23:10:23.230210
9810 23:10:23.483628 00080000 ################################################################
9811 23:10:23.483759
9812 23:10:23.734699 00100000 ################################################################
9813 23:10:23.734828
9814 23:10:23.985283 00180000 ################################################################
9815 23:10:23.985417
9816 23:10:24.239042 00200000 ################################################################
9817 23:10:24.239171
9818 23:10:24.490702 00280000 ################################################################
9819 23:10:24.490833
9820 23:10:24.741818 00300000 ################################################################
9821 23:10:24.741950
9822 23:10:24.992105 00380000 ################################################################
9823 23:10:24.992240
9824 23:10:25.245686 00400000 ################################################################
9825 23:10:25.245817
9826 23:10:25.497258 00480000 ################################################################
9827 23:10:25.497390
9828 23:10:25.748322 00500000 ################################################################
9829 23:10:25.748482
9830 23:10:26.018430 00580000 ################################################################
9831 23:10:26.018567
9832 23:10:26.306996 00600000 ################################################################
9833 23:10:26.307130
9834 23:10:26.557687 00680000 ################################################################
9835 23:10:26.557849
9836 23:10:26.839333 00700000 ################################################################
9837 23:10:26.839464
9838 23:10:27.113224 00780000 ################################################################
9839 23:10:27.113359
9840 23:10:27.379002 00800000 ################################################################
9841 23:10:27.379130
9842 23:10:27.633693 00880000 ################################################################
9843 23:10:27.633826
9844 23:10:27.884479 00900000 ################################################################
9845 23:10:27.884608
9846 23:10:28.140923 00980000 ################################################################
9847 23:10:28.141057
9848 23:10:28.392212 00a00000 ################################################################
9849 23:10:28.392346
9850 23:10:28.643353 00a80000 ################################################################
9851 23:10:28.643484
9852 23:10:28.897502 00b00000 ################################################################
9853 23:10:28.897652
9854 23:10:29.154241 00b80000 ################################################################
9855 23:10:29.154370
9856 23:10:29.405154 00c00000 ################################################################
9857 23:10:29.405283
9858 23:10:29.655721 00c80000 ################################################################
9859 23:10:29.655845
9860 23:10:29.908722 00d00000 ################################################################
9861 23:10:29.908850
9862 23:10:30.160121 00d80000 ################################################################
9863 23:10:30.160249
9864 23:10:30.412143 00e00000 ################################################################
9865 23:10:30.412276
9866 23:10:30.663166 00e80000 ################################################################
9867 23:10:30.663301
9868 23:10:30.917568 00f00000 ################################################################
9869 23:10:30.917694
9870 23:10:31.175459 00f80000 ################################################################
9871 23:10:31.175590
9872 23:10:31.429987 01000000 ################################################################
9873 23:10:31.430129
9874 23:10:31.718596 01080000 ################################################################
9875 23:10:31.718727
9876 23:10:31.997979 01100000 ################################################################
9877 23:10:31.998105
9878 23:10:32.277899 01180000 ################################################################
9879 23:10:32.278026
9880 23:10:32.563573 01200000 ################################################################
9881 23:10:32.563726
9882 23:10:32.847955 01280000 ################################################################
9883 23:10:32.848107
9884 23:10:33.126877 01300000 ################################################################
9885 23:10:33.127030
9886 23:10:33.406736 01380000 ################################################################
9887 23:10:33.406862
9888 23:10:33.695189 01400000 ################################################################
9889 23:10:33.695316
9890 23:10:33.990344 01480000 ################################################################
9891 23:10:33.990468
9892 23:10:34.281122 01500000 ################################################################
9893 23:10:34.281250
9894 23:10:34.584245 01580000 ################################################################
9895 23:10:34.584374
9896 23:10:34.887378 01600000 ################################################################
9897 23:10:34.887508
9898 23:10:35.189416 01680000 ################################################################
9899 23:10:35.189546
9900 23:10:35.475385 01700000 ################################################################
9901 23:10:35.475516
9902 23:10:35.768861 01780000 ################################################################
9903 23:10:35.768991
9904 23:10:36.053718 01800000 ################################################################
9905 23:10:36.053892
9906 23:10:36.347646 01880000 ################################################################
9907 23:10:36.347778
9908 23:10:36.641515 01900000 ################################################################
9909 23:10:36.641643
9910 23:10:36.929534 01980000 ################################################################
9911 23:10:36.929698
9912 23:10:37.207301 01a00000 ################################################################
9913 23:10:37.207423
9914 23:10:37.490449 01a80000 ################################################################
9915 23:10:37.490582
9916 23:10:37.772843 01b00000 ################################################################
9917 23:10:37.772973
9918 23:10:38.056488 01b80000 ################################################################
9919 23:10:38.056643
9920 23:10:38.347413 01c00000 ################################################################
9921 23:10:38.347544
9922 23:10:38.641660 01c80000 ################################################################
9923 23:10:38.641787
9924 23:10:38.934682 01d00000 ################################################################
9925 23:10:38.934831
9926 23:10:39.211605 01d80000 ################################################################
9927 23:10:39.211764
9928 23:10:39.492023 01e00000 ################################################################
9929 23:10:39.492147
9930 23:10:39.786310 01e80000 ################################################################
9931 23:10:39.786439
9932 23:10:40.067754 01f00000 ################################################################
9933 23:10:40.067880
9934 23:10:40.351596 01f80000 ################################################################
9935 23:10:40.351750
9936 23:10:40.638400 02000000 ################################################################
9937 23:10:40.638543
9938 23:10:40.923015 02080000 ################################################################
9939 23:10:40.923143
9940 23:10:41.201869 02100000 ################################################################
9941 23:10:41.202009
9942 23:10:41.482851 02180000 ################################################################
9943 23:10:41.483005
9944 23:10:41.775733 02200000 ################################################################
9945 23:10:41.775883
9946 23:10:42.055056 02280000 ################################################################
9947 23:10:42.055216
9948 23:10:42.338798 02300000 ################################################################
9949 23:10:42.338944
9950 23:10:42.626419 02380000 ################################################################
9951 23:10:42.626566
9952 23:10:42.913642 02400000 ################################################################
9953 23:10:42.913778
9954 23:10:43.192569 02480000 ################################################################
9955 23:10:43.192749
9956 23:10:43.479517 02500000 ################################################################
9957 23:10:43.479671
9958 23:10:43.759302 02580000 ################################################################
9959 23:10:43.759438
9960 23:10:44.058900 02600000 ################################################################
9961 23:10:44.059073
9962 23:10:44.359409 02680000 ################################################################
9963 23:10:44.359541
9964 23:10:44.637441 02700000 ################################################################
9965 23:10:44.637579
9966 23:10:44.919368 02780000 ################################################################
9967 23:10:44.919527
9968 23:10:45.213176 02800000 ################################################################
9969 23:10:45.213316
9970 23:10:45.500764 02880000 ################################################################
9971 23:10:45.500895
9972 23:10:45.769408 02900000 ################################################################
9973 23:10:45.769546
9974 23:10:46.019924 02980000 ################################################################
9975 23:10:46.020056
9976 23:10:46.276940 02a00000 ################################################################
9977 23:10:46.277071
9978 23:10:46.528066 02a80000 ################################################################
9979 23:10:46.528198
9980 23:10:46.778710 02b00000 ################################################################
9981 23:10:46.778845
9982 23:10:47.030415 02b80000 ################################################################
9983 23:10:47.030548
9984 23:10:47.281304 02c00000 ################################################################
9985 23:10:47.281443
9986 23:10:47.536301 02c80000 ################################################################
9987 23:10:47.536463
9988 23:10:47.808101 02d00000 ################################################################
9989 23:10:47.808277
9990 23:10:48.060064 02d80000 ################################################################
9991 23:10:48.060229
9992 23:10:48.314474 02e00000 ################################################################
9993 23:10:48.314610
9994 23:10:48.568081 02e80000 ################################################################
9995 23:10:48.568213
9996 23:10:48.834839 02f00000 ################################################################
9997 23:10:48.834978
9998 23:10:49.127398 02f80000 ################################################################
9999 23:10:49.127540
10000 23:10:49.417564 03000000 ################################################################
10001 23:10:49.417697
10002 23:10:49.447553 03080000 ###### done.
10003 23:10:49.447992
10004 23:10:49.451174 The bootfile was 50904682 bytes long.
10005 23:10:49.451597
10006 23:10:49.454147 Sending tftp read request... done.
10007 23:10:49.454569
10008 23:10:49.457765 Waiting for the transfer...
10009 23:10:49.458186
10010 23:10:49.458520 00000000 # done.
10011 23:10:49.458846
10012 23:10:49.464335 Command line loaded dynamically from TFTP file: 12395386/tftp-deploy-_crc1ad_/kernel/cmdline
10013 23:10:49.468154
10014 23:10:49.481048 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10015 23:10:49.481627
10016 23:10:49.481998 Loading FIT.
10017 23:10:49.482342
10018 23:10:49.484425 Image ramdisk-1 has 39374984 bytes.
10019 23:10:49.484934
10020 23:10:49.487857 Image fdt-1 has 47278 bytes.
10021 23:10:49.488318
10022 23:10:49.490848 Image kernel-1 has 11480388 bytes.
10023 23:10:49.491408
10024 23:10:49.497642 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10025 23:10:49.498213
10026 23:10:49.517320 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10027 23:10:49.517894
10028 23:10:49.520655 Choosing best match conf-1 for compat google,spherion-rev3.
10029 23:10:49.525610
10030 23:10:49.529879 Connected to device vid:did:rid of 1ae0:0028:00
10031 23:10:49.537200
10032 23:10:49.540530 tpm_get_response: command 0x17b, return code 0x0
10033 23:10:49.541174
10034 23:10:49.543538 ec_init: CrosEC protocol v3 supported (256, 248)
10035 23:10:49.547997
10036 23:10:49.551149 tpm_cleanup: add release locality here.
10037 23:10:49.551613
10038 23:10:49.551984 Shutting down all USB controllers.
10039 23:10:49.554346
10040 23:10:49.554806 Removing current net device
10041 23:10:49.555175
10042 23:10:49.561447 Exiting depthcharge with code 4 at timestamp: 59732941
10043 23:10:49.561990
10044 23:10:49.564781 LZMA decompressing kernel-1 to 0x821a6718
10045 23:10:49.565339
10046 23:10:49.567766 LZMA decompressing kernel-1 to 0x40000000
10047 23:10:51.003028
10048 23:10:51.003653 jumping to kernel
10049 23:10:51.005965 end: 2.2.4 bootloader-commands (duration 00:00:33) [common]
10050 23:10:51.006529 start: 2.2.5 auto-login-action (timeout 00:03:53) [common]
10051 23:10:51.006947 Setting prompt string to ['Linux version [0-9]']
10052 23:10:51.007328 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10053 23:10:51.007706 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10054 23:10:51.053010
10055 23:10:51.056482 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10056 23:10:51.059921 start: 2.2.5.1 login-action (timeout 00:03:53) [common]
10057 23:10:51.060241 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10058 23:10:51.060445 Setting prompt string to []
10059 23:10:51.060659 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10060 23:10:51.060891 Using line separator: #'\n'#
10061 23:10:51.061058 No login prompt set.
10062 23:10:51.061226 Parsing kernel messages
10063 23:10:51.061378 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10064 23:10:51.061655 [login-action] Waiting for messages, (timeout 00:03:53)
10065 23:10:51.079452 [ 0.000000] Linux version 6.1.67-cip12-rt7 (KernelCI@build-j59954-arm64-gcc-10-defconfig-arm64-chromebook-nblph) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023
10066 23:10:51.082742 [ 0.000000] random: crng init done
10067 23:10:51.089250 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10068 23:10:51.092347 [ 0.000000] efi: UEFI not found.
10069 23:10:51.099535 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10070 23:10:51.109062 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10071 23:10:51.118968 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10072 23:10:51.125385 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10073 23:10:51.131949 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10074 23:10:51.138914 [ 0.000000] printk: bootconsole [mtk8250] enabled
10075 23:10:51.145714 [ 0.000000] NUMA: No NUMA configuration found
10076 23:10:51.151987 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10077 23:10:51.158808 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d3a00-0x13f7d5fff]
10078 23:10:51.159373 [ 0.000000] Zone ranges:
10079 23:10:51.165346 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10080 23:10:51.168489 [ 0.000000] DMA32 empty
10081 23:10:51.174968 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10082 23:10:51.178580 [ 0.000000] Movable zone start for each node
10083 23:10:51.181533 [ 0.000000] Early memory node ranges
10084 23:10:51.188014 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10085 23:10:51.194904 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10086 23:10:51.201711 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10087 23:10:51.208111 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10088 23:10:51.214788 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10089 23:10:51.221274 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10090 23:10:51.252460 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10091 23:10:51.258947 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10092 23:10:51.265626 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10093 23:10:51.269263 [ 0.000000] psci: probing for conduit method from DT.
10094 23:10:51.275636 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10095 23:10:51.278818 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10096 23:10:51.285675 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10097 23:10:51.288438 [ 0.000000] psci: SMC Calling Convention v1.2
10098 23:10:51.295090 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10099 23:10:51.298732 [ 0.000000] Detected VIPT I-cache on CPU0
10100 23:10:51.305409 [ 0.000000] CPU features: detected: GIC system register CPU interface
10101 23:10:51.312126 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10102 23:10:51.318547 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10103 23:10:51.325273 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10104 23:10:51.331824 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10105 23:10:51.341995 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10106 23:10:51.345120 [ 0.000000] alternatives: applying boot alternatives
10107 23:10:51.351425 [ 0.000000] Fallback order for Node 0: 0
10108 23:10:51.358377 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10109 23:10:51.361327 [ 0.000000] Policy zone: Normal
10110 23:10:51.374537 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10111 23:10:51.384513 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10112 23:10:51.395151 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10113 23:10:51.404964 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10114 23:10:51.411446 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10115 23:10:51.414905 <6>[ 0.000000] software IO TLB: area num 8.
10116 23:10:51.470604 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10117 23:10:51.550779 <6>[ 0.000000] Memory: 3815856K/4191232K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 342608K reserved, 32768K cma-reserved)
10118 23:10:51.557299 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10119 23:10:51.564152 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10120 23:10:51.567611 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10121 23:10:51.574111 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10122 23:10:51.580884 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10123 23:10:51.583849 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10124 23:10:51.594101 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10125 23:10:51.600237 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10126 23:10:51.606944 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10127 23:10:51.613359 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10128 23:10:51.616913 <6>[ 0.000000] GICv3: 608 SPIs implemented
10129 23:10:51.620176 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10130 23:10:51.626524 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10131 23:10:51.630013 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10132 23:10:51.636320 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10133 23:10:51.649572 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10134 23:10:51.663150 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10135 23:10:51.669453 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10136 23:10:51.677620 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10137 23:10:51.690386 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10138 23:10:51.696935 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10139 23:10:51.704152 <6>[ 0.009229] Console: colour dummy device 80x25
10140 23:10:51.713997 <6>[ 0.013951] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10141 23:10:51.720657 <6>[ 0.024458] pid_max: default: 32768 minimum: 301
10142 23:10:51.723710 <6>[ 0.029329] LSM: Security Framework initializing
10143 23:10:51.730644 <6>[ 0.034274] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10144 23:10:51.740140 <6>[ 0.041926] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10145 23:10:51.746977 <6>[ 0.051142] cblist_init_generic: Setting adjustable number of callback queues.
10146 23:10:51.753419 <6>[ 0.058631] cblist_init_generic: Setting shift to 3 and lim to 1.
10147 23:10:51.763603 <6>[ 0.064968] cblist_init_generic: Setting adjustable number of callback queues.
10148 23:10:51.766616 <6>[ 0.072396] cblist_init_generic: Setting shift to 3 and lim to 1.
10149 23:10:51.773714 <6>[ 0.078835] rcu: Hierarchical SRCU implementation.
10150 23:10:51.779938 <6>[ 0.078837] rcu: Max phase no-delay instances is 1000.
10151 23:10:51.786824 <6>[ 0.078862] printk: bootconsole [mtk8250] printing thread started
10152 23:10:51.793599 <6>[ 0.097195] EFI services will not be available.
10153 23:10:51.796508 <6>[ 0.097369] smp: Bringing up secondary CPUs ...
10154 23:10:51.800039 <6>[ 0.097674] Detected VIPT I-cache on CPU1
10155 23:10:51.810285 <6>[ 0.097742] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10156 23:10:51.816239 <6>[ 0.097773] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10157 23:10:51.825074 <6>[ 0.125595] Detected VIPT I-cache on CPU2
10158 23:10:51.831961 <6>[ 0.125641] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10159 23:10:51.838453 <6>[ 0.125656] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10160 23:10:51.844990 <6>[ 0.125910] Detected VIPT I-cache on CPU3
10161 23:10:51.851707 <6>[ 0.125956] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10162 23:10:51.858501 <6>[ 0.125969] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10163 23:10:51.861290 <6>[ 0.126284] CPU features: detected: Spectre-v4
10164 23:10:51.868207 <6>[ 0.126290] CPU features: detected: Spectre-BHB
10165 23:10:51.871350 <6>[ 0.126294] Detected PIPT I-cache on CPU4
10166 23:10:51.878179 <6>[ 0.126354] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10167 23:10:51.884755 <6>[ 0.126370] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10168 23:10:51.890961 <6>[ 0.126661] Detected PIPT I-cache on CPU5
10169 23:10:51.897801 <6>[ 0.126721] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10170 23:10:51.904465 <6>[ 0.126737] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10171 23:10:51.907610 <6>[ 0.127011] Detected PIPT I-cache on CPU6
10172 23:10:51.914080 <6>[ 0.127072] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10173 23:10:51.923766 <6>[ 0.127088] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10174 23:10:51.927057 <6>[ 0.127383] Detected PIPT I-cache on CPU7
10175 23:10:51.934143 <6>[ 0.127446] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10176 23:10:51.940565 <6>[ 0.127462] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10177 23:10:51.944166 <6>[ 0.127509] smp: Brought up 1 node, 8 CPUs
10178 23:10:51.950194 <6>[ 0.127513] SMP: Total of 8 processors activated.
10179 23:10:51.956845 <6>[ 0.127516] CPU features: detected: 32-bit EL0 Support
10180 23:10:51.963654 <6>[ 0.127518] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10181 23:10:51.970181 <6>[ 0.127520] CPU features: detected: Common not Private translations
10182 23:10:51.976930 <6>[ 0.127522] CPU features: detected: CRC32 instructions
10183 23:10:51.983487 <6>[ 0.127524] CPU features: detected: RCpc load-acquire (LDAPR)
10184 23:10:51.986590 <6>[ 0.127526] CPU features: detected: LSE atomic instructions
10185 23:10:51.993448 <6>[ 0.127527] CPU features: detected: Privileged Access Never
10186 23:10:51.999831 <6>[ 0.127529] CPU features: detected: RAS Extension Support
10187 23:10:52.006514 <6>[ 0.127532] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10188 23:10:52.009614 <6>[ 0.127599] CPU: All CPU(s) started at EL2
10189 23:10:52.039089 � �k�k��,�,Z5��}��չѕ�5R�<6>[ < 0.343780] printk: console [ttyS0] printing thread started
10190 23:10:52.042644 5<6>[ 0.343799] printk: console [ttyS0] enabled
10191 23:10:52.049067 >[ 0.224362] VFS: Disk quotas dquot_6.6.0
10192 23:10:52.055396 <6>[ 0.343803] printk: bootconsole [mtk8250] disabled
10193 23:10:52.062190 <6>[ 0.358230] printk: bootconsole [mtk8250] printing thread stopped
10194 23:10:52.065609 <6>[ 0.359584] SuperH (H)SCI(F) driver initialized
10195 23:10:52.072164 <6>[ 0.360068] msm_serial: driver initialized
10196 23:10:52.078651 <6>[ 0.364692] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10197 23:10:52.088887 <6>[ 0.364721] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10198 23:10:52.095575 <6>[ 0.364750] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10199 23:10:52.104779 <6>[ 0.364780] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10200 23:10:52.114836 <6>[ 0.364801] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10201 23:10:52.126892 <6>[ 0.364829] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10202 23:10:52.141532 <6>[ 0.364858] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10203 23:10:52.147050 <6>[ 0.364977] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10204 23:10:52.153703 <6>[ 0.365006] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10205 23:10:52.156903 <6>[ 0.375243] loop: module loaded
10206 23:10:52.161538 <6>[ 0.377790] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10207 23:10:52.164825 <4>[ 0.394618] mtk-pmic-keys: Failed to locate of_node [id: -1]
10208 23:10:52.168290 <6>[ 0.395532] megasas: 07.719.03.00-rc1
10209 23:10:52.174788 <6>[ 0.407668] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10210 23:10:52.177640 <6>[ 0.407757] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10211 23:10:52.184630 <6>[ 0.419753] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10212 23:10:52.197285 <6>[ 0.473270] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10213 23:10:53.526742 <6>[ 1.831353] Freeing initrd memory: 38448K
10214 23:10:53.534552 <6>[ 1.837563] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10215 23:10:53.541308 <6>[ 1.842400] tun: Universal TUN/TAP device driver, 1.6
10216 23:10:53.544796 <6>[ 1.843181] thunder_xcv, ver 1.0
10217 23:10:53.547840 <6>[ 1.843199] thunder_bgx, ver 1.0
10218 23:10:53.551254 <6>[ 1.843216] nicpf, ver 1.0
10219 23:10:53.557577 <6>[ 1.844293] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10220 23:10:53.564162 <6>[ 1.844296] hns3: Copyright (c) 2017 Huawei Corporation.
10221 23:10:53.567594 <6>[ 1.844321] hclge is initializing
10222 23:10:53.573981 <6>[ 1.844336] e1000: Intel(R) PRO/1000 Network Driver
10223 23:10:53.577480 <6>[ 1.844338] e1000: Copyright (c) 1999-2006 Intel Corporation.
10224 23:10:53.584656 <6>[ 1.844357] e1000e: Intel(R) PRO/1000 Network Driver
10225 23:10:53.592087 <6>[ 1.844358] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10226 23:10:53.595039 <6>[ 1.844374] igb: Intel(R) Gigabit Ethernet Network Driver
10227 23:10:53.602040 <6>[ 1.844376] igb: Copyright (c) 2007-2014 Intel Corporation.
10228 23:10:53.609331 <6>[ 1.844389] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10229 23:10:53.616212 <6>[ 1.844391] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10230 23:10:53.619601 <6>[ 1.844685] sky2: driver version 1.30
10231 23:10:53.622783 <6>[ 1.845762] VFIO - User Level meta-driver version: 0.3
10232 23:10:53.629089 <6>[ 1.848600] usbcore: registered new interface driver usb-storage
10233 23:10:53.635727 <6>[ 1.848800] usbcore: registered new device driver onboard-usb-hub
10234 23:10:53.642536 <6>[ 1.851610] mt6397-rtc mt6359-rtc: registered as rtc0
10235 23:10:53.649403 <6>[ 1.851762] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-27T23:11:12 UTC (1703718672)
10236 23:10:53.655911 <6>[ 1.852389] i2c_dev: i2c /dev entries driver
10237 23:10:53.662371 <6>[ 1.859614] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10238 23:10:53.668968 <6>[ 1.874590] cpu cpu0: EM: created perf domain
10239 23:10:53.672354 <6>[ 1.874919] cpu cpu4: EM: created perf domain
10240 23:10:53.678868 <6>[ 1.878474] sdhci: Secure Digital Host Controller Interface driver
10241 23:10:53.682117 <6>[ 1.878475] sdhci: Copyright(c) Pierre Ossman
10242 23:10:53.688622 <6>[ 1.878800] Synopsys Designware Multimedia Card Interface Driver
10243 23:10:53.695604 <6>[ 1.879161] sdhci-pltfm: SDHCI platform and OF driver helper
10244 23:10:53.701703 <6>[ 1.883460] ledtrig-cpu: registered to indicate activity on CPUs
10245 23:10:53.705432 <6>[ 1.884205] mmc0: CQHCI version 5.10
10246 23:10:53.712158 <6>[ 1.884231] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10247 23:10:53.718832 <6>[ 1.884510] usbcore: registered new interface driver usbhid
10248 23:10:53.721631 <6>[ 1.884512] usbhid: USB HID core driver
10249 23:10:53.728515 <6>[ 1.884626] spi_master spi0: will run message pump with realtime priority
10250 23:10:53.741212 <6>[ 1.916971] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10251 23:10:53.754855 <6>[ 1.919376] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10252 23:10:53.761163 <6>[ 1.920330] cros-ec-spi spi0.0: Chrome EC device registered
10253 23:10:53.771274 <6>[ 1.932324] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10254 23:10:53.774700 <6>[ 1.933236] NET: Registered PF_PACKET protocol family
10255 23:10:53.781320 <6>[ 1.933343] 9pnet: Installing 9P2000 support
10256 23:10:53.784653 <5>[ 1.933389] Key type dns_resolver registered
10257 23:10:53.787579 <6>[ 1.933749] registered taskstats version 1
10258 23:10:53.794371 <5>[ 1.933766] Loading compiled-in X.509 certificates
10259 23:10:53.804289 <4>[ 1.949702] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10260 23:10:53.814264 <4>[ 1.949895] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10261 23:10:53.820769 <3>[ 1.949907] debugfs: File 'uA_load' in directory '/' already present!
10262 23:10:53.827338 <3>[ 1.949915] debugfs: File 'min_uV' in directory '/' already present!
10263 23:10:53.834138 <3>[ 1.949919] debugfs: File 'max_uV' in directory '/' already present!
10264 23:10:53.844335 <3>[ 1.949923] debugfs: File 'constraint_flags' in directory '/' already present!
10265 23:10:53.850595 <3>[ 1.952229] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10266 23:10:53.857458 <6>[ 1.964459] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10267 23:10:53.863978 <6>[ 1.965221] xhci-mtk 11200000.usb: xHCI Host Controller
10268 23:10:53.870593 <6>[ 1.965252] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10269 23:10:53.880291 <6>[ 1.965497] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10270 23:10:53.886927 <6>[ 1.965562] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10271 23:10:53.890282 <6>[ 1.965714] xhci-mtk 11200000.usb: xHCI Host Controller
10272 23:10:53.900685 <6>[ 1.965728] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10273 23:10:53.906864 <6>[ 1.965741] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10274 23:10:53.909873 <6>[ 1.966382] hub 1-0:1.0: USB hub found
10275 23:10:53.913560 <6>[ 1.966414] hub 1-0:1.0: 1 port detected
10276 23:10:53.923751 <6>[ 1.966810] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10277 23:10:53.926834 <6>[ 1.967106] hub 2-0:1.0: USB hub found
10278 23:10:53.929950 <6>[ 1.967119] hub 2-0:1.0: 1 port detected
10279 23:10:53.936411 <6>[ 1.970132] mtk-msdc 11f70000.mmc: Got CD GPIO
10280 23:10:53.940030 <6>[ 1.978329] mmc0: Command Queue Engine enabled
10281 23:10:53.946661 <6>[ 1.978342] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10282 23:10:53.953242 <6>[ 1.978861] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10283 23:10:53.956249 <6>[ 1.982130] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10284 23:10:53.963224 <6>[ 1.983104] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10285 23:10:53.966371 <6>[ 1.983811] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10286 23:10:53.972811 <6>[ 1.984710] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10287 23:10:53.982815 <6>[ 1.985219] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10288 23:10:53.989625 <6>[ 1.985225] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10289 23:10:53.999600 <4>[ 1.985377] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10290 23:10:54.005846 <6>[ 1.986007] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10291 23:10:54.015832 <6>[ 1.986010] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10292 23:10:54.022774 <6>[ 1.986124] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10293 23:10:54.032213 <6>[ 1.986134] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10294 23:10:54.038885 <6>[ 1.986139] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10295 23:10:54.048634 <6>[ 1.986144] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10296 23:10:54.055324 <6>[ 1.987693] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10297 23:10:54.065440 <6>[ 1.987712] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10298 23:10:54.071991 <6>[ 1.987718] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10299 23:10:54.081964 <6>[ 1.987725] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10300 23:10:54.088645 <6>[ 1.987731] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10301 23:10:54.098449 <6>[ 1.987737] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10302 23:10:54.105321 <6>[ 1.987744] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10303 23:10:54.115563 <6>[ 1.987750] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10304 23:10:54.121874 <6>[ 1.987757] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10305 23:10:54.131333 <6>[ 1.987763] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10306 23:10:54.138002 <6>[ 1.987769] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10307 23:10:54.148066 <6>[ 1.987775] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10308 23:10:54.154349 <6>[ 1.987781] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10309 23:10:54.164843 <6>[ 1.987788] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10310 23:10:54.174238 <6>[ 1.987794] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10311 23:10:54.181060 <6>[ 1.988358] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10312 23:10:54.184308 <6>[ 1.989301] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10313 23:10:54.190848 <6>[ 1.989848] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10314 23:10:54.197755 <6>[ 1.990460] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10315 23:10:54.204113 <6>[ 1.991093] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10316 23:10:54.214140 <6>[ 1.991284] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10317 23:10:54.223766 <6>[ 1.991299] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10318 23:10:54.233561 <6>[ 1.991304] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10319 23:10:54.243824 <6>[ 1.991309] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10320 23:10:54.253446 <6>[ 1.991315] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10321 23:10:54.260199 <6>[ 1.991320] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10322 23:10:54.270733 <6>[ 1.991325] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10323 23:10:54.280209 <6>[ 1.991330] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10324 23:10:54.289962 <6>[ 1.991335] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10325 23:10:54.299813 <6>[ 1.991341] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10326 23:10:54.309954 <6>[ 1.991346] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10327 23:10:54.316259 <6>[ 1.991956] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10328 23:10:54.323112 <6>[ 2.396426] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10329 23:10:54.329654 <6>[ 2.551995] hub 1-1:1.0: USB hub found
10330 23:10:54.332798 <6>[ 2.552217] hub 1-1:1.0: 4 ports detected
10331 23:10:54.336408 <6>[ 2.555029] hub 1-1:1.0: USB hub found
10332 23:10:54.339315 <6>[ 2.555290] hub 1-1:1.0: 4 ports detected
10333 23:10:54.377959 <6>[ 2.676589] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10334 23:10:54.398821 <6>[ 2.700595] hub 2-1:1.0: USB hub found
10335 23:10:54.401788 <6>[ 2.700943] hub 2-1:1.0: 3 ports detected
10336 23:10:54.405442 <6>[ 2.703580] hub 2-1:1.0: USB hub found
10337 23:10:54.408550 <6>[ 2.703897] hub 2-1:1.0: 3 ports detected
10338 23:10:54.570097 <6>[ 2.868527] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10339 23:10:54.694807 <6>[ 2.996361] hub 1-1.4:1.0: USB hub found
10340 23:10:54.698088 <6>[ 2.996811] hub 1-1.4:1.0: 2 ports detected
10341 23:10:54.701535 <6>[ 3.000135] hub 1-1.4:1.0: USB hub found
10342 23:10:54.707938 <6>[ 3.000571] hub 1-1.4:1.0: 2 ports detected
10343 23:10:54.774369 <6>[ 3.072741] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10344 23:10:54.989882 <6>[ 3.288525] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10345 23:10:55.174055 <6>[ 3.472531] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10346 23:11:05.998217 <6>[ 14.305590] ALSA device list:
10347 23:11:06.004951 <6>[ 14.305612] No soundcards found.
10348 23:11:06.008244 <6>[ 14.309893] Freeing unused kernel memory: 8448K
10349 23:11:06.011461 <6>[ 14.310103] Run /init as init process
10350 23:11:06.045575 <6>[ 14.351995] NET: Registered PF_INET6 protocol family
10351 23:11:06.048794 <6>[ 14.353202] Segment Routing with IPv6
10352 23:11:06.055382 <6>[ 14.353220] In-situ OAM (IOAM) with IPv6
10353 23:11:06.064521
10354 23:11:06.087745 Welcome to [1mDebian GNU/Linu<30>[ 14.373661] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10355 23:11:06.094252 <30>[ 14.374342] systemd[1]: Detected architecture arm64.
10356 23:11:06.097513 x 11 (bullseye)[0m!
10357 23:11:06.098088
10358 23:11:06.113455 <30>[ 14.416534] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10359 23:11:06.233382 <30>[ 14.532863] systemd[1]: Queued start job for default target Graphical Interface.
10360 23:11:06.258065 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 14.561380] systemd[1]: Created slice system-getty.slice.
10361 23:11:06.261328 m-getty.slice[0m.
10362 23:11:06.284967 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 14.585076] systemd[1]: Created slice system-modprobe.slice.
10363 23:11:06.285551 m-modprobe.slice[0m.
10364 23:11:06.308967 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 14.609220] systemd[1]: Created slice system-serial\x2dgetty.slice.
10365 23:11:06.312310 m-serial\x2dgetty.slice[0m.
10366 23:11:06.331125 [[0;32m OK [0m] Created slic<30>[ 14.634247] systemd[1]: Created slice User and Session Slice.
10367 23:11:06.334226 e [0;1;39mUser and Session Slice[0m.
10368 23:11:06.357207 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 14.657172] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10369 23:11:06.360513 ssword …ts to Console Directory Watch[0m.
10370 23:11:06.384990 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 14.685112] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10371 23:11:06.388500 sword R…uests to Wall Directory Watch[0m.
10372 23:11:06.416419 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 14.712946] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10373 23:11:06.426694 l Encrypted Volu<30>[ 14.713165] systemd[1]: Reached target Local Encrypted Volumes.
10374 23:11:06.427287 mes[0m.
10375 23:11:06.445583 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 14.748999] systemd[1]: Reached target Paths.
10376 23:11:06.446178 s[0m.
10377 23:11:06.468745 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 14.768525] systemd[1]: Reached target Remote File Systems.
10378 23:11:06.469339 te File Systems[0m.
10379 23:11:06.484795 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 14.788505] systemd[1]: Reached target Slices.
10380 23:11:06.485361 es[0m.
10381 23:11:06.505120 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 14.808542] systemd[1]: Reached target Swap.
10382 23:11:06.505712 [0m.
10383 23:11:06.528671 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 14.829013] systemd[1]: Listening on initctl Compatibility Named Pipe.
10384 23:11:06.532108 l Compatibility Named Pipe[0m.
10385 23:11:06.539043 [[0;32m OK [<30>[ 14.844107] systemd[1]: Listening on Journal Audit Socket.
10386 23:11:06.545276 0m] Listening on [0;1;39mJournal Audit Socket[0m.
10387 23:11:06.562379 [[0;32m OK [0m] Listening on<30>[ 14.865663] systemd[1]: Listening on Journal Socket (/dev/log).
10388 23:11:06.565502 [0;1;39mJournal Socket (/dev/log)[0m.
10389 23:11:06.585409 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 14.889047] systemd[1]: Listening on Journal Socket.
10390 23:11:06.588863 l Socket[0m.
10391 23:11:06.608877 [[0;32m OK [0m] Listening on [0;1;39mNetwor<30>[ 14.909201] systemd[1]: Listening on Network Service Netlink Socket.
10392 23:11:06.612390 k Service Netlink Socket[0m.
10393 23:11:06.632512 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 14.933049] systemd[1]: Listening on udev Control Socket.
10394 23:11:06.633125 ontrol Socket[0m.
10395 23:11:06.654167 [[0;32m OK [0m] Listening on<30>[ 14.957564] systemd[1]: Listening on udev Kernel Socket.
10396 23:11:06.657428 [0;1;39mudev Kernel Socket[0m.
10397 23:11:06.704800 Mounting [0;1;39mHuge Pages File Syste<30>[ 15.004607] systemd[1]: Mounting Huge Pages File System...
10398 23:11:06.705384 m[0m...
10399 23:11:06.728126 Mounting [0;1;39mPOSIX Message Queue F<30>[ 15.028380] systemd[1]: Mounting POSIX Message Queue File System...
10400 23:11:06.728704 ile System[0m...
10401 23:11:06.756123 Mounting [0;1;39mKernel Debug File Sys<30>[ 15.056411] systemd[1]: Mounting Kernel Debug File System...
10402 23:11:06.756744 tem[0m...
10403 23:11:06.776389 <30>[ 15.076976] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10404 23:11:06.786716 <30>[ 15.081325] systemd[1]: Starting Create list of static device nodes for the current kernel...
10405 23:11:06.792922 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10406 23:11:06.816751 Startin<30>[ 15.120100] systemd[1]: Starting Load Kernel Module configfs...
10407 23:11:06.819630 g [0;1;39mLoad Kernel Module configfs[0m...
10408 23:11:06.844409 Starting [0;1;39mLoad Kernel Module dr<30>[ 15.144815] systemd[1]: Starting Load Kernel Module drm...
10409 23:11:06.845037 m[0m...
10410 23:11:06.864634 <30>[ 15.164826] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10411 23:11:06.877110 Starting [0;1;39mJournal Service[0m..<30>[ 15.180920] systemd[1]: Starting Journal Service...
10412 23:11:06.877678 .
10413 23:11:06.899649 Startin<30>[ 15.203071] systemd[1]: Starting Load Kernel Modules...
10414 23:11:06.902645 g [0;1;39mLoad Kernel Modules[0m...
10415 23:11:06.926542 Starting [0;1;39mRemou<30>[ 15.230013] systemd[1]: Starting Remount Root and Kernel File Systems...
10416 23:11:06.930421 nt Root and Kernel File Systems[0m...
10417 23:11:06.998780 Starting [0;1;39mColdp<30>[ 15.301959] systemd[1]: Starting Coldplug All udev Devices...
10418 23:11:07.002096 lug All udev Devices[0m...
10419 23:11:07.020640 [[0;32m OK [<30>[ 15.327348] systemd[1]: Started Journal Service.
10420 23:11:07.027075 0m] Started [0;1;39mJournal Service[0m.
10421 23:11:07.043554 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10422 23:11:07.058457 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10423 23:11:07.074425 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10424 23:11:07.094680 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10425 23:11:07.116976 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10426 23:11:07.140574 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10427 23:11:07.163939 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10428 23:11:07.183964 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10429 23:11:07.198058 See 'systemctl status systemd-remount-fs.service' for details.
10430 23:11:07.257284 Mounting [0;1;39mKernel Configuration File System[0m...
10431 23:11:07.278524 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10432 23:11:07.305777 Starting [0;1;39mLoad/<46>[ 15.605431] systemd-journald[189]: Received client request to flush runtime journal.
10433 23:11:07.306363 Save Random Seed[0m...
10434 23:11:07.363525 Starting [0;1;39mApply Kernel Variables[0m...
10435 23:11:07.382233 Starting [0;1;39mCreate System Users[0m...
10436 23:11:07.400788 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10437 23:11:07.418969 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10438 23:11:07.442280 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10439 23:11:07.459569 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10440 23:11:07.475454 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10441 23:11:07.491413 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10442 23:11:07.530033 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10443 23:11:07.557364 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10444 23:11:07.574017 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10445 23:11:07.589284 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10446 23:11:07.642685 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10447 23:11:07.665516 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10448 23:11:07.682953 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10449 23:11:07.702202 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10450 23:11:07.767637 Starting [0;1;39mNetwork Service[0m...
10451 23:11:07.792597 Starting [0;1;39mNetwork Time Synchronization[0m...
10452 23:11:07.817848 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10453 23:11:07.832662 <6>[ 16.135090] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10454 23:11:07.839239 <6>[ 16.135169] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10455 23:11:07.850658 <6>[ 16.135180] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10456 23:11:07.857380 <6>[ 16.135222] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10457 23:11:07.863695 <6>[ 16.142433] remoteproc remoteproc0: scp is available
10458 23:11:07.870305 [[0;32m OK [<6>[ 16.143226] remoteproc remoteproc0: powering up scp
10459 23:11:07.880528 0m] Started [0;<6>[ 16.143236] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10460 23:11:07.886645 1;39mNetwork Ser<6>[ 16.143271] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10461 23:11:07.890220 vice[0m.
10462 23:11:07.896832 <3>[ 16.181753] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10463 23:11:07.903570 <3>[ 16.181765] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10464 23:11:07.913417 <3>[ 16.181769] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10465 23:11:07.920219 <3>[ 16.201121] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10466 23:11:07.930000 <3>[ 16.201142] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10467 23:11:07.936363 <3>[ 16.201150] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10468 23:11:07.946345 [[0;32m OK [<3>[ 16.201159] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10469 23:11:07.956625 0m] Finished [0<3>[ 16.201168] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10470 23:11:07.966438 ;1;39mUpdate UTM<4>[ 16.201922] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10471 23:11:07.972679 P about System B<4>[ 16.202100] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10472 23:11:07.982826 oot/Shutdown[0m<3>[ 16.222096] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10473 23:11:07.983413 .
10474 23:11:07.992579 <3>[ 16.236988] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10475 23:11:07.999373 <3>[ 16.237003] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10476 23:11:08.008936 <3>[ 16.237012] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10477 23:11:08.015883 <3>[ 16.238406] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10478 23:11:08.025619 <3>[ 16.238422] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10479 23:11:08.032353 <3>[ 16.238429] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10480 23:11:08.041921 [[0;32m OK [<3>[ 16.238438] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10481 23:11:08.052407 0m] Found device<3>[ 16.238448] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10482 23:11:08.062340 [0;1;39m/dev/t<3>[ 16.238493] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10483 23:11:08.062906 tyS0[0m.
10484 23:11:08.071905 <6>[ 16.268802] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10485 23:11:08.078212 <6>[ 16.268815] remoteproc remoteproc0: remote processor scp is now up
10486 23:11:08.084903 <6>[ 16.268814] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10487 23:11:08.091640 <6>[ 16.305948] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10488 23:11:08.098294 <6>[ 16.305965] pci_bus 0000:00: root bus resource [bus 00-ff]
10489 23:11:08.104802 <6>[ 16.305971] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10490 23:11:08.114713 <6>[ 16.305977] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10491 23:11:08.121334 <6>[ 16.306016] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10492 23:11:08.127951 <6>[ 16.306037] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10493 23:11:08.134703 [[0;32m OK [<6>[ 16.306122] pci 0000:00:00.0: supports D1 D2
10494 23:11:08.141079 0m] Started [0;<6>[ 16.306125] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10495 23:11:08.150943 1;39mNetwork Tim<6>[ 16.307730] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10496 23:11:08.158242 e Synchronizatio<6>[ 16.307846] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10497 23:11:08.168263 <6>[ 16.307877] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10498 23:11:08.175081 <6>[ 16.307897] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10499 23:11:08.181653 <6>[ 16.307915] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10500 23:11:08.185283 <6>[ 16.308028] pci 0000:01:00.0: supports D1 D2
10501 23:11:08.192572 <6>[ 16.308031] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10502 23:11:08.199444 <6>[ 16.319250] mc: Linux media interface: v0.10
10503 23:11:08.206028 <6>[ 16.319297] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10504 23:11:08.209370 n[0m.
10505 23:11:08.216137 <6>[ 16.330222] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10506 23:11:08.222447 <6>[ 16.330260] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10507 23:11:08.232571 <6>[ 16.330263] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10508 23:11:08.239364 <6>[ 16.330273] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10509 23:11:08.246580 <6>[ 16.330286] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10510 23:11:08.253447 <6>[ 16.330299] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10511 23:11:08.260406 <6>[ 16.330310] pci 0000:00:00.0: PCI bridge to [bus 01]
10512 23:11:08.267436 <6>[ 16.330315] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10513 23:11:08.274067 <6>[ 16.338305] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10514 23:11:08.281007 <6>[ 16.347504] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10515 23:11:08.291101 [[0;32m OK [0m] Created slic<6>[ 16.365256] videodev: Linux video capture interface: v2.00
10516 23:11:08.297771 e [0;1;39msyste<6>[ 16.376849] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10517 23:11:08.304754 m-systemd\x2dbac<6>[ 16.377799] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10518 23:11:08.311523 klight.slice[0m<6>[ 16.383479] usbcore: registered new interface driver r8152
10519 23:11:08.312151 .
10520 23:11:08.321634 <6>[ 16.387365] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10521 23:11:08.332566 <6>[ 16.390138] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10522 23:11:08.339078 <6>[ 16.418097] usbcore: registered new interface driver cdc_ether
10523 23:11:08.345936 <6>[ 16.449655] usbcore: registered new interface driver r8153_ecm
10524 23:11:08.352442 <4>[ 16.455154] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10525 23:11:08.359259 <4>[ 16.455154] Fallback method does not support PEC.
10526 23:11:08.362586 <6>[ 16.455878] Bluetooth: Core ver 2.22
10527 23:11:08.366415 <6>[ 16.456689] NET: Registered PF_BLUETOOTH protocol family
10528 23:11:08.372965 <6>[ 16.456695] Bluetooth: HCI device and connection manager initialized
10529 23:11:08.380039 <6>[ 16.456748] Bluetooth: HCI socket layer initialized
10530 23:11:08.383103 <6>[ 16.456765] Bluetooth: L2CAP socket layer initialized
10531 23:11:08.390344 [[0;32m OK [<6>[ 16.456814] Bluetooth: SCO socket layer initialized
10532 23:11:08.400178 <3>[ 16.472998] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10533 23:11:08.407120 0m] Reached targ<6>[ 16.476096] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10534 23:11:08.417641 et [0;1;39mBlue<6>[ 16.480698] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10535 23:11:08.418199 tooth[0m.
10536 23:11:08.430921 <6>[ 16.497218] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10537 23:11:08.437586 <6>[ 16.507984] usbcore: registered new interface driver uvcvideo
10538 23:11:08.444790 <3>[ 16.510314] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10539 23:11:08.454735 <4>[ 16.520453] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10540 23:11:08.461421 <4>[ 16.520466] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10541 23:11:08.470960 <3>[ 16.527442] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10542 23:11:08.477737 <5>[ 16.542742] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10543 23:11:08.487784 <6>[ 16.550478] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10544 23:11:08.491056 <6>[ 16.554227] usbcore: registered new interface driver btusb
10545 23:11:08.500763 <4>[ 16.557538] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10546 23:11:08.507643 <3>[ 16.557563] Bluetooth: hci0: Failed to load firmware file (-2)
10547 23:11:08.513778 <3>[ 16.557567] Bluetooth: hci0: Failed to set up firmware (-2)
10548 23:11:08.523886 <4>[ 16.557571] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10549 23:11:08.530306 <6>[ 16.558625] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10550 23:11:08.540184 <6>[ 16.560485] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10551 23:11:08.547284 <3>[ 16.562847] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10552 23:11:08.556939 <3>[ 16.563649] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10553 23:11:08.563716 <5>[ 16.568220] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10554 23:11:08.573641 <4>[ 16.568346] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10555 23:11:08.577022 <6>[ 16.568357] cfg80211: failed to load regulatory.db
10556 23:11:08.586765 <3>[ 16.580119] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10557 23:11:08.589894 <6>[ 16.588394] r8152 2-1.3:1.0 eth0: v1.12.13
10558 23:11:08.596531 <6>[ 16.599540] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10559 23:11:08.606603 <3>[ 16.601263] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10560 23:11:08.613147 <3>[ 16.620935] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10561 23:11:08.623286 <3>[ 16.640756] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10562 23:11:08.629375 <6>[ 16.651708] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10563 23:11:08.636117 <6>[ 16.651798] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10564 23:11:08.646476 <3>[ 16.660408] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10565 23:11:08.652897 <6>[ 16.668349] mt7921e 0000:01:00.0: ASIC revision: 79610010
10566 23:11:08.659328 <6>[ 16.762618] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10567 23:11:08.662914 <6>[ 16.762618]
10568 23:11:08.665810 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10569 23:11:08.685914 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10570 23:11:08.704965 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10571 23:11:08.720355 <6>[ 17.022597] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10572 23:11:08.754166 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10573 23:11:08.777219 Starting [0;1;39mNetwork Name Resolution[0m...
10574 23:11:08.800073 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10575 23:11:08.830835 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10576 23:11:08.845876 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10577 23:11:08.869086 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10578 23:11:08.881419 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10579 23:11:08.901188 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10580 23:11:08.916540 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10581 23:11:08.929693 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10582 23:11:08.949244 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10583 23:11:08.961535 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10584 23:11:08.977351 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10585 23:11:09.026296 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10586 23:11:09.061379 Starting [0;1;39mUser Login Management[0m...
10587 23:11:09.082253 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10588 23:11:09.106010 Starting [0;1;39mPermit User Sessions[0m...
10589 23:11:09.122496 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10590 23:11:09.140182 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10591 23:11:09.198176 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10592 23:11:09.218283 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10593 23:11:09.233806 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10594 23:11:09.250426 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10595 23:11:09.267229 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10596 23:11:09.281868 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10597 23:11:09.326147 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10598 23:11:09.359133 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10599 23:11:09.401407
10600 23:11:09.401967
10601 23:11:09.404785 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10602 23:11:09.405350
10603 23:11:09.407970 debian-bullseye-arm64 login: root (automatic login)
10604 23:11:09.408626
10605 23:11:09.409058
10606 23:11:09.425225 Linux debian-bullseye-arm64 6.1.67-cip12-rt7 #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023 aarch64
10607 23:11:09.425795
10608 23:11:09.431803 The programs included with the Debian GNU/Linux system are free software;
10609 23:11:09.438306 the exact distribution terms for each program are described in the
10610 23:11:09.441632 individual files in /usr/share/doc/*/copyright.
10611 23:11:09.442207
10612 23:11:09.448575 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10613 23:11:09.451570 permitted by applicable law.
10614 23:11:09.453111 Matched prompt #10: / #
10616 23:11:09.454329 Setting prompt string to ['/ #']
10617 23:11:09.454808 end: 2.2.5.1 login-action (duration 00:00:18) [common]
10619 23:11:09.455898 end: 2.2.5 auto-login-action (duration 00:00:18) [common]
10620 23:11:09.456385 start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
10621 23:11:09.456827 Setting prompt string to ['/ #']
10622 23:11:09.457182 Forcing a shell prompt, looking for ['/ #']
10624 23:11:09.508123 / #
10625 23:11:09.509055 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10626 23:11:09.509530 Waiting using forced prompt support (timeout 00:02:30)
10627 23:11:09.514536
10628 23:11:09.515492 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10629 23:11:09.516037 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
10630 23:11:09.516532 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10631 23:11:09.517080 end: 2.2 depthcharge-retry (duration 00:01:25) [common]
10632 23:11:09.517546 end: 2 depthcharge-action (duration 00:01:25) [common]
10633 23:11:09.518046 start: 3 lava-test-retry (timeout 00:08:16) [common]
10634 23:11:09.518528 start: 3.1 lava-test-shell (timeout 00:08:16) [common]
10635 23:11:09.518937 Using namespace: common
10637 23:11:09.620241 / # #
10638 23:11:09.620947 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10639 23:11:09.621567 <6>[ 17.863791] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10640 23:11:09.627217 #
10641 23:11:09.628108 Using /lava-12395386
10643 23:11:09.729473 / # export SHELL=/bin/sh
10644 23:11:09.735951 export SHELL=/bin/sh
10646 23:11:09.837627 / # . /lava-12395386/environment
10647 23:11:09.844089 . /lava-12395386/environment
10649 23:11:09.945880 / # /lava-12395386/bin/lava-test-runner /lava-12395386/0
10650 23:11:09.946519 Test shell timeout: 10s (minimum of the action and connection timeout)
10651 23:11:09.952626 /lava-12395386/bin/lava-test-runner /lava-12395386/0
10652 23:11:09.975122 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
10653 23:11:09.981907 + cd /lava-12395386/0/tests/0_v4l2-compliance-mtk-vcodec-enc
10654 23:11:09.982375 + cat uuid
10655 23:11:09.985060 + UUID=12395386_1.5.2.3.1
10656 23:11:09.985520 + set +x
10657 23:11:09.991959 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 12395386_1.5.2.3.1>
10658 23:11:09.992862 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 12395386_1.5.2.3.1
10659 23:11:09.993277 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (12395386_1.5.2.3.1)
10660 23:11:09.993728 Skipping test definition patterns.
10661 23:11:09.994854 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
10662 23:11:10.001566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
10663 23:11:10.002049 device: /dev/video2
10664 23:11:10.002680 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
10666 23:11:10.012201 <4>[ 18.314730] use of bytesused == 0 is deprecated and will be removed in the future,
10667 23:11:10.015547 <4>[ 18.314740] use the actual size instead.
10668 23:11:10.029590 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
10669 23:11:10.039207 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
10670 23:11:10.044266
10671 23:11:10.057978 Compliance test for mtk-vcodec-enc device /dev/video2:
10672 23:11:10.068353 <6>[ 18.371055] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c6803bd: link becomes ready
10673 23:11:10.071652 <6>[ 18.371484] r8152 2-1.3:1.0 enx00e04c6803bd: carrier on
10674 23:11:10.074448
10675 23:11:10.085692 Driver Info:
10676 23:11:10.095778 Driver name : mtk-vcodec-enc
10677 23:11:10.109232 Card type : MT8192 video encoder
10678 23:11:10.118848 Bus info : platform:17020000.vcodec
10679 23:11:10.125867 Driver version : 6.1.67
10680 23:11:10.136546 Capabilities : 0x84204000
10681 23:11:10.147249 Video Memory-to-Memory Multiplanar
10682 23:11:10.158024 Streaming
10683 23:11:10.167895 Extended Pix Format
10684 23:11:10.179630 Device Capabilities
10685 23:11:10.190239 Device Caps : 0x04204000
10686 23:11:10.199416 Video Memory-to-Memory Multiplanar
10687 23:11:10.210426 Streaming
10688 23:11:10.220529 Extended Pix Format
10689 23:11:10.235531 Detected Stateful Encoder
10690 23:11:10.247319
10691 23:11:10.257626 Required ioctls:
10692 23:11:10.275320 <LAVA_SIGNAL_TESTSET START Required-ioctls>
10693 23:11:10.275986 test VIDIOC_QUERYCAP: OK
10694 23:11:10.276765 Received signal: <TESTSET> START Required-ioctls
10695 23:11:10.277257 Starting test_set Required-ioctls
10696 23:11:10.299811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
10697 23:11:10.300629 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
10699 23:11:10.303242 test invalid ioctls: OK
10700 23:11:10.322686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
10701 23:11:10.323249
10702 23:11:10.323894 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
10704 23:11:10.333386 Allow for multiple opens:
10705 23:11:10.341635 <LAVA_SIGNAL_TESTSET STOP>
10706 23:11:10.342469 Received signal: <TESTSET> STOP
10707 23:11:10.342871 Closing test_set Required-ioctls
10708 23:11:10.352108 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
10709 23:11:10.352946 Received signal: <TESTSET> START Allow-for-multiple-opens
10710 23:11:10.353341 Starting test_set Allow-for-multiple-opens
10711 23:11:10.355360 test second /dev/video2 open: OK
10712 23:11:10.375201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
10713 23:11:10.376128 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
10715 23:11:10.378607 test VIDIOC_QUERYCAP: OK
10716 23:11:10.399222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
10717 23:11:10.400068 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
10719 23:11:10.402379 test VIDIOC_G/S_PRIORITY: OK
10720 23:11:10.430020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
10721 23:11:10.430856 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
10723 23:11:10.432852 test for unlimited opens: OK
10724 23:11:10.453558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
10725 23:11:10.454119
10726 23:11:10.454763 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
10728 23:11:10.462870 Debug ioctls:
10729 23:11:10.470155 <LAVA_SIGNAL_TESTSET STOP>
10730 23:11:10.470987 Received signal: <TESTSET> STOP
10731 23:11:10.471372 Closing test_set Allow-for-multiple-opens
10732 23:11:10.479591 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
10733 23:11:10.480317 Received signal: <TESTSET> START Debug-ioctls
10734 23:11:10.480701 Starting test_set Debug-ioctls
10735 23:11:10.482924 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
10736 23:11:10.510594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
10737 23:11:10.511440 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
10739 23:11:10.517097 test VIDIOC_LOG_STATUS: OK (Not Supported)
10740 23:11:10.533038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
10741 23:11:10.533600
10742 23:11:10.534237 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
10744 23:11:10.541336 Input ioctls:
10745 23:11:10.547323 <LAVA_SIGNAL_TESTSET STOP>
10746 23:11:10.548153 Received signal: <TESTSET> STOP
10747 23:11:10.548554 Closing test_set Debug-ioctls
10748 23:11:10.557069 <LAVA_SIGNAL_TESTSET START Input-ioctls>
10749 23:11:10.557909 Received signal: <TESTSET> START Input-ioctls
10750 23:11:10.558294 Starting test_set Input-ioctls
10751 23:11:10.560299 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
10752 23:11:10.583934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
10753 23:11:10.584821 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
10755 23:11:10.587056 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
10756 23:11:10.605030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
10757 23:11:10.605877 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
10759 23:11:10.611378 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
10760 23:11:10.630832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
10761 23:11:10.631670 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
10763 23:11:10.637302 test VIDIOC_ENUMAUDIO: OK (Not Supported)
10764 23:11:10.655418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
10765 23:11:10.656254 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
10767 23:11:10.658742 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
10768 23:11:10.683552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
10769 23:11:10.684389 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
10771 23:11:10.686384 test VIDIOC_G/S_AUDIO: OK (Not Supported)
10772 23:11:10.707980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
10773 23:11:10.708870 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
10775 23:11:10.710954 Inputs: 0 Audio Inputs: 0 Tuners: 0
10776 23:11:10.719532
10777 23:11:10.738449 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
10778 23:11:10.759044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
10779 23:11:10.759908 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
10781 23:11:10.765692 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
10782 23:11:10.787456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
10783 23:11:10.788294 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
10785 23:11:10.793871 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
10786 23:11:10.811123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
10787 23:11:10.811936 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
10789 23:11:10.817889 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
10790 23:11:10.834882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
10791 23:11:10.835684 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
10793 23:11:10.841643 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
10794 23:11:10.865245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
10795 23:11:10.865807
10796 23:11:10.866448 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
10798 23:11:10.883494 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
10799 23:11:10.908135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
10800 23:11:10.908964 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
10802 23:11:10.914806 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
10803 23:11:10.936962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
10804 23:11:10.937804 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
10806 23:11:10.940299 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
10807 23:11:10.957976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
10808 23:11:10.958819 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
10810 23:11:10.961436 test VIDIOC_G/S_EDID: OK (Not Supported)
10811 23:11:10.981621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
10812 23:11:10.982175
10813 23:11:10.982812 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
10815 23:11:10.992533 Control ioctls:
10816 23:11:11.000309 <LAVA_SIGNAL_TESTSET STOP>
10817 23:11:11.001328 Received signal: <TESTSET> STOP
10818 23:11:11.001716 Closing test_set Input-ioctls
10819 23:11:11.011680 <LAVA_SIGNAL_TESTSET START Control-ioctls>
10820 23:11:11.012403 Received signal: <TESTSET> START Control-ioctls
10821 23:11:11.012823 Starting test_set Control-ioctls
10822 23:11:11.014989 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
10823 23:11:11.039411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
10824 23:11:11.039963 test VIDIOC_QUERYCTRL: OK
10825 23:11:11.040642 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
10827 23:11:11.059819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
10828 23:11:11.060625 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
10830 23:11:11.063244 test VIDIOC_G/S_CTRL: OK
10831 23:11:11.083279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
10832 23:11:11.084227 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
10834 23:11:11.086382 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
10835 23:11:11.107246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
10836 23:11:11.108083 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
10838 23:11:11.117127 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
10839 23:11:11.120989 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
10840 23:11:11.146111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
10841 23:11:11.146945 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
10843 23:11:11.149168 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
10844 23:11:11.167561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
10845 23:11:11.168397 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
10847 23:11:11.170895 Standard Controls: 16 Private Controls: 0
10848 23:11:11.176649
10849 23:11:11.187584 Format ioctls:
10850 23:11:11.198099 <LAVA_SIGNAL_TESTSET STOP>
10851 23:11:11.198921 Received signal: <TESTSET> STOP
10852 23:11:11.199303 Closing test_set Control-ioctls
10853 23:11:11.207745 <LAVA_SIGNAL_TESTSET START Format-ioctls>
10854 23:11:11.208576 Received signal: <TESTSET> START Format-ioctls
10855 23:11:11.209001 Starting test_set Format-ioctls
10856 23:11:11.210985 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
10857 23:11:11.234114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
10858 23:11:11.235138 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
10860 23:11:11.237265 test VIDIOC_G/S_PARM: OK
10861 23:11:11.254904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
10862 23:11:11.255735 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
10864 23:11:11.258312 test VIDIOC_G_FBUF: OK (Not Supported)
10865 23:11:11.279121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
10866 23:11:11.279949 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
10868 23:11:11.282518 test VIDIOC_G_FMT: OK
10869 23:11:11.308459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
10870 23:11:11.309354 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
10872 23:11:11.311561 test VIDIOC_TRY_FMT: OK
10873 23:11:11.345643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
10874 23:11:11.346480 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
10876 23:11:11.355553 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
10877 23:11:11.356111 test VIDIOC_S_FMT: FAIL
10878 23:11:11.376196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
10879 23:11:11.377041 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
10881 23:11:11.379320 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
10882 23:11:11.399392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
10883 23:11:11.400244 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
10885 23:11:11.402178 test Cropping: OK
10886 23:11:11.420510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
10887 23:11:11.421382 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
10889 23:11:11.423608 test Composing: OK (Not Supported)
10890 23:11:11.444536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
10891 23:11:11.445434 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
10893 23:11:11.447979 test Scaling: OK (Not Supported)
10894 23:11:11.473415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
10895 23:11:11.473969
10896 23:11:11.474608 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
10898 23:11:11.483522 Codec ioctls:
10899 23:11:11.491179 <LAVA_SIGNAL_TESTSET STOP>
10900 23:11:11.492009 Received signal: <TESTSET> STOP
10901 23:11:11.492407 Closing test_set Format-ioctls
10902 23:11:11.500340 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
10903 23:11:11.501240 Received signal: <TESTSET> START Codec-ioctls
10904 23:11:11.501810 Starting test_set Codec-ioctls
10905 23:11:11.503324 test VIDIOC_(TRY_)ENCODER_CMD: OK
10906 23:11:11.528529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
10907 23:11:11.529409 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
10909 23:11:11.534985 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
10910 23:11:11.552477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
10911 23:11:11.553370 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
10913 23:11:11.558970 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
10914 23:11:11.577798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
10915 23:11:11.578350
10916 23:11:11.579019 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
10918 23:11:11.591050 Buffer ioctls:
10919 23:11:11.598221 <LAVA_SIGNAL_TESTSET STOP>
10920 23:11:11.599051 Received signal: <TESTSET> STOP
10921 23:11:11.599433 Closing test_set Codec-ioctls
10922 23:11:11.607464 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
10923 23:11:11.608279 Received signal: <TESTSET> START Buffer-ioctls
10924 23:11:11.608686 Starting test_set Buffer-ioctls
10925 23:11:11.610687 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
10926 23:11:11.635516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
10927 23:11:11.636124 test VIDIOC_EXPBUF: OK
10928 23:11:11.636816 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
10930 23:11:11.656593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
10931 23:11:11.657469 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
10933 23:11:11.659610 test Requests: OK (Not Supported)
10934 23:11:11.680026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
10935 23:11:11.680568
10936 23:11:11.681235 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
10938 23:11:11.691205 Test input 0:
10939 23:11:11.700530
10940 23:11:11.712641 Streaming ioctls:
10941 23:11:11.720350 <LAVA_SIGNAL_TESTSET STOP>
10942 23:11:11.721233 Received signal: <TESTSET> STOP
10943 23:11:11.721621 Closing test_set Buffer-ioctls
10944 23:11:11.730223 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
10945 23:11:11.731069 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
10946 23:11:11.731461 Starting test_set Streaming-ioctls_Test-input-0
10947 23:11:11.733347 test read/write: OK (Not Supported)
10948 23:11:11.753234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
10949 23:11:11.754066 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
10951 23:11:11.759596 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
10952 23:11:11.771555 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
10953 23:11:11.775214 test blocking wait: FAIL
10954 23:11:11.798997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
10955 23:11:11.799837 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
10957 23:11:11.808455 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
10958 23:11:11.809044 test MMAP (select): FAIL
10959 23:11:11.835755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
10960 23:11:11.836593 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
10962 23:11:11.842050 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
10963 23:11:11.846369 test MMAP (epoll): FAIL
10964 23:11:11.871569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
10965 23:11:11.872536 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
10967 23:11:11.881399 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
10968 23:11:11.888121 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
10969 23:11:11.897389 test USERPTR (select): FAIL
10970 23:11:11.922012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
10971 23:11:11.922849 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
10973 23:11:11.928428 test DMABUF: Cannot test, specify --expbuf-device
10974 23:11:11.929051
10975 23:11:11.951358 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
10976 23:11:11.956110 <LAVA_TEST_RUNNER EXIT>
10977 23:11:11.956939 ok: lava_test_shell seems to have completed
10978 23:11:11.957391 Marking unfinished test run as failed
10980 23:11:11.962690 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
10981 23:11:11.963358 end: 3.1 lava-test-shell (duration 00:00:02) [common]
10982 23:11:11.963844 end: 3 lava-test-retry (duration 00:00:02) [common]
10983 23:11:11.964318 start: 4 finalize (timeout 00:08:13) [common]
10984 23:11:11.964852 start: 4.1 power-off (timeout 00:00:30) [common]
10985 23:11:11.965656 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
10986 23:11:12.051625 >> Command sent successfully.
10987 23:11:12.056110 Returned 0 in 0 seconds
10988 23:11:12.157157 end: 4.1 power-off (duration 00:00:00) [common]
10990 23:11:12.158690 start: 4.2 read-feedback (timeout 00:08:13) [common]
10991 23:11:12.159967 Listened to connection for namespace 'common' for up to 1s
10992 23:11:13.160642 Finalising connection for namespace 'common'
10993 23:11:13.161470 Disconnecting from shell: Finalise
10994 23:11:13.161904 / #
10995 23:11:13.263048 end: 4.2 read-feedback (duration 00:00:01) [common]
10996 23:11:13.263809 end: 4 finalize (duration 00:00:01) [common]
10997 23:11:13.264449 Cleaning after the job
10998 23:11:13.265020 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395386/tftp-deploy-_crc1ad_/ramdisk
10999 23:11:13.292337 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395386/tftp-deploy-_crc1ad_/kernel
11000 23:11:13.312243 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395386/tftp-deploy-_crc1ad_/dtb
11001 23:11:13.312530 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395386/tftp-deploy-_crc1ad_/modules
11002 23:11:13.322826 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12395386
11003 23:11:13.391287 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12395386
11004 23:11:13.391464 Job finished correctly