Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 13
- Kernel Errors: 27
- Errors: 1
1 23:05:49.513909 lava-dispatcher, installed at version: 2023.10
2 23:05:49.514114 start: 0 validate
3 23:05:49.514247 Start time: 2023-12-27 23:05:49.514232+00:00 (UTC)
4 23:05:49.514362 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:05:49.514494 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 23:05:49.808214 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:05:49.808380 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:05:50.059005 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:05:50.059812 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:06:16.881132 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:06:16.881872 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.66-cip11-rt6-10-g38253b8903b4%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:06:17.408741 validate duration: 27.89
14 23:06:17.410077 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:06:17.410604 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:06:17.411085 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:06:17.411758 Not decompressing ramdisk as can be used compressed.
18 23:06:17.412247 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 23:06:17.412616 saving as /var/lib/lava/dispatcher/tmp/12395342/tftp-deploy-964i7d0v/ramdisk/rootfs.cpio.gz
20 23:06:17.412968 total size: 26246609 (25 MB)
21 23:06:20.562162 progress 0 % (0 MB)
22 23:06:20.570907 progress 5 % (1 MB)
23 23:06:20.580254 progress 10 % (2 MB)
24 23:06:20.589576 progress 15 % (3 MB)
25 23:06:20.598415 progress 20 % (5 MB)
26 23:06:20.605947 progress 25 % (6 MB)
27 23:06:20.612873 progress 30 % (7 MB)
28 23:06:20.619914 progress 35 % (8 MB)
29 23:06:20.626783 progress 40 % (10 MB)
30 23:06:20.633708 progress 45 % (11 MB)
31 23:06:20.640726 progress 50 % (12 MB)
32 23:06:20.647454 progress 55 % (13 MB)
33 23:06:20.654141 progress 60 % (15 MB)
34 23:06:20.660918 progress 65 % (16 MB)
35 23:06:20.667661 progress 70 % (17 MB)
36 23:06:20.674539 progress 75 % (18 MB)
37 23:06:20.681430 progress 80 % (20 MB)
38 23:06:20.688099 progress 85 % (21 MB)
39 23:06:20.694823 progress 90 % (22 MB)
40 23:06:20.701622 progress 95 % (23 MB)
41 23:06:20.708372 progress 100 % (25 MB)
42 23:06:20.708614 25 MB downloaded in 3.30 s (7.60 MB/s)
43 23:06:20.708763 end: 1.1.1 http-download (duration 00:00:03) [common]
45 23:06:20.708999 end: 1.1 download-retry (duration 00:00:03) [common]
46 23:06:20.709082 start: 1.2 download-retry (timeout 00:09:57) [common]
47 23:06:20.709162 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 23:06:20.709297 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:06:20.709364 saving as /var/lib/lava/dispatcher/tmp/12395342/tftp-deploy-964i7d0v/kernel/Image
50 23:06:20.709421 total size: 50024960 (47 MB)
51 23:06:20.709480 No compression specified
52 23:06:20.710568 progress 0 % (0 MB)
53 23:06:20.723405 progress 5 % (2 MB)
54 23:06:20.736437 progress 10 % (4 MB)
55 23:06:20.749372 progress 15 % (7 MB)
56 23:06:20.762545 progress 20 % (9 MB)
57 23:06:20.775426 progress 25 % (11 MB)
58 23:06:20.788351 progress 30 % (14 MB)
59 23:06:20.801434 progress 35 % (16 MB)
60 23:06:20.814401 progress 40 % (19 MB)
61 23:06:20.827325 progress 45 % (21 MB)
62 23:06:20.840386 progress 50 % (23 MB)
63 23:06:20.853345 progress 55 % (26 MB)
64 23:06:20.866256 progress 60 % (28 MB)
65 23:06:20.906436 progress 65 % (31 MB)
66 23:06:20.919400 progress 70 % (33 MB)
67 23:06:20.932539 progress 75 % (35 MB)
68 23:06:20.945639 progress 80 % (38 MB)
69 23:06:20.958752 progress 85 % (40 MB)
70 23:06:20.971708 progress 90 % (42 MB)
71 23:06:20.984880 progress 95 % (45 MB)
72 23:06:20.997878 progress 100 % (47 MB)
73 23:06:20.998122 47 MB downloaded in 0.29 s (165.25 MB/s)
74 23:06:20.998278 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:06:20.998522 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:06:20.998612 start: 1.3 download-retry (timeout 00:09:56) [common]
78 23:06:20.998699 start: 1.3.1 http-download (timeout 00:09:56) [common]
79 23:06:20.998836 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:06:20.998904 saving as /var/lib/lava/dispatcher/tmp/12395342/tftp-deploy-964i7d0v/dtb/mt8192-asurada-spherion-r0.dtb
81 23:06:20.998964 total size: 47278 (0 MB)
82 23:06:20.999023 No compression specified
83 23:06:21.000219 progress 69 % (0 MB)
84 23:06:21.000524 progress 100 % (0 MB)
85 23:06:21.000710 0 MB downloaded in 0.00 s (25.85 MB/s)
86 23:06:21.000834 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:06:21.001054 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:06:21.001138 start: 1.4 download-retry (timeout 00:09:56) [common]
90 23:06:21.001218 start: 1.4.1 http-download (timeout 00:09:56) [common]
91 23:06:21.001335 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.66-cip11-rt6-10-g38253b8903b4/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:06:21.001402 saving as /var/lib/lava/dispatcher/tmp/12395342/tftp-deploy-964i7d0v/modules/modules.tar
93 23:06:21.001464 total size: 8633892 (8 MB)
94 23:06:21.001525 Using unxz to decompress xz
95 23:06:21.008462 progress 0 % (0 MB)
96 23:06:21.029355 progress 5 % (0 MB)
97 23:06:21.053204 progress 10 % (0 MB)
98 23:06:21.076959 progress 15 % (1 MB)
99 23:06:21.100947 progress 20 % (1 MB)
100 23:06:21.125278 progress 25 % (2 MB)
101 23:06:21.153090 progress 30 % (2 MB)
102 23:06:21.177771 progress 35 % (2 MB)
103 23:06:21.201409 progress 40 % (3 MB)
104 23:06:21.225931 progress 45 % (3 MB)
105 23:06:21.251631 progress 50 % (4 MB)
106 23:06:21.276384 progress 55 % (4 MB)
107 23:06:21.303404 progress 60 % (4 MB)
108 23:06:21.329343 progress 65 % (5 MB)
109 23:06:21.354737 progress 70 % (5 MB)
110 23:06:21.378034 progress 75 % (6 MB)
111 23:06:21.405593 progress 80 % (6 MB)
112 23:06:21.431519 progress 85 % (7 MB)
113 23:06:21.458795 progress 90 % (7 MB)
114 23:06:21.489030 progress 95 % (7 MB)
115 23:06:21.517443 progress 100 % (8 MB)
116 23:06:21.523492 8 MB downloaded in 0.52 s (15.77 MB/s)
117 23:06:21.523856 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:06:21.524241 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:06:21.524370 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 23:06:21.524503 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 23:06:21.524639 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:06:21.524767 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 23:06:21.525065 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7
125 23:06:21.525256 makedir: /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin
126 23:06:21.525405 makedir: /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/tests
127 23:06:21.525548 makedir: /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/results
128 23:06:21.525704 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-add-keys
129 23:06:21.525906 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-add-sources
130 23:06:21.526088 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-background-process-start
131 23:06:21.526266 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-background-process-stop
132 23:06:21.526442 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-common-functions
133 23:06:21.526618 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-echo-ipv4
134 23:06:21.526800 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-install-packages
135 23:06:21.526977 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-installed-packages
136 23:06:21.527157 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-os-build
137 23:06:21.527337 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-probe-channel
138 23:06:21.527525 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-probe-ip
139 23:06:21.527759 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-target-ip
140 23:06:21.527937 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-target-mac
141 23:06:21.528116 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-target-storage
142 23:06:21.528300 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-test-case
143 23:06:21.528479 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-test-event
144 23:06:21.528656 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-test-feedback
145 23:06:21.528836 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-test-raise
146 23:06:21.529013 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-test-reference
147 23:06:21.529195 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-test-runner
148 23:06:21.529371 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-test-set
149 23:06:21.529564 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-test-shell
150 23:06:21.529758 Updating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-install-packages (oe)
151 23:06:21.529978 Updating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/bin/lava-installed-packages (oe)
152 23:06:21.530154 Creating /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/environment
153 23:06:21.530302 LAVA metadata
154 23:06:21.530413 - LAVA_JOB_ID=12395342
155 23:06:21.530510 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:06:21.530652 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 23:06:21.530755 skipped lava-vland-overlay
158 23:06:21.530866 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:06:21.530985 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 23:06:21.531086 skipped lava-multinode-overlay
161 23:06:21.531200 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:06:21.531329 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 23:06:21.531470 Loading test definitions
164 23:06:21.531604 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:56) [common]
165 23:06:21.531762 Using /lava-12395342 at stage 0
166 23:06:21.532206 uuid=12395342_1.5.2.3.1 testdef=None
167 23:06:21.532326 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:06:21.532452 start: 1.5.2.3.2 test-overlay (timeout 00:09:56) [common]
169 23:06:21.533182 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:06:21.533510 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:56) [common]
172 23:06:21.534417 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:06:21.534763 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:56) [common]
175 23:06:21.535609 runner path: /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/0/tests/0_v4l2-compliance-uvc test_uuid 12395342_1.5.2.3.1
176 23:06:21.535853 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:06:21.536179 Creating lava-test-runner.conf files
179 23:06:21.536272 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12395342/lava-overlay-htu07bn7/lava-12395342/0 for stage 0
180 23:06:21.536396 - 0_v4l2-compliance-uvc
181 23:06:21.536536 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:06:21.536658 start: 1.5.2.4 compress-overlay (timeout 00:09:56) [common]
183 23:06:21.546063 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:06:21.546211 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:56) [common]
185 23:06:21.546331 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:06:21.546455 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:06:21.546581 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
188 23:06:22.271336 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 23:06:22.271851 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
190 23:06:22.272019 extracting modules file /var/lib/lava/dispatcher/tmp/12395342/tftp-deploy-964i7d0v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12395342/extract-overlay-ramdisk-pyhywiev/ramdisk
191 23:06:22.520764 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:06:22.520933 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
193 23:06:22.521030 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12395342/compress-overlay-bv27sc6d/overlay-1.5.2.4.tar.gz to ramdisk
194 23:06:22.521101 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12395342/compress-overlay-bv27sc6d/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12395342/extract-overlay-ramdisk-pyhywiev/ramdisk
195 23:06:22.527813 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:06:22.527929 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
197 23:06:22.528021 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:06:22.528115 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
199 23:06:22.528191 Building ramdisk /var/lib/lava/dispatcher/tmp/12395342/extract-overlay-ramdisk-pyhywiev/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12395342/extract-overlay-ramdisk-pyhywiev/ramdisk
200 23:06:23.148109 >> 228450 blocks
201 23:06:27.037523 rename /var/lib/lava/dispatcher/tmp/12395342/extract-overlay-ramdisk-pyhywiev/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12395342/tftp-deploy-964i7d0v/ramdisk/ramdisk.cpio.gz
202 23:06:27.037988 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 23:06:27.038110 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 23:06:27.038225 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 23:06:27.038370 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12395342/tftp-deploy-964i7d0v/kernel/Image'
206 23:06:39.985489 Returned 0 in 12 seconds
207 23:06:40.086166 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12395342/tftp-deploy-964i7d0v/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12395342/tftp-deploy-964i7d0v/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12395342/tftp-deploy-964i7d0v/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12395342/tftp-deploy-964i7d0v/kernel/image.itb
208 23:06:40.718435 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:06:40.718821 output: Created: Wed Dec 27 23:06:40 2023
210 23:06:40.718900 output: Image 0 (kernel-1)
211 23:06:40.718967 output: Description:
212 23:06:40.719032 output: Created: Wed Dec 27 23:06:40 2023
213 23:06:40.719093 output: Type: Kernel Image
214 23:06:40.719156 output: Compression: lzma compressed
215 23:06:40.719216 output: Data Size: 11480388 Bytes = 11211.32 KiB = 10.95 MiB
216 23:06:40.719274 output: Architecture: AArch64
217 23:06:40.719331 output: OS: Linux
218 23:06:40.719385 output: Load Address: 0x00000000
219 23:06:40.719440 output: Entry Point: 0x00000000
220 23:06:40.719494 output: Hash algo: crc32
221 23:06:40.719549 output: Hash value: a55b2f0b
222 23:06:40.719603 output: Image 1 (fdt-1)
223 23:06:40.719657 output: Description: mt8192-asurada-spherion-r0
224 23:06:40.719757 output: Created: Wed Dec 27 23:06:40 2023
225 23:06:40.719811 output: Type: Flat Device Tree
226 23:06:40.719863 output: Compression: uncompressed
227 23:06:40.719916 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 23:06:40.719993 output: Architecture: AArch64
229 23:06:40.720090 output: Hash algo: crc32
230 23:06:40.720142 output: Hash value: cc4352de
231 23:06:40.720195 output: Image 2 (ramdisk-1)
232 23:06:40.720247 output: Description: unavailable
233 23:06:40.720298 output: Created: Wed Dec 27 23:06:40 2023
234 23:06:40.720350 output: Type: RAMDisk Image
235 23:06:40.720402 output: Compression: Unknown Compression
236 23:06:40.720454 output: Data Size: 39372515 Bytes = 38449.72 KiB = 37.55 MiB
237 23:06:40.720506 output: Architecture: AArch64
238 23:06:40.720558 output: OS: Linux
239 23:06:40.720610 output: Load Address: unavailable
240 23:06:40.720661 output: Entry Point: unavailable
241 23:06:40.720713 output: Hash algo: crc32
242 23:06:40.720764 output: Hash value: 6d147790
243 23:06:40.720816 output: Default Configuration: 'conf-1'
244 23:06:40.720867 output: Configuration 0 (conf-1)
245 23:06:40.720919 output: Description: mt8192-asurada-spherion-r0
246 23:06:40.720970 output: Kernel: kernel-1
247 23:06:40.721022 output: Init Ramdisk: ramdisk-1
248 23:06:40.721073 output: FDT: fdt-1
249 23:06:40.721124 output: Loadables: kernel-1
250 23:06:40.721175 output:
251 23:06:40.721369 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 23:06:40.721466 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 23:06:40.721570 end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
254 23:06:40.721666 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 23:06:40.721743 No LXC device requested
256 23:06:40.721821 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:06:40.721904 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 23:06:40.721984 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:06:40.722054 Checking files for TFTP limit of 4294967296 bytes.
260 23:06:40.722558 end: 1 tftp-deploy (duration 00:00:23) [common]
261 23:06:40.722663 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:06:40.722752 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:06:40.722879 substitutions:
264 23:06:40.722944 - {DTB}: 12395342/tftp-deploy-964i7d0v/dtb/mt8192-asurada-spherion-r0.dtb
265 23:06:40.723007 - {INITRD}: 12395342/tftp-deploy-964i7d0v/ramdisk/ramdisk.cpio.gz
266 23:06:40.723065 - {KERNEL}: 12395342/tftp-deploy-964i7d0v/kernel/Image
267 23:06:40.723121 - {LAVA_MAC}: None
268 23:06:40.723175 - {PRESEED_CONFIG}: None
269 23:06:40.723229 - {PRESEED_LOCAL}: None
270 23:06:40.723285 - {RAMDISK}: 12395342/tftp-deploy-964i7d0v/ramdisk/ramdisk.cpio.gz
271 23:06:40.723340 - {ROOT_PART}: None
272 23:06:40.723394 - {ROOT}: None
273 23:06:40.723448 - {SERVER_IP}: 192.168.201.1
274 23:06:40.723500 - {TEE}: None
275 23:06:40.723553 Parsed boot commands:
276 23:06:40.723605 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:06:40.723829 Parsed boot commands: tftpboot 192.168.201.1 12395342/tftp-deploy-964i7d0v/kernel/image.itb 12395342/tftp-deploy-964i7d0v/kernel/cmdline
278 23:06:40.723920 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:06:40.724005 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:06:40.724097 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:06:40.724203 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:06:40.724287 Not connected, no need to disconnect.
283 23:06:40.724390 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:06:40.724466 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:06:40.724544 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 23:06:40.728804 Setting prompt string to ['lava-test: # ']
287 23:06:40.729214 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:06:40.729334 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:06:40.729466 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:06:40.729597 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:06:40.729851 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
292 23:06:45.854945 >> Command sent successfully.
293 23:06:45.857411 Returned 0 in 5 seconds
294 23:06:45.957825 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:06:45.958287 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:06:45.958423 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:06:45.958552 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:06:45.958654 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:06:45.958757 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:06:45.959129 [Enter `^Ec?' for help]
302 23:06:46.131233
303 23:06:46.131439
304 23:06:46.131543 F0: 102B 0000
305 23:06:46.131642
306 23:06:46.131777 F3: 1001 0000 [0200]
307 23:06:46.131869
308 23:06:46.134539 F3: 1001 0000
309 23:06:46.134645
310 23:06:46.134739 F7: 102D 0000
311 23:06:46.134831
312 23:06:46.134919 F1: 0000 0000
313 23:06:46.135007
314 23:06:46.138575 V0: 0000 0000 [0001]
315 23:06:46.138684
316 23:06:46.138777 00: 0007 8000
317 23:06:46.138870
318 23:06:46.142110 01: 0000 0000
319 23:06:46.142218
320 23:06:46.142312 BP: 0C00 0209 [0000]
321 23:06:46.142402
322 23:06:46.144771 G0: 1182 0000
323 23:06:46.144877
324 23:06:46.144970 EC: 0000 0021 [4000]
325 23:06:46.145061
326 23:06:46.147945 S7: 0000 0000 [0000]
327 23:06:46.148052
328 23:06:46.148145 CC: 0000 0000 [0001]
329 23:06:46.148236
330 23:06:46.152052 T0: 0000 0040 [010F]
331 23:06:46.152158
332 23:06:46.152251 Jump to BL
333 23:06:46.152340
334 23:06:46.178002
335 23:06:46.178179
336 23:06:46.178282
337 23:06:46.184932 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 23:06:46.189228 ARM64: Exception handlers installed.
339 23:06:46.192078 ARM64: Testing exception
340 23:06:46.196262 ARM64: Done test exception
341 23:06:46.203162 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 23:06:46.213331 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 23:06:46.219454 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 23:06:46.229633 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 23:06:46.236563 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 23:06:46.242988 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 23:06:46.254205 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 23:06:46.260626 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 23:06:46.280545 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 23:06:46.284512 WDT: Last reset was cold boot
351 23:06:46.286965 SPI1(PAD0) initialized at 2873684 Hz
352 23:06:46.290688 SPI5(PAD0) initialized at 992727 Hz
353 23:06:46.294439 VBOOT: Loading verstage.
354 23:06:46.300603 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 23:06:46.303928 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 23:06:46.306904 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 23:06:46.310096 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 23:06:46.318063 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 23:06:46.325056 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 23:06:46.335067 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 23:06:46.335182
362 23:06:46.335272
363 23:06:46.346000 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 23:06:46.349648 ARM64: Exception handlers installed.
365 23:06:46.352429 ARM64: Testing exception
366 23:06:46.352533 ARM64: Done test exception
367 23:06:46.358377 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 23:06:46.361939 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 23:06:46.376293 Probing TPM: . done!
370 23:06:46.376404 TPM ready after 0 ms
371 23:06:46.382953 Connected to device vid:did:rid of 1ae0:0028:00
372 23:06:46.393021 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 23:06:46.431646 Initialized TPM device CR50 revision 0
374 23:06:46.443774 tlcl_send_startup: Startup return code is 0
375 23:06:46.443894 TPM: setup succeeded
376 23:06:46.455083 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 23:06:46.463359 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 23:06:46.471027 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 23:06:46.482323 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 23:06:46.485892 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 23:06:46.488790 in-header: 03 07 00 00 08 00 00 00
382 23:06:46.492269 in-data: aa e4 47 04 13 02 00 00
383 23:06:46.495953 Chrome EC: UHEPI supported
384 23:06:46.502850 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 23:06:46.505474 in-header: 03 ad 00 00 08 00 00 00
386 23:06:46.509208 in-data: 00 20 20 08 00 00 00 00
387 23:06:46.509315 Phase 1
388 23:06:46.515414 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 23:06:46.521997 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 23:06:46.525415 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 23:06:46.528513 Recovery requested (1009000e)
392 23:06:46.538570 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 23:06:46.542099 tlcl_extend: response is 0
394 23:06:46.550593 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 23:06:46.555105 tlcl_extend: response is 0
396 23:06:46.562235 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 23:06:46.582474 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 23:06:46.589026 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 23:06:46.589111
400 23:06:46.589176
401 23:06:46.600083 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 23:06:46.603584 ARM64: Exception handlers installed.
403 23:06:46.603668 ARM64: Testing exception
404 23:06:46.606897 ARM64: Done test exception
405 23:06:46.628721 pmic_efuse_setting: Set efuses in 11 msecs
406 23:06:46.631822 pmwrap_interface_init: Select PMIF_VLD_RDY
407 23:06:46.635510 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 23:06:46.642105 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 23:06:46.645347 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 23:06:46.652541 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 23:06:46.655786 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 23:06:46.662660 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 23:06:46.665706 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 23:06:46.672445 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 23:06:46.676076 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 23:06:46.678997 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 23:06:46.685644 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 23:06:46.688839 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 23:06:46.692038 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 23:06:46.699339 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 23:06:46.706074 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 23:06:46.712557 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 23:06:46.716191 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 23:06:46.723031 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 23:06:46.729279 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 23:06:46.736014 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 23:06:46.739610 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 23:06:46.746768 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 23:06:46.750742 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 23:06:46.756661 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 23:06:46.760623 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 23:06:46.766828 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 23:06:46.773809 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 23:06:46.777036 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 23:06:46.780570 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 23:06:46.787510 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 23:06:46.791201 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 23:06:46.797657 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 23:06:46.801679 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 23:06:46.807906 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 23:06:46.811879 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 23:06:46.818320 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 23:06:46.822038 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 23:06:46.825715 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 23:06:46.832962 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 23:06:46.836443 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 23:06:46.839659 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 23:06:46.846501 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 23:06:46.849437 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 23:06:46.852808 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 23:06:46.859162 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 23:06:46.863067 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 23:06:46.865986 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 23:06:46.868575 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 23:06:46.875417 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 23:06:46.878702 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 23:06:46.881996 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 23:06:46.892450 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 23:06:46.898545 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 23:06:46.905156 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 23:06:46.911889 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 23:06:46.921875 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 23:06:46.925250 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 23:06:46.928284 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:06:46.935195 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 23:06:46.942303 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x0
467 23:06:46.944926 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 23:06:46.952412 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
469 23:06:46.955439 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 23:06:46.964988 [RTC]rtc_get_frequency_meter,154: input=15, output=834
471 23:06:46.974818 [RTC]rtc_get_frequency_meter,154: input=7, output=709
472 23:06:46.984038 [RTC]rtc_get_frequency_meter,154: input=11, output=772
473 23:06:46.993243 [RTC]rtc_get_frequency_meter,154: input=13, output=803
474 23:06:47.002810 [RTC]rtc_get_frequency_meter,154: input=12, output=788
475 23:06:47.012687 [RTC]rtc_get_frequency_meter,154: input=12, output=787
476 23:06:47.022371 [RTC]rtc_get_frequency_meter,154: input=13, output=804
477 23:06:47.025817 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
478 23:06:47.032459 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
479 23:06:47.036253 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 23:06:47.039199 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 23:06:47.046114 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 23:06:47.049390 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 23:06:47.053407 ADC[4]: Raw value=903031 ID=7
484 23:06:47.053490 ADC[3]: Raw value=214021 ID=1
485 23:06:47.055796 RAM Code: 0x71
486 23:06:47.059323 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 23:06:47.065813 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 23:06:47.072150 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 23:06:47.079115 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 23:06:47.082203 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 23:06:47.085854 in-header: 03 07 00 00 08 00 00 00
492 23:06:47.089393 in-data: aa e4 47 04 13 02 00 00
493 23:06:47.092183 Chrome EC: UHEPI supported
494 23:06:47.099288 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 23:06:47.102398 in-header: 03 dd 00 00 08 00 00 00
496 23:06:47.105731 in-data: 90 20 60 08 00 00 00 00
497 23:06:47.110024 MRC: failed to locate region type 0.
498 23:06:47.115267 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 23:06:47.118746 DRAM-K: Running full calibration
500 23:06:47.125432 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 23:06:47.125514 header.status = 0x0
502 23:06:47.128359 header.version = 0x6 (expected: 0x6)
503 23:06:47.132534 header.size = 0xd00 (expected: 0xd00)
504 23:06:47.135160 header.flags = 0x0
505 23:06:47.141974 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 23:06:47.159128 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
507 23:06:47.165388 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 23:06:47.168954 dram_init: ddr_geometry: 2
509 23:06:47.172199 [EMI] MDL number = 2
510 23:06:47.172285 [EMI] Get MDL freq = 0
511 23:06:47.175563 dram_init: ddr_type: 0
512 23:06:47.175679 is_discrete_lpddr4: 1
513 23:06:47.178966 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 23:06:47.179048
515 23:06:47.179112
516 23:06:47.182605 [Bian_co] ETT version 0.0.0.1
517 23:06:47.188996 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 23:06:47.189079
519 23:06:47.192329 dramc_set_vcore_voltage set vcore to 650000
520 23:06:47.195169 Read voltage for 800, 4
521 23:06:47.195250 Vio18 = 0
522 23:06:47.195316 Vcore = 650000
523 23:06:47.199069 Vdram = 0
524 23:06:47.199151 Vddq = 0
525 23:06:47.199215 Vmddr = 0
526 23:06:47.201816 dram_init: config_dvfs: 1
527 23:06:47.205178 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 23:06:47.212325 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 23:06:47.215405 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
530 23:06:47.218774 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
531 23:06:47.221595 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
532 23:06:47.228392 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
533 23:06:47.228494 MEM_TYPE=3, freq_sel=18
534 23:06:47.231440 sv_algorithm_assistance_LP4_1600
535 23:06:47.235074 ============ PULL DRAM RESETB DOWN ============
536 23:06:47.241807 ========== PULL DRAM RESETB DOWN end =========
537 23:06:47.245566 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 23:06:47.248147 ===================================
539 23:06:47.251732 LPDDR4 DRAM CONFIGURATION
540 23:06:47.255334 ===================================
541 23:06:47.255753 EX_ROW_EN[0] = 0x0
542 23:06:47.259271 EX_ROW_EN[1] = 0x0
543 23:06:47.259815 LP4Y_EN = 0x0
544 23:06:47.261826 WORK_FSP = 0x0
545 23:06:47.262184 WL = 0x2
546 23:06:47.265699 RL = 0x2
547 23:06:47.268336 BL = 0x2
548 23:06:47.268699 RPST = 0x0
549 23:06:47.272160 RD_PRE = 0x0
550 23:06:47.272634 WR_PRE = 0x1
551 23:06:47.275405 WR_PST = 0x0
552 23:06:47.275923 DBI_WR = 0x0
553 23:06:47.278857 DBI_RD = 0x0
554 23:06:47.279216 OTF = 0x1
555 23:06:47.282066 ===================================
556 23:06:47.285067 ===================================
557 23:06:47.288449 ANA top config
558 23:06:47.291408 ===================================
559 23:06:47.291806 DLL_ASYNC_EN = 0
560 23:06:47.295007 ALL_SLAVE_EN = 1
561 23:06:47.298682 NEW_RANK_MODE = 1
562 23:06:47.301359 DLL_IDLE_MODE = 1
563 23:06:47.301777 LP45_APHY_COMB_EN = 1
564 23:06:47.305131 TX_ODT_DIS = 1
565 23:06:47.308562 NEW_8X_MODE = 1
566 23:06:47.311893 ===================================
567 23:06:47.314980 ===================================
568 23:06:47.319403 data_rate = 1600
569 23:06:47.321624 CKR = 1
570 23:06:47.325264 DQ_P2S_RATIO = 8
571 23:06:47.328441 ===================================
572 23:06:47.328806 CA_P2S_RATIO = 8
573 23:06:47.331744 DQ_CA_OPEN = 0
574 23:06:47.335020 DQ_SEMI_OPEN = 0
575 23:06:47.338005 CA_SEMI_OPEN = 0
576 23:06:47.341693 CA_FULL_RATE = 0
577 23:06:47.342162 DQ_CKDIV4_EN = 1
578 23:06:47.344911 CA_CKDIV4_EN = 1
579 23:06:47.348422 CA_PREDIV_EN = 0
580 23:06:47.351900 PH8_DLY = 0
581 23:06:47.355191 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 23:06:47.358506 DQ_AAMCK_DIV = 4
583 23:06:47.358974 CA_AAMCK_DIV = 4
584 23:06:47.361710 CA_ADMCK_DIV = 4
585 23:06:47.364647 DQ_TRACK_CA_EN = 0
586 23:06:47.368496 CA_PICK = 800
587 23:06:47.371550 CA_MCKIO = 800
588 23:06:47.374644 MCKIO_SEMI = 0
589 23:06:47.378501 PLL_FREQ = 3068
590 23:06:47.382143 DQ_UI_PI_RATIO = 32
591 23:06:47.382614 CA_UI_PI_RATIO = 0
592 23:06:47.384605 ===================================
593 23:06:47.387754 ===================================
594 23:06:47.391248 memory_type:LPDDR4
595 23:06:47.394845 GP_NUM : 10
596 23:06:47.395313 SRAM_EN : 1
597 23:06:47.398283 MD32_EN : 0
598 23:06:47.401255 ===================================
599 23:06:47.404771 [ANA_INIT] >>>>>>>>>>>>>>
600 23:06:47.405240 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 23:06:47.408322 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 23:06:47.411011 ===================================
603 23:06:47.414991 data_rate = 1600,PCW = 0X7600
604 23:06:47.418575 ===================================
605 23:06:47.421146 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 23:06:47.427872 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:06:47.434806 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 23:06:47.437867 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 23:06:47.440776 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:06:47.444204 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 23:06:47.447549 [ANA_INIT] flow start
612 23:06:47.448103 [ANA_INIT] PLL >>>>>>>>
613 23:06:47.451085 [ANA_INIT] PLL <<<<<<<<
614 23:06:47.454451 [ANA_INIT] MIDPI >>>>>>>>
615 23:06:47.457351 [ANA_INIT] MIDPI <<<<<<<<
616 23:06:47.457758 [ANA_INIT] DLL >>>>>>>>
617 23:06:47.461307 [ANA_INIT] flow end
618 23:06:47.464190 ============ LP4 DIFF to SE enter ============
619 23:06:47.467659 ============ LP4 DIFF to SE exit ============
620 23:06:47.470765 [ANA_INIT] <<<<<<<<<<<<<
621 23:06:47.474501 [Flow] Enable top DCM control >>>>>
622 23:06:47.477751 [Flow] Enable top DCM control <<<<<
623 23:06:47.480683 Enable DLL master slave shuffle
624 23:06:47.487212 ==============================================================
625 23:06:47.487729 Gating Mode config
626 23:06:47.494438 ==============================================================
627 23:06:47.494989 Config description:
628 23:06:47.504870 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 23:06:47.511226 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 23:06:47.518059 SELPH_MODE 0: By rank 1: By Phase
631 23:06:47.521027 ==============================================================
632 23:06:47.524498 GAT_TRACK_EN = 1
633 23:06:47.527786 RX_GATING_MODE = 2
634 23:06:47.531089 RX_GATING_TRACK_MODE = 2
635 23:06:47.534002 SELPH_MODE = 1
636 23:06:47.537190 PICG_EARLY_EN = 1
637 23:06:47.540374 VALID_LAT_VALUE = 1
638 23:06:47.547634 ==============================================================
639 23:06:47.550508 Enter into Gating configuration >>>>
640 23:06:47.553839 Exit from Gating configuration <<<<
641 23:06:47.554377 Enter into DVFS_PRE_config >>>>>
642 23:06:47.567420 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 23:06:47.570897 Exit from DVFS_PRE_config <<<<<
644 23:06:47.573699 Enter into PICG configuration >>>>
645 23:06:47.576889 Exit from PICG configuration <<<<
646 23:06:47.577321 [RX_INPUT] configuration >>>>>
647 23:06:47.580585 [RX_INPUT] configuration <<<<<
648 23:06:47.587460 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 23:06:47.591306 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 23:06:47.597774 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 23:06:47.604922 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 23:06:47.608487 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 23:06:47.615922 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 23:06:47.619515 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 23:06:47.623329 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 23:06:47.631000 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 23:06:47.634088 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 23:06:47.637845 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 23:06:47.641706 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 23:06:47.644638 ===================================
661 23:06:47.648855 LPDDR4 DRAM CONFIGURATION
662 23:06:47.651728 ===================================
663 23:06:47.652177 EX_ROW_EN[0] = 0x0
664 23:06:47.655761 EX_ROW_EN[1] = 0x0
665 23:06:47.656352 LP4Y_EN = 0x0
666 23:06:47.659339 WORK_FSP = 0x0
667 23:06:47.659912 WL = 0x2
668 23:06:47.662828 RL = 0x2
669 23:06:47.663276 BL = 0x2
670 23:06:47.667131 RPST = 0x0
671 23:06:47.667721 RD_PRE = 0x0
672 23:06:47.668247 WR_PRE = 0x1
673 23:06:47.670233 WR_PST = 0x0
674 23:06:47.670625 DBI_WR = 0x0
675 23:06:47.674269 DBI_RD = 0x0
676 23:06:47.674864 OTF = 0x1
677 23:06:47.677564 ===================================
678 23:06:47.681109 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 23:06:47.684935 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 23:06:47.692399 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 23:06:47.696097 ===================================
682 23:06:47.696491 LPDDR4 DRAM CONFIGURATION
683 23:06:47.699393 ===================================
684 23:06:47.702858 EX_ROW_EN[0] = 0x10
685 23:06:47.703256 EX_ROW_EN[1] = 0x0
686 23:06:47.707303 LP4Y_EN = 0x0
687 23:06:47.707838 WORK_FSP = 0x0
688 23:06:47.711162 WL = 0x2
689 23:06:47.711738 RL = 0x2
690 23:06:47.715180 BL = 0x2
691 23:06:47.715748 RPST = 0x0
692 23:06:47.718460 RD_PRE = 0x0
693 23:06:47.718974 WR_PRE = 0x1
694 23:06:47.719292 WR_PST = 0x0
695 23:06:47.721745 DBI_WR = 0x0
696 23:06:47.722248 DBI_RD = 0x0
697 23:06:47.725153 OTF = 0x1
698 23:06:47.728549 ===================================
699 23:06:47.736197 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 23:06:47.739770 nWR fixed to 40
701 23:06:47.740181 [ModeRegInit_LP4] CH0 RK0
702 23:06:47.743639 [ModeRegInit_LP4] CH0 RK1
703 23:06:47.744151 [ModeRegInit_LP4] CH1 RK0
704 23:06:47.746777 [ModeRegInit_LP4] CH1 RK1
705 23:06:47.750560 match AC timing 13
706 23:06:47.754818 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 23:06:47.757776 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 23:06:47.760946 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 23:06:47.767736 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 23:06:47.771502 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 23:06:47.774501 [EMI DOE] emi_dcm 0
712 23:06:47.777918 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 23:06:47.778453 ==
714 23:06:47.781164 Dram Type= 6, Freq= 0, CH_0, rank 0
715 23:06:47.784005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 23:06:47.784464 ==
717 23:06:47.791639 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 23:06:47.795237 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 23:06:47.805710 [CA 0] Center 37 (6~68) winsize 63
720 23:06:47.808766 [CA 1] Center 37 (6~68) winsize 63
721 23:06:47.812076 [CA 2] Center 34 (4~65) winsize 62
722 23:06:47.815205 [CA 3] Center 34 (4~65) winsize 62
723 23:06:47.819278 [CA 4] Center 33 (3~64) winsize 62
724 23:06:47.822235 [CA 5] Center 33 (3~64) winsize 62
725 23:06:47.822624
726 23:06:47.826237 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 23:06:47.826734
728 23:06:47.829242 [CATrainingPosCal] consider 1 rank data
729 23:06:47.832553 u2DelayCellTimex100 = 270/100 ps
730 23:06:47.836389 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
731 23:06:47.839505 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 23:06:47.842225 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 23:06:47.846237 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 23:06:47.849842 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 23:06:47.856385 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 23:06:47.856807
737 23:06:47.858994 CA PerBit enable=1, Macro0, CA PI delay=33
738 23:06:47.859411
739 23:06:47.862424 [CBTSetCACLKResult] CA Dly = 33
740 23:06:47.862848 CS Dly: 6 (0~37)
741 23:06:47.863159 ==
742 23:06:47.866237 Dram Type= 6, Freq= 0, CH_0, rank 1
743 23:06:47.869326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 23:06:47.872812 ==
745 23:06:47.876207 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 23:06:47.882438 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 23:06:47.891440 [CA 0] Center 37 (6~68) winsize 63
748 23:06:47.895133 [CA 1] Center 37 (7~68) winsize 62
749 23:06:47.897872 [CA 2] Center 34 (4~65) winsize 62
750 23:06:47.901123 [CA 3] Center 34 (4~65) winsize 62
751 23:06:47.904959 [CA 4] Center 33 (3~64) winsize 62
752 23:06:47.908622 [CA 5] Center 33 (3~64) winsize 62
753 23:06:47.909089
754 23:06:47.912050 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 23:06:47.912576
756 23:06:47.914832 [CATrainingPosCal] consider 2 rank data
757 23:06:47.917991 u2DelayCellTimex100 = 270/100 ps
758 23:06:47.921405 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
759 23:06:47.924800 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 23:06:47.931991 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 23:06:47.936022 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 23:06:47.938807 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 23:06:47.942883 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 23:06:47.943303
765 23:06:47.945842 CA PerBit enable=1, Macro0, CA PI delay=33
766 23:06:47.946345
767 23:06:47.949604 [CBTSetCACLKResult] CA Dly = 33
768 23:06:47.950024 CS Dly: 6 (0~38)
769 23:06:47.950409
770 23:06:47.952945 ----->DramcWriteLeveling(PI) begin...
771 23:06:47.953418 ==
772 23:06:47.956533 Dram Type= 6, Freq= 0, CH_0, rank 0
773 23:06:47.960321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 23:06:47.960766 ==
775 23:06:47.963399 Write leveling (Byte 0): 32 => 32
776 23:06:47.967592 Write leveling (Byte 1): 32 => 32
777 23:06:47.971013 DramcWriteLeveling(PI) end<-----
778 23:06:47.971557
779 23:06:47.971954 ==
780 23:06:47.973355 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:06:47.977136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 23:06:47.977871 ==
783 23:06:47.980097 [Gating] SW mode calibration
784 23:06:47.986879 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 23:06:47.993725 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 23:06:47.997125 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 23:06:47.999845 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 23:06:48.007359 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 23:06:48.010307 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 23:06:48.013892 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:06:48.020596 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:06:48.023442 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:06:48.026617 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:06:48.033790 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:06:48.036464 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:06:48.039914 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:06:48.046603 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 23:06:48.049917 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:06:48.053043 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:06:48.060209 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:06:48.063385 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:06:48.066910 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 23:06:48.073004 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
804 23:06:48.076358 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 23:06:48.080055 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 23:06:48.086370 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:06:48.089345 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:06:48.092822 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:06:48.099627 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:06:48.102474 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 23:06:48.106478 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 23:06:48.112476 0 9 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
813 23:06:48.116195 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
814 23:06:48.119908 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 23:06:48.126435 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 23:06:48.129285 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 23:06:48.133039 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 23:06:48.138798 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 23:06:48.142741 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
820 23:06:48.146067 0 10 8 | B1->B0 | 3434 2828 | 0 0 | (0 0) (1 0)
821 23:06:48.152193 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
822 23:06:48.155439 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:06:48.159146 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:06:48.165393 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:06:48.168566 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:06:48.172347 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:06:48.179215 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 23:06:48.182366 0 11 8 | B1->B0 | 2525 3838 | 0 0 | (0 0) (0 0)
829 23:06:48.186001 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
830 23:06:48.192667 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 23:06:48.195709 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 23:06:48.198855 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 23:06:48.202059 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 23:06:48.209010 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 23:06:48.212361 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 23:06:48.215234 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 23:06:48.222373 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 23:06:48.225645 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:06:48.228638 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:06:48.235279 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:06:48.238513 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:06:48.241798 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:06:48.248618 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:06:48.252043 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:06:48.255517 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 23:06:48.262239 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 23:06:48.265075 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 23:06:48.268436 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 23:06:48.274934 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 23:06:48.278975 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 23:06:48.281521 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 23:06:48.288320 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 23:06:48.288854 Total UI for P1: 0, mck2ui 16
854 23:06:48.295742 best dqsien dly found for B0: ( 0, 14, 4)
855 23:06:48.298839 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 23:06:48.302118 Total UI for P1: 0, mck2ui 16
857 23:06:48.305820 best dqsien dly found for B1: ( 0, 14, 8)
858 23:06:48.308786 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 23:06:48.312727 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 23:06:48.313325
861 23:06:48.315403 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 23:06:48.319198 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 23:06:48.322350 [Gating] SW calibration Done
864 23:06:48.322888 ==
865 23:06:48.325957 Dram Type= 6, Freq= 0, CH_0, rank 0
866 23:06:48.329579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 23:06:48.330003 ==
868 23:06:48.330372 RX Vref Scan: 0
869 23:06:48.333205
870 23:06:48.333686 RX Vref 0 -> 0, step: 1
871 23:06:48.334065
872 23:06:48.336487 RX Delay -130 -> 252, step: 16
873 23:06:48.340293 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 23:06:48.343773 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 23:06:48.347536 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 23:06:48.351030 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 23:06:48.359039 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 23:06:48.362245 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 23:06:48.366021 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 23:06:48.369376 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 23:06:48.372717 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 23:06:48.375917 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 23:06:48.379558 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 23:06:48.386288 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 23:06:48.389227 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
886 23:06:48.392717 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
887 23:06:48.396259 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 23:06:48.399237 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 23:06:48.402705 ==
890 23:06:48.403230 Dram Type= 6, Freq= 0, CH_0, rank 0
891 23:06:48.409511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 23:06:48.410049 ==
893 23:06:48.410392 DQS Delay:
894 23:06:48.413835 DQS0 = 0, DQS1 = 0
895 23:06:48.414383 DQM Delay:
896 23:06:48.414728 DQM0 = 87, DQM1 = 75
897 23:06:48.416974 DQ Delay:
898 23:06:48.420524 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 23:06:48.420945 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
900 23:06:48.424226 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
901 23:06:48.427342 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
902 23:06:48.427805
903 23:06:48.428145
904 23:06:48.428478 ==
905 23:06:48.431149 Dram Type= 6, Freq= 0, CH_0, rank 0
906 23:06:48.435160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 23:06:48.438035 ==
908 23:06:48.438622
909 23:06:48.439044
910 23:06:48.439410 TX Vref Scan disable
911 23:06:48.441534 == TX Byte 0 ==
912 23:06:48.444794 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
913 23:06:48.448110 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
914 23:06:48.451726 == TX Byte 1 ==
915 23:06:48.454321 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
916 23:06:48.461354 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
917 23:06:48.461885 ==
918 23:06:48.464335 Dram Type= 6, Freq= 0, CH_0, rank 0
919 23:06:48.467795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 23:06:48.468329 ==
921 23:06:48.480298 TX Vref=22, minBit 5, minWin=27, winSum=442
922 23:06:48.483455 TX Vref=24, minBit 4, minWin=27, winSum=443
923 23:06:48.486699 TX Vref=26, minBit 8, minWin=27, winSum=449
924 23:06:48.489928 TX Vref=28, minBit 1, minWin=28, winSum=451
925 23:06:48.493534 TX Vref=30, minBit 10, minWin=27, winSum=450
926 23:06:48.497068 TX Vref=32, minBit 5, minWin=27, winSum=444
927 23:06:48.503757 [TxChooseVref] Worse bit 1, Min win 28, Win sum 451, Final Vref 28
928 23:06:48.504186
929 23:06:48.506911 Final TX Range 1 Vref 28
930 23:06:48.507339
931 23:06:48.507716 ==
932 23:06:48.510328 Dram Type= 6, Freq= 0, CH_0, rank 0
933 23:06:48.513226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 23:06:48.513654 ==
935 23:06:48.516523
936 23:06:48.516944
937 23:06:48.517279 TX Vref Scan disable
938 23:06:48.519946 == TX Byte 0 ==
939 23:06:48.523171 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
940 23:06:48.527282 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
941 23:06:48.530337 == TX Byte 1 ==
942 23:06:48.533368 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
943 23:06:48.536937 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
944 23:06:48.540226
945 23:06:48.540648 [DATLAT]
946 23:06:48.540984 Freq=800, CH0 RK0
947 23:06:48.541297
948 23:06:48.544036 DATLAT Default: 0xa
949 23:06:48.544456 0, 0xFFFF, sum = 0
950 23:06:48.546753 1, 0xFFFF, sum = 0
951 23:06:48.547183 2, 0xFFFF, sum = 0
952 23:06:48.550107 3, 0xFFFF, sum = 0
953 23:06:48.550547 4, 0xFFFF, sum = 0
954 23:06:48.553504 5, 0xFFFF, sum = 0
955 23:06:48.556479 6, 0xFFFF, sum = 0
956 23:06:48.556942 7, 0xFFFF, sum = 0
957 23:06:48.560136 8, 0xFFFF, sum = 0
958 23:06:48.560660 9, 0x0, sum = 1
959 23:06:48.561002 10, 0x0, sum = 2
960 23:06:48.563294 11, 0x0, sum = 3
961 23:06:48.563876 12, 0x0, sum = 4
962 23:06:48.566544 best_step = 10
963 23:06:48.567062
964 23:06:48.567402 ==
965 23:06:48.570689 Dram Type= 6, Freq= 0, CH_0, rank 0
966 23:06:48.573347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 23:06:48.573875 ==
968 23:06:48.576566 RX Vref Scan: 1
969 23:06:48.577085
970 23:06:48.577420 Set Vref Range= 32 -> 127
971 23:06:48.579748
972 23:06:48.580266 RX Vref 32 -> 127, step: 1
973 23:06:48.580608
974 23:06:48.583659 RX Delay -95 -> 252, step: 8
975 23:06:48.584129
976 23:06:48.586537 Set Vref, RX VrefLevel [Byte0]: 32
977 23:06:48.589652 [Byte1]: 32
978 23:06:48.590077
979 23:06:48.593191 Set Vref, RX VrefLevel [Byte0]: 33
980 23:06:48.596183 [Byte1]: 33
981 23:06:48.600785
982 23:06:48.601305 Set Vref, RX VrefLevel [Byte0]: 34
983 23:06:48.603459 [Byte1]: 34
984 23:06:48.608482
985 23:06:48.609015 Set Vref, RX VrefLevel [Byte0]: 35
986 23:06:48.611314 [Byte1]: 35
987 23:06:48.615860
988 23:06:48.616375 Set Vref, RX VrefLevel [Byte0]: 36
989 23:06:48.618637 [Byte1]: 36
990 23:06:48.624069
991 23:06:48.624742 Set Vref, RX VrefLevel [Byte0]: 37
992 23:06:48.627490 [Byte1]: 37
993 23:06:48.631336
994 23:06:48.631897 Set Vref, RX VrefLevel [Byte0]: 38
995 23:06:48.634113 [Byte1]: 38
996 23:06:48.638323
997 23:06:48.638850 Set Vref, RX VrefLevel [Byte0]: 39
998 23:06:48.642016 [Byte1]: 39
999 23:06:48.645806
1000 23:06:48.646373 Set Vref, RX VrefLevel [Byte0]: 40
1001 23:06:48.649486 [Byte1]: 40
1002 23:06:48.653501
1003 23:06:48.654056 Set Vref, RX VrefLevel [Byte0]: 41
1004 23:06:48.657459 [Byte1]: 41
1005 23:06:48.660953
1006 23:06:48.661376 Set Vref, RX VrefLevel [Byte0]: 42
1007 23:06:48.664353 [Byte1]: 42
1008 23:06:48.669287
1009 23:06:48.669813 Set Vref, RX VrefLevel [Byte0]: 43
1010 23:06:48.672265 [Byte1]: 43
1011 23:06:48.676207
1012 23:06:48.676733 Set Vref, RX VrefLevel [Byte0]: 44
1013 23:06:48.679533 [Byte1]: 44
1014 23:06:48.684159
1015 23:06:48.684584 Set Vref, RX VrefLevel [Byte0]: 45
1016 23:06:48.687306 [Byte1]: 45
1017 23:06:48.691775
1018 23:06:48.692238 Set Vref, RX VrefLevel [Byte0]: 46
1019 23:06:48.694678 [Byte1]: 46
1020 23:06:48.699757
1021 23:06:48.700278 Set Vref, RX VrefLevel [Byte0]: 47
1022 23:06:48.702096 [Byte1]: 47
1023 23:06:48.706437
1024 23:06:48.706882 Set Vref, RX VrefLevel [Byte0]: 48
1025 23:06:48.711237 [Byte1]: 48
1026 23:06:48.714377
1027 23:06:48.714887 Set Vref, RX VrefLevel [Byte0]: 49
1028 23:06:48.717809 [Byte1]: 49
1029 23:06:48.722323
1030 23:06:48.722830 Set Vref, RX VrefLevel [Byte0]: 50
1031 23:06:48.725274 [Byte1]: 50
1032 23:06:48.729441
1033 23:06:48.729859 Set Vref, RX VrefLevel [Byte0]: 51
1034 23:06:48.733383 [Byte1]: 51
1035 23:06:48.737925
1036 23:06:48.738488 Set Vref, RX VrefLevel [Byte0]: 52
1037 23:06:48.740854 [Byte1]: 52
1038 23:06:48.744421
1039 23:06:48.744995 Set Vref, RX VrefLevel [Byte0]: 53
1040 23:06:48.748174 [Byte1]: 53
1041 23:06:48.752202
1042 23:06:48.755650 Set Vref, RX VrefLevel [Byte0]: 54
1043 23:06:48.756133 [Byte1]: 54
1044 23:06:48.760204
1045 23:06:48.760718 Set Vref, RX VrefLevel [Byte0]: 55
1046 23:06:48.763118 [Byte1]: 55
1047 23:06:48.767846
1048 23:06:48.768530 Set Vref, RX VrefLevel [Byte0]: 56
1049 23:06:48.771021 [Byte1]: 56
1050 23:06:48.775372
1051 23:06:48.775957 Set Vref, RX VrefLevel [Byte0]: 57
1052 23:06:48.778635 [Byte1]: 57
1053 23:06:48.782760
1054 23:06:48.783181 Set Vref, RX VrefLevel [Byte0]: 58
1055 23:06:48.786331 [Byte1]: 58
1056 23:06:48.790034
1057 23:06:48.790454 Set Vref, RX VrefLevel [Byte0]: 59
1058 23:06:48.793545 [Byte1]: 59
1059 23:06:48.797837
1060 23:06:48.798347 Set Vref, RX VrefLevel [Byte0]: 60
1061 23:06:48.801019 [Byte1]: 60
1062 23:06:48.805075
1063 23:06:48.805518 Set Vref, RX VrefLevel [Byte0]: 61
1064 23:06:48.808547 [Byte1]: 61
1065 23:06:48.812979
1066 23:06:48.813494 Set Vref, RX VrefLevel [Byte0]: 62
1067 23:06:48.816557 [Byte1]: 62
1068 23:06:48.820461
1069 23:06:48.820879 Set Vref, RX VrefLevel [Byte0]: 63
1070 23:06:48.824100 [Byte1]: 63
1071 23:06:48.828789
1072 23:06:48.829306 Set Vref, RX VrefLevel [Byte0]: 64
1073 23:06:48.831807 [Byte1]: 64
1074 23:06:48.835841
1075 23:06:48.836258 Set Vref, RX VrefLevel [Byte0]: 65
1076 23:06:48.839017 [Byte1]: 65
1077 23:06:48.843892
1078 23:06:48.844629 Set Vref, RX VrefLevel [Byte0]: 66
1079 23:06:48.846918 [Byte1]: 66
1080 23:06:48.851013
1081 23:06:48.854588 Set Vref, RX VrefLevel [Byte0]: 67
1082 23:06:48.855040 [Byte1]: 67
1083 23:06:48.858610
1084 23:06:48.859120 Set Vref, RX VrefLevel [Byte0]: 68
1085 23:06:48.862451 [Byte1]: 68
1086 23:06:48.866507
1087 23:06:48.866920 Set Vref, RX VrefLevel [Byte0]: 69
1088 23:06:48.869796 [Byte1]: 69
1089 23:06:48.874306
1090 23:06:48.874846 Set Vref, RX VrefLevel [Byte0]: 70
1091 23:06:48.877583 [Byte1]: 70
1092 23:06:48.881620
1093 23:06:48.882155 Set Vref, RX VrefLevel [Byte0]: 71
1094 23:06:48.884348 [Byte1]: 71
1095 23:06:48.889306
1096 23:06:48.889719 Set Vref, RX VrefLevel [Byte0]: 72
1097 23:06:48.892345 [Byte1]: 72
1098 23:06:48.896495
1099 23:06:48.896921 Set Vref, RX VrefLevel [Byte0]: 73
1100 23:06:48.900086 [Byte1]: 73
1101 23:06:48.904393
1102 23:06:48.904926 Set Vref, RX VrefLevel [Byte0]: 74
1103 23:06:48.907837 [Byte1]: 74
1104 23:06:48.911854
1105 23:06:48.912372 Set Vref, RX VrefLevel [Byte0]: 75
1106 23:06:48.915345 [Byte1]: 75
1107 23:06:48.919381
1108 23:06:48.919943 Set Vref, RX VrefLevel [Byte0]: 76
1109 23:06:48.922833 [Byte1]: 76
1110 23:06:48.926906
1111 23:06:48.927466 Set Vref, RX VrefLevel [Byte0]: 77
1112 23:06:48.930229 [Byte1]: 77
1113 23:06:48.934296
1114 23:06:48.934711 Set Vref, RX VrefLevel [Byte0]: 78
1115 23:06:48.937844 [Byte1]: 78
1116 23:06:48.942340
1117 23:06:48.942859 Set Vref, RX VrefLevel [Byte0]: 79
1118 23:06:48.945606 [Byte1]: 79
1119 23:06:48.949853
1120 23:06:48.950363 Set Vref, RX VrefLevel [Byte0]: 80
1121 23:06:48.952966 [Byte1]: 80
1122 23:06:48.957777
1123 23:06:48.958289 Final RX Vref Byte 0 = 64 to rank0
1124 23:06:48.960975 Final RX Vref Byte 1 = 60 to rank0
1125 23:06:48.964889 Final RX Vref Byte 0 = 64 to rank1
1126 23:06:48.968271 Final RX Vref Byte 1 = 60 to rank1==
1127 23:06:48.971839 Dram Type= 6, Freq= 0, CH_0, rank 0
1128 23:06:48.975740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1129 23:06:48.976282 ==
1130 23:06:48.976623 DQS Delay:
1131 23:06:48.979488 DQS0 = 0, DQS1 = 0
1132 23:06:48.980071 DQM Delay:
1133 23:06:48.983535 DQM0 = 86, DQM1 = 76
1134 23:06:48.984005 DQ Delay:
1135 23:06:48.986977 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =80
1136 23:06:48.990063 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1137 23:06:48.993709 DQ8 =68, DQ9 =68, DQ10 =76, DQ11 =68
1138 23:06:48.997052 DQ12 =80, DQ13 =76, DQ14 =88, DQ15 =84
1139 23:06:48.997468
1140 23:06:48.997793
1141 23:06:49.004661 [DQSOSCAuto] RK0, (LSB)MR18= 0x4728, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
1142 23:06:49.008498 CH0 RK0: MR19=606, MR18=4728
1143 23:06:49.012547 CH0_RK0: MR19=0x606, MR18=0x4728, DQSOSC=392, MR23=63, INC=96, DEC=64
1144 23:06:49.012981
1145 23:06:49.015409 ----->DramcWriteLeveling(PI) begin...
1146 23:06:49.015964 ==
1147 23:06:49.019454 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 23:06:49.023320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1149 23:06:49.023884 ==
1150 23:06:49.027439 Write leveling (Byte 0): 33 => 33
1151 23:06:49.030639 Write leveling (Byte 1): 30 => 30
1152 23:06:49.034351 DramcWriteLeveling(PI) end<-----
1153 23:06:49.034909
1154 23:06:49.035248 ==
1155 23:06:49.037505 Dram Type= 6, Freq= 0, CH_0, rank 1
1156 23:06:49.040664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 23:06:49.041230 ==
1158 23:06:49.044447 [Gating] SW mode calibration
1159 23:06:49.092535 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1160 23:06:49.093402 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1161 23:06:49.093778 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1162 23:06:49.094181 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1163 23:06:49.094507 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1164 23:06:49.094809 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1165 23:06:49.095162 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 23:06:49.095464 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 23:06:49.095832 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:06:49.096137 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:06:49.137298 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 23:06:49.137816 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 23:06:49.138158 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:06:49.138813 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:06:49.139163 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:06:49.139529 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 23:06:49.139900 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 23:06:49.140202 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 23:06:49.140493 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 23:06:49.140776 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1179 23:06:49.180719 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1180 23:06:49.181598 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1181 23:06:49.181972 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 23:06:49.182293 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 23:06:49.182595 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 23:06:49.182885 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 23:06:49.183172 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 23:06:49.183457 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 23:06:49.183849 0 9 8 | B1->B0 | 2424 2e2e | 0 1 | (0 0) (1 1)
1188 23:06:49.184215 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1189 23:06:49.224690 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 23:06:49.225670 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 23:06:49.226043 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 23:06:49.226366 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 23:06:49.226736 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 23:06:49.227051 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1195 23:06:49.227442 0 10 8 | B1->B0 | 2f2f 2c2c | 0 0 | (0 0) (0 0)
1196 23:06:49.227791 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 23:06:49.228092 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 23:06:49.228433 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 23:06:49.231444 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 23:06:49.234422 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 23:06:49.238470 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 23:06:49.242651 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 23:06:49.246058 0 11 8 | B1->B0 | 2e2e 3f3f | 0 0 | (0 0) (0 0)
1204 23:06:49.248953 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1205 23:06:49.253376 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 23:06:49.259961 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 23:06:49.262686 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 23:06:49.266504 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 23:06:49.271194 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 23:06:49.277565 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 23:06:49.281287 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1212 23:06:49.284319 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:06:49.287984 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 23:06:49.295151 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 23:06:49.298983 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 23:06:49.302727 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 23:06:49.306063 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 23:06:49.310430 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 23:06:49.316724 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 23:06:49.321110 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 23:06:49.324451 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 23:06:49.328222 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 23:06:49.334589 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 23:06:49.338717 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 23:06:49.341983 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 23:06:49.346308 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 23:06:49.349459 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1228 23:06:49.354091 Total UI for P1: 0, mck2ui 16
1229 23:06:49.356718 best dqsien dly found for B0: ( 0, 14, 6)
1230 23:06:49.359976 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1231 23:06:49.363476 Total UI for P1: 0, mck2ui 16
1232 23:06:49.367432 best dqsien dly found for B1: ( 0, 14, 8)
1233 23:06:49.371066 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1234 23:06:49.375198 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1235 23:06:49.375947
1236 23:06:49.378543 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1237 23:06:49.382197 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1238 23:06:49.386522 [Gating] SW calibration Done
1239 23:06:49.387233 ==
1240 23:06:49.389447 Dram Type= 6, Freq= 0, CH_0, rank 1
1241 23:06:49.393392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1242 23:06:49.393821 ==
1243 23:06:49.394156 RX Vref Scan: 0
1244 23:06:49.394470
1245 23:06:49.396430 RX Vref 0 -> 0, step: 1
1246 23:06:49.396850
1247 23:06:49.399777 RX Delay -130 -> 252, step: 16
1248 23:06:49.404048 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1249 23:06:49.407852 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1250 23:06:49.411470 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1251 23:06:49.414730 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1252 23:06:49.418512 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1253 23:06:49.422036 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1254 23:06:49.429198 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1255 23:06:49.433188 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1256 23:06:49.436998 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1257 23:06:49.440234 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1258 23:06:49.443965 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1259 23:06:49.447854 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1260 23:06:49.450475 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1261 23:06:49.457401 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1262 23:06:49.460472 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1263 23:06:49.465416 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1264 23:06:49.465939 ==
1265 23:06:49.466884 Dram Type= 6, Freq= 0, CH_0, rank 1
1266 23:06:49.470443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1267 23:06:49.470979 ==
1268 23:06:49.473843 DQS Delay:
1269 23:06:49.474350 DQS0 = 0, DQS1 = 0
1270 23:06:49.477072 DQM Delay:
1271 23:06:49.477489 DQM0 = 83, DQM1 = 74
1272 23:06:49.477821 DQ Delay:
1273 23:06:49.480332 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1274 23:06:49.483766 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1275 23:06:49.487071 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =69
1276 23:06:49.490094 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1277 23:06:49.490513
1278 23:06:49.490837
1279 23:06:49.493513 ==
1280 23:06:49.496865 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 23:06:49.500788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 23:06:49.501305 ==
1283 23:06:49.501642
1284 23:06:49.501945
1285 23:06:49.503204 TX Vref Scan disable
1286 23:06:49.503617 == TX Byte 0 ==
1287 23:06:49.510288 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1288 23:06:49.513561 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1289 23:06:49.514081 == TX Byte 1 ==
1290 23:06:49.520801 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1291 23:06:49.524121 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1292 23:06:49.524639 ==
1293 23:06:49.526924 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 23:06:49.529566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 23:06:49.529981 ==
1296 23:06:49.543550 TX Vref=22, minBit 9, minWin=27, winSum=444
1297 23:06:49.547314 TX Vref=24, minBit 4, minWin=27, winSum=442
1298 23:06:49.550341 TX Vref=26, minBit 8, minWin=27, winSum=447
1299 23:06:49.553885 TX Vref=28, minBit 9, minWin=27, winSum=450
1300 23:06:49.557084 TX Vref=30, minBit 8, minWin=27, winSum=447
1301 23:06:49.560502 TX Vref=32, minBit 9, minWin=27, winSum=446
1302 23:06:49.567440 [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 28
1303 23:06:49.567891
1304 23:06:49.570378 Final TX Range 1 Vref 28
1305 23:06:49.570830
1306 23:06:49.571264 ==
1307 23:06:49.573586 Dram Type= 6, Freq= 0, CH_0, rank 1
1308 23:06:49.577019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1309 23:06:49.577436 ==
1310 23:06:49.577762
1311 23:06:49.578058
1312 23:06:49.580206 TX Vref Scan disable
1313 23:06:49.584005 == TX Byte 0 ==
1314 23:06:49.586937 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1315 23:06:49.590274 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1316 23:06:49.593362 == TX Byte 1 ==
1317 23:06:49.596870 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1318 23:06:49.600256 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1319 23:06:49.604135
1320 23:06:49.604538 [DATLAT]
1321 23:06:49.604862 Freq=800, CH0 RK1
1322 23:06:49.605169
1323 23:06:49.607153 DATLAT Default: 0xa
1324 23:06:49.607563 0, 0xFFFF, sum = 0
1325 23:06:49.610282 1, 0xFFFF, sum = 0
1326 23:06:49.610795 2, 0xFFFF, sum = 0
1327 23:06:49.614042 3, 0xFFFF, sum = 0
1328 23:06:49.616730 4, 0xFFFF, sum = 0
1329 23:06:49.617148 5, 0xFFFF, sum = 0
1330 23:06:49.619932 6, 0xFFFF, sum = 0
1331 23:06:49.620352 7, 0xFFFF, sum = 0
1332 23:06:49.623480 8, 0xFFFF, sum = 0
1333 23:06:49.623937 9, 0x0, sum = 1
1334 23:06:49.624271 10, 0x0, sum = 2
1335 23:06:49.627008 11, 0x0, sum = 3
1336 23:06:49.627431 12, 0x0, sum = 4
1337 23:06:49.630119 best_step = 10
1338 23:06:49.630527
1339 23:06:49.630853 ==
1340 23:06:49.634067 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 23:06:49.636644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 23:06:49.637061 ==
1343 23:06:49.640382 RX Vref Scan: 0
1344 23:06:49.640882
1345 23:06:49.641209 RX Vref 0 -> 0, step: 1
1346 23:06:49.643275
1347 23:06:49.643729 RX Delay -111 -> 252, step: 8
1348 23:06:49.650052 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1349 23:06:49.653418 iDelay=209, Bit 1, Center 88 (-31 ~ 208) 240
1350 23:06:49.657392 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1351 23:06:49.660009 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1352 23:06:49.663641 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1353 23:06:49.670333 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1354 23:06:49.673431 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1355 23:06:49.677231 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1356 23:06:49.679984 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1357 23:06:49.683960 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1358 23:06:49.690189 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1359 23:06:49.693331 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1360 23:06:49.697419 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1361 23:06:49.700107 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1362 23:06:49.706912 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1363 23:06:49.710446 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1364 23:06:49.710951 ==
1365 23:06:49.713951 Dram Type= 6, Freq= 0, CH_0, rank 1
1366 23:06:49.717338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1367 23:06:49.717856 ==
1368 23:06:49.718188 DQS Delay:
1369 23:06:49.719998 DQS0 = 0, DQS1 = 0
1370 23:06:49.720409 DQM Delay:
1371 23:06:49.723763 DQM0 = 84, DQM1 = 77
1372 23:06:49.724269 DQ Delay:
1373 23:06:49.726857 DQ0 =80, DQ1 =88, DQ2 =80, DQ3 =84
1374 23:06:49.730491 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1375 23:06:49.733493 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1376 23:06:49.737281 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1377 23:06:49.737701
1378 23:06:49.738031
1379 23:06:49.746511 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c02, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
1380 23:06:49.747020 CH0 RK1: MR19=606, MR18=3C02
1381 23:06:49.753142 CH0_RK1: MR19=0x606, MR18=0x3C02, DQSOSC=394, MR23=63, INC=95, DEC=63
1382 23:06:49.756717 [RxdqsGatingPostProcess] freq 800
1383 23:06:49.763538 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1384 23:06:49.766089 Pre-setting of DQS Precalculation
1385 23:06:49.769708 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1386 23:06:49.770123 ==
1387 23:06:49.772849 Dram Type= 6, Freq= 0, CH_1, rank 0
1388 23:06:49.779455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1389 23:06:49.779911 ==
1390 23:06:49.783003 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1391 23:06:49.789851 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1392 23:06:49.798534 [CA 0] Center 36 (6~67) winsize 62
1393 23:06:49.802126 [CA 1] Center 36 (6~67) winsize 62
1394 23:06:49.805751 [CA 2] Center 34 (4~65) winsize 62
1395 23:06:49.809136 [CA 3] Center 34 (3~65) winsize 63
1396 23:06:49.812206 [CA 4] Center 34 (4~65) winsize 62
1397 23:06:49.815406 [CA 5] Center 34 (3~65) winsize 63
1398 23:06:49.815961
1399 23:06:49.818608 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1400 23:06:49.819023
1401 23:06:49.822125 [CATrainingPosCal] consider 1 rank data
1402 23:06:49.825755 u2DelayCellTimex100 = 270/100 ps
1403 23:06:49.828578 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1404 23:06:49.835629 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1405 23:06:49.838487 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1406 23:06:49.841368 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1407 23:06:49.845099 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1408 23:06:49.848417 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1409 23:06:49.848959
1410 23:06:49.851591 CA PerBit enable=1, Macro0, CA PI delay=34
1411 23:06:49.852047
1412 23:06:49.855059 [CBTSetCACLKResult] CA Dly = 34
1413 23:06:49.858499 CS Dly: 5 (0~36)
1414 23:06:49.858906 ==
1415 23:06:49.861306 Dram Type= 6, Freq= 0, CH_1, rank 1
1416 23:06:49.865204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1417 23:06:49.865647 ==
1418 23:06:49.871435 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1419 23:06:49.874867 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1420 23:06:49.885633 [CA 0] Center 36 (6~67) winsize 62
1421 23:06:49.888170 [CA 1] Center 36 (6~67) winsize 62
1422 23:06:49.892033 [CA 2] Center 34 (4~65) winsize 62
1423 23:06:49.894871 [CA 3] Center 34 (3~65) winsize 63
1424 23:06:49.898187 [CA 4] Center 34 (4~65) winsize 62
1425 23:06:49.901628 [CA 5] Center 33 (3~64) winsize 62
1426 23:06:49.902039
1427 23:06:49.904733 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1428 23:06:49.905142
1429 23:06:49.908421 [CATrainingPosCal] consider 2 rank data
1430 23:06:49.911337 u2DelayCellTimex100 = 270/100 ps
1431 23:06:49.915174 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1432 23:06:49.918010 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1433 23:06:49.924644 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1434 23:06:49.928260 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1435 23:06:49.931205 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1436 23:06:49.935338 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1437 23:06:49.935904
1438 23:06:49.938183 CA PerBit enable=1, Macro0, CA PI delay=33
1439 23:06:49.938613
1440 23:06:49.941000 [CBTSetCACLKResult] CA Dly = 33
1441 23:06:49.941430 CS Dly: 6 (0~38)
1442 23:06:49.941866
1443 23:06:49.945260 ----->DramcWriteLeveling(PI) begin...
1444 23:06:49.947745 ==
1445 23:06:49.951707 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 23:06:49.954677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 23:06:49.955092 ==
1448 23:06:49.957590 Write leveling (Byte 0): 30 => 30
1449 23:06:49.961361 Write leveling (Byte 1): 30 => 30
1450 23:06:49.964582 DramcWriteLeveling(PI) end<-----
1451 23:06:49.964992
1452 23:06:49.965316 ==
1453 23:06:49.967429 Dram Type= 6, Freq= 0, CH_1, rank 0
1454 23:06:49.971323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1455 23:06:49.971884 ==
1456 23:06:49.974316 [Gating] SW mode calibration
1457 23:06:49.981041 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1458 23:06:49.988055 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1459 23:06:49.991766 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1460 23:06:49.994462 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1461 23:06:50.000726 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1462 23:06:50.004358 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 23:06:50.007661 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 23:06:50.014654 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 23:06:50.017110 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 23:06:50.020913 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 23:06:50.027633 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 23:06:50.031060 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 23:06:50.033883 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:06:50.037767 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:06:50.044650 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:06:50.047632 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 23:06:50.050877 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 23:06:50.057219 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 23:06:50.060646 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 23:06:50.064106 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1477 23:06:50.071021 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1478 23:06:50.074317 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 23:06:50.077703 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 23:06:50.084006 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 23:06:50.087602 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 23:06:50.090827 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 23:06:50.097311 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 23:06:50.100440 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 23:06:50.103725 0 9 8 | B1->B0 | 2a2a 3232 | 0 0 | (0 0) (0 0)
1486 23:06:50.110730 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 23:06:50.114062 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 23:06:50.116788 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 23:06:50.123794 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 23:06:50.126871 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 23:06:50.130098 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 23:06:50.136996 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1493 23:06:50.140806 0 10 8 | B1->B0 | 2a2a 2525 | 0 0 | (0 0) (0 0)
1494 23:06:50.143455 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 23:06:50.150295 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 23:06:50.153738 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 23:06:50.156743 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 23:06:50.163313 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 23:06:50.166471 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 23:06:50.170304 0 11 4 | B1->B0 | 2424 2a2a | 0 1 | (0 0) (0 0)
1501 23:06:50.176324 0 11 8 | B1->B0 | 3a3a 4242 | 1 0 | (1 1) (0 0)
1502 23:06:50.179995 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 23:06:50.183040 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 23:06:50.190550 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 23:06:50.193139 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 23:06:50.196507 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 23:06:50.203262 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1508 23:06:50.207048 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1509 23:06:50.209703 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1510 23:06:50.213198 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:06:50.219740 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 23:06:50.222720 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 23:06:50.226573 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 23:06:50.233398 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 23:06:50.236418 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 23:06:50.239536 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 23:06:50.246583 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 23:06:50.249491 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 23:06:50.252825 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 23:06:50.259829 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 23:06:50.262814 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 23:06:50.266785 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 23:06:50.272544 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 23:06:50.275987 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1525 23:06:50.279194 Total UI for P1: 0, mck2ui 16
1526 23:06:50.282591 best dqsien dly found for B0: ( 0, 14, 2)
1527 23:06:50.285869 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1528 23:06:50.289466 Total UI for P1: 0, mck2ui 16
1529 23:06:50.292729 best dqsien dly found for B1: ( 0, 14, 4)
1530 23:06:50.295377 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1531 23:06:50.298858 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1532 23:06:50.301993
1533 23:06:50.306075 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1534 23:06:50.308945 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1535 23:06:50.312526 [Gating] SW calibration Done
1536 23:06:50.313045 ==
1537 23:06:50.315534 Dram Type= 6, Freq= 0, CH_1, rank 0
1538 23:06:50.318837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1539 23:06:50.319280 ==
1540 23:06:50.319609 RX Vref Scan: 0
1541 23:06:50.319951
1542 23:06:50.322091 RX Vref 0 -> 0, step: 1
1543 23:06:50.322502
1544 23:06:50.325469 RX Delay -130 -> 252, step: 16
1545 23:06:50.329024 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1546 23:06:50.332394 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1547 23:06:50.338975 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1548 23:06:50.342032 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1549 23:06:50.345796 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1550 23:06:50.348676 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1551 23:06:50.352723 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1552 23:06:50.358956 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1553 23:06:50.362155 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1554 23:06:50.365227 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1555 23:06:50.368745 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1556 23:06:50.372212 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1557 23:06:50.378862 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1558 23:06:50.382294 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1559 23:06:50.385599 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1560 23:06:50.388329 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1561 23:06:50.388742 ==
1562 23:06:50.391563 Dram Type= 6, Freq= 0, CH_1, rank 0
1563 23:06:50.398224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1564 23:06:50.398641 ==
1565 23:06:50.398968 DQS Delay:
1566 23:06:50.402027 DQS0 = 0, DQS1 = 0
1567 23:06:50.402440 DQM Delay:
1568 23:06:50.404840 DQM0 = 89, DQM1 = 78
1569 23:06:50.405251 DQ Delay:
1570 23:06:50.408149 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1571 23:06:50.411749 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1572 23:06:50.415146 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1573 23:06:50.418116 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1574 23:06:50.418530
1575 23:06:50.418856
1576 23:06:50.419159 ==
1577 23:06:50.421765 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 23:06:50.425452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 23:06:50.425963 ==
1580 23:06:50.426294
1581 23:06:50.426595
1582 23:06:50.428177 TX Vref Scan disable
1583 23:06:50.431831 == TX Byte 0 ==
1584 23:06:50.435613 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1585 23:06:50.438176 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1586 23:06:50.441430 == TX Byte 1 ==
1587 23:06:50.444988 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1588 23:06:50.448119 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1589 23:06:50.448596 ==
1590 23:06:50.451797 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 23:06:50.454665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 23:06:50.457766 ==
1593 23:06:50.469826 TX Vref=22, minBit 10, minWin=26, winSum=438
1594 23:06:50.472768 TX Vref=24, minBit 15, minWin=26, winSum=441
1595 23:06:50.476165 TX Vref=26, minBit 8, minWin=27, winSum=445
1596 23:06:50.479772 TX Vref=28, minBit 9, minWin=27, winSum=451
1597 23:06:50.482636 TX Vref=30, minBit 9, minWin=27, winSum=449
1598 23:06:50.489778 TX Vref=32, minBit 8, minWin=27, winSum=442
1599 23:06:50.492856 [TxChooseVref] Worse bit 9, Min win 27, Win sum 451, Final Vref 28
1600 23:06:50.493394
1601 23:06:50.495584 Final TX Range 1 Vref 28
1602 23:06:50.496025
1603 23:06:50.496351 ==
1604 23:06:50.499464 Dram Type= 6, Freq= 0, CH_1, rank 0
1605 23:06:50.502892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1606 23:06:50.505738 ==
1607 23:06:50.506161
1608 23:06:50.506491
1609 23:06:50.506793 TX Vref Scan disable
1610 23:06:50.509283 == TX Byte 0 ==
1611 23:06:50.513082 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1612 23:06:50.519263 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1613 23:06:50.519842 == TX Byte 1 ==
1614 23:06:50.522624 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1615 23:06:50.529495 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1616 23:06:50.530022
1617 23:06:50.530461 [DATLAT]
1618 23:06:50.530869 Freq=800, CH1 RK0
1619 23:06:50.531271
1620 23:06:50.532585 DATLAT Default: 0xa
1621 23:06:50.533011 0, 0xFFFF, sum = 0
1622 23:06:50.536233 1, 0xFFFF, sum = 0
1623 23:06:50.536684 2, 0xFFFF, sum = 0
1624 23:06:50.539113 3, 0xFFFF, sum = 0
1625 23:06:50.542308 4, 0xFFFF, sum = 0
1626 23:06:50.542728 5, 0xFFFF, sum = 0
1627 23:06:50.545820 6, 0xFFFF, sum = 0
1628 23:06:50.546241 7, 0xFFFF, sum = 0
1629 23:06:50.548890 8, 0xFFFF, sum = 0
1630 23:06:50.549306 9, 0x0, sum = 1
1631 23:06:50.552731 10, 0x0, sum = 2
1632 23:06:50.553149 11, 0x0, sum = 3
1633 23:06:50.553486 12, 0x0, sum = 4
1634 23:06:50.555816 best_step = 10
1635 23:06:50.556264
1636 23:06:50.556598 ==
1637 23:06:50.558975 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 23:06:50.563049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 23:06:50.563645 ==
1640 23:06:50.566033 RX Vref Scan: 1
1641 23:06:50.566543
1642 23:06:50.568976 Set Vref Range= 32 -> 127
1643 23:06:50.569390
1644 23:06:50.569714 RX Vref 32 -> 127, step: 1
1645 23:06:50.570129
1646 23:06:50.572099 RX Delay -95 -> 252, step: 8
1647 23:06:50.572510
1648 23:06:50.575493 Set Vref, RX VrefLevel [Byte0]: 32
1649 23:06:50.579380 [Byte1]: 32
1650 23:06:50.579833
1651 23:06:50.582693 Set Vref, RX VrefLevel [Byte0]: 33
1652 23:06:50.586192 [Byte1]: 33
1653 23:06:50.589696
1654 23:06:50.590111 Set Vref, RX VrefLevel [Byte0]: 34
1655 23:06:50.592645 [Byte1]: 34
1656 23:06:50.597749
1657 23:06:50.598298 Set Vref, RX VrefLevel [Byte0]: 35
1658 23:06:50.601019 [Byte1]: 35
1659 23:06:50.605254
1660 23:06:50.605922 Set Vref, RX VrefLevel [Byte0]: 36
1661 23:06:50.607941 [Byte1]: 36
1662 23:06:50.612377
1663 23:06:50.612808 Set Vref, RX VrefLevel [Byte0]: 37
1664 23:06:50.615663 [Byte1]: 37
1665 23:06:50.619655
1666 23:06:50.620083 Set Vref, RX VrefLevel [Byte0]: 38
1667 23:06:50.623250 [Byte1]: 38
1668 23:06:50.627603
1669 23:06:50.628051 Set Vref, RX VrefLevel [Byte0]: 39
1670 23:06:50.630882 [Byte1]: 39
1671 23:06:50.635070
1672 23:06:50.635637 Set Vref, RX VrefLevel [Byte0]: 40
1673 23:06:50.638309 [Byte1]: 40
1674 23:06:50.643193
1675 23:06:50.643638 Set Vref, RX VrefLevel [Byte0]: 41
1676 23:06:50.646291 [Byte1]: 41
1677 23:06:50.650793
1678 23:06:50.651226 Set Vref, RX VrefLevel [Byte0]: 42
1679 23:06:50.656819 [Byte1]: 42
1680 23:06:50.657229
1681 23:06:50.660071 Set Vref, RX VrefLevel [Byte0]: 43
1682 23:06:50.663904 [Byte1]: 43
1683 23:06:50.664318
1684 23:06:50.666713 Set Vref, RX VrefLevel [Byte0]: 44
1685 23:06:50.669978 [Byte1]: 44
1686 23:06:50.673470
1687 23:06:50.673875 Set Vref, RX VrefLevel [Byte0]: 45
1688 23:06:50.676347 [Byte1]: 45
1689 23:06:50.680569
1690 23:06:50.681057 Set Vref, RX VrefLevel [Byte0]: 46
1691 23:06:50.684027 [Byte1]: 46
1692 23:06:50.688515
1693 23:06:50.688923 Set Vref, RX VrefLevel [Byte0]: 47
1694 23:06:50.692029 [Byte1]: 47
1695 23:06:50.695871
1696 23:06:50.696278 Set Vref, RX VrefLevel [Byte0]: 48
1697 23:06:50.699545 [Byte1]: 48
1698 23:06:50.703546
1699 23:06:50.704121 Set Vref, RX VrefLevel [Byte0]: 49
1700 23:06:50.707319 [Byte1]: 49
1701 23:06:50.711074
1702 23:06:50.711589 Set Vref, RX VrefLevel [Byte0]: 50
1703 23:06:50.714294 [Byte1]: 50
1704 23:06:50.718742
1705 23:06:50.719248 Set Vref, RX VrefLevel [Byte0]: 51
1706 23:06:50.721902 [Byte1]: 51
1707 23:06:50.726310
1708 23:06:50.726717 Set Vref, RX VrefLevel [Byte0]: 52
1709 23:06:50.729960 [Byte1]: 52
1710 23:06:50.733705
1711 23:06:50.734119 Set Vref, RX VrefLevel [Byte0]: 53
1712 23:06:50.737143 [Byte1]: 53
1713 23:06:50.741412
1714 23:06:50.741940 Set Vref, RX VrefLevel [Byte0]: 54
1715 23:06:50.745055 [Byte1]: 54
1716 23:06:50.749380
1717 23:06:50.749882 Set Vref, RX VrefLevel [Byte0]: 55
1718 23:06:50.755723 [Byte1]: 55
1719 23:06:50.756250
1720 23:06:50.759081 Set Vref, RX VrefLevel [Byte0]: 56
1721 23:06:50.762267 [Byte1]: 56
1722 23:06:50.762671
1723 23:06:50.765281 Set Vref, RX VrefLevel [Byte0]: 57
1724 23:06:50.768806 [Byte1]: 57
1725 23:06:50.769222
1726 23:06:50.771845 Set Vref, RX VrefLevel [Byte0]: 58
1727 23:06:50.775649 [Byte1]: 58
1728 23:06:50.779760
1729 23:06:50.780174 Set Vref, RX VrefLevel [Byte0]: 59
1730 23:06:50.782726 [Byte1]: 59
1731 23:06:50.787420
1732 23:06:50.788009 Set Vref, RX VrefLevel [Byte0]: 60
1733 23:06:50.790157 [Byte1]: 60
1734 23:06:50.795057
1735 23:06:50.795586 Set Vref, RX VrefLevel [Byte0]: 61
1736 23:06:50.798245 [Byte1]: 61
1737 23:06:50.802060
1738 23:06:50.802468 Set Vref, RX VrefLevel [Byte0]: 62
1739 23:06:50.805868 [Byte1]: 62
1740 23:06:50.810701
1741 23:06:50.811213 Set Vref, RX VrefLevel [Byte0]: 63
1742 23:06:50.814067 [Byte1]: 63
1743 23:06:50.817490
1744 23:06:50.817903 Set Vref, RX VrefLevel [Byte0]: 64
1745 23:06:50.820926 [Byte1]: 64
1746 23:06:50.825579
1747 23:06:50.826082 Set Vref, RX VrefLevel [Byte0]: 65
1748 23:06:50.828412 [Byte1]: 65
1749 23:06:50.832871
1750 23:06:50.833367 Set Vref, RX VrefLevel [Byte0]: 66
1751 23:06:50.836051 [Byte1]: 66
1752 23:06:50.840437
1753 23:06:50.840936 Set Vref, RX VrefLevel [Byte0]: 67
1754 23:06:50.844038 [Byte1]: 67
1755 23:06:50.847895
1756 23:06:50.848353 Set Vref, RX VrefLevel [Byte0]: 68
1757 23:06:50.854332 [Byte1]: 68
1758 23:06:50.854836
1759 23:06:50.857701 Set Vref, RX VrefLevel [Byte0]: 69
1760 23:06:50.861028 [Byte1]: 69
1761 23:06:50.861590
1762 23:06:50.864262 Set Vref, RX VrefLevel [Byte0]: 70
1763 23:06:50.867850 [Byte1]: 70
1764 23:06:50.871034
1765 23:06:50.871539 Set Vref, RX VrefLevel [Byte0]: 71
1766 23:06:50.873988 [Byte1]: 71
1767 23:06:50.877993
1768 23:06:50.878443 Set Vref, RX VrefLevel [Byte0]: 72
1769 23:06:50.881668 [Byte1]: 72
1770 23:06:50.885845
1771 23:06:50.886351 Set Vref, RX VrefLevel [Byte0]: 73
1772 23:06:50.889566 [Byte1]: 73
1773 23:06:50.893265
1774 23:06:50.893727 Set Vref, RX VrefLevel [Byte0]: 74
1775 23:06:50.896695 [Byte1]: 74
1776 23:06:50.900938
1777 23:06:50.901343 Set Vref, RX VrefLevel [Byte0]: 75
1778 23:06:50.904840 [Byte1]: 75
1779 23:06:50.908778
1780 23:06:50.909283 Set Vref, RX VrefLevel [Byte0]: 76
1781 23:06:50.912350 [Byte1]: 76
1782 23:06:50.916218
1783 23:06:50.916672 Set Vref, RX VrefLevel [Byte0]: 77
1784 23:06:50.920059 [Byte1]: 77
1785 23:06:50.923732
1786 23:06:50.924142 Final RX Vref Byte 0 = 54 to rank0
1787 23:06:50.927127 Final RX Vref Byte 1 = 62 to rank0
1788 23:06:50.930239 Final RX Vref Byte 0 = 54 to rank1
1789 23:06:50.933975 Final RX Vref Byte 1 = 62 to rank1==
1790 23:06:50.936952 Dram Type= 6, Freq= 0, CH_1, rank 0
1791 23:06:50.943627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1792 23:06:50.944082 ==
1793 23:06:50.944411 DQS Delay:
1794 23:06:50.946989 DQS0 = 0, DQS1 = 0
1795 23:06:50.947470 DQM Delay:
1796 23:06:50.947858 DQM0 = 87, DQM1 = 79
1797 23:06:50.950090 DQ Delay:
1798 23:06:50.953634 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1799 23:06:50.956886 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
1800 23:06:50.960166 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1801 23:06:50.963597 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =92
1802 23:06:50.964066
1803 23:06:50.964424
1804 23:06:50.970036 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e1b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
1805 23:06:50.973532 CH1 RK0: MR19=606, MR18=2E1B
1806 23:06:50.980162 CH1_RK0: MR19=0x606, MR18=0x2E1B, DQSOSC=398, MR23=63, INC=93, DEC=62
1807 23:06:50.980580
1808 23:06:50.983414 ----->DramcWriteLeveling(PI) begin...
1809 23:06:50.983963 ==
1810 23:06:50.987220 Dram Type= 6, Freq= 0, CH_1, rank 1
1811 23:06:50.989866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1812 23:06:50.990289 ==
1813 23:06:50.993445 Write leveling (Byte 0): 26 => 26
1814 23:06:50.996418 Write leveling (Byte 1): 27 => 27
1815 23:06:51.000177 DramcWriteLeveling(PI) end<-----
1816 23:06:51.000725
1817 23:06:51.001053 ==
1818 23:06:51.003356 Dram Type= 6, Freq= 0, CH_1, rank 1
1819 23:06:51.006476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1820 23:06:51.006885 ==
1821 23:06:51.009917 [Gating] SW mode calibration
1822 23:06:51.016469 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1823 23:06:51.023098 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1824 23:06:51.026495 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1825 23:06:51.033520 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1826 23:06:51.036385 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1827 23:06:51.039793 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 23:06:51.046275 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 23:06:51.049502 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 23:06:51.052913 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 23:06:51.059357 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 23:06:51.063407 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 23:06:51.065926 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 23:06:51.073795 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 23:06:51.076127 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 23:06:51.079400 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 23:06:51.085771 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 23:06:51.088890 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 23:06:51.092527 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 23:06:51.099107 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1841 23:06:51.103565 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1842 23:06:51.106319 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1843 23:06:51.109336 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 23:06:51.115906 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 23:06:51.118942 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 23:06:51.122434 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 23:06:51.129001 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 23:06:51.132573 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 23:06:51.136073 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 23:06:51.142107 0 9 8 | B1->B0 | 3131 2828 | 1 1 | (1 1) (1 1)
1851 23:06:51.146221 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 23:06:51.148616 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 23:06:51.155039 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 23:06:51.158709 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 23:06:51.161893 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 23:06:51.168887 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1857 23:06:51.171814 0 10 4 | B1->B0 | 3030 3434 | 0 1 | (0 1) (1 0)
1858 23:06:51.175720 0 10 8 | B1->B0 | 2727 2d2d | 0 0 | (0 0) (1 0)
1859 23:06:51.182094 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 23:06:51.185165 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 23:06:51.188993 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 23:06:51.194891 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 23:06:51.198166 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 23:06:51.201751 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 23:06:51.208241 0 11 4 | B1->B0 | 2e2e 2424 | 0 1 | (1 1) (0 0)
1866 23:06:51.211313 0 11 8 | B1->B0 | 3e3e 3838 | 0 0 | (1 1) (1 1)
1867 23:06:51.214672 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 23:06:51.221684 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 23:06:51.225716 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 23:06:51.228239 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 23:06:51.234809 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 23:06:51.238283 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 23:06:51.241313 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1874 23:06:51.248274 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 23:06:51.251617 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 23:06:51.254796 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 23:06:51.261202 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 23:06:51.265211 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 23:06:51.268000 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 23:06:51.274700 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 23:06:51.277886 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 23:06:51.281049 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 23:06:51.288089 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 23:06:51.291528 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 23:06:51.294591 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 23:06:51.300975 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 23:06:51.303960 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 23:06:51.307795 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 23:06:51.314293 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1890 23:06:51.317242 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 23:06:51.320655 Total UI for P1: 0, mck2ui 16
1892 23:06:51.324321 best dqsien dly found for B0: ( 0, 14, 4)
1893 23:06:51.327640 Total UI for P1: 0, mck2ui 16
1894 23:06:51.330445 best dqsien dly found for B1: ( 0, 14, 4)
1895 23:06:51.333753 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1896 23:06:51.336993 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1897 23:06:51.337094
1898 23:06:51.340623 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1899 23:06:51.343668 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1900 23:06:51.347219 [Gating] SW calibration Done
1901 23:06:51.347318 ==
1902 23:06:51.350225 Dram Type= 6, Freq= 0, CH_1, rank 1
1903 23:06:51.353681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1904 23:06:51.353783 ==
1905 23:06:51.356872 RX Vref Scan: 0
1906 23:06:51.356972
1907 23:06:51.360124 RX Vref 0 -> 0, step: 1
1908 23:06:51.360223
1909 23:06:51.360301 RX Delay -130 -> 252, step: 16
1910 23:06:51.367107 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1911 23:06:51.370404 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1912 23:06:51.373555 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1913 23:06:51.377342 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1914 23:06:51.380223 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1915 23:06:51.386898 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1916 23:06:51.390370 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1917 23:06:51.394106 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1918 23:06:51.397081 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1919 23:06:51.400254 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1920 23:06:51.406867 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1921 23:06:51.410437 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1922 23:06:51.413760 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1923 23:06:51.416503 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1924 23:06:51.423652 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1925 23:06:51.426731 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1926 23:06:51.426911 ==
1927 23:06:51.429952 Dram Type= 6, Freq= 0, CH_1, rank 1
1928 23:06:51.433450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1929 23:06:51.433579 ==
1930 23:06:51.436920 DQS Delay:
1931 23:06:51.437031 DQS0 = 0, DQS1 = 0
1932 23:06:51.437118 DQM Delay:
1933 23:06:51.439873 DQM0 = 87, DQM1 = 79
1934 23:06:51.439985 DQ Delay:
1935 23:06:51.442964 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1936 23:06:51.446742 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1937 23:06:51.450325 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1938 23:06:51.453657 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1939 23:06:51.453765
1940 23:06:51.453849
1941 23:06:51.453927 ==
1942 23:06:51.456231 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 23:06:51.463264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 23:06:51.463719 ==
1945 23:06:51.464063
1946 23:06:51.464368
1947 23:06:51.464657 TX Vref Scan disable
1948 23:06:51.466677 == TX Byte 0 ==
1949 23:06:51.470482 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1950 23:06:51.476747 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1951 23:06:51.477159 == TX Byte 1 ==
1952 23:06:51.480146 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1953 23:06:51.487560 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1954 23:06:51.488261 ==
1955 23:06:51.489883 Dram Type= 6, Freq= 0, CH_1, rank 1
1956 23:06:51.492972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1957 23:06:51.493420 ==
1958 23:06:51.505733 TX Vref=22, minBit 1, minWin=27, winSum=442
1959 23:06:51.508846 TX Vref=24, minBit 0, minWin=27, winSum=447
1960 23:06:51.512512 TX Vref=26, minBit 1, minWin=27, winSum=449
1961 23:06:51.516054 TX Vref=28, minBit 8, minWin=27, winSum=449
1962 23:06:51.519378 TX Vref=30, minBit 8, minWin=27, winSum=450
1963 23:06:51.525328 TX Vref=32, minBit 10, minWin=27, winSum=450
1964 23:06:51.528772 [TxChooseVref] Worse bit 8, Min win 27, Win sum 450, Final Vref 30
1965 23:06:51.528911
1966 23:06:51.532535 Final TX Range 1 Vref 30
1967 23:06:51.532637
1968 23:06:51.532727 ==
1969 23:06:51.535482 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 23:06:51.538864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 23:06:51.538964 ==
1972 23:06:51.542016
1973 23:06:51.542112
1974 23:06:51.542198 TX Vref Scan disable
1975 23:06:51.546488 == TX Byte 0 ==
1976 23:06:51.549176 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1977 23:06:51.552231 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1978 23:06:51.556029 == TX Byte 1 ==
1979 23:06:51.558984 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1980 23:06:51.562564 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1981 23:06:51.566446
1982 23:06:51.566550 [DATLAT]
1983 23:06:51.566646 Freq=800, CH1 RK1
1984 23:06:51.566735
1985 23:06:51.569281 DATLAT Default: 0xa
1986 23:06:51.569388 0, 0xFFFF, sum = 0
1987 23:06:51.572667 1, 0xFFFF, sum = 0
1988 23:06:51.573201 2, 0xFFFF, sum = 0
1989 23:06:51.575905 3, 0xFFFF, sum = 0
1990 23:06:51.579060 4, 0xFFFF, sum = 0
1991 23:06:51.579743 5, 0xFFFF, sum = 0
1992 23:06:51.582738 6, 0xFFFF, sum = 0
1993 23:06:51.583378 7, 0xFFFF, sum = 0
1994 23:06:51.585701 8, 0xFFFF, sum = 0
1995 23:06:51.586328 9, 0x0, sum = 1
1996 23:06:51.589097 10, 0x0, sum = 2
1997 23:06:51.589650 11, 0x0, sum = 3
1998 23:06:51.589990 12, 0x0, sum = 4
1999 23:06:51.592645 best_step = 10
2000 23:06:51.593051
2001 23:06:51.593434 ==
2002 23:06:51.596375 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 23:06:51.599401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 23:06:51.599726 ==
2005 23:06:51.602202 RX Vref Scan: 0
2006 23:06:51.602421
2007 23:06:51.602594 RX Vref 0 -> 0, step: 1
2008 23:06:51.605437
2009 23:06:51.605656 RX Delay -95 -> 252, step: 8
2010 23:06:51.612443 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2011 23:06:51.615931 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2012 23:06:51.619045 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2013 23:06:51.622312 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2014 23:06:51.625430 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2015 23:06:51.632342 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2016 23:06:51.635824 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2017 23:06:51.639409 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2018 23:06:51.642364 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2019 23:06:51.645524 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2020 23:06:51.652111 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2021 23:06:51.655481 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2022 23:06:51.659019 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2023 23:06:51.662149 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2024 23:06:51.668935 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2025 23:06:51.671990 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2026 23:06:51.672233 ==
2027 23:06:51.674872 Dram Type= 6, Freq= 0, CH_1, rank 1
2028 23:06:51.678923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2029 23:06:51.679088 ==
2030 23:06:51.681722 DQS Delay:
2031 23:06:51.681898 DQS0 = 0, DQS1 = 0
2032 23:06:51.682054 DQM Delay:
2033 23:06:51.685069 DQM0 = 87, DQM1 = 79
2034 23:06:51.685239 DQ Delay:
2035 23:06:51.688301 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2036 23:06:51.691775 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2037 23:06:51.694898 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =68
2038 23:06:51.698809 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2039 23:06:51.698983
2040 23:06:51.699141
2041 23:06:51.708215 [DQSOSCAuto] RK1, (LSB)MR18= 0x1910, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2042 23:06:51.711199 CH1 RK1: MR19=606, MR18=1910
2043 23:06:51.714843 CH1_RK1: MR19=0x606, MR18=0x1910, DQSOSC=403, MR23=63, INC=90, DEC=60
2044 23:06:51.718152 [RxdqsGatingPostProcess] freq 800
2045 23:06:51.724730 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2046 23:06:51.728071 Pre-setting of DQS Precalculation
2047 23:06:51.731852 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2048 23:06:51.741321 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2049 23:06:51.748064 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2050 23:06:51.748257
2051 23:06:51.748424
2052 23:06:51.751512 [Calibration Summary] 1600 Mbps
2053 23:06:51.751667 CH 0, Rank 0
2054 23:06:51.754980 SW Impedance : PASS
2055 23:06:51.755101 DUTY Scan : NO K
2056 23:06:51.758357 ZQ Calibration : PASS
2057 23:06:51.761635 Jitter Meter : NO K
2058 23:06:51.761775 CBT Training : PASS
2059 23:06:51.765482 Write leveling : PASS
2060 23:06:51.768338 RX DQS gating : PASS
2061 23:06:51.768453 RX DQ/DQS(RDDQC) : PASS
2062 23:06:51.771442 TX DQ/DQS : PASS
2063 23:06:51.774556 RX DATLAT : PASS
2064 23:06:51.774670 RX DQ/DQS(Engine): PASS
2065 23:06:51.778382 TX OE : NO K
2066 23:06:51.778573 All Pass.
2067 23:06:51.778673
2068 23:06:51.781752 CH 0, Rank 1
2069 23:06:51.781969 SW Impedance : PASS
2070 23:06:51.784435 DUTY Scan : NO K
2071 23:06:51.788058 ZQ Calibration : PASS
2072 23:06:51.788254 Jitter Meter : NO K
2073 23:06:51.791248 CBT Training : PASS
2074 23:06:51.791448 Write leveling : PASS
2075 23:06:51.794487 RX DQS gating : PASS
2076 23:06:51.797733 RX DQ/DQS(RDDQC) : PASS
2077 23:06:51.797943 TX DQ/DQS : PASS
2078 23:06:51.801316 RX DATLAT : PASS
2079 23:06:51.804513 RX DQ/DQS(Engine): PASS
2080 23:06:51.804805 TX OE : NO K
2081 23:06:51.808031 All Pass.
2082 23:06:51.808358
2083 23:06:51.808574 CH 1, Rank 0
2084 23:06:51.812087 SW Impedance : PASS
2085 23:06:51.812577 DUTY Scan : NO K
2086 23:06:51.815140 ZQ Calibration : PASS
2087 23:06:51.818454 Jitter Meter : NO K
2088 23:06:51.819030 CBT Training : PASS
2089 23:06:51.821655 Write leveling : PASS
2090 23:06:51.824999 RX DQS gating : PASS
2091 23:06:51.825406 RX DQ/DQS(RDDQC) : PASS
2092 23:06:51.828271 TX DQ/DQS : PASS
2093 23:06:51.831330 RX DATLAT : PASS
2094 23:06:51.831793 RX DQ/DQS(Engine): PASS
2095 23:06:51.835027 TX OE : NO K
2096 23:06:51.835438 All Pass.
2097 23:06:51.835807
2098 23:06:51.836120 CH 1, Rank 1
2099 23:06:51.838251 SW Impedance : PASS
2100 23:06:51.841793 DUTY Scan : NO K
2101 23:06:51.842304 ZQ Calibration : PASS
2102 23:06:51.845228 Jitter Meter : NO K
2103 23:06:51.848486 CBT Training : PASS
2104 23:06:51.848899 Write leveling : PASS
2105 23:06:51.851155 RX DQS gating : PASS
2106 23:06:51.854683 RX DQ/DQS(RDDQC) : PASS
2107 23:06:51.855193 TX DQ/DQS : PASS
2108 23:06:51.857830 RX DATLAT : PASS
2109 23:06:51.862046 RX DQ/DQS(Engine): PASS
2110 23:06:51.862549 TX OE : NO K
2111 23:06:51.864939 All Pass.
2112 23:06:51.865348
2113 23:06:51.865675 DramC Write-DBI off
2114 23:06:51.867862 PER_BANK_REFRESH: Hybrid Mode
2115 23:06:51.868278 TX_TRACKING: ON
2116 23:06:51.871152 [GetDramInforAfterCalByMRR] Vendor 6.
2117 23:06:51.877758 [GetDramInforAfterCalByMRR] Revision 606.
2118 23:06:51.881236 [GetDramInforAfterCalByMRR] Revision 2 0.
2119 23:06:51.881650 MR0 0x3b3b
2120 23:06:51.881976 MR8 0x5151
2121 23:06:51.884841 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2122 23:06:51.885255
2123 23:06:51.888094 MR0 0x3b3b
2124 23:06:51.888498 MR8 0x5151
2125 23:06:51.891634 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2126 23:06:51.892077
2127 23:06:51.901520 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2128 23:06:51.904820 [FAST_K] Save calibration result to emmc
2129 23:06:51.907983 [FAST_K] Save calibration result to emmc
2130 23:06:51.911125 dram_init: config_dvfs: 1
2131 23:06:51.914750 dramc_set_vcore_voltage set vcore to 662500
2132 23:06:51.918930 Read voltage for 1200, 2
2133 23:06:51.919445 Vio18 = 0
2134 23:06:51.919837 Vcore = 662500
2135 23:06:51.921770 Vdram = 0
2136 23:06:51.922281 Vddq = 0
2137 23:06:51.922608 Vmddr = 0
2138 23:06:51.928291 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2139 23:06:51.931472 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2140 23:06:51.934610 MEM_TYPE=3, freq_sel=15
2141 23:06:51.937967 sv_algorithm_assistance_LP4_1600
2142 23:06:51.941223 ============ PULL DRAM RESETB DOWN ============
2143 23:06:51.944586 ========== PULL DRAM RESETB DOWN end =========
2144 23:06:51.951287 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2145 23:06:51.954448 ===================================
2146 23:06:51.954904 LPDDR4 DRAM CONFIGURATION
2147 23:06:51.957994 ===================================
2148 23:06:51.960709 EX_ROW_EN[0] = 0x0
2149 23:06:51.964265 EX_ROW_EN[1] = 0x0
2150 23:06:51.964744 LP4Y_EN = 0x0
2151 23:06:51.967358 WORK_FSP = 0x0
2152 23:06:51.967853 WL = 0x4
2153 23:06:51.971761 RL = 0x4
2154 23:06:51.972214 BL = 0x2
2155 23:06:51.975150 RPST = 0x0
2156 23:06:51.975750 RD_PRE = 0x0
2157 23:06:51.978509 WR_PRE = 0x1
2158 23:06:51.978961 WR_PST = 0x0
2159 23:06:51.981119 DBI_WR = 0x0
2160 23:06:51.981530 DBI_RD = 0x0
2161 23:06:51.985376 OTF = 0x1
2162 23:06:51.987524 ===================================
2163 23:06:51.991152 ===================================
2164 23:06:51.991750 ANA top config
2165 23:06:51.994473 ===================================
2166 23:06:51.997417 DLL_ASYNC_EN = 0
2167 23:06:52.001214 ALL_SLAVE_EN = 0
2168 23:06:52.004823 NEW_RANK_MODE = 1
2169 23:06:52.005380 DLL_IDLE_MODE = 1
2170 23:06:52.007942 LP45_APHY_COMB_EN = 1
2171 23:06:52.011244 TX_ODT_DIS = 1
2172 23:06:52.014568 NEW_8X_MODE = 1
2173 23:06:52.018349 ===================================
2174 23:06:52.021347 ===================================
2175 23:06:52.024640 data_rate = 2400
2176 23:06:52.025191 CKR = 1
2177 23:06:52.027726 DQ_P2S_RATIO = 8
2178 23:06:52.031382 ===================================
2179 23:06:52.035032 CA_P2S_RATIO = 8
2180 23:06:52.037976 DQ_CA_OPEN = 0
2181 23:06:52.041657 DQ_SEMI_OPEN = 0
2182 23:06:52.042210 CA_SEMI_OPEN = 0
2183 23:06:52.044315 CA_FULL_RATE = 0
2184 23:06:52.047268 DQ_CKDIV4_EN = 0
2185 23:06:52.051243 CA_CKDIV4_EN = 0
2186 23:06:52.054444 CA_PREDIV_EN = 0
2187 23:06:52.057732 PH8_DLY = 17
2188 23:06:52.060651 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2189 23:06:52.061112 DQ_AAMCK_DIV = 4
2190 23:06:52.064144 CA_AAMCK_DIV = 4
2191 23:06:52.067481 CA_ADMCK_DIV = 4
2192 23:06:52.070336 DQ_TRACK_CA_EN = 0
2193 23:06:52.074560 CA_PICK = 1200
2194 23:06:52.077679 CA_MCKIO = 1200
2195 23:06:52.078231 MCKIO_SEMI = 0
2196 23:06:52.080761 PLL_FREQ = 2366
2197 23:06:52.083843 DQ_UI_PI_RATIO = 32
2198 23:06:52.087522 CA_UI_PI_RATIO = 0
2199 23:06:52.090875 ===================================
2200 23:06:52.094147 ===================================
2201 23:06:52.098046 memory_type:LPDDR4
2202 23:06:52.098595 GP_NUM : 10
2203 23:06:52.100741 SRAM_EN : 1
2204 23:06:52.104630 MD32_EN : 0
2205 23:06:52.107584 ===================================
2206 23:06:52.108182 [ANA_INIT] >>>>>>>>>>>>>>
2207 23:06:52.110609 <<<<<< [CONFIGURE PHASE]: ANA_TX
2208 23:06:52.114711 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2209 23:06:52.117467 ===================================
2210 23:06:52.121024 data_rate = 2400,PCW = 0X5b00
2211 23:06:52.124125 ===================================
2212 23:06:52.126844 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2213 23:06:52.134517 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2214 23:06:52.137517 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2215 23:06:52.143933 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2216 23:06:52.147234 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2217 23:06:52.150739 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2218 23:06:52.153806 [ANA_INIT] flow start
2219 23:06:52.154487 [ANA_INIT] PLL >>>>>>>>
2220 23:06:52.157110 [ANA_INIT] PLL <<<<<<<<
2221 23:06:52.160024 [ANA_INIT] MIDPI >>>>>>>>
2222 23:06:52.160485 [ANA_INIT] MIDPI <<<<<<<<
2223 23:06:52.163758 [ANA_INIT] DLL >>>>>>>>
2224 23:06:52.166995 [ANA_INIT] DLL <<<<<<<<
2225 23:06:52.167547 [ANA_INIT] flow end
2226 23:06:52.174190 ============ LP4 DIFF to SE enter ============
2227 23:06:52.176926 ============ LP4 DIFF to SE exit ============
2228 23:06:52.177383 [ANA_INIT] <<<<<<<<<<<<<
2229 23:06:52.180260 [Flow] Enable top DCM control >>>>>
2230 23:06:52.183366 [Flow] Enable top DCM control <<<<<
2231 23:06:52.186513 Enable DLL master slave shuffle
2232 23:06:52.193058 ==============================================================
2233 23:06:52.196573 Gating Mode config
2234 23:06:52.200079 ==============================================================
2235 23:06:52.203365 Config description:
2236 23:06:52.213589 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2237 23:06:52.219965 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2238 23:06:52.223049 SELPH_MODE 0: By rank 1: By Phase
2239 23:06:52.230221 ==============================================================
2240 23:06:52.233006 GAT_TRACK_EN = 1
2241 23:06:52.236251 RX_GATING_MODE = 2
2242 23:06:52.239654 RX_GATING_TRACK_MODE = 2
2243 23:06:52.240161 SELPH_MODE = 1
2244 23:06:52.242792 PICG_EARLY_EN = 1
2245 23:06:52.246380 VALID_LAT_VALUE = 1
2246 23:06:52.252745 ==============================================================
2247 23:06:52.256037 Enter into Gating configuration >>>>
2248 23:06:52.259989 Exit from Gating configuration <<<<
2249 23:06:52.263126 Enter into DVFS_PRE_config >>>>>
2250 23:06:52.272918 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2251 23:06:52.276602 Exit from DVFS_PRE_config <<<<<
2252 23:06:52.279506 Enter into PICG configuration >>>>
2253 23:06:52.282489 Exit from PICG configuration <<<<
2254 23:06:52.286005 [RX_INPUT] configuration >>>>>
2255 23:06:52.289340 [RX_INPUT] configuration <<<<<
2256 23:06:52.293103 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2257 23:06:52.299380 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2258 23:06:52.305812 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2259 23:06:52.312537 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2260 23:06:52.318847 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2261 23:06:52.322925 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2262 23:06:52.329058 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2263 23:06:52.332523 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2264 23:06:52.335605 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2265 23:06:52.338826 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2266 23:06:52.345629 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2267 23:06:52.349282 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2268 23:06:52.352136 ===================================
2269 23:06:52.355583 LPDDR4 DRAM CONFIGURATION
2270 23:06:52.358736 ===================================
2271 23:06:52.359154 EX_ROW_EN[0] = 0x0
2272 23:06:52.362468 EX_ROW_EN[1] = 0x0
2273 23:06:52.362882 LP4Y_EN = 0x0
2274 23:06:52.365613 WORK_FSP = 0x0
2275 23:06:52.366125 WL = 0x4
2276 23:06:52.368523 RL = 0x4
2277 23:06:52.368943 BL = 0x2
2278 23:06:52.372299 RPST = 0x0
2279 23:06:52.372750 RD_PRE = 0x0
2280 23:06:52.375088 WR_PRE = 0x1
2281 23:06:52.375615 WR_PST = 0x0
2282 23:06:52.378761 DBI_WR = 0x0
2283 23:06:52.382400 DBI_RD = 0x0
2284 23:06:52.382810 OTF = 0x1
2285 23:06:52.385228 ===================================
2286 23:06:52.388374 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2287 23:06:52.392529 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2288 23:06:52.398949 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2289 23:06:52.402155 ===================================
2290 23:06:52.405527 LPDDR4 DRAM CONFIGURATION
2291 23:06:52.409002 ===================================
2292 23:06:52.409415 EX_ROW_EN[0] = 0x10
2293 23:06:52.411878 EX_ROW_EN[1] = 0x0
2294 23:06:52.412286 LP4Y_EN = 0x0
2295 23:06:52.415406 WORK_FSP = 0x0
2296 23:06:52.415802 WL = 0x4
2297 23:06:52.419018 RL = 0x4
2298 23:06:52.419424 BL = 0x2
2299 23:06:52.422037 RPST = 0x0
2300 23:06:52.422442 RD_PRE = 0x0
2301 23:06:52.425065 WR_PRE = 0x1
2302 23:06:52.425473 WR_PST = 0x0
2303 23:06:52.428679 DBI_WR = 0x0
2304 23:06:52.429090 DBI_RD = 0x0
2305 23:06:52.432059 OTF = 0x1
2306 23:06:52.435803 ===================================
2307 23:06:52.441585 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2308 23:06:52.441971 ==
2309 23:06:52.445281 Dram Type= 6, Freq= 0, CH_0, rank 0
2310 23:06:52.448420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2311 23:06:52.448718 ==
2312 23:06:52.451724 [Duty_Offset_Calibration]
2313 23:06:52.452015 B0:1 B1:-1 CA:0
2314 23:06:52.452246
2315 23:06:52.454961 [DutyScan_Calibration_Flow] k_type=0
2316 23:06:52.465672
2317 23:06:52.466023 ==CLK 0==
2318 23:06:52.469232 Final CLK duty delay cell = 0
2319 23:06:52.472089 [0] MAX Duty = 5125%(X100), DQS PI = 24
2320 23:06:52.475220 [0] MIN Duty = 4875%(X100), DQS PI = 8
2321 23:06:52.479648 [0] AVG Duty = 5000%(X100)
2322 23:06:52.480132
2323 23:06:52.482250 CH0 CLK Duty spec in!! Max-Min= 250%
2324 23:06:52.485488 [DutyScan_Calibration_Flow] ====Done====
2325 23:06:52.485939
2326 23:06:52.489043 [DutyScan_Calibration_Flow] k_type=1
2327 23:06:52.505117
2328 23:06:52.505682 ==DQS 0 ==
2329 23:06:52.507806 Final DQS duty delay cell = -4
2330 23:06:52.511184 [-4] MAX Duty = 5093%(X100), DQS PI = 16
2331 23:06:52.514987 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2332 23:06:52.518190 [-4] AVG Duty = 4984%(X100)
2333 23:06:52.518743
2334 23:06:52.519217 ==DQS 1 ==
2335 23:06:52.520843 Final DQS duty delay cell = 0
2336 23:06:52.524185 [0] MAX Duty = 5124%(X100), DQS PI = 4
2337 23:06:52.527222 [0] MIN Duty = 5000%(X100), DQS PI = 24
2338 23:06:52.531094 [0] AVG Duty = 5062%(X100)
2339 23:06:52.531726
2340 23:06:52.534499 CH0 DQS 0 Duty spec in!! Max-Min= 218%
2341 23:06:52.535058
2342 23:06:52.537635 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2343 23:06:52.540776 [DutyScan_Calibration_Flow] ====Done====
2344 23:06:52.541280
2345 23:06:52.544386 [DutyScan_Calibration_Flow] k_type=3
2346 23:06:52.561802
2347 23:06:52.562318 ==DQM 0 ==
2348 23:06:52.564913 Final DQM duty delay cell = 0
2349 23:06:52.568583 [0] MAX Duty = 5031%(X100), DQS PI = 16
2350 23:06:52.572243 [0] MIN Duty = 4875%(X100), DQS PI = 6
2351 23:06:52.575278 [0] AVG Duty = 4953%(X100)
2352 23:06:52.575833
2353 23:06:52.576197 ==DQM 1 ==
2354 23:06:52.578802 Final DQM duty delay cell = 4
2355 23:06:52.581568 [4] MAX Duty = 5187%(X100), DQS PI = 14
2356 23:06:52.585030 [4] MIN Duty = 5000%(X100), DQS PI = 24
2357 23:06:52.588955 [4] AVG Duty = 5093%(X100)
2358 23:06:52.589497
2359 23:06:52.592296 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2360 23:06:52.592748
2361 23:06:52.595364 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2362 23:06:52.598680 [DutyScan_Calibration_Flow] ====Done====
2363 23:06:52.599127
2364 23:06:52.601520 [DutyScan_Calibration_Flow] k_type=2
2365 23:06:52.617537
2366 23:06:52.618050 ==DQ 0 ==
2367 23:06:52.621034 Final DQ duty delay cell = -4
2368 23:06:52.624672 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2369 23:06:52.627614 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2370 23:06:52.630770 [-4] AVG Duty = 4969%(X100)
2371 23:06:52.631405
2372 23:06:52.631789 ==DQ 1 ==
2373 23:06:52.634626 Final DQ duty delay cell = 0
2374 23:06:52.637489 [0] MAX Duty = 5125%(X100), DQS PI = 50
2375 23:06:52.640571 [0] MIN Duty = 5000%(X100), DQS PI = 40
2376 23:06:52.644005 [0] AVG Duty = 5062%(X100)
2377 23:06:52.644671
2378 23:06:52.647400 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2379 23:06:52.647971
2380 23:06:52.650519 CH0 DQ 1 Duty spec in!! Max-Min= 125%
2381 23:06:52.654396 [DutyScan_Calibration_Flow] ====Done====
2382 23:06:52.655048 ==
2383 23:06:52.657395 Dram Type= 6, Freq= 0, CH_1, rank 0
2384 23:06:52.660750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2385 23:06:52.661300 ==
2386 23:06:52.664166 [Duty_Offset_Calibration]
2387 23:06:52.664616 B0:-1 B1:1 CA:2
2388 23:06:52.664943
2389 23:06:52.667059 [DutyScan_Calibration_Flow] k_type=0
2390 23:06:52.678414
2391 23:06:52.678930 ==CLK 0==
2392 23:06:52.682080 Final CLK duty delay cell = 0
2393 23:06:52.684315 [0] MAX Duty = 5156%(X100), DQS PI = 22
2394 23:06:52.687988 [0] MIN Duty = 4969%(X100), DQS PI = 60
2395 23:06:52.688486 [0] AVG Duty = 5062%(X100)
2396 23:06:52.691085
2397 23:06:52.694566 CH1 CLK Duty spec in!! Max-Min= 187%
2398 23:06:52.697957 [DutyScan_Calibration_Flow] ====Done====
2399 23:06:52.698368
2400 23:06:52.701354 [DutyScan_Calibration_Flow] k_type=1
2401 23:06:52.717539
2402 23:06:52.718119 ==DQS 0 ==
2403 23:06:52.720949 Final DQS duty delay cell = 0
2404 23:06:52.724056 [0] MAX Duty = 5125%(X100), DQS PI = 48
2405 23:06:52.727369 [0] MIN Duty = 4938%(X100), DQS PI = 6
2406 23:06:52.730536 [0] AVG Duty = 5031%(X100)
2407 23:06:52.731034
2408 23:06:52.731360 ==DQS 1 ==
2409 23:06:52.734046 Final DQS duty delay cell = 0
2410 23:06:52.737169 [0] MAX Duty = 5094%(X100), DQS PI = 10
2411 23:06:52.740499 [0] MIN Duty = 4969%(X100), DQS PI = 58
2412 23:06:52.743792 [0] AVG Duty = 5031%(X100)
2413 23:06:52.744199
2414 23:06:52.747181 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2415 23:06:52.747634
2416 23:06:52.750524 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2417 23:06:52.753441 [DutyScan_Calibration_Flow] ====Done====
2418 23:06:52.753986
2419 23:06:52.757293 [DutyScan_Calibration_Flow] k_type=3
2420 23:06:52.772743
2421 23:06:52.773363 ==DQM 0 ==
2422 23:06:52.776123 Final DQM duty delay cell = -4
2423 23:06:52.779397 [-4] MAX Duty = 5031%(X100), DQS PI = 16
2424 23:06:52.782710 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2425 23:06:52.786409 [-4] AVG Duty = 4953%(X100)
2426 23:06:52.786956
2427 23:06:52.787471 ==DQM 1 ==
2428 23:06:52.789349 Final DQM duty delay cell = 0
2429 23:06:52.793214 [0] MAX Duty = 5187%(X100), DQS PI = 4
2430 23:06:52.796221 [0] MIN Duty = 5000%(X100), DQS PI = 32
2431 23:06:52.799646 [0] AVG Duty = 5093%(X100)
2432 23:06:52.800223
2433 23:06:52.802955 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2434 23:06:52.803572
2435 23:06:52.806909 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2436 23:06:52.809861 [DutyScan_Calibration_Flow] ====Done====
2437 23:06:52.810385
2438 23:06:52.813328 [DutyScan_Calibration_Flow] k_type=2
2439 23:06:52.830357
2440 23:06:52.831028 ==DQ 0 ==
2441 23:06:52.833021 Final DQ duty delay cell = 0
2442 23:06:52.836278 [0] MAX Duty = 5218%(X100), DQS PI = 30
2443 23:06:52.840212 [0] MIN Duty = 4876%(X100), DQS PI = 8
2444 23:06:52.840691 [0] AVG Duty = 5047%(X100)
2445 23:06:52.841015
2446 23:06:52.842832 ==DQ 1 ==
2447 23:06:52.846228 Final DQ duty delay cell = 0
2448 23:06:52.849231 [0] MAX Duty = 5124%(X100), DQS PI = 10
2449 23:06:52.852701 [0] MIN Duty = 4969%(X100), DQS PI = 58
2450 23:06:52.853109 [0] AVG Duty = 5046%(X100)
2451 23:06:52.853479
2452 23:06:52.859402 CH1 DQ 0 Duty spec in!! Max-Min= 342%
2453 23:06:52.859946
2454 23:06:52.863433 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2455 23:06:52.865859 [DutyScan_Calibration_Flow] ====Done====
2456 23:06:52.869578 nWR fixed to 30
2457 23:06:52.869992 [ModeRegInit_LP4] CH0 RK0
2458 23:06:52.872410 [ModeRegInit_LP4] CH0 RK1
2459 23:06:52.875655 [ModeRegInit_LP4] CH1 RK0
2460 23:06:52.879596 [ModeRegInit_LP4] CH1 RK1
2461 23:06:52.880157 match AC timing 7
2462 23:06:52.885753 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2463 23:06:52.889002 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2464 23:06:52.892368 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2465 23:06:52.898996 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2466 23:06:52.902482 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2467 23:06:52.902959 ==
2468 23:06:52.905751 Dram Type= 6, Freq= 0, CH_0, rank 0
2469 23:06:52.908940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2470 23:06:52.909608 ==
2471 23:06:52.916066 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2472 23:06:52.922181 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2473 23:06:52.929814 [CA 0] Center 39 (9~70) winsize 62
2474 23:06:52.933822 [CA 1] Center 39 (9~69) winsize 61
2475 23:06:52.936329 [CA 2] Center 35 (5~66) winsize 62
2476 23:06:52.939475 [CA 3] Center 35 (5~66) winsize 62
2477 23:06:52.943421 [CA 4] Center 33 (4~63) winsize 60
2478 23:06:52.946814 [CA 5] Center 33 (3~63) winsize 61
2479 23:06:52.947508
2480 23:06:52.949274 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2481 23:06:52.949687
2482 23:06:52.953125 [CATrainingPosCal] consider 1 rank data
2483 23:06:52.956057 u2DelayCellTimex100 = 270/100 ps
2484 23:06:52.959455 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2485 23:06:52.962565 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2486 23:06:52.969452 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2487 23:06:52.972836 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2488 23:06:52.976142 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2489 23:06:52.979840 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2490 23:06:52.980258
2491 23:06:52.982906 CA PerBit enable=1, Macro0, CA PI delay=33
2492 23:06:52.983411
2493 23:06:52.985983 [CBTSetCACLKResult] CA Dly = 33
2494 23:06:52.986396 CS Dly: 8 (0~39)
2495 23:06:52.989262 ==
2496 23:06:52.992677 Dram Type= 6, Freq= 0, CH_0, rank 1
2497 23:06:52.996643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2498 23:06:52.997187 ==
2499 23:06:52.999120 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2500 23:06:53.006036 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2501 23:06:53.015528 [CA 0] Center 39 (9~70) winsize 62
2502 23:06:53.019081 [CA 1] Center 39 (9~70) winsize 62
2503 23:06:53.021758 [CA 2] Center 35 (5~66) winsize 62
2504 23:06:53.025402 [CA 3] Center 34 (4~65) winsize 62
2505 23:06:53.028651 [CA 4] Center 33 (3~64) winsize 62
2506 23:06:53.032602 [CA 5] Center 33 (3~63) winsize 61
2507 23:06:53.033129
2508 23:06:53.035291 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2509 23:06:53.035929
2510 23:06:53.038863 [CATrainingPosCal] consider 2 rank data
2511 23:06:53.041689 u2DelayCellTimex100 = 270/100 ps
2512 23:06:53.044989 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2513 23:06:53.051640 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2514 23:06:53.055137 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2515 23:06:53.058249 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2516 23:06:53.061712 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2517 23:06:53.065111 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2518 23:06:53.065524
2519 23:06:53.068797 CA PerBit enable=1, Macro0, CA PI delay=33
2520 23:06:53.069276
2521 23:06:53.072139 [CBTSetCACLKResult] CA Dly = 33
2522 23:06:53.072552 CS Dly: 9 (0~41)
2523 23:06:53.072879
2524 23:06:53.074931 ----->DramcWriteLeveling(PI) begin...
2525 23:06:53.078564 ==
2526 23:06:53.081752 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 23:06:53.084920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 23:06:53.085340 ==
2529 23:06:53.088314 Write leveling (Byte 0): 32 => 32
2530 23:06:53.091747 Write leveling (Byte 1): 29 => 29
2531 23:06:53.094711 DramcWriteLeveling(PI) end<-----
2532 23:06:53.095124
2533 23:06:53.095455 ==
2534 23:06:53.098971 Dram Type= 6, Freq= 0, CH_0, rank 0
2535 23:06:53.101478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2536 23:06:53.101913 ==
2537 23:06:53.104810 [Gating] SW mode calibration
2538 23:06:53.111806 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2539 23:06:53.118079 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2540 23:06:53.121160 0 15 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2541 23:06:53.124746 0 15 4 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
2542 23:06:53.131102 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 23:06:53.134773 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 23:06:53.137929 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 23:06:53.144432 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 23:06:53.147739 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2547 23:06:53.151706 0 15 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
2548 23:06:53.158454 1 0 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
2549 23:06:53.160819 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 23:06:53.164222 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 23:06:53.170994 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 23:06:53.174158 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 23:06:53.177567 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 23:06:53.184473 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 23:06:53.187388 1 0 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2556 23:06:53.191439 1 1 0 | B1->B0 | 2726 4545 | 1 0 | (0 0) (0 0)
2557 23:06:53.194648 1 1 4 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
2558 23:06:53.200519 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 23:06:53.204618 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 23:06:53.210732 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 23:06:53.213767 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 23:06:53.217267 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 23:06:53.224359 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2564 23:06:53.227353 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2565 23:06:53.230935 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 23:06:53.233856 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 23:06:53.240405 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 23:06:53.243527 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 23:06:53.247498 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 23:06:53.253687 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 23:06:53.257294 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 23:06:53.260214 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 23:06:53.267799 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 23:06:53.270406 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 23:06:53.273290 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 23:06:53.280982 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 23:06:53.283817 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 23:06:53.286750 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 23:06:53.293653 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2580 23:06:53.297140 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2581 23:06:53.300239 Total UI for P1: 0, mck2ui 16
2582 23:06:53.303338 best dqsien dly found for B0: ( 1, 3, 28)
2583 23:06:53.306579 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2584 23:06:53.313499 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 23:06:53.314043 Total UI for P1: 0, mck2ui 16
2586 23:06:53.319989 best dqsien dly found for B1: ( 1, 4, 2)
2587 23:06:53.323715 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2588 23:06:53.326755 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2589 23:06:53.327270
2590 23:06:53.329614 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2591 23:06:53.333508 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2592 23:06:53.336718 [Gating] SW calibration Done
2593 23:06:53.337132 ==
2594 23:06:53.339784 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 23:06:53.343031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 23:06:53.343445 ==
2597 23:06:53.346537 RX Vref Scan: 0
2598 23:06:53.347052
2599 23:06:53.347383 RX Vref 0 -> 0, step: 1
2600 23:06:53.347726
2601 23:06:53.350122 RX Delay -40 -> 252, step: 8
2602 23:06:53.353348 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2603 23:06:53.359401 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2604 23:06:53.362970 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2605 23:06:53.366630 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2606 23:06:53.369163 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2607 23:06:53.372999 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2608 23:06:53.379529 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2609 23:06:53.382841 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2610 23:06:53.386489 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2611 23:06:53.389057 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2612 23:06:53.392722 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2613 23:06:53.399253 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2614 23:06:53.402453 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2615 23:06:53.405961 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2616 23:06:53.409677 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2617 23:06:53.416076 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2618 23:06:53.416530 ==
2619 23:06:53.418862 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 23:06:53.422636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 23:06:53.423053 ==
2622 23:06:53.423381 DQS Delay:
2623 23:06:53.425838 DQS0 = 0, DQS1 = 0
2624 23:06:53.426385 DQM Delay:
2625 23:06:53.429408 DQM0 = 119, DQM1 = 107
2626 23:06:53.429962 DQ Delay:
2627 23:06:53.432385 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2628 23:06:53.435546 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2629 23:06:53.438973 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2630 23:06:53.442059 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2631 23:06:53.442456
2632 23:06:53.442808
2633 23:06:53.445568 ==
2634 23:06:53.448445 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 23:06:53.451649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 23:06:53.451953 ==
2637 23:06:53.452184
2638 23:06:53.452397
2639 23:06:53.455351 TX Vref Scan disable
2640 23:06:53.455776 == TX Byte 0 ==
2641 23:06:53.459139 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2642 23:06:53.465389 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2643 23:06:53.465812 == TX Byte 1 ==
2644 23:06:53.468403 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2645 23:06:53.475413 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2646 23:06:53.475958 ==
2647 23:06:53.478370 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 23:06:53.482023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 23:06:53.482467 ==
2650 23:06:53.494314 TX Vref=22, minBit 1, minWin=25, winSum=421
2651 23:06:53.497600 TX Vref=24, minBit 1, minWin=25, winSum=426
2652 23:06:53.500774 TX Vref=26, minBit 4, minWin=26, winSum=433
2653 23:06:53.504583 TX Vref=28, minBit 1, minWin=26, winSum=433
2654 23:06:53.508484 TX Vref=30, minBit 14, minWin=26, winSum=436
2655 23:06:53.514383 TX Vref=32, minBit 4, minWin=26, winSum=427
2656 23:06:53.517631 [TxChooseVref] Worse bit 14, Min win 26, Win sum 436, Final Vref 30
2657 23:06:53.518052
2658 23:06:53.520718 Final TX Range 1 Vref 30
2659 23:06:53.521135
2660 23:06:53.521464 ==
2661 23:06:53.524217 Dram Type= 6, Freq= 0, CH_0, rank 0
2662 23:06:53.527624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2663 23:06:53.530668 ==
2664 23:06:53.531179
2665 23:06:53.531511
2666 23:06:53.531870 TX Vref Scan disable
2667 23:06:53.534340 == TX Byte 0 ==
2668 23:06:53.537432 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2669 23:06:53.544375 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2670 23:06:53.545164 == TX Byte 1 ==
2671 23:06:53.547708 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2672 23:06:53.554626 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2673 23:06:53.555277
2674 23:06:53.555735 [DATLAT]
2675 23:06:53.556151 Freq=1200, CH0 RK0
2676 23:06:53.556589
2677 23:06:53.557310 DATLAT Default: 0xd
2678 23:06:53.557652 0, 0xFFFF, sum = 0
2679 23:06:53.561168 1, 0xFFFF, sum = 0
2680 23:06:53.561603 2, 0xFFFF, sum = 0
2681 23:06:53.564140 3, 0xFFFF, sum = 0
2682 23:06:53.567228 4, 0xFFFF, sum = 0
2683 23:06:53.567655 5, 0xFFFF, sum = 0
2684 23:06:53.570430 6, 0xFFFF, sum = 0
2685 23:06:53.570848 7, 0xFFFF, sum = 0
2686 23:06:53.573805 8, 0xFFFF, sum = 0
2687 23:06:53.574239 9, 0xFFFF, sum = 0
2688 23:06:53.577313 10, 0xFFFF, sum = 0
2689 23:06:53.577736 11, 0xFFFF, sum = 0
2690 23:06:53.580280 12, 0x0, sum = 1
2691 23:06:53.580701 13, 0x0, sum = 2
2692 23:06:53.583721 14, 0x0, sum = 3
2693 23:06:53.584147 15, 0x0, sum = 4
2694 23:06:53.584480 best_step = 13
2695 23:06:53.587094
2696 23:06:53.587508 ==
2697 23:06:53.590610 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 23:06:53.593598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 23:06:53.594022 ==
2700 23:06:53.594351 RX Vref Scan: 1
2701 23:06:53.594663
2702 23:06:53.597021 Set Vref Range= 32 -> 127
2703 23:06:53.597437
2704 23:06:53.600496 RX Vref 32 -> 127, step: 1
2705 23:06:53.600909
2706 23:06:53.603967 RX Delay -21 -> 252, step: 4
2707 23:06:53.604387
2708 23:06:53.606833 Set Vref, RX VrefLevel [Byte0]: 32
2709 23:06:53.610651 [Byte1]: 32
2710 23:06:53.611067
2711 23:06:53.613642 Set Vref, RX VrefLevel [Byte0]: 33
2712 23:06:53.617118 [Byte1]: 33
2713 23:06:53.620628
2714 23:06:53.621056 Set Vref, RX VrefLevel [Byte0]: 34
2715 23:06:53.624033 [Byte1]: 34
2716 23:06:53.628595
2717 23:06:53.629114 Set Vref, RX VrefLevel [Byte0]: 35
2718 23:06:53.632233 [Byte1]: 35
2719 23:06:53.636723
2720 23:06:53.637242 Set Vref, RX VrefLevel [Byte0]: 36
2721 23:06:53.640046 [Byte1]: 36
2722 23:06:53.644218
2723 23:06:53.644741 Set Vref, RX VrefLevel [Byte0]: 37
2724 23:06:53.648091 [Byte1]: 37
2725 23:06:53.652619
2726 23:06:53.653128 Set Vref, RX VrefLevel [Byte0]: 38
2727 23:06:53.655746 [Byte1]: 38
2728 23:06:53.660389
2729 23:06:53.660831 Set Vref, RX VrefLevel [Byte0]: 39
2730 23:06:53.663136 [Byte1]: 39
2731 23:06:53.668688
2732 23:06:53.669251 Set Vref, RX VrefLevel [Byte0]: 40
2733 23:06:53.671825 [Byte1]: 40
2734 23:06:53.676207
2735 23:06:53.676763 Set Vref, RX VrefLevel [Byte0]: 41
2736 23:06:53.679891 [Byte1]: 41
2737 23:06:53.684686
2738 23:06:53.685245 Set Vref, RX VrefLevel [Byte0]: 42
2739 23:06:53.687210 [Byte1]: 42
2740 23:06:53.691917
2741 23:06:53.692441 Set Vref, RX VrefLevel [Byte0]: 43
2742 23:06:53.695043 [Byte1]: 43
2743 23:06:53.699626
2744 23:06:53.700127 Set Vref, RX VrefLevel [Byte0]: 44
2745 23:06:53.703441 [Byte1]: 44
2746 23:06:53.708164
2747 23:06:53.708769 Set Vref, RX VrefLevel [Byte0]: 45
2748 23:06:53.711798 [Byte1]: 45
2749 23:06:53.716116
2750 23:06:53.716602 Set Vref, RX VrefLevel [Byte0]: 46
2751 23:06:53.719040 [Byte1]: 46
2752 23:06:53.723453
2753 23:06:53.723904 Set Vref, RX VrefLevel [Byte0]: 47
2754 23:06:53.730251 [Byte1]: 47
2755 23:06:53.730666
2756 23:06:53.733550 Set Vref, RX VrefLevel [Byte0]: 48
2757 23:06:53.736714 [Byte1]: 48
2758 23:06:53.737129
2759 23:06:53.740162 Set Vref, RX VrefLevel [Byte0]: 49
2760 23:06:53.742822 [Byte1]: 49
2761 23:06:53.747077
2762 23:06:53.747489 Set Vref, RX VrefLevel [Byte0]: 50
2763 23:06:53.750951 [Byte1]: 50
2764 23:06:53.755235
2765 23:06:53.755810 Set Vref, RX VrefLevel [Byte0]: 51
2766 23:06:53.758778 [Byte1]: 51
2767 23:06:53.763353
2768 23:06:53.763796 Set Vref, RX VrefLevel [Byte0]: 52
2769 23:06:53.766440 [Byte1]: 52
2770 23:06:53.770673
2771 23:06:53.771092 Set Vref, RX VrefLevel [Byte0]: 53
2772 23:06:53.774284 [Byte1]: 53
2773 23:06:53.779221
2774 23:06:53.779633 Set Vref, RX VrefLevel [Byte0]: 54
2775 23:06:53.782648 [Byte1]: 54
2776 23:06:53.786762
2777 23:06:53.787191 Set Vref, RX VrefLevel [Byte0]: 55
2778 23:06:53.790237 [Byte1]: 55
2779 23:06:53.795142
2780 23:06:53.795569 Set Vref, RX VrefLevel [Byte0]: 56
2781 23:06:53.798321 [Byte1]: 56
2782 23:06:53.803110
2783 23:06:53.803523 Set Vref, RX VrefLevel [Byte0]: 57
2784 23:06:53.805897 [Byte1]: 57
2785 23:06:53.810745
2786 23:06:53.811163 Set Vref, RX VrefLevel [Byte0]: 58
2787 23:06:53.814206 [Byte1]: 58
2788 23:06:53.818541
2789 23:06:53.818954 Set Vref, RX VrefLevel [Byte0]: 59
2790 23:06:53.822633 [Byte1]: 59
2791 23:06:53.826725
2792 23:06:53.827135 Set Vref, RX VrefLevel [Byte0]: 60
2793 23:06:53.830279 [Byte1]: 60
2794 23:06:53.834649
2795 23:06:53.835062 Set Vref, RX VrefLevel [Byte0]: 61
2796 23:06:53.837554 [Byte1]: 61
2797 23:06:53.842498
2798 23:06:53.842910 Set Vref, RX VrefLevel [Byte0]: 62
2799 23:06:53.845666 [Byte1]: 62
2800 23:06:53.850338
2801 23:06:53.850751 Set Vref, RX VrefLevel [Byte0]: 63
2802 23:06:53.853833 [Byte1]: 63
2803 23:06:53.858590
2804 23:06:53.859002 Set Vref, RX VrefLevel [Byte0]: 64
2805 23:06:53.861263 [Byte1]: 64
2806 23:06:53.865735
2807 23:06:53.866287 Set Vref, RX VrefLevel [Byte0]: 65
2808 23:06:53.869215 [Byte1]: 65
2809 23:06:53.874121
2810 23:06:53.874571 Set Vref, RX VrefLevel [Byte0]: 66
2811 23:06:53.876979 [Byte1]: 66
2812 23:06:53.881941
2813 23:06:53.882264 Set Vref, RX VrefLevel [Byte0]: 67
2814 23:06:53.884964 [Byte1]: 67
2815 23:06:53.889733
2816 23:06:53.889956 Set Vref, RX VrefLevel [Byte0]: 68
2817 23:06:53.892983 [Byte1]: 68
2818 23:06:53.897962
2819 23:06:53.898142 Set Vref, RX VrefLevel [Byte0]: 69
2820 23:06:53.900995 [Byte1]: 69
2821 23:06:53.905319
2822 23:06:53.905497 Set Vref, RX VrefLevel [Byte0]: 70
2823 23:06:53.909220 [Byte1]: 70
2824 23:06:53.913618
2825 23:06:53.913797 Set Vref, RX VrefLevel [Byte0]: 71
2826 23:06:53.917418 [Byte1]: 71
2827 23:06:53.921690
2828 23:06:53.921960 Set Vref, RX VrefLevel [Byte0]: 72
2829 23:06:53.927963 [Byte1]: 72
2830 23:06:53.928213
2831 23:06:53.931059 Set Vref, RX VrefLevel [Byte0]: 73
2832 23:06:53.934325 [Byte1]: 73
2833 23:06:53.934508
2834 23:06:53.938120 Set Vref, RX VrefLevel [Byte0]: 74
2835 23:06:53.941019 [Byte1]: 74
2836 23:06:53.945463
2837 23:06:53.945721 Set Vref, RX VrefLevel [Byte0]: 75
2838 23:06:53.948564 [Byte1]: 75
2839 23:06:53.954210
2840 23:06:53.954726 Set Vref, RX VrefLevel [Byte0]: 76
2841 23:06:53.956693 [Byte1]: 76
2842 23:06:53.961052
2843 23:06:53.961469 Set Vref, RX VrefLevel [Byte0]: 77
2844 23:06:53.964916 [Byte1]: 77
2845 23:06:53.969208
2846 23:06:53.969758 Final RX Vref Byte 0 = 59 to rank0
2847 23:06:53.972699 Final RX Vref Byte 1 = 48 to rank0
2848 23:06:53.975970 Final RX Vref Byte 0 = 59 to rank1
2849 23:06:53.979474 Final RX Vref Byte 1 = 48 to rank1==
2850 23:06:53.982559 Dram Type= 6, Freq= 0, CH_0, rank 0
2851 23:06:53.989746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2852 23:06:53.990165 ==
2853 23:06:53.990494 DQS Delay:
2854 23:06:53.992542 DQS0 = 0, DQS1 = 0
2855 23:06:53.993007 DQM Delay:
2856 23:06:53.993341 DQM0 = 119, DQM1 = 106
2857 23:06:53.995556 DQ Delay:
2858 23:06:53.999527 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =114
2859 23:06:54.002198 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =128
2860 23:06:54.006078 DQ8 =98, DQ9 =92, DQ10 =108, DQ11 =100
2861 23:06:54.008585 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116
2862 23:06:54.009005
2863 23:06:54.009333
2864 23:06:54.019002 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 403 ps
2865 23:06:54.019541 CH0 RK0: MR19=403, MR18=12FE
2866 23:06:54.025571 CH0_RK0: MR19=0x403, MR18=0x12FE, DQSOSC=403, MR23=63, INC=40, DEC=26
2867 23:06:54.026215
2868 23:06:54.028624 ----->DramcWriteLeveling(PI) begin...
2869 23:06:54.029065 ==
2870 23:06:54.032296 Dram Type= 6, Freq= 0, CH_0, rank 1
2871 23:06:54.038611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2872 23:06:54.039146 ==
2873 23:06:54.042238 Write leveling (Byte 0): 32 => 32
2874 23:06:54.042822 Write leveling (Byte 1): 31 => 31
2875 23:06:54.045478 DramcWriteLeveling(PI) end<-----
2876 23:06:54.045938
2877 23:06:54.048847 ==
2878 23:06:54.049346 Dram Type= 6, Freq= 0, CH_0, rank 1
2879 23:06:54.055515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2880 23:06:54.056027 ==
2881 23:06:54.058539 [Gating] SW mode calibration
2882 23:06:54.065436 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2883 23:06:54.068352 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2884 23:06:54.075343 0 15 0 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
2885 23:06:54.078437 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
2886 23:06:54.081426 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2887 23:06:54.088229 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2888 23:06:54.091430 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2889 23:06:54.094952 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2890 23:06:54.101895 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2891 23:06:54.105398 0 15 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2892 23:06:54.108220 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2893 23:06:54.114817 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2894 23:06:54.118070 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 23:06:54.121727 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 23:06:54.128341 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2897 23:06:54.131422 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2898 23:06:54.134860 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2899 23:06:54.141363 1 0 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2900 23:06:54.144731 1 1 0 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
2901 23:06:54.148124 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 23:06:54.151767 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 23:06:54.158078 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 23:06:54.161299 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 23:06:54.164889 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 23:06:54.171824 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 23:06:54.174800 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2908 23:06:54.178469 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2909 23:06:54.185091 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 23:06:54.188465 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 23:06:54.191434 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 23:06:54.198890 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 23:06:54.201474 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 23:06:54.204987 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 23:06:54.211777 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 23:06:54.215260 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 23:06:54.217864 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 23:06:54.225291 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 23:06:54.227835 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 23:06:54.231332 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 23:06:54.238201 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 23:06:54.240986 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 23:06:54.244281 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2924 23:06:54.250973 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 23:06:54.251517 Total UI for P1: 0, mck2ui 16
2926 23:06:54.257537 best dqsien dly found for B0: ( 1, 3, 28)
2927 23:06:54.258115 Total UI for P1: 0, mck2ui 16
2928 23:06:54.264240 best dqsien dly found for B1: ( 1, 3, 30)
2929 23:06:54.267463 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2930 23:06:54.271620 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2931 23:06:54.272258
2932 23:06:54.274029 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2933 23:06:54.277803 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2934 23:06:54.280732 [Gating] SW calibration Done
2935 23:06:54.281192 ==
2936 23:06:54.284385 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 23:06:54.287774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 23:06:54.288301 ==
2939 23:06:54.291399 RX Vref Scan: 0
2940 23:06:54.292068
2941 23:06:54.292538 RX Vref 0 -> 0, step: 1
2942 23:06:54.292940
2943 23:06:54.294215 RX Delay -40 -> 252, step: 8
2944 23:06:54.297481 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2945 23:06:54.304236 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2946 23:06:54.307390 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2947 23:06:54.310524 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2948 23:06:54.314175 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2949 23:06:54.317044 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2950 23:06:54.324332 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2951 23:06:54.327105 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2952 23:06:54.330437 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2953 23:06:54.333294 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2954 23:06:54.336827 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2955 23:06:54.343618 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2956 23:06:54.346744 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2957 23:06:54.349797 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2958 23:06:54.353687 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2959 23:06:54.360007 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2960 23:06:54.360425 ==
2961 23:06:54.363541 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 23:06:54.366273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 23:06:54.366786 ==
2964 23:06:54.367187 DQS Delay:
2965 23:06:54.369742 DQS0 = 0, DQS1 = 0
2966 23:06:54.370374 DQM Delay:
2967 23:06:54.373179 DQM0 = 117, DQM1 = 108
2968 23:06:54.373666 DQ Delay:
2969 23:06:54.376175 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
2970 23:06:54.379784 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2971 23:06:54.383049 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2972 23:06:54.386393 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
2973 23:06:54.386943
2974 23:06:54.387409
2975 23:06:54.389828 ==
2976 23:06:54.390243 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 23:06:54.396236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 23:06:54.396656 ==
2979 23:06:54.397001
2980 23:06:54.397305
2981 23:06:54.399656 TX Vref Scan disable
2982 23:06:54.400121 == TX Byte 0 ==
2983 23:06:54.402707 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2984 23:06:54.409761 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2985 23:06:54.410194 == TX Byte 1 ==
2986 23:06:54.412845 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2987 23:06:54.419927 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2988 23:06:54.420352 ==
2989 23:06:54.422833 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 23:06:54.426173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 23:06:54.426565 ==
2992 23:06:54.437966 TX Vref=22, minBit 5, minWin=25, winSum=427
2993 23:06:54.441369 TX Vref=24, minBit 1, minWin=26, winSum=429
2994 23:06:54.445942 TX Vref=26, minBit 1, minWin=26, winSum=431
2995 23:06:54.448448 TX Vref=28, minBit 13, minWin=26, winSum=435
2996 23:06:54.451495 TX Vref=30, minBit 11, minWin=26, winSum=432
2997 23:06:54.458421 TX Vref=32, minBit 11, minWin=26, winSum=430
2998 23:06:54.461590 [TxChooseVref] Worse bit 13, Min win 26, Win sum 435, Final Vref 28
2999 23:06:54.462012
3000 23:06:54.464932 Final TX Range 1 Vref 28
3001 23:06:54.465354
3002 23:06:54.465683 ==
3003 23:06:54.468086 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 23:06:54.471536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 23:06:54.474960 ==
3006 23:06:54.475415
3007 23:06:54.475792
3008 23:06:54.476110 TX Vref Scan disable
3009 23:06:54.477996 == TX Byte 0 ==
3010 23:06:54.481549 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3011 23:06:54.488353 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3012 23:06:54.488858 == TX Byte 1 ==
3013 23:06:54.491835 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3014 23:06:54.497752 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3015 23:06:54.498310
3016 23:06:54.498785 [DATLAT]
3017 23:06:54.499258 Freq=1200, CH0 RK1
3018 23:06:54.499630
3019 23:06:54.501431 DATLAT Default: 0xd
3020 23:06:54.501875 0, 0xFFFF, sum = 0
3021 23:06:54.504844 1, 0xFFFF, sum = 0
3022 23:06:54.508625 2, 0xFFFF, sum = 0
3023 23:06:54.509052 3, 0xFFFF, sum = 0
3024 23:06:54.511195 4, 0xFFFF, sum = 0
3025 23:06:54.511813 5, 0xFFFF, sum = 0
3026 23:06:54.514812 6, 0xFFFF, sum = 0
3027 23:06:54.515286 7, 0xFFFF, sum = 0
3028 23:06:54.517773 8, 0xFFFF, sum = 0
3029 23:06:54.518199 9, 0xFFFF, sum = 0
3030 23:06:54.521064 10, 0xFFFF, sum = 0
3031 23:06:54.521488 11, 0xFFFF, sum = 0
3032 23:06:54.524475 12, 0x0, sum = 1
3033 23:06:54.525035 13, 0x0, sum = 2
3034 23:06:54.528115 14, 0x0, sum = 3
3035 23:06:54.528799 15, 0x0, sum = 4
3036 23:06:54.531324 best_step = 13
3037 23:06:54.531429
3038 23:06:54.531494 ==
3039 23:06:54.534653 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 23:06:54.538079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 23:06:54.538161 ==
3042 23:06:54.538225 RX Vref Scan: 0
3043 23:06:54.538285
3044 23:06:54.541937 RX Vref 0 -> 0, step: 1
3045 23:06:54.542018
3046 23:06:54.544416 RX Delay -21 -> 252, step: 4
3047 23:06:54.547374 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3048 23:06:54.554234 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3049 23:06:54.557450 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3050 23:06:54.560820 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3051 23:06:54.564050 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3052 23:06:54.567910 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3053 23:06:54.574071 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3054 23:06:54.577944 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3055 23:06:54.580599 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3056 23:06:54.584549 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3057 23:06:54.587181 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3058 23:06:54.594162 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3059 23:06:54.597226 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3060 23:06:54.601092 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3061 23:06:54.603877 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3062 23:06:54.607218 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3063 23:06:54.610623 ==
3064 23:06:54.614103 Dram Type= 6, Freq= 0, CH_0, rank 1
3065 23:06:54.617254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3066 23:06:54.617401 ==
3067 23:06:54.617571 DQS Delay:
3068 23:06:54.620455 DQS0 = 0, DQS1 = 0
3069 23:06:54.620592 DQM Delay:
3070 23:06:54.623709 DQM0 = 116, DQM1 = 107
3071 23:06:54.623870 DQ Delay:
3072 23:06:54.627236 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3073 23:06:54.630851 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3074 23:06:54.634619 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3075 23:06:54.637475 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3076 23:06:54.637749
3077 23:06:54.637967
3078 23:06:54.647355 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe5, (MSB)MR19= 0x403, tDQSOscB0 = 421 ps tDQSOscB1 = 405 ps
3079 23:06:54.647791 CH0 RK1: MR19=403, MR18=BE5
3080 23:06:54.654356 CH0_RK1: MR19=0x403, MR18=0xBE5, DQSOSC=405, MR23=63, INC=39, DEC=26
3081 23:06:54.657009 [RxdqsGatingPostProcess] freq 1200
3082 23:06:54.663574 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3083 23:06:54.666543 best DQS0 dly(2T, 0.5T) = (0, 11)
3084 23:06:54.670641 best DQS1 dly(2T, 0.5T) = (0, 12)
3085 23:06:54.673891 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3086 23:06:54.677001 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3087 23:06:54.680202 best DQS0 dly(2T, 0.5T) = (0, 11)
3088 23:06:54.683583 best DQS1 dly(2T, 0.5T) = (0, 11)
3089 23:06:54.686642 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3090 23:06:54.690252 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3091 23:06:54.690333 Pre-setting of DQS Precalculation
3092 23:06:54.696548 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3093 23:06:54.696636 ==
3094 23:06:54.700836 Dram Type= 6, Freq= 0, CH_1, rank 0
3095 23:06:54.703733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 23:06:54.703899 ==
3097 23:06:54.710330 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3098 23:06:54.716609 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3099 23:06:54.724188 [CA 0] Center 37 (7~67) winsize 61
3100 23:06:54.727746 [CA 1] Center 38 (8~68) winsize 61
3101 23:06:54.730841 [CA 2] Center 34 (4~64) winsize 61
3102 23:06:54.734963 [CA 3] Center 33 (3~64) winsize 62
3103 23:06:54.738084 [CA 4] Center 34 (4~64) winsize 61
3104 23:06:54.741533 [CA 5] Center 33 (3~64) winsize 62
3105 23:06:54.741857
3106 23:06:54.744437 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3107 23:06:54.744764
3108 23:06:54.748191 [CATrainingPosCal] consider 1 rank data
3109 23:06:54.751350 u2DelayCellTimex100 = 270/100 ps
3110 23:06:54.754508 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3111 23:06:54.761441 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3112 23:06:54.764325 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3113 23:06:54.767511 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3114 23:06:54.771042 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3115 23:06:54.774770 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3116 23:06:54.775235
3117 23:06:54.778157 CA PerBit enable=1, Macro0, CA PI delay=33
3118 23:06:54.778711
3119 23:06:54.781482 [CBTSetCACLKResult] CA Dly = 33
3120 23:06:54.781939 CS Dly: 5 (0~36)
3121 23:06:54.784291 ==
3122 23:06:54.787654 Dram Type= 6, Freq= 0, CH_1, rank 1
3123 23:06:54.791331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 23:06:54.791967 ==
3125 23:06:54.794176 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3126 23:06:54.800915 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3127 23:06:54.810256 [CA 0] Center 37 (7~68) winsize 62
3128 23:06:54.813774 [CA 1] Center 38 (8~68) winsize 61
3129 23:06:54.816959 [CA 2] Center 34 (4~65) winsize 62
3130 23:06:54.820277 [CA 3] Center 33 (3~64) winsize 62
3131 23:06:54.823565 [CA 4] Center 34 (3~65) winsize 63
3132 23:06:54.827315 [CA 5] Center 33 (3~64) winsize 62
3133 23:06:54.827922
3134 23:06:54.830521 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3135 23:06:54.831063
3136 23:06:54.833326 [CATrainingPosCal] consider 2 rank data
3137 23:06:54.837230 u2DelayCellTimex100 = 270/100 ps
3138 23:06:54.840052 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3139 23:06:54.843307 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3140 23:06:54.849770 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3141 23:06:54.853587 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3142 23:06:54.857652 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3143 23:06:54.860401 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3144 23:06:54.860953
3145 23:06:54.863792 CA PerBit enable=1, Macro0, CA PI delay=33
3146 23:06:54.864591
3147 23:06:54.866496 [CBTSetCACLKResult] CA Dly = 33
3148 23:06:54.866953 CS Dly: 7 (0~40)
3149 23:06:54.870465
3150 23:06:54.873224 ----->DramcWriteLeveling(PI) begin...
3151 23:06:54.873690 ==
3152 23:06:54.876761 Dram Type= 6, Freq= 0, CH_1, rank 0
3153 23:06:54.879470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3154 23:06:54.880065 ==
3155 23:06:54.883273 Write leveling (Byte 0): 25 => 25
3156 23:06:54.886284 Write leveling (Byte 1): 28 => 28
3157 23:06:54.889202 DramcWriteLeveling(PI) end<-----
3158 23:06:54.889885
3159 23:06:54.890472 ==
3160 23:06:54.893021 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 23:06:54.896142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 23:06:54.896727 ==
3163 23:06:54.899220 [Gating] SW mode calibration
3164 23:06:54.905838 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3165 23:06:54.912876 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3166 23:06:54.915868 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3167 23:06:54.919494 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 23:06:54.926123 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 23:06:54.929335 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3170 23:06:54.932477 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3171 23:06:54.939233 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3172 23:06:54.942408 0 15 24 | B1->B0 | 3434 2c2c | 0 1 | (0 0) (1 0)
3173 23:06:54.946143 0 15 28 | B1->B0 | 2626 2323 | 1 0 | (1 0) (1 0)
3174 23:06:54.952311 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3175 23:06:54.955807 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 23:06:54.959500 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 23:06:54.966036 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3178 23:06:54.969174 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3179 23:06:54.972617 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 23:06:54.979339 1 0 24 | B1->B0 | 2626 3737 | 1 1 | (0 0) (0 0)
3181 23:06:54.982928 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3182 23:06:54.985642 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 23:06:54.989427 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 23:06:54.996439 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 23:06:54.999026 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 23:06:55.002214 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 23:06:55.008748 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 23:06:55.012326 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3189 23:06:55.015543 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3190 23:06:55.022376 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 23:06:55.026928 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 23:06:55.029182 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 23:06:55.035966 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 23:06:55.039219 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 23:06:55.041790 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 23:06:55.048557 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 23:06:55.052040 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 23:06:55.056293 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 23:06:55.061795 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 23:06:55.065835 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 23:06:55.069291 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 23:06:55.075155 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 23:06:55.078986 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 23:06:55.081774 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3205 23:06:55.088377 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3206 23:06:55.088810 Total UI for P1: 0, mck2ui 16
3207 23:06:55.094944 best dqsien dly found for B0: ( 1, 3, 24)
3208 23:06:55.098827 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3209 23:06:55.101513 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 23:06:55.105247 Total UI for P1: 0, mck2ui 16
3211 23:06:55.108416 best dqsien dly found for B1: ( 1, 3, 28)
3212 23:06:55.112087 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3213 23:06:55.115993 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3214 23:06:55.116444
3215 23:06:55.118405 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3216 23:06:55.124951 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3217 23:06:55.125362 [Gating] SW calibration Done
3218 23:06:55.128271 ==
3219 23:06:55.128680 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 23:06:55.134922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3221 23:06:55.135338 ==
3222 23:06:55.135660 RX Vref Scan: 0
3223 23:06:55.136022
3224 23:06:55.138020 RX Vref 0 -> 0, step: 1
3225 23:06:55.138431
3226 23:06:55.141564 RX Delay -40 -> 252, step: 8
3227 23:06:55.145073 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3228 23:06:55.148531 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3229 23:06:55.154861 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3230 23:06:55.158291 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3231 23:06:55.161999 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3232 23:06:55.164960 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3233 23:06:55.168113 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3234 23:06:55.170933 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3235 23:06:55.177795 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3236 23:06:55.181561 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3237 23:06:55.184092 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3238 23:06:55.187730 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3239 23:06:55.190937 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3240 23:06:55.198220 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3241 23:06:55.201280 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3242 23:06:55.205205 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3243 23:06:55.205620 ==
3244 23:06:55.207450 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 23:06:55.211055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 23:06:55.214722 ==
3247 23:06:55.215129 DQS Delay:
3248 23:06:55.215449 DQS0 = 0, DQS1 = 0
3249 23:06:55.217886 DQM Delay:
3250 23:06:55.218291 DQM0 = 117, DQM1 = 108
3251 23:06:55.221342 DQ Delay:
3252 23:06:55.224627 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3253 23:06:55.227581 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3254 23:06:55.232114 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3255 23:06:55.234078 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =119
3256 23:06:55.234489
3257 23:06:55.234813
3258 23:06:55.235109 ==
3259 23:06:55.237538 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 23:06:55.241759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 23:06:55.242367 ==
3262 23:06:55.242790
3263 23:06:55.243160
3264 23:06:55.244855 TX Vref Scan disable
3265 23:06:55.247931 == TX Byte 0 ==
3266 23:06:55.250387 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3267 23:06:55.254263 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3268 23:06:55.257356 == TX Byte 1 ==
3269 23:06:55.260667 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3270 23:06:55.264035 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3271 23:06:55.264340 ==
3272 23:06:55.267459 Dram Type= 6, Freq= 0, CH_1, rank 0
3273 23:06:55.274241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3274 23:06:55.274536 ==
3275 23:06:55.284000 TX Vref=22, minBit 10, minWin=25, winSum=417
3276 23:06:55.287270 TX Vref=24, minBit 10, minWin=25, winSum=420
3277 23:06:55.290849 TX Vref=26, minBit 9, minWin=25, winSum=427
3278 23:06:55.293915 TX Vref=28, minBit 9, minWin=25, winSum=431
3279 23:06:55.297631 TX Vref=30, minBit 9, minWin=25, winSum=428
3280 23:06:55.303818 TX Vref=32, minBit 9, minWin=25, winSum=424
3281 23:06:55.307649 [TxChooseVref] Worse bit 9, Min win 25, Win sum 431, Final Vref 28
3282 23:06:55.308035
3283 23:06:55.310953 Final TX Range 1 Vref 28
3284 23:06:55.311250
3285 23:06:55.311484 ==
3286 23:06:55.313680 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 23:06:55.317163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 23:06:55.320503 ==
3289 23:06:55.320796
3290 23:06:55.321110
3291 23:06:55.321481 TX Vref Scan disable
3292 23:06:55.323931 == TX Byte 0 ==
3293 23:06:55.327408 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3294 23:06:55.334453 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3295 23:06:55.334823 == TX Byte 1 ==
3296 23:06:55.336987 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3297 23:06:55.344147 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3298 23:06:55.344470
3299 23:06:55.344796 [DATLAT]
3300 23:06:55.345018 Freq=1200, CH1 RK0
3301 23:06:55.345257
3302 23:06:55.347241 DATLAT Default: 0xd
3303 23:06:55.350334 0, 0xFFFF, sum = 0
3304 23:06:55.350635 1, 0xFFFF, sum = 0
3305 23:06:55.353542 2, 0xFFFF, sum = 0
3306 23:06:55.353839 3, 0xFFFF, sum = 0
3307 23:06:55.356877 4, 0xFFFF, sum = 0
3308 23:06:55.357231 5, 0xFFFF, sum = 0
3309 23:06:55.360246 6, 0xFFFF, sum = 0
3310 23:06:55.360542 7, 0xFFFF, sum = 0
3311 23:06:55.363400 8, 0xFFFF, sum = 0
3312 23:06:55.363741 9, 0xFFFF, sum = 0
3313 23:06:55.366666 10, 0xFFFF, sum = 0
3314 23:06:55.366960 11, 0xFFFF, sum = 0
3315 23:06:55.370177 12, 0x0, sum = 1
3316 23:06:55.370478 13, 0x0, sum = 2
3317 23:06:55.373544 14, 0x0, sum = 3
3318 23:06:55.373841 15, 0x0, sum = 4
3319 23:06:55.376677 best_step = 13
3320 23:06:55.376974
3321 23:06:55.377206 ==
3322 23:06:55.380291 Dram Type= 6, Freq= 0, CH_1, rank 0
3323 23:06:55.383962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3324 23:06:55.384374 ==
3325 23:06:55.387046 RX Vref Scan: 1
3326 23:06:55.387572
3327 23:06:55.387984 Set Vref Range= 32 -> 127
3328 23:06:55.388299
3329 23:06:55.390489 RX Vref 32 -> 127, step: 1
3330 23:06:55.390898
3331 23:06:55.393565 RX Delay -21 -> 252, step: 4
3332 23:06:55.394052
3333 23:06:55.396546 Set Vref, RX VrefLevel [Byte0]: 32
3334 23:06:55.400465 [Byte1]: 32
3335 23:06:55.400893
3336 23:06:55.403268 Set Vref, RX VrefLevel [Byte0]: 33
3337 23:06:55.406915 [Byte1]: 33
3338 23:06:55.410645
3339 23:06:55.414490 Set Vref, RX VrefLevel [Byte0]: 34
3340 23:06:55.417073 [Byte1]: 34
3341 23:06:55.417581
3342 23:06:55.420257 Set Vref, RX VrefLevel [Byte0]: 35
3343 23:06:55.423735 [Byte1]: 35
3344 23:06:55.424265
3345 23:06:55.426997 Set Vref, RX VrefLevel [Byte0]: 36
3346 23:06:55.430039 [Byte1]: 36
3347 23:06:55.434626
3348 23:06:55.435121 Set Vref, RX VrefLevel [Byte0]: 37
3349 23:06:55.437499 [Byte1]: 37
3350 23:06:55.442368
3351 23:06:55.442869 Set Vref, RX VrefLevel [Byte0]: 38
3352 23:06:55.445512 [Byte1]: 38
3353 23:06:55.450629
3354 23:06:55.451109 Set Vref, RX VrefLevel [Byte0]: 39
3355 23:06:55.453877 [Byte1]: 39
3356 23:06:55.458335
3357 23:06:55.458794 Set Vref, RX VrefLevel [Byte0]: 40
3358 23:06:55.461805 [Byte1]: 40
3359 23:06:55.466599
3360 23:06:55.467003 Set Vref, RX VrefLevel [Byte0]: 41
3361 23:06:55.469375 [Byte1]: 41
3362 23:06:55.474568
3363 23:06:55.475285 Set Vref, RX VrefLevel [Byte0]: 42
3364 23:06:55.477340 [Byte1]: 42
3365 23:06:55.482100
3366 23:06:55.482510 Set Vref, RX VrefLevel [Byte0]: 43
3367 23:06:55.485031 [Byte1]: 43
3368 23:06:55.489938
3369 23:06:55.490391 Set Vref, RX VrefLevel [Byte0]: 44
3370 23:06:55.493514 [Byte1]: 44
3371 23:06:55.498249
3372 23:06:55.498668 Set Vref, RX VrefLevel [Byte0]: 45
3373 23:06:55.500828 [Byte1]: 45
3374 23:06:55.506400
3375 23:06:55.506813 Set Vref, RX VrefLevel [Byte0]: 46
3376 23:06:55.508761 [Byte1]: 46
3377 23:06:55.513696
3378 23:06:55.514106 Set Vref, RX VrefLevel [Byte0]: 47
3379 23:06:55.516877 [Byte1]: 47
3380 23:06:55.521299
3381 23:06:55.521710 Set Vref, RX VrefLevel [Byte0]: 48
3382 23:06:55.524475 [Byte1]: 48
3383 23:06:55.529734
3384 23:06:55.530143 Set Vref, RX VrefLevel [Byte0]: 49
3385 23:06:55.532669 [Byte1]: 49
3386 23:06:55.537120
3387 23:06:55.537530 Set Vref, RX VrefLevel [Byte0]: 50
3388 23:06:55.540793 [Byte1]: 50
3389 23:06:55.545568
3390 23:06:55.546127 Set Vref, RX VrefLevel [Byte0]: 51
3391 23:06:55.548959 [Byte1]: 51
3392 23:06:55.553058
3393 23:06:55.553469 Set Vref, RX VrefLevel [Byte0]: 52
3394 23:06:55.556673 [Byte1]: 52
3395 23:06:55.561188
3396 23:06:55.561601 Set Vref, RX VrefLevel [Byte0]: 53
3397 23:06:55.564493 [Byte1]: 53
3398 23:06:55.569363
3399 23:06:55.569837 Set Vref, RX VrefLevel [Byte0]: 54
3400 23:06:55.572221 [Byte1]: 54
3401 23:06:55.576941
3402 23:06:55.577510 Set Vref, RX VrefLevel [Byte0]: 55
3403 23:06:55.580186 [Byte1]: 55
3404 23:06:55.584600
3405 23:06:55.585009 Set Vref, RX VrefLevel [Byte0]: 56
3406 23:06:55.587984 [Byte1]: 56
3407 23:06:55.592848
3408 23:06:55.593262 Set Vref, RX VrefLevel [Byte0]: 57
3409 23:06:55.596076 [Byte1]: 57
3410 23:06:55.601357
3411 23:06:55.601808 Set Vref, RX VrefLevel [Byte0]: 58
3412 23:06:55.604222 [Byte1]: 58
3413 23:06:55.609267
3414 23:06:55.609682 Set Vref, RX VrefLevel [Byte0]: 59
3415 23:06:55.611855 [Byte1]: 59
3416 23:06:55.616599
3417 23:06:55.617110 Set Vref, RX VrefLevel [Byte0]: 60
3418 23:06:55.620221 [Byte1]: 60
3419 23:06:55.625151
3420 23:06:55.625663 Set Vref, RX VrefLevel [Byte0]: 61
3421 23:06:55.628094 [Byte1]: 61
3422 23:06:55.632821
3423 23:06:55.633376 Set Vref, RX VrefLevel [Byte0]: 62
3424 23:06:55.635798 [Byte1]: 62
3425 23:06:55.640322
3426 23:06:55.640781 Set Vref, RX VrefLevel [Byte0]: 63
3427 23:06:55.643861 [Byte1]: 63
3428 23:06:55.648133
3429 23:06:55.648547 Set Vref, RX VrefLevel [Byte0]: 64
3430 23:06:55.651973 [Byte1]: 64
3431 23:06:55.656239
3432 23:06:55.656756 Set Vref, RX VrefLevel [Byte0]: 65
3433 23:06:55.659513 [Byte1]: 65
3434 23:06:55.664768
3435 23:06:55.665319 Set Vref, RX VrefLevel [Byte0]: 66
3436 23:06:55.667927 [Byte1]: 66
3437 23:06:55.672127
3438 23:06:55.672583 Set Vref, RX VrefLevel [Byte0]: 67
3439 23:06:55.675544 [Byte1]: 67
3440 23:06:55.680422
3441 23:06:55.680878 Final RX Vref Byte 0 = 47 to rank0
3442 23:06:55.683152 Final RX Vref Byte 1 = 59 to rank0
3443 23:06:55.686893 Final RX Vref Byte 0 = 47 to rank1
3444 23:06:55.689845 Final RX Vref Byte 1 = 59 to rank1==
3445 23:06:55.693516 Dram Type= 6, Freq= 0, CH_1, rank 0
3446 23:06:55.699476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 23:06:55.699994 ==
3448 23:06:55.700327 DQS Delay:
3449 23:06:55.700634 DQS0 = 0, DQS1 = 0
3450 23:06:55.703351 DQM Delay:
3451 23:06:55.703906 DQM0 = 115, DQM1 = 111
3452 23:06:55.706900 DQ Delay:
3453 23:06:55.709772 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =112
3454 23:06:55.713296 DQ4 =112, DQ5 =126, DQ6 =126, DQ7 =114
3455 23:06:55.716548 DQ8 =100, DQ9 =102, DQ10 =116, DQ11 =100
3456 23:06:55.719704 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3457 23:06:55.720133
3458 23:06:55.720464
3459 23:06:55.729969 [DQSOSCAuto] RK0, (LSB)MR18= 0x6fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 407 ps
3460 23:06:55.730506 CH1 RK0: MR19=403, MR18=6FA
3461 23:06:55.736603 CH1_RK0: MR19=0x403, MR18=0x6FA, DQSOSC=407, MR23=63, INC=39, DEC=26
3462 23:06:55.737118
3463 23:06:55.740128 ----->DramcWriteLeveling(PI) begin...
3464 23:06:55.740645 ==
3465 23:06:55.742964 Dram Type= 6, Freq= 0, CH_1, rank 1
3466 23:06:55.749518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3467 23:06:55.750031 ==
3468 23:06:55.750364 Write leveling (Byte 0): 26 => 26
3469 23:06:55.753178 Write leveling (Byte 1): 28 => 28
3470 23:06:55.756396 DramcWriteLeveling(PI) end<-----
3471 23:06:55.756812
3472 23:06:55.757140 ==
3473 23:06:55.759326 Dram Type= 6, Freq= 0, CH_1, rank 1
3474 23:06:55.765878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3475 23:06:55.766380 ==
3476 23:06:55.769284 [Gating] SW mode calibration
3477 23:06:55.775858 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3478 23:06:55.779413 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3479 23:06:55.787400 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3480 23:06:55.789313 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3481 23:06:55.792360 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3482 23:06:55.799731 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3483 23:06:55.802750 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 23:06:55.806097 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 23:06:55.812397 0 15 24 | B1->B0 | 2e2e 3232 | 0 1 | (0 0) (1 0)
3486 23:06:55.815722 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3487 23:06:55.818933 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3488 23:06:55.825998 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3489 23:06:55.828950 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3490 23:06:55.832269 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 23:06:55.839406 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 23:06:55.842281 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 23:06:55.845058 1 0 24 | B1->B0 | 3d3d 2b2b | 0 1 | (0 0) (0 0)
3494 23:06:55.851949 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3495 23:06:55.855336 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3496 23:06:55.858928 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 23:06:55.865349 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 23:06:55.868965 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 23:06:55.871834 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 23:06:55.878172 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 23:06:55.881651 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 23:06:55.885577 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3503 23:06:55.892293 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3504 23:06:55.895083 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3505 23:06:55.898070 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 23:06:55.904435 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 23:06:55.908300 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 23:06:55.911379 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 23:06:55.918565 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 23:06:55.921294 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 23:06:55.925019 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 23:06:55.931861 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 23:06:55.934856 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 23:06:55.937422 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 23:06:55.944560 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 23:06:55.948356 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 23:06:55.950933 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3518 23:06:55.957677 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3519 23:06:55.960899 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 23:06:55.964108 Total UI for P1: 0, mck2ui 16
3521 23:06:55.967400 best dqsien dly found for B0: ( 1, 3, 28)
3522 23:06:55.970902 Total UI for P1: 0, mck2ui 16
3523 23:06:55.974256 best dqsien dly found for B1: ( 1, 3, 26)
3524 23:06:55.977505 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3525 23:06:55.981011 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3526 23:06:55.981805
3527 23:06:55.984177 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3528 23:06:55.987602 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3529 23:06:55.990711 [Gating] SW calibration Done
3530 23:06:55.991231 ==
3531 23:06:55.994485 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 23:06:55.996930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 23:06:55.997471 ==
3534 23:06:56.000739 RX Vref Scan: 0
3535 23:06:56.001144
3536 23:06:56.003519 RX Vref 0 -> 0, step: 1
3537 23:06:56.003962
3538 23:06:56.004299 RX Delay -40 -> 252, step: 8
3539 23:06:56.010053 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3540 23:06:56.013855 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3541 23:06:56.017331 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3542 23:06:56.021001 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3543 23:06:56.023976 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3544 23:06:56.030674 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3545 23:06:56.033732 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3546 23:06:56.037017 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3547 23:06:56.040210 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3548 23:06:56.043847 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3549 23:06:56.049923 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3550 23:06:56.053846 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3551 23:06:56.056648 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3552 23:06:56.060001 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3553 23:06:56.066676 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3554 23:06:56.070172 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3555 23:06:56.070679 ==
3556 23:06:56.073439 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 23:06:56.076576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 23:06:56.077191 ==
3559 23:06:56.079810 DQS Delay:
3560 23:06:56.080250 DQS0 = 0, DQS1 = 0
3561 23:06:56.080791 DQM Delay:
3562 23:06:56.083306 DQM0 = 116, DQM1 = 110
3563 23:06:56.083764 DQ Delay:
3564 23:06:56.086495 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =111
3565 23:06:56.089763 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3566 23:06:56.093137 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3567 23:06:56.099865 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3568 23:06:56.100375
3569 23:06:56.100705
3570 23:06:56.101008 ==
3571 23:06:56.102981 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 23:06:56.106460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 23:06:56.106984 ==
3574 23:06:56.107319
3575 23:06:56.107621
3576 23:06:56.110224 TX Vref Scan disable
3577 23:06:56.110742 == TX Byte 0 ==
3578 23:06:56.116586 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3579 23:06:56.119171 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3580 23:06:56.119581 == TX Byte 1 ==
3581 23:06:56.126516 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3582 23:06:56.129986 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3583 23:06:56.130507 ==
3584 23:06:56.132700 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 23:06:56.136140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 23:06:56.136557 ==
3587 23:06:56.149393 TX Vref=22, minBit 1, minWin=25, winSum=424
3588 23:06:56.151997 TX Vref=24, minBit 1, minWin=26, winSum=430
3589 23:06:56.156142 TX Vref=26, minBit 9, minWin=26, winSum=429
3590 23:06:56.158885 TX Vref=28, minBit 8, minWin=26, winSum=430
3591 23:06:56.161816 TX Vref=30, minBit 9, minWin=26, winSum=435
3592 23:06:56.168579 TX Vref=32, minBit 9, minWin=26, winSum=433
3593 23:06:56.172188 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3594 23:06:56.172647
3595 23:06:56.175164 Final TX Range 1 Vref 30
3596 23:06:56.175621
3597 23:06:56.176039 ==
3598 23:06:56.178853 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 23:06:56.181926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 23:06:56.185451 ==
3601 23:06:56.185862
3602 23:06:56.186185
3603 23:06:56.186490 TX Vref Scan disable
3604 23:06:56.188464 == TX Byte 0 ==
3605 23:06:56.192820 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3606 23:06:56.198403 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3607 23:06:56.198815 == TX Byte 1 ==
3608 23:06:56.202134 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3609 23:06:56.208349 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3610 23:06:56.208767
3611 23:06:56.209095 [DATLAT]
3612 23:06:56.209393 Freq=1200, CH1 RK1
3613 23:06:56.209689
3614 23:06:56.211500 DATLAT Default: 0xd
3615 23:06:56.211959 0, 0xFFFF, sum = 0
3616 23:06:56.215326 1, 0xFFFF, sum = 0
3617 23:06:56.217984 2, 0xFFFF, sum = 0
3618 23:06:56.218400 3, 0xFFFF, sum = 0
3619 23:06:56.221374 4, 0xFFFF, sum = 0
3620 23:06:56.221791 5, 0xFFFF, sum = 0
3621 23:06:56.224628 6, 0xFFFF, sum = 0
3622 23:06:56.225150 7, 0xFFFF, sum = 0
3623 23:06:56.227778 8, 0xFFFF, sum = 0
3624 23:06:56.228197 9, 0xFFFF, sum = 0
3625 23:06:56.232058 10, 0xFFFF, sum = 0
3626 23:06:56.232478 11, 0xFFFF, sum = 0
3627 23:06:56.234388 12, 0x0, sum = 1
3628 23:06:56.234804 13, 0x0, sum = 2
3629 23:06:56.238104 14, 0x0, sum = 3
3630 23:06:56.238625 15, 0x0, sum = 4
3631 23:06:56.241380 best_step = 13
3632 23:06:56.241895
3633 23:06:56.242224 ==
3634 23:06:56.244322 Dram Type= 6, Freq= 0, CH_1, rank 1
3635 23:06:56.247937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3636 23:06:56.248461 ==
3637 23:06:56.251501 RX Vref Scan: 0
3638 23:06:56.252056
3639 23:06:56.252388 RX Vref 0 -> 0, step: 1
3640 23:06:56.252707
3641 23:06:56.254601 RX Delay -21 -> 252, step: 4
3642 23:06:56.261286 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3643 23:06:56.264311 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3644 23:06:56.267713 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3645 23:06:56.271624 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3646 23:06:56.274090 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3647 23:06:56.281042 iDelay=199, Bit 5, Center 126 (63 ~ 190) 128
3648 23:06:56.284435 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3649 23:06:56.287457 iDelay=199, Bit 7, Center 114 (51 ~ 178) 128
3650 23:06:56.291200 iDelay=199, Bit 8, Center 100 (35 ~ 166) 132
3651 23:06:56.294311 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3652 23:06:56.301167 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3653 23:06:56.303628 iDelay=199, Bit 11, Center 104 (39 ~ 170) 132
3654 23:06:56.307229 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3655 23:06:56.310229 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3656 23:06:56.316973 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3657 23:06:56.320048 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3658 23:06:56.320511 ==
3659 23:06:56.323923 Dram Type= 6, Freq= 0, CH_1, rank 1
3660 23:06:56.327014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3661 23:06:56.327586 ==
3662 23:06:56.330822 DQS Delay:
3663 23:06:56.331383 DQS0 = 0, DQS1 = 0
3664 23:06:56.331808 DQM Delay:
3665 23:06:56.334093 DQM0 = 116, DQM1 = 111
3666 23:06:56.334660 DQ Delay:
3667 23:06:56.337575 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3668 23:06:56.340171 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =114
3669 23:06:56.347042 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =104
3670 23:06:56.350076 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =120
3671 23:06:56.350659
3672 23:06:56.351028
3673 23:06:56.356793 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7f1, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 413 ps
3674 23:06:56.359852 CH1 RK1: MR19=303, MR18=F7F1
3675 23:06:56.366586 CH1_RK1: MR19=0x303, MR18=0xF7F1, DQSOSC=413, MR23=63, INC=38, DEC=25
3676 23:06:56.370115 [RxdqsGatingPostProcess] freq 1200
3677 23:06:56.376084 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3678 23:06:56.376621 best DQS0 dly(2T, 0.5T) = (0, 11)
3679 23:06:56.379518 best DQS1 dly(2T, 0.5T) = (0, 11)
3680 23:06:56.382726 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3681 23:06:56.386394 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3682 23:06:56.389389 best DQS0 dly(2T, 0.5T) = (0, 11)
3683 23:06:56.393185 best DQS1 dly(2T, 0.5T) = (0, 11)
3684 23:06:56.395768 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3685 23:06:56.399357 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3686 23:06:56.402662 Pre-setting of DQS Precalculation
3687 23:06:56.409049 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3688 23:06:56.415631 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3689 23:06:56.422828 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3690 23:06:56.423407
3691 23:06:56.423824
3692 23:06:56.425525 [Calibration Summary] 2400 Mbps
3693 23:06:56.425981 CH 0, Rank 0
3694 23:06:56.429423 SW Impedance : PASS
3695 23:06:56.431992 DUTY Scan : NO K
3696 23:06:56.432540 ZQ Calibration : PASS
3697 23:06:56.435635 Jitter Meter : NO K
3698 23:06:56.438957 CBT Training : PASS
3699 23:06:56.439503 Write leveling : PASS
3700 23:06:56.442413 RX DQS gating : PASS
3701 23:06:56.446260 RX DQ/DQS(RDDQC) : PASS
3702 23:06:56.446809 TX DQ/DQS : PASS
3703 23:06:56.448374 RX DATLAT : PASS
3704 23:06:56.452552 RX DQ/DQS(Engine): PASS
3705 23:06:56.453167 TX OE : NO K
3706 23:06:56.455343 All Pass.
3707 23:06:56.455833
3708 23:06:56.456198 CH 0, Rank 1
3709 23:06:56.458859 SW Impedance : PASS
3710 23:06:56.459407 DUTY Scan : NO K
3711 23:06:56.462026 ZQ Calibration : PASS
3712 23:06:56.465466 Jitter Meter : NO K
3713 23:06:56.466026 CBT Training : PASS
3714 23:06:56.468190 Write leveling : PASS
3715 23:06:56.471601 RX DQS gating : PASS
3716 23:06:56.472406 RX DQ/DQS(RDDQC) : PASS
3717 23:06:56.474947 TX DQ/DQS : PASS
3718 23:06:56.475494 RX DATLAT : PASS
3719 23:06:56.478946 RX DQ/DQS(Engine): PASS
3720 23:06:56.481589 TX OE : NO K
3721 23:06:56.482048 All Pass.
3722 23:06:56.482410
3723 23:06:56.482746 CH 1, Rank 0
3724 23:06:56.485812 SW Impedance : PASS
3725 23:06:56.487906 DUTY Scan : NO K
3726 23:06:56.488401 ZQ Calibration : PASS
3727 23:06:56.491739 Jitter Meter : NO K
3728 23:06:56.494694 CBT Training : PASS
3729 23:06:56.495243 Write leveling : PASS
3730 23:06:56.497943 RX DQS gating : PASS
3731 23:06:56.501752 RX DQ/DQS(RDDQC) : PASS
3732 23:06:56.502204 TX DQ/DQS : PASS
3733 23:06:56.504776 RX DATLAT : PASS
3734 23:06:56.508018 RX DQ/DQS(Engine): PASS
3735 23:06:56.508476 TX OE : NO K
3736 23:06:56.511362 All Pass.
3737 23:06:56.511850
3738 23:06:56.512216 CH 1, Rank 1
3739 23:06:56.514472 SW Impedance : PASS
3740 23:06:56.514926 DUTY Scan : NO K
3741 23:06:56.517959 ZQ Calibration : PASS
3742 23:06:56.521709 Jitter Meter : NO K
3743 23:06:56.522262 CBT Training : PASS
3744 23:06:56.524669 Write leveling : PASS
3745 23:06:56.528550 RX DQS gating : PASS
3746 23:06:56.529098 RX DQ/DQS(RDDQC) : PASS
3747 23:06:56.531713 TX DQ/DQS : PASS
3748 23:06:56.534668 RX DATLAT : PASS
3749 23:06:56.535124 RX DQ/DQS(Engine): PASS
3750 23:06:56.538303 TX OE : NO K
3751 23:06:56.538851 All Pass.
3752 23:06:56.539213
3753 23:06:56.541416 DramC Write-DBI off
3754 23:06:56.544092 PER_BANK_REFRESH: Hybrid Mode
3755 23:06:56.544547 TX_TRACKING: ON
3756 23:06:56.554636 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3757 23:06:56.557627 [FAST_K] Save calibration result to emmc
3758 23:06:56.560905 dramc_set_vcore_voltage set vcore to 650000
3759 23:06:56.564229 Read voltage for 600, 5
3760 23:06:56.564679 Vio18 = 0
3761 23:06:56.565033 Vcore = 650000
3762 23:06:56.567509 Vdram = 0
3763 23:06:56.568025 Vddq = 0
3764 23:06:56.568400 Vmddr = 0
3765 23:06:56.574747 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3766 23:06:56.577509 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3767 23:06:56.580532 MEM_TYPE=3, freq_sel=19
3768 23:06:56.583912 sv_algorithm_assistance_LP4_1600
3769 23:06:56.587366 ============ PULL DRAM RESETB DOWN ============
3770 23:06:56.590684 ========== PULL DRAM RESETB DOWN end =========
3771 23:06:56.597088 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3772 23:06:56.600431 ===================================
3773 23:06:56.600896 LPDDR4 DRAM CONFIGURATION
3774 23:06:56.603996 ===================================
3775 23:06:56.607663 EX_ROW_EN[0] = 0x0
3776 23:06:56.611032 EX_ROW_EN[1] = 0x0
3777 23:06:56.611591 LP4Y_EN = 0x0
3778 23:06:56.613852 WORK_FSP = 0x0
3779 23:06:56.614309 WL = 0x2
3780 23:06:56.617811 RL = 0x2
3781 23:06:56.618372 BL = 0x2
3782 23:06:56.620106 RPST = 0x0
3783 23:06:56.620561 RD_PRE = 0x0
3784 23:06:56.623889 WR_PRE = 0x1
3785 23:06:56.624346 WR_PST = 0x0
3786 23:06:56.627519 DBI_WR = 0x0
3787 23:06:56.628145 DBI_RD = 0x0
3788 23:06:56.630645 OTF = 0x1
3789 23:06:56.634331 ===================================
3790 23:06:56.637523 ===================================
3791 23:06:56.638075 ANA top config
3792 23:06:56.640599 ===================================
3793 23:06:56.643821 DLL_ASYNC_EN = 0
3794 23:06:56.646868 ALL_SLAVE_EN = 1
3795 23:06:56.650619 NEW_RANK_MODE = 1
3796 23:06:56.651175 DLL_IDLE_MODE = 1
3797 23:06:56.653746 LP45_APHY_COMB_EN = 1
3798 23:06:56.657111 TX_ODT_DIS = 1
3799 23:06:56.660305 NEW_8X_MODE = 1
3800 23:06:56.663631 ===================================
3801 23:06:56.666490 ===================================
3802 23:06:56.670854 data_rate = 1200
3803 23:06:56.673164 CKR = 1
3804 23:06:56.673624 DQ_P2S_RATIO = 8
3805 23:06:56.676702 ===================================
3806 23:06:56.679866 CA_P2S_RATIO = 8
3807 23:06:56.683136 DQ_CA_OPEN = 0
3808 23:06:56.686866 DQ_SEMI_OPEN = 0
3809 23:06:56.689230 CA_SEMI_OPEN = 0
3810 23:06:56.693164 CA_FULL_RATE = 0
3811 23:06:56.693806 DQ_CKDIV4_EN = 1
3812 23:06:56.696043 CA_CKDIV4_EN = 1
3813 23:06:56.699592 CA_PREDIV_EN = 0
3814 23:06:56.703090 PH8_DLY = 0
3815 23:06:56.706153 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3816 23:06:56.709333 DQ_AAMCK_DIV = 4
3817 23:06:56.709829 CA_AAMCK_DIV = 4
3818 23:06:56.712878 CA_ADMCK_DIV = 4
3819 23:06:56.716325 DQ_TRACK_CA_EN = 0
3820 23:06:56.720029 CA_PICK = 600
3821 23:06:56.722928 CA_MCKIO = 600
3822 23:06:56.726556 MCKIO_SEMI = 0
3823 23:06:56.729307 PLL_FREQ = 2288
3824 23:06:56.729774 DQ_UI_PI_RATIO = 32
3825 23:06:56.732676 CA_UI_PI_RATIO = 0
3826 23:06:56.735852 ===================================
3827 23:06:56.739255 ===================================
3828 23:06:56.742496 memory_type:LPDDR4
3829 23:06:56.746271 GP_NUM : 10
3830 23:06:56.746831 SRAM_EN : 1
3831 23:06:56.749389 MD32_EN : 0
3832 23:06:56.752291 ===================================
3833 23:06:56.756028 [ANA_INIT] >>>>>>>>>>>>>>
3834 23:06:56.756590 <<<<<< [CONFIGURE PHASE]: ANA_TX
3835 23:06:56.762292 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3836 23:06:56.765760 ===================================
3837 23:06:56.766324 data_rate = 1200,PCW = 0X5800
3838 23:06:56.768783 ===================================
3839 23:06:56.771736 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3840 23:06:56.779032 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3841 23:06:56.785277 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3842 23:06:56.788294 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3843 23:06:56.791876 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3844 23:06:56.795399 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3845 23:06:56.798082 [ANA_INIT] flow start
3846 23:06:56.801695 [ANA_INIT] PLL >>>>>>>>
3847 23:06:56.802154 [ANA_INIT] PLL <<<<<<<<
3848 23:06:56.805587 [ANA_INIT] MIDPI >>>>>>>>
3849 23:06:56.808506 [ANA_INIT] MIDPI <<<<<<<<
3850 23:06:56.808920 [ANA_INIT] DLL >>>>>>>>
3851 23:06:56.811812 [ANA_INIT] flow end
3852 23:06:56.815240 ============ LP4 DIFF to SE enter ============
3853 23:06:56.818775 ============ LP4 DIFF to SE exit ============
3854 23:06:56.821822 [ANA_INIT] <<<<<<<<<<<<<
3855 23:06:56.824526 [Flow] Enable top DCM control >>>>>
3856 23:06:56.828631 [Flow] Enable top DCM control <<<<<
3857 23:06:56.831794 Enable DLL master slave shuffle
3858 23:06:56.838305 ==============================================================
3859 23:06:56.838867 Gating Mode config
3860 23:06:56.844604 ==============================================================
3861 23:06:56.847652 Config description:
3862 23:06:56.854201 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3863 23:06:56.861279 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3864 23:06:56.867317 SELPH_MODE 0: By rank 1: By Phase
3865 23:06:56.873764 ==============================================================
3866 23:06:56.877287 GAT_TRACK_EN = 1
3867 23:06:56.877786 RX_GATING_MODE = 2
3868 23:06:56.880368 RX_GATING_TRACK_MODE = 2
3869 23:06:56.883999 SELPH_MODE = 1
3870 23:06:56.887397 PICG_EARLY_EN = 1
3871 23:06:56.890297 VALID_LAT_VALUE = 1
3872 23:06:56.897395 ==============================================================
3873 23:06:56.900332 Enter into Gating configuration >>>>
3874 23:06:56.903619 Exit from Gating configuration <<<<
3875 23:06:56.907018 Enter into DVFS_PRE_config >>>>>
3876 23:06:56.917107 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3877 23:06:56.919789 Exit from DVFS_PRE_config <<<<<
3878 23:06:56.923638 Enter into PICG configuration >>>>
3879 23:06:56.926503 Exit from PICG configuration <<<<
3880 23:06:56.929669 [RX_INPUT] configuration >>>>>
3881 23:06:56.933263 [RX_INPUT] configuration <<<<<
3882 23:06:56.936412 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3883 23:06:56.943291 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3884 23:06:56.949810 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3885 23:06:56.955788 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3886 23:06:56.959582 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3887 23:06:56.965867 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3888 23:06:56.969664 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3889 23:06:56.975390 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3890 23:06:56.979053 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3891 23:06:56.982374 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3892 23:06:56.985320 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3893 23:06:56.991873 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3894 23:06:56.995442 ===================================
3895 23:06:56.998585 LPDDR4 DRAM CONFIGURATION
3896 23:06:57.002357 ===================================
3897 23:06:57.002444 EX_ROW_EN[0] = 0x0
3898 23:06:57.005479 EX_ROW_EN[1] = 0x0
3899 23:06:57.005561 LP4Y_EN = 0x0
3900 23:06:57.008638 WORK_FSP = 0x0
3901 23:06:57.008722 WL = 0x2
3902 23:06:57.011785 RL = 0x2
3903 23:06:57.011887 BL = 0x2
3904 23:06:57.015633 RPST = 0x0
3905 23:06:57.015724 RD_PRE = 0x0
3906 23:06:57.019311 WR_PRE = 0x1
3907 23:06:57.019395 WR_PST = 0x0
3908 23:06:57.021929 DBI_WR = 0x0
3909 23:06:57.025751 DBI_RD = 0x0
3910 23:06:57.025833 OTF = 0x1
3911 23:06:57.028447 ===================================
3912 23:06:57.031693 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3913 23:06:57.035495 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3914 23:06:57.041790 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3915 23:06:57.044800 ===================================
3916 23:06:57.048590 LPDDR4 DRAM CONFIGURATION
3917 23:06:57.051930 ===================================
3918 23:06:57.052013 EX_ROW_EN[0] = 0x10
3919 23:06:57.054750 EX_ROW_EN[1] = 0x0
3920 23:06:57.054832 LP4Y_EN = 0x0
3921 23:06:57.057757 WORK_FSP = 0x0
3922 23:06:57.057846 WL = 0x2
3923 23:06:57.061618 RL = 0x2
3924 23:06:57.061702 BL = 0x2
3925 23:06:57.064750 RPST = 0x0
3926 23:06:57.064833 RD_PRE = 0x0
3927 23:06:57.067993 WR_PRE = 0x1
3928 23:06:57.068079 WR_PST = 0x0
3929 23:06:57.071182 DBI_WR = 0x0
3930 23:06:57.075475 DBI_RD = 0x0
3931 23:06:57.075558 OTF = 0x1
3932 23:06:57.079415 ===================================
3933 23:06:57.084740 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3934 23:06:57.088473 nWR fixed to 30
3935 23:06:57.091654 [ModeRegInit_LP4] CH0 RK0
3936 23:06:57.092125 [ModeRegInit_LP4] CH0 RK1
3937 23:06:57.094928 [ModeRegInit_LP4] CH1 RK0
3938 23:06:57.098217 [ModeRegInit_LP4] CH1 RK1
3939 23:06:57.098308 match AC timing 17
3940 23:06:57.105101 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3941 23:06:57.107645 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3942 23:06:57.111395 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3943 23:06:57.117968 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3944 23:06:57.121424 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3945 23:06:57.121507 ==
3946 23:06:57.124697 Dram Type= 6, Freq= 0, CH_0, rank 0
3947 23:06:57.127518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3948 23:06:57.127618 ==
3949 23:06:57.134151 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3950 23:06:57.141315 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3951 23:06:57.144715 [CA 0] Center 36 (6~66) winsize 61
3952 23:06:57.147996 [CA 1] Center 36 (6~66) winsize 61
3953 23:06:57.151300 [CA 2] Center 34 (3~65) winsize 63
3954 23:06:57.154552 [CA 3] Center 34 (3~65) winsize 63
3955 23:06:57.158305 [CA 4] Center 33 (3~64) winsize 62
3956 23:06:57.161001 [CA 5] Center 33 (3~64) winsize 62
3957 23:06:57.161411
3958 23:06:57.164541 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3959 23:06:57.164955
3960 23:06:57.167898 [CATrainingPosCal] consider 1 rank data
3961 23:06:57.170942 u2DelayCellTimex100 = 270/100 ps
3962 23:06:57.174690 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3963 23:06:57.177719 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3964 23:06:57.180653 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
3965 23:06:57.183946 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3966 23:06:57.190545 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3967 23:06:57.193802 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3968 23:06:57.193930
3969 23:06:57.197170 CA PerBit enable=1, Macro0, CA PI delay=33
3970 23:06:57.197282
3971 23:06:57.200468 [CBTSetCACLKResult] CA Dly = 33
3972 23:06:57.200645 CS Dly: 5 (0~36)
3973 23:06:57.200743 ==
3974 23:06:57.203973 Dram Type= 6, Freq= 0, CH_0, rank 1
3975 23:06:57.211142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 23:06:57.211319 ==
3977 23:06:57.214610 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3978 23:06:57.220477 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3979 23:06:57.224214 [CA 0] Center 36 (6~66) winsize 61
3980 23:06:57.227365 [CA 1] Center 36 (6~66) winsize 61
3981 23:06:57.230325 [CA 2] Center 34 (4~64) winsize 61
3982 23:06:57.234313 [CA 3] Center 34 (4~64) winsize 61
3983 23:06:57.237535 [CA 4] Center 33 (2~64) winsize 63
3984 23:06:57.240644 [CA 5] Center 33 (2~64) winsize 63
3985 23:06:57.240855
3986 23:06:57.244079 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3987 23:06:57.244309
3988 23:06:57.247181 [CATrainingPosCal] consider 2 rank data
3989 23:06:57.250096 u2DelayCellTimex100 = 270/100 ps
3990 23:06:57.253916 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3991 23:06:57.260525 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3992 23:06:57.263819 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3993 23:06:57.267042 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3994 23:06:57.270186 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3995 23:06:57.273819 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3996 23:06:57.274373
3997 23:06:57.277440 CA PerBit enable=1, Macro0, CA PI delay=33
3998 23:06:57.277895
3999 23:06:57.279916 [CBTSetCACLKResult] CA Dly = 33
4000 23:06:57.283393 CS Dly: 5 (0~36)
4001 23:06:57.283847
4002 23:06:57.286686 ----->DramcWriteLeveling(PI) begin...
4003 23:06:57.287127 ==
4004 23:06:57.290044 Dram Type= 6, Freq= 0, CH_0, rank 0
4005 23:06:57.293749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4006 23:06:57.294273 ==
4007 23:06:57.296327 Write leveling (Byte 0): 31 => 31
4008 23:06:57.300000 Write leveling (Byte 1): 30 => 30
4009 23:06:57.304223 DramcWriteLeveling(PI) end<-----
4010 23:06:57.304733
4011 23:06:57.305108 ==
4012 23:06:57.306911 Dram Type= 6, Freq= 0, CH_0, rank 0
4013 23:06:57.310131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4014 23:06:57.310648 ==
4015 23:06:57.313950 [Gating] SW mode calibration
4016 23:06:57.319752 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4017 23:06:57.326743 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4018 23:06:57.329859 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4019 23:06:57.333652 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4020 23:06:57.339735 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4021 23:06:57.342896 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4022 23:06:57.346327 0 9 16 | B1->B0 | 3232 2323 | 0 0 | (1 1) (0 0)
4023 23:06:57.353008 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4024 23:06:57.356139 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 23:06:57.359960 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 23:06:57.366041 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4027 23:06:57.369044 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 23:06:57.372798 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 23:06:57.379547 0 10 12 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
4030 23:06:57.383158 0 10 16 | B1->B0 | 3333 3d3d | 0 0 | (0 0) (0 0)
4031 23:06:57.385644 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4032 23:06:57.392306 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 23:06:57.395494 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 23:06:57.399113 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 23:06:57.405572 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 23:06:57.409842 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 23:06:57.412133 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4038 23:06:57.418989 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4039 23:06:57.422574 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 23:06:57.425507 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 23:06:57.432585 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 23:06:57.435744 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 23:06:57.438644 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 23:06:57.446156 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 23:06:57.448434 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 23:06:57.452813 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 23:06:57.458311 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 23:06:57.462470 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 23:06:57.465134 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 23:06:57.471966 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 23:06:57.474707 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 23:06:57.478168 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 23:06:57.484624 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 23:06:57.488341 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4055 23:06:57.491946 Total UI for P1: 0, mck2ui 16
4056 23:06:57.494321 best dqsien dly found for B0: ( 0, 13, 14)
4057 23:06:57.497760 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 23:06:57.501532 Total UI for P1: 0, mck2ui 16
4059 23:06:57.504491 best dqsien dly found for B1: ( 0, 13, 16)
4060 23:06:57.508324 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4061 23:06:57.511139 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4062 23:06:57.511550
4063 23:06:57.517657 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4064 23:06:57.521371 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4065 23:06:57.524560 [Gating] SW calibration Done
4066 23:06:57.525065 ==
4067 23:06:57.527571 Dram Type= 6, Freq= 0, CH_0, rank 0
4068 23:06:57.531135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4069 23:06:57.531645 ==
4070 23:06:57.532028 RX Vref Scan: 0
4071 23:06:57.532337
4072 23:06:57.534141 RX Vref 0 -> 0, step: 1
4073 23:06:57.534649
4074 23:06:57.537644 RX Delay -230 -> 252, step: 16
4075 23:06:57.540546 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4076 23:06:57.548084 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4077 23:06:57.551168 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4078 23:06:57.554065 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4079 23:06:57.556931 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4080 23:06:57.560996 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4081 23:06:57.567460 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4082 23:06:57.570378 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4083 23:06:57.573773 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4084 23:06:57.577018 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4085 23:06:57.584568 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4086 23:06:57.587549 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4087 23:06:57.590748 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4088 23:06:57.593394 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4089 23:06:57.600716 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4090 23:06:57.603831 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4091 23:06:57.604242 ==
4092 23:06:57.607146 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 23:06:57.610050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 23:06:57.610467 ==
4095 23:06:57.613415 DQS Delay:
4096 23:06:57.613958 DQS0 = 0, DQS1 = 0
4097 23:06:57.614463 DQM Delay:
4098 23:06:57.616549 DQM0 = 44, DQM1 = 37
4099 23:06:57.616963 DQ Delay:
4100 23:06:57.620165 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4101 23:06:57.623248 DQ4 =49, DQ5 =41, DQ6 =49, DQ7 =49
4102 23:06:57.626919 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4103 23:06:57.629492 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4104 23:06:57.629907
4105 23:06:57.630230
4106 23:06:57.630529 ==
4107 23:06:57.633595 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 23:06:57.640025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 23:06:57.640542 ==
4110 23:06:57.640878
4111 23:06:57.641184
4112 23:06:57.641475 TX Vref Scan disable
4113 23:06:57.643472 == TX Byte 0 ==
4114 23:06:57.646917 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4115 23:06:57.653789 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4116 23:06:57.654352 == TX Byte 1 ==
4117 23:06:57.657157 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4118 23:06:57.663786 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4119 23:06:57.664350 ==
4120 23:06:57.666681 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 23:06:57.669746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 23:06:57.670205 ==
4123 23:06:57.670568
4124 23:06:57.670900
4125 23:06:57.673384 TX Vref Scan disable
4126 23:06:57.676851 == TX Byte 0 ==
4127 23:06:57.679843 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4128 23:06:57.683855 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4129 23:06:57.686384 == TX Byte 1 ==
4130 23:06:57.689678 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4131 23:06:57.693093 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4132 23:06:57.693549
4133 23:06:57.693906 [DATLAT]
4134 23:06:57.696679 Freq=600, CH0 RK0
4135 23:06:57.697224
4136 23:06:57.699922 DATLAT Default: 0x9
4137 23:06:57.700390 0, 0xFFFF, sum = 0
4138 23:06:57.703254 1, 0xFFFF, sum = 0
4139 23:06:57.704037 2, 0xFFFF, sum = 0
4140 23:06:57.706937 3, 0xFFFF, sum = 0
4141 23:06:57.707512 4, 0xFFFF, sum = 0
4142 23:06:57.709441 5, 0xFFFF, sum = 0
4143 23:06:57.709904 6, 0xFFFF, sum = 0
4144 23:06:57.713115 7, 0xFFFF, sum = 0
4145 23:06:57.713573 8, 0x0, sum = 1
4146 23:06:57.716453 9, 0x0, sum = 2
4147 23:06:57.717012 10, 0x0, sum = 3
4148 23:06:57.719469 11, 0x0, sum = 4
4149 23:06:57.719978 best_step = 9
4150 23:06:57.720338
4151 23:06:57.720710 ==
4152 23:06:57.722550 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 23:06:57.726232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 23:06:57.726739 ==
4155 23:06:57.729292 RX Vref Scan: 1
4156 23:06:57.729705
4157 23:06:57.733183 RX Vref 0 -> 0, step: 1
4158 23:06:57.733696
4159 23:06:57.734028 RX Delay -179 -> 252, step: 8
4160 23:06:57.736642
4161 23:06:57.737277 Set Vref, RX VrefLevel [Byte0]: 59
4162 23:06:57.739146 [Byte1]: 48
4163 23:06:57.743819
4164 23:06:57.744320 Final RX Vref Byte 0 = 59 to rank0
4165 23:06:57.747464 Final RX Vref Byte 1 = 48 to rank0
4166 23:06:57.750844 Final RX Vref Byte 0 = 59 to rank1
4167 23:06:57.753887 Final RX Vref Byte 1 = 48 to rank1==
4168 23:06:57.757404 Dram Type= 6, Freq= 0, CH_0, rank 0
4169 23:06:57.764158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 23:06:57.764674 ==
4171 23:06:57.765005 DQS Delay:
4172 23:06:57.767164 DQS0 = 0, DQS1 = 0
4173 23:06:57.767720 DQM Delay:
4174 23:06:57.768061 DQM0 = 43, DQM1 = 32
4175 23:06:57.770535 DQ Delay:
4176 23:06:57.773800 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4177 23:06:57.776761 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4178 23:06:57.780697 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4179 23:06:57.784497 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4180 23:06:57.785008
4181 23:06:57.785335
4182 23:06:57.789908 [DQSOSCAuto] RK0, (LSB)MR18= 0x633b, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
4183 23:06:57.794192 CH0 RK0: MR19=808, MR18=633B
4184 23:06:57.800292 CH0_RK0: MR19=0x808, MR18=0x633B, DQSOSC=391, MR23=63, INC=171, DEC=114
4185 23:06:57.800707
4186 23:06:57.803433 ----->DramcWriteLeveling(PI) begin...
4187 23:06:57.804019 ==
4188 23:06:57.806571 Dram Type= 6, Freq= 0, CH_0, rank 1
4189 23:06:57.809761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 23:06:57.810251 ==
4191 23:06:57.813378 Write leveling (Byte 0): 33 => 33
4192 23:06:57.816700 Write leveling (Byte 1): 32 => 32
4193 23:06:57.820115 DramcWriteLeveling(PI) end<-----
4194 23:06:57.820629
4195 23:06:57.820957 ==
4196 23:06:57.822864 Dram Type= 6, Freq= 0, CH_0, rank 1
4197 23:06:57.826922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 23:06:57.829562 ==
4199 23:06:57.829978 [Gating] SW mode calibration
4200 23:06:57.839606 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4201 23:06:57.843741 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4202 23:06:57.846838 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4203 23:06:57.853365 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4204 23:06:57.856370 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4205 23:06:57.859829 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
4206 23:06:57.866119 0 9 16 | B1->B0 | 2b2b 2626 | 0 0 | (1 1) (0 0)
4207 23:06:57.869237 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4208 23:06:57.872627 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 23:06:57.879066 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 23:06:57.882866 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 23:06:57.885647 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 23:06:57.892591 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 23:06:57.895652 0 10 12 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
4214 23:06:57.899549 0 10 16 | B1->B0 | 3b3b 4141 | 0 0 | (0 0) (1 1)
4215 23:06:57.905544 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 23:06:57.908539 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 23:06:57.911953 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 23:06:57.918790 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 23:06:57.921959 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 23:06:57.925395 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 23:06:57.931911 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4222 23:06:57.935395 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4223 23:06:57.938310 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4224 23:06:57.945084 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 23:06:57.948634 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 23:06:57.951536 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 23:06:57.957984 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 23:06:57.962068 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 23:06:57.964595 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 23:06:57.971494 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 23:06:57.974850 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 23:06:57.977978 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 23:06:57.984887 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 23:06:57.987828 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 23:06:57.991330 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 23:06:57.997610 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 23:06:58.001236 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4238 23:06:58.004070 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4239 23:06:58.007646 Total UI for P1: 0, mck2ui 16
4240 23:06:58.011106 best dqsien dly found for B0: ( 0, 13, 12)
4241 23:06:58.017939 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 23:06:58.020616 Total UI for P1: 0, mck2ui 16
4243 23:06:58.024411 best dqsien dly found for B1: ( 0, 13, 16)
4244 23:06:58.027547 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4245 23:06:58.031150 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4246 23:06:58.031770
4247 23:06:58.033958 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4248 23:06:58.037424 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4249 23:06:58.040886 [Gating] SW calibration Done
4250 23:06:58.041343 ==
4251 23:06:58.044066 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 23:06:58.047187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 23:06:58.047795 ==
4254 23:06:58.051010 RX Vref Scan: 0
4255 23:06:58.051464
4256 23:06:58.054178 RX Vref 0 -> 0, step: 1
4257 23:06:58.054727
4258 23:06:58.055091 RX Delay -230 -> 252, step: 16
4259 23:06:58.060959 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4260 23:06:58.064211 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4261 23:06:58.067252 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4262 23:06:58.070645 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4263 23:06:58.076731 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4264 23:06:58.079997 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4265 23:06:58.083509 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4266 23:06:58.087174 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4267 23:06:58.093585 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4268 23:06:58.096754 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4269 23:06:58.100285 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4270 23:06:58.103439 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4271 23:06:58.109962 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4272 23:06:58.113197 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4273 23:06:58.116791 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4274 23:06:58.120038 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4275 23:06:58.120588 ==
4276 23:06:58.123273 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 23:06:58.130571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 23:06:58.131127 ==
4279 23:06:58.131491 DQS Delay:
4280 23:06:58.133783 DQS0 = 0, DQS1 = 0
4281 23:06:58.134329 DQM Delay:
4282 23:06:58.134688 DQM0 = 43, DQM1 = 36
4283 23:06:58.136972 DQ Delay:
4284 23:06:58.140300 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4285 23:06:58.143341 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4286 23:06:58.146757 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4287 23:06:58.150129 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =41
4288 23:06:58.150781
4289 23:06:58.151167
4290 23:06:58.151781 ==
4291 23:06:58.152634 Dram Type= 6, Freq= 0, CH_0, rank 1
4292 23:06:58.155956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4293 23:06:58.156416 ==
4294 23:06:58.156776
4295 23:06:58.157109
4296 23:06:58.159789 TX Vref Scan disable
4297 23:06:58.162823 == TX Byte 0 ==
4298 23:06:58.166348 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4299 23:06:58.169617 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4300 23:06:58.172767 == TX Byte 1 ==
4301 23:06:58.176491 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4302 23:06:58.179208 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4303 23:06:58.179619 ==
4304 23:06:58.182725 Dram Type= 6, Freq= 0, CH_0, rank 1
4305 23:06:58.186227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4306 23:06:58.189781 ==
4307 23:06:58.190188
4308 23:06:58.190618
4309 23:06:58.191073 TX Vref Scan disable
4310 23:06:58.193136 == TX Byte 0 ==
4311 23:06:58.196218 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4312 23:06:58.202927 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4313 23:06:58.203338 == TX Byte 1 ==
4314 23:06:58.205966 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4315 23:06:58.212477 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4316 23:06:58.212886
4317 23:06:58.213211 [DATLAT]
4318 23:06:58.213567 Freq=600, CH0 RK1
4319 23:06:58.213881
4320 23:06:58.215780 DATLAT Default: 0x9
4321 23:06:58.218853 0, 0xFFFF, sum = 0
4322 23:06:58.219293 1, 0xFFFF, sum = 0
4323 23:06:58.222850 2, 0xFFFF, sum = 0
4324 23:06:58.223264 3, 0xFFFF, sum = 0
4325 23:06:58.225567 4, 0xFFFF, sum = 0
4326 23:06:58.225981 5, 0xFFFF, sum = 0
4327 23:06:58.229311 6, 0xFFFF, sum = 0
4328 23:06:58.229727 7, 0xFFFF, sum = 0
4329 23:06:58.232099 8, 0x0, sum = 1
4330 23:06:58.232513 9, 0x0, sum = 2
4331 23:06:58.235951 10, 0x0, sum = 3
4332 23:06:58.236458 11, 0x0, sum = 4
4333 23:06:58.236792 best_step = 9
4334 23:06:58.237094
4335 23:06:58.239415 ==
4336 23:06:58.242892 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 23:06:58.246068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 23:06:58.246580 ==
4339 23:06:58.246912 RX Vref Scan: 0
4340 23:06:58.247210
4341 23:06:58.248529 RX Vref 0 -> 0, step: 1
4342 23:06:58.248941
4343 23:06:58.251916 RX Delay -179 -> 252, step: 8
4344 23:06:58.258890 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4345 23:06:58.262207 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4346 23:06:58.265171 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4347 23:06:58.268801 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4348 23:06:58.275588 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4349 23:06:58.278887 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4350 23:06:58.282436 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4351 23:06:58.285380 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4352 23:06:58.288615 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4353 23:06:58.295384 iDelay=205, Bit 9, Center 24 (-123 ~ 172) 296
4354 23:06:58.297988 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4355 23:06:58.301778 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4356 23:06:58.304869 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4357 23:06:58.311652 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4358 23:06:58.314944 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4359 23:06:58.318091 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4360 23:06:58.318602 ==
4361 23:06:58.321338 Dram Type= 6, Freq= 0, CH_0, rank 1
4362 23:06:58.324331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 23:06:58.328080 ==
4364 23:06:58.328586 DQS Delay:
4365 23:06:58.328910 DQS0 = 0, DQS1 = 0
4366 23:06:58.331101 DQM Delay:
4367 23:06:58.331603 DQM0 = 42, DQM1 = 37
4368 23:06:58.335109 DQ Delay:
4369 23:06:58.338398 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4370 23:06:58.338902 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4371 23:06:58.340990 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =28
4372 23:06:58.347250 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4373 23:06:58.347789
4374 23:06:58.348118
4375 23:06:58.354279 [DQSOSCAuto] RK1, (LSB)MR18= 0x6518, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 390 ps
4376 23:06:58.357769 CH0 RK1: MR19=808, MR18=6518
4377 23:06:58.364155 CH0_RK1: MR19=0x808, MR18=0x6518, DQSOSC=390, MR23=63, INC=172, DEC=114
4378 23:06:58.367519 [RxdqsGatingPostProcess] freq 600
4379 23:06:58.370550 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4380 23:06:58.373687 Pre-setting of DQS Precalculation
4381 23:06:58.380152 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4382 23:06:58.380608 ==
4383 23:06:58.383509 Dram Type= 6, Freq= 0, CH_1, rank 0
4384 23:06:58.387089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 23:06:58.387636 ==
4386 23:06:58.393382 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4387 23:06:58.400200 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4388 23:06:58.404165 [CA 0] Center 35 (5~66) winsize 62
4389 23:06:58.406591 [CA 1] Center 35 (5~66) winsize 62
4390 23:06:58.409728 [CA 2] Center 34 (4~65) winsize 62
4391 23:06:58.413761 [CA 3] Center 33 (3~64) winsize 62
4392 23:06:58.416854 [CA 4] Center 34 (3~65) winsize 63
4393 23:06:58.419590 [CA 5] Center 33 (3~64) winsize 62
4394 23:06:58.420155
4395 23:06:58.423220 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4396 23:06:58.423822
4397 23:06:58.426687 [CATrainingPosCal] consider 1 rank data
4398 23:06:58.430141 u2DelayCellTimex100 = 270/100 ps
4399 23:06:58.432875 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4400 23:06:58.436668 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4401 23:06:58.440150 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4402 23:06:58.443638 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4403 23:06:58.447387 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4404 23:06:58.453174 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4405 23:06:58.453725
4406 23:06:58.457586 CA PerBit enable=1, Macro0, CA PI delay=33
4407 23:06:58.458322
4408 23:06:58.459350 [CBTSetCACLKResult] CA Dly = 33
4409 23:06:58.459842 CS Dly: 4 (0~35)
4410 23:06:58.460208 ==
4411 23:06:58.463076 Dram Type= 6, Freq= 0, CH_1, rank 1
4412 23:06:58.466412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 23:06:58.469320 ==
4414 23:06:58.472640 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4415 23:06:58.479651 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4416 23:06:58.482441 [CA 0] Center 35 (5~66) winsize 62
4417 23:06:58.485733 [CA 1] Center 36 (6~66) winsize 61
4418 23:06:58.489541 [CA 2] Center 34 (4~65) winsize 62
4419 23:06:58.492441 [CA 3] Center 34 (3~65) winsize 63
4420 23:06:58.495735 [CA 4] Center 34 (4~65) winsize 62
4421 23:06:58.499010 [CA 5] Center 34 (3~65) winsize 63
4422 23:06:58.499558
4423 23:06:58.501979 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4424 23:06:58.502463
4425 23:06:58.505513 [CATrainingPosCal] consider 2 rank data
4426 23:06:58.508696 u2DelayCellTimex100 = 270/100 ps
4427 23:06:58.511666 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4428 23:06:58.515264 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4429 23:06:58.521823 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4430 23:06:58.525344 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4431 23:06:58.528349 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4432 23:06:58.532549 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4433 23:06:58.533104
4434 23:06:58.535503 CA PerBit enable=1, Macro0, CA PI delay=33
4435 23:06:58.536093
4436 23:06:58.538505 [CBTSetCACLKResult] CA Dly = 33
4437 23:06:58.539053 CS Dly: 5 (0~37)
4438 23:06:58.541539
4439 23:06:58.544825 ----->DramcWriteLeveling(PI) begin...
4440 23:06:58.545392 ==
4441 23:06:58.548436 Dram Type= 6, Freq= 0, CH_1, rank 0
4442 23:06:58.551467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4443 23:06:58.552050 ==
4444 23:06:58.555095 Write leveling (Byte 0): 31 => 31
4445 23:06:58.558178 Write leveling (Byte 1): 31 => 31
4446 23:06:58.561494 DramcWriteLeveling(PI) end<-----
4447 23:06:58.562045
4448 23:06:58.562464 ==
4449 23:06:58.564428 Dram Type= 6, Freq= 0, CH_1, rank 0
4450 23:06:58.567653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4451 23:06:58.568247 ==
4452 23:06:58.572250 [Gating] SW mode calibration
4453 23:06:58.577634 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4454 23:06:58.584094 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4455 23:06:58.588344 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4456 23:06:58.590775 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4457 23:06:58.597995 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4458 23:06:58.600814 0 9 12 | B1->B0 | 3131 2f2f | 0 0 | (0 1) (1 1)
4459 23:06:58.604695 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4460 23:06:58.610821 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 23:06:58.614309 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 23:06:58.617550 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 23:06:58.623636 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 23:06:58.627444 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 23:06:58.630977 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4466 23:06:58.636934 0 10 12 | B1->B0 | 3535 3838 | 0 0 | (0 0) (1 1)
4467 23:06:58.640382 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4468 23:06:58.643560 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 23:06:58.651309 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 23:06:58.653714 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 23:06:58.656725 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 23:06:58.663606 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 23:06:58.667129 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 23:06:58.670055 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4475 23:06:58.676113 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4476 23:06:58.680709 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 23:06:58.682748 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 23:06:58.690064 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 23:06:58.692608 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 23:06:58.696165 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 23:06:58.703265 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 23:06:58.706017 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 23:06:58.709252 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 23:06:58.716099 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 23:06:58.719842 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 23:06:58.722489 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 23:06:58.729343 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 23:06:58.732660 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 23:06:58.735830 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4490 23:06:58.742817 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4491 23:06:58.745999 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4492 23:06:58.749304 Total UI for P1: 0, mck2ui 16
4493 23:06:58.752650 best dqsien dly found for B0: ( 0, 13, 10)
4494 23:06:58.755665 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 23:06:58.759439 Total UI for P1: 0, mck2ui 16
4496 23:06:58.762419 best dqsien dly found for B1: ( 0, 13, 14)
4497 23:06:58.765619 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4498 23:06:58.772221 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4499 23:06:58.772757
4500 23:06:58.775931 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4501 23:06:58.778660 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4502 23:06:58.782172 [Gating] SW calibration Done
4503 23:06:58.782727 ==
4504 23:06:58.785437 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 23:06:58.789029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 23:06:58.789588 ==
4507 23:06:58.791990 RX Vref Scan: 0
4508 23:06:58.792446
4509 23:06:58.792807 RX Vref 0 -> 0, step: 1
4510 23:06:58.793146
4511 23:06:58.794861 RX Delay -230 -> 252, step: 16
4512 23:06:58.798688 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4513 23:06:58.806006 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4514 23:06:58.808281 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4515 23:06:58.811841 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4516 23:06:58.815257 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4517 23:06:58.821307 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4518 23:06:58.824709 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4519 23:06:58.828187 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4520 23:06:58.831625 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4521 23:06:58.834848 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4522 23:06:58.841253 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4523 23:06:58.844683 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4524 23:06:58.848077 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4525 23:06:58.851715 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4526 23:06:58.857635 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4527 23:06:58.860989 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4528 23:06:58.861541 ==
4529 23:06:58.864077 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 23:06:58.868105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 23:06:58.868662 ==
4532 23:06:58.871046 DQS Delay:
4533 23:06:58.871596 DQS0 = 0, DQS1 = 0
4534 23:06:58.874333 DQM Delay:
4535 23:06:58.874789 DQM0 = 46, DQM1 = 37
4536 23:06:58.875154 DQ Delay:
4537 23:06:58.877872 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4538 23:06:58.880970 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4539 23:06:58.884504 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4540 23:06:58.888094 DQ12 =49, DQ13 =41, DQ14 =49, DQ15 =49
4541 23:06:58.888659
4542 23:06:58.889023
4543 23:06:58.890704 ==
4544 23:06:58.894173 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 23:06:58.897408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 23:06:58.897964 ==
4547 23:06:58.898332
4548 23:06:58.898665
4549 23:06:58.900345 TX Vref Scan disable
4550 23:06:58.900800 == TX Byte 0 ==
4551 23:06:58.907181 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4552 23:06:58.910469 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4553 23:06:58.911021 == TX Byte 1 ==
4554 23:06:58.916908 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4555 23:06:58.920424 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4556 23:06:58.920931 ==
4557 23:06:58.923486 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 23:06:58.927622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 23:06:58.928198 ==
4560 23:06:58.928534
4561 23:06:58.928839
4562 23:06:58.930432 TX Vref Scan disable
4563 23:06:58.933539 == TX Byte 0 ==
4564 23:06:58.937460 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4565 23:06:58.940776 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4566 23:06:58.943569 == TX Byte 1 ==
4567 23:06:58.947002 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4568 23:06:58.950222 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4569 23:06:58.950733
4570 23:06:58.953262 [DATLAT]
4571 23:06:58.953677 Freq=600, CH1 RK0
4572 23:06:58.954005
4573 23:06:58.956620 DATLAT Default: 0x9
4574 23:06:58.957132 0, 0xFFFF, sum = 0
4575 23:06:58.959999 1, 0xFFFF, sum = 0
4576 23:06:58.960518 2, 0xFFFF, sum = 0
4577 23:06:58.963613 3, 0xFFFF, sum = 0
4578 23:06:58.964157 4, 0xFFFF, sum = 0
4579 23:06:58.966941 5, 0xFFFF, sum = 0
4580 23:06:58.969998 6, 0xFFFF, sum = 0
4581 23:06:58.970520 7, 0xFFFF, sum = 0
4582 23:06:58.973334 8, 0x0, sum = 1
4583 23:06:58.973866 9, 0x0, sum = 2
4584 23:06:58.974206 10, 0x0, sum = 3
4585 23:06:58.976429 11, 0x0, sum = 4
4586 23:06:58.976919 best_step = 9
4587 23:06:58.977254
4588 23:06:58.977559 ==
4589 23:06:58.979240 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 23:06:58.986341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 23:06:58.986857 ==
4592 23:06:58.987194 RX Vref Scan: 1
4593 23:06:58.987502
4594 23:06:58.989429 RX Vref 0 -> 0, step: 1
4595 23:06:58.989843
4596 23:06:58.992841 RX Delay -195 -> 252, step: 8
4597 23:06:58.993258
4598 23:06:58.996477 Set Vref, RX VrefLevel [Byte0]: 47
4599 23:06:59.000051 [Byte1]: 59
4600 23:06:59.000466
4601 23:06:59.002682 Final RX Vref Byte 0 = 47 to rank0
4602 23:06:59.006721 Final RX Vref Byte 1 = 59 to rank0
4603 23:06:59.009121 Final RX Vref Byte 0 = 47 to rank1
4604 23:06:59.012367 Final RX Vref Byte 1 = 59 to rank1==
4605 23:06:59.016154 Dram Type= 6, Freq= 0, CH_1, rank 0
4606 23:06:59.019822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 23:06:59.022811 ==
4608 23:06:59.023319 DQS Delay:
4609 23:06:59.023650 DQS0 = 0, DQS1 = 0
4610 23:06:59.025775 DQM Delay:
4611 23:06:59.026312 DQM0 = 48, DQM1 = 38
4612 23:06:59.028671 DQ Delay:
4613 23:06:59.029090 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =44
4614 23:06:59.032417 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =40
4615 23:06:59.035766 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4616 23:06:59.038729 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4617 23:06:59.039236
4618 23:06:59.042031
4619 23:06:59.048528 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d32, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4620 23:06:59.052673 CH1 RK0: MR19=808, MR18=4D32
4621 23:06:59.058558 CH1_RK0: MR19=0x808, MR18=0x4D32, DQSOSC=395, MR23=63, INC=168, DEC=112
4622 23:06:59.059057
4623 23:06:59.061991 ----->DramcWriteLeveling(PI) begin...
4624 23:06:59.062417 ==
4625 23:06:59.065233 Dram Type= 6, Freq= 0, CH_1, rank 1
4626 23:06:59.068775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 23:06:59.069289 ==
4628 23:06:59.072352 Write leveling (Byte 0): 29 => 29
4629 23:06:59.075029 Write leveling (Byte 1): 30 => 30
4630 23:06:59.078585 DramcWriteLeveling(PI) end<-----
4631 23:06:59.079097
4632 23:06:59.079423 ==
4633 23:06:59.082088 Dram Type= 6, Freq= 0, CH_1, rank 1
4634 23:06:59.084862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 23:06:59.085284 ==
4636 23:06:59.088630 [Gating] SW mode calibration
4637 23:06:59.094958 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4638 23:06:59.101631 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4639 23:06:59.105274 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4640 23:06:59.111422 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4641 23:06:59.115441 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4642 23:06:59.118900 0 9 12 | B1->B0 | 2f2f 3434 | 1 0 | (1 0) (1 0)
4643 23:06:59.124889 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4644 23:06:59.127795 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 23:06:59.131379 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 23:06:59.139009 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 23:06:59.141342 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 23:06:59.144964 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 23:06:59.148383 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4650 23:06:59.155017 0 10 12 | B1->B0 | 3232 2a2a | 0 0 | (0 0) (0 0)
4651 23:06:59.158029 0 10 16 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
4652 23:06:59.161295 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 23:06:59.167798 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 23:06:59.171165 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 23:06:59.174371 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 23:06:59.180920 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 23:06:59.184460 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 23:06:59.187540 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4659 23:06:59.193948 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 23:06:59.197453 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 23:06:59.200625 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 23:06:59.207396 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 23:06:59.210676 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 23:06:59.214085 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 23:06:59.221113 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 23:06:59.224063 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 23:06:59.226821 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 23:06:59.233597 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 23:06:59.236967 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 23:06:59.240325 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 23:06:59.246458 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 23:06:59.250006 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 23:06:59.253501 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 23:06:59.260150 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4675 23:06:59.263474 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 23:06:59.267285 Total UI for P1: 0, mck2ui 16
4677 23:06:59.269759 best dqsien dly found for B0: ( 0, 13, 12)
4678 23:06:59.273349 Total UI for P1: 0, mck2ui 16
4679 23:06:59.277086 best dqsien dly found for B1: ( 0, 13, 14)
4680 23:06:59.280192 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4681 23:06:59.282887 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4682 23:06:59.283302
4683 23:06:59.286956 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4684 23:06:59.293040 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4685 23:06:59.293534 [Gating] SW calibration Done
4686 23:06:59.293880 ==
4687 23:06:59.296609 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 23:06:59.303072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 23:06:59.303590 ==
4690 23:06:59.304026 RX Vref Scan: 0
4691 23:06:59.304344
4692 23:06:59.306294 RX Vref 0 -> 0, step: 1
4693 23:06:59.306802
4694 23:06:59.309877 RX Delay -230 -> 252, step: 16
4695 23:06:59.312630 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4696 23:06:59.316003 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4697 23:06:59.323023 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4698 23:06:59.326522 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4699 23:06:59.329665 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4700 23:06:59.332868 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4701 23:06:59.336265 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4702 23:06:59.342690 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4703 23:06:59.346180 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4704 23:06:59.349243 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4705 23:06:59.352657 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4706 23:06:59.358973 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4707 23:06:59.363080 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4708 23:06:59.365446 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4709 23:06:59.369060 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4710 23:06:59.375535 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4711 23:06:59.376196 ==
4712 23:06:59.379504 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 23:06:59.382236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 23:06:59.382787 ==
4715 23:06:59.383225 DQS Delay:
4716 23:06:59.385073 DQS0 = 0, DQS1 = 0
4717 23:06:59.385533 DQM Delay:
4718 23:06:59.389526 DQM0 = 44, DQM1 = 37
4719 23:06:59.390079 DQ Delay:
4720 23:06:59.392311 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4721 23:06:59.395803 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4722 23:06:59.398912 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4723 23:06:59.401879 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4724 23:06:59.402431
4725 23:06:59.402793
4726 23:06:59.403129 ==
4727 23:06:59.405084 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 23:06:59.408835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 23:06:59.411857 ==
4730 23:06:59.412312
4731 23:06:59.412779
4732 23:06:59.413130 TX Vref Scan disable
4733 23:06:59.414876 == TX Byte 0 ==
4734 23:06:59.417901 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4735 23:06:59.424644 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4736 23:06:59.425061 == TX Byte 1 ==
4737 23:06:59.427734 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4738 23:06:59.435014 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4739 23:06:59.435524 ==
4740 23:06:59.437823 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 23:06:59.440909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 23:06:59.441325 ==
4743 23:06:59.441655
4744 23:06:59.441957
4745 23:06:59.444423 TX Vref Scan disable
4746 23:06:59.447744 == TX Byte 0 ==
4747 23:06:59.451135 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4748 23:06:59.454565 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4749 23:06:59.457517 == TX Byte 1 ==
4750 23:06:59.461652 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4751 23:06:59.464499 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4752 23:06:59.464910
4753 23:06:59.465236 [DATLAT]
4754 23:06:59.468336 Freq=600, CH1 RK1
4755 23:06:59.468852
4756 23:06:59.471042 DATLAT Default: 0x9
4757 23:06:59.471600 0, 0xFFFF, sum = 0
4758 23:06:59.474284 1, 0xFFFF, sum = 0
4759 23:06:59.474849 2, 0xFFFF, sum = 0
4760 23:06:59.477724 3, 0xFFFF, sum = 0
4761 23:06:59.478145 4, 0xFFFF, sum = 0
4762 23:06:59.481034 5, 0xFFFF, sum = 0
4763 23:06:59.481557 6, 0xFFFF, sum = 0
4764 23:06:59.484209 7, 0xFFFF, sum = 0
4765 23:06:59.484640 8, 0x0, sum = 1
4766 23:06:59.488327 9, 0x0, sum = 2
4767 23:06:59.488848 10, 0x0, sum = 3
4768 23:06:59.491327 11, 0x0, sum = 4
4769 23:06:59.491898 best_step = 9
4770 23:06:59.492233
4771 23:06:59.492535 ==
4772 23:06:59.494567 Dram Type= 6, Freq= 0, CH_1, rank 1
4773 23:06:59.497397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4774 23:06:59.497813 ==
4775 23:06:59.500886 RX Vref Scan: 0
4776 23:06:59.501295
4777 23:06:59.503920 RX Vref 0 -> 0, step: 1
4778 23:06:59.504330
4779 23:06:59.504658 RX Delay -195 -> 252, step: 8
4780 23:06:59.512420 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4781 23:06:59.515773 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4782 23:06:59.518483 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4783 23:06:59.521742 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4784 23:06:59.528604 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4785 23:06:59.532189 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4786 23:06:59.535095 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4787 23:06:59.539205 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4788 23:06:59.541827 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4789 23:06:59.548815 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4790 23:06:59.551585 iDelay=213, Bit 10, Center 40 (-115 ~ 196) 312
4791 23:06:59.555071 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4792 23:06:59.558598 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4793 23:06:59.564549 iDelay=213, Bit 13, Center 48 (-107 ~ 204) 312
4794 23:06:59.568013 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4795 23:06:59.571095 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4796 23:06:59.571625 ==
4797 23:06:59.574415 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 23:06:59.581036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 23:06:59.581585 ==
4800 23:06:59.581946 DQS Delay:
4801 23:06:59.584140 DQS0 = 0, DQS1 = 0
4802 23:06:59.584593 DQM Delay:
4803 23:06:59.584952 DQM0 = 45, DQM1 = 37
4804 23:06:59.588221 DQ Delay:
4805 23:06:59.590949 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4806 23:06:59.594956 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4807 23:06:59.598023 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4808 23:06:59.600719 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =48
4809 23:06:59.601176
4810 23:06:59.601532
4811 23:06:59.607512 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 400 ps
4812 23:06:59.610849 CH1 RK1: MR19=808, MR18=2F22
4813 23:06:59.617307 CH1_RK1: MR19=0x808, MR18=0x2F22, DQSOSC=400, MR23=63, INC=163, DEC=109
4814 23:06:59.620571 [RxdqsGatingPostProcess] freq 600
4815 23:06:59.624629 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4816 23:06:59.627325 Pre-setting of DQS Precalculation
4817 23:06:59.633770 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4818 23:06:59.640850 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4819 23:06:59.647178 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4820 23:06:59.647784
4821 23:06:59.648153
4822 23:06:59.650739 [Calibration Summary] 1200 Mbps
4823 23:06:59.653557 CH 0, Rank 0
4824 23:06:59.654107 SW Impedance : PASS
4825 23:06:59.656812 DUTY Scan : NO K
4826 23:06:59.659889 ZQ Calibration : PASS
4827 23:06:59.660545 Jitter Meter : NO K
4828 23:06:59.663476 CBT Training : PASS
4829 23:06:59.664078 Write leveling : PASS
4830 23:06:59.666609 RX DQS gating : PASS
4831 23:06:59.670306 RX DQ/DQS(RDDQC) : PASS
4832 23:06:59.670856 TX DQ/DQS : PASS
4833 23:06:59.673192 RX DATLAT : PASS
4834 23:06:59.676746 RX DQ/DQS(Engine): PASS
4835 23:06:59.677298 TX OE : NO K
4836 23:06:59.680385 All Pass.
4837 23:06:59.680954
4838 23:06:59.681321 CH 0, Rank 1
4839 23:06:59.683493 SW Impedance : PASS
4840 23:06:59.684012 DUTY Scan : NO K
4841 23:06:59.686391 ZQ Calibration : PASS
4842 23:06:59.689951 Jitter Meter : NO K
4843 23:06:59.690405 CBT Training : PASS
4844 23:06:59.692950 Write leveling : PASS
4845 23:06:59.696482 RX DQS gating : PASS
4846 23:06:59.697050 RX DQ/DQS(RDDQC) : PASS
4847 23:06:59.700873 TX DQ/DQS : PASS
4848 23:06:59.703281 RX DATLAT : PASS
4849 23:06:59.703789 RX DQ/DQS(Engine): PASS
4850 23:06:59.706701 TX OE : NO K
4851 23:06:59.707267 All Pass.
4852 23:06:59.707638
4853 23:06:59.709762 CH 1, Rank 0
4854 23:06:59.710214 SW Impedance : PASS
4855 23:06:59.712616 DUTY Scan : NO K
4856 23:06:59.716196 ZQ Calibration : PASS
4857 23:06:59.716607 Jitter Meter : NO K
4858 23:06:59.719225 CBT Training : PASS
4859 23:06:59.722789 Write leveling : PASS
4860 23:06:59.723291 RX DQS gating : PASS
4861 23:06:59.726109 RX DQ/DQS(RDDQC) : PASS
4862 23:06:59.730219 TX DQ/DQS : PASS
4863 23:06:59.730733 RX DATLAT : PASS
4864 23:06:59.732374 RX DQ/DQS(Engine): PASS
4865 23:06:59.735781 TX OE : NO K
4866 23:06:59.736195 All Pass.
4867 23:06:59.736522
4868 23:06:59.736822 CH 1, Rank 1
4869 23:06:59.739447 SW Impedance : PASS
4870 23:06:59.742725 DUTY Scan : NO K
4871 23:06:59.743246 ZQ Calibration : PASS
4872 23:06:59.746160 Jitter Meter : NO K
4873 23:06:59.746671 CBT Training : PASS
4874 23:06:59.749100 Write leveling : PASS
4875 23:06:59.752458 RX DQS gating : PASS
4876 23:06:59.752915 RX DQ/DQS(RDDQC) : PASS
4877 23:06:59.755627 TX DQ/DQS : PASS
4878 23:06:59.759362 RX DATLAT : PASS
4879 23:06:59.759956 RX DQ/DQS(Engine): PASS
4880 23:06:59.762415 TX OE : NO K
4881 23:06:59.762872 All Pass.
4882 23:06:59.763233
4883 23:06:59.765942 DramC Write-DBI off
4884 23:06:59.768773 PER_BANK_REFRESH: Hybrid Mode
4885 23:06:59.769225 TX_TRACKING: ON
4886 23:06:59.778895 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4887 23:06:59.782267 [FAST_K] Save calibration result to emmc
4888 23:06:59.785441 dramc_set_vcore_voltage set vcore to 662500
4889 23:06:59.788631 Read voltage for 933, 3
4890 23:06:59.789222 Vio18 = 0
4891 23:06:59.792081 Vcore = 662500
4892 23:06:59.792529 Vdram = 0
4893 23:06:59.792928 Vddq = 0
4894 23:06:59.793262 Vmddr = 0
4895 23:06:59.798724 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4896 23:06:59.804957 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4897 23:06:59.805370 MEM_TYPE=3, freq_sel=17
4898 23:06:59.808176 sv_algorithm_assistance_LP4_1600
4899 23:06:59.812368 ============ PULL DRAM RESETB DOWN ============
4900 23:06:59.818151 ========== PULL DRAM RESETB DOWN end =========
4901 23:06:59.821818 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4902 23:06:59.824755 ===================================
4903 23:06:59.828368 LPDDR4 DRAM CONFIGURATION
4904 23:06:59.831442 ===================================
4905 23:06:59.831991 EX_ROW_EN[0] = 0x0
4906 23:06:59.835068 EX_ROW_EN[1] = 0x0
4907 23:06:59.835625 LP4Y_EN = 0x0
4908 23:06:59.837987 WORK_FSP = 0x0
4909 23:06:59.838538 WL = 0x3
4910 23:06:59.841758 RL = 0x3
4911 23:06:59.844410 BL = 0x2
4912 23:06:59.844962 RPST = 0x0
4913 23:06:59.848029 RD_PRE = 0x0
4914 23:06:59.848579 WR_PRE = 0x1
4915 23:06:59.851231 WR_PST = 0x0
4916 23:06:59.851905 DBI_WR = 0x0
4917 23:06:59.854550 DBI_RD = 0x0
4918 23:06:59.855101 OTF = 0x1
4919 23:06:59.858086 ===================================
4920 23:06:59.861391 ===================================
4921 23:06:59.864201 ANA top config
4922 23:06:59.867569 ===================================
4923 23:06:59.868167 DLL_ASYNC_EN = 0
4924 23:06:59.870839 ALL_SLAVE_EN = 1
4925 23:06:59.874689 NEW_RANK_MODE = 1
4926 23:06:59.878096 DLL_IDLE_MODE = 1
4927 23:06:59.881210 LP45_APHY_COMB_EN = 1
4928 23:06:59.881777 TX_ODT_DIS = 1
4929 23:06:59.883930 NEW_8X_MODE = 1
4930 23:06:59.887790 ===================================
4931 23:06:59.890442 ===================================
4932 23:06:59.894017 data_rate = 1866
4933 23:06:59.896986 CKR = 1
4934 23:06:59.901031 DQ_P2S_RATIO = 8
4935 23:06:59.903602 ===================================
4936 23:06:59.907256 CA_P2S_RATIO = 8
4937 23:06:59.907844 DQ_CA_OPEN = 0
4938 23:06:59.910225 DQ_SEMI_OPEN = 0
4939 23:06:59.913558 CA_SEMI_OPEN = 0
4940 23:06:59.916927 CA_FULL_RATE = 0
4941 23:06:59.920290 DQ_CKDIV4_EN = 1
4942 23:06:59.923619 CA_CKDIV4_EN = 1
4943 23:06:59.924105 CA_PREDIV_EN = 0
4944 23:06:59.927302 PH8_DLY = 0
4945 23:06:59.930977 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4946 23:06:59.934074 DQ_AAMCK_DIV = 4
4947 23:06:59.936939 CA_AAMCK_DIV = 4
4948 23:06:59.940985 CA_ADMCK_DIV = 4
4949 23:06:59.941537 DQ_TRACK_CA_EN = 0
4950 23:06:59.943777 CA_PICK = 933
4951 23:06:59.947428 CA_MCKIO = 933
4952 23:06:59.950346 MCKIO_SEMI = 0
4953 23:06:59.954332 PLL_FREQ = 3732
4954 23:06:59.957107 DQ_UI_PI_RATIO = 32
4955 23:06:59.960613 CA_UI_PI_RATIO = 0
4956 23:06:59.964287 ===================================
4957 23:06:59.966535 ===================================
4958 23:06:59.966986 memory_type:LPDDR4
4959 23:06:59.970704 GP_NUM : 10
4960 23:06:59.973027 SRAM_EN : 1
4961 23:06:59.973490 MD32_EN : 0
4962 23:06:59.976348 ===================================
4963 23:06:59.980125 [ANA_INIT] >>>>>>>>>>>>>>
4964 23:06:59.983905 <<<<<< [CONFIGURE PHASE]: ANA_TX
4965 23:06:59.986528 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4966 23:06:59.990025 ===================================
4967 23:06:59.992892 data_rate = 1866,PCW = 0X8f00
4968 23:06:59.996712 ===================================
4969 23:06:59.999431 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4970 23:07:00.003264 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4971 23:07:00.009791 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4972 23:07:00.012667 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4973 23:07:00.015806 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4974 23:07:00.019661 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4975 23:07:00.023246 [ANA_INIT] flow start
4976 23:07:00.026458 [ANA_INIT] PLL >>>>>>>>
4977 23:07:00.027006 [ANA_INIT] PLL <<<<<<<<
4978 23:07:00.030069 [ANA_INIT] MIDPI >>>>>>>>
4979 23:07:00.032859 [ANA_INIT] MIDPI <<<<<<<<
4980 23:07:00.036050 [ANA_INIT] DLL >>>>>>>>
4981 23:07:00.036516 [ANA_INIT] flow end
4982 23:07:00.039399 ============ LP4 DIFF to SE enter ============
4983 23:07:00.045958 ============ LP4 DIFF to SE exit ============
4984 23:07:00.046505 [ANA_INIT] <<<<<<<<<<<<<
4985 23:07:00.049579 [Flow] Enable top DCM control >>>>>
4986 23:07:00.052347 [Flow] Enable top DCM control <<<<<
4987 23:07:00.056116 Enable DLL master slave shuffle
4988 23:07:00.062895 ==============================================================
4989 23:07:00.063445 Gating Mode config
4990 23:07:00.068874 ==============================================================
4991 23:07:00.072444 Config description:
4992 23:07:00.082304 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4993 23:07:00.089386 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4994 23:07:00.092019 SELPH_MODE 0: By rank 1: By Phase
4995 23:07:00.098562 ==============================================================
4996 23:07:00.101979 GAT_TRACK_EN = 1
4997 23:07:00.105020 RX_GATING_MODE = 2
4998 23:07:00.108559 RX_GATING_TRACK_MODE = 2
4999 23:07:00.109050 SELPH_MODE = 1
5000 23:07:00.111724 PICG_EARLY_EN = 1
5001 23:07:00.115344 VALID_LAT_VALUE = 1
5002 23:07:00.122081 ==============================================================
5003 23:07:00.125378 Enter into Gating configuration >>>>
5004 23:07:00.128418 Exit from Gating configuration <<<<
5005 23:07:00.131660 Enter into DVFS_PRE_config >>>>>
5006 23:07:00.142499 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5007 23:07:00.145166 Exit from DVFS_PRE_config <<<<<
5008 23:07:00.148261 Enter into PICG configuration >>>>
5009 23:07:00.151855 Exit from PICG configuration <<<<
5010 23:07:00.155138 [RX_INPUT] configuration >>>>>
5011 23:07:00.158509 [RX_INPUT] configuration <<<<<
5012 23:07:00.162253 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5013 23:07:00.168040 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5014 23:07:00.174562 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5015 23:07:00.181426 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5016 23:07:00.187976 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5017 23:07:00.191208 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5018 23:07:00.197893 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5019 23:07:00.201761 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5020 23:07:00.204174 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5021 23:07:00.207518 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5022 23:07:00.214215 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5023 23:07:00.217065 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5024 23:07:00.220441 ===================================
5025 23:07:00.223873 LPDDR4 DRAM CONFIGURATION
5026 23:07:00.227361 ===================================
5027 23:07:00.228168 EX_ROW_EN[0] = 0x0
5028 23:07:00.230758 EX_ROW_EN[1] = 0x0
5029 23:07:00.231320 LP4Y_EN = 0x0
5030 23:07:00.235637 WORK_FSP = 0x0
5031 23:07:00.237140 WL = 0x3
5032 23:07:00.237587 RL = 0x3
5033 23:07:00.240450 BL = 0x2
5034 23:07:00.241000 RPST = 0x0
5035 23:07:00.243989 RD_PRE = 0x0
5036 23:07:00.244439 WR_PRE = 0x1
5037 23:07:00.247368 WR_PST = 0x0
5038 23:07:00.247997 DBI_WR = 0x0
5039 23:07:00.250703 DBI_RD = 0x0
5040 23:07:00.251250 OTF = 0x1
5041 23:07:00.253635 ===================================
5042 23:07:00.257449 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5043 23:07:00.263376 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5044 23:07:00.266945 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5045 23:07:00.270554 ===================================
5046 23:07:00.273227 LPDDR4 DRAM CONFIGURATION
5047 23:07:00.276412 ===================================
5048 23:07:00.276864 EX_ROW_EN[0] = 0x10
5049 23:07:00.279668 EX_ROW_EN[1] = 0x0
5050 23:07:00.283360 LP4Y_EN = 0x0
5051 23:07:00.284010 WORK_FSP = 0x0
5052 23:07:00.286646 WL = 0x3
5053 23:07:00.287163 RL = 0x3
5054 23:07:00.289824 BL = 0x2
5055 23:07:00.290303 RPST = 0x0
5056 23:07:00.293240 RD_PRE = 0x0
5057 23:07:00.293694 WR_PRE = 0x1
5058 23:07:00.296555 WR_PST = 0x0
5059 23:07:00.297139 DBI_WR = 0x0
5060 23:07:00.300188 DBI_RD = 0x0
5061 23:07:00.300706 OTF = 0x1
5062 23:07:00.303288 ===================================
5063 23:07:00.310013 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5064 23:07:00.313426 nWR fixed to 30
5065 23:07:00.317019 [ModeRegInit_LP4] CH0 RK0
5066 23:07:00.317497 [ModeRegInit_LP4] CH0 RK1
5067 23:07:00.320295 [ModeRegInit_LP4] CH1 RK0
5068 23:07:00.323505 [ModeRegInit_LP4] CH1 RK1
5069 23:07:00.324033 match AC timing 9
5070 23:07:00.330885 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5071 23:07:00.334216 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5072 23:07:00.336775 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5073 23:07:00.343077 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5074 23:07:00.346771 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5075 23:07:00.347184 ==
5076 23:07:00.349759 Dram Type= 6, Freq= 0, CH_0, rank 0
5077 23:07:00.353379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5078 23:07:00.357031 ==
5079 23:07:00.359964 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5080 23:07:00.366339 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5081 23:07:00.370016 [CA 0] Center 37 (7~68) winsize 62
5082 23:07:00.374091 [CA 1] Center 37 (7~68) winsize 62
5083 23:07:00.376513 [CA 2] Center 34 (4~65) winsize 62
5084 23:07:00.379872 [CA 3] Center 35 (5~65) winsize 61
5085 23:07:00.383540 [CA 4] Center 33 (3~64) winsize 62
5086 23:07:00.386333 [CA 5] Center 33 (3~64) winsize 62
5087 23:07:00.386745
5088 23:07:00.389899 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5089 23:07:00.390413
5090 23:07:00.392714 [CATrainingPosCal] consider 1 rank data
5091 23:07:00.396848 u2DelayCellTimex100 = 270/100 ps
5092 23:07:00.399368 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5093 23:07:00.402835 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5094 23:07:00.406008 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5095 23:07:00.412942 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5096 23:07:00.416018 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5097 23:07:00.419552 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5098 23:07:00.420194
5099 23:07:00.422800 CA PerBit enable=1, Macro0, CA PI delay=33
5100 23:07:00.423251
5101 23:07:00.425732 [CBTSetCACLKResult] CA Dly = 33
5102 23:07:00.426183 CS Dly: 7 (0~38)
5103 23:07:00.426542 ==
5104 23:07:00.429358 Dram Type= 6, Freq= 0, CH_0, rank 1
5105 23:07:00.435802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 23:07:00.436359 ==
5107 23:07:00.439551 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5108 23:07:00.445429 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5109 23:07:00.449504 [CA 0] Center 37 (7~68) winsize 62
5110 23:07:00.452265 [CA 1] Center 37 (7~68) winsize 62
5111 23:07:00.455837 [CA 2] Center 34 (4~65) winsize 62
5112 23:07:00.459422 [CA 3] Center 34 (4~65) winsize 62
5113 23:07:00.462242 [CA 4] Center 33 (3~64) winsize 62
5114 23:07:00.466004 [CA 5] Center 33 (3~63) winsize 61
5115 23:07:00.466554
5116 23:07:00.468650 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5117 23:07:00.469105
5118 23:07:00.472048 [CATrainingPosCal] consider 2 rank data
5119 23:07:00.475496 u2DelayCellTimex100 = 270/100 ps
5120 23:07:00.478888 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5121 23:07:00.485157 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5122 23:07:00.488436 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5123 23:07:00.492238 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5124 23:07:00.495808 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5125 23:07:00.498396 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5126 23:07:00.498852
5127 23:07:00.501629 CA PerBit enable=1, Macro0, CA PI delay=33
5128 23:07:00.502080
5129 23:07:00.505015 [CBTSetCACLKResult] CA Dly = 33
5130 23:07:00.508376 CS Dly: 7 (0~39)
5131 23:07:00.508829
5132 23:07:00.511604 ----->DramcWriteLeveling(PI) begin...
5133 23:07:00.512291 ==
5134 23:07:00.515181 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 23:07:00.518201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 23:07:00.518609 ==
5137 23:07:00.521799 Write leveling (Byte 0): 33 => 33
5138 23:07:00.524600 Write leveling (Byte 1): 30 => 30
5139 23:07:00.527799 DramcWriteLeveling(PI) end<-----
5140 23:07:00.528211
5141 23:07:00.528532 ==
5142 23:07:00.531569 Dram Type= 6, Freq= 0, CH_0, rank 0
5143 23:07:00.534550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 23:07:00.535064 ==
5145 23:07:00.538206 [Gating] SW mode calibration
5146 23:07:00.545005 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5147 23:07:00.551567 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5148 23:07:00.554684 0 14 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5149 23:07:00.560634 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5150 23:07:00.564207 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 23:07:00.567611 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 23:07:00.574399 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 23:07:00.577975 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 23:07:00.580761 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5155 23:07:00.587222 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5156 23:07:00.591090 0 15 0 | B1->B0 | 3434 2424 | 0 0 | (1 0) (0 0)
5157 23:07:00.593879 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 23:07:00.600582 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 23:07:00.603391 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 23:07:00.607473 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 23:07:00.613635 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 23:07:00.616977 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 23:07:00.620172 0 15 28 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5164 23:07:00.627000 1 0 0 | B1->B0 | 3333 4444 | 0 0 | (0 0) (0 0)
5165 23:07:00.630402 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 23:07:00.633233 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 23:07:00.640005 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 23:07:00.643740 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 23:07:00.646713 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 23:07:00.653856 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 23:07:00.656602 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5172 23:07:00.660359 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5173 23:07:00.666538 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5174 23:07:00.669948 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 23:07:00.673250 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 23:07:00.677129 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 23:07:00.683108 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 23:07:00.686369 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 23:07:00.689617 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 23:07:00.696331 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 23:07:00.699812 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 23:07:00.702891 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 23:07:00.709369 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 23:07:00.713235 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 23:07:00.716863 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 23:07:00.722330 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 23:07:00.726014 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 23:07:00.729126 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5189 23:07:00.732679 Total UI for P1: 0, mck2ui 16
5190 23:07:00.735444 best dqsien dly found for B0: ( 1, 2, 30)
5191 23:07:00.742543 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5192 23:07:00.746010 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 23:07:00.748999 Total UI for P1: 0, mck2ui 16
5194 23:07:00.752533 best dqsien dly found for B1: ( 1, 3, 2)
5195 23:07:00.756341 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5196 23:07:00.759129 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5197 23:07:00.759580
5198 23:07:00.762764 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5199 23:07:00.765909 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5200 23:07:00.769406 [Gating] SW calibration Done
5201 23:07:00.769858 ==
5202 23:07:00.772526 Dram Type= 6, Freq= 0, CH_0, rank 0
5203 23:07:00.778421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5204 23:07:00.778956 ==
5205 23:07:00.779314 RX Vref Scan: 0
5206 23:07:00.779646
5207 23:07:00.782370 RX Vref 0 -> 0, step: 1
5208 23:07:00.782915
5209 23:07:00.785002 RX Delay -80 -> 252, step: 8
5210 23:07:00.788907 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5211 23:07:00.792524 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5212 23:07:00.795584 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5213 23:07:00.798643 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5214 23:07:00.805055 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5215 23:07:00.808277 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5216 23:07:00.811792 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5217 23:07:00.814964 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5218 23:07:00.818474 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5219 23:07:00.824959 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5220 23:07:00.828459 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5221 23:07:00.832255 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5222 23:07:00.834865 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5223 23:07:00.837802 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5224 23:07:00.845419 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5225 23:07:00.848158 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5226 23:07:00.848622 ==
5227 23:07:00.851232 Dram Type= 6, Freq= 0, CH_0, rank 0
5228 23:07:00.854563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5229 23:07:00.855144 ==
5230 23:07:00.858013 DQS Delay:
5231 23:07:00.858527 DQS0 = 0, DQS1 = 0
5232 23:07:00.858905 DQM Delay:
5233 23:07:00.861084 DQM0 = 97, DQM1 = 85
5234 23:07:00.861499 DQ Delay:
5235 23:07:00.864453 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5236 23:07:00.867886 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5237 23:07:00.870956 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5238 23:07:00.874628 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =91
5239 23:07:00.875151
5240 23:07:00.875573
5241 23:07:00.875937 ==
5242 23:07:00.877572 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 23:07:00.884937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 23:07:00.885461 ==
5245 23:07:00.885794
5246 23:07:00.886114
5247 23:07:00.886407 TX Vref Scan disable
5248 23:07:00.888126 == TX Byte 0 ==
5249 23:07:00.891727 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5250 23:07:00.897651 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5251 23:07:00.898161 == TX Byte 1 ==
5252 23:07:00.900522 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5253 23:07:00.907804 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5254 23:07:00.908225 ==
5255 23:07:00.910985 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 23:07:00.914285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 23:07:00.914824 ==
5258 23:07:00.915161
5259 23:07:00.915467
5260 23:07:00.918113 TX Vref Scan disable
5261 23:07:00.921001 == TX Byte 0 ==
5262 23:07:00.923628 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5263 23:07:00.927049 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5264 23:07:00.930973 == TX Byte 1 ==
5265 23:07:00.934196 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5266 23:07:00.937643 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5267 23:07:00.938108
5268 23:07:00.938473 [DATLAT]
5269 23:07:00.940462 Freq=933, CH0 RK0
5270 23:07:00.940925
5271 23:07:00.943534 DATLAT Default: 0xd
5272 23:07:00.944049 0, 0xFFFF, sum = 0
5273 23:07:00.946928 1, 0xFFFF, sum = 0
5274 23:07:00.947389 2, 0xFFFF, sum = 0
5275 23:07:00.950170 3, 0xFFFF, sum = 0
5276 23:07:00.950714 4, 0xFFFF, sum = 0
5277 23:07:00.953758 5, 0xFFFF, sum = 0
5278 23:07:00.954315 6, 0xFFFF, sum = 0
5279 23:07:00.957308 7, 0xFFFF, sum = 0
5280 23:07:00.957871 8, 0xFFFF, sum = 0
5281 23:07:00.959898 9, 0xFFFF, sum = 0
5282 23:07:00.960364 10, 0x0, sum = 1
5283 23:07:00.963409 11, 0x0, sum = 2
5284 23:07:00.964054 12, 0x0, sum = 3
5285 23:07:00.967140 13, 0x0, sum = 4
5286 23:07:00.967744 best_step = 11
5287 23:07:00.968116
5288 23:07:00.968453 ==
5289 23:07:00.970122 Dram Type= 6, Freq= 0, CH_0, rank 0
5290 23:07:00.973389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 23:07:00.977215 ==
5292 23:07:00.977788 RX Vref Scan: 1
5293 23:07:00.978156
5294 23:07:00.979663 RX Vref 0 -> 0, step: 1
5295 23:07:00.980151
5296 23:07:00.983182 RX Delay -61 -> 252, step: 4
5297 23:07:00.983630
5298 23:07:00.986429 Set Vref, RX VrefLevel [Byte0]: 59
5299 23:07:00.989602 [Byte1]: 48
5300 23:07:00.990038
5301 23:07:00.992611 Final RX Vref Byte 0 = 59 to rank0
5302 23:07:00.996153 Final RX Vref Byte 1 = 48 to rank0
5303 23:07:00.999213 Final RX Vref Byte 0 = 59 to rank1
5304 23:07:01.002882 Final RX Vref Byte 1 = 48 to rank1==
5305 23:07:01.006023 Dram Type= 6, Freq= 0, CH_0, rank 0
5306 23:07:01.009341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 23:07:01.009849 ==
5308 23:07:01.013119 DQS Delay:
5309 23:07:01.013529 DQS0 = 0, DQS1 = 0
5310 23:07:01.013854 DQM Delay:
5311 23:07:01.015822 DQM0 = 96, DQM1 = 85
5312 23:07:01.016233 DQ Delay:
5313 23:07:01.019751 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =92
5314 23:07:01.022711 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5315 23:07:01.026174 DQ8 =76, DQ9 =74, DQ10 =86, DQ11 =80
5316 23:07:01.029187 DQ12 =92, DQ13 =88, DQ14 =94, DQ15 =92
5317 23:07:01.029598
5318 23:07:01.029956
5319 23:07:01.039227 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d14, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5320 23:07:01.042359 CH0 RK0: MR19=505, MR18=2D14
5321 23:07:01.049245 CH0_RK0: MR19=0x505, MR18=0x2D14, DQSOSC=407, MR23=63, INC=65, DEC=43
5322 23:07:01.049798
5323 23:07:01.052100 ----->DramcWriteLeveling(PI) begin...
5324 23:07:01.052653 ==
5325 23:07:01.056036 Dram Type= 6, Freq= 0, CH_0, rank 1
5326 23:07:01.058857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 23:07:01.059404 ==
5328 23:07:01.062273 Write leveling (Byte 0): 33 => 33
5329 23:07:01.065248 Write leveling (Byte 1): 33 => 33
5330 23:07:01.068672 DramcWriteLeveling(PI) end<-----
5331 23:07:01.069214
5332 23:07:01.069568 ==
5333 23:07:01.072065 Dram Type= 6, Freq= 0, CH_0, rank 1
5334 23:07:01.076281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5335 23:07:01.076850 ==
5336 23:07:01.078971 [Gating] SW mode calibration
5337 23:07:01.085395 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5338 23:07:01.092122 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5339 23:07:01.095406 0 14 0 | B1->B0 | 2d2d 3333 | 0 0 | (0 0) (0 0)
5340 23:07:01.098586 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 23:07:01.105439 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 23:07:01.108303 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 23:07:01.112023 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 23:07:01.118228 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 23:07:01.122242 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5346 23:07:01.124961 0 14 28 | B1->B0 | 3333 2e2e | 0 1 | (0 0) (1 1)
5347 23:07:01.131362 0 15 0 | B1->B0 | 2c2c 2828 | 0 0 | (0 1) (0 0)
5348 23:07:01.134798 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 23:07:01.138162 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 23:07:01.144879 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 23:07:01.148238 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 23:07:01.151541 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 23:07:01.158748 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 23:07:01.162574 0 15 28 | B1->B0 | 2424 3636 | 0 1 | (0 0) (0 0)
5355 23:07:01.164177 1 0 0 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
5356 23:07:01.171148 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 23:07:01.174180 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 23:07:01.177702 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 23:07:01.184571 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 23:07:01.187099 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 23:07:01.191012 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 23:07:01.197444 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5363 23:07:01.200621 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5364 23:07:01.203965 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 23:07:01.210674 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 23:07:01.214006 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 23:07:01.217205 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 23:07:01.223435 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 23:07:01.227282 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 23:07:01.230672 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 23:07:01.236482 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 23:07:01.240418 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 23:07:01.243566 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 23:07:01.249812 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 23:07:01.253137 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 23:07:01.256779 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 23:07:01.263224 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 23:07:01.266928 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5379 23:07:01.269695 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5380 23:07:01.273125 Total UI for P1: 0, mck2ui 16
5381 23:07:01.276213 best dqsien dly found for B0: ( 1, 2, 30)
5382 23:07:01.283337 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 23:07:01.283920 Total UI for P1: 0, mck2ui 16
5384 23:07:01.289300 best dqsien dly found for B1: ( 1, 2, 30)
5385 23:07:01.293336 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5386 23:07:01.296737 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5387 23:07:01.297294
5388 23:07:01.299900 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5389 23:07:01.303286 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5390 23:07:01.306346 [Gating] SW calibration Done
5391 23:07:01.306798 ==
5392 23:07:01.309539 Dram Type= 6, Freq= 0, CH_0, rank 1
5393 23:07:01.312811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5394 23:07:01.313272 ==
5395 23:07:01.316050 RX Vref Scan: 0
5396 23:07:01.316587
5397 23:07:01.316947 RX Vref 0 -> 0, step: 1
5398 23:07:01.319137
5399 23:07:01.319757 RX Delay -80 -> 252, step: 8
5400 23:07:01.325478 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5401 23:07:01.329294 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5402 23:07:01.332272 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5403 23:07:01.336079 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5404 23:07:01.339107 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5405 23:07:01.342410 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5406 23:07:01.348935 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5407 23:07:01.351850 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5408 23:07:01.355825 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5409 23:07:01.358678 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5410 23:07:01.362305 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5411 23:07:01.368606 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5412 23:07:01.372959 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5413 23:07:01.374926 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5414 23:07:01.378419 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5415 23:07:01.381749 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5416 23:07:01.382381 ==
5417 23:07:01.384960 Dram Type= 6, Freq= 0, CH_0, rank 1
5418 23:07:01.391741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5419 23:07:01.392165 ==
5420 23:07:01.392495 DQS Delay:
5421 23:07:01.395300 DQS0 = 0, DQS1 = 0
5422 23:07:01.395875 DQM Delay:
5423 23:07:01.396218 DQM0 = 96, DQM1 = 87
5424 23:07:01.398294 DQ Delay:
5425 23:07:01.401452 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5426 23:07:01.406046 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5427 23:07:01.408603 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5428 23:07:01.411947 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =91
5429 23:07:01.412367
5430 23:07:01.412698
5431 23:07:01.413017 ==
5432 23:07:01.415417 Dram Type= 6, Freq= 0, CH_0, rank 1
5433 23:07:01.417941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5434 23:07:01.418374 ==
5435 23:07:01.418704
5436 23:07:01.419010
5437 23:07:01.421962 TX Vref Scan disable
5438 23:07:01.425261 == TX Byte 0 ==
5439 23:07:01.428201 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5440 23:07:01.431476 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5441 23:07:01.435603 == TX Byte 1 ==
5442 23:07:01.438591 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5443 23:07:01.442202 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5444 23:07:01.442731 ==
5445 23:07:01.445132 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 23:07:01.448332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 23:07:01.448752 ==
5448 23:07:01.451545
5449 23:07:01.452096
5450 23:07:01.452428 TX Vref Scan disable
5451 23:07:01.454686 == TX Byte 0 ==
5452 23:07:01.458199 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5453 23:07:01.465441 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5454 23:07:01.465970 == TX Byte 1 ==
5455 23:07:01.468445 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5456 23:07:01.474857 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5457 23:07:01.475426
5458 23:07:01.475850 [DATLAT]
5459 23:07:01.476197 Freq=933, CH0 RK1
5460 23:07:01.476525
5461 23:07:01.477900 DATLAT Default: 0xb
5462 23:07:01.478357 0, 0xFFFF, sum = 0
5463 23:07:01.481616 1, 0xFFFF, sum = 0
5464 23:07:01.485061 2, 0xFFFF, sum = 0
5465 23:07:01.485699 3, 0xFFFF, sum = 0
5466 23:07:01.487786 4, 0xFFFF, sum = 0
5467 23:07:01.488253 5, 0xFFFF, sum = 0
5468 23:07:01.491497 6, 0xFFFF, sum = 0
5469 23:07:01.492100 7, 0xFFFF, sum = 0
5470 23:07:01.494823 8, 0xFFFF, sum = 0
5471 23:07:01.495570 9, 0xFFFF, sum = 0
5472 23:07:01.497457 10, 0x0, sum = 1
5473 23:07:01.497923 11, 0x0, sum = 2
5474 23:07:01.501018 12, 0x0, sum = 3
5475 23:07:01.501578 13, 0x0, sum = 4
5476 23:07:01.504148 best_step = 11
5477 23:07:01.504608
5478 23:07:01.504961 ==
5479 23:07:01.507373 Dram Type= 6, Freq= 0, CH_0, rank 1
5480 23:07:01.511112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5481 23:07:01.511828 ==
5482 23:07:01.512209 RX Vref Scan: 0
5483 23:07:01.512552
5484 23:07:01.514274 RX Vref 0 -> 0, step: 1
5485 23:07:01.514733
5486 23:07:01.517348 RX Delay -61 -> 252, step: 4
5487 23:07:01.524025 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5488 23:07:01.527568 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5489 23:07:01.531058 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5490 23:07:01.534602 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5491 23:07:01.537243 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5492 23:07:01.540974 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5493 23:07:01.548960 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5494 23:07:01.550653 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5495 23:07:01.553641 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5496 23:07:01.557372 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5497 23:07:01.560260 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5498 23:07:01.566735 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5499 23:07:01.570238 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5500 23:07:01.573820 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5501 23:07:01.576964 iDelay=203, Bit 14, Center 94 (3 ~ 186) 184
5502 23:07:01.580279 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5503 23:07:01.583132 ==
5504 23:07:01.586570 Dram Type= 6, Freq= 0, CH_0, rank 1
5505 23:07:01.589948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 23:07:01.590366 ==
5507 23:07:01.590695 DQS Delay:
5508 23:07:01.593098 DQS0 = 0, DQS1 = 0
5509 23:07:01.593178 DQM Delay:
5510 23:07:01.596839 DQM0 = 95, DQM1 = 85
5511 23:07:01.596920 DQ Delay:
5512 23:07:01.599188 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =94
5513 23:07:01.602600 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5514 23:07:01.605925 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =78
5515 23:07:01.609167 DQ12 =92, DQ13 =92, DQ14 =94, DQ15 =92
5516 23:07:01.609250
5517 23:07:01.609314
5518 23:07:01.615573 [DQSOSCAuto] RK1, (LSB)MR18= 0x25f5, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 410 ps
5519 23:07:01.619111 CH0 RK1: MR19=504, MR18=25F5
5520 23:07:01.625630 CH0_RK1: MR19=0x504, MR18=0x25F5, DQSOSC=410, MR23=63, INC=64, DEC=42
5521 23:07:01.628987 [RxdqsGatingPostProcess] freq 933
5522 23:07:01.635826 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5523 23:07:01.638963 best DQS0 dly(2T, 0.5T) = (0, 10)
5524 23:07:01.639067 best DQS1 dly(2T, 0.5T) = (0, 11)
5525 23:07:01.642650 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5526 23:07:01.645650 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5527 23:07:01.648759 best DQS0 dly(2T, 0.5T) = (0, 10)
5528 23:07:01.652116 best DQS1 dly(2T, 0.5T) = (0, 10)
5529 23:07:01.655484 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5530 23:07:01.658853 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5531 23:07:01.662219 Pre-setting of DQS Precalculation
5532 23:07:01.668483 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5533 23:07:01.668622 ==
5534 23:07:01.672092 Dram Type= 6, Freq= 0, CH_1, rank 0
5535 23:07:01.675148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5536 23:07:01.675229 ==
5537 23:07:01.681810 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5538 23:07:01.688282 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5539 23:07:01.691553 [CA 0] Center 36 (6~67) winsize 62
5540 23:07:01.694931 [CA 1] Center 37 (6~68) winsize 63
5541 23:07:01.698111 [CA 2] Center 34 (4~64) winsize 61
5542 23:07:01.701176 [CA 3] Center 33 (3~64) winsize 62
5543 23:07:01.705407 [CA 4] Center 34 (4~64) winsize 61
5544 23:07:01.708267 [CA 5] Center 33 (3~64) winsize 62
5545 23:07:01.708348
5546 23:07:01.711318 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5547 23:07:01.711422
5548 23:07:01.714784 [CATrainingPosCal] consider 1 rank data
5549 23:07:01.717835 u2DelayCellTimex100 = 270/100 ps
5550 23:07:01.721003 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5551 23:07:01.724747 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5552 23:07:01.727962 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5553 23:07:01.731312 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5554 23:07:01.734341 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5555 23:07:01.737762 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5556 23:07:01.737865
5557 23:07:01.744874 CA PerBit enable=1, Macro0, CA PI delay=33
5558 23:07:01.744971
5559 23:07:01.745060 [CBTSetCACLKResult] CA Dly = 33
5560 23:07:01.747990 CS Dly: 6 (0~37)
5561 23:07:01.748060 ==
5562 23:07:01.751972 Dram Type= 6, Freq= 0, CH_1, rank 1
5563 23:07:01.754565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5564 23:07:01.754647 ==
5565 23:07:01.761471 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5566 23:07:01.767651 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5567 23:07:01.770883 [CA 0] Center 36 (6~67) winsize 62
5568 23:07:01.774411 [CA 1] Center 36 (6~67) winsize 62
5569 23:07:01.777887 [CA 2] Center 34 (4~65) winsize 62
5570 23:07:01.780680 [CA 3] Center 33 (3~64) winsize 62
5571 23:07:01.784871 [CA 4] Center 34 (3~65) winsize 63
5572 23:07:01.787652 [CA 5] Center 33 (3~64) winsize 62
5573 23:07:01.787780
5574 23:07:01.790449 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5575 23:07:01.790533
5576 23:07:01.794134 [CATrainingPosCal] consider 2 rank data
5577 23:07:01.797022 u2DelayCellTimex100 = 270/100 ps
5578 23:07:01.800427 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5579 23:07:01.803736 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5580 23:07:01.807423 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5581 23:07:01.811223 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5582 23:07:01.813757 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5583 23:07:01.820631 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5584 23:07:01.820712
5585 23:07:01.823788 CA PerBit enable=1, Macro0, CA PI delay=33
5586 23:07:01.823864
5587 23:07:01.827166 [CBTSetCACLKResult] CA Dly = 33
5588 23:07:01.827269 CS Dly: 7 (0~39)
5589 23:07:01.827362
5590 23:07:01.830603 ----->DramcWriteLeveling(PI) begin...
5591 23:07:01.830717 ==
5592 23:07:01.833465 Dram Type= 6, Freq= 0, CH_1, rank 0
5593 23:07:01.840031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5594 23:07:01.840112 ==
5595 23:07:01.843517 Write leveling (Byte 0): 27 => 27
5596 23:07:01.843630 Write leveling (Byte 1): 28 => 28
5597 23:07:01.847115 DramcWriteLeveling(PI) end<-----
5598 23:07:01.847195
5599 23:07:01.847257 ==
5600 23:07:01.850405 Dram Type= 6, Freq= 0, CH_1, rank 0
5601 23:07:01.856996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 23:07:01.857076 ==
5603 23:07:01.860708 [Gating] SW mode calibration
5604 23:07:01.866571 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5605 23:07:01.869985 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5606 23:07:01.876248 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5607 23:07:01.879643 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 23:07:01.882953 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 23:07:01.889827 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 23:07:01.893016 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 23:07:01.896466 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 23:07:01.902705 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
5613 23:07:01.905915 0 14 28 | B1->B0 | 2d2d 2525 | 0 0 | (1 0) (0 0)
5614 23:07:01.909642 0 15 0 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
5615 23:07:01.916482 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 23:07:01.919164 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 23:07:01.922476 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 23:07:01.929676 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 23:07:01.933307 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 23:07:01.935845 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
5621 23:07:01.942750 0 15 28 | B1->B0 | 3838 4343 | 1 0 | (0 0) (0 0)
5622 23:07:01.945781 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 23:07:01.949357 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 23:07:01.955890 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 23:07:01.958895 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 23:07:01.962198 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 23:07:01.968923 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 23:07:01.972457 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5629 23:07:01.975660 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5630 23:07:01.982903 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5631 23:07:01.985738 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 23:07:01.988750 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 23:07:01.995383 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 23:07:01.998943 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 23:07:02.002095 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 23:07:02.008909 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 23:07:02.012171 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 23:07:02.015039 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 23:07:02.021841 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 23:07:02.024802 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 23:07:02.028103 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 23:07:02.035204 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 23:07:02.038390 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5644 23:07:02.041782 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5645 23:07:02.047867 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5646 23:07:02.051614 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 23:07:02.054870 Total UI for P1: 0, mck2ui 16
5648 23:07:02.058190 best dqsien dly found for B0: ( 1, 2, 24)
5649 23:07:02.061286 Total UI for P1: 0, mck2ui 16
5650 23:07:02.065058 best dqsien dly found for B1: ( 1, 2, 28)
5651 23:07:02.067940 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5652 23:07:02.071505 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5653 23:07:02.071586
5654 23:07:02.075217 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5655 23:07:02.078191 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5656 23:07:02.081455 [Gating] SW calibration Done
5657 23:07:02.081536 ==
5658 23:07:02.084796 Dram Type= 6, Freq= 0, CH_1, rank 0
5659 23:07:02.087850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5660 23:07:02.091252 ==
5661 23:07:02.091332 RX Vref Scan: 0
5662 23:07:02.091396
5663 23:07:02.095025 RX Vref 0 -> 0, step: 1
5664 23:07:02.095106
5665 23:07:02.095170 RX Delay -80 -> 252, step: 8
5666 23:07:02.101320 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5667 23:07:02.105713 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5668 23:07:02.108276 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5669 23:07:02.111691 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5670 23:07:02.114484 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5671 23:07:02.117793 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5672 23:07:02.124625 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5673 23:07:02.127529 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5674 23:07:02.130978 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5675 23:07:02.134045 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5676 23:07:02.137797 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5677 23:07:02.144139 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5678 23:07:02.147842 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5679 23:07:02.151006 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5680 23:07:02.154484 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5681 23:07:02.157377 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5682 23:07:02.161508 ==
5683 23:07:02.161589 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 23:07:02.167482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 23:07:02.167579 ==
5686 23:07:02.167645 DQS Delay:
5687 23:07:02.170844 DQS0 = 0, DQS1 = 0
5688 23:07:02.170952 DQM Delay:
5689 23:07:02.174256 DQM0 = 101, DQM1 = 90
5690 23:07:02.174341 DQ Delay:
5691 23:07:02.177330 DQ0 =103, DQ1 =99, DQ2 =91, DQ3 =99
5692 23:07:02.180471 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =95
5693 23:07:02.183765 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5694 23:07:02.187150 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =99
5695 23:07:02.187230
5696 23:07:02.187332
5697 23:07:02.187391 ==
5698 23:07:02.191180 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 23:07:02.193421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 23:07:02.193517 ==
5701 23:07:02.193602
5702 23:07:02.197367
5703 23:07:02.197448 TX Vref Scan disable
5704 23:07:02.200063 == TX Byte 0 ==
5705 23:07:02.203823 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5706 23:07:02.206647 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5707 23:07:02.210429 == TX Byte 1 ==
5708 23:07:02.214098 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5709 23:07:02.217143 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5710 23:07:02.217224 ==
5711 23:07:02.220076 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 23:07:02.226729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 23:07:02.226828 ==
5714 23:07:02.226922
5715 23:07:02.226996
5716 23:07:02.227070 TX Vref Scan disable
5717 23:07:02.231224 == TX Byte 0 ==
5718 23:07:02.234745 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5719 23:07:02.240693 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5720 23:07:02.240774 == TX Byte 1 ==
5721 23:07:02.244382 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5722 23:07:02.250553 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5723 23:07:02.250662
5724 23:07:02.250726 [DATLAT]
5725 23:07:02.250785 Freq=933, CH1 RK0
5726 23:07:02.250856
5727 23:07:02.254067 DATLAT Default: 0xd
5728 23:07:02.254178 0, 0xFFFF, sum = 0
5729 23:07:02.257231 1, 0xFFFF, sum = 0
5730 23:07:02.260395 2, 0xFFFF, sum = 0
5731 23:07:02.260477 3, 0xFFFF, sum = 0
5732 23:07:02.264048 4, 0xFFFF, sum = 0
5733 23:07:02.264130 5, 0xFFFF, sum = 0
5734 23:07:02.267623 6, 0xFFFF, sum = 0
5735 23:07:02.267729 7, 0xFFFF, sum = 0
5736 23:07:02.271734 8, 0xFFFF, sum = 0
5737 23:07:02.271817 9, 0xFFFF, sum = 0
5738 23:07:02.273416 10, 0x0, sum = 1
5739 23:07:02.273499 11, 0x0, sum = 2
5740 23:07:02.277570 12, 0x0, sum = 3
5741 23:07:02.277666 13, 0x0, sum = 4
5742 23:07:02.280425 best_step = 11
5743 23:07:02.280506
5744 23:07:02.280569 ==
5745 23:07:02.283874 Dram Type= 6, Freq= 0, CH_1, rank 0
5746 23:07:02.286525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 23:07:02.286621 ==
5748 23:07:02.286699 RX Vref Scan: 1
5749 23:07:02.290330
5750 23:07:02.290462 RX Vref 0 -> 0, step: 1
5751 23:07:02.290615
5752 23:07:02.293218 RX Delay -69 -> 252, step: 4
5753 23:07:02.293351
5754 23:07:02.296473 Set Vref, RX VrefLevel [Byte0]: 47
5755 23:07:02.300259 [Byte1]: 59
5756 23:07:02.303613
5757 23:07:02.303770 Final RX Vref Byte 0 = 47 to rank0
5758 23:07:02.306898 Final RX Vref Byte 1 = 59 to rank0
5759 23:07:02.309769 Final RX Vref Byte 0 = 47 to rank1
5760 23:07:02.312895 Final RX Vref Byte 1 = 59 to rank1==
5761 23:07:02.316550 Dram Type= 6, Freq= 0, CH_1, rank 0
5762 23:07:02.323268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 23:07:02.323394 ==
5764 23:07:02.323557 DQS Delay:
5765 23:07:02.326871 DQS0 = 0, DQS1 = 0
5766 23:07:02.326990 DQM Delay:
5767 23:07:02.327095 DQM0 = 101, DQM1 = 94
5768 23:07:02.330103 DQ Delay:
5769 23:07:02.333082 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5770 23:07:02.336506 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =98
5771 23:07:02.339388 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =84
5772 23:07:02.342750 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5773 23:07:02.342883
5774 23:07:02.343003
5775 23:07:02.349833 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d0d, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5776 23:07:02.352845 CH1 RK0: MR19=505, MR18=1D0D
5777 23:07:02.359256 CH1_RK0: MR19=0x505, MR18=0x1D0D, DQSOSC=412, MR23=63, INC=63, DEC=42
5778 23:07:02.359366
5779 23:07:02.362912 ----->DramcWriteLeveling(PI) begin...
5780 23:07:02.363020 ==
5781 23:07:02.366017 Dram Type= 6, Freq= 0, CH_1, rank 1
5782 23:07:02.372123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 23:07:02.372281 ==
5784 23:07:02.375662 Write leveling (Byte 0): 28 => 28
5785 23:07:02.375793 Write leveling (Byte 1): 28 => 28
5786 23:07:02.378920 DramcWriteLeveling(PI) end<-----
5787 23:07:02.379047
5788 23:07:02.381927 ==
5789 23:07:02.385532 Dram Type= 6, Freq= 0, CH_1, rank 1
5790 23:07:02.388652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 23:07:02.388804 ==
5792 23:07:02.391556 [Gating] SW mode calibration
5793 23:07:02.398911 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5794 23:07:02.401879 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5795 23:07:02.408267 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5796 23:07:02.411862 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 23:07:02.414996 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 23:07:02.421366 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 23:07:02.424916 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 23:07:02.428290 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 23:07:02.434992 0 14 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)
5802 23:07:02.438247 0 14 28 | B1->B0 | 2626 2f2f | 0 0 | (0 0) (0 1)
5803 23:07:02.441555 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 23:07:02.447799 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 23:07:02.450965 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 23:07:02.454541 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 23:07:02.461427 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 23:07:02.463933 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 23:07:02.467536 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 23:07:02.473925 0 15 28 | B1->B0 | 3939 3232 | 0 1 | (0 0) (0 0)
5811 23:07:02.477497 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 23:07:02.483928 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 23:07:02.486897 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 23:07:02.490289 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 23:07:02.493558 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 23:07:02.500387 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 23:07:02.504062 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 23:07:02.510263 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5819 23:07:02.513280 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5820 23:07:02.516849 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 23:07:02.520066 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 23:07:02.526560 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 23:07:02.530347 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 23:07:02.533837 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 23:07:02.539897 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 23:07:02.543187 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 23:07:02.547081 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 23:07:02.553344 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 23:07:02.556703 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 23:07:02.559542 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 23:07:02.566293 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 23:07:02.569906 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5833 23:07:02.572950 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 23:07:02.579459 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5835 23:07:02.582742 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 23:07:02.586431 Total UI for P1: 0, mck2ui 16
5837 23:07:02.589507 best dqsien dly found for B0: ( 1, 2, 28)
5838 23:07:02.593352 Total UI for P1: 0, mck2ui 16
5839 23:07:02.595923 best dqsien dly found for B1: ( 1, 2, 28)
5840 23:07:02.599245 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5841 23:07:02.602510 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5842 23:07:02.602616
5843 23:07:02.606185 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5844 23:07:02.612261 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5845 23:07:02.612393 [Gating] SW calibration Done
5846 23:07:02.612500 ==
5847 23:07:02.615451 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 23:07:02.622259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 23:07:02.622350 ==
5850 23:07:02.622438 RX Vref Scan: 0
5851 23:07:02.622521
5852 23:07:02.625594 RX Vref 0 -> 0, step: 1
5853 23:07:02.625680
5854 23:07:02.629315 RX Delay -80 -> 252, step: 8
5855 23:07:02.632286 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5856 23:07:02.635370 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5857 23:07:02.638697 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5858 23:07:02.645576 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5859 23:07:02.648383 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5860 23:07:02.651903 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5861 23:07:02.655204 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5862 23:07:02.658082 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5863 23:07:02.661408 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5864 23:07:02.668023 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5865 23:07:02.671346 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5866 23:07:02.675352 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5867 23:07:02.678413 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5868 23:07:02.681469 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5869 23:07:02.687898 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5870 23:07:02.691382 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5871 23:07:02.691478 ==
5872 23:07:02.694631 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 23:07:02.697684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 23:07:02.697763 ==
5875 23:07:02.701490 DQS Delay:
5876 23:07:02.701564 DQS0 = 0, DQS1 = 0
5877 23:07:02.701633 DQM Delay:
5878 23:07:02.704349 DQM0 = 99, DQM1 = 91
5879 23:07:02.704450 DQ Delay:
5880 23:07:02.707798 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5881 23:07:02.710819 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5882 23:07:02.714539 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5883 23:07:02.717721 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5884 23:07:02.717821
5885 23:07:02.717911
5886 23:07:02.721031 ==
5887 23:07:02.721137 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 23:07:02.727593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 23:07:02.727702 ==
5890 23:07:02.727788
5891 23:07:02.727850
5892 23:07:02.730364 TX Vref Scan disable
5893 23:07:02.730464 == TX Byte 0 ==
5894 23:07:02.733865 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5895 23:07:02.740616 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5896 23:07:02.740706 == TX Byte 1 ==
5897 23:07:02.746880 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5898 23:07:02.750540 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5899 23:07:02.750629 ==
5900 23:07:02.754041 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 23:07:02.756802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 23:07:02.756895 ==
5903 23:07:02.756960
5904 23:07:02.757019
5905 23:07:02.760065 TX Vref Scan disable
5906 23:07:02.763833 == TX Byte 0 ==
5907 23:07:02.766806 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5908 23:07:02.770264 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5909 23:07:02.773312 == TX Byte 1 ==
5910 23:07:02.776979 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5911 23:07:02.780332 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5912 23:07:02.780433
5913 23:07:02.783272 [DATLAT]
5914 23:07:02.783341 Freq=933, CH1 RK1
5915 23:07:02.783432
5916 23:07:02.786575 DATLAT Default: 0xb
5917 23:07:02.786674 0, 0xFFFF, sum = 0
5918 23:07:02.789711 1, 0xFFFF, sum = 0
5919 23:07:02.789786 2, 0xFFFF, sum = 0
5920 23:07:02.792937 3, 0xFFFF, sum = 0
5921 23:07:02.793014 4, 0xFFFF, sum = 0
5922 23:07:02.796155 5, 0xFFFF, sum = 0
5923 23:07:02.796243 6, 0xFFFF, sum = 0
5924 23:07:02.799703 7, 0xFFFF, sum = 0
5925 23:07:02.799796 8, 0xFFFF, sum = 0
5926 23:07:02.802918 9, 0xFFFF, sum = 0
5927 23:07:02.803019 10, 0x0, sum = 1
5928 23:07:02.806259 11, 0x0, sum = 2
5929 23:07:02.806333 12, 0x0, sum = 3
5930 23:07:02.810449 13, 0x0, sum = 4
5931 23:07:02.810558 best_step = 11
5932 23:07:02.810651
5933 23:07:02.810747 ==
5934 23:07:02.812975 Dram Type= 6, Freq= 0, CH_1, rank 1
5935 23:07:02.819891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5936 23:07:02.819967 ==
5937 23:07:02.820029 RX Vref Scan: 0
5938 23:07:02.820086
5939 23:07:02.822756 RX Vref 0 -> 0, step: 1
5940 23:07:02.822824
5941 23:07:02.826252 RX Delay -61 -> 252, step: 4
5942 23:07:02.829291 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5943 23:07:02.836319 iDelay=207, Bit 1, Center 96 (11 ~ 182) 172
5944 23:07:02.839301 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5945 23:07:02.842390 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5946 23:07:02.845910 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
5947 23:07:02.849275 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5948 23:07:02.855959 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
5949 23:07:02.858870 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5950 23:07:02.862359 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
5951 23:07:02.865956 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5952 23:07:02.868878 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5953 23:07:02.872064 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5954 23:07:02.878896 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
5955 23:07:02.881940 iDelay=207, Bit 13, Center 100 (7 ~ 194) 188
5956 23:07:02.885517 iDelay=207, Bit 14, Center 100 (7 ~ 194) 188
5957 23:07:02.888983 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5958 23:07:02.889081 ==
5959 23:07:02.893506 Dram Type= 6, Freq= 0, CH_1, rank 1
5960 23:07:02.899245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5961 23:07:02.899322 ==
5962 23:07:02.899389 DQS Delay:
5963 23:07:02.899448 DQS0 = 0, DQS1 = 0
5964 23:07:02.902260 DQM Delay:
5965 23:07:02.902356 DQM0 = 101, DQM1 = 93
5966 23:07:02.905267 DQ Delay:
5967 23:07:02.909285 DQ0 =104, DQ1 =96, DQ2 =90, DQ3 =98
5968 23:07:02.911897 DQ4 =100, DQ5 =110, DQ6 =116, DQ7 =98
5969 23:07:02.915053 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =84
5970 23:07:02.918275 DQ12 =102, DQ13 =100, DQ14 =100, DQ15 =102
5971 23:07:02.918375
5972 23:07:02.918464
5973 23:07:02.925018 [DQSOSCAuto] RK1, (LSB)MR18= 0xa03, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 418 ps
5974 23:07:02.928315 CH1 RK1: MR19=505, MR18=A03
5975 23:07:02.935400 CH1_RK1: MR19=0x505, MR18=0xA03, DQSOSC=418, MR23=63, INC=62, DEC=41
5976 23:07:02.938300 [RxdqsGatingPostProcess] freq 933
5977 23:07:02.945773 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5978 23:07:02.945882 best DQS0 dly(2T, 0.5T) = (0, 10)
5979 23:07:02.949181 best DQS1 dly(2T, 0.5T) = (0, 10)
5980 23:07:02.951617 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5981 23:07:02.954914 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5982 23:07:02.958326 best DQS0 dly(2T, 0.5T) = (0, 10)
5983 23:07:02.961393 best DQS1 dly(2T, 0.5T) = (0, 10)
5984 23:07:02.964732 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5985 23:07:02.968452 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5986 23:07:02.971524 Pre-setting of DQS Precalculation
5987 23:07:02.977580 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5988 23:07:02.984248 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5989 23:07:02.991720 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5990 23:07:02.991809
5991 23:07:02.991870
5992 23:07:02.994538 [Calibration Summary] 1866 Mbps
5993 23:07:02.994634 CH 0, Rank 0
5994 23:07:02.998200 SW Impedance : PASS
5995 23:07:03.000619 DUTY Scan : NO K
5996 23:07:03.000690 ZQ Calibration : PASS
5997 23:07:03.004382 Jitter Meter : NO K
5998 23:07:03.007751 CBT Training : PASS
5999 23:07:03.007859 Write leveling : PASS
6000 23:07:03.010786 RX DQS gating : PASS
6001 23:07:03.014155 RX DQ/DQS(RDDQC) : PASS
6002 23:07:03.014261 TX DQ/DQS : PASS
6003 23:07:03.017148 RX DATLAT : PASS
6004 23:07:03.021183 RX DQ/DQS(Engine): PASS
6005 23:07:03.021284 TX OE : NO K
6006 23:07:03.021377 All Pass.
6007 23:07:03.023927
6008 23:07:03.024041 CH 0, Rank 1
6009 23:07:03.027147 SW Impedance : PASS
6010 23:07:03.027218 DUTY Scan : NO K
6011 23:07:03.030849 ZQ Calibration : PASS
6012 23:07:03.030922 Jitter Meter : NO K
6013 23:07:03.033952 CBT Training : PASS
6014 23:07:03.037392 Write leveling : PASS
6015 23:07:03.037464 RX DQS gating : PASS
6016 23:07:03.040317 RX DQ/DQS(RDDQC) : PASS
6017 23:07:03.044161 TX DQ/DQS : PASS
6018 23:07:03.044235 RX DATLAT : PASS
6019 23:07:03.047433 RX DQ/DQS(Engine): PASS
6020 23:07:03.050309 TX OE : NO K
6021 23:07:03.050389 All Pass.
6022 23:07:03.050451
6023 23:07:03.050508 CH 1, Rank 0
6024 23:07:03.054011 SW Impedance : PASS
6025 23:07:03.056917 DUTY Scan : NO K
6026 23:07:03.056990 ZQ Calibration : PASS
6027 23:07:03.060659 Jitter Meter : NO K
6028 23:07:03.063904 CBT Training : PASS
6029 23:07:03.063987 Write leveling : PASS
6030 23:07:03.067128 RX DQS gating : PASS
6031 23:07:03.070083 RX DQ/DQS(RDDQC) : PASS
6032 23:07:03.070156 TX DQ/DQS : PASS
6033 23:07:03.073992 RX DATLAT : PASS
6034 23:07:03.076852 RX DQ/DQS(Engine): PASS
6035 23:07:03.076922 TX OE : NO K
6036 23:07:03.080563 All Pass.
6037 23:07:03.080636
6038 23:07:03.080696 CH 1, Rank 1
6039 23:07:03.083787 SW Impedance : PASS
6040 23:07:03.083861 DUTY Scan : NO K
6041 23:07:03.087556 ZQ Calibration : PASS
6042 23:07:03.090093 Jitter Meter : NO K
6043 23:07:03.090168 CBT Training : PASS
6044 23:07:03.093306 Write leveling : PASS
6045 23:07:03.096662 RX DQS gating : PASS
6046 23:07:03.096740 RX DQ/DQS(RDDQC) : PASS
6047 23:07:03.099871 TX DQ/DQS : PASS
6048 23:07:03.103379 RX DATLAT : PASS
6049 23:07:03.103447 RX DQ/DQS(Engine): PASS
6050 23:07:03.106255 TX OE : NO K
6051 23:07:03.106328 All Pass.
6052 23:07:03.106411
6053 23:07:03.110137 DramC Write-DBI off
6054 23:07:03.112749 PER_BANK_REFRESH: Hybrid Mode
6055 23:07:03.112822 TX_TRACKING: ON
6056 23:07:03.123066 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6057 23:07:03.126324 [FAST_K] Save calibration result to emmc
6058 23:07:03.129605 dramc_set_vcore_voltage set vcore to 650000
6059 23:07:03.133304 Read voltage for 400, 6
6060 23:07:03.133377 Vio18 = 0
6061 23:07:03.133439 Vcore = 650000
6062 23:07:03.135839 Vdram = 0
6063 23:07:03.135908 Vddq = 0
6064 23:07:03.135971 Vmddr = 0
6065 23:07:03.142680 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6066 23:07:03.146351 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6067 23:07:03.149006 MEM_TYPE=3, freq_sel=20
6068 23:07:03.152666 sv_algorithm_assistance_LP4_800
6069 23:07:03.155957 ============ PULL DRAM RESETB DOWN ============
6070 23:07:03.159255 ========== PULL DRAM RESETB DOWN end =========
6071 23:07:03.166059 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6072 23:07:03.168796 ===================================
6073 23:07:03.168866 LPDDR4 DRAM CONFIGURATION
6074 23:07:03.172280 ===================================
6075 23:07:03.175564 EX_ROW_EN[0] = 0x0
6076 23:07:03.178951 EX_ROW_EN[1] = 0x0
6077 23:07:03.179030 LP4Y_EN = 0x0
6078 23:07:03.182052 WORK_FSP = 0x0
6079 23:07:03.182123 WL = 0x2
6080 23:07:03.185346 RL = 0x2
6081 23:07:03.185418 BL = 0x2
6082 23:07:03.189066 RPST = 0x0
6083 23:07:03.189136 RD_PRE = 0x0
6084 23:07:03.192541 WR_PRE = 0x1
6085 23:07:03.192610 WR_PST = 0x0
6086 23:07:03.195389 DBI_WR = 0x0
6087 23:07:03.195456 DBI_RD = 0x0
6088 23:07:03.198691 OTF = 0x1
6089 23:07:03.201924 ===================================
6090 23:07:03.205351 ===================================
6091 23:07:03.205425 ANA top config
6092 23:07:03.208582 ===================================
6093 23:07:03.211663 DLL_ASYNC_EN = 0
6094 23:07:03.214950 ALL_SLAVE_EN = 1
6095 23:07:03.218165 NEW_RANK_MODE = 1
6096 23:07:03.221949 DLL_IDLE_MODE = 1
6097 23:07:03.222022 LP45_APHY_COMB_EN = 1
6098 23:07:03.225186 TX_ODT_DIS = 1
6099 23:07:03.228027 NEW_8X_MODE = 1
6100 23:07:03.231754 ===================================
6101 23:07:03.235301 ===================================
6102 23:07:03.238552 data_rate = 800
6103 23:07:03.241655 CKR = 1
6104 23:07:03.241734 DQ_P2S_RATIO = 4
6105 23:07:03.244880 ===================================
6106 23:07:03.248769 CA_P2S_RATIO = 4
6107 23:07:03.251535 DQ_CA_OPEN = 0
6108 23:07:03.255052 DQ_SEMI_OPEN = 1
6109 23:07:03.257908 CA_SEMI_OPEN = 1
6110 23:07:03.261294 CA_FULL_RATE = 0
6111 23:07:03.261363 DQ_CKDIV4_EN = 0
6112 23:07:03.264446 CA_CKDIV4_EN = 1
6113 23:07:03.268059 CA_PREDIV_EN = 0
6114 23:07:03.271493 PH8_DLY = 0
6115 23:07:03.274766 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6116 23:07:03.278098 DQ_AAMCK_DIV = 0
6117 23:07:03.278185 CA_AAMCK_DIV = 0
6118 23:07:03.281347 CA_ADMCK_DIV = 4
6119 23:07:03.284424 DQ_TRACK_CA_EN = 0
6120 23:07:03.288089 CA_PICK = 800
6121 23:07:03.290881 CA_MCKIO = 400
6122 23:07:03.294406 MCKIO_SEMI = 400
6123 23:07:03.297553 PLL_FREQ = 3016
6124 23:07:03.301109 DQ_UI_PI_RATIO = 32
6125 23:07:03.301176 CA_UI_PI_RATIO = 32
6126 23:07:03.304953 ===================================
6127 23:07:03.307645 ===================================
6128 23:07:03.311197 memory_type:LPDDR4
6129 23:07:03.315035 GP_NUM : 10
6130 23:07:03.315112 SRAM_EN : 1
6131 23:07:03.318544 MD32_EN : 0
6132 23:07:03.320763 ===================================
6133 23:07:03.324001 [ANA_INIT] >>>>>>>>>>>>>>
6134 23:07:03.327123 <<<<<< [CONFIGURE PHASE]: ANA_TX
6135 23:07:03.331119 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6136 23:07:03.333941 ===================================
6137 23:07:03.334021 data_rate = 800,PCW = 0X7400
6138 23:07:03.337166 ===================================
6139 23:07:03.340452 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6140 23:07:03.346895 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6141 23:07:03.360839 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6142 23:07:03.363370 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6143 23:07:03.366739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6144 23:07:03.370024 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6145 23:07:03.373187 [ANA_INIT] flow start
6146 23:07:03.373257 [ANA_INIT] PLL >>>>>>>>
6147 23:07:03.376320 [ANA_INIT] PLL <<<<<<<<
6148 23:07:03.380243 [ANA_INIT] MIDPI >>>>>>>>
6149 23:07:03.383012 [ANA_INIT] MIDPI <<<<<<<<
6150 23:07:03.383111 [ANA_INIT] DLL >>>>>>>>
6151 23:07:03.386373 [ANA_INIT] flow end
6152 23:07:03.389668 ============ LP4 DIFF to SE enter ============
6153 23:07:03.393010 ============ LP4 DIFF to SE exit ============
6154 23:07:03.396103 [ANA_INIT] <<<<<<<<<<<<<
6155 23:07:03.399587 [Flow] Enable top DCM control >>>>>
6156 23:07:03.402942 [Flow] Enable top DCM control <<<<<
6157 23:07:03.406152 Enable DLL master slave shuffle
6158 23:07:03.412724 ==============================================================
6159 23:07:03.412842 Gating Mode config
6160 23:07:03.419624 ==============================================================
6161 23:07:03.419763 Config description:
6162 23:07:03.429593 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6163 23:07:03.436030 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6164 23:07:03.442664 SELPH_MODE 0: By rank 1: By Phase
6165 23:07:03.445789 ==============================================================
6166 23:07:03.449547 GAT_TRACK_EN = 0
6167 23:07:03.452205 RX_GATING_MODE = 2
6168 23:07:03.455551 RX_GATING_TRACK_MODE = 2
6169 23:07:03.458881 SELPH_MODE = 1
6170 23:07:03.462514 PICG_EARLY_EN = 1
6171 23:07:03.465500 VALID_LAT_VALUE = 1
6172 23:07:03.472232 ==============================================================
6173 23:07:03.476048 Enter into Gating configuration >>>>
6174 23:07:03.478824 Exit from Gating configuration <<<<
6175 23:07:03.481789 Enter into DVFS_PRE_config >>>>>
6176 23:07:03.491855 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6177 23:07:03.495821 Exit from DVFS_PRE_config <<<<<
6178 23:07:03.498453 Enter into PICG configuration >>>>
6179 23:07:03.501723 Exit from PICG configuration <<<<
6180 23:07:03.505592 [RX_INPUT] configuration >>>>>
6181 23:07:03.505699 [RX_INPUT] configuration <<<<<
6182 23:07:03.511776 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6183 23:07:03.518376 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6184 23:07:03.524962 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6185 23:07:03.528120 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6186 23:07:03.534741 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6187 23:07:03.541479 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6188 23:07:03.545506 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6189 23:07:03.548301 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6190 23:07:03.554902 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6191 23:07:03.557910 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6192 23:07:03.561278 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6193 23:07:03.568037 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6194 23:07:03.571400 ===================================
6195 23:07:03.571524 LPDDR4 DRAM CONFIGURATION
6196 23:07:03.575115 ===================================
6197 23:07:03.577879 EX_ROW_EN[0] = 0x0
6198 23:07:03.580969 EX_ROW_EN[1] = 0x0
6199 23:07:03.581050 LP4Y_EN = 0x0
6200 23:07:03.584673 WORK_FSP = 0x0
6201 23:07:03.584753 WL = 0x2
6202 23:07:03.587844 RL = 0x2
6203 23:07:03.587915 BL = 0x2
6204 23:07:03.591144 RPST = 0x0
6205 23:07:03.591215 RD_PRE = 0x0
6206 23:07:03.594062 WR_PRE = 0x1
6207 23:07:03.594139 WR_PST = 0x0
6208 23:07:03.597679 DBI_WR = 0x0
6209 23:07:03.597754 DBI_RD = 0x0
6210 23:07:03.601008 OTF = 0x1
6211 23:07:03.604474 ===================================
6212 23:07:03.607790 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6213 23:07:03.612370 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6214 23:07:03.617343 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6215 23:07:03.621049 ===================================
6216 23:07:03.621131 LPDDR4 DRAM CONFIGURATION
6217 23:07:03.624677 ===================================
6218 23:07:03.627626 EX_ROW_EN[0] = 0x10
6219 23:07:03.631006 EX_ROW_EN[1] = 0x0
6220 23:07:03.631077 LP4Y_EN = 0x0
6221 23:07:03.634277 WORK_FSP = 0x0
6222 23:07:03.634350 WL = 0x2
6223 23:07:03.637459 RL = 0x2
6224 23:07:03.637532 BL = 0x2
6225 23:07:03.640895 RPST = 0x0
6226 23:07:03.640968 RD_PRE = 0x0
6227 23:07:03.643796 WR_PRE = 0x1
6228 23:07:03.643864 WR_PST = 0x0
6229 23:07:03.647463 DBI_WR = 0x0
6230 23:07:03.647534 DBI_RD = 0x0
6231 23:07:03.650206 OTF = 0x1
6232 23:07:03.653904 ===================================
6233 23:07:03.660886 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6234 23:07:03.663408 nWR fixed to 30
6235 23:07:03.666603 [ModeRegInit_LP4] CH0 RK0
6236 23:07:03.666674 [ModeRegInit_LP4] CH0 RK1
6237 23:07:03.670236 [ModeRegInit_LP4] CH1 RK0
6238 23:07:03.673881 [ModeRegInit_LP4] CH1 RK1
6239 23:07:03.673953 match AC timing 19
6240 23:07:03.680745 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6241 23:07:03.683391 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6242 23:07:03.686490 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6243 23:07:03.693656 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6244 23:07:03.696749 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6245 23:07:03.696820 ==
6246 23:07:03.699866 Dram Type= 6, Freq= 0, CH_0, rank 0
6247 23:07:03.702799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6248 23:07:03.702873 ==
6249 23:07:03.709290 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6250 23:07:03.715962 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6251 23:07:03.719547 [CA 0] Center 36 (8~64) winsize 57
6252 23:07:03.722561 [CA 1] Center 36 (8~64) winsize 57
6253 23:07:03.726114 [CA 2] Center 36 (8~64) winsize 57
6254 23:07:03.729269 [CA 3] Center 36 (8~64) winsize 57
6255 23:07:03.732457 [CA 4] Center 36 (8~64) winsize 57
6256 23:07:03.736088 [CA 5] Center 36 (8~64) winsize 57
6257 23:07:03.736165
6258 23:07:03.739658 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6259 23:07:03.739770
6260 23:07:03.742349 [CATrainingPosCal] consider 1 rank data
6261 23:07:03.746008 u2DelayCellTimex100 = 270/100 ps
6262 23:07:03.749349 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 23:07:03.752617 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 23:07:03.755915 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 23:07:03.758941 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 23:07:03.762119 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 23:07:03.765466 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 23:07:03.765537
6269 23:07:03.771964 CA PerBit enable=1, Macro0, CA PI delay=36
6270 23:07:03.772038
6271 23:07:03.772104 [CBTSetCACLKResult] CA Dly = 36
6272 23:07:03.775215 CS Dly: 1 (0~32)
6273 23:07:03.775288 ==
6274 23:07:03.778531 Dram Type= 6, Freq= 0, CH_0, rank 1
6275 23:07:03.781735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 23:07:03.781809 ==
6277 23:07:03.788789 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6278 23:07:03.795202 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6279 23:07:03.798803 [CA 0] Center 36 (8~64) winsize 57
6280 23:07:03.801800 [CA 1] Center 36 (8~64) winsize 57
6281 23:07:03.804755 [CA 2] Center 36 (8~64) winsize 57
6282 23:07:03.808314 [CA 3] Center 36 (8~64) winsize 57
6283 23:07:03.808388 [CA 4] Center 36 (8~64) winsize 57
6284 23:07:03.812187 [CA 5] Center 36 (8~64) winsize 57
6285 23:07:03.812264
6286 23:07:03.818567 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6287 23:07:03.818638
6288 23:07:03.821557 [CATrainingPosCal] consider 2 rank data
6289 23:07:03.825081 u2DelayCellTimex100 = 270/100 ps
6290 23:07:03.828419 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 23:07:03.831844 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 23:07:03.834483 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 23:07:03.837745 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 23:07:03.841360 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 23:07:03.845046 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 23:07:03.845122
6297 23:07:03.848272 CA PerBit enable=1, Macro0, CA PI delay=36
6298 23:07:03.848346
6299 23:07:03.851263 [CBTSetCACLKResult] CA Dly = 36
6300 23:07:03.854482 CS Dly: 1 (0~32)
6301 23:07:03.854561
6302 23:07:03.858118 ----->DramcWriteLeveling(PI) begin...
6303 23:07:03.858202 ==
6304 23:07:03.861024 Dram Type= 6, Freq= 0, CH_0, rank 0
6305 23:07:03.864358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 23:07:03.864439 ==
6307 23:07:03.868137 Write leveling (Byte 0): 40 => 8
6308 23:07:03.870885 Write leveling (Byte 1): 32 => 0
6309 23:07:03.874479 DramcWriteLeveling(PI) end<-----
6310 23:07:03.874554
6311 23:07:03.874616 ==
6312 23:07:03.877807 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 23:07:03.881105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 23:07:03.881180 ==
6315 23:07:03.884768 [Gating] SW mode calibration
6316 23:07:03.890855 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6317 23:07:03.897434 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6318 23:07:03.900538 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6319 23:07:03.907349 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6320 23:07:03.910767 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6321 23:07:03.914092 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6322 23:07:03.920893 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6323 23:07:03.923866 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6324 23:07:03.927161 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6325 23:07:03.933924 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 23:07:03.936840 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6327 23:07:03.940555 Total UI for P1: 0, mck2ui 16
6328 23:07:03.943538 best dqsien dly found for B0: ( 0, 14, 24)
6329 23:07:03.947164 Total UI for P1: 0, mck2ui 16
6330 23:07:03.950254 best dqsien dly found for B1: ( 0, 14, 24)
6331 23:07:03.953432 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6332 23:07:03.956750 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6333 23:07:03.956823
6334 23:07:03.960364 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6335 23:07:03.963507 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6336 23:07:03.967035 [Gating] SW calibration Done
6337 23:07:03.967108 ==
6338 23:07:03.969911 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 23:07:03.973807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 23:07:03.976506 ==
6341 23:07:03.976576 RX Vref Scan: 0
6342 23:07:03.976636
6343 23:07:03.980198 RX Vref 0 -> 0, step: 1
6344 23:07:03.980278
6345 23:07:03.983519 RX Delay -410 -> 252, step: 16
6346 23:07:03.986176 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6347 23:07:03.989996 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6348 23:07:03.992916 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6349 23:07:04.000693 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6350 23:07:04.003457 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6351 23:07:04.006583 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6352 23:07:04.010136 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6353 23:07:04.016310 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6354 23:07:04.020200 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6355 23:07:04.022936 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6356 23:07:04.026179 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6357 23:07:04.033017 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6358 23:07:04.036161 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6359 23:07:04.039761 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6360 23:07:04.046494 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6361 23:07:04.049211 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6362 23:07:04.049286 ==
6363 23:07:04.053447 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 23:07:04.055792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 23:07:04.055887 ==
6366 23:07:04.059438 DQS Delay:
6367 23:07:04.059540 DQS0 = 43, DQS1 = 59
6368 23:07:04.059632 DQM Delay:
6369 23:07:04.062602 DQM0 = 10, DQM1 = 12
6370 23:07:04.062670 DQ Delay:
6371 23:07:04.066129 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6372 23:07:04.069002 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6373 23:07:04.072256 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6374 23:07:04.075779 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6375 23:07:04.075859
6376 23:07:04.075921
6377 23:07:04.075978 ==
6378 23:07:04.078800 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 23:07:04.085716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 23:07:04.085794 ==
6381 23:07:04.085864
6382 23:07:04.085923
6383 23:07:04.085980 TX Vref Scan disable
6384 23:07:04.089065 == TX Byte 0 ==
6385 23:07:04.091873 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6386 23:07:04.095974 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6387 23:07:04.098532 == TX Byte 1 ==
6388 23:07:04.101958 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6389 23:07:04.105603 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6390 23:07:04.105677 ==
6391 23:07:04.108544 Dram Type= 6, Freq= 0, CH_0, rank 0
6392 23:07:04.114880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6393 23:07:04.114959 ==
6394 23:07:04.115028
6395 23:07:04.115085
6396 23:07:04.118579 TX Vref Scan disable
6397 23:07:04.118647 == TX Byte 0 ==
6398 23:07:04.121883 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6399 23:07:04.128757 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6400 23:07:04.128833 == TX Byte 1 ==
6401 23:07:04.131974 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6402 23:07:04.138345 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6403 23:07:04.138418
6404 23:07:04.138483 [DATLAT]
6405 23:07:04.138542 Freq=400, CH0 RK0
6406 23:07:04.138597
6407 23:07:04.141635 DATLAT Default: 0xf
6408 23:07:04.144740 0, 0xFFFF, sum = 0
6409 23:07:04.144810 1, 0xFFFF, sum = 0
6410 23:07:04.148193 2, 0xFFFF, sum = 0
6411 23:07:04.148265 3, 0xFFFF, sum = 0
6412 23:07:04.151140 4, 0xFFFF, sum = 0
6413 23:07:04.151205 5, 0xFFFF, sum = 0
6414 23:07:04.154650 6, 0xFFFF, sum = 0
6415 23:07:04.154730 7, 0xFFFF, sum = 0
6416 23:07:04.158151 8, 0xFFFF, sum = 0
6417 23:07:04.158224 9, 0xFFFF, sum = 0
6418 23:07:04.161618 10, 0xFFFF, sum = 0
6419 23:07:04.161687 11, 0xFFFF, sum = 0
6420 23:07:04.164555 12, 0xFFFF, sum = 0
6421 23:07:04.164626 13, 0x0, sum = 1
6422 23:07:04.167941 14, 0x0, sum = 2
6423 23:07:04.168021 15, 0x0, sum = 3
6424 23:07:04.170970 16, 0x0, sum = 4
6425 23:07:04.171036 best_step = 14
6426 23:07:04.171100
6427 23:07:04.171156 ==
6428 23:07:04.174608 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 23:07:04.181405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 23:07:04.181476 ==
6431 23:07:04.181544 RX Vref Scan: 1
6432 23:07:04.181600
6433 23:07:04.184286 RX Vref 0 -> 0, step: 1
6434 23:07:04.184357
6435 23:07:04.187727 RX Delay -359 -> 252, step: 8
6436 23:07:04.187793
6437 23:07:04.190839 Set Vref, RX VrefLevel [Byte0]: 59
6438 23:07:04.194221 [Byte1]: 48
6439 23:07:04.197504
6440 23:07:04.197600 Final RX Vref Byte 0 = 59 to rank0
6441 23:07:04.200771 Final RX Vref Byte 1 = 48 to rank0
6442 23:07:04.204301 Final RX Vref Byte 0 = 59 to rank1
6443 23:07:04.207484 Final RX Vref Byte 1 = 48 to rank1==
6444 23:07:04.210673 Dram Type= 6, Freq= 0, CH_0, rank 0
6445 23:07:04.217063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 23:07:04.217143 ==
6447 23:07:04.217205 DQS Delay:
6448 23:07:04.220319 DQS0 = 48, DQS1 = 60
6449 23:07:04.220390 DQM Delay:
6450 23:07:04.220447 DQM0 = 11, DQM1 = 11
6451 23:07:04.224121 DQ Delay:
6452 23:07:04.226889 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6453 23:07:04.230111 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6454 23:07:04.230181 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6455 23:07:04.234415 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6456 23:07:04.237356
6457 23:07:04.237425
6458 23:07:04.243261 [DQSOSCAuto] RK0, (LSB)MR18= 0xc285, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 385 ps
6459 23:07:04.246512 CH0 RK0: MR19=C0C, MR18=C285
6460 23:07:04.253479 CH0_RK0: MR19=0xC0C, MR18=0xC285, DQSOSC=385, MR23=63, INC=398, DEC=265
6461 23:07:04.253551 ==
6462 23:07:04.256756 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 23:07:04.259889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 23:07:04.259960 ==
6465 23:07:04.263538 [Gating] SW mode calibration
6466 23:07:04.269621 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6467 23:07:04.276218 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6468 23:07:04.279624 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6469 23:07:04.282814 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6470 23:07:04.289903 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6471 23:07:04.292707 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6472 23:07:04.296602 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 23:07:04.302374 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6474 23:07:04.306316 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 23:07:04.309030 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 23:07:04.315916 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6477 23:07:04.319290 Total UI for P1: 0, mck2ui 16
6478 23:07:04.322991 best dqsien dly found for B0: ( 0, 14, 24)
6479 23:07:04.325635 Total UI for P1: 0, mck2ui 16
6480 23:07:04.328963 best dqsien dly found for B1: ( 0, 14, 24)
6481 23:07:04.332621 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6482 23:07:04.335426 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6483 23:07:04.335506
6484 23:07:04.339132 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6485 23:07:04.342275 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6486 23:07:04.345328 [Gating] SW calibration Done
6487 23:07:04.345408 ==
6488 23:07:04.348568 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 23:07:04.352588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 23:07:04.352668 ==
6491 23:07:04.355642 RX Vref Scan: 0
6492 23:07:04.355767
6493 23:07:04.359098 RX Vref 0 -> 0, step: 1
6494 23:07:04.359177
6495 23:07:04.361865 RX Delay -410 -> 252, step: 16
6496 23:07:04.365523 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6497 23:07:04.368744 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6498 23:07:04.371923 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6499 23:07:04.378316 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6500 23:07:04.381668 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6501 23:07:04.385675 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6502 23:07:04.388376 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6503 23:07:04.395247 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6504 23:07:04.398881 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6505 23:07:04.402063 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6506 23:07:04.405018 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6507 23:07:04.411528 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6508 23:07:04.414528 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6509 23:07:04.418147 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6510 23:07:04.424203 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6511 23:07:04.427372 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6512 23:07:04.427457 ==
6513 23:07:04.430887 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 23:07:04.434241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 23:07:04.434309 ==
6516 23:07:04.437736 DQS Delay:
6517 23:07:04.437803 DQS0 = 43, DQS1 = 51
6518 23:07:04.440912 DQM Delay:
6519 23:07:04.440983 DQM0 = 11, DQM1 = 9
6520 23:07:04.441042 DQ Delay:
6521 23:07:04.444021 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6522 23:07:04.447461 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6523 23:07:04.451190 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6524 23:07:04.453997 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6525 23:07:04.454063
6526 23:07:04.454121
6527 23:07:04.454176 ==
6528 23:07:04.456834 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 23:07:04.464243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 23:07:04.464317 ==
6531 23:07:04.464378
6532 23:07:04.464435
6533 23:07:04.464497 TX Vref Scan disable
6534 23:07:04.467194 == TX Byte 0 ==
6535 23:07:04.470395 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6536 23:07:04.473751 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6537 23:07:04.477001 == TX Byte 1 ==
6538 23:07:04.480030 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6539 23:07:04.483529 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6540 23:07:04.483598 ==
6541 23:07:04.486685 Dram Type= 6, Freq= 0, CH_0, rank 1
6542 23:07:04.493345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6543 23:07:04.493419 ==
6544 23:07:04.493484
6545 23:07:04.493541
6546 23:07:04.493595 TX Vref Scan disable
6547 23:07:04.496460 == TX Byte 0 ==
6548 23:07:04.499840 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6549 23:07:04.503817 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6550 23:07:04.506742 == TX Byte 1 ==
6551 23:07:04.509889 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6552 23:07:04.513383 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6553 23:07:04.513462
6554 23:07:04.516093 [DATLAT]
6555 23:07:04.516171 Freq=400, CH0 RK1
6556 23:07:04.516232
6557 23:07:04.519528 DATLAT Default: 0xe
6558 23:07:04.519620 0, 0xFFFF, sum = 0
6559 23:07:04.522754 1, 0xFFFF, sum = 0
6560 23:07:04.522824 2, 0xFFFF, sum = 0
6561 23:07:04.526396 3, 0xFFFF, sum = 0
6562 23:07:04.526474 4, 0xFFFF, sum = 0
6563 23:07:04.529761 5, 0xFFFF, sum = 0
6564 23:07:04.529828 6, 0xFFFF, sum = 0
6565 23:07:04.533141 7, 0xFFFF, sum = 0
6566 23:07:04.533208 8, 0xFFFF, sum = 0
6567 23:07:04.536030 9, 0xFFFF, sum = 0
6568 23:07:04.539784 10, 0xFFFF, sum = 0
6569 23:07:04.539888 11, 0xFFFF, sum = 0
6570 23:07:04.542817 12, 0xFFFF, sum = 0
6571 23:07:04.542918 13, 0x0, sum = 1
6572 23:07:04.546065 14, 0x0, sum = 2
6573 23:07:04.546131 15, 0x0, sum = 3
6574 23:07:04.549337 16, 0x0, sum = 4
6575 23:07:04.549405 best_step = 14
6576 23:07:04.549464
6577 23:07:04.549526 ==
6578 23:07:04.552600 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 23:07:04.556244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 23:07:04.556310 ==
6581 23:07:04.559347 RX Vref Scan: 0
6582 23:07:04.559410
6583 23:07:04.563005 RX Vref 0 -> 0, step: 1
6584 23:07:04.563070
6585 23:07:04.563133 RX Delay -343 -> 252, step: 8
6586 23:07:04.571214 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6587 23:07:04.574621 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6588 23:07:04.577966 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6589 23:07:04.584800 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6590 23:07:04.588365 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6591 23:07:04.591553 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6592 23:07:04.594467 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6593 23:07:04.601068 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6594 23:07:04.604571 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6595 23:07:04.608128 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6596 23:07:04.611299 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6597 23:07:04.618177 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6598 23:07:04.620912 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6599 23:07:04.624111 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6600 23:07:04.627240 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6601 23:07:04.634016 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6602 23:07:04.634144 ==
6603 23:07:04.637154 Dram Type= 6, Freq= 0, CH_0, rank 1
6604 23:07:04.641345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 23:07:04.641446 ==
6606 23:07:04.641535 DQS Delay:
6607 23:07:04.643907 DQS0 = 44, DQS1 = 60
6608 23:07:04.643989 DQM Delay:
6609 23:07:04.647498 DQM0 = 8, DQM1 = 16
6610 23:07:04.647606 DQ Delay:
6611 23:07:04.650858 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6612 23:07:04.654015 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6613 23:07:04.656959 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6614 23:07:04.660383 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6615 23:07:04.660493
6616 23:07:04.660580
6617 23:07:04.669996 [DQSOSCAuto] RK1, (LSB)MR18= 0xb843, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6618 23:07:04.670113 CH0 RK1: MR19=C0C, MR18=B843
6619 23:07:04.676596 CH0_RK1: MR19=0xC0C, MR18=0xB843, DQSOSC=386, MR23=63, INC=396, DEC=264
6620 23:07:04.680300 [RxdqsGatingPostProcess] freq 400
6621 23:07:04.686852 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6622 23:07:04.690460 best DQS0 dly(2T, 0.5T) = (0, 10)
6623 23:07:04.694362 best DQS1 dly(2T, 0.5T) = (0, 10)
6624 23:07:04.696461 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6625 23:07:04.700167 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6626 23:07:04.703371 best DQS0 dly(2T, 0.5T) = (0, 10)
6627 23:07:04.703451 best DQS1 dly(2T, 0.5T) = (0, 10)
6628 23:07:04.706585 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6629 23:07:04.710025 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6630 23:07:04.713461 Pre-setting of DQS Precalculation
6631 23:07:04.719849 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6632 23:07:04.719931 ==
6633 23:07:04.723015 Dram Type= 6, Freq= 0, CH_1, rank 0
6634 23:07:04.726021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 23:07:04.726130 ==
6636 23:07:04.732933 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6637 23:07:04.739723 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6638 23:07:04.742627 [CA 0] Center 36 (8~64) winsize 57
6639 23:07:04.746046 [CA 1] Center 36 (8~64) winsize 57
6640 23:07:04.749294 [CA 2] Center 36 (8~64) winsize 57
6641 23:07:04.749376 [CA 3] Center 36 (8~64) winsize 57
6642 23:07:04.752750 [CA 4] Center 36 (8~64) winsize 57
6643 23:07:04.756252 [CA 5] Center 36 (8~64) winsize 57
6644 23:07:04.756335
6645 23:07:04.762615 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6646 23:07:04.762698
6647 23:07:04.765630 [CATrainingPosCal] consider 1 rank data
6648 23:07:04.769087 u2DelayCellTimex100 = 270/100 ps
6649 23:07:04.772210 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 23:07:04.775877 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 23:07:04.779436 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 23:07:04.782520 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 23:07:04.786057 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 23:07:04.788746 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 23:07:04.788828
6656 23:07:04.792223 CA PerBit enable=1, Macro0, CA PI delay=36
6657 23:07:04.792305
6658 23:07:04.795475 [CBTSetCACLKResult] CA Dly = 36
6659 23:07:04.798776 CS Dly: 1 (0~32)
6660 23:07:04.798857 ==
6661 23:07:04.802588 Dram Type= 6, Freq= 0, CH_1, rank 1
6662 23:07:04.805395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 23:07:04.805477 ==
6664 23:07:04.812513 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6665 23:07:04.818460 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6666 23:07:04.821903 [CA 0] Center 36 (8~64) winsize 57
6667 23:07:04.821984 [CA 1] Center 36 (8~64) winsize 57
6668 23:07:04.825347 [CA 2] Center 36 (8~64) winsize 57
6669 23:07:04.828692 [CA 3] Center 36 (8~64) winsize 57
6670 23:07:04.832194 [CA 4] Center 36 (8~64) winsize 57
6671 23:07:04.835046 [CA 5] Center 36 (8~64) winsize 57
6672 23:07:04.835126
6673 23:07:04.838580 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6674 23:07:04.838661
6675 23:07:04.845716 [CATrainingPosCal] consider 2 rank data
6676 23:07:04.845798 u2DelayCellTimex100 = 270/100 ps
6677 23:07:04.851617 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 23:07:04.855011 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 23:07:04.858498 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 23:07:04.861841 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 23:07:04.865049 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 23:07:04.868544 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 23:07:04.868625
6684 23:07:04.871401 CA PerBit enable=1, Macro0, CA PI delay=36
6685 23:07:04.871482
6686 23:07:04.874919 [CBTSetCACLKResult] CA Dly = 36
6687 23:07:04.877897 CS Dly: 1 (0~32)
6688 23:07:04.877977
6689 23:07:04.881420 ----->DramcWriteLeveling(PI) begin...
6690 23:07:04.881502 ==
6691 23:07:04.884907 Dram Type= 6, Freq= 0, CH_1, rank 0
6692 23:07:04.888066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 23:07:04.888147 ==
6694 23:07:04.891629 Write leveling (Byte 0): 40 => 8
6695 23:07:04.894866 Write leveling (Byte 1): 40 => 8
6696 23:07:04.898043 DramcWriteLeveling(PI) end<-----
6697 23:07:04.898124
6698 23:07:04.898188 ==
6699 23:07:04.901376 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 23:07:04.904882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 23:07:04.904963 ==
6702 23:07:04.908356 [Gating] SW mode calibration
6703 23:07:04.915037 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6704 23:07:04.921297 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6705 23:07:04.925242 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6706 23:07:04.927853 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6707 23:07:04.934712 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6708 23:07:04.938113 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6709 23:07:04.941635 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6710 23:07:04.948298 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6711 23:07:04.951021 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6712 23:07:04.954407 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 23:07:04.961156 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6714 23:07:04.961237 Total UI for P1: 0, mck2ui 16
6715 23:07:04.967640 best dqsien dly found for B0: ( 0, 14, 24)
6716 23:07:04.967753 Total UI for P1: 0, mck2ui 16
6717 23:07:04.974056 best dqsien dly found for B1: ( 0, 14, 24)
6718 23:07:04.977233 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6719 23:07:04.980705 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6720 23:07:04.980785
6721 23:07:04.984274 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6722 23:07:04.987127 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6723 23:07:04.990548 [Gating] SW calibration Done
6724 23:07:04.990643 ==
6725 23:07:04.993807 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 23:07:04.996868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 23:07:04.996940 ==
6728 23:07:05.000444 RX Vref Scan: 0
6729 23:07:05.000516
6730 23:07:05.000624 RX Vref 0 -> 0, step: 1
6731 23:07:05.003984
6732 23:07:05.004054 RX Delay -410 -> 252, step: 16
6733 23:07:05.010264 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6734 23:07:05.013479 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6735 23:07:05.016713 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6736 23:07:05.020150 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6737 23:07:05.027199 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6738 23:07:05.030075 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6739 23:07:05.033631 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6740 23:07:05.039986 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6741 23:07:05.043095 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6742 23:07:05.046756 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6743 23:07:05.049937 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6744 23:07:05.056424 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6745 23:07:05.059475 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6746 23:07:05.063110 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6747 23:07:05.066563 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6748 23:07:05.072559 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6749 23:07:05.072640 ==
6750 23:07:05.076201 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 23:07:05.080693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 23:07:05.080775 ==
6753 23:07:05.080837 DQS Delay:
6754 23:07:05.082800 DQS0 = 43, DQS1 = 51
6755 23:07:05.082901 DQM Delay:
6756 23:07:05.085977 DQM0 = 12, DQM1 = 14
6757 23:07:05.086048 DQ Delay:
6758 23:07:05.089158 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6759 23:07:05.092496 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6760 23:07:05.095812 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6761 23:07:05.099825 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6762 23:07:05.099925
6763 23:07:05.100012
6764 23:07:05.100101 ==
6765 23:07:05.102419 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 23:07:05.105834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 23:07:05.105901 ==
6768 23:07:05.105958
6769 23:07:05.108910
6770 23:07:05.108976 TX Vref Scan disable
6771 23:07:05.112531 == TX Byte 0 ==
6772 23:07:05.115646 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 23:07:05.119317 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 23:07:05.122293 == TX Byte 1 ==
6775 23:07:05.125232 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 23:07:05.128908 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 23:07:05.128987 ==
6778 23:07:05.131939 Dram Type= 6, Freq= 0, CH_1, rank 0
6779 23:07:05.135278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6780 23:07:05.139184 ==
6781 23:07:05.139256
6782 23:07:05.139316
6783 23:07:05.139372 TX Vref Scan disable
6784 23:07:05.141964 == TX Byte 0 ==
6785 23:07:05.145568 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6786 23:07:05.148480 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6787 23:07:05.151920 == TX Byte 1 ==
6788 23:07:05.155438 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6789 23:07:05.158550 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6790 23:07:05.158623
6791 23:07:05.161824 [DATLAT]
6792 23:07:05.161894 Freq=400, CH1 RK0
6793 23:07:05.161953
6794 23:07:05.165139 DATLAT Default: 0xf
6795 23:07:05.165203 0, 0xFFFF, sum = 0
6796 23:07:05.168152 1, 0xFFFF, sum = 0
6797 23:07:05.168222 2, 0xFFFF, sum = 0
6798 23:07:05.171558 3, 0xFFFF, sum = 0
6799 23:07:05.171636 4, 0xFFFF, sum = 0
6800 23:07:05.174992 5, 0xFFFF, sum = 0
6801 23:07:05.175062 6, 0xFFFF, sum = 0
6802 23:07:05.178515 7, 0xFFFF, sum = 0
6803 23:07:05.178591 8, 0xFFFF, sum = 0
6804 23:07:05.182169 9, 0xFFFF, sum = 0
6805 23:07:05.182241 10, 0xFFFF, sum = 0
6806 23:07:05.184926 11, 0xFFFF, sum = 0
6807 23:07:05.189141 12, 0xFFFF, sum = 0
6808 23:07:05.189211 13, 0x0, sum = 1
6809 23:07:05.189271 14, 0x0, sum = 2
6810 23:07:05.192051 15, 0x0, sum = 3
6811 23:07:05.192127 16, 0x0, sum = 4
6812 23:07:05.194717 best_step = 14
6813 23:07:05.194786
6814 23:07:05.194892 ==
6815 23:07:05.198357 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 23:07:05.201231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 23:07:05.201329 ==
6818 23:07:05.204657 RX Vref Scan: 1
6819 23:07:05.204731
6820 23:07:05.204789 RX Vref 0 -> 0, step: 1
6821 23:07:05.207835
6822 23:07:05.207900 RX Delay -343 -> 252, step: 8
6823 23:07:05.207959
6824 23:07:05.211821 Set Vref, RX VrefLevel [Byte0]: 47
6825 23:07:05.214231 [Byte1]: 59
6826 23:07:05.219947
6827 23:07:05.220044 Final RX Vref Byte 0 = 47 to rank0
6828 23:07:05.222652 Final RX Vref Byte 1 = 59 to rank0
6829 23:07:05.226718 Final RX Vref Byte 0 = 47 to rank1
6830 23:07:05.229456 Final RX Vref Byte 1 = 59 to rank1==
6831 23:07:05.232691 Dram Type= 6, Freq= 0, CH_1, rank 0
6832 23:07:05.239085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 23:07:05.239167 ==
6834 23:07:05.239231 DQS Delay:
6835 23:07:05.242640 DQS0 = 44, DQS1 = 56
6836 23:07:05.242721 DQM Delay:
6837 23:07:05.242785 DQM0 = 7, DQM1 = 12
6838 23:07:05.245867 DQ Delay:
6839 23:07:05.248945 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6840 23:07:05.252740 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6841 23:07:05.252821 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6842 23:07:05.256432 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =24
6843 23:07:05.259220
6844 23:07:05.259300
6845 23:07:05.265925 [DQSOSCAuto] RK0, (LSB)MR18= 0x9b72, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6846 23:07:05.269296 CH1 RK0: MR19=C0C, MR18=9B72
6847 23:07:05.275523 CH1_RK0: MR19=0xC0C, MR18=0x9B72, DQSOSC=390, MR23=63, INC=388, DEC=258
6848 23:07:05.275604 ==
6849 23:07:05.278689 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 23:07:05.282278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 23:07:05.282359 ==
6852 23:07:05.285793 [Gating] SW mode calibration
6853 23:07:05.291820 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6854 23:07:05.298631 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6855 23:07:05.302109 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6856 23:07:05.305489 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6857 23:07:05.312159 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6858 23:07:05.315280 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6859 23:07:05.318715 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6860 23:07:05.325158 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6861 23:07:05.328070 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6862 23:07:05.332015 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 23:07:05.338235 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6864 23:07:05.338343 Total UI for P1: 0, mck2ui 16
6865 23:07:05.344653 best dqsien dly found for B0: ( 0, 14, 24)
6866 23:07:05.344735 Total UI for P1: 0, mck2ui 16
6867 23:07:05.351228 best dqsien dly found for B1: ( 0, 14, 24)
6868 23:07:05.354988 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6869 23:07:05.358005 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6870 23:07:05.358087
6871 23:07:05.361504 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6872 23:07:05.364435 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6873 23:07:05.368265 [Gating] SW calibration Done
6874 23:07:05.368352 ==
6875 23:07:05.371441 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 23:07:05.375193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 23:07:05.375276 ==
6878 23:07:05.377754 RX Vref Scan: 0
6879 23:07:05.377835
6880 23:07:05.377899 RX Vref 0 -> 0, step: 1
6881 23:07:05.381051
6882 23:07:05.381131 RX Delay -410 -> 252, step: 16
6883 23:07:05.388246 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6884 23:07:05.391355 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6885 23:07:05.394536 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6886 23:07:05.398302 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6887 23:07:05.404530 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6888 23:07:05.407566 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6889 23:07:05.411294 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6890 23:07:05.414503 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6891 23:07:05.420836 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6892 23:07:05.424858 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6893 23:07:05.427827 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6894 23:07:05.430607 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6895 23:07:05.437159 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6896 23:07:05.440904 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6897 23:07:05.444322 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6898 23:07:05.450768 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6899 23:07:05.450849 ==
6900 23:07:05.453979 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 23:07:05.457033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 23:07:05.457115 ==
6903 23:07:05.457179 DQS Delay:
6904 23:07:05.460253 DQS0 = 51, DQS1 = 51
6905 23:07:05.460361 DQM Delay:
6906 23:07:05.463663 DQM0 = 19, DQM1 = 15
6907 23:07:05.463783 DQ Delay:
6908 23:07:05.467138 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6909 23:07:05.470594 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6910 23:07:05.473776 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6911 23:07:05.476967 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6912 23:07:05.477052
6913 23:07:05.477129
6914 23:07:05.477190 ==
6915 23:07:05.480122 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 23:07:05.483632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 23:07:05.483779 ==
6918 23:07:05.486807
6919 23:07:05.486886
6920 23:07:05.486949 TX Vref Scan disable
6921 23:07:05.490176 == TX Byte 0 ==
6922 23:07:05.493438 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6923 23:07:05.496410 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6924 23:07:05.500195 == TX Byte 1 ==
6925 23:07:05.503604 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6926 23:07:05.507029 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6927 23:07:05.507110 ==
6928 23:07:05.509779 Dram Type= 6, Freq= 0, CH_1, rank 1
6929 23:07:05.513256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6930 23:07:05.516149 ==
6931 23:07:05.516230
6932 23:07:05.516293
6933 23:07:05.516353 TX Vref Scan disable
6934 23:07:05.520045 == TX Byte 0 ==
6935 23:07:05.522786 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6936 23:07:05.526739 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6937 23:07:05.529793 == TX Byte 1 ==
6938 23:07:05.532902 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6939 23:07:05.536183 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6940 23:07:05.536264
6941 23:07:05.539144 [DATLAT]
6942 23:07:05.539224 Freq=400, CH1 RK1
6943 23:07:05.539289
6944 23:07:05.543208 DATLAT Default: 0xe
6945 23:07:05.543289 0, 0xFFFF, sum = 0
6946 23:07:05.545780 1, 0xFFFF, sum = 0
6947 23:07:05.545889 2, 0xFFFF, sum = 0
6948 23:07:05.549271 3, 0xFFFF, sum = 0
6949 23:07:05.549353 4, 0xFFFF, sum = 0
6950 23:07:05.552574 5, 0xFFFF, sum = 0
6951 23:07:05.552656 6, 0xFFFF, sum = 0
6952 23:07:05.555659 7, 0xFFFF, sum = 0
6953 23:07:05.555780 8, 0xFFFF, sum = 0
6954 23:07:05.559173 9, 0xFFFF, sum = 0
6955 23:07:05.559255 10, 0xFFFF, sum = 0
6956 23:07:05.562184 11, 0xFFFF, sum = 0
6957 23:07:05.565521 12, 0xFFFF, sum = 0
6958 23:07:05.565610 13, 0x0, sum = 1
6959 23:07:05.569120 14, 0x0, sum = 2
6960 23:07:05.569201 15, 0x0, sum = 3
6961 23:07:05.569266 16, 0x0, sum = 4
6962 23:07:05.572495 best_step = 14
6963 23:07:05.572575
6964 23:07:05.572639 ==
6965 23:07:05.575661 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 23:07:05.578676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 23:07:05.578757 ==
6968 23:07:05.581927 RX Vref Scan: 0
6969 23:07:05.582023
6970 23:07:05.585720 RX Vref 0 -> 0, step: 1
6971 23:07:05.585801
6972 23:07:05.585880 RX Delay -343 -> 252, step: 8
6973 23:07:05.594092 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
6974 23:07:05.597050 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6975 23:07:05.601045 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
6976 23:07:05.607225 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6977 23:07:05.610337 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
6978 23:07:05.613631 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
6979 23:07:05.617776 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6980 23:07:05.623607 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6981 23:07:05.627227 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6982 23:07:05.630864 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6983 23:07:05.633855 iDelay=225, Bit 10, Center -40 (-287 ~ 208) 496
6984 23:07:05.640015 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6985 23:07:05.643373 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6986 23:07:05.646991 iDelay=225, Bit 13, Center -36 (-287 ~ 216) 504
6987 23:07:05.649893 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6988 23:07:05.656639 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
6989 23:07:05.656721 ==
6990 23:07:05.660273 Dram Type= 6, Freq= 0, CH_1, rank 1
6991 23:07:05.663347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6992 23:07:05.663428 ==
6993 23:07:05.663521 DQS Delay:
6994 23:07:05.666638 DQS0 = 48, DQS1 = 56
6995 23:07:05.666718 DQM Delay:
6996 23:07:05.669489 DQM0 = 12, DQM1 = 11
6997 23:07:05.669569 DQ Delay:
6998 23:07:05.672886 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6999 23:07:05.676523 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
7000 23:07:05.679793 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
7001 23:07:05.683007 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
7002 23:07:05.683084
7003 23:07:05.683147
7004 23:07:05.692923 [DQSOSCAuto] RK1, (LSB)MR18= 0x6654, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 396 ps
7005 23:07:05.693020 CH1 RK1: MR19=C0C, MR18=6654
7006 23:07:05.699182 CH1_RK1: MR19=0xC0C, MR18=0x6654, DQSOSC=396, MR23=63, INC=376, DEC=251
7007 23:07:05.702566 [RxdqsGatingPostProcess] freq 400
7008 23:07:05.709326 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7009 23:07:05.712682 best DQS0 dly(2T, 0.5T) = (0, 10)
7010 23:07:05.716324 best DQS1 dly(2T, 0.5T) = (0, 10)
7011 23:07:05.719248 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7012 23:07:05.723391 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7013 23:07:05.725869 best DQS0 dly(2T, 0.5T) = (0, 10)
7014 23:07:05.725951 best DQS1 dly(2T, 0.5T) = (0, 10)
7015 23:07:05.728925 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7016 23:07:05.732260 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7017 23:07:05.735559 Pre-setting of DQS Precalculation
7018 23:07:05.742088 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7019 23:07:05.748842 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7020 23:07:05.755303 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7021 23:07:05.755402
7022 23:07:05.755496
7023 23:07:05.758511 [Calibration Summary] 800 Mbps
7024 23:07:05.762077 CH 0, Rank 0
7025 23:07:05.762144 SW Impedance : PASS
7026 23:07:05.765362 DUTY Scan : NO K
7027 23:07:05.768596 ZQ Calibration : PASS
7028 23:07:05.768669 Jitter Meter : NO K
7029 23:07:05.771905 CBT Training : PASS
7030 23:07:05.775329 Write leveling : PASS
7031 23:07:05.775422 RX DQS gating : PASS
7032 23:07:05.778499 RX DQ/DQS(RDDQC) : PASS
7033 23:07:05.781723 TX DQ/DQS : PASS
7034 23:07:05.781792 RX DATLAT : PASS
7035 23:07:05.785818 RX DQ/DQS(Engine): PASS
7036 23:07:05.785887 TX OE : NO K
7037 23:07:05.788125 All Pass.
7038 23:07:05.788196
7039 23:07:05.788262 CH 0, Rank 1
7040 23:07:05.791739 SW Impedance : PASS
7041 23:07:05.791807 DUTY Scan : NO K
7042 23:07:05.795343 ZQ Calibration : PASS
7043 23:07:05.798464 Jitter Meter : NO K
7044 23:07:05.798531 CBT Training : PASS
7045 23:07:05.801601 Write leveling : NO K
7046 23:07:05.804482 RX DQS gating : PASS
7047 23:07:05.804554 RX DQ/DQS(RDDQC) : PASS
7048 23:07:05.808004 TX DQ/DQS : PASS
7049 23:07:05.811493 RX DATLAT : PASS
7050 23:07:05.811609 RX DQ/DQS(Engine): PASS
7051 23:07:05.814513 TX OE : NO K
7052 23:07:05.814614 All Pass.
7053 23:07:05.814732
7054 23:07:05.817852 CH 1, Rank 0
7055 23:07:05.817920 SW Impedance : PASS
7056 23:07:05.821895 DUTY Scan : NO K
7057 23:07:05.824372 ZQ Calibration : PASS
7058 23:07:05.824453 Jitter Meter : NO K
7059 23:07:05.827602 CBT Training : PASS
7060 23:07:05.831002 Write leveling : PASS
7061 23:07:05.831115 RX DQS gating : PASS
7062 23:07:05.834215 RX DQ/DQS(RDDQC) : PASS
7063 23:07:05.838723 TX DQ/DQS : PASS
7064 23:07:05.838795 RX DATLAT : PASS
7065 23:07:05.840702 RX DQ/DQS(Engine): PASS
7066 23:07:05.844227 TX OE : NO K
7067 23:07:05.844305 All Pass.
7068 23:07:05.844375
7069 23:07:05.844433 CH 1, Rank 1
7070 23:07:05.847208 SW Impedance : PASS
7071 23:07:05.850353 DUTY Scan : NO K
7072 23:07:05.850421 ZQ Calibration : PASS
7073 23:07:05.854009 Jitter Meter : NO K
7074 23:07:05.857506 CBT Training : PASS
7075 23:07:05.857580 Write leveling : NO K
7076 23:07:05.860400 RX DQS gating : PASS
7077 23:07:05.863553 RX DQ/DQS(RDDQC) : PASS
7078 23:07:05.863647 TX DQ/DQS : PASS
7079 23:07:05.867516 RX DATLAT : PASS
7080 23:07:05.870331 RX DQ/DQS(Engine): PASS
7081 23:07:05.870398 TX OE : NO K
7082 23:07:05.873592 All Pass.
7083 23:07:05.873660
7084 23:07:05.873724 DramC Write-DBI off
7085 23:07:05.876835 PER_BANK_REFRESH: Hybrid Mode
7086 23:07:05.876900 TX_TRACKING: ON
7087 23:07:05.886378 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7088 23:07:05.890104 [FAST_K] Save calibration result to emmc
7089 23:07:05.893544 dramc_set_vcore_voltage set vcore to 725000
7090 23:07:05.896528 Read voltage for 1600, 0
7091 23:07:05.896606 Vio18 = 0
7092 23:07:05.900222 Vcore = 725000
7093 23:07:05.900289 Vdram = 0
7094 23:07:05.900354 Vddq = 0
7095 23:07:05.903320 Vmddr = 0
7096 23:07:05.906181 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7097 23:07:05.912499 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7098 23:07:05.912582 MEM_TYPE=3, freq_sel=13
7099 23:07:05.915796 sv_algorithm_assistance_LP4_3733
7100 23:07:05.922613 ============ PULL DRAM RESETB DOWN ============
7101 23:07:05.926089 ========== PULL DRAM RESETB DOWN end =========
7102 23:07:05.928997 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7103 23:07:05.932644 ===================================
7104 23:07:05.935807 LPDDR4 DRAM CONFIGURATION
7105 23:07:05.939120 ===================================
7106 23:07:05.942319 EX_ROW_EN[0] = 0x0
7107 23:07:05.942399 EX_ROW_EN[1] = 0x0
7108 23:07:05.945681 LP4Y_EN = 0x0
7109 23:07:05.945762 WORK_FSP = 0x1
7110 23:07:05.949344 WL = 0x5
7111 23:07:05.949425 RL = 0x5
7112 23:07:05.952507 BL = 0x2
7113 23:07:05.952591 RPST = 0x0
7114 23:07:05.955485 RD_PRE = 0x0
7115 23:07:05.955565 WR_PRE = 0x1
7116 23:07:05.958765 WR_PST = 0x1
7117 23:07:05.958845 DBI_WR = 0x0
7118 23:07:05.962506 DBI_RD = 0x0
7119 23:07:05.965880 OTF = 0x1
7120 23:07:05.969256 ===================================
7121 23:07:05.969337 ===================================
7122 23:07:05.972500 ANA top config
7123 23:07:05.975691 ===================================
7124 23:07:05.978829 DLL_ASYNC_EN = 0
7125 23:07:05.978909 ALL_SLAVE_EN = 0
7126 23:07:05.981761 NEW_RANK_MODE = 1
7127 23:07:05.985687 DLL_IDLE_MODE = 1
7128 23:07:05.988563 LP45_APHY_COMB_EN = 1
7129 23:07:05.992537 TX_ODT_DIS = 0
7130 23:07:05.992619 NEW_8X_MODE = 1
7131 23:07:05.995733 ===================================
7132 23:07:05.999343 ===================================
7133 23:07:06.002437 data_rate = 3200
7134 23:07:06.005280 CKR = 1
7135 23:07:06.008359 DQ_P2S_RATIO = 8
7136 23:07:06.012108 ===================================
7137 23:07:06.015321 CA_P2S_RATIO = 8
7138 23:07:06.018285 DQ_CA_OPEN = 0
7139 23:07:06.018366 DQ_SEMI_OPEN = 0
7140 23:07:06.021942 CA_SEMI_OPEN = 0
7141 23:07:06.024876 CA_FULL_RATE = 0
7142 23:07:06.028469 DQ_CKDIV4_EN = 0
7143 23:07:06.031741 CA_CKDIV4_EN = 0
7144 23:07:06.035408 CA_PREDIV_EN = 0
7145 23:07:06.035488 PH8_DLY = 12
7146 23:07:06.038636 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7147 23:07:06.042239 DQ_AAMCK_DIV = 4
7148 23:07:06.044702 CA_AAMCK_DIV = 4
7149 23:07:06.048212 CA_ADMCK_DIV = 4
7150 23:07:06.051365 DQ_TRACK_CA_EN = 0
7151 23:07:06.054560 CA_PICK = 1600
7152 23:07:06.054640 CA_MCKIO = 1600
7153 23:07:06.058846 MCKIO_SEMI = 0
7154 23:07:06.061281 PLL_FREQ = 3068
7155 23:07:06.064964 DQ_UI_PI_RATIO = 32
7156 23:07:06.068572 CA_UI_PI_RATIO = 0
7157 23:07:06.071205 ===================================
7158 23:07:06.074506 ===================================
7159 23:07:06.077689 memory_type:LPDDR4
7160 23:07:06.077769 GP_NUM : 10
7161 23:07:06.081106 SRAM_EN : 1
7162 23:07:06.081208 MD32_EN : 0
7163 23:07:06.084247 ===================================
7164 23:07:06.088077 [ANA_INIT] >>>>>>>>>>>>>>
7165 23:07:06.091200 <<<<<< [CONFIGURE PHASE]: ANA_TX
7166 23:07:06.094605 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7167 23:07:06.097920 ===================================
7168 23:07:06.100780 data_rate = 3200,PCW = 0X7600
7169 23:07:06.104056 ===================================
7170 23:07:06.107832 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7171 23:07:06.114502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7172 23:07:06.117816 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7173 23:07:06.124034 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7174 23:07:06.127676 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7175 23:07:06.130755 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7176 23:07:06.130836 [ANA_INIT] flow start
7177 23:07:06.134585 [ANA_INIT] PLL >>>>>>>>
7178 23:07:06.137788 [ANA_INIT] PLL <<<<<<<<
7179 23:07:06.137900 [ANA_INIT] MIDPI >>>>>>>>
7180 23:07:06.141048 [ANA_INIT] MIDPI <<<<<<<<
7181 23:07:06.143832 [ANA_INIT] DLL >>>>>>>>
7182 23:07:06.147936 [ANA_INIT] DLL <<<<<<<<
7183 23:07:06.148016 [ANA_INIT] flow end
7184 23:07:06.150843 ============ LP4 DIFF to SE enter ============
7185 23:07:06.157278 ============ LP4 DIFF to SE exit ============
7186 23:07:06.157359 [ANA_INIT] <<<<<<<<<<<<<
7187 23:07:06.160753 [Flow] Enable top DCM control >>>>>
7188 23:07:06.163275 [Flow] Enable top DCM control <<<<<
7189 23:07:06.166626 Enable DLL master slave shuffle
7190 23:07:06.173800 ==============================================================
7191 23:07:06.173881 Gating Mode config
7192 23:07:06.180351 ==============================================================
7193 23:07:06.183536 Config description:
7194 23:07:06.193648 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7195 23:07:06.199819 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7196 23:07:06.203190 SELPH_MODE 0: By rank 1: By Phase
7197 23:07:06.210296 ==============================================================
7198 23:07:06.213505 GAT_TRACK_EN = 1
7199 23:07:06.216705 RX_GATING_MODE = 2
7200 23:07:06.216786 RX_GATING_TRACK_MODE = 2
7201 23:07:06.219581 SELPH_MODE = 1
7202 23:07:06.222898 PICG_EARLY_EN = 1
7203 23:07:06.226347 VALID_LAT_VALUE = 1
7204 23:07:06.233410 ==============================================================
7205 23:07:06.236338 Enter into Gating configuration >>>>
7206 23:07:06.240085 Exit from Gating configuration <<<<
7207 23:07:06.242838 Enter into DVFS_PRE_config >>>>>
7208 23:07:06.253147 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7209 23:07:06.256257 Exit from DVFS_PRE_config <<<<<
7210 23:07:06.259258 Enter into PICG configuration >>>>
7211 23:07:06.262599 Exit from PICG configuration <<<<
7212 23:07:06.266070 [RX_INPUT] configuration >>>>>
7213 23:07:06.269116 [RX_INPUT] configuration <<<<<
7214 23:07:06.273006 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7215 23:07:06.279842 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7216 23:07:06.285942 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7217 23:07:06.292223 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7218 23:07:06.298811 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7219 23:07:06.305273 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7220 23:07:06.308843 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7221 23:07:06.312128 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7222 23:07:06.315276 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7223 23:07:06.322184 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7224 23:07:06.325670 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7225 23:07:06.328664 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7226 23:07:06.331823 ===================================
7227 23:07:06.335213 LPDDR4 DRAM CONFIGURATION
7228 23:07:06.338255 ===================================
7229 23:07:06.338336 EX_ROW_EN[0] = 0x0
7230 23:07:06.341889 EX_ROW_EN[1] = 0x0
7231 23:07:06.344784 LP4Y_EN = 0x0
7232 23:07:06.344864 WORK_FSP = 0x1
7233 23:07:06.348215 WL = 0x5
7234 23:07:06.348295 RL = 0x5
7235 23:07:06.351641 BL = 0x2
7236 23:07:06.351771 RPST = 0x0
7237 23:07:06.355068 RD_PRE = 0x0
7238 23:07:06.355148 WR_PRE = 0x1
7239 23:07:06.358463 WR_PST = 0x1
7240 23:07:06.358543 DBI_WR = 0x0
7241 23:07:06.361889 DBI_RD = 0x0
7242 23:07:06.361969 OTF = 0x1
7243 23:07:06.364790 ===================================
7244 23:07:06.368414 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7245 23:07:06.374608 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7246 23:07:06.378249 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7247 23:07:06.381331 ===================================
7248 23:07:06.384680 LPDDR4 DRAM CONFIGURATION
7249 23:07:06.387873 ===================================
7250 23:07:06.387954 EX_ROW_EN[0] = 0x10
7251 23:07:06.391211 EX_ROW_EN[1] = 0x0
7252 23:07:06.394387 LP4Y_EN = 0x0
7253 23:07:06.394496 WORK_FSP = 0x1
7254 23:07:06.398199 WL = 0x5
7255 23:07:06.398286 RL = 0x5
7256 23:07:06.400831 BL = 0x2
7257 23:07:06.400911 RPST = 0x0
7258 23:07:06.404630 RD_PRE = 0x0
7259 23:07:06.404711 WR_PRE = 0x1
7260 23:07:06.407647 WR_PST = 0x1
7261 23:07:06.407753 DBI_WR = 0x0
7262 23:07:06.411215 DBI_RD = 0x0
7263 23:07:06.411296 OTF = 0x1
7264 23:07:06.414565 ===================================
7265 23:07:06.420666 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7266 23:07:06.420748 ==
7267 23:07:06.424080 Dram Type= 6, Freq= 0, CH_0, rank 0
7268 23:07:06.427844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7269 23:07:06.431102 ==
7270 23:07:06.431183 [Duty_Offset_Calibration]
7271 23:07:06.434708 B0:1 B1:-1 CA:1
7272 23:07:06.434789
7273 23:07:06.437929 [DutyScan_Calibration_Flow] k_type=0
7274 23:07:06.446414
7275 23:07:06.446517 ==CLK 0==
7276 23:07:06.449593 Final CLK duty delay cell = 0
7277 23:07:06.453152 [0] MAX Duty = 5156%(X100), DQS PI = 22
7278 23:07:06.455973 [0] MIN Duty = 4907%(X100), DQS PI = 6
7279 23:07:06.456082 [0] AVG Duty = 5031%(X100)
7280 23:07:06.459796
7281 23:07:06.462877 CH0 CLK Duty spec in!! Max-Min= 249%
7282 23:07:06.466383 [DutyScan_Calibration_Flow] ====Done====
7283 23:07:06.466464
7284 23:07:06.469683 [DutyScan_Calibration_Flow] k_type=1
7285 23:07:06.485091
7286 23:07:06.485171 ==DQS 0 ==
7287 23:07:06.488735 Final DQS duty delay cell = -4
7288 23:07:06.492026 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7289 23:07:06.495348 [-4] MIN Duty = 4844%(X100), DQS PI = 58
7290 23:07:06.498279 [-4] AVG Duty = 4922%(X100)
7291 23:07:06.498388
7292 23:07:06.498453 ==DQS 1 ==
7293 23:07:06.501740 Final DQS duty delay cell = 0
7294 23:07:06.505146 [0] MAX Duty = 5156%(X100), DQS PI = 0
7295 23:07:06.508362 [0] MIN Duty = 5031%(X100), DQS PI = 18
7296 23:07:06.511524 [0] AVG Duty = 5093%(X100)
7297 23:07:06.511604
7298 23:07:06.515252 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7299 23:07:06.515333
7300 23:07:06.518177 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7301 23:07:06.521435 [DutyScan_Calibration_Flow] ====Done====
7302 23:07:06.521530
7303 23:07:06.525720 [DutyScan_Calibration_Flow] k_type=3
7304 23:07:06.542714
7305 23:07:06.542793 ==DQM 0 ==
7306 23:07:06.546150 Final DQM duty delay cell = 0
7307 23:07:06.549968 [0] MAX Duty = 5124%(X100), DQS PI = 22
7308 23:07:06.553665 [0] MIN Duty = 4907%(X100), DQS PI = 10
7309 23:07:06.556186 [0] AVG Duty = 5015%(X100)
7310 23:07:06.556267
7311 23:07:06.556329 ==DQM 1 ==
7312 23:07:06.559799 Final DQM duty delay cell = 0
7313 23:07:06.563114 [0] MAX Duty = 5031%(X100), DQS PI = 54
7314 23:07:06.566221 [0] MIN Duty = 4813%(X100), DQS PI = 20
7315 23:07:06.569265 [0] AVG Duty = 4922%(X100)
7316 23:07:06.569369
7317 23:07:06.573507 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7318 23:07:06.573578
7319 23:07:06.576122 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7320 23:07:06.579598 [DutyScan_Calibration_Flow] ====Done====
7321 23:07:06.579664
7322 23:07:06.582326 [DutyScan_Calibration_Flow] k_type=2
7323 23:07:06.599077
7324 23:07:06.599157 ==DQ 0 ==
7325 23:07:06.602409 Final DQ duty delay cell = -4
7326 23:07:06.605796 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7327 23:07:06.609125 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7328 23:07:06.612143 [-4] AVG Duty = 4953%(X100)
7329 23:07:06.612214
7330 23:07:06.612273 ==DQ 1 ==
7331 23:07:06.615498 Final DQ duty delay cell = 0
7332 23:07:06.619781 [0] MAX Duty = 5125%(X100), DQS PI = 4
7333 23:07:06.622209 [0] MIN Duty = 5000%(X100), DQS PI = 36
7334 23:07:06.625721 [0] AVG Duty = 5062%(X100)
7335 23:07:06.625795
7336 23:07:06.628660 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7337 23:07:06.628728
7338 23:07:06.632420 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7339 23:07:06.635585 [DutyScan_Calibration_Flow] ====Done====
7340 23:07:06.635701 ==
7341 23:07:06.638802 Dram Type= 6, Freq= 0, CH_1, rank 0
7342 23:07:06.641857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7343 23:07:06.641923 ==
7344 23:07:06.645221 [Duty_Offset_Calibration]
7345 23:07:06.645294 B0:-1 B1:1 CA:2
7346 23:07:06.645386
7347 23:07:06.648595 [DutyScan_Calibration_Flow] k_type=0
7348 23:07:06.659956
7349 23:07:06.660026 ==CLK 0==
7350 23:07:06.663378 Final CLK duty delay cell = 0
7351 23:07:06.666611 [0] MAX Duty = 5187%(X100), DQS PI = 24
7352 23:07:06.669624 [0] MIN Duty = 4969%(X100), DQS PI = 0
7353 23:07:06.673383 [0] AVG Duty = 5078%(X100)
7354 23:07:06.673463
7355 23:07:06.676255 CH1 CLK Duty spec in!! Max-Min= 218%
7356 23:07:06.679848 [DutyScan_Calibration_Flow] ====Done====
7357 23:07:06.679928
7358 23:07:06.682881 [DutyScan_Calibration_Flow] k_type=1
7359 23:07:06.700019
7360 23:07:06.700098 ==DQS 0 ==
7361 23:07:06.702574 Final DQS duty delay cell = 0
7362 23:07:06.706573 [0] MAX Duty = 5124%(X100), DQS PI = 18
7363 23:07:06.709510 [0] MIN Duty = 4907%(X100), DQS PI = 10
7364 23:07:06.712619 [0] AVG Duty = 5015%(X100)
7365 23:07:06.712699
7366 23:07:06.712762 ==DQS 1 ==
7367 23:07:06.715805 Final DQS duty delay cell = 0
7368 23:07:06.719464 [0] MAX Duty = 5093%(X100), DQS PI = 24
7369 23:07:06.722743 [0] MIN Duty = 4969%(X100), DQS PI = 56
7370 23:07:06.725594 [0] AVG Duty = 5031%(X100)
7371 23:07:06.725673
7372 23:07:06.729359 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7373 23:07:06.729461
7374 23:07:06.732444 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7375 23:07:06.735827 [DutyScan_Calibration_Flow] ====Done====
7376 23:07:06.735934
7377 23:07:06.738908 [DutyScan_Calibration_Flow] k_type=3
7378 23:07:06.756402
7379 23:07:06.756483 ==DQM 0 ==
7380 23:07:06.758734 Final DQM duty delay cell = -4
7381 23:07:06.762245 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7382 23:07:06.765664 [-4] MIN Duty = 4782%(X100), DQS PI = 10
7383 23:07:06.768853 [-4] AVG Duty = 4906%(X100)
7384 23:07:06.768976
7385 23:07:06.769042 ==DQM 1 ==
7386 23:07:06.772008 Final DQM duty delay cell = 0
7387 23:07:06.775107 [0] MAX Duty = 5156%(X100), DQS PI = 2
7388 23:07:06.778396 [0] MIN Duty = 4969%(X100), DQS PI = 32
7389 23:07:06.781673 [0] AVG Duty = 5062%(X100)
7390 23:07:06.781739
7391 23:07:06.784948 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7392 23:07:06.785023
7393 23:07:06.788554 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7394 23:07:06.791757 [DutyScan_Calibration_Flow] ====Done====
7395 23:07:06.791828
7396 23:07:06.795374 [DutyScan_Calibration_Flow] k_type=2
7397 23:07:06.813180
7398 23:07:06.813288 ==DQ 0 ==
7399 23:07:06.816430 Final DQ duty delay cell = 0
7400 23:07:06.819634 [0] MAX Duty = 5187%(X100), DQS PI = 32
7401 23:07:06.822948 [0] MIN Duty = 4906%(X100), DQS PI = 8
7402 23:07:06.823017 [0] AVG Duty = 5046%(X100)
7403 23:07:06.823076
7404 23:07:06.826046 ==DQ 1 ==
7405 23:07:06.829282 Final DQ duty delay cell = 0
7406 23:07:06.832522 [0] MAX Duty = 5156%(X100), DQS PI = 10
7407 23:07:06.835988 [0] MIN Duty = 4938%(X100), DQS PI = 60
7408 23:07:06.836056 [0] AVG Duty = 5047%(X100)
7409 23:07:06.836115
7410 23:07:06.839723 CH1 DQ 0 Duty spec in!! Max-Min= 281%
7411 23:07:06.842433
7412 23:07:06.846006 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7413 23:07:06.849257 [DutyScan_Calibration_Flow] ====Done====
7414 23:07:06.852946 nWR fixed to 30
7415 23:07:06.853020 [ModeRegInit_LP4] CH0 RK0
7416 23:07:06.855909 [ModeRegInit_LP4] CH0 RK1
7417 23:07:06.859297 [ModeRegInit_LP4] CH1 RK0
7418 23:07:06.862321 [ModeRegInit_LP4] CH1 RK1
7419 23:07:06.862394 match AC timing 5
7420 23:07:06.868946 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7421 23:07:06.872307 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7422 23:07:06.875641 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7423 23:07:06.882088 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7424 23:07:06.885918 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7425 23:07:06.885986 [MiockJmeterHQA]
7426 23:07:06.886045
7427 23:07:06.889228 [DramcMiockJmeter] u1RxGatingPI = 0
7428 23:07:06.891965 0 : 4255, 4030
7429 23:07:06.892033 4 : 4257, 4027
7430 23:07:06.895555 8 : 4252, 4027
7431 23:07:06.895628 12 : 4363, 4137
7432 23:07:06.895697 16 : 4363, 4137
7433 23:07:06.899114 20 : 4253, 4027
7434 23:07:06.899181 24 : 4252, 4026
7435 23:07:06.902492 28 : 4252, 4027
7436 23:07:06.902558 32 : 4363, 4137
7437 23:07:06.905363 36 : 4252, 4026
7438 23:07:06.905428 40 : 4363, 4138
7439 23:07:06.908668 44 : 4252, 4027
7440 23:07:06.908731 48 : 4253, 4026
7441 23:07:06.908788 52 : 4253, 4027
7442 23:07:06.912476 56 : 4254, 4029
7443 23:07:06.912549 60 : 4363, 4137
7444 23:07:06.915278 64 : 4253, 4029
7445 23:07:06.915382 68 : 4360, 4137
7446 23:07:06.919191 72 : 4250, 4027
7447 23:07:06.919274 76 : 4250, 4026
7448 23:07:06.921964 80 : 4250, 4026
7449 23:07:06.922036 84 : 4361, 4137
7450 23:07:06.922138 88 : 4250, 4026
7451 23:07:06.924866 92 : 4361, 634
7452 23:07:06.924934 96 : 4252, 0
7453 23:07:06.928151 100 : 4252, 0
7454 23:07:06.928223 104 : 4363, 0
7455 23:07:06.928283 108 : 4250, 0
7456 23:07:06.931385 112 : 4250, 0
7457 23:07:06.931486 116 : 4250, 0
7458 23:07:06.934930 120 : 4250, 0
7459 23:07:06.935053 124 : 4253, 0
7460 23:07:06.935145 128 : 4361, 0
7461 23:07:06.938151 132 : 4250, 0
7462 23:07:06.938218 136 : 4250, 0
7463 23:07:06.941969 140 : 4252, 0
7464 23:07:06.942042 144 : 4360, 0
7465 23:07:06.942101 148 : 4250, 0
7466 23:07:06.945116 152 : 4250, 0
7467 23:07:06.945205 156 : 4250, 0
7468 23:07:06.948746 160 : 4250, 0
7469 23:07:06.948813 164 : 4252, 0
7470 23:07:06.948872 168 : 4250, 0
7471 23:07:06.951402 172 : 4250, 0
7472 23:07:06.951494 176 : 4252, 0
7473 23:07:06.951588 180 : 4361, 0
7474 23:07:06.954840 184 : 4250, 0
7475 23:07:06.954906 188 : 4250, 0
7476 23:07:06.957749 192 : 4250, 0
7477 23:07:06.957836 196 : 4361, 0
7478 23:07:06.957910 200 : 4361, 0
7479 23:07:06.961643 204 : 4249, 0
7480 23:07:06.961714 208 : 4250, 0
7481 23:07:06.965268 212 : 4363, 0
7482 23:07:06.965345 216 : 4250, 0
7483 23:07:06.965431 220 : 4250, 0
7484 23:07:06.968611 224 : 4250, 412
7485 23:07:06.968683 228 : 4361, 3666
7486 23:07:06.970942 232 : 4250, 4027
7487 23:07:06.971008 236 : 4361, 4138
7488 23:07:06.975055 240 : 4253, 4029
7489 23:07:06.975127 244 : 4250, 4027
7490 23:07:06.978101 248 : 4250, 4027
7491 23:07:06.978173 252 : 4252, 4029
7492 23:07:06.981008 256 : 4250, 4027
7493 23:07:06.981100 260 : 4250, 4027
7494 23:07:06.984394 264 : 4252, 4027
7495 23:07:06.984462 268 : 4252, 4029
7496 23:07:06.987347 272 : 4250, 4027
7497 23:07:06.987415 276 : 4361, 4137
7498 23:07:06.987479 280 : 4361, 4137
7499 23:07:06.990817 284 : 4250, 4026
7500 23:07:06.990916 288 : 4363, 4140
7501 23:07:06.994501 292 : 4361, 4137
7502 23:07:06.994571 296 : 4250, 4027
7503 23:07:06.997630 300 : 4250, 4027
7504 23:07:06.997699 304 : 4253, 4030
7505 23:07:07.000685 308 : 4250, 4027
7506 23:07:07.000764 312 : 4250, 4027
7507 23:07:07.004570 316 : 4250, 4027
7508 23:07:07.004637 320 : 4253, 4029
7509 23:07:07.007488 324 : 4250, 4027
7510 23:07:07.007586 328 : 4360, 4138
7511 23:07:07.011048 332 : 4361, 4137
7512 23:07:07.011115 336 : 4250, 3919
7513 23:07:07.011174 340 : 4363, 2203
7514 23:07:07.014387 344 : 4361, 28
7515 23:07:07.014477
7516 23:07:07.017995 MIOCK jitter meter ch=0
7517 23:07:07.018065
7518 23:07:07.021134 1T = (344-92) = 252 dly cells
7519 23:07:07.024247 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7520 23:07:07.024328 ==
7521 23:07:07.027087 Dram Type= 6, Freq= 0, CH_0, rank 0
7522 23:07:07.034207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7523 23:07:07.034284 ==
7524 23:07:07.037529 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7525 23:07:07.043822 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7526 23:07:07.046985 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7527 23:07:07.053562 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7528 23:07:07.061708 [CA 0] Center 43 (12~74) winsize 63
7529 23:07:07.064768 [CA 1] Center 42 (12~73) winsize 62
7530 23:07:07.067748 [CA 2] Center 38 (9~68) winsize 60
7531 23:07:07.071147 [CA 3] Center 38 (8~68) winsize 61
7532 23:07:07.074335 [CA 4] Center 36 (7~66) winsize 60
7533 23:07:07.077819 [CA 5] Center 35 (6~65) winsize 60
7534 23:07:07.077891
7535 23:07:07.081413 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7536 23:07:07.081486
7537 23:07:07.087450 [CATrainingPosCal] consider 1 rank data
7538 23:07:07.087542 u2DelayCellTimex100 = 258/100 ps
7539 23:07:07.094568 CA0 delay=43 (12~74),Diff = 8 PI (30 cell)
7540 23:07:07.097239 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7541 23:07:07.100790 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7542 23:07:07.104402 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7543 23:07:07.107908 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7544 23:07:07.111028 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7545 23:07:07.111122
7546 23:07:07.113977 CA PerBit enable=1, Macro0, CA PI delay=35
7547 23:07:07.114050
7548 23:07:07.117375 [CBTSetCACLKResult] CA Dly = 35
7549 23:07:07.120306 CS Dly: 12 (0~43)
7550 23:07:07.125219 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7551 23:07:07.127271 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7552 23:07:07.130763 ==
7553 23:07:07.130850 Dram Type= 6, Freq= 0, CH_0, rank 1
7554 23:07:07.136748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7555 23:07:07.136817 ==
7556 23:07:07.140035 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7557 23:07:07.146524 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7558 23:07:07.150062 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7559 23:07:07.157984 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7560 23:07:07.164911 [CA 0] Center 43 (13~74) winsize 62
7561 23:07:07.168573 [CA 1] Center 44 (14~74) winsize 61
7562 23:07:07.171581 [CA 2] Center 38 (9~68) winsize 60
7563 23:07:07.174632 [CA 3] Center 38 (9~68) winsize 60
7564 23:07:07.178015 [CA 4] Center 36 (7~66) winsize 60
7565 23:07:07.181432 [CA 5] Center 36 (7~66) winsize 60
7566 23:07:07.181516
7567 23:07:07.184480 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7568 23:07:07.184551
7569 23:07:07.187847 [CATrainingPosCal] consider 2 rank data
7570 23:07:07.191383 u2DelayCellTimex100 = 258/100 ps
7571 23:07:07.197927 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7572 23:07:07.201059 CA1 delay=43 (14~73),Diff = 7 PI (26 cell)
7573 23:07:07.204533 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7574 23:07:07.207919 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7575 23:07:07.211049 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7576 23:07:07.214486 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7577 23:07:07.214560
7578 23:07:07.217898 CA PerBit enable=1, Macro0, CA PI delay=36
7579 23:07:07.217976
7580 23:07:07.220736 [CBTSetCACLKResult] CA Dly = 36
7581 23:07:07.224160 CS Dly: 12 (0~43)
7582 23:07:07.227308 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7583 23:07:07.231134 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7584 23:07:07.231253
7585 23:07:07.234741 ----->DramcWriteLeveling(PI) begin...
7586 23:07:07.234809 ==
7587 23:07:07.237677 Dram Type= 6, Freq= 0, CH_0, rank 0
7588 23:07:07.243925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7589 23:07:07.244003 ==
7590 23:07:07.247494 Write leveling (Byte 0): 35 => 35
7591 23:07:07.250400 Write leveling (Byte 1): 26 => 26
7592 23:07:07.250478 DramcWriteLeveling(PI) end<-----
7593 23:07:07.253996
7594 23:07:07.254063 ==
7595 23:07:07.256750 Dram Type= 6, Freq= 0, CH_0, rank 0
7596 23:07:07.260562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7597 23:07:07.260630 ==
7598 23:07:07.263865 [Gating] SW mode calibration
7599 23:07:07.271138 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7600 23:07:07.274056 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7601 23:07:07.280274 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 23:07:07.283369 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 23:07:07.287193 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 23:07:07.293451 1 4 12 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
7605 23:07:07.296471 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7606 23:07:07.299846 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (1 1) (1 1)
7607 23:07:07.306644 1 4 24 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7608 23:07:07.309941 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7609 23:07:07.313071 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7610 23:07:07.319728 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 23:07:07.323324 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7612 23:07:07.326800 1 5 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (0 1)
7613 23:07:07.332985 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7614 23:07:07.336343 1 5 20 | B1->B0 | 3131 2323 | 0 0 | (1 0) (0 0)
7615 23:07:07.339605 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7616 23:07:07.346334 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 23:07:07.349980 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 23:07:07.353178 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 23:07:07.359069 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7620 23:07:07.362749 1 6 12 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
7621 23:07:07.366030 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7622 23:07:07.373539 1 6 20 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
7623 23:07:07.375622 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7624 23:07:07.379304 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 23:07:07.385500 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 23:07:07.389252 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 23:07:07.392026 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7628 23:07:07.399090 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7629 23:07:07.402350 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7630 23:07:07.408580 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7631 23:07:07.411996 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 23:07:07.415282 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 23:07:07.422043 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 23:07:07.425011 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 23:07:07.428639 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 23:07:07.431606 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 23:07:07.438854 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 23:07:07.441637 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 23:07:07.445133 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 23:07:07.451641 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 23:07:07.454655 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 23:07:07.458547 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 23:07:07.465013 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7644 23:07:07.468358 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7645 23:07:07.471147 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7646 23:07:07.474678 Total UI for P1: 0, mck2ui 16
7647 23:07:07.478131 best dqsien dly found for B0: ( 1, 9, 10)
7648 23:07:07.484544 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7649 23:07:07.487997 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 23:07:07.491513 Total UI for P1: 0, mck2ui 16
7651 23:07:07.494723 best dqsien dly found for B1: ( 1, 9, 20)
7652 23:07:07.497634 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7653 23:07:07.501550 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7654 23:07:07.501623
7655 23:07:07.504300 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7656 23:07:07.511109 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7657 23:07:07.511181 [Gating] SW calibration Done
7658 23:07:07.511247 ==
7659 23:07:07.514120 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 23:07:07.520736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 23:07:07.520813 ==
7662 23:07:07.520882 RX Vref Scan: 0
7663 23:07:07.520940
7664 23:07:07.524103 RX Vref 0 -> 0, step: 1
7665 23:07:07.524173
7666 23:07:07.527655 RX Delay 0 -> 252, step: 8
7667 23:07:07.530953 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7668 23:07:07.533774 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7669 23:07:07.537403 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7670 23:07:07.543928 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7671 23:07:07.547807 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7672 23:07:07.551017 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7673 23:07:07.554924 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7674 23:07:07.557591 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7675 23:07:07.564035 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7676 23:07:07.567513 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7677 23:07:07.570313 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7678 23:07:07.573498 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7679 23:07:07.576781 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7680 23:07:07.583791 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7681 23:07:07.586902 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7682 23:07:07.590234 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7683 23:07:07.590304 ==
7684 23:07:07.593795 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 23:07:07.597107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 23:07:07.600417 ==
7687 23:07:07.600491 DQS Delay:
7688 23:07:07.600550 DQS0 = 0, DQS1 = 0
7689 23:07:07.603969 DQM Delay:
7690 23:07:07.604034 DQM0 = 135, DQM1 = 127
7691 23:07:07.607361 DQ Delay:
7692 23:07:07.610157 DQ0 =131, DQ1 =139, DQ2 =131, DQ3 =131
7693 23:07:07.613226 DQ4 =135, DQ5 =123, DQ6 =143, DQ7 =147
7694 23:07:07.616653 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7695 23:07:07.620056 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7696 23:07:07.620128
7697 23:07:07.620188
7698 23:07:07.620250 ==
7699 23:07:07.623194 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 23:07:07.626785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 23:07:07.626853 ==
7702 23:07:07.629762
7703 23:07:07.629841
7704 23:07:07.629904 TX Vref Scan disable
7705 23:07:07.633133 == TX Byte 0 ==
7706 23:07:07.636752 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7707 23:07:07.639777 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7708 23:07:07.642953 == TX Byte 1 ==
7709 23:07:07.646272 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7710 23:07:07.649788 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7711 23:07:07.649856 ==
7712 23:07:07.653340 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 23:07:07.659526 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 23:07:07.659594 ==
7715 23:07:07.672439
7716 23:07:07.675888 TX Vref early break, caculate TX vref
7717 23:07:07.678967 TX Vref=16, minBit 14, minWin=22, winSum=373
7718 23:07:07.682100 TX Vref=18, minBit 7, minWin=22, winSum=376
7719 23:07:07.685406 TX Vref=20, minBit 1, minWin=23, winSum=393
7720 23:07:07.688485 TX Vref=22, minBit 1, minWin=24, winSum=403
7721 23:07:07.695196 TX Vref=24, minBit 0, minWin=25, winSum=412
7722 23:07:07.698856 TX Vref=26, minBit 2, minWin=25, winSum=417
7723 23:07:07.701756 TX Vref=28, minBit 4, minWin=25, winSum=415
7724 23:07:07.705362 TX Vref=30, minBit 0, minWin=25, winSum=409
7725 23:07:07.708395 TX Vref=32, minBit 0, minWin=24, winSum=396
7726 23:07:07.711706 TX Vref=34, minBit 4, minWin=22, winSum=386
7727 23:07:07.717951 [TxChooseVref] Worse bit 2, Min win 25, Win sum 417, Final Vref 26
7728 23:07:07.718034
7729 23:07:07.721198 Final TX Range 0 Vref 26
7730 23:07:07.721270
7731 23:07:07.721329 ==
7732 23:07:07.724942 Dram Type= 6, Freq= 0, CH_0, rank 0
7733 23:07:07.728023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7734 23:07:07.728102 ==
7735 23:07:07.728164
7736 23:07:07.731544
7737 23:07:07.731611 TX Vref Scan disable
7738 23:07:07.738464 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7739 23:07:07.738540 == TX Byte 0 ==
7740 23:07:07.741424 u2DelayCellOfst[0]=15 cells (4 PI)
7741 23:07:07.744644 u2DelayCellOfst[1]=18 cells (5 PI)
7742 23:07:07.748124 u2DelayCellOfst[2]=15 cells (4 PI)
7743 23:07:07.751164 u2DelayCellOfst[3]=15 cells (4 PI)
7744 23:07:07.754782 u2DelayCellOfst[4]=11 cells (3 PI)
7745 23:07:07.758172 u2DelayCellOfst[5]=0 cells (0 PI)
7746 23:07:07.760940 u2DelayCellOfst[6]=22 cells (6 PI)
7747 23:07:07.764389 u2DelayCellOfst[7]=22 cells (6 PI)
7748 23:07:07.767883 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7749 23:07:07.771087 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7750 23:07:07.774307 == TX Byte 1 ==
7751 23:07:07.778546 u2DelayCellOfst[8]=0 cells (0 PI)
7752 23:07:07.781310 u2DelayCellOfst[9]=0 cells (0 PI)
7753 23:07:07.784063 u2DelayCellOfst[10]=3 cells (1 PI)
7754 23:07:07.787338 u2DelayCellOfst[11]=0 cells (0 PI)
7755 23:07:07.790986 u2DelayCellOfst[12]=7 cells (2 PI)
7756 23:07:07.791069 u2DelayCellOfst[13]=7 cells (2 PI)
7757 23:07:07.793827 u2DelayCellOfst[14]=11 cells (3 PI)
7758 23:07:07.797133 u2DelayCellOfst[15]=7 cells (2 PI)
7759 23:07:07.804168 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7760 23:07:07.807362 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7761 23:07:07.807445 DramC Write-DBI on
7762 23:07:07.810787 ==
7763 23:07:07.813582 Dram Type= 6, Freq= 0, CH_0, rank 0
7764 23:07:07.816797 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7765 23:07:07.816922 ==
7766 23:07:07.817034
7767 23:07:07.817112
7768 23:07:07.820557 TX Vref Scan disable
7769 23:07:07.820653 == TX Byte 0 ==
7770 23:07:07.826672 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7771 23:07:07.826770 == TX Byte 1 ==
7772 23:07:07.830648 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7773 23:07:07.833705 DramC Write-DBI off
7774 23:07:07.833786
7775 23:07:07.833849 [DATLAT]
7776 23:07:07.836536 Freq=1600, CH0 RK0
7777 23:07:07.836616
7778 23:07:07.836679 DATLAT Default: 0xf
7779 23:07:07.839909 0, 0xFFFF, sum = 0
7780 23:07:07.839983 1, 0xFFFF, sum = 0
7781 23:07:07.843221 2, 0xFFFF, sum = 0
7782 23:07:07.846398 3, 0xFFFF, sum = 0
7783 23:07:07.846488 4, 0xFFFF, sum = 0
7784 23:07:07.850063 5, 0xFFFF, sum = 0
7785 23:07:07.850149 6, 0xFFFF, sum = 0
7786 23:07:07.852987 7, 0xFFFF, sum = 0
7787 23:07:07.853055 8, 0xFFFF, sum = 0
7788 23:07:07.856170 9, 0xFFFF, sum = 0
7789 23:07:07.856253 10, 0xFFFF, sum = 0
7790 23:07:07.859581 11, 0xFFFF, sum = 0
7791 23:07:07.859712 12, 0xFFFF, sum = 0
7792 23:07:07.862874 13, 0xFFFF, sum = 0
7793 23:07:07.862949 14, 0x0, sum = 1
7794 23:07:07.866374 15, 0x0, sum = 2
7795 23:07:07.866448 16, 0x0, sum = 3
7796 23:07:07.869773 17, 0x0, sum = 4
7797 23:07:07.869847 best_step = 15
7798 23:07:07.869909
7799 23:07:07.869965 ==
7800 23:07:07.872800 Dram Type= 6, Freq= 0, CH_0, rank 0
7801 23:07:07.879235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7802 23:07:07.879336 ==
7803 23:07:07.879427 RX Vref Scan: 1
7804 23:07:07.879519
7805 23:07:07.882806 Set Vref Range= 24 -> 127
7806 23:07:07.882879
7807 23:07:07.886571 RX Vref 24 -> 127, step: 1
7808 23:07:07.886644
7809 23:07:07.886740 RX Delay 19 -> 252, step: 4
7810 23:07:07.889858
7811 23:07:07.889953 Set Vref, RX VrefLevel [Byte0]: 24
7812 23:07:07.892427 [Byte1]: 24
7813 23:07:07.896863
7814 23:07:07.896952 Set Vref, RX VrefLevel [Byte0]: 25
7815 23:07:07.900210 [Byte1]: 25
7816 23:07:07.904696
7817 23:07:07.904774 Set Vref, RX VrefLevel [Byte0]: 26
7818 23:07:07.907613 [Byte1]: 26
7819 23:07:07.912156
7820 23:07:07.912253 Set Vref, RX VrefLevel [Byte0]: 27
7821 23:07:07.915130 [Byte1]: 27
7822 23:07:07.919480
7823 23:07:07.919574 Set Vref, RX VrefLevel [Byte0]: 28
7824 23:07:07.922649 [Byte1]: 28
7825 23:07:07.927213
7826 23:07:07.927320 Set Vref, RX VrefLevel [Byte0]: 29
7827 23:07:07.930118 [Byte1]: 29
7828 23:07:07.934460
7829 23:07:07.934560 Set Vref, RX VrefLevel [Byte0]: 30
7830 23:07:07.937980 [Byte1]: 30
7831 23:07:07.942137
7832 23:07:07.942239 Set Vref, RX VrefLevel [Byte0]: 31
7833 23:07:07.946528 [Byte1]: 31
7834 23:07:07.949799
7835 23:07:07.952880 Set Vref, RX VrefLevel [Byte0]: 32
7836 23:07:07.956632 [Byte1]: 32
7837 23:07:07.956706
7838 23:07:07.959829 Set Vref, RX VrefLevel [Byte0]: 33
7839 23:07:07.963228 [Byte1]: 33
7840 23:07:07.963322
7841 23:07:07.966118 Set Vref, RX VrefLevel [Byte0]: 34
7842 23:07:07.969617 [Byte1]: 34
7843 23:07:07.969712
7844 23:07:07.972949 Set Vref, RX VrefLevel [Byte0]: 35
7845 23:07:07.975629 [Byte1]: 35
7846 23:07:07.980235
7847 23:07:07.980316 Set Vref, RX VrefLevel [Byte0]: 36
7848 23:07:07.983523 [Byte1]: 36
7849 23:07:07.987851
7850 23:07:07.987931 Set Vref, RX VrefLevel [Byte0]: 37
7851 23:07:07.990940 [Byte1]: 37
7852 23:07:07.995104
7853 23:07:07.995211 Set Vref, RX VrefLevel [Byte0]: 38
7854 23:07:07.998345 [Byte1]: 38
7855 23:07:08.002996
7856 23:07:08.003077 Set Vref, RX VrefLevel [Byte0]: 39
7857 23:07:08.006395 [Byte1]: 39
7858 23:07:08.010354
7859 23:07:08.010434 Set Vref, RX VrefLevel [Byte0]: 40
7860 23:07:08.013752 [Byte1]: 40
7861 23:07:08.018058
7862 23:07:08.018140 Set Vref, RX VrefLevel [Byte0]: 41
7863 23:07:08.021990 [Byte1]: 41
7864 23:07:08.026622
7865 23:07:08.026725 Set Vref, RX VrefLevel [Byte0]: 42
7866 23:07:08.028965 [Byte1]: 42
7867 23:07:08.033293
7868 23:07:08.033377 Set Vref, RX VrefLevel [Byte0]: 43
7869 23:07:08.036495 [Byte1]: 43
7870 23:07:08.040738
7871 23:07:08.040822 Set Vref, RX VrefLevel [Byte0]: 44
7872 23:07:08.043942 [Byte1]: 44
7873 23:07:08.047986
7874 23:07:08.048062 Set Vref, RX VrefLevel [Byte0]: 45
7875 23:07:08.051378 [Byte1]: 45
7876 23:07:08.055545
7877 23:07:08.055644 Set Vref, RX VrefLevel [Byte0]: 46
7878 23:07:08.058822 [Byte1]: 46
7879 23:07:08.063337
7880 23:07:08.063413 Set Vref, RX VrefLevel [Byte0]: 47
7881 23:07:08.066496 [Byte1]: 47
7882 23:07:08.070980
7883 23:07:08.071058 Set Vref, RX VrefLevel [Byte0]: 48
7884 23:07:08.074082 [Byte1]: 48
7885 23:07:08.078878
7886 23:07:08.078974 Set Vref, RX VrefLevel [Byte0]: 49
7887 23:07:08.081949 [Byte1]: 49
7888 23:07:08.086144
7889 23:07:08.086224 Set Vref, RX VrefLevel [Byte0]: 50
7890 23:07:08.089862 [Byte1]: 50
7891 23:07:08.093912
7892 23:07:08.093987 Set Vref, RX VrefLevel [Byte0]: 51
7893 23:07:08.096757 [Byte1]: 51
7894 23:07:08.101205
7895 23:07:08.101289 Set Vref, RX VrefLevel [Byte0]: 52
7896 23:07:08.104538 [Byte1]: 52
7897 23:07:08.108690
7898 23:07:08.108775 Set Vref, RX VrefLevel [Byte0]: 53
7899 23:07:08.112169 [Byte1]: 53
7900 23:07:08.116257
7901 23:07:08.116336 Set Vref, RX VrefLevel [Byte0]: 54
7902 23:07:08.119869 [Byte1]: 54
7903 23:07:08.124007
7904 23:07:08.124087 Set Vref, RX VrefLevel [Byte0]: 55
7905 23:07:08.127309 [Byte1]: 55
7906 23:07:08.131833
7907 23:07:08.131935 Set Vref, RX VrefLevel [Byte0]: 56
7908 23:07:08.135003 [Byte1]: 56
7909 23:07:08.139091
7910 23:07:08.139168 Set Vref, RX VrefLevel [Byte0]: 57
7911 23:07:08.142510 [Byte1]: 57
7912 23:07:08.147151
7913 23:07:08.147233 Set Vref, RX VrefLevel [Byte0]: 58
7914 23:07:08.150672 [Byte1]: 58
7915 23:07:08.154395
7916 23:07:08.154475 Set Vref, RX VrefLevel [Byte0]: 59
7917 23:07:08.157666 [Byte1]: 59
7918 23:07:08.161590
7919 23:07:08.161671 Set Vref, RX VrefLevel [Byte0]: 60
7920 23:07:08.165035 [Byte1]: 60
7921 23:07:08.170255
7922 23:07:08.170335 Set Vref, RX VrefLevel [Byte0]: 61
7923 23:07:08.172773 [Byte1]: 61
7924 23:07:08.176974
7925 23:07:08.177054 Set Vref, RX VrefLevel [Byte0]: 62
7926 23:07:08.180087 [Byte1]: 62
7927 23:07:08.184541
7928 23:07:08.184621 Set Vref, RX VrefLevel [Byte0]: 63
7929 23:07:08.188054 [Byte1]: 63
7930 23:07:08.192284
7931 23:07:08.192365 Set Vref, RX VrefLevel [Byte0]: 64
7932 23:07:08.195941 [Byte1]: 64
7933 23:07:08.199955
7934 23:07:08.200035 Set Vref, RX VrefLevel [Byte0]: 65
7935 23:07:08.203262 [Byte1]: 65
7936 23:07:08.207120
7937 23:07:08.207228 Set Vref, RX VrefLevel [Byte0]: 66
7938 23:07:08.210776 [Byte1]: 66
7939 23:07:08.214829
7940 23:07:08.214939 Set Vref, RX VrefLevel [Byte0]: 67
7941 23:07:08.218153 [Byte1]: 67
7942 23:07:08.222656
7943 23:07:08.222750 Set Vref, RX VrefLevel [Byte0]: 68
7944 23:07:08.225677 [Byte1]: 68
7945 23:07:08.230260
7946 23:07:08.230348 Set Vref, RX VrefLevel [Byte0]: 69
7947 23:07:08.233285 [Byte1]: 69
7948 23:07:08.237855
7949 23:07:08.237932 Set Vref, RX VrefLevel [Byte0]: 70
7950 23:07:08.240689 [Byte1]: 70
7951 23:07:08.245483
7952 23:07:08.245559 Set Vref, RX VrefLevel [Byte0]: 71
7953 23:07:08.248710 [Byte1]: 71
7954 23:07:08.252810
7955 23:07:08.252886 Set Vref, RX VrefLevel [Byte0]: 72
7956 23:07:08.256446 [Byte1]: 72
7957 23:07:08.260093
7958 23:07:08.260167 Set Vref, RX VrefLevel [Byte0]: 73
7959 23:07:08.263637 [Byte1]: 73
7960 23:07:08.267751
7961 23:07:08.267834 Set Vref, RX VrefLevel [Byte0]: 74
7962 23:07:08.271034 [Byte1]: 74
7963 23:07:08.275380
7964 23:07:08.275453 Set Vref, RX VrefLevel [Byte0]: 75
7965 23:07:08.278547 [Byte1]: 75
7966 23:07:08.283200
7967 23:07:08.283273 Set Vref, RX VrefLevel [Byte0]: 76
7968 23:07:08.286334 [Byte1]: 76
7969 23:07:08.290373
7970 23:07:08.290447 Set Vref, RX VrefLevel [Byte0]: 77
7971 23:07:08.293863 [Byte1]: 77
7972 23:07:08.298089
7973 23:07:08.298162 Set Vref, RX VrefLevel [Byte0]: 78
7974 23:07:08.301623 [Byte1]: 78
7975 23:07:08.305761
7976 23:07:08.305833 Set Vref, RX VrefLevel [Byte0]: 79
7977 23:07:08.308839 [Byte1]: 79
7978 23:07:08.313678
7979 23:07:08.313751 Set Vref, RX VrefLevel [Byte0]: 80
7980 23:07:08.316733 [Byte1]: 80
7981 23:07:08.320693
7982 23:07:08.320775 Final RX Vref Byte 0 = 62 to rank0
7983 23:07:08.324384 Final RX Vref Byte 1 = 58 to rank0
7984 23:07:08.327336 Final RX Vref Byte 0 = 62 to rank1
7985 23:07:08.331182 Final RX Vref Byte 1 = 58 to rank1==
7986 23:07:08.334139 Dram Type= 6, Freq= 0, CH_0, rank 0
7987 23:07:08.340903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7988 23:07:08.340988 ==
7989 23:07:08.341071 DQS Delay:
7990 23:07:08.341148 DQS0 = 0, DQS1 = 0
7991 23:07:08.343761 DQM Delay:
7992 23:07:08.343860 DQM0 = 132, DQM1 = 124
7993 23:07:08.347093 DQ Delay:
7994 23:07:08.350619 DQ0 =130, DQ1 =132, DQ2 =130, DQ3 =130
7995 23:07:08.354192 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =142
7996 23:07:08.357835 DQ8 =116, DQ9 =114, DQ10 =124, DQ11 =118
7997 23:07:08.360719 DQ12 =130, DQ13 =128, DQ14 =132, DQ15 =130
7998 23:07:08.360796
7999 23:07:08.360878
8000 23:07:08.360962
8001 23:07:08.363601 [DramC_TX_OE_Calibration] TA2
8002 23:07:08.367094 Original DQ_B0 (3 6) =30, OEN = 27
8003 23:07:08.370417 Original DQ_B1 (3 6) =30, OEN = 27
8004 23:07:08.374527 24, 0x0, End_B0=24 End_B1=24
8005 23:07:08.374636 25, 0x0, End_B0=25 End_B1=25
8006 23:07:08.378579 26, 0x0, End_B0=26 End_B1=26
8007 23:07:08.381018 27, 0x0, End_B0=27 End_B1=27
8008 23:07:08.383717 28, 0x0, End_B0=28 End_B1=28
8009 23:07:08.387464 29, 0x0, End_B0=29 End_B1=29
8010 23:07:08.387546 30, 0x0, End_B0=30 End_B1=30
8011 23:07:08.390982 31, 0x4141, End_B0=30 End_B1=30
8012 23:07:08.393681 Byte0 end_step=30 best_step=27
8013 23:07:08.396552 Byte1 end_step=30 best_step=27
8014 23:07:08.400010 Byte0 TX OE(2T, 0.5T) = (3, 3)
8015 23:07:08.404054 Byte1 TX OE(2T, 0.5T) = (3, 3)
8016 23:07:08.404136
8017 23:07:08.404201
8018 23:07:08.409848 [DQSOSCAuto] RK0, (LSB)MR18= 0x2213, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
8019 23:07:08.412984 CH0 RK0: MR19=303, MR18=2213
8020 23:07:08.419535 CH0_RK0: MR19=0x303, MR18=0x2213, DQSOSC=392, MR23=63, INC=24, DEC=16
8021 23:07:08.419654
8022 23:07:08.422809 ----->DramcWriteLeveling(PI) begin...
8023 23:07:08.422880 ==
8024 23:07:08.426611 Dram Type= 6, Freq= 0, CH_0, rank 1
8025 23:07:08.430286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8026 23:07:08.430362 ==
8027 23:07:08.432953 Write leveling (Byte 0): 35 => 35
8028 23:07:08.436695 Write leveling (Byte 1): 29 => 29
8029 23:07:08.439198 DramcWriteLeveling(PI) end<-----
8030 23:07:08.439287
8031 23:07:08.439351 ==
8032 23:07:08.442702 Dram Type= 6, Freq= 0, CH_0, rank 1
8033 23:07:08.449017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8034 23:07:08.449093 ==
8035 23:07:08.449155 [Gating] SW mode calibration
8036 23:07:08.459555 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8037 23:07:08.462830 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8038 23:07:08.466320 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 23:07:08.472946 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 23:07:08.476250 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 23:07:08.479245 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8042 23:07:08.485781 1 4 16 | B1->B0 | 2525 3433 | 0 1 | (0 0) (0 0)
8043 23:07:08.490070 1 4 20 | B1->B0 | 3332 3434 | 1 1 | (1 1) (1 1)
8044 23:07:08.493027 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 23:07:08.499259 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8046 23:07:08.502357 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 23:07:08.505674 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8048 23:07:08.512273 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8049 23:07:08.515350 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8050 23:07:08.518971 1 5 16 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 0)
8051 23:07:08.525560 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
8052 23:07:08.528682 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 23:07:08.531796 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 23:07:08.538543 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 23:07:08.541742 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 23:07:08.545055 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 23:07:08.551880 1 6 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
8058 23:07:08.554920 1 6 16 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8059 23:07:08.558514 1 6 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8060 23:07:08.564941 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8061 23:07:08.568295 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 23:07:08.572063 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 23:07:08.578311 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 23:07:08.581580 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8065 23:07:08.584955 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8066 23:07:08.591453 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8067 23:07:08.595143 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8068 23:07:08.598242 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 23:07:08.604668 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 23:07:08.607986 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 23:07:08.611160 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 23:07:08.618082 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 23:07:08.621891 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 23:07:08.624298 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 23:07:08.630840 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 23:07:08.634233 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 23:07:08.637397 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 23:07:08.644184 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 23:07:08.647461 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 23:07:08.651042 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 23:07:08.657335 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8082 23:07:08.660708 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8083 23:07:08.664051 Total UI for P1: 0, mck2ui 16
8084 23:07:08.667172 best dqsien dly found for B0: ( 1, 9, 12)
8085 23:07:08.670461 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8086 23:07:08.676849 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 23:07:08.676930 Total UI for P1: 0, mck2ui 16
8088 23:07:08.683770 best dqsien dly found for B1: ( 1, 9, 18)
8089 23:07:08.687087 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8090 23:07:08.690339 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8091 23:07:08.690417
8092 23:07:08.694001 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8093 23:07:08.696689 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8094 23:07:08.700450 [Gating] SW calibration Done
8095 23:07:08.700525 ==
8096 23:07:08.703428 Dram Type= 6, Freq= 0, CH_0, rank 1
8097 23:07:08.706619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8098 23:07:08.706690 ==
8099 23:07:08.710172 RX Vref Scan: 0
8100 23:07:08.710243
8101 23:07:08.710303 RX Vref 0 -> 0, step: 1
8102 23:07:08.713833
8103 23:07:08.713906 RX Delay 0 -> 252, step: 8
8104 23:07:08.719924 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8105 23:07:08.723500 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8106 23:07:08.727337 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8107 23:07:08.729802 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8108 23:07:08.733123 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8109 23:07:08.740514 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8110 23:07:08.742809 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8111 23:07:08.746192 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8112 23:07:08.749595 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8113 23:07:08.752909 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8114 23:07:08.759517 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8115 23:07:08.762794 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8116 23:07:08.766400 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8117 23:07:08.769554 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8118 23:07:08.772911 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8119 23:07:08.779581 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8120 23:07:08.779704 ==
8121 23:07:08.782570 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 23:07:08.785827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 23:07:08.785903 ==
8124 23:07:08.785969 DQS Delay:
8125 23:07:08.789541 DQS0 = 0, DQS1 = 0
8126 23:07:08.789620 DQM Delay:
8127 23:07:08.792588 DQM0 = 133, DQM1 = 128
8128 23:07:08.792658 DQ Delay:
8129 23:07:08.795762 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
8130 23:07:08.798981 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8131 23:07:08.802589 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8132 23:07:08.806060 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8133 23:07:08.809415
8134 23:07:08.809490
8135 23:07:08.809551 ==
8136 23:07:08.812777 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 23:07:08.815457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 23:07:08.815561 ==
8139 23:07:08.815653
8140 23:07:08.815758
8141 23:07:08.819043 TX Vref Scan disable
8142 23:07:08.819115 == TX Byte 0 ==
8143 23:07:08.825911 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8144 23:07:08.829241 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8145 23:07:08.829328 == TX Byte 1 ==
8146 23:07:08.836181 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8147 23:07:08.839514 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8148 23:07:08.839616 ==
8149 23:07:08.842457 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 23:07:08.845359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 23:07:08.845434 ==
8152 23:07:08.858648
8153 23:07:08.861631 TX Vref early break, caculate TX vref
8154 23:07:08.865040 TX Vref=16, minBit 3, minWin=22, winSum=380
8155 23:07:08.868671 TX Vref=18, minBit 1, minWin=23, winSum=393
8156 23:07:08.872398 TX Vref=20, minBit 1, minWin=23, winSum=398
8157 23:07:08.875513 TX Vref=22, minBit 2, minWin=23, winSum=405
8158 23:07:08.878478 TX Vref=24, minBit 3, minWin=23, winSum=413
8159 23:07:08.885063 TX Vref=26, minBit 4, minWin=24, winSum=416
8160 23:07:08.888427 TX Vref=28, minBit 1, minWin=24, winSum=421
8161 23:07:08.892041 TX Vref=30, minBit 1, minWin=23, winSum=406
8162 23:07:08.895293 TX Vref=32, minBit 0, minWin=24, winSum=397
8163 23:07:08.901769 [TxChooseVref] Worse bit 1, Min win 24, Win sum 421, Final Vref 28
8164 23:07:08.901852
8165 23:07:08.904722 Final TX Range 0 Vref 28
8166 23:07:08.904800
8167 23:07:08.904863 ==
8168 23:07:08.908097 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 23:07:08.911216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 23:07:08.911290 ==
8171 23:07:08.911355
8172 23:07:08.911414
8173 23:07:08.914833 TX Vref Scan disable
8174 23:07:08.921385 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8175 23:07:08.921473 == TX Byte 0 ==
8176 23:07:08.924714 u2DelayCellOfst[0]=15 cells (4 PI)
8177 23:07:08.927768 u2DelayCellOfst[1]=18 cells (5 PI)
8178 23:07:08.931058 u2DelayCellOfst[2]=15 cells (4 PI)
8179 23:07:08.934397 u2DelayCellOfst[3]=18 cells (5 PI)
8180 23:07:08.937724 u2DelayCellOfst[4]=11 cells (3 PI)
8181 23:07:08.941299 u2DelayCellOfst[5]=0 cells (0 PI)
8182 23:07:08.944677 u2DelayCellOfst[6]=22 cells (6 PI)
8183 23:07:08.947658 u2DelayCellOfst[7]=22 cells (6 PI)
8184 23:07:08.950855 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8185 23:07:08.954355 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8186 23:07:08.957452 == TX Byte 1 ==
8187 23:07:08.957540 u2DelayCellOfst[8]=0 cells (0 PI)
8188 23:07:08.960735 u2DelayCellOfst[9]=0 cells (0 PI)
8189 23:07:08.964507 u2DelayCellOfst[10]=7 cells (2 PI)
8190 23:07:08.967611 u2DelayCellOfst[11]=0 cells (0 PI)
8191 23:07:08.970885 u2DelayCellOfst[12]=11 cells (3 PI)
8192 23:07:08.974128 u2DelayCellOfst[13]=11 cells (3 PI)
8193 23:07:08.977451 u2DelayCellOfst[14]=15 cells (4 PI)
8194 23:07:08.980618 u2DelayCellOfst[15]=7 cells (2 PI)
8195 23:07:08.984456 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8196 23:07:08.990817 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8197 23:07:08.990917 DramC Write-DBI on
8198 23:07:08.990997 ==
8199 23:07:08.993931 Dram Type= 6, Freq= 0, CH_0, rank 1
8200 23:07:08.997498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8201 23:07:09.001000 ==
8202 23:07:09.001104
8203 23:07:09.001197
8204 23:07:09.001283 TX Vref Scan disable
8205 23:07:09.003994 == TX Byte 0 ==
8206 23:07:09.007608 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8207 23:07:09.010998 == TX Byte 1 ==
8208 23:07:09.014312 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8209 23:07:09.017779 DramC Write-DBI off
8210 23:07:09.017886
8211 23:07:09.017977 [DATLAT]
8212 23:07:09.018064 Freq=1600, CH0 RK1
8213 23:07:09.018155
8214 23:07:09.021149 DATLAT Default: 0xf
8215 23:07:09.024854 0, 0xFFFF, sum = 0
8216 23:07:09.024954 1, 0xFFFF, sum = 0
8217 23:07:09.027888 2, 0xFFFF, sum = 0
8218 23:07:09.027992 3, 0xFFFF, sum = 0
8219 23:07:09.030516 4, 0xFFFF, sum = 0
8220 23:07:09.030619 5, 0xFFFF, sum = 0
8221 23:07:09.034315 6, 0xFFFF, sum = 0
8222 23:07:09.034392 7, 0xFFFF, sum = 0
8223 23:07:09.037427 8, 0xFFFF, sum = 0
8224 23:07:09.037501 9, 0xFFFF, sum = 0
8225 23:07:09.040308 10, 0xFFFF, sum = 0
8226 23:07:09.040384 11, 0xFFFF, sum = 0
8227 23:07:09.043638 12, 0xFFFF, sum = 0
8228 23:07:09.043765 13, 0xFFFF, sum = 0
8229 23:07:09.046941 14, 0x0, sum = 1
8230 23:07:09.047015 15, 0x0, sum = 2
8231 23:07:09.050308 16, 0x0, sum = 3
8232 23:07:09.050420 17, 0x0, sum = 4
8233 23:07:09.053348 best_step = 15
8234 23:07:09.053423
8235 23:07:09.053486 ==
8236 23:07:09.056794 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 23:07:09.060420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 23:07:09.060496 ==
8239 23:07:09.063396 RX Vref Scan: 0
8240 23:07:09.063469
8241 23:07:09.063528 RX Vref 0 -> 0, step: 1
8242 23:07:09.063584
8243 23:07:09.067271 RX Delay 11 -> 252, step: 4
8244 23:07:09.073264 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8245 23:07:09.077127 iDelay=195, Bit 1, Center 134 (83 ~ 186) 104
8246 23:07:09.080136 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8247 23:07:09.082913 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8248 23:07:09.086447 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8249 23:07:09.092841 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8250 23:07:09.096390 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8251 23:07:09.100505 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8252 23:07:09.102985 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8253 23:07:09.106207 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8254 23:07:09.113006 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8255 23:07:09.115904 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8256 23:07:09.119625 iDelay=195, Bit 12, Center 130 (75 ~ 186) 112
8257 23:07:09.122823 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8258 23:07:09.129492 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8259 23:07:09.132568 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8260 23:07:09.132642 ==
8261 23:07:09.136763 Dram Type= 6, Freq= 0, CH_0, rank 1
8262 23:07:09.139565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 23:07:09.139663 ==
8264 23:07:09.142707 DQS Delay:
8265 23:07:09.142775 DQS0 = 0, DQS1 = 0
8266 23:07:09.142835 DQM Delay:
8267 23:07:09.146031 DQM0 = 130, DQM1 = 125
8268 23:07:09.146111 DQ Delay:
8269 23:07:09.149043 DQ0 =128, DQ1 =134, DQ2 =126, DQ3 =128
8270 23:07:09.152386 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8271 23:07:09.155830 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8272 23:07:09.162585 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8273 23:07:09.162663
8274 23:07:09.162724
8275 23:07:09.162780
8276 23:07:09.167037 [DramC_TX_OE_Calibration] TA2
8277 23:07:09.169580 Original DQ_B0 (3 6) =30, OEN = 27
8278 23:07:09.169657 Original DQ_B1 (3 6) =30, OEN = 27
8279 23:07:09.172497 24, 0x0, End_B0=24 End_B1=24
8280 23:07:09.175531 25, 0x0, End_B0=25 End_B1=25
8281 23:07:09.178770 26, 0x0, End_B0=26 End_B1=26
8282 23:07:09.182911 27, 0x0, End_B0=27 End_B1=27
8283 23:07:09.182997 28, 0x0, End_B0=28 End_B1=28
8284 23:07:09.185930 29, 0x0, End_B0=29 End_B1=29
8285 23:07:09.188687 30, 0x0, End_B0=30 End_B1=30
8286 23:07:09.192252 31, 0x4545, End_B0=30 End_B1=30
8287 23:07:09.195145 Byte0 end_step=30 best_step=27
8288 23:07:09.198861 Byte1 end_step=30 best_step=27
8289 23:07:09.198934 Byte0 TX OE(2T, 0.5T) = (3, 3)
8290 23:07:09.201796 Byte1 TX OE(2T, 0.5T) = (3, 3)
8291 23:07:09.201870
8292 23:07:09.201933
8293 23:07:09.212063 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e01, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8294 23:07:09.215438 CH0 RK1: MR19=303, MR18=1E01
8295 23:07:09.218332 CH0_RK1: MR19=0x303, MR18=0x1E01, DQSOSC=394, MR23=63, INC=23, DEC=15
8296 23:07:09.221510 [RxdqsGatingPostProcess] freq 1600
8297 23:07:09.228713 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8298 23:07:09.231604 best DQS0 dly(2T, 0.5T) = (1, 1)
8299 23:07:09.235105 best DQS1 dly(2T, 0.5T) = (1, 1)
8300 23:07:09.238194 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8301 23:07:09.241555 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8302 23:07:09.244953 best DQS0 dly(2T, 0.5T) = (1, 1)
8303 23:07:09.248305 best DQS1 dly(2T, 0.5T) = (1, 1)
8304 23:07:09.251502 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8305 23:07:09.251582 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8306 23:07:09.254841 Pre-setting of DQS Precalculation
8307 23:07:09.261481 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8308 23:07:09.261562 ==
8309 23:07:09.264585 Dram Type= 6, Freq= 0, CH_1, rank 0
8310 23:07:09.267920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 23:07:09.268002 ==
8312 23:07:09.274402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8313 23:07:09.277865 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8314 23:07:09.281249 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8315 23:07:09.287879 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8316 23:07:09.297402 [CA 0] Center 42 (13~72) winsize 60
8317 23:07:09.300773 [CA 1] Center 43 (14~72) winsize 59
8318 23:07:09.304362 [CA 2] Center 37 (9~66) winsize 58
8319 23:07:09.307691 [CA 3] Center 37 (8~66) winsize 59
8320 23:07:09.310549 [CA 4] Center 38 (8~68) winsize 61
8321 23:07:09.314078 [CA 5] Center 37 (8~67) winsize 60
8322 23:07:09.314149
8323 23:07:09.317197 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8324 23:07:09.317268
8325 23:07:09.323928 [CATrainingPosCal] consider 1 rank data
8326 23:07:09.324007 u2DelayCellTimex100 = 258/100 ps
8327 23:07:09.330255 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8328 23:07:09.333735 CA1 delay=43 (14~72),Diff = 6 PI (22 cell)
8329 23:07:09.337253 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8330 23:07:09.340469 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8331 23:07:09.343464 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8332 23:07:09.347001 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8333 23:07:09.347076
8334 23:07:09.350219 CA PerBit enable=1, Macro0, CA PI delay=37
8335 23:07:09.350287
8336 23:07:09.353493 [CBTSetCACLKResult] CA Dly = 37
8337 23:07:09.356825 CS Dly: 9 (0~40)
8338 23:07:09.359933 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8339 23:07:09.363229 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8340 23:07:09.363299 ==
8341 23:07:09.366510 Dram Type= 6, Freq= 0, CH_1, rank 1
8342 23:07:09.373325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 23:07:09.373396 ==
8344 23:07:09.376494 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8345 23:07:09.382933 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8346 23:07:09.386712 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8347 23:07:09.392887 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8348 23:07:09.401122 [CA 0] Center 42 (13~72) winsize 60
8349 23:07:09.403795 [CA 1] Center 42 (13~72) winsize 60
8350 23:07:09.407362 [CA 2] Center 38 (9~67) winsize 59
8351 23:07:09.410373 [CA 3] Center 37 (8~67) winsize 60
8352 23:07:09.414027 [CA 4] Center 37 (8~67) winsize 60
8353 23:07:09.417603 [CA 5] Center 37 (8~67) winsize 60
8354 23:07:09.417678
8355 23:07:09.420562 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8356 23:07:09.420696
8357 23:07:09.423410 [CATrainingPosCal] consider 2 rank data
8358 23:07:09.427127 u2DelayCellTimex100 = 258/100 ps
8359 23:07:09.433520 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8360 23:07:09.436841 CA1 delay=43 (14~72),Diff = 6 PI (22 cell)
8361 23:07:09.440050 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8362 23:07:09.443362 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8363 23:07:09.446445 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8364 23:07:09.450022 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8365 23:07:09.450096
8366 23:07:09.453117 CA PerBit enable=1, Macro0, CA PI delay=37
8367 23:07:09.453198
8368 23:07:09.456420 [CBTSetCACLKResult] CA Dly = 37
8369 23:07:09.460019 CS Dly: 10 (0~43)
8370 23:07:09.463584 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8371 23:07:09.466423 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8372 23:07:09.466497
8373 23:07:09.469455 ----->DramcWriteLeveling(PI) begin...
8374 23:07:09.469530 ==
8375 23:07:09.473200 Dram Type= 6, Freq= 0, CH_1, rank 0
8376 23:07:09.479494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 23:07:09.479567 ==
8378 23:07:09.482849 Write leveling (Byte 0): 24 => 24
8379 23:07:09.486327 Write leveling (Byte 1): 27 => 27
8380 23:07:09.486396 DramcWriteLeveling(PI) end<-----
8381 23:07:09.486468
8382 23:07:09.490238 ==
8383 23:07:09.493189 Dram Type= 6, Freq= 0, CH_1, rank 0
8384 23:07:09.496440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8385 23:07:09.496516 ==
8386 23:07:09.499826 [Gating] SW mode calibration
8387 23:07:09.506140 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8388 23:07:09.509633 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8389 23:07:09.516261 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 23:07:09.519933 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 23:07:09.522673 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 23:07:09.529269 1 4 12 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 0)
8393 23:07:09.532956 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 23:07:09.536055 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 23:07:09.542423 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 23:07:09.545771 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 23:07:09.549126 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 23:07:09.556090 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 23:07:09.559017 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8400 23:07:09.562539 1 5 12 | B1->B0 | 3434 2b2b | 0 0 | (0 1) (1 0)
8401 23:07:09.568637 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8402 23:07:09.572381 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 23:07:09.575819 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 23:07:09.582144 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 23:07:09.585172 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 23:07:09.589691 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 23:07:09.595378 1 6 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
8408 23:07:09.598629 1 6 12 | B1->B0 | 4444 4343 | 1 0 | (0 0) (0 0)
8409 23:07:09.602276 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 23:07:09.608229 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 23:07:09.611416 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 23:07:09.614939 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 23:07:09.621815 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 23:07:09.624993 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 23:07:09.628077 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8416 23:07:09.635163 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8417 23:07:09.638279 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8418 23:07:09.641008 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 23:07:09.647629 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 23:07:09.651022 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 23:07:09.654879 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 23:07:09.661414 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 23:07:09.664232 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 23:07:09.668341 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 23:07:09.674404 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 23:07:09.677643 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 23:07:09.680553 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 23:07:09.687296 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 23:07:09.690617 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 23:07:09.693718 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 23:07:09.700412 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8432 23:07:09.703943 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8433 23:07:09.707284 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 23:07:09.710138 Total UI for P1: 0, mck2ui 16
8435 23:07:09.714451 best dqsien dly found for B0: ( 1, 9, 10)
8436 23:07:09.717338 Total UI for P1: 0, mck2ui 16
8437 23:07:09.720382 best dqsien dly found for B1: ( 1, 9, 12)
8438 23:07:09.724222 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8439 23:07:09.727302 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8440 23:07:09.730260
8441 23:07:09.733475 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8442 23:07:09.736943 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8443 23:07:09.740281 [Gating] SW calibration Done
8444 23:07:09.740361 ==
8445 23:07:09.743690 Dram Type= 6, Freq= 0, CH_1, rank 0
8446 23:07:09.746686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8447 23:07:09.746782 ==
8448 23:07:09.750590 RX Vref Scan: 0
8449 23:07:09.750690
8450 23:07:09.750791 RX Vref 0 -> 0, step: 1
8451 23:07:09.750884
8452 23:07:09.753612 RX Delay 0 -> 252, step: 8
8453 23:07:09.756575 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8454 23:07:09.760039 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8455 23:07:09.767008 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8456 23:07:09.769915 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8457 23:07:09.773512 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8458 23:07:09.776871 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8459 23:07:09.780323 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8460 23:07:09.786743 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8461 23:07:09.789707 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8462 23:07:09.793539 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8463 23:07:09.796094 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8464 23:07:09.802735 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8465 23:07:09.806783 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8466 23:07:09.809994 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8467 23:07:09.813152 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8468 23:07:09.816663 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8469 23:07:09.819576 ==
8470 23:07:09.819654 Dram Type= 6, Freq= 0, CH_1, rank 0
8471 23:07:09.825992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8472 23:07:09.826070 ==
8473 23:07:09.826133 DQS Delay:
8474 23:07:09.829306 DQS0 = 0, DQS1 = 0
8475 23:07:09.829387 DQM Delay:
8476 23:07:09.832523 DQM0 = 137, DQM1 = 129
8477 23:07:09.832608 DQ Delay:
8478 23:07:09.836227 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =135
8479 23:07:09.839305 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8480 23:07:09.843003 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8481 23:07:09.846195 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =139
8482 23:07:09.846266
8483 23:07:09.846326
8484 23:07:09.846388 ==
8485 23:07:09.848981 Dram Type= 6, Freq= 0, CH_1, rank 0
8486 23:07:09.855425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8487 23:07:09.855508 ==
8488 23:07:09.855570
8489 23:07:09.855628
8490 23:07:09.855727 TX Vref Scan disable
8491 23:07:09.859271 == TX Byte 0 ==
8492 23:07:09.862888 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8493 23:07:09.869041 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8494 23:07:09.869114 == TX Byte 1 ==
8495 23:07:09.872271 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8496 23:07:09.879523 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8497 23:07:09.879596 ==
8498 23:07:09.882507 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 23:07:09.886048 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 23:07:09.886118 ==
8501 23:07:09.897426
8502 23:07:09.900947 TX Vref early break, caculate TX vref
8503 23:07:09.903981 TX Vref=16, minBit 0, minWin=22, winSum=376
8504 23:07:09.907048 TX Vref=18, minBit 0, minWin=22, winSum=381
8505 23:07:09.910400 TX Vref=20, minBit 0, minWin=23, winSum=392
8506 23:07:09.913379 TX Vref=22, minBit 0, minWin=23, winSum=402
8507 23:07:09.916974 TX Vref=24, minBit 0, minWin=24, winSum=412
8508 23:07:09.923341 TX Vref=26, minBit 0, minWin=24, winSum=418
8509 23:07:09.927176 TX Vref=28, minBit 1, minWin=24, winSum=423
8510 23:07:09.930235 TX Vref=30, minBit 0, minWin=24, winSum=412
8511 23:07:09.933808 TX Vref=32, minBit 1, minWin=23, winSum=399
8512 23:07:09.940158 [TxChooseVref] Worse bit 1, Min win 24, Win sum 423, Final Vref 28
8513 23:07:09.940234
8514 23:07:09.943630 Final TX Range 0 Vref 28
8515 23:07:09.943733
8516 23:07:09.943796 ==
8517 23:07:09.946391 Dram Type= 6, Freq= 0, CH_1, rank 0
8518 23:07:09.949961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8519 23:07:09.950031 ==
8520 23:07:09.950104
8521 23:07:09.950163
8522 23:07:09.953451 TX Vref Scan disable
8523 23:07:09.959453 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8524 23:07:09.959534 == TX Byte 0 ==
8525 23:07:09.963176 u2DelayCellOfst[0]=18 cells (5 PI)
8526 23:07:09.966383 u2DelayCellOfst[1]=11 cells (3 PI)
8527 23:07:09.969686 u2DelayCellOfst[2]=0 cells (0 PI)
8528 23:07:09.973139 u2DelayCellOfst[3]=3 cells (1 PI)
8529 23:07:09.976563 u2DelayCellOfst[4]=7 cells (2 PI)
8530 23:07:09.979638 u2DelayCellOfst[5]=22 cells (6 PI)
8531 23:07:09.982790 u2DelayCellOfst[6]=22 cells (6 PI)
8532 23:07:09.982900 u2DelayCellOfst[7]=7 cells (2 PI)
8533 23:07:09.989307 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8534 23:07:09.992969 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8535 23:07:09.995820 == TX Byte 1 ==
8536 23:07:09.995896 u2DelayCellOfst[8]=0 cells (0 PI)
8537 23:07:09.999556 u2DelayCellOfst[9]=3 cells (1 PI)
8538 23:07:10.002801 u2DelayCellOfst[10]=11 cells (3 PI)
8539 23:07:10.006012 u2DelayCellOfst[11]=7 cells (2 PI)
8540 23:07:10.009646 u2DelayCellOfst[12]=18 cells (5 PI)
8541 23:07:10.012453 u2DelayCellOfst[13]=15 cells (4 PI)
8542 23:07:10.015871 u2DelayCellOfst[14]=18 cells (5 PI)
8543 23:07:10.018916 u2DelayCellOfst[15]=18 cells (5 PI)
8544 23:07:10.022552 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8545 23:07:10.029008 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8546 23:07:10.029114 DramC Write-DBI on
8547 23:07:10.029200 ==
8548 23:07:10.032537 Dram Type= 6, Freq= 0, CH_1, rank 0
8549 23:07:10.039108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8550 23:07:10.039220 ==
8551 23:07:10.039312
8552 23:07:10.039399
8553 23:07:10.039490 TX Vref Scan disable
8554 23:07:10.042652 == TX Byte 0 ==
8555 23:07:10.046241 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8556 23:07:10.049413 == TX Byte 1 ==
8557 23:07:10.052139 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8558 23:07:10.055516 DramC Write-DBI off
8559 23:07:10.055617
8560 23:07:10.055745 [DATLAT]
8561 23:07:10.055807 Freq=1600, CH1 RK0
8562 23:07:10.055863
8563 23:07:10.059290 DATLAT Default: 0xf
8564 23:07:10.062400 0, 0xFFFF, sum = 0
8565 23:07:10.062475 1, 0xFFFF, sum = 0
8566 23:07:10.065502 2, 0xFFFF, sum = 0
8567 23:07:10.065576 3, 0xFFFF, sum = 0
8568 23:07:10.069221 4, 0xFFFF, sum = 0
8569 23:07:10.069318 5, 0xFFFF, sum = 0
8570 23:07:10.072518 6, 0xFFFF, sum = 0
8571 23:07:10.072620 7, 0xFFFF, sum = 0
8572 23:07:10.075645 8, 0xFFFF, sum = 0
8573 23:07:10.075768 9, 0xFFFF, sum = 0
8574 23:07:10.078724 10, 0xFFFF, sum = 0
8575 23:07:10.078798 11, 0xFFFF, sum = 0
8576 23:07:10.081924 12, 0xFFFF, sum = 0
8577 23:07:10.082023 13, 0xFFFF, sum = 0
8578 23:07:10.085299 14, 0x0, sum = 1
8579 23:07:10.085382 15, 0x0, sum = 2
8580 23:07:10.088403 16, 0x0, sum = 3
8581 23:07:10.088484 17, 0x0, sum = 4
8582 23:07:10.092006 best_step = 15
8583 23:07:10.092088
8584 23:07:10.092169 ==
8585 23:07:10.095209 Dram Type= 6, Freq= 0, CH_1, rank 0
8586 23:07:10.098956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8587 23:07:10.099033 ==
8588 23:07:10.101967 RX Vref Scan: 1
8589 23:07:10.102048
8590 23:07:10.102111 Set Vref Range= 24 -> 127
8591 23:07:10.102171
8592 23:07:10.105081 RX Vref 24 -> 127, step: 1
8593 23:07:10.105150
8594 23:07:10.108307 RX Delay 11 -> 252, step: 4
8595 23:07:10.108373
8596 23:07:10.111629 Set Vref, RX VrefLevel [Byte0]: 24
8597 23:07:10.114803 [Byte1]: 24
8598 23:07:10.114869
8599 23:07:10.118221 Set Vref, RX VrefLevel [Byte0]: 25
8600 23:07:10.121485 [Byte1]: 25
8601 23:07:10.125914
8602 23:07:10.126000 Set Vref, RX VrefLevel [Byte0]: 26
8603 23:07:10.128757 [Byte1]: 26
8604 23:07:10.132809
8605 23:07:10.132887 Set Vref, RX VrefLevel [Byte0]: 27
8606 23:07:10.136315 [Byte1]: 27
8607 23:07:10.140480
8608 23:07:10.140548 Set Vref, RX VrefLevel [Byte0]: 28
8609 23:07:10.143858 [Byte1]: 28
8610 23:07:10.147920
8611 23:07:10.147994 Set Vref, RX VrefLevel [Byte0]: 29
8612 23:07:10.151248 [Byte1]: 29
8613 23:07:10.156495
8614 23:07:10.156565 Set Vref, RX VrefLevel [Byte0]: 30
8615 23:07:10.158739 [Byte1]: 30
8616 23:07:10.163458
8617 23:07:10.163526 Set Vref, RX VrefLevel [Byte0]: 31
8618 23:07:10.166381 [Byte1]: 31
8619 23:07:10.171034
8620 23:07:10.171101 Set Vref, RX VrefLevel [Byte0]: 32
8621 23:07:10.174152 [Byte1]: 32
8622 23:07:10.178287
8623 23:07:10.178355 Set Vref, RX VrefLevel [Byte0]: 33
8624 23:07:10.182462 [Byte1]: 33
8625 23:07:10.186150
8626 23:07:10.186238 Set Vref, RX VrefLevel [Byte0]: 34
8627 23:07:10.189548 [Byte1]: 34
8628 23:07:10.194072
8629 23:07:10.194169 Set Vref, RX VrefLevel [Byte0]: 35
8630 23:07:10.196971 [Byte1]: 35
8631 23:07:10.201292
8632 23:07:10.201387 Set Vref, RX VrefLevel [Byte0]: 36
8633 23:07:10.205008 [Byte1]: 36
8634 23:07:10.209185
8635 23:07:10.209284 Set Vref, RX VrefLevel [Byte0]: 37
8636 23:07:10.212495 [Byte1]: 37
8637 23:07:10.216500
8638 23:07:10.216576 Set Vref, RX VrefLevel [Byte0]: 38
8639 23:07:10.219844 [Byte1]: 38
8640 23:07:10.224246
8641 23:07:10.224328 Set Vref, RX VrefLevel [Byte0]: 39
8642 23:07:10.227633 [Byte1]: 39
8643 23:07:10.231980
8644 23:07:10.232053 Set Vref, RX VrefLevel [Byte0]: 40
8645 23:07:10.235527 [Byte1]: 40
8646 23:07:10.239764
8647 23:07:10.239868 Set Vref, RX VrefLevel [Byte0]: 41
8648 23:07:10.243529 [Byte1]: 41
8649 23:07:10.246943
8650 23:07:10.247022 Set Vref, RX VrefLevel [Byte0]: 42
8651 23:07:10.250338 [Byte1]: 42
8652 23:07:10.254815
8653 23:07:10.254898 Set Vref, RX VrefLevel [Byte0]: 43
8654 23:07:10.258052 [Byte1]: 43
8655 23:07:10.262078
8656 23:07:10.262154 Set Vref, RX VrefLevel [Byte0]: 44
8657 23:07:10.265556 [Byte1]: 44
8658 23:07:10.269881
8659 23:07:10.269964 Set Vref, RX VrefLevel [Byte0]: 45
8660 23:07:10.273780 [Byte1]: 45
8661 23:07:10.277684
8662 23:07:10.277763 Set Vref, RX VrefLevel [Byte0]: 46
8663 23:07:10.281183 [Byte1]: 46
8664 23:07:10.285720
8665 23:07:10.285800 Set Vref, RX VrefLevel [Byte0]: 47
8666 23:07:10.288362 [Byte1]: 47
8667 23:07:10.292746
8668 23:07:10.292822 Set Vref, RX VrefLevel [Byte0]: 48
8669 23:07:10.296023 [Byte1]: 48
8670 23:07:10.300237
8671 23:07:10.300312 Set Vref, RX VrefLevel [Byte0]: 49
8672 23:07:10.303620 [Byte1]: 49
8673 23:07:10.307906
8674 23:07:10.307980 Set Vref, RX VrefLevel [Byte0]: 50
8675 23:07:10.311397 [Byte1]: 50
8676 23:07:10.315332
8677 23:07:10.315407 Set Vref, RX VrefLevel [Byte0]: 51
8678 23:07:10.319207 [Byte1]: 51
8679 23:07:10.322921
8680 23:07:10.322998 Set Vref, RX VrefLevel [Byte0]: 52
8681 23:07:10.326497 [Byte1]: 52
8682 23:07:10.330854
8683 23:07:10.330933 Set Vref, RX VrefLevel [Byte0]: 53
8684 23:07:10.334251 [Byte1]: 53
8685 23:07:10.338708
8686 23:07:10.338789 Set Vref, RX VrefLevel [Byte0]: 54
8687 23:07:10.341803 [Byte1]: 54
8688 23:07:10.345860
8689 23:07:10.345940 Set Vref, RX VrefLevel [Byte0]: 55
8690 23:07:10.349252 [Byte1]: 55
8691 23:07:10.353579
8692 23:07:10.353653 Set Vref, RX VrefLevel [Byte0]: 56
8693 23:07:10.357631 [Byte1]: 56
8694 23:07:10.361642
8695 23:07:10.361721 Set Vref, RX VrefLevel [Byte0]: 57
8696 23:07:10.364581 [Byte1]: 57
8697 23:07:10.368728
8698 23:07:10.368804 Set Vref, RX VrefLevel [Byte0]: 58
8699 23:07:10.372580 [Byte1]: 58
8700 23:07:10.376227
8701 23:07:10.376312 Set Vref, RX VrefLevel [Byte0]: 59
8702 23:07:10.379566 [Byte1]: 59
8703 23:07:10.384434
8704 23:07:10.384515 Set Vref, RX VrefLevel [Byte0]: 60
8705 23:07:10.387232 [Byte1]: 60
8706 23:07:10.391477
8707 23:07:10.391553 Set Vref, RX VrefLevel [Byte0]: 61
8708 23:07:10.395126 [Byte1]: 61
8709 23:07:10.399129
8710 23:07:10.399209 Set Vref, RX VrefLevel [Byte0]: 62
8711 23:07:10.402720 [Byte1]: 62
8712 23:07:10.406908
8713 23:07:10.406989 Set Vref, RX VrefLevel [Byte0]: 63
8714 23:07:10.410047 [Byte1]: 63
8715 23:07:10.414696
8716 23:07:10.414772 Set Vref, RX VrefLevel [Byte0]: 64
8717 23:07:10.418020 [Byte1]: 64
8718 23:07:10.422125
8719 23:07:10.422207 Set Vref, RX VrefLevel [Byte0]: 65
8720 23:07:10.425531 [Byte1]: 65
8721 23:07:10.429735
8722 23:07:10.429840 Set Vref, RX VrefLevel [Byte0]: 66
8723 23:07:10.433175 [Byte1]: 66
8724 23:07:10.437709
8725 23:07:10.437855 Set Vref, RX VrefLevel [Byte0]: 67
8726 23:07:10.441007 [Byte1]: 67
8727 23:07:10.445068
8728 23:07:10.445155 Set Vref, RX VrefLevel [Byte0]: 68
8729 23:07:10.448316 [Byte1]: 68
8730 23:07:10.452848
8731 23:07:10.452928 Set Vref, RX VrefLevel [Byte0]: 69
8732 23:07:10.456118 [Byte1]: 69
8733 23:07:10.460359
8734 23:07:10.460440 Set Vref, RX VrefLevel [Byte0]: 70
8735 23:07:10.463291 [Byte1]: 70
8736 23:07:10.468362
8737 23:07:10.468443 Set Vref, RX VrefLevel [Byte0]: 71
8738 23:07:10.471553 [Byte1]: 71
8739 23:07:10.475234
8740 23:07:10.475314 Set Vref, RX VrefLevel [Byte0]: 72
8741 23:07:10.478823 [Byte1]: 72
8742 23:07:10.483061
8743 23:07:10.483141 Final RX Vref Byte 0 = 52 to rank0
8744 23:07:10.486873 Final RX Vref Byte 1 = 59 to rank0
8745 23:07:10.489497 Final RX Vref Byte 0 = 52 to rank1
8746 23:07:10.492987 Final RX Vref Byte 1 = 59 to rank1==
8747 23:07:10.496472 Dram Type= 6, Freq= 0, CH_1, rank 0
8748 23:07:10.502514 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8749 23:07:10.502624 ==
8750 23:07:10.502723 DQS Delay:
8751 23:07:10.505998 DQS0 = 0, DQS1 = 0
8752 23:07:10.506138 DQM Delay:
8753 23:07:10.509675 DQM0 = 133, DQM1 = 128
8754 23:07:10.509750 DQ Delay:
8755 23:07:10.513208 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =130
8756 23:07:10.516101 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =128
8757 23:07:10.518927 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =118
8758 23:07:10.522880 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8759 23:07:10.522962
8760 23:07:10.523025
8761 23:07:10.523084
8762 23:07:10.525832 [DramC_TX_OE_Calibration] TA2
8763 23:07:10.529127 Original DQ_B0 (3 6) =30, OEN = 27
8764 23:07:10.532230 Original DQ_B1 (3 6) =30, OEN = 27
8765 23:07:10.535785 24, 0x0, End_B0=24 End_B1=24
8766 23:07:10.539027 25, 0x0, End_B0=25 End_B1=25
8767 23:07:10.539109 26, 0x0, End_B0=26 End_B1=26
8768 23:07:10.542620 27, 0x0, End_B0=27 End_B1=27
8769 23:07:10.545675 28, 0x0, End_B0=28 End_B1=28
8770 23:07:10.549332 29, 0x0, End_B0=29 End_B1=29
8771 23:07:10.549415 30, 0x0, End_B0=30 End_B1=30
8772 23:07:10.552066 31, 0x4141, End_B0=30 End_B1=30
8773 23:07:10.555382 Byte0 end_step=30 best_step=27
8774 23:07:10.559213 Byte1 end_step=30 best_step=27
8775 23:07:10.561824 Byte0 TX OE(2T, 0.5T) = (3, 3)
8776 23:07:10.565628 Byte1 TX OE(2T, 0.5T) = (3, 3)
8777 23:07:10.565709
8778 23:07:10.565773
8779 23:07:10.571623 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
8780 23:07:10.574897 CH1 RK0: MR19=303, MR18=1A10
8781 23:07:10.581830 CH1_RK0: MR19=0x303, MR18=0x1A10, DQSOSC=396, MR23=63, INC=23, DEC=15
8782 23:07:10.581909
8783 23:07:10.585148 ----->DramcWriteLeveling(PI) begin...
8784 23:07:10.585229 ==
8785 23:07:10.588541 Dram Type= 6, Freq= 0, CH_1, rank 1
8786 23:07:10.592270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8787 23:07:10.592345 ==
8788 23:07:10.594738 Write leveling (Byte 0): 24 => 24
8789 23:07:10.598169 Write leveling (Byte 1): 25 => 25
8790 23:07:10.601574 DramcWriteLeveling(PI) end<-----
8791 23:07:10.601648
8792 23:07:10.601709 ==
8793 23:07:10.605323 Dram Type= 6, Freq= 0, CH_1, rank 1
8794 23:07:10.608095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8795 23:07:10.611663 ==
8796 23:07:10.611783 [Gating] SW mode calibration
8797 23:07:10.621197 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8798 23:07:10.624698 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8799 23:07:10.627952 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 23:07:10.634507 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 23:07:10.638572 1 4 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8802 23:07:10.641168 1 4 12 | B1->B0 | 3232 2323 | 0 0 | (1 1) (0 0)
8803 23:07:10.647929 1 4 16 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
8804 23:07:10.651197 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8805 23:07:10.654709 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8806 23:07:10.662175 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8807 23:07:10.664288 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8808 23:07:10.667812 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8809 23:07:10.674097 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8810 23:07:10.677491 1 5 12 | B1->B0 | 2626 3434 | 0 1 | (1 0) (1 0)
8811 23:07:10.680536 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8812 23:07:10.687549 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 23:07:10.690962 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 23:07:10.694019 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8815 23:07:10.700386 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8816 23:07:10.703635 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8817 23:07:10.707287 1 6 8 | B1->B0 | 3737 2323 | 0 0 | (0 0) (0 0)
8818 23:07:10.714267 1 6 12 | B1->B0 | 4545 2a2a | 0 0 | (0 0) (0 0)
8819 23:07:10.717381 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 23:07:10.720716 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 23:07:10.726937 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8822 23:07:10.730000 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8823 23:07:10.733658 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8824 23:07:10.740269 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 23:07:10.743288 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8826 23:07:10.746672 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8827 23:07:10.753251 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8828 23:07:10.756711 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 23:07:10.760188 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 23:07:10.766376 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 23:07:10.769542 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 23:07:10.772926 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 23:07:10.779808 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 23:07:10.782833 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 23:07:10.786126 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 23:07:10.792861 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 23:07:10.796574 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 23:07:10.799924 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 23:07:10.805871 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 23:07:10.809578 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 23:07:10.812615 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8842 23:07:10.819694 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8843 23:07:10.823043 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8844 23:07:10.825801 Total UI for P1: 0, mck2ui 16
8845 23:07:10.828989 best dqsien dly found for B0: ( 1, 9, 10)
8846 23:07:10.832899 Total UI for P1: 0, mck2ui 16
8847 23:07:10.835827 best dqsien dly found for B1: ( 1, 9, 10)
8848 23:07:10.839079 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8849 23:07:10.842480 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8850 23:07:10.842554
8851 23:07:10.845912 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8852 23:07:10.852357 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8853 23:07:10.852437 [Gating] SW calibration Done
8854 23:07:10.852500 ==
8855 23:07:10.855705 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 23:07:10.862243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 23:07:10.862318 ==
8858 23:07:10.862380 RX Vref Scan: 0
8859 23:07:10.862438
8860 23:07:10.865195 RX Vref 0 -> 0, step: 1
8861 23:07:10.865276
8862 23:07:10.868578 RX Delay 0 -> 252, step: 8
8863 23:07:10.872176 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8864 23:07:10.875633 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8865 23:07:10.878939 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8866 23:07:10.885448 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8867 23:07:10.889321 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8868 23:07:10.891976 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8869 23:07:10.894820 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8870 23:07:10.898292 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8871 23:07:10.904700 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8872 23:07:10.908638 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8873 23:07:10.911813 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8874 23:07:10.914825 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8875 23:07:10.918194 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8876 23:07:10.925083 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8877 23:07:10.928175 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8878 23:07:10.931185 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8879 23:07:10.931260 ==
8880 23:07:10.934767 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 23:07:10.937932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 23:07:10.941358 ==
8883 23:07:10.941436 DQS Delay:
8884 23:07:10.941500 DQS0 = 0, DQS1 = 0
8885 23:07:10.944599 DQM Delay:
8886 23:07:10.944671 DQM0 = 136, DQM1 = 129
8887 23:07:10.947838 DQ Delay:
8888 23:07:10.951238 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8889 23:07:10.954155 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8890 23:07:10.957719 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8891 23:07:10.960968 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8892 23:07:10.961041
8893 23:07:10.961102
8894 23:07:10.961159 ==
8895 23:07:10.964563 Dram Type= 6, Freq= 0, CH_1, rank 1
8896 23:07:10.968046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8897 23:07:10.971132 ==
8898 23:07:10.971204
8899 23:07:10.971264
8900 23:07:10.971327 TX Vref Scan disable
8901 23:07:10.974407 == TX Byte 0 ==
8902 23:07:10.977394 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8903 23:07:10.980967 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8904 23:07:10.984542 == TX Byte 1 ==
8905 23:07:10.988344 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8906 23:07:10.990877 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8907 23:07:10.990977 ==
8908 23:07:10.994306 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 23:07:11.000836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 23:07:11.000912 ==
8911 23:07:11.013349
8912 23:07:11.015861 TX Vref early break, caculate TX vref
8913 23:07:11.019071 TX Vref=16, minBit 0, minWin=23, winSum=384
8914 23:07:11.022721 TX Vref=18, minBit 0, minWin=24, winSum=397
8915 23:07:11.026410 TX Vref=20, minBit 1, minWin=23, winSum=398
8916 23:07:11.029352 TX Vref=22, minBit 0, minWin=24, winSum=409
8917 23:07:11.032176 TX Vref=24, minBit 0, minWin=24, winSum=416
8918 23:07:11.039095 TX Vref=26, minBit 0, minWin=25, winSum=426
8919 23:07:11.042490 TX Vref=28, minBit 0, minWin=25, winSum=426
8920 23:07:11.045837 TX Vref=30, minBit 0, minWin=24, winSum=416
8921 23:07:11.048907 TX Vref=32, minBit 0, minWin=24, winSum=404
8922 23:07:11.052139 TX Vref=34, minBit 0, minWin=23, winSum=399
8923 23:07:11.059027 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 26
8924 23:07:11.059111
8925 23:07:11.061776 Final TX Range 0 Vref 26
8926 23:07:11.061848
8927 23:07:11.061909 ==
8928 23:07:11.065267 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 23:07:11.068300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 23:07:11.068374 ==
8931 23:07:11.068436
8932 23:07:11.068493
8933 23:07:11.071976 TX Vref Scan disable
8934 23:07:11.078417 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8935 23:07:11.078499 == TX Byte 0 ==
8936 23:07:11.081763 u2DelayCellOfst[0]=18 cells (5 PI)
8937 23:07:11.085241 u2DelayCellOfst[1]=11 cells (3 PI)
8938 23:07:11.087994 u2DelayCellOfst[2]=0 cells (0 PI)
8939 23:07:11.091631 u2DelayCellOfst[3]=7 cells (2 PI)
8940 23:07:11.094728 u2DelayCellOfst[4]=7 cells (2 PI)
8941 23:07:11.098749 u2DelayCellOfst[5]=18 cells (5 PI)
8942 23:07:11.101349 u2DelayCellOfst[6]=18 cells (5 PI)
8943 23:07:11.104639 u2DelayCellOfst[7]=7 cells (2 PI)
8944 23:07:11.108436 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8945 23:07:11.111621 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8946 23:07:11.114550 == TX Byte 1 ==
8947 23:07:11.118134 u2DelayCellOfst[8]=0 cells (0 PI)
8948 23:07:11.121491 u2DelayCellOfst[9]=7 cells (2 PI)
8949 23:07:11.121573 u2DelayCellOfst[10]=11 cells (3 PI)
8950 23:07:11.125176 u2DelayCellOfst[11]=7 cells (2 PI)
8951 23:07:11.127839 u2DelayCellOfst[12]=15 cells (4 PI)
8952 23:07:11.131070 u2DelayCellOfst[13]=18 cells (5 PI)
8953 23:07:11.134429 u2DelayCellOfst[14]=18 cells (5 PI)
8954 23:07:11.137761 u2DelayCellOfst[15]=18 cells (5 PI)
8955 23:07:11.144544 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8956 23:07:11.147725 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8957 23:07:11.147806 DramC Write-DBI on
8958 23:07:11.147874 ==
8959 23:07:11.151201 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 23:07:11.157446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 23:07:11.157528 ==
8962 23:07:11.157607
8963 23:07:11.157680
8964 23:07:11.160734 TX Vref Scan disable
8965 23:07:11.160815 == TX Byte 0 ==
8966 23:07:11.167079 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8967 23:07:11.167160 == TX Byte 1 ==
8968 23:07:11.171141 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8969 23:07:11.174373 DramC Write-DBI off
8970 23:07:11.174455
8971 23:07:11.174540 [DATLAT]
8972 23:07:11.177655 Freq=1600, CH1 RK1
8973 23:07:11.177736
8974 23:07:11.177800 DATLAT Default: 0xf
8975 23:07:11.180513 0, 0xFFFF, sum = 0
8976 23:07:11.180595 1, 0xFFFF, sum = 0
8977 23:07:11.183792 2, 0xFFFF, sum = 0
8978 23:07:11.183873 3, 0xFFFF, sum = 0
8979 23:07:11.187146 4, 0xFFFF, sum = 0
8980 23:07:11.187228 5, 0xFFFF, sum = 0
8981 23:07:11.190229 6, 0xFFFF, sum = 0
8982 23:07:11.190310 7, 0xFFFF, sum = 0
8983 23:07:11.194282 8, 0xFFFF, sum = 0
8984 23:07:11.196905 9, 0xFFFF, sum = 0
8985 23:07:11.196988 10, 0xFFFF, sum = 0
8986 23:07:11.200619 11, 0xFFFF, sum = 0
8987 23:07:11.200756 12, 0xFFFF, sum = 0
8988 23:07:11.203717 13, 0xFFFF, sum = 0
8989 23:07:11.203803 14, 0x0, sum = 1
8990 23:07:11.206762 15, 0x0, sum = 2
8991 23:07:11.206832 16, 0x0, sum = 3
8992 23:07:11.209974 17, 0x0, sum = 4
8993 23:07:11.210043 best_step = 15
8994 23:07:11.210101
8995 23:07:11.210156 ==
8996 23:07:11.213383 Dram Type= 6, Freq= 0, CH_1, rank 1
8997 23:07:11.216366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8998 23:07:11.219852 ==
8999 23:07:11.219934 RX Vref Scan: 0
9000 23:07:11.220016
9001 23:07:11.223656 RX Vref 0 -> 0, step: 1
9002 23:07:11.223783
9003 23:07:11.223849 RX Delay 11 -> 252, step: 4
9004 23:07:11.231051 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9005 23:07:11.234562 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9006 23:07:11.237665 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9007 23:07:11.240497 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9008 23:07:11.247210 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9009 23:07:11.250611 iDelay=203, Bit 5, Center 144 (95 ~ 194) 100
9010 23:07:11.254103 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9011 23:07:11.256899 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9012 23:07:11.260394 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9013 23:07:11.263668 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9014 23:07:11.270190 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9015 23:07:11.273339 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9016 23:07:11.276906 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9017 23:07:11.280061 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9018 23:07:11.286570 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9019 23:07:11.290090 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9020 23:07:11.290172 ==
9021 23:07:11.293814 Dram Type= 6, Freq= 0, CH_1, rank 1
9022 23:07:11.296720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9023 23:07:11.296802 ==
9024 23:07:11.299908 DQS Delay:
9025 23:07:11.300015 DQS0 = 0, DQS1 = 0
9026 23:07:11.300112 DQM Delay:
9027 23:07:11.303091 DQM0 = 134, DQM1 = 127
9028 23:07:11.303159 DQ Delay:
9029 23:07:11.306309 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9030 23:07:11.309830 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =130
9031 23:07:11.316406 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =118
9032 23:07:11.320218 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =138
9033 23:07:11.320300
9034 23:07:11.320364
9035 23:07:11.320423
9036 23:07:11.323334 [DramC_TX_OE_Calibration] TA2
9037 23:07:11.326018 Original DQ_B0 (3 6) =30, OEN = 27
9038 23:07:11.329574 Original DQ_B1 (3 6) =30, OEN = 27
9039 23:07:11.329657 24, 0x0, End_B0=24 End_B1=24
9040 23:07:11.333189 25, 0x0, End_B0=25 End_B1=25
9041 23:07:11.336610 26, 0x0, End_B0=26 End_B1=26
9042 23:07:11.339769 27, 0x0, End_B0=27 End_B1=27
9043 23:07:11.339868 28, 0x0, End_B0=28 End_B1=28
9044 23:07:11.342560 29, 0x0, End_B0=29 End_B1=29
9045 23:07:11.346031 30, 0x0, End_B0=30 End_B1=30
9046 23:07:11.349851 31, 0x4141, End_B0=30 End_B1=30
9047 23:07:11.353000 Byte0 end_step=30 best_step=27
9048 23:07:11.356388 Byte1 end_step=30 best_step=27
9049 23:07:11.356470 Byte0 TX OE(2T, 0.5T) = (3, 3)
9050 23:07:11.359384 Byte1 TX OE(2T, 0.5T) = (3, 3)
9051 23:07:11.359465
9052 23:07:11.359528
9053 23:07:11.369370 [DQSOSCAuto] RK1, (LSB)MR18= 0xd09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
9054 23:07:11.373362 CH1 RK1: MR19=303, MR18=D09
9055 23:07:11.375904 CH1_RK1: MR19=0x303, MR18=0xD09, DQSOSC=403, MR23=63, INC=22, DEC=15
9056 23:07:11.378986 [RxdqsGatingPostProcess] freq 1600
9057 23:07:11.385828 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9058 23:07:11.389237 best DQS0 dly(2T, 0.5T) = (1, 1)
9059 23:07:11.392720 best DQS1 dly(2T, 0.5T) = (1, 1)
9060 23:07:11.395469 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9061 23:07:11.399018 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9062 23:07:11.401963 best DQS0 dly(2T, 0.5T) = (1, 1)
9063 23:07:11.405806 best DQS1 dly(2T, 0.5T) = (1, 1)
9064 23:07:11.408623 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9065 23:07:11.408694 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9066 23:07:11.412015 Pre-setting of DQS Precalculation
9067 23:07:11.418374 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9068 23:07:11.425426 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9069 23:07:11.432198 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9070 23:07:11.432281
9071 23:07:11.432343
9072 23:07:11.435079 [Calibration Summary] 3200 Mbps
9073 23:07:11.438451 CH 0, Rank 0
9074 23:07:11.438532 SW Impedance : PASS
9075 23:07:11.441925 DUTY Scan : NO K
9076 23:07:11.445416 ZQ Calibration : PASS
9077 23:07:11.445497 Jitter Meter : NO K
9078 23:07:11.448572 CBT Training : PASS
9079 23:07:11.451550 Write leveling : PASS
9080 23:07:11.451631 RX DQS gating : PASS
9081 23:07:11.454841 RX DQ/DQS(RDDQC) : PASS
9082 23:07:11.454922 TX DQ/DQS : PASS
9083 23:07:11.457961 RX DATLAT : PASS
9084 23:07:11.461864 RX DQ/DQS(Engine): PASS
9085 23:07:11.461945 TX OE : PASS
9086 23:07:11.465003 All Pass.
9087 23:07:11.465083
9088 23:07:11.465147 CH 0, Rank 1
9089 23:07:11.468123 SW Impedance : PASS
9090 23:07:11.468204 DUTY Scan : NO K
9091 23:07:11.471545 ZQ Calibration : PASS
9092 23:07:11.475003 Jitter Meter : NO K
9093 23:07:11.475126 CBT Training : PASS
9094 23:07:11.478210 Write leveling : PASS
9095 23:07:11.481443 RX DQS gating : PASS
9096 23:07:11.481514 RX DQ/DQS(RDDQC) : PASS
9097 23:07:11.484881 TX DQ/DQS : PASS
9098 23:07:11.487970 RX DATLAT : PASS
9099 23:07:11.488053 RX DQ/DQS(Engine): PASS
9100 23:07:11.491651 TX OE : PASS
9101 23:07:11.491774 All Pass.
9102 23:07:11.491840
9103 23:07:11.494315 CH 1, Rank 0
9104 23:07:11.494396 SW Impedance : PASS
9105 23:07:11.497850 DUTY Scan : NO K
9106 23:07:11.501028 ZQ Calibration : PASS
9107 23:07:11.501109 Jitter Meter : NO K
9108 23:07:11.504411 CBT Training : PASS
9109 23:07:11.508162 Write leveling : PASS
9110 23:07:11.508258 RX DQS gating : PASS
9111 23:07:11.510913 RX DQ/DQS(RDDQC) : PASS
9112 23:07:11.514210 TX DQ/DQS : PASS
9113 23:07:11.514292 RX DATLAT : PASS
9114 23:07:11.517607 RX DQ/DQS(Engine): PASS
9115 23:07:11.521752 TX OE : PASS
9116 23:07:11.521834 All Pass.
9117 23:07:11.521898
9118 23:07:11.521957 CH 1, Rank 1
9119 23:07:11.524263 SW Impedance : PASS
9120 23:07:11.527548 DUTY Scan : NO K
9121 23:07:11.527629 ZQ Calibration : PASS
9122 23:07:11.530990 Jitter Meter : NO K
9123 23:07:11.531071 CBT Training : PASS
9124 23:07:11.534585 Write leveling : PASS
9125 23:07:11.537339 RX DQS gating : PASS
9126 23:07:11.537423 RX DQ/DQS(RDDQC) : PASS
9127 23:07:11.541206 TX DQ/DQS : PASS
9128 23:07:11.544479 RX DATLAT : PASS
9129 23:07:11.544560 RX DQ/DQS(Engine): PASS
9130 23:07:11.547322 TX OE : PASS
9131 23:07:11.547403 All Pass.
9132 23:07:11.547467
9133 23:07:11.550644 DramC Write-DBI on
9134 23:07:11.553925 PER_BANK_REFRESH: Hybrid Mode
9135 23:07:11.554006 TX_TRACKING: ON
9136 23:07:11.563904 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9137 23:07:11.570997 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9138 23:07:11.577213 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9139 23:07:11.583661 [FAST_K] Save calibration result to emmc
9140 23:07:11.583782 sync common calibartion params.
9141 23:07:11.587001 sync cbt_mode0:1, 1:1
9142 23:07:11.590284 dram_init: ddr_geometry: 2
9143 23:07:11.593484 dram_init: ddr_geometry: 2
9144 23:07:11.593610 dram_init: ddr_geometry: 2
9145 23:07:11.597184 0:dram_rank_size:100000000
9146 23:07:11.600100 1:dram_rank_size:100000000
9147 23:07:11.603636 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9148 23:07:11.607475 DFS_SHUFFLE_HW_MODE: ON
9149 23:07:11.611248 dramc_set_vcore_voltage set vcore to 725000
9150 23:07:11.613457 Read voltage for 1600, 0
9151 23:07:11.613538 Vio18 = 0
9152 23:07:11.616622 Vcore = 725000
9153 23:07:11.616702 Vdram = 0
9154 23:07:11.616765 Vddq = 0
9155 23:07:11.616823 Vmddr = 0
9156 23:07:11.620407 switch to 3200 Mbps bootup
9157 23:07:11.623537 [DramcRunTimeConfig]
9158 23:07:11.623642 PHYPLL
9159 23:07:11.627602 DPM_CONTROL_AFTERK: ON
9160 23:07:11.627726 PER_BANK_REFRESH: ON
9161 23:07:11.630499 REFRESH_OVERHEAD_REDUCTION: ON
9162 23:07:11.633601 CMD_PICG_NEW_MODE: OFF
9163 23:07:11.633681 XRTWTW_NEW_MODE: ON
9164 23:07:11.636419 XRTRTR_NEW_MODE: ON
9165 23:07:11.636513 TX_TRACKING: ON
9166 23:07:11.639821 RDSEL_TRACKING: OFF
9167 23:07:11.643192 DQS Precalculation for DVFS: ON
9168 23:07:11.643272 RX_TRACKING: OFF
9169 23:07:11.646622 HW_GATING DBG: ON
9170 23:07:11.646732 ZQCS_ENABLE_LP4: ON
9171 23:07:11.649857 RX_PICG_NEW_MODE: ON
9172 23:07:11.649936 TX_PICG_NEW_MODE: ON
9173 23:07:11.653856 ENABLE_RX_DCM_DPHY: ON
9174 23:07:11.656442 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9175 23:07:11.659595 DUMMY_READ_FOR_TRACKING: OFF
9176 23:07:11.659687 !!! SPM_CONTROL_AFTERK: OFF
9177 23:07:11.663279 !!! SPM could not control APHY
9178 23:07:11.666437 IMPEDANCE_TRACKING: ON
9179 23:07:11.666507 TEMP_SENSOR: ON
9180 23:07:11.670005 HW_SAVE_FOR_SR: OFF
9181 23:07:11.673027 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9182 23:07:11.676360 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9183 23:07:11.676435 Read ODT Tracking: ON
9184 23:07:11.679087 Refresh Rate DeBounce: ON
9185 23:07:11.683195 DFS_NO_QUEUE_FLUSH: ON
9186 23:07:11.686185 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9187 23:07:11.686252 ENABLE_DFS_RUNTIME_MRW: OFF
9188 23:07:11.689751 DDR_RESERVE_NEW_MODE: ON
9189 23:07:11.692880 MR_CBT_SWITCH_FREQ: ON
9190 23:07:11.692949 =========================
9191 23:07:11.712949 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9192 23:07:11.716321 dram_init: ddr_geometry: 2
9193 23:07:11.734921 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9194 23:07:11.738370 dram_init: dram init end (result: 0)
9195 23:07:11.745048 DRAM-K: Full calibration passed in 24614 msecs
9196 23:07:11.748165 MRC: failed to locate region type 0.
9197 23:07:11.748244 DRAM rank0 size:0x100000000,
9198 23:07:11.751598 DRAM rank1 size=0x100000000
9199 23:07:11.761216 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9200 23:07:11.767560 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9201 23:07:11.774037 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9202 23:07:11.780635 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9203 23:07:11.784406 DRAM rank0 size:0x100000000,
9204 23:07:11.787495 DRAM rank1 size=0x100000000
9205 23:07:11.787596 CBMEM:
9206 23:07:11.790945 IMD: root @ 0xfffff000 254 entries.
9207 23:07:11.794003 IMD: root @ 0xffffec00 62 entries.
9208 23:07:11.797329 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9209 23:07:11.803993 WARNING: RO_VPD is uninitialized or empty.
9210 23:07:11.807528 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9211 23:07:11.814945 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9212 23:07:11.827328 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9213 23:07:11.838749 BS: romstage times (exec / console): total (unknown) / 24114 ms
9214 23:07:11.838825
9215 23:07:11.838887
9216 23:07:11.849999 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9217 23:07:11.851968 ARM64: Exception handlers installed.
9218 23:07:11.855803 ARM64: Testing exception
9219 23:07:11.858662 ARM64: Done test exception
9220 23:07:11.858757 Enumerating buses...
9221 23:07:11.862535 Show all devs... Before device enumeration.
9222 23:07:11.865514 Root Device: enabled 1
9223 23:07:11.868301 CPU_CLUSTER: 0: enabled 1
9224 23:07:11.868407 CPU: 00: enabled 1
9225 23:07:11.871813 Compare with tree...
9226 23:07:11.871887 Root Device: enabled 1
9227 23:07:11.875386 CPU_CLUSTER: 0: enabled 1
9228 23:07:11.878439 CPU: 00: enabled 1
9229 23:07:11.878513 Root Device scanning...
9230 23:07:11.882154 scan_static_bus for Root Device
9231 23:07:11.884791 CPU_CLUSTER: 0 enabled
9232 23:07:11.888221 scan_static_bus for Root Device done
9233 23:07:11.891975 scan_bus: bus Root Device finished in 8 msecs
9234 23:07:11.892049 done
9235 23:07:11.898433 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9236 23:07:11.901457 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9237 23:07:11.908175 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9238 23:07:11.912143 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9239 23:07:11.914971 Allocating resources...
9240 23:07:11.918080 Reading resources...
9241 23:07:11.921045 Root Device read_resources bus 0 link: 0
9242 23:07:11.925315 DRAM rank0 size:0x100000000,
9243 23:07:11.925388 DRAM rank1 size=0x100000000
9244 23:07:11.927840 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9245 23:07:11.931090 CPU: 00 missing read_resources
9246 23:07:11.937571 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9247 23:07:11.941301 Root Device read_resources bus 0 link: 0 done
9248 23:07:11.944698 Done reading resources.
9249 23:07:11.947717 Show resources in subtree (Root Device)...After reading.
9250 23:07:11.951406 Root Device child on link 0 CPU_CLUSTER: 0
9251 23:07:11.954358 CPU_CLUSTER: 0 child on link 0 CPU: 00
9252 23:07:11.964263 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9253 23:07:11.964353 CPU: 00
9254 23:07:11.967486 Root Device assign_resources, bus 0 link: 0
9255 23:07:11.970973 CPU_CLUSTER: 0 missing set_resources
9256 23:07:11.977707 Root Device assign_resources, bus 0 link: 0 done
9257 23:07:11.977795 Done setting resources.
9258 23:07:11.984254 Show resources in subtree (Root Device)...After assigning values.
9259 23:07:11.987025 Root Device child on link 0 CPU_CLUSTER: 0
9260 23:07:11.990904 CPU_CLUSTER: 0 child on link 0 CPU: 00
9261 23:07:12.000913 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9262 23:07:12.000997 CPU: 00
9263 23:07:12.003521 Done allocating resources.
9264 23:07:12.010462 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9265 23:07:12.010543 Enabling resources...
9266 23:07:12.010677 done.
9267 23:07:12.017035 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9268 23:07:12.020160 Initializing devices...
9269 23:07:12.020266 Root Device init
9270 23:07:12.024051 init hardware done!
9271 23:07:12.024157 0x00000018: ctrlr->caps
9272 23:07:12.026610 52.000 MHz: ctrlr->f_max
9273 23:07:12.030537 0.400 MHz: ctrlr->f_min
9274 23:07:12.030618 0x40ff8080: ctrlr->voltages
9275 23:07:12.033234 sclk: 390625
9276 23:07:12.033302 Bus Width = 1
9277 23:07:12.036645 sclk: 390625
9278 23:07:12.036713 Bus Width = 1
9279 23:07:12.040622 Early init status = 3
9280 23:07:12.043613 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9281 23:07:12.046557 in-header: 03 fc 00 00 01 00 00 00
9282 23:07:12.050313 in-data: 00
9283 23:07:12.052997 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9284 23:07:12.057754 in-header: 03 fd 00 00 00 00 00 00
9285 23:07:12.061575 in-data:
9286 23:07:12.064127 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9287 23:07:12.067441 in-header: 03 fc 00 00 01 00 00 00
9288 23:07:12.070796 in-data: 00
9289 23:07:12.074152 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9290 23:07:12.078916 in-header: 03 fd 00 00 00 00 00 00
9291 23:07:12.082398 in-data:
9292 23:07:12.085364 [SSUSB] Setting up USB HOST controller...
9293 23:07:12.088906 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9294 23:07:12.093054 [SSUSB] phy power-on done.
9295 23:07:12.095254 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9296 23:07:12.102232 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9297 23:07:12.105374 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9298 23:07:12.112252 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9299 23:07:12.118315 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9300 23:07:12.125312 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9301 23:07:12.131708 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9302 23:07:12.138778 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9303 23:07:12.141678 SPM: binary array size = 0x9dc
9304 23:07:12.145124 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9305 23:07:12.151352 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9306 23:07:12.158232 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9307 23:07:12.164604 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9308 23:07:12.167869 configure_display: Starting display init
9309 23:07:12.201968 anx7625_power_on_init: Init interface.
9310 23:07:12.205064 anx7625_disable_pd_protocol: Disabled PD feature.
9311 23:07:12.208633 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9312 23:07:12.236655 anx7625_start_dp_work: Secure OCM version=00
9313 23:07:12.239774 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9314 23:07:12.254360 sp_tx_get_edid_block: EDID Block = 1
9315 23:07:12.357605 Extracted contents:
9316 23:07:12.360466 header: 00 ff ff ff ff ff ff 00
9317 23:07:12.363928 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9318 23:07:12.367331 version: 01 04
9319 23:07:12.370877 basic params: 95 1f 11 78 0a
9320 23:07:12.373894 chroma info: 76 90 94 55 54 90 27 21 50 54
9321 23:07:12.376983 established: 00 00 00
9322 23:07:12.383998 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9323 23:07:12.386843 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9324 23:07:12.393369 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9325 23:07:12.399984 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9326 23:07:12.406593 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9327 23:07:12.410306 extensions: 00
9328 23:07:12.410389 checksum: fb
9329 23:07:12.410475
9330 23:07:12.413683 Manufacturer: IVO Model 57d Serial Number 0
9331 23:07:12.416584 Made week 0 of 2020
9332 23:07:12.416667 EDID version: 1.4
9333 23:07:12.419958 Digital display
9334 23:07:12.423501 6 bits per primary color channel
9335 23:07:12.423586 DisplayPort interface
9336 23:07:12.426711 Maximum image size: 31 cm x 17 cm
9337 23:07:12.429792 Gamma: 220%
9338 23:07:12.429875 Check DPMS levels
9339 23:07:12.432862 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9340 23:07:12.439715 First detailed timing is preferred timing
9341 23:07:12.439815 Established timings supported:
9342 23:07:12.442859 Standard timings supported:
9343 23:07:12.446065 Detailed timings
9344 23:07:12.449759 Hex of detail: 383680a07038204018303c0035ae10000019
9345 23:07:12.456173 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9346 23:07:12.459550 0780 0798 07c8 0820 hborder 0
9347 23:07:12.463020 0438 043b 0447 0458 vborder 0
9348 23:07:12.466813 -hsync -vsync
9349 23:07:12.466911 Did detailed timing
9350 23:07:12.472927 Hex of detail: 000000000000000000000000000000000000
9351 23:07:12.475883 Manufacturer-specified data, tag 0
9352 23:07:12.479082 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9353 23:07:12.482598 ASCII string: InfoVision
9354 23:07:12.486082 Hex of detail: 000000fe00523134304e574635205248200a
9355 23:07:12.489381 ASCII string: R140NWF5 RH
9356 23:07:12.489465 Checksum
9357 23:07:12.492731 Checksum: 0xfb (valid)
9358 23:07:12.495862 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9359 23:07:12.498865 DSI data_rate: 832800000 bps
9360 23:07:12.505642 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9361 23:07:12.509244 anx7625_parse_edid: pixelclock(138800).
9362 23:07:12.512051 hactive(1920), hsync(48), hfp(24), hbp(88)
9363 23:07:12.516460 vactive(1080), vsync(12), vfp(3), vbp(17)
9364 23:07:12.518732 anx7625_dsi_config: config dsi.
9365 23:07:12.525383 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9366 23:07:12.539097 anx7625_dsi_config: success to config DSI
9367 23:07:12.542211 anx7625_dp_start: MIPI phy setup OK.
9368 23:07:12.545629 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9369 23:07:12.548961 mtk_ddp_mode_set invalid vrefresh 60
9370 23:07:12.552388 main_disp_path_setup
9371 23:07:12.552471 ovl_layer_smi_id_en
9372 23:07:12.555870 ovl_layer_smi_id_en
9373 23:07:12.555954 ccorr_config
9374 23:07:12.556071 aal_config
9375 23:07:12.558755 gamma_config
9376 23:07:12.558839 postmask_config
9377 23:07:12.561699 dither_config
9378 23:07:12.565378 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9379 23:07:12.572284 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9380 23:07:12.575215 Root Device init finished in 551 msecs
9381 23:07:12.578661 CPU_CLUSTER: 0 init
9382 23:07:12.585211 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9383 23:07:12.591787 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9384 23:07:12.591871 APU_MBOX 0x190000b0 = 0x10001
9385 23:07:12.594825 APU_MBOX 0x190001b0 = 0x10001
9386 23:07:12.598475 APU_MBOX 0x190005b0 = 0x10001
9387 23:07:12.601775 APU_MBOX 0x190006b0 = 0x10001
9388 23:07:12.608131 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9389 23:07:12.618546 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9390 23:07:12.630511 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9391 23:07:12.636983 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9392 23:07:12.648906 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9393 23:07:12.657983 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9394 23:07:12.661437 CPU_CLUSTER: 0 init finished in 81 msecs
9395 23:07:12.664472 Devices initialized
9396 23:07:12.667812 Show all devs... After init.
9397 23:07:12.667895 Root Device: enabled 1
9398 23:07:12.671459 CPU_CLUSTER: 0: enabled 1
9399 23:07:12.674591 CPU: 00: enabled 1
9400 23:07:12.677656 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9401 23:07:12.681047 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9402 23:07:12.684286 ELOG: NV offset 0x57f000 size 0x1000
9403 23:07:12.691254 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9404 23:07:12.697777 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9405 23:07:12.700683 ELOG: Event(17) added with size 13 at 2023-12-27 23:07:40 UTC
9406 23:07:12.707140 out: cmd=0x121: 03 db 21 01 00 00 00 00
9407 23:07:12.711075 in-header: 03 d2 00 00 2c 00 00 00
9408 23:07:12.720762 in-data: 8d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9409 23:07:12.727275 ELOG: Event(A1) added with size 10 at 2023-12-27 23:07:40 UTC
9410 23:07:12.733418 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9411 23:07:12.740909 ELOG: Event(A0) added with size 9 at 2023-12-27 23:07:40 UTC
9412 23:07:12.743363 elog_add_boot_reason: Logged dev mode boot
9413 23:07:12.750131 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9414 23:07:12.750215 Finalize devices...
9415 23:07:12.753353 Devices finalized
9416 23:07:12.756793 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9417 23:07:12.759991 Writing coreboot table at 0xffe64000
9418 23:07:12.767262 0. 000000000010a000-0000000000113fff: RAMSTAGE
9419 23:07:12.769749 1. 0000000040000000-00000000400fffff: RAM
9420 23:07:12.773436 2. 0000000040100000-000000004032afff: RAMSTAGE
9421 23:07:12.776283 3. 000000004032b000-00000000545fffff: RAM
9422 23:07:12.779822 4. 0000000054600000-000000005465ffff: BL31
9423 23:07:12.782821 5. 0000000054660000-00000000ffe63fff: RAM
9424 23:07:12.789515 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9425 23:07:12.792728 7. 0000000100000000-000000023fffffff: RAM
9426 23:07:12.795914 Passing 5 GPIOs to payload:
9427 23:07:12.799455 NAME | PORT | POLARITY | VALUE
9428 23:07:12.805604 EC in RW | 0x000000aa | low | undefined
9429 23:07:12.809479 EC interrupt | 0x00000005 | low | undefined
9430 23:07:12.815942 TPM interrupt | 0x000000ab | high | undefined
9431 23:07:12.818919 SD card detect | 0x00000011 | high | undefined
9432 23:07:12.822483 speaker enable | 0x00000093 | high | undefined
9433 23:07:12.829014 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9434 23:07:12.832381 in-header: 03 f9 00 00 02 00 00 00
9435 23:07:12.832465 in-data: 02 00
9436 23:07:12.835276 ADC[4]: Raw value=904509 ID=7
9437 23:07:12.839278 ADC[3]: Raw value=214021 ID=1
9438 23:07:12.839361 RAM Code: 0x71
9439 23:07:12.842244 ADC[6]: Raw value=75036 ID=0
9440 23:07:12.844991 ADC[5]: Raw value=212912 ID=1
9441 23:07:12.845075 SKU Code: 0x1
9442 23:07:12.851593 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a1a9
9443 23:07:12.855356 coreboot table: 964 bytes.
9444 23:07:12.858171 IMD ROOT 0. 0xfffff000 0x00001000
9445 23:07:12.861330 IMD SMALL 1. 0xffffe000 0x00001000
9446 23:07:12.865002 RO MCACHE 2. 0xffffc000 0x00001104
9447 23:07:12.868188 CONSOLE 3. 0xfff7c000 0x00080000
9448 23:07:12.871611 FMAP 4. 0xfff7b000 0x00000452
9449 23:07:12.875098 TIME STAMP 5. 0xfff7a000 0x00000910
9450 23:07:12.878177 VBOOT WORK 6. 0xfff66000 0x00014000
9451 23:07:12.881623 RAMOOPS 7. 0xffe66000 0x00100000
9452 23:07:12.884687 COREBOOT 8. 0xffe64000 0x00002000
9453 23:07:12.884800 IMD small region:
9454 23:07:12.888685 IMD ROOT 0. 0xffffec00 0x00000400
9455 23:07:12.891125 VPD 1. 0xffffeb80 0x0000006c
9456 23:07:12.894297 MMC STATUS 2. 0xffffeb60 0x00000004
9457 23:07:12.900971 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9458 23:07:12.901067 Probing TPM: done!
9459 23:07:12.907818 Connected to device vid:did:rid of 1ae0:0028:00
9460 23:07:12.918261 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9461 23:07:12.921284 Initialized TPM device CR50 revision 0
9462 23:07:12.921365 Checking cr50 for pending updates
9463 23:07:12.927435 Reading cr50 TPM mode
9464 23:07:12.935985 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9465 23:07:12.943289 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9466 23:07:12.982805 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9467 23:07:12.986469 Checking segment from ROM address 0x40100000
9468 23:07:12.990164 Checking segment from ROM address 0x4010001c
9469 23:07:12.996401 Loading segment from ROM address 0x40100000
9470 23:07:12.996485 code (compression=0)
9471 23:07:13.006500 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9472 23:07:13.012906 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9473 23:07:13.012991 it's not compressed!
9474 23:07:13.019219 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9475 23:07:13.026580 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9476 23:07:13.043707 Loading segment from ROM address 0x4010001c
9477 23:07:13.043827 Entry Point 0x80000000
9478 23:07:13.046776 Loaded segments
9479 23:07:13.049718 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9480 23:07:13.056748 Jumping to boot code at 0x80000000(0xffe64000)
9481 23:07:13.062940 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9482 23:07:13.069403 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9483 23:07:13.077980 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9484 23:07:13.081164 Checking segment from ROM address 0x40100000
9485 23:07:13.084355 Checking segment from ROM address 0x4010001c
9486 23:07:13.091449 Loading segment from ROM address 0x40100000
9487 23:07:13.091534 code (compression=1)
9488 23:07:13.097497 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9489 23:07:13.107394 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9490 23:07:13.107478 using LZMA
9491 23:07:13.116159 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9492 23:07:13.122762 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9493 23:07:13.126178 Loading segment from ROM address 0x4010001c
9494 23:07:13.126261 Entry Point 0x54601000
9495 23:07:13.129434 Loaded segments
9496 23:07:13.133458 NOTICE: MT8192 bl31_setup
9497 23:07:13.139572 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9498 23:07:13.142899 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9499 23:07:13.146330 WARNING: region 0:
9500 23:07:13.149784 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9501 23:07:13.149868 WARNING: region 1:
9502 23:07:13.156741 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9503 23:07:13.159364 WARNING: region 2:
9504 23:07:13.162748 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9505 23:07:13.166449 WARNING: region 3:
9506 23:07:13.169067 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9507 23:07:13.173041 WARNING: region 4:
9508 23:07:13.179742 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9509 23:07:13.179838 WARNING: region 5:
9510 23:07:13.183450 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9511 23:07:13.185887 WARNING: region 6:
9512 23:07:13.189181 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9513 23:07:13.192669 WARNING: region 7:
9514 23:07:13.195703 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9515 23:07:13.202615 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9516 23:07:13.206221 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9517 23:07:13.212489 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9518 23:07:13.215498 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9519 23:07:13.218714 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9520 23:07:13.225590 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9521 23:07:13.228808 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9522 23:07:13.232462 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9523 23:07:13.238729 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9524 23:07:13.242260 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9525 23:07:13.248635 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9526 23:07:13.252122 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9527 23:07:13.255831 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9528 23:07:13.262495 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9529 23:07:13.265298 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9530 23:07:13.268740 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9531 23:07:13.275705 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9532 23:07:13.279218 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9533 23:07:13.281976 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9534 23:07:13.288957 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9535 23:07:13.292179 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9536 23:07:13.298969 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9537 23:07:13.302617 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9538 23:07:13.305359 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9539 23:07:13.312178 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9540 23:07:13.315488 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9541 23:07:13.322370 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9542 23:07:13.325482 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9543 23:07:13.328874 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9544 23:07:13.335423 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9545 23:07:13.339377 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9546 23:07:13.345208 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9547 23:07:13.349126 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9548 23:07:13.352096 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9549 23:07:13.355260 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9550 23:07:13.362120 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9551 23:07:13.365608 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9552 23:07:13.368750 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9553 23:07:13.371933 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9554 23:07:13.378747 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9555 23:07:13.381909 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9556 23:07:13.385048 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9557 23:07:13.388416 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9558 23:07:13.395338 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9559 23:07:13.398768 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9560 23:07:13.402346 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9561 23:07:13.405419 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9562 23:07:13.412437 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9563 23:07:13.415171 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9564 23:07:13.421733 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9565 23:07:13.425373 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9566 23:07:13.428619 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9567 23:07:13.435278 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9568 23:07:13.438354 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9569 23:07:13.445041 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9570 23:07:13.447916 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9571 23:07:13.454801 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9572 23:07:13.458227 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9573 23:07:13.461597 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9574 23:07:13.468043 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9575 23:07:13.471300 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9576 23:07:13.477612 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9577 23:07:13.480897 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9578 23:07:13.487771 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9579 23:07:13.491355 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9580 23:07:13.497533 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9581 23:07:13.500714 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9582 23:07:13.507427 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9583 23:07:13.510762 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9584 23:07:13.514486 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9585 23:07:13.520938 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9586 23:07:13.524543 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9587 23:07:13.530464 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9588 23:07:13.533812 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9589 23:07:13.541265 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9590 23:07:13.544400 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9591 23:07:13.550489 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9592 23:07:13.553497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9593 23:07:13.557391 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9594 23:07:13.563464 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9595 23:07:13.566960 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9596 23:07:13.573874 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9597 23:07:13.577342 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9598 23:07:13.583617 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9599 23:07:13.587194 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9600 23:07:13.590807 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9601 23:07:13.596950 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9602 23:07:13.600239 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9603 23:07:13.607071 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9604 23:07:13.610181 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9605 23:07:13.616937 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9606 23:07:13.620197 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9607 23:07:13.624351 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9608 23:07:13.630987 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9609 23:07:13.634286 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9610 23:07:13.640560 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9611 23:07:13.643572 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9612 23:07:13.646938 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9613 23:07:13.653411 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9614 23:07:13.657020 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9615 23:07:13.659880 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9616 23:07:13.666510 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9617 23:07:13.670234 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9618 23:07:13.673440 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9619 23:07:13.680562 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9620 23:07:13.683256 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9621 23:07:13.686880 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9622 23:07:13.693577 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9623 23:07:13.696665 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9624 23:07:13.702969 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9625 23:07:13.706702 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9626 23:07:13.712993 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9627 23:07:13.716655 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9628 23:07:13.720158 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9629 23:07:13.726332 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9630 23:07:13.729761 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9631 23:07:13.733551 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9632 23:07:13.739733 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9633 23:07:13.742939 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9634 23:07:13.746247 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9635 23:07:13.752958 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9636 23:07:13.756199 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9637 23:07:13.759766 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9638 23:07:13.762922 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9639 23:07:13.769519 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9640 23:07:13.773238 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9641 23:07:13.776746 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9642 23:07:13.783096 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9643 23:07:13.786170 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9644 23:07:13.793371 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9645 23:07:13.796069 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9646 23:07:13.799507 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9647 23:07:13.806200 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9648 23:07:13.809089 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9649 23:07:13.815883 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9650 23:07:13.819188 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9651 23:07:13.825468 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9652 23:07:13.829099 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9653 23:07:13.832422 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9654 23:07:13.838879 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9655 23:07:13.843005 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9656 23:07:13.845520 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9657 23:07:13.851924 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9658 23:07:13.855326 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9659 23:07:13.861810 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9660 23:07:13.865247 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9661 23:07:13.868966 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9662 23:07:13.875638 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9663 23:07:13.878289 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9664 23:07:13.885176 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9665 23:07:13.888375 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9666 23:07:13.892052 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9667 23:07:13.898512 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9668 23:07:13.901837 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9669 23:07:13.908361 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9670 23:07:13.911867 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9671 23:07:13.914825 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9672 23:07:13.921334 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9673 23:07:13.925098 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9674 23:07:13.931277 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9675 23:07:13.934728 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9676 23:07:13.937895 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9677 23:07:13.944813 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9678 23:07:13.947685 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9679 23:07:13.954596 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9680 23:07:13.958107 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9681 23:07:13.960904 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9682 23:07:13.967447 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9683 23:07:13.971264 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9684 23:07:13.977699 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9685 23:07:13.981316 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9686 23:07:13.984127 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9687 23:07:13.990943 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9688 23:07:13.994197 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9689 23:07:14.000492 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9690 23:07:14.004310 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9691 23:07:14.007095 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9692 23:07:14.013728 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9693 23:07:14.016861 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9694 23:07:14.023464 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9695 23:07:14.026648 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9696 23:07:14.029968 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9697 23:07:14.036750 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9698 23:07:14.039913 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9699 23:07:14.046789 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9700 23:07:14.050020 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9701 23:07:14.053429 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9702 23:07:14.059697 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9703 23:07:14.062989 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9704 23:07:14.069961 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9705 23:07:14.072781 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9706 23:07:14.080025 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9707 23:07:14.082834 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9708 23:07:14.086158 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9709 23:07:14.093061 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9710 23:07:14.096362 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9711 23:07:14.102462 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9712 23:07:14.106088 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9713 23:07:14.112662 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9714 23:07:14.115768 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9715 23:07:14.119059 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9716 23:07:14.125715 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9717 23:07:14.129537 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9718 23:07:14.135870 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9719 23:07:14.138691 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9720 23:07:14.145351 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9721 23:07:14.148737 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9722 23:07:14.152383 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9723 23:07:14.159185 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9724 23:07:14.161993 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9725 23:07:14.168439 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9726 23:07:14.171698 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9727 23:07:14.178289 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9728 23:07:14.182379 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9729 23:07:14.185310 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9730 23:07:14.191576 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9731 23:07:14.195374 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9732 23:07:14.201548 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9733 23:07:14.204825 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9734 23:07:14.211616 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9735 23:07:14.215046 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9736 23:07:14.219126 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9737 23:07:14.224872 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9738 23:07:14.228662 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9739 23:07:14.234830 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9740 23:07:14.237778 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9741 23:07:14.244782 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9742 23:07:14.247882 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9743 23:07:14.251309 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9744 23:07:14.254612 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9745 23:07:14.261079 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9746 23:07:14.264153 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9747 23:07:14.267549 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9748 23:07:14.270943 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9749 23:07:14.277989 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9750 23:07:14.280767 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9751 23:07:14.287716 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9752 23:07:14.290852 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9753 23:07:14.294526 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9754 23:07:14.300863 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9755 23:07:14.304127 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9756 23:07:14.310653 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9757 23:07:14.314143 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9758 23:07:14.317042 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9759 23:07:14.324270 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9760 23:07:14.327402 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9761 23:07:14.330846 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9762 23:07:14.336756 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9763 23:07:14.340582 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9764 23:07:14.343732 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9765 23:07:14.350536 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9766 23:07:14.353316 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9767 23:07:14.360643 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9768 23:07:14.363652 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9769 23:07:14.366646 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9770 23:07:14.373319 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9771 23:07:14.376909 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9772 23:07:14.383092 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9773 23:07:14.386453 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9774 23:07:14.389736 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9775 23:07:14.396261 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9776 23:07:14.400121 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9777 23:07:14.403521 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9778 23:07:14.409174 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9779 23:07:14.413241 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9780 23:07:14.419279 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9781 23:07:14.422738 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9782 23:07:14.426572 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9783 23:07:14.432649 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9784 23:07:14.435884 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9785 23:07:14.439290 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9786 23:07:14.442180 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9787 23:07:14.445457 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9788 23:07:14.452500 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9789 23:07:14.455383 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9790 23:07:14.458878 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9791 23:07:14.462181 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9792 23:07:14.468631 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9793 23:07:14.472033 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9794 23:07:14.475169 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9795 23:07:14.481848 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9796 23:07:14.485274 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9797 23:07:14.488431 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9798 23:07:14.494880 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9799 23:07:14.498789 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9800 23:07:14.504960 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9801 23:07:14.508373 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9802 23:07:14.511954 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9803 23:07:14.518812 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9804 23:07:14.521480 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9805 23:07:14.528744 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9806 23:07:14.531262 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9807 23:07:14.538039 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9808 23:07:14.541682 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9809 23:07:14.545743 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9810 23:07:14.551048 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9811 23:07:14.554958 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9812 23:07:14.561143 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9813 23:07:14.564577 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9814 23:07:14.568165 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9815 23:07:14.574187 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9816 23:07:14.577727 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9817 23:07:14.584372 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9818 23:07:14.587609 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9819 23:07:14.594092 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9820 23:07:14.597603 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9821 23:07:14.600943 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9822 23:07:14.607303 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9823 23:07:14.610752 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9824 23:07:14.617027 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9825 23:07:14.620490 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9826 23:07:14.623681 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9827 23:07:14.630313 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9828 23:07:14.633930 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9829 23:07:14.640289 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9830 23:07:14.643374 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9831 23:07:14.650596 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9832 23:07:14.653737 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9833 23:07:14.656738 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9834 23:07:14.663193 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9835 23:07:14.666825 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9836 23:07:14.673761 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9837 23:07:14.676447 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9838 23:07:14.679925 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9839 23:07:14.686980 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9840 23:07:14.689904 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9841 23:07:14.696627 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9842 23:07:14.699947 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9843 23:07:14.706871 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9844 23:07:14.709788 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9845 23:07:14.713314 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9846 23:07:14.719237 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9847 23:07:14.722640 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9848 23:07:14.729561 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9849 23:07:14.733331 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9850 23:07:14.736165 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9851 23:07:14.742431 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9852 23:07:14.746811 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9853 23:07:14.752552 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9854 23:07:14.755549 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9855 23:07:14.762575 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9856 23:07:14.765583 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9857 23:07:14.768945 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9858 23:07:14.775399 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9859 23:07:14.778805 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9860 23:07:14.785235 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9861 23:07:14.788965 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9862 23:07:14.791996 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9863 23:07:14.798822 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9864 23:07:14.801764 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9865 23:07:14.808281 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9866 23:07:14.811703 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9867 23:07:14.818200 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9868 23:07:14.821898 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9869 23:07:14.824935 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9870 23:07:14.831743 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9871 23:07:14.835202 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9872 23:07:14.841998 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9873 23:07:14.844824 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9874 23:07:14.851556 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9875 23:07:14.854974 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9876 23:07:14.858477 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9877 23:07:14.864744 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9878 23:07:14.868249 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9879 23:07:14.875103 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9880 23:07:14.877936 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9881 23:07:14.884552 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9882 23:07:14.888734 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9883 23:07:14.894632 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9884 23:07:14.898026 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9885 23:07:14.901660 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9886 23:07:14.907752 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9887 23:07:14.911437 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9888 23:07:14.918096 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9889 23:07:14.921199 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9890 23:07:14.927493 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9891 23:07:14.931468 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9892 23:07:14.934053 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9893 23:07:14.941025 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9894 23:07:14.944570 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9895 23:07:14.950494 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9896 23:07:14.953691 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9897 23:07:14.961455 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9898 23:07:14.963594 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9899 23:07:14.970140 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9900 23:07:14.974199 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9901 23:07:14.977389 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9902 23:07:14.983321 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9903 23:07:14.986863 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9904 23:07:14.993237 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9905 23:07:14.996546 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9906 23:07:15.003978 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9907 23:07:15.006615 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9908 23:07:15.013614 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9909 23:07:15.016816 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9910 23:07:15.023001 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9911 23:07:15.026378 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9912 23:07:15.029471 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9913 23:07:15.036413 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9914 23:07:15.039905 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9915 23:07:15.046023 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9916 23:07:15.049568 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9917 23:07:15.053032 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9918 23:07:15.059215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9919 23:07:15.063275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9920 23:07:15.069266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9921 23:07:15.072860 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9922 23:07:15.079548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9923 23:07:15.082638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9924 23:07:15.089355 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9925 23:07:15.092730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9926 23:07:15.099112 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9927 23:07:15.102273 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9928 23:07:15.109284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9929 23:07:15.112314 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9930 23:07:15.119203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9931 23:07:15.122278 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9932 23:07:15.129189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9933 23:07:15.132672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9934 23:07:15.139101 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9935 23:07:15.142612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9936 23:07:15.148732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9937 23:07:15.151985 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9938 23:07:15.159155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9939 23:07:15.161940 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9940 23:07:15.168643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9941 23:07:15.171850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9942 23:07:15.178629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9943 23:07:15.181666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9944 23:07:15.188230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9945 23:07:15.191809 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9946 23:07:15.198194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9947 23:07:15.201517 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9948 23:07:15.208328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9949 23:07:15.211408 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9950 23:07:15.215056 INFO: [APUAPC] vio 0
9951 23:07:15.218150 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9952 23:07:15.224576 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9953 23:07:15.228492 INFO: [APUAPC] D0_APC_0: 0x400510
9954 23:07:15.228599 INFO: [APUAPC] D0_APC_1: 0x0
9955 23:07:15.231113 INFO: [APUAPC] D0_APC_2: 0x1540
9956 23:07:15.234559 INFO: [APUAPC] D0_APC_3: 0x0
9957 23:07:15.237868 INFO: [APUAPC] D1_APC_0: 0xffffffff
9958 23:07:15.240860 INFO: [APUAPC] D1_APC_1: 0xffffffff
9959 23:07:15.244139 INFO: [APUAPC] D1_APC_2: 0x3fffff
9960 23:07:15.247799 INFO: [APUAPC] D1_APC_3: 0x0
9961 23:07:15.251376 INFO: [APUAPC] D2_APC_0: 0xffffffff
9962 23:07:15.254254 INFO: [APUAPC] D2_APC_1: 0xffffffff
9963 23:07:15.257485 INFO: [APUAPC] D2_APC_2: 0x3fffff
9964 23:07:15.260866 INFO: [APUAPC] D2_APC_3: 0x0
9965 23:07:15.264448 INFO: [APUAPC] D3_APC_0: 0xffffffff
9966 23:07:15.267516 INFO: [APUAPC] D3_APC_1: 0xffffffff
9967 23:07:15.270722 INFO: [APUAPC] D3_APC_2: 0x3fffff
9968 23:07:15.274252 INFO: [APUAPC] D3_APC_3: 0x0
9969 23:07:15.277452 INFO: [APUAPC] D4_APC_0: 0xffffffff
9970 23:07:15.280991 INFO: [APUAPC] D4_APC_1: 0xffffffff
9971 23:07:15.283982 INFO: [APUAPC] D4_APC_2: 0x3fffff
9972 23:07:15.287263 INFO: [APUAPC] D4_APC_3: 0x0
9973 23:07:15.290700 INFO: [APUAPC] D5_APC_0: 0xffffffff
9974 23:07:15.294357 INFO: [APUAPC] D5_APC_1: 0xffffffff
9975 23:07:15.297124 INFO: [APUAPC] D5_APC_2: 0x3fffff
9976 23:07:15.301023 INFO: [APUAPC] D5_APC_3: 0x0
9977 23:07:15.303730 INFO: [APUAPC] D6_APC_0: 0xffffffff
9978 23:07:15.307114 INFO: [APUAPC] D6_APC_1: 0xffffffff
9979 23:07:15.310964 INFO: [APUAPC] D6_APC_2: 0x3fffff
9980 23:07:15.313893 INFO: [APUAPC] D6_APC_3: 0x0
9981 23:07:15.317052 INFO: [APUAPC] D7_APC_0: 0xffffffff
9982 23:07:15.320389 INFO: [APUAPC] D7_APC_1: 0xffffffff
9983 23:07:15.323955 INFO: [APUAPC] D7_APC_2: 0x3fffff
9984 23:07:15.326929 INFO: [APUAPC] D7_APC_3: 0x0
9985 23:07:15.330022 INFO: [APUAPC] D8_APC_0: 0xffffffff
9986 23:07:15.333925 INFO: [APUAPC] D8_APC_1: 0xffffffff
9987 23:07:15.336611 INFO: [APUAPC] D8_APC_2: 0x3fffff
9988 23:07:15.340365 INFO: [APUAPC] D8_APC_3: 0x0
9989 23:07:15.343333 INFO: [APUAPC] D9_APC_0: 0xffffffff
9990 23:07:15.347325 INFO: [APUAPC] D9_APC_1: 0xffffffff
9991 23:07:15.350434 INFO: [APUAPC] D9_APC_2: 0x3fffff
9992 23:07:15.353216 INFO: [APUAPC] D9_APC_3: 0x0
9993 23:07:15.356943 INFO: [APUAPC] D10_APC_0: 0xffffffff
9994 23:07:15.359902 INFO: [APUAPC] D10_APC_1: 0xffffffff
9995 23:07:15.363187 INFO: [APUAPC] D10_APC_2: 0x3fffff
9996 23:07:15.366795 INFO: [APUAPC] D10_APC_3: 0x0
9997 23:07:15.369810 INFO: [APUAPC] D11_APC_0: 0xffffffff
9998 23:07:15.373258 INFO: [APUAPC] D11_APC_1: 0xffffffff
9999 23:07:15.376814 INFO: [APUAPC] D11_APC_2: 0x3fffff
10000 23:07:15.380254 INFO: [APUAPC] D11_APC_3: 0x0
10001 23:07:15.383094 INFO: [APUAPC] D12_APC_0: 0xffffffff
10002 23:07:15.386401 INFO: [APUAPC] D12_APC_1: 0xffffffff
10003 23:07:15.389877 INFO: [APUAPC] D12_APC_2: 0x3fffff
10004 23:07:15.393004 INFO: [APUAPC] D12_APC_3: 0x0
10005 23:07:15.396449 INFO: [APUAPC] D13_APC_0: 0xffffffff
10006 23:07:15.399876 INFO: [APUAPC] D13_APC_1: 0xffffffff
10007 23:07:15.403096 INFO: [APUAPC] D13_APC_2: 0x3fffff
10008 23:07:15.406195 INFO: [APUAPC] D13_APC_3: 0x0
10009 23:07:15.409186 INFO: [APUAPC] D14_APC_0: 0xffffffff
10010 23:07:15.413793 INFO: [APUAPC] D14_APC_1: 0xffffffff
10011 23:07:15.416043 INFO: [APUAPC] D14_APC_2: 0x3fffff
10012 23:07:15.419870 INFO: [APUAPC] D14_APC_3: 0x0
10013 23:07:15.423139 INFO: [APUAPC] D15_APC_0: 0xffffffff
10014 23:07:15.426309 INFO: [APUAPC] D15_APC_1: 0xffffffff
10015 23:07:15.429015 INFO: [APUAPC] D15_APC_2: 0x3fffff
10016 23:07:15.432417 INFO: [APUAPC] D15_APC_3: 0x0
10017 23:07:15.436524 INFO: [APUAPC] APC_CON: 0x4
10018 23:07:15.438991 INFO: [NOCDAPC] D0_APC_0: 0x0
10019 23:07:15.442650 INFO: [NOCDAPC] D0_APC_1: 0x0
10020 23:07:15.446035 INFO: [NOCDAPC] D1_APC_0: 0x0
10021 23:07:15.446130 INFO: [NOCDAPC] D1_APC_1: 0xfff
10022 23:07:15.449392 INFO: [NOCDAPC] D2_APC_0: 0x0
10023 23:07:15.452693 INFO: [NOCDAPC] D2_APC_1: 0xfff
10024 23:07:15.455358 INFO: [NOCDAPC] D3_APC_0: 0x0
10025 23:07:15.458717 INFO: [NOCDAPC] D3_APC_1: 0xfff
10026 23:07:15.462515 INFO: [NOCDAPC] D4_APC_0: 0x0
10027 23:07:15.465317 INFO: [NOCDAPC] D4_APC_1: 0xfff
10028 23:07:15.468644 INFO: [NOCDAPC] D5_APC_0: 0x0
10029 23:07:15.472100 INFO: [NOCDAPC] D5_APC_1: 0xfff
10030 23:07:15.475446 INFO: [NOCDAPC] D6_APC_0: 0x0
10031 23:07:15.478723 INFO: [NOCDAPC] D6_APC_1: 0xfff
10032 23:07:15.478806 INFO: [NOCDAPC] D7_APC_0: 0x0
10033 23:07:15.481798 INFO: [NOCDAPC] D7_APC_1: 0xfff
10034 23:07:15.485217 INFO: [NOCDAPC] D8_APC_0: 0x0
10035 23:07:15.488619 INFO: [NOCDAPC] D8_APC_1: 0xfff
10036 23:07:15.492233 INFO: [NOCDAPC] D9_APC_0: 0x0
10037 23:07:15.495453 INFO: [NOCDAPC] D9_APC_1: 0xfff
10038 23:07:15.498544 INFO: [NOCDAPC] D10_APC_0: 0x0
10039 23:07:15.501904 INFO: [NOCDAPC] D10_APC_1: 0xfff
10040 23:07:15.505084 INFO: [NOCDAPC] D11_APC_0: 0x0
10041 23:07:15.508489 INFO: [NOCDAPC] D11_APC_1: 0xfff
10042 23:07:15.511895 INFO: [NOCDAPC] D12_APC_0: 0x0
10043 23:07:15.515120 INFO: [NOCDAPC] D12_APC_1: 0xfff
10044 23:07:15.518164 INFO: [NOCDAPC] D13_APC_0: 0x0
10045 23:07:15.522261 INFO: [NOCDAPC] D13_APC_1: 0xfff
10046 23:07:15.524509 INFO: [NOCDAPC] D14_APC_0: 0x0
10047 23:07:15.528246 INFO: [NOCDAPC] D14_APC_1: 0xfff
10048 23:07:15.528350 INFO: [NOCDAPC] D15_APC_0: 0x0
10049 23:07:15.531560 INFO: [NOCDAPC] D15_APC_1: 0xfff
10050 23:07:15.535099 INFO: [NOCDAPC] APC_CON: 0x4
10051 23:07:15.538189 INFO: [APUAPC] set_apusys_apc done
10052 23:07:15.541112 INFO: [DEVAPC] devapc_init done
10053 23:07:15.548045 INFO: GICv3 without legacy support detected.
10054 23:07:15.551109 INFO: ARM GICv3 driver initialized in EL3
10055 23:07:15.555642 INFO: Maximum SPI INTID supported: 639
10056 23:07:15.558295 INFO: BL31: Initializing runtime services
10057 23:07:15.564059 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10058 23:07:15.567709 INFO: SPM: enable CPC mode
10059 23:07:15.571245 INFO: mcdi ready for mcusys-off-idle and system suspend
10060 23:07:15.577404 INFO: BL31: Preparing for EL3 exit to normal world
10061 23:07:15.581178 INFO: Entry point address = 0x80000000
10062 23:07:15.581260 INFO: SPSR = 0x8
10063 23:07:15.587409
10064 23:07:15.587491
10065 23:07:15.587556
10066 23:07:15.590867 Starting depthcharge on Spherion...
10067 23:07:15.590950
10068 23:07:15.591015 Wipe memory regions:
10069 23:07:15.591076
10070 23:07:15.591770 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10071 23:07:15.591881 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10072 23:07:15.591969 Setting prompt string to ['asurada:']
10073 23:07:15.592049 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10074 23:07:15.594002 [0x00000040000000, 0x00000054600000)
10075 23:07:15.716649
10076 23:07:15.716762 [0x00000054660000, 0x00000080000000)
10077 23:07:15.977352
10078 23:07:15.977487 [0x000000821a7280, 0x000000ffe64000)
10079 23:07:16.721893
10080 23:07:16.722038 [0x00000100000000, 0x00000240000000)
10081 23:07:18.612132
10082 23:07:18.615420 Initializing XHCI USB controller at 0x11200000.
10083 23:07:19.596782
10084 23:07:19.596928 R8152: Initializing
10085 23:07:19.597000
10086 23:07:19.600090 Version 9 (ocp_data = 6010)
10087 23:07:19.600172
10088 23:07:19.603588 R8152: Done initializing
10089 23:07:19.603680
10090 23:07:19.603761 Adding net device
10091 23:07:20.000914
10092 23:07:20.004783 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10093 23:07:20.004879
10094 23:07:20.004944
10095 23:07:20.005007
10096 23:07:20.005283 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10098 23:07:20.105624 asurada: tftpboot 192.168.201.1 12395342/tftp-deploy-964i7d0v/kernel/image.itb 12395342/tftp-deploy-964i7d0v/kernel/cmdline
10099 23:07:20.105784 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10100 23:07:20.105915 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10101 23:07:20.109902 tftpboot 192.168.201.1 12395342/tftp-deploy-964i7d0v/kernel/image.itp-deploy-964i7d0v/kernel/cmdline
10102 23:07:20.110003
10103 23:07:20.110069 Waiting for link
10104 23:07:20.311567
10105 23:07:20.311732 done.
10106 23:07:20.311804
10107 23:07:20.311866 MAC: f4:f5:e8:50:de:0a
10108 23:07:20.311925
10109 23:07:20.315113 Sending DHCP discover... done.
10110 23:07:20.315195
10111 23:07:20.318245 Waiting for reply... done.
10112 23:07:20.318327
10113 23:07:20.321491 Sending DHCP request... done.
10114 23:07:20.321572
10115 23:07:20.325869 Waiting for reply... done.
10116 23:07:20.325983
10117 23:07:20.326049 My ip is 192.168.201.14
10118 23:07:20.326109
10119 23:07:20.329224 The DHCP server ip is 192.168.201.1
10120 23:07:20.329306
10121 23:07:20.336326 TFTP server IP predefined by user: 192.168.201.1
10122 23:07:20.336454
10123 23:07:20.343064 Bootfile predefined by user: 12395342/tftp-deploy-964i7d0v/kernel/image.itb
10124 23:07:20.343149
10125 23:07:20.345547 Sending tftp read request... done.
10126 23:07:20.345656
10127 23:07:20.348991 Waiting for the transfer...
10128 23:07:20.349075
10129 23:07:20.579197 00000000 ################################################################
10130 23:07:20.579341
10131 23:07:20.802809 00080000 ################################################################
10132 23:07:20.802949
10133 23:07:21.029384 00100000 ################################################################
10134 23:07:21.029513
10135 23:07:21.260911 00180000 ################################################################
10136 23:07:21.261041
10137 23:07:21.487431 00200000 ################################################################
10138 23:07:21.487563
10139 23:07:21.713739 00280000 ################################################################
10140 23:07:21.713880
10141 23:07:21.938973 00300000 ################################################################
10142 23:07:21.939118
10143 23:07:22.188722 00380000 ################################################################
10144 23:07:22.188863
10145 23:07:22.439829 00400000 ################################################################
10146 23:07:22.439982
10147 23:07:22.701270 00480000 ################################################################
10148 23:07:22.701408
10149 23:07:22.946754 00500000 ################################################################
10150 23:07:22.946898
10151 23:07:23.183155 00580000 ################################################################
10152 23:07:23.183301
10153 23:07:23.418444 00600000 ################################################################
10154 23:07:23.418585
10155 23:07:23.653436 00680000 ################################################################
10156 23:07:23.653575
10157 23:07:23.902680 00700000 ################################################################
10158 23:07:23.902858
10159 23:07:24.129467 00780000 ################################################################
10160 23:07:24.129606
10161 23:07:24.356643 00800000 ################################################################
10162 23:07:24.356774
10163 23:07:24.585851 00880000 ################################################################
10164 23:07:24.585983
10165 23:07:24.811901 00900000 ################################################################
10166 23:07:24.812029
10167 23:07:25.039339 00980000 ################################################################
10168 23:07:25.039484
10169 23:07:25.292500 00a00000 ################################################################
10170 23:07:25.292641
10171 23:07:25.522339 00a80000 ################################################################
10172 23:07:25.522475
10173 23:07:25.748875 00b00000 ################################################################
10174 23:07:25.749012
10175 23:07:26.002333 00b80000 ################################################################
10176 23:07:26.002505
10177 23:07:26.250480 00c00000 ################################################################
10178 23:07:26.250634
10179 23:07:26.486885 00c80000 ################################################################
10180 23:07:26.487023
10181 23:07:26.727903 00d00000 ################################################################
10182 23:07:26.728051
10183 23:07:26.965887 00d80000 ################################################################
10184 23:07:26.966027
10185 23:07:27.204057 00e00000 ################################################################
10186 23:07:27.204198
10187 23:07:27.446069 00e80000 ################################################################
10188 23:07:27.446244
10189 23:07:27.691893 00f00000 ################################################################
10190 23:07:27.692031
10191 23:07:27.923492 00f80000 ################################################################
10192 23:07:27.923626
10193 23:07:28.159143 01000000 ################################################################
10194 23:07:28.159278
10195 23:07:28.399230 01080000 ################################################################
10196 23:07:28.399363
10197 23:07:28.663784 01100000 ################################################################
10198 23:07:28.663920
10199 23:07:28.891870 01180000 ################################################################
10200 23:07:28.892002
10201 23:07:29.118882 01200000 ################################################################
10202 23:07:29.119012
10203 23:07:29.353534 01280000 ################################################################
10204 23:07:29.353681
10205 23:07:29.581330 01300000 ################################################################
10206 23:07:29.581473
10207 23:07:29.821823 01380000 ################################################################
10208 23:07:29.821961
10209 23:07:30.056508 01400000 ################################################################
10210 23:07:30.056676
10211 23:07:30.307323 01480000 ################################################################
10212 23:07:30.307461
10213 23:07:30.540672 01500000 ################################################################
10214 23:07:30.540816
10215 23:07:30.774954 01580000 ################################################################
10216 23:07:30.775094
10217 23:07:31.008120 01600000 ################################################################
10218 23:07:31.008255
10219 23:07:31.234593 01680000 ################################################################
10220 23:07:31.234728
10221 23:07:31.465090 01700000 ################################################################
10222 23:07:31.465225
10223 23:07:31.709288 01780000 ################################################################
10224 23:07:31.709421
10225 23:07:31.954416 01800000 ################################################################
10226 23:07:31.954551
10227 23:07:32.185220 01880000 ################################################################
10228 23:07:32.185351
10229 23:07:32.439530 01900000 ################################################################
10230 23:07:32.439658
10231 23:07:32.678781 01980000 ################################################################
10232 23:07:32.678910
10233 23:07:32.918225 01a00000 ################################################################
10234 23:07:32.918367
10235 23:07:33.156649 01a80000 ################################################################
10236 23:07:33.156786
10237 23:07:33.401796 01b00000 ################################################################
10238 23:07:33.401937
10239 23:07:33.637985 01b80000 ################################################################
10240 23:07:33.638131
10241 23:07:33.881516 01c00000 ################################################################
10242 23:07:33.881681
10243 23:07:34.119985 01c80000 ################################################################
10244 23:07:34.120144
10245 23:07:34.367659 01d00000 ################################################################
10246 23:07:34.367852
10247 23:07:34.628501 01d80000 ################################################################
10248 23:07:34.628632
10249 23:07:34.888451 01e00000 ################################################################
10250 23:07:34.888590
10251 23:07:35.159688 01e80000 ################################################################
10252 23:07:35.159824
10253 23:07:35.424826 01f00000 ################################################################
10254 23:07:35.424964
10255 23:07:35.697566 01f80000 ################################################################
10256 23:07:35.697696
10257 23:07:35.967313 02000000 ################################################################
10258 23:07:35.967452
10259 23:07:36.219628 02080000 ################################################################
10260 23:07:36.219834
10261 23:07:36.446982 02100000 ################################################################
10262 23:07:36.447112
10263 23:07:36.704942 02180000 ################################################################
10264 23:07:36.705074
10265 23:07:36.968373 02200000 ################################################################
10266 23:07:36.968509
10267 23:07:37.215362 02280000 ################################################################
10268 23:07:37.215489
10269 23:07:37.479093 02300000 ################################################################
10270 23:07:37.479223
10271 23:07:37.719338 02380000 ################################################################
10272 23:07:37.719468
10273 23:07:37.953045 02400000 ################################################################
10274 23:07:37.953181
10275 23:07:38.181613 02480000 ################################################################
10276 23:07:38.181742
10277 23:07:38.427335 02500000 ################################################################
10278 23:07:38.427467
10279 23:07:38.657843 02580000 ################################################################
10280 23:07:38.657983
10281 23:07:38.888041 02600000 ################################################################
10282 23:07:38.888182
10283 23:07:39.133336 02680000 ################################################################
10284 23:07:39.133472
10285 23:07:39.364638 02700000 ################################################################
10286 23:07:39.364768
10287 23:07:39.603226 02780000 ################################################################
10288 23:07:39.603417
10289 23:07:39.866828 02800000 ################################################################
10290 23:07:39.866960
10291 23:07:40.113493 02880000 ################################################################
10292 23:07:40.113625
10293 23:07:40.348435 02900000 ################################################################
10294 23:07:40.348570
10295 23:07:40.575914 02980000 ################################################################
10296 23:07:40.576087
10297 23:07:40.813890 02a00000 ################################################################
10298 23:07:40.814026
10299 23:07:41.049279 02a80000 ################################################################
10300 23:07:41.049429
10301 23:07:41.275058 02b00000 ################################################################
10302 23:07:41.275211
10303 23:07:41.525552 02b80000 ################################################################
10304 23:07:41.525699
10305 23:07:41.765570 02c00000 ################################################################
10306 23:07:41.765747
10307 23:07:42.014295 02c80000 ################################################################
10308 23:07:42.014457
10309 23:07:42.256568 02d00000 ################################################################
10310 23:07:42.256725
10311 23:07:42.491602 02d80000 ################################################################
10312 23:07:42.491791
10313 23:07:42.719466 02e00000 ################################################################
10314 23:07:42.719604
10315 23:07:42.957133 02e80000 ################################################################
10316 23:07:42.957266
10317 23:07:43.202366 02f00000 ################################################################
10318 23:07:43.202525
10319 23:07:43.442640 02f80000 ################################################################
10320 23:07:43.442796
10321 23:07:43.670535 03000000 ################################################################
10322 23:07:43.670676
10323 23:07:43.689695 03080000 ###### done.
10324 23:07:43.689801
10325 23:07:43.692797 The bootfile was 50902214 bytes long.
10326 23:07:43.692880
10327 23:07:43.696981 Sending tftp read request... done.
10328 23:07:43.697063
10329 23:07:43.699271 Waiting for the transfer...
10330 23:07:43.699353
10331 23:07:43.702619 00000000 # done.
10332 23:07:43.702730
10333 23:07:43.708998 Command line loaded dynamically from TFTP file: 12395342/tftp-deploy-964i7d0v/kernel/cmdline
10334 23:07:43.709086
10335 23:07:43.722510 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10336 23:07:43.722614
10337 23:07:43.722706 Loading FIT.
10338 23:07:43.725483
10339 23:07:43.725593 Image ramdisk-1 has 39372515 bytes.
10340 23:07:43.725688
10341 23:07:43.728574 Image fdt-1 has 47278 bytes.
10342 23:07:43.728707
10343 23:07:43.732771 Image kernel-1 has 11480388 bytes.
10344 23:07:43.732930
10345 23:07:43.742085 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10346 23:07:43.742237
10347 23:07:43.758878 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10348 23:07:43.759231
10349 23:07:43.765808 Choosing best match conf-1 for compat google,spherion-rev2.
10350 23:07:43.769008
10351 23:07:43.773345 Connected to device vid:did:rid of 1ae0:0028:00
10352 23:07:43.780538
10353 23:07:43.783583 tpm_get_response: command 0x17b, return code 0x0
10354 23:07:43.784063
10355 23:07:43.787325 ec_init: CrosEC protocol v3 supported (256, 248)
10356 23:07:43.791361
10357 23:07:43.794604 tpm_cleanup: add release locality here.
10358 23:07:43.795024
10359 23:07:43.795353 Shutting down all USB controllers.
10360 23:07:43.798214
10361 23:07:43.798629 Removing current net device
10362 23:07:43.798981
10363 23:07:43.804316 Exiting depthcharge with code 4 at timestamp: 57622833
10364 23:07:43.804764
10365 23:07:43.807834 LZMA decompressing kernel-1 to 0x821a6718
10366 23:07:43.808259
10367 23:07:43.811659 LZMA decompressing kernel-1 to 0x40000000
10368 23:07:45.246889
10369 23:07:45.247019 jumping to kernel
10370 23:07:45.247869 end: 2.2.4 bootloader-commands (duration 00:00:30) [common]
10371 23:07:45.247976 start: 2.2.5 auto-login-action (timeout 00:03:55) [common]
10372 23:07:45.248052 Setting prompt string to ['Linux version [0-9]']
10373 23:07:45.248155 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10374 23:07:45.248256 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10375 23:07:45.328889
10376 23:07:45.331984 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10377 23:07:45.335828 start: 2.2.5.1 login-action (timeout 00:03:55) [common]
10378 23:07:45.336291 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10379 23:07:45.336651 Setting prompt string to []
10380 23:07:45.337109 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10381 23:07:45.337785 Using line separator: #'\n'#
10382 23:07:45.338254 No login prompt set.
10383 23:07:45.338803 Parsing kernel messages
10384 23:07:45.339291 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10385 23:07:45.340087 [login-action] Waiting for messages, (timeout 00:03:55)
10386 23:07:45.355230 [ 0.000000] Linux version 6.1.67-cip12-rt7 (KernelCI@build-j59954-arm64-gcc-10-defconfig-arm64-chromebook-nblph) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023
10387 23:07:45.358447 [ 0.000000] random: crng init done
10388 23:07:45.364849 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10389 23:07:45.368320 [ 0.000000] efi: UEFI not found.
10390 23:07:45.375151 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10391 23:07:45.384568 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10392 23:07:45.394325 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10393 23:07:45.401511 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10394 23:07:45.407435 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10395 23:07:45.414118 [ 0.000000] printk: bootconsole [mtk8250] enabled
10396 23:07:45.420889 [ 0.000000] NUMA: No NUMA configuration found
10397 23:07:45.427864 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10398 23:07:45.433873 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]
10399 23:07:45.434166 [ 0.000000] Zone ranges:
10400 23:07:45.440655 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10401 23:07:45.444310 [ 0.000000] DMA32 empty
10402 23:07:45.450623 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10403 23:07:45.454419 [ 0.000000] Movable zone start for each node
10404 23:07:45.457425 [ 0.000000] Early memory node ranges
10405 23:07:45.464540 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10406 23:07:45.470661 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10407 23:07:45.476934 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10408 23:07:45.483285 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10409 23:07:45.490355 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10410 23:07:45.496885 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10411 23:07:45.553819 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10412 23:07:45.559884 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10413 23:07:45.567040 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10414 23:07:45.570835 [ 0.000000] psci: probing for conduit method from DT.
10415 23:07:45.577145 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10416 23:07:45.580173 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10417 23:07:45.586652 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10418 23:07:45.589692 [ 0.000000] psci: SMC Calling Convention v1.2
10419 23:07:45.596248 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10420 23:07:45.600100 [ 0.000000] Detected VIPT I-cache on CPU0
10421 23:07:45.606218 [ 0.000000] CPU features: detected: GIC system register CPU interface
10422 23:07:45.612934 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10423 23:07:45.619310 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10424 23:07:45.626040 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10425 23:07:45.636377 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10426 23:07:45.642538 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10427 23:07:45.646303 [ 0.000000] alternatives: applying boot alternatives
10428 23:07:45.653697 [ 0.000000] Fallback order for Node 0: 0
10429 23:07:45.659585 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10430 23:07:45.662352 [ 0.000000] Policy zone: Normal
10431 23:07:45.676249 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10432 23:07:45.685366 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10433 23:07:45.698140 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10434 23:07:45.707998 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10435 23:07:45.714468 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10436 23:07:45.717664 <6>[ 0.000000] software IO TLB: area num 8.
10437 23:07:45.774405 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10438 23:07:45.923847 <6>[ 0.000000] Memory: 7930268K/8385536K available (17984K kernel code, 4116K rwdata, 18184K rodata, 8448K init, 615K bss, 422500K reserved, 32768K cma-reserved)
10439 23:07:45.929853 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10440 23:07:45.936343 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10441 23:07:45.939851 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10442 23:07:45.946713 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10443 23:07:45.952911 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10444 23:07:45.956438 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10445 23:07:45.966522 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10446 23:07:45.972811 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10447 23:07:45.979563 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10448 23:07:45.985907 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10449 23:07:45.989519 <6>[ 0.000000] GICv3: 608 SPIs implemented
10450 23:07:45.992891 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10451 23:07:45.999398 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10452 23:07:46.002655 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10453 23:07:46.009241 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10454 23:07:46.022195 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10455 23:07:46.035765 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10456 23:07:46.041676 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10457 23:07:46.050302 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10458 23:07:46.062800 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10459 23:07:46.069523 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10460 23:07:46.076142 <6>[ 0.009231] Console: colour dummy device 80x25
10461 23:07:46.086450 <6>[ 0.013954] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10462 23:07:46.092618 <6>[ 0.024396] pid_max: default: 32768 minimum: 301
10463 23:07:46.096124 <6>[ 0.029268] LSM: Security Framework initializing
10464 23:07:46.102867 <6>[ 0.034206] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10465 23:07:46.112442 <6>[ 0.042069] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10466 23:07:46.122659 <6>[ 0.051473] cblist_init_generic: Setting adjustable number of callback queues.
10467 23:07:46.126161 <6>[ 0.058917] cblist_init_generic: Setting shift to 3 and lim to 1.
10468 23:07:46.136062 <6>[ 0.065293] cblist_init_generic: Setting adjustable number of callback queues.
10469 23:07:46.142341 <6>[ 0.072721] cblist_init_generic: Setting shift to 3 and lim to 1.
10470 23:07:46.146038 <6>[ 0.079201] rcu: Hierarchical SRCU implementation.
10471 23:07:46.152528 <6>[ 0.079203] rcu: Max phase no-delay instances is 1000.
10472 23:07:46.159095 <6>[ 0.079226] printk: bootconsole [mtk8250] printing thread started
10473 23:07:46.165508 <6>[ 0.097520] EFI services will not be available.
10474 23:07:46.168528 <6>[ 0.097718] smp: Bringing up secondary CPUs ...
10475 23:07:46.175144 <6>[ 0.098023] Detected VIPT I-cache on CPU1
10476 23:07:46.182123 <6>[ 0.098090] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10477 23:07:46.188618 <6>[ 0.098120] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10478 23:07:46.198188 <6>[ 0.126022] Detected VIPT I-cache on CPU2
10479 23:07:46.207786 <6>[ 0.126069] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10480 23:07:46.214233 <6>[ 0.126085] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10481 23:07:46.217787 <6>[ 0.126340] Detected VIPT I-cache on CPU3
10482 23:07:46.224214 <6>[ 0.126386] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10483 23:07:46.230701 <6>[ 0.126400] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10484 23:07:46.237927 <6>[ 0.126710] CPU features: detected: Spectre-v4
10485 23:07:46.240961 <6>[ 0.126716] CPU features: detected: Spectre-BHB
10486 23:07:46.244689 <6>[ 0.126720] Detected PIPT I-cache on CPU4
10487 23:07:46.250769 <6>[ 0.126779] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10488 23:07:46.260582 <6>[ 0.126795] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10489 23:07:46.263597 <6>[ 0.127086] Detected PIPT I-cache on CPU5
10490 23:07:46.270140 <6>[ 0.127148] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10491 23:07:46.276719 <6>[ 0.127164] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10492 23:07:46.280214 <6>[ 0.127439] Detected PIPT I-cache on CPU6
10493 23:07:46.290509 <6>[ 0.127502] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10494 23:07:46.296559 <6>[ 0.127518] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10495 23:07:46.300319 <6>[ 0.127807] Detected PIPT I-cache on CPU7
10496 23:07:46.306371 <6>[ 0.127870] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10497 23:07:46.313062 <6>[ 0.127886] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10498 23:07:46.319388 <6>[ 0.127932] smp: Brought up 1 node, 8 CPUs
10499 23:07:46.323088 <6>[ 0.127936] SMP: Total of 8 processors activated.
10500 23:07:46.329370 <6>[ 0.127939] CPU features: detected: 32-bit EL0 Support
10501 23:07:46.335776 <6>[ 0.127941] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10502 23:07:46.342357 <6>[ 0.127943] CPU features: detected: Common not Private translations
10503 23:07:46.349331 <6>[ 0.127945] CPU features: detected: CRC32 instructions
10504 23:07:46.355099 <6>[ 0.127948] CPU features: detected: RCpc load-acquire (LDAPR)
10505 23:07:46.361806 <6>[ 0.127949] CPU features: detected: LSE atomic instructions
10506 23:07:46.365356 <6>[ 0.127951] CPU features: detected: Privileged Access Never
10507 23:07:46.371896 <6>[ 0.127952] CPU features: detected: RAS Extension Support
10508 23:07:46.378472 <6>[ 0.127955] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10509 23:07:46.385936 <6>[ 0.128025] CPU: All CPU(s) started at EL2
10510 23:07:46.388579 <6>[ 0.128027] alternatives: applying system-wide alternatives
10511 23:07:46.391574 <6>[ 0.141106] devtmpfs: initialized
10512 23:07:46.401589 <6>[ 0.147397] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10513 23:07:46.431472 <���V���ѕɕ���}%9Q��ɽѽ����2�����5S�<6>[ 0<.364832] printk: console [ttyS0] printing thread started
10514 23:07:46.437893 6<6>[ 0.364853] printk: console [ttyS0] enabled
10515 23:07:46.444932 >[ 0.228777] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10516 23:07:46.452521 <6>[ 0.364858] printk: bootconsole [mtk8250] disabled
10517 23:07:46.458801 <6>[ 0.382946] printk: bootconsole [mtk8250] printing thread stopped
10518 23:07:46.462338 <6>[ 0.384177] SuperH (H)SCI(F) driver initialized
10519 23:07:46.468663 <6>[ 0.384659] msm_serial: driver initialized
10520 23:07:46.474961 <6>[ 0.389275] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10521 23:07:46.485891 <6>[ 0.389304] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10522 23:07:46.496108 <6>[ 0.389333] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10523 23:07:46.501924 <6>[ 0.389363] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10524 23:07:46.520130 <6>[ 0.389384] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10525 23:07:46.521274 <6>[ 0.389411] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10526 23:07:46.540291 <6>[ 0.389439] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10527 23:07:46.545865 <6>[ 0.389562] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10528 23:07:46.550111 <6>[ 0.389594] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10529 23:07:46.556368 <6>[ 0.400443] loop: module loaded
10530 23:07:46.561998 <6>[ 0.403035] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10531 23:07:46.565879 <4>[ 0.419599] mtk-pmic-keys: Failed to locate of_node [id: -1]
10532 23:07:46.568346 <6>[ 0.420488] megasas: 07.719.03.00-rc1
10533 23:07:46.571704 <6>[ 0.432884] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10534 23:07:46.575423 <6>[ 0.432992] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10535 23:07:46.581122 <6>[ 0.444830] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10536 23:07:46.595057 <6>[ 0.503198] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10537 23:07:47.896174 <6>[ 1.827783] Freeing initrd memory: 38444K
10538 23:07:47.904483 <6>[ 1.833956] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10539 23:07:47.911183 <6>[ 1.838553] tun: Universal TUN/TAP device driver, 1.6
10540 23:07:47.915238 <6>[ 1.839296] thunder_xcv, ver 1.0
10541 23:07:47.917561 <6>[ 1.839317] thunder_bgx, ver 1.0
10542 23:07:47.920875 <6>[ 1.839330] nicpf, ver 1.0
10543 23:07:47.927543 <6>[ 1.840380] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10544 23:07:47.933893 <6>[ 1.840383] hns3: Copyright (c) 2017 Huawei Corporation.
10545 23:07:47.937627 <6>[ 1.840408] hclge is initializing
10546 23:07:47.944271 <6>[ 1.840420] e1000: Intel(R) PRO/1000 Network Driver
10547 23:07:47.947885 <6>[ 1.840422] e1000: Copyright (c) 1999-2006 Intel Corporation.
10548 23:07:47.954939 <6>[ 1.840439] e1000e: Intel(R) PRO/1000 Network Driver
10549 23:07:47.961288 <6>[ 1.840441] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10550 23:07:47.964649 <6>[ 1.840456] igb: Intel(R) Gigabit Ethernet Network Driver
10551 23:07:47.971089 <6>[ 1.840458] igb: Copyright (c) 2007-2014 Intel Corporation.
10552 23:07:47.977919 <6>[ 1.840473] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10553 23:07:47.984753 <6>[ 1.840475] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10554 23:07:47.988308 <6>[ 1.840764] sky2: driver version 1.30
10555 23:07:47.991939 <6>[ 1.841847] VFIO - User Level meta-driver version: 0.3
10556 23:07:47.998164 <6>[ 1.844667] usbcore: registered new interface driver usb-storage
10557 23:07:48.004745 <6>[ 1.844850] usbcore: registered new device driver onboard-usb-hub
10558 23:07:48.011517 <6>[ 1.847611] mt6397-rtc mt6359-rtc: registered as rtc0
10559 23:07:48.021295 <6>[ 1.847762] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-27T23:08:15 UTC (1703718495)
10560 23:07:48.024435 <6>[ 1.848368] i2c_dev: i2c /dev entries driver
10561 23:07:48.030754 <6>[ 1.855525] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10562 23:07:48.037713 <6>[ 1.870511] cpu cpu0: EM: created perf domain
10563 23:07:48.040908 <6>[ 1.870832] cpu cpu4: EM: created perf domain
10564 23:07:48.047440 <6>[ 1.872111] sdhci: Secure Digital Host Controller Interface driver
10565 23:07:48.054376 <6>[ 1.872112] sdhci: Copyright(c) Pierre Ossman
10566 23:07:48.057750 <6>[ 1.872468] Synopsys Designware Multimedia Card Interface Driver
10567 23:07:48.065041 <6>[ 1.872837] sdhci-pltfm: SDHCI platform and OF driver helper
10568 23:07:48.070714 <6>[ 1.875555] ledtrig-cpu: registered to indicate activity on CPUs
10569 23:07:48.077305 <6>[ 1.876218] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10570 23:07:48.081262 <6>[ 1.876226] mmc0: CQHCI version 5.10
10571 23:07:48.087558 <6>[ 1.876502] usbcore: registered new interface driver usbhid
10572 23:07:48.090600 <6>[ 1.876504] usbhid: USB HID core driver
10573 23:07:48.097082 <6>[ 1.876618] spi_master spi0: will run message pump with realtime priority
10574 23:07:48.110187 <6>[ 1.908520] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10575 23:07:48.124051 <6>[ 1.910668] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10576 23:07:48.130141 <6>[ 1.911688] cros-ec-spi spi0.0: Chrome EC device registered
10577 23:07:48.140104 <6>[ 1.928028] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10578 23:07:48.146474 <6>[ 1.930298] NET: Registered PF_PACKET protocol family
10579 23:07:48.149883 <6>[ 1.930394] 9pnet: Installing 9P2000 support
10580 23:07:48.152836 <5>[ 1.930435] Key type dns_resolver registered
10581 23:07:48.160270 <6>[ 1.930814] registered taskstats version 1
10582 23:07:48.162797 <5>[ 1.930830] Loading compiled-in X.509 certificates
10583 23:07:48.173314 <4>[ 1.953214] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10584 23:07:48.183183 <4>[ 1.953359] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10585 23:07:48.189427 <3>[ 1.953369] debugfs: File 'uA_load' in directory '/' already present!
10586 23:07:48.195949 <3>[ 1.953378] debugfs: File 'min_uV' in directory '/' already present!
10587 23:07:48.202600 <3>[ 1.953381] debugfs: File 'max_uV' in directory '/' already present!
10588 23:07:48.212922 <3>[ 1.953384] debugfs: File 'constraint_flags' in directory '/' already present!
10589 23:07:48.219321 <3>[ 1.955375] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10590 23:07:48.225791 <6>[ 1.963839] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10591 23:07:48.232247 <6>[ 1.964430] xhci-mtk 11200000.usb: xHCI Host Controller
10592 23:07:48.239338 <6>[ 1.964452] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10593 23:07:48.249196 <6>[ 1.964669] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10594 23:07:48.255624 <6>[ 1.964722] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10595 23:07:48.261791 <6>[ 1.964815] xhci-mtk 11200000.usb: xHCI Host Controller
10596 23:07:48.268957 <6>[ 1.964821] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10597 23:07:48.275928 <6>[ 1.964828] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10598 23:07:48.278620 <6>[ 1.965207] hub 1-0:1.0: USB hub found
10599 23:07:48.285166 <6>[ 1.965225] hub 1-0:1.0: 1 port detected
10600 23:07:48.292252 <6>[ 1.965398] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10601 23:07:48.295597 <6>[ 1.965641] hub 2-0:1.0: USB hub found
10602 23:07:48.302096 <6>[ 1.965657] hub 2-0:1.0: 1 port detected
10603 23:07:48.305857 <6>[ 1.968555] mtk-msdc 11f70000.mmc: Got CD GPIO
10604 23:07:48.308308 <6>[ 1.980166] mmc0: Command Queue Engine enabled
10605 23:07:48.315048 <6>[ 1.980179] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10606 23:07:48.321836 <6>[ 1.980711] mmcblk0: mmc0:0001 DA4128 116 GiB
10607 23:07:48.328356 <6>[ 1.983809] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10608 23:07:48.338824 <6>[ 1.983817] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10609 23:07:48.345588 <4>[ 1.983975] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10610 23:07:48.351707 <6>[ 1.984107] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10611 23:07:48.361831 <6>[ 1.984613] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10612 23:07:48.367949 <6>[ 1.984617] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10613 23:07:48.375111 <6>[ 1.984741] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10614 23:07:48.384483 <6>[ 1.984753] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10615 23:07:48.391182 <6>[ 1.984757] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10616 23:07:48.401181 <6>[ 1.984762] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10617 23:07:48.404316 <6>[ 1.985179] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10618 23:07:48.411219 <6>[ 1.986011] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10619 23:07:48.417858 <6>[ 1.986676] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10620 23:07:48.424034 <6>[ 1.986878] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10621 23:07:48.434428 <6>[ 1.986897] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10622 23:07:48.443931 <6>[ 1.986904] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10623 23:07:48.450721 <6>[ 1.986911] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10624 23:07:48.460673 <6>[ 1.986917] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10625 23:07:48.467301 <6>[ 1.986923] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10626 23:07:48.476893 <6>[ 1.986930] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10627 23:07:48.483563 <6>[ 1.986937] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10628 23:07:48.493724 <6>[ 1.986943] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10629 23:07:48.499968 <6>[ 1.986949] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10630 23:07:48.510654 <6>[ 1.986956] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10631 23:07:48.516590 <6>[ 1.986962] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10632 23:07:48.526910 <6>[ 1.986968] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10633 23:07:48.532965 <6>[ 1.986975] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10634 23:07:48.543065 <6>[ 1.986981] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10635 23:07:48.549775 <6>[ 1.987625] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10636 23:07:48.556592 <6>[ 1.988498] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10637 23:07:48.562958 <6>[ 1.989051] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10638 23:07:48.570007 <6>[ 1.989728] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10639 23:07:48.576366 <6>[ 1.990410] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10640 23:07:48.585593 <6>[ 1.990600] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10641 23:07:48.592533 <6>[ 1.990613] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10642 23:07:48.602538 <6>[ 1.990619] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10643 23:07:48.612098 <6>[ 1.990624] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10644 23:07:48.622583 <6>[ 1.990629] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10645 23:07:48.632455 <6>[ 1.990635] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10646 23:07:48.638849 <6>[ 1.990640] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10647 23:07:48.648751 <6>[ 1.990645] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10648 23:07:48.658280 <6>[ 1.990650] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10649 23:07:48.668816 <6>[ 1.990657] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10650 23:07:48.678594 <6>[ 1.990661] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10651 23:07:48.688111 <6>[ 1.991487] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10652 23:07:48.695108 <6>[ 2.381593] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10653 23:07:48.698465 <6>[ 2.538577] hub 1-1:1.0: USB hub found
10654 23:07:48.701833 <6>[ 2.538995] hub 1-1:1.0: 4 ports detected
10655 23:07:48.708079 <6>[ 2.543261] hub 1-1:1.0: USB hub found
10656 23:07:48.711150 <6>[ 2.543633] hub 1-1:1.0: 4 ports detected
10657 23:07:48.739727 <6>[ 2.665831] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10658 23:07:48.760154 <6>[ 2.691611] hub 2-1:1.0: USB hub found
10659 23:07:48.763264 <6>[ 2.692076] hub 2-1:1.0: 3 ports detected
10660 23:07:48.766715 <6>[ 2.695534] hub 2-1:1.0: USB hub found
10661 23:07:48.769980 <6>[ 2.695898] hub 2-1:1.0: 3 ports detected
10662 23:07:48.931995 <6>[ 2.857731] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10663 23:07:49.052792 <6>[ 2.983331] hub 1-1.1:1.0: USB hub found
10664 23:07:49.056001 <6>[ 2.983396] hub 1-1.1:1.0: 4 ports detected
10665 23:07:49.163839 <6>[ 3.089609] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10666 23:07:49.284766 <6>[ 3.216813] hub 1-1.4:1.0: USB hub found
10667 23:07:49.287704 <6>[ 3.217139] hub 1-1.4:1.0: 2 ports detected
10668 23:07:49.291253 <6>[ 3.220462] hub 1-1.4:1.0: USB hub found
10669 23:07:49.297405 <6>[ 3.220780] hub 1-1.4:1.0: 2 ports detected
10670 23:07:49.367782 <6>[ 3.293781] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10671 23:07:49.583794 <6>[ 3.509786] usb 1-1.4.1: new high-speed USB device number 6 using xhci-mtk
10672 23:07:49.767518 <6>[ 3.693803] usb 1-1.4.2: new high-speed USB device number 7 using xhci-mtk
10673 23:08:00.340395 <6>[ 14.274866] ALSA device list:
10674 23:08:00.346803 <6>[ 14.274890] No soundcards found.
10675 23:08:00.349972 <6>[ 14.279462] Freeing unused kernel memory: 8448K
10676 23:08:00.354061 <6>[ 14.279624] Run /init as init process
10677 23:08:00.379387 <6>[ 14.312662] NET: Registered PF_INET6 protocol family
10678 23:08:00.382823 <6>[ 14.313594] Segment Routing with IPv6
10679 23:08:00.389107 <6>[ 14.313608] In-situ OAM (IOAM) with IPv6
10680 23:08:00.393383
10681 23:08:00.419604 Welcome to [1mDebian GNU/Linux 11 (bullseye)<30>[ 14.329665] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10682 23:08:00.420208 [0m!
10683 23:08:00.420573
10684 23:08:00.425528 <30>[ 14.330240] systemd[1]: Detected architecture arm64.
10685 23:08:00.432249 <30>[ 14.364211] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10686 23:08:00.590722 <30>[ 14.519505] systemd[1]: Queued start job for default target Graphical Interface.
10687 23:08:00.608087 [[0;32m OK [0m] Created slic<30>[ 14.538819] systemd[1]: Created slice system-getty.slice.
10688 23:08:00.611451 e [0;1;39msystem-getty.slice[0m.
10689 23:08:00.634644 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 14.562065] systemd[1]: Created slice system-modprobe.slice.
10690 23:08:00.635203 m-modprobe.slice[0m.
10691 23:08:00.658478 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 14.586270] systemd[1]: Created slice system-serial\x2dgetty.slice.
10692 23:08:00.661731 m-serial\x2dgetty.slice[0m.
10693 23:08:00.680767 [[0;32m OK [0m] Created slic<30>[ 14.611023] systemd[1]: Created slice User and Session Slice.
10694 23:08:00.683813 e [0;1;39mUser and Session Slice[0m.
10695 23:08:00.706367 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 14.634102] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10696 23:08:00.709695 ssword …ts to Console Directory Watch[0m.
10697 23:08:00.734582 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 14.661957] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10698 23:08:00.737850 sword R…uests to Wall Directory Watch[0m.
10699 23:08:00.761745 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 14.685883] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10700 23:08:00.768372 <30>[ 14.686094] systemd[1]: Reached target Local Encrypted Volumes.
10701 23:08:00.771513 l Encrypted Volumes[0m.
10702 23:08:00.791578 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 14.721943] systemd[1]: Reached target Paths.
10703 23:08:00.792126 s[0m.
10704 23:08:00.814288 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 14.741809] systemd[1]: Reached target Remote File Systems.
10705 23:08:00.814827 te File Systems[0m.
10706 23:08:00.835082 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 14.766156] systemd[1]: Reached target Slices.
10707 23:08:00.835651 es[0m.
10708 23:08:00.854894 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 14.785809] systemd[1]: Reached target Swap.
10709 23:08:00.855434 [0m.
10710 23:08:00.878803 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 14.806344] systemd[1]: Listening on initctl Compatibility Named Pipe.
10711 23:08:00.882601 l Compatibility Named Pipe[0m.
10712 23:08:00.891832 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 14.821677] systemd[1]: Listening on Journal Audit Socket.
10713 23:08:00.895140 l Audit Socket[0m.
10714 23:08:00.914991 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 14.842340] systemd[1]: Listening on Journal Socket (/dev/log).
10715 23:08:00.915555 l Socket (/dev/log)[0m.
10716 23:08:00.935847 [[0;32m OK [0m] Listening on<30>[ 14.867064] systemd[1]: Listening on Journal Socket.
10717 23:08:00.940270 [0;1;39mJournal Socket[0m.
10718 23:08:00.958957 [[0;32m OK [0m] Listening on [0;1;39mNetwor<30>[ 14.886551] systemd[1]: Listening on Network Service Netlink Socket.
10719 23:08:00.962040 k Service Netlink Socket[0m.
10720 23:08:00.983507 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 14.910429] systemd[1]: Listening on udev Control Socket.
10721 23:08:00.984245 ontrol Socket[0m.
10722 23:08:01.004429 [[0;32m OK [0m] Listening on<30>[ 14.934890] systemd[1]: Listening on udev Kernel Socket.
10723 23:08:01.007266 [0;1;39mudev Kernel Socket[0m.
10724 23:08:01.062833 Mounting [0;1;39mHuge Pages File Syste<30>[ 14.990011] systemd[1]: Mounting Huge Pages File System...
10725 23:08:01.063387 m[0m...
10726 23:08:01.081217 Mounting [0;1;39mPOSIX<30>[ 15.011649] systemd[1]: Mounting POSIX Message Queue File System...
10727 23:08:01.083892 Message Queue File System[0m...
10728 23:08:01.105441 Mountin<30>[ 15.036375] systemd[1]: Mounting Kernel Debug File System...
10729 23:08:01.108381 g [0;1;39mKernel Debug File System[0m...
10730 23:08:01.134675 <30>[ 15.061893] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10731 23:08:01.166676 Starting [0;1;39mCreate list of st…o<30>[ 15.094497] systemd[1]: Starting Create list of static device nodes for the current kernel...
10732 23:08:01.170335 des for the current kernel[0m...
10733 23:08:01.195827 Starting [0;1;39mLoad <30>[ 15.126544] systemd[1]: Starting Load Kernel Module configfs...
10734 23:08:01.199558 Kernel Module configfs[0m...
10735 23:08:01.224296 Starting [0;1;39mLoad <30>[ 15.154902] systemd[1]: Starting Load Kernel Module drm...
10736 23:08:01.227291 Kernel Module drm[0m...
10737 23:08:01.248510 <30>[ 15.174306] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10738 23:08:01.260360 Starting [0;1;39mJourn<30>[ 15.191364] systemd[1]: Starting Journal Service...
10739 23:08:01.260901 al Service[0m...
10740 23:08:01.285043 Starting [0;1;39mLoad <30>[ 15.215254] systemd[1]: Starting Load Kernel Modules...
10741 23:08:01.287455 Kernel Modules[0m...
10742 23:08:01.312421 Starting [0;1;39mRemou<30>[ 15.242935] systemd[1]: Starting Remount Root and Kernel File Systems...
10743 23:08:01.319054 nt Root and Kernel File Systems[0m...
10744 23:08:01.343196 Starting [0;1;39mColdplug All udev Dev<30>[ 15.270512] systemd[1]: Starting Coldplug All udev Devices...
10745 23:08:01.343795 ices[0m...
10746 23:08:01.359296 [[0;32m OK [<30>[ 15.292958] systemd[1]: Started Journal Service.
10747 23:08:01.365390 0m] Started [0;1;39mJournal Service[0m.
10748 23:08:01.381437 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10749 23:08:01.403357 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10750 23:08:01.416455 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10751 23:08:01.436936 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10752 23:08:01.454378 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10753 23:08:01.472879 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10754 23:08:01.489728 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10755 23:08:01.509332 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10756 23:08:01.523508 See 'systemctl status systemd-remount-fs.service' for details.
10757 23:08:01.585022 Mounting [0;1;39mKernel Configuration File System[0m...
10758 23:08:01.604978 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10759 23:08:01.622790 <46>[ 15.549595] systemd-journald[192]: Received client request to flush runtime journal.
10760 23:08:01.634309 Starting [0;1;39mLoad/Save Random Seed[0m...
10761 23:08:01.654542 Starting [0;1;39mApply Kernel Variables[0m...
10762 23:08:01.674733 Starting [0;1;39mCreate System Users[0m...
10763 23:08:01.693562 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10764 23:08:01.712694 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10765 23:08:01.732411 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10766 23:08:01.749976 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10767 23:08:01.769215 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10768 23:08:01.789983 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10769 23:08:01.844863 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10770 23:08:01.866721 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10771 23:08:01.880163 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10772 23:08:01.896313 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10773 23:08:01.951944 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10774 23:08:01.976557 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10775 23:08:01.998011 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10776 23:08:02.018247 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10777 23:08:02.082186 Starting [0;1;39mNetwork Service[0m...
10778 23:08:02.109457 Starting [0;1;39mNetwork Time Synchronization[0m...
10779 23:08:02.133134 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10780 23:08:02.154558 <6>[ 16.084267] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10781 23:08:02.157803 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10782 23:08:02.170987 <6>[ 16.100262] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10783 23:08:02.176761 <6>[ 16.100339] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10784 23:08:02.187518 <6>[ 16.100351] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10785 23:08:02.193543 <6>[ 16.112882] remoteproc remoteproc0: scp is available
10786 23:08:02.197149 <6>[ 16.112977] remoteproc remoteproc0: powering up scp
10787 23:08:02.207064 [[0;32m OK [<6>[ 16.112983] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10788 23:08:02.212989 <6>[ 16.113016] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10789 23:08:02.216176 0m] Found device [0;1;39m/dev/ttyS0[0m.
10790 23:08:02.236012 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10791 23:08:02.252646 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10792 23:08:02.266310 <4>[ 16.196292] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10793 23:08:02.272790 <4>[ 16.200436] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10794 23:08:02.282633 <6>[ 16.200535] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10795 23:08:02.289169 <3>[ 16.205211] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10796 23:08:02.299310 <3>[ 16.205277] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10797 23:08:02.310368 [[0;32m OK [0m] Created slice [0;1;39msyste<3>[ 16.205290] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10798 23:08:02.320573 m-systemd\x2dbac<3>[ 16.217907] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10799 23:08:02.329764 klight.slice[0m<3>[ 16.217923] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10800 23:08:02.339757 <3>[ 16.217926] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10801 23:08:02.346353 <3>[ 16.217931] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10802 23:08:02.346869 .
10803 23:08:02.355776 <3>[ 16.217934] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10804 23:08:02.362845 <3>[ 16.219617] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10805 23:08:02.370177 <3>[ 16.219713] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10806 23:08:02.379771 [[0;32m OK [<3>[ 16.219718] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10807 23:08:02.390333 0m] Reached targ<3>[ 16.219722] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10808 23:08:02.400362 et [0;1;39mSyst<3>[ 16.219792] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10809 23:08:02.407400 <3>[ 16.219794] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10810 23:08:02.417468 <3>[ 16.219797] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10811 23:08:02.424163 em Time Set[0m.<3>[ 16.219802] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10812 23:08:02.433963 <3>[ 16.219804] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10813 23:08:02.434531
10814 23:08:02.440885 <3>[ 16.219820] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10815 23:08:02.444390 <6>[ 16.224293] mc: Linux media interface: v0.10
10816 23:08:02.453746 <4>[ 16.237315] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10817 23:08:02.463247 <4>[ 16.237315] Fallback method does not support PEC.
10818 23:08:02.467232 <6>[ 16.238749] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10819 23:08:02.477228 [[0;32m OK [0m] Reached targ<6>[ 16.238753] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10820 23:08:02.484432 et [0;1;39mSyst<6>[ 16.238767] remoteproc remoteproc0: remote processor scp is now up
10821 23:08:02.491271 <6>[ 16.241190] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10822 23:08:02.498668 <6>[ 16.241205] pci_bus 0000:00: root bus resource [bus 00-ff]
10823 23:08:02.504169 <6>[ 16.241215] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10824 23:08:02.518104 em Time Synchron<6>[ 16.241220] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10825 23:08:02.518623 ized[0m.
10826 23:08:02.524381 <6>[ 16.241263] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10827 23:08:02.532018 <6>[ 16.241285] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10828 23:08:02.535634 <6>[ 16.241399] pci 0000:00:00.0: supports D1 D2
10829 23:08:02.541789 <6>[ 16.241403] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10830 23:08:02.549075 <6>[ 16.245430] videodev: Linux video capture interface: v2.00
10831 23:08:02.559391 <3>[ 16.258358] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10832 23:08:02.565963 <6>[ 16.265769] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10833 23:08:02.572483 <6>[ 16.266652] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10834 23:08:02.579183 <6>[ 16.266700] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10835 23:08:02.586354 <6>[ 16.266726] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10836 23:08:02.593069 <6>[ 16.266744] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10837 23:08:02.600187 <6>[ 16.266889] pci 0000:01:00.0: supports D1 D2
10838 23:08:02.606902 <6>[ 16.266892] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10839 23:08:02.610315 <6>[ 16.270347] usbcore: registered new interface driver r8152
10840 23:08:02.616704 <6>[ 16.277564] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10841 23:08:02.627490 <6>[ 16.277638] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10842 23:08:02.633484 <6>[ 16.277647] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10843 23:08:02.644220 <6>[ 16.277666] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10844 23:08:02.650430 <6>[ 16.277682] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10845 23:08:02.656975 <6>[ 16.277699] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10846 23:08:02.663528 <6>[ 16.277717] pci 0000:00:00.0: PCI bridge to [bus 01]
10847 23:08:02.670087 <6>[ 16.277727] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10848 23:08:02.676733 <6>[ 16.277940] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10849 23:08:02.683966 <6>[ 16.279015] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10850 23:08:02.689752 <6>[ 16.279224] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10851 23:08:02.700168 <6>[ 16.288312] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10852 23:08:02.709792 <6>[ 16.288854] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10853 23:08:02.716585 <3>[ 16.305823] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10854 23:08:02.726538 <3>[ 16.306694] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10855 23:08:02.736779 <6>[ 16.334866] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10856 23:08:02.742734 <3>[ 16.336120] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10857 23:08:02.752941 <6>[ 16.361358] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10858 23:08:02.759709 <3>[ 16.374644] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10859 23:08:02.769026 <3>[ 16.375359] power_supply sbs-5-000b: driver failed to report `status' property: -6
10860 23:08:02.776237 <6>[ 16.385773] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10861 23:08:02.782782 <6>[ 16.389003] usbcore: registered new interface driver cdc_ether
10862 23:08:02.788959 <6>[ 16.395511] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10863 23:08:02.795662 <6>[ 16.409016] Bluetooth: Core ver 2.22
10864 23:08:02.799302 <6>[ 16.409189] NET: Registered PF_BLUETOOTH protocol family
10865 23:08:02.805596 <6>[ 16.409193] Bluetooth: HCI device and connection manager initialized
10866 23:08:02.811889 <6>[ 16.409229] Bluetooth: HCI socket layer initialized
10867 23:08:02.815207 <6>[ 16.409245] Bluetooth: L2CAP socket layer initialized
10868 23:08:02.822298 <6>[ 16.409261] usbcore: registered new interface driver r8153_ecm
10869 23:08:02.828276 <6>[ 16.409268] Bluetooth: SCO socket layer initialized
10870 23:08:02.838443 Starting [0;1;39mLoad/<5>[ 16.412464] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10871 23:08:02.848276 Save Screen …o<5>[ 16.423590] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10872 23:08:02.855365 <4>[ 16.423680] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10873 23:08:02.861546 <6>[ 16.423688] cfg80211: failed to load regulatory.db
10874 23:08:02.868383 <3>[ 16.424602] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 23:08:02.877550 f leds:white:kbd<3>[ 16.425485] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10876 23:08:02.888058 _backlight[0m..<6>[ 16.434124] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10877 23:08:02.888471 .
10878 23:08:02.901227 <6>[ 16.435699] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10879 23:08:02.904307 <6>[ 16.435814] usbcore: registered new interface driver uvcvideo
10880 23:08:02.914592 <3>[ 16.450460] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 23:08:02.924344 <3>[ 16.471604] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 23:08:02.930647 <6>[ 16.476574] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10883 23:08:02.937461 <6>[ 16.476777] usbcore: registered new interface driver btusb
10884 23:08:02.947527 <4>[ 16.477970] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10885 23:08:02.953972 <3>[ 16.477994] Bluetooth: hci0: Failed to load firmware file (-2)
10886 23:08:02.957023 <3>[ 16.477999] Bluetooth: hci0: Failed to set up firmware (-2)
10887 23:08:02.966952 <4>[ 16.478004] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10888 23:08:02.977853 <4>[ 16.479181] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10889 23:08:02.987167 <4>[ 16.479198] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10890 23:08:02.990123 <6>[ 16.530284] r8152 1-1.1.1:1.0 eth0: v1.12.13
10891 23:08:02.996513 <6>[ 16.539535] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10892 23:08:03.003857 <6>[ 16.539663] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10893 23:08:03.009690 <6>[ 16.543843] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10894 23:08:03.016590 <6>[ 16.557625] mt7921e 0000:01:00.0: ASIC revision: 79610010
10895 23:08:03.023397 <6>[ 16.653657] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10896 23:08:03.027139 <6>[ 16.653657]
10897 23:08:03.036148 <6>[ 16.925733] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10898 23:08:03.039712 Starting [0;1;39mNetwork Name Resolution[0m...
10899 23:08:03.064245 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10900 23:08:03.083944 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10901 23:08:03.232497 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10902 23:08:03.247102 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10903 23:08:03.267123 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10904 23:08:03.279224 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10905 23:08:03.298719 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10906 23:08:03.314829 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10907 23:08:03.327796 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10908 23:08:03.347593 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10909 23:08:03.360549 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10910 23:08:03.375587 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10911 23:08:03.395989 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10912 23:08:03.453651 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10913 23:08:03.487481 Starting [0;1;39mUser Login Management[0m...
10914 23:08:03.508100 Starting [0;1;39mPermit User Sessions[0m...
10915 23:08:03.528058 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10916 23:08:03.549637 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10917 23:08:03.573226 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10918 23:08:03.591621 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10919 23:08:03.615960 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10920 23:08:03.632493 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10921 23:08:03.648335 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10922 23:08:03.665523 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10923 23:08:03.680338 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10924 23:08:03.740407 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10925 23:08:03.769235 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10926 23:08:03.803993
10927 23:08:03.804545
10928 23:08:03.806816 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10929 23:08:03.807297
10930 23:08:03.810264 debian-bullseye-arm64 login: root (automatic login)
10931 23:08:03.810835
10932 23:08:03.811203
10933 23:08:03.827434 Linux debian-bullseye-arm64 6.1.67-cip12-rt7 #1 SMP PREEMPT Wed Dec 27 22:50:56 UTC 2023 aarch64
10934 23:08:03.828031
10935 23:08:03.833922 The programs included with the Debian GNU/Linux system are free software;
10936 23:08:03.847013 the exact distribution terms for each program are described in th<6>[ 17.776152] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10937 23:08:03.847580 e
10938 23:08:03.850089 individual files in /usr/share/doc/*/copyright.
10939 23:08:03.850541
10940 23:08:03.856771 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10941 23:08:03.859788 permitted by applicable law.
10942 23:08:03.861164 Matched prompt #10: / #
10944 23:08:03.862264 Setting prompt string to ['/ #']
10945 23:08:03.862727 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10947 23:08:03.863979 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10948 23:08:03.864475 start: 2.2.6 expect-shell-connection (timeout 00:03:37) [common]
10949 23:08:03.864859 Setting prompt string to ['/ #']
10950 23:08:03.865195 Forcing a shell prompt, looking for ['/ #']
10952 23:08:03.916252 / #
10953 23:08:03.916912 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10954 23:08:03.917332 Waiting using forced prompt support (timeout 00:02:30)
10955 23:08:03.923091
10956 23:08:03.924017 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10957 23:08:03.924547 start: 2.2.7 export-device-env (timeout 00:03:37) [common]
10958 23:08:03.925260 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10959 23:08:03.925769 end: 2.2 depthcharge-retry (duration 00:01:23) [common]
10960 23:08:03.926223 end: 2 depthcharge-action (duration 00:01:23) [common]
10961 23:08:03.926699 start: 3 lava-test-retry (timeout 00:08:13) [common]
10962 23:08:03.927247 start: 3.1 lava-test-shell (timeout 00:08:13) [common]
10963 23:08:03.927643 Using namespace: common
10965 23:08:04.028833 / # #
10966 23:08:04.029422 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10967 23:08:04.035818 #
10968 23:08:04.036620 Using /lava-12395342
10970 23:08:04.137780 / # export SHELL=/bin/sh
10971 23:08:04.144770 export SHELL=/bin/sh
10973 23:08:04.246370 / # . /lava-12395342/environment
10974 23:08:04.250065 . /lava-12395342/environment<6>[ 18.179674] IPv6: ADDRCONF(NETDEV_CHANGE): enxf4f5e850de0a: link becomes ready
10975 23:08:04.292338 <6>[ 18.180225] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10976 23:08:04.292892
10978 23:08:04.394585 / # /lava-12395342/bin/lava-test-runner /lava-12395342/0
10979 23:08:04.395206 Test shell timeout: 10s (minimum of the action and connection timeout)
10980 23:08:04.401237 /lava-12395342/bin/lava-test-runner /lava-12395342/0
10981 23:08:04.425712 + export TESTRUN_ID=0_v4l2-compliance-uvc
10982 23:08:04.428993 + cd /lava-12395342/0/tests/0_v4l2-compliance-uvc
10983 23:08:04.429545 + cat uuid
10984 23:08:04.432044 + UUID=12395342_1.5.2.3.1
10985 23:08:04.432593 + set +x
10986 23:08:04.438878 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 12395342_1.5.2.3.1>
10987 23:08:04.439750 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 12395342_1.5.2.3.1
10988 23:08:04.440166 Starting test lava.0_v4l2-compliance-uvc (12395342_1.5.2.3.1)
10989 23:08:04.440606 Skipping test definition patterns.
10990 23:08:04.442266 + /usr/bin/v4l2-parser.sh -d uvcvideo
10991 23:08:04.448564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
10992 23:08:04.449158 device: /dev/video0
10993 23:08:04.449800 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
10995 23:08:10.948646 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
10996 23:08:10.958278 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
10997 23:08:10.966695
10998 23:08:10.985498 Compliance test for uvcvideo device /dev/video0:
10999 23:08:10.993537
11000 23:08:11.007026 Driver Info:
11001 23:08:11.017020 Driver name : uvcvideo
11002 23:08:11.031963 Card type : HD User Facing: HD User Facing
11003 23:08:11.047766 Bus info : usb-11200000.usb-1.4.1
11004 23:08:11.058310 Driver version : 6.1.67
11005 23:08:11.071668 Capabilities : 0x84a00001
11006 23:08:11.084386 Metadata Capture
11007 23:08:11.100203 Streaming
11008 23:08:11.114832 Extended Pix Format
11009 23:08:11.126015 Device Capabilities
11010 23:08:11.143485 Device Caps : 0x04200001
11011 23:08:11.157624 Streaming
11012 23:08:11.172719 Extended Pix Format
11013 23:08:11.189380 Media Driver Info:
11014 23:08:11.200579 Driver name : uvcvideo
11015 23:08:11.217726 Model : HD User Facing: HD User Facing
11016 23:08:11.224512 Serial : 200901010001
11017 23:08:11.241314 Bus info : usb-11200000.usb-1.4.1
11018 23:08:11.252675 Media version : 6.1.67
11019 23:08:11.270021 Hardware revision: 0x00009758 (38744)
11020 23:08:11.278266 Driver version : 6.1.67
11021 23:08:11.289646 Interface Info:
11022 23:08:11.303937 <LAVA_SIGNAL_TESTSET START Interface-Info>
11023 23:08:11.304490 ID : 0x03000002
11024 23:08:11.305230 Received signal: <TESTSET> START Interface-Info
11025 23:08:11.305635 Starting test_set Interface-Info
11026 23:08:11.314112 Type : V4L Video
11027 23:08:11.326993 Entity Info:
11028 23:08:11.332438 <LAVA_SIGNAL_TESTSET STOP>
11029 23:08:11.333303 Received signal: <TESTSET> STOP
11030 23:08:11.333770 Closing test_set Interface-Info
11031 23:08:11.342388 <LAVA_SIGNAL_TESTSET START Entity-Info>
11032 23:08:11.343228 Received signal: <TESTSET> START Entity-Info
11033 23:08:11.343625 Starting test_set Entity-Info
11034 23:08:11.345414 ID : 0x00000001 (1)
11035 23:08:11.356565 Name : HD User Facing: HD User Facing
11036 23:08:11.364370 Function : V4L2 I/O
11037 23:08:11.381136 Flags : default
11038 23:08:11.392548 Pad 0x01000007 : 0: Sink
11039 23:08:11.413575 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11040 23:08:11.414145
11041 23:08:11.427179 Required ioctls:
11042 23:08:11.437303 <LAVA_SIGNAL_TESTSET STOP>
11043 23:08:11.438143 Received signal: <TESTSET> STOP
11044 23:08:11.438534 Closing test_set Entity-Info
11045 23:08:11.447854 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11046 23:08:11.448692 Received signal: <TESTSET> START Required-ioctls
11047 23:08:11.449112 Starting test_set Required-ioctls
11048 23:08:11.451359 test MC information (see 'Media Driver Info' above): OK
11049 23:08:11.478265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11050 23:08:11.479146 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11052 23:08:11.480799 test VIDIOC_QUERYCAP: OK
11053 23:08:11.504820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11054 23:08:11.505686 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11056 23:08:11.510250 test invalid ioctls: OK
11057 23:08:11.531931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11058 23:08:11.532479
11059 23:08:11.533121 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11061 23:08:11.544359 Allow for multiple opens:
11062 23:08:11.551393 <LAVA_SIGNAL_TESTSET STOP>
11063 23:08:11.552262 Received signal: <TESTSET> STOP
11064 23:08:11.552663 Closing test_set Required-ioctls
11065 23:08:11.562128 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11066 23:08:11.562971 Received signal: <TESTSET> START Allow-for-multiple-opens
11067 23:08:11.563369 Starting test_set Allow-for-multiple-opens
11068 23:08:11.565175 test second /dev/video0 open: OK
11069 23:08:11.588502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11070 23:08:11.589346 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11072 23:08:11.591706 test VIDIOC_QUERYCAP: OK
11073 23:08:11.613464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11074 23:08:11.614330 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11076 23:08:11.615612 test VIDIOC_G/S_PRIORITY: OK
11077 23:08:11.636693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11078 23:08:11.637510 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11080 23:08:11.640144 test for unlimited opens: OK
11081 23:08:11.663157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11082 23:08:11.663758
11083 23:08:11.664412 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11085 23:08:11.674838 Debug ioctls:
11086 23:08:11.682668 <LAVA_SIGNAL_TESTSET STOP>
11087 23:08:11.683498 Received signal: <TESTSET> STOP
11088 23:08:11.683928 Closing test_set Allow-for-multiple-opens
11089 23:08:11.691151 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11090 23:08:11.692010 Received signal: <TESTSET> START Debug-ioctls
11091 23:08:11.692410 Starting test_set Debug-ioctls
11092 23:08:11.694692 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11093 23:08:11.720644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11094 23:08:11.721500 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11096 23:08:11.727069 test VIDIOC_LOG_STATUS: OK (Not Supported)
11097 23:08:11.748255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11098 23:08:11.748798
11099 23:08:11.749473 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11101 23:08:11.760711 Input ioctls:
11102 23:08:11.767589 <LAVA_SIGNAL_TESTSET STOP>
11103 23:08:11.768460 Received signal: <TESTSET> STOP
11104 23:08:11.768851 Closing test_set Debug-ioctls
11105 23:08:11.777839 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11106 23:08:11.778684 Received signal: <TESTSET> START Input-ioctls
11107 23:08:11.779079 Starting test_set Input-ioctls
11108 23:08:11.780709 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11109 23:08:11.805677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11110 23:08:11.806566 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11112 23:08:11.809663 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11113 23:08:11.827807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11114 23:08:11.828610 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11116 23:08:11.834509 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11117 23:08:11.854740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11118 23:08:11.855584 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11120 23:08:11.859388 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11121 23:08:11.885229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11122 23:08:11.886066 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11124 23:08:11.887905 test VIDIOC_G/S/ENUMINPUT: OK
11125 23:08:11.911831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11126 23:08:11.912723 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11128 23:08:11.914812 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11129 23:08:11.940299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11130 23:08:11.941109 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11132 23:08:11.944000 Inputs: 1 Audio Inputs: 0 Tuners: 0
11133 23:08:11.952251
11134 23:08:11.975885 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11135 23:08:11.997578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11136 23:08:11.998477 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11138 23:08:12.004005 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11139 23:08:12.028176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11140 23:08:12.029052 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11142 23:08:12.034370 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11143 23:08:12.055082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11144 23:08:12.055934 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11146 23:08:12.061042 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11147 23:08:12.080493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11148 23:08:12.081331 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11150 23:08:12.086627 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11151 23:08:12.107285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11152 23:08:12.108137 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11154 23:08:12.111482
11155 23:08:12.129113 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11156 23:08:12.152025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11157 23:08:12.152856 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11159 23:08:12.158387 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11160 23:08:12.181838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11161 23:08:12.182723 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11163 23:08:12.186170 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11164 23:08:12.204630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11165 23:08:12.205431 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11167 23:08:12.208351 test VIDIOC_G/S_EDID: OK (Not Supported)
11168 23:08:12.228840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11169 23:08:12.229376
11170 23:08:12.230009 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11172 23:08:12.241043 Control ioctls (Input 0):
11173 23:08:12.247184 <LAVA_SIGNAL_TESTSET STOP>
11174 23:08:12.248044 Received signal: <TESTSET> STOP
11175 23:08:12.248446 Closing test_set Input-ioctls
11176 23:08:12.256848 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11177 23:08:12.257672 Received signal: <TESTSET> START Control-ioctls-Input-0
11178 23:08:12.258069 Starting test_set Control-ioctls-Input-0
11179 23:08:12.260072 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11180 23:08:12.285511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11181 23:08:12.286101 test VIDIOC_QUERYCTRL: OK
11182 23:08:12.286742 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11184 23:08:12.306356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11185 23:08:12.307198 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11187 23:08:12.309744 test VIDIOC_G/S_CTRL: OK
11188 23:08:12.332891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11189 23:08:12.333704 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11191 23:08:12.336018 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11192 23:08:12.356109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11193 23:08:12.356942 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11195 23:08:12.363197 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11196 23:08:12.389204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11197 23:08:12.390044 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11199 23:08:12.392108 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11200 23:08:12.411100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11201 23:08:12.412010 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11203 23:08:12.414778 Standard Controls: 16 Private Controls: 0
11204 23:08:12.421205
11205 23:08:12.429943 Format ioctls (Input 0):
11206 23:08:12.438397 <LAVA_SIGNAL_TESTSET STOP>
11207 23:08:12.439231 Received signal: <TESTSET> STOP
11208 23:08:12.439616 Closing test_set Control-ioctls-Input-0
11209 23:08:12.448981 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11210 23:08:12.449817 Received signal: <TESTSET> START Format-ioctls-Input-0
11211 23:08:12.450273 Starting test_set Format-ioctls-Input-0
11212 23:08:12.450806 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11213 23:08:12.475787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11214 23:08:12.476634 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11216 23:08:12.478693 test VIDIOC_G/S_PARM: OK
11217 23:08:12.501988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11218 23:08:12.502826 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11220 23:08:12.505424 test VIDIOC_G_FBUF: OK (Not Supported)
11221 23:08:12.527212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11222 23:08:12.528238 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11224 23:08:12.530234 test VIDIOC_G_FMT: OK
11225 23:08:12.551817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11226 23:08:12.552645 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11228 23:08:12.554154 test VIDIOC_TRY_FMT: OK
11229 23:08:12.576320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11230 23:08:12.577158 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11232 23:08:12.582188 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11233 23:08:12.585888 test VIDIOC_S_FMT: OK
11234 23:08:12.615667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11235 23:08:12.616542 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11237 23:08:12.619252 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11238 23:08:12.641738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11239 23:08:12.642626 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11241 23:08:12.644592 test Cropping: OK (Not Supported)
11242 23:08:12.670947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11243 23:08:12.671811 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11245 23:08:12.674140 test Composing: OK (Not Supported)
11246 23:08:12.700699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11247 23:08:12.701580 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11249 23:08:12.703604 test Scaling: OK (Not Supported)
11250 23:08:12.728778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11251 23:08:12.729317
11252 23:08:12.729946 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11254 23:08:12.741014 Codec ioctls (Input 0):
11255 23:08:12.748339 <LAVA_SIGNAL_TESTSET STOP>
11256 23:08:12.749166 Received signal: <TESTSET> STOP
11257 23:08:12.749551 Closing test_set Format-ioctls-Input-0
11258 23:08:12.758387 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11259 23:08:12.759234 Received signal: <TESTSET> START Codec-ioctls-Input-0
11260 23:08:12.759644 Starting test_set Codec-ioctls-Input-0
11261 23:08:12.761696 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11262 23:08:12.783199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11263 23:08:12.784072 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11265 23:08:12.790484 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11266 23:08:12.806947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11267 23:08:12.807828 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11269 23:08:12.813090 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11270 23:08:12.832289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11271 23:08:12.832829
11272 23:08:12.833473 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11274 23:08:12.845272 Buffer ioctls (Input 0):
11275 23:08:12.854667 <LAVA_SIGNAL_TESTSET STOP>
11276 23:08:12.855439 Received signal: <TESTSET> STOP
11277 23:08:12.855815 Closing test_set Codec-ioctls-Input-0
11278 23:08:12.864787 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11279 23:08:12.865624 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11280 23:08:12.866023 Starting test_set Buffer-ioctls-Input-0
11281 23:08:12.867474 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11282 23:08:12.891909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11283 23:08:12.892405 test VIDIOC_EXPBUF: OK
11284 23:08:12.893003 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11286 23:08:12.912945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11287 23:08:12.913812 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11289 23:08:12.916397 test Requests: OK (Not Supported)
11290 23:08:12.943826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11291 23:08:12.944411
11292 23:08:12.945065 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11294 23:08:12.953439 Test input 0:
11295 23:08:12.964384
11296 23:08:12.975391 Streaming ioctls:
11297 23:08:12.983664 <LAVA_SIGNAL_TESTSET STOP>
11298 23:08:12.984535 Received signal: <TESTSET> STOP
11299 23:08:12.984922 Closing test_set Buffer-ioctls-Input-0
11300 23:08:12.993249 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11301 23:08:12.994091 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11302 23:08:12.994491 Starting test_set Streaming-ioctls_Test-input-0
11303 23:08:12.996365 test read/write: OK (Not Supported)
11304 23:08:13.018827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11305 23:08:13.019727 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11307 23:08:13.021811 test blocking wait: OK
11308 23:08:13.043726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11309 23:08:13.044560 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11311 23:08:13.054988 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11312 23:08:13.056998 test MMAP (no poll): FAIL
11313 23:08:13.079728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11314 23:08:13.080572 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11316 23:08:13.089065 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11317 23:08:13.092350 test MMAP (select): FAIL
11318 23:08:13.114733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11319 23:08:13.115584 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11321 23:08:13.125435 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11322 23:08:13.125992 test MMAP (epoll): FAIL
11323 23:08:13.150355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11324 23:08:13.150902
11325 23:08:13.151547 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11327 23:08:13.164041
11328 23:08:13.340774
11329 23:08:13.350690 test USERPTR (no poll): OK
11330 23:08:13.375059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11331 23:08:13.375630
11332 23:08:13.376334 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11334 23:08:13.387784
11335 23:08:13.582034
11336 23:08:13.595419 test USERPTR (select): OK
11337 23:08:13.620112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11338 23:08:13.620918 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11340 23:08:13.627293 test DMABUF: Cannot test, specify --expbuf-device
11341 23:08:13.633593
11342 23:08:13.655236 Total for uvcvideo device /dev/video0: 53, Succeeded: 50, Failed: 3, Warnings: 3
11343 23:08:13.657974 <LAVA_TEST_RUNNER EXIT>
11344 23:08:13.658800 ok: lava_test_shell seems to have completed
11345 23:08:13.659217 Marking unfinished test run as failed
11347 23:08:13.664414 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11348 23:08:13.665068 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11349 23:08:13.665539 end: 3 lava-test-retry (duration 00:00:10) [common]
11350 23:08:13.666006 start: 4 finalize (timeout 00:08:04) [common]
11351 23:08:13.666488 start: 4.1 power-off (timeout 00:00:30) [common]
11352 23:08:13.667305 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11353 23:08:13.754582 >> Command sent successfully.
11354 23:08:13.766337 Returned 0 in 0 seconds
11355 23:08:13.867769 end: 4.1 power-off (duration 00:00:00) [common]
11357 23:08:13.869343 start: 4.2 read-feedback (timeout 00:08:04) [common]
11358 23:08:13.870632 Listened to connection for namespace 'common' for up to 1s
11359 23:08:14.871238 Finalising connection for namespace 'common'
11360 23:08:14.871964 Disconnecting from shell: Finalise
11361 23:08:14.872405 / #
11362 23:08:14.973417 end: 4.2 read-feedback (duration 00:00:01) [common]
11363 23:08:14.974160 end: 4 finalize (duration 00:00:01) [common]
11364 23:08:14.974801 Cleaning after the job
11365 23:08:14.975338 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395342/tftp-deploy-964i7d0v/ramdisk
11366 23:08:15.000620 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395342/tftp-deploy-964i7d0v/kernel
11367 23:08:15.018602 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395342/tftp-deploy-964i7d0v/dtb
11368 23:08:15.018886 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12395342/tftp-deploy-964i7d0v/modules
11369 23:08:15.028650 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12395342
11370 23:08:15.101038 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12395342
11371 23:08:15.101213 Job finished correctly