Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 16
- Kernel Errors: 27
1 12:10:27.707975 lava-dispatcher, installed at version: 2023.10
2 12:10:27.708187 start: 0 validate
3 12:10:27.708322 Start time: 2024-01-31 12:10:27.708315+00:00 (UTC)
4 12:10:27.708477 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:10:27.708610 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:10:27.979438 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:10:27.980236 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:10:28.252453 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:10:28.253212 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:11:28.586152 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:11:28.587134 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:11:29.119039 validate duration: 61.41
14 12:11:29.120370 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:11:29.120906 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:11:29.121376 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:11:29.121994 Not decompressing ramdisk as can be used compressed.
18 12:11:29.122497 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 12:11:29.122884 saving as /var/lib/lava/dispatcher/tmp/12669528/tftp-deploy-1gcokwmw/ramdisk/rootfs.cpio.gz
20 12:11:29.123251 total size: 8181372 (7 MB)
21 12:11:36.864775 progress 0 % (0 MB)
22 12:11:36.878182 progress 5 % (0 MB)
23 12:11:36.889032 progress 10 % (0 MB)
24 12:11:36.899460 progress 15 % (1 MB)
25 12:11:36.905834 progress 20 % (1 MB)
26 12:11:36.910984 progress 25 % (1 MB)
27 12:11:36.915002 progress 30 % (2 MB)
28 12:11:36.918875 progress 35 % (2 MB)
29 12:11:36.922188 progress 40 % (3 MB)
30 12:11:36.925356 progress 45 % (3 MB)
31 12:11:36.928219 progress 50 % (3 MB)
32 12:11:36.930976 progress 55 % (4 MB)
33 12:11:36.933420 progress 60 % (4 MB)
34 12:11:36.935957 progress 65 % (5 MB)
35 12:11:36.938142 progress 70 % (5 MB)
36 12:11:36.940395 progress 75 % (5 MB)
37 12:11:36.942501 progress 80 % (6 MB)
38 12:11:36.944743 progress 85 % (6 MB)
39 12:11:36.946790 progress 90 % (7 MB)
40 12:11:36.949038 progress 95 % (7 MB)
41 12:11:36.951095 progress 100 % (7 MB)
42 12:11:36.951291 7 MB downloaded in 7.83 s (1.00 MB/s)
43 12:11:36.951441 end: 1.1.1 http-download (duration 00:00:08) [common]
45 12:11:36.951688 end: 1.1 download-retry (duration 00:00:08) [common]
46 12:11:36.951812 start: 1.2 download-retry (timeout 00:09:52) [common]
47 12:11:36.951901 start: 1.2.1 http-download (timeout 00:09:52) [common]
48 12:11:36.952037 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:11:36.952108 saving as /var/lib/lava/dispatcher/tmp/12669528/tftp-deploy-1gcokwmw/kernel/Image
50 12:11:36.952168 total size: 51532288 (49 MB)
51 12:11:36.952229 No compression specified
52 12:11:37.219333 progress 0 % (0 MB)
53 12:11:37.266574 progress 5 % (2 MB)
54 12:11:37.284725 progress 10 % (4 MB)
55 12:11:37.298312 progress 15 % (7 MB)
56 12:11:37.311604 progress 20 % (9 MB)
57 12:11:37.324880 progress 25 % (12 MB)
58 12:11:37.338159 progress 30 % (14 MB)
59 12:11:37.351563 progress 35 % (17 MB)
60 12:11:37.364914 progress 40 % (19 MB)
61 12:11:37.378129 progress 45 % (22 MB)
62 12:11:37.391617 progress 50 % (24 MB)
63 12:11:37.404923 progress 55 % (27 MB)
64 12:11:37.418317 progress 60 % (29 MB)
65 12:11:37.431693 progress 65 % (31 MB)
66 12:11:37.444982 progress 70 % (34 MB)
67 12:11:37.458294 progress 75 % (36 MB)
68 12:11:37.471571 progress 80 % (39 MB)
69 12:11:37.484756 progress 85 % (41 MB)
70 12:11:37.498322 progress 90 % (44 MB)
71 12:11:37.511538 progress 95 % (46 MB)
72 12:11:37.524578 progress 100 % (49 MB)
73 12:11:37.524782 49 MB downloaded in 0.57 s (85.83 MB/s)
74 12:11:37.524931 end: 1.2.1 http-download (duration 00:00:01) [common]
76 12:11:37.525164 end: 1.2 download-retry (duration 00:00:01) [common]
77 12:11:37.525249 start: 1.3 download-retry (timeout 00:09:52) [common]
78 12:11:37.525333 start: 1.3.1 http-download (timeout 00:09:52) [common]
79 12:11:37.525472 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:11:37.525544 saving as /var/lib/lava/dispatcher/tmp/12669528/tftp-deploy-1gcokwmw/dtb/mt8192-asurada-spherion-r0.dtb
81 12:11:37.525605 total size: 47278 (0 MB)
82 12:11:37.525667 No compression specified
83 12:11:37.526860 progress 69 % (0 MB)
84 12:11:37.527135 progress 100 % (0 MB)
85 12:11:37.527289 0 MB downloaded in 0.00 s (26.82 MB/s)
86 12:11:37.527410 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:11:37.527628 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:11:37.527751 start: 1.4 download-retry (timeout 00:09:52) [common]
90 12:11:37.527879 start: 1.4.1 http-download (timeout 00:09:52) [common]
91 12:11:37.527993 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:11:37.528061 saving as /var/lib/lava/dispatcher/tmp/12669528/tftp-deploy-1gcokwmw/modules/modules.tar
93 12:11:37.528122 total size: 8639916 (8 MB)
94 12:11:37.528183 Using unxz to decompress xz
95 12:11:37.532319 progress 0 % (0 MB)
96 12:11:37.553369 progress 5 % (0 MB)
97 12:11:37.576641 progress 10 % (0 MB)
98 12:11:37.600030 progress 15 % (1 MB)
99 12:11:37.623152 progress 20 % (1 MB)
100 12:11:37.647096 progress 25 % (2 MB)
101 12:11:37.674529 progress 30 % (2 MB)
102 12:11:37.698355 progress 35 % (2 MB)
103 12:11:37.721260 progress 40 % (3 MB)
104 12:11:37.745487 progress 45 % (3 MB)
105 12:11:37.770647 progress 50 % (4 MB)
106 12:11:37.796320 progress 55 % (4 MB)
107 12:11:37.820625 progress 60 % (4 MB)
108 12:11:37.846155 progress 65 % (5 MB)
109 12:11:37.870649 progress 70 % (5 MB)
110 12:11:37.893746 progress 75 % (6 MB)
111 12:11:37.920056 progress 80 % (6 MB)
112 12:11:37.947515 progress 85 % (7 MB)
113 12:11:37.972004 progress 90 % (7 MB)
114 12:11:38.001174 progress 95 % (7 MB)
115 12:11:38.028257 progress 100 % (8 MB)
116 12:11:38.034072 8 MB downloaded in 0.51 s (16.29 MB/s)
117 12:11:38.034350 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:11:38.034603 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:11:38.034695 start: 1.5 prepare-tftp-overlay (timeout 00:09:51) [common]
121 12:11:38.034787 start: 1.5.1 extract-nfsrootfs (timeout 00:09:51) [common]
122 12:11:38.034884 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:11:38.035000 start: 1.5.2 lava-overlay (timeout 00:09:51) [common]
124 12:11:38.035233 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_
125 12:11:38.035373 makedir: /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin
126 12:11:38.035477 makedir: /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/tests
127 12:11:38.035576 makedir: /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/results
128 12:11:38.035719 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-add-keys
129 12:11:38.035894 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-add-sources
130 12:11:38.036023 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-background-process-start
131 12:11:38.036201 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-background-process-stop
132 12:11:38.036332 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-common-functions
133 12:11:38.036457 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-echo-ipv4
134 12:11:38.036582 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-install-packages
135 12:11:38.036706 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-installed-packages
136 12:11:38.036830 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-os-build
137 12:11:38.036956 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-probe-channel
138 12:11:38.037101 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-probe-ip
139 12:11:38.037229 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-target-ip
140 12:11:38.037418 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-target-mac
141 12:11:38.037570 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-target-storage
142 12:11:38.037713 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-test-case
143 12:11:38.037840 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-test-event
144 12:11:38.037964 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-test-feedback
145 12:11:38.038087 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-test-raise
146 12:11:38.038212 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-test-reference
147 12:11:38.038338 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-test-runner
148 12:11:38.038462 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-test-set
149 12:11:38.038588 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-test-shell
150 12:11:38.038716 Updating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-install-packages (oe)
151 12:11:38.038870 Updating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/bin/lava-installed-packages (oe)
152 12:11:38.038994 Creating /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/environment
153 12:11:38.039092 LAVA metadata
154 12:11:38.039182 - LAVA_JOB_ID=12669528
155 12:11:38.039274 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:11:38.039420 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:51) [common]
157 12:11:38.039503 skipped lava-vland-overlay
158 12:11:38.039578 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:11:38.039661 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:51) [common]
160 12:11:38.039780 skipped lava-multinode-overlay
161 12:11:38.039854 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:11:38.039934 start: 1.5.2.3 test-definition (timeout 00:09:51) [common]
163 12:11:38.040008 Loading test definitions
164 12:11:38.040121 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:51) [common]
165 12:11:38.040209 Using /lava-12669528 at stage 0
166 12:11:38.040528 uuid=12669528_1.5.2.3.1 testdef=None
167 12:11:38.040616 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:11:38.040715 start: 1.5.2.3.2 test-overlay (timeout 00:09:51) [common]
169 12:11:38.041846 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:11:38.042062 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:51) [common]
172 12:11:38.042690 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:11:38.042913 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:51) [common]
175 12:11:38.043635 runner path: /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/0/tests/0_dmesg test_uuid 12669528_1.5.2.3.1
176 12:11:38.043841 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:11:38.044066 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:51) [common]
179 12:11:38.044137 Using /lava-12669528 at stage 1
180 12:11:38.044427 uuid=12669528_1.5.2.3.5 testdef=None
181 12:11:38.044513 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 12:11:38.044596 start: 1.5.2.3.6 test-overlay (timeout 00:09:51) [common]
183 12:11:38.045130 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 12:11:38.045350 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:51) [common]
186 12:11:38.046020 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 12:11:38.046271 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:51) [common]
189 12:11:38.046878 runner path: /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/1/tests/1_bootrr test_uuid 12669528_1.5.2.3.5
190 12:11:38.047056 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 12:11:38.047259 Creating lava-test-runner.conf files
193 12:11:38.047321 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/0 for stage 0
194 12:11:38.047411 - 0_dmesg
195 12:11:38.047489 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12669528/lava-overlay-2twc281_/lava-12669528/1 for stage 1
196 12:11:38.047579 - 1_bootrr
197 12:11:38.047678 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 12:11:38.047815 start: 1.5.2.4 compress-overlay (timeout 00:09:51) [common]
199 12:11:38.055819 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 12:11:38.055919 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:51) [common]
201 12:11:38.056001 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 12:11:38.056085 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 12:11:38.056167 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:51) [common]
204 12:11:38.303394 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 12:11:38.303845 start: 1.5.4 extract-modules (timeout 00:09:51) [common]
206 12:11:38.303961 extracting modules file /var/lib/lava/dispatcher/tmp/12669528/tftp-deploy-1gcokwmw/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12669528/extract-overlay-ramdisk-mcddzjda/ramdisk
207 12:11:38.520545 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 12:11:38.520710 start: 1.5.5 apply-overlay-tftp (timeout 00:09:51) [common]
209 12:11:38.520802 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12669528/compress-overlay-clcpx_vc/overlay-1.5.2.4.tar.gz to ramdisk
210 12:11:38.520872 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12669528/compress-overlay-clcpx_vc/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12669528/extract-overlay-ramdisk-mcddzjda/ramdisk
211 12:11:38.528956 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 12:11:38.529062 start: 1.5.6 configure-preseed-file (timeout 00:09:51) [common]
213 12:11:38.529151 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 12:11:38.529237 start: 1.5.7 compress-ramdisk (timeout 00:09:51) [common]
215 12:11:38.529314 Building ramdisk /var/lib/lava/dispatcher/tmp/12669528/extract-overlay-ramdisk-mcddzjda/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12669528/extract-overlay-ramdisk-mcddzjda/ramdisk
216 12:11:38.930789 >> 145326 blocks
217 12:11:41.174413 rename /var/lib/lava/dispatcher/tmp/12669528/extract-overlay-ramdisk-mcddzjda/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12669528/tftp-deploy-1gcokwmw/ramdisk/ramdisk.cpio.gz
218 12:11:41.174874 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 12:11:41.175003 start: 1.5.8 prepare-kernel (timeout 00:09:48) [common]
220 12:11:41.175101 start: 1.5.8.1 prepare-fit (timeout 00:09:48) [common]
221 12:11:41.175208 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12669528/tftp-deploy-1gcokwmw/kernel/Image'
222 12:11:53.443995 Returned 0 in 12 seconds
223 12:11:53.544925 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12669528/tftp-deploy-1gcokwmw/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12669528/tftp-deploy-1gcokwmw/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12669528/tftp-deploy-1gcokwmw/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12669528/tftp-deploy-1gcokwmw/kernel/image.itb
224 12:11:53.964434 output: FIT description: Kernel Image image with one or more FDT blobs
225 12:11:53.964814 output: Created: Wed Jan 31 12:11:53 2024
226 12:11:53.964885 output: Image 0 (kernel-1)
227 12:11:53.964951 output: Description:
228 12:11:53.965013 output: Created: Wed Jan 31 12:11:53 2024
229 12:11:53.965073 output: Type: Kernel Image
230 12:11:53.965147 output: Compression: lzma compressed
231 12:11:53.965220 output: Data Size: 12047284 Bytes = 11764.93 KiB = 11.49 MiB
232 12:11:53.965281 output: Architecture: AArch64
233 12:11:53.965339 output: OS: Linux
234 12:11:53.965395 output: Load Address: 0x00000000
235 12:11:53.965451 output: Entry Point: 0x00000000
236 12:11:53.965573 output: Hash algo: crc32
237 12:11:53.965698 output: Hash value: 5a47eb78
238 12:11:53.965758 output: Image 1 (fdt-1)
239 12:11:53.965826 output: Description: mt8192-asurada-spherion-r0
240 12:11:53.965881 output: Created: Wed Jan 31 12:11:53 2024
241 12:11:53.965933 output: Type: Flat Device Tree
242 12:11:53.965985 output: Compression: uncompressed
243 12:11:53.966038 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 12:11:53.966091 output: Architecture: AArch64
245 12:11:53.966171 output: Hash algo: crc32
246 12:11:53.966223 output: Hash value: cc4352de
247 12:11:53.966274 output: Image 2 (ramdisk-1)
248 12:11:53.966326 output: Description: unavailable
249 12:11:53.966378 output: Created: Wed Jan 31 12:11:53 2024
250 12:11:53.966431 output: Type: RAMDisk Image
251 12:11:53.966483 output: Compression: Unknown Compression
252 12:11:53.966535 output: Data Size: 21403464 Bytes = 20901.82 KiB = 20.41 MiB
253 12:11:53.966588 output: Architecture: AArch64
254 12:11:53.966640 output: OS: Linux
255 12:11:53.966691 output: Load Address: unavailable
256 12:11:53.966742 output: Entry Point: unavailable
257 12:11:53.966794 output: Hash algo: crc32
258 12:11:53.966846 output: Hash value: 665afbd4
259 12:11:53.966897 output: Default Configuration: 'conf-1'
260 12:11:53.966949 output: Configuration 0 (conf-1)
261 12:11:53.967001 output: Description: mt8192-asurada-spherion-r0
262 12:11:53.967052 output: Kernel: kernel-1
263 12:11:53.967104 output: Init Ramdisk: ramdisk-1
264 12:11:53.967155 output: FDT: fdt-1
265 12:11:53.967207 output: Loadables: kernel-1
266 12:11:53.967258 output:
267 12:11:53.967454 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
268 12:11:53.967548 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
269 12:11:53.967645 end: 1.5 prepare-tftp-overlay (duration 00:00:16) [common]
270 12:11:53.967793 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
271 12:11:53.967870 No LXC device requested
272 12:11:53.967947 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 12:11:53.968030 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
274 12:11:53.968107 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 12:11:53.968178 Checking files for TFTP limit of 4294967296 bytes.
276 12:11:53.968701 end: 1 tftp-deploy (duration 00:00:25) [common]
277 12:11:53.968800 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 12:11:53.968884 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 12:11:53.969005 substitutions:
280 12:11:53.969071 - {DTB}: 12669528/tftp-deploy-1gcokwmw/dtb/mt8192-asurada-spherion-r0.dtb
281 12:11:53.969136 - {INITRD}: 12669528/tftp-deploy-1gcokwmw/ramdisk/ramdisk.cpio.gz
282 12:11:53.969194 - {KERNEL}: 12669528/tftp-deploy-1gcokwmw/kernel/Image
283 12:11:53.969252 - {LAVA_MAC}: None
284 12:11:53.969307 - {PRESEED_CONFIG}: None
285 12:11:53.969361 - {PRESEED_LOCAL}: None
286 12:11:53.969413 - {RAMDISK}: 12669528/tftp-deploy-1gcokwmw/ramdisk/ramdisk.cpio.gz
287 12:11:53.969467 - {ROOT_PART}: None
288 12:11:53.969519 - {ROOT}: None
289 12:11:53.969572 - {SERVER_IP}: 192.168.201.1
290 12:11:53.969625 - {TEE}: None
291 12:11:53.969678 Parsed boot commands:
292 12:11:53.969730 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 12:11:53.969962 Parsed boot commands: tftpboot 192.168.201.1 12669528/tftp-deploy-1gcokwmw/kernel/image.itb 12669528/tftp-deploy-1gcokwmw/kernel/cmdline
294 12:11:53.970056 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 12:11:53.970141 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 12:11:53.970236 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 12:11:53.970323 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 12:11:53.970395 Not connected, no need to disconnect.
299 12:11:53.970468 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 12:11:53.970550 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 12:11:53.970616 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
302 12:11:53.974557 Setting prompt string to ['lava-test: # ']
303 12:11:53.974914 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 12:11:53.975022 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 12:11:53.975135 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 12:11:53.975220 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 12:11:53.975450 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
308 12:11:59.109121 >> Command sent successfully.
309 12:11:59.120204 Returned 0 in 5 seconds
310 12:11:59.221479 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 12:11:59.222906 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 12:11:59.223449 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 12:11:59.224089 Setting prompt string to 'Starting depthcharge on Spherion...'
315 12:11:59.224494 Changing prompt to 'Starting depthcharge on Spherion...'
316 12:11:59.224846 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 12:11:59.226117 [Enter `^Ec?' for help]
318 12:11:59.386421
319 12:11:59.387037
320 12:11:59.387434 F0: 102B 0000
321 12:11:59.387858
322 12:11:59.388196 F3: 1001 0000 [0200]
323 12:11:59.388529
324 12:11:59.389723 F3: 1001 0000
325 12:11:59.390193
326 12:11:59.390560 F7: 102D 0000
327 12:11:59.390909
328 12:11:59.391242 F1: 0000 0000
329 12:11:59.393034
330 12:11:59.393500 V0: 0000 0000 [0001]
331 12:11:59.393873
332 12:11:59.394218 00: 0007 8000
333 12:11:59.394577
334 12:11:59.396838 01: 0000 0000
335 12:11:59.397315
336 12:11:59.397686 BP: 0C00 0209 [0000]
337 12:11:59.398027
338 12:11:59.400977 G0: 1182 0000
339 12:11:59.401442
340 12:11:59.401829 EC: 0000 0021 [4000]
341 12:11:59.402178
342 12:11:59.404694 S7: 0000 0000 [0000]
343 12:11:59.405237
344 12:11:59.405582 CC: 0000 0000 [0001]
345 12:11:59.405897
346 12:11:59.407843 T0: 0000 0040 [010F]
347 12:11:59.408268
348 12:11:59.408625 Jump to BL
349 12:11:59.408949
350 12:11:59.433180
351 12:11:59.433731
352 12:11:59.434102
353 12:11:59.440793 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 12:11:59.443658 ARM64: Exception handlers installed.
355 12:11:59.447312 ARM64: Testing exception
356 12:11:59.451120 ARM64: Done test exception
357 12:11:59.457377 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 12:11:59.468311 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 12:11:59.476069 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 12:11:59.485894 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 12:11:59.492566 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 12:11:59.500633 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 12:11:59.509845 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 12:11:59.516707 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 12:11:59.535943 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 12:11:59.538802 WDT: Last reset was cold boot
367 12:11:59.542144 SPI1(PAD0) initialized at 2873684 Hz
368 12:11:59.546536 SPI5(PAD0) initialized at 992727 Hz
369 12:11:59.549399 VBOOT: Loading verstage.
370 12:11:59.555563 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 12:11:59.559494 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 12:11:59.562881 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 12:11:59.566244 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 12:11:59.573318 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 12:11:59.579704 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 12:11:59.591304 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 12:11:59.591919
378 12:11:59.592300
379 12:11:59.600389 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 12:11:59.604773 ARM64: Exception handlers installed.
381 12:11:59.607406 ARM64: Testing exception
382 12:11:59.608069 ARM64: Done test exception
383 12:11:59.614280 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 12:11:59.616944 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 12:11:59.631391 Probing TPM: . done!
386 12:11:59.632024 TPM ready after 0 ms
387 12:11:59.638731 Connected to device vid:did:rid of 1ae0:0028:00
388 12:11:59.648693 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
389 12:11:59.689873 Initialized TPM device CR50 revision 0
390 12:11:59.701564 tlcl_send_startup: Startup return code is 0
391 12:11:59.702134 TPM: setup succeeded
392 12:11:59.712626 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 12:11:59.721230 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 12:11:59.728178 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 12:11:59.740060 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 12:11:59.744082 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 12:11:59.747401 in-header: 03 07 00 00 08 00 00 00
398 12:11:59.750393 in-data: aa e4 47 04 13 02 00 00
399 12:11:59.753277 Chrome EC: UHEPI supported
400 12:11:59.759944 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 12:11:59.763240 in-header: 03 ad 00 00 08 00 00 00
402 12:11:59.766495 in-data: 00 20 20 08 00 00 00 00
403 12:11:59.767098 Phase 1
404 12:11:59.769490 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 12:11:59.776082 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 12:11:59.782867 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 12:11:59.786107 Recovery requested (1009000e)
408 12:11:59.790207 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 12:11:59.798832 tlcl_extend: response is 0
410 12:11:59.809343 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 12:11:59.812369 tlcl_extend: response is 0
412 12:11:59.819436 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 12:11:59.839871 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
414 12:11:59.846595 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 12:11:59.847168
416 12:11:59.847540
417 12:11:59.856873 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 12:11:59.860018 ARM64: Exception handlers installed.
419 12:11:59.863433 ARM64: Testing exception
420 12:11:59.864034 ARM64: Done test exception
421 12:11:59.885811 pmic_efuse_setting: Set efuses in 11 msecs
422 12:11:59.889128 pmwrap_interface_init: Select PMIF_VLD_RDY
423 12:11:59.893060 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 12:11:59.899169 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 12:11:59.902435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 12:11:59.909744 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 12:11:59.912654 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 12:11:59.919507 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 12:11:59.922423 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 12:11:59.930209 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 12:11:59.932860 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 12:11:59.936964 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 12:11:59.942831 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 12:11:59.946490 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 12:11:59.949453 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 12:11:59.956670 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 12:11:59.962943 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 12:11:59.969663 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 12:11:59.973386 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 12:11:59.979986 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 12:11:59.986622 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 12:11:59.989709 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 12:11:59.996172 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 12:12:00.004252 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 12:12:00.007388 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 12:12:00.015168 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 12:12:00.017766 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 12:12:00.024517 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 12:12:00.027958 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 12:12:00.034483 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 12:12:00.038224 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 12:12:00.044988 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 12:12:00.048746 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 12:12:00.055481 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 12:12:00.058716 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 12:12:00.065138 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 12:12:00.068486 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 12:12:00.075703 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 12:12:00.078584 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 12:12:00.084995 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 12:12:00.088946 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 12:12:00.093194 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 12:12:00.096010 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 12:12:00.099746 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 12:12:00.106600 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 12:12:00.109729 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 12:12:00.113375 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 12:12:00.120093 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 12:12:00.123724 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 12:12:00.126885 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 12:12:00.133102 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 12:12:00.136849 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 12:12:00.139974 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 12:12:00.146486 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 12:12:00.156974 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 12:12:00.160113 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 12:12:00.169717 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 12:12:00.176720 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 12:12:00.184233 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 12:12:00.186493 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 12:12:00.190084 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 12:12:00.197280 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x1e
483 12:12:00.204595 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 12:12:00.208377 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
485 12:12:00.214800 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 12:12:00.221948 [RTC]rtc_get_frequency_meter,154: input=15, output=835
487 12:12:00.231407 [RTC]rtc_get_frequency_meter,154: input=7, output=708
488 12:12:00.240924 [RTC]rtc_get_frequency_meter,154: input=11, output=772
489 12:12:00.250984 [RTC]rtc_get_frequency_meter,154: input=13, output=803
490 12:12:00.260223 [RTC]rtc_get_frequency_meter,154: input=12, output=788
491 12:12:00.269559 [RTC]rtc_get_frequency_meter,154: input=12, output=788
492 12:12:00.279283 [RTC]rtc_get_frequency_meter,154: input=13, output=803
493 12:12:00.282396 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
494 12:12:00.290454 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
495 12:12:00.292911 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 12:12:00.296708 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 12:12:00.303448 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 12:12:00.306028 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 12:12:00.309375 ADC[4]: Raw value=904509 ID=7
500 12:12:00.309882 ADC[3]: Raw value=212912 ID=1
501 12:12:00.312599 RAM Code: 0x71
502 12:12:00.316526 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 12:12:00.323117 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 12:12:00.329761 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 12:12:00.336125 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 12:12:00.338883 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 12:12:00.342945 in-header: 03 07 00 00 08 00 00 00
508 12:12:00.346319 in-data: aa e4 47 04 13 02 00 00
509 12:12:00.349481 Chrome EC: UHEPI supported
510 12:12:00.356174 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 12:12:00.359559 in-header: 03 dd 00 00 08 00 00 00
512 12:12:00.363072 in-data: 90 20 60 08 00 00 00 00
513 12:12:00.366270 MRC: failed to locate region type 0.
514 12:12:00.372311 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 12:12:00.375976 DRAM-K: Running full calibration
516 12:12:00.383258 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 12:12:00.383836 header.status = 0x0
518 12:12:00.385942 header.version = 0x6 (expected: 0x6)
519 12:12:00.389253 header.size = 0xd00 (expected: 0xd00)
520 12:12:00.392205 header.flags = 0x0
521 12:12:00.398833 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 12:12:00.416580 read SPI 0x72590 0x1c583: 12496 us, 9290 KB/s, 74.320 Mbps
523 12:12:00.423083 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 12:12:00.426599 dram_init: ddr_geometry: 2
525 12:12:00.430116 [EMI] MDL number = 2
526 12:12:00.430609 [EMI] Get MDL freq = 0
527 12:12:00.432915 dram_init: ddr_type: 0
528 12:12:00.433383 is_discrete_lpddr4: 1
529 12:12:00.435942 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 12:12:00.436505
531 12:12:00.436904
532 12:12:00.439802 [Bian_co] ETT version 0.0.0.1
533 12:12:00.446105 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 12:12:00.446699
535 12:12:00.449203 dramc_set_vcore_voltage set vcore to 650000
536 12:12:00.452268 Read voltage for 800, 4
537 12:12:00.452734 Vio18 = 0
538 12:12:00.453128 Vcore = 650000
539 12:12:00.455780 Vdram = 0
540 12:12:00.456259 Vddq = 0
541 12:12:00.456630 Vmddr = 0
542 12:12:00.459338 dram_init: config_dvfs: 1
543 12:12:00.462530 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 12:12:00.469662 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 12:12:00.472386 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
546 12:12:00.476165 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
547 12:12:00.479077 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
548 12:12:00.482379 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
549 12:12:00.486169 MEM_TYPE=3, freq_sel=18
550 12:12:00.489610 sv_algorithm_assistance_LP4_1600
551 12:12:00.492282 ============ PULL DRAM RESETB DOWN ============
552 12:12:00.499054 ========== PULL DRAM RESETB DOWN end =========
553 12:12:00.503031 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 12:12:00.506361 ===================================
555 12:12:00.509494 LPDDR4 DRAM CONFIGURATION
556 12:12:00.513099 ===================================
557 12:12:00.513568 EX_ROW_EN[0] = 0x0
558 12:12:00.515794 EX_ROW_EN[1] = 0x0
559 12:12:00.516263 LP4Y_EN = 0x0
560 12:12:00.519129 WORK_FSP = 0x0
561 12:12:00.519622 WL = 0x2
562 12:12:00.522251 RL = 0x2
563 12:12:00.522961 BL = 0x2
564 12:12:00.526171 RPST = 0x0
565 12:12:00.526593 RD_PRE = 0x0
566 12:12:00.528904 WR_PRE = 0x1
567 12:12:00.529323 WR_PST = 0x0
568 12:12:00.532366 DBI_WR = 0x0
569 12:12:00.536064 DBI_RD = 0x0
570 12:12:00.536589 OTF = 0x1
571 12:12:00.539376 ===================================
572 12:12:00.542046 ===================================
573 12:12:00.542575 ANA top config
574 12:12:00.545767 ===================================
575 12:12:00.549305 DLL_ASYNC_EN = 0
576 12:12:00.552508 ALL_SLAVE_EN = 1
577 12:12:00.555788 NEW_RANK_MODE = 1
578 12:12:00.559135 DLL_IDLE_MODE = 1
579 12:12:00.559658 LP45_APHY_COMB_EN = 1
580 12:12:00.562575 TX_ODT_DIS = 1
581 12:12:00.565081 NEW_8X_MODE = 1
582 12:12:00.568692 ===================================
583 12:12:00.572874 ===================================
584 12:12:00.575656 data_rate = 1600
585 12:12:00.578524 CKR = 1
586 12:12:00.578948 DQ_P2S_RATIO = 8
587 12:12:00.582015 ===================================
588 12:12:00.584976 CA_P2S_RATIO = 8
589 12:12:00.589199 DQ_CA_OPEN = 0
590 12:12:00.591901 DQ_SEMI_OPEN = 0
591 12:12:00.595536 CA_SEMI_OPEN = 0
592 12:12:00.598227 CA_FULL_RATE = 0
593 12:12:00.598838 DQ_CKDIV4_EN = 1
594 12:12:00.602133 CA_CKDIV4_EN = 1
595 12:12:00.604961 CA_PREDIV_EN = 0
596 12:12:00.608680 PH8_DLY = 0
597 12:12:00.611897 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 12:12:00.615232 DQ_AAMCK_DIV = 4
599 12:12:00.615800 CA_AAMCK_DIV = 4
600 12:12:00.618608 CA_ADMCK_DIV = 4
601 12:12:00.621902 DQ_TRACK_CA_EN = 0
602 12:12:00.625578 CA_PICK = 800
603 12:12:00.628365 CA_MCKIO = 800
604 12:12:00.631763 MCKIO_SEMI = 0
605 12:12:00.635239 PLL_FREQ = 3068
606 12:12:00.635662 DQ_UI_PI_RATIO = 32
607 12:12:00.638310 CA_UI_PI_RATIO = 0
608 12:12:00.641988 ===================================
609 12:12:00.644322 ===================================
610 12:12:00.649140 memory_type:LPDDR4
611 12:12:00.651853 GP_NUM : 10
612 12:12:00.652307 SRAM_EN : 1
613 12:12:00.655000 MD32_EN : 0
614 12:12:00.658212 ===================================
615 12:12:00.661008 [ANA_INIT] >>>>>>>>>>>>>>
616 12:12:00.661441 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 12:12:00.667763 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 12:12:00.671199 ===================================
619 12:12:00.671823 data_rate = 1600,PCW = 0X7600
620 12:12:00.674314 ===================================
621 12:12:00.678215 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 12:12:00.684614 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 12:12:00.690984 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 12:12:00.694722 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 12:12:00.697762 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 12:12:00.701131 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 12:12:00.704447 [ANA_INIT] flow start
628 12:12:00.704918 [ANA_INIT] PLL >>>>>>>>
629 12:12:00.707593 [ANA_INIT] PLL <<<<<<<<
630 12:12:00.710991 [ANA_INIT] MIDPI >>>>>>>>
631 12:12:00.714625 [ANA_INIT] MIDPI <<<<<<<<
632 12:12:00.715228 [ANA_INIT] DLL >>>>>>>>
633 12:12:00.717458 [ANA_INIT] flow end
634 12:12:00.720633 ============ LP4 DIFF to SE enter ============
635 12:12:00.724441 ============ LP4 DIFF to SE exit ============
636 12:12:00.727540 [ANA_INIT] <<<<<<<<<<<<<
637 12:12:00.731228 [Flow] Enable top DCM control >>>>>
638 12:12:00.734369 [Flow] Enable top DCM control <<<<<
639 12:12:00.737748 Enable DLL master slave shuffle
640 12:12:00.744430 ==============================================================
641 12:12:00.745012 Gating Mode config
642 12:12:00.750556 ==============================================================
643 12:12:00.751123 Config description:
644 12:12:00.761236 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 12:12:00.767492 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 12:12:00.773753 SELPH_MODE 0: By rank 1: By Phase
647 12:12:00.777170 ==============================================================
648 12:12:00.780496 GAT_TRACK_EN = 1
649 12:12:00.784250 RX_GATING_MODE = 2
650 12:12:00.787386 RX_GATING_TRACK_MODE = 2
651 12:12:00.790519 SELPH_MODE = 1
652 12:12:00.793582 PICG_EARLY_EN = 1
653 12:12:00.797001 VALID_LAT_VALUE = 1
654 12:12:00.800469 ==============================================================
655 12:12:00.803544 Enter into Gating configuration >>>>
656 12:12:00.807046 Exit from Gating configuration <<<<
657 12:12:00.810644 Enter into DVFS_PRE_config >>>>>
658 12:12:00.823780 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 12:12:00.827231 Exit from DVFS_PRE_config <<<<<
660 12:12:00.830372 Enter into PICG configuration >>>>
661 12:12:00.833599 Exit from PICG configuration <<<<
662 12:12:00.834067 [RX_INPUT] configuration >>>>>
663 12:12:00.836947 [RX_INPUT] configuration <<<<<
664 12:12:00.844314 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 12:12:00.847458 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 12:12:00.854037 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 12:12:00.860981 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 12:12:00.868166 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 12:12:00.872178 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 12:12:00.875068 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 12:12:00.882931 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 12:12:00.886998 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 12:12:00.890789 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 12:12:00.893709 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 12:12:00.897646 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 12:12:00.900878 ===================================
677 12:12:00.904145 LPDDR4 DRAM CONFIGURATION
678 12:12:00.908253 ===================================
679 12:12:00.908681 EX_ROW_EN[0] = 0x0
680 12:12:00.911788 EX_ROW_EN[1] = 0x0
681 12:12:00.912212 LP4Y_EN = 0x0
682 12:12:00.914966 WORK_FSP = 0x0
683 12:12:00.915458 WL = 0x2
684 12:12:00.918853 RL = 0x2
685 12:12:00.919276 BL = 0x2
686 12:12:00.922162 RPST = 0x0
687 12:12:00.922585 RD_PRE = 0x0
688 12:12:00.926231 WR_PRE = 0x1
689 12:12:00.926673 WR_PST = 0x0
690 12:12:00.930094 DBI_WR = 0x0
691 12:12:00.930636 DBI_RD = 0x0
692 12:12:00.933709 OTF = 0x1
693 12:12:00.934137 ===================================
694 12:12:00.937153 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 12:12:00.945109 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 12:12:00.948401 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 12:12:00.951840 ===================================
698 12:12:00.952265 LPDDR4 DRAM CONFIGURATION
699 12:12:00.955108 ===================================
700 12:12:00.959540 EX_ROW_EN[0] = 0x10
701 12:12:00.960124 EX_ROW_EN[1] = 0x0
702 12:12:00.962926 LP4Y_EN = 0x0
703 12:12:00.963347 WORK_FSP = 0x0
704 12:12:00.966494 WL = 0x2
705 12:12:00.966921 RL = 0x2
706 12:12:00.970043 BL = 0x2
707 12:12:00.970467 RPST = 0x0
708 12:12:00.973388 RD_PRE = 0x0
709 12:12:00.973814 WR_PRE = 0x1
710 12:12:00.977250 WR_PST = 0x0
711 12:12:00.977675 DBI_WR = 0x0
712 12:12:00.980904 DBI_RD = 0x0
713 12:12:00.981381 OTF = 0x1
714 12:12:00.984300 ===================================
715 12:12:00.991707 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 12:12:00.994780 nWR fixed to 40
717 12:12:00.995207 [ModeRegInit_LP4] CH0 RK0
718 12:12:00.998733 [ModeRegInit_LP4] CH0 RK1
719 12:12:01.002676 [ModeRegInit_LP4] CH1 RK0
720 12:12:01.003107 [ModeRegInit_LP4] CH1 RK1
721 12:12:01.006458 match AC timing 13
722 12:12:01.009312 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 12:12:01.013141 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 12:12:01.019720 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 12:12:01.024363 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 12:12:01.026906 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 12:12:01.030444 [EMI DOE] emi_dcm 0
728 12:12:01.033827 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 12:12:01.034360 ==
730 12:12:01.036352 Dram Type= 6, Freq= 0, CH_0, rank 0
731 12:12:01.040690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 12:12:01.041220 ==
733 12:12:01.046603 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 12:12:01.053278 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 12:12:01.062068 [CA 0] Center 37 (6~68) winsize 63
736 12:12:01.065330 [CA 1] Center 36 (6~67) winsize 62
737 12:12:01.068742 [CA 2] Center 34 (4~65) winsize 62
738 12:12:01.072154 [CA 3] Center 34 (4~65) winsize 62
739 12:12:01.075794 [CA 4] Center 33 (3~64) winsize 62
740 12:12:01.079457 [CA 5] Center 33 (3~64) winsize 62
741 12:12:01.080098
742 12:12:01.082410 [CmdBusTrainingLP45] Vref(ca) range 1: 30
743 12:12:01.082882
744 12:12:01.085628 [CATrainingPosCal] consider 1 rank data
745 12:12:01.088353 u2DelayCellTimex100 = 270/100 ps
746 12:12:01.091810 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
747 12:12:01.095289 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
748 12:12:01.099059 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
749 12:12:01.105104 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
750 12:12:01.108448 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
751 12:12:01.112069 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
752 12:12:01.112715
753 12:12:01.115385 CA PerBit enable=1, Macro0, CA PI delay=33
754 12:12:01.115887
755 12:12:01.119083 [CBTSetCACLKResult] CA Dly = 33
756 12:12:01.119785 CS Dly: 6 (0~37)
757 12:12:01.120151 ==
758 12:12:01.121581 Dram Type= 6, Freq= 0, CH_0, rank 1
759 12:12:01.128555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 12:12:01.128982 ==
761 12:12:01.131396 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 12:12:01.138871 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 12:12:01.147974 [CA 0] Center 37 (6~68) winsize 63
764 12:12:01.151911 [CA 1] Center 37 (7~67) winsize 61
765 12:12:01.155447 [CA 2] Center 34 (4~65) winsize 62
766 12:12:01.158373 [CA 3] Center 34 (4~65) winsize 62
767 12:12:01.160920 [CA 4] Center 33 (3~64) winsize 62
768 12:12:01.164425 [CA 5] Center 33 (2~64) winsize 63
769 12:12:01.164852
770 12:12:01.167630 [CmdBusTrainingLP45] Vref(ca) range 1: 32
771 12:12:01.168093
772 12:12:01.171646 [CATrainingPosCal] consider 2 rank data
773 12:12:01.174602 u2DelayCellTimex100 = 270/100 ps
774 12:12:01.177688 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
775 12:12:01.184786 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
776 12:12:01.188093 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
777 12:12:01.192089 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
778 12:12:01.195587 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
779 12:12:01.198954 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
780 12:12:01.199532
781 12:12:01.202583 CA PerBit enable=1, Macro0, CA PI delay=33
782 12:12:01.203051
783 12:12:01.206142 [CBTSetCACLKResult] CA Dly = 33
784 12:12:01.206610 CS Dly: 6 (0~38)
785 12:12:01.206985
786 12:12:01.209965 ----->DramcWriteLeveling(PI) begin...
787 12:12:01.210576 ==
788 12:12:01.213671 Dram Type= 6, Freq= 0, CH_0, rank 0
789 12:12:01.216712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 12:12:01.217213 ==
791 12:12:01.220157 Write leveling (Byte 0): 34 => 34
792 12:12:01.223601 Write leveling (Byte 1): 31 => 31
793 12:12:01.226596 DramcWriteLeveling(PI) end<-----
794 12:12:01.227066
795 12:12:01.227440 ==
796 12:12:01.229897 Dram Type= 6, Freq= 0, CH_0, rank 0
797 12:12:01.233574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 12:12:01.234148 ==
799 12:12:01.236944 [Gating] SW mode calibration
800 12:12:01.243321 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 12:12:01.250563 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 12:12:01.253788 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 12:12:01.260197 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
804 12:12:01.262957 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
805 12:12:01.267053 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 12:12:01.269854 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:12:01.276825 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:12:01.280101 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:12:01.282974 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:12:01.289755 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:12:01.293653 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:12:01.296533 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 12:12:01.303337 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 12:12:01.306332 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 12:12:01.309474 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 12:12:01.316678 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 12:12:01.319775 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 12:12:01.323778 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 12:12:01.329533 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
820 12:12:01.333233 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
821 12:12:01.336290 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
822 12:12:01.343155 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:12:01.346154 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:12:01.350273 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:12:01.356089 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:12:01.360299 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:12:01.363103 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:12:01.369314 0 9 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
829 12:12:01.373218 0 9 12 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
830 12:12:01.376175 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 12:12:01.382463 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 12:12:01.386428 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 12:12:01.389516 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 12:12:01.396265 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 12:12:01.399367 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
836 12:12:01.402418 0 10 8 | B1->B0 | 3333 2a2a | 1 1 | (1 1) (1 0)
837 12:12:01.409529 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
838 12:12:01.412500 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 12:12:01.416454 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 12:12:01.420305 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 12:12:01.426413 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 12:12:01.429946 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 12:12:01.433026 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 12:12:01.439480 0 11 8 | B1->B0 | 2626 3737 | 0 0 | (0 0) (1 1)
845 12:12:01.442303 0 11 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
846 12:12:01.446123 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 12:12:01.452295 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 12:12:01.456611 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 12:12:01.459453 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 12:12:01.466716 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 12:12:01.469065 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
852 12:12:01.472409 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
853 12:12:01.479304 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
854 12:12:01.482456 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 12:12:01.485556 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 12:12:01.493312 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 12:12:01.495969 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 12:12:01.499231 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 12:12:01.505695 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 12:12:01.509540 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 12:12:01.512421 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 12:12:01.516049 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 12:12:01.522565 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 12:12:01.526319 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 12:12:01.529315 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 12:12:01.535725 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 12:12:01.539042 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
868 12:12:01.542828 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
869 12:12:01.549183 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 12:12:01.553182 Total UI for P1: 0, mck2ui 16
871 12:12:01.556260 best dqsien dly found for B0: ( 0, 14, 6)
872 12:12:01.556691 Total UI for P1: 0, mck2ui 16
873 12:12:01.562402 best dqsien dly found for B1: ( 0, 14, 8)
874 12:12:01.566132 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
875 12:12:01.569349 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
876 12:12:01.569823
877 12:12:01.572222 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
878 12:12:01.576764 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
879 12:12:01.579890 [Gating] SW calibration Done
880 12:12:01.580438 ==
881 12:12:01.583127 Dram Type= 6, Freq= 0, CH_0, rank 0
882 12:12:01.587188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
883 12:12:01.587797 ==
884 12:12:01.588175 RX Vref Scan: 0
885 12:12:01.588525
886 12:12:01.589708 RX Vref 0 -> 0, step: 1
887 12:12:01.590178
888 12:12:01.593566 RX Delay -130 -> 252, step: 16
889 12:12:01.597053 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
890 12:12:01.600595 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
891 12:12:01.604175 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
892 12:12:01.608020 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
893 12:12:01.614391 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
894 12:12:01.618375 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
895 12:12:01.622462 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
896 12:12:01.625164 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
897 12:12:01.628795 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
898 12:12:01.632801 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
899 12:12:01.636539 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
900 12:12:01.640604 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
901 12:12:01.644025 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
902 12:12:01.651124 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
903 12:12:01.654344 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
904 12:12:01.657760 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
905 12:12:01.658184 ==
906 12:12:01.661107 Dram Type= 6, Freq= 0, CH_0, rank 0
907 12:12:01.664476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 12:12:01.664900 ==
909 12:12:01.667729 DQS Delay:
910 12:12:01.668152 DQS0 = 0, DQS1 = 0
911 12:12:01.668543 DQM Delay:
912 12:12:01.671497 DQM0 = 85, DQM1 = 71
913 12:12:01.671962 DQ Delay:
914 12:12:01.674638 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
915 12:12:01.677711 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
916 12:12:01.681442 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
917 12:12:01.684241 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
918 12:12:01.684690
919 12:12:01.685062
920 12:12:01.685377 ==
921 12:12:01.687855 Dram Type= 6, Freq= 0, CH_0, rank 0
922 12:12:01.694103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 12:12:01.694671 ==
924 12:12:01.695015
925 12:12:01.695333
926 12:12:01.695644 TX Vref Scan disable
927 12:12:01.697920 == TX Byte 0 ==
928 12:12:01.701356 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
929 12:12:01.704355 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
930 12:12:01.707814 == TX Byte 1 ==
931 12:12:01.711733 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
932 12:12:01.715467 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
933 12:12:01.716032 ==
934 12:12:01.719085 Dram Type= 6, Freq= 0, CH_0, rank 0
935 12:12:01.722400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 12:12:01.722825 ==
937 12:12:01.737478 TX Vref=22, minBit 0, minWin=27, winSum=438
938 12:12:01.741342 TX Vref=24, minBit 8, minWin=27, winSum=445
939 12:12:01.744643 TX Vref=26, minBit 8, minWin=27, winSum=447
940 12:12:01.747528 TX Vref=28, minBit 8, minWin=27, winSum=447
941 12:12:01.751535 TX Vref=30, minBit 10, minWin=27, winSum=448
942 12:12:01.754601 TX Vref=32, minBit 4, minWin=27, winSum=445
943 12:12:01.761174 [TxChooseVref] Worse bit 10, Min win 27, Win sum 448, Final Vref 30
944 12:12:01.761732
945 12:12:01.765078 Final TX Range 1 Vref 30
946 12:12:01.765680
947 12:12:01.766073 ==
948 12:12:01.768224 Dram Type= 6, Freq= 0, CH_0, rank 0
949 12:12:01.771775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 12:12:01.772206 ==
951 12:12:01.772542
952 12:12:01.772858
953 12:12:01.774317 TX Vref Scan disable
954 12:12:01.778286 == TX Byte 0 ==
955 12:12:01.781211 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
956 12:12:01.784327 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
957 12:12:01.788310 == TX Byte 1 ==
958 12:12:01.791175 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
959 12:12:01.795027 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
960 12:12:01.795454
961 12:12:01.797845 [DATLAT]
962 12:12:01.798368 Freq=800, CH0 RK0
963 12:12:01.798710
964 12:12:01.800814 DATLAT Default: 0xa
965 12:12:01.801239 0, 0xFFFF, sum = 0
966 12:12:01.804853 1, 0xFFFF, sum = 0
967 12:12:01.805297 2, 0xFFFF, sum = 0
968 12:12:01.808547 3, 0xFFFF, sum = 0
969 12:12:01.808976 4, 0xFFFF, sum = 0
970 12:12:01.811480 5, 0xFFFF, sum = 0
971 12:12:01.811956 6, 0xFFFF, sum = 0
972 12:12:01.814802 7, 0xFFFF, sum = 0
973 12:12:01.815330 8, 0xFFFF, sum = 0
974 12:12:01.817976 9, 0x0, sum = 1
975 12:12:01.818407 10, 0x0, sum = 2
976 12:12:01.820887 11, 0x0, sum = 3
977 12:12:01.821316 12, 0x0, sum = 4
978 12:12:01.824184 best_step = 10
979 12:12:01.824608
980 12:12:01.824945 ==
981 12:12:01.827723 Dram Type= 6, Freq= 0, CH_0, rank 0
982 12:12:01.830917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 12:12:01.831338 ==
984 12:12:01.831701 RX Vref Scan: 1
985 12:12:01.834097
986 12:12:01.834512 Set Vref Range= 32 -> 127
987 12:12:01.834847
988 12:12:01.837511 RX Vref 32 -> 127, step: 1
989 12:12:01.837931
990 12:12:01.841260 RX Delay -111 -> 252, step: 8
991 12:12:01.841681
992 12:12:01.844577 Set Vref, RX VrefLevel [Byte0]: 32
993 12:12:01.847848 [Byte1]: 32
994 12:12:01.848373
995 12:12:01.851248 Set Vref, RX VrefLevel [Byte0]: 33
996 12:12:01.854049 [Byte1]: 33
997 12:12:01.857844
998 12:12:01.858368 Set Vref, RX VrefLevel [Byte0]: 34
999 12:12:01.861274 [Byte1]: 34
1000 12:12:01.865464
1001 12:12:01.866024 Set Vref, RX VrefLevel [Byte0]: 35
1002 12:12:01.868403 [Byte1]: 35
1003 12:12:01.873556
1004 12:12:01.874138 Set Vref, RX VrefLevel [Byte0]: 36
1005 12:12:01.876377 [Byte1]: 36
1006 12:12:01.880957
1007 12:12:01.881533 Set Vref, RX VrefLevel [Byte0]: 37
1008 12:12:01.884069 [Byte1]: 37
1009 12:12:01.888133
1010 12:12:01.888700 Set Vref, RX VrefLevel [Byte0]: 38
1011 12:12:01.892052 [Byte1]: 38
1012 12:12:01.895820
1013 12:12:01.896282 Set Vref, RX VrefLevel [Byte0]: 39
1014 12:12:01.899600 [Byte1]: 39
1015 12:12:01.904002
1016 12:12:01.904574 Set Vref, RX VrefLevel [Byte0]: 40
1017 12:12:01.906499 [Byte1]: 40
1018 12:12:01.911031
1019 12:12:01.911598 Set Vref, RX VrefLevel [Byte0]: 41
1020 12:12:01.914825 [Byte1]: 41
1021 12:12:01.918475
1022 12:12:01.918896 Set Vref, RX VrefLevel [Byte0]: 42
1023 12:12:01.922245 [Byte1]: 42
1024 12:12:01.926204
1025 12:12:01.926784 Set Vref, RX VrefLevel [Byte0]: 43
1026 12:12:01.929464 [Byte1]: 43
1027 12:12:01.933625
1028 12:12:01.934080 Set Vref, RX VrefLevel [Byte0]: 44
1029 12:12:01.937628 [Byte1]: 44
1030 12:12:01.941886
1031 12:12:01.942468 Set Vref, RX VrefLevel [Byte0]: 45
1032 12:12:01.945650 [Byte1]: 45
1033 12:12:01.949391
1034 12:12:01.949869 Set Vref, RX VrefLevel [Byte0]: 46
1035 12:12:01.953012 [Byte1]: 46
1036 12:12:01.956967
1037 12:12:01.957557 Set Vref, RX VrefLevel [Byte0]: 47
1038 12:12:01.960847 [Byte1]: 47
1039 12:12:01.965684
1040 12:12:01.966196 Set Vref, RX VrefLevel [Byte0]: 48
1041 12:12:01.968089 [Byte1]: 48
1042 12:12:01.972242
1043 12:12:01.975763 Set Vref, RX VrefLevel [Byte0]: 49
1044 12:12:01.976276 [Byte1]: 49
1045 12:12:01.980535
1046 12:12:01.981023 Set Vref, RX VrefLevel [Byte0]: 50
1047 12:12:01.984123 [Byte1]: 50
1048 12:12:01.989352
1049 12:12:01.989907 Set Vref, RX VrefLevel [Byte0]: 51
1050 12:12:01.990848 [Byte1]: 51
1051 12:12:01.995913
1052 12:12:01.996423 Set Vref, RX VrefLevel [Byte0]: 52
1053 12:12:01.999053 [Byte1]: 52
1054 12:12:02.003360
1055 12:12:02.003917 Set Vref, RX VrefLevel [Byte0]: 53
1056 12:12:02.006345 [Byte1]: 53
1057 12:12:02.010789
1058 12:12:02.011363 Set Vref, RX VrefLevel [Byte0]: 54
1059 12:12:02.013988 [Byte1]: 54
1060 12:12:02.018721
1061 12:12:02.019184 Set Vref, RX VrefLevel [Byte0]: 55
1062 12:12:02.021258 [Byte1]: 55
1063 12:12:02.026172
1064 12:12:02.026629 Set Vref, RX VrefLevel [Byte0]: 56
1065 12:12:02.029202 [Byte1]: 56
1066 12:12:02.033325
1067 12:12:02.033740 Set Vref, RX VrefLevel [Byte0]: 57
1068 12:12:02.036621 [Byte1]: 57
1069 12:12:02.041195
1070 12:12:02.041651 Set Vref, RX VrefLevel [Byte0]: 58
1071 12:12:02.045587 [Byte1]: 58
1072 12:12:02.048997
1073 12:12:02.049408 Set Vref, RX VrefLevel [Byte0]: 59
1074 12:12:02.052061 [Byte1]: 59
1075 12:12:02.057326
1076 12:12:02.057848 Set Vref, RX VrefLevel [Byte0]: 60
1077 12:12:02.060081 [Byte1]: 60
1078 12:12:02.064171
1079 12:12:02.064586 Set Vref, RX VrefLevel [Byte0]: 61
1080 12:12:02.067589 [Byte1]: 61
1081 12:12:02.072063
1082 12:12:02.072597 Set Vref, RX VrefLevel [Byte0]: 62
1083 12:12:02.075030 [Byte1]: 62
1084 12:12:02.080212
1085 12:12:02.080757 Set Vref, RX VrefLevel [Byte0]: 63
1086 12:12:02.083803 [Byte1]: 63
1087 12:12:02.087047
1088 12:12:02.087477 Set Vref, RX VrefLevel [Byte0]: 64
1089 12:12:02.091046 [Byte1]: 64
1090 12:12:02.094581
1091 12:12:02.095288 Set Vref, RX VrefLevel [Byte0]: 65
1092 12:12:02.098115 [Byte1]: 65
1093 12:12:02.102482
1094 12:12:02.102993 Set Vref, RX VrefLevel [Byte0]: 66
1095 12:12:02.105265 [Byte1]: 66
1096 12:12:02.110135
1097 12:12:02.110551 Set Vref, RX VrefLevel [Byte0]: 67
1098 12:12:02.113399 [Byte1]: 67
1099 12:12:02.118093
1100 12:12:02.120571 Set Vref, RX VrefLevel [Byte0]: 68
1101 12:12:02.120987 [Byte1]: 68
1102 12:12:02.126102
1103 12:12:02.126693 Set Vref, RX VrefLevel [Byte0]: 69
1104 12:12:02.128671 [Byte1]: 69
1105 12:12:02.132951
1106 12:12:02.133500 Set Vref, RX VrefLevel [Byte0]: 70
1107 12:12:02.136441 [Byte1]: 70
1108 12:12:02.140725
1109 12:12:02.141226 Set Vref, RX VrefLevel [Byte0]: 71
1110 12:12:02.144240 [Byte1]: 71
1111 12:12:02.148197
1112 12:12:02.148651 Set Vref, RX VrefLevel [Byte0]: 72
1113 12:12:02.151562 [Byte1]: 72
1114 12:12:02.156707
1115 12:12:02.157218 Set Vref, RX VrefLevel [Byte0]: 73
1116 12:12:02.159025 [Byte1]: 73
1117 12:12:02.163816
1118 12:12:02.164622 Set Vref, RX VrefLevel [Byte0]: 74
1119 12:12:02.166995 [Byte1]: 74
1120 12:12:02.171074
1121 12:12:02.171561 Set Vref, RX VrefLevel [Byte0]: 75
1122 12:12:02.174719 [Byte1]: 75
1123 12:12:02.178509
1124 12:12:02.179000 Set Vref, RX VrefLevel [Byte0]: 76
1125 12:12:02.181612 [Byte1]: 76
1126 12:12:02.186341
1127 12:12:02.186850 Set Vref, RX VrefLevel [Byte0]: 77
1128 12:12:02.189639 [Byte1]: 77
1129 12:12:02.194118
1130 12:12:02.194558 Set Vref, RX VrefLevel [Byte0]: 78
1131 12:12:02.197700 [Byte1]: 78
1132 12:12:02.201999
1133 12:12:02.202544 Set Vref, RX VrefLevel [Byte0]: 79
1134 12:12:02.204973 [Byte1]: 79
1135 12:12:02.208803
1136 12:12:02.209235 Set Vref, RX VrefLevel [Byte0]: 80
1137 12:12:02.212932 [Byte1]: 80
1138 12:12:02.218316
1139 12:12:02.219034 Set Vref, RX VrefLevel [Byte0]: 81
1140 12:12:02.220273 [Byte1]: 81
1141 12:12:02.225368
1142 12:12:02.225981 Final RX Vref Byte 0 = 67 to rank0
1143 12:12:02.228618 Final RX Vref Byte 1 = 50 to rank0
1144 12:12:02.232653 Final RX Vref Byte 0 = 67 to rank1
1145 12:12:02.235495 Final RX Vref Byte 1 = 50 to rank1==
1146 12:12:02.239431 Dram Type= 6, Freq= 0, CH_0, rank 0
1147 12:12:02.243158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 12:12:02.243580 ==
1149 12:12:02.243991 DQS Delay:
1150 12:12:02.247099 DQS0 = 0, DQS1 = 0
1151 12:12:02.247622 DQM Delay:
1152 12:12:02.250696 DQM0 = 88, DQM1 = 76
1153 12:12:02.251240 DQ Delay:
1154 12:12:02.254384 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1155 12:12:02.259001 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1156 12:12:02.259535 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1157 12:12:02.262170 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1158 12:12:02.262681
1159 12:12:02.263013
1160 12:12:02.272453 [DQSOSCAuto] RK0, (LSB)MR18= 0x4324, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps
1161 12:12:02.272958 CH0 RK0: MR19=606, MR18=4324
1162 12:12:02.279896 CH0_RK0: MR19=0x606, MR18=0x4324, DQSOSC=393, MR23=63, INC=95, DEC=63
1163 12:12:02.280422
1164 12:12:02.283323 ----->DramcWriteLeveling(PI) begin...
1165 12:12:02.283795 ==
1166 12:12:02.286995 Dram Type= 6, Freq= 0, CH_0, rank 1
1167 12:12:02.290454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1168 12:12:02.290878 ==
1169 12:12:02.294644 Write leveling (Byte 0): 31 => 31
1170 12:12:02.298157 Write leveling (Byte 1): 31 => 31
1171 12:12:02.301478 DramcWriteLeveling(PI) end<-----
1172 12:12:02.301985
1173 12:12:02.302316 ==
1174 12:12:02.346028 Dram Type= 6, Freq= 0, CH_0, rank 1
1175 12:12:02.346619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1176 12:12:02.346999 ==
1177 12:12:02.347769 [Gating] SW mode calibration
1178 12:12:02.348147 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1179 12:12:02.348492 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1180 12:12:02.348824 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1181 12:12:02.349147 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1182 12:12:02.349530 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1183 12:12:02.349858 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1184 12:12:02.350173 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 12:12:02.390354 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 12:12:02.391286 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 12:12:02.392173 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 12:12:02.392579 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 12:12:02.393256 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:12:02.393620 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:12:02.394172 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:12:02.394656 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:12:02.394999 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:12:02.395389 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 12:12:02.424027 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 12:12:02.424585 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 12:12:02.424960 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1198 12:12:02.425308 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1199 12:12:02.425638 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 12:12:02.426302 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 12:12:02.426624 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 12:12:02.426918 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 12:12:02.428315 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 12:12:02.435138 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 12:12:02.438054 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 12:12:02.441993 0 9 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
1207 12:12:02.448158 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1208 12:12:02.451589 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1209 12:12:02.454564 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1210 12:12:02.461734 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1211 12:12:02.464451 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1212 12:12:02.468388 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1213 12:12:02.474825 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1214 12:12:02.478478 0 10 8 | B1->B0 | 3131 2b2b | 1 1 | (1 0) (1 1)
1215 12:12:02.481441 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1216 12:12:02.484304 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 12:12:02.490998 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 12:12:02.494967 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 12:12:02.502350 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 12:12:02.504150 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 12:12:02.507542 0 11 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1222 12:12:02.510592 0 11 8 | B1->B0 | 2d2d 3c3c | 0 0 | (0 0) (1 1)
1223 12:12:02.517775 0 11 12 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
1224 12:12:02.520591 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1225 12:12:02.523762 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 12:12:02.531178 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1227 12:12:02.533848 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1228 12:12:02.538013 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1229 12:12:02.544376 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1230 12:12:02.546884 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1231 12:12:02.550594 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 12:12:02.557370 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 12:12:02.560548 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 12:12:02.564042 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 12:12:02.570985 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 12:12:02.573950 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1237 12:12:02.577541 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1238 12:12:02.584353 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1239 12:12:02.587011 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1240 12:12:02.591013 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1241 12:12:02.597341 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1242 12:12:02.600137 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1243 12:12:02.603909 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 12:12:02.609864 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 12:12:02.613838 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1246 12:12:02.617256 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1247 12:12:02.624057 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1248 12:12:02.624614 Total UI for P1: 0, mck2ui 16
1249 12:12:02.630171 best dqsien dly found for B0: ( 0, 14, 6)
1250 12:12:02.630717 Total UI for P1: 0, mck2ui 16
1251 12:12:02.636645 best dqsien dly found for B1: ( 0, 14, 6)
1252 12:12:02.640076 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1253 12:12:02.642964 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1254 12:12:02.643432
1255 12:12:02.646255 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1256 12:12:02.649673 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1257 12:12:02.652997 [Gating] SW calibration Done
1258 12:12:02.653441 ==
1259 12:12:02.656380 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 12:12:02.660105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 12:12:02.660627 ==
1262 12:12:02.663647 RX Vref Scan: 0
1263 12:12:02.664191
1264 12:12:02.664526 RX Vref 0 -> 0, step: 1
1265 12:12:02.664835
1266 12:12:02.666263 RX Delay -130 -> 252, step: 16
1267 12:12:02.670042 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1268 12:12:02.676226 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1269 12:12:02.680299 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1270 12:12:02.683536 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1271 12:12:02.686577 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1272 12:12:02.689699 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1273 12:12:02.696679 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1274 12:12:02.699518 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1275 12:12:02.702728 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1276 12:12:02.706351 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1277 12:12:02.709642 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1278 12:12:02.716340 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1279 12:12:02.719867 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1280 12:12:02.722933 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1281 12:12:02.726724 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1282 12:12:02.732555 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1283 12:12:02.733024 ==
1284 12:12:02.737057 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 12:12:02.739980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 12:12:02.740553 ==
1287 12:12:02.740930 DQS Delay:
1288 12:12:02.742814 DQS0 = 0, DQS1 = 0
1289 12:12:02.743330 DQM Delay:
1290 12:12:02.745669 DQM0 = 83, DQM1 = 77
1291 12:12:02.746234 DQ Delay:
1292 12:12:02.749228 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1293 12:12:02.752444 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1294 12:12:02.755476 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1295 12:12:02.759376 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1296 12:12:02.759957
1297 12:12:02.760302
1298 12:12:02.760617 ==
1299 12:12:02.762476 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 12:12:02.765411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 12:12:02.765887 ==
1302 12:12:02.766263
1303 12:12:02.769340
1304 12:12:02.769851 TX Vref Scan disable
1305 12:12:02.772882 == TX Byte 0 ==
1306 12:12:02.776030 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1307 12:12:02.779120 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1308 12:12:02.782444 == TX Byte 1 ==
1309 12:12:02.785378 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1310 12:12:02.788648 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1311 12:12:02.789069 ==
1312 12:12:02.792115 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 12:12:02.798537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1314 12:12:02.798958 ==
1315 12:12:02.810842 TX Vref=22, minBit 0, minWin=27, winSum=444
1316 12:12:02.813755 TX Vref=24, minBit 8, minWin=27, winSum=449
1317 12:12:02.817210 TX Vref=26, minBit 8, minWin=27, winSum=447
1318 12:12:02.820186 TX Vref=28, minBit 12, minWin=27, winSum=450
1319 12:12:02.824156 TX Vref=30, minBit 4, minWin=27, winSum=447
1320 12:12:02.830539 TX Vref=32, minBit 8, minWin=27, winSum=446
1321 12:12:02.833539 [TxChooseVref] Worse bit 12, Min win 27, Win sum 450, Final Vref 28
1322 12:12:02.834086
1323 12:12:02.836904 Final TX Range 1 Vref 28
1324 12:12:02.837421
1325 12:12:02.837750 ==
1326 12:12:02.840168 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 12:12:02.843829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 12:12:02.847209 ==
1329 12:12:02.847766
1330 12:12:02.848107
1331 12:12:02.848417 TX Vref Scan disable
1332 12:12:02.850770 == TX Byte 0 ==
1333 12:12:02.854092 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1334 12:12:02.861522 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1335 12:12:02.862034 == TX Byte 1 ==
1336 12:12:02.863561 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1337 12:12:02.870583 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1338 12:12:02.871094
1339 12:12:02.871427 [DATLAT]
1340 12:12:02.871771 Freq=800, CH0 RK1
1341 12:12:02.872078
1342 12:12:02.873979 DATLAT Default: 0xa
1343 12:12:02.874499 0, 0xFFFF, sum = 0
1344 12:12:02.876778 1, 0xFFFF, sum = 0
1345 12:12:02.877201 2, 0xFFFF, sum = 0
1346 12:12:02.880855 3, 0xFFFF, sum = 0
1347 12:12:02.884069 4, 0xFFFF, sum = 0
1348 12:12:02.884613 5, 0xFFFF, sum = 0
1349 12:12:02.886986 6, 0xFFFF, sum = 0
1350 12:12:02.887475 7, 0xFFFF, sum = 0
1351 12:12:02.890825 8, 0xFFFF, sum = 0
1352 12:12:02.891343 9, 0x0, sum = 1
1353 12:12:02.894533 10, 0x0, sum = 2
1354 12:12:02.895058 11, 0x0, sum = 3
1355 12:12:02.895399 12, 0x0, sum = 4
1356 12:12:02.897118 best_step = 10
1357 12:12:02.897537
1358 12:12:02.897883 ==
1359 12:12:02.899979 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 12:12:02.903494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 12:12:02.904084 ==
1362 12:12:02.907004 RX Vref Scan: 0
1363 12:12:02.907515
1364 12:12:02.909872 RX Vref 0 -> 0, step: 1
1365 12:12:02.910472
1366 12:12:02.910813 RX Delay -111 -> 252, step: 8
1367 12:12:02.917146 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1368 12:12:02.920863 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1369 12:12:02.924143 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1370 12:12:02.928122 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1371 12:12:02.930759 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1372 12:12:02.937820 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1373 12:12:02.940393 iDelay=217, Bit 6, Center 96 (-15 ~ 208) 224
1374 12:12:02.943709 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1375 12:12:02.946857 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1376 12:12:02.950788 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1377 12:12:02.957046 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1378 12:12:02.960619 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1379 12:12:02.963874 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1380 12:12:02.967728 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1381 12:12:02.973918 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1382 12:12:02.976799 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1383 12:12:02.977351 ==
1384 12:12:02.979905 Dram Type= 6, Freq= 0, CH_0, rank 1
1385 12:12:02.983816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 12:12:02.984366 ==
1387 12:12:02.986727 DQS Delay:
1388 12:12:02.987186 DQS0 = 0, DQS1 = 0
1389 12:12:02.987621 DQM Delay:
1390 12:12:02.990152 DQM0 = 86, DQM1 = 77
1391 12:12:02.990700 DQ Delay:
1392 12:12:02.993812 DQ0 =84, DQ1 =92, DQ2 =76, DQ3 =84
1393 12:12:02.997195 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =96
1394 12:12:03.000653 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1395 12:12:03.003467 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1396 12:12:03.004031
1397 12:12:03.004370
1398 12:12:03.013610 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f05, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1399 12:12:03.014117 CH0 RK1: MR19=606, MR18=3F05
1400 12:12:03.020490 CH0_RK1: MR19=0x606, MR18=0x3F05, DQSOSC=393, MR23=63, INC=95, DEC=63
1401 12:12:03.023212 [RxdqsGatingPostProcess] freq 800
1402 12:12:03.030623 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1403 12:12:03.033466 Pre-setting of DQS Precalculation
1404 12:12:03.036865 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1405 12:12:03.037381 ==
1406 12:12:03.040691 Dram Type= 6, Freq= 0, CH_1, rank 0
1407 12:12:03.046448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 12:12:03.046872 ==
1409 12:12:03.049865 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 12:12:03.056473 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 12:12:03.065839 [CA 0] Center 36 (6~67) winsize 62
1412 12:12:03.069139 [CA 1] Center 36 (6~67) winsize 62
1413 12:12:03.072148 [CA 2] Center 34 (4~65) winsize 62
1414 12:12:03.075451 [CA 3] Center 34 (4~65) winsize 62
1415 12:12:03.079183 [CA 4] Center 34 (4~65) winsize 62
1416 12:12:03.082844 [CA 5] Center 34 (3~65) winsize 63
1417 12:12:03.083048
1418 12:12:03.085224 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1419 12:12:03.085404
1420 12:12:03.088425 [CATrainingPosCal] consider 1 rank data
1421 12:12:03.092677 u2DelayCellTimex100 = 270/100 ps
1422 12:12:03.095146 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 12:12:03.102824 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 12:12:03.105587 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1425 12:12:03.109169 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 12:12:03.111641 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1427 12:12:03.115826 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1428 12:12:03.116212
1429 12:12:03.118890 CA PerBit enable=1, Macro0, CA PI delay=34
1430 12:12:03.119376
1431 12:12:03.121591 [CBTSetCACLKResult] CA Dly = 34
1432 12:12:03.121977 CS Dly: 5 (0~36)
1433 12:12:03.125650 ==
1434 12:12:03.128638 Dram Type= 6, Freq= 0, CH_1, rank 1
1435 12:12:03.132322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 12:12:03.132790 ==
1437 12:12:03.136544 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1438 12:12:03.142060 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1439 12:12:03.152145 [CA 0] Center 36 (6~67) winsize 62
1440 12:12:03.155740 [CA 1] Center 36 (6~67) winsize 62
1441 12:12:03.159175 [CA 2] Center 34 (4~65) winsize 62
1442 12:12:03.162784 [CA 3] Center 34 (3~65) winsize 63
1443 12:12:03.165653 [CA 4] Center 34 (4~65) winsize 62
1444 12:12:03.168694 [CA 5] Center 34 (4~65) winsize 62
1445 12:12:03.169157
1446 12:12:03.171751 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1447 12:12:03.172221
1448 12:12:03.175983 [CATrainingPosCal] consider 2 rank data
1449 12:12:03.178830 u2DelayCellTimex100 = 270/100 ps
1450 12:12:03.182350 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1451 12:12:03.185190 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1452 12:12:03.192607 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1453 12:12:03.195373 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1454 12:12:03.198704 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1455 12:12:03.201679 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1456 12:12:03.202238
1457 12:12:03.204965 CA PerBit enable=1, Macro0, CA PI delay=34
1458 12:12:03.205578
1459 12:12:03.208635 [CBTSetCACLKResult] CA Dly = 34
1460 12:12:03.209195 CS Dly: 6 (0~38)
1461 12:12:03.209568
1462 12:12:03.211588 ----->DramcWriteLeveling(PI) begin...
1463 12:12:03.214888 ==
1464 12:12:03.218982 Dram Type= 6, Freq= 0, CH_1, rank 0
1465 12:12:03.221619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1466 12:12:03.222087 ==
1467 12:12:03.225256 Write leveling (Byte 0): 27 => 27
1468 12:12:03.228446 Write leveling (Byte 1): 28 => 28
1469 12:12:03.231503 DramcWriteLeveling(PI) end<-----
1470 12:12:03.231987
1471 12:12:03.232364 ==
1472 12:12:03.234865 Dram Type= 6, Freq= 0, CH_1, rank 0
1473 12:12:03.238708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1474 12:12:03.239264 ==
1475 12:12:03.241299 [Gating] SW mode calibration
1476 12:12:03.248284 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1477 12:12:03.254660 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1478 12:12:03.257645 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1479 12:12:03.261411 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1480 12:12:03.268107 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1481 12:12:03.271140 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 12:12:03.274543 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 12:12:03.281069 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 12:12:03.284517 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 12:12:03.287454 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:12:03.293924 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:12:03.298086 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:12:03.301200 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:12:03.307828 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:12:03.310936 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:12:03.314185 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 12:12:03.320562 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 12:12:03.323981 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 12:12:03.327313 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1495 12:12:03.334849 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1496 12:12:03.338135 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 12:12:03.340429 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 12:12:03.343667 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 12:12:03.350612 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 12:12:03.353916 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 12:12:03.357172 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 12:12:03.363789 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 12:12:03.367197 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1504 12:12:03.371508 0 9 8 | B1->B0 | 2d2d 2e2e | 0 1 | (0 0) (1 1)
1505 12:12:03.377199 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1506 12:12:03.379999 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1507 12:12:03.383750 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1508 12:12:03.390157 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1509 12:12:03.393273 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1510 12:12:03.396923 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1511 12:12:03.403494 0 10 4 | B1->B0 | 3434 3131 | 0 1 | (1 0) (0 0)
1512 12:12:03.407865 0 10 8 | B1->B0 | 2b2b 2525 | 0 0 | (1 1) (0 0)
1513 12:12:03.410248 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 12:12:03.417135 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 12:12:03.420059 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 12:12:03.423580 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 12:12:03.431283 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 12:12:03.433404 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 12:12:03.436610 0 11 4 | B1->B0 | 2a2a 2929 | 0 0 | (0 0) (0 0)
1520 12:12:03.443363 0 11 8 | B1->B0 | 3636 3d3d | 1 0 | (0 0) (0 0)
1521 12:12:03.447309 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1522 12:12:03.450079 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1523 12:12:03.457171 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1524 12:12:03.459734 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1525 12:12:03.463484 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1526 12:12:03.470015 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1527 12:12:03.473034 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1528 12:12:03.475858 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 12:12:03.483300 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 12:12:03.486063 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 12:12:03.490156 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 12:12:03.496252 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 12:12:03.499163 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 12:12:03.503747 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 12:12:03.509243 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1536 12:12:03.513301 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1537 12:12:03.518157 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1538 12:12:03.522668 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1539 12:12:03.525895 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1540 12:12:03.529342 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 12:12:03.536009 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 12:12:03.539601 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 12:12:03.542641 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1544 12:12:03.549535 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1545 12:12:03.550100 Total UI for P1: 0, mck2ui 16
1546 12:12:03.552328 best dqsien dly found for B0: ( 0, 14, 4)
1547 12:12:03.556314 Total UI for P1: 0, mck2ui 16
1548 12:12:03.559403 best dqsien dly found for B1: ( 0, 14, 6)
1549 12:12:03.563216 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1550 12:12:03.569592 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1551 12:12:03.570159
1552 12:12:03.572620 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1553 12:12:03.576005 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1554 12:12:03.579205 [Gating] SW calibration Done
1555 12:12:03.579753 ==
1556 12:12:03.582980 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 12:12:03.585589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1558 12:12:03.586134 ==
1559 12:12:03.586500 RX Vref Scan: 0
1560 12:12:03.589139
1561 12:12:03.589607 RX Vref 0 -> 0, step: 1
1562 12:12:03.589976
1563 12:12:03.592707 RX Delay -130 -> 252, step: 16
1564 12:12:03.595828 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1565 12:12:03.602239 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1566 12:12:03.606016 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1567 12:12:03.609413 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1568 12:12:03.612127 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1569 12:12:03.615607 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1570 12:12:03.622157 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1571 12:12:03.625988 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1572 12:12:03.630198 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1573 12:12:03.631852 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1574 12:12:03.635497 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1575 12:12:03.642477 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1576 12:12:03.645169 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1577 12:12:03.648858 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1578 12:12:03.651546 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1579 12:12:03.655335 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1580 12:12:03.658625 ==
1581 12:12:03.662320 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 12:12:03.665255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 12:12:03.665825 ==
1584 12:12:03.666196 DQS Delay:
1585 12:12:03.668920 DQS0 = 0, DQS1 = 0
1586 12:12:03.669481 DQM Delay:
1587 12:12:03.671545 DQM0 = 89, DQM1 = 79
1588 12:12:03.672154 DQ Delay:
1589 12:12:03.675288 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1590 12:12:03.678628 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1591 12:12:03.681845 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1592 12:12:03.684835 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1593 12:12:03.685254
1594 12:12:03.685581
1595 12:12:03.685891 ==
1596 12:12:03.688419 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 12:12:03.691443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 12:12:03.692060 ==
1599 12:12:03.692512
1600 12:12:03.692927
1601 12:12:03.694721 TX Vref Scan disable
1602 12:12:03.698498 == TX Byte 0 ==
1603 12:12:03.701710 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1604 12:12:03.704993 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1605 12:12:03.708286 == TX Byte 1 ==
1606 12:12:03.712026 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1607 12:12:03.714668 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1608 12:12:03.715276 ==
1609 12:12:03.718213 Dram Type= 6, Freq= 0, CH_1, rank 0
1610 12:12:03.724789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1611 12:12:03.725207 ==
1612 12:12:03.736344 TX Vref=22, minBit 9, minWin=27, winSum=446
1613 12:12:03.739838 TX Vref=24, minBit 8, minWin=27, winSum=446
1614 12:12:03.743725 TX Vref=26, minBit 10, minWin=27, winSum=452
1615 12:12:03.746452 TX Vref=28, minBit 10, minWin=27, winSum=449
1616 12:12:03.750767 TX Vref=30, minBit 8, minWin=27, winSum=450
1617 12:12:03.756301 TX Vref=32, minBit 8, minWin=27, winSum=447
1618 12:12:03.759704 [TxChooseVref] Worse bit 10, Min win 27, Win sum 452, Final Vref 26
1619 12:12:03.760192
1620 12:12:03.763506 Final TX Range 1 Vref 26
1621 12:12:03.764107
1622 12:12:03.764481 ==
1623 12:12:03.765952 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 12:12:03.772306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 12:12:03.772819 ==
1626 12:12:03.773163
1627 12:12:03.773480
1628 12:12:03.773777 TX Vref Scan disable
1629 12:12:03.776688 == TX Byte 0 ==
1630 12:12:03.779915 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1631 12:12:03.784084 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1632 12:12:03.786608 == TX Byte 1 ==
1633 12:12:03.790400 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1634 12:12:03.796833 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1635 12:12:03.797401
1636 12:12:03.797776 [DATLAT]
1637 12:12:03.798122 Freq=800, CH1 RK0
1638 12:12:03.798566
1639 12:12:03.800247 DATLAT Default: 0xa
1640 12:12:03.800893 0, 0xFFFF, sum = 0
1641 12:12:03.802923 1, 0xFFFF, sum = 0
1642 12:12:03.803497 2, 0xFFFF, sum = 0
1643 12:12:03.807017 3, 0xFFFF, sum = 0
1644 12:12:03.810296 4, 0xFFFF, sum = 0
1645 12:12:03.810827 5, 0xFFFF, sum = 0
1646 12:12:03.813514 6, 0xFFFF, sum = 0
1647 12:12:03.813939 7, 0xFFFF, sum = 0
1648 12:12:03.816971 8, 0xFFFF, sum = 0
1649 12:12:03.817394 9, 0x0, sum = 1
1650 12:12:03.817731 10, 0x0, sum = 2
1651 12:12:03.820056 11, 0x0, sum = 3
1652 12:12:03.820472 12, 0x0, sum = 4
1653 12:12:03.823098 best_step = 10
1654 12:12:03.823510
1655 12:12:03.823878 ==
1656 12:12:03.826454 Dram Type= 6, Freq= 0, CH_1, rank 0
1657 12:12:03.829971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1658 12:12:03.830497 ==
1659 12:12:03.833595 RX Vref Scan: 1
1660 12:12:03.834112
1661 12:12:03.836134 Set Vref Range= 32 -> 127
1662 12:12:03.836549
1663 12:12:03.836943 RX Vref 32 -> 127, step: 1
1664 12:12:03.837259
1665 12:12:03.839787 RX Delay -95 -> 252, step: 8
1666 12:12:03.840301
1667 12:12:03.842622 Set Vref, RX VrefLevel [Byte0]: 32
1668 12:12:03.845925 [Byte1]: 32
1669 12:12:03.846457
1670 12:12:03.849571 Set Vref, RX VrefLevel [Byte0]: 33
1671 12:12:03.853387 [Byte1]: 33
1672 12:12:03.856683
1673 12:12:03.857202 Set Vref, RX VrefLevel [Byte0]: 34
1674 12:12:03.860478 [Byte1]: 34
1675 12:12:03.864847
1676 12:12:03.865362 Set Vref, RX VrefLevel [Byte0]: 35
1677 12:12:03.868356 [Byte1]: 35
1678 12:12:03.872229
1679 12:12:03.872748 Set Vref, RX VrefLevel [Byte0]: 36
1680 12:12:03.875155 [Byte1]: 36
1681 12:12:03.879762
1682 12:12:03.880272 Set Vref, RX VrefLevel [Byte0]: 37
1683 12:12:03.883063 [Byte1]: 37
1684 12:12:03.887751
1685 12:12:03.888162 Set Vref, RX VrefLevel [Byte0]: 38
1686 12:12:03.890529 [Byte1]: 38
1687 12:12:03.895374
1688 12:12:03.895936 Set Vref, RX VrefLevel [Byte0]: 39
1689 12:12:03.898382 [Byte1]: 39
1690 12:12:03.902684
1691 12:12:03.903209 Set Vref, RX VrefLevel [Byte0]: 40
1692 12:12:03.906102 [Byte1]: 40
1693 12:12:03.910037
1694 12:12:03.910605 Set Vref, RX VrefLevel [Byte0]: 41
1695 12:12:03.916330 [Byte1]: 41
1696 12:12:03.916879
1697 12:12:03.919832 Set Vref, RX VrefLevel [Byte0]: 42
1698 12:12:03.923033 [Byte1]: 42
1699 12:12:03.923501
1700 12:12:03.927340 Set Vref, RX VrefLevel [Byte0]: 43
1701 12:12:03.930013 [Byte1]: 43
1702 12:12:03.930580
1703 12:12:03.933454 Set Vref, RX VrefLevel [Byte0]: 44
1704 12:12:03.936831 [Byte1]: 44
1705 12:12:03.940458
1706 12:12:03.941027 Set Vref, RX VrefLevel [Byte0]: 45
1707 12:12:03.943854 [Byte1]: 45
1708 12:12:03.948699
1709 12:12:03.949267 Set Vref, RX VrefLevel [Byte0]: 46
1710 12:12:03.951328 [Byte1]: 46
1711 12:12:03.955849
1712 12:12:03.956433 Set Vref, RX VrefLevel [Byte0]: 47
1713 12:12:03.959427 [Byte1]: 47
1714 12:12:03.964184
1715 12:12:03.964768 Set Vref, RX VrefLevel [Byte0]: 48
1716 12:12:03.966642 [Byte1]: 48
1717 12:12:03.970828
1718 12:12:03.971409 Set Vref, RX VrefLevel [Byte0]: 49
1719 12:12:03.974274 [Byte1]: 49
1720 12:12:03.979006
1721 12:12:03.979570 Set Vref, RX VrefLevel [Byte0]: 50
1722 12:12:03.981681 [Byte1]: 50
1723 12:12:03.987394
1724 12:12:03.988029 Set Vref, RX VrefLevel [Byte0]: 51
1725 12:12:03.989368 [Byte1]: 51
1726 12:12:03.994832
1727 12:12:03.995396 Set Vref, RX VrefLevel [Byte0]: 52
1728 12:12:03.997024 [Byte1]: 52
1729 12:12:04.000895
1730 12:12:04.001357 Set Vref, RX VrefLevel [Byte0]: 53
1731 12:12:04.004577 [Byte1]: 53
1732 12:12:04.008865
1733 12:12:04.009423 Set Vref, RX VrefLevel [Byte0]: 54
1734 12:12:04.015254 [Byte1]: 54
1735 12:12:04.016055
1736 12:12:04.018610 Set Vref, RX VrefLevel [Byte0]: 55
1737 12:12:04.021671 [Byte1]: 55
1738 12:12:04.022237
1739 12:12:04.025501 Set Vref, RX VrefLevel [Byte0]: 56
1740 12:12:04.028670 [Byte1]: 56
1741 12:12:04.029136
1742 12:12:04.032002 Set Vref, RX VrefLevel [Byte0]: 57
1743 12:12:04.035838 [Byte1]: 57
1744 12:12:04.039410
1745 12:12:04.040026 Set Vref, RX VrefLevel [Byte0]: 58
1746 12:12:04.042881 [Byte1]: 58
1747 12:12:04.046865
1748 12:12:04.047431 Set Vref, RX VrefLevel [Byte0]: 59
1749 12:12:04.050284 [Byte1]: 59
1750 12:12:04.054257
1751 12:12:04.054817 Set Vref, RX VrefLevel [Byte0]: 60
1752 12:12:04.057869 [Byte1]: 60
1753 12:12:04.062093
1754 12:12:04.062662 Set Vref, RX VrefLevel [Byte0]: 61
1755 12:12:04.065113 [Byte1]: 61
1756 12:12:04.069785
1757 12:12:04.070345 Set Vref, RX VrefLevel [Byte0]: 62
1758 12:12:04.073805 [Byte1]: 62
1759 12:12:04.077703
1760 12:12:04.078167 Set Vref, RX VrefLevel [Byte0]: 63
1761 12:12:04.080318 [Byte1]: 63
1762 12:12:04.084869
1763 12:12:04.085427 Set Vref, RX VrefLevel [Byte0]: 64
1764 12:12:04.088654 [Byte1]: 64
1765 12:12:04.092488
1766 12:12:04.092954 Set Vref, RX VrefLevel [Byte0]: 65
1767 12:12:04.096297 [Byte1]: 65
1768 12:12:04.099907
1769 12:12:04.100469 Set Vref, RX VrefLevel [Byte0]: 66
1770 12:12:04.103598 [Byte1]: 66
1771 12:12:04.107814
1772 12:12:04.108390 Set Vref, RX VrefLevel [Byte0]: 67
1773 12:12:04.111041 [Byte1]: 67
1774 12:12:04.115097
1775 12:12:04.115736 Set Vref, RX VrefLevel [Byte0]: 68
1776 12:12:04.118382 [Byte1]: 68
1777 12:12:04.122344
1778 12:12:04.122827 Set Vref, RX VrefLevel [Byte0]: 69
1779 12:12:04.126568 [Byte1]: 69
1780 12:12:04.131090
1781 12:12:04.131723 Set Vref, RX VrefLevel [Byte0]: 70
1782 12:12:04.133329 [Byte1]: 70
1783 12:12:04.138298
1784 12:12:04.138873 Set Vref, RX VrefLevel [Byte0]: 71
1785 12:12:04.141175 [Byte1]: 71
1786 12:12:04.145597
1787 12:12:04.146092 Set Vref, RX VrefLevel [Byte0]: 72
1788 12:12:04.149299 [Byte1]: 72
1789 12:12:04.152721
1790 12:12:04.153203 Set Vref, RX VrefLevel [Byte0]: 73
1791 12:12:04.156312 [Byte1]: 73
1792 12:12:04.160726
1793 12:12:04.161302 Set Vref, RX VrefLevel [Byte0]: 74
1794 12:12:04.164186 [Byte1]: 74
1795 12:12:04.168061
1796 12:12:04.168633 Set Vref, RX VrefLevel [Byte0]: 75
1797 12:12:04.171579 [Byte1]: 75
1798 12:12:04.176235
1799 12:12:04.176966 Set Vref, RX VrefLevel [Byte0]: 76
1800 12:12:04.179752 [Byte1]: 76
1801 12:12:04.183827
1802 12:12:04.184406 Set Vref, RX VrefLevel [Byte0]: 77
1803 12:12:04.186626 [Byte1]: 77
1804 12:12:04.191227
1805 12:12:04.191732 Set Vref, RX VrefLevel [Byte0]: 78
1806 12:12:04.194486 [Byte1]: 78
1807 12:12:04.198838
1808 12:12:04.199430 Final RX Vref Byte 0 = 56 to rank0
1809 12:12:04.201926 Final RX Vref Byte 1 = 67 to rank0
1810 12:12:04.205675 Final RX Vref Byte 0 = 56 to rank1
1811 12:12:04.208865 Final RX Vref Byte 1 = 67 to rank1==
1812 12:12:04.212671 Dram Type= 6, Freq= 0, CH_1, rank 0
1813 12:12:04.218383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 12:12:04.218950 ==
1815 12:12:04.219442 DQS Delay:
1816 12:12:04.222063 DQS0 = 0, DQS1 = 0
1817 12:12:04.222704 DQM Delay:
1818 12:12:04.223196 DQM0 = 86, DQM1 = 78
1819 12:12:04.225206 DQ Delay:
1820 12:12:04.229577 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1821 12:12:04.231510 DQ4 =80, DQ5 =100, DQ6 =100, DQ7 =80
1822 12:12:04.235442 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
1823 12:12:04.238620 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1824 12:12:04.239199
1825 12:12:04.239812
1826 12:12:04.245723 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f1b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1827 12:12:04.248361 CH1 RK0: MR19=606, MR18=2F1B
1828 12:12:04.254973 CH1_RK0: MR19=0x606, MR18=0x2F1B, DQSOSC=397, MR23=63, INC=93, DEC=62
1829 12:12:04.255548
1830 12:12:04.258969 ----->DramcWriteLeveling(PI) begin...
1831 12:12:04.259548 ==
1832 12:12:04.261549 Dram Type= 6, Freq= 0, CH_1, rank 1
1833 12:12:04.265265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 12:12:04.265836 ==
1835 12:12:04.268225 Write leveling (Byte 0): 26 => 26
1836 12:12:04.272572 Write leveling (Byte 1): 29 => 29
1837 12:12:04.274520 DramcWriteLeveling(PI) end<-----
1838 12:12:04.274985
1839 12:12:04.275355 ==
1840 12:12:04.278166 Dram Type= 6, Freq= 0, CH_1, rank 1
1841 12:12:04.281326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1842 12:12:04.281793 ==
1843 12:12:04.285656 [Gating] SW mode calibration
1844 12:12:04.291636 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1845 12:12:04.297948 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1846 12:12:04.301488 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1847 12:12:04.309195 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1848 12:12:04.311524 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 12:12:04.314866 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 12:12:04.321622 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 12:12:04.324620 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 12:12:04.328222 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 12:12:04.331541 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 12:12:04.338309 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 12:12:04.341075 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 12:12:04.344420 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 12:12:04.350882 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 12:12:04.354986 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 12:12:04.358091 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 12:12:04.364340 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 12:12:04.367965 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 12:12:04.370987 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 12:12:04.377997 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1864 12:12:04.381331 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 12:12:04.384172 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 12:12:04.390903 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 12:12:04.394961 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 12:12:04.397740 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 12:12:04.404539 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 12:12:04.407581 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 12:12:04.411133 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 12:12:04.417708 0 9 8 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
1873 12:12:04.420898 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 12:12:04.424405 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 12:12:04.430984 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1876 12:12:04.434037 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1877 12:12:04.438044 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1878 12:12:04.444369 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1879 12:12:04.447363 0 10 4 | B1->B0 | 3131 3434 | 1 1 | (1 0) (1 0)
1880 12:12:04.451479 0 10 8 | B1->B0 | 2424 2f2f | 0 1 | (0 0) (1 0)
1881 12:12:04.454176 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 12:12:04.461122 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 12:12:04.464076 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 12:12:04.468197 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 12:12:04.474439 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 12:12:04.477243 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 12:12:04.480556 0 11 4 | B1->B0 | 3030 2928 | 0 1 | (0 0) (0 0)
1888 12:12:04.487571 0 11 8 | B1->B0 | 4141 3a3a | 0 0 | (0 0) (0 0)
1889 12:12:04.490604 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 12:12:04.494275 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 12:12:04.500704 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 12:12:04.503967 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 12:12:04.507121 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 12:12:04.514571 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1895 12:12:04.517240 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1896 12:12:04.520721 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 12:12:04.527449 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 12:12:04.531237 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 12:12:04.534074 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 12:12:04.541062 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 12:12:04.544402 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 12:12:04.547459 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 12:12:04.553587 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 12:12:04.557114 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 12:12:04.560424 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 12:12:04.567514 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 12:12:04.570299 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 12:12:04.573477 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 12:12:04.580409 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 12:12:04.583817 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 12:12:04.586804 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1912 12:12:04.593987 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1913 12:12:04.594515 Total UI for P1: 0, mck2ui 16
1914 12:12:04.599908 best dqsien dly found for B1: ( 0, 14, 4)
1915 12:12:04.603633 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 12:12:04.606646 Total UI for P1: 0, mck2ui 16
1917 12:12:04.609870 best dqsien dly found for B0: ( 0, 14, 6)
1918 12:12:04.613084 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1919 12:12:04.616792 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1920 12:12:04.617321
1921 12:12:04.619469 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1922 12:12:04.622943 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1923 12:12:04.626434 [Gating] SW calibration Done
1924 12:12:04.626861 ==
1925 12:12:04.630067 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 12:12:04.632869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 12:12:04.636948 ==
1928 12:12:04.637370 RX Vref Scan: 0
1929 12:12:04.637706
1930 12:12:04.639882 RX Vref 0 -> 0, step: 1
1931 12:12:04.640303
1932 12:12:04.643116 RX Delay -130 -> 252, step: 16
1933 12:12:04.646237 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1934 12:12:04.650813 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1935 12:12:04.653190 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1936 12:12:04.656353 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1937 12:12:04.663960 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1938 12:12:04.666710 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1939 12:12:04.669959 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1940 12:12:04.672779 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1941 12:12:04.675733 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1942 12:12:04.682498 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1943 12:12:04.685805 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1944 12:12:04.689628 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1945 12:12:04.692389 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1946 12:12:04.699482 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1947 12:12:04.702414 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1948 12:12:04.705925 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1949 12:12:04.706456 ==
1950 12:12:04.709131 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 12:12:04.712198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 12:12:04.712620 ==
1953 12:12:04.715651 DQS Delay:
1954 12:12:04.716214 DQS0 = 0, DQS1 = 0
1955 12:12:04.718975 DQM Delay:
1956 12:12:04.719484 DQM0 = 86, DQM1 = 78
1957 12:12:04.720016 DQ Delay:
1958 12:12:04.722355 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1959 12:12:04.725227 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1960 12:12:04.728891 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1961 12:12:04.732289 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1962 12:12:04.732818
1963 12:12:04.733167
1964 12:12:04.735388 ==
1965 12:12:04.739182 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 12:12:04.742696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 12:12:04.743225 ==
1968 12:12:04.743605
1969 12:12:04.744138
1970 12:12:04.745573 TX Vref Scan disable
1971 12:12:04.745991 == TX Byte 0 ==
1972 12:12:04.752352 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1973 12:12:04.755547 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1974 12:12:04.756017 == TX Byte 1 ==
1975 12:12:04.762266 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1976 12:12:04.765181 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1977 12:12:04.765625 ==
1978 12:12:04.768185 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 12:12:04.772458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 12:12:04.772988 ==
1981 12:12:04.785368 TX Vref=22, minBit 1, minWin=27, winSum=442
1982 12:12:04.788824 TX Vref=24, minBit 1, minWin=27, winSum=445
1983 12:12:04.792212 TX Vref=26, minBit 1, minWin=27, winSum=447
1984 12:12:04.796162 TX Vref=28, minBit 13, minWin=27, winSum=450
1985 12:12:04.798474 TX Vref=30, minBit 13, minWin=27, winSum=449
1986 12:12:04.805650 TX Vref=32, minBit 8, minWin=27, winSum=448
1987 12:12:04.808554 [TxChooseVref] Worse bit 13, Min win 27, Win sum 450, Final Vref 28
1988 12:12:04.809097
1989 12:12:04.811832 Final TX Range 1 Vref 28
1990 12:12:04.812361
1991 12:12:04.812701 ==
1992 12:12:04.815041 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 12:12:04.821423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 12:12:04.821940 ==
1995 12:12:04.822276
1996 12:12:04.822590
1997 12:12:04.822888 TX Vref Scan disable
1998 12:12:04.825511 == TX Byte 0 ==
1999 12:12:04.829177 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2000 12:12:04.835791 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2001 12:12:04.836218 == TX Byte 1 ==
2002 12:12:04.838595 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2003 12:12:04.845585 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2004 12:12:04.846100
2005 12:12:04.846460 [DATLAT]
2006 12:12:04.846777 Freq=800, CH1 RK1
2007 12:12:04.847124
2008 12:12:04.848636 DATLAT Default: 0xa
2009 12:12:04.849058 0, 0xFFFF, sum = 0
2010 12:12:04.851916 1, 0xFFFF, sum = 0
2011 12:12:04.852383 2, 0xFFFF, sum = 0
2012 12:12:04.855381 3, 0xFFFF, sum = 0
2013 12:12:04.859146 4, 0xFFFF, sum = 0
2014 12:12:04.859715 5, 0xFFFF, sum = 0
2015 12:12:04.862600 6, 0xFFFF, sum = 0
2016 12:12:04.863137 7, 0xFFFF, sum = 0
2017 12:12:04.865724 8, 0xFFFF, sum = 0
2018 12:12:04.866274 9, 0x0, sum = 1
2019 12:12:04.866623 10, 0x0, sum = 2
2020 12:12:04.869119 11, 0x0, sum = 3
2021 12:12:04.869549 12, 0x0, sum = 4
2022 12:12:04.872421 best_step = 10
2023 12:12:04.872841
2024 12:12:04.873172 ==
2025 12:12:04.875591 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 12:12:04.878700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 12:12:04.879123 ==
2028 12:12:04.884250 RX Vref Scan: 0
2029 12:12:04.884769
2030 12:12:04.885107 RX Vref 0 -> 0, step: 1
2031 12:12:04.885422
2032 12:12:04.886072 RX Delay -95 -> 252, step: 8
2033 12:12:04.892342 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2034 12:12:04.895506 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2035 12:12:04.898932 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2036 12:12:04.902523 iDelay=217, Bit 3, Center 88 (-23 ~ 200) 224
2037 12:12:04.905817 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2038 12:12:04.912048 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2039 12:12:04.915967 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2040 12:12:04.918932 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2041 12:12:04.922088 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2042 12:12:04.925437 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2043 12:12:04.932200 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
2044 12:12:04.935418 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2045 12:12:04.938529 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2046 12:12:04.942748 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2047 12:12:04.949172 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2048 12:12:04.952155 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2049 12:12:04.952727 ==
2050 12:12:04.955477 Dram Type= 6, Freq= 0, CH_1, rank 1
2051 12:12:04.958993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2052 12:12:04.959565 ==
2053 12:12:04.961745 DQS Delay:
2054 12:12:04.962310 DQS0 = 0, DQS1 = 0
2055 12:12:04.962677 DQM Delay:
2056 12:12:04.965028 DQM0 = 87, DQM1 = 78
2057 12:12:04.965671 DQ Delay:
2058 12:12:04.968395 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =88
2059 12:12:04.971774 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2060 12:12:04.975109 DQ8 =68, DQ9 =68, DQ10 =76, DQ11 =72
2061 12:12:04.978295 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2062 12:12:04.978757
2063 12:12:04.979123
2064 12:12:04.988723 [DQSOSCAuto] RK1, (LSB)MR18= 0x160e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
2065 12:12:04.991758 CH1 RK1: MR19=606, MR18=160E
2066 12:12:04.995951 CH1_RK1: MR19=0x606, MR18=0x160E, DQSOSC=404, MR23=63, INC=90, DEC=60
2067 12:12:04.998043 [RxdqsGatingPostProcess] freq 800
2068 12:12:05.005034 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2069 12:12:05.008623 Pre-setting of DQS Precalculation
2070 12:12:05.012140 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2071 12:12:05.021442 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2072 12:12:05.028671 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2073 12:12:05.029195
2074 12:12:05.029532
2075 12:12:05.031389 [Calibration Summary] 1600 Mbps
2076 12:12:05.031995 CH 0, Rank 0
2077 12:12:05.035298 SW Impedance : PASS
2078 12:12:05.035808 DUTY Scan : NO K
2079 12:12:05.037814 ZQ Calibration : PASS
2080 12:12:05.041303 Jitter Meter : NO K
2081 12:12:05.041860 CBT Training : PASS
2082 12:12:05.044977 Write leveling : PASS
2083 12:12:05.048447 RX DQS gating : PASS
2084 12:12:05.048913 RX DQ/DQS(RDDQC) : PASS
2085 12:12:05.051138 TX DQ/DQS : PASS
2086 12:12:05.054513 RX DATLAT : PASS
2087 12:12:05.054924 RX DQ/DQS(Engine): PASS
2088 12:12:05.057802 TX OE : NO K
2089 12:12:05.058268 All Pass.
2090 12:12:05.058637
2091 12:12:05.060937 CH 0, Rank 1
2092 12:12:05.061400 SW Impedance : PASS
2093 12:12:05.064273 DUTY Scan : NO K
2094 12:12:05.067493 ZQ Calibration : PASS
2095 12:12:05.067998 Jitter Meter : NO K
2096 12:12:05.071126 CBT Training : PASS
2097 12:12:05.071721 Write leveling : PASS
2098 12:12:05.074170 RX DQS gating : PASS
2099 12:12:05.077332 RX DQ/DQS(RDDQC) : PASS
2100 12:12:05.077876 TX DQ/DQS : PASS
2101 12:12:05.081039 RX DATLAT : PASS
2102 12:12:05.084425 RX DQ/DQS(Engine): PASS
2103 12:12:05.084906 TX OE : NO K
2104 12:12:05.087949 All Pass.
2105 12:12:05.088459
2106 12:12:05.088796 CH 1, Rank 0
2107 12:12:05.090516 SW Impedance : PASS
2108 12:12:05.090935 DUTY Scan : NO K
2109 12:12:05.094267 ZQ Calibration : PASS
2110 12:12:05.097133 Jitter Meter : NO K
2111 12:12:05.097555 CBT Training : PASS
2112 12:12:05.100311 Write leveling : PASS
2113 12:12:05.104649 RX DQS gating : PASS
2114 12:12:05.105165 RX DQ/DQS(RDDQC) : PASS
2115 12:12:05.107075 TX DQ/DQS : PASS
2116 12:12:05.110715 RX DATLAT : PASS
2117 12:12:05.111235 RX DQ/DQS(Engine): PASS
2118 12:12:05.113838 TX OE : NO K
2119 12:12:05.114358 All Pass.
2120 12:12:05.114694
2121 12:12:05.117487 CH 1, Rank 1
2122 12:12:05.118024 SW Impedance : PASS
2123 12:12:05.120698 DUTY Scan : NO K
2124 12:12:05.124003 ZQ Calibration : PASS
2125 12:12:05.124448 Jitter Meter : NO K
2126 12:12:05.127264 CBT Training : PASS
2127 12:12:05.130423 Write leveling : PASS
2128 12:12:05.130947 RX DQS gating : PASS
2129 12:12:05.133901 RX DQ/DQS(RDDQC) : PASS
2130 12:12:05.134426 TX DQ/DQS : PASS
2131 12:12:05.137589 RX DATLAT : PASS
2132 12:12:05.140125 RX DQ/DQS(Engine): PASS
2133 12:12:05.140591 TX OE : NO K
2134 12:12:05.143584 All Pass.
2135 12:12:05.144101
2136 12:12:05.144473 DramC Write-DBI off
2137 12:12:05.146808 PER_BANK_REFRESH: Hybrid Mode
2138 12:12:05.150556 TX_TRACKING: ON
2139 12:12:05.153872 [GetDramInforAfterCalByMRR] Vendor 6.
2140 12:12:05.157739 [GetDramInforAfterCalByMRR] Revision 606.
2141 12:12:05.160568 [GetDramInforAfterCalByMRR] Revision 2 0.
2142 12:12:05.161138 MR0 0x3b3b
2143 12:12:05.161510 MR8 0x5151
2144 12:12:05.167086 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2145 12:12:05.167654
2146 12:12:05.168067 MR0 0x3b3b
2147 12:12:05.168412 MR8 0x5151
2148 12:12:05.170220 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2149 12:12:05.170792
2150 12:12:05.180182 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2151 12:12:05.183718 [FAST_K] Save calibration result to emmc
2152 12:12:05.187275 [FAST_K] Save calibration result to emmc
2153 12:12:05.190409 dram_init: config_dvfs: 1
2154 12:12:05.193942 dramc_set_vcore_voltage set vcore to 662500
2155 12:12:05.196868 Read voltage for 1200, 2
2156 12:12:05.197425 Vio18 = 0
2157 12:12:05.197798 Vcore = 662500
2158 12:12:05.200747 Vdram = 0
2159 12:12:05.201313 Vddq = 0
2160 12:12:05.201685 Vmddr = 0
2161 12:12:05.207247 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2162 12:12:05.210224 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2163 12:12:05.213932 MEM_TYPE=3, freq_sel=15
2164 12:12:05.216900 sv_algorithm_assistance_LP4_1600
2165 12:12:05.220269 ============ PULL DRAM RESETB DOWN ============
2166 12:12:05.226552 ========== PULL DRAM RESETB DOWN end =========
2167 12:12:05.230612 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2168 12:12:05.233524 ===================================
2169 12:12:05.237545 LPDDR4 DRAM CONFIGURATION
2170 12:12:05.239749 ===================================
2171 12:12:05.240219 EX_ROW_EN[0] = 0x0
2172 12:12:05.243625 EX_ROW_EN[1] = 0x0
2173 12:12:05.244232 LP4Y_EN = 0x0
2174 12:12:05.246635 WORK_FSP = 0x0
2175 12:12:05.247196 WL = 0x4
2176 12:12:05.249770 RL = 0x4
2177 12:12:05.250334 BL = 0x2
2178 12:12:05.253149 RPST = 0x0
2179 12:12:05.253711 RD_PRE = 0x0
2180 12:12:05.256526 WR_PRE = 0x1
2181 12:12:05.256991 WR_PST = 0x0
2182 12:12:05.259787 DBI_WR = 0x0
2183 12:12:05.264227 DBI_RD = 0x0
2184 12:12:05.264795 OTF = 0x1
2185 12:12:05.266817 ===================================
2186 12:12:05.269933 ===================================
2187 12:12:05.270401 ANA top config
2188 12:12:05.274409 ===================================
2189 12:12:05.277044 DLL_ASYNC_EN = 0
2190 12:12:05.279758 ALL_SLAVE_EN = 0
2191 12:12:05.283058 NEW_RANK_MODE = 1
2192 12:12:05.286340 DLL_IDLE_MODE = 1
2193 12:12:05.286909 LP45_APHY_COMB_EN = 1
2194 12:12:05.289882 TX_ODT_DIS = 1
2195 12:12:05.293031 NEW_8X_MODE = 1
2196 12:12:05.295963 ===================================
2197 12:12:05.299648 ===================================
2198 12:12:05.303178 data_rate = 2400
2199 12:12:05.306096 CKR = 1
2200 12:12:05.306662 DQ_P2S_RATIO = 8
2201 12:12:05.309282 ===================================
2202 12:12:05.312595 CA_P2S_RATIO = 8
2203 12:12:05.316137 DQ_CA_OPEN = 0
2204 12:12:05.319885 DQ_SEMI_OPEN = 0
2205 12:12:05.322405 CA_SEMI_OPEN = 0
2206 12:12:05.325996 CA_FULL_RATE = 0
2207 12:12:05.326478 DQ_CKDIV4_EN = 0
2208 12:12:05.329107 CA_CKDIV4_EN = 0
2209 12:12:05.332916 CA_PREDIV_EN = 0
2210 12:12:05.335958 PH8_DLY = 17
2211 12:12:05.340157 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2212 12:12:05.342641 DQ_AAMCK_DIV = 4
2213 12:12:05.346031 CA_AAMCK_DIV = 4
2214 12:12:05.346613 CA_ADMCK_DIV = 4
2215 12:12:05.348767 DQ_TRACK_CA_EN = 0
2216 12:12:05.352765 CA_PICK = 1200
2217 12:12:05.356048 CA_MCKIO = 1200
2218 12:12:05.359259 MCKIO_SEMI = 0
2219 12:12:05.362577 PLL_FREQ = 2366
2220 12:12:05.366499 DQ_UI_PI_RATIO = 32
2221 12:12:05.367083 CA_UI_PI_RATIO = 0
2222 12:12:05.369210 ===================================
2223 12:12:05.372521 ===================================
2224 12:12:05.376140 memory_type:LPDDR4
2225 12:12:05.378636 GP_NUM : 10
2226 12:12:05.379103 SRAM_EN : 1
2227 12:12:05.382511 MD32_EN : 0
2228 12:12:05.385193 ===================================
2229 12:12:05.389672 [ANA_INIT] >>>>>>>>>>>>>>
2230 12:12:05.392158 <<<<<< [CONFIGURE PHASE]: ANA_TX
2231 12:12:05.395320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2232 12:12:05.399206 ===================================
2233 12:12:05.399628 data_rate = 2400,PCW = 0X5b00
2234 12:12:05.402150 ===================================
2235 12:12:05.405496 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2236 12:12:05.411816 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2237 12:12:05.419157 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2238 12:12:05.422276 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2239 12:12:05.425840 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2240 12:12:05.428441 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2241 12:12:05.432196 [ANA_INIT] flow start
2242 12:12:05.432618 [ANA_INIT] PLL >>>>>>>>
2243 12:12:05.435777 [ANA_INIT] PLL <<<<<<<<
2244 12:12:05.438358 [ANA_INIT] MIDPI >>>>>>>>
2245 12:12:05.441672 [ANA_INIT] MIDPI <<<<<<<<
2246 12:12:05.442094 [ANA_INIT] DLL >>>>>>>>
2247 12:12:05.446339 [ANA_INIT] DLL <<<<<<<<
2248 12:12:05.449405 [ANA_INIT] flow end
2249 12:12:05.452075 ============ LP4 DIFF to SE enter ============
2250 12:12:05.455780 ============ LP4 DIFF to SE exit ============
2251 12:12:05.458857 [ANA_INIT] <<<<<<<<<<<<<
2252 12:12:05.461923 [Flow] Enable top DCM control >>>>>
2253 12:12:05.464953 [Flow] Enable top DCM control <<<<<
2254 12:12:05.468394 Enable DLL master slave shuffle
2255 12:12:05.471798 ==============================================================
2256 12:12:05.474863 Gating Mode config
2257 12:12:05.481907 ==============================================================
2258 12:12:05.482417 Config description:
2259 12:12:05.491449 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2260 12:12:05.497979 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2261 12:12:05.501559 SELPH_MODE 0: By rank 1: By Phase
2262 12:12:05.508268 ==============================================================
2263 12:12:05.511760 GAT_TRACK_EN = 1
2264 12:12:05.514908 RX_GATING_MODE = 2
2265 12:12:05.517966 RX_GATING_TRACK_MODE = 2
2266 12:12:05.521466 SELPH_MODE = 1
2267 12:12:05.524328 PICG_EARLY_EN = 1
2268 12:12:05.528136 VALID_LAT_VALUE = 1
2269 12:12:05.531448 ==============================================================
2270 12:12:05.534949 Enter into Gating configuration >>>>
2271 12:12:05.538235 Exit from Gating configuration <<<<
2272 12:12:05.541347 Enter into DVFS_PRE_config >>>>>
2273 12:12:05.555380 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2274 12:12:05.556016 Exit from DVFS_PRE_config <<<<<
2275 12:12:05.558871 Enter into PICG configuration >>>>
2276 12:12:05.561307 Exit from PICG configuration <<<<
2277 12:12:05.564869 [RX_INPUT] configuration >>>>>
2278 12:12:05.568122 [RX_INPUT] configuration <<<<<
2279 12:12:05.574233 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2280 12:12:05.577645 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2281 12:12:05.584344 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2282 12:12:05.591225 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2283 12:12:05.597413 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2284 12:12:05.604577 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2285 12:12:05.607555 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2286 12:12:05.611334 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2287 12:12:05.614313 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2288 12:12:05.620805 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2289 12:12:05.624162 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2290 12:12:05.627136 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2291 12:12:05.630398 ===================================
2292 12:12:05.634209 LPDDR4 DRAM CONFIGURATION
2293 12:12:05.637209 ===================================
2294 12:12:05.640556 EX_ROW_EN[0] = 0x0
2295 12:12:05.641120 EX_ROW_EN[1] = 0x0
2296 12:12:05.644195 LP4Y_EN = 0x0
2297 12:12:05.644659 WORK_FSP = 0x0
2298 12:12:05.646901 WL = 0x4
2299 12:12:05.647365 RL = 0x4
2300 12:12:05.650705 BL = 0x2
2301 12:12:05.651272 RPST = 0x0
2302 12:12:05.653731 RD_PRE = 0x0
2303 12:12:05.654288 WR_PRE = 0x1
2304 12:12:05.657200 WR_PST = 0x0
2305 12:12:05.657660 DBI_WR = 0x0
2306 12:12:05.660712 DBI_RD = 0x0
2307 12:12:05.661267 OTF = 0x1
2308 12:12:05.663783 ===================================
2309 12:12:05.667751 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2310 12:12:05.673973 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2311 12:12:05.677130 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2312 12:12:05.680499 ===================================
2313 12:12:05.683433 LPDDR4 DRAM CONFIGURATION
2314 12:12:05.686782 ===================================
2315 12:12:05.687204 EX_ROW_EN[0] = 0x10
2316 12:12:05.690946 EX_ROW_EN[1] = 0x0
2317 12:12:05.694511 LP4Y_EN = 0x0
2318 12:12:05.694932 WORK_FSP = 0x0
2319 12:12:05.697491 WL = 0x4
2320 12:12:05.698011 RL = 0x4
2321 12:12:05.700724 BL = 0x2
2322 12:12:05.701140 RPST = 0x0
2323 12:12:05.703896 RD_PRE = 0x0
2324 12:12:05.704312 WR_PRE = 0x1
2325 12:12:05.706991 WR_PST = 0x0
2326 12:12:05.707407 DBI_WR = 0x0
2327 12:12:05.709962 DBI_RD = 0x0
2328 12:12:05.710377 OTF = 0x1
2329 12:12:05.713357 ===================================
2330 12:12:05.720526 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2331 12:12:05.720946 ==
2332 12:12:05.723153 Dram Type= 6, Freq= 0, CH_0, rank 0
2333 12:12:05.726469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2334 12:12:05.730411 ==
2335 12:12:05.730939 [Duty_Offset_Calibration]
2336 12:12:05.733833 B0:1 B1:-1 CA:0
2337 12:12:05.734254
2338 12:12:05.736761 [DutyScan_Calibration_Flow] k_type=0
2339 12:12:05.745310
2340 12:12:05.745831 ==CLK 0==
2341 12:12:05.749033 Final CLK duty delay cell = 0
2342 12:12:05.752030 [0] MAX Duty = 5094%(X100), DQS PI = 14
2343 12:12:05.755362 [0] MIN Duty = 4875%(X100), DQS PI = 10
2344 12:12:05.755926 [0] AVG Duty = 4984%(X100)
2345 12:12:05.758475
2346 12:12:05.762341 CH0 CLK Duty spec in!! Max-Min= 219%
2347 12:12:05.765577 [DutyScan_Calibration_Flow] ====Done====
2348 12:12:05.766110
2349 12:12:05.769029 [DutyScan_Calibration_Flow] k_type=1
2350 12:12:05.784176
2351 12:12:05.784740 ==DQS 0 ==
2352 12:12:05.787604 Final DQS duty delay cell = -4
2353 12:12:05.790550 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2354 12:12:05.793465 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2355 12:12:05.797497 [-4] AVG Duty = 4968%(X100)
2356 12:12:05.798065
2357 12:12:05.798434 ==DQS 1 ==
2358 12:12:05.800318 Final DQS duty delay cell = 0
2359 12:12:05.803439 [0] MAX Duty = 5124%(X100), DQS PI = 4
2360 12:12:05.806928 [0] MIN Duty = 5000%(X100), DQS PI = 22
2361 12:12:05.810491 [0] AVG Duty = 5062%(X100)
2362 12:12:05.810952
2363 12:12:05.813617 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2364 12:12:05.814078
2365 12:12:05.816782 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2366 12:12:05.820704 [DutyScan_Calibration_Flow] ====Done====
2367 12:12:05.821277
2368 12:12:05.823178 [DutyScan_Calibration_Flow] k_type=3
2369 12:12:05.841590
2370 12:12:05.842154 ==DQM 0 ==
2371 12:12:05.845410 Final DQM duty delay cell = 0
2372 12:12:05.848358 [0] MAX Duty = 5062%(X100), DQS PI = 22
2373 12:12:05.852086 [0] MIN Duty = 4875%(X100), DQS PI = 8
2374 12:12:05.852549 [0] AVG Duty = 4968%(X100)
2375 12:12:05.854622
2376 12:12:05.855181 ==DQM 1 ==
2377 12:12:05.858156 Final DQM duty delay cell = 4
2378 12:12:05.860930 [4] MAX Duty = 5187%(X100), DQS PI = 14
2379 12:12:05.864377 [4] MIN Duty = 5000%(X100), DQS PI = 24
2380 12:12:05.867852 [4] AVG Duty = 5093%(X100)
2381 12:12:05.868415
2382 12:12:05.871088 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2383 12:12:05.871653
2384 12:12:05.874473 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2385 12:12:05.878381 [DutyScan_Calibration_Flow] ====Done====
2386 12:12:05.878959
2387 12:12:05.881651 [DutyScan_Calibration_Flow] k_type=2
2388 12:12:05.896541
2389 12:12:05.897266 ==DQ 0 ==
2390 12:12:05.899279 Final DQ duty delay cell = -4
2391 12:12:05.902889 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2392 12:12:05.906251 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2393 12:12:05.910042 [-4] AVG Duty = 4969%(X100)
2394 12:12:05.910617
2395 12:12:05.910992 ==DQ 1 ==
2396 12:12:05.913388 Final DQ duty delay cell = -4
2397 12:12:05.915870 [-4] MAX Duty = 5000%(X100), DQS PI = 56
2398 12:12:05.919966 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2399 12:12:05.922730 [-4] AVG Duty = 4938%(X100)
2400 12:12:05.923296
2401 12:12:05.926070 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2402 12:12:05.926640
2403 12:12:05.929786 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2404 12:12:05.933326 [DutyScan_Calibration_Flow] ====Done====
2405 12:12:05.933912 ==
2406 12:12:05.936537 Dram Type= 6, Freq= 0, CH_1, rank 0
2407 12:12:05.939097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2408 12:12:05.939847 ==
2409 12:12:05.942423 [Duty_Offset_Calibration]
2410 12:12:05.946258 B0:-1 B1:1 CA:2
2411 12:12:05.946819
2412 12:12:05.949533 [DutyScan_Calibration_Flow] k_type=0
2413 12:12:05.957155
2414 12:12:05.957723 ==CLK 0==
2415 12:12:05.960261 Final CLK duty delay cell = 0
2416 12:12:05.964249 [0] MAX Duty = 5156%(X100), DQS PI = 22
2417 12:12:05.967096 [0] MIN Duty = 4969%(X100), DQS PI = 62
2418 12:12:05.967662 [0] AVG Duty = 5062%(X100)
2419 12:12:05.970846
2420 12:12:05.973375 CH1 CLK Duty spec in!! Max-Min= 187%
2421 12:12:05.976874 [DutyScan_Calibration_Flow] ====Done====
2422 12:12:05.977437
2423 12:12:05.979921 [DutyScan_Calibration_Flow] k_type=1
2424 12:12:05.996196
2425 12:12:05.996754 ==DQS 0 ==
2426 12:12:05.999795 Final DQS duty delay cell = 0
2427 12:12:06.003034 [0] MAX Duty = 5156%(X100), DQS PI = 48
2428 12:12:06.006314 [0] MIN Duty = 4907%(X100), DQS PI = 8
2429 12:12:06.009886 [0] AVG Duty = 5031%(X100)
2430 12:12:06.010447
2431 12:12:06.010813 ==DQS 1 ==
2432 12:12:06.013288 Final DQS duty delay cell = 0
2433 12:12:06.016309 [0] MAX Duty = 5094%(X100), DQS PI = 12
2434 12:12:06.020031 [0] MIN Duty = 4969%(X100), DQS PI = 58
2435 12:12:06.023135 [0] AVG Duty = 5031%(X100)
2436 12:12:06.023742
2437 12:12:06.026344 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2438 12:12:06.027037
2439 12:12:06.029686 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2440 12:12:06.032878 [DutyScan_Calibration_Flow] ====Done====
2441 12:12:06.033447
2442 12:12:06.035944 [DutyScan_Calibration_Flow] k_type=3
2443 12:12:06.052359
2444 12:12:06.053047 ==DQM 0 ==
2445 12:12:06.056660 Final DQM duty delay cell = -4
2446 12:12:06.058654 [-4] MAX Duty = 5062%(X100), DQS PI = 36
2447 12:12:06.062110 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2448 12:12:06.064987 [-4] AVG Duty = 4969%(X100)
2449 12:12:06.065453
2450 12:12:06.065822 ==DQM 1 ==
2451 12:12:06.068727 Final DQM duty delay cell = 0
2452 12:12:06.071576 [0] MAX Duty = 5156%(X100), DQS PI = 8
2453 12:12:06.075002 [0] MIN Duty = 4969%(X100), DQS PI = 32
2454 12:12:06.078984 [0] AVG Duty = 5062%(X100)
2455 12:12:06.079550
2456 12:12:06.081828 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2457 12:12:06.082392
2458 12:12:06.084832 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2459 12:12:06.088588 [DutyScan_Calibration_Flow] ====Done====
2460 12:12:06.089161
2461 12:12:06.092134 [DutyScan_Calibration_Flow] k_type=2
2462 12:12:06.108910
2463 12:12:06.109523 ==DQ 0 ==
2464 12:12:06.113102 Final DQ duty delay cell = 0
2465 12:12:06.115170 [0] MAX Duty = 5156%(X100), DQS PI = 28
2466 12:12:06.118812 [0] MIN Duty = 4907%(X100), DQS PI = 8
2467 12:12:06.119387 [0] AVG Duty = 5031%(X100)
2468 12:12:06.119820
2469 12:12:06.122160 ==DQ 1 ==
2470 12:12:06.126042 Final DQ duty delay cell = 0
2471 12:12:06.128393 [0] MAX Duty = 5124%(X100), DQS PI = 12
2472 12:12:06.132295 [0] MIN Duty = 4969%(X100), DQS PI = 0
2473 12:12:06.132855 [0] AVG Duty = 5046%(X100)
2474 12:12:06.133227
2475 12:12:06.135469 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2476 12:12:06.139127
2477 12:12:06.141832 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2478 12:12:06.145884 [DutyScan_Calibration_Flow] ====Done====
2479 12:12:06.149039 nWR fixed to 30
2480 12:12:06.149508 [ModeRegInit_LP4] CH0 RK0
2481 12:12:06.152180 [ModeRegInit_LP4] CH0 RK1
2482 12:12:06.155156 [ModeRegInit_LP4] CH1 RK0
2483 12:12:06.155767 [ModeRegInit_LP4] CH1 RK1
2484 12:12:06.158220 match AC timing 7
2485 12:12:06.161604 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2486 12:12:06.165189 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2487 12:12:06.171659 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2488 12:12:06.174965 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2489 12:12:06.181700 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2490 12:12:06.182168 ==
2491 12:12:06.185153 Dram Type= 6, Freq= 0, CH_0, rank 0
2492 12:12:06.188330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2493 12:12:06.188755 ==
2494 12:12:06.195363 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2495 12:12:06.201436 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2496 12:12:06.208810 [CA 0] Center 39 (9~70) winsize 62
2497 12:12:06.212048 [CA 1] Center 39 (9~70) winsize 62
2498 12:12:06.216234 [CA 2] Center 35 (5~66) winsize 62
2499 12:12:06.218605 [CA 3] Center 35 (5~65) winsize 61
2500 12:12:06.222218 [CA 4] Center 34 (4~64) winsize 61
2501 12:12:06.225153 [CA 5] Center 33 (3~63) winsize 61
2502 12:12:06.225622
2503 12:12:06.229248 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2504 12:12:06.229717
2505 12:12:06.233552 [CATrainingPosCal] consider 1 rank data
2506 12:12:06.234960 u2DelayCellTimex100 = 270/100 ps
2507 12:12:06.239001 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2508 12:12:06.242474 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2509 12:12:06.248002 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2510 12:12:06.251597 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2511 12:12:06.255229 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2512 12:12:06.258330 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2513 12:12:06.258908
2514 12:12:06.261694 CA PerBit enable=1, Macro0, CA PI delay=33
2515 12:12:06.262173
2516 12:12:06.264963 [CBTSetCACLKResult] CA Dly = 33
2517 12:12:06.265541 CS Dly: 8 (0~39)
2518 12:12:06.268071 ==
2519 12:12:06.271273 Dram Type= 6, Freq= 0, CH_0, rank 1
2520 12:12:06.274527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 12:12:06.275014 ==
2522 12:12:06.278464 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2523 12:12:06.284984 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2524 12:12:06.294594 [CA 0] Center 39 (9~70) winsize 62
2525 12:12:06.297794 [CA 1] Center 39 (9~70) winsize 62
2526 12:12:06.300844 [CA 2] Center 35 (5~66) winsize 62
2527 12:12:06.304356 [CA 3] Center 34 (4~65) winsize 62
2528 12:12:06.307667 [CA 4] Center 33 (3~64) winsize 62
2529 12:12:06.311782 [CA 5] Center 33 (3~63) winsize 61
2530 12:12:06.312362
2531 12:12:06.314186 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2532 12:12:06.314760
2533 12:12:06.317260 [CATrainingPosCal] consider 2 rank data
2534 12:12:06.320959 u2DelayCellTimex100 = 270/100 ps
2535 12:12:06.324288 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2536 12:12:06.330751 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2537 12:12:06.334388 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2538 12:12:06.337639 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2539 12:12:06.340805 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2540 12:12:06.343925 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2541 12:12:06.344409
2542 12:12:06.347248 CA PerBit enable=1, Macro0, CA PI delay=33
2543 12:12:06.347878
2544 12:12:06.351650 [CBTSetCACLKResult] CA Dly = 33
2545 12:12:06.352277 CS Dly: 9 (0~41)
2546 12:12:06.353857
2547 12:12:06.357298 ----->DramcWriteLeveling(PI) begin...
2548 12:12:06.357878 ==
2549 12:12:06.360592 Dram Type= 6, Freq= 0, CH_0, rank 0
2550 12:12:06.363660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2551 12:12:06.364185 ==
2552 12:12:06.367834 Write leveling (Byte 0): 34 => 34
2553 12:12:06.370397 Write leveling (Byte 1): 29 => 29
2554 12:12:06.374294 DramcWriteLeveling(PI) end<-----
2555 12:12:06.374832
2556 12:12:06.375208 ==
2557 12:12:06.376783 Dram Type= 6, Freq= 0, CH_0, rank 0
2558 12:12:06.380120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2559 12:12:06.380594 ==
2560 12:12:06.383390 [Gating] SW mode calibration
2561 12:12:06.390331 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2562 12:12:06.397196 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2563 12:12:06.400193 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
2564 12:12:06.404049 0 15 4 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
2565 12:12:06.410628 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2566 12:12:06.414154 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2567 12:12:06.417088 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2568 12:12:06.424394 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2569 12:12:06.426862 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2570 12:12:06.430263 0 15 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
2571 12:12:06.437071 1 0 0 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
2572 12:12:06.440645 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2573 12:12:06.443422 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 12:12:06.450272 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2575 12:12:06.453210 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2576 12:12:06.456635 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2577 12:12:06.463089 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2578 12:12:06.466645 1 0 28 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
2579 12:12:06.469779 1 1 0 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2580 12:12:06.473015 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2581 12:12:06.479508 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 12:12:06.483622 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 12:12:06.486745 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 12:12:06.492735 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 12:12:06.496218 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2586 12:12:06.499591 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2587 12:12:06.506238 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2588 12:12:06.509669 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 12:12:06.512755 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 12:12:06.519884 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 12:12:06.522648 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 12:12:06.525971 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 12:12:06.532505 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 12:12:06.536285 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 12:12:06.539560 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 12:12:06.546086 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 12:12:06.548806 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 12:12:06.552654 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 12:12:06.559266 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 12:12:06.562702 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 12:12:06.565995 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 12:12:06.572982 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2603 12:12:06.575912 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2604 12:12:06.578838 Total UI for P1: 0, mck2ui 16
2605 12:12:06.582848 best dqsien dly found for B0: ( 1, 3, 28)
2606 12:12:06.585791 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2607 12:12:06.593670 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 12:12:06.594229 Total UI for P1: 0, mck2ui 16
2609 12:12:06.599724 best dqsien dly found for B1: ( 1, 4, 2)
2610 12:12:06.602622 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2611 12:12:06.606168 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2612 12:12:06.606592
2613 12:12:06.608935 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2614 12:12:06.612873 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2615 12:12:06.616045 [Gating] SW calibration Done
2616 12:12:06.616470 ==
2617 12:12:06.619265 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 12:12:06.622418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 12:12:06.622844 ==
2620 12:12:06.625229 RX Vref Scan: 0
2621 12:12:06.625650
2622 12:12:06.625987 RX Vref 0 -> 0, step: 1
2623 12:12:06.626298
2624 12:12:06.629615 RX Delay -40 -> 252, step: 8
2625 12:12:06.631919 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2626 12:12:06.638483 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2627 12:12:06.642116 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2628 12:12:06.645499 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2629 12:12:06.648827 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2630 12:12:06.651666 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2631 12:12:06.658359 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2632 12:12:06.661962 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2633 12:12:06.665041 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2634 12:12:06.668774 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2635 12:12:06.671811 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2636 12:12:06.678318 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2637 12:12:06.681605 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2638 12:12:06.685076 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2639 12:12:06.688037 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2640 12:12:06.695462 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2641 12:12:06.695936 ==
2642 12:12:06.698350 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 12:12:06.701936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 12:12:06.702376 ==
2645 12:12:06.702820 DQS Delay:
2646 12:12:06.704797 DQS0 = 0, DQS1 = 0
2647 12:12:06.705234 DQM Delay:
2648 12:12:06.708319 DQM0 = 119, DQM1 = 106
2649 12:12:06.708753 DQ Delay:
2650 12:12:06.711334 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2651 12:12:06.714817 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2652 12:12:06.718062 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2653 12:12:06.721065 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2654 12:12:06.721508
2655 12:12:06.721951
2656 12:12:06.724231 ==
2657 12:12:06.728209 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 12:12:06.731238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 12:12:06.731662 ==
2660 12:12:06.732095
2661 12:12:06.732417
2662 12:12:06.734455 TX Vref Scan disable
2663 12:12:06.734878 == TX Byte 0 ==
2664 12:12:06.737448 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2665 12:12:06.743975 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2666 12:12:06.744418 == TX Byte 1 ==
2667 12:12:06.750881 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2668 12:12:06.753945 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2669 12:12:06.754490 ==
2670 12:12:06.757510 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 12:12:06.760371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 12:12:06.760810 ==
2673 12:12:06.773924 TX Vref=22, minBit 5, minWin=25, winSum=418
2674 12:12:06.776777 TX Vref=24, minBit 1, minWin=25, winSum=423
2675 12:12:06.780003 TX Vref=26, minBit 4, minWin=26, winSum=432
2676 12:12:06.783467 TX Vref=28, minBit 10, minWin=26, winSum=434
2677 12:12:06.786611 TX Vref=30, minBit 10, minWin=26, winSum=438
2678 12:12:06.792703 TX Vref=32, minBit 5, minWin=26, winSum=433
2679 12:12:06.796236 [TxChooseVref] Worse bit 10, Min win 26, Win sum 438, Final Vref 30
2680 12:12:06.796677
2681 12:12:06.799735 Final TX Range 1 Vref 30
2682 12:12:06.800175
2683 12:12:06.800616 ==
2684 12:12:06.803118 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 12:12:06.806096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 12:12:06.809514 ==
2687 12:12:06.809952
2688 12:12:06.810398
2689 12:12:06.810813 TX Vref Scan disable
2690 12:12:06.813492 == TX Byte 0 ==
2691 12:12:06.816792 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2692 12:12:06.823099 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2693 12:12:06.823538 == TX Byte 1 ==
2694 12:12:06.826680 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2695 12:12:06.833603 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2696 12:12:06.834045
2697 12:12:06.834490 [DATLAT]
2698 12:12:06.834912 Freq=1200, CH0 RK0
2699 12:12:06.835323
2700 12:12:06.836713 DATLAT Default: 0xd
2701 12:12:06.837147 0, 0xFFFF, sum = 0
2702 12:12:06.839840 1, 0xFFFF, sum = 0
2703 12:12:06.840283 2, 0xFFFF, sum = 0
2704 12:12:06.843130 3, 0xFFFF, sum = 0
2705 12:12:06.846242 4, 0xFFFF, sum = 0
2706 12:12:06.846685 5, 0xFFFF, sum = 0
2707 12:12:06.850332 6, 0xFFFF, sum = 0
2708 12:12:06.850762 7, 0xFFFF, sum = 0
2709 12:12:06.853159 8, 0xFFFF, sum = 0
2710 12:12:06.853607 9, 0xFFFF, sum = 0
2711 12:12:06.856421 10, 0xFFFF, sum = 0
2712 12:12:06.856866 11, 0xFFFF, sum = 0
2713 12:12:06.859312 12, 0x0, sum = 1
2714 12:12:06.859939 13, 0x0, sum = 2
2715 12:12:06.863279 14, 0x0, sum = 3
2716 12:12:06.863762 15, 0x0, sum = 4
2717 12:12:06.866035 best_step = 13
2718 12:12:06.866472
2719 12:12:06.866916 ==
2720 12:12:06.869979 Dram Type= 6, Freq= 0, CH_0, rank 0
2721 12:12:06.872793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2722 12:12:06.873233 ==
2723 12:12:06.873679 RX Vref Scan: 1
2724 12:12:06.876160
2725 12:12:06.876593 Set Vref Range= 32 -> 127
2726 12:12:06.877039
2727 12:12:06.879857 RX Vref 32 -> 127, step: 1
2728 12:12:06.880282
2729 12:12:06.882652 RX Delay -21 -> 252, step: 4
2730 12:12:06.883075
2731 12:12:06.886118 Set Vref, RX VrefLevel [Byte0]: 32
2732 12:12:06.889683 [Byte1]: 32
2733 12:12:06.890184
2734 12:12:06.892711 Set Vref, RX VrefLevel [Byte0]: 33
2735 12:12:06.895806 [Byte1]: 33
2736 12:12:06.900057
2737 12:12:06.900478 Set Vref, RX VrefLevel [Byte0]: 34
2738 12:12:06.903707 [Byte1]: 34
2739 12:12:06.907595
2740 12:12:06.908077 Set Vref, RX VrefLevel [Byte0]: 35
2741 12:12:06.910853 [Byte1]: 35
2742 12:12:06.916284
2743 12:12:06.916762 Set Vref, RX VrefLevel [Byte0]: 36
2744 12:12:06.918816 [Byte1]: 36
2745 12:12:06.923507
2746 12:12:06.923983 Set Vref, RX VrefLevel [Byte0]: 37
2747 12:12:06.926700 [Byte1]: 37
2748 12:12:06.931484
2749 12:12:06.932018 Set Vref, RX VrefLevel [Byte0]: 38
2750 12:12:06.934680 [Byte1]: 38
2751 12:12:06.939444
2752 12:12:06.939928 Set Vref, RX VrefLevel [Byte0]: 39
2753 12:12:06.942708 [Byte1]: 39
2754 12:12:06.947319
2755 12:12:06.947907 Set Vref, RX VrefLevel [Byte0]: 40
2756 12:12:06.950925 [Byte1]: 40
2757 12:12:06.954795
2758 12:12:06.955222 Set Vref, RX VrefLevel [Byte0]: 41
2759 12:12:06.958124 [Byte1]: 41
2760 12:12:06.963184
2761 12:12:06.963603 Set Vref, RX VrefLevel [Byte0]: 42
2762 12:12:06.966433 [Byte1]: 42
2763 12:12:06.971081
2764 12:12:06.971647 Set Vref, RX VrefLevel [Byte0]: 43
2765 12:12:06.974066 [Byte1]: 43
2766 12:12:06.978766
2767 12:12:06.979187 Set Vref, RX VrefLevel [Byte0]: 44
2768 12:12:06.982039 [Byte1]: 44
2769 12:12:06.986796
2770 12:12:06.987217 Set Vref, RX VrefLevel [Byte0]: 45
2771 12:12:06.990073 [Byte1]: 45
2772 12:12:06.994903
2773 12:12:06.995386 Set Vref, RX VrefLevel [Byte0]: 46
2774 12:12:06.998140 [Byte1]: 46
2775 12:12:07.002509
2776 12:12:07.002932 Set Vref, RX VrefLevel [Byte0]: 47
2777 12:12:07.006150 [Byte1]: 47
2778 12:12:07.010472
2779 12:12:07.010892 Set Vref, RX VrefLevel [Byte0]: 48
2780 12:12:07.014382 [Byte1]: 48
2781 12:12:07.018394
2782 12:12:07.021795 Set Vref, RX VrefLevel [Byte0]: 49
2783 12:12:07.022221 [Byte1]: 49
2784 12:12:07.026723
2785 12:12:07.027241 Set Vref, RX VrefLevel [Byte0]: 50
2786 12:12:07.029757 [Byte1]: 50
2787 12:12:07.035745
2788 12:12:07.036263 Set Vref, RX VrefLevel [Byte0]: 51
2789 12:12:07.038019 [Byte1]: 51
2790 12:12:07.042359
2791 12:12:07.042884 Set Vref, RX VrefLevel [Byte0]: 52
2792 12:12:07.045862 [Byte1]: 52
2793 12:12:07.050621
2794 12:12:07.051148 Set Vref, RX VrefLevel [Byte0]: 53
2795 12:12:07.053978 [Byte1]: 53
2796 12:12:07.057969
2797 12:12:07.058395 Set Vref, RX VrefLevel [Byte0]: 54
2798 12:12:07.061526 [Byte1]: 54
2799 12:12:07.067143
2800 12:12:07.067753 Set Vref, RX VrefLevel [Byte0]: 55
2801 12:12:07.069926 [Byte1]: 55
2802 12:12:07.074834
2803 12:12:07.075396 Set Vref, RX VrefLevel [Byte0]: 56
2804 12:12:07.077453 [Byte1]: 56
2805 12:12:07.082897
2806 12:12:07.083452 Set Vref, RX VrefLevel [Byte0]: 57
2807 12:12:07.085216 [Byte1]: 57
2808 12:12:07.090451
2809 12:12:07.091010 Set Vref, RX VrefLevel [Byte0]: 58
2810 12:12:07.093136 [Byte1]: 58
2811 12:12:07.097931
2812 12:12:07.098491 Set Vref, RX VrefLevel [Byte0]: 59
2813 12:12:07.101456 [Byte1]: 59
2814 12:12:07.106181
2815 12:12:07.106648 Set Vref, RX VrefLevel [Byte0]: 60
2816 12:12:07.108970 [Byte1]: 60
2817 12:12:07.114387
2818 12:12:07.114955 Set Vref, RX VrefLevel [Byte0]: 61
2819 12:12:07.117140 [Byte1]: 61
2820 12:12:07.121999
2821 12:12:07.122573 Set Vref, RX VrefLevel [Byte0]: 62
2822 12:12:07.125189 [Byte1]: 62
2823 12:12:07.129712
2824 12:12:07.130334 Set Vref, RX VrefLevel [Byte0]: 63
2825 12:12:07.132895 [Byte1]: 63
2826 12:12:07.138077
2827 12:12:07.138646 Set Vref, RX VrefLevel [Byte0]: 64
2828 12:12:07.141864 [Byte1]: 64
2829 12:12:07.145813
2830 12:12:07.146382 Set Vref, RX VrefLevel [Byte0]: 65
2831 12:12:07.148544 [Byte1]: 65
2832 12:12:07.153330
2833 12:12:07.153794 Set Vref, RX VrefLevel [Byte0]: 66
2834 12:12:07.156553 [Byte1]: 66
2835 12:12:07.161502
2836 12:12:07.162076 Set Vref, RX VrefLevel [Byte0]: 67
2837 12:12:07.165239 [Byte1]: 67
2838 12:12:07.169441
2839 12:12:07.170009 Set Vref, RX VrefLevel [Byte0]: 68
2840 12:12:07.172864 [Byte1]: 68
2841 12:12:07.177183
2842 12:12:07.177756 Set Vref, RX VrefLevel [Byte0]: 69
2843 12:12:07.180980 [Byte1]: 69
2844 12:12:07.184955
2845 12:12:07.185530 Set Vref, RX VrefLevel [Byte0]: 70
2846 12:12:07.188529 [Byte1]: 70
2847 12:12:07.193027
2848 12:12:07.193488 Set Vref, RX VrefLevel [Byte0]: 71
2849 12:12:07.196339 [Byte1]: 71
2850 12:12:07.201185
2851 12:12:07.201758 Set Vref, RX VrefLevel [Byte0]: 72
2852 12:12:07.204251 [Byte1]: 72
2853 12:12:07.208727
2854 12:12:07.209295 Set Vref, RX VrefLevel [Byte0]: 73
2855 12:12:07.212149 [Byte1]: 73
2856 12:12:07.216728
2857 12:12:07.217295 Set Vref, RX VrefLevel [Byte0]: 74
2858 12:12:07.220091 [Byte1]: 74
2859 12:12:07.225102
2860 12:12:07.225676 Set Vref, RX VrefLevel [Byte0]: 75
2861 12:12:07.228473 [Byte1]: 75
2862 12:12:07.232319
2863 12:12:07.232782 Set Vref, RX VrefLevel [Byte0]: 76
2864 12:12:07.235656 [Byte1]: 76
2865 12:12:07.240932
2866 12:12:07.241394 Set Vref, RX VrefLevel [Byte0]: 77
2867 12:12:07.243421 [Byte1]: 77
2868 12:12:07.248266
2869 12:12:07.248728 Set Vref, RX VrefLevel [Byte0]: 78
2870 12:12:07.251813 [Byte1]: 78
2871 12:12:07.256573
2872 12:12:07.256994 Final RX Vref Byte 0 = 60 to rank0
2873 12:12:07.259926 Final RX Vref Byte 1 = 58 to rank0
2874 12:12:07.263132 Final RX Vref Byte 0 = 60 to rank1
2875 12:12:07.266441 Final RX Vref Byte 1 = 58 to rank1==
2876 12:12:07.269804 Dram Type= 6, Freq= 0, CH_0, rank 0
2877 12:12:07.276648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2878 12:12:07.277113 ==
2879 12:12:07.277450 DQS Delay:
2880 12:12:07.277777 DQS0 = 0, DQS1 = 0
2881 12:12:07.279615 DQM Delay:
2882 12:12:07.280073 DQM0 = 119, DQM1 = 108
2883 12:12:07.282916 DQ Delay:
2884 12:12:07.286234 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2885 12:12:07.291017 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =128
2886 12:12:07.293063 DQ8 =96, DQ9 =94, DQ10 =112, DQ11 =102
2887 12:12:07.295998 DQ12 =112, DQ13 =112, DQ14 =122, DQ15 =114
2888 12:12:07.296440
2889 12:12:07.296782
2890 12:12:07.306251 [DQSOSCAuto] RK0, (LSB)MR18= 0x11fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2891 12:12:07.306681 CH0 RK0: MR19=403, MR18=11FD
2892 12:12:07.313073 CH0_RK0: MR19=0x403, MR18=0x11FD, DQSOSC=403, MR23=63, INC=40, DEC=26
2893 12:12:07.313603
2894 12:12:07.315849 ----->DramcWriteLeveling(PI) begin...
2895 12:12:07.316280 ==
2896 12:12:07.319060 Dram Type= 6, Freq= 0, CH_0, rank 1
2897 12:12:07.326017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2898 12:12:07.326566 ==
2899 12:12:07.328899 Write leveling (Byte 0): 32 => 32
2900 12:12:07.329325 Write leveling (Byte 1): 30 => 30
2901 12:12:07.332243 DramcWriteLeveling(PI) end<-----
2902 12:12:07.332669
2903 12:12:07.335528 ==
2904 12:12:07.335985 Dram Type= 6, Freq= 0, CH_0, rank 1
2905 12:12:07.343349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2906 12:12:07.343813 ==
2907 12:12:07.345738 [Gating] SW mode calibration
2908 12:12:07.352320 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2909 12:12:07.356181 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2910 12:12:07.362362 0 15 0 | B1->B0 | 2323 3434 | 1 0 | (1 1) (0 0)
2911 12:12:07.365809 0 15 4 | B1->B0 | 3433 3434 | 1 1 | (0 0) (1 1)
2912 12:12:07.369028 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2913 12:12:07.375622 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2914 12:12:07.378941 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2915 12:12:07.382524 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2916 12:12:07.389597 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2917 12:12:07.392425 0 15 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
2918 12:12:07.395403 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2919 12:12:07.402345 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 12:12:07.405537 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2921 12:12:07.408624 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2922 12:12:07.412447 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2923 12:12:07.418660 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2924 12:12:07.422068 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2925 12:12:07.425430 1 0 28 | B1->B0 | 2424 3636 | 0 0 | (0 0) (1 1)
2926 12:12:07.432371 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2927 12:12:07.435499 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 12:12:07.438803 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 12:12:07.445398 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 12:12:07.448583 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 12:12:07.451722 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 12:12:07.458793 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 12:12:07.462091 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2934 12:12:07.464922 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2935 12:12:07.471574 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 12:12:07.475373 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 12:12:07.478331 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 12:12:07.485429 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 12:12:07.488639 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 12:12:07.491774 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 12:12:07.499102 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 12:12:07.501594 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 12:12:07.505187 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 12:12:07.511459 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 12:12:07.514789 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 12:12:07.518731 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 12:12:07.524994 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 12:12:07.528281 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2949 12:12:07.531544 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2950 12:12:07.538506 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2951 12:12:07.542178 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2952 12:12:07.544648 Total UI for P1: 0, mck2ui 16
2953 12:12:07.547989 best dqsien dly found for B0: ( 1, 3, 28)
2954 12:12:07.551285 Total UI for P1: 0, mck2ui 16
2955 12:12:07.555043 best dqsien dly found for B1: ( 1, 4, 0)
2956 12:12:07.558140 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2957 12:12:07.561320 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2958 12:12:07.561746
2959 12:12:07.565610 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2960 12:12:07.568569 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2961 12:12:07.571160 [Gating] SW calibration Done
2962 12:12:07.571617 ==
2963 12:12:07.574884 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 12:12:07.578102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 12:12:07.578529 ==
2966 12:12:07.581560 RX Vref Scan: 0
2967 12:12:07.581983
2968 12:12:07.584835 RX Vref 0 -> 0, step: 1
2969 12:12:07.585259
2970 12:12:07.585707 RX Delay -40 -> 252, step: 8
2971 12:12:07.591203 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2972 12:12:07.595212 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2973 12:12:07.598382 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2974 12:12:07.601965 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2975 12:12:07.604915 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2976 12:12:07.611324 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2977 12:12:07.614904 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2978 12:12:07.617830 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2979 12:12:07.621667 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
2980 12:12:07.624265 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2981 12:12:07.631900 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2982 12:12:07.635054 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2983 12:12:07.637659 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2984 12:12:07.640795 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2985 12:12:07.644367 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2986 12:12:07.651557 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2987 12:12:07.652043 ==
2988 12:12:07.654499 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 12:12:07.657488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 12:12:07.657912 ==
2991 12:12:07.658251 DQS Delay:
2992 12:12:07.661056 DQS0 = 0, DQS1 = 0
2993 12:12:07.661476 DQM Delay:
2994 12:12:07.664255 DQM0 = 117, DQM1 = 109
2995 12:12:07.664677 DQ Delay:
2996 12:12:07.667455 DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115
2997 12:12:07.671093 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2998 12:12:07.674468 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
2999 12:12:07.677748 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =119
3000 12:12:07.678173
3001 12:12:07.678515
3002 12:12:07.680950 ==
3003 12:12:07.684300 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 12:12:07.687340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 12:12:07.687797 ==
3006 12:12:07.688174
3007 12:12:07.688523
3008 12:12:07.691384 TX Vref Scan disable
3009 12:12:07.691846 == TX Byte 0 ==
3010 12:12:07.694436 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3011 12:12:07.700937 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3012 12:12:07.701361 == TX Byte 1 ==
3013 12:12:07.707921 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3014 12:12:07.711054 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3015 12:12:07.711478 ==
3016 12:12:07.713985 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 12:12:07.717595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 12:12:07.718021 ==
3019 12:12:07.729800 TX Vref=22, minBit 1, minWin=25, winSum=423
3020 12:12:07.733303 TX Vref=24, minBit 5, minWin=25, winSum=426
3021 12:12:07.736464 TX Vref=26, minBit 1, minWin=26, winSum=431
3022 12:12:07.739732 TX Vref=28, minBit 1, minWin=26, winSum=431
3023 12:12:07.743308 TX Vref=30, minBit 13, minWin=26, winSum=435
3024 12:12:07.750780 TX Vref=32, minBit 2, minWin=26, winSum=436
3025 12:12:07.753351 [TxChooseVref] Worse bit 2, Min win 26, Win sum 436, Final Vref 32
3026 12:12:07.753825
3027 12:12:07.756453 Final TX Range 1 Vref 32
3028 12:12:07.756919
3029 12:12:07.757288 ==
3030 12:12:07.759551 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 12:12:07.762704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 12:12:07.766318 ==
3033 12:12:07.766882
3034 12:12:07.767257
3035 12:12:07.767599 TX Vref Scan disable
3036 12:12:07.770005 == TX Byte 0 ==
3037 12:12:07.773105 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3038 12:12:07.776197 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3039 12:12:07.779642 == TX Byte 1 ==
3040 12:12:07.782896 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3041 12:12:07.789738 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3042 12:12:07.790301
3043 12:12:07.790678 [DATLAT]
3044 12:12:07.791021 Freq=1200, CH0 RK1
3045 12:12:07.791354
3046 12:12:07.792630 DATLAT Default: 0xd
3047 12:12:07.793097 0, 0xFFFF, sum = 0
3048 12:12:07.796213 1, 0xFFFF, sum = 0
3049 12:12:07.799325 2, 0xFFFF, sum = 0
3050 12:12:07.799829 3, 0xFFFF, sum = 0
3051 12:12:07.802499 4, 0xFFFF, sum = 0
3052 12:12:07.803068 5, 0xFFFF, sum = 0
3053 12:12:07.806821 6, 0xFFFF, sum = 0
3054 12:12:07.807413 7, 0xFFFF, sum = 0
3055 12:12:07.809822 8, 0xFFFF, sum = 0
3056 12:12:07.810308 9, 0xFFFF, sum = 0
3057 12:12:07.813300 10, 0xFFFF, sum = 0
3058 12:12:07.813867 11, 0xFFFF, sum = 0
3059 12:12:07.816580 12, 0x0, sum = 1
3060 12:12:07.817185 13, 0x0, sum = 2
3061 12:12:07.819356 14, 0x0, sum = 3
3062 12:12:07.819980 15, 0x0, sum = 4
3063 12:12:07.822387 best_step = 13
3064 12:12:07.822850
3065 12:12:07.823224 ==
3066 12:12:07.825647 Dram Type= 6, Freq= 0, CH_0, rank 1
3067 12:12:07.829376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 12:12:07.829941 ==
3069 12:12:07.830320 RX Vref Scan: 0
3070 12:12:07.832035
3071 12:12:07.832529 RX Vref 0 -> 0, step: 1
3072 12:12:07.832902
3073 12:12:07.836518 RX Delay -21 -> 252, step: 4
3074 12:12:07.842589 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3075 12:12:07.846158 iDelay=199, Bit 1, Center 120 (47 ~ 194) 148
3076 12:12:07.849613 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3077 12:12:07.852256 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3078 12:12:07.856335 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3079 12:12:07.862831 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3080 12:12:07.866062 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3081 12:12:07.869487 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3082 12:12:07.872219 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3083 12:12:07.875633 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3084 12:12:07.878746 iDelay=199, Bit 10, Center 114 (47 ~ 182) 136
3085 12:12:07.886404 iDelay=199, Bit 11, Center 104 (39 ~ 170) 132
3086 12:12:07.888992 iDelay=199, Bit 12, Center 116 (51 ~ 182) 132
3087 12:12:07.892992 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
3088 12:12:07.895449 iDelay=199, Bit 14, Center 122 (59 ~ 186) 128
3089 12:12:07.902125 iDelay=199, Bit 15, Center 118 (55 ~ 182) 128
3090 12:12:07.902688 ==
3091 12:12:07.905588 Dram Type= 6, Freq= 0, CH_0, rank 1
3092 12:12:07.908622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 12:12:07.909094 ==
3094 12:12:07.909469 DQS Delay:
3095 12:12:07.911959 DQS0 = 0, DQS1 = 0
3096 12:12:07.912520 DQM Delay:
3097 12:12:07.915839 DQM0 = 116, DQM1 = 110
3098 12:12:07.916392 DQ Delay:
3099 12:12:07.918688 DQ0 =114, DQ1 =120, DQ2 =110, DQ3 =114
3100 12:12:07.921764 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3101 12:12:07.925048 DQ8 =98, DQ9 =94, DQ10 =114, DQ11 =104
3102 12:12:07.928489 DQ12 =116, DQ13 =114, DQ14 =122, DQ15 =118
3103 12:12:07.928960
3104 12:12:07.929362
3105 12:12:07.939239 [DQSOSCAuto] RK1, (LSB)MR18= 0xee9, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 404 ps
3106 12:12:07.941905 CH0 RK1: MR19=403, MR18=EE9
3107 12:12:07.945918 CH0_RK1: MR19=0x403, MR18=0xEE9, DQSOSC=404, MR23=63, INC=40, DEC=26
3108 12:12:07.948575 [RxdqsGatingPostProcess] freq 1200
3109 12:12:07.954834 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3110 12:12:07.958554 best DQS0 dly(2T, 0.5T) = (0, 11)
3111 12:12:07.961821 best DQS1 dly(2T, 0.5T) = (0, 12)
3112 12:12:07.964761 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3113 12:12:07.968383 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3114 12:12:07.971630 best DQS0 dly(2T, 0.5T) = (0, 11)
3115 12:12:07.974751 best DQS1 dly(2T, 0.5T) = (0, 12)
3116 12:12:07.978420 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3117 12:12:07.981812 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3118 12:12:07.982237 Pre-setting of DQS Precalculation
3119 12:12:07.988187 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3120 12:12:07.988777 ==
3121 12:12:07.992564 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 12:12:07.995100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 12:12:07.995560 ==
3124 12:12:08.001667 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3125 12:12:08.007798 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3126 12:12:08.015765 [CA 0] Center 37 (7~68) winsize 62
3127 12:12:08.019179 [CA 1] Center 37 (7~68) winsize 62
3128 12:12:08.022409 [CA 2] Center 34 (4~64) winsize 61
3129 12:12:08.025755 [CA 3] Center 33 (3~64) winsize 62
3130 12:12:08.028618 [CA 4] Center 34 (4~64) winsize 61
3131 12:12:08.032813 [CA 5] Center 33 (3~64) winsize 62
3132 12:12:08.033236
3133 12:12:08.036110 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3134 12:12:08.036533
3135 12:12:08.038768 [CATrainingPosCal] consider 1 rank data
3136 12:12:08.042278 u2DelayCellTimex100 = 270/100 ps
3137 12:12:08.045511 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3138 12:12:08.048583 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3139 12:12:08.055361 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3140 12:12:08.059121 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3141 12:12:08.062029 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3142 12:12:08.065545 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3143 12:12:08.065968
3144 12:12:08.068945 CA PerBit enable=1, Macro0, CA PI delay=33
3145 12:12:08.069368
3146 12:12:08.072011 [CBTSetCACLKResult] CA Dly = 33
3147 12:12:08.072435 CS Dly: 5 (0~36)
3148 12:12:08.072773 ==
3149 12:12:08.075225 Dram Type= 6, Freq= 0, CH_1, rank 1
3150 12:12:08.082520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3151 12:12:08.083035 ==
3152 12:12:08.085564 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3153 12:12:08.092048 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3154 12:12:08.101310 [CA 0] Center 37 (7~68) winsize 62
3155 12:12:08.104731 [CA 1] Center 38 (8~68) winsize 61
3156 12:12:08.107974 [CA 2] Center 34 (4~65) winsize 62
3157 12:12:08.111063 [CA 3] Center 33 (3~64) winsize 62
3158 12:12:08.115827 [CA 4] Center 34 (4~65) winsize 62
3159 12:12:08.118495 [CA 5] Center 33 (3~64) winsize 62
3160 12:12:08.118913
3161 12:12:08.121654 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3162 12:12:08.122076
3163 12:12:08.124529 [CATrainingPosCal] consider 2 rank data
3164 12:12:08.127653 u2DelayCellTimex100 = 270/100 ps
3165 12:12:08.131579 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3166 12:12:08.134243 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3167 12:12:08.140882 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3168 12:12:08.144107 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3169 12:12:08.147587 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3170 12:12:08.151276 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3171 12:12:08.151747
3172 12:12:08.154405 CA PerBit enable=1, Macro0, CA PI delay=33
3173 12:12:08.154822
3174 12:12:08.157356 [CBTSetCACLKResult] CA Dly = 33
3175 12:12:08.157772 CS Dly: 7 (0~40)
3176 12:12:08.160806
3177 12:12:08.164296 ----->DramcWriteLeveling(PI) begin...
3178 12:12:08.164809 ==
3179 12:12:08.167546 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 12:12:08.170562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 12:12:08.170983 ==
3182 12:12:08.174841 Write leveling (Byte 0): 25 => 25
3183 12:12:08.177131 Write leveling (Byte 1): 26 => 26
3184 12:12:08.180686 DramcWriteLeveling(PI) end<-----
3185 12:12:08.181107
3186 12:12:08.181441 ==
3187 12:12:08.183884 Dram Type= 6, Freq= 0, CH_1, rank 0
3188 12:12:08.187705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3189 12:12:08.188130 ==
3190 12:12:08.190270 [Gating] SW mode calibration
3191 12:12:08.196980 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3192 12:12:08.203913 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3193 12:12:08.207013 0 15 0 | B1->B0 | 3131 3434 | 1 0 | (0 0) (0 0)
3194 12:12:08.210271 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3195 12:12:08.217108 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3196 12:12:08.220783 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3197 12:12:08.223940 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3198 12:12:08.230236 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 12:12:08.233681 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
3200 12:12:08.237059 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
3201 12:12:08.243753 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 12:12:08.247011 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 12:12:08.250189 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3204 12:12:08.254229 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3205 12:12:08.260334 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 12:12:08.263844 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 12:12:08.266844 1 0 24 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
3208 12:12:08.274062 1 0 28 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
3209 12:12:08.277472 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 12:12:08.280402 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 12:12:08.287308 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 12:12:08.290589 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 12:12:08.293868 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 12:12:08.300429 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 12:12:08.303787 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3216 12:12:08.307427 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3217 12:12:08.314194 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 12:12:08.316842 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 12:12:08.320517 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 12:12:08.327202 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 12:12:08.330137 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 12:12:08.333600 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 12:12:08.340588 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 12:12:08.344041 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 12:12:08.347553 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 12:12:08.353265 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 12:12:08.356903 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 12:12:08.360241 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 12:12:08.366598 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 12:12:08.369876 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 12:12:08.373398 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3232 12:12:08.379805 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3233 12:12:08.380308 Total UI for P1: 0, mck2ui 16
3234 12:12:08.383004 best dqsien dly found for B0: ( 1, 3, 24)
3235 12:12:08.389553 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3236 12:12:08.393928 Total UI for P1: 0, mck2ui 16
3237 12:12:08.396554 best dqsien dly found for B1: ( 1, 3, 26)
3238 12:12:08.400056 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3239 12:12:08.403490 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3240 12:12:08.403945
3241 12:12:08.405940 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3242 12:12:08.410296 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3243 12:12:08.413810 [Gating] SW calibration Done
3244 12:12:08.414286 ==
3245 12:12:08.416315 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 12:12:08.420396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 12:12:08.423454 ==
3248 12:12:08.423927 RX Vref Scan: 0
3249 12:12:08.424353
3250 12:12:08.426457 RX Vref 0 -> 0, step: 1
3251 12:12:08.426881
3252 12:12:08.429620 RX Delay -40 -> 252, step: 8
3253 12:12:08.432354 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3254 12:12:08.436066 iDelay=208, Bit 1, Center 115 (48 ~ 183) 136
3255 12:12:08.439949 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3256 12:12:08.443354 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3257 12:12:08.450024 iDelay=208, Bit 4, Center 115 (48 ~ 183) 136
3258 12:12:08.452403 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3259 12:12:08.455884 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3260 12:12:08.460255 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3261 12:12:08.463002 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3262 12:12:08.466521 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3263 12:12:08.473136 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3264 12:12:08.476184 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3265 12:12:08.479342 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3266 12:12:08.482335 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3267 12:12:08.488928 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3268 12:12:08.492780 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3269 12:12:08.493370 ==
3270 12:12:08.496064 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 12:12:08.498954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 12:12:08.499423 ==
3273 12:12:08.499841 DQS Delay:
3274 12:12:08.502942 DQS0 = 0, DQS1 = 0
3275 12:12:08.503512 DQM Delay:
3276 12:12:08.506364 DQM0 = 118, DQM1 = 108
3277 12:12:08.506951 DQ Delay:
3278 12:12:08.508818 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =115
3279 12:12:08.512261 DQ4 =115, DQ5 =131, DQ6 =123, DQ7 =115
3280 12:12:08.515785 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3281 12:12:08.519832 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =119
3282 12:12:08.520406
3283 12:12:08.522613
3284 12:12:08.523075 ==
3285 12:12:08.525632 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 12:12:08.529183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 12:12:08.529758 ==
3288 12:12:08.530133
3289 12:12:08.530537
3290 12:12:08.532140 TX Vref Scan disable
3291 12:12:08.532603 == TX Byte 0 ==
3292 12:12:08.539636 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3293 12:12:08.542808 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3294 12:12:08.543283 == TX Byte 1 ==
3295 12:12:08.549158 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3296 12:12:08.552432 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3297 12:12:08.552904 ==
3298 12:12:08.555410 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 12:12:08.558887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 12:12:08.559462 ==
3301 12:12:08.571376 TX Vref=22, minBit 8, minWin=25, winSum=417
3302 12:12:08.574427 TX Vref=24, minBit 8, minWin=25, winSum=423
3303 12:12:08.577768 TX Vref=26, minBit 10, minWin=25, winSum=428
3304 12:12:08.581119 TX Vref=28, minBit 2, minWin=26, winSum=432
3305 12:12:08.584063 TX Vref=30, minBit 9, minWin=25, winSum=432
3306 12:12:08.591056 TX Vref=32, minBit 9, minWin=25, winSum=428
3307 12:12:08.594091 [TxChooseVref] Worse bit 2, Min win 26, Win sum 432, Final Vref 28
3308 12:12:08.594666
3309 12:12:08.597357 Final TX Range 1 Vref 28
3310 12:12:08.597950
3311 12:12:08.598383 ==
3312 12:12:08.600810 Dram Type= 6, Freq= 0, CH_1, rank 0
3313 12:12:08.604225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3314 12:12:08.604691 ==
3315 12:12:08.608347
3316 12:12:08.608804
3317 12:12:08.609172 TX Vref Scan disable
3318 12:12:08.610922 == TX Byte 0 ==
3319 12:12:08.614273 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3320 12:12:08.617754 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3321 12:12:08.620738 == TX Byte 1 ==
3322 12:12:08.624226 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3323 12:12:08.630956 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3324 12:12:08.631374
3325 12:12:08.631750 [DATLAT]
3326 12:12:08.632072 Freq=1200, CH1 RK0
3327 12:12:08.632375
3328 12:12:08.633930 DATLAT Default: 0xd
3329 12:12:08.634354 0, 0xFFFF, sum = 0
3330 12:12:08.637455 1, 0xFFFF, sum = 0
3331 12:12:08.641398 2, 0xFFFF, sum = 0
3332 12:12:08.641824 3, 0xFFFF, sum = 0
3333 12:12:08.643864 4, 0xFFFF, sum = 0
3334 12:12:08.644290 5, 0xFFFF, sum = 0
3335 12:12:08.647321 6, 0xFFFF, sum = 0
3336 12:12:08.647782 7, 0xFFFF, sum = 0
3337 12:12:08.650459 8, 0xFFFF, sum = 0
3338 12:12:08.650881 9, 0xFFFF, sum = 0
3339 12:12:08.653688 10, 0xFFFF, sum = 0
3340 12:12:08.654302 11, 0xFFFF, sum = 0
3341 12:12:08.656728 12, 0x0, sum = 1
3342 12:12:08.657157 13, 0x0, sum = 2
3343 12:12:08.660168 14, 0x0, sum = 3
3344 12:12:08.660593 15, 0x0, sum = 4
3345 12:12:08.663734 best_step = 13
3346 12:12:08.664240
3347 12:12:08.664580 ==
3348 12:12:08.667604 Dram Type= 6, Freq= 0, CH_1, rank 0
3349 12:12:08.670239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3350 12:12:08.670662 ==
3351 12:12:08.670997 RX Vref Scan: 1
3352 12:12:08.673875
3353 12:12:08.674289 Set Vref Range= 32 -> 127
3354 12:12:08.674629
3355 12:12:08.676966 RX Vref 32 -> 127, step: 1
3356 12:12:08.677385
3357 12:12:08.680476 RX Delay -21 -> 252, step: 4
3358 12:12:08.680895
3359 12:12:08.683264 Set Vref, RX VrefLevel [Byte0]: 32
3360 12:12:08.686768 [Byte1]: 32
3361 12:12:08.687186
3362 12:12:08.689904 Set Vref, RX VrefLevel [Byte0]: 33
3363 12:12:08.693194 [Byte1]: 33
3364 12:12:08.697125
3365 12:12:08.697545 Set Vref, RX VrefLevel [Byte0]: 34
3366 12:12:08.700508 [Byte1]: 34
3367 12:12:08.705101
3368 12:12:08.705769 Set Vref, RX VrefLevel [Byte0]: 35
3369 12:12:08.708530 [Byte1]: 35
3370 12:12:08.713182
3371 12:12:08.713598 Set Vref, RX VrefLevel [Byte0]: 36
3372 12:12:08.716333 [Byte1]: 36
3373 12:12:08.720831
3374 12:12:08.721248 Set Vref, RX VrefLevel [Byte0]: 37
3375 12:12:08.724630 [Byte1]: 37
3376 12:12:08.728664
3377 12:12:08.729093 Set Vref, RX VrefLevel [Byte0]: 38
3378 12:12:08.732471 [Byte1]: 38
3379 12:12:08.737049
3380 12:12:08.737467 Set Vref, RX VrefLevel [Byte0]: 39
3381 12:12:08.740469 [Byte1]: 39
3382 12:12:08.744744
3383 12:12:08.745178 Set Vref, RX VrefLevel [Byte0]: 40
3384 12:12:08.747787 [Byte1]: 40
3385 12:12:08.752582
3386 12:12:08.753002 Set Vref, RX VrefLevel [Byte0]: 41
3387 12:12:08.756322 [Byte1]: 41
3388 12:12:08.760469
3389 12:12:08.760907 Set Vref, RX VrefLevel [Byte0]: 42
3390 12:12:08.763728 [Byte1]: 42
3391 12:12:08.768441
3392 12:12:08.768881 Set Vref, RX VrefLevel [Byte0]: 43
3393 12:12:08.771614 [Byte1]: 43
3394 12:12:08.776343
3395 12:12:08.776772 Set Vref, RX VrefLevel [Byte0]: 44
3396 12:12:08.779785 [Byte1]: 44
3397 12:12:08.784071
3398 12:12:08.784482 Set Vref, RX VrefLevel [Byte0]: 45
3399 12:12:08.787583 [Byte1]: 45
3400 12:12:08.791964
3401 12:12:08.792376 Set Vref, RX VrefLevel [Byte0]: 46
3402 12:12:08.795337 [Byte1]: 46
3403 12:12:08.799944
3404 12:12:08.800357 Set Vref, RX VrefLevel [Byte0]: 47
3405 12:12:08.803047 [Byte1]: 47
3406 12:12:08.808152
3407 12:12:08.808559 Set Vref, RX VrefLevel [Byte0]: 48
3408 12:12:08.811603 [Byte1]: 48
3409 12:12:08.815893
3410 12:12:08.816358 Set Vref, RX VrefLevel [Byte0]: 49
3411 12:12:08.819356 [Byte1]: 49
3412 12:12:08.824535
3413 12:12:08.824946 Set Vref, RX VrefLevel [Byte0]: 50
3414 12:12:08.827085 [Byte1]: 50
3415 12:12:08.832202
3416 12:12:08.832711 Set Vref, RX VrefLevel [Byte0]: 51
3417 12:12:08.835497 [Byte1]: 51
3418 12:12:08.840083
3419 12:12:08.840634 Set Vref, RX VrefLevel [Byte0]: 52
3420 12:12:08.843250 [Byte1]: 52
3421 12:12:08.848112
3422 12:12:08.848624 Set Vref, RX VrefLevel [Byte0]: 53
3423 12:12:08.851109 [Byte1]: 53
3424 12:12:08.856902
3425 12:12:08.857461 Set Vref, RX VrefLevel [Byte0]: 54
3426 12:12:08.859304 [Byte1]: 54
3427 12:12:08.863906
3428 12:12:08.864474 Set Vref, RX VrefLevel [Byte0]: 55
3429 12:12:08.866628 [Byte1]: 55
3430 12:12:08.871594
3431 12:12:08.872197 Set Vref, RX VrefLevel [Byte0]: 56
3432 12:12:08.874602 [Byte1]: 56
3433 12:12:08.879449
3434 12:12:08.880096 Set Vref, RX VrefLevel [Byte0]: 57
3435 12:12:08.882843 [Byte1]: 57
3436 12:12:08.887246
3437 12:12:08.887759 Set Vref, RX VrefLevel [Byte0]: 58
3438 12:12:08.890445 [Byte1]: 58
3439 12:12:08.895021
3440 12:12:08.895500 Set Vref, RX VrefLevel [Byte0]: 59
3441 12:12:08.898474 [Byte1]: 59
3442 12:12:08.902798
3443 12:12:08.903252 Set Vref, RX VrefLevel [Byte0]: 60
3444 12:12:08.906325 [Byte1]: 60
3445 12:12:08.911547
3446 12:12:08.912149 Set Vref, RX VrefLevel [Byte0]: 61
3447 12:12:08.914688 [Byte1]: 61
3448 12:12:08.919251
3449 12:12:08.919868 Set Vref, RX VrefLevel [Byte0]: 62
3450 12:12:08.923370 [Byte1]: 62
3451 12:12:08.926850
3452 12:12:08.927406 Set Vref, RX VrefLevel [Byte0]: 63
3453 12:12:08.930449 [Byte1]: 63
3454 12:12:08.934472
3455 12:12:08.935103 Set Vref, RX VrefLevel [Byte0]: 64
3456 12:12:08.938210 [Byte1]: 64
3457 12:12:08.942643
3458 12:12:08.943099 Set Vref, RX VrefLevel [Byte0]: 65
3459 12:12:08.946381 [Byte1]: 65
3460 12:12:08.951351
3461 12:12:08.951977 Set Vref, RX VrefLevel [Byte0]: 66
3462 12:12:08.954208 [Byte1]: 66
3463 12:12:08.958672
3464 12:12:08.959231 Final RX Vref Byte 0 = 50 to rank0
3465 12:12:08.962456 Final RX Vref Byte 1 = 60 to rank0
3466 12:12:08.965053 Final RX Vref Byte 0 = 50 to rank1
3467 12:12:08.968435 Final RX Vref Byte 1 = 60 to rank1==
3468 12:12:08.971849 Dram Type= 6, Freq= 0, CH_1, rank 0
3469 12:12:08.979181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3470 12:12:08.979821 ==
3471 12:12:08.980308 DQS Delay:
3472 12:12:08.980825 DQS0 = 0, DQS1 = 0
3473 12:12:08.981577 DQM Delay:
3474 12:12:08.981941 DQM0 = 116, DQM1 = 113
3475 12:12:08.985254 DQ Delay:
3476 12:12:08.989057 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =110
3477 12:12:08.992044 DQ4 =114, DQ5 =126, DQ6 =126, DQ7 =112
3478 12:12:08.995446 DQ8 =100, DQ9 =100, DQ10 =116, DQ11 =102
3479 12:12:08.998393 DQ12 =120, DQ13 =120, DQ14 =124, DQ15 =122
3480 12:12:08.998938
3481 12:12:08.999328
3482 12:12:09.005271 [DQSOSCAuto] RK0, (LSB)MR18= 0xf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 410 ps
3483 12:12:09.009468 CH1 RK0: MR19=403, MR18=F4
3484 12:12:09.015179 CH1_RK0: MR19=0x403, MR18=0xF4, DQSOSC=410, MR23=63, INC=39, DEC=26
3485 12:12:09.015817
3486 12:12:09.018217 ----->DramcWriteLeveling(PI) begin...
3487 12:12:09.018682 ==
3488 12:12:09.022084 Dram Type= 6, Freq= 0, CH_1, rank 1
3489 12:12:09.024822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3490 12:12:09.027952 ==
3491 12:12:09.028410 Write leveling (Byte 0): 25 => 25
3492 12:12:09.031516 Write leveling (Byte 1): 27 => 27
3493 12:12:09.034529 DramcWriteLeveling(PI) end<-----
3494 12:12:09.035041
3495 12:12:09.035401 ==
3496 12:12:09.038069 Dram Type= 6, Freq= 0, CH_1, rank 1
3497 12:12:09.044494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3498 12:12:09.044960 ==
3499 12:12:09.047612 [Gating] SW mode calibration
3500 12:12:09.054656 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3501 12:12:09.058041 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3502 12:12:09.064386 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 12:12:09.067851 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 12:12:09.071492 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 12:12:09.078459 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 12:12:09.081164 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 12:12:09.084241 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 12:12:09.090632 0 15 24 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
3509 12:12:09.094728 0 15 28 | B1->B0 | 2424 2727 | 0 0 | (0 0) (1 0)
3510 12:12:09.097483 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 12:12:09.105526 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 12:12:09.106898 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 12:12:09.110561 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 12:12:09.117189 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 12:12:09.120759 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 12:12:09.124311 1 0 24 | B1->B0 | 4242 2e2e | 0 1 | (0 0) (0 0)
3517 12:12:09.130654 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 12:12:09.134049 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 12:12:09.136887 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 12:12:09.143336 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 12:12:09.147548 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 12:12:09.150028 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 12:12:09.157348 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 12:12:09.161311 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 12:12:09.163182 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3526 12:12:09.169940 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 12:12:09.173387 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 12:12:09.176183 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 12:12:09.183838 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 12:12:09.186833 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 12:12:09.189652 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 12:12:09.197080 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 12:12:09.199837 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 12:12:09.203544 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 12:12:09.210706 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 12:12:09.212577 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 12:12:09.216230 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 12:12:09.222831 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 12:12:09.225646 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 12:12:09.229438 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3541 12:12:09.236219 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3542 12:12:09.239010 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 12:12:09.243260 Total UI for P1: 0, mck2ui 16
3544 12:12:09.246337 best dqsien dly found for B0: ( 1, 3, 26)
3545 12:12:09.248832 Total UI for P1: 0, mck2ui 16
3546 12:12:09.251994 best dqsien dly found for B1: ( 1, 3, 26)
3547 12:12:09.255570 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3548 12:12:09.259559 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3549 12:12:09.260168
3550 12:12:09.262554 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3551 12:12:09.265811 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3552 12:12:09.268478 [Gating] SW calibration Done
3553 12:12:09.268935 ==
3554 12:12:09.271804 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 12:12:09.275602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 12:12:09.278755 ==
3557 12:12:09.279377 RX Vref Scan: 0
3558 12:12:09.279814
3559 12:12:09.281968 RX Vref 0 -> 0, step: 1
3560 12:12:09.282531
3561 12:12:09.285186 RX Delay -40 -> 252, step: 8
3562 12:12:09.288369 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3563 12:12:09.291751 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3564 12:12:09.295883 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3565 12:12:09.298814 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3566 12:12:09.305632 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3567 12:12:09.308730 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3568 12:12:09.312312 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3569 12:12:09.315115 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3570 12:12:09.318386 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3571 12:12:09.324759 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3572 12:12:09.328288 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3573 12:12:09.331243 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3574 12:12:09.334818 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3575 12:12:09.337920 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3576 12:12:09.344404 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3577 12:12:09.347795 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3578 12:12:09.348267 ==
3579 12:12:09.351786 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 12:12:09.355014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 12:12:09.355640 ==
3582 12:12:09.358480 DQS Delay:
3583 12:12:09.359031 DQS0 = 0, DQS1 = 0
3584 12:12:09.359398 DQM Delay:
3585 12:12:09.361343 DQM0 = 116, DQM1 = 110
3586 12:12:09.361901 DQ Delay:
3587 12:12:09.364734 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3588 12:12:09.368327 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3589 12:12:09.371511 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =103
3590 12:12:09.378016 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3591 12:12:09.378577
3592 12:12:09.378945
3593 12:12:09.379279 ==
3594 12:12:09.381311 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 12:12:09.384607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 12:12:09.385069 ==
3597 12:12:09.385433
3598 12:12:09.385768
3599 12:12:09.387299 TX Vref Scan disable
3600 12:12:09.387801 == TX Byte 0 ==
3601 12:12:09.394708 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3602 12:12:09.397516 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3603 12:12:09.400716 == TX Byte 1 ==
3604 12:12:09.404324 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3605 12:12:09.407360 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3606 12:12:09.407989 ==
3607 12:12:09.410982 Dram Type= 6, Freq= 0, CH_1, rank 1
3608 12:12:09.414118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3609 12:12:09.417743 ==
3610 12:12:09.427617 TX Vref=22, minBit 9, minWin=25, winSum=426
3611 12:12:09.430948 TX Vref=24, minBit 9, minWin=26, winSum=433
3612 12:12:09.434360 TX Vref=26, minBit 9, minWin=26, winSum=431
3613 12:12:09.436636 TX Vref=28, minBit 9, minWin=26, winSum=436
3614 12:12:09.440098 TX Vref=30, minBit 8, minWin=26, winSum=433
3615 12:12:09.446853 TX Vref=32, minBit 7, minWin=26, winSum=434
3616 12:12:09.450260 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 28
3617 12:12:09.450898
3618 12:12:09.453555 Final TX Range 1 Vref 28
3619 12:12:09.454121
3620 12:12:09.454488 ==
3621 12:12:09.456811 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 12:12:09.460252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 12:12:09.463247 ==
3624 12:12:09.463847
3625 12:12:09.464217
3626 12:12:09.464555 TX Vref Scan disable
3627 12:12:09.466910 == TX Byte 0 ==
3628 12:12:09.470973 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3629 12:12:09.476651 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3630 12:12:09.477123 == TX Byte 1 ==
3631 12:12:09.480126 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3632 12:12:09.487040 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3633 12:12:09.487604
3634 12:12:09.488174 [DATLAT]
3635 12:12:09.488532 Freq=1200, CH1 RK1
3636 12:12:09.488888
3637 12:12:09.489614 DATLAT Default: 0xd
3638 12:12:09.493518 0, 0xFFFF, sum = 0
3639 12:12:09.494090 1, 0xFFFF, sum = 0
3640 12:12:09.496672 2, 0xFFFF, sum = 0
3641 12:12:09.497160 3, 0xFFFF, sum = 0
3642 12:12:09.499513 4, 0xFFFF, sum = 0
3643 12:12:09.500129 5, 0xFFFF, sum = 0
3644 12:12:09.502925 6, 0xFFFF, sum = 0
3645 12:12:09.503493 7, 0xFFFF, sum = 0
3646 12:12:09.506390 8, 0xFFFF, sum = 0
3647 12:12:09.507014 9, 0xFFFF, sum = 0
3648 12:12:09.510117 10, 0xFFFF, sum = 0
3649 12:12:09.510685 11, 0xFFFF, sum = 0
3650 12:12:09.512559 12, 0x0, sum = 1
3651 12:12:09.513027 13, 0x0, sum = 2
3652 12:12:09.517050 14, 0x0, sum = 3
3653 12:12:09.517618 15, 0x0, sum = 4
3654 12:12:09.519578 best_step = 13
3655 12:12:09.520113
3656 12:12:09.520478 ==
3657 12:12:09.522814 Dram Type= 6, Freq= 0, CH_1, rank 1
3658 12:12:09.526006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3659 12:12:09.526490 ==
3660 12:12:09.529992 RX Vref Scan: 0
3661 12:12:09.530555
3662 12:12:09.530930 RX Vref 0 -> 0, step: 1
3663 12:12:09.531277
3664 12:12:09.532907 RX Delay -13 -> 252, step: 4
3665 12:12:09.539729 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3666 12:12:09.542536 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3667 12:12:09.546027 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3668 12:12:09.549060 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3669 12:12:09.552510 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3670 12:12:09.559156 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3671 12:12:09.562057 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3672 12:12:09.565822 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3673 12:12:09.569003 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3674 12:12:09.572317 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3675 12:12:09.578847 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3676 12:12:09.582554 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3677 12:12:09.585533 iDelay=199, Bit 12, Center 118 (55 ~ 182) 128
3678 12:12:09.588429 iDelay=199, Bit 13, Center 120 (55 ~ 186) 132
3679 12:12:09.595503 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3680 12:12:09.599641 iDelay=199, Bit 15, Center 122 (55 ~ 190) 136
3681 12:12:09.600308 ==
3682 12:12:09.601998 Dram Type= 6, Freq= 0, CH_1, rank 1
3683 12:12:09.605604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3684 12:12:09.606169 ==
3685 12:12:09.609334 DQS Delay:
3686 12:12:09.609896 DQS0 = 0, DQS1 = 0
3687 12:12:09.610263 DQM Delay:
3688 12:12:09.612210 DQM0 = 116, DQM1 = 111
3689 12:12:09.612666 DQ Delay:
3690 12:12:09.615270 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =112
3691 12:12:09.619216 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =116
3692 12:12:09.621817 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =102
3693 12:12:09.628591 DQ12 =118, DQ13 =120, DQ14 =120, DQ15 =122
3694 12:12:09.629145
3695 12:12:09.629528
3696 12:12:09.634654 [DQSOSCAuto] RK1, (LSB)MR18= 0xf7f2, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
3697 12:12:09.638273 CH1 RK1: MR19=303, MR18=F7F2
3698 12:12:09.644840 CH1_RK1: MR19=0x303, MR18=0xF7F2, DQSOSC=413, MR23=63, INC=38, DEC=25
3699 12:12:09.648705 [RxdqsGatingPostProcess] freq 1200
3700 12:12:09.651974 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3701 12:12:09.654579 best DQS0 dly(2T, 0.5T) = (0, 11)
3702 12:12:09.658546 best DQS1 dly(2T, 0.5T) = (0, 11)
3703 12:12:09.661488 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3704 12:12:09.665087 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3705 12:12:09.668345 best DQS0 dly(2T, 0.5T) = (0, 11)
3706 12:12:09.671644 best DQS1 dly(2T, 0.5T) = (0, 11)
3707 12:12:09.674893 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3708 12:12:09.677974 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3709 12:12:09.681838 Pre-setting of DQS Precalculation
3710 12:12:09.687319 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3711 12:12:09.693955 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3712 12:12:09.700649 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3713 12:12:09.701211
3714 12:12:09.701575
3715 12:12:09.703579 [Calibration Summary] 2400 Mbps
3716 12:12:09.704078 CH 0, Rank 0
3717 12:12:09.707550 SW Impedance : PASS
3718 12:12:09.710961 DUTY Scan : NO K
3719 12:12:09.711482 ZQ Calibration : PASS
3720 12:12:09.713768 Jitter Meter : NO K
3721 12:12:09.717059 CBT Training : PASS
3722 12:12:09.717473 Write leveling : PASS
3723 12:12:09.720100 RX DQS gating : PASS
3724 12:12:09.724393 RX DQ/DQS(RDDQC) : PASS
3725 12:12:09.724808 TX DQ/DQS : PASS
3726 12:12:09.727760 RX DATLAT : PASS
3727 12:12:09.728178 RX DQ/DQS(Engine): PASS
3728 12:12:09.730181 TX OE : NO K
3729 12:12:09.730705 All Pass.
3730 12:12:09.731044
3731 12:12:09.733531 CH 0, Rank 1
3732 12:12:09.736886 SW Impedance : PASS
3733 12:12:09.737300 DUTY Scan : NO K
3734 12:12:09.740541 ZQ Calibration : PASS
3735 12:12:09.740953 Jitter Meter : NO K
3736 12:12:09.743027 CBT Training : PASS
3737 12:12:09.746627 Write leveling : PASS
3738 12:12:09.747256 RX DQS gating : PASS
3739 12:12:09.749914 RX DQ/DQS(RDDQC) : PASS
3740 12:12:09.753872 TX DQ/DQS : PASS
3741 12:12:09.754486 RX DATLAT : PASS
3742 12:12:09.756487 RX DQ/DQS(Engine): PASS
3743 12:12:09.760423 TX OE : NO K
3744 12:12:09.760847 All Pass.
3745 12:12:09.761186
3746 12:12:09.761500 CH 1, Rank 0
3747 12:12:09.763163 SW Impedance : PASS
3748 12:12:09.767033 DUTY Scan : NO K
3749 12:12:09.767476 ZQ Calibration : PASS
3750 12:12:09.770116 Jitter Meter : NO K
3751 12:12:09.773345 CBT Training : PASS
3752 12:12:09.773767 Write leveling : PASS
3753 12:12:09.776524 RX DQS gating : PASS
3754 12:12:09.779709 RX DQ/DQS(RDDQC) : PASS
3755 12:12:09.780132 TX DQ/DQS : PASS
3756 12:12:09.783027 RX DATLAT : PASS
3757 12:12:09.786323 RX DQ/DQS(Engine): PASS
3758 12:12:09.786736 TX OE : NO K
3759 12:12:09.789910 All Pass.
3760 12:12:09.790319
3761 12:12:09.790645 CH 1, Rank 1
3762 12:12:09.793274 SW Impedance : PASS
3763 12:12:09.793810 DUTY Scan : NO K
3764 12:12:09.795853 ZQ Calibration : PASS
3765 12:12:09.800148 Jitter Meter : NO K
3766 12:12:09.800690 CBT Training : PASS
3767 12:12:09.802527 Write leveling : PASS
3768 12:12:09.806496 RX DQS gating : PASS
3769 12:12:09.807013 RX DQ/DQS(RDDQC) : PASS
3770 12:12:09.809710 TX DQ/DQS : PASS
3771 12:12:09.812395 RX DATLAT : PASS
3772 12:12:09.812810 RX DQ/DQS(Engine): PASS
3773 12:12:09.816599 TX OE : NO K
3774 12:12:09.817126 All Pass.
3775 12:12:09.817459
3776 12:12:09.819108 DramC Write-DBI off
3777 12:12:09.823130 PER_BANK_REFRESH: Hybrid Mode
3778 12:12:09.823644 TX_TRACKING: ON
3779 12:12:09.832764 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3780 12:12:09.835340 [FAST_K] Save calibration result to emmc
3781 12:12:09.838867 dramc_set_vcore_voltage set vcore to 650000
3782 12:12:09.842848 Read voltage for 600, 5
3783 12:12:09.843413 Vio18 = 0
3784 12:12:09.843841 Vcore = 650000
3785 12:12:09.845623 Vdram = 0
3786 12:12:09.846091 Vddq = 0
3787 12:12:09.846422 Vmddr = 0
3788 12:12:09.852725 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3789 12:12:09.855772 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3790 12:12:09.858972 MEM_TYPE=3, freq_sel=19
3791 12:12:09.862148 sv_algorithm_assistance_LP4_1600
3792 12:12:09.865446 ============ PULL DRAM RESETB DOWN ============
3793 12:12:09.868557 ========== PULL DRAM RESETB DOWN end =========
3794 12:12:09.875429 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3795 12:12:09.878777 ===================================
3796 12:12:09.879294 LPDDR4 DRAM CONFIGURATION
3797 12:12:09.882057 ===================================
3798 12:12:09.885323 EX_ROW_EN[0] = 0x0
3799 12:12:09.888261 EX_ROW_EN[1] = 0x0
3800 12:12:09.888674 LP4Y_EN = 0x0
3801 12:12:09.892134 WORK_FSP = 0x0
3802 12:12:09.892546 WL = 0x2
3803 12:12:09.895125 RL = 0x2
3804 12:12:09.895632 BL = 0x2
3805 12:12:09.898308 RPST = 0x0
3806 12:12:09.898817 RD_PRE = 0x0
3807 12:12:09.901866 WR_PRE = 0x1
3808 12:12:09.902280 WR_PST = 0x0
3809 12:12:09.904767 DBI_WR = 0x0
3810 12:12:09.905178 DBI_RD = 0x0
3811 12:12:09.908206 OTF = 0x1
3812 12:12:09.911719 ===================================
3813 12:12:09.914427 ===================================
3814 12:12:09.914843 ANA top config
3815 12:12:09.918398 ===================================
3816 12:12:09.921541 DLL_ASYNC_EN = 0
3817 12:12:09.924923 ALL_SLAVE_EN = 1
3818 12:12:09.927882 NEW_RANK_MODE = 1
3819 12:12:09.928305 DLL_IDLE_MODE = 1
3820 12:12:09.931941 LP45_APHY_COMB_EN = 1
3821 12:12:09.934913 TX_ODT_DIS = 1
3822 12:12:09.937998 NEW_8X_MODE = 1
3823 12:12:09.941672 ===================================
3824 12:12:09.944710 ===================================
3825 12:12:09.949821 data_rate = 1200
3826 12:12:09.950330 CKR = 1
3827 12:12:09.951276 DQ_P2S_RATIO = 8
3828 12:12:09.955358 ===================================
3829 12:12:09.957677 CA_P2S_RATIO = 8
3830 12:12:09.961198 DQ_CA_OPEN = 0
3831 12:12:09.964860 DQ_SEMI_OPEN = 0
3832 12:12:09.967966 CA_SEMI_OPEN = 0
3833 12:12:09.971012 CA_FULL_RATE = 0
3834 12:12:09.971528 DQ_CKDIV4_EN = 1
3835 12:12:09.974094 CA_CKDIV4_EN = 1
3836 12:12:09.977831 CA_PREDIV_EN = 0
3837 12:12:09.980405 PH8_DLY = 0
3838 12:12:09.984143 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3839 12:12:09.987495 DQ_AAMCK_DIV = 4
3840 12:12:09.988115 CA_AAMCK_DIV = 4
3841 12:12:09.990604 CA_ADMCK_DIV = 4
3842 12:12:09.993964 DQ_TRACK_CA_EN = 0
3843 12:12:09.997633 CA_PICK = 600
3844 12:12:10.000861 CA_MCKIO = 600
3845 12:12:10.004586 MCKIO_SEMI = 0
3846 12:12:10.008534 PLL_FREQ = 2288
3847 12:12:10.009054 DQ_UI_PI_RATIO = 32
3848 12:12:10.010726 CA_UI_PI_RATIO = 0
3849 12:12:10.013903 ===================================
3850 12:12:10.016933 ===================================
3851 12:12:10.020372 memory_type:LPDDR4
3852 12:12:10.024115 GP_NUM : 10
3853 12:12:10.024629 SRAM_EN : 1
3854 12:12:10.027306 MD32_EN : 0
3855 12:12:10.030930 ===================================
3856 12:12:10.033521 [ANA_INIT] >>>>>>>>>>>>>>
3857 12:12:10.034008 <<<<<< [CONFIGURE PHASE]: ANA_TX
3858 12:12:10.039873 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3859 12:12:10.044323 ===================================
3860 12:12:10.044888 data_rate = 1200,PCW = 0X5800
3861 12:12:10.046909 ===================================
3862 12:12:10.050254 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3863 12:12:10.056966 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3864 12:12:10.063204 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3865 12:12:10.067088 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3866 12:12:10.070347 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3867 12:12:10.073409 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3868 12:12:10.076557 [ANA_INIT] flow start
3869 12:12:10.079895 [ANA_INIT] PLL >>>>>>>>
3870 12:12:10.080454 [ANA_INIT] PLL <<<<<<<<
3871 12:12:10.083274 [ANA_INIT] MIDPI >>>>>>>>
3872 12:12:10.086177 [ANA_INIT] MIDPI <<<<<<<<
3873 12:12:10.086633 [ANA_INIT] DLL >>>>>>>>
3874 12:12:10.089301 [ANA_INIT] flow end
3875 12:12:10.092540 ============ LP4 DIFF to SE enter ============
3876 12:12:10.096330 ============ LP4 DIFF to SE exit ============
3877 12:12:10.099619 [ANA_INIT] <<<<<<<<<<<<<
3878 12:12:10.102546 [Flow] Enable top DCM control >>>>>
3879 12:12:10.106531 [Flow] Enable top DCM control <<<<<
3880 12:12:10.109550 Enable DLL master slave shuffle
3881 12:12:10.116415 ==============================================================
3882 12:12:10.117023 Gating Mode config
3883 12:12:10.122635 ==============================================================
3884 12:12:10.123197 Config description:
3885 12:12:10.132645 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3886 12:12:10.138845 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3887 12:12:10.145606 SELPH_MODE 0: By rank 1: By Phase
3888 12:12:10.152447 ==============================================================
3889 12:12:10.152922 GAT_TRACK_EN = 1
3890 12:12:10.155822 RX_GATING_MODE = 2
3891 12:12:10.159246 RX_GATING_TRACK_MODE = 2
3892 12:12:10.162836 SELPH_MODE = 1
3893 12:12:10.165715 PICG_EARLY_EN = 1
3894 12:12:10.168676 VALID_LAT_VALUE = 1
3895 12:12:10.175412 ==============================================================
3896 12:12:10.179053 Enter into Gating configuration >>>>
3897 12:12:10.182074 Exit from Gating configuration <<<<
3898 12:12:10.185982 Enter into DVFS_PRE_config >>>>>
3899 12:12:10.195270 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3900 12:12:10.199040 Exit from DVFS_PRE_config <<<<<
3901 12:12:10.201756 Enter into PICG configuration >>>>
3902 12:12:10.205717 Exit from PICG configuration <<<<
3903 12:12:10.208833 [RX_INPUT] configuration >>>>>
3904 12:12:10.212068 [RX_INPUT] configuration <<<<<
3905 12:12:10.215852 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3906 12:12:10.221685 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3907 12:12:10.228390 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3908 12:12:10.232822 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3909 12:12:10.238666 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3910 12:12:10.244988 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3911 12:12:10.248330 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3912 12:12:10.255808 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3913 12:12:10.258245 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3914 12:12:10.261573 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3915 12:12:10.264295 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3916 12:12:10.271367 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3917 12:12:10.274471 ===================================
3918 12:12:10.275033 LPDDR4 DRAM CONFIGURATION
3919 12:12:10.278341 ===================================
3920 12:12:10.280879 EX_ROW_EN[0] = 0x0
3921 12:12:10.284800 EX_ROW_EN[1] = 0x0
3922 12:12:10.285476 LP4Y_EN = 0x0
3923 12:12:10.288059 WORK_FSP = 0x0
3924 12:12:10.288615 WL = 0x2
3925 12:12:10.291191 RL = 0x2
3926 12:12:10.291781 BL = 0x2
3927 12:12:10.294673 RPST = 0x0
3928 12:12:10.295226 RD_PRE = 0x0
3929 12:12:10.297492 WR_PRE = 0x1
3930 12:12:10.297949 WR_PST = 0x0
3931 12:12:10.300848 DBI_WR = 0x0
3932 12:12:10.301293 DBI_RD = 0x0
3933 12:12:10.303812 OTF = 0x1
3934 12:12:10.307816 ===================================
3935 12:12:10.311208 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3936 12:12:10.313812 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3937 12:12:10.320407 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3938 12:12:10.323783 ===================================
3939 12:12:10.327192 LPDDR4 DRAM CONFIGURATION
3940 12:12:10.330651 ===================================
3941 12:12:10.331216 EX_ROW_EN[0] = 0x10
3942 12:12:10.333605 EX_ROW_EN[1] = 0x0
3943 12:12:10.334062 LP4Y_EN = 0x0
3944 12:12:10.337957 WORK_FSP = 0x0
3945 12:12:10.338424 WL = 0x2
3946 12:12:10.340258 RL = 0x2
3947 12:12:10.340724 BL = 0x2
3948 12:12:10.343453 RPST = 0x0
3949 12:12:10.344109 RD_PRE = 0x0
3950 12:12:10.347515 WR_PRE = 0x1
3951 12:12:10.348127 WR_PST = 0x0
3952 12:12:10.349900 DBI_WR = 0x0
3953 12:12:10.353821 DBI_RD = 0x0
3954 12:12:10.354407 OTF = 0x1
3955 12:12:10.356643 ===================================
3956 12:12:10.364307 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3957 12:12:10.366635 nWR fixed to 30
3958 12:12:10.369817 [ModeRegInit_LP4] CH0 RK0
3959 12:12:10.370280 [ModeRegInit_LP4] CH0 RK1
3960 12:12:10.373567 [ModeRegInit_LP4] CH1 RK0
3961 12:12:10.376674 [ModeRegInit_LP4] CH1 RK1
3962 12:12:10.377266 match AC timing 17
3963 12:12:10.383635 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3964 12:12:10.386391 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3965 12:12:10.389832 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3966 12:12:10.396609 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3967 12:12:10.399860 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3968 12:12:10.400436 ==
3969 12:12:10.403062 Dram Type= 6, Freq= 0, CH_0, rank 0
3970 12:12:10.406852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 12:12:10.407444 ==
3972 12:12:10.412463 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3973 12:12:10.419312 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3974 12:12:10.422703 [CA 0] Center 36 (6~66) winsize 61
3975 12:12:10.426248 [CA 1] Center 36 (6~66) winsize 61
3976 12:12:10.429292 [CA 2] Center 34 (4~65) winsize 62
3977 12:12:10.432615 [CA 3] Center 34 (4~65) winsize 62
3978 12:12:10.435585 [CA 4] Center 33 (3~64) winsize 62
3979 12:12:10.439155 [CA 5] Center 33 (2~64) winsize 63
3980 12:12:10.439795
3981 12:12:10.442667 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3982 12:12:10.443223
3983 12:12:10.446527 [CATrainingPosCal] consider 1 rank data
3984 12:12:10.448967 u2DelayCellTimex100 = 270/100 ps
3985 12:12:10.452150 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3986 12:12:10.455566 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3987 12:12:10.459061 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3988 12:12:10.465662 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3989 12:12:10.468823 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3990 12:12:10.472183 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3991 12:12:10.472668
3992 12:12:10.475091 CA PerBit enable=1, Macro0, CA PI delay=33
3993 12:12:10.475506
3994 12:12:10.478825 [CBTSetCACLKResult] CA Dly = 33
3995 12:12:10.479343 CS Dly: 6 (0~37)
3996 12:12:10.479861 ==
3997 12:12:10.482481 Dram Type= 6, Freq= 0, CH_0, rank 1
3998 12:12:10.488648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3999 12:12:10.489165 ==
4000 12:12:10.491656 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4001 12:12:10.498641 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4002 12:12:10.502321 [CA 0] Center 35 (5~66) winsize 62
4003 12:12:10.505193 [CA 1] Center 36 (6~66) winsize 61
4004 12:12:10.508668 [CA 2] Center 34 (3~65) winsize 63
4005 12:12:10.511850 [CA 3] Center 33 (3~64) winsize 62
4006 12:12:10.515730 [CA 4] Center 33 (2~64) winsize 63
4007 12:12:10.520124 [CA 5] Center 33 (2~64) winsize 63
4008 12:12:10.520681
4009 12:12:10.522074 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4010 12:12:10.522534
4011 12:12:10.525254 [CATrainingPosCal] consider 2 rank data
4012 12:12:10.528378 u2DelayCellTimex100 = 270/100 ps
4013 12:12:10.534770 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4014 12:12:10.538982 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4015 12:12:10.541775 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4016 12:12:10.544731 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4017 12:12:10.548691 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4018 12:12:10.551380 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4019 12:12:10.551902
4020 12:12:10.554460 CA PerBit enable=1, Macro0, CA PI delay=33
4021 12:12:10.554918
4022 12:12:10.557697 [CBTSetCACLKResult] CA Dly = 33
4023 12:12:10.561595 CS Dly: 5 (0~36)
4024 12:12:10.562155
4025 12:12:10.564602 ----->DramcWriteLeveling(PI) begin...
4026 12:12:10.565067 ==
4027 12:12:10.567706 Dram Type= 6, Freq= 0, CH_0, rank 0
4028 12:12:10.571523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4029 12:12:10.572043 ==
4030 12:12:10.574834 Write leveling (Byte 0): 30 => 30
4031 12:12:10.578124 Write leveling (Byte 1): 28 => 28
4032 12:12:10.581420 DramcWriteLeveling(PI) end<-----
4033 12:12:10.581982
4034 12:12:10.582352 ==
4035 12:12:10.584316 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 12:12:10.587555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 12:12:10.588074 ==
4038 12:12:10.591048 [Gating] SW mode calibration
4039 12:12:10.597826 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4040 12:12:10.603884 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4041 12:12:10.607877 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4042 12:12:10.611112 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4043 12:12:10.618236 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4044 12:12:10.621254 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4045 12:12:10.624438 0 9 16 | B1->B0 | 3131 2323 | 1 0 | (0 1) (1 0)
4046 12:12:10.630981 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 12:12:10.634776 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 12:12:10.637056 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 12:12:10.643980 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 12:12:10.648244 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 12:12:10.650232 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 12:12:10.657133 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4053 12:12:10.660415 0 10 16 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
4054 12:12:10.663350 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 12:12:10.669849 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 12:12:10.673622 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 12:12:10.677488 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 12:12:10.683790 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 12:12:10.686569 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 12:12:10.689608 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 12:12:10.696708 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4062 12:12:10.700430 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 12:12:10.703071 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 12:12:10.709871 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 12:12:10.713799 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 12:12:10.716340 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 12:12:10.722822 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 12:12:10.726788 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 12:12:10.729889 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 12:12:10.735812 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 12:12:10.739594 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 12:12:10.742788 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 12:12:10.750333 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 12:12:10.752555 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 12:12:10.756055 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 12:12:10.762970 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4077 12:12:10.765791 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 12:12:10.768677 Total UI for P1: 0, mck2ui 16
4079 12:12:10.772039 best dqsien dly found for B0: ( 0, 13, 12)
4080 12:12:10.776120 Total UI for P1: 0, mck2ui 16
4081 12:12:10.779467 best dqsien dly found for B1: ( 0, 13, 14)
4082 12:12:10.782110 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4083 12:12:10.785646 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4084 12:12:10.786228
4085 12:12:10.788407 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4086 12:12:10.795782 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4087 12:12:10.796248 [Gating] SW calibration Done
4088 12:12:10.796583 ==
4089 12:12:10.798605 Dram Type= 6, Freq= 0, CH_0, rank 0
4090 12:12:10.805405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4091 12:12:10.805822 ==
4092 12:12:10.806153 RX Vref Scan: 0
4093 12:12:10.806460
4094 12:12:10.808732 RX Vref 0 -> 0, step: 1
4095 12:12:10.809143
4096 12:12:10.811520 RX Delay -230 -> 252, step: 16
4097 12:12:10.815405 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4098 12:12:10.818230 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4099 12:12:10.825050 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4100 12:12:10.828024 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4101 12:12:10.831319 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4102 12:12:10.834893 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4103 12:12:10.837934 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4104 12:12:10.845087 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4105 12:12:10.848605 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4106 12:12:10.851656 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4107 12:12:10.855343 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4108 12:12:10.861804 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4109 12:12:10.864252 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4110 12:12:10.867492 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4111 12:12:10.871494 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4112 12:12:10.877799 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4113 12:12:10.878361 ==
4114 12:12:10.880868 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 12:12:10.884206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 12:12:10.884640 ==
4117 12:12:10.884991 DQS Delay:
4118 12:12:10.887737 DQS0 = 0, DQS1 = 0
4119 12:12:10.888166 DQM Delay:
4120 12:12:10.890945 DQM0 = 43, DQM1 = 31
4121 12:12:10.891545 DQ Delay:
4122 12:12:10.893990 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4123 12:12:10.897643 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4124 12:12:10.900645 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4125 12:12:10.903874 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4126 12:12:10.904294
4127 12:12:10.904630
4128 12:12:10.904940 ==
4129 12:12:10.907310 Dram Type= 6, Freq= 0, CH_0, rank 0
4130 12:12:10.913607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 12:12:10.914111 ==
4132 12:12:10.914445
4133 12:12:10.914749
4134 12:12:10.915039 TX Vref Scan disable
4135 12:12:10.917262 == TX Byte 0 ==
4136 12:12:10.920876 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4137 12:12:10.927448 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4138 12:12:10.928054 == TX Byte 1 ==
4139 12:12:10.930408 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4140 12:12:10.937207 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4141 12:12:10.937755 ==
4142 12:12:10.940515 Dram Type= 6, Freq= 0, CH_0, rank 0
4143 12:12:10.944009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 12:12:10.944568 ==
4145 12:12:10.944973
4146 12:12:10.945316
4147 12:12:10.947882 TX Vref Scan disable
4148 12:12:10.950657 == TX Byte 0 ==
4149 12:12:10.953626 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4150 12:12:10.957800 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4151 12:12:10.960028 == TX Byte 1 ==
4152 12:12:10.963783 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4153 12:12:10.967208 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4154 12:12:10.967828
4155 12:12:10.968199 [DATLAT]
4156 12:12:10.969950 Freq=600, CH0 RK0
4157 12:12:10.970407
4158 12:12:10.973520 DATLAT Default: 0x9
4159 12:12:10.973981 0, 0xFFFF, sum = 0
4160 12:12:10.977354 1, 0xFFFF, sum = 0
4161 12:12:10.977922 2, 0xFFFF, sum = 0
4162 12:12:10.979751 3, 0xFFFF, sum = 0
4163 12:12:10.980219 4, 0xFFFF, sum = 0
4164 12:12:10.983838 5, 0xFFFF, sum = 0
4165 12:12:10.984413 6, 0xFFFF, sum = 0
4166 12:12:10.986775 7, 0xFFFF, sum = 0
4167 12:12:10.987340 8, 0x0, sum = 1
4168 12:12:10.990028 9, 0x0, sum = 2
4169 12:12:10.990492 10, 0x0, sum = 3
4170 12:12:10.993067 11, 0x0, sum = 4
4171 12:12:10.993530 best_step = 9
4172 12:12:10.993915
4173 12:12:10.994255 ==
4174 12:12:10.997168 Dram Type= 6, Freq= 0, CH_0, rank 0
4175 12:12:11.000104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 12:12:11.000667 ==
4177 12:12:11.003319 RX Vref Scan: 1
4178 12:12:11.003843
4179 12:12:11.006964 RX Vref 0 -> 0, step: 1
4180 12:12:11.007523
4181 12:12:11.007983 RX Delay -195 -> 252, step: 8
4182 12:12:11.008336
4183 12:12:11.010404 Set Vref, RX VrefLevel [Byte0]: 60
4184 12:12:11.013341 [Byte1]: 58
4185 12:12:11.018073
4186 12:12:11.018529 Final RX Vref Byte 0 = 60 to rank0
4187 12:12:11.020987 Final RX Vref Byte 1 = 58 to rank0
4188 12:12:11.024053 Final RX Vref Byte 0 = 60 to rank1
4189 12:12:11.027940 Final RX Vref Byte 1 = 58 to rank1==
4190 12:12:11.031046 Dram Type= 6, Freq= 0, CH_0, rank 0
4191 12:12:11.037951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 12:12:11.038516 ==
4193 12:12:11.038886 DQS Delay:
4194 12:12:11.040839 DQS0 = 0, DQS1 = 0
4195 12:12:11.041316 DQM Delay:
4196 12:12:11.041688 DQM0 = 44, DQM1 = 32
4197 12:12:11.044617 DQ Delay:
4198 12:12:11.047310 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4199 12:12:11.050480 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4200 12:12:11.053755 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4201 12:12:11.057028 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4202 12:12:11.057485
4203 12:12:11.057850
4204 12:12:11.064583 [DQSOSCAuto] RK0, (LSB)MR18= 0x6b42, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 389 ps
4205 12:12:11.067261 CH0 RK0: MR19=808, MR18=6B42
4206 12:12:11.073807 CH0_RK0: MR19=0x808, MR18=0x6B42, DQSOSC=389, MR23=63, INC=173, DEC=115
4207 12:12:11.074334
4208 12:12:11.077262 ----->DramcWriteLeveling(PI) begin...
4209 12:12:11.077687 ==
4210 12:12:11.080644 Dram Type= 6, Freq= 0, CH_0, rank 1
4211 12:12:11.084221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4212 12:12:11.084750 ==
4213 12:12:11.087713 Write leveling (Byte 0): 32 => 32
4214 12:12:11.091456 Write leveling (Byte 1): 30 => 30
4215 12:12:11.093712 DramcWriteLeveling(PI) end<-----
4216 12:12:11.094234
4217 12:12:11.094571 ==
4218 12:12:11.096905 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 12:12:11.103585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 12:12:11.104114 ==
4221 12:12:11.104450 [Gating] SW mode calibration
4222 12:12:11.113241 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4223 12:12:11.116318 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4224 12:12:11.120082 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4225 12:12:11.126657 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4226 12:12:11.130738 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4227 12:12:11.133514 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4228 12:12:11.139547 0 9 16 | B1->B0 | 2b2b 2727 | 0 0 | (0 0) (0 0)
4229 12:12:11.142895 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 12:12:11.146600 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 12:12:11.152646 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 12:12:11.156145 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 12:12:11.159262 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 12:12:11.167159 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 12:12:11.169037 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 12:12:11.172496 0 10 16 | B1->B0 | 3737 3c3c | 0 1 | (0 0) (0 0)
4237 12:12:11.179820 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 12:12:11.182529 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 12:12:11.186418 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 12:12:11.192319 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 12:12:11.195489 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 12:12:11.199481 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 12:12:11.205424 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4244 12:12:11.208718 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4245 12:12:11.212021 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 12:12:11.218668 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 12:12:11.222942 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 12:12:11.225364 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 12:12:11.231795 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 12:12:11.235391 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 12:12:11.238304 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 12:12:11.245427 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 12:12:11.248695 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 12:12:11.251637 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 12:12:11.257927 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 12:12:11.261462 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 12:12:11.264459 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 12:12:11.271794 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 12:12:11.275433 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4260 12:12:11.277913 Total UI for P1: 0, mck2ui 16
4261 12:12:11.282003 best dqsien dly found for B1: ( 0, 13, 10)
4262 12:12:11.284222 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4263 12:12:11.288227 Total UI for P1: 0, mck2ui 16
4264 12:12:11.291288 best dqsien dly found for B0: ( 0, 13, 12)
4265 12:12:11.294765 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4266 12:12:11.301375 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4267 12:12:11.301986
4268 12:12:11.304757 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4269 12:12:11.307911 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4270 12:12:11.310931 [Gating] SW calibration Done
4271 12:12:11.311501 ==
4272 12:12:11.314126 Dram Type= 6, Freq= 0, CH_0, rank 1
4273 12:12:11.317533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4274 12:12:11.318001 ==
4275 12:12:11.320580 RX Vref Scan: 0
4276 12:12:11.321154
4277 12:12:11.321532 RX Vref 0 -> 0, step: 1
4278 12:12:11.321881
4279 12:12:11.324081 RX Delay -230 -> 252, step: 16
4280 12:12:11.330776 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4281 12:12:11.334086 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4282 12:12:11.337059 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4283 12:12:11.340294 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4284 12:12:11.343601 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4285 12:12:11.350405 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4286 12:12:11.353360 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4287 12:12:11.357203 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4288 12:12:11.359781 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4289 12:12:11.366614 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4290 12:12:11.370490 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4291 12:12:11.373472 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4292 12:12:11.376295 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4293 12:12:11.383214 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4294 12:12:11.386234 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4295 12:12:11.390098 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4296 12:12:11.390692 ==
4297 12:12:11.393022 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 12:12:11.399442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 12:12:11.399955 ==
4300 12:12:11.400331 DQS Delay:
4301 12:12:11.400680 DQS0 = 0, DQS1 = 0
4302 12:12:11.403599 DQM Delay:
4303 12:12:11.404111 DQM0 = 41, DQM1 = 35
4304 12:12:11.405950 DQ Delay:
4305 12:12:11.409692 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4306 12:12:11.412744 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4307 12:12:11.413213 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4308 12:12:11.419716 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4309 12:12:11.420140
4310 12:12:11.420476
4311 12:12:11.420787 ==
4312 12:12:11.422339 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 12:12:11.426234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 12:12:11.426670 ==
4315 12:12:11.427003
4316 12:12:11.427311
4317 12:12:11.428867 TX Vref Scan disable
4318 12:12:11.429219 == TX Byte 0 ==
4319 12:12:11.435713 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4320 12:12:11.438660 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4321 12:12:11.438885 == TX Byte 1 ==
4322 12:12:11.445402 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4323 12:12:11.448733 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4324 12:12:11.448885 ==
4325 12:12:11.451836 Dram Type= 6, Freq= 0, CH_0, rank 1
4326 12:12:11.455278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 12:12:11.455409 ==
4328 12:12:11.455513
4329 12:12:11.458342
4330 12:12:11.458509 TX Vref Scan disable
4331 12:12:11.461987 == TX Byte 0 ==
4332 12:12:11.465617 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4333 12:12:11.471959 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4334 12:12:11.472084 == TX Byte 1 ==
4335 12:12:11.475947 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4336 12:12:11.481918 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4337 12:12:11.482049
4338 12:12:11.482151 [DATLAT]
4339 12:12:11.482247 Freq=600, CH0 RK1
4340 12:12:11.482341
4341 12:12:11.484683 DATLAT Default: 0x9
4342 12:12:11.488805 0, 0xFFFF, sum = 0
4343 12:12:11.488938 1, 0xFFFF, sum = 0
4344 12:12:11.491635 2, 0xFFFF, sum = 0
4345 12:12:11.491813 3, 0xFFFF, sum = 0
4346 12:12:11.494633 4, 0xFFFF, sum = 0
4347 12:12:11.494813 5, 0xFFFF, sum = 0
4348 12:12:11.498479 6, 0xFFFF, sum = 0
4349 12:12:11.498655 7, 0xFFFF, sum = 0
4350 12:12:11.501368 8, 0x0, sum = 1
4351 12:12:11.501675 9, 0x0, sum = 2
4352 12:12:11.504704 10, 0x0, sum = 3
4353 12:12:11.505023 11, 0x0, sum = 4
4354 12:12:11.505217 best_step = 9
4355 12:12:11.508700
4356 12:12:11.508890 ==
4357 12:12:11.511151 Dram Type= 6, Freq= 0, CH_0, rank 1
4358 12:12:11.514595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4359 12:12:11.514811 ==
4360 12:12:11.514997 RX Vref Scan: 0
4361 12:12:11.515163
4362 12:12:11.517682 RX Vref 0 -> 0, step: 1
4363 12:12:11.517878
4364 12:12:11.521055 RX Delay -195 -> 252, step: 8
4365 12:12:11.527487 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4366 12:12:11.531222 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4367 12:12:11.534457 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4368 12:12:11.537914 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4369 12:12:11.544577 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4370 12:12:11.547998 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4371 12:12:11.551147 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4372 12:12:11.554240 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4373 12:12:11.558142 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4374 12:12:11.563973 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4375 12:12:11.567145 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4376 12:12:11.570572 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4377 12:12:11.576873 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4378 12:12:11.580116 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4379 12:12:11.584582 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4380 12:12:11.587353 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4381 12:12:11.587594 ==
4382 12:12:11.590797 Dram Type= 6, Freq= 0, CH_0, rank 1
4383 12:12:11.597053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4384 12:12:11.597348 ==
4385 12:12:11.597526 DQS Delay:
4386 12:12:11.600727 DQS0 = 0, DQS1 = 0
4387 12:12:11.601062 DQM Delay:
4388 12:12:11.601271 DQM0 = 41, DQM1 = 36
4389 12:12:11.604190 DQ Delay:
4390 12:12:11.607148 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4391 12:12:11.611089 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4392 12:12:11.614435 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4393 12:12:11.617306 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4394 12:12:11.617775
4395 12:12:11.618149
4396 12:12:11.624061 [DQSOSCAuto] RK1, (LSB)MR18= 0x5e11, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
4397 12:12:11.627197 CH0 RK1: MR19=808, MR18=5E11
4398 12:12:11.633804 CH0_RK1: MR19=0x808, MR18=0x5E11, DQSOSC=392, MR23=63, INC=170, DEC=113
4399 12:12:11.636981 [RxdqsGatingPostProcess] freq 600
4400 12:12:11.640246 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4401 12:12:11.643566 Pre-setting of DQS Precalculation
4402 12:12:11.650496 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4403 12:12:11.651062 ==
4404 12:12:11.653458 Dram Type= 6, Freq= 0, CH_1, rank 0
4405 12:12:11.656651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4406 12:12:11.657283 ==
4407 12:12:11.663452 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4408 12:12:11.670606 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4409 12:12:11.673094 [CA 0] Center 35 (5~66) winsize 62
4410 12:12:11.676633 [CA 1] Center 35 (5~66) winsize 62
4411 12:12:11.679821 [CA 2] Center 34 (3~65) winsize 63
4412 12:12:11.683550 [CA 3] Center 33 (3~64) winsize 62
4413 12:12:11.686824 [CA 4] Center 34 (4~64) winsize 61
4414 12:12:11.690877 [CA 5] Center 33 (3~64) winsize 62
4415 12:12:11.691436
4416 12:12:11.693061 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4417 12:12:11.693678
4418 12:12:11.696008 [CATrainingPosCal] consider 1 rank data
4419 12:12:11.699369 u2DelayCellTimex100 = 270/100 ps
4420 12:12:11.703196 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4421 12:12:11.706009 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4422 12:12:11.709471 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4423 12:12:11.713059 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4424 12:12:11.716301 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4425 12:12:11.719431 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4426 12:12:11.722917
4427 12:12:11.726324 CA PerBit enable=1, Macro0, CA PI delay=33
4428 12:12:11.726884
4429 12:12:11.729454 [CBTSetCACLKResult] CA Dly = 33
4430 12:12:11.730017 CS Dly: 4 (0~35)
4431 12:12:11.730395 ==
4432 12:12:11.733016 Dram Type= 6, Freq= 0, CH_1, rank 1
4433 12:12:11.735617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4434 12:12:11.738976 ==
4435 12:12:11.742063 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4436 12:12:11.748829 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4437 12:12:11.752166 [CA 0] Center 35 (5~66) winsize 62
4438 12:12:11.755580 [CA 1] Center 36 (6~66) winsize 61
4439 12:12:11.759355 [CA 2] Center 34 (4~65) winsize 62
4440 12:12:11.762268 [CA 3] Center 34 (3~65) winsize 63
4441 12:12:11.765653 [CA 4] Center 34 (4~65) winsize 62
4442 12:12:11.769141 [CA 5] Center 34 (3~65) winsize 63
4443 12:12:11.769703
4444 12:12:11.772004 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4445 12:12:11.772470
4446 12:12:11.775172 [CATrainingPosCal] consider 2 rank data
4447 12:12:11.778710 u2DelayCellTimex100 = 270/100 ps
4448 12:12:11.782109 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4449 12:12:11.786427 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4450 12:12:11.792325 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4451 12:12:11.795246 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4452 12:12:11.798163 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4453 12:12:11.801881 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4454 12:12:11.802439
4455 12:12:11.804891 CA PerBit enable=1, Macro0, CA PI delay=33
4456 12:12:11.805351
4457 12:12:11.808438 [CBTSetCACLKResult] CA Dly = 33
4458 12:12:11.809268 CS Dly: 5 (0~38)
4459 12:12:11.809680
4460 12:12:11.811365 ----->DramcWriteLeveling(PI) begin...
4461 12:12:11.814617 ==
4462 12:12:11.818664 Dram Type= 6, Freq= 0, CH_1, rank 0
4463 12:12:11.822434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4464 12:12:11.822997 ==
4465 12:12:11.825164 Write leveling (Byte 0): 30 => 30
4466 12:12:11.828293 Write leveling (Byte 1): 30 => 30
4467 12:12:11.831366 DramcWriteLeveling(PI) end<-----
4468 12:12:11.832039
4469 12:12:11.832468 ==
4470 12:12:11.834784 Dram Type= 6, Freq= 0, CH_1, rank 0
4471 12:12:11.837944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 12:12:11.838407 ==
4473 12:12:11.841165 [Gating] SW mode calibration
4474 12:12:11.847949 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4475 12:12:11.854882 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4476 12:12:11.858075 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4477 12:12:11.861538 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4478 12:12:11.867423 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4479 12:12:11.870892 0 9 12 | B1->B0 | 3232 3030 | 1 0 | (1 1) (0 1)
4480 12:12:11.873927 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 12:12:11.880537 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 12:12:11.883999 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 12:12:11.887188 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 12:12:11.893998 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 12:12:11.897285 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 12:12:11.900592 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 12:12:11.907125 0 10 12 | B1->B0 | 3333 3838 | 0 1 | (1 1) (0 0)
4488 12:12:11.910475 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 12:12:11.913998 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 12:12:11.920402 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 12:12:11.923883 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 12:12:11.927040 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 12:12:11.933551 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 12:12:11.936732 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 12:12:11.940208 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 12:12:11.947038 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 12:12:11.950590 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 12:12:11.953635 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 12:12:11.959808 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 12:12:11.963252 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 12:12:11.966877 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 12:12:11.972666 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 12:12:11.976570 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 12:12:11.979951 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 12:12:11.986416 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 12:12:11.989107 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 12:12:11.992946 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 12:12:11.999829 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 12:12:12.002775 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 12:12:12.005971 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 12:12:12.012537 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4512 12:12:12.016253 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 12:12:12.020104 Total UI for P1: 0, mck2ui 16
4514 12:12:12.022803 best dqsien dly found for B0: ( 0, 13, 12)
4515 12:12:12.026242 Total UI for P1: 0, mck2ui 16
4516 12:12:12.029015 best dqsien dly found for B1: ( 0, 13, 14)
4517 12:12:12.032491 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4518 12:12:12.035836 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4519 12:12:12.036392
4520 12:12:12.039440 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4521 12:12:12.041862 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4522 12:12:12.045526 [Gating] SW calibration Done
4523 12:12:12.046091 ==
4524 12:12:12.048566 Dram Type= 6, Freq= 0, CH_1, rank 0
4525 12:12:12.055923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4526 12:12:12.056477 ==
4527 12:12:12.056853 RX Vref Scan: 0
4528 12:12:12.057200
4529 12:12:12.058297 RX Vref 0 -> 0, step: 1
4530 12:12:12.058760
4531 12:12:12.061623 RX Delay -230 -> 252, step: 16
4532 12:12:12.065609 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4533 12:12:12.068022 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4534 12:12:12.071933 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4535 12:12:12.079164 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4536 12:12:12.081984 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4537 12:12:12.084684 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4538 12:12:12.088377 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4539 12:12:12.095299 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4540 12:12:12.098052 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4541 12:12:12.101576 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4542 12:12:12.104775 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4543 12:12:12.111515 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4544 12:12:12.114367 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4545 12:12:12.118321 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4546 12:12:12.120904 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4547 12:12:12.128296 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4548 12:12:12.128853 ==
4549 12:12:12.131288 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 12:12:12.134829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 12:12:12.135405 ==
4552 12:12:12.135962 DQS Delay:
4553 12:12:12.137672 DQS0 = 0, DQS1 = 0
4554 12:12:12.138128 DQM Delay:
4555 12:12:12.140590 DQM0 = 47, DQM1 = 38
4556 12:12:12.141049 DQ Delay:
4557 12:12:12.144321 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4558 12:12:12.147306 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4559 12:12:12.150668 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25
4560 12:12:12.153742 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4561 12:12:12.154204
4562 12:12:12.154571
4563 12:12:12.154906 ==
4564 12:12:12.157663 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 12:12:12.160460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 12:12:12.163858 ==
4567 12:12:12.164325
4568 12:12:12.164697
4569 12:12:12.165039 TX Vref Scan disable
4570 12:12:12.167528 == TX Byte 0 ==
4571 12:12:12.170586 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4572 12:12:12.173822 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4573 12:12:12.177182 == TX Byte 1 ==
4574 12:12:12.180130 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4575 12:12:12.187401 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4576 12:12:12.188013 ==
4577 12:12:12.190729 Dram Type= 6, Freq= 0, CH_1, rank 0
4578 12:12:12.193617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 12:12:12.194179 ==
4580 12:12:12.194584
4581 12:12:12.194935
4582 12:12:12.197033 TX Vref Scan disable
4583 12:12:12.200249 == TX Byte 0 ==
4584 12:12:12.203011 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4585 12:12:12.206531 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4586 12:12:12.210165 == TX Byte 1 ==
4587 12:12:12.213099 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4588 12:12:12.216201 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4589 12:12:12.216668
4590 12:12:12.217035 [DATLAT]
4591 12:12:12.219380 Freq=600, CH1 RK0
4592 12:12:12.219924
4593 12:12:12.223252 DATLAT Default: 0x9
4594 12:12:12.223764 0, 0xFFFF, sum = 0
4595 12:12:12.226336 1, 0xFFFF, sum = 0
4596 12:12:12.226893 2, 0xFFFF, sum = 0
4597 12:12:12.230026 3, 0xFFFF, sum = 0
4598 12:12:12.230590 4, 0xFFFF, sum = 0
4599 12:12:12.232946 5, 0xFFFF, sum = 0
4600 12:12:12.233418 6, 0xFFFF, sum = 0
4601 12:12:12.235894 7, 0xFFFF, sum = 0
4602 12:12:12.236368 8, 0x0, sum = 1
4603 12:12:12.239530 9, 0x0, sum = 2
4604 12:12:12.240090 10, 0x0, sum = 3
4605 12:12:12.242364 11, 0x0, sum = 4
4606 12:12:12.242834 best_step = 9
4607 12:12:12.243204
4608 12:12:12.243548 ==
4609 12:12:12.246023 Dram Type= 6, Freq= 0, CH_1, rank 0
4610 12:12:12.249281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4611 12:12:12.249757 ==
4612 12:12:12.253156 RX Vref Scan: 1
4613 12:12:12.253621
4614 12:12:12.255767 RX Vref 0 -> 0, step: 1
4615 12:12:12.256239
4616 12:12:12.256610 RX Delay -195 -> 252, step: 8
4617 12:12:12.259217
4618 12:12:12.259763 Set Vref, RX VrefLevel [Byte0]: 50
4619 12:12:12.262475 [Byte1]: 60
4620 12:12:12.267280
4621 12:12:12.267756 Final RX Vref Byte 0 = 50 to rank0
4622 12:12:12.270643 Final RX Vref Byte 1 = 60 to rank0
4623 12:12:12.273817 Final RX Vref Byte 0 = 50 to rank1
4624 12:12:12.277408 Final RX Vref Byte 1 = 60 to rank1==
4625 12:12:12.280825 Dram Type= 6, Freq= 0, CH_1, rank 0
4626 12:12:12.287064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 12:12:12.287586 ==
4628 12:12:12.288029 DQS Delay:
4629 12:12:12.290579 DQS0 = 0, DQS1 = 0
4630 12:12:12.291099 DQM Delay:
4631 12:12:12.291441 DQM0 = 48, DQM1 = 38
4632 12:12:12.293933 DQ Delay:
4633 12:12:12.296464 DQ0 =56, DQ1 =44, DQ2 =40, DQ3 =44
4634 12:12:12.300627 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4635 12:12:12.303579 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4636 12:12:12.306662 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4637 12:12:12.307093
4638 12:12:12.307430
4639 12:12:12.313403 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b30, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4640 12:12:12.316509 CH1 RK0: MR19=808, MR18=4B30
4641 12:12:12.323505 CH1_RK0: MR19=0x808, MR18=0x4B30, DQSOSC=395, MR23=63, INC=168, DEC=112
4642 12:12:12.324115
4643 12:12:12.326899 ----->DramcWriteLeveling(PI) begin...
4644 12:12:12.327442 ==
4645 12:12:12.329946 Dram Type= 6, Freq= 0, CH_1, rank 1
4646 12:12:12.333194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4647 12:12:12.333624 ==
4648 12:12:12.336626 Write leveling (Byte 0): 30 => 30
4649 12:12:12.339968 Write leveling (Byte 1): 31 => 31
4650 12:12:12.343710 DramcWriteLeveling(PI) end<-----
4651 12:12:12.344230
4652 12:12:12.344569 ==
4653 12:12:12.346444 Dram Type= 6, Freq= 0, CH_1, rank 1
4654 12:12:12.349838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 12:12:12.353136 ==
4656 12:12:12.353560 [Gating] SW mode calibration
4657 12:12:12.362669 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4658 12:12:12.366064 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4659 12:12:12.369555 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4660 12:12:12.376383 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4661 12:12:12.379449 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4662 12:12:12.382470 0 9 12 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 0)
4663 12:12:12.389500 0 9 16 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4664 12:12:12.392413 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 12:12:12.395653 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 12:12:12.402249 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 12:12:12.405339 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 12:12:12.408860 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 12:12:12.415731 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 12:12:12.418865 0 10 12 | B1->B0 | 3c3c 2a2a | 1 0 | (0 0) (0 0)
4671 12:12:12.422317 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 12:12:12.428450 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 12:12:12.431790 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 12:12:12.435087 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 12:12:12.441825 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 12:12:12.445251 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 12:12:12.448492 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 12:12:12.454739 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 12:12:12.458395 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 12:12:12.461498 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 12:12:12.468279 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 12:12:12.471159 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 12:12:12.474493 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 12:12:12.481277 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 12:12:12.484387 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 12:12:12.490814 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 12:12:12.494304 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 12:12:12.497536 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 12:12:12.504779 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 12:12:12.507909 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 12:12:12.510971 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 12:12:12.517367 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 12:12:12.520243 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 12:12:12.523652 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4695 12:12:12.527524 Total UI for P1: 0, mck2ui 16
4696 12:12:12.530668 best dqsien dly found for B1: ( 0, 13, 10)
4697 12:12:12.537333 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 12:12:12.537759 Total UI for P1: 0, mck2ui 16
4699 12:12:12.543668 best dqsien dly found for B0: ( 0, 13, 14)
4700 12:12:12.546611 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4701 12:12:12.550705 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4702 12:12:12.551228
4703 12:12:12.554592 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4704 12:12:12.556762 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4705 12:12:12.560214 [Gating] SW calibration Done
4706 12:12:12.560799 ==
4707 12:12:12.563163 Dram Type= 6, Freq= 0, CH_1, rank 1
4708 12:12:12.566857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4709 12:12:12.567419 ==
4710 12:12:12.569729 RX Vref Scan: 0
4711 12:12:12.570192
4712 12:12:12.570591 RX Vref 0 -> 0, step: 1
4713 12:12:12.570940
4714 12:12:12.573354 RX Delay -230 -> 252, step: 16
4715 12:12:12.580086 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4716 12:12:12.583819 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4717 12:12:12.586489 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4718 12:12:12.590082 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4719 12:12:12.593649 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4720 12:12:12.599643 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4721 12:12:12.603095 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4722 12:12:12.606502 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4723 12:12:12.609559 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4724 12:12:12.616212 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4725 12:12:12.619942 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4726 12:12:12.623252 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4727 12:12:12.626423 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4728 12:12:12.632633 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4729 12:12:12.636460 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4730 12:12:12.639154 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4731 12:12:12.639612 ==
4732 12:12:12.643003 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 12:12:12.645809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 12:12:12.649149 ==
4735 12:12:12.649608 DQS Delay:
4736 12:12:12.649971 DQS0 = 0, DQS1 = 0
4737 12:12:12.652522 DQM Delay:
4738 12:12:12.653079 DQM0 = 44, DQM1 = 39
4739 12:12:12.655755 DQ Delay:
4740 12:12:12.659552 DQ0 =57, DQ1 =41, DQ2 =25, DQ3 =41
4741 12:12:12.660170 DQ4 =33, DQ5 =57, DQ6 =57, DQ7 =41
4742 12:12:12.662417 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4743 12:12:12.669615 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4744 12:12:12.670173
4745 12:12:12.670540
4746 12:12:12.670880 ==
4747 12:12:12.672030 Dram Type= 6, Freq= 0, CH_1, rank 1
4748 12:12:12.676258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4749 12:12:12.676846 ==
4750 12:12:12.677279
4751 12:12:12.677625
4752 12:12:12.679030 TX Vref Scan disable
4753 12:12:12.679484 == TX Byte 0 ==
4754 12:12:12.685922 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4755 12:12:12.688942 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4756 12:12:12.689499 == TX Byte 1 ==
4757 12:12:12.695558 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4758 12:12:12.698279 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4759 12:12:12.698784 ==
4760 12:12:12.701867 Dram Type= 6, Freq= 0, CH_1, rank 1
4761 12:12:12.705348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4762 12:12:12.705917 ==
4763 12:12:12.708287
4764 12:12:12.708752
4765 12:12:12.709117 TX Vref Scan disable
4766 12:12:12.712142 == TX Byte 0 ==
4767 12:12:12.715433 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4768 12:12:12.722580 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4769 12:12:12.723127 == TX Byte 1 ==
4770 12:12:12.725268 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4771 12:12:12.732227 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4772 12:12:12.732790
4773 12:12:12.733159 [DATLAT]
4774 12:12:12.733502 Freq=600, CH1 RK1
4775 12:12:12.733832
4776 12:12:12.735609 DATLAT Default: 0x9
4777 12:12:12.736201 0, 0xFFFF, sum = 0
4778 12:12:12.738111 1, 0xFFFF, sum = 0
4779 12:12:12.741432 2, 0xFFFF, sum = 0
4780 12:12:12.741898 3, 0xFFFF, sum = 0
4781 12:12:12.745922 4, 0xFFFF, sum = 0
4782 12:12:12.746485 5, 0xFFFF, sum = 0
4783 12:12:12.748261 6, 0xFFFF, sum = 0
4784 12:12:12.748725 7, 0xFFFF, sum = 0
4785 12:12:12.751898 8, 0x0, sum = 1
4786 12:12:12.752459 9, 0x0, sum = 2
4787 12:12:12.752835 10, 0x0, sum = 3
4788 12:12:12.755253 11, 0x0, sum = 4
4789 12:12:12.756068 best_step = 9
4790 12:12:12.756465
4791 12:12:12.756819 ==
4792 12:12:12.758508 Dram Type= 6, Freq= 0, CH_1, rank 1
4793 12:12:12.764587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4794 12:12:12.765072 ==
4795 12:12:12.765444 RX Vref Scan: 0
4796 12:12:12.765792
4797 12:12:12.768915 RX Vref 0 -> 0, step: 1
4798 12:12:12.769474
4799 12:12:12.771597 RX Delay -179 -> 252, step: 8
4800 12:12:12.775175 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4801 12:12:12.781600 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4802 12:12:12.784291 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4803 12:12:12.788080 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4804 12:12:12.791635 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4805 12:12:12.797642 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4806 12:12:12.801130 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4807 12:12:12.804553 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4808 12:12:12.808163 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4809 12:12:12.811324 iDelay=213, Bit 9, Center 28 (-123 ~ 180) 304
4810 12:12:12.817478 iDelay=213, Bit 10, Center 40 (-115 ~ 196) 312
4811 12:12:12.821170 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4812 12:12:12.824262 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4813 12:12:12.827419 iDelay=213, Bit 13, Center 48 (-107 ~ 204) 312
4814 12:12:12.834293 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4815 12:12:12.837769 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4816 12:12:12.838354 ==
4817 12:12:12.840977 Dram Type= 6, Freq= 0, CH_1, rank 1
4818 12:12:12.844248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4819 12:12:12.844729 ==
4820 12:12:12.847998 DQS Delay:
4821 12:12:12.848454 DQS0 = 0, DQS1 = 0
4822 12:12:12.850907 DQM Delay:
4823 12:12:12.851464 DQM0 = 45, DQM1 = 38
4824 12:12:12.851928 DQ Delay:
4825 12:12:12.853945 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4826 12:12:12.857650 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4827 12:12:12.861485 DQ8 =24, DQ9 =28, DQ10 =40, DQ11 =28
4828 12:12:12.863603 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =48
4829 12:12:12.864167
4830 12:12:12.864775
4831 12:12:12.874437 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b20, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4832 12:12:12.877522 CH1 RK1: MR19=808, MR18=2B20
4833 12:12:12.883869 CH1_RK1: MR19=0x808, MR18=0x2B20, DQSOSC=401, MR23=63, INC=163, DEC=108
4834 12:12:12.886886 [RxdqsGatingPostProcess] freq 600
4835 12:12:12.891144 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4836 12:12:12.893391 Pre-setting of DQS Precalculation
4837 12:12:12.899952 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4838 12:12:12.906771 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4839 12:12:12.913377 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4840 12:12:12.913938
4841 12:12:12.914394
4842 12:12:12.916284 [Calibration Summary] 1200 Mbps
4843 12:12:12.916740 CH 0, Rank 0
4844 12:12:12.919666 SW Impedance : PASS
4845 12:12:12.923113 DUTY Scan : NO K
4846 12:12:12.923570 ZQ Calibration : PASS
4847 12:12:12.926975 Jitter Meter : NO K
4848 12:12:12.930547 CBT Training : PASS
4849 12:12:12.931101 Write leveling : PASS
4850 12:12:12.933469 RX DQS gating : PASS
4851 12:12:12.933925 RX DQ/DQS(RDDQC) : PASS
4852 12:12:12.936564 TX DQ/DQS : PASS
4853 12:12:12.939720 RX DATLAT : PASS
4854 12:12:12.940182 RX DQ/DQS(Engine): PASS
4855 12:12:12.942799 TX OE : NO K
4856 12:12:12.943393 All Pass.
4857 12:12:12.943861
4858 12:12:12.946331 CH 0, Rank 1
4859 12:12:12.947011 SW Impedance : PASS
4860 12:12:12.949475 DUTY Scan : NO K
4861 12:12:12.952752 ZQ Calibration : PASS
4862 12:12:12.953209 Jitter Meter : NO K
4863 12:12:12.956201 CBT Training : PASS
4864 12:12:12.959264 Write leveling : PASS
4865 12:12:12.959712 RX DQS gating : PASS
4866 12:12:12.962721 RX DQ/DQS(RDDQC) : PASS
4867 12:12:12.966281 TX DQ/DQS : PASS
4868 12:12:12.966834 RX DATLAT : PASS
4869 12:12:12.968998 RX DQ/DQS(Engine): PASS
4870 12:12:12.972591 TX OE : NO K
4871 12:12:12.973012 All Pass.
4872 12:12:12.973345
4873 12:12:12.973650 CH 1, Rank 0
4874 12:12:12.976547 SW Impedance : PASS
4875 12:12:12.979281 DUTY Scan : NO K
4876 12:12:12.979836 ZQ Calibration : PASS
4877 12:12:12.982533 Jitter Meter : NO K
4878 12:12:12.985860 CBT Training : PASS
4879 12:12:12.986272 Write leveling : PASS
4880 12:12:12.988704 RX DQS gating : PASS
4881 12:12:12.992548 RX DQ/DQS(RDDQC) : PASS
4882 12:12:12.992962 TX DQ/DQS : PASS
4883 12:12:12.995985 RX DATLAT : PASS
4884 12:12:12.999322 RX DQ/DQS(Engine): PASS
4885 12:12:12.999817 TX OE : NO K
4886 12:12:13.000165 All Pass.
4887 12:12:13.000481
4888 12:12:13.003144 CH 1, Rank 1
4889 12:12:13.003666 SW Impedance : PASS
4890 12:12:13.005883 DUTY Scan : NO K
4891 12:12:13.008776 ZQ Calibration : PASS
4892 12:12:13.009275 Jitter Meter : NO K
4893 12:12:13.012464 CBT Training : PASS
4894 12:12:13.015866 Write leveling : PASS
4895 12:12:13.016425 RX DQS gating : PASS
4896 12:12:13.019420 RX DQ/DQS(RDDQC) : PASS
4897 12:12:13.021911 TX DQ/DQS : PASS
4898 12:12:13.022376 RX DATLAT : PASS
4899 12:12:13.025952 RX DQ/DQS(Engine): PASS
4900 12:12:13.028667 TX OE : NO K
4901 12:12:13.029133 All Pass.
4902 12:12:13.029502
4903 12:12:13.031972 DramC Write-DBI off
4904 12:12:13.032432 PER_BANK_REFRESH: Hybrid Mode
4905 12:12:13.035006 TX_TRACKING: ON
4906 12:12:13.044920 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4907 12:12:13.048471 [FAST_K] Save calibration result to emmc
4908 12:12:13.053152 dramc_set_vcore_voltage set vcore to 662500
4909 12:12:13.053730 Read voltage for 933, 3
4910 12:12:13.055943 Vio18 = 0
4911 12:12:13.056405 Vcore = 662500
4912 12:12:13.056772 Vdram = 0
4913 12:12:13.058183 Vddq = 0
4914 12:12:13.058642 Vmddr = 0
4915 12:12:13.064847 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4916 12:12:13.068236 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4917 12:12:13.071650 MEM_TYPE=3, freq_sel=17
4918 12:12:13.074804 sv_algorithm_assistance_LP4_1600
4919 12:12:13.078330 ============ PULL DRAM RESETB DOWN ============
4920 12:12:13.081916 ========== PULL DRAM RESETB DOWN end =========
4921 12:12:13.088378 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4922 12:12:13.090799 ===================================
4923 12:12:13.091260 LPDDR4 DRAM CONFIGURATION
4924 12:12:13.094399 ===================================
4925 12:12:13.098318 EX_ROW_EN[0] = 0x0
4926 12:12:13.101547 EX_ROW_EN[1] = 0x0
4927 12:12:13.102105 LP4Y_EN = 0x0
4928 12:12:13.104369 WORK_FSP = 0x0
4929 12:12:13.104932 WL = 0x3
4930 12:12:13.107622 RL = 0x3
4931 12:12:13.108133 BL = 0x2
4932 12:12:13.111245 RPST = 0x0
4933 12:12:13.111860 RD_PRE = 0x0
4934 12:12:13.114800 WR_PRE = 0x1
4935 12:12:13.115356 WR_PST = 0x0
4936 12:12:13.118324 DBI_WR = 0x0
4937 12:12:13.119178 DBI_RD = 0x0
4938 12:12:13.120762 OTF = 0x1
4939 12:12:13.124457 ===================================
4940 12:12:13.127508 ===================================
4941 12:12:13.128198 ANA top config
4942 12:12:13.130463 ===================================
4943 12:12:13.133769 DLL_ASYNC_EN = 0
4944 12:12:13.137392 ALL_SLAVE_EN = 1
4945 12:12:13.140991 NEW_RANK_MODE = 1
4946 12:12:13.141455 DLL_IDLE_MODE = 1
4947 12:12:13.144071 LP45_APHY_COMB_EN = 1
4948 12:12:13.147498 TX_ODT_DIS = 1
4949 12:12:13.151063 NEW_8X_MODE = 1
4950 12:12:13.153910 ===================================
4951 12:12:13.157189 ===================================
4952 12:12:13.161080 data_rate = 1866
4953 12:12:13.161546 CKR = 1
4954 12:12:13.164381 DQ_P2S_RATIO = 8
4955 12:12:13.167392 ===================================
4956 12:12:13.170713 CA_P2S_RATIO = 8
4957 12:12:13.173472 DQ_CA_OPEN = 0
4958 12:12:13.177019 DQ_SEMI_OPEN = 0
4959 12:12:13.180916 CA_SEMI_OPEN = 0
4960 12:12:13.184131 CA_FULL_RATE = 0
4961 12:12:13.184697 DQ_CKDIV4_EN = 1
4962 12:12:13.186828 CA_CKDIV4_EN = 1
4963 12:12:13.190082 CA_PREDIV_EN = 0
4964 12:12:13.193067 PH8_DLY = 0
4965 12:12:13.196640 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4966 12:12:13.200090 DQ_AAMCK_DIV = 4
4967 12:12:13.200660 CA_AAMCK_DIV = 4
4968 12:12:13.203125 CA_ADMCK_DIV = 4
4969 12:12:13.206641 DQ_TRACK_CA_EN = 0
4970 12:12:13.209979 CA_PICK = 933
4971 12:12:13.212859 CA_MCKIO = 933
4972 12:12:13.216466 MCKIO_SEMI = 0
4973 12:12:13.219617 PLL_FREQ = 3732
4974 12:12:13.220250 DQ_UI_PI_RATIO = 32
4975 12:12:13.223159 CA_UI_PI_RATIO = 0
4976 12:12:13.226801 ===================================
4977 12:12:13.229819 ===================================
4978 12:12:13.233774 memory_type:LPDDR4
4979 12:12:13.235846 GP_NUM : 10
4980 12:12:13.236311 SRAM_EN : 1
4981 12:12:13.239635 MD32_EN : 0
4982 12:12:13.242654 ===================================
4983 12:12:13.246186 [ANA_INIT] >>>>>>>>>>>>>>
4984 12:12:13.246753 <<<<<< [CONFIGURE PHASE]: ANA_TX
4985 12:12:13.252905 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4986 12:12:13.255581 ===================================
4987 12:12:13.256092 data_rate = 1866,PCW = 0X8f00
4988 12:12:13.258900 ===================================
4989 12:12:13.263241 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4990 12:12:13.268978 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4991 12:12:13.275541 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4992 12:12:13.279710 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4993 12:12:13.282315 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4994 12:12:13.285770 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4995 12:12:13.288479 [ANA_INIT] flow start
4996 12:12:13.292280 [ANA_INIT] PLL >>>>>>>>
4997 12:12:13.292839 [ANA_INIT] PLL <<<<<<<<
4998 12:12:13.295948 [ANA_INIT] MIDPI >>>>>>>>
4999 12:12:13.298339 [ANA_INIT] MIDPI <<<<<<<<
5000 12:12:13.298807 [ANA_INIT] DLL >>>>>>>>
5001 12:12:13.301717 [ANA_INIT] flow end
5002 12:12:13.304894 ============ LP4 DIFF to SE enter ============
5003 12:12:13.308376 ============ LP4 DIFF to SE exit ============
5004 12:12:13.312339 [ANA_INIT] <<<<<<<<<<<<<
5005 12:12:13.315595 [Flow] Enable top DCM control >>>>>
5006 12:12:13.318578 [Flow] Enable top DCM control <<<<<
5007 12:12:13.321463 Enable DLL master slave shuffle
5008 12:12:13.328379 ==============================================================
5009 12:12:13.328946 Gating Mode config
5010 12:12:13.334781 ==============================================================
5011 12:12:13.338410 Config description:
5012 12:12:13.344535 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5013 12:12:13.354387 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5014 12:12:13.357653 SELPH_MODE 0: By rank 1: By Phase
5015 12:12:13.365296 ==============================================================
5016 12:12:13.367508 GAT_TRACK_EN = 1
5017 12:12:13.371075 RX_GATING_MODE = 2
5018 12:12:13.371642 RX_GATING_TRACK_MODE = 2
5019 12:12:13.374495 SELPH_MODE = 1
5020 12:12:13.377942 PICG_EARLY_EN = 1
5021 12:12:13.381440 VALID_LAT_VALUE = 1
5022 12:12:13.387542 ==============================================================
5023 12:12:13.390731 Enter into Gating configuration >>>>
5024 12:12:13.394253 Exit from Gating configuration <<<<
5025 12:12:13.397154 Enter into DVFS_PRE_config >>>>>
5026 12:12:13.407321 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5027 12:12:13.410120 Exit from DVFS_PRE_config <<<<<
5028 12:12:13.414745 Enter into PICG configuration >>>>
5029 12:12:13.418423 Exit from PICG configuration <<<<
5030 12:12:13.420400 [RX_INPUT] configuration >>>>>
5031 12:12:13.424035 [RX_INPUT] configuration <<<<<
5032 12:12:13.427283 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5033 12:12:13.433702 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5034 12:12:13.439856 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5035 12:12:13.446310 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5036 12:12:13.453336 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5037 12:12:13.456120 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5038 12:12:13.463436 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5039 12:12:13.466200 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5040 12:12:13.469528 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5041 12:12:13.472742 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5042 12:12:13.479024 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5043 12:12:13.483490 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5044 12:12:13.486599 ===================================
5045 12:12:13.489143 LPDDR4 DRAM CONFIGURATION
5046 12:12:13.492402 ===================================
5047 12:12:13.492870 EX_ROW_EN[0] = 0x0
5048 12:12:13.496122 EX_ROW_EN[1] = 0x0
5049 12:12:13.496580 LP4Y_EN = 0x0
5050 12:12:13.499421 WORK_FSP = 0x0
5051 12:12:13.499932 WL = 0x3
5052 12:12:13.502891 RL = 0x3
5053 12:12:13.505989 BL = 0x2
5054 12:12:13.506590 RPST = 0x0
5055 12:12:13.509676 RD_PRE = 0x0
5056 12:12:13.510150 WR_PRE = 0x1
5057 12:12:13.512487 WR_PST = 0x0
5058 12:12:13.512944 DBI_WR = 0x0
5059 12:12:13.515740 DBI_RD = 0x0
5060 12:12:13.516297 OTF = 0x1
5061 12:12:13.519232 ===================================
5062 12:12:13.522338 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5063 12:12:13.529238 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5064 12:12:13.532886 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5065 12:12:13.535225 ===================================
5066 12:12:13.538802 LPDDR4 DRAM CONFIGURATION
5067 12:12:13.542096 ===================================
5068 12:12:13.542556 EX_ROW_EN[0] = 0x10
5069 12:12:13.544962 EX_ROW_EN[1] = 0x0
5070 12:12:13.545434 LP4Y_EN = 0x0
5071 12:12:13.548564 WORK_FSP = 0x0
5072 12:12:13.551949 WL = 0x3
5073 12:12:13.552504 RL = 0x3
5074 12:12:13.555031 BL = 0x2
5075 12:12:13.555590 RPST = 0x0
5076 12:12:13.558494 RD_PRE = 0x0
5077 12:12:13.558965 WR_PRE = 0x1
5078 12:12:13.561593 WR_PST = 0x0
5079 12:12:13.562049 DBI_WR = 0x0
5080 12:12:13.564714 DBI_RD = 0x0
5081 12:12:13.565172 OTF = 0x1
5082 12:12:13.568308 ===================================
5083 12:12:13.574759 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5084 12:12:13.579523 nWR fixed to 30
5085 12:12:13.583490 [ModeRegInit_LP4] CH0 RK0
5086 12:12:13.583995 [ModeRegInit_LP4] CH0 RK1
5087 12:12:13.586471 [ModeRegInit_LP4] CH1 RK0
5088 12:12:13.588826 [ModeRegInit_LP4] CH1 RK1
5089 12:12:13.589313 match AC timing 9
5090 12:12:13.596145 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5091 12:12:13.599575 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5092 12:12:13.602834 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5093 12:12:13.608672 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5094 12:12:13.612478 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5095 12:12:13.613046 ==
5096 12:12:13.615653 Dram Type= 6, Freq= 0, CH_0, rank 0
5097 12:12:13.618972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5098 12:12:13.619583 ==
5099 12:12:13.625291 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5100 12:12:13.631597 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5101 12:12:13.635421 [CA 0] Center 37 (7~68) winsize 62
5102 12:12:13.638646 [CA 1] Center 37 (7~68) winsize 62
5103 12:12:13.641560 [CA 2] Center 34 (4~65) winsize 62
5104 12:12:13.645015 [CA 3] Center 35 (5~65) winsize 61
5105 12:12:13.648335 [CA 4] Center 33 (3~64) winsize 62
5106 12:12:13.651606 [CA 5] Center 33 (4~63) winsize 60
5107 12:12:13.652222
5108 12:12:13.655111 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5109 12:12:13.655785
5110 12:12:13.658673 [CATrainingPosCal] consider 1 rank data
5111 12:12:13.661567 u2DelayCellTimex100 = 270/100 ps
5112 12:12:13.664355 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5113 12:12:13.668722 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5114 12:12:13.671424 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5115 12:12:13.678108 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5116 12:12:13.681805 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5117 12:12:13.684310 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5118 12:12:13.684776
5119 12:12:13.687786 CA PerBit enable=1, Macro0, CA PI delay=33
5120 12:12:13.688347
5121 12:12:13.691283 [CBTSetCACLKResult] CA Dly = 33
5122 12:12:13.691800 CS Dly: 7 (0~38)
5123 12:12:13.692178 ==
5124 12:12:13.694142 Dram Type= 6, Freq= 0, CH_0, rank 1
5125 12:12:13.701222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5126 12:12:13.701810 ==
5127 12:12:13.704128 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5128 12:12:13.710905 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5129 12:12:13.714278 [CA 0] Center 37 (7~68) winsize 62
5130 12:12:13.717410 [CA 1] Center 37 (7~68) winsize 62
5131 12:12:13.720540 [CA 2] Center 34 (4~65) winsize 62
5132 12:12:13.724481 [CA 3] Center 34 (4~65) winsize 62
5133 12:12:13.727823 [CA 4] Center 33 (3~64) winsize 62
5134 12:12:13.730560 [CA 5] Center 32 (2~63) winsize 62
5135 12:12:13.731026
5136 12:12:13.733726 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5137 12:12:13.734331
5138 12:12:13.736920 [CATrainingPosCal] consider 2 rank data
5139 12:12:13.740820 u2DelayCellTimex100 = 270/100 ps
5140 12:12:13.744258 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5141 12:12:13.750776 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5142 12:12:13.754980 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5143 12:12:13.757022 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5144 12:12:13.760101 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5145 12:12:13.764578 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5146 12:12:13.765147
5147 12:12:13.766647 CA PerBit enable=1, Macro0, CA PI delay=33
5148 12:12:13.767113
5149 12:12:13.770674 [CBTSetCACLKResult] CA Dly = 33
5150 12:12:13.773788 CS Dly: 7 (0~39)
5151 12:12:13.774356
5152 12:12:13.776613 ----->DramcWriteLeveling(PI) begin...
5153 12:12:13.777084 ==
5154 12:12:13.780347 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 12:12:13.783532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 12:12:13.784055 ==
5157 12:12:13.786712 Write leveling (Byte 0): 32 => 32
5158 12:12:13.790540 Write leveling (Byte 1): 31 => 31
5159 12:12:13.793358 DramcWriteLeveling(PI) end<-----
5160 12:12:13.793837
5161 12:12:13.794208 ==
5162 12:12:13.796628 Dram Type= 6, Freq= 0, CH_0, rank 0
5163 12:12:13.800077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5164 12:12:13.800652 ==
5165 12:12:13.804390 [Gating] SW mode calibration
5166 12:12:13.810228 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5167 12:12:13.816247 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5168 12:12:13.819533 0 14 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5169 12:12:13.822954 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5170 12:12:13.829927 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 12:12:13.832514 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 12:12:13.836464 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 12:12:13.842966 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 12:12:13.846425 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 12:12:13.849269 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
5176 12:12:13.856255 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (1 0)
5177 12:12:13.859562 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 12:12:13.862778 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 12:12:13.869091 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 12:12:13.872462 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 12:12:13.875921 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 12:12:13.883260 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 12:12:13.885865 0 15 28 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
5184 12:12:13.888645 1 0 0 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
5185 12:12:13.895304 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5186 12:12:13.898843 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 12:12:13.902538 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 12:12:13.908740 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 12:12:13.911746 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 12:12:13.915298 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 12:12:13.921735 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5192 12:12:13.925421 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5193 12:12:13.928975 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 12:12:13.935214 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 12:12:13.938920 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 12:12:13.941713 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 12:12:13.948193 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 12:12:13.951545 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 12:12:13.955117 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 12:12:13.961472 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 12:12:13.964935 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 12:12:13.968699 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 12:12:13.974622 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 12:12:13.977830 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 12:12:13.981469 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 12:12:13.988113 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 12:12:13.991371 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5208 12:12:13.994841 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5209 12:12:13.997500 Total UI for P1: 0, mck2ui 16
5210 12:12:14.000895 best dqsien dly found for B0: ( 1, 2, 28)
5211 12:12:14.007315 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5212 12:12:14.010636 Total UI for P1: 0, mck2ui 16
5213 12:12:14.014518 best dqsien dly found for B1: ( 1, 2, 30)
5214 12:12:14.018055 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5215 12:12:14.020843 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5216 12:12:14.021404
5217 12:12:14.023901 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5218 12:12:14.027413 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5219 12:12:14.030647 [Gating] SW calibration Done
5220 12:12:14.031111 ==
5221 12:12:14.034418 Dram Type= 6, Freq= 0, CH_0, rank 0
5222 12:12:14.037234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5223 12:12:14.037769 ==
5224 12:12:14.040785 RX Vref Scan: 0
5225 12:12:14.041436
5226 12:12:14.044236 RX Vref 0 -> 0, step: 1
5227 12:12:14.044660
5228 12:12:14.044994 RX Delay -80 -> 252, step: 8
5229 12:12:14.051028 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5230 12:12:14.054175 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5231 12:12:14.057365 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5232 12:12:14.060200 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5233 12:12:14.063379 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5234 12:12:14.067483 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5235 12:12:14.073211 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5236 12:12:14.076712 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5237 12:12:14.080258 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5238 12:12:14.083810 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5239 12:12:14.087035 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5240 12:12:14.093194 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5241 12:12:14.096998 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5242 12:12:14.100003 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5243 12:12:14.103338 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5244 12:12:14.106443 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5245 12:12:14.109770 ==
5246 12:12:14.110191 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 12:12:14.116509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 12:12:14.116968 ==
5249 12:12:14.117350 DQS Delay:
5250 12:12:14.120232 DQS0 = 0, DQS1 = 0
5251 12:12:14.120654 DQM Delay:
5252 12:12:14.123294 DQM0 = 97, DQM1 = 86
5253 12:12:14.123751 DQ Delay:
5254 12:12:14.126305 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5255 12:12:14.130144 DQ4 =99, DQ5 =91, DQ6 =107, DQ7 =107
5256 12:12:14.132596 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5257 12:12:14.136341 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5258 12:12:14.136909
5259 12:12:14.137256
5260 12:12:14.137572 ==
5261 12:12:14.139892 Dram Type= 6, Freq= 0, CH_0, rank 0
5262 12:12:14.142568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5263 12:12:14.142992 ==
5264 12:12:14.143329
5265 12:12:14.146430
5266 12:12:14.146850 TX Vref Scan disable
5267 12:12:14.148939 == TX Byte 0 ==
5268 12:12:14.152443 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5269 12:12:14.155778 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5270 12:12:14.159016 == TX Byte 1 ==
5271 12:12:14.162621 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5272 12:12:14.166452 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5273 12:12:14.166949 ==
5274 12:12:14.169053 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 12:12:14.175348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 12:12:14.175872 ==
5277 12:12:14.176242
5278 12:12:14.176557
5279 12:12:14.176854 TX Vref Scan disable
5280 12:12:14.179475 == TX Byte 0 ==
5281 12:12:14.183502 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5282 12:12:14.190186 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5283 12:12:14.190705 == TX Byte 1 ==
5284 12:12:14.193232 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5285 12:12:14.200046 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5286 12:12:14.200595
5287 12:12:14.200972 [DATLAT]
5288 12:12:14.201322 Freq=933, CH0 RK0
5289 12:12:14.201658
5290 12:12:14.202766 DATLAT Default: 0xd
5291 12:12:14.203229 0, 0xFFFF, sum = 0
5292 12:12:14.206526 1, 0xFFFF, sum = 0
5293 12:12:14.209556 2, 0xFFFF, sum = 0
5294 12:12:14.210187 3, 0xFFFF, sum = 0
5295 12:12:14.213185 4, 0xFFFF, sum = 0
5296 12:12:14.213648 5, 0xFFFF, sum = 0
5297 12:12:14.216017 6, 0xFFFF, sum = 0
5298 12:12:14.216481 7, 0xFFFF, sum = 0
5299 12:12:14.219665 8, 0xFFFF, sum = 0
5300 12:12:14.220320 9, 0xFFFF, sum = 0
5301 12:12:14.222825 10, 0x0, sum = 1
5302 12:12:14.223394 11, 0x0, sum = 2
5303 12:12:14.225663 12, 0x0, sum = 3
5304 12:12:14.226136 13, 0x0, sum = 4
5305 12:12:14.229017 best_step = 11
5306 12:12:14.229475
5307 12:12:14.229845 ==
5308 12:12:14.232310 Dram Type= 6, Freq= 0, CH_0, rank 0
5309 12:12:14.235561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5310 12:12:14.236078 ==
5311 12:12:14.236452 RX Vref Scan: 1
5312 12:12:14.239462
5313 12:12:14.239923 RX Vref 0 -> 0, step: 1
5314 12:12:14.240258
5315 12:12:14.242781 RX Delay -69 -> 252, step: 4
5316 12:12:14.243197
5317 12:12:14.245922 Set Vref, RX VrefLevel [Byte0]: 60
5318 12:12:14.248947 [Byte1]: 58
5319 12:12:14.252625
5320 12:12:14.253042 Final RX Vref Byte 0 = 60 to rank0
5321 12:12:14.255918 Final RX Vref Byte 1 = 58 to rank0
5322 12:12:14.259195 Final RX Vref Byte 0 = 60 to rank1
5323 12:12:14.262394 Final RX Vref Byte 1 = 58 to rank1==
5324 12:12:14.265592 Dram Type= 6, Freq= 0, CH_0, rank 0
5325 12:12:14.272466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 12:12:14.273218 ==
5327 12:12:14.273600 DQS Delay:
5328 12:12:14.275695 DQS0 = 0, DQS1 = 0
5329 12:12:14.276216 DQM Delay:
5330 12:12:14.276555 DQM0 = 98, DQM1 = 89
5331 12:12:14.279048 DQ Delay:
5332 12:12:14.282354 DQ0 =96, DQ1 =100, DQ2 =94, DQ3 =94
5333 12:12:14.285880 DQ4 =98, DQ5 =90, DQ6 =106, DQ7 =106
5334 12:12:14.288779 DQ8 =82, DQ9 =78, DQ10 =88, DQ11 =84
5335 12:12:14.292174 DQ12 =94, DQ13 =90, DQ14 =100, DQ15 =96
5336 12:12:14.292611
5337 12:12:14.292945
5338 12:12:14.298637 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5339 12:12:14.302702 CH0 RK0: MR19=505, MR18=2F15
5340 12:12:14.308386 CH0_RK0: MR19=0x505, MR18=0x2F15, DQSOSC=407, MR23=63, INC=65, DEC=43
5341 12:12:14.308922
5342 12:12:14.311642 ----->DramcWriteLeveling(PI) begin...
5343 12:12:14.312206 ==
5344 12:12:14.315450 Dram Type= 6, Freq= 0, CH_0, rank 1
5345 12:12:14.318565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 12:12:14.319098 ==
5347 12:12:14.321754 Write leveling (Byte 0): 35 => 35
5348 12:12:14.324968 Write leveling (Byte 1): 31 => 31
5349 12:12:14.328172 DramcWriteLeveling(PI) end<-----
5350 12:12:14.328596
5351 12:12:14.328934 ==
5352 12:12:14.331650 Dram Type= 6, Freq= 0, CH_0, rank 1
5353 12:12:14.338408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5354 12:12:14.338928 ==
5355 12:12:14.339267 [Gating] SW mode calibration
5356 12:12:14.348018 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5357 12:12:14.351524 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5358 12:12:14.354813 0 14 0 | B1->B0 | 2828 3232 | 0 0 | (0 0) (0 0)
5359 12:12:14.361384 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 12:12:14.364327 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 12:12:14.367821 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 12:12:14.374444 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 12:12:14.378436 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 12:12:14.381148 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5365 12:12:14.387890 0 14 28 | B1->B0 | 3232 2e2e | 0 1 | (0 0) (1 1)
5366 12:12:14.391445 0 15 0 | B1->B0 | 2d2d 2727 | 0 0 | (0 0) (0 0)
5367 12:12:14.394383 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 12:12:14.400893 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 12:12:14.404319 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 12:12:14.407710 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 12:12:14.414404 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 12:12:14.417755 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 12:12:14.420949 0 15 28 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)
5374 12:12:14.427215 1 0 0 | B1->B0 | 4343 4545 | 0 0 | (0 0) (0 0)
5375 12:12:14.430631 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 12:12:14.434351 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 12:12:14.440687 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 12:12:14.443529 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 12:12:14.447434 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 12:12:14.454168 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 12:12:14.457883 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 12:12:14.459852 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5383 12:12:14.467142 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 12:12:14.469893 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 12:12:14.473145 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 12:12:14.479838 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 12:12:14.483168 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 12:12:14.486537 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 12:12:14.493110 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 12:12:14.496134 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 12:12:14.499539 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 12:12:14.507547 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 12:12:14.510364 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 12:12:14.515837 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 12:12:14.519499 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 12:12:14.523479 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 12:12:14.526002 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5398 12:12:14.532507 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5399 12:12:14.536362 Total UI for P1: 0, mck2ui 16
5400 12:12:14.539512 best dqsien dly found for B0: ( 1, 2, 28)
5401 12:12:14.542946 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 12:12:14.546118 Total UI for P1: 0, mck2ui 16
5403 12:12:14.549219 best dqsien dly found for B1: ( 1, 3, 0)
5404 12:12:14.552974 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5405 12:12:14.555622 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5406 12:12:14.556215
5407 12:12:14.558969 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5408 12:12:14.565413 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5409 12:12:14.565959 [Gating] SW calibration Done
5410 12:12:14.566334 ==
5411 12:12:14.568564 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 12:12:14.575027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 12:12:14.575498 ==
5414 12:12:14.575918 RX Vref Scan: 0
5415 12:12:14.576270
5416 12:12:14.579061 RX Vref 0 -> 0, step: 1
5417 12:12:14.579622
5418 12:12:14.582301 RX Delay -80 -> 252, step: 8
5419 12:12:14.585019 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5420 12:12:14.588520 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5421 12:12:14.592081 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5422 12:12:14.595140 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5423 12:12:14.601910 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5424 12:12:14.605098 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5425 12:12:14.608915 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5426 12:12:14.611554 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5427 12:12:14.615173 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5428 12:12:14.621691 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5429 12:12:14.625315 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5430 12:12:14.628156 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5431 12:12:14.631649 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5432 12:12:14.635433 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5433 12:12:14.638158 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5434 12:12:14.644695 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5435 12:12:14.645181 ==
5436 12:12:14.648152 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 12:12:14.651982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 12:12:14.652548 ==
5439 12:12:14.652921 DQS Delay:
5440 12:12:14.654995 DQS0 = 0, DQS1 = 0
5441 12:12:14.655567 DQM Delay:
5442 12:12:14.657670 DQM0 = 97, DQM1 = 89
5443 12:12:14.658129 DQ Delay:
5444 12:12:14.661587 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5445 12:12:14.664796 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5446 12:12:14.667787 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5447 12:12:14.671333 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5448 12:12:14.671943
5449 12:12:14.672319
5450 12:12:14.672660 ==
5451 12:12:14.674830 Dram Type= 6, Freq= 0, CH_0, rank 1
5452 12:12:14.681169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5453 12:12:14.681735 ==
5454 12:12:14.682102
5455 12:12:14.682437
5456 12:12:14.682758 TX Vref Scan disable
5457 12:12:14.684797 == TX Byte 0 ==
5458 12:12:14.688324 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5459 12:12:14.693933 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5460 12:12:14.694514 == TX Byte 1 ==
5461 12:12:14.697670 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5462 12:12:14.704985 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5463 12:12:14.705496 ==
5464 12:12:14.708135 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 12:12:14.711179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 12:12:14.711598 ==
5467 12:12:14.711986
5468 12:12:14.712299
5469 12:12:14.714001 TX Vref Scan disable
5470 12:12:14.714413 == TX Byte 0 ==
5471 12:12:14.720236 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5472 12:12:14.724102 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5473 12:12:14.727352 == TX Byte 1 ==
5474 12:12:14.730703 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5475 12:12:14.734697 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5476 12:12:14.735215
5477 12:12:14.735554 [DATLAT]
5478 12:12:14.737150 Freq=933, CH0 RK1
5479 12:12:14.737571
5480 12:12:14.739926 DATLAT Default: 0xb
5481 12:12:14.740347 0, 0xFFFF, sum = 0
5482 12:12:14.743449 1, 0xFFFF, sum = 0
5483 12:12:14.743932 2, 0xFFFF, sum = 0
5484 12:12:14.747538 3, 0xFFFF, sum = 0
5485 12:12:14.748118 4, 0xFFFF, sum = 0
5486 12:12:14.750296 5, 0xFFFF, sum = 0
5487 12:12:14.750815 6, 0xFFFF, sum = 0
5488 12:12:14.753711 7, 0xFFFF, sum = 0
5489 12:12:14.754257 8, 0xFFFF, sum = 0
5490 12:12:14.757145 9, 0xFFFF, sum = 0
5491 12:12:14.757675 10, 0x0, sum = 1
5492 12:12:14.760300 11, 0x0, sum = 2
5493 12:12:14.760773 12, 0x0, sum = 3
5494 12:12:14.764711 13, 0x0, sum = 4
5495 12:12:14.765275 best_step = 11
5496 12:12:14.765644
5497 12:12:14.765985 ==
5498 12:12:14.766742 Dram Type= 6, Freq= 0, CH_0, rank 1
5499 12:12:14.769541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5500 12:12:14.773688 ==
5501 12:12:14.774469 RX Vref Scan: 0
5502 12:12:14.774888
5503 12:12:14.776519 RX Vref 0 -> 0, step: 1
5504 12:12:14.776983
5505 12:12:14.780207 RX Delay -61 -> 252, step: 4
5506 12:12:14.783551 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5507 12:12:14.786202 iDelay=203, Bit 1, Center 98 (3 ~ 194) 192
5508 12:12:14.793001 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5509 12:12:14.796759 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5510 12:12:14.799341 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5511 12:12:14.802375 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5512 12:12:14.806465 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5513 12:12:14.809211 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5514 12:12:14.815932 iDelay=203, Bit 8, Center 82 (-9 ~ 174) 184
5515 12:12:14.819016 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5516 12:12:14.824094 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5517 12:12:14.825401 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5518 12:12:14.829050 iDelay=203, Bit 12, Center 94 (-1 ~ 190) 192
5519 12:12:14.835790 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5520 12:12:14.839288 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5521 12:12:14.842633 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5522 12:12:14.843243 ==
5523 12:12:14.845383 Dram Type= 6, Freq= 0, CH_0, rank 1
5524 12:12:14.848762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5525 12:12:14.849226 ==
5526 12:12:14.851893 DQS Delay:
5527 12:12:14.852356 DQS0 = 0, DQS1 = 0
5528 12:12:14.855489 DQM Delay:
5529 12:12:14.856108 DQM0 = 95, DQM1 = 89
5530 12:12:14.856482 DQ Delay:
5531 12:12:14.858687 DQ0 =92, DQ1 =98, DQ2 =88, DQ3 =92
5532 12:12:14.862035 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5533 12:12:14.866033 DQ8 =82, DQ9 =78, DQ10 =90, DQ11 =82
5534 12:12:14.868266 DQ12 =94, DQ13 =96, DQ14 =98, DQ15 =96
5535 12:12:14.868727
5536 12:12:14.869091
5537 12:12:14.878720 [DQSOSCAuto] RK1, (LSB)MR18= 0x25f5, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 410 ps
5538 12:12:14.882316 CH0 RK1: MR19=504, MR18=25F5
5539 12:12:14.888638 CH0_RK1: MR19=0x504, MR18=0x25F5, DQSOSC=410, MR23=63, INC=64, DEC=42
5540 12:12:14.889201 [RxdqsGatingPostProcess] freq 933
5541 12:12:14.895876 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5542 12:12:14.898597 best DQS0 dly(2T, 0.5T) = (0, 10)
5543 12:12:14.901748 best DQS1 dly(2T, 0.5T) = (0, 10)
5544 12:12:14.906233 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5545 12:12:14.909439 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5546 12:12:14.911598 best DQS0 dly(2T, 0.5T) = (0, 10)
5547 12:12:14.914580 best DQS1 dly(2T, 0.5T) = (0, 11)
5548 12:12:14.917983 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5549 12:12:14.920953 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5550 12:12:14.924626 Pre-setting of DQS Precalculation
5551 12:12:14.928201 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5552 12:12:14.928662 ==
5553 12:12:14.931283 Dram Type= 6, Freq= 0, CH_1, rank 0
5554 12:12:14.937556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5555 12:12:14.938135 ==
5556 12:12:14.942219 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5557 12:12:14.948353 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5558 12:12:14.951063 [CA 0] Center 37 (7~67) winsize 61
5559 12:12:14.954651 [CA 1] Center 37 (7~68) winsize 62
5560 12:12:14.957980 [CA 2] Center 34 (4~65) winsize 62
5561 12:12:14.961060 [CA 3] Center 33 (3~64) winsize 62
5562 12:12:14.964195 [CA 4] Center 34 (4~65) winsize 62
5563 12:12:14.967844 [CA 5] Center 33 (3~64) winsize 62
5564 12:12:14.968396
5565 12:12:14.970772 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5566 12:12:14.971330
5567 12:12:14.974061 [CATrainingPosCal] consider 1 rank data
5568 12:12:14.977275 u2DelayCellTimex100 = 270/100 ps
5569 12:12:14.980389 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5570 12:12:14.987402 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5571 12:12:14.990542 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5572 12:12:14.993547 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5573 12:12:14.996989 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5574 12:12:15.000929 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5575 12:12:15.001403
5576 12:12:15.003636 CA PerBit enable=1, Macro0, CA PI delay=33
5577 12:12:15.004154
5578 12:12:15.007034 [CBTSetCACLKResult] CA Dly = 33
5579 12:12:15.010056 CS Dly: 6 (0~37)
5580 12:12:15.010511 ==
5581 12:12:15.013292 Dram Type= 6, Freq= 0, CH_1, rank 1
5582 12:12:15.017028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 12:12:15.017592 ==
5584 12:12:15.023792 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5585 12:12:15.027261 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5586 12:12:15.031178 [CA 0] Center 36 (6~67) winsize 62
5587 12:12:15.034047 [CA 1] Center 37 (7~68) winsize 62
5588 12:12:15.037561 [CA 2] Center 34 (4~65) winsize 62
5589 12:12:15.041426 [CA 3] Center 34 (3~65) winsize 63
5590 12:12:15.043975 [CA 4] Center 34 (3~65) winsize 63
5591 12:12:15.047414 [CA 5] Center 33 (3~64) winsize 62
5592 12:12:15.048076
5593 12:12:15.051148 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5594 12:12:15.051758
5595 12:12:15.053961 [CATrainingPosCal] consider 2 rank data
5596 12:12:15.057243 u2DelayCellTimex100 = 270/100 ps
5597 12:12:15.060801 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5598 12:12:15.067378 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5599 12:12:15.071368 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5600 12:12:15.073627 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5601 12:12:15.077089 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5602 12:12:15.080202 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5603 12:12:15.080764
5604 12:12:15.083494 CA PerBit enable=1, Macro0, CA PI delay=33
5605 12:12:15.084101
5606 12:12:15.086638 [CBTSetCACLKResult] CA Dly = 33
5607 12:12:15.090664 CS Dly: 7 (0~39)
5608 12:12:15.091221
5609 12:12:15.093595 ----->DramcWriteLeveling(PI) begin...
5610 12:12:15.094165 ==
5611 12:12:15.096382 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 12:12:15.100133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 12:12:15.100696 ==
5614 12:12:15.102816 Write leveling (Byte 0): 24 => 24
5615 12:12:15.106311 Write leveling (Byte 1): 26 => 26
5616 12:12:15.109574 DramcWriteLeveling(PI) end<-----
5617 12:12:15.110218
5618 12:12:15.110664 ==
5619 12:12:15.113629 Dram Type= 6, Freq= 0, CH_1, rank 0
5620 12:12:15.116970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5621 12:12:15.117439 ==
5622 12:12:15.119221 [Gating] SW mode calibration
5623 12:12:15.126223 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5624 12:12:15.133042 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5625 12:12:15.136109 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 12:12:15.143111 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 12:12:15.145868 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 12:12:15.149363 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 12:12:15.152546 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 12:12:15.159398 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5631 12:12:15.163260 0 14 24 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 0)
5632 12:12:15.165573 0 14 28 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
5633 12:12:15.172517 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5634 12:12:15.175778 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 12:12:15.178738 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 12:12:15.185551 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 12:12:15.188740 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 12:12:15.192008 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 12:12:15.198621 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5640 12:12:15.202227 0 15 28 | B1->B0 | 3736 3a3a | 1 0 | (0 0) (1 1)
5641 12:12:15.205687 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 12:12:15.212425 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 12:12:15.214968 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 12:12:15.218854 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 12:12:15.224757 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 12:12:15.229004 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 12:12:15.232207 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5648 12:12:15.238385 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5649 12:12:15.241644 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 12:12:15.245104 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 12:12:15.252134 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 12:12:15.255080 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 12:12:15.258687 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 12:12:15.264557 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 12:12:15.268473 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 12:12:15.271370 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 12:12:15.278385 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 12:12:15.281839 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 12:12:15.284471 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 12:12:15.291518 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 12:12:15.295113 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 12:12:15.297987 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 12:12:15.303991 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5664 12:12:15.307834 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 12:12:15.311080 Total UI for P1: 0, mck2ui 16
5666 12:12:15.314442 best dqsien dly found for B0: ( 1, 2, 24)
5667 12:12:15.317385 Total UI for P1: 0, mck2ui 16
5668 12:12:15.321671 best dqsien dly found for B1: ( 1, 2, 24)
5669 12:12:15.324096 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5670 12:12:15.327299 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5671 12:12:15.327908
5672 12:12:15.331041 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5673 12:12:15.336955 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5674 12:12:15.337656 [Gating] SW calibration Done
5675 12:12:15.338193 ==
5676 12:12:15.340567 Dram Type= 6, Freq= 0, CH_1, rank 0
5677 12:12:15.347335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5678 12:12:15.347982 ==
5679 12:12:15.348365 RX Vref Scan: 0
5680 12:12:15.348711
5681 12:12:15.350289 RX Vref 0 -> 0, step: 1
5682 12:12:15.350740
5683 12:12:15.354224 RX Delay -80 -> 252, step: 8
5684 12:12:15.357436 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5685 12:12:15.362124 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5686 12:12:15.364427 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5687 12:12:15.366940 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5688 12:12:15.373416 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5689 12:12:15.376654 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5690 12:12:15.379851 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5691 12:12:15.383514 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5692 12:12:15.386814 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5693 12:12:15.393444 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5694 12:12:15.396319 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5695 12:12:15.400246 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5696 12:12:15.402901 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5697 12:12:15.406991 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5698 12:12:15.413375 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5699 12:12:15.416949 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5700 12:12:15.417510 ==
5701 12:12:15.420295 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 12:12:15.423247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 12:12:15.423865 ==
5704 12:12:15.424247 DQS Delay:
5705 12:12:15.426175 DQS0 = 0, DQS1 = 0
5706 12:12:15.426735 DQM Delay:
5707 12:12:15.429735 DQM0 = 102, DQM1 = 91
5708 12:12:15.430209 DQ Delay:
5709 12:12:15.433070 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =99
5710 12:12:15.436205 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5711 12:12:15.439354 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5712 12:12:15.442909 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5713 12:12:15.443377
5714 12:12:15.443825
5715 12:12:15.444188 ==
5716 12:12:15.446112 Dram Type= 6, Freq= 0, CH_1, rank 0
5717 12:12:15.452392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5718 12:12:15.452856 ==
5719 12:12:15.453219
5720 12:12:15.453558
5721 12:12:15.453897 TX Vref Scan disable
5722 12:12:15.456729 == TX Byte 0 ==
5723 12:12:15.459237 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5724 12:12:15.466093 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5725 12:12:15.466666 == TX Byte 1 ==
5726 12:12:15.469348 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5727 12:12:15.475930 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5728 12:12:15.476601 ==
5729 12:12:15.479092 Dram Type= 6, Freq= 0, CH_1, rank 0
5730 12:12:15.482784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 12:12:15.483245 ==
5732 12:12:15.483614
5733 12:12:15.483996
5734 12:12:15.486640 TX Vref Scan disable
5735 12:12:15.487360 == TX Byte 0 ==
5736 12:12:15.491955 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5737 12:12:15.495601 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5738 12:12:15.498890 == TX Byte 1 ==
5739 12:12:15.502145 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5740 12:12:15.505912 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5741 12:12:15.506475
5742 12:12:15.506842 [DATLAT]
5743 12:12:15.508662 Freq=933, CH1 RK0
5744 12:12:15.509121
5745 12:12:15.512157 DATLAT Default: 0xd
5746 12:12:15.512708 0, 0xFFFF, sum = 0
5747 12:12:15.515186 1, 0xFFFF, sum = 0
5748 12:12:15.515651 2, 0xFFFF, sum = 0
5749 12:12:15.518765 3, 0xFFFF, sum = 0
5750 12:12:15.519331 4, 0xFFFF, sum = 0
5751 12:12:15.522306 5, 0xFFFF, sum = 0
5752 12:12:15.522873 6, 0xFFFF, sum = 0
5753 12:12:15.525389 7, 0xFFFF, sum = 0
5754 12:12:15.525956 8, 0xFFFF, sum = 0
5755 12:12:15.528857 9, 0xFFFF, sum = 0
5756 12:12:15.529343 10, 0x0, sum = 1
5757 12:12:15.532539 11, 0x0, sum = 2
5758 12:12:15.533105 12, 0x0, sum = 3
5759 12:12:15.535520 13, 0x0, sum = 4
5760 12:12:15.536137 best_step = 11
5761 12:12:15.536509
5762 12:12:15.536848 ==
5763 12:12:15.538610 Dram Type= 6, Freq= 0, CH_1, rank 0
5764 12:12:15.542179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 12:12:15.545427 ==
5766 12:12:15.545886 RX Vref Scan: 1
5767 12:12:15.546249
5768 12:12:15.548214 RX Vref 0 -> 0, step: 1
5769 12:12:15.548831
5770 12:12:15.552358 RX Delay -69 -> 252, step: 4
5771 12:12:15.552814
5772 12:12:15.555189 Set Vref, RX VrefLevel [Byte0]: 50
5773 12:12:15.558555 [Byte1]: 60
5774 12:12:15.559016
5775 12:12:15.561588 Final RX Vref Byte 0 = 50 to rank0
5776 12:12:15.564717 Final RX Vref Byte 1 = 60 to rank0
5777 12:12:15.568581 Final RX Vref Byte 0 = 50 to rank1
5778 12:12:15.571725 Final RX Vref Byte 1 = 60 to rank1==
5779 12:12:15.575312 Dram Type= 6, Freq= 0, CH_1, rank 0
5780 12:12:15.578129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 12:12:15.578595 ==
5782 12:12:15.581124 DQS Delay:
5783 12:12:15.581615 DQS0 = 0, DQS1 = 0
5784 12:12:15.581986 DQM Delay:
5785 12:12:15.584912 DQM0 = 101, DQM1 = 95
5786 12:12:15.585378 DQ Delay:
5787 12:12:15.587565 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5788 12:12:15.591235 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =96
5789 12:12:15.594697 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =84
5790 12:12:15.597581 DQ12 =102, DQ13 =102, DQ14 =104, DQ15 =104
5791 12:12:15.598043
5792 12:12:15.602316
5793 12:12:15.608426 [DQSOSCAuto] RK0, (LSB)MR18= 0x1909, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5794 12:12:15.611071 CH1 RK0: MR19=505, MR18=1909
5795 12:12:15.617808 CH1_RK0: MR19=0x505, MR18=0x1909, DQSOSC=413, MR23=63, INC=63, DEC=42
5796 12:12:15.618368
5797 12:12:15.621706 ----->DramcWriteLeveling(PI) begin...
5798 12:12:15.622293 ==
5799 12:12:15.623951 Dram Type= 6, Freq= 0, CH_1, rank 1
5800 12:12:15.627564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 12:12:15.628160 ==
5802 12:12:15.630808 Write leveling (Byte 0): 26 => 26
5803 12:12:15.634823 Write leveling (Byte 1): 26 => 26
5804 12:12:15.636865 DramcWriteLeveling(PI) end<-----
5805 12:12:15.637379
5806 12:12:15.637749 ==
5807 12:12:15.640931 Dram Type= 6, Freq= 0, CH_1, rank 1
5808 12:12:15.643722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5809 12:12:15.644301 ==
5810 12:12:15.646853 [Gating] SW mode calibration
5811 12:12:15.654045 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5812 12:12:15.660356 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5813 12:12:15.664141 0 14 0 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5814 12:12:15.670180 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 12:12:15.673805 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 12:12:15.676330 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 12:12:15.683645 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 12:12:15.687662 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5819 12:12:15.689802 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5820 12:12:15.696656 0 14 28 | B1->B0 | 2828 3131 | 0 0 | (0 0) (0 1)
5821 12:12:15.700299 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5822 12:12:15.703144 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 12:12:15.709606 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 12:12:15.713103 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 12:12:15.716358 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 12:12:15.723341 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 12:12:15.726335 0 15 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5828 12:12:15.730538 0 15 28 | B1->B0 | 3939 2d2d | 1 0 | (0 0) (1 1)
5829 12:12:15.736004 1 0 0 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
5830 12:12:15.738896 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 12:12:15.743355 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 12:12:15.748811 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 12:12:15.752040 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 12:12:15.756129 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 12:12:15.762926 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5836 12:12:15.765862 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5837 12:12:15.769374 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5838 12:12:15.775488 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 12:12:15.779600 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 12:12:15.782615 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 12:12:15.788805 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 12:12:15.792210 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 12:12:15.795207 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 12:12:15.802633 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 12:12:15.804777 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 12:12:15.808375 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 12:12:15.815328 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 12:12:15.819084 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 12:12:15.821971 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 12:12:15.828141 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 12:12:15.831272 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 12:12:15.835187 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5853 12:12:15.841402 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 12:12:15.841972 Total UI for P1: 0, mck2ui 16
5855 12:12:15.847849 best dqsien dly found for B0: ( 1, 2, 30)
5856 12:12:15.848417 Total UI for P1: 0, mck2ui 16
5857 12:12:15.854253 best dqsien dly found for B1: ( 1, 2, 28)
5858 12:12:15.858277 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5859 12:12:15.860857 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5860 12:12:15.861325
5861 12:12:15.864276 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5862 12:12:15.867453 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5863 12:12:15.870800 [Gating] SW calibration Done
5864 12:12:15.871359 ==
5865 12:12:15.874118 Dram Type= 6, Freq= 0, CH_1, rank 1
5866 12:12:15.877097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5867 12:12:15.877563 ==
5868 12:12:15.881296 RX Vref Scan: 0
5869 12:12:15.881772
5870 12:12:15.882139 RX Vref 0 -> 0, step: 1
5871 12:12:15.882486
5872 12:12:15.884290 RX Delay -80 -> 252, step: 8
5873 12:12:15.890789 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5874 12:12:15.894072 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5875 12:12:15.897491 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5876 12:12:15.900530 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5877 12:12:15.903954 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5878 12:12:15.907947 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5879 12:12:15.913738 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5880 12:12:15.916862 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5881 12:12:15.920989 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5882 12:12:15.924146 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5883 12:12:15.927085 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5884 12:12:15.933691 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5885 12:12:15.936635 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5886 12:12:15.939996 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5887 12:12:15.943495 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5888 12:12:15.947593 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5889 12:12:15.948204 ==
5890 12:12:15.950087 Dram Type= 6, Freq= 0, CH_1, rank 1
5891 12:12:15.957627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5892 12:12:15.958196 ==
5893 12:12:15.958573 DQS Delay:
5894 12:12:15.960053 DQS0 = 0, DQS1 = 0
5895 12:12:15.960516 DQM Delay:
5896 12:12:15.963324 DQM0 = 101, DQM1 = 91
5897 12:12:15.963933 DQ Delay:
5898 12:12:15.966179 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =103
5899 12:12:15.969866 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =95
5900 12:12:15.973297 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5901 12:12:15.976191 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =99
5902 12:12:15.976656
5903 12:12:15.977028
5904 12:12:15.977368 ==
5905 12:12:15.981079 Dram Type= 6, Freq= 0, CH_1, rank 1
5906 12:12:15.982548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5907 12:12:15.983016 ==
5908 12:12:15.985655
5909 12:12:15.986057
5910 12:12:15.986403 TX Vref Scan disable
5911 12:12:15.989183 == TX Byte 0 ==
5912 12:12:15.992387 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5913 12:12:15.995719 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5914 12:12:15.999623 == TX Byte 1 ==
5915 12:12:16.002713 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5916 12:12:16.005698 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5917 12:12:16.009136 ==
5918 12:12:16.012669 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 12:12:16.015287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 12:12:16.015741 ==
5921 12:12:16.016131
5922 12:12:16.016475
5923 12:12:16.018951 TX Vref Scan disable
5924 12:12:16.019509 == TX Byte 0 ==
5925 12:12:16.025524 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5926 12:12:16.028839 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5927 12:12:16.029307 == TX Byte 1 ==
5928 12:12:16.035286 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5929 12:12:16.038669 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5930 12:12:16.039227
5931 12:12:16.039596 [DATLAT]
5932 12:12:16.041755 Freq=933, CH1 RK1
5933 12:12:16.042328
5934 12:12:16.042696 DATLAT Default: 0xb
5935 12:12:16.044938 0, 0xFFFF, sum = 0
5936 12:12:16.045428 1, 0xFFFF, sum = 0
5937 12:12:16.048919 2, 0xFFFF, sum = 0
5938 12:12:16.049386 3, 0xFFFF, sum = 0
5939 12:12:16.051607 4, 0xFFFF, sum = 0
5940 12:12:16.052171 5, 0xFFFF, sum = 0
5941 12:12:16.055398 6, 0xFFFF, sum = 0
5942 12:12:16.058854 7, 0xFFFF, sum = 0
5943 12:12:16.059381 8, 0xFFFF, sum = 0
5944 12:12:16.061883 9, 0xFFFF, sum = 0
5945 12:12:16.062304 10, 0x0, sum = 1
5946 12:12:16.064713 11, 0x0, sum = 2
5947 12:12:16.065141 12, 0x0, sum = 3
5948 12:12:16.065479 13, 0x0, sum = 4
5949 12:12:16.068731 best_step = 11
5950 12:12:16.069294
5951 12:12:16.069632 ==
5952 12:12:16.072056 Dram Type= 6, Freq= 0, CH_1, rank 1
5953 12:12:16.075194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5954 12:12:16.075769 ==
5955 12:12:16.078150 RX Vref Scan: 0
5956 12:12:16.078677
5957 12:12:16.081323 RX Vref 0 -> 0, step: 1
5958 12:12:16.081748
5959 12:12:16.082283 RX Delay -61 -> 252, step: 4
5960 12:12:16.089284 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5961 12:12:16.092375 iDelay=207, Bit 1, Center 96 (11 ~ 182) 172
5962 12:12:16.095503 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5963 12:12:16.099307 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5964 12:12:16.102304 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
5965 12:12:16.109072 iDelay=207, Bit 5, Center 112 (27 ~ 198) 172
5966 12:12:16.112642 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
5967 12:12:16.115511 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5968 12:12:16.119092 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
5969 12:12:16.122630 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5970 12:12:16.125584 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5971 12:12:16.132458 iDelay=207, Bit 11, Center 86 (-5 ~ 178) 184
5972 12:12:16.135791 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
5973 12:12:16.138684 iDelay=207, Bit 13, Center 104 (15 ~ 194) 180
5974 12:12:16.141879 iDelay=207, Bit 14, Center 104 (15 ~ 194) 180
5975 12:12:16.149307 iDelay=207, Bit 15, Center 104 (15 ~ 194) 180
5976 12:12:16.149770 ==
5977 12:12:16.152074 Dram Type= 6, Freq= 0, CH_1, rank 1
5978 12:12:16.156644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5979 12:12:16.157326 ==
5980 12:12:16.157710 DQS Delay:
5981 12:12:16.158406 DQS0 = 0, DQS1 = 0
5982 12:12:16.158777 DQM Delay:
5983 12:12:16.161832 DQM0 = 102, DQM1 = 95
5984 12:12:16.162293 DQ Delay:
5985 12:12:16.165140 DQ0 =106, DQ1 =96, DQ2 =90, DQ3 =98
5986 12:12:16.168431 DQ4 =100, DQ5 =112, DQ6 =116, DQ7 =98
5987 12:12:16.171756 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =86
5988 12:12:16.175719 DQ12 =104, DQ13 =104, DQ14 =104, DQ15 =104
5989 12:12:16.176286
5990 12:12:16.176658
5991 12:12:16.185179 [DQSOSCAuto] RK1, (LSB)MR18= 0xa05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 418 ps
5992 12:12:16.185751 CH1 RK1: MR19=505, MR18=A05
5993 12:12:16.191728 CH1_RK1: MR19=0x505, MR18=0xA05, DQSOSC=418, MR23=63, INC=62, DEC=41
5994 12:12:16.194991 [RxdqsGatingPostProcess] freq 933
5995 12:12:16.200953 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5996 12:12:16.204402 best DQS0 dly(2T, 0.5T) = (0, 10)
5997 12:12:16.207851 best DQS1 dly(2T, 0.5T) = (0, 10)
5998 12:12:16.211460 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5999 12:12:16.214401 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6000 12:12:16.217753 best DQS0 dly(2T, 0.5T) = (0, 10)
6001 12:12:16.221140 best DQS1 dly(2T, 0.5T) = (0, 10)
6002 12:12:16.224590 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6003 12:12:16.227844 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6004 12:12:16.231231 Pre-setting of DQS Precalculation
6005 12:12:16.233923 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6006 12:12:16.240345 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6007 12:12:16.247293 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6008 12:12:16.247885
6009 12:12:16.250467
6010 12:12:16.250927 [Calibration Summary] 1866 Mbps
6011 12:12:16.253811 CH 0, Rank 0
6012 12:12:16.254538 SW Impedance : PASS
6013 12:12:16.256995 DUTY Scan : NO K
6014 12:12:16.260812 ZQ Calibration : PASS
6015 12:12:16.261389 Jitter Meter : NO K
6016 12:12:16.263551 CBT Training : PASS
6017 12:12:16.266662 Write leveling : PASS
6018 12:12:16.267122 RX DQS gating : PASS
6019 12:12:16.271044 RX DQ/DQS(RDDQC) : PASS
6020 12:12:16.273859 TX DQ/DQS : PASS
6021 12:12:16.274323 RX DATLAT : PASS
6022 12:12:16.276929 RX DQ/DQS(Engine): PASS
6023 12:12:16.279892 TX OE : NO K
6024 12:12:16.280337 All Pass.
6025 12:12:16.280670
6026 12:12:16.280979 CH 0, Rank 1
6027 12:12:16.283851 SW Impedance : PASS
6028 12:12:16.286524 DUTY Scan : NO K
6029 12:12:16.286952 ZQ Calibration : PASS
6030 12:12:16.290151 Jitter Meter : NO K
6031 12:12:16.293264 CBT Training : PASS
6032 12:12:16.293692 Write leveling : PASS
6033 12:12:16.296395 RX DQS gating : PASS
6034 12:12:16.299979 RX DQ/DQS(RDDQC) : PASS
6035 12:12:16.300405 TX DQ/DQS : PASS
6036 12:12:16.303642 RX DATLAT : PASS
6037 12:12:16.304239 RX DQ/DQS(Engine): PASS
6038 12:12:16.306650 TX OE : NO K
6039 12:12:16.307070 All Pass.
6040 12:12:16.307404
6041 12:12:16.310158 CH 1, Rank 0
6042 12:12:16.310678 SW Impedance : PASS
6043 12:12:16.313234 DUTY Scan : NO K
6044 12:12:16.316398 ZQ Calibration : PASS
6045 12:12:16.316865 Jitter Meter : NO K
6046 12:12:16.320041 CBT Training : PASS
6047 12:12:16.323373 Write leveling : PASS
6048 12:12:16.323838 RX DQS gating : PASS
6049 12:12:16.325931 RX DQ/DQS(RDDQC) : PASS
6050 12:12:16.329454 TX DQ/DQS : PASS
6051 12:12:16.329881 RX DATLAT : PASS
6052 12:12:16.332682 RX DQ/DQS(Engine): PASS
6053 12:12:16.336079 TX OE : NO K
6054 12:12:16.336618 All Pass.
6055 12:12:16.337063
6056 12:12:16.337473 CH 1, Rank 1
6057 12:12:16.339090 SW Impedance : PASS
6058 12:12:16.342921 DUTY Scan : NO K
6059 12:12:16.343454 ZQ Calibration : PASS
6060 12:12:16.346122 Jitter Meter : NO K
6061 12:12:16.349154 CBT Training : PASS
6062 12:12:16.349580 Write leveling : PASS
6063 12:12:16.353515 RX DQS gating : PASS
6064 12:12:16.356161 RX DQ/DQS(RDDQC) : PASS
6065 12:12:16.356590 TX DQ/DQS : PASS
6066 12:12:16.359243 RX DATLAT : PASS
6067 12:12:16.362168 RX DQ/DQS(Engine): PASS
6068 12:12:16.362601 TX OE : NO K
6069 12:12:16.366038 All Pass.
6070 12:12:16.366567
6071 12:12:16.367013 DramC Write-DBI off
6072 12:12:16.369290 PER_BANK_REFRESH: Hybrid Mode
6073 12:12:16.369719 TX_TRACKING: ON
6074 12:12:16.379177 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6075 12:12:16.382814 [FAST_K] Save calibration result to emmc
6076 12:12:16.386043 dramc_set_vcore_voltage set vcore to 650000
6077 12:12:16.389361 Read voltage for 400, 6
6078 12:12:16.389896 Vio18 = 0
6079 12:12:16.391935 Vcore = 650000
6080 12:12:16.392361 Vdram = 0
6081 12:12:16.392795 Vddq = 0
6082 12:12:16.396241 Vmddr = 0
6083 12:12:16.398694 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6084 12:12:16.405989 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6085 12:12:16.406518 MEM_TYPE=3, freq_sel=20
6086 12:12:16.409403 sv_algorithm_assistance_LP4_800
6087 12:12:16.412117 ============ PULL DRAM RESETB DOWN ============
6088 12:12:16.418870 ========== PULL DRAM RESETB DOWN end =========
6089 12:12:16.422223 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6090 12:12:16.425443 ===================================
6091 12:12:16.428537 LPDDR4 DRAM CONFIGURATION
6092 12:12:16.431791 ===================================
6093 12:12:16.432424 EX_ROW_EN[0] = 0x0
6094 12:12:16.435835 EX_ROW_EN[1] = 0x0
6095 12:12:16.438338 LP4Y_EN = 0x0
6096 12:12:16.438890 WORK_FSP = 0x0
6097 12:12:16.441481 WL = 0x2
6098 12:12:16.441936 RL = 0x2
6099 12:12:16.445073 BL = 0x2
6100 12:12:16.445530 RPST = 0x0
6101 12:12:16.448143 RD_PRE = 0x0
6102 12:12:16.448603 WR_PRE = 0x1
6103 12:12:16.451631 WR_PST = 0x0
6104 12:12:16.452117 DBI_WR = 0x0
6105 12:12:16.455035 DBI_RD = 0x0
6106 12:12:16.455599 OTF = 0x1
6107 12:12:16.458068 ===================================
6108 12:12:16.461428 ===================================
6109 12:12:16.464896 ANA top config
6110 12:12:16.468158 ===================================
6111 12:12:16.471206 DLL_ASYNC_EN = 0
6112 12:12:16.471664 ALL_SLAVE_EN = 1
6113 12:12:16.474929 NEW_RANK_MODE = 1
6114 12:12:16.477933 DLL_IDLE_MODE = 1
6115 12:12:16.481786 LP45_APHY_COMB_EN = 1
6116 12:12:16.482244 TX_ODT_DIS = 1
6117 12:12:16.484850 NEW_8X_MODE = 1
6118 12:12:16.488012 ===================================
6119 12:12:16.491447 ===================================
6120 12:12:16.495383 data_rate = 800
6121 12:12:16.498576 CKR = 1
6122 12:12:16.501088 DQ_P2S_RATIO = 4
6123 12:12:16.504219 ===================================
6124 12:12:16.507766 CA_P2S_RATIO = 4
6125 12:12:16.508334 DQ_CA_OPEN = 0
6126 12:12:16.511514 DQ_SEMI_OPEN = 1
6127 12:12:16.515171 CA_SEMI_OPEN = 1
6128 12:12:16.518040 CA_FULL_RATE = 0
6129 12:12:16.521322 DQ_CKDIV4_EN = 0
6130 12:12:16.525221 CA_CKDIV4_EN = 1
6131 12:12:16.525792 CA_PREDIV_EN = 0
6132 12:12:16.528215 PH8_DLY = 0
6133 12:12:16.531851 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6134 12:12:16.534306 DQ_AAMCK_DIV = 0
6135 12:12:16.537768 CA_AAMCK_DIV = 0
6136 12:12:16.540951 CA_ADMCK_DIV = 4
6137 12:12:16.541414 DQ_TRACK_CA_EN = 0
6138 12:12:16.545623 CA_PICK = 800
6139 12:12:16.547150 CA_MCKIO = 400
6140 12:12:16.550575 MCKIO_SEMI = 400
6141 12:12:16.553771 PLL_FREQ = 3016
6142 12:12:16.557573 DQ_UI_PI_RATIO = 32
6143 12:12:16.560774 CA_UI_PI_RATIO = 32
6144 12:12:16.564023 ===================================
6145 12:12:16.567478 ===================================
6146 12:12:16.568076 memory_type:LPDDR4
6147 12:12:16.570605 GP_NUM : 10
6148 12:12:16.573627 SRAM_EN : 1
6149 12:12:16.574089 MD32_EN : 0
6150 12:12:16.577091 ===================================
6151 12:12:16.580346 [ANA_INIT] >>>>>>>>>>>>>>
6152 12:12:16.583727 <<<<<< [CONFIGURE PHASE]: ANA_TX
6153 12:12:16.586666 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6154 12:12:16.590309 ===================================
6155 12:12:16.594277 data_rate = 800,PCW = 0X7400
6156 12:12:16.597863 ===================================
6157 12:12:16.600293 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6158 12:12:16.604662 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6159 12:12:16.616604 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6160 12:12:16.620093 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6161 12:12:16.623654 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6162 12:12:16.626111 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6163 12:12:16.630821 [ANA_INIT] flow start
6164 12:12:16.633647 [ANA_INIT] PLL >>>>>>>>
6165 12:12:16.634232 [ANA_INIT] PLL <<<<<<<<
6166 12:12:16.636592 [ANA_INIT] MIDPI >>>>>>>>
6167 12:12:16.639665 [ANA_INIT] MIDPI <<<<<<<<
6168 12:12:16.642584 [ANA_INIT] DLL >>>>>>>>
6169 12:12:16.643040 [ANA_INIT] flow end
6170 12:12:16.646543 ============ LP4 DIFF to SE enter ============
6171 12:12:16.653170 ============ LP4 DIFF to SE exit ============
6172 12:12:16.653632 [ANA_INIT] <<<<<<<<<<<<<
6173 12:12:16.655931 [Flow] Enable top DCM control >>>>>
6174 12:12:16.659907 [Flow] Enable top DCM control <<<<<
6175 12:12:16.663457 Enable DLL master slave shuffle
6176 12:12:16.669577 ==============================================================
6177 12:12:16.670127 Gating Mode config
6178 12:12:16.675946 ==============================================================
6179 12:12:16.679498 Config description:
6180 12:12:16.689407 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6181 12:12:16.695840 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6182 12:12:16.699057 SELPH_MODE 0: By rank 1: By Phase
6183 12:12:16.705366 ==============================================================
6184 12:12:16.709858 GAT_TRACK_EN = 0
6185 12:12:16.712174 RX_GATING_MODE = 2
6186 12:12:16.715369 RX_GATING_TRACK_MODE = 2
6187 12:12:16.715871 SELPH_MODE = 1
6188 12:12:16.718900 PICG_EARLY_EN = 1
6189 12:12:16.722052 VALID_LAT_VALUE = 1
6190 12:12:16.729078 ==============================================================
6191 12:12:16.732654 Enter into Gating configuration >>>>
6192 12:12:16.735431 Exit from Gating configuration <<<<
6193 12:12:16.739536 Enter into DVFS_PRE_config >>>>>
6194 12:12:16.748660 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6195 12:12:16.751815 Exit from DVFS_PRE_config <<<<<
6196 12:12:16.755484 Enter into PICG configuration >>>>
6197 12:12:16.758023 Exit from PICG configuration <<<<
6198 12:12:16.761981 [RX_INPUT] configuration >>>>>
6199 12:12:16.764618 [RX_INPUT] configuration <<<<<
6200 12:12:16.768065 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6201 12:12:16.775225 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6202 12:12:16.781572 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6203 12:12:16.788404 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6204 12:12:16.794829 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6205 12:12:16.800779 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6206 12:12:16.804601 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6207 12:12:16.807310 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6208 12:12:16.810901 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6209 12:12:16.817580 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6210 12:12:16.822185 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6211 12:12:16.824216 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6212 12:12:16.827349 ===================================
6213 12:12:16.831946 LPDDR4 DRAM CONFIGURATION
6214 12:12:16.834440 ===================================
6215 12:12:16.834999 EX_ROW_EN[0] = 0x0
6216 12:12:16.837658 EX_ROW_EN[1] = 0x0
6217 12:12:16.840676 LP4Y_EN = 0x0
6218 12:12:16.841235 WORK_FSP = 0x0
6219 12:12:16.844437 WL = 0x2
6220 12:12:16.844996 RL = 0x2
6221 12:12:16.847441 BL = 0x2
6222 12:12:16.847937 RPST = 0x0
6223 12:12:16.850691 RD_PRE = 0x0
6224 12:12:16.851145 WR_PRE = 0x1
6225 12:12:16.853931 WR_PST = 0x0
6226 12:12:16.854388 DBI_WR = 0x0
6227 12:12:16.857167 DBI_RD = 0x0
6228 12:12:16.857726 OTF = 0x1
6229 12:12:16.860340 ===================================
6230 12:12:16.864555 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6231 12:12:16.870677 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6232 12:12:16.873749 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6233 12:12:16.877144 ===================================
6234 12:12:16.880523 LPDDR4 DRAM CONFIGURATION
6235 12:12:16.884300 ===================================
6236 12:12:16.884860 EX_ROW_EN[0] = 0x10
6237 12:12:16.887015 EX_ROW_EN[1] = 0x0
6238 12:12:16.887469 LP4Y_EN = 0x0
6239 12:12:16.890383 WORK_FSP = 0x0
6240 12:12:16.895292 WL = 0x2
6241 12:12:16.895903 RL = 0x2
6242 12:12:16.896654 BL = 0x2
6243 12:12:16.897029 RPST = 0x0
6244 12:12:16.901003 RD_PRE = 0x0
6245 12:12:16.901569 WR_PRE = 0x1
6246 12:12:16.904236 WR_PST = 0x0
6247 12:12:16.904700 DBI_WR = 0x0
6248 12:12:16.906510 DBI_RD = 0x0
6249 12:12:16.906969 OTF = 0x1
6250 12:12:16.910334 ===================================
6251 12:12:16.916217 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6252 12:12:16.920843 nWR fixed to 30
6253 12:12:16.924045 [ModeRegInit_LP4] CH0 RK0
6254 12:12:16.924506 [ModeRegInit_LP4] CH0 RK1
6255 12:12:16.927145 [ModeRegInit_LP4] CH1 RK0
6256 12:12:16.930981 [ModeRegInit_LP4] CH1 RK1
6257 12:12:16.931548 match AC timing 19
6258 12:12:16.937963 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6259 12:12:16.940380 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6260 12:12:16.944437 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6261 12:12:16.951072 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6262 12:12:16.953427 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6263 12:12:16.953906 ==
6264 12:12:16.957616 Dram Type= 6, Freq= 0, CH_0, rank 0
6265 12:12:16.960635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 12:12:16.961102 ==
6267 12:12:16.967392 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6268 12:12:16.973628 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6269 12:12:16.976585 [CA 0] Center 36 (8~64) winsize 57
6270 12:12:16.980342 [CA 1] Center 36 (8~64) winsize 57
6271 12:12:16.983531 [CA 2] Center 36 (8~64) winsize 57
6272 12:12:16.987118 [CA 3] Center 36 (8~64) winsize 57
6273 12:12:16.990235 [CA 4] Center 36 (8~64) winsize 57
6274 12:12:16.993559 [CA 5] Center 36 (8~64) winsize 57
6275 12:12:16.994019
6276 12:12:16.996966 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6277 12:12:16.997533
6278 12:12:16.999654 [CATrainingPosCal] consider 1 rank data
6279 12:12:17.003507 u2DelayCellTimex100 = 270/100 ps
6280 12:12:17.006245 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 12:12:17.009911 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 12:12:17.013306 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 12:12:17.017468 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 12:12:17.019741 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 12:12:17.023459 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 12:12:17.023973
6287 12:12:17.029511 CA PerBit enable=1, Macro0, CA PI delay=36
6288 12:12:17.030085
6289 12:12:17.030460 [CBTSetCACLKResult] CA Dly = 36
6290 12:12:17.032788 CS Dly: 1 (0~32)
6291 12:12:17.033273 ==
6292 12:12:17.035844 Dram Type= 6, Freq= 0, CH_0, rank 1
6293 12:12:17.040015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 12:12:17.040592 ==
6295 12:12:17.046740 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6296 12:12:17.052586 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6297 12:12:17.055940 [CA 0] Center 36 (8~64) winsize 57
6298 12:12:17.059259 [CA 1] Center 36 (8~64) winsize 57
6299 12:12:17.062990 [CA 2] Center 36 (8~64) winsize 57
6300 12:12:17.066232 [CA 3] Center 36 (8~64) winsize 57
6301 12:12:17.068772 [CA 4] Center 36 (8~64) winsize 57
6302 12:12:17.069245 [CA 5] Center 36 (8~64) winsize 57
6303 12:12:17.073069
6304 12:12:17.075461 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6305 12:12:17.075973
6306 12:12:17.079099 [CATrainingPosCal] consider 2 rank data
6307 12:12:17.082583 u2DelayCellTimex100 = 270/100 ps
6308 12:12:17.085571 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 12:12:17.088569 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 12:12:17.092708 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 12:12:17.094997 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 12:12:17.098419 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 12:12:17.101950 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 12:12:17.102416
6315 12:12:17.105332 CA PerBit enable=1, Macro0, CA PI delay=36
6316 12:12:17.108595
6317 12:12:17.109055 [CBTSetCACLKResult] CA Dly = 36
6318 12:12:17.111656 CS Dly: 1 (0~32)
6319 12:12:17.112121
6320 12:12:17.115140 ----->DramcWriteLeveling(PI) begin...
6321 12:12:17.115510 ==
6322 12:12:17.118238 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 12:12:17.121987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 12:12:17.122448 ==
6325 12:12:17.125120 Write leveling (Byte 0): 40 => 8
6326 12:12:17.128410 Write leveling (Byte 1): 32 => 0
6327 12:12:17.131721 DramcWriteLeveling(PI) end<-----
6328 12:12:17.132152
6329 12:12:17.132419 ==
6330 12:12:17.134349 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 12:12:17.137689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 12:12:17.141718 ==
6333 12:12:17.142137 [Gating] SW mode calibration
6334 12:12:17.151208 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6335 12:12:17.154609 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6336 12:12:17.158262 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6337 12:12:17.165014 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6338 12:12:17.167354 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6339 12:12:17.170641 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6340 12:12:17.177738 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 12:12:17.180735 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 12:12:17.184222 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 12:12:17.190294 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6344 12:12:17.193739 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6345 12:12:17.196899 Total UI for P1: 0, mck2ui 16
6346 12:12:17.200775 best dqsien dly found for B0: ( 0, 14, 24)
6347 12:12:17.203778 Total UI for P1: 0, mck2ui 16
6348 12:12:17.207173 best dqsien dly found for B1: ( 0, 14, 24)
6349 12:12:17.210334 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6350 12:12:17.213442 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6351 12:12:17.213863
6352 12:12:17.217109 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6353 12:12:17.223793 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6354 12:12:17.224216 [Gating] SW calibration Done
6355 12:12:17.224551 ==
6356 12:12:17.226878 Dram Type= 6, Freq= 0, CH_0, rank 0
6357 12:12:17.233418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6358 12:12:17.233877 ==
6359 12:12:17.234217 RX Vref Scan: 0
6360 12:12:17.234534
6361 12:12:17.236416 RX Vref 0 -> 0, step: 1
6362 12:12:17.236831
6363 12:12:17.240150 RX Delay -410 -> 252, step: 16
6364 12:12:17.243142 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6365 12:12:17.247140 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6366 12:12:17.253019 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6367 12:12:17.256149 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6368 12:12:17.259320 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6369 12:12:17.263266 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6370 12:12:17.269879 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6371 12:12:17.273012 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6372 12:12:17.277199 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6373 12:12:17.279737 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6374 12:12:17.286665 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6375 12:12:17.289487 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6376 12:12:17.292670 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6377 12:12:17.299815 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6378 12:12:17.303108 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6379 12:12:17.305630 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6380 12:12:17.306047 ==
6381 12:12:17.309530 Dram Type= 6, Freq= 0, CH_0, rank 0
6382 12:12:17.316098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6383 12:12:17.316629 ==
6384 12:12:17.316968 DQS Delay:
6385 12:12:17.317287 DQS0 = 43, DQS1 = 59
6386 12:12:17.318853 DQM Delay:
6387 12:12:17.319274 DQM0 = 9, DQM1 = 11
6388 12:12:17.322977 DQ Delay:
6389 12:12:17.323518 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6390 12:12:17.326116 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6391 12:12:17.328845 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6392 12:12:17.332572 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6393 12:12:17.333095
6394 12:12:17.333433
6395 12:12:17.335868 ==
6396 12:12:17.338816 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 12:12:17.341778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 12:12:17.342222 ==
6399 12:12:17.342564
6400 12:12:17.342877
6401 12:12:17.345606 TX Vref Scan disable
6402 12:12:17.346022 == TX Byte 0 ==
6403 12:12:17.348605 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6404 12:12:17.355060 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6405 12:12:17.355483 == TX Byte 1 ==
6406 12:12:17.358210 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6407 12:12:17.365054 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6408 12:12:17.365532 ==
6409 12:12:17.368012 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 12:12:17.372068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 12:12:17.372481 ==
6412 12:12:17.372810
6413 12:12:17.373112
6414 12:12:17.374746 TX Vref Scan disable
6415 12:12:17.375275 == TX Byte 0 ==
6416 12:12:17.381733 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6417 12:12:17.385185 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6418 12:12:17.385646 == TX Byte 1 ==
6419 12:12:17.391126 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6420 12:12:17.394479 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6421 12:12:17.394894
6422 12:12:17.395221 [DATLAT]
6423 12:12:17.397967 Freq=400, CH0 RK0
6424 12:12:17.398382
6425 12:12:17.398705 DATLAT Default: 0xf
6426 12:12:17.401071 0, 0xFFFF, sum = 0
6427 12:12:17.401496 1, 0xFFFF, sum = 0
6428 12:12:17.404107 2, 0xFFFF, sum = 0
6429 12:12:17.404527 3, 0xFFFF, sum = 0
6430 12:12:17.408152 4, 0xFFFF, sum = 0
6431 12:12:17.408575 5, 0xFFFF, sum = 0
6432 12:12:17.411297 6, 0xFFFF, sum = 0
6433 12:12:17.411745 7, 0xFFFF, sum = 0
6434 12:12:17.414988 8, 0xFFFF, sum = 0
6435 12:12:17.418792 9, 0xFFFF, sum = 0
6436 12:12:17.419361 10, 0xFFFF, sum = 0
6437 12:12:17.421569 11, 0xFFFF, sum = 0
6438 12:12:17.422122 12, 0xFFFF, sum = 0
6439 12:12:17.425069 13, 0x0, sum = 1
6440 12:12:17.425640 14, 0x0, sum = 2
6441 12:12:17.427555 15, 0x0, sum = 3
6442 12:12:17.428059 16, 0x0, sum = 4
6443 12:12:17.428438 best_step = 14
6444 12:12:17.428777
6445 12:12:17.430994 ==
6446 12:12:17.434712 Dram Type= 6, Freq= 0, CH_0, rank 0
6447 12:12:17.437536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 12:12:17.438104 ==
6449 12:12:17.438475 RX Vref Scan: 1
6450 12:12:17.438817
6451 12:12:17.441077 RX Vref 0 -> 0, step: 1
6452 12:12:17.441540
6453 12:12:17.444216 RX Delay -359 -> 252, step: 8
6454 12:12:17.444781
6455 12:12:17.447946 Set Vref, RX VrefLevel [Byte0]: 60
6456 12:12:17.450927 [Byte1]: 58
6457 12:12:17.454751
6458 12:12:17.455242 Final RX Vref Byte 0 = 60 to rank0
6459 12:12:17.458352 Final RX Vref Byte 1 = 58 to rank0
6460 12:12:17.461447 Final RX Vref Byte 0 = 60 to rank1
6461 12:12:17.465050 Final RX Vref Byte 1 = 58 to rank1==
6462 12:12:17.468261 Dram Type= 6, Freq= 0, CH_0, rank 0
6463 12:12:17.474887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 12:12:17.475666 ==
6465 12:12:17.476113 DQS Delay:
6466 12:12:17.477590 DQS0 = 48, DQS1 = 60
6467 12:12:17.478056 DQM Delay:
6468 12:12:17.478421 DQM0 = 11, DQM1 = 11
6469 12:12:17.481373 DQ Delay:
6470 12:12:17.484720 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6471 12:12:17.488247 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6472 12:12:17.488813 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6473 12:12:17.491156 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20
6474 12:12:17.494383
6475 12:12:17.494949
6476 12:12:17.500741 [DQSOSCAuto] RK0, (LSB)MR18= 0xbd7f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6477 12:12:17.504660 CH0 RK0: MR19=C0C, MR18=BD7F
6478 12:12:17.511224 CH0_RK0: MR19=0xC0C, MR18=0xBD7F, DQSOSC=386, MR23=63, INC=396, DEC=264
6479 12:12:17.511737 ==
6480 12:12:17.514504 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 12:12:17.517726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 12:12:17.518304 ==
6483 12:12:17.521012 [Gating] SW mode calibration
6484 12:12:17.527637 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6485 12:12:17.534621 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6486 12:12:17.537730 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6487 12:12:17.540828 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6488 12:12:17.547534 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6489 12:12:17.550992 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6490 12:12:17.554344 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 12:12:17.560485 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 12:12:17.564143 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 12:12:17.567087 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6494 12:12:17.574047 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6495 12:12:17.574610 Total UI for P1: 0, mck2ui 16
6496 12:12:17.580188 best dqsien dly found for B0: ( 0, 14, 24)
6497 12:12:17.580757 Total UI for P1: 0, mck2ui 16
6498 12:12:17.586585 best dqsien dly found for B1: ( 0, 14, 24)
6499 12:12:17.589811 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6500 12:12:17.593557 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6501 12:12:17.594130
6502 12:12:17.596277 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6503 12:12:17.599937 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6504 12:12:17.603066 [Gating] SW calibration Done
6505 12:12:17.603631 ==
6506 12:12:17.606707 Dram Type= 6, Freq= 0, CH_0, rank 1
6507 12:12:17.610142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6508 12:12:17.610717 ==
6509 12:12:17.613368 RX Vref Scan: 0
6510 12:12:17.613932
6511 12:12:17.614303 RX Vref 0 -> 0, step: 1
6512 12:12:17.616556
6513 12:12:17.617017 RX Delay -410 -> 252, step: 16
6514 12:12:17.623304 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6515 12:12:17.626365 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6516 12:12:17.630328 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6517 12:12:17.633167 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6518 12:12:17.640349 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6519 12:12:17.643213 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6520 12:12:17.646436 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6521 12:12:17.650058 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6522 12:12:17.656391 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6523 12:12:17.659629 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6524 12:12:17.664045 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6525 12:12:17.670148 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6526 12:12:17.672300 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6527 12:12:17.676092 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6528 12:12:17.680114 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6529 12:12:17.686122 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6530 12:12:17.686692 ==
6531 12:12:17.689018 Dram Type= 6, Freq= 0, CH_0, rank 1
6532 12:12:17.692263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6533 12:12:17.692732 ==
6534 12:12:17.693103 DQS Delay:
6535 12:12:17.696457 DQS0 = 43, DQS1 = 59
6536 12:12:17.697021 DQM Delay:
6537 12:12:17.699197 DQM0 = 10, DQM1 = 16
6538 12:12:17.699802 DQ Delay:
6539 12:12:17.702944 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6540 12:12:17.705664 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6541 12:12:17.709147 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6542 12:12:17.713027 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6543 12:12:17.713594
6544 12:12:17.713965
6545 12:12:17.714304 ==
6546 12:12:17.715531 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 12:12:17.719106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 12:12:17.719802 ==
6549 12:12:17.720188
6550 12:12:17.720532
6551 12:12:17.722646 TX Vref Scan disable
6552 12:12:17.725737 == TX Byte 0 ==
6553 12:12:17.728338 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6554 12:12:17.732134 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6555 12:12:17.735628 == TX Byte 1 ==
6556 12:12:17.738732 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6557 12:12:17.742182 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6558 12:12:17.742749 ==
6559 12:12:17.745432 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 12:12:17.748797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 12:12:17.749354 ==
6562 12:12:17.751710
6563 12:12:17.752177
6564 12:12:17.752547 TX Vref Scan disable
6565 12:12:17.755027 == TX Byte 0 ==
6566 12:12:17.758511 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6567 12:12:17.762023 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6568 12:12:17.764630 == TX Byte 1 ==
6569 12:12:17.768562 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6570 12:12:17.771941 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6571 12:12:17.772513
6572 12:12:17.772886 [DATLAT]
6573 12:12:17.775005 Freq=400, CH0 RK1
6574 12:12:17.775467
6575 12:12:17.778270 DATLAT Default: 0xe
6576 12:12:17.778822 0, 0xFFFF, sum = 0
6577 12:12:17.781876 1, 0xFFFF, sum = 0
6578 12:12:17.782433 2, 0xFFFF, sum = 0
6579 12:12:17.784625 3, 0xFFFF, sum = 0
6580 12:12:17.785098 4, 0xFFFF, sum = 0
6581 12:12:17.788628 5, 0xFFFF, sum = 0
6582 12:12:17.789188 6, 0xFFFF, sum = 0
6583 12:12:17.792923 7, 0xFFFF, sum = 0
6584 12:12:17.793478 8, 0xFFFF, sum = 0
6585 12:12:17.795816 9, 0xFFFF, sum = 0
6586 12:12:17.796468 10, 0xFFFF, sum = 0
6587 12:12:17.797935 11, 0xFFFF, sum = 0
6588 12:12:17.798406 12, 0xFFFF, sum = 0
6589 12:12:17.801531 13, 0x0, sum = 1
6590 12:12:17.802029 14, 0x0, sum = 2
6591 12:12:17.804395 15, 0x0, sum = 3
6592 12:12:17.804866 16, 0x0, sum = 4
6593 12:12:17.807785 best_step = 14
6594 12:12:17.808318
6595 12:12:17.808686 ==
6596 12:12:17.812169 Dram Type= 6, Freq= 0, CH_0, rank 1
6597 12:12:17.815158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 12:12:17.815979 ==
6599 12:12:17.817518 RX Vref Scan: 0
6600 12:12:17.817980
6601 12:12:17.818349 RX Vref 0 -> 0, step: 1
6602 12:12:17.818696
6603 12:12:17.821503 RX Delay -359 -> 252, step: 8
6604 12:12:17.828927 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6605 12:12:17.832428 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6606 12:12:17.835660 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6607 12:12:17.842283 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6608 12:12:17.846217 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6609 12:12:17.848601 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6610 12:12:17.852436 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6611 12:12:17.859286 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6612 12:12:17.862260 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6613 12:12:17.865432 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6614 12:12:17.868246 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6615 12:12:17.875129 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6616 12:12:17.878655 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6617 12:12:17.882142 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6618 12:12:17.888384 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6619 12:12:17.891317 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6620 12:12:17.892067 ==
6621 12:12:17.895473 Dram Type= 6, Freq= 0, CH_0, rank 1
6622 12:12:17.897605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6623 12:12:17.898073 ==
6624 12:12:17.901248 DQS Delay:
6625 12:12:17.901875 DQS0 = 44, DQS1 = 60
6626 12:12:17.902254 DQM Delay:
6627 12:12:17.905082 DQM0 = 8, DQM1 = 14
6628 12:12:17.905653 DQ Delay:
6629 12:12:17.907592 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =4
6630 12:12:17.911364 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6631 12:12:17.914988 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6632 12:12:17.918402 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6633 12:12:17.918975
6634 12:12:17.919347
6635 12:12:17.927615 [DQSOSCAuto] RK1, (LSB)MR18= 0xb945, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6636 12:12:17.928194 CH0 RK1: MR19=C0C, MR18=B945
6637 12:12:17.934578 CH0_RK1: MR19=0xC0C, MR18=0xB945, DQSOSC=386, MR23=63, INC=396, DEC=264
6638 12:12:17.937577 [RxdqsGatingPostProcess] freq 400
6639 12:12:17.944270 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6640 12:12:17.947477 best DQS0 dly(2T, 0.5T) = (0, 10)
6641 12:12:17.950712 best DQS1 dly(2T, 0.5T) = (0, 10)
6642 12:12:17.954021 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6643 12:12:17.957183 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6644 12:12:17.960215 best DQS0 dly(2T, 0.5T) = (0, 10)
6645 12:12:17.963664 best DQS1 dly(2T, 0.5T) = (0, 10)
6646 12:12:17.966845 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6647 12:12:17.970687 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6648 12:12:17.971263 Pre-setting of DQS Precalculation
6649 12:12:17.977737 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6650 12:12:17.978304 ==
6651 12:12:17.981130 Dram Type= 6, Freq= 0, CH_1, rank 0
6652 12:12:17.983728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 12:12:17.984304 ==
6654 12:12:17.991139 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6655 12:12:17.996973 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6656 12:12:18.000939 [CA 0] Center 36 (8~64) winsize 57
6657 12:12:18.003583 [CA 1] Center 36 (8~64) winsize 57
6658 12:12:18.007587 [CA 2] Center 36 (8~64) winsize 57
6659 12:12:18.010694 [CA 3] Center 36 (8~64) winsize 57
6660 12:12:18.013109 [CA 4] Center 36 (8~64) winsize 57
6661 12:12:18.013679 [CA 5] Center 36 (8~64) winsize 57
6662 12:12:18.016626
6663 12:12:18.020096 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6664 12:12:18.020666
6665 12:12:18.023158 [CATrainingPosCal] consider 1 rank data
6666 12:12:18.027321 u2DelayCellTimex100 = 270/100 ps
6667 12:12:18.029860 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 12:12:18.033225 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 12:12:18.036176 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 12:12:18.039886 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 12:12:18.042762 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 12:12:18.046533 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 12:12:18.047107
6674 12:12:18.049376 CA PerBit enable=1, Macro0, CA PI delay=36
6675 12:12:18.053064
6676 12:12:18.053625 [CBTSetCACLKResult] CA Dly = 36
6677 12:12:18.056726 CS Dly: 1 (0~32)
6678 12:12:18.057287 ==
6679 12:12:18.059741 Dram Type= 6, Freq= 0, CH_1, rank 1
6680 12:12:18.062570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 12:12:18.063035 ==
6682 12:12:18.069306 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6683 12:12:18.076379 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6684 12:12:18.079711 [CA 0] Center 36 (8~64) winsize 57
6685 12:12:18.082515 [CA 1] Center 36 (8~64) winsize 57
6686 12:12:18.085450 [CA 2] Center 36 (8~64) winsize 57
6687 12:12:18.085918 [CA 3] Center 36 (8~64) winsize 57
6688 12:12:18.089358 [CA 4] Center 36 (8~64) winsize 57
6689 12:12:18.092361 [CA 5] Center 36 (8~64) winsize 57
6690 12:12:18.093189
6691 12:12:18.099191 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6692 12:12:18.099796
6693 12:12:18.102309 [CATrainingPosCal] consider 2 rank data
6694 12:12:18.106944 u2DelayCellTimex100 = 270/100 ps
6695 12:12:18.108744 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 12:12:18.112872 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 12:12:18.115837 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 12:12:18.118715 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 12:12:18.122210 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 12:12:18.125987 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 12:12:18.126555
6702 12:12:18.128900 CA PerBit enable=1, Macro0, CA PI delay=36
6703 12:12:18.129362
6704 12:12:18.132115 [CBTSetCACLKResult] CA Dly = 36
6705 12:12:18.135482 CS Dly: 1 (0~32)
6706 12:12:18.136090
6707 12:12:18.139085 ----->DramcWriteLeveling(PI) begin...
6708 12:12:18.139660 ==
6709 12:12:18.142001 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 12:12:18.145557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 12:12:18.146130 ==
6712 12:12:18.148546 Write leveling (Byte 0): 40 => 8
6713 12:12:18.152305 Write leveling (Byte 1): 40 => 8
6714 12:12:18.155070 DramcWriteLeveling(PI) end<-----
6715 12:12:18.155637
6716 12:12:18.156049 ==
6717 12:12:18.158461 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 12:12:18.161746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 12:12:18.162320 ==
6720 12:12:18.165449 [Gating] SW mode calibration
6721 12:12:18.171951 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6722 12:12:18.179164 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6723 12:12:18.181642 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6724 12:12:18.187989 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6725 12:12:18.191088 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6726 12:12:18.194725 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6727 12:12:18.201213 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 12:12:18.204294 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 12:12:18.208164 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 12:12:18.214549 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6731 12:12:18.217344 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6732 12:12:18.221720 Total UI for P1: 0, mck2ui 16
6733 12:12:18.224878 best dqsien dly found for B0: ( 0, 14, 24)
6734 12:12:18.227720 Total UI for P1: 0, mck2ui 16
6735 12:12:18.230980 best dqsien dly found for B1: ( 0, 14, 24)
6736 12:12:18.234693 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6737 12:12:18.237183 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6738 12:12:18.237646
6739 12:12:18.240521 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6740 12:12:18.244160 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6741 12:12:18.247328 [Gating] SW calibration Done
6742 12:12:18.247921 ==
6743 12:12:18.250386 Dram Type= 6, Freq= 0, CH_1, rank 0
6744 12:12:18.254812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6745 12:12:18.256852 ==
6746 12:12:18.257353 RX Vref Scan: 0
6747 12:12:18.257727
6748 12:12:18.260342 RX Vref 0 -> 0, step: 1
6749 12:12:18.260902
6750 12:12:18.263888 RX Delay -410 -> 252, step: 16
6751 12:12:18.267340 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6752 12:12:18.270560 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6753 12:12:18.277227 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6754 12:12:18.280580 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6755 12:12:18.283763 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6756 12:12:18.287469 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6757 12:12:18.293564 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6758 12:12:18.296789 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6759 12:12:18.300097 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6760 12:12:18.302923 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6761 12:12:18.309752 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6762 12:12:18.313004 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6763 12:12:18.316258 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6764 12:12:18.319621 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6765 12:12:18.326083 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6766 12:12:18.329415 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6767 12:12:18.329904 ==
6768 12:12:18.333002 Dram Type= 6, Freq= 0, CH_1, rank 0
6769 12:12:18.337159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6770 12:12:18.337645 ==
6771 12:12:18.340053 DQS Delay:
6772 12:12:18.340634 DQS0 = 43, DQS1 = 51
6773 12:12:18.343112 DQM Delay:
6774 12:12:18.343591 DQM0 = 12, DQM1 = 14
6775 12:12:18.344126 DQ Delay:
6776 12:12:18.345826 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6777 12:12:18.349783 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6778 12:12:18.352437 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6779 12:12:18.356170 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6780 12:12:18.356698
6781 12:12:18.357038
6782 12:12:18.357350 ==
6783 12:12:18.359547 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 12:12:18.365375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 12:12:18.365886 ==
6786 12:12:18.366264
6787 12:12:18.366606
6788 12:12:18.366929 TX Vref Scan disable
6789 12:12:18.369102 == TX Byte 0 ==
6790 12:12:18.372655 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6791 12:12:18.376017 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6792 12:12:18.379127 == TX Byte 1 ==
6793 12:12:18.382255 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6794 12:12:18.385318 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6795 12:12:18.388977 ==
6796 12:12:18.389564 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 12:12:18.395412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 12:12:18.396175 ==
6799 12:12:18.396673
6800 12:12:18.397134
6801 12:12:18.398550 TX Vref Scan disable
6802 12:12:18.399049 == TX Byte 0 ==
6803 12:12:18.401708 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6804 12:12:18.408568 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6805 12:12:18.409101 == TX Byte 1 ==
6806 12:12:18.411626 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6807 12:12:18.418367 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6808 12:12:18.418829
6809 12:12:18.419201 [DATLAT]
6810 12:12:18.419514 Freq=400, CH1 RK0
6811 12:12:18.419897
6812 12:12:18.421600 DATLAT Default: 0xf
6813 12:12:18.422076 0, 0xFFFF, sum = 0
6814 12:12:18.425040 1, 0xFFFF, sum = 0
6815 12:12:18.428072 2, 0xFFFF, sum = 0
6816 12:12:18.428607 3, 0xFFFF, sum = 0
6817 12:12:18.431818 4, 0xFFFF, sum = 0
6818 12:12:18.432258 5, 0xFFFF, sum = 0
6819 12:12:18.434871 6, 0xFFFF, sum = 0
6820 12:12:18.435296 7, 0xFFFF, sum = 0
6821 12:12:18.438221 8, 0xFFFF, sum = 0
6822 12:12:18.438644 9, 0xFFFF, sum = 0
6823 12:12:18.441925 10, 0xFFFF, sum = 0
6824 12:12:18.442481 11, 0xFFFF, sum = 0
6825 12:12:18.444867 12, 0xFFFF, sum = 0
6826 12:12:18.445427 13, 0x0, sum = 1
6827 12:12:18.448848 14, 0x0, sum = 2
6828 12:12:18.449392 15, 0x0, sum = 3
6829 12:12:18.451487 16, 0x0, sum = 4
6830 12:12:18.452230 best_step = 14
6831 12:12:18.452806
6832 12:12:18.453144 ==
6833 12:12:18.454995 Dram Type= 6, Freq= 0, CH_1, rank 0
6834 12:12:18.458169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 12:12:18.461602 ==
6836 12:12:18.462038 RX Vref Scan: 1
6837 12:12:18.462482
6838 12:12:18.464838 RX Vref 0 -> 0, step: 1
6839 12:12:18.465311
6840 12:12:18.467577 RX Delay -343 -> 252, step: 8
6841 12:12:18.468042
6842 12:12:18.471090 Set Vref, RX VrefLevel [Byte0]: 50
6843 12:12:18.474935 [Byte1]: 60
6844 12:12:18.475457
6845 12:12:18.478105 Final RX Vref Byte 0 = 50 to rank0
6846 12:12:18.481092 Final RX Vref Byte 1 = 60 to rank0
6847 12:12:18.484133 Final RX Vref Byte 0 = 50 to rank1
6848 12:12:18.487791 Final RX Vref Byte 1 = 60 to rank1==
6849 12:12:18.491762 Dram Type= 6, Freq= 0, CH_1, rank 0
6850 12:12:18.494292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 12:12:18.497167 ==
6852 12:12:18.497588 DQS Delay:
6853 12:12:18.497925 DQS0 = 44, DQS1 = 56
6854 12:12:18.501336 DQM Delay:
6855 12:12:18.501870 DQM0 = 9, DQM1 = 13
6856 12:12:18.504079 DQ Delay:
6857 12:12:18.504544 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6858 12:12:18.507515 DQ4 =4, DQ5 =20, DQ6 =16, DQ7 =4
6859 12:12:18.510566 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6860 12:12:18.514257 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =24
6861 12:12:18.514775
6862 12:12:18.515143
6863 12:12:18.523819 [DQSOSCAuto] RK0, (LSB)MR18= 0x9f75, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 389 ps
6864 12:12:18.527609 CH1 RK0: MR19=C0C, MR18=9F75
6865 12:12:18.534078 CH1_RK0: MR19=0xC0C, MR18=0x9F75, DQSOSC=389, MR23=63, INC=390, DEC=260
6866 12:12:18.534635 ==
6867 12:12:18.537196 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 12:12:18.540687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 12:12:18.541242 ==
6870 12:12:18.543839 [Gating] SW mode calibration
6871 12:12:18.550226 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6872 12:12:18.556875 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6873 12:12:18.560020 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6874 12:12:18.563862 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6875 12:12:18.570247 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6876 12:12:18.573573 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6877 12:12:18.576483 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 12:12:18.583727 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 12:12:18.586906 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 12:12:18.589914 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6881 12:12:18.596440 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6882 12:12:18.596992 Total UI for P1: 0, mck2ui 16
6883 12:12:18.599863 best dqsien dly found for B0: ( 0, 14, 24)
6884 12:12:18.603396 Total UI for P1: 0, mck2ui 16
6885 12:12:18.607451 best dqsien dly found for B1: ( 0, 14, 24)
6886 12:12:18.613354 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6887 12:12:18.615782 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6888 12:12:18.616245
6889 12:12:18.619398 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6890 12:12:18.622233 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6891 12:12:18.625856 [Gating] SW calibration Done
6892 12:12:18.626432 ==
6893 12:12:18.629636 Dram Type= 6, Freq= 0, CH_1, rank 1
6894 12:12:18.633446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6895 12:12:18.634030 ==
6896 12:12:18.635464 RX Vref Scan: 0
6897 12:12:18.636011
6898 12:12:18.636497 RX Vref 0 -> 0, step: 1
6899 12:12:18.636960
6900 12:12:18.639127 RX Delay -410 -> 252, step: 16
6901 12:12:18.646004 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6902 12:12:18.649014 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6903 12:12:18.652547 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6904 12:12:18.656262 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6905 12:12:18.662742 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6906 12:12:18.665446 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6907 12:12:18.668735 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6908 12:12:18.672031 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6909 12:12:18.678726 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6910 12:12:18.682069 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6911 12:12:18.685373 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6912 12:12:18.688562 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6913 12:12:18.695199 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6914 12:12:18.698866 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6915 12:12:18.702227 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6916 12:12:18.708136 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6917 12:12:18.708707 ==
6918 12:12:18.711841 Dram Type= 6, Freq= 0, CH_1, rank 1
6919 12:12:18.715179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6920 12:12:18.715811 ==
6921 12:12:18.716308 DQS Delay:
6922 12:12:18.718206 DQS0 = 51, DQS1 = 51
6923 12:12:18.718686 DQM Delay:
6924 12:12:18.722030 DQM0 = 19, DQM1 = 15
6925 12:12:18.722607 DQ Delay:
6926 12:12:18.724824 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6927 12:12:18.727926 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6928 12:12:18.731167 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6929 12:12:18.734562 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6930 12:12:18.735135
6931 12:12:18.735634
6932 12:12:18.736143 ==
6933 12:12:18.737677 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 12:12:18.741258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 12:12:18.741844 ==
6936 12:12:18.744398
6937 12:12:18.744882
6938 12:12:18.745369 TX Vref Scan disable
6939 12:12:18.747964 == TX Byte 0 ==
6940 12:12:18.750705 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6941 12:12:18.754342 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6942 12:12:18.757327 == TX Byte 1 ==
6943 12:12:18.761500 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6944 12:12:18.764031 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6945 12:12:18.764519 ==
6946 12:12:18.767653 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 12:12:18.770426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 12:12:18.774133 ==
6949 12:12:18.774615
6950 12:12:18.775102
6951 12:12:18.775561 TX Vref Scan disable
6952 12:12:18.777630 == TX Byte 0 ==
6953 12:12:18.780845 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6954 12:12:18.784554 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6955 12:12:18.787349 == TX Byte 1 ==
6956 12:12:18.791262 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6957 12:12:18.794071 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6958 12:12:18.794634
6959 12:12:18.797352 [DATLAT]
6960 12:12:18.797835 Freq=400, CH1 RK1
6961 12:12:18.798331
6962 12:12:18.800476 DATLAT Default: 0xe
6963 12:12:18.800957 0, 0xFFFF, sum = 0
6964 12:12:18.804085 1, 0xFFFF, sum = 0
6965 12:12:18.804571 2, 0xFFFF, sum = 0
6966 12:12:18.806891 3, 0xFFFF, sum = 0
6967 12:12:18.807335 4, 0xFFFF, sum = 0
6968 12:12:18.811213 5, 0xFFFF, sum = 0
6969 12:12:18.811796 6, 0xFFFF, sum = 0
6970 12:12:18.813832 7, 0xFFFF, sum = 0
6971 12:12:18.814372 8, 0xFFFF, sum = 0
6972 12:12:18.816897 9, 0xFFFF, sum = 0
6973 12:12:18.817340 10, 0xFFFF, sum = 0
6974 12:12:18.820798 11, 0xFFFF, sum = 0
6975 12:12:18.823848 12, 0xFFFF, sum = 0
6976 12:12:18.824289 13, 0x0, sum = 1
6977 12:12:18.824634 14, 0x0, sum = 2
6978 12:12:18.827136 15, 0x0, sum = 3
6979 12:12:18.827665 16, 0x0, sum = 4
6980 12:12:18.829862 best_step = 14
6981 12:12:18.830278
6982 12:12:18.830608 ==
6983 12:12:18.833338 Dram Type= 6, Freq= 0, CH_1, rank 1
6984 12:12:18.836487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6985 12:12:18.836908 ==
6986 12:12:18.840035 RX Vref Scan: 0
6987 12:12:18.840454
6988 12:12:18.840786 RX Vref 0 -> 0, step: 1
6989 12:12:18.841098
6990 12:12:18.843598 RX Delay -343 -> 252, step: 8
6991 12:12:18.852124 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
6992 12:12:18.855021 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6993 12:12:18.858424 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
6994 12:12:18.864846 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
6995 12:12:18.867645 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
6996 12:12:18.871154 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
6997 12:12:18.874353 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
6998 12:12:18.881187 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
6999 12:12:18.884062 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7000 12:12:18.887640 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7001 12:12:18.891767 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7002 12:12:18.897308 iDelay=225, Bit 11, Center -52 (-303 ~ 200) 504
7003 12:12:18.901176 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7004 12:12:18.904596 iDelay=225, Bit 13, Center -36 (-287 ~ 216) 504
7005 12:12:18.907663 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7006 12:12:18.914401 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
7007 12:12:18.914966 ==
7008 12:12:18.917843 Dram Type= 6, Freq= 0, CH_1, rank 1
7009 12:12:18.921182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7010 12:12:18.921759 ==
7011 12:12:18.922134 DQS Delay:
7012 12:12:18.923964 DQS0 = 44, DQS1 = 56
7013 12:12:18.924427 DQM Delay:
7014 12:12:18.927481 DQM0 = 9, DQM1 = 12
7015 12:12:18.928078 DQ Delay:
7016 12:12:18.930759 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
7017 12:12:18.933949 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
7018 12:12:18.936989 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7019 12:12:18.940615 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
7020 12:12:18.941082
7021 12:12:18.941452
7022 12:12:18.950064 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c5b, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7023 12:12:18.950641 CH1 RK1: MR19=C0C, MR18=6C5B
7024 12:12:18.956854 CH1_RK1: MR19=0xC0C, MR18=0x6C5B, DQSOSC=396, MR23=63, INC=376, DEC=251
7025 12:12:18.960007 [RxdqsGatingPostProcess] freq 400
7026 12:12:18.966897 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7027 12:12:18.970730 best DQS0 dly(2T, 0.5T) = (0, 10)
7028 12:12:18.973371 best DQS1 dly(2T, 0.5T) = (0, 10)
7029 12:12:18.977129 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7030 12:12:18.979922 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7031 12:12:18.983259 best DQS0 dly(2T, 0.5T) = (0, 10)
7032 12:12:18.983889 best DQS1 dly(2T, 0.5T) = (0, 10)
7033 12:12:18.986934 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7034 12:12:18.990116 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7035 12:12:18.993315 Pre-setting of DQS Precalculation
7036 12:12:18.999544 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7037 12:12:19.006206 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7038 12:12:19.012666 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7039 12:12:19.013131
7040 12:12:19.013496
7041 12:12:19.016368 [Calibration Summary] 800 Mbps
7042 12:12:19.019498 CH 0, Rank 0
7043 12:12:19.020023 SW Impedance : PASS
7044 12:12:19.022743 DUTY Scan : NO K
7045 12:12:19.026480 ZQ Calibration : PASS
7046 12:12:19.027051 Jitter Meter : NO K
7047 12:12:19.030231 CBT Training : PASS
7048 12:12:19.030893 Write leveling : PASS
7049 12:12:19.032563 RX DQS gating : PASS
7050 12:12:19.036217 RX DQ/DQS(RDDQC) : PASS
7051 12:12:19.036782 TX DQ/DQS : PASS
7052 12:12:19.039520 RX DATLAT : PASS
7053 12:12:19.042764 RX DQ/DQS(Engine): PASS
7054 12:12:19.043332 TX OE : NO K
7055 12:12:19.046187 All Pass.
7056 12:12:19.046754
7057 12:12:19.047126 CH 0, Rank 1
7058 12:12:19.049413 SW Impedance : PASS
7059 12:12:19.049991 DUTY Scan : NO K
7060 12:12:19.052297 ZQ Calibration : PASS
7061 12:12:19.056098 Jitter Meter : NO K
7062 12:12:19.056722 CBT Training : PASS
7063 12:12:19.059031 Write leveling : NO K
7064 12:12:19.062980 RX DQS gating : PASS
7065 12:12:19.063554 RX DQ/DQS(RDDQC) : PASS
7066 12:12:19.065308 TX DQ/DQS : PASS
7067 12:12:19.069430 RX DATLAT : PASS
7068 12:12:19.069909 RX DQ/DQS(Engine): PASS
7069 12:12:19.071794 TX OE : NO K
7070 12:12:19.072281 All Pass.
7071 12:12:19.072767
7072 12:12:19.075436 CH 1, Rank 0
7073 12:12:19.076068 SW Impedance : PASS
7074 12:12:19.078862 DUTY Scan : NO K
7075 12:12:19.082121 ZQ Calibration : PASS
7076 12:12:19.082696 Jitter Meter : NO K
7077 12:12:19.086044 CBT Training : PASS
7078 12:12:19.089250 Write leveling : PASS
7079 12:12:19.089835 RX DQS gating : PASS
7080 12:12:19.091756 RX DQ/DQS(RDDQC) : PASS
7081 12:12:19.095328 TX DQ/DQS : PASS
7082 12:12:19.095953 RX DATLAT : PASS
7083 12:12:19.098533 RX DQ/DQS(Engine): PASS
7084 12:12:19.102078 TX OE : NO K
7085 12:12:19.102657 All Pass.
7086 12:12:19.103156
7087 12:12:19.103619 CH 1, Rank 1
7088 12:12:19.105418 SW Impedance : PASS
7089 12:12:19.108389 DUTY Scan : NO K
7090 12:12:19.108859 ZQ Calibration : PASS
7091 12:12:19.111638 Jitter Meter : NO K
7092 12:12:19.114928 CBT Training : PASS
7093 12:12:19.115486 Write leveling : NO K
7094 12:12:19.118205 RX DQS gating : PASS
7095 12:12:19.118687 RX DQ/DQS(RDDQC) : PASS
7096 12:12:19.122043 TX DQ/DQS : PASS
7097 12:12:19.124836 RX DATLAT : PASS
7098 12:12:19.125369 RX DQ/DQS(Engine): PASS
7099 12:12:19.128218 TX OE : NO K
7100 12:12:19.128697 All Pass.
7101 12:12:19.129066
7102 12:12:19.131539 DramC Write-DBI off
7103 12:12:19.134650 PER_BANK_REFRESH: Hybrid Mode
7104 12:12:19.135112 TX_TRACKING: ON
7105 12:12:19.144822 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7106 12:12:19.148160 [FAST_K] Save calibration result to emmc
7107 12:12:19.151354 dramc_set_vcore_voltage set vcore to 725000
7108 12:12:19.155278 Read voltage for 1600, 0
7109 12:12:19.155839 Vio18 = 0
7110 12:12:19.157829 Vcore = 725000
7111 12:12:19.158253 Vdram = 0
7112 12:12:19.158592 Vddq = 0
7113 12:12:19.158905 Vmddr = 0
7114 12:12:19.165803 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7115 12:12:19.171333 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7116 12:12:19.171895 MEM_TYPE=3, freq_sel=13
7117 12:12:19.174047 sv_algorithm_assistance_LP4_3733
7118 12:12:19.177338 ============ PULL DRAM RESETB DOWN ============
7119 12:12:19.184608 ========== PULL DRAM RESETB DOWN end =========
7120 12:12:19.187557 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7121 12:12:19.191571 ===================================
7122 12:12:19.194314 LPDDR4 DRAM CONFIGURATION
7123 12:12:19.197810 ===================================
7124 12:12:19.198339 EX_ROW_EN[0] = 0x0
7125 12:12:19.200643 EX_ROW_EN[1] = 0x0
7126 12:12:19.204490 LP4Y_EN = 0x0
7127 12:12:19.205016 WORK_FSP = 0x1
7128 12:12:19.207210 WL = 0x5
7129 12:12:19.207771 RL = 0x5
7130 12:12:19.211321 BL = 0x2
7131 12:12:19.211896 RPST = 0x0
7132 12:12:19.213711 RD_PRE = 0x0
7133 12:12:19.214149 WR_PRE = 0x1
7134 12:12:19.217528 WR_PST = 0x1
7135 12:12:19.218065 DBI_WR = 0x0
7136 12:12:19.220966 DBI_RD = 0x0
7137 12:12:19.221499 OTF = 0x1
7138 12:12:19.223980 ===================================
7139 12:12:19.227243 ===================================
7140 12:12:19.230466 ANA top config
7141 12:12:19.233799 ===================================
7142 12:12:19.234242 DLL_ASYNC_EN = 0
7143 12:12:19.237353 ALL_SLAVE_EN = 0
7144 12:12:19.240263 NEW_RANK_MODE = 1
7145 12:12:19.243851 DLL_IDLE_MODE = 1
7146 12:12:19.247265 LP45_APHY_COMB_EN = 1
7147 12:12:19.247842 TX_ODT_DIS = 0
7148 12:12:19.251494 NEW_8X_MODE = 1
7149 12:12:19.253165 ===================================
7150 12:12:19.256715 ===================================
7151 12:12:19.260104 data_rate = 3200
7152 12:12:19.263516 CKR = 1
7153 12:12:19.266688 DQ_P2S_RATIO = 8
7154 12:12:19.270046 ===================================
7155 12:12:19.272998 CA_P2S_RATIO = 8
7156 12:12:19.273416 DQ_CA_OPEN = 0
7157 12:12:19.277141 DQ_SEMI_OPEN = 0
7158 12:12:19.280188 CA_SEMI_OPEN = 0
7159 12:12:19.283205 CA_FULL_RATE = 0
7160 12:12:19.286703 DQ_CKDIV4_EN = 0
7161 12:12:19.289586 CA_CKDIV4_EN = 0
7162 12:12:19.290050 CA_PREDIV_EN = 0
7163 12:12:19.292875 PH8_DLY = 12
7164 12:12:19.296298 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7165 12:12:19.299259 DQ_AAMCK_DIV = 4
7166 12:12:19.303185 CA_AAMCK_DIV = 4
7167 12:12:19.306435 CA_ADMCK_DIV = 4
7168 12:12:19.309460 DQ_TRACK_CA_EN = 0
7169 12:12:19.309925 CA_PICK = 1600
7170 12:12:19.312290 CA_MCKIO = 1600
7171 12:12:19.316529 MCKIO_SEMI = 0
7172 12:12:19.319537 PLL_FREQ = 3068
7173 12:12:19.323751 DQ_UI_PI_RATIO = 32
7174 12:12:19.326153 CA_UI_PI_RATIO = 0
7175 12:12:19.329314 ===================================
7176 12:12:19.332249 ===================================
7177 12:12:19.336152 memory_type:LPDDR4
7178 12:12:19.336615 GP_NUM : 10
7179 12:12:19.339145 SRAM_EN : 1
7180 12:12:19.339748 MD32_EN : 0
7181 12:12:19.342541 ===================================
7182 12:12:19.345529 [ANA_INIT] >>>>>>>>>>>>>>
7183 12:12:19.348763 <<<<<< [CONFIGURE PHASE]: ANA_TX
7184 12:12:19.352609 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7185 12:12:19.355720 ===================================
7186 12:12:19.358760 data_rate = 3200,PCW = 0X7600
7187 12:12:19.362060 ===================================
7188 12:12:19.365635 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7189 12:12:19.371853 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7190 12:12:19.375779 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7191 12:12:19.382429 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7192 12:12:19.385453 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7193 12:12:19.389010 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7194 12:12:19.389570 [ANA_INIT] flow start
7195 12:12:19.391864 [ANA_INIT] PLL >>>>>>>>
7196 12:12:19.395525 [ANA_INIT] PLL <<<<<<<<
7197 12:12:19.396048 [ANA_INIT] MIDPI >>>>>>>>
7198 12:12:19.398719 [ANA_INIT] MIDPI <<<<<<<<
7199 12:12:19.401426 [ANA_INIT] DLL >>>>>>>>
7200 12:12:19.404575 [ANA_INIT] DLL <<<<<<<<
7201 12:12:19.405041 [ANA_INIT] flow end
7202 12:12:19.408605 ============ LP4 DIFF to SE enter ============
7203 12:12:19.415016 ============ LP4 DIFF to SE exit ============
7204 12:12:19.415583 [ANA_INIT] <<<<<<<<<<<<<
7205 12:12:19.418029 [Flow] Enable top DCM control >>>>>
7206 12:12:19.421807 [Flow] Enable top DCM control <<<<<
7207 12:12:19.424687 Enable DLL master slave shuffle
7208 12:12:19.431297 ==============================================================
7209 12:12:19.431816 Gating Mode config
7210 12:12:19.438294 ==============================================================
7211 12:12:19.441383 Config description:
7212 12:12:19.451934 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7213 12:12:19.458222 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7214 12:12:19.461574 SELPH_MODE 0: By rank 1: By Phase
7215 12:12:19.467638 ==============================================================
7216 12:12:19.471055 GAT_TRACK_EN = 1
7217 12:12:19.471617 RX_GATING_MODE = 2
7218 12:12:19.474828 RX_GATING_TRACK_MODE = 2
7219 12:12:19.477947 SELPH_MODE = 1
7220 12:12:19.481005 PICG_EARLY_EN = 1
7221 12:12:19.484391 VALID_LAT_VALUE = 1
7222 12:12:19.490947 ==============================================================
7223 12:12:19.494234 Enter into Gating configuration >>>>
7224 12:12:19.497556 Exit from Gating configuration <<<<
7225 12:12:19.500744 Enter into DVFS_PRE_config >>>>>
7226 12:12:19.510794 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7227 12:12:19.513937 Exit from DVFS_PRE_config <<<<<
7228 12:12:19.517167 Enter into PICG configuration >>>>
7229 12:12:19.521169 Exit from PICG configuration <<<<
7230 12:12:19.524167 [RX_INPUT] configuration >>>>>
7231 12:12:19.527177 [RX_INPUT] configuration <<<<<
7232 12:12:19.530179 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7233 12:12:19.537128 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7234 12:12:19.543276 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7235 12:12:19.550121 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7236 12:12:19.553198 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7237 12:12:19.559832 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7238 12:12:19.567539 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7239 12:12:19.571037 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7240 12:12:19.574879 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7241 12:12:19.576700 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7242 12:12:19.579770 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7243 12:12:19.586517 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7244 12:12:19.589901 ===================================
7245 12:12:19.593162 LPDDR4 DRAM CONFIGURATION
7246 12:12:19.596827 ===================================
7247 12:12:19.597628 EX_ROW_EN[0] = 0x0
7248 12:12:19.599721 EX_ROW_EN[1] = 0x0
7249 12:12:19.600190 LP4Y_EN = 0x0
7250 12:12:19.603090 WORK_FSP = 0x1
7251 12:12:19.603552 WL = 0x5
7252 12:12:19.606940 RL = 0x5
7253 12:12:19.607507 BL = 0x2
7254 12:12:19.609371 RPST = 0x0
7255 12:12:19.609829 RD_PRE = 0x0
7256 12:12:19.612645 WR_PRE = 0x1
7257 12:12:19.617163 WR_PST = 0x1
7258 12:12:19.617721 DBI_WR = 0x0
7259 12:12:19.619561 DBI_RD = 0x0
7260 12:12:19.620058 OTF = 0x1
7261 12:12:19.623416 ===================================
7262 12:12:19.625964 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7263 12:12:19.632580 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7264 12:12:19.636809 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7265 12:12:19.639462 ===================================
7266 12:12:19.643075 LPDDR4 DRAM CONFIGURATION
7267 12:12:19.645832 ===================================
7268 12:12:19.646297 EX_ROW_EN[0] = 0x10
7269 12:12:19.649199 EX_ROW_EN[1] = 0x0
7270 12:12:19.649767 LP4Y_EN = 0x0
7271 12:12:19.652581 WORK_FSP = 0x1
7272 12:12:19.653146 WL = 0x5
7273 12:12:19.656170 RL = 0x5
7274 12:12:19.656737 BL = 0x2
7275 12:12:19.659553 RPST = 0x0
7276 12:12:19.663614 RD_PRE = 0x0
7277 12:12:19.664233 WR_PRE = 0x1
7278 12:12:19.665354 WR_PST = 0x1
7279 12:12:19.665816 DBI_WR = 0x0
7280 12:12:19.669391 DBI_RD = 0x0
7281 12:12:19.669975 OTF = 0x1
7282 12:12:19.672071 ===================================
7283 12:12:19.678607 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7284 12:12:19.679173 ==
7285 12:12:19.682508 Dram Type= 6, Freq= 0, CH_0, rank 0
7286 12:12:19.685929 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7287 12:12:19.686502 ==
7288 12:12:19.689736 [Duty_Offset_Calibration]
7289 12:12:19.692300 B0:1 B1:-1 CA:0
7290 12:12:19.692867
7291 12:12:19.695794 [DutyScan_Calibration_Flow] k_type=0
7292 12:12:19.704170
7293 12:12:19.704633 ==CLK 0==
7294 12:12:19.707006 Final CLK duty delay cell = 0
7295 12:12:19.710463 [0] MAX Duty = 5124%(X100), DQS PI = 22
7296 12:12:19.713862 [0] MIN Duty = 4907%(X100), DQS PI = 4
7297 12:12:19.714331 [0] AVG Duty = 5015%(X100)
7298 12:12:19.716907
7299 12:12:19.720080 CH0 CLK Duty spec in!! Max-Min= 217%
7300 12:12:19.723758 [DutyScan_Calibration_Flow] ====Done====
7301 12:12:19.724324
7302 12:12:19.727135 [DutyScan_Calibration_Flow] k_type=1
7303 12:12:19.743398
7304 12:12:19.744017 ==DQS 0 ==
7305 12:12:19.746352 Final DQS duty delay cell = -4
7306 12:12:19.749884 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7307 12:12:19.752491 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7308 12:12:19.755828 [-4] AVG Duty = 4922%(X100)
7309 12:12:19.756296
7310 12:12:19.756671 ==DQS 1 ==
7311 12:12:19.760020 Final DQS duty delay cell = 0
7312 12:12:19.762657 [0] MAX Duty = 5187%(X100), DQS PI = 4
7313 12:12:19.766323 [0] MIN Duty = 5031%(X100), DQS PI = 16
7314 12:12:19.769187 [0] AVG Duty = 5109%(X100)
7315 12:12:19.769649
7316 12:12:19.772187 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7317 12:12:19.772655
7318 12:12:19.775450 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7319 12:12:19.779344 [DutyScan_Calibration_Flow] ====Done====
7320 12:12:19.779940
7321 12:12:19.782590 [DutyScan_Calibration_Flow] k_type=3
7322 12:12:19.801087
7323 12:12:19.801635 ==DQM 0 ==
7324 12:12:19.803273 Final DQM duty delay cell = 0
7325 12:12:19.807105 [0] MAX Duty = 5124%(X100), DQS PI = 24
7326 12:12:19.809976 [0] MIN Duty = 4907%(X100), DQS PI = 10
7327 12:12:19.813507 [0] AVG Duty = 5015%(X100)
7328 12:12:19.813967
7329 12:12:19.814334 ==DQM 1 ==
7330 12:12:19.816578 Final DQM duty delay cell = 0
7331 12:12:19.820601 [0] MAX Duty = 5000%(X100), DQS PI = 4
7332 12:12:19.823200 [0] MIN Duty = 4813%(X100), DQS PI = 20
7333 12:12:19.826684 [0] AVG Duty = 4906%(X100)
7334 12:12:19.827103
7335 12:12:19.829809 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7336 12:12:19.830231
7337 12:12:19.832920 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7338 12:12:19.837323 [DutyScan_Calibration_Flow] ====Done====
7339 12:12:19.837747
7340 12:12:19.840445 [DutyScan_Calibration_Flow] k_type=2
7341 12:12:19.856640
7342 12:12:19.857210 ==DQ 0 ==
7343 12:12:19.860359 Final DQ duty delay cell = -4
7344 12:12:19.863766 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7345 12:12:19.866933 [-4] MIN Duty = 4876%(X100), DQS PI = 50
7346 12:12:19.870348 [-4] AVG Duty = 4953%(X100)
7347 12:12:19.870906
7348 12:12:19.871278 ==DQ 1 ==
7349 12:12:19.872963 Final DQ duty delay cell = 0
7350 12:12:19.876543 [0] MAX Duty = 5125%(X100), DQS PI = 2
7351 12:12:19.879978 [0] MIN Duty = 5000%(X100), DQS PI = 36
7352 12:12:19.883222 [0] AVG Duty = 5062%(X100)
7353 12:12:19.883805
7354 12:12:19.886475 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7355 12:12:19.887033
7356 12:12:19.889702 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7357 12:12:19.894031 [DutyScan_Calibration_Flow] ====Done====
7358 12:12:19.894582 ==
7359 12:12:19.896372 Dram Type= 6, Freq= 0, CH_1, rank 0
7360 12:12:19.899525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7361 12:12:19.900043 ==
7362 12:12:19.902520 [Duty_Offset_Calibration]
7363 12:12:19.903190 B0:-1 B1:1 CA:2
7364 12:12:19.903572
7365 12:12:19.906440 [DutyScan_Calibration_Flow] k_type=0
7366 12:12:19.917407
7367 12:12:19.917960 ==CLK 0==
7368 12:12:19.920806 Final CLK duty delay cell = 0
7369 12:12:19.923856 [0] MAX Duty = 5187%(X100), DQS PI = 22
7370 12:12:19.927199 [0] MIN Duty = 5000%(X100), DQS PI = 0
7371 12:12:19.930603 [0] AVG Duty = 5093%(X100)
7372 12:12:19.931066
7373 12:12:19.934207 CH1 CLK Duty spec in!! Max-Min= 187%
7374 12:12:19.936697 [DutyScan_Calibration_Flow] ====Done====
7375 12:12:19.937165
7376 12:12:19.941076 [DutyScan_Calibration_Flow] k_type=1
7377 12:12:19.956917
7378 12:12:19.957482 ==DQS 0 ==
7379 12:12:19.960579 Final DQS duty delay cell = 0
7380 12:12:19.964101 [0] MAX Duty = 5124%(X100), DQS PI = 18
7381 12:12:19.966975 [0] MIN Duty = 4907%(X100), DQS PI = 10
7382 12:12:19.969926 [0] AVG Duty = 5015%(X100)
7383 12:12:19.970392
7384 12:12:19.970764 ==DQS 1 ==
7385 12:12:19.973277 Final DQS duty delay cell = 0
7386 12:12:19.977131 [0] MAX Duty = 5093%(X100), DQS PI = 26
7387 12:12:19.980219 [0] MIN Duty = 4969%(X100), DQS PI = 56
7388 12:12:19.983362 [0] AVG Duty = 5031%(X100)
7389 12:12:19.983821
7390 12:12:19.987133 CH1 DQS 0 Duty spec in!! Max-Min= 217%
7391 12:12:19.987652
7392 12:12:19.990352 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7393 12:12:19.993296 [DutyScan_Calibration_Flow] ====Done====
7394 12:12:19.993812
7395 12:12:19.997164 [DutyScan_Calibration_Flow] k_type=3
7396 12:12:20.012931
7397 12:12:20.013486 ==DQM 0 ==
7398 12:12:20.016773 Final DQM duty delay cell = -4
7399 12:12:20.019824 [-4] MAX Duty = 5062%(X100), DQS PI = 18
7400 12:12:20.022919 [-4] MIN Duty = 4782%(X100), DQS PI = 10
7401 12:12:20.026524 [-4] AVG Duty = 4922%(X100)
7402 12:12:20.026991
7403 12:12:20.027359 ==DQM 1 ==
7404 12:12:20.029939 Final DQM duty delay cell = 0
7405 12:12:20.032832 [0] MAX Duty = 5125%(X100), DQS PI = 2
7406 12:12:20.036835 [0] MIN Duty = 4969%(X100), DQS PI = 34
7407 12:12:20.039470 [0] AVG Duty = 5047%(X100)
7408 12:12:20.040065
7409 12:12:20.042439 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7410 12:12:20.042906
7411 12:12:20.046092 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7412 12:12:20.049637 [DutyScan_Calibration_Flow] ====Done====
7413 12:12:20.050190
7414 12:12:20.052656 [DutyScan_Calibration_Flow] k_type=2
7415 12:12:20.070698
7416 12:12:20.071330 ==DQ 0 ==
7417 12:12:20.074140 Final DQ duty delay cell = 0
7418 12:12:20.076671 [0] MAX Duty = 5156%(X100), DQS PI = 30
7419 12:12:20.081066 [0] MIN Duty = 4906%(X100), DQS PI = 10
7420 12:12:20.083654 [0] AVG Duty = 5031%(X100)
7421 12:12:20.084159
7422 12:12:20.084528 ==DQ 1 ==
7423 12:12:20.087001 Final DQ duty delay cell = 0
7424 12:12:20.090561 [0] MAX Duty = 5156%(X100), DQS PI = 8
7425 12:12:20.094298 [0] MIN Duty = 4969%(X100), DQS PI = 56
7426 12:12:20.094868 [0] AVG Duty = 5062%(X100)
7427 12:12:20.097109
7428 12:12:20.100247 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7429 12:12:20.100725
7430 12:12:20.102877 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7431 12:12:20.106442 [DutyScan_Calibration_Flow] ====Done====
7432 12:12:20.110363 nWR fixed to 30
7433 12:12:20.110932 [ModeRegInit_LP4] CH0 RK0
7434 12:12:20.112942 [ModeRegInit_LP4] CH0 RK1
7435 12:12:20.116301 [ModeRegInit_LP4] CH1 RK0
7436 12:12:20.120138 [ModeRegInit_LP4] CH1 RK1
7437 12:12:20.120702 match AC timing 5
7438 12:12:20.126374 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7439 12:12:20.129851 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7440 12:12:20.132711 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7441 12:12:20.139655 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7442 12:12:20.142686 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7443 12:12:20.143189 [MiockJmeterHQA]
7444 12:12:20.143557
7445 12:12:20.145982 [DramcMiockJmeter] u1RxGatingPI = 0
7446 12:12:20.149653 0 : 4363, 4137
7447 12:12:20.150233 4 : 4253, 4026
7448 12:12:20.152384 8 : 4365, 4140
7449 12:12:20.152852 12 : 4363, 4137
7450 12:12:20.155929 16 : 4255, 4030
7451 12:12:20.156397 20 : 4252, 4027
7452 12:12:20.156768 24 : 4253, 4027
7453 12:12:20.160035 28 : 4253, 4026
7454 12:12:20.160606 32 : 4252, 4027
7455 12:12:20.162720 36 : 4254, 4029
7456 12:12:20.163189 40 : 4363, 4137
7457 12:12:20.165834 44 : 4252, 4027
7458 12:12:20.166409 48 : 4253, 4026
7459 12:12:20.169256 52 : 4252, 4027
7460 12:12:20.169722 56 : 4255, 4029
7461 12:12:20.170096 60 : 4252, 4027
7462 12:12:20.172166 64 : 4363, 4138
7463 12:12:20.172681 68 : 4360, 4137
7464 12:12:20.175578 72 : 4250, 4027
7465 12:12:20.176069 76 : 4253, 4027
7466 12:12:20.179107 80 : 4250, 4026
7467 12:12:20.179719 84 : 4250, 4027
7468 12:12:20.182180 88 : 4252, 4029
7469 12:12:20.182647 92 : 4361, 555
7470 12:12:20.183023 96 : 4249, 0
7471 12:12:20.186503 100 : 4361, 0
7472 12:12:20.187035 104 : 4360, 0
7473 12:12:20.187380 108 : 4361, 0
7474 12:12:20.189822 112 : 4250, 0
7475 12:12:20.190247 116 : 4250, 0
7476 12:12:20.192167 120 : 4250, 0
7477 12:12:20.192593 124 : 4250, 0
7478 12:12:20.192933 128 : 4250, 0
7479 12:12:20.195751 132 : 4250, 0
7480 12:12:20.196175 136 : 4253, 0
7481 12:12:20.199215 140 : 4250, 0
7482 12:12:20.199788 144 : 4250, 0
7483 12:12:20.200134 148 : 4252, 0
7484 12:12:20.202943 152 : 4361, 0
7485 12:12:20.203475 156 : 4250, 0
7486 12:12:20.205624 160 : 4361, 0
7487 12:12:20.206047 164 : 4250, 0
7488 12:12:20.206381 168 : 4250, 0
7489 12:12:20.209399 172 : 4250, 0
7490 12:12:20.209951 176 : 4250, 0
7491 12:12:20.212187 180 : 4250, 0
7492 12:12:20.212614 184 : 4250, 0
7493 12:12:20.212953 188 : 4253, 0
7494 12:12:20.216238 192 : 4250, 0
7495 12:12:20.216662 196 : 4361, 0
7496 12:12:20.218498 200 : 4250, 0
7497 12:12:20.218920 204 : 4361, 0
7498 12:12:20.219259 208 : 4360, 0
7499 12:12:20.222067 212 : 4363, 0
7500 12:12:20.222494 216 : 4250, 0
7501 12:12:20.222831 220 : 4249, 0
7502 12:12:20.225709 224 : 4250, 421
7503 12:12:20.226240 228 : 4250, 3709
7504 12:12:20.228920 232 : 4250, 4027
7505 12:12:20.229449 236 : 4360, 4137
7506 12:12:20.232571 240 : 4250, 4027
7507 12:12:20.233100 244 : 4250, 4027
7508 12:12:20.235372 248 : 4250, 4027
7509 12:12:20.235938 252 : 4252, 4029
7510 12:12:20.238309 256 : 4250, 4026
7511 12:12:20.238836 260 : 4250, 4027
7512 12:12:20.241912 264 : 4360, 4138
7513 12:12:20.242446 268 : 4250, 4027
7514 12:12:20.245288 272 : 4250, 4026
7515 12:12:20.245710 276 : 4361, 4137
7516 12:12:20.248046 280 : 4250, 4027
7517 12:12:20.248470 284 : 4250, 4027
7518 12:12:20.248809 288 : 4363, 4140
7519 12:12:20.252199 292 : 4250, 4026
7520 12:12:20.252731 296 : 4250, 4027
7521 12:12:20.254821 300 : 4249, 4027
7522 12:12:20.255355 304 : 4252, 4029
7523 12:12:20.258468 308 : 4250, 4026
7524 12:12:20.258999 312 : 4250, 4027
7525 12:12:20.261655 316 : 4360, 4138
7526 12:12:20.262220 320 : 4249, 4027
7527 12:12:20.264412 324 : 4250, 4026
7528 12:12:20.264839 328 : 4361, 4137
7529 12:12:20.268061 332 : 4250, 4027
7530 12:12:20.268591 336 : 4250, 3729
7531 12:12:20.271115 340 : 4363, 1965
7532 12:12:20.271594
7533 12:12:20.272006 MIOCK jitter meter ch=0
7534 12:12:20.272325
7535 12:12:20.274137 1T = (340-92) = 248 dly cells
7536 12:12:20.281135 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7537 12:12:20.281575 ==
7538 12:12:20.284263 Dram Type= 6, Freq= 0, CH_0, rank 0
7539 12:12:20.287787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7540 12:12:20.288206 ==
7541 12:12:20.294488 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7542 12:12:20.297743 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7543 12:12:20.303993 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7544 12:12:20.307331 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7545 12:12:20.317729 [CA 0] Center 43 (13~74) winsize 62
7546 12:12:20.320571 [CA 1] Center 43 (13~74) winsize 62
7547 12:12:20.324683 [CA 2] Center 39 (10~69) winsize 60
7548 12:12:20.327982 [CA 3] Center 39 (9~69) winsize 61
7549 12:12:20.331403 [CA 4] Center 37 (8~66) winsize 59
7550 12:12:20.334802 [CA 5] Center 36 (7~66) winsize 60
7551 12:12:20.335378
7552 12:12:20.338027 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7553 12:12:20.338597
7554 12:12:20.343846 [CATrainingPosCal] consider 1 rank data
7555 12:12:20.344323 u2DelayCellTimex100 = 262/100 ps
7556 12:12:20.350763 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7557 12:12:20.353886 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7558 12:12:20.357300 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7559 12:12:20.360926 CA3 delay=39 (9~69),Diff = 3 PI (11 cell)
7560 12:12:20.364123 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7561 12:12:20.366642 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7562 12:12:20.367063
7563 12:12:20.370028 CA PerBit enable=1, Macro0, CA PI delay=36
7564 12:12:20.370619
7565 12:12:20.373361 [CBTSetCACLKResult] CA Dly = 36
7566 12:12:20.376759 CS Dly: 12 (0~43)
7567 12:12:20.380116 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7568 12:12:20.383923 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7569 12:12:20.384498 ==
7570 12:12:20.386522 Dram Type= 6, Freq= 0, CH_0, rank 1
7571 12:12:20.392711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7572 12:12:20.393158 ==
7573 12:12:20.397198 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7574 12:12:20.402923 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7575 12:12:20.406185 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7576 12:12:20.412589 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7577 12:12:20.421207 [CA 0] Center 43 (13~74) winsize 62
7578 12:12:20.424267 [CA 1] Center 44 (14~74) winsize 61
7579 12:12:20.427581 [CA 2] Center 38 (9~68) winsize 60
7580 12:12:20.431249 [CA 3] Center 38 (9~68) winsize 60
7581 12:12:20.434091 [CA 4] Center 36 (7~66) winsize 60
7582 12:12:20.437883 [CA 5] Center 36 (6~66) winsize 61
7583 12:12:20.438399
7584 12:12:20.441005 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7585 12:12:20.441486
7586 12:12:20.447666 [CATrainingPosCal] consider 2 rank data
7587 12:12:20.448283 u2DelayCellTimex100 = 262/100 ps
7588 12:12:20.453762 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7589 12:12:20.457172 CA1 delay=44 (14~74),Diff = 8 PI (29 cell)
7590 12:12:20.460346 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7591 12:12:20.463439 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7592 12:12:20.467169 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7593 12:12:20.470614 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7594 12:12:20.471125
7595 12:12:20.473557 CA PerBit enable=1, Macro0, CA PI delay=36
7596 12:12:20.474076
7597 12:12:20.477182 [CBTSetCACLKResult] CA Dly = 36
7598 12:12:20.480466 CS Dly: 12 (0~44)
7599 12:12:20.483287 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7600 12:12:20.486577 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7601 12:12:20.487089
7602 12:12:20.489829 ----->DramcWriteLeveling(PI) begin...
7603 12:12:20.493305 ==
7604 12:12:20.493824 Dram Type= 6, Freq= 0, CH_0, rank 0
7605 12:12:20.500029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7606 12:12:20.500541 ==
7607 12:12:20.503269 Write leveling (Byte 0): 35 => 35
7608 12:12:20.506640 Write leveling (Byte 1): 26 => 26
7609 12:12:20.510251 DramcWriteLeveling(PI) end<-----
7610 12:12:20.510767
7611 12:12:20.511108 ==
7612 12:12:20.513908 Dram Type= 6, Freq= 0, CH_0, rank 0
7613 12:12:20.516511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7614 12:12:20.516937 ==
7615 12:12:20.519650 [Gating] SW mode calibration
7616 12:12:20.526184 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7617 12:12:20.532877 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7618 12:12:20.536905 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 12:12:20.539614 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 12:12:20.546827 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 12:12:20.549853 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7622 12:12:20.552708 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7623 12:12:20.559534 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (1 1) (1 1)
7624 12:12:20.563169 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7625 12:12:20.566244 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7626 12:12:20.570176 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7627 12:12:20.576200 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7628 12:12:20.579526 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7629 12:12:20.582641 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
7630 12:12:20.588954 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7631 12:12:20.592282 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7632 12:12:20.598821 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
7633 12:12:20.602024 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 12:12:20.606219 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7635 12:12:20.612172 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 12:12:20.615582 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 12:12:20.618589 1 6 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (1 1)
7638 12:12:20.625369 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7639 12:12:20.628570 1 6 20 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
7640 12:12:20.631741 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
7641 12:12:20.635569 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 12:12:20.641815 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 12:12:20.645636 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 12:12:20.648495 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7645 12:12:20.655429 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7646 12:12:20.658613 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7647 12:12:20.661618 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7648 12:12:20.668860 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 12:12:20.671741 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 12:12:20.674834 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 12:12:20.681590 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 12:12:20.685160 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 12:12:20.687985 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 12:12:20.695617 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 12:12:20.698125 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 12:12:20.701089 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 12:12:20.708216 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 12:12:20.711317 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 12:12:20.714705 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 12:12:20.721394 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7661 12:12:20.725194 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7662 12:12:20.727791 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7663 12:12:20.731439 Total UI for P1: 0, mck2ui 16
7664 12:12:20.734599 best dqsien dly found for B0: ( 1, 9, 10)
7665 12:12:20.741397 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7666 12:12:20.744121 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7667 12:12:20.747759 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7668 12:12:20.750965 Total UI for P1: 0, mck2ui 16
7669 12:12:20.754018 best dqsien dly found for B1: ( 1, 9, 22)
7670 12:12:20.757529 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7671 12:12:20.761782 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7672 12:12:20.764226
7673 12:12:20.767380 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7674 12:12:20.771234 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7675 12:12:20.773986 [Gating] SW calibration Done
7676 12:12:20.774449 ==
7677 12:12:20.777753 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 12:12:20.781177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 12:12:20.781695 ==
7680 12:12:20.783882 RX Vref Scan: 0
7681 12:12:20.784303
7682 12:12:20.784639 RX Vref 0 -> 0, step: 1
7683 12:12:20.784951
7684 12:12:20.787306 RX Delay 0 -> 252, step: 8
7685 12:12:20.790458 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7686 12:12:20.794104 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7687 12:12:20.800700 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7688 12:12:20.803617 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7689 12:12:20.807209 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7690 12:12:20.811158 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7691 12:12:20.814255 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7692 12:12:20.820502 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7693 12:12:20.824202 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7694 12:12:20.827845 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7695 12:12:20.831029 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7696 12:12:20.836813 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7697 12:12:20.839826 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7698 12:12:20.843714 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7699 12:12:20.846534 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7700 12:12:20.850241 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7701 12:12:20.853747 ==
7702 12:12:20.856697 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 12:12:20.860292 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 12:12:20.860800 ==
7705 12:12:20.861145 DQS Delay:
7706 12:12:20.863901 DQS0 = 0, DQS1 = 0
7707 12:12:20.864428 DQM Delay:
7708 12:12:20.866817 DQM0 = 136, DQM1 = 126
7709 12:12:20.867335 DQ Delay:
7710 12:12:20.869892 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7711 12:12:20.873775 DQ4 =135, DQ5 =123, DQ6 =147, DQ7 =147
7712 12:12:20.876497 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7713 12:12:20.880380 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7714 12:12:20.880802
7715 12:12:20.881137
7716 12:12:20.881450 ==
7717 12:12:20.883039 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 12:12:20.890061 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 12:12:20.890580 ==
7720 12:12:20.891027
7721 12:12:20.891442
7722 12:12:20.891929 TX Vref Scan disable
7723 12:12:20.893428 == TX Byte 0 ==
7724 12:12:20.896401 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7725 12:12:20.903843 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7726 12:12:20.904377 == TX Byte 1 ==
7727 12:12:20.906558 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7728 12:12:20.912669 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7729 12:12:20.913107 ==
7730 12:12:20.915880 Dram Type= 6, Freq= 0, CH_0, rank 0
7731 12:12:20.919367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7732 12:12:20.919843 ==
7733 12:12:20.934001
7734 12:12:20.937483 TX Vref early break, caculate TX vref
7735 12:12:20.941028 TX Vref=16, minBit 4, minWin=22, winSum=368
7736 12:12:20.944049 TX Vref=18, minBit 0, minWin=23, winSum=377
7737 12:12:20.947298 TX Vref=20, minBit 1, minWin=23, winSum=386
7738 12:12:20.951029 TX Vref=22, minBit 1, minWin=24, winSum=398
7739 12:12:20.954139 TX Vref=24, minBit 0, minWin=25, winSum=411
7740 12:12:20.960637 TX Vref=26, minBit 0, minWin=25, winSum=411
7741 12:12:20.964096 TX Vref=28, minBit 0, minWin=24, winSum=408
7742 12:12:20.967995 TX Vref=30, minBit 0, minWin=25, winSum=406
7743 12:12:20.970933 TX Vref=32, minBit 7, minWin=23, winSum=401
7744 12:12:20.974218 TX Vref=34, minBit 4, minWin=23, winSum=390
7745 12:12:20.976729 TX Vref=36, minBit 4, minWin=22, winSum=379
7746 12:12:20.983954 [TxChooseVref] Worse bit 0, Min win 25, Win sum 411, Final Vref 24
7747 12:12:20.984533
7748 12:12:20.987031 Final TX Range 0 Vref 24
7749 12:12:20.987588
7750 12:12:20.988031 ==
7751 12:12:20.990270 Dram Type= 6, Freq= 0, CH_0, rank 0
7752 12:12:20.994253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7753 12:12:20.994778 ==
7754 12:12:20.997621
7755 12:12:20.998177
7756 12:12:20.998542 TX Vref Scan disable
7757 12:12:21.003495 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7758 12:12:21.004120 == TX Byte 0 ==
7759 12:12:21.006598 u2DelayCellOfst[0]=14 cells (4 PI)
7760 12:12:21.010450 u2DelayCellOfst[1]=18 cells (5 PI)
7761 12:12:21.013923 u2DelayCellOfst[2]=14 cells (4 PI)
7762 12:12:21.016305 u2DelayCellOfst[3]=14 cells (4 PI)
7763 12:12:21.020462 u2DelayCellOfst[4]=7 cells (2 PI)
7764 12:12:21.023064 u2DelayCellOfst[5]=0 cells (0 PI)
7765 12:12:21.026660 u2DelayCellOfst[6]=18 cells (5 PI)
7766 12:12:21.029554 u2DelayCellOfst[7]=18 cells (5 PI)
7767 12:12:21.033516 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7768 12:12:21.036380 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7769 12:12:21.039760 == TX Byte 1 ==
7770 12:12:21.042716 u2DelayCellOfst[8]=0 cells (0 PI)
7771 12:12:21.046721 u2DelayCellOfst[9]=0 cells (0 PI)
7772 12:12:21.050464 u2DelayCellOfst[10]=7 cells (2 PI)
7773 12:12:21.053284 u2DelayCellOfst[11]=3 cells (1 PI)
7774 12:12:21.056229 u2DelayCellOfst[12]=11 cells (3 PI)
7775 12:12:21.059577 u2DelayCellOfst[13]=14 cells (4 PI)
7776 12:12:21.063144 u2DelayCellOfst[14]=14 cells (4 PI)
7777 12:12:21.063749 u2DelayCellOfst[15]=11 cells (3 PI)
7778 12:12:21.069354 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7779 12:12:21.073414 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7780 12:12:21.076106 DramC Write-DBI on
7781 12:12:21.076665 ==
7782 12:12:21.079103 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 12:12:21.082379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 12:12:21.082843 ==
7785 12:12:21.083206
7786 12:12:21.083543
7787 12:12:21.085659 TX Vref Scan disable
7788 12:12:21.086130 == TX Byte 0 ==
7789 12:12:21.092351 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7790 12:12:21.092914 == TX Byte 1 ==
7791 12:12:21.099052 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7792 12:12:21.099641 DramC Write-DBI off
7793 12:12:21.100115
7794 12:12:21.100470 [DATLAT]
7795 12:12:21.102205 Freq=1600, CH0 RK0
7796 12:12:21.102668
7797 12:12:21.105331 DATLAT Default: 0xf
7798 12:12:21.105797 0, 0xFFFF, sum = 0
7799 12:12:21.108712 1, 0xFFFF, sum = 0
7800 12:12:21.109144 2, 0xFFFF, sum = 0
7801 12:12:21.112163 3, 0xFFFF, sum = 0
7802 12:12:21.112591 4, 0xFFFF, sum = 0
7803 12:12:21.115658 5, 0xFFFF, sum = 0
7804 12:12:21.116127 6, 0xFFFF, sum = 0
7805 12:12:21.119087 7, 0xFFFF, sum = 0
7806 12:12:21.119778 8, 0xFFFF, sum = 0
7807 12:12:21.121858 9, 0xFFFF, sum = 0
7808 12:12:21.122287 10, 0xFFFF, sum = 0
7809 12:12:21.125546 11, 0xFFFF, sum = 0
7810 12:12:21.126073 12, 0xFFFF, sum = 0
7811 12:12:21.128887 13, 0xFFFF, sum = 0
7812 12:12:21.129315 14, 0x0, sum = 1
7813 12:12:21.132103 15, 0x0, sum = 2
7814 12:12:21.132540 16, 0x0, sum = 3
7815 12:12:21.134959 17, 0x0, sum = 4
7816 12:12:21.135380 best_step = 15
7817 12:12:21.135740
7818 12:12:21.136054 ==
7819 12:12:21.138430 Dram Type= 6, Freq= 0, CH_0, rank 0
7820 12:12:21.145329 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7821 12:12:21.145894 ==
7822 12:12:21.146266 RX Vref Scan: 1
7823 12:12:21.146576
7824 12:12:21.148276 Set Vref Range= 24 -> 127
7825 12:12:21.148733
7826 12:12:21.152395 RX Vref 24 -> 127, step: 1
7827 12:12:21.152816
7828 12:12:21.154817 RX Delay 11 -> 252, step: 4
7829 12:12:21.155409
7830 12:12:21.158379 Set Vref, RX VrefLevel [Byte0]: 24
7831 12:12:21.161258 [Byte1]: 24
7832 12:12:21.161675
7833 12:12:21.164650 Set Vref, RX VrefLevel [Byte0]: 25
7834 12:12:21.168117 [Byte1]: 25
7835 12:12:21.168634
7836 12:12:21.171889 Set Vref, RX VrefLevel [Byte0]: 26
7837 12:12:21.174699 [Byte1]: 26
7838 12:12:21.177895
7839 12:12:21.178410 Set Vref, RX VrefLevel [Byte0]: 27
7840 12:12:21.181166 [Byte1]: 27
7841 12:12:21.185370
7842 12:12:21.185883 Set Vref, RX VrefLevel [Byte0]: 28
7843 12:12:21.188787 [Byte1]: 28
7844 12:12:21.193818
7845 12:12:21.194337 Set Vref, RX VrefLevel [Byte0]: 29
7846 12:12:21.196560 [Byte1]: 29
7847 12:12:21.201157
7848 12:12:21.201672 Set Vref, RX VrefLevel [Byte0]: 30
7849 12:12:21.203925 [Byte1]: 30
7850 12:12:21.208369
7851 12:12:21.208921 Set Vref, RX VrefLevel [Byte0]: 31
7852 12:12:21.211384 [Byte1]: 31
7853 12:12:21.216336
7854 12:12:21.216891 Set Vref, RX VrefLevel [Byte0]: 32
7855 12:12:21.219352 [Byte1]: 32
7856 12:12:21.223817
7857 12:12:21.224367 Set Vref, RX VrefLevel [Byte0]: 33
7858 12:12:21.227382 [Byte1]: 33
7859 12:12:21.231171
7860 12:12:21.231792 Set Vref, RX VrefLevel [Byte0]: 34
7861 12:12:21.234843 [Byte1]: 34
7862 12:12:21.238995
7863 12:12:21.239559 Set Vref, RX VrefLevel [Byte0]: 35
7864 12:12:21.241924 [Byte1]: 35
7865 12:12:21.246342
7866 12:12:21.246819 Set Vref, RX VrefLevel [Byte0]: 36
7867 12:12:21.249314 [Byte1]: 36
7868 12:12:21.254192
7869 12:12:21.254766 Set Vref, RX VrefLevel [Byte0]: 37
7870 12:12:21.257572 [Byte1]: 37
7871 12:12:21.261810
7872 12:12:21.262382 Set Vref, RX VrefLevel [Byte0]: 38
7873 12:12:21.264676 [Byte1]: 38
7874 12:12:21.269819
7875 12:12:21.270399 Set Vref, RX VrefLevel [Byte0]: 39
7876 12:12:21.272548 [Byte1]: 39
7877 12:12:21.277294
7878 12:12:21.277862 Set Vref, RX VrefLevel [Byte0]: 40
7879 12:12:21.280402 [Byte1]: 40
7880 12:12:21.284865
7881 12:12:21.285430 Set Vref, RX VrefLevel [Byte0]: 41
7882 12:12:21.288128 [Byte1]: 41
7883 12:12:21.292340
7884 12:12:21.292904 Set Vref, RX VrefLevel [Byte0]: 42
7885 12:12:21.295513 [Byte1]: 42
7886 12:12:21.300036
7887 12:12:21.300608 Set Vref, RX VrefLevel [Byte0]: 43
7888 12:12:21.303495 [Byte1]: 43
7889 12:12:21.307636
7890 12:12:21.308210 Set Vref, RX VrefLevel [Byte0]: 44
7891 12:12:21.310732 [Byte1]: 44
7892 12:12:21.314836
7893 12:12:21.315351 Set Vref, RX VrefLevel [Byte0]: 45
7894 12:12:21.319074 [Byte1]: 45
7895 12:12:21.322602
7896 12:12:21.323148 Set Vref, RX VrefLevel [Byte0]: 46
7897 12:12:21.326105 [Byte1]: 46
7898 12:12:21.330200
7899 12:12:21.330672 Set Vref, RX VrefLevel [Byte0]: 47
7900 12:12:21.333611 [Byte1]: 47
7901 12:12:21.338398
7902 12:12:21.338914 Set Vref, RX VrefLevel [Byte0]: 48
7903 12:12:21.341554 [Byte1]: 48
7904 12:12:21.345480
7905 12:12:21.346047 Set Vref, RX VrefLevel [Byte0]: 49
7906 12:12:21.348527 [Byte1]: 49
7907 12:12:21.352957
7908 12:12:21.353525 Set Vref, RX VrefLevel [Byte0]: 50
7909 12:12:21.356620 [Byte1]: 50
7910 12:12:21.360800
7911 12:12:21.361270 Set Vref, RX VrefLevel [Byte0]: 51
7912 12:12:21.363577 [Byte1]: 51
7913 12:12:21.368078
7914 12:12:21.368652 Set Vref, RX VrefLevel [Byte0]: 52
7915 12:12:21.372177 [Byte1]: 52
7916 12:12:21.376099
7917 12:12:21.376577 Set Vref, RX VrefLevel [Byte0]: 53
7918 12:12:21.379125 [Byte1]: 53
7919 12:12:21.383651
7920 12:12:21.384263 Set Vref, RX VrefLevel [Byte0]: 54
7921 12:12:21.386950 [Byte1]: 54
7922 12:12:21.390996
7923 12:12:21.391529 Set Vref, RX VrefLevel [Byte0]: 55
7924 12:12:21.394366 [Byte1]: 55
7925 12:12:21.398489
7926 12:12:21.398920 Set Vref, RX VrefLevel [Byte0]: 56
7927 12:12:21.402361 [Byte1]: 56
7928 12:12:21.406182
7929 12:12:21.406618 Set Vref, RX VrefLevel [Byte0]: 57
7930 12:12:21.409813 [Byte1]: 57
7931 12:12:21.414135
7932 12:12:21.414598 Set Vref, RX VrefLevel [Byte0]: 58
7933 12:12:21.417504 [Byte1]: 58
7934 12:12:21.421551
7935 12:12:21.421980 Set Vref, RX VrefLevel [Byte0]: 59
7936 12:12:21.424613 [Byte1]: 59
7937 12:12:21.429364
7938 12:12:21.429899 Set Vref, RX VrefLevel [Byte0]: 60
7939 12:12:21.432324 [Byte1]: 60
7940 12:12:21.436490
7941 12:12:21.436921 Set Vref, RX VrefLevel [Byte0]: 61
7942 12:12:21.440702 [Byte1]: 61
7943 12:12:21.444282
7944 12:12:21.444843 Set Vref, RX VrefLevel [Byte0]: 62
7945 12:12:21.447567 [Byte1]: 62
7946 12:12:21.452849
7947 12:12:21.453383 Set Vref, RX VrefLevel [Byte0]: 63
7948 12:12:21.455576 [Byte1]: 63
7949 12:12:21.460442
7950 12:12:21.460970 Set Vref, RX VrefLevel [Byte0]: 64
7951 12:12:21.463036 [Byte1]: 64
7952 12:12:21.467171
7953 12:12:21.467739 Set Vref, RX VrefLevel [Byte0]: 65
7954 12:12:21.470284 [Byte1]: 65
7955 12:12:21.475505
7956 12:12:21.476096 Set Vref, RX VrefLevel [Byte0]: 66
7957 12:12:21.478738 [Byte1]: 66
7958 12:12:21.482862
7959 12:12:21.483390 Set Vref, RX VrefLevel [Byte0]: 67
7960 12:12:21.485874 [Byte1]: 67
7961 12:12:21.489653
7962 12:12:21.490203 Set Vref, RX VrefLevel [Byte0]: 68
7963 12:12:21.493184 [Byte1]: 68
7964 12:12:21.497897
7965 12:12:21.498413 Set Vref, RX VrefLevel [Byte0]: 69
7966 12:12:21.501042 [Byte1]: 69
7967 12:12:21.505947
7968 12:12:21.506460 Set Vref, RX VrefLevel [Byte0]: 70
7969 12:12:21.509011 [Byte1]: 70
7970 12:12:21.512687
7971 12:12:21.513102 Set Vref, RX VrefLevel [Byte0]: 71
7972 12:12:21.515853 [Byte1]: 71
7973 12:12:21.520501
7974 12:12:21.521018 Set Vref, RX VrefLevel [Byte0]: 72
7975 12:12:21.524061 [Byte1]: 72
7976 12:12:21.528427
7977 12:12:21.528941 Set Vref, RX VrefLevel [Byte0]: 73
7978 12:12:21.532082 [Byte1]: 73
7979 12:12:21.535548
7980 12:12:21.536131 Set Vref, RX VrefLevel [Byte0]: 74
7981 12:12:21.538959 [Byte1]: 74
7982 12:12:21.543510
7983 12:12:21.544085 Set Vref, RX VrefLevel [Byte0]: 75
7984 12:12:21.546845 [Byte1]: 75
7985 12:12:21.550732
7986 12:12:21.551251 Set Vref, RX VrefLevel [Byte0]: 76
7987 12:12:21.554167 [Byte1]: 76
7988 12:12:21.558371
7989 12:12:21.558887 Set Vref, RX VrefLevel [Byte0]: 77
7990 12:12:21.561800 [Byte1]: 77
7991 12:12:21.566277
7992 12:12:21.566801 Set Vref, RX VrefLevel [Byte0]: 78
7993 12:12:21.569734 [Byte1]: 78
7994 12:12:21.574078
7995 12:12:21.574495 Set Vref, RX VrefLevel [Byte0]: 79
7996 12:12:21.576753 [Byte1]: 79
7997 12:12:21.581532
7998 12:12:21.582069 Set Vref, RX VrefLevel [Byte0]: 80
7999 12:12:21.585035 [Byte1]: 80
8000 12:12:21.588783
8001 12:12:21.589201 Final RX Vref Byte 0 = 67 to rank0
8002 12:12:21.592402 Final RX Vref Byte 1 = 60 to rank0
8003 12:12:21.595422 Final RX Vref Byte 0 = 67 to rank1
8004 12:12:21.599233 Final RX Vref Byte 1 = 60 to rank1==
8005 12:12:21.602581 Dram Type= 6, Freq= 0, CH_0, rank 0
8006 12:12:21.609183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 12:12:21.609723 ==
8008 12:12:21.610066 DQS Delay:
8009 12:12:21.610378 DQS0 = 0, DQS1 = 0
8010 12:12:21.612562 DQM Delay:
8011 12:12:21.613012 DQM0 = 133, DQM1 = 123
8012 12:12:21.615560 DQ Delay:
8013 12:12:21.619574 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
8014 12:12:21.622130 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8015 12:12:21.625425 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8016 12:12:21.628764 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =128
8017 12:12:21.629325
8018 12:12:21.629695
8019 12:12:21.630153
8020 12:12:21.632332 [DramC_TX_OE_Calibration] TA2
8021 12:12:21.635613 Original DQ_B0 (3 6) =30, OEN = 27
8022 12:12:21.638937 Original DQ_B1 (3 6) =30, OEN = 27
8023 12:12:21.642485 24, 0x0, End_B0=24 End_B1=24
8024 12:12:21.643051 25, 0x0, End_B0=25 End_B1=25
8025 12:12:21.644902 26, 0x0, End_B0=26 End_B1=26
8026 12:12:21.648449 27, 0x0, End_B0=27 End_B1=27
8027 12:12:21.652372 28, 0x0, End_B0=28 End_B1=28
8028 12:12:21.655194 29, 0x0, End_B0=29 End_B1=29
8029 12:12:21.656005 30, 0x0, End_B0=30 End_B1=30
8030 12:12:21.658106 31, 0x4141, End_B0=30 End_B1=30
8031 12:12:21.661794 Byte0 end_step=30 best_step=27
8032 12:12:21.664771 Byte1 end_step=30 best_step=27
8033 12:12:21.668299 Byte0 TX OE(2T, 0.5T) = (3, 3)
8034 12:12:21.671268 Byte1 TX OE(2T, 0.5T) = (3, 3)
8035 12:12:21.671720
8036 12:12:21.672064
8037 12:12:21.678718 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 394 ps
8038 12:12:21.681730 CH0 RK0: MR19=303, MR18=1F10
8039 12:12:21.688264 CH0_RK0: MR19=0x303, MR18=0x1F10, DQSOSC=394, MR23=63, INC=23, DEC=15
8040 12:12:21.688691
8041 12:12:21.691056 ----->DramcWriteLeveling(PI) begin...
8042 12:12:21.691485 ==
8043 12:12:21.694372 Dram Type= 6, Freq= 0, CH_0, rank 1
8044 12:12:21.698501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8045 12:12:21.699017 ==
8046 12:12:21.700820 Write leveling (Byte 0): 34 => 34
8047 12:12:21.704586 Write leveling (Byte 1): 27 => 27
8048 12:12:21.707804 DramcWriteLeveling(PI) end<-----
8049 12:12:21.708225
8050 12:12:21.708558 ==
8051 12:12:21.711215 Dram Type= 6, Freq= 0, CH_0, rank 1
8052 12:12:21.714395 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8053 12:12:21.717307 ==
8054 12:12:21.717940 [Gating] SW mode calibration
8055 12:12:21.727851 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8056 12:12:21.730755 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8057 12:12:21.734176 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 12:12:21.741059 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8059 12:12:21.744276 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 12:12:21.747039 1 4 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8061 12:12:21.753770 1 4 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8062 12:12:21.756721 1 4 20 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
8063 12:12:21.760585 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8064 12:12:21.766751 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 12:12:21.770753 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 12:12:21.774343 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 12:12:21.780180 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 12:12:21.783904 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8069 12:12:21.787347 1 5 16 | B1->B0 | 3434 2626 | 1 1 | (1 0) (1 0)
8070 12:12:21.793950 1 5 20 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8071 12:12:21.796955 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
8072 12:12:21.800202 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 12:12:21.807130 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 12:12:21.810554 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 12:12:21.813491 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 12:12:21.819742 1 6 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
8077 12:12:21.822847 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
8078 12:12:21.826202 1 6 20 | B1->B0 | 3030 4646 | 1 0 | (0 0) (0 0)
8079 12:12:21.833204 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 12:12:21.836039 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 12:12:21.839780 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 12:12:21.846569 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 12:12:21.849298 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8084 12:12:21.853383 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8085 12:12:21.859714 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8086 12:12:21.863580 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8087 12:12:21.865752 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 12:12:21.872714 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 12:12:21.876120 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 12:12:21.879119 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 12:12:21.885956 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 12:12:21.888810 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 12:12:21.892959 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 12:12:21.899253 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 12:12:21.902203 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 12:12:21.906260 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 12:12:21.911944 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 12:12:21.915560 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 12:12:21.918238 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 12:12:21.924853 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8101 12:12:21.928284 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8102 12:12:21.931775 Total UI for P1: 0, mck2ui 16
8103 12:12:21.935707 best dqsien dly found for B0: ( 1, 9, 12)
8104 12:12:21.939047 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8105 12:12:21.945044 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8106 12:12:21.948587 Total UI for P1: 0, mck2ui 16
8107 12:12:21.951552 best dqsien dly found for B1: ( 1, 9, 18)
8108 12:12:21.954561 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8109 12:12:21.957974 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8110 12:12:21.958443
8111 12:12:21.961135 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8112 12:12:21.964843 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8113 12:12:21.968334 [Gating] SW calibration Done
8114 12:12:21.968892 ==
8115 12:12:21.971301 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 12:12:21.974916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 12:12:21.975479 ==
8118 12:12:21.977748 RX Vref Scan: 0
8119 12:12:21.978327
8120 12:12:21.980937 RX Vref 0 -> 0, step: 1
8121 12:12:21.981405
8122 12:12:21.981776 RX Delay 0 -> 252, step: 8
8123 12:12:21.987549 iDelay=208, Bit 0, Center 131 (72 ~ 191) 120
8124 12:12:21.991268 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8125 12:12:21.994536 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8126 12:12:21.997658 iDelay=208, Bit 3, Center 127 (72 ~ 183) 112
8127 12:12:22.000682 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8128 12:12:22.007544 iDelay=208, Bit 5, Center 123 (64 ~ 183) 120
8129 12:12:22.010987 iDelay=208, Bit 6, Center 139 (80 ~ 199) 120
8130 12:12:22.014379 iDelay=208, Bit 7, Center 147 (88 ~ 207) 120
8131 12:12:22.017217 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8132 12:12:22.020374 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8133 12:12:22.027181 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8134 12:12:22.030661 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8135 12:12:22.034209 iDelay=208, Bit 12, Center 131 (72 ~ 191) 120
8136 12:12:22.038971 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8137 12:12:22.044036 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8138 12:12:22.047063 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8139 12:12:22.047533 ==
8140 12:12:22.050508 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 12:12:22.053668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 12:12:22.054138 ==
8143 12:12:22.057476 DQS Delay:
8144 12:12:22.058039 DQS0 = 0, DQS1 = 0
8145 12:12:22.058410 DQM Delay:
8146 12:12:22.059958 DQM0 = 133, DQM1 = 127
8147 12:12:22.060495 DQ Delay:
8148 12:12:22.063574 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8149 12:12:22.067282 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =147
8150 12:12:22.073880 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8151 12:12:22.076733 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8152 12:12:22.077197
8153 12:12:22.077564
8154 12:12:22.077907 ==
8155 12:12:22.080343 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 12:12:22.083100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 12:12:22.083661 ==
8158 12:12:22.084106
8159 12:12:22.084655
8160 12:12:22.087022 TX Vref Scan disable
8161 12:12:22.089951 == TX Byte 0 ==
8162 12:12:22.093094 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8163 12:12:22.096758 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8164 12:12:22.099981 == TX Byte 1 ==
8165 12:12:22.103534 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8166 12:12:22.106761 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8167 12:12:22.107321 ==
8168 12:12:22.109703 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 12:12:22.112598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 12:12:22.116231 ==
8171 12:12:22.127933
8172 12:12:22.131267 TX Vref early break, caculate TX vref
8173 12:12:22.135105 TX Vref=16, minBit 1, minWin=22, winSum=376
8174 12:12:22.138365 TX Vref=18, minBit 1, minWin=22, winSum=384
8175 12:12:22.140947 TX Vref=20, minBit 1, minWin=24, winSum=393
8176 12:12:22.144821 TX Vref=22, minBit 1, minWin=23, winSum=399
8177 12:12:22.148528 TX Vref=24, minBit 1, minWin=24, winSum=406
8178 12:12:22.154708 TX Vref=26, minBit 0, minWin=24, winSum=409
8179 12:12:22.157722 TX Vref=28, minBit 0, minWin=24, winSum=406
8180 12:12:22.160817 TX Vref=30, minBit 1, minWin=23, winSum=400
8181 12:12:22.164588 TX Vref=32, minBit 0, minWin=24, winSum=392
8182 12:12:22.168064 TX Vref=34, minBit 1, minWin=23, winSum=383
8183 12:12:22.174693 [TxChooseVref] Worse bit 0, Min win 24, Win sum 409, Final Vref 26
8184 12:12:22.175255
8185 12:12:22.177497 Final TX Range 0 Vref 26
8186 12:12:22.177962
8187 12:12:22.178330 ==
8188 12:12:22.181136 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 12:12:22.184261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 12:12:22.184861 ==
8191 12:12:22.185418
8192 12:12:22.185800
8193 12:12:22.188064 TX Vref Scan disable
8194 12:12:22.194113 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8195 12:12:22.194577 == TX Byte 0 ==
8196 12:12:22.197530 u2DelayCellOfst[0]=11 cells (3 PI)
8197 12:12:22.201081 u2DelayCellOfst[1]=18 cells (5 PI)
8198 12:12:22.203746 u2DelayCellOfst[2]=11 cells (3 PI)
8199 12:12:22.207643 u2DelayCellOfst[3]=14 cells (4 PI)
8200 12:12:22.210463 u2DelayCellOfst[4]=7 cells (2 PI)
8201 12:12:22.214724 u2DelayCellOfst[5]=0 cells (0 PI)
8202 12:12:22.217668 u2DelayCellOfst[6]=18 cells (5 PI)
8203 12:12:22.220367 u2DelayCellOfst[7]=18 cells (5 PI)
8204 12:12:22.224468 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8205 12:12:22.227489 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8206 12:12:22.230669 == TX Byte 1 ==
8207 12:12:22.233724 u2DelayCellOfst[8]=0 cells (0 PI)
8208 12:12:22.237532 u2DelayCellOfst[9]=3 cells (1 PI)
8209 12:12:22.238001 u2DelayCellOfst[10]=7 cells (2 PI)
8210 12:12:22.240462 u2DelayCellOfst[11]=3 cells (1 PI)
8211 12:12:22.243552 u2DelayCellOfst[12]=11 cells (3 PI)
8212 12:12:22.246896 u2DelayCellOfst[13]=11 cells (3 PI)
8213 12:12:22.250106 u2DelayCellOfst[14]=18 cells (5 PI)
8214 12:12:22.253566 u2DelayCellOfst[15]=11 cells (3 PI)
8215 12:12:22.260829 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8216 12:12:22.263385 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8217 12:12:22.263894 DramC Write-DBI on
8218 12:12:22.264272 ==
8219 12:12:22.266585 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 12:12:22.273107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 12:12:22.273666 ==
8222 12:12:22.274044
8223 12:12:22.274390
8224 12:12:22.276404 TX Vref Scan disable
8225 12:12:22.276867 == TX Byte 0 ==
8226 12:12:22.283541 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8227 12:12:22.284135 == TX Byte 1 ==
8228 12:12:22.286479 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8229 12:12:22.289721 DramC Write-DBI off
8230 12:12:22.290278
8231 12:12:22.290650 [DATLAT]
8232 12:12:22.292971 Freq=1600, CH0 RK1
8233 12:12:22.293478
8234 12:12:22.294017 DATLAT Default: 0xf
8235 12:12:22.296465 0, 0xFFFF, sum = 0
8236 12:12:22.296938 1, 0xFFFF, sum = 0
8237 12:12:22.299225 2, 0xFFFF, sum = 0
8238 12:12:22.299770 3, 0xFFFF, sum = 0
8239 12:12:22.303354 4, 0xFFFF, sum = 0
8240 12:12:22.304039 5, 0xFFFF, sum = 0
8241 12:12:22.305987 6, 0xFFFF, sum = 0
8242 12:12:22.306554 7, 0xFFFF, sum = 0
8243 12:12:22.309650 8, 0xFFFF, sum = 0
8244 12:12:22.313443 9, 0xFFFF, sum = 0
8245 12:12:22.314013 10, 0xFFFF, sum = 0
8246 12:12:22.316280 11, 0xFFFF, sum = 0
8247 12:12:22.317000 12, 0xFFFF, sum = 0
8248 12:12:22.319169 13, 0xFFFF, sum = 0
8249 12:12:22.319635 14, 0x0, sum = 1
8250 12:12:22.322589 15, 0x0, sum = 2
8251 12:12:22.323155 16, 0x0, sum = 3
8252 12:12:22.325700 17, 0x0, sum = 4
8253 12:12:22.326205 best_step = 15
8254 12:12:22.326576
8255 12:12:22.326923 ==
8256 12:12:22.328997 Dram Type= 6, Freq= 0, CH_0, rank 1
8257 12:12:22.333046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8258 12:12:22.333510 ==
8259 12:12:22.336036 RX Vref Scan: 0
8260 12:12:22.336452
8261 12:12:22.339569 RX Vref 0 -> 0, step: 1
8262 12:12:22.340137
8263 12:12:22.340477 RX Delay 11 -> 252, step: 4
8264 12:12:22.346564 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8265 12:12:22.349866 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8266 12:12:22.353667 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8267 12:12:22.356424 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8268 12:12:22.359852 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8269 12:12:22.366459 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8270 12:12:22.369823 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8271 12:12:22.372995 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8272 12:12:22.375994 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8273 12:12:22.382888 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8274 12:12:22.386134 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8275 12:12:22.389657 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8276 12:12:22.392932 iDelay=195, Bit 12, Center 130 (75 ~ 186) 112
8277 12:12:22.396435 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8278 12:12:22.402294 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8279 12:12:22.405418 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8280 12:12:22.405881 ==
8281 12:12:22.408514 Dram Type= 6, Freq= 0, CH_0, rank 1
8282 12:12:22.412228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8283 12:12:22.412691 ==
8284 12:12:22.415890 DQS Delay:
8285 12:12:22.416366 DQS0 = 0, DQS1 = 0
8286 12:12:22.418562 DQM Delay:
8287 12:12:22.419039 DQM0 = 130, DQM1 = 125
8288 12:12:22.419523 DQ Delay:
8289 12:12:22.422151 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8290 12:12:22.428695 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =140
8291 12:12:22.432006 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8292 12:12:22.435622 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8293 12:12:22.436205
8294 12:12:22.436652
8295 12:12:22.437195
8296 12:12:22.438088 [DramC_TX_OE_Calibration] TA2
8297 12:12:22.442370 Original DQ_B0 (3 6) =30, OEN = 27
8298 12:12:22.446085 Original DQ_B1 (3 6) =30, OEN = 27
8299 12:12:22.446614 24, 0x0, End_B0=24 End_B1=24
8300 12:12:22.448216 25, 0x0, End_B0=25 End_B1=25
8301 12:12:22.451475 26, 0x0, End_B0=26 End_B1=26
8302 12:12:22.455471 27, 0x0, End_B0=27 End_B1=27
8303 12:12:22.458410 28, 0x0, End_B0=28 End_B1=28
8304 12:12:22.458886 29, 0x0, End_B0=29 End_B1=29
8305 12:12:22.462216 30, 0x0, End_B0=30 End_B1=30
8306 12:12:22.465403 31, 0x4141, End_B0=30 End_B1=30
8307 12:12:22.468565 Byte0 end_step=30 best_step=27
8308 12:12:22.471620 Byte1 end_step=30 best_step=27
8309 12:12:22.475401 Byte0 TX OE(2T, 0.5T) = (3, 3)
8310 12:12:22.475944 Byte1 TX OE(2T, 0.5T) = (3, 3)
8311 12:12:22.476323
8312 12:12:22.476665
8313 12:12:22.484748 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e00, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 394 ps
8314 12:12:22.487859 CH0 RK1: MR19=303, MR18=1E00
8315 12:12:22.494859 CH0_RK1: MR19=0x303, MR18=0x1E00, DQSOSC=394, MR23=63, INC=23, DEC=15
8316 12:12:22.495381 [RxdqsGatingPostProcess] freq 1600
8317 12:12:22.501120 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8318 12:12:22.505115 best DQS0 dly(2T, 0.5T) = (1, 1)
8319 12:12:22.508228 best DQS1 dly(2T, 0.5T) = (1, 1)
8320 12:12:22.511218 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8321 12:12:22.514723 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8322 12:12:22.517715 best DQS0 dly(2T, 0.5T) = (1, 1)
8323 12:12:22.521181 best DQS1 dly(2T, 0.5T) = (1, 1)
8324 12:12:22.524812 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8325 12:12:22.527300 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8326 12:12:22.527748 Pre-setting of DQS Precalculation
8327 12:12:22.535199 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8328 12:12:22.535614 ==
8329 12:12:22.537648 Dram Type= 6, Freq= 0, CH_1, rank 0
8330 12:12:22.540837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8331 12:12:22.541359 ==
8332 12:12:22.547695 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8333 12:12:22.550917 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8334 12:12:22.557592 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8335 12:12:22.560477 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8336 12:12:22.571992 [CA 0] Center 41 (12~71) winsize 60
8337 12:12:22.574113 [CA 1] Center 42 (12~72) winsize 61
8338 12:12:22.577107 [CA 2] Center 37 (8~66) winsize 59
8339 12:12:22.580521 [CA 3] Center 36 (7~65) winsize 59
8340 12:12:22.584772 [CA 4] Center 36 (7~66) winsize 60
8341 12:12:22.587611 [CA 5] Center 36 (7~66) winsize 60
8342 12:12:22.588139
8343 12:12:22.590572 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8344 12:12:22.591127
8345 12:12:22.594276 [CATrainingPosCal] consider 1 rank data
8346 12:12:22.597123 u2DelayCellTimex100 = 262/100 ps
8347 12:12:22.600648 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8348 12:12:22.607341 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8349 12:12:22.610871 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8350 12:12:22.613283 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8351 12:12:22.617637 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8352 12:12:22.620373 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8353 12:12:22.620792
8354 12:12:22.623834 CA PerBit enable=1, Macro0, CA PI delay=36
8355 12:12:22.624341
8356 12:12:22.626602 [CBTSetCACLKResult] CA Dly = 36
8357 12:12:22.629976 CS Dly: 9 (0~40)
8358 12:12:22.633365 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8359 12:12:22.636735 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8360 12:12:22.637291 ==
8361 12:12:22.639617 Dram Type= 6, Freq= 0, CH_1, rank 1
8362 12:12:22.646494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8363 12:12:22.647057 ==
8364 12:12:22.650005 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8365 12:12:22.656575 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8366 12:12:22.659273 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8367 12:12:22.666198 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8368 12:12:22.673964 [CA 0] Center 42 (13~71) winsize 59
8369 12:12:22.677173 [CA 1] Center 43 (13~73) winsize 61
8370 12:12:22.680200 [CA 2] Center 37 (8~67) winsize 60
8371 12:12:22.683824 [CA 3] Center 37 (7~67) winsize 61
8372 12:12:22.687242 [CA 4] Center 38 (9~67) winsize 59
8373 12:12:22.690525 [CA 5] Center 37 (8~67) winsize 60
8374 12:12:22.691085
8375 12:12:22.693758 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8376 12:12:22.694362
8377 12:12:22.697085 [CATrainingPosCal] consider 2 rank data
8378 12:12:22.700264 u2DelayCellTimex100 = 262/100 ps
8379 12:12:22.707304 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8380 12:12:22.710917 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8381 12:12:22.713710 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8382 12:12:22.716636 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8383 12:12:22.720028 CA4 delay=37 (9~66),Diff = 1 PI (3 cell)
8384 12:12:22.723460 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8385 12:12:22.724062
8386 12:12:22.726868 CA PerBit enable=1, Macro0, CA PI delay=36
8387 12:12:22.727336
8388 12:12:22.730289 [CBTSetCACLKResult] CA Dly = 36
8389 12:12:22.733123 CS Dly: 10 (0~43)
8390 12:12:22.736494 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8391 12:12:22.739699 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8392 12:12:22.740160
8393 12:12:22.742906 ----->DramcWriteLeveling(PI) begin...
8394 12:12:22.743377 ==
8395 12:12:22.746475 Dram Type= 6, Freq= 0, CH_1, rank 0
8396 12:12:22.752520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8397 12:12:22.752946 ==
8398 12:12:22.756520 Write leveling (Byte 0): 23 => 23
8399 12:12:22.759237 Write leveling (Byte 1): 27 => 27
8400 12:12:22.759807 DramcWriteLeveling(PI) end<-----
8401 12:12:22.762842
8402 12:12:22.763283 ==
8403 12:12:22.765624 Dram Type= 6, Freq= 0, CH_1, rank 0
8404 12:12:22.769396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8405 12:12:22.769815 ==
8406 12:12:22.773301 [Gating] SW mode calibration
8407 12:12:22.780272 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8408 12:12:22.785414 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8409 12:12:22.788832 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 12:12:22.792416 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 12:12:22.799199 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 12:12:22.801972 1 4 12 | B1->B0 | 2929 2e2e | 0 0 | (0 0) (1 1)
8413 12:12:22.805757 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 12:12:22.811923 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8415 12:12:22.815290 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8416 12:12:22.818665 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8417 12:12:22.825314 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 12:12:22.828481 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 12:12:22.831411 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
8420 12:12:22.838700 1 5 12 | B1->B0 | 3030 2525 | 1 0 | (1 0) (1 0)
8421 12:12:22.841877 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 12:12:22.845563 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 12:12:22.852466 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 12:12:22.854644 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 12:12:22.858683 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 12:12:22.864742 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 12:12:22.868082 1 6 8 | B1->B0 | 2929 2e2e | 0 0 | (0 0) (0 0)
8428 12:12:22.871307 1 6 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
8429 12:12:22.878259 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 12:12:22.881011 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 12:12:22.884229 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 12:12:22.891280 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 12:12:22.895379 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 12:12:22.898236 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 12:12:22.904340 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 12:12:22.908018 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8437 12:12:22.911460 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8438 12:12:22.917395 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 12:12:22.921499 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 12:12:22.924638 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 12:12:22.930971 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 12:12:22.934071 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 12:12:22.937153 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 12:12:22.944461 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 12:12:22.947755 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 12:12:22.950999 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 12:12:22.957231 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 12:12:22.959875 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 12:12:22.963417 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 12:12:22.970338 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 12:12:22.973658 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8452 12:12:22.976684 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8453 12:12:22.983121 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8454 12:12:22.983704 Total UI for P1: 0, mck2ui 16
8455 12:12:22.989922 best dqsien dly found for B0: ( 1, 9, 10)
8456 12:12:22.992995 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8457 12:12:22.997150 Total UI for P1: 0, mck2ui 16
8458 12:12:23.000113 best dqsien dly found for B1: ( 1, 9, 12)
8459 12:12:23.003110 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8460 12:12:23.006199 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8461 12:12:23.006630
8462 12:12:23.009904 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8463 12:12:23.012972 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8464 12:12:23.016854 [Gating] SW calibration Done
8465 12:12:23.017404 ==
8466 12:12:23.019379 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 12:12:23.022756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 12:12:23.026582 ==
8469 12:12:23.027150 RX Vref Scan: 0
8470 12:12:23.027496
8471 12:12:23.029968 RX Vref 0 -> 0, step: 1
8472 12:12:23.030381
8473 12:12:23.034375 RX Delay 0 -> 252, step: 8
8474 12:12:23.036714 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8475 12:12:23.039044 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8476 12:12:23.043201 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8477 12:12:23.046570 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8478 12:12:23.052653 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8479 12:12:23.056102 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8480 12:12:23.059283 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8481 12:12:23.062435 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8482 12:12:23.065482 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8483 12:12:23.072679 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8484 12:12:23.076347 iDelay=208, Bit 10, Center 131 (80 ~ 183) 104
8485 12:12:23.079060 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8486 12:12:23.082395 iDelay=208, Bit 12, Center 139 (88 ~ 191) 104
8487 12:12:23.088882 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8488 12:12:23.091906 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8489 12:12:23.095829 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8490 12:12:23.096381 ==
8491 12:12:23.098554 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 12:12:23.102021 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 12:12:23.102576 ==
8494 12:12:23.105273 DQS Delay:
8495 12:12:23.105729 DQS0 = 0, DQS1 = 0
8496 12:12:23.108794 DQM Delay:
8497 12:12:23.109254 DQM0 = 138, DQM1 = 130
8498 12:12:23.109620 DQ Delay:
8499 12:12:23.115222 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8500 12:12:23.118329 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8501 12:12:23.121550 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8502 12:12:23.124933 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =135
8503 12:12:23.125518
8504 12:12:23.125997
8505 12:12:23.126445 ==
8506 12:12:23.127972 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 12:12:23.131323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 12:12:23.131797 ==
8509 12:12:23.132232
8510 12:12:23.132641
8511 12:12:23.135044 TX Vref Scan disable
8512 12:12:23.138646 == TX Byte 0 ==
8513 12:12:23.141966 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8514 12:12:23.145550 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8515 12:12:23.148057 == TX Byte 1 ==
8516 12:12:23.151884 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8517 12:12:23.154560 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8518 12:12:23.155099 ==
8519 12:12:23.157983 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 12:12:23.164360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 12:12:23.164927 ==
8522 12:12:23.176448
8523 12:12:23.179323 TX Vref early break, caculate TX vref
8524 12:12:23.183088 TX Vref=16, minBit 0, minWin=21, winSum=372
8525 12:12:23.186278 TX Vref=18, minBit 5, minWin=21, winSum=378
8526 12:12:23.189118 TX Vref=20, minBit 0, minWin=23, winSum=390
8527 12:12:23.192930 TX Vref=22, minBit 0, minWin=23, winSum=399
8528 12:12:23.196057 TX Vref=24, minBit 0, minWin=24, winSum=409
8529 12:12:23.202480 TX Vref=26, minBit 5, minWin=24, winSum=412
8530 12:12:23.205780 TX Vref=28, minBit 0, minWin=23, winSum=414
8531 12:12:23.209415 TX Vref=30, minBit 5, minWin=24, winSum=411
8532 12:12:23.212258 TX Vref=32, minBit 0, minWin=23, winSum=399
8533 12:12:23.215362 TX Vref=34, minBit 5, minWin=22, winSum=387
8534 12:12:23.222437 [TxChooseVref] Worse bit 5, Min win 24, Win sum 412, Final Vref 26
8535 12:12:23.223066
8536 12:12:23.225745 Final TX Range 0 Vref 26
8537 12:12:23.226328
8538 12:12:23.226662 ==
8539 12:12:23.229023 Dram Type= 6, Freq= 0, CH_1, rank 0
8540 12:12:23.232074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8541 12:12:23.232533 ==
8542 12:12:23.232904
8543 12:12:23.233258
8544 12:12:23.235434 TX Vref Scan disable
8545 12:12:23.242194 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8546 12:12:23.242780 == TX Byte 0 ==
8547 12:12:23.244856 u2DelayCellOfst[0]=18 cells (5 PI)
8548 12:12:23.248279 u2DelayCellOfst[1]=14 cells (4 PI)
8549 12:12:23.251617 u2DelayCellOfst[2]=0 cells (0 PI)
8550 12:12:23.254697 u2DelayCellOfst[3]=7 cells (2 PI)
8551 12:12:23.258493 u2DelayCellOfst[4]=7 cells (2 PI)
8552 12:12:23.262009 u2DelayCellOfst[5]=22 cells (6 PI)
8553 12:12:23.265211 u2DelayCellOfst[6]=22 cells (6 PI)
8554 12:12:23.268550 u2DelayCellOfst[7]=7 cells (2 PI)
8555 12:12:23.271740 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8556 12:12:23.274736 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8557 12:12:23.278499 == TX Byte 1 ==
8558 12:12:23.281419 u2DelayCellOfst[8]=0 cells (0 PI)
8559 12:12:23.285419 u2DelayCellOfst[9]=3 cells (1 PI)
8560 12:12:23.285848 u2DelayCellOfst[10]=11 cells (3 PI)
8561 12:12:23.287810 u2DelayCellOfst[11]=3 cells (1 PI)
8562 12:12:23.291919 u2DelayCellOfst[12]=14 cells (4 PI)
8563 12:12:23.294470 u2DelayCellOfst[13]=18 cells (5 PI)
8564 12:12:23.297898 u2DelayCellOfst[14]=18 cells (5 PI)
8565 12:12:23.301427 u2DelayCellOfst[15]=14 cells (4 PI)
8566 12:12:23.307847 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8567 12:12:23.311618 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8568 12:12:23.312133 DramC Write-DBI on
8569 12:12:23.312595 ==
8570 12:12:23.314204 Dram Type= 6, Freq= 0, CH_1, rank 0
8571 12:12:23.321673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8572 12:12:23.322147 ==
8573 12:12:23.322496
8574 12:12:23.322830
8575 12:12:23.325046 TX Vref Scan disable
8576 12:12:23.325468 == TX Byte 0 ==
8577 12:12:23.331477 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8578 12:12:23.332081 == TX Byte 1 ==
8579 12:12:23.334329 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8580 12:12:23.337915 DramC Write-DBI off
8581 12:12:23.338439
8582 12:12:23.338828 [DATLAT]
8583 12:12:23.340510 Freq=1600, CH1 RK0
8584 12:12:23.340958
8585 12:12:23.341314 DATLAT Default: 0xf
8586 12:12:23.344146 0, 0xFFFF, sum = 0
8587 12:12:23.344577 1, 0xFFFF, sum = 0
8588 12:12:23.347307 2, 0xFFFF, sum = 0
8589 12:12:23.347801 3, 0xFFFF, sum = 0
8590 12:12:23.350530 4, 0xFFFF, sum = 0
8591 12:12:23.350978 5, 0xFFFF, sum = 0
8592 12:12:23.354046 6, 0xFFFF, sum = 0
8593 12:12:23.354476 7, 0xFFFF, sum = 0
8594 12:12:23.357450 8, 0xFFFF, sum = 0
8595 12:12:23.360521 9, 0xFFFF, sum = 0
8596 12:12:23.360951 10, 0xFFFF, sum = 0
8597 12:12:23.363838 11, 0xFFFF, sum = 0
8598 12:12:23.364312 12, 0xFFFF, sum = 0
8599 12:12:23.367028 13, 0xFFFF, sum = 0
8600 12:12:23.367486 14, 0x0, sum = 1
8601 12:12:23.370702 15, 0x0, sum = 2
8602 12:12:23.371160 16, 0x0, sum = 3
8603 12:12:23.374174 17, 0x0, sum = 4
8604 12:12:23.374627 best_step = 15
8605 12:12:23.374969
8606 12:12:23.375282 ==
8607 12:12:23.377347 Dram Type= 6, Freq= 0, CH_1, rank 0
8608 12:12:23.380597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8609 12:12:23.383488 ==
8610 12:12:23.383970 RX Vref Scan: 1
8611 12:12:23.384350
8612 12:12:23.386814 Set Vref Range= 24 -> 127
8613 12:12:23.387237
8614 12:12:23.390513 RX Vref 24 -> 127, step: 1
8615 12:12:23.390937
8616 12:12:23.391300 RX Delay 11 -> 252, step: 4
8617 12:12:23.391621
8618 12:12:23.393197 Set Vref, RX VrefLevel [Byte0]: 24
8619 12:12:23.396365 [Byte1]: 24
8620 12:12:23.400526
8621 12:12:23.400950 Set Vref, RX VrefLevel [Byte0]: 25
8622 12:12:23.403657 [Byte1]: 25
8623 12:12:23.408062
8624 12:12:23.408483 Set Vref, RX VrefLevel [Byte0]: 26
8625 12:12:23.411326 [Byte1]: 26
8626 12:12:23.415500
8627 12:12:23.415967 Set Vref, RX VrefLevel [Byte0]: 27
8628 12:12:23.418551 [Byte1]: 27
8629 12:12:23.423319
8630 12:12:23.423786 Set Vref, RX VrefLevel [Byte0]: 28
8631 12:12:23.426405 [Byte1]: 28
8632 12:12:23.430872
8633 12:12:23.431282 Set Vref, RX VrefLevel [Byte0]: 29
8634 12:12:23.434170 [Byte1]: 29
8635 12:12:23.438562
8636 12:12:23.439074 Set Vref, RX VrefLevel [Byte0]: 30
8637 12:12:23.441755 [Byte1]: 30
8638 12:12:23.446098
8639 12:12:23.449577 Set Vref, RX VrefLevel [Byte0]: 31
8640 12:12:23.452508 [Byte1]: 31
8641 12:12:23.452922
8642 12:12:23.456277 Set Vref, RX VrefLevel [Byte0]: 32
8643 12:12:23.459769 [Byte1]: 32
8644 12:12:23.460362
8645 12:12:23.462533 Set Vref, RX VrefLevel [Byte0]: 33
8646 12:12:23.465842 [Byte1]: 33
8647 12:12:23.469406
8648 12:12:23.469924 Set Vref, RX VrefLevel [Byte0]: 34
8649 12:12:23.473042 [Byte1]: 34
8650 12:12:23.476649
8651 12:12:23.477170 Set Vref, RX VrefLevel [Byte0]: 35
8652 12:12:23.480426 [Byte1]: 35
8653 12:12:23.484929
8654 12:12:23.485449 Set Vref, RX VrefLevel [Byte0]: 36
8655 12:12:23.488370 [Byte1]: 36
8656 12:12:23.492076
8657 12:12:23.492591 Set Vref, RX VrefLevel [Byte0]: 37
8658 12:12:23.495562 [Byte1]: 37
8659 12:12:23.499558
8660 12:12:23.500140 Set Vref, RX VrefLevel [Byte0]: 38
8661 12:12:23.503033 [Byte1]: 38
8662 12:12:23.507020
8663 12:12:23.507533 Set Vref, RX VrefLevel [Byte0]: 39
8664 12:12:23.510351 [Byte1]: 39
8665 12:12:23.514754
8666 12:12:23.515268 Set Vref, RX VrefLevel [Byte0]: 40
8667 12:12:23.518035 [Byte1]: 40
8668 12:12:23.522220
8669 12:12:23.522645 Set Vref, RX VrefLevel [Byte0]: 41
8670 12:12:23.525227 [Byte1]: 41
8671 12:12:23.530911
8672 12:12:23.531430 Set Vref, RX VrefLevel [Byte0]: 42
8673 12:12:23.532897 [Byte1]: 42
8674 12:12:23.537652
8675 12:12:23.538169 Set Vref, RX VrefLevel [Byte0]: 43
8676 12:12:23.540964 [Byte1]: 43
8677 12:12:23.544986
8678 12:12:23.548539 Set Vref, RX VrefLevel [Byte0]: 44
8679 12:12:23.551799 [Byte1]: 44
8680 12:12:23.552216
8681 12:12:23.555296 Set Vref, RX VrefLevel [Byte0]: 45
8682 12:12:23.558263 [Byte1]: 45
8683 12:12:23.558873
8684 12:12:23.561169 Set Vref, RX VrefLevel [Byte0]: 46
8685 12:12:23.565713 [Byte1]: 46
8686 12:12:23.566144
8687 12:12:23.568715 Set Vref, RX VrefLevel [Byte0]: 47
8688 12:12:23.571048 [Byte1]: 47
8689 12:12:23.575123
8690 12:12:23.575540 Set Vref, RX VrefLevel [Byte0]: 48
8691 12:12:23.579039 [Byte1]: 48
8692 12:12:23.583339
8693 12:12:23.583954 Set Vref, RX VrefLevel [Byte0]: 49
8694 12:12:23.586116 [Byte1]: 49
8695 12:12:23.590906
8696 12:12:23.591319 Set Vref, RX VrefLevel [Byte0]: 50
8697 12:12:23.594001 [Byte1]: 50
8698 12:12:23.599521
8699 12:12:23.600127 Set Vref, RX VrefLevel [Byte0]: 51
8700 12:12:23.601488 [Byte1]: 51
8701 12:12:23.606345
8702 12:12:23.606775 Set Vref, RX VrefLevel [Byte0]: 52
8703 12:12:23.609319 [Byte1]: 52
8704 12:12:23.613938
8705 12:12:23.614463 Set Vref, RX VrefLevel [Byte0]: 53
8706 12:12:23.616905 [Byte1]: 53
8707 12:12:23.621023
8708 12:12:23.621551 Set Vref, RX VrefLevel [Byte0]: 54
8709 12:12:23.624096 [Byte1]: 54
8710 12:12:23.629442
8711 12:12:23.629967 Set Vref, RX VrefLevel [Byte0]: 55
8712 12:12:23.632281 [Byte1]: 55
8713 12:12:23.636175
8714 12:12:23.636588 Set Vref, RX VrefLevel [Byte0]: 56
8715 12:12:23.640080 [Byte1]: 56
8716 12:12:23.644472
8717 12:12:23.644997 Set Vref, RX VrefLevel [Byte0]: 57
8718 12:12:23.648101 [Byte1]: 57
8719 12:12:23.651579
8720 12:12:23.652034 Set Vref, RX VrefLevel [Byte0]: 58
8721 12:12:23.655367 [Byte1]: 58
8722 12:12:23.659648
8723 12:12:23.660216 Set Vref, RX VrefLevel [Byte0]: 59
8724 12:12:23.662884 [Byte1]: 59
8725 12:12:23.667279
8726 12:12:23.667865 Set Vref, RX VrefLevel [Byte0]: 60
8727 12:12:23.670137 [Byte1]: 60
8728 12:12:23.674565
8729 12:12:23.675088 Set Vref, RX VrefLevel [Byte0]: 61
8730 12:12:23.679144 [Byte1]: 61
8731 12:12:23.682372
8732 12:12:23.682892 Set Vref, RX VrefLevel [Byte0]: 62
8733 12:12:23.685267 [Byte1]: 62
8734 12:12:23.689954
8735 12:12:23.690485 Set Vref, RX VrefLevel [Byte0]: 63
8736 12:12:23.693196 [Byte1]: 63
8737 12:12:23.697713
8738 12:12:23.698238 Set Vref, RX VrefLevel [Byte0]: 64
8739 12:12:23.700929 [Byte1]: 64
8740 12:12:23.705835
8741 12:12:23.706352 Set Vref, RX VrefLevel [Byte0]: 65
8742 12:12:23.708271 [Byte1]: 65
8743 12:12:23.712673
8744 12:12:23.713210 Set Vref, RX VrefLevel [Byte0]: 66
8745 12:12:23.716253 [Byte1]: 66
8746 12:12:23.720286
8747 12:12:23.720701 Set Vref, RX VrefLevel [Byte0]: 67
8748 12:12:23.723923 [Byte1]: 67
8749 12:12:23.727470
8750 12:12:23.727972 Set Vref, RX VrefLevel [Byte0]: 68
8751 12:12:23.731623 [Byte1]: 68
8752 12:12:23.735735
8753 12:12:23.736160 Set Vref, RX VrefLevel [Byte0]: 69
8754 12:12:23.739196 [Byte1]: 69
8755 12:12:23.743202
8756 12:12:23.746061 Set Vref, RX VrefLevel [Byte0]: 70
8757 12:12:23.749264 [Byte1]: 70
8758 12:12:23.749726
8759 12:12:23.752550 Set Vref, RX VrefLevel [Byte0]: 71
8760 12:12:23.756074 [Byte1]: 71
8761 12:12:23.756585
8762 12:12:23.759348 Set Vref, RX VrefLevel [Byte0]: 72
8763 12:12:23.762959 [Byte1]: 72
8764 12:12:23.765859
8765 12:12:23.766340 Set Vref, RX VrefLevel [Byte0]: 73
8766 12:12:23.769224 [Byte1]: 73
8767 12:12:23.774144
8768 12:12:23.774722 Final RX Vref Byte 0 = 54 to rank0
8769 12:12:23.776609 Final RX Vref Byte 1 = 58 to rank0
8770 12:12:23.779953 Final RX Vref Byte 0 = 54 to rank1
8771 12:12:23.783869 Final RX Vref Byte 1 = 58 to rank1==
8772 12:12:23.786507 Dram Type= 6, Freq= 0, CH_1, rank 0
8773 12:12:23.793385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8774 12:12:23.793940 ==
8775 12:12:23.794311 DQS Delay:
8776 12:12:23.797136 DQS0 = 0, DQS1 = 0
8777 12:12:23.797600 DQM Delay:
8778 12:12:23.799522 DQM0 = 135, DQM1 = 129
8779 12:12:23.800020 DQ Delay:
8780 12:12:23.802734 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8781 12:12:23.806046 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =130
8782 12:12:23.810080 DQ8 =116, DQ9 =116, DQ10 =132, DQ11 =118
8783 12:12:23.812706 DQ12 =136, DQ13 =138, DQ14 =138, DQ15 =140
8784 12:12:23.813189
8785 12:12:23.813592
8786 12:12:23.813935
8787 12:12:23.816583 [DramC_TX_OE_Calibration] TA2
8788 12:12:23.819747 Original DQ_B0 (3 6) =30, OEN = 27
8789 12:12:23.822569 Original DQ_B1 (3 6) =30, OEN = 27
8790 12:12:23.825714 24, 0x0, End_B0=24 End_B1=24
8791 12:12:23.828885 25, 0x0, End_B0=25 End_B1=25
8792 12:12:23.829313 26, 0x0, End_B0=26 End_B1=26
8793 12:12:23.833072 27, 0x0, End_B0=27 End_B1=27
8794 12:12:23.835750 28, 0x0, End_B0=28 End_B1=28
8795 12:12:23.839019 29, 0x0, End_B0=29 End_B1=29
8796 12:12:23.842050 30, 0x0, End_B0=30 End_B1=30
8797 12:12:23.842475 31, 0x4141, End_B0=30 End_B1=30
8798 12:12:23.846051 Byte0 end_step=30 best_step=27
8799 12:12:23.848605 Byte1 end_step=30 best_step=27
8800 12:12:23.851846 Byte0 TX OE(2T, 0.5T) = (3, 3)
8801 12:12:23.855469 Byte1 TX OE(2T, 0.5T) = (3, 3)
8802 12:12:23.855956
8803 12:12:23.856293
8804 12:12:23.861946 [DQSOSCAuto] RK0, (LSB)MR18= 0x170c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8805 12:12:23.865302 CH1 RK0: MR19=303, MR18=170C
8806 12:12:23.872202 CH1_RK0: MR19=0x303, MR18=0x170C, DQSOSC=398, MR23=63, INC=23, DEC=15
8807 12:12:23.872708
8808 12:12:23.875456 ----->DramcWriteLeveling(PI) begin...
8809 12:12:23.876058 ==
8810 12:12:23.878669 Dram Type= 6, Freq= 0, CH_1, rank 1
8811 12:12:23.882051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8812 12:12:23.884907 ==
8813 12:12:23.885327 Write leveling (Byte 0): 25 => 25
8814 12:12:23.888116 Write leveling (Byte 1): 27 => 27
8815 12:12:23.891777 DramcWriteLeveling(PI) end<-----
8816 12:12:23.892194
8817 12:12:23.892526 ==
8818 12:12:23.894692 Dram Type= 6, Freq= 0, CH_1, rank 1
8819 12:12:23.901355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8820 12:12:23.901804 ==
8821 12:12:23.902140 [Gating] SW mode calibration
8822 12:12:23.912170 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8823 12:12:23.915768 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8824 12:12:23.921318 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 12:12:23.924488 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 12:12:23.928174 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8827 12:12:23.934858 1 4 12 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8828 12:12:23.937996 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8829 12:12:23.941023 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8830 12:12:23.948586 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 12:12:23.951414 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 12:12:23.954820 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 12:12:23.960766 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 12:12:23.964474 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8835 12:12:23.967873 1 5 12 | B1->B0 | 2323 3333 | 0 1 | (1 0) (1 0)
8836 12:12:23.974063 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8837 12:12:23.977241 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 12:12:23.980710 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 12:12:23.987069 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 12:12:23.990311 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 12:12:23.994138 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 12:12:24.000704 1 6 8 | B1->B0 | 2b2b 2323 | 1 0 | (0 0) (0 0)
8843 12:12:24.004451 1 6 12 | B1->B0 | 4444 2626 | 0 0 | (0 0) (0 0)
8844 12:12:24.007170 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8845 12:12:24.013268 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8846 12:12:24.017645 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 12:12:24.020285 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 12:12:24.026911 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 12:12:24.029952 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 12:12:24.033463 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8851 12:12:24.040297 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8852 12:12:24.043566 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8853 12:12:24.046909 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 12:12:24.053160 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 12:12:24.056517 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 12:12:24.060171 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 12:12:24.066905 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 12:12:24.070134 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 12:12:24.072760 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 12:12:24.079620 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 12:12:24.083393 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 12:12:24.086320 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 12:12:24.093237 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 12:12:24.096305 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 12:12:24.099953 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 12:12:24.106382 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8867 12:12:24.109016 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8868 12:12:24.112452 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 12:12:24.115898 Total UI for P1: 0, mck2ui 16
8870 12:12:24.118991 best dqsien dly found for B0: ( 1, 9, 12)
8871 12:12:24.122597 Total UI for P1: 0, mck2ui 16
8872 12:12:24.125719 best dqsien dly found for B1: ( 1, 9, 10)
8873 12:12:24.128776 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8874 12:12:24.132201 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8875 12:12:24.132664
8876 12:12:24.139207 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8877 12:12:24.143103 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8878 12:12:24.143631 [Gating] SW calibration Done
8879 12:12:24.145653 ==
8880 12:12:24.148565 Dram Type= 6, Freq= 0, CH_1, rank 1
8881 12:12:24.152249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8882 12:12:24.152672 ==
8883 12:12:24.153006 RX Vref Scan: 0
8884 12:12:24.153314
8885 12:12:24.155263 RX Vref 0 -> 0, step: 1
8886 12:12:24.155821
8887 12:12:24.159062 RX Delay 0 -> 252, step: 8
8888 12:12:24.162236 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8889 12:12:24.165225 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8890 12:12:24.168909 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8891 12:12:24.175824 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8892 12:12:24.178527 iDelay=208, Bit 4, Center 135 (72 ~ 199) 128
8893 12:12:24.181647 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8894 12:12:24.185188 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8895 12:12:24.191436 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8896 12:12:24.195175 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8897 12:12:24.198368 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8898 12:12:24.201716 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8899 12:12:24.204580 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8900 12:12:24.212042 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8901 12:12:24.214627 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8902 12:12:24.217974 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8903 12:12:24.221386 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8904 12:12:24.221808 ==
8905 12:12:24.224683 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 12:12:24.231966 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 12:12:24.232442 ==
8908 12:12:24.232811 DQS Delay:
8909 12:12:24.234750 DQS0 = 0, DQS1 = 0
8910 12:12:24.235166 DQM Delay:
8911 12:12:24.235499 DQM0 = 137, DQM1 = 130
8912 12:12:24.237977 DQ Delay:
8913 12:12:24.241602 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8914 12:12:24.244769 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8915 12:12:24.248213 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =119
8916 12:12:24.251446 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8917 12:12:24.252051
8918 12:12:24.252397
8919 12:12:24.252705 ==
8920 12:12:24.254379 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 12:12:24.260897 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 12:12:24.261419 ==
8923 12:12:24.261754
8924 12:12:24.262140
8925 12:12:24.262456 TX Vref Scan disable
8926 12:12:24.264554 == TX Byte 0 ==
8927 12:12:24.267536 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8928 12:12:24.274113 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8929 12:12:24.274640 == TX Byte 1 ==
8930 12:12:24.277150 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8931 12:12:24.284309 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8932 12:12:24.284833 ==
8933 12:12:24.287714 Dram Type= 6, Freq= 0, CH_1, rank 1
8934 12:12:24.290597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8935 12:12:24.291122 ==
8936 12:12:24.303543
8937 12:12:24.306782 TX Vref early break, caculate TX vref
8938 12:12:24.309748 TX Vref=16, minBit 1, minWin=22, winSum=385
8939 12:12:24.313067 TX Vref=18, minBit 1, minWin=23, winSum=395
8940 12:12:24.316510 TX Vref=20, minBit 0, minWin=24, winSum=406
8941 12:12:24.320014 TX Vref=22, minBit 1, minWin=25, winSum=412
8942 12:12:24.322842 TX Vref=24, minBit 15, minWin=25, winSum=422
8943 12:12:24.330496 TX Vref=26, minBit 1, minWin=25, winSum=427
8944 12:12:24.333795 TX Vref=28, minBit 0, minWin=25, winSum=424
8945 12:12:24.336284 TX Vref=30, minBit 0, minWin=25, winSum=421
8946 12:12:24.339549 TX Vref=32, minBit 0, minWin=25, winSum=412
8947 12:12:24.342850 TX Vref=34, minBit 0, minWin=24, winSum=400
8948 12:12:24.349710 [TxChooseVref] Worse bit 1, Min win 25, Win sum 427, Final Vref 26
8949 12:12:24.350296
8950 12:12:24.352399 Final TX Range 0 Vref 26
8951 12:12:24.352816
8952 12:12:24.353148 ==
8953 12:12:24.355545 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 12:12:24.359476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 12:12:24.360089 ==
8956 12:12:24.360436
8957 12:12:24.360748
8958 12:12:24.362567 TX Vref Scan disable
8959 12:12:24.369085 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8960 12:12:24.369634 == TX Byte 0 ==
8961 12:12:24.373039 u2DelayCellOfst[0]=18 cells (5 PI)
8962 12:12:24.375466 u2DelayCellOfst[1]=14 cells (4 PI)
8963 12:12:24.378977 u2DelayCellOfst[2]=0 cells (0 PI)
8964 12:12:24.382463 u2DelayCellOfst[3]=7 cells (2 PI)
8965 12:12:24.385405 u2DelayCellOfst[4]=11 cells (3 PI)
8966 12:12:24.389366 u2DelayCellOfst[5]=22 cells (6 PI)
8967 12:12:24.392020 u2DelayCellOfst[6]=22 cells (6 PI)
8968 12:12:24.395416 u2DelayCellOfst[7]=7 cells (2 PI)
8969 12:12:24.398486 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8970 12:12:24.402204 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8971 12:12:24.405989 == TX Byte 1 ==
8972 12:12:24.408376 u2DelayCellOfst[8]=0 cells (0 PI)
8973 12:12:24.411525 u2DelayCellOfst[9]=7 cells (2 PI)
8974 12:12:24.415734 u2DelayCellOfst[10]=11 cells (3 PI)
8975 12:12:24.416277 u2DelayCellOfst[11]=7 cells (2 PI)
8976 12:12:24.418472 u2DelayCellOfst[12]=14 cells (4 PI)
8977 12:12:24.421843 u2DelayCellOfst[13]=18 cells (5 PI)
8978 12:12:24.425003 u2DelayCellOfst[14]=18 cells (5 PI)
8979 12:12:24.428578 u2DelayCellOfst[15]=18 cells (5 PI)
8980 12:12:24.435249 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8981 12:12:24.438493 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8982 12:12:24.439021 DramC Write-DBI on
8983 12:12:24.441308 ==
8984 12:12:24.445562 Dram Type= 6, Freq= 0, CH_1, rank 1
8985 12:12:24.448077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8986 12:12:24.448498 ==
8987 12:12:24.448833
8988 12:12:24.449143
8989 12:12:24.451953 TX Vref Scan disable
8990 12:12:24.452467 == TX Byte 0 ==
8991 12:12:24.458353 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8992 12:12:24.458871 == TX Byte 1 ==
8993 12:12:24.461661 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8994 12:12:24.464943 DramC Write-DBI off
8995 12:12:24.465498
8996 12:12:24.465865 [DATLAT]
8997 12:12:24.468377 Freq=1600, CH1 RK1
8998 12:12:24.468833
8999 12:12:24.469191 DATLAT Default: 0xf
9000 12:12:24.471323 0, 0xFFFF, sum = 0
9001 12:12:24.471925 1, 0xFFFF, sum = 0
9002 12:12:24.475084 2, 0xFFFF, sum = 0
9003 12:12:24.475649 3, 0xFFFF, sum = 0
9004 12:12:24.478170 4, 0xFFFF, sum = 0
9005 12:12:24.478731 5, 0xFFFF, sum = 0
9006 12:12:24.481062 6, 0xFFFF, sum = 0
9007 12:12:24.481526 7, 0xFFFF, sum = 0
9008 12:12:24.484491 8, 0xFFFF, sum = 0
9009 12:12:24.487731 9, 0xFFFF, sum = 0
9010 12:12:24.488152 10, 0xFFFF, sum = 0
9011 12:12:24.491773 11, 0xFFFF, sum = 0
9012 12:12:24.492310 12, 0xFFFF, sum = 0
9013 12:12:24.494464 13, 0xFFFF, sum = 0
9014 12:12:24.494988 14, 0x0, sum = 1
9015 12:12:24.497951 15, 0x0, sum = 2
9016 12:12:24.498373 16, 0x0, sum = 3
9017 12:12:24.501644 17, 0x0, sum = 4
9018 12:12:24.502169 best_step = 15
9019 12:12:24.502501
9020 12:12:24.502809 ==
9021 12:12:24.504388 Dram Type= 6, Freq= 0, CH_1, rank 1
9022 12:12:24.508127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9023 12:12:24.508653 ==
9024 12:12:24.511212 RX Vref Scan: 0
9025 12:12:24.511763
9026 12:12:24.514280 RX Vref 0 -> 0, step: 1
9027 12:12:24.514807
9028 12:12:24.515140 RX Delay 11 -> 252, step: 4
9029 12:12:24.521505 iDelay=203, Bit 0, Center 138 (83 ~ 194) 112
9030 12:12:24.525142 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9031 12:12:24.528695 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9032 12:12:24.531322 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9033 12:12:24.538174 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9034 12:12:24.541222 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9035 12:12:24.544865 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9036 12:12:24.548170 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9037 12:12:24.551426 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9038 12:12:24.557718 iDelay=203, Bit 9, Center 114 (59 ~ 170) 112
9039 12:12:24.561343 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9040 12:12:24.564310 iDelay=203, Bit 11, Center 118 (67 ~ 170) 104
9041 12:12:24.567878 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9042 12:12:24.571211 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9043 12:12:24.578081 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9044 12:12:24.580510 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9045 12:12:24.580978 ==
9046 12:12:24.583876 Dram Type= 6, Freq= 0, CH_1, rank 1
9047 12:12:24.587796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9048 12:12:24.588266 ==
9049 12:12:24.590593 DQS Delay:
9050 12:12:24.591184 DQS0 = 0, DQS1 = 0
9051 12:12:24.591557 DQM Delay:
9052 12:12:24.594239 DQM0 = 134, DQM1 = 127
9053 12:12:24.594794 DQ Delay:
9054 12:12:24.597157 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9055 12:12:24.600753 DQ4 =134, DQ5 =144, DQ6 =146, DQ7 =130
9056 12:12:24.607466 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =118
9057 12:12:24.610422 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9058 12:12:24.610958
9059 12:12:24.611290
9060 12:12:24.611599
9061 12:12:24.613790 [DramC_TX_OE_Calibration] TA2
9062 12:12:24.616931 Original DQ_B0 (3 6) =30, OEN = 27
9063 12:12:24.620608 Original DQ_B1 (3 6) =30, OEN = 27
9064 12:12:24.621170 24, 0x0, End_B0=24 End_B1=24
9065 12:12:24.623944 25, 0x0, End_B0=25 End_B1=25
9066 12:12:24.627287 26, 0x0, End_B0=26 End_B1=26
9067 12:12:24.630692 27, 0x0, End_B0=27 End_B1=27
9068 12:12:24.631163 28, 0x0, End_B0=28 End_B1=28
9069 12:12:24.634463 29, 0x0, End_B0=29 End_B1=29
9070 12:12:24.637224 30, 0x0, End_B0=30 End_B1=30
9071 12:12:24.640248 31, 0x4545, End_B0=30 End_B1=30
9072 12:12:24.643734 Byte0 end_step=30 best_step=27
9073 12:12:24.647174 Byte1 end_step=30 best_step=27
9074 12:12:24.647793 Byte0 TX OE(2T, 0.5T) = (3, 3)
9075 12:12:24.649888 Byte1 TX OE(2T, 0.5T) = (3, 3)
9076 12:12:24.650474
9077 12:12:24.650822
9078 12:12:24.660055 [DQSOSCAuto] RK1, (LSB)MR18= 0xb07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9079 12:12:24.663579 CH1 RK1: MR19=303, MR18=B07
9080 12:12:24.667152 CH1_RK1: MR19=0x303, MR18=0xB07, DQSOSC=404, MR23=63, INC=22, DEC=15
9081 12:12:24.669765 [RxdqsGatingPostProcess] freq 1600
9082 12:12:24.676486 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9083 12:12:24.679821 best DQS0 dly(2T, 0.5T) = (1, 1)
9084 12:12:24.683056 best DQS1 dly(2T, 0.5T) = (1, 1)
9085 12:12:24.686923 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9086 12:12:24.689897 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9087 12:12:24.692652 best DQS0 dly(2T, 0.5T) = (1, 1)
9088 12:12:24.696146 best DQS1 dly(2T, 0.5T) = (1, 1)
9089 12:12:24.700154 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9090 12:12:24.703930 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9091 12:12:24.704485 Pre-setting of DQS Precalculation
9092 12:12:24.709278 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9093 12:12:24.715777 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9094 12:12:24.722639 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9095 12:12:24.723260
9096 12:12:24.723630
9097 12:12:24.726455 [Calibration Summary] 3200 Mbps
9098 12:12:24.729141 CH 0, Rank 0
9099 12:12:24.729788 SW Impedance : PASS
9100 12:12:24.732301 DUTY Scan : NO K
9101 12:12:24.736311 ZQ Calibration : PASS
9102 12:12:24.736887 Jitter Meter : NO K
9103 12:12:24.738937 CBT Training : PASS
9104 12:12:24.742425 Write leveling : PASS
9105 12:12:24.742845 RX DQS gating : PASS
9106 12:12:24.746283 RX DQ/DQS(RDDQC) : PASS
9107 12:12:24.746797 TX DQ/DQS : PASS
9108 12:12:24.749381 RX DATLAT : PASS
9109 12:12:24.752937 RX DQ/DQS(Engine): PASS
9110 12:12:24.753453 TX OE : PASS
9111 12:12:24.755733 All Pass.
9112 12:12:24.756165
9113 12:12:24.756611 CH 0, Rank 1
9114 12:12:24.759250 SW Impedance : PASS
9115 12:12:24.759830 DUTY Scan : NO K
9116 12:12:24.762982 ZQ Calibration : PASS
9117 12:12:24.765738 Jitter Meter : NO K
9118 12:12:24.766271 CBT Training : PASS
9119 12:12:24.769183 Write leveling : PASS
9120 12:12:24.772198 RX DQS gating : PASS
9121 12:12:24.772714 RX DQ/DQS(RDDQC) : PASS
9122 12:12:24.775442 TX DQ/DQS : PASS
9123 12:12:24.778421 RX DATLAT : PASS
9124 12:12:24.778899 RX DQ/DQS(Engine): PASS
9125 12:12:24.782139 TX OE : PASS
9126 12:12:24.782668 All Pass.
9127 12:12:24.783105
9128 12:12:24.785528 CH 1, Rank 0
9129 12:12:24.785948 SW Impedance : PASS
9130 12:12:24.788540 DUTY Scan : NO K
9131 12:12:24.792137 ZQ Calibration : PASS
9132 12:12:24.792700 Jitter Meter : NO K
9133 12:12:24.795603 CBT Training : PASS
9134 12:12:24.798469 Write leveling : PASS
9135 12:12:24.798937 RX DQS gating : PASS
9136 12:12:24.802201 RX DQ/DQS(RDDQC) : PASS
9137 12:12:24.805040 TX DQ/DQS : PASS
9138 12:12:24.805602 RX DATLAT : PASS
9139 12:12:24.809429 RX DQ/DQS(Engine): PASS
9140 12:12:24.812455 TX OE : PASS
9141 12:12:24.813013 All Pass.
9142 12:12:24.813387
9143 12:12:24.813729 CH 1, Rank 1
9144 12:12:24.815163 SW Impedance : PASS
9145 12:12:24.818646 DUTY Scan : NO K
9146 12:12:24.819216 ZQ Calibration : PASS
9147 12:12:24.822252 Jitter Meter : NO K
9148 12:12:24.824740 CBT Training : PASS
9149 12:12:24.825205 Write leveling : PASS
9150 12:12:24.828009 RX DQS gating : PASS
9151 12:12:24.831199 RX DQ/DQS(RDDQC) : PASS
9152 12:12:24.831619 TX DQ/DQS : PASS
9153 12:12:24.834463 RX DATLAT : PASS
9154 12:12:24.834884 RX DQ/DQS(Engine): PASS
9155 12:12:24.838063 TX OE : PASS
9156 12:12:24.838485 All Pass.
9157 12:12:24.838823
9158 12:12:24.841557 DramC Write-DBI on
9159 12:12:24.844399 PER_BANK_REFRESH: Hybrid Mode
9160 12:12:24.844819 TX_TRACKING: ON
9161 12:12:24.854901 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9162 12:12:24.861011 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9163 12:12:24.870746 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9164 12:12:24.873984 [FAST_K] Save calibration result to emmc
9165 12:12:24.877477 sync common calibartion params.
9166 12:12:24.877903 sync cbt_mode0:1, 1:1
9167 12:12:24.880467 dram_init: ddr_geometry: 2
9168 12:12:24.883642 dram_init: ddr_geometry: 2
9169 12:12:24.884109 dram_init: ddr_geometry: 2
9170 12:12:24.887211 0:dram_rank_size:100000000
9171 12:12:24.890670 1:dram_rank_size:100000000
9172 12:12:24.897855 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9173 12:12:24.898377 DFS_SHUFFLE_HW_MODE: ON
9174 12:12:24.900265 dramc_set_vcore_voltage set vcore to 725000
9175 12:12:24.904125 Read voltage for 1600, 0
9176 12:12:24.904642 Vio18 = 0
9177 12:12:24.906933 Vcore = 725000
9178 12:12:24.907452 Vdram = 0
9179 12:12:24.907850 Vddq = 0
9180 12:12:24.909834 Vmddr = 0
9181 12:12:24.910208 switch to 3200 Mbps bootup
9182 12:12:24.913480 [DramcRunTimeConfig]
9183 12:12:24.913898 PHYPLL
9184 12:12:24.917039 DPM_CONTROL_AFTERK: ON
9185 12:12:24.917554 PER_BANK_REFRESH: ON
9186 12:12:24.919888 REFRESH_OVERHEAD_REDUCTION: ON
9187 12:12:24.922924 CMD_PICG_NEW_MODE: OFF
9188 12:12:24.923347 XRTWTW_NEW_MODE: ON
9189 12:12:24.926792 XRTRTR_NEW_MODE: ON
9190 12:12:24.927215 TX_TRACKING: ON
9191 12:12:24.929965 RDSEL_TRACKING: OFF
9192 12:12:24.933571 DQS Precalculation for DVFS: ON
9193 12:12:24.933991 RX_TRACKING: OFF
9194 12:12:24.937315 HW_GATING DBG: ON
9195 12:12:24.937742 ZQCS_ENABLE_LP4: ON
9196 12:12:24.940047 RX_PICG_NEW_MODE: ON
9197 12:12:24.940468 TX_PICG_NEW_MODE: ON
9198 12:12:24.943167 ENABLE_RX_DCM_DPHY: ON
9199 12:12:24.946455 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9200 12:12:24.949781 DUMMY_READ_FOR_TRACKING: OFF
9201 12:12:24.952766 !!! SPM_CONTROL_AFTERK: OFF
9202 12:12:24.953521 !!! SPM could not control APHY
9203 12:12:24.956069 IMPEDANCE_TRACKING: ON
9204 12:12:24.956630 TEMP_SENSOR: ON
9205 12:12:24.959446 HW_SAVE_FOR_SR: OFF
9206 12:12:24.962797 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9207 12:12:24.966197 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9208 12:12:24.969746 Read ODT Tracking: ON
9209 12:12:24.970167 Refresh Rate DeBounce: ON
9210 12:12:24.972425 DFS_NO_QUEUE_FLUSH: ON
9211 12:12:24.976071 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9212 12:12:24.979333 ENABLE_DFS_RUNTIME_MRW: OFF
9213 12:12:24.979898 DDR_RESERVE_NEW_MODE: ON
9214 12:12:24.982361 MR_CBT_SWITCH_FREQ: ON
9215 12:12:24.986045 =========================
9216 12:12:25.004654 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9217 12:12:25.006972 dram_init: ddr_geometry: 2
9218 12:12:25.025320 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9219 12:12:25.028345 dram_init: dram init end (result: 0)
9220 12:12:25.035239 DRAM-K: Full calibration passed in 24647 msecs
9221 12:12:25.038966 MRC: failed to locate region type 0.
9222 12:12:25.039442 DRAM rank0 size:0x100000000,
9223 12:12:25.041774 DRAM rank1 size=0x100000000
9224 12:12:25.052558 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9225 12:12:25.058620 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9226 12:12:25.064932 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9227 12:12:25.074701 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9228 12:12:25.075258 DRAM rank0 size:0x100000000,
9229 12:12:25.078089 DRAM rank1 size=0x100000000
9230 12:12:25.078645 CBMEM:
9231 12:12:25.081769 IMD: root @ 0xfffff000 254 entries.
9232 12:12:25.084763 IMD: root @ 0xffffec00 62 entries.
9233 12:12:25.088352 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9234 12:12:25.095510 WARNING: RO_VPD is uninitialized or empty.
9235 12:12:25.098338 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9236 12:12:25.105715 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9237 12:12:25.118612 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9238 12:12:25.129959 BS: romstage times (exec / console): total (unknown) / 24135 ms
9239 12:12:25.130523
9240 12:12:25.130958
9241 12:12:25.139583 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9242 12:12:25.143106 ARM64: Exception handlers installed.
9243 12:12:25.146331 ARM64: Testing exception
9244 12:12:25.149315 ARM64: Done test exception
9245 12:12:25.149889 Enumerating buses...
9246 12:12:25.153552 Show all devs... Before device enumeration.
9247 12:12:25.156247 Root Device: enabled 1
9248 12:12:25.159394 CPU_CLUSTER: 0: enabled 1
9249 12:12:25.160021 CPU: 00: enabled 1
9250 12:12:25.162899 Compare with tree...
9251 12:12:25.163429 Root Device: enabled 1
9252 12:12:25.165663 CPU_CLUSTER: 0: enabled 1
9253 12:12:25.168856 CPU: 00: enabled 1
9254 12:12:25.169334 Root Device scanning...
9255 12:12:25.172873 scan_static_bus for Root Device
9256 12:12:25.176739 CPU_CLUSTER: 0 enabled
9257 12:12:25.178934 scan_static_bus for Root Device done
9258 12:12:25.181920 scan_bus: bus Root Device finished in 8 msecs
9259 12:12:25.182430 done
9260 12:12:25.188701 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9261 12:12:25.192239 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9262 12:12:25.198788 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9263 12:12:25.205062 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9264 12:12:25.205612 Allocating resources...
9265 12:12:25.208896 Reading resources...
9266 12:12:25.211821 Root Device read_resources bus 0 link: 0
9267 12:12:25.215436 DRAM rank0 size:0x100000000,
9268 12:12:25.215936 DRAM rank1 size=0x100000000
9269 12:12:25.221896 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9270 12:12:25.222377 CPU: 00 missing read_resources
9271 12:12:25.229094 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9272 12:12:25.231968 Root Device read_resources bus 0 link: 0 done
9273 12:12:25.234792 Done reading resources.
9274 12:12:25.238943 Show resources in subtree (Root Device)...After reading.
9275 12:12:25.241849 Root Device child on link 0 CPU_CLUSTER: 0
9276 12:12:25.245419 CPU_CLUSTER: 0 child on link 0 CPU: 00
9277 12:12:25.254542 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9278 12:12:25.255056 CPU: 00
9279 12:12:25.261268 Root Device assign_resources, bus 0 link: 0
9280 12:12:25.264389 CPU_CLUSTER: 0 missing set_resources
9281 12:12:25.267758 Root Device assign_resources, bus 0 link: 0 done
9282 12:12:25.271379 Done setting resources.
9283 12:12:25.274266 Show resources in subtree (Root Device)...After assigning values.
9284 12:12:25.280843 Root Device child on link 0 CPU_CLUSTER: 0
9285 12:12:25.284263 CPU_CLUSTER: 0 child on link 0 CPU: 00
9286 12:12:25.290581 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9287 12:12:25.294214 CPU: 00
9288 12:12:25.294812 Done allocating resources.
9289 12:12:25.300525 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9290 12:12:25.304409 Enabling resources...
9291 12:12:25.304965 done.
9292 12:12:25.307481 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9293 12:12:25.310126 Initializing devices...
9294 12:12:25.310586 Root Device init
9295 12:12:25.314046 init hardware done!
9296 12:12:25.317604 0x00000018: ctrlr->caps
9297 12:12:25.318178 52.000 MHz: ctrlr->f_max
9298 12:12:25.320249 0.400 MHz: ctrlr->f_min
9299 12:12:25.324048 0x40ff8080: ctrlr->voltages
9300 12:12:25.324522 sclk: 390625
9301 12:12:25.324889 Bus Width = 1
9302 12:12:25.327173 sclk: 390625
9303 12:12:25.327633 Bus Width = 1
9304 12:12:25.330376 Early init status = 3
9305 12:12:25.334706 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9306 12:12:25.338511 in-header: 03 fc 00 00 01 00 00 00
9307 12:12:25.341246 in-data: 00
9308 12:12:25.344541 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9309 12:12:25.349938 in-header: 03 fd 00 00 00 00 00 00
9310 12:12:25.353161 in-data:
9311 12:12:25.356271 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9312 12:12:25.363874 in-header: 03 fc 00 00 01 00 00 00
9313 12:12:25.364364 in-data: 00
9314 12:12:25.366712 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9315 12:12:25.374805 in-header: 03 fd 00 00 00 00 00 00
9316 12:12:25.379148 in-data:
9317 12:12:25.382205 [SSUSB] Setting up USB HOST controller...
9318 12:12:25.385085 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9319 12:12:25.388108 [SSUSB] phy power-on done.
9320 12:12:25.391319 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9321 12:12:25.398626 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9322 12:12:25.401486 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9323 12:12:25.408153 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9324 12:12:25.415124 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9325 12:12:25.421075 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9326 12:12:25.427631 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9327 12:12:25.434916 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9328 12:12:25.438224 SPM: binary array size = 0x9dc
9329 12:12:25.441013 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9330 12:12:25.447853 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9331 12:12:25.454423 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9332 12:12:25.461190 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9333 12:12:25.463985 configure_display: Starting display init
9334 12:12:25.498694 anx7625_power_on_init: Init interface.
9335 12:12:25.501796 anx7625_disable_pd_protocol: Disabled PD feature.
9336 12:12:25.505284 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9337 12:12:25.532375 anx7625_start_dp_work: Secure OCM version=00
9338 12:12:25.536013 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9339 12:12:25.550911 sp_tx_get_edid_block: EDID Block = 1
9340 12:12:25.654077 Extracted contents:
9341 12:12:25.656391 header: 00 ff ff ff ff ff ff 00
9342 12:12:25.661032 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9343 12:12:25.663127 version: 01 04
9344 12:12:25.666646 basic params: 95 1f 11 78 0a
9345 12:12:25.669666 chroma info: 76 90 94 55 54 90 27 21 50 54
9346 12:12:25.673711 established: 00 00 00
9347 12:12:25.679778 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9348 12:12:25.683108 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9349 12:12:25.689302 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9350 12:12:25.696859 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9351 12:12:25.702856 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9352 12:12:25.705904 extensions: 00
9353 12:12:25.706437 checksum: fb
9354 12:12:25.706814
9355 12:12:25.709855 Manufacturer: IVO Model 57d Serial Number 0
9356 12:12:25.712784 Made week 0 of 2020
9357 12:12:25.716472 EDID version: 1.4
9358 12:12:25.717022 Digital display
9359 12:12:25.719387 6 bits per primary color channel
9360 12:12:25.720000 DisplayPort interface
9361 12:12:25.722289 Maximum image size: 31 cm x 17 cm
9362 12:12:25.726090 Gamma: 220%
9363 12:12:25.726623 Check DPMS levels
9364 12:12:25.732455 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9365 12:12:25.735384 First detailed timing is preferred timing
9366 12:12:25.735916 Established timings supported:
9367 12:12:25.739043 Standard timings supported:
9368 12:12:25.742408 Detailed timings
9369 12:12:25.745932 Hex of detail: 383680a07038204018303c0035ae10000019
9370 12:12:25.752050 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9371 12:12:25.756084 0780 0798 07c8 0820 hborder 0
9372 12:12:25.758441 0438 043b 0447 0458 vborder 0
9373 12:12:25.762053 -hsync -vsync
9374 12:12:25.762608 Did detailed timing
9375 12:12:25.768564 Hex of detail: 000000000000000000000000000000000000
9376 12:12:25.771813 Manufacturer-specified data, tag 0
9377 12:12:25.775910 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9378 12:12:25.778690 ASCII string: InfoVision
9379 12:12:25.782269 Hex of detail: 000000fe00523134304e574635205248200a
9380 12:12:25.785380 ASCII string: R140NWF5 RH
9381 12:12:25.785837 Checksum
9382 12:12:25.788004 Checksum: 0xfb (valid)
9383 12:12:25.792518 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9384 12:12:25.795047 DSI data_rate: 832800000 bps
9385 12:12:25.801384 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9386 12:12:25.805392 anx7625_parse_edid: pixelclock(138800).
9387 12:12:25.808047 hactive(1920), hsync(48), hfp(24), hbp(88)
9388 12:12:25.811772 vactive(1080), vsync(12), vfp(3), vbp(17)
9389 12:12:25.814856 anx7625_dsi_config: config dsi.
9390 12:12:25.821299 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9391 12:12:25.835172 anx7625_dsi_config: success to config DSI
9392 12:12:25.838546 anx7625_dp_start: MIPI phy setup OK.
9393 12:12:25.842366 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9394 12:12:25.845465 mtk_ddp_mode_set invalid vrefresh 60
9395 12:12:25.848535 main_disp_path_setup
9396 12:12:25.849000 ovl_layer_smi_id_en
9397 12:12:25.852010 ovl_layer_smi_id_en
9398 12:12:25.852646 ccorr_config
9399 12:12:25.853025 aal_config
9400 12:12:25.855239 gamma_config
9401 12:12:25.855786 postmask_config
9402 12:12:25.858206 dither_config
9403 12:12:25.861291 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9404 12:12:25.868737 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9405 12:12:25.871800 Root Device init finished in 556 msecs
9406 12:12:25.875294 CPU_CLUSTER: 0 init
9407 12:12:25.881658 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9408 12:12:25.888676 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9409 12:12:25.889254 APU_MBOX 0x190000b0 = 0x10001
9410 12:12:25.891455 APU_MBOX 0x190001b0 = 0x10001
9411 12:12:25.894271 APU_MBOX 0x190005b0 = 0x10001
9412 12:12:25.898252 APU_MBOX 0x190006b0 = 0x10001
9413 12:12:25.904479 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9414 12:12:25.914949 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9415 12:12:25.927644 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9416 12:12:25.933058 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9417 12:12:25.945396 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9418 12:12:25.953949 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9419 12:12:25.957460 CPU_CLUSTER: 0 init finished in 81 msecs
9420 12:12:25.961434 Devices initialized
9421 12:12:25.964183 Show all devs... After init.
9422 12:12:25.964650 Root Device: enabled 1
9423 12:12:25.967436 CPU_CLUSTER: 0: enabled 1
9424 12:12:25.970412 CPU: 00: enabled 1
9425 12:12:25.974079 BS: BS_DEV_INIT run times (exec / console): 215 / 447 ms
9426 12:12:25.977134 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9427 12:12:25.980337 ELOG: NV offset 0x57f000 size 0x1000
9428 12:12:25.987329 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9429 12:12:25.993753 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9430 12:12:25.996913 ELOG: Event(17) added with size 13 at 2024-01-31 12:12:26 UTC
9431 12:12:26.000274 out: cmd=0x121: 03 db 21 01 00 00 00 00
9432 12:12:26.004483 in-header: 03 a7 00 00 2c 00 00 00
9433 12:12:26.017815 in-data: b8 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9434 12:12:26.024759 ELOG: Event(A1) added with size 10 at 2024-01-31 12:12:26 UTC
9435 12:12:26.030673 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9436 12:12:26.037279 ELOG: Event(A0) added with size 9 at 2024-01-31 12:12:26 UTC
9437 12:12:26.040413 elog_add_boot_reason: Logged dev mode boot
9438 12:12:26.044012 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9439 12:12:26.047580 Finalize devices...
9440 12:12:26.048129 Devices finalized
9441 12:12:26.053832 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9442 12:12:26.057199 Writing coreboot table at 0xffe64000
9443 12:12:26.060217 0. 000000000010a000-0000000000113fff: RAMSTAGE
9444 12:12:26.064380 1. 0000000040000000-00000000400fffff: RAM
9445 12:12:26.070917 2. 0000000040100000-000000004032afff: RAMSTAGE
9446 12:12:26.074307 3. 000000004032b000-00000000545fffff: RAM
9447 12:12:26.076863 4. 0000000054600000-000000005465ffff: BL31
9448 12:12:26.080163 5. 0000000054660000-00000000ffe63fff: RAM
9449 12:12:26.086939 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9450 12:12:26.090179 7. 0000000100000000-000000023fffffff: RAM
9451 12:12:26.093440 Passing 5 GPIOs to payload:
9452 12:12:26.096811 NAME | PORT | POLARITY | VALUE
9453 12:12:26.100104 EC in RW | 0x000000aa | low | undefined
9454 12:12:26.106352 EC interrupt | 0x00000005 | low | undefined
9455 12:12:26.110223 TPM interrupt | 0x000000ab | high | undefined
9456 12:12:26.116637 SD card detect | 0x00000011 | high | undefined
9457 12:12:26.119961 speaker enable | 0x00000093 | high | undefined
9458 12:12:26.123233 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9459 12:12:26.126475 in-header: 03 f9 00 00 02 00 00 00
9460 12:12:26.130716 in-data: 02 00
9461 12:12:26.131140 ADC[4]: Raw value=901552 ID=7
9462 12:12:26.132873 ADC[3]: Raw value=213282 ID=1
9463 12:12:26.136469 RAM Code: 0x71
9464 12:12:26.136925 ADC[6]: Raw value=75036 ID=0
9465 12:12:26.139905 ADC[5]: Raw value=213282 ID=1
9466 12:12:26.142874 SKU Code: 0x1
9467 12:12:26.146855 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3c95
9468 12:12:26.149988 coreboot table: 964 bytes.
9469 12:12:26.153095 IMD ROOT 0. 0xfffff000 0x00001000
9470 12:12:26.156421 IMD SMALL 1. 0xffffe000 0x00001000
9471 12:12:26.159789 RO MCACHE 2. 0xffffc000 0x00001104
9472 12:12:26.162935 CONSOLE 3. 0xfff7c000 0x00080000
9473 12:12:26.166571 FMAP 4. 0xfff7b000 0x00000452
9474 12:12:26.169575 TIME STAMP 5. 0xfff7a000 0x00000910
9475 12:12:26.172654 VBOOT WORK 6. 0xfff66000 0x00014000
9476 12:12:26.175789 RAMOOPS 7. 0xffe66000 0x00100000
9477 12:12:26.179184 COREBOOT 8. 0xffe64000 0x00002000
9478 12:12:26.182766 IMD small region:
9479 12:12:26.185726 IMD ROOT 0. 0xffffec00 0x00000400
9480 12:12:26.188959 VPD 1. 0xffffeb80 0x0000006c
9481 12:12:26.192392 MMC STATUS 2. 0xffffeb60 0x00000004
9482 12:12:26.196070 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9483 12:12:26.199082 Probing TPM: done!
9484 12:12:26.202442 Connected to device vid:did:rid of 1ae0:0028:00
9485 12:12:26.212869 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9486 12:12:26.217284 Initialized TPM device CR50 revision 0
9487 12:12:26.219932 Checking cr50 for pending updates
9488 12:12:26.223981 Reading cr50 TPM mode
9489 12:12:26.232242 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9490 12:12:26.239550 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9491 12:12:26.279381 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9492 12:12:26.282681 Checking segment from ROM address 0x40100000
9493 12:12:26.285504 Checking segment from ROM address 0x4010001c
9494 12:12:26.292221 Loading segment from ROM address 0x40100000
9495 12:12:26.292790 code (compression=0)
9496 12:12:26.302298 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9497 12:12:26.309337 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9498 12:12:26.309908 it's not compressed!
9499 12:12:26.315776 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9500 12:12:26.322607 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9501 12:12:26.339210 Loading segment from ROM address 0x4010001c
9502 12:12:26.339989 Entry Point 0x80000000
9503 12:12:26.343639 Loaded segments
9504 12:12:26.346447 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9505 12:12:26.352997 Jumping to boot code at 0x80000000(0xffe64000)
9506 12:12:26.359876 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9507 12:12:26.366634 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9508 12:12:26.374483 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9509 12:12:26.377388 Checking segment from ROM address 0x40100000
9510 12:12:26.380363 Checking segment from ROM address 0x4010001c
9511 12:12:26.386836 Loading segment from ROM address 0x40100000
9512 12:12:26.387332 code (compression=1)
9513 12:12:26.393876 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9514 12:12:26.403574 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9515 12:12:26.404070 using LZMA
9516 12:12:26.412662 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9517 12:12:26.419019 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9518 12:12:26.422751 Loading segment from ROM address 0x4010001c
9519 12:12:26.423320 Entry Point 0x54601000
9520 12:12:26.426030 Loaded segments
9521 12:12:26.428905 NOTICE: MT8192 bl31_setup
9522 12:12:26.436418 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9523 12:12:26.439285 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9524 12:12:26.442681 WARNING: region 0:
9525 12:12:26.445845 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9526 12:12:26.446417 WARNING: region 1:
9527 12:12:26.452054 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9528 12:12:26.455923 WARNING: region 2:
9529 12:12:26.459277 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9530 12:12:26.462318 WARNING: region 3:
9531 12:12:26.465626 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9532 12:12:26.468971 WARNING: region 4:
9533 12:12:26.475788 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9534 12:12:26.476279 WARNING: region 5:
9535 12:12:26.478757 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9536 12:12:26.482034 WARNING: region 6:
9537 12:12:26.485430 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9538 12:12:26.488496 WARNING: region 7:
9539 12:12:26.491848 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9540 12:12:26.498744 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9541 12:12:26.501661 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9542 12:12:26.508681 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9543 12:12:26.512031 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9544 12:12:26.514693 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9545 12:12:26.522313 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9546 12:12:26.524849 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9547 12:12:26.528148 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9548 12:12:26.535226 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9549 12:12:26.538646 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9550 12:12:26.544867 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9551 12:12:26.548157 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9552 12:12:26.551607 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9553 12:12:26.557839 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9554 12:12:26.561713 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9555 12:12:26.565998 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9556 12:12:26.571285 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9557 12:12:26.574431 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9558 12:12:26.581314 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9559 12:12:26.584633 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9560 12:12:26.587814 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9561 12:12:26.594569 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9562 12:12:26.597829 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9563 12:12:26.604903 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9564 12:12:26.608345 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9565 12:12:26.611081 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9566 12:12:26.617439 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9567 12:12:26.621237 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9568 12:12:26.627599 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9569 12:12:26.631497 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9570 12:12:26.634540 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9571 12:12:26.640704 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9572 12:12:26.644217 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9573 12:12:26.648102 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9574 12:12:26.654721 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9575 12:12:26.657101 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9576 12:12:26.661082 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9577 12:12:26.664069 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9578 12:12:26.670303 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9579 12:12:26.673618 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9580 12:12:26.676711 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9581 12:12:26.681025 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9582 12:12:26.686875 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9583 12:12:26.690712 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9584 12:12:26.694424 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9585 12:12:26.696672 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9586 12:12:26.703932 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9587 12:12:26.706962 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9588 12:12:26.710384 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9589 12:12:26.717214 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9590 12:12:26.719823 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9591 12:12:26.727835 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9592 12:12:26.729559 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9593 12:12:26.736313 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9594 12:12:26.739587 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9595 12:12:26.743269 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9596 12:12:26.750195 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9597 12:12:26.753068 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9598 12:12:26.760270 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9599 12:12:26.763877 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9600 12:12:26.769696 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9601 12:12:26.772721 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9602 12:12:26.779727 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9603 12:12:26.783182 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9604 12:12:26.789667 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9605 12:12:26.792634 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9606 12:12:26.796643 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9607 12:12:26.803108 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9608 12:12:26.807049 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9609 12:12:26.812712 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9610 12:12:26.816094 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9611 12:12:26.822490 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9612 12:12:26.826809 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9613 12:12:26.829182 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9614 12:12:26.835959 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9615 12:12:26.839468 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9616 12:12:26.845642 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9617 12:12:26.849145 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9618 12:12:26.856100 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9619 12:12:26.859704 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9620 12:12:26.866417 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9621 12:12:26.868968 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9622 12:12:26.872544 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9623 12:12:26.879354 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9624 12:12:26.882267 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9625 12:12:26.888875 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9626 12:12:26.892444 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9627 12:12:26.898841 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9628 12:12:26.902117 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9629 12:12:26.906010 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9630 12:12:26.912779 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9631 12:12:26.915731 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9632 12:12:26.922551 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9633 12:12:26.926259 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9634 12:12:26.932257 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9635 12:12:26.934980 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9636 12:12:26.939453 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9637 12:12:26.945754 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9638 12:12:26.948905 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9639 12:12:26.952187 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9640 12:12:26.955434 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9641 12:12:26.963026 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9642 12:12:26.965547 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9643 12:12:26.971803 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9644 12:12:26.975248 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9645 12:12:26.978527 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9646 12:12:26.985454 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9647 12:12:26.988691 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9648 12:12:26.995279 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9649 12:12:26.998515 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9650 12:12:27.001639 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9651 12:12:27.008506 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9652 12:12:27.012405 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9653 12:12:27.018363 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9654 12:12:27.021223 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9655 12:12:27.025308 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9656 12:12:27.031624 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9657 12:12:27.034696 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9658 12:12:27.038298 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9659 12:12:27.044319 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9660 12:12:27.048332 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9661 12:12:27.052139 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9662 12:12:27.054598 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9663 12:12:27.060908 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9664 12:12:27.064517 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9665 12:12:27.068146 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9666 12:12:27.075037 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9667 12:12:27.078071 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9668 12:12:27.084332 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9669 12:12:27.087975 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9670 12:12:27.091864 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9671 12:12:27.098503 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9672 12:12:27.101109 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9673 12:12:27.108066 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9674 12:12:27.110944 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9675 12:12:27.113995 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9676 12:12:27.120750 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9677 12:12:27.124323 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9678 12:12:27.131043 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9679 12:12:27.133991 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9680 12:12:27.137067 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9681 12:12:27.143822 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9682 12:12:27.147233 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9683 12:12:27.153392 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9684 12:12:27.157152 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9685 12:12:27.160758 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9686 12:12:27.166768 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9687 12:12:27.170311 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9688 12:12:27.176846 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9689 12:12:27.179766 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9690 12:12:27.183541 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9691 12:12:27.190229 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9692 12:12:27.193370 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9693 12:12:27.200583 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9694 12:12:27.203113 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9695 12:12:27.207163 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9696 12:12:27.213460 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9697 12:12:27.216328 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9698 12:12:27.223320 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9699 12:12:27.226756 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9700 12:12:27.229790 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9701 12:12:27.236247 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9702 12:12:27.240398 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9703 12:12:27.246407 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9704 12:12:27.249086 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9705 12:12:27.253282 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9706 12:12:27.259838 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9707 12:12:27.263110 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9708 12:12:27.269145 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9709 12:12:27.273351 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9710 12:12:27.275788 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9711 12:12:27.282905 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9712 12:12:27.286188 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9713 12:12:27.292287 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9714 12:12:27.296150 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9715 12:12:27.299380 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9716 12:12:27.305339 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9717 12:12:27.308789 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9718 12:12:27.316002 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9719 12:12:27.318708 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9720 12:12:27.322367 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9721 12:12:27.329311 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9722 12:12:27.332339 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9723 12:12:27.339031 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9724 12:12:27.341728 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9725 12:12:27.344884 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9726 12:12:27.351927 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9727 12:12:27.355487 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9728 12:12:27.361148 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9729 12:12:27.365457 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9730 12:12:27.371646 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9731 12:12:27.374700 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9732 12:12:27.378119 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9733 12:12:27.384392 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9734 12:12:27.387772 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9735 12:12:27.394999 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9736 12:12:27.398362 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9737 12:12:27.401014 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9738 12:12:27.408225 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9739 12:12:27.411531 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9740 12:12:27.418278 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9741 12:12:27.421459 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9742 12:12:27.427996 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9743 12:12:27.431054 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9744 12:12:27.434934 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9745 12:12:27.441325 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9746 12:12:27.444218 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9747 12:12:27.450916 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9748 12:12:27.454812 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9749 12:12:27.460587 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9750 12:12:27.463712 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9751 12:12:27.467938 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9752 12:12:27.474131 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9753 12:12:27.477241 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9754 12:12:27.483562 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9755 12:12:27.487294 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9756 12:12:27.490527 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9757 12:12:27.497335 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9758 12:12:27.500645 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9759 12:12:27.507269 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9760 12:12:27.510699 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9761 12:12:27.517515 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9762 12:12:27.520554 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9763 12:12:27.523433 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9764 12:12:27.530623 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9765 12:12:27.533787 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9766 12:12:27.540405 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9767 12:12:27.544002 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9768 12:12:27.550234 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9769 12:12:27.553397 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9770 12:12:27.556982 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9771 12:12:27.559849 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9772 12:12:27.563431 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9773 12:12:27.569916 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9774 12:12:27.573409 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9775 12:12:27.576599 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9776 12:12:27.582967 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9777 12:12:27.586738 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9778 12:12:27.589667 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9779 12:12:27.596448 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9780 12:12:27.599482 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9781 12:12:27.606749 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9782 12:12:27.610325 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9783 12:12:27.613020 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9784 12:12:27.619280 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9785 12:12:27.622764 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9786 12:12:27.629521 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9787 12:12:27.632352 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9788 12:12:27.635547 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9789 12:12:27.641763 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9790 12:12:27.645242 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9791 12:12:27.651808 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9792 12:12:27.655722 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9793 12:12:27.659097 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9794 12:12:27.665411 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9795 12:12:27.668649 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9796 12:12:27.671666 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9797 12:12:27.678847 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9798 12:12:27.681796 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9799 12:12:27.684973 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9800 12:12:27.691953 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9801 12:12:27.695180 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9802 12:12:27.701507 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9803 12:12:27.704694 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9804 12:12:27.708421 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9805 12:12:27.715437 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9806 12:12:27.718084 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9807 12:12:27.724769 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9808 12:12:27.728905 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9809 12:12:27.731664 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9810 12:12:27.735426 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9811 12:12:27.738109 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9812 12:12:27.744365 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9813 12:12:27.747372 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9814 12:12:27.751064 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9815 12:12:27.754030 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9816 12:12:27.761446 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9817 12:12:27.764415 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9818 12:12:27.768002 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9819 12:12:27.770660 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9820 12:12:27.777547 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9821 12:12:27.781049 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9822 12:12:27.787444 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9823 12:12:27.790690 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9824 12:12:27.794024 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9825 12:12:27.800945 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9826 12:12:27.803926 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9827 12:12:27.810889 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9828 12:12:27.813696 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9829 12:12:27.817213 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9830 12:12:27.823580 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9831 12:12:27.827355 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9832 12:12:27.833513 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9833 12:12:27.836625 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9834 12:12:27.843446 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9835 12:12:27.847170 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9836 12:12:27.849966 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9837 12:12:27.857108 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9838 12:12:27.859625 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9839 12:12:27.866989 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9840 12:12:27.869682 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9841 12:12:27.876295 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9842 12:12:27.879937 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9843 12:12:27.883297 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9844 12:12:27.889657 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9845 12:12:27.892969 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9846 12:12:27.899973 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9847 12:12:27.903105 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9848 12:12:27.906729 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9849 12:12:27.912621 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9850 12:12:27.915964 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9851 12:12:27.922736 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9852 12:12:27.925952 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9853 12:12:27.929402 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9854 12:12:27.935727 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9855 12:12:27.939855 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9856 12:12:27.945632 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9857 12:12:27.948762 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9858 12:12:27.955663 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9859 12:12:27.959089 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9860 12:12:27.965787 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9861 12:12:27.969024 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9862 12:12:27.972001 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9863 12:12:27.978794 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9864 12:12:27.982029 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9865 12:12:27.989335 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9866 12:12:27.992311 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9867 12:12:27.995368 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9868 12:12:28.001923 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9869 12:12:28.004871 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9870 12:12:28.012037 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9871 12:12:28.015205 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9872 12:12:28.018955 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9873 12:12:28.025547 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9874 12:12:28.028882 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9875 12:12:28.035039 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9876 12:12:28.038388 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9877 12:12:28.042061 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9878 12:12:28.048655 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9879 12:12:28.051796 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9880 12:12:28.058395 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9881 12:12:28.062311 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9882 12:12:28.068607 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9883 12:12:28.071010 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9884 12:12:28.074345 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9885 12:12:28.080956 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9886 12:12:28.084224 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9887 12:12:28.091529 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9888 12:12:28.095027 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9889 12:12:28.098191 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9890 12:12:28.104569 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9891 12:12:28.107609 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9892 12:12:28.114840 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9893 12:12:28.117894 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9894 12:12:28.121212 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9895 12:12:28.127845 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9896 12:12:28.130710 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9897 12:12:28.137359 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9898 12:12:28.141305 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9899 12:12:28.147406 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9900 12:12:28.150142 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9901 12:12:28.157219 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9902 12:12:28.160663 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9903 12:12:28.167356 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9904 12:12:28.170683 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9905 12:12:28.173775 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9906 12:12:28.180600 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9907 12:12:28.183723 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9908 12:12:28.190541 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9909 12:12:28.192917 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9910 12:12:28.199559 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9911 12:12:28.202908 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9912 12:12:28.209826 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9913 12:12:28.212572 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9914 12:12:28.216349 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9915 12:12:28.222631 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9916 12:12:28.226610 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9917 12:12:28.232687 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9918 12:12:28.236425 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9919 12:12:28.243345 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9920 12:12:28.246492 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9921 12:12:28.252415 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9922 12:12:28.255586 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9923 12:12:28.259790 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9924 12:12:28.266393 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9925 12:12:28.268829 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9926 12:12:28.275624 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9927 12:12:28.278998 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9928 12:12:28.286078 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9929 12:12:28.288718 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9930 12:12:28.295369 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9931 12:12:28.298509 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9932 12:12:28.302630 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9933 12:12:28.309052 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9934 12:12:28.311869 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9935 12:12:28.319165 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9936 12:12:28.322095 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9937 12:12:28.328441 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9938 12:12:28.332161 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9939 12:12:28.338453 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9940 12:12:28.342438 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9941 12:12:28.345035 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9942 12:12:28.351444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9943 12:12:28.355202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9944 12:12:28.361794 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9945 12:12:28.364635 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9946 12:12:28.371435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9947 12:12:28.374865 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9948 12:12:28.381481 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9949 12:12:28.384713 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9950 12:12:28.391336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9951 12:12:28.394443 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9952 12:12:28.401929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9953 12:12:28.404670 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9954 12:12:28.408068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9955 12:12:28.414747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9956 12:12:28.417693 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9957 12:12:28.424454 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9958 12:12:28.427887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9959 12:12:28.434793 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9960 12:12:28.437628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9961 12:12:28.444194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9962 12:12:28.447058 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9963 12:12:28.453858 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9964 12:12:28.457691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9965 12:12:28.464264 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9966 12:12:28.467764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9967 12:12:28.474508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9968 12:12:28.480134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9969 12:12:28.484021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9970 12:12:28.490899 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9971 12:12:28.494009 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9972 12:12:28.500255 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9973 12:12:28.503245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9974 12:12:28.507097 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9975 12:12:28.510810 INFO: [APUAPC] vio 0
9976 12:12:28.514229 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9977 12:12:28.520721 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9978 12:12:28.523235 INFO: [APUAPC] D0_APC_0: 0x400510
9979 12:12:28.527317 INFO: [APUAPC] D0_APC_1: 0x0
9980 12:12:28.530294 INFO: [APUAPC] D0_APC_2: 0x1540
9981 12:12:28.530875 INFO: [APUAPC] D0_APC_3: 0x0
9982 12:12:28.537069 INFO: [APUAPC] D1_APC_0: 0xffffffff
9983 12:12:28.539710 INFO: [APUAPC] D1_APC_1: 0xffffffff
9984 12:12:28.543310 INFO: [APUAPC] D1_APC_2: 0x3fffff
9985 12:12:28.543914 INFO: [APUAPC] D1_APC_3: 0x0
9986 12:12:28.547322 INFO: [APUAPC] D2_APC_0: 0xffffffff
9987 12:12:28.553835 INFO: [APUAPC] D2_APC_1: 0xffffffff
9988 12:12:28.554355 INFO: [APUAPC] D2_APC_2: 0x3fffff
9989 12:12:28.556750 INFO: [APUAPC] D2_APC_3: 0x0
9990 12:12:28.559875 INFO: [APUAPC] D3_APC_0: 0xffffffff
9991 12:12:28.563539 INFO: [APUAPC] D3_APC_1: 0xffffffff
9992 12:12:28.566908 INFO: [APUAPC] D3_APC_2: 0x3fffff
9993 12:12:28.570412 INFO: [APUAPC] D3_APC_3: 0x0
9994 12:12:28.573116 INFO: [APUAPC] D4_APC_0: 0xffffffff
9995 12:12:28.576273 INFO: [APUAPC] D4_APC_1: 0xffffffff
9996 12:12:28.580049 INFO: [APUAPC] D4_APC_2: 0x3fffff
9997 12:12:28.582526 INFO: [APUAPC] D4_APC_3: 0x0
9998 12:12:28.586161 INFO: [APUAPC] D5_APC_0: 0xffffffff
9999 12:12:28.589688 INFO: [APUAPC] D5_APC_1: 0xffffffff
10000 12:12:28.593016 INFO: [APUAPC] D5_APC_2: 0x3fffff
10001 12:12:28.596338 INFO: [APUAPC] D5_APC_3: 0x0
10002 12:12:28.599961 INFO: [APUAPC] D6_APC_0: 0xffffffff
10003 12:12:28.602976 INFO: [APUAPC] D6_APC_1: 0xffffffff
10004 12:12:28.606086 INFO: [APUAPC] D6_APC_2: 0x3fffff
10005 12:12:28.610329 INFO: [APUAPC] D6_APC_3: 0x0
10006 12:12:28.613154 INFO: [APUAPC] D7_APC_0: 0xffffffff
10007 12:12:28.617154 INFO: [APUAPC] D7_APC_1: 0xffffffff
10008 12:12:28.620427 INFO: [APUAPC] D7_APC_2: 0x3fffff
10009 12:12:28.622918 INFO: [APUAPC] D7_APC_3: 0x0
10010 12:12:28.626987 INFO: [APUAPC] D8_APC_0: 0xffffffff
10011 12:12:28.629120 INFO: [APUAPC] D8_APC_1: 0xffffffff
10012 12:12:28.632594 INFO: [APUAPC] D8_APC_2: 0x3fffff
10013 12:12:28.636236 INFO: [APUAPC] D8_APC_3: 0x0
10014 12:12:28.639303 INFO: [APUAPC] D9_APC_0: 0xffffffff
10015 12:12:28.642270 INFO: [APUAPC] D9_APC_1: 0xffffffff
10016 12:12:28.646378 INFO: [APUAPC] D9_APC_2: 0x3fffff
10017 12:12:28.649005 INFO: [APUAPC] D9_APC_3: 0x0
10018 12:12:28.652477 INFO: [APUAPC] D10_APC_0: 0xffffffff
10019 12:12:28.656183 INFO: [APUAPC] D10_APC_1: 0xffffffff
10020 12:12:28.659108 INFO: [APUAPC] D10_APC_2: 0x3fffff
10021 12:12:28.662969 INFO: [APUAPC] D10_APC_3: 0x0
10022 12:12:28.665228 INFO: [APUAPC] D11_APC_0: 0xffffffff
10023 12:12:28.669471 INFO: [APUAPC] D11_APC_1: 0xffffffff
10024 12:12:28.671877 INFO: [APUAPC] D11_APC_2: 0x3fffff
10025 12:12:28.675281 INFO: [APUAPC] D11_APC_3: 0x0
10026 12:12:28.678712 INFO: [APUAPC] D12_APC_0: 0xffffffff
10027 12:12:28.681871 INFO: [APUAPC] D12_APC_1: 0xffffffff
10028 12:12:28.685862 INFO: [APUAPC] D12_APC_2: 0x3fffff
10029 12:12:28.688556 INFO: [APUAPC] D12_APC_3: 0x0
10030 12:12:28.692111 INFO: [APUAPC] D13_APC_0: 0xffffffff
10031 12:12:28.695314 INFO: [APUAPC] D13_APC_1: 0xffffffff
10032 12:12:28.698930 INFO: [APUAPC] D13_APC_2: 0x3fffff
10033 12:12:28.702162 INFO: [APUAPC] D13_APC_3: 0x0
10034 12:12:28.704985 INFO: [APUAPC] D14_APC_0: 0xffffffff
10035 12:12:28.709227 INFO: [APUAPC] D14_APC_1: 0xffffffff
10036 12:12:28.711937 INFO: [APUAPC] D14_APC_2: 0x3fffff
10037 12:12:28.715768 INFO: [APUAPC] D14_APC_3: 0x0
10038 12:12:28.718673 INFO: [APUAPC] D15_APC_0: 0xffffffff
10039 12:12:28.722008 INFO: [APUAPC] D15_APC_1: 0xffffffff
10040 12:12:28.725294 INFO: [APUAPC] D15_APC_2: 0x3fffff
10041 12:12:28.729514 INFO: [APUAPC] D15_APC_3: 0x0
10042 12:12:28.731840 INFO: [APUAPC] APC_CON: 0x4
10043 12:12:28.735480 INFO: [NOCDAPC] D0_APC_0: 0x0
10044 12:12:28.738317 INFO: [NOCDAPC] D0_APC_1: 0x0
10045 12:12:28.741561 INFO: [NOCDAPC] D1_APC_0: 0x0
10046 12:12:28.745225 INFO: [NOCDAPC] D1_APC_1: 0xfff
10047 12:12:28.745745 INFO: [NOCDAPC] D2_APC_0: 0x0
10048 12:12:28.748047 INFO: [NOCDAPC] D2_APC_1: 0xfff
10049 12:12:28.751258 INFO: [NOCDAPC] D3_APC_0: 0x0
10050 12:12:28.754826 INFO: [NOCDAPC] D3_APC_1: 0xfff
10051 12:12:28.758337 INFO: [NOCDAPC] D4_APC_0: 0x0
10052 12:12:28.761959 INFO: [NOCDAPC] D4_APC_1: 0xfff
10053 12:12:28.764644 INFO: [NOCDAPC] D5_APC_0: 0x0
10054 12:12:28.767904 INFO: [NOCDAPC] D5_APC_1: 0xfff
10055 12:12:28.771824 INFO: [NOCDAPC] D6_APC_0: 0x0
10056 12:12:28.775593 INFO: [NOCDAPC] D6_APC_1: 0xfff
10057 12:12:28.778398 INFO: [NOCDAPC] D7_APC_0: 0x0
10058 12:12:28.778908 INFO: [NOCDAPC] D7_APC_1: 0xfff
10059 12:12:28.781445 INFO: [NOCDAPC] D8_APC_0: 0x0
10060 12:12:28.784352 INFO: [NOCDAPC] D8_APC_1: 0xfff
10061 12:12:28.788057 INFO: [NOCDAPC] D9_APC_0: 0x0
10062 12:12:28.791343 INFO: [NOCDAPC] D9_APC_1: 0xfff
10063 12:12:28.795358 INFO: [NOCDAPC] D10_APC_0: 0x0
10064 12:12:28.797819 INFO: [NOCDAPC] D10_APC_1: 0xfff
10065 12:12:28.800804 INFO: [NOCDAPC] D11_APC_0: 0x0
10066 12:12:28.804841 INFO: [NOCDAPC] D11_APC_1: 0xfff
10067 12:12:28.807509 INFO: [NOCDAPC] D12_APC_0: 0x0
10068 12:12:28.810805 INFO: [NOCDAPC] D12_APC_1: 0xfff
10069 12:12:28.814327 INFO: [NOCDAPC] D13_APC_0: 0x0
10070 12:12:28.818211 INFO: [NOCDAPC] D13_APC_1: 0xfff
10071 12:12:28.821144 INFO: [NOCDAPC] D14_APC_0: 0x0
10072 12:12:28.824098 INFO: [NOCDAPC] D14_APC_1: 0xfff
10073 12:12:28.824527 INFO: [NOCDAPC] D15_APC_0: 0x0
10074 12:12:28.828682 INFO: [NOCDAPC] D15_APC_1: 0xfff
10075 12:12:28.831558 INFO: [NOCDAPC] APC_CON: 0x4
10076 12:12:28.834138 INFO: [APUAPC] set_apusys_apc done
10077 12:12:28.837233 INFO: [DEVAPC] devapc_init done
10078 12:12:28.843982 INFO: GICv3 without legacy support detected.
10079 12:12:28.846920 INFO: ARM GICv3 driver initialized in EL3
10080 12:12:28.850409 INFO: Maximum SPI INTID supported: 639
10081 12:12:28.853882 INFO: BL31: Initializing runtime services
10082 12:12:28.860488 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10083 12:12:28.863273 INFO: SPM: enable CPC mode
10084 12:12:28.866888 INFO: mcdi ready for mcusys-off-idle and system suspend
10085 12:12:28.873413 INFO: BL31: Preparing for EL3 exit to normal world
10086 12:12:28.876643 INFO: Entry point address = 0x80000000
10087 12:12:28.877110 INFO: SPSR = 0x8
10088 12:12:28.884689
10089 12:12:28.885251
10090 12:12:28.885618
10091 12:12:28.887853 Starting depthcharge on Spherion...
10092 12:12:28.888409
10093 12:12:28.888776 Wipe memory regions:
10094 12:12:28.889116
10095 12:12:28.891811 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10096 12:12:28.892348 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10097 12:12:28.892797 Setting prompt string to ['asurada:']
10098 12:12:28.893232 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10099 12:12:28.893980 [0x00000040000000, 0x00000054600000)
10100 12:12:29.013213
10101 12:12:29.013772 [0x00000054660000, 0x00000080000000)
10102 12:12:29.273171
10103 12:12:29.273801 [0x000000821a7280, 0x000000ffe64000)
10104 12:12:30.018874
10105 12:12:30.019424 [0x00000100000000, 0x00000240000000)
10106 12:12:31.908048
10107 12:12:31.911168 Initializing XHCI USB controller at 0x11200000.
10108 12:12:32.893209
10109 12:12:32.893765 R8152: Initializing
10110 12:12:32.894167
10111 12:12:32.896075 Version 9 (ocp_data = 6010)
10112 12:12:32.896532
10113 12:12:32.899105 R8152: Done initializing
10114 12:12:32.899660
10115 12:12:32.900095 Adding net device
10116 12:12:33.298799
10117 12:12:33.301841 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10118 12:12:33.302421
10119 12:12:33.302787
10120 12:12:33.303128
10121 12:12:33.304004 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10123 12:12:33.405739 asurada: tftpboot 192.168.201.1 12669528/tftp-deploy-1gcokwmw/kernel/image.itb 12669528/tftp-deploy-1gcokwmw/kernel/cmdline
10124 12:12:33.406389 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10125 12:12:33.406873 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10126 12:12:33.412405 tftpboot 192.168.201.1 12669528/tftp-deploy-1gcokwmw/kernel/image.itp-deploy-1gcokwmw/kernel/cmdline
10127 12:12:33.413161
10128 12:12:33.413708 Waiting for link
10129 12:12:33.613446
10130 12:12:33.614072 done.
10131 12:12:33.614514
10132 12:12:33.614881 MAC: f4:f5:e8:50:de:0a
10133 12:12:33.615285
10134 12:12:33.616558 Sending DHCP discover... done.
10135 12:12:33.617014
10136 12:12:33.619924 Waiting for reply... done.
10137 12:12:33.620383
10138 12:12:33.624176 Sending DHCP request... done.
10139 12:12:33.624638
10140 12:12:33.628492 Waiting for reply... done.
10141 12:12:33.628948
10142 12:12:33.629312 My ip is 192.168.201.14
10143 12:12:33.629761
10144 12:12:33.632093 The DHCP server ip is 192.168.201.1
10145 12:12:33.632553
10146 12:12:33.638262 TFTP server IP predefined by user: 192.168.201.1
10147 12:12:33.638820
10148 12:12:33.644558 Bootfile predefined by user: 12669528/tftp-deploy-1gcokwmw/kernel/image.itb
10149 12:12:33.645020
10150 12:12:33.647931 Sending tftp read request... done.
10151 12:12:33.648513
10152 12:12:33.654392 Waiting for the transfer...
10153 12:12:33.654999
10154 12:12:33.928386 00000000 ################################################################
10155 12:12:33.928535
10156 12:12:34.181574 00080000 ################################################################
10157 12:12:34.181711
10158 12:12:34.435545 00100000 ################################################################
10159 12:12:34.435749
10160 12:12:34.678966 00180000 ################################################################
10161 12:12:34.679096
10162 12:12:34.942982 00200000 ################################################################
10163 12:12:34.943128
10164 12:12:35.194000 00280000 ################################################################
10165 12:12:35.194134
10166 12:12:35.451749 00300000 ################################################################
10167 12:12:35.451884
10168 12:12:35.701854 00380000 ################################################################
10169 12:12:35.701986
10170 12:12:35.954974 00400000 ################################################################
10171 12:12:35.955112
10172 12:12:36.191564 00480000 ################################################################
10173 12:12:36.191763
10174 12:12:36.422453 00500000 ################################################################
10175 12:12:36.422590
10176 12:12:36.683602 00580000 ################################################################
10177 12:12:36.683748
10178 12:12:36.952170 00600000 ################################################################
10179 12:12:36.952337
10180 12:12:37.222193 00680000 ################################################################
10181 12:12:37.222339
10182 12:12:37.477726 00700000 ################################################################
10183 12:12:37.477860
10184 12:12:37.749944 00780000 ################################################################
10185 12:12:37.750077
10186 12:12:38.021805 00800000 ################################################################
10187 12:12:38.021944
10188 12:12:38.291854 00880000 ################################################################
10189 12:12:38.291994
10190 12:12:38.522529 00900000 ################################################################
10191 12:12:38.522662
10192 12:12:38.748053 00980000 ################################################################
10193 12:12:38.748186
10194 12:12:39.012091 00a00000 ################################################################
10195 12:12:39.012252
10196 12:12:39.280652 00a80000 ################################################################
10197 12:12:39.280792
10198 12:12:39.532980 00b00000 ################################################################
10199 12:12:39.533124
10200 12:12:39.802471 00b80000 ################################################################
10201 12:12:39.802614
10202 12:12:40.074633 00c00000 ################################################################
10203 12:12:40.074764
10204 12:12:40.338852 00c80000 ################################################################
10205 12:12:40.338997
10206 12:12:40.587211 00d00000 ################################################################
10207 12:12:40.587352
10208 12:12:40.850220 00d80000 ################################################################
10209 12:12:40.850355
10210 12:12:41.116004 00e00000 ################################################################
10211 12:12:41.116137
10212 12:12:41.378258 00e80000 ################################################################
10213 12:12:41.378401
10214 12:12:41.635772 00f00000 ################################################################
10215 12:12:41.635913
10216 12:12:41.891707 00f80000 ################################################################
10217 12:12:41.891856
10218 12:12:42.162579 01000000 ################################################################
10219 12:12:42.162715
10220 12:12:42.409164 01080000 ################################################################
10221 12:12:42.409314
10222 12:12:42.656162 01100000 ################################################################
10223 12:12:42.656299
10224 12:12:42.921934 01180000 ################################################################
10225 12:12:42.922073
10226 12:12:43.182210 01200000 ################################################################
10227 12:12:43.182350
10228 12:12:43.443479 01280000 ################################################################
10229 12:12:43.443649
10230 12:12:43.691531 01300000 ################################################################
10231 12:12:43.691707
10232 12:12:43.928157 01380000 ################################################################
10233 12:12:43.928319
10234 12:12:44.193004 01400000 ################################################################
10235 12:12:44.193137
10236 12:12:44.448515 01480000 ################################################################
10237 12:12:44.448658
10238 12:12:44.696042 01500000 ################################################################
10239 12:12:44.696190
10240 12:12:44.949820 01580000 ################################################################
10241 12:12:44.949952
10242 12:12:45.221143 01600000 ################################################################
10243 12:12:45.221281
10244 12:12:45.487452 01680000 ################################################################
10245 12:12:45.487643
10246 12:12:45.742914 01700000 ################################################################
10247 12:12:45.743063
10248 12:12:46.015304 01780000 ################################################################
10249 12:12:46.015440
10250 12:12:46.281518 01800000 ################################################################
10251 12:12:46.281656
10252 12:12:46.553270 01880000 ################################################################
10253 12:12:46.553408
10254 12:12:46.810201 01900000 ################################################################
10255 12:12:46.810346
10256 12:12:47.071737 01980000 ################################################################
10257 12:12:47.071876
10258 12:12:47.317086 01a00000 ################################################################
10259 12:12:47.317223
10260 12:12:47.561831 01a80000 ################################################################
10261 12:12:47.561975
10262 12:12:47.815666 01b00000 ################################################################
10263 12:12:47.815844
10264 12:12:48.080942 01b80000 ################################################################
10265 12:12:48.081079
10266 12:12:48.338521 01c00000 ################################################################
10267 12:12:48.338658
10268 12:12:48.594499 01c80000 ################################################################
10269 12:12:48.594633
10270 12:12:48.840242 01d00000 ################################################################
10271 12:12:48.840383
10272 12:12:49.093118 01d80000 ################################################################
10273 12:12:49.093258
10274 12:12:49.336441 01e00000 ################################################################
10275 12:12:49.336578
10276 12:12:49.564320 01e80000 ################################################################
10277 12:12:49.564447
10278 12:12:49.803201 01f00000 ################################################################
10279 12:12:49.803333
10280 12:12:50.028533 01f80000 ########################################################## done.
10281 12:12:50.028670
10282 12:12:50.032536 The bootfile was 33500058 bytes long.
10283 12:12:50.032629
10284 12:12:50.034947 Sending tftp read request... done.
10285 12:12:50.035039
10286 12:12:50.039653 Waiting for the transfer...
10287 12:12:50.039767
10288 12:12:50.039847 00000000 # done.
10289 12:12:50.039922
10290 12:12:50.048771 Command line loaded dynamically from TFTP file: 12669528/tftp-deploy-1gcokwmw/kernel/cmdline
10291 12:12:50.048968
10292 12:12:50.061456 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10293 12:12:50.061676
10294 12:12:50.061803 Loading FIT.
10295 12:12:50.061951
10296 12:12:50.065255 Image ramdisk-1 has 21403464 bytes.
10297 12:12:50.065499
10298 12:12:50.068376 Image fdt-1 has 47278 bytes.
10299 12:12:50.068564
10300 12:12:50.072080 Image kernel-1 has 12047284 bytes.
10301 12:12:50.072383
10302 12:12:50.081573 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10303 12:12:50.081957
10304 12:12:50.098616 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10305 12:12:50.099212
10306 12:12:50.104981 Choosing best match conf-1 for compat google,spherion-rev2.
10307 12:12:50.105533
10308 12:12:50.111469 Connected to device vid:did:rid of 1ae0:0028:00
10309 12:12:50.119429
10310 12:12:50.121978 tpm_get_response: command 0x17b, return code 0x0
10311 12:12:50.122454
10312 12:12:50.125602 ec_init: CrosEC protocol v3 supported (256, 248)
10313 12:12:50.129605
10314 12:12:50.133344 tpm_cleanup: add release locality here.
10315 12:12:50.133816
10316 12:12:50.134190 Shutting down all USB controllers.
10317 12:12:50.137438
10318 12:12:50.137998 Removing current net device
10319 12:12:50.138377
10320 12:12:50.143308 Exiting depthcharge with code 4 at timestamp: 50706545
10321 12:12:50.143905
10322 12:12:50.146533 LZMA decompressing kernel-1 to 0x821a6718
10323 12:12:50.147097
10324 12:12:50.150063 LZMA decompressing kernel-1 to 0x40000000
10325 12:12:51.650239
10326 12:12:51.650798 jumping to kernel
10327 12:12:51.652589 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10328 12:12:51.653139 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10329 12:12:51.653555 Setting prompt string to ['Linux version [0-9]']
10330 12:12:51.653930 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10331 12:12:51.654305 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10332 12:12:51.731606
10333 12:12:51.735856 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10334 12:12:51.739197 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10335 12:12:51.739804 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10336 12:12:51.740212 Setting prompt string to []
10337 12:12:51.740652 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10338 12:12:51.741062 Using line separator: #'\n'#
10339 12:12:51.741404 No login prompt set.
10340 12:12:51.741753 Parsing kernel messages
10341 12:12:51.742068 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10342 12:12:51.742620 [login-action] Waiting for messages, (timeout 00:04:02)
10343 12:12:51.758109 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j93261-arm64-gcc-10-defconfig-arm64-chromebook-cwjwh) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024
10344 12:12:51.761248 [ 0.000000] random: crng init done
10345 12:12:51.768180 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10346 12:12:51.771594 [ 0.000000] efi: UEFI not found.
10347 12:12:51.777854 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10348 12:12:51.784794 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10349 12:12:51.795090 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10350 12:12:51.804320 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10351 12:12:51.811236 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10352 12:12:51.817588 [ 0.000000] printk: bootconsole [mtk8250] enabled
10353 12:12:51.824135 [ 0.000000] NUMA: No NUMA configuration found
10354 12:12:51.830852 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10355 12:12:51.833908 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10356 12:12:51.837202 [ 0.000000] Zone ranges:
10357 12:12:51.845205 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10358 12:12:51.847747 [ 0.000000] DMA32 empty
10359 12:12:51.853749 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10360 12:12:51.857818 [ 0.000000] Movable zone start for each node
10361 12:12:51.860538 [ 0.000000] Early memory node ranges
10362 12:12:51.866570 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10363 12:12:51.873999 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10364 12:12:51.880399 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10365 12:12:51.886794 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10366 12:12:51.893798 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10367 12:12:51.899921 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10368 12:12:51.956372 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10369 12:12:51.963070 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10370 12:12:51.969453 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10371 12:12:51.972774 [ 0.000000] psci: probing for conduit method from DT.
10372 12:12:51.979486 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10373 12:12:51.982635 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10374 12:12:51.989558 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10375 12:12:51.992633 [ 0.000000] psci: SMC Calling Convention v1.2
10376 12:12:52.000203 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10377 12:12:52.002522 [ 0.000000] Detected VIPT I-cache on CPU0
10378 12:12:52.009059 [ 0.000000] CPU features: detected: GIC system register CPU interface
10379 12:12:52.016026 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10380 12:12:52.022608 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10381 12:12:52.029350 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10382 12:12:52.039085 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10383 12:12:52.045588 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10384 12:12:52.049131 [ 0.000000] alternatives: applying boot alternatives
10385 12:12:52.055176 [ 0.000000] Fallback order for Node 0: 0
10386 12:12:52.062396 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10387 12:12:52.065265 [ 0.000000] Policy zone: Normal
10388 12:12:52.078313 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10389 12:12:52.088293 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10390 12:12:52.101380 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10391 12:12:52.110216 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10392 12:12:52.116858 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10393 12:12:52.120384 <6>[ 0.000000] software IO TLB: area num 8.
10394 12:12:52.177024 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10395 12:12:52.326900 <6>[ 0.000000] Memory: 7946352K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 406416K reserved, 32768K cma-reserved)
10396 12:12:52.333367 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10397 12:12:52.339791 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10398 12:12:52.343374 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10399 12:12:52.350086 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10400 12:12:52.356872 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10401 12:12:52.360139 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10402 12:12:52.369799 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10403 12:12:52.376316 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10404 12:12:52.382791 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10405 12:12:52.389524 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10406 12:12:52.393277 <6>[ 0.000000] GICv3: 608 SPIs implemented
10407 12:12:52.396002 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10408 12:12:52.402362 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10409 12:12:52.405967 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10410 12:12:52.412824 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10411 12:12:52.425394 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10412 12:12:52.439039 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10413 12:12:52.445445 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10414 12:12:52.454283 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10415 12:12:52.466286 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10416 12:12:52.472967 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10417 12:12:52.479763 <6>[ 0.009187] Console: colour dummy device 80x25
10418 12:12:52.489738 <6>[ 0.013913] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10419 12:12:52.496414 <6>[ 0.024355] pid_max: default: 32768 minimum: 301
10420 12:12:52.499634 <6>[ 0.029256] LSM: Security Framework initializing
10421 12:12:52.505998 <6>[ 0.034193] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10422 12:12:52.515837 <6>[ 0.042008] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10423 12:12:52.526724 <6>[ 0.051434] cblist_init_generic: Setting adjustable number of callback queues.
10424 12:12:52.529025 <6>[ 0.058876] cblist_init_generic: Setting shift to 3 and lim to 1.
10425 12:12:52.539647 <6>[ 0.065255] cblist_init_generic: Setting adjustable number of callback queues.
10426 12:12:52.546044 <6>[ 0.072682] cblist_init_generic: Setting shift to 3 and lim to 1.
10427 12:12:52.549651 <6>[ 0.079124] rcu: Hierarchical SRCU implementation.
10428 12:12:52.556124 <6>[ 0.084139] rcu: Max phase no-delay instances is 1000.
10429 12:12:52.562310 <6>[ 0.091165] EFI services will not be available.
10430 12:12:52.565325 <6>[ 0.096152] smp: Bringing up secondary CPUs ...
10431 12:12:52.574452 <6>[ 0.101227] Detected VIPT I-cache on CPU1
10432 12:12:52.580754 <6>[ 0.101296] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10433 12:12:52.589357 <6>[ 0.101326] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10434 12:12:52.592272 <6>[ 0.101666] Detected VIPT I-cache on CPU2
10435 12:12:52.601425 <6>[ 0.101717] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10436 12:12:52.606972 <6>[ 0.101735] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10437 12:12:52.610821 <6>[ 0.101993] Detected VIPT I-cache on CPU3
10438 12:12:52.617253 <6>[ 0.102040] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10439 12:12:52.623193 <6>[ 0.102055] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10440 12:12:52.629987 <6>[ 0.102358] CPU features: detected: Spectre-v4
10441 12:12:52.633359 <6>[ 0.102364] CPU features: detected: Spectre-BHB
10442 12:12:52.637088 <6>[ 0.102369] Detected PIPT I-cache on CPU4
10443 12:12:52.643083 <6>[ 0.102425] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10444 12:12:52.653112 <6>[ 0.102441] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10445 12:12:52.656431 <6>[ 0.102734] Detected PIPT I-cache on CPU5
10446 12:12:52.663371 <6>[ 0.102795] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10447 12:12:52.669786 <6>[ 0.102813] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10448 12:12:52.673038 <6>[ 0.103091] Detected PIPT I-cache on CPU6
10449 12:12:52.683015 <6>[ 0.103154] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10450 12:12:52.689486 <6>[ 0.103170] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10451 12:12:52.692668 <6>[ 0.103466] Detected PIPT I-cache on CPU7
10452 12:12:52.699187 <6>[ 0.103530] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10453 12:12:52.705697 <6>[ 0.103548] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10454 12:12:52.709909 <6>[ 0.103594] smp: Brought up 1 node, 8 CPUs
10455 12:12:52.716027 <6>[ 0.244952] SMP: Total of 8 processors activated.
10456 12:12:52.722508 <6>[ 0.249903] CPU features: detected: 32-bit EL0 Support
10457 12:12:52.729198 <6>[ 0.255266] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10458 12:12:52.735413 <6>[ 0.264121] CPU features: detected: Common not Private translations
10459 12:12:52.742390 <6>[ 0.270596] CPU features: detected: CRC32 instructions
10460 12:12:52.748880 <6>[ 0.275947] CPU features: detected: RCpc load-acquire (LDAPR)
10461 12:12:52.752155 <6>[ 0.281908] CPU features: detected: LSE atomic instructions
10462 12:12:52.759180 <6>[ 0.287689] CPU features: detected: Privileged Access Never
10463 12:12:52.765589 <6>[ 0.293469] CPU features: detected: RAS Extension Support
10464 12:12:52.772289 <6>[ 0.299113] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10465 12:12:52.775637 <6>[ 0.306331] CPU: All CPU(s) started at EL2
10466 12:12:52.781713 <6>[ 0.310675] alternatives: applying system-wide alternatives
10467 12:12:52.792193 <6>[ 0.321393] devtmpfs: initialized
10468 12:12:52.808055 <6>[ 0.330324] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10469 12:12:52.814265 <6>[ 0.340285] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10470 12:12:52.820485 <6>[ 0.348545] pinctrl core: initialized pinctrl subsystem
10471 12:12:52.824135 <6>[ 0.355189] DMI not present or invalid.
10472 12:12:52.830385 <6>[ 0.359543] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10473 12:12:52.840163 <6>[ 0.366416] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10474 12:12:52.847263 <6>[ 0.374003] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10475 12:12:52.857012 <6>[ 0.382233] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10476 12:12:52.860786 <6>[ 0.390477] audit: initializing netlink subsys (disabled)
10477 12:12:52.870120 <5>[ 0.396171] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10478 12:12:52.876541 <6>[ 0.396865] thermal_sys: Registered thermal governor 'step_wise'
10479 12:12:52.884049 <6>[ 0.404139] thermal_sys: Registered thermal governor 'power_allocator'
10480 12:12:52.886375 <6>[ 0.410394] cpuidle: using governor menu
10481 12:12:52.893176 <6>[ 0.421354] NET: Registered PF_QIPCRTR protocol family
10482 12:12:52.899782 <6>[ 0.426828] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10483 12:12:52.906207 <6>[ 0.433928] ASID allocator initialised with 32768 entries
10484 12:12:52.909327 <6>[ 0.440489] Serial: AMBA PL011 UART driver
10485 12:12:52.919765 <4>[ 0.449269] Trying to register duplicate clock ID: 134
10486 12:12:52.975825 <6>[ 0.508565] KASLR enabled
10487 12:12:52.990421 <6>[ 0.516352] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10488 12:12:52.997179 <6>[ 0.523366] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10489 12:12:53.003761 <6>[ 0.529856] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10490 12:12:53.009777 <6>[ 0.536859] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10491 12:12:53.016405 <6>[ 0.543345] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10492 12:12:53.023378 <6>[ 0.550347] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10493 12:12:53.029734 <6>[ 0.556834] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10494 12:12:53.035967 <6>[ 0.563837] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10495 12:12:53.039780 <6>[ 0.571352] ACPI: Interpreter disabled.
10496 12:12:53.048823 <6>[ 0.577727] iommu: Default domain type: Translated
10497 12:12:53.054654 <6>[ 0.582841] iommu: DMA domain TLB invalidation policy: strict mode
10498 12:12:53.058294 <5>[ 0.589499] SCSI subsystem initialized
10499 12:12:53.065576 <6>[ 0.593656] usbcore: registered new interface driver usbfs
10500 12:12:53.071778 <6>[ 0.599392] usbcore: registered new interface driver hub
10501 12:12:53.075258 <6>[ 0.604946] usbcore: registered new device driver usb
10502 12:12:53.081943 <6>[ 0.611046] pps_core: LinuxPPS API ver. 1 registered
10503 12:12:53.091780 <6>[ 0.616241] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10504 12:12:53.095821 <6>[ 0.625590] PTP clock support registered
10505 12:12:53.098234 <6>[ 0.629834] EDAC MC: Ver: 3.0.0
10506 12:12:53.105610 <6>[ 0.635005] FPGA manager framework
10507 12:12:53.111657 <6>[ 0.638684] Advanced Linux Sound Architecture Driver Initialized.
10508 12:12:53.115625 <6>[ 0.645465] vgaarb: loaded
10509 12:12:53.121915 <6>[ 0.648616] clocksource: Switched to clocksource arch_sys_counter
10510 12:12:53.125085 <5>[ 0.655054] VFS: Disk quotas dquot_6.6.0
10511 12:12:53.131359 <6>[ 0.659237] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10512 12:12:53.134808 <6>[ 0.666429] pnp: PnP ACPI: disabled
10513 12:12:53.144529 <6>[ 0.673165] NET: Registered PF_INET protocol family
10514 12:12:53.153690 <6>[ 0.678752] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10515 12:12:53.164979 <6>[ 0.691068] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10516 12:12:53.175405 <6>[ 0.699884] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10517 12:12:53.181577 <6>[ 0.707852] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10518 12:12:53.191227 <6>[ 0.716553] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10519 12:12:53.197727 <6>[ 0.726299] TCP: Hash tables configured (established 65536 bind 65536)
10520 12:12:53.204599 <6>[ 0.733156] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10521 12:12:53.215249 <6>[ 0.740355] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10522 12:12:53.220888 <6>[ 0.748060] NET: Registered PF_UNIX/PF_LOCAL protocol family
10523 12:12:53.226972 <6>[ 0.754236] RPC: Registered named UNIX socket transport module.
10524 12:12:53.230814 <6>[ 0.760389] RPC: Registered udp transport module.
10525 12:12:53.236798 <6>[ 0.765324] RPC: Registered tcp transport module.
10526 12:12:53.243460 <6>[ 0.770257] RPC: Registered tcp NFSv4.1 backchannel transport module.
10527 12:12:53.246993 <6>[ 0.776925] PCI: CLS 0 bytes, default 64
10528 12:12:53.250368 <6>[ 0.781292] Unpacking initramfs...
10529 12:12:53.260956 <6>[ 0.785437] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10530 12:12:53.266799 <6>[ 0.794091] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10531 12:12:53.273955 <6>[ 0.802956] kvm [1]: IPA Size Limit: 40 bits
10532 12:12:53.276716 <6>[ 0.807485] kvm [1]: GICv3: no GICV resource entry
10533 12:12:53.284407 <6>[ 0.812507] kvm [1]: disabling GICv2 emulation
10534 12:12:53.290588 <6>[ 0.817194] kvm [1]: GIC system register CPU interface enabled
10535 12:12:53.293382 <6>[ 0.823354] kvm [1]: vgic interrupt IRQ18
10536 12:12:53.299648 <6>[ 0.827707] kvm [1]: VHE mode initialized successfully
10537 12:12:53.303170 <5>[ 0.834107] Initialise system trusted keyrings
10538 12:12:53.309562 <6>[ 0.838934] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10539 12:12:53.319450 <6>[ 0.848979] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10540 12:12:53.326720 <5>[ 0.855367] NFS: Registering the id_resolver key type
10541 12:12:53.329102 <5>[ 0.860663] Key type id_resolver registered
10542 12:12:53.337001 <5>[ 0.865077] Key type id_legacy registered
10543 12:12:53.342552 <6>[ 0.869363] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10544 12:12:53.349056 <6>[ 0.876285] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10545 12:12:53.356327 <6>[ 0.884033] 9p: Installing v9fs 9p2000 file system support
10546 12:12:53.391961 <5>[ 0.921400] Key type asymmetric registered
10547 12:12:53.395332 <5>[ 0.925732] Asymmetric key parser 'x509' registered
10548 12:12:53.405120 <6>[ 0.930878] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10549 12:12:53.408915 <6>[ 0.938494] io scheduler mq-deadline registered
10550 12:12:53.411284 <6>[ 0.943255] io scheduler kyber registered
10551 12:12:53.430614 <6>[ 0.960168] EINJ: ACPI disabled.
10552 12:12:53.463594 <4>[ 0.986156] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10553 12:12:53.474275 <4>[ 0.996802] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10554 12:12:53.488598 <6>[ 1.018190] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10555 12:12:53.496631 <6>[ 1.026214] printk: console [ttyS0] disabled
10556 12:12:53.524444 <6>[ 1.050867] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10557 12:12:53.531581 <6>[ 1.060342] printk: console [ttyS0] enabled
10558 12:12:53.534884 <6>[ 1.060342] printk: console [ttyS0] enabled
10559 12:12:53.541287 <6>[ 1.069238] printk: bootconsole [mtk8250] disabled
10560 12:12:53.544608 <6>[ 1.069238] printk: bootconsole [mtk8250] disabled
10561 12:12:53.551434 <6>[ 1.080344] SuperH (H)SCI(F) driver initialized
10562 12:12:53.555241 <6>[ 1.085618] msm_serial: driver initialized
10563 12:12:53.568889 <6>[ 1.094560] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10564 12:12:53.578482 <6>[ 1.103108] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10565 12:12:53.585050 <6>[ 1.111651] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10566 12:12:53.594747 <6>[ 1.120283] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10567 12:12:53.601711 <6>[ 1.128996] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10568 12:12:53.611649 <6>[ 1.137711] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10569 12:12:53.621742 <6>[ 1.146264] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10570 12:12:53.628124 <6>[ 1.155083] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10571 12:12:53.638247 <6>[ 1.163626] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10572 12:12:53.649798 <6>[ 1.179336] loop: module loaded
10573 12:12:53.656037 <6>[ 1.185454] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10574 12:12:53.679536 <4>[ 1.208977] mtk-pmic-keys: Failed to locate of_node [id: -1]
10575 12:12:53.686718 <6>[ 1.216016] megasas: 07.719.03.00-rc1
10576 12:12:53.696169 <6>[ 1.225694] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10577 12:12:53.703853 <6>[ 1.232023] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10578 12:12:53.719559 <6>[ 1.248628] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10579 12:12:53.779546 <6>[ 1.302175] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10580 12:12:54.195885 <6>[ 1.725606] Freeing initrd memory: 20900K
10581 12:12:54.212536 <6>[ 1.741373] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10582 12:12:54.223422 <6>[ 1.752323] tun: Universal TUN/TAP device driver, 1.6
10583 12:12:54.226887 <6>[ 1.758383] thunder_xcv, ver 1.0
10584 12:12:54.229560 <6>[ 1.761890] thunder_bgx, ver 1.0
10585 12:12:54.233698 <6>[ 1.765386] nicpf, ver 1.0
10586 12:12:54.243251 <6>[ 1.769407] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10587 12:12:54.246757 <6>[ 1.776882] hns3: Copyright (c) 2017 Huawei Corporation.
10588 12:12:54.253491 <6>[ 1.782471] hclge is initializing
10589 12:12:54.256104 <6>[ 1.786047] e1000: Intel(R) PRO/1000 Network Driver
10590 12:12:54.263613 <6>[ 1.791175] e1000: Copyright (c) 1999-2006 Intel Corporation.
10591 12:12:54.266106 <6>[ 1.797188] e1000e: Intel(R) PRO/1000 Network Driver
10592 12:12:54.274079 <6>[ 1.802404] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10593 12:12:54.279935 <6>[ 1.808593] igb: Intel(R) Gigabit Ethernet Network Driver
10594 12:12:54.286914 <6>[ 1.814242] igb: Copyright (c) 2007-2014 Intel Corporation.
10595 12:12:54.292714 <6>[ 1.820079] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10596 12:12:54.299629 <6>[ 1.826597] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10597 12:12:54.302626 <6>[ 1.833057] sky2: driver version 1.30
10598 12:12:54.309408 <6>[ 1.838053] VFIO - User Level meta-driver version: 0.3
10599 12:12:54.316635 <6>[ 1.846278] usbcore: registered new interface driver usb-storage
10600 12:12:54.323630 <6>[ 1.852729] usbcore: registered new device driver onboard-usb-hub
10601 12:12:54.333013 <6>[ 1.861923] mt6397-rtc mt6359-rtc: registered as rtc0
10602 12:12:54.342356 <6>[ 1.867384] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-31T12:12:54 UTC (1706703174)
10603 12:12:54.345596 <6>[ 1.876974] i2c_dev: i2c /dev entries driver
10604 12:12:54.363208 <6>[ 1.888841] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10605 12:12:54.382749 <6>[ 1.911865] cpu cpu0: EM: created perf domain
10606 12:12:54.385656 <6>[ 1.916802] cpu cpu4: EM: created perf domain
10607 12:12:54.392909 <6>[ 1.922442] sdhci: Secure Digital Host Controller Interface driver
10608 12:12:54.399560 <6>[ 1.928877] sdhci: Copyright(c) Pierre Ossman
10609 12:12:54.406566 <6>[ 1.933825] Synopsys Designware Multimedia Card Interface Driver
10610 12:12:54.413040 <6>[ 1.940452] sdhci-pltfm: SDHCI platform and OF driver helper
10611 12:12:54.416539 <6>[ 1.940546] mmc0: CQHCI version 5.10
10612 12:12:54.422752 <6>[ 1.950566] ledtrig-cpu: registered to indicate activity on CPUs
10613 12:12:54.429620 <6>[ 1.957677] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10614 12:12:54.436155 <6>[ 1.964735] usbcore: registered new interface driver usbhid
10615 12:12:54.439186 <6>[ 1.970556] usbhid: USB HID core driver
10616 12:12:54.446081 <6>[ 1.974754] spi_master spi0: will run message pump with realtime priority
10617 12:12:54.495110 <6>[ 2.018240] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10618 12:12:54.513962 <6>[ 2.033389] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10619 12:12:54.516917 <6>[ 2.046995] mmc0: Command Queue Engine enabled
10620 12:12:54.523936 <6>[ 2.051776] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10621 12:12:54.530627 <6>[ 2.058754] cros-ec-spi spi0.0: Chrome EC device registered
10622 12:12:54.533660 <6>[ 2.059241] mmcblk0: mmc0:0001 DA4128 116 GiB
10623 12:12:54.544916 <6>[ 2.074633] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10624 12:12:54.552441 <6>[ 2.081991] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10625 12:12:54.558883 <6>[ 2.087891] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10626 12:12:54.565768 <6>[ 2.093884] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10627 12:12:54.575836 <6>[ 2.100663] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10628 12:12:54.582297 <6>[ 2.111308] NET: Registered PF_PACKET protocol family
10629 12:12:54.586163 <6>[ 2.116728] 9pnet: Installing 9P2000 support
10630 12:12:54.592928 <5>[ 2.121302] Key type dns_resolver registered
10631 12:12:54.595150 <6>[ 2.126301] registered taskstats version 1
10632 12:12:54.601841 <5>[ 2.130698] Loading compiled-in X.509 certificates
10633 12:12:54.632128 <4>[ 2.154712] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10634 12:12:54.641919 <4>[ 2.165693] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10635 12:12:54.648218 <3>[ 2.176265] debugfs: File 'uA_load' in directory '/' already present!
10636 12:12:54.654982 <3>[ 2.182974] debugfs: File 'min_uV' in directory '/' already present!
10637 12:12:54.661635 <3>[ 2.189586] debugfs: File 'max_uV' in directory '/' already present!
10638 12:12:54.668799 <3>[ 2.196195] debugfs: File 'constraint_flags' in directory '/' already present!
10639 12:12:54.679591 <3>[ 2.205947] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10640 12:12:54.694634 <6>[ 2.223912] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10641 12:12:54.701346 <6>[ 2.230848] xhci-mtk 11200000.usb: xHCI Host Controller
10642 12:12:54.707821 <6>[ 2.236353] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10643 12:12:54.718562 <6>[ 2.244232] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10644 12:12:54.724434 <6>[ 2.253670] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10645 12:12:54.731354 <6>[ 2.259793] xhci-mtk 11200000.usb: xHCI Host Controller
10646 12:12:54.737934 <6>[ 2.265283] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10647 12:12:54.744298 <6>[ 2.272940] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10648 12:12:54.751034 <6>[ 2.280897] hub 1-0:1.0: USB hub found
10649 12:12:54.754850 <6>[ 2.284922] hub 1-0:1.0: 1 port detected
10650 12:12:54.764346 <6>[ 2.289251] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10651 12:12:54.768469 <6>[ 2.298099] hub 2-0:1.0: USB hub found
10652 12:12:54.770869 <6>[ 2.302146] hub 2-0:1.0: 1 port detected
10653 12:12:54.780262 <6>[ 2.310242] mtk-msdc 11f70000.mmc: Got CD GPIO
10654 12:12:54.794009 <6>[ 2.319774] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10655 12:12:54.800126 <6>[ 2.327794] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10656 12:12:54.809898 <4>[ 2.335715] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10657 12:12:54.819981 <6>[ 2.345288] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10658 12:12:54.826786 <6>[ 2.353366] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10659 12:12:54.833466 <6>[ 2.361386] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10660 12:12:54.843215 <6>[ 2.369311] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10661 12:12:54.849411 <6>[ 2.377130] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10662 12:12:54.859535 <6>[ 2.384949] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10663 12:12:54.869516 <6>[ 2.395350] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10664 12:12:54.876810 <6>[ 2.403725] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10665 12:12:54.886546 <6>[ 2.412076] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10666 12:12:54.892755 <6>[ 2.420415] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10667 12:12:54.903208 <6>[ 2.428757] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10668 12:12:54.913806 <6>[ 2.437096] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10669 12:12:54.920582 <6>[ 2.445435] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10670 12:12:54.929300 <6>[ 2.453774] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10671 12:12:54.935226 <6>[ 2.462113] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10672 12:12:54.946016 <6>[ 2.470451] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10673 12:12:54.952060 <6>[ 2.478790] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10674 12:12:54.962356 <6>[ 2.487128] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10675 12:12:54.969390 <6>[ 2.495467] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10676 12:12:54.978682 <6>[ 2.503805] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10677 12:12:54.985208 <6>[ 2.512151] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10678 12:12:54.991869 <6>[ 2.520881] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10679 12:12:54.999145 <6>[ 2.528038] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10680 12:12:55.005345 <6>[ 2.534813] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10681 12:12:55.015512 <6>[ 2.541572] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10682 12:12:55.021699 <6>[ 2.548512] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10683 12:12:55.028478 <6>[ 2.555356] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10684 12:12:55.038383 <6>[ 2.564486] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10685 12:12:55.048207 <6>[ 2.573607] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10686 12:12:55.058069 <6>[ 2.582900] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10687 12:12:55.068527 <6>[ 2.592366] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10688 12:12:55.077947 <6>[ 2.601832] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10689 12:12:55.084444 <6>[ 2.610950] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10690 12:12:55.094295 <6>[ 2.620416] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10691 12:12:55.104393 <6>[ 2.629534] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10692 12:12:55.113932 <6>[ 2.638828] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10693 12:12:55.124104 <6>[ 2.648989] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10694 12:12:55.133812 <6>[ 2.660373] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10695 12:12:55.174150 <6>[ 2.700883] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10696 12:12:55.329986 <6>[ 2.858947] hub 1-1:1.0: USB hub found
10697 12:12:55.333373 <6>[ 2.863496] hub 1-1:1.0: 4 ports detected
10698 12:12:55.342986 <6>[ 2.872134] hub 1-1:1.0: USB hub found
10699 12:12:55.345755 <6>[ 2.876470] hub 1-1:1.0: 4 ports detected
10700 12:12:55.454736 <6>[ 2.981258] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10701 12:12:55.480671 <6>[ 3.010603] hub 2-1:1.0: USB hub found
10702 12:12:55.484008 <6>[ 3.015090] hub 2-1:1.0: 3 ports detected
10703 12:12:55.493530 <6>[ 3.023224] hub 2-1:1.0: USB hub found
10704 12:12:55.496366 <6>[ 3.027686] hub 2-1:1.0: 3 ports detected
10705 12:12:55.670495 <6>[ 3.196915] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10706 12:12:55.801990 <6>[ 3.330844] hub 1-1.1:1.0: USB hub found
10707 12:12:55.804320 <6>[ 3.335175] hub 1-1.1:1.0: 4 ports detected
10708 12:12:55.919275 <6>[ 3.445018] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10709 12:12:56.050749 <6>[ 3.580511] hub 1-1.4:1.0: USB hub found
10710 12:12:56.053927 <6>[ 3.585195] hub 1-1.4:1.0: 2 ports detected
10711 12:12:56.063903 <6>[ 3.593380] hub 1-1.4:1.0: USB hub found
10712 12:12:56.067227 <6>[ 3.597950] hub 1-1.4:1.0: 2 ports detected
10713 12:12:56.130847 <6>[ 3.656804] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10714 12:12:56.362693 <6>[ 3.888933] usb 1-1.4.1: new high-speed USB device number 6 using xhci-mtk
10715 12:12:56.554591 <6>[ 4.080934] usb 1-1.4.2: new high-speed USB device number 7 using xhci-mtk
10716 12:13:07.431639 <6>[ 14.965884] ALSA device list:
10717 12:13:07.438845 <6>[ 14.969184] No soundcards found.
10718 12:13:07.445964 <6>[ 14.977126] Freeing unused kernel memory: 8448K
10719 12:13:07.449934 <6>[ 14.982156] Run /init as init process
10720 12:13:07.485097 Starting syslogd: OK
10721 12:13:07.487988 Starting klogd: OK
10722 12:13:07.497317 Running sysctl: OK
10723 12:13:07.504496 Populating /dev using udev: <30>[ 15.036658] udevd[184]: starting version 3.2.9
10724 12:13:07.514179 <27>[ 15.044401] udevd[184]: specified user 'tss' unknown
10725 12:13:07.520202 <27>[ 15.049794] udevd[184]: specified group 'tss' unknown
10726 12:13:07.523177 <30>[ 15.056256] udevd[185]: starting eudev-3.2.9
10727 12:13:07.544887 <27>[ 15.075941] udevd[185]: specified user 'tss' unknown
10728 12:13:07.552235 <27>[ 15.081419] udevd[185]: specified group 'tss' unknown
10729 12:13:07.686149 <6>[ 15.214087] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10730 12:13:07.703515 <6>[ 15.234585] remoteproc remoteproc0: scp is available
10731 12:13:07.710644 <6>[ 15.240368] remoteproc remoteproc0: powering up scp
10732 12:13:07.717117 <6>[ 15.245703] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10733 12:13:07.723307 <6>[ 15.254167] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10734 12:13:07.751291 <6>[ 15.279075] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10735 12:13:07.761624 <6>[ 15.287101] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10736 12:13:07.767883 <6>[ 15.296023] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10737 12:13:07.787847 <6>[ 15.318146] usbcore: registered new device driver r8152-cfgselector
10738 12:13:07.797245 <3>[ 15.319415] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10739 12:13:07.804054 <3>[ 15.333041] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10740 12:13:07.813869 <6>[ 15.335130] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10741 12:13:07.820594 <3>[ 15.341153] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10742 12:13:07.826423 <6>[ 15.342158] mc: Linux media interface: v0.10
10743 12:13:07.832951 <3>[ 15.342507] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10744 12:13:07.843540 <3>[ 15.342534] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10745 12:13:07.850708 <3>[ 15.342543] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 12:13:07.856517 <3>[ 15.342555] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10747 12:13:07.866230 <3>[ 15.342561] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10748 12:13:07.872661 <3>[ 15.342646] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10749 12:13:07.883302 <3>[ 15.342705] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10750 12:13:07.889651 <3>[ 15.342709] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 12:13:07.900367 <3>[ 15.342713] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10752 12:13:07.906910 <4>[ 15.342965] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10753 12:13:07.912716 <3>[ 15.343043] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10754 12:13:07.922434 <3>[ 15.343057] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 12:13:07.929714 <3>[ 15.343065] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 12:13:07.939308 <3>[ 15.343075] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10757 12:13:07.946295 <3>[ 15.343082] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10758 12:13:07.956013 <3>[ 15.343160] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 12:13:07.962493 <4>[ 15.343173] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10760 12:13:07.969380 <4>[ 15.388646] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10761 12:13:07.975220 <4>[ 15.388646] Fallback method does not support PEC.
10762 12:13:07.982240 <6>[ 15.389179] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10763 12:13:07.992603 <6>[ 15.394295] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10764 12:13:07.999221 <3>[ 15.422411] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10765 12:13:08.005403 <6>[ 15.426104] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10766 12:13:08.011701 <6>[ 15.426113] pci_bus 0000:00: root bus resource [bus 00-ff]
10767 12:13:08.018839 <6>[ 15.426119] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10768 12:13:08.028817 <6>[ 15.426124] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10769 12:13:08.034918 <6>[ 15.426162] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10770 12:13:08.041608 <6>[ 15.426185] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10771 12:13:08.048582 <6>[ 15.426252] remoteproc remoteproc0: remote processor scp is now up
10772 12:13:08.054966 <6>[ 15.426284] pci 0000:00:00.0: supports D1 D2
10773 12:13:08.061814 <6>[ 15.434602] r8152-cfgselector 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10774 12:13:08.068191 <6>[ 15.441814] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10775 12:13:08.078523 <6>[ 15.443602] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10776 12:13:08.088171 <6>[ 15.527250] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10777 12:13:08.094141 <6>[ 15.536120] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10778 12:13:08.104260 <6>[ 15.536762] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10779 12:13:08.112150 <6>[ 15.537258] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10780 12:13:08.121141 <6>[ 15.537327] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10781 12:13:08.128074 <6>[ 15.540113] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10782 12:13:08.134884 <6>[ 15.556043] videodev: Linux video capture interface: v2.00
10783 12:13:08.141217 <6>[ 15.565913] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10784 12:13:08.144231 <6>[ 15.579499] Bluetooth: Core ver 2.22
10785 12:13:08.154346 <4>[ 15.580468] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10786 12:13:08.164245 <4>[ 15.580475] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10787 12:13:08.171093 <6>[ 15.585887] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10788 12:13:08.177719 <6>[ 15.590373] NET: Registered PF_BLUETOOTH protocol family
10789 12:13:08.185003 <6>[ 15.598833] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10790 12:13:08.191355 <6>[ 15.605695] Bluetooth: HCI device and connection manager initialized
10791 12:13:08.193592 <6>[ 15.614075] pci 0000:01:00.0: supports D1 D2
10792 12:13:08.200474 <6>[ 15.623289] Bluetooth: HCI socket layer initialized
10793 12:13:08.207448 <6>[ 15.624284] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10794 12:13:08.219877 <6>[ 15.625759] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10795 12:13:08.227156 <6>[ 15.625859] usbcore: registered new interface driver uvcvideo
10796 12:13:08.233661 <6>[ 15.629549] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10797 12:13:08.236668 <6>[ 15.639605] Bluetooth: L2CAP socket layer initialized
10798 12:13:08.242990 <6>[ 15.640792] r8152 1-1.1.1:1.0 eth0: v1.12.13
10799 12:13:08.247256 <6>[ 15.640846] usbcore: registered new interface driver r8152
10800 12:13:08.252977 <6>[ 15.657802] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10801 12:13:08.263555 <6>[ 15.660672] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10802 12:13:08.269848 <6>[ 15.660715] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10803 12:13:08.276400 <6>[ 15.660720] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10804 12:13:08.286397 <6>[ 15.660731] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10805 12:13:08.293179 <6>[ 15.660743] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10806 12:13:08.302805 <6>[ 15.660756] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10807 12:13:08.306086 <6>[ 15.660768] pci 0000:00:00.0: PCI bridge to [bus 01]
10808 12:13:08.315558 <6>[ 15.660772] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10809 12:13:08.322249 <3>[ 15.661242] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10810 12:13:08.329275 <6>[ 15.665270] Bluetooth: SCO socket layer initialized
10811 12:13:08.335527 <6>[ 15.665441] usbcore: registered new interface driver cdc_ether
10812 12:13:08.341999 <6>[ 15.671185] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10813 12:13:08.348695 <6>[ 15.671267] usbcore: registered new interface driver r8153_ecm
10814 12:13:08.351900 <6>[ 15.720672] usbcore: registered new interface driver btusb
10815 12:13:08.361922 <4>[ 15.721773] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10816 12:13:08.368873 <3>[ 15.721781] Bluetooth: hci0: Failed to load firmware file (-2)
10817 12:13:08.375055 <3>[ 15.721783] Bluetooth: hci0: Failed to set up firmware (-2)
10818 12:13:08.385211 <4>[ 15.721786] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10819 12:13:08.391956 <6>[ 15.727257] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10820 12:13:08.398541 <6>[ 15.928392] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10821 12:13:08.415702 <5>[ 15.943456] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10822 12:13:08.449150 <5>[ 15.976827] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10823 12:13:08.455985 <5>[ 15.984290] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10824 12:13:08.465463 <4>[ 15.992800] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10825 12:13:08.472104 <6>[ 16.001688] cfg80211: failed to load regulatory.db
10826 12:13:08.521322 <6>[ 16.048477] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10827 12:13:08.527751 <6>[ 16.056001] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10828 12:13:08.551488 <6>[ 16.082716] mt7921e 0000:01:00.0: ASIC revision: 79610010
10829 12:13:08.653911 <6>[ 16.181412] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10830 12:13:08.657170 <6>[ 16.181412]
10831 12:13:08.657593 done
10832 12:13:08.664799 Saving random seed: OK
10833 12:13:08.679032 Starting network: OK
10834 12:13:08.718775 Starting dropbear sshd: <6>[ 16.249950] NET: Registered PF_INET6 protocol family
10835 12:13:08.725629 <6>[ 16.256360] Segment Routing with IPv6
10836 12:13:08.728225 <6>[ 16.260307] In-situ OAM (IOAM) with IPv6
10837 12:13:08.732127 OK
10838 12:13:08.741284 /bin/sh: can't access tty; job control turned off
10839 12:13:08.742639 Matched prompt #10: / #
10841 12:13:08.743806 Setting prompt string to ['/ #']
10842 12:13:08.744385 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10844 12:13:08.745471 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10845 12:13:08.745965 start: 2.2.6 expect-shell-connection (timeout 00:03:45) [common]
10846 12:13:08.746374 Setting prompt string to ['/ #']
10847 12:13:08.746717 Forcing a shell prompt, looking for ['/ #']
10849 12:13:08.797708 / #
10850 12:13:08.798362 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10851 12:13:08.798940 Waiting using forced prompt support (timeout 00:02:30)
10852 12:13:08.804713
10853 12:13:08.805686 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10854 12:13:08.806231 start: 2.2.7 export-device-env (timeout 00:03:45) [common]
10855 12:13:08.806742 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10856 12:13:08.807208 end: 2.2 depthcharge-retry (duration 00:01:15) [common]
10857 12:13:08.807664 end: 2 depthcharge-action (duration 00:01:15) [common]
10858 12:13:08.808185 start: 3 lava-test-retry (timeout 00:01:00) [common]
10859 12:13:08.808666 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10860 12:13:08.809073 Using namespace: common
10862 12:13:08.910254 / # #
10863 12:13:08.910956 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10864 12:13:08.920130 #<6>[ 16.448045] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10865 12:13:08.920711
10866 12:13:08.921399 Using /lava-12669528
10868 12:13:09.022637 / #export SHELL=/bin/sh
10869 12:13:09.029172 export SHELL=/bin/sh
10871 12:13:09.131123 / # . /lava-12669528/environment
10872 12:13:09.138523 . /lava-12669528/environment
10874 12:13:09.240408 / # /lava-12669528/bin/lava-test-runner /lava-12669528/0
10875 12:13:09.241037 Test shell timeout: 10s (minimum of the action and connection timeout)
10876 12:13:09.247091 /lava-12669528/bin/lava-test-runner /lava-12669528/0
10877 12:13:09.265741 + export 'TESTRUN_ID=0_dmesg'
10878 12:13:09.272486 + c<8>[ 16.801764] <LAVA_SIGNAL_STARTRUN 0_dmesg 12669528_1.5.2.3.1>
10879 12:13:09.273507 Received signal: <STARTRUN> 0_dmesg 12669528_1.5.2.3.1
10880 12:13:09.273935 Starting test lava.0_dmesg (12669528_1.5.2.3.1)
10881 12:13:09.274383 Skipping test definition patterns.
10882 12:13:09.274922 d /lava-12669528/0/tests/0_dmesg
10883 12:13:09.275299 + cat uuid
10884 12:13:09.279166 + UUID=12669528_1.5.2.3.1
10885 12:13:09.279771 + set +x
10886 12:13:09.285936 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10887 12:13:09.295116 <8>[ 16.822670] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10888 12:13:09.295938 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10890 12:13:09.314936 <8>[ 16.842533] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10891 12:13:09.315838 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10893 12:13:09.333123 <8>[ 16.861131] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10894 12:13:09.333975 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10896 12:13:09.336272 + set +x
10897 12:13:09.339845 <8>[ 16.870505] <LAVA_SIGNAL_ENDRUN 0_dmesg 12669528_1.5.2.3.1>
10898 12:13:09.340688 Received signal: <ENDRUN> 0_dmesg 12669528_1.5.2.3.1
10899 12:13:09.341142 Ending use of test pattern.
10900 12:13:09.341492 Ending test lava.0_dmesg (12669528_1.5.2.3.1), duration 0.07
10902 12:13:09.343296 <LAVA_TEST_RUNNER EXIT>
10903 12:13:09.344018 ok: lava_test_shell seems to have completed
10904 12:13:09.344587 alert: pass
crit: pass
emerg: pass
10905 12:13:09.345039 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10906 12:13:09.345489 end: 3 lava-test-retry (duration 00:00:01) [common]
10907 12:13:09.345942 start: 4 lava-test-retry (timeout 00:01:00) [common]
10908 12:13:09.346400 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10909 12:13:09.346750 Using namespace: common
10911 12:13:09.447989 / # #
10912 12:13:09.448640 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10913 12:13:09.449326 Using /lava-12669528
10915 12:13:09.550653 export SHELL=/bin/sh
10916 12:13:09.551451 #
10918 12:13:09.653045 / # export SHELL=/bin/sh. /lava-12669528/environment
10919 12:13:09.653855
10921 12:13:09.755585 / # . /lava-12669528/environment/lava-12669528/bin/lava-test-runner /lava-12669528/1
10922 12:13:09.756244 Test shell timeout: 10s (minimum of the action and connection timeout)
10923 12:13:09.756857
10924 12:13:09.766764 / # /lava-12669528/bin/lava-test-runner /lava-12669528/1<6>[ 17.297805] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10925 12:13:09.767329
10926 12:13:09.787440 + export 'TESTRUN_ID=1_bootrr'
10927 12:13:09.794173 <8>[ 17.323195] <LAVA_SIGNAL_STARTRUN 1_bootrr 12669528_1.5.2.3.5>
10928 12:13:09.795011 Received signal: <STARTRUN> 1_bootrr 12669528_1.5.2.3.5
10929 12:13:09.795423 Starting test lava.1_bootrr (12669528_1.5.2.3.5)
10930 12:13:09.795908 Skipping test definition patterns.
10931 12:13:09.796993 + cd /lava-12669528/1/tests/1_bootrr
10932 12:13:09.797462 + cat uuid
10933 12:13:09.800560 + UUID=12669528_1.5.2.3.5
10934 12:13:09.801119 + set +x
10935 12:13:09.810356 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-12669528/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10936 12:13:09.820398 + cd /opt/bootr<8>[ 17.347941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10937 12:13:09.820883 r/libexec/bootrr
10938 12:13:09.821519 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10940 12:13:09.823370 + sh helpers/bootrr-auto
10941 12:13:09.826865 /lava-12669528/1/../bin/lava-test-case
10942 12:13:09.829690 /lava-12669528/1/../bin/lava-test-case
10943 12:13:09.837162 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10945 12:13:09.840151 <8>[ 17.366028] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10946 12:13:09.844546 /usr/bin/tpm2_getcap
10947 12:13:09.881536 /lava-12669528/1/../bin/lava-test-case
10948 12:13:09.887647 <8>[ 17.417759] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10949 12:13:09.888527 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10951 12:13:09.908565 /lava-12669528/1/../bin/lava-test-case
10952 12:13:09.914862 <8>[ 17.443017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10953 12:13:09.915716 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10955 12:13:09.926899 /lava-12669528/1/../bin/lava-test-case
10956 12:13:09.933230 <8>[ 17.461508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10957 12:13:09.934070 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10959 12:13:09.945085 /lava-12669528/1/../bin/lava-test-case
10960 12:13:09.952270 <8>[ 17.480102] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10961 12:13:09.953106 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10963 12:13:09.964602 /lava-12669528/1/../bin/lava-test-case
10964 12:13:09.971303 <8>[ 17.499231] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10965 12:13:09.972173 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10967 12:13:09.983775 /lava-12669528/1/../bin/lava-test-case
10968 12:13:09.990376 <8>[ 17.518865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10969 12:13:09.991249 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10971 12:13:10.002441 /lava-12669528/1/../bin/lava-test-case
10972 12:13:10.009134 <8>[ 17.537051] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10973 12:13:10.010133 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10975 12:13:10.021461 /lava-12669528/1/../bin/lava-test-case
10976 12:13:10.027797 <8>[ 17.555503] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10977 12:13:10.028638 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10979 12:13:10.037051 /lava-12669528/1/../bin/lava-test-case
10980 12:13:10.043577 <8>[ 17.571440] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10981 12:13:10.044465 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10983 12:13:10.057202 /lava-12669528/1/../bin/lava-test-case
10984 12:13:10.067637 <8>[ 17.595513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10985 12:13:10.068565 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10987 12:13:10.080348 /lava-12669528/1/../bin/lava-test-case
10988 12:13:10.087403 <8>[ 17.614980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10989 12:13:10.088299 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10991 12:13:10.099162 /lava-12669528/1/../bin/lava-test-case
10992 12:13:10.108727 <8>[ 17.636120] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10993 12:13:10.109583 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10995 12:13:10.120322 /lava-12669528/1/../bin/lava-test-case
10996 12:13:10.127048 <8>[ 17.655463] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10997 12:13:10.127887 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10999 12:13:10.136792 /lava-12669528/1/../bin/lava-test-case
11000 12:13:10.143249 <8>[ 17.671237] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11001 12:13:10.144423 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11003 12:13:10.162418 /lava-12669528/1/../bin/lava-tes<8>[ 17.689180] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11004 12:13:10.162979 t-case
11005 12:13:10.163623 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11007 12:13:10.178437 /lava-12669528/1/../bin/lava-tes<8>[ 17.705322] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11008 12:13:10.179001 t-case
11009 12:13:10.179660 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11011 12:13:10.197270 /lava-12669528/1/../bin/lava-tes<8>[ 17.724483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11012 12:13:10.197850 t-case
11013 12:13:10.198502 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11015 12:13:10.204898 /lava-12669528/1/../bin/lava-test-case
11016 12:13:10.211318 <8>[ 17.741038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11017 12:13:10.212245 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11019 12:13:10.224229 /lava-12669528/1/../bin/lava-test-case
11020 12:13:10.234437 <8>[ 17.762002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11021 12:13:10.235339 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11023 12:13:10.242343 /lava-12669528/1/../bin/lava-test-case
11024 12:13:10.248540 <8>[ 17.777124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11025 12:13:10.249285 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11027 12:13:10.261540 /lava-12669528/1/../bin/lava-test-case
11028 12:13:10.271953 <8>[ 17.798844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11029 12:13:10.272775 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11031 12:13:10.279370 /lava-12669528/1/../bin/lava-test-case
11032 12:13:10.286259 <8>[ 17.814634] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11033 12:13:10.287099 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11035 12:13:10.298230 /lava-12669528/1/../bin/lava-test-case
11036 12:13:10.304066 <8>[ 17.833234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11037 12:13:10.304991 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11039 12:13:10.315457 /lava-12669528/1/../bin/lava-test-case
11040 12:13:10.322071 <8>[ 17.851121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11041 12:13:10.322836 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11043 12:13:10.332723 /lava-12669528/1/../bin/lava-test-case
11044 12:13:10.338373 <8>[ 17.866260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11045 12:13:10.339140 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11047 12:13:10.349270 /lava-12669528/1/../bin/lava-test-case
11048 12:13:10.356029 <8>[ 17.884830] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11049 12:13:10.356905 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11051 12:13:10.365674 /lava-12669528/1/../bin/lava-test-case
11052 12:13:10.372283 <8>[ 17.901181] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11053 12:13:10.373052 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11055 12:13:10.384023 /lava-12669528/1/../bin/lava-test-case
11056 12:13:10.390508 <8>[ 17.919206] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11057 12:13:10.391387 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11059 12:13:10.402376 /lava-12669528/1/../bin/lava-test-case
11060 12:13:10.412048 <8>[ 17.939779] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11061 12:13:10.412922 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11063 12:13:10.422991 /lava-12669528/1/../bin/lava-test-case
11064 12:13:10.429644 <8>[ 17.959103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11065 12:13:10.430689 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11067 12:13:10.441890 /lava-12669528/1/../bin/lava-test-case
11068 12:13:10.448714 <8>[ 17.977246] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11069 12:13:10.449583 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11071 12:13:10.458652 /lava-12669528/1/../bin/lava-test-case
11072 12:13:10.465496 <8>[ 17.993555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11073 12:13:10.466380 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11075 12:13:10.476667 /lava-12669528/1/../bin/lava-test-case
11076 12:13:10.482919 <8>[ 18.011931] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11077 12:13:10.483888 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11079 12:13:10.494635 /lava-12669528/1/../bin/lava-test-case
11080 12:13:10.500973 <8>[ 18.029638] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11081 12:13:10.501797 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11083 12:13:10.510473 /lava-12669528/1/../bin/lava-test-case
11084 12:13:10.517733 <8>[ 18.046183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11085 12:13:10.518615 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11087 12:13:10.530494 /lava-12669528/1/../bin/lava-test-case
11088 12:13:10.537073 <8>[ 18.066338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11089 12:13:10.537919 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11091 12:13:10.546560 /lava-12669528/1/../bin/lava-test-case
11092 12:13:10.554135 <8>[ 18.081360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11093 12:13:10.554979 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11095 12:13:10.564050 /lava-12669528/1/../bin/lava-test-case
11096 12:13:10.570633 <8>[ 18.099653] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11097 12:13:10.571511 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11099 12:13:10.580109 /lava-12669528/1/../bin/lava-test-case
11100 12:13:10.586333 <8>[ 18.115018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11101 12:13:10.587187 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11103 12:13:10.597982 /lava-12669528/1/../bin/lava-test-case
11104 12:13:10.604619 <8>[ 18.132356] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11105 12:13:10.605490 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11107 12:13:10.614660 /lava-12669528/1/../bin/lava-test-case
11108 12:13:10.624200 <8>[ 18.150402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11109 12:13:10.625060 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11111 12:13:10.634051 /lava-12669528/1/../bin/lava-test-case
11112 12:13:10.641964 <8>[ 18.168880] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11113 12:13:10.643005 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11115 12:13:10.649327 /lava-12669528/1/../bin/lava-test-case
11116 12:13:10.656094 <8>[ 18.185540] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11117 12:13:10.656912 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11119 12:13:10.668874 /lava-12669528/1/../bin/lava-test-case
11120 12:13:10.675395 <8>[ 18.203771] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11121 12:13:10.676295 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11123 12:13:10.684376 /lava-12669528/1/../bin/lava-test-case
11124 12:13:10.690516 <8>[ 18.219546] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11125 12:13:10.691361 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11127 12:13:10.702234 /lava-12669528/1/../bin/lava-test-case
11128 12:13:10.708617 <8>[ 18.237890] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11129 12:13:10.709456 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11131 12:13:10.717516 /lava-12669528/1/../bin/lava-test-case
11132 12:13:10.724446 <8>[ 18.252899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11133 12:13:10.725280 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11135 12:13:10.735781 /lava-12669528/1/../bin/lava-test-case
11136 12:13:10.742038 <8>[ 18.270824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11137 12:13:10.742912 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11139 12:13:10.752347 /lava-12669528/1/../bin/lava-test-case
11140 12:13:10.759425 <8>[ 18.288525] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11141 12:13:10.760285 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11143 12:13:10.769259 /lava-12669528/1/../bin/lava-test-case
11144 12:13:10.776301 <8>[ 18.305028] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11145 12:13:10.777076 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11147 12:13:10.788571 /lava-12669528/1/../bin/lava-test-case
11148 12:13:10.794705 <8>[ 18.323534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11149 12:13:10.795542 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11151 12:13:10.803261 /lava-12669528/1/../bin/lava-test-case
11152 12:13:10.810016 <8>[ 18.339038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11153 12:13:10.810693 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11155 12:13:10.829391 /lava-12669528/1/../bin/lava-tes<8>[ 18.356295] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11156 12:13:10.830003 t-case
11157 12:13:10.830618 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11159 12:13:10.839495 /lava-12669528/1/../bin/lava-test-case
11160 12:13:10.850201 <8>[ 18.377418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11161 12:13:10.850880 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11163 12:13:10.860980 /lava-12669528/1/../bin/lava-test-case
11164 12:13:10.868173 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11166 12:13:10.870645 <8>[ 18.397903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11167 12:13:10.881036 /lava-12669528/1/../bin/lava-test-case
11168 12:13:10.887001 <8>[ 18.416078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11169 12:13:10.887773 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11171 12:13:10.897628 /lava-12669528/1/../bin/lava-test-case
11172 12:13:10.908639 <8>[ 18.436082] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11173 12:13:10.909458 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11175 12:13:10.916974 /lava-12669528/1/../bin/lava-test-case
11176 12:13:10.922804 <8>[ 18.451184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11177 12:13:10.923537 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11179 12:13:10.933815 /lava-12669528/1/../bin/lava-test-case
11180 12:13:10.943934 <8>[ 18.471560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11181 12:13:10.944873 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11183 12:13:10.955408 /lava-12669528/1/../bin/lava-test-case
11184 12:13:10.966331 <8>[ 18.494117] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11185 12:13:10.967171 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11187 12:13:10.974117 /lava-12669528/1/../bin/lava-test-case
11188 12:13:10.983808 <8>[ 18.512239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11189 12:13:10.984710 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11191 12:13:10.995489 /lava-12669528/1/../bin/lava-test-case
11192 12:13:11.002491 <8>[ 18.531378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11193 12:13:11.003338 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11195 12:13:11.011364 /lava-12669528/1/../bin/lava-test-case
11196 12:13:11.018133 <8>[ 18.546170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11197 12:13:11.018979 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11199 12:13:11.029373 /lava-12669528/1/../bin/lava-test-case
11200 12:13:11.035894 <8>[ 18.564516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11201 12:13:11.036724 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11203 12:13:11.044535 /lava-12669528/1/../bin/lava-test-case
11204 12:13:11.051099 <8>[ 18.579820] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11205 12:13:11.051945 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11207 12:13:11.062717 /lava-12669528/1/../bin/lava-test-case
11208 12:13:11.068941 <8>[ 18.597087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11209 12:13:11.069788 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11211 12:13:11.080558 /lava-12669528/1/../bin/lava-test-case
11212 12:13:11.086689 <8>[ 18.615780] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11213 12:13:11.087524 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11215 12:13:11.098062 /lava-12669528/1/../bin/lava-test-case
11216 12:13:11.104590 <8>[ 18.633594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11217 12:13:11.105442 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11219 12:13:11.117479 /lava-12669528/1/../bin/lava-test-case
11220 12:13:11.127424 <8>[ 18.655688] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11221 12:13:11.128212 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11223 12:13:11.138176 /lava-12669528/1/../bin/lava-test-case
11224 12:13:11.144290 <8>[ 18.673728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11225 12:13:11.145176 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11227 12:13:11.155828 /lava-12669528/1/../bin/lava-test-case
11228 12:13:11.162181 <8>[ 18.691170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11229 12:13:11.163026 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11231 12:13:11.174818 /lava-12669528/1/../bin/lava-test-case
11232 12:13:11.181470 <8>[ 18.709670] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11233 12:13:11.182314 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11235 12:13:11.191554 /lava-12669528/1/../bin/lava-test-case
11236 12:13:11.198290 <8>[ 18.726912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11237 12:13:11.199136 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11239 12:13:11.208564 /lava-12669528/1/../bin/lava-test-case
11240 12:13:11.215353 <8>[ 18.744431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11241 12:13:11.216263 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11243 12:13:11.227056 /lava-12669528/1/../bin/lava-test-case
11244 12:13:11.233846 <8>[ 18.762805] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11245 12:13:11.234688 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11247 12:13:11.244599 /lava-12669528/1/../bin/lava-test-case
11248 12:13:11.254659 <8>[ 18.782922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11249 12:13:11.255504 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11251 12:13:11.266062 /lava-12669528/1/../bin/lava-test-case
11252 12:13:11.272305 <8>[ 18.801175] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11253 12:13:11.273109 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11255 12:13:11.283042 /lava-12669528/1/../bin/lava-test-case
11256 12:13:11.289506 <8>[ 18.819570] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11257 12:13:11.290330 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11259 12:13:11.310059 /lava-12669528/1/../bin/lava-tes<8>[ 18.837495] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11260 12:13:11.310624 t-case
11261 12:13:11.311343 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11263 12:13:11.318974 /lava-12669528/1/../bin/lava-test-case
11264 12:13:11.326771 <8>[ 18.855313] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11265 12:13:11.327634 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11267 12:13:11.336216 /lava-12669528/1/../bin/lava-test-case
11268 12:13:11.342950 <8>[ 18.871707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11269 12:13:11.343922 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11271 12:13:11.354235 /lava-12669528/1/../bin/lava-test-case
11272 12:13:11.360557 <8>[ 18.889884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11273 12:13:11.361499 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11275 12:13:11.370522 /lava-12669528/1/../bin/lava-test-case
11276 12:13:11.377035 <8>[ 18.905946] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11277 12:13:11.377878 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11279 12:13:11.388657 /lava-12669528/1/../bin/lava-test-case
11280 12:13:11.394947 <8>[ 18.923704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11281 12:13:11.395823 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11283 12:13:11.403373 /lava-12669528/1/../bin/lava-test-case
11284 12:13:11.410387 <8>[ 18.939164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11285 12:13:11.411228 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11287 12:13:11.422012 /lava-12669528/1/../bin/lava-test-case
11288 12:13:11.428503 <8>[ 18.958219] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11289 12:13:11.429317 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11291 12:13:11.438758 /lava-12669528/1/../bin/lava-test-case
11292 12:13:11.445282 <8>[ 18.973409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11293 12:13:11.446127 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11295 12:13:11.456492 /lava-12669528/1/../bin/lava-test-case
11296 12:13:11.463270 <8>[ 18.991621] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11297 12:13:11.464173 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11299 12:13:11.472412 /lava-12669528/1/../bin/lava-test-case
11300 12:13:11.479659 <8>[ 19.007748] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11301 12:13:11.480550 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11303 12:13:11.491432 /lava-12669528/1/../bin/lava-test-case
11304 12:13:11.498452 <8>[ 19.027183] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11305 12:13:11.499330 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11307 12:13:11.508080 /lava-12669528/1/../bin/lava-test-case
11308 12:13:11.513862 <8>[ 19.042914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11309 12:13:11.514709 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11311 12:13:11.526415 /lava-12669528/1/../bin/lava-test-case
11312 12:13:11.532899 <8>[ 19.062249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11313 12:13:11.533826 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11315 12:13:11.544584 /lava-12669528/1/../bin/lava-test-case
11316 12:13:11.551208 <8>[ 19.080054] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11317 12:13:11.551992 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11319 12:13:11.560700 /lava-12669528/1/../bin/lava-test-case
11320 12:13:11.567307 <8>[ 19.095490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11321 12:13:11.568203 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11323 12:13:11.578128 /lava-12669528/1/../bin/lava-test-case
11324 12:13:11.584557 <8>[ 19.113653] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11325 12:13:11.585548 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11327 12:13:11.593916 /lava-12669528/1/../bin/lava-test-case
11328 12:13:11.603555 <8>[ 19.131914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11329 12:13:11.604499 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11331 12:13:11.613766 /lava-12669528/1/../bin/lava-test-case
11332 12:13:11.620284 <8>[ 19.149853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11333 12:13:11.621205 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11335 12:13:11.630859 /lava-12669528/1/../bin/lava-test-case
11336 12:13:11.636445 <8>[ 19.164434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11337 12:13:11.637307 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11339 12:13:12.649339 /lava-12669528/1/../bin/lava-test-case
11340 12:13:12.655218 <8>[ 20.183857] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11341 12:13:12.655508 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11343 12:13:12.665506 /lava-12669528/1/../bin/lava-test-case
11344 12:13:12.672318 <8>[ 20.201447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11345 12:13:12.673123 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11347 12:13:13.687547 /lava-12669528/1/../bin/lava-test-case
11348 12:13:13.693787 <8>[ 21.222459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11349 12:13:13.694617 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11351 12:13:13.701864 /lava-12669528/1/../bin/lava-test-case
11352 12:13:13.712831 <8>[ 21.240636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11353 12:13:13.713675 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11355 12:13:14.726067 /lava-12669528/1/../bin/lava-test-case
11356 12:13:14.732235 <8>[ 22.261055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11357 12:13:14.732970 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11359 12:13:14.742866 /lava-12669528/1/../bin/lava-test-case
11360 12:13:14.752985 <8>[ 22.281676] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11361 12:13:14.753826 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11363 12:13:15.771722 /lava-12669528/1/../bin/lava-test-case
11364 12:13:15.777299 <8>[ 23.307386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11365 12:13:15.778143 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11367 12:13:15.787590 /lava-12669528/1/../bin/lava-test-case
11368 12:13:15.794540 <8>[ 23.322270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11369 12:13:15.795407 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11371 12:13:16.808055 /lava-12669528/1/../bin/lava-test-case
11372 12:13:16.813593 <8>[ 24.342576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11373 12:13:16.814342 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11375 12:13:16.830513 /lava-12669528/1/../bin/lava-tes<8>[ 24.358850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11376 12:13:16.831019 t-case
11377 12:13:16.831612 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11379 12:13:17.843264 /lava-12669528/1/../bin/lava-test-case
11380 12:13:17.850138 <8>[ 25.378436] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11381 12:13:17.850812 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11383 12:13:17.866486 /lava-12669528/1/../bin/lava-tes<8>[ 25.395130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11384 12:13:17.867055 t-case
11385 12:13:17.867876 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11387 12:13:18.879343 /lava-12669528/1/../bin/lava-test-case
11388 12:13:18.885030 <8>[ 26.414323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11389 12:13:18.885867 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11391 12:13:18.902997 /lava-12669528/1/../bin/lava-tes<8>[ 26.430864] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11392 12:13:18.903573 t-case
11393 12:13:18.904269 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11395 12:13:18.910828 /lava-12669528/1/../bin/lava-test-case
11396 12:13:18.917526 <8>[ 26.445706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11397 12:13:18.918401 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11399 12:13:19.932240 /lava-12669528/1/../bin/lava-test-case
11400 12:13:19.939118 <8>[ 27.468528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11401 12:13:19.940025 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11403 12:13:19.948189 /lava-12669528/1/../bin/lava-test-case
11404 12:13:19.954258 <8>[ 27.483698] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11405 12:13:19.955113 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11407 12:13:19.968724 /lava-12669528/1/../bin/lava-test-case
11408 12:13:19.975640 <8>[ 27.504537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11409 12:13:19.976539 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11411 12:13:19.985203 /lava-12669528/1/../bin/lava-test-case
11412 12:13:19.994626 <8>[ 27.522320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11413 12:13:19.995598 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11415 12:13:20.005570 /lava-12669528/1/../bin/lava-test-case
11416 12:13:20.012539 <8>[ 27.542542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11417 12:13:20.013438 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11419 12:13:20.023340 /lava-12669528/1/../bin/lava-test-case
11420 12:13:20.030119 <8>[ 27.560043] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11421 12:13:20.030973 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11423 12:13:20.042052 /lava-12669528/1/../bin/lava-test-case
11424 12:13:20.048083 <8>[ 27.577321] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11425 12:13:20.048936 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11427 12:13:20.065905 /lava-12669528/1/../bin/lava-tes<8>[ 27.594257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11428 12:13:20.066501 t-case
11429 12:13:20.067156 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11431 12:13:20.076153 /lava-12669528/1/../bin/lava-test-case
11432 12:13:20.086177 <8>[ 27.614063] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11433 12:13:20.087038 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11435 12:13:20.096489 /lava-12669528/1/../bin/lava-test-case
11436 12:13:20.103418 <8>[ 27.632312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11437 12:13:20.104331 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11439 12:13:20.121327 /lava-12669528/1/../bin/lava-tes<8>[ 27.649803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11440 12:13:20.121900 t-case
11441 12:13:20.122550 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11443 12:13:20.140309 /lava-12669528/1/../bin/lava-tes<8>[ 27.668814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11444 12:13:20.140877 t-case
11445 12:13:20.141522 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11447 12:13:20.156326 /lava-12669528/1/../bin/lava-tes<8>[ 27.684819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11448 12:13:20.156893 t-case
11449 12:13:20.157537 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11451 12:13:20.166729 /lava-12669528/1/../bin/lava-test-case
11452 12:13:20.175912 <8>[ 27.704255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11453 12:13:20.176663 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11455 12:13:20.185251 /lava-12669528/1/../bin/lava-test-case
11456 12:13:20.192020 <8>[ 27.720824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11457 12:13:20.192940 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11459 12:13:20.202912 /lava-12669528/1/../bin/lava-test-case
11460 12:13:20.209282 <8>[ 27.739709] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11461 12:13:20.210134 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11463 12:13:20.220112 /lava-12669528/1/../bin/lava-test-case
11464 12:13:20.226816 <8>[ 27.756247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11465 12:13:20.227648 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11467 12:13:20.238192 /lava-12669528/1/../bin/lava-test-case
11468 12:13:20.245425 <8>[ 27.775357] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11469 12:13:20.246281 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11471 12:13:20.254805 /lava-12669528/1/../bin/lava-test-case
11472 12:13:20.261053 <8>[ 27.790369] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11473 12:13:20.261797 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11475 12:13:20.273076 /lava-12669528/1/../bin/lava-test-case
11476 12:13:20.279280 <8>[ 27.808791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11477 12:13:20.280189 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11479 12:13:20.287450 /lava-12669528/1/../bin/lava-test-case
11480 12:13:20.294666 <8>[ 27.824533] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11481 12:13:20.295540 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11483 12:13:21.309090 /lava-12669528/1/../bin/lava-test-case
11484 12:13:21.316181 <8>[ 28.846215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11485 12:13:21.317028 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11487 12:13:22.331013 /lava-12669528/1/../bin/lava-test-case
11488 12:13:22.337641 <8>[ 29.866941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11489 12:13:22.338488 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11491 12:13:22.357052 /lava-12669528/1/../bin/lava-tes<8>[ 29.885592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11492 12:13:22.357643 t-case
11493 12:13:22.358295 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11495 12:13:22.367266 /lava-12669528/1/../bin/lava-test-case
11496 12:13:22.373158 <8>[ 29.903962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11497 12:13:22.374002 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11499 12:13:22.389452 /lava-12669528/1/../bin/lava-tes<8>[ 29.918738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11500 12:13:22.390012 t-case
11501 12:13:22.390650 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11503 12:13:22.401746 /lava-12669528/1/../bin/lava-test-case
11504 12:13:22.408313 <8>[ 29.939285] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11505 12:13:22.409058 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11507 12:13:22.418430 /lava-12669528/1/../bin/lava-test-case
11508 12:13:22.424246 <8>[ 29.954863] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11509 12:13:22.425076 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11511 12:13:22.436962 /lava-12669528/1/../bin/lava-test-case
11512 12:13:22.443254 <8>[ 29.973158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11513 12:13:22.444145 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11515 12:13:22.454349 /lava-12669528/1/../bin/lava-test-case
11516 12:13:22.460894 <8>[ 29.990711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11517 12:13:22.461782 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11519 12:13:22.471163 /lava-12669528/1/../bin/lava-test-case
11520 12:13:22.478201 <8>[ 30.007967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11521 12:13:22.479024 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11523 12:13:22.489501 /lava-12669528/1/../bin/lava-test-case
11524 12:13:22.496209 <8>[ 30.026653] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11525 12:13:22.497067 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11527 12:13:22.510219 /lava-12669528/1/../bin/lava-test-case
11528 12:13:22.515509 <8>[ 30.045963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11529 12:13:22.516421 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11531 12:13:22.531795 /lava-12669528/1/../bin/lava-tes<8>[ 30.060364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11532 12:13:22.532351 t-case
11533 12:13:22.532990 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11535 12:13:22.549011 /lava-12669528/1/../bin/lava-tes<8>[ 30.077621] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11536 12:13:22.549583 t-case
11537 12:13:22.550231 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11539 12:13:22.557674 /lava-12669528/1/../bin/lava-test-case
11540 12:13:22.563911 <8>[ 30.094004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11541 12:13:22.564764 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11543 12:13:22.574943 /lava-12669528/1/../bin/lava-test-case
11544 12:13:22.581590 <8>[ 30.111730] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11545 12:13:22.582448 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11547 12:13:22.590085 /lava-12669528/1/../bin/lava-test-case
11548 12:13:22.596672 <8>[ 30.127215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11549 12:13:22.597414 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11551 12:13:22.607908 /lava-12669528/1/../bin/lava-test-case
11552 12:13:22.614178 <8>[ 30.144312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11553 12:13:22.615036 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11555 12:13:22.623714 /lava-12669528/1/../bin/lava-test-case
11556 12:13:22.630294 <8>[ 30.159469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11557 12:13:22.631168 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11559 12:13:22.640695 /lava-12669528/1/../bin/lava-test-case
11560 12:13:22.647451 <8>[ 30.178086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11561 12:13:22.648356 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11563 12:13:22.657708 /lava-12669528/1/../bin/lava-test-case
11564 12:13:22.664677 <8>[ 30.193499] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11565 12:13:22.665535 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11567 12:13:22.678196 /lava-12669528/1/../bin/lava-test-case
11568 12:13:22.683793 <8>[ 30.213046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11569 12:13:22.684779 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11571 12:13:23.695933 /lava-12669528/1/../bin/lava-test-case
11572 12:13:23.702452 <8>[ 31.233282] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11573 12:13:23.702711 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11575 12:13:24.715362 /lava-12669528/1/../bin/lava-test-case
11576 12:13:24.722098 <8>[ 32.251763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11577 12:13:24.722954 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11578 12:13:24.723435 Bad test result: blocked
11579 12:13:24.733021 /lava-12669528/1/../bin/lava-test-case
11580 12:13:24.740023 <8>[ 32.270784] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11581 12:13:24.740890 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11583 12:13:25.754231 /lava-12669528/1/../bin/lava-test-case
11584 12:13:25.760499 <8>[ 33.290876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11585 12:13:25.761347 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11587 12:13:25.780233 /lava-12669528/1/../bin/lava-tes<8>[ 33.309554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11588 12:13:25.780813 t-case
11589 12:13:25.781566 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11591 12:13:25.795007 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11593 12:13:25.797861 /lava-12669528/1/../bin/lava-tes<8>[ 33.326905] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11594 12:13:25.798434 t-case
11595 12:13:25.808224 /lava-12669528/1/../bin/lava-test-case
11596 12:13:25.814118 <8>[ 33.345353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11597 12:13:25.814973 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11599 12:13:25.824404 /lava-12669528/1/../bin/lava-test-case
11600 12:13:25.831448 <8>[ 33.361134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11601 12:13:25.832395 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11603 12:13:25.841938 /lava-12669528/1/../bin/lava-test-case
11604 12:13:25.848524 <8>[ 33.378431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11605 12:13:25.849372 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11607 12:13:25.864327 /lava-12669528/1/../bin/lava-tes<8>[ 33.393438] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11608 12:13:25.864900 t-case
11609 12:13:25.865548 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11611 12:13:26.876053 /lava-12669528/1/../bin/lava-test-case
11612 12:13:26.882193 <8>[ 34.412161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11613 12:13:26.883052 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11615 12:13:26.899267 /lava-12669528/1/../bin/lava-tes<8>[ 34.428042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11616 12:13:26.899886 t-case
11617 12:13:26.900537 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11619 12:13:27.912255 /lava-12669528/1/../bin/lava-test-case
11620 12:13:27.919338 <8>[ 35.449257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11621 12:13:27.920202 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11623 12:13:27.929326 /lava-12669528/1/../bin/lava-test-case
11624 12:13:27.936187 <8>[ 35.468099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11625 12:13:27.936923 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11627 12:13:28.950802 /lava-12669528/1/../bin/lava-test-case
11628 12:13:28.956261 <8>[ 36.488599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11629 12:13:28.957061 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11631 12:13:28.968200 /lava-12669528/1/../bin/lava-test-case
11632 12:13:28.975078 <8>[ 36.504891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11633 12:13:28.975923 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11635 12:13:29.989523 /lava-12669528/1/../bin/lava-test-case
11636 12:13:29.997303 <8>[ 37.526865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11637 12:13:29.998137 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11639 12:13:30.015163 /lava-12669528/1/../bin/lava-tes<8>[ 37.544351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11640 12:13:30.015804 t-case
11641 12:13:30.016578 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11643 12:13:30.028692 /lava-12669528/1/../bin/lava-tes<8>[ 37.561349] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11644 12:13:30.029572 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11646 12:13:30.031405 t-case
11647 12:13:30.042247 /lava-12669528/1/../bin/lava-test-case
11648 12:13:30.048887 <8>[ 37.579138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11649 12:13:30.049642 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11651 12:13:30.058319 /lava-12669528/1/../bin/lava-test-case
11652 12:13:30.064380 <8>[ 37.594321] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11653 12:13:30.065139 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11655 12:13:30.079240 /lava-12669528/1/../bin/lava-test-case
11656 12:13:30.086372 <8>[ 37.615981] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11657 12:13:30.087240 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11659 12:13:30.094212 /lava-12669528/1/../bin/lava-test-case
11660 12:13:30.100209 <8>[ 37.631874] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11661 12:13:30.101084 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11663 12:13:30.114136 /lava-12669528/1/../bin/lava-test-case
11664 12:13:30.120019 <8>[ 37.650616] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11665 12:13:30.120779 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11667 12:13:30.128807 /lava-12669528/1/../bin/lava-test-case
11668 12:13:30.134987 <8>[ 37.666247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11669 12:13:30.135965 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11671 12:13:30.147880 /lava-12669528/1/../bin/lava-test-case
11672 12:13:30.154830 <8>[ 37.685523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11673 12:13:30.155770 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11675 12:13:30.162567 + <8>[ 37.696368] <LAVA_SIGNAL_ENDRUN 1_bootrr 12669528_1.5.2.3.5>
11676 12:13:30.163382 Received signal: <ENDRUN> 1_bootrr 12669528_1.5.2.3.5
11677 12:13:30.163853 Ending use of test pattern.
11678 12:13:30.164214 Ending test lava.1_bootrr (12669528_1.5.2.3.5), duration 20.37
11680 12:13:30.165922 set +x
11681 12:13:30.166307 <LAVA_TEST_RUNNER EXIT>
11682 12:13:30.166920 ok: lava_test_shell seems to have completed
11683 12:13:30.172404 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11684 12:13:30.173175 end: 4.1 lava-test-shell (duration 00:00:21) [common]
11685 12:13:30.173650 end: 4 lava-test-retry (duration 00:00:21) [common]
11686 12:13:30.174136 start: 5 finalize (timeout 00:07:59) [common]
11687 12:13:30.174575 start: 5.1 power-off (timeout 00:00:30) [common]
11688 12:13:30.175306 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11689 12:13:30.296562 >> Command sent successfully.
11690 12:13:30.300648 Returned 0 in 0 seconds
11691 12:13:30.401583 end: 5.1 power-off (duration 00:00:00) [common]
11693 12:13:30.403380 start: 5.2 read-feedback (timeout 00:07:59) [common]
11694 12:13:30.404699 Listened to connection for namespace 'common' for up to 1s
11695 12:13:31.405398 Finalising connection for namespace 'common'
11696 12:13:31.406088 Disconnecting from shell: Finalise
11697 12:13:31.406497 / #
11698 12:13:31.507528 end: 5.2 read-feedback (duration 00:00:01) [common]
11699 12:13:31.508368 end: 5 finalize (duration 00:00:01) [common]
11700 12:13:31.509005 Cleaning after the job
11701 12:13:31.509529 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669528/tftp-deploy-1gcokwmw/ramdisk
11702 12:13:31.523353 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669528/tftp-deploy-1gcokwmw/kernel
11703 12:13:31.553144 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669528/tftp-deploy-1gcokwmw/dtb
11704 12:13:31.553534 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669528/tftp-deploy-1gcokwmw/modules
11705 12:13:31.565637 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12669528
11706 12:13:31.615981 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12669528
11707 12:13:31.616161 Job finished correctly