Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 17
- Kernel Errors: 38
1 12:13:14.417231 lava-dispatcher, installed at version: 2023.10
2 12:13:14.417450 start: 0 validate
3 12:13:14.417591 Start time: 2024-01-31 12:13:14.417583+00:00 (UTC)
4 12:13:14.417721 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:13:14.417850 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 12:13:14.693245 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:13:14.694229 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:13:28.475853 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:13:28.476622 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:13:28.745509 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:13:28.746228 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:13:29.009130 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:13:29.009848 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:13:33.027111 validate duration: 18.61
16 12:13:33.028395 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:13:33.029003 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:13:33.029506 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:13:33.030127 Not decompressing ramdisk as can be used compressed.
20 12:13:33.030609 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
21 12:13:33.030967 saving as /var/lib/lava/dispatcher/tmp/12669535/tftp-deploy-ejgbvkr4/ramdisk/initrd.cpio.gz
22 12:13:33.031324 total size: 4665412 (4 MB)
23 12:13:33.298041 progress 0 % (0 MB)
24 12:13:33.300976 progress 5 % (0 MB)
25 12:13:33.303454 progress 10 % (0 MB)
26 12:13:33.305581 progress 15 % (0 MB)
27 12:13:33.307580 progress 20 % (0 MB)
28 12:13:33.309509 progress 25 % (1 MB)
29 12:13:33.311241 progress 30 % (1 MB)
30 12:13:33.313023 progress 35 % (1 MB)
31 12:13:33.314677 progress 40 % (1 MB)
32 12:13:33.316517 progress 45 % (2 MB)
33 12:13:33.318054 progress 50 % (2 MB)
34 12:13:33.319556 progress 55 % (2 MB)
35 12:13:33.320939 progress 60 % (2 MB)
36 12:13:33.322312 progress 65 % (2 MB)
37 12:13:33.323677 progress 70 % (3 MB)
38 12:13:33.324999 progress 75 % (3 MB)
39 12:13:33.326249 progress 80 % (3 MB)
40 12:13:33.327666 progress 85 % (3 MB)
41 12:13:33.328917 progress 90 % (4 MB)
42 12:13:33.330154 progress 95 % (4 MB)
43 12:13:33.331391 progress 100 % (4 MB)
44 12:13:33.331545 4 MB downloaded in 0.30 s (14.82 MB/s)
45 12:13:33.331690 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:13:33.331927 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:13:33.332012 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:13:33.332094 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:13:33.332217 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:13:33.332289 saving as /var/lib/lava/dispatcher/tmp/12669535/tftp-deploy-ejgbvkr4/kernel/Image
52 12:13:33.332350 total size: 51532288 (49 MB)
53 12:13:33.332410 No compression specified
54 12:13:33.333485 progress 0 % (0 MB)
55 12:13:33.346844 progress 5 % (2 MB)
56 12:13:33.360265 progress 10 % (4 MB)
57 12:13:33.373844 progress 15 % (7 MB)
58 12:13:33.387521 progress 20 % (9 MB)
59 12:13:33.401093 progress 25 % (12 MB)
60 12:13:33.414252 progress 30 % (14 MB)
61 12:13:33.427655 progress 35 % (17 MB)
62 12:13:33.440899 progress 40 % (19 MB)
63 12:13:33.454262 progress 45 % (22 MB)
64 12:13:33.467698 progress 50 % (24 MB)
65 12:13:33.481059 progress 55 % (27 MB)
66 12:13:33.494745 progress 60 % (29 MB)
67 12:13:33.508221 progress 65 % (31 MB)
68 12:13:33.521808 progress 70 % (34 MB)
69 12:13:33.535654 progress 75 % (36 MB)
70 12:13:33.549619 progress 80 % (39 MB)
71 12:13:33.562923 progress 85 % (41 MB)
72 12:13:33.576249 progress 90 % (44 MB)
73 12:13:33.589538 progress 95 % (46 MB)
74 12:13:33.602430 progress 100 % (49 MB)
75 12:13:33.602656 49 MB downloaded in 0.27 s (181.81 MB/s)
76 12:13:33.602799 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:13:33.603028 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:13:33.603114 start: 1.3 download-retry (timeout 00:09:59) [common]
80 12:13:33.603203 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 12:13:33.603322 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:13:33.603391 saving as /var/lib/lava/dispatcher/tmp/12669535/tftp-deploy-ejgbvkr4/dtb/mt8192-asurada-spherion-r0.dtb
83 12:13:33.603451 total size: 47278 (0 MB)
84 12:13:33.603510 No compression specified
85 12:13:33.604613 progress 69 % (0 MB)
86 12:13:33.604886 progress 100 % (0 MB)
87 12:13:33.605042 0 MB downloaded in 0.00 s (28.38 MB/s)
88 12:13:33.605162 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:13:33.605384 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:13:33.605468 start: 1.4 download-retry (timeout 00:09:59) [common]
92 12:13:33.605548 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 12:13:33.605660 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
94 12:13:33.605726 saving as /var/lib/lava/dispatcher/tmp/12669535/tftp-deploy-ejgbvkr4/nfsrootfs/full.rootfs.tar
95 12:13:33.605786 total size: 125290964 (119 MB)
96 12:13:33.605845 Using unxz to decompress xz
97 12:13:33.610058 progress 0 % (0 MB)
98 12:13:33.934318 progress 5 % (6 MB)
99 12:13:34.263141 progress 10 % (11 MB)
100 12:13:34.590807 progress 15 % (17 MB)
101 12:13:34.773324 progress 20 % (23 MB)
102 12:13:34.945731 progress 25 % (29 MB)
103 12:13:35.291445 progress 30 % (35 MB)
104 12:13:35.641222 progress 35 % (41 MB)
105 12:13:36.022526 progress 40 % (47 MB)
106 12:13:36.394157 progress 45 % (53 MB)
107 12:13:36.776068 progress 50 % (59 MB)
108 12:13:37.123173 progress 55 % (65 MB)
109 12:13:37.482695 progress 60 % (71 MB)
110 12:13:37.818275 progress 65 % (77 MB)
111 12:13:38.178384 progress 70 % (83 MB)
112 12:13:38.554020 progress 75 % (89 MB)
113 12:13:38.969011 progress 80 % (95 MB)
114 12:13:39.402136 progress 85 % (101 MB)
115 12:13:39.645795 progress 90 % (107 MB)
116 12:13:39.980279 progress 95 % (113 MB)
117 12:13:40.355997 progress 100 % (119 MB)
118 12:13:40.361855 119 MB downloaded in 6.76 s (17.69 MB/s)
119 12:13:40.362151 end: 1.4.1 http-download (duration 00:00:07) [common]
121 12:13:40.362544 end: 1.4 download-retry (duration 00:00:07) [common]
122 12:13:40.362662 start: 1.5 download-retry (timeout 00:09:53) [common]
123 12:13:40.362782 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 12:13:40.362971 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:13:40.363069 saving as /var/lib/lava/dispatcher/tmp/12669535/tftp-deploy-ejgbvkr4/modules/modules.tar
126 12:13:40.363158 total size: 8639916 (8 MB)
127 12:13:40.363251 Using unxz to decompress xz
128 12:13:40.632866 progress 0 % (0 MB)
129 12:13:40.689268 progress 5 % (0 MB)
130 12:13:40.713933 progress 10 % (0 MB)
131 12:13:40.737620 progress 15 % (1 MB)
132 12:13:40.761149 progress 20 % (1 MB)
133 12:13:40.785154 progress 25 % (2 MB)
134 12:13:40.812947 progress 30 % (2 MB)
135 12:13:40.837287 progress 35 % (2 MB)
136 12:13:40.860797 progress 40 % (3 MB)
137 12:13:40.885265 progress 45 % (3 MB)
138 12:13:40.910656 progress 50 % (4 MB)
139 12:13:40.936889 progress 55 % (4 MB)
140 12:13:40.961894 progress 60 % (4 MB)
141 12:13:40.988135 progress 65 % (5 MB)
142 12:13:41.013125 progress 70 % (5 MB)
143 12:13:41.036756 progress 75 % (6 MB)
144 12:13:41.064139 progress 80 % (6 MB)
145 12:13:41.092123 progress 85 % (7 MB)
146 12:13:41.117205 progress 90 % (7 MB)
147 12:13:41.146993 progress 95 % (7 MB)
148 12:13:41.174896 progress 100 % (8 MB)
149 12:13:41.180818 8 MB downloaded in 0.82 s (10.08 MB/s)
150 12:13:41.181071 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:13:41.181329 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:13:41.181420 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 12:13:41.181515 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 12:13:43.339704 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12669535/extract-nfsrootfs-gf8v15sn
156 12:13:43.339890 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 12:13:43.339990 start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
158 12:13:43.340152 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj
159 12:13:43.340295 makedir: /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin
160 12:13:43.340402 makedir: /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/tests
161 12:13:43.340506 makedir: /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/results
162 12:13:43.340606 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-add-keys
163 12:13:43.340750 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-add-sources
164 12:13:43.340881 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-background-process-start
165 12:13:43.341010 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-background-process-stop
166 12:13:43.341136 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-common-functions
167 12:13:43.341263 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-echo-ipv4
168 12:13:43.341390 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-install-packages
169 12:13:43.341516 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-installed-packages
170 12:13:43.341640 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-os-build
171 12:13:43.341767 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-probe-channel
172 12:13:43.341894 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-probe-ip
173 12:13:43.342018 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-target-ip
174 12:13:43.342143 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-target-mac
175 12:13:43.342267 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-target-storage
176 12:13:43.342394 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-test-case
177 12:13:43.342520 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-test-event
178 12:13:43.342644 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-test-feedback
179 12:13:43.342768 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-test-raise
180 12:13:43.342893 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-test-reference
181 12:13:43.343017 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-test-runner
182 12:13:43.343143 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-test-set
183 12:13:43.343268 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-test-shell
184 12:13:43.343396 Updating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-install-packages (oe)
185 12:13:43.343543 Updating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/bin/lava-installed-packages (oe)
186 12:13:43.343668 Creating /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/environment
187 12:13:43.343765 LAVA metadata
188 12:13:43.343835 - LAVA_JOB_ID=12669535
189 12:13:43.343899 - LAVA_DISPATCHER_IP=192.168.201.1
190 12:13:43.344000 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
191 12:13:43.344068 skipped lava-vland-overlay
192 12:13:43.344143 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 12:13:43.344223 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
194 12:13:43.344341 skipped lava-multinode-overlay
195 12:13:43.344429 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 12:13:43.344511 start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
197 12:13:43.344587 Loading test definitions
198 12:13:43.344679 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
199 12:13:43.344751 Using /lava-12669535 at stage 0
200 12:13:43.345066 uuid=12669535_1.6.2.3.1 testdef=None
201 12:13:43.345157 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 12:13:43.345244 start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
203 12:13:43.345748 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 12:13:43.345972 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
206 12:13:43.346620 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 12:13:43.346851 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
209 12:13:43.347472 runner path: /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/0/tests/0_dmesg test_uuid 12669535_1.6.2.3.1
210 12:13:43.347628 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 12:13:43.347853 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:50) [common]
213 12:13:43.347925 Using /lava-12669535 at stage 1
214 12:13:43.348239 uuid=12669535_1.6.2.3.5 testdef=None
215 12:13:43.348364 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 12:13:43.348452 start: 1.6.2.3.6 test-overlay (timeout 00:09:50) [common]
217 12:13:43.348926 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 12:13:43.349144 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:50) [common]
220 12:13:43.349814 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 12:13:43.350042 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
223 12:13:43.350668 runner path: /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/1/tests/1_bootrr test_uuid 12669535_1.6.2.3.5
224 12:13:43.350823 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 12:13:43.351027 Creating lava-test-runner.conf files
227 12:13:43.351091 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/0 for stage 0
228 12:13:43.351182 - 0_dmesg
229 12:13:43.351262 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12669535/lava-overlay-g5wzruvj/lava-12669535/1 for stage 1
230 12:13:43.351354 - 1_bootrr
231 12:13:43.351449 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 12:13:43.351535 start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
233 12:13:43.358987 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 12:13:43.359092 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
235 12:13:43.359179 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 12:13:43.359265 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 12:13:43.359353 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
238 12:13:43.482455 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 12:13:43.482836 start: 1.6.4 extract-modules (timeout 00:09:50) [common]
240 12:13:43.482956 extracting modules file /var/lib/lava/dispatcher/tmp/12669535/tftp-deploy-ejgbvkr4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12669535/extract-nfsrootfs-gf8v15sn
241 12:13:43.711176 extracting modules file /var/lib/lava/dispatcher/tmp/12669535/tftp-deploy-ejgbvkr4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12669535/extract-overlay-ramdisk-uf6308a1/ramdisk
242 12:13:43.944590 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 12:13:43.944745 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 12:13:43.944837 [common] Applying overlay to NFS
245 12:13:43.944913 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12669535/compress-overlay-9lakkq3y/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12669535/extract-nfsrootfs-gf8v15sn
246 12:13:43.953340 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 12:13:43.953472 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 12:13:43.953567 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 12:13:43.953657 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 12:13:43.953737 Building ramdisk /var/lib/lava/dispatcher/tmp/12669535/extract-overlay-ramdisk-uf6308a1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12669535/extract-overlay-ramdisk-uf6308a1/ramdisk
251 12:13:44.328474 >> 119414 blocks
252 12:13:46.264840 rename /var/lib/lava/dispatcher/tmp/12669535/extract-overlay-ramdisk-uf6308a1/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12669535/tftp-deploy-ejgbvkr4/ramdisk/ramdisk.cpio.gz
253 12:13:46.265303 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 12:13:46.265435 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 12:13:46.265540 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 12:13:46.265646 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12669535/tftp-deploy-ejgbvkr4/kernel/Image'
257 12:13:59.289189 Returned 0 in 13 seconds
258 12:13:59.389942 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12669535/tftp-deploy-ejgbvkr4/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12669535/tftp-deploy-ejgbvkr4/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12669535/tftp-deploy-ejgbvkr4/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12669535/tftp-deploy-ejgbvkr4/kernel/image.itb
259 12:13:59.780867 output: FIT description: Kernel Image image with one or more FDT blobs
260 12:13:59.781259 output: Created: Wed Jan 31 12:13:59 2024
261 12:13:59.781334 output: Image 0 (kernel-1)
262 12:13:59.781402 output: Description:
263 12:13:59.781466 output: Created: Wed Jan 31 12:13:59 2024
264 12:13:59.781528 output: Type: Kernel Image
265 12:13:59.781590 output: Compression: lzma compressed
266 12:13:59.781646 output: Data Size: 12047284 Bytes = 11764.93 KiB = 11.49 MiB
267 12:13:59.781704 output: Architecture: AArch64
268 12:13:59.781760 output: OS: Linux
269 12:13:59.781816 output: Load Address: 0x00000000
270 12:13:59.781872 output: Entry Point: 0x00000000
271 12:13:59.781928 output: Hash algo: crc32
272 12:13:59.781984 output: Hash value: 5a47eb78
273 12:13:59.782040 output: Image 1 (fdt-1)
274 12:13:59.782093 output: Description: mt8192-asurada-spherion-r0
275 12:13:59.782145 output: Created: Wed Jan 31 12:13:59 2024
276 12:13:59.782199 output: Type: Flat Device Tree
277 12:13:59.782252 output: Compression: uncompressed
278 12:13:59.782305 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
279 12:13:59.782358 output: Architecture: AArch64
280 12:13:59.782410 output: Hash algo: crc32
281 12:13:59.782463 output: Hash value: cc4352de
282 12:13:59.782516 output: Image 2 (ramdisk-1)
283 12:13:59.782569 output: Description: unavailable
284 12:13:59.782622 output: Created: Wed Jan 31 12:13:59 2024
285 12:13:59.782675 output: Type: RAMDisk Image
286 12:13:59.782728 output: Compression: Unknown Compression
287 12:13:59.782790 output: Data Size: 17798360 Bytes = 17381.21 KiB = 16.97 MiB
288 12:13:59.782853 output: Architecture: AArch64
289 12:13:59.782907 output: OS: Linux
290 12:13:59.782961 output: Load Address: unavailable
291 12:13:59.783014 output: Entry Point: unavailable
292 12:13:59.783067 output: Hash algo: crc32
293 12:13:59.783120 output: Hash value: 7f2f5f8d
294 12:13:59.783174 output: Default Configuration: 'conf-1'
295 12:13:59.783227 output: Configuration 0 (conf-1)
296 12:13:59.783280 output: Description: mt8192-asurada-spherion-r0
297 12:13:59.783333 output: Kernel: kernel-1
298 12:13:59.783387 output: Init Ramdisk: ramdisk-1
299 12:13:59.783440 output: FDT: fdt-1
300 12:13:59.783493 output: Loadables: kernel-1
301 12:13:59.783546 output:
302 12:13:59.783754 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
303 12:13:59.783858 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
304 12:13:59.783965 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
305 12:13:59.784061 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:33) [common]
306 12:13:59.784142 No LXC device requested
307 12:13:59.784223 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 12:13:59.784341 start: 1.8 deploy-device-env (timeout 00:09:33) [common]
309 12:13:59.784435 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 12:13:59.784503 Checking files for TFTP limit of 4294967296 bytes.
311 12:13:59.785020 end: 1 tftp-deploy (duration 00:00:27) [common]
312 12:13:59.785126 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 12:13:59.785221 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 12:13:59.785349 substitutions:
315 12:13:59.785417 - {DTB}: 12669535/tftp-deploy-ejgbvkr4/dtb/mt8192-asurada-spherion-r0.dtb
316 12:13:59.785481 - {INITRD}: 12669535/tftp-deploy-ejgbvkr4/ramdisk/ramdisk.cpio.gz
317 12:13:59.785541 - {KERNEL}: 12669535/tftp-deploy-ejgbvkr4/kernel/Image
318 12:13:59.785600 - {LAVA_MAC}: None
319 12:13:59.785658 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12669535/extract-nfsrootfs-gf8v15sn
320 12:13:59.785716 - {NFS_SERVER_IP}: 192.168.201.1
321 12:13:59.785772 - {PRESEED_CONFIG}: None
322 12:13:59.785828 - {PRESEED_LOCAL}: None
323 12:13:59.785884 - {RAMDISK}: 12669535/tftp-deploy-ejgbvkr4/ramdisk/ramdisk.cpio.gz
324 12:13:59.785939 - {ROOT_PART}: None
325 12:13:59.785995 - {ROOT}: None
326 12:13:59.786049 - {SERVER_IP}: 192.168.201.1
327 12:13:59.786104 - {TEE}: None
328 12:13:59.786159 Parsed boot commands:
329 12:13:59.786212 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 12:13:59.786402 Parsed boot commands: tftpboot 192.168.201.1 12669535/tftp-deploy-ejgbvkr4/kernel/image.itb 12669535/tftp-deploy-ejgbvkr4/kernel/cmdline
331 12:13:59.786490 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 12:13:59.786573 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 12:13:59.786668 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 12:13:59.786753 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 12:13:59.786824 Not connected, no need to disconnect.
336 12:13:59.786900 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 12:13:59.786985 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 12:13:59.787054 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
339 12:13:59.791124 Setting prompt string to ['lava-test: # ']
340 12:13:59.791494 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 12:13:59.791605 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 12:13:59.791708 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 12:13:59.791801 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 12:13:59.792062 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
345 12:14:04.939103 >> Command sent successfully.
346 12:14:04.950123 Returned 0 in 5 seconds
347 12:14:05.051364 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 12:14:05.053028 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 12:14:05.053537 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 12:14:05.054015 Setting prompt string to 'Starting depthcharge on Spherion...'
352 12:14:05.054476 Changing prompt to 'Starting depthcharge on Spherion...'
353 12:14:05.054850 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 12:14:05.056121 [Enter `^Ec?' for help]
355 12:14:05.215163
356 12:14:05.215726
357 12:14:05.216090 F0: 102B 0000
358 12:14:05.216538
359 12:14:05.217087 F3: 1001 0000 [0200]
360 12:14:05.218241
361 12:14:05.218674 F3: 1001 0000
362 12:14:05.219021
363 12:14:05.219341 F7: 102D 0000
364 12:14:05.219661
365 12:14:05.221498 F1: 0000 0000
366 12:14:05.221934
367 12:14:05.222278 V0: 0000 0000 [0001]
368 12:14:05.222616
369 12:14:05.224824 00: 0007 8000
370 12:14:05.225281
371 12:14:05.225628 01: 0000 0000
372 12:14:05.225961
373 12:14:05.228353 BP: 0C00 0209 [0000]
374 12:14:05.228791
375 12:14:05.229140 G0: 1182 0000
376 12:14:05.229466
377 12:14:05.232438 EC: 0000 0021 [4000]
378 12:14:05.232977
379 12:14:05.233332 S7: 0000 0000 [0000]
380 12:14:05.233711
381 12:14:05.235338 CC: 0000 0000 [0001]
382 12:14:05.235831
383 12:14:05.236398 T0: 0000 0040 [010F]
384 12:14:05.236755
385 12:14:05.237078 Jump to BL
386 12:14:05.238471
387 12:14:05.262358
388 12:14:05.262907
389 12:14:05.263257
390 12:14:05.269711 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 12:14:05.272777 ARM64: Exception handlers installed.
392 12:14:05.277128 ARM64: Testing exception
393 12:14:05.279814 ARM64: Done test exception
394 12:14:05.286723 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 12:14:05.296862 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 12:14:05.303392 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 12:14:05.313313 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 12:14:05.320358 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 12:14:05.326959 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 12:14:05.338636 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 12:14:05.345594 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 12:14:05.364789 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 12:14:05.367753 WDT: Last reset was cold boot
404 12:14:05.371498 SPI1(PAD0) initialized at 2873684 Hz
405 12:14:05.375057 SPI5(PAD0) initialized at 992727 Hz
406 12:14:05.378358 VBOOT: Loading verstage.
407 12:14:05.385273 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 12:14:05.389715 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 12:14:05.392665 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 12:14:05.395788 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 12:14:05.402316 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 12:14:05.409197 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 12:14:05.419914 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
414 12:14:05.420534
415 12:14:05.420928
416 12:14:05.430310 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 12:14:05.434059 ARM64: Exception handlers installed.
418 12:14:05.436903 ARM64: Testing exception
419 12:14:05.437422 ARM64: Done test exception
420 12:14:05.443664 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 12:14:05.447260 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:14:05.460960 Probing TPM: . done!
423 12:14:05.461507 TPM ready after 0 ms
424 12:14:05.468689 Connected to device vid:did:rid of 1ae0:0028:00
425 12:14:05.475519 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
426 12:14:05.534534 Initialized TPM device CR50 revision 0
427 12:14:05.545722 tlcl_send_startup: Startup return code is 0
428 12:14:05.546210 TPM: setup succeeded
429 12:14:05.557204 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 12:14:05.566454 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 12:14:05.578235 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 12:14:05.588211 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 12:14:05.592460 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 12:14:05.596110 in-header: 03 07 00 00 08 00 00 00
435 12:14:05.599440 in-data: aa e4 47 04 13 02 00 00
436 12:14:05.599941 Chrome EC: UHEPI supported
437 12:14:05.606830 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 12:14:05.611342 in-header: 03 95 00 00 08 00 00 00
439 12:14:05.615254 in-data: 18 20 20 08 00 00 00 00
440 12:14:05.615736 Phase 1
441 12:14:05.618925 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 12:14:05.626479 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 12:14:05.633371 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 12:14:05.633937 Recovery requested (1009000e)
445 12:14:05.646120 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 12:14:05.650385 tlcl_extend: response is 0
447 12:14:05.659373 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 12:14:05.664497 tlcl_extend: response is 0
449 12:14:05.671663 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 12:14:05.691633 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
451 12:14:05.698168 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 12:14:05.698746
453 12:14:05.699123
454 12:14:05.708356 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 12:14:05.711692 ARM64: Exception handlers installed.
456 12:14:05.714593 ARM64: Testing exception
457 12:14:05.715089 ARM64: Done test exception
458 12:14:05.736767 pmic_efuse_setting: Set efuses in 11 msecs
459 12:14:05.740705 pmwrap_interface_init: Select PMIF_VLD_RDY
460 12:14:05.747298 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 12:14:05.750331 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 12:14:05.753979 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 12:14:05.761661 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 12:14:05.765368 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 12:14:05.768880 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 12:14:05.776435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 12:14:05.779710 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 12:14:05.783410 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 12:14:05.791061 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 12:14:05.794603 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 12:14:05.798297 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 12:14:05.801462 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 12:14:05.809608 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 12:14:05.817310 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 12:14:05.820443 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 12:14:05.827709 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 12:14:05.831386 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 12:14:05.838776 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 12:14:05.842277 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 12:14:05.850082 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 12:14:05.853993 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 12:14:05.860780 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 12:14:05.865036 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 12:14:05.871519 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 12:14:05.875324 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 12:14:05.882853 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 12:14:05.886640 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 12:14:05.890545 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 12:14:05.898115 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 12:14:05.901031 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 12:14:05.904839 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 12:14:05.912698 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 12:14:05.916273 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 12:14:05.919490 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 12:14:05.927836 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 12:14:05.931534 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 12:14:05.935520 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 12:14:05.939183 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 12:14:05.946312 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 12:14:05.949697 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 12:14:05.953625 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 12:14:05.957110 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 12:14:05.960993 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 12:14:05.968419 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 12:14:05.972271 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 12:14:05.975471 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 12:14:05.979117 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 12:14:05.982907 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 12:14:05.986423 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 12:14:05.990111 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 12:14:06.001108 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 12:14:06.008903 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 12:14:06.012681 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 12:14:06.020412 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 12:14:06.030615 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 12:14:06.034743 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 12:14:06.038440 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 12:14:06.041426 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 12:14:06.050042 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
520 12:14:06.053753 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 12:14:06.062599 [RTC]rtc_osc_init,62: osc32con val = 0xde70
522 12:14:06.065704 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 12:14:06.074610 [RTC]rtc_get_frequency_meter,154: input=15, output=759
524 12:14:06.083881 [RTC]rtc_get_frequency_meter,154: input=23, output=943
525 12:14:06.093973 [RTC]rtc_get_frequency_meter,154: input=19, output=850
526 12:14:06.103277 [RTC]rtc_get_frequency_meter,154: input=17, output=805
527 12:14:06.113080 [RTC]rtc_get_frequency_meter,154: input=16, output=781
528 12:14:06.121743 [RTC]rtc_get_frequency_meter,154: input=16, output=781
529 12:14:06.131972 [RTC]rtc_get_frequency_meter,154: input=17, output=805
530 12:14:06.135860 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
531 12:14:06.139323 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
532 12:14:06.143715 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
533 12:14:06.151665 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
534 12:14:06.154931 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
535 12:14:06.158547 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
536 12:14:06.162397 ADC[4]: Raw value=906573 ID=7
537 12:14:06.162832 ADC[3]: Raw value=213810 ID=1
538 12:14:06.166277 RAM Code: 0x71
539 12:14:06.170244 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
540 12:14:06.173460 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
541 12:14:06.181824 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
542 12:14:06.188759 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
543 12:14:06.192163 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
544 12:14:06.195674 in-header: 03 07 00 00 08 00 00 00
545 12:14:06.200617 in-data: aa e4 47 04 13 02 00 00
546 12:14:06.203921 Chrome EC: UHEPI supported
547 12:14:06.207043 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
548 12:14:06.211324 in-header: 03 95 00 00 08 00 00 00
549 12:14:06.215186 in-data: 18 20 20 08 00 00 00 00
550 12:14:06.218981 MRC: failed to locate region type 0.
551 12:14:06.225955 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
552 12:14:06.230016 DRAM-K: Running full calibration
553 12:14:06.233613 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 12:14:06.237029 header.status = 0x0
555 12:14:06.241207 header.version = 0x6 (expected: 0x6)
556 12:14:06.244331 header.size = 0xd00 (expected: 0xd00)
557 12:14:06.244819 header.flags = 0x0
558 12:14:06.252035 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
559 12:14:06.269095 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
560 12:14:06.276226 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
561 12:14:06.276763 dram_init: ddr_geometry: 2
562 12:14:06.280007 [EMI] MDL number = 2
563 12:14:06.284267 [EMI] Get MDL freq = 0
564 12:14:06.284745 dram_init: ddr_type: 0
565 12:14:06.287617 is_discrete_lpddr4: 1
566 12:14:06.288053 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
567 12:14:06.291664
568 12:14:06.292150
569 12:14:06.292742 [Bian_co] ETT version 0.0.0.1
570 12:14:06.298767 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
571 12:14:06.299247
572 12:14:06.302558 dramc_set_vcore_voltage set vcore to 650000
573 12:14:06.303004 Read voltage for 800, 4
574 12:14:06.303659 Vio18 = 0
575 12:14:06.306717 Vcore = 650000
576 12:14:06.307149 Vdram = 0
577 12:14:06.307495 Vddq = 0
578 12:14:06.310265 Vmddr = 0
579 12:14:06.310861 dram_init: config_dvfs: 1
580 12:14:06.314626 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
581 12:14:06.321322 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
582 12:14:06.325132 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
583 12:14:06.328715 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
584 12:14:06.332758 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
585 12:14:06.336601 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
586 12:14:06.337050 MEM_TYPE=3, freq_sel=18
587 12:14:06.340211 sv_algorithm_assistance_LP4_1600
588 12:14:06.346973 ============ PULL DRAM RESETB DOWN ============
589 12:14:06.350337 ========== PULL DRAM RESETB DOWN end =========
590 12:14:06.354049 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
591 12:14:06.357043 ===================================
592 12:14:06.360788 LPDDR4 DRAM CONFIGURATION
593 12:14:06.364385 ===================================
594 12:14:06.364921 EX_ROW_EN[0] = 0x0
595 12:14:06.368248 EX_ROW_EN[1] = 0x0
596 12:14:06.368741 LP4Y_EN = 0x0
597 12:14:06.371473 WORK_FSP = 0x0
598 12:14:06.371988 WL = 0x2
599 12:14:06.375299 RL = 0x2
600 12:14:06.375772 BL = 0x2
601 12:14:06.379471 RPST = 0x0
602 12:14:06.380140 RD_PRE = 0x0
603 12:14:06.382397 WR_PRE = 0x1
604 12:14:06.383089 WR_PST = 0x0
605 12:14:06.385721 DBI_WR = 0x0
606 12:14:06.386156 DBI_RD = 0x0
607 12:14:06.389219 OTF = 0x1
608 12:14:06.392208 ===================================
609 12:14:06.395778 ===================================
610 12:14:06.396213 ANA top config
611 12:14:06.399208 ===================================
612 12:14:06.402538 DLL_ASYNC_EN = 0
613 12:14:06.405858 ALL_SLAVE_EN = 1
614 12:14:06.406294 NEW_RANK_MODE = 1
615 12:14:06.409084 DLL_IDLE_MODE = 1
616 12:14:06.412472 LP45_APHY_COMB_EN = 1
617 12:14:06.415899 TX_ODT_DIS = 1
618 12:14:06.416475 NEW_8X_MODE = 1
619 12:14:06.419529 ===================================
620 12:14:06.422905 ===================================
621 12:14:06.426182 data_rate = 1600
622 12:14:06.429778 CKR = 1
623 12:14:06.433628 DQ_P2S_RATIO = 8
624 12:14:06.436635 ===================================
625 12:14:06.439916 CA_P2S_RATIO = 8
626 12:14:06.440400 DQ_CA_OPEN = 0
627 12:14:06.442870 DQ_SEMI_OPEN = 0
628 12:14:06.446869 CA_SEMI_OPEN = 0
629 12:14:06.449853 CA_FULL_RATE = 0
630 12:14:06.453111 DQ_CKDIV4_EN = 1
631 12:14:06.456124 CA_CKDIV4_EN = 1
632 12:14:06.456593 CA_PREDIV_EN = 0
633 12:14:06.459979 PH8_DLY = 0
634 12:14:06.463085 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
635 12:14:06.466474 DQ_AAMCK_DIV = 4
636 12:14:06.470227 CA_AAMCK_DIV = 4
637 12:14:06.470658 CA_ADMCK_DIV = 4
638 12:14:06.473110 DQ_TRACK_CA_EN = 0
639 12:14:06.476911 CA_PICK = 800
640 12:14:06.479972 CA_MCKIO = 800
641 12:14:06.483844 MCKIO_SEMI = 0
642 12:14:06.487642 PLL_FREQ = 3068
643 12:14:06.488093 DQ_UI_PI_RATIO = 32
644 12:14:06.491400 CA_UI_PI_RATIO = 0
645 12:14:06.495193 ===================================
646 12:14:06.498962 ===================================
647 12:14:06.499493 memory_type:LPDDR4
648 12:14:06.502845 GP_NUM : 10
649 12:14:06.506530 SRAM_EN : 1
650 12:14:06.506961 MD32_EN : 0
651 12:14:06.510443 ===================================
652 12:14:06.514223 [ANA_INIT] >>>>>>>>>>>>>>
653 12:14:06.514732 <<<<<< [CONFIGURE PHASE]: ANA_TX
654 12:14:06.518109 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
655 12:14:06.521265 ===================================
656 12:14:06.524141 data_rate = 1600,PCW = 0X7600
657 12:14:06.527957 ===================================
658 12:14:06.531608 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
659 12:14:06.537931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
660 12:14:06.540889 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
661 12:14:06.547833 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
662 12:14:06.551001 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
663 12:14:06.554460 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
664 12:14:06.554894 [ANA_INIT] flow start
665 12:14:06.557687 [ANA_INIT] PLL >>>>>>>>
666 12:14:06.561256 [ANA_INIT] PLL <<<<<<<<
667 12:14:06.561689 [ANA_INIT] MIDPI >>>>>>>>
668 12:14:06.564330 [ANA_INIT] MIDPI <<<<<<<<
669 12:14:06.567759 [ANA_INIT] DLL >>>>>>>>
670 12:14:06.568191 [ANA_INIT] flow end
671 12:14:06.574262 ============ LP4 DIFF to SE enter ============
672 12:14:06.577803 ============ LP4 DIFF to SE exit ============
673 12:14:06.581256 [ANA_INIT] <<<<<<<<<<<<<
674 12:14:06.584753 [Flow] Enable top DCM control >>>>>
675 12:14:06.588090 [Flow] Enable top DCM control <<<<<
676 12:14:06.588568 Enable DLL master slave shuffle
677 12:14:06.594808 ==============================================================
678 12:14:06.598113 Gating Mode config
679 12:14:06.601104 ==============================================================
680 12:14:06.605190 Config description:
681 12:14:06.614558 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
682 12:14:06.621400 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
683 12:14:06.624679 SELPH_MODE 0: By rank 1: By Phase
684 12:14:06.630913 ==============================================================
685 12:14:06.634681 GAT_TRACK_EN = 1
686 12:14:06.637871 RX_GATING_MODE = 2
687 12:14:06.641478 RX_GATING_TRACK_MODE = 2
688 12:14:06.641719 SELPH_MODE = 1
689 12:14:06.644266 PICG_EARLY_EN = 1
690 12:14:06.647695 VALID_LAT_VALUE = 1
691 12:14:06.654569 ==============================================================
692 12:14:06.657792 Enter into Gating configuration >>>>
693 12:14:06.661235 Exit from Gating configuration <<<<
694 12:14:06.664987 Enter into DVFS_PRE_config >>>>>
695 12:14:06.674571 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
696 12:14:06.678109 Exit from DVFS_PRE_config <<<<<
697 12:14:06.681545 Enter into PICG configuration >>>>
698 12:14:06.684841 Exit from PICG configuration <<<<
699 12:14:06.688009 [RX_INPUT] configuration >>>>>
700 12:14:06.691190 [RX_INPUT] configuration <<<<<
701 12:14:06.694390 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
702 12:14:06.700900 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
703 12:14:06.708056 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
704 12:14:06.711098 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
705 12:14:06.717987 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
706 12:14:06.724687 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
707 12:14:06.727767 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
708 12:14:06.730961 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
709 12:14:06.737962 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
710 12:14:06.740999 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
711 12:14:06.744627 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
712 12:14:06.751480 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
713 12:14:06.754907 ===================================
714 12:14:06.755340 LPDDR4 DRAM CONFIGURATION
715 12:14:06.758038 ===================================
716 12:14:06.761320 EX_ROW_EN[0] = 0x0
717 12:14:06.764783 EX_ROW_EN[1] = 0x0
718 12:14:06.765217 LP4Y_EN = 0x0
719 12:14:06.768065 WORK_FSP = 0x0
720 12:14:06.768552 WL = 0x2
721 12:14:06.771643 RL = 0x2
722 12:14:06.771950 BL = 0x2
723 12:14:06.774771 RPST = 0x0
724 12:14:06.775003 RD_PRE = 0x0
725 12:14:06.777811 WR_PRE = 0x1
726 12:14:06.778044 WR_PST = 0x0
727 12:14:06.781335 DBI_WR = 0x0
728 12:14:06.781521 DBI_RD = 0x0
729 12:14:06.784598 OTF = 0x1
730 12:14:06.787738 ===================================
731 12:14:06.791431 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
732 12:14:06.794527 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
733 12:14:06.798394 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
734 12:14:06.801456 ===================================
735 12:14:06.805084 LPDDR4 DRAM CONFIGURATION
736 12:14:06.807964 ===================================
737 12:14:06.811785 EX_ROW_EN[0] = 0x10
738 12:14:06.811943 EX_ROW_EN[1] = 0x0
739 12:14:06.814953 LP4Y_EN = 0x0
740 12:14:06.815110 WORK_FSP = 0x0
741 12:14:06.818373 WL = 0x2
742 12:14:06.818528 RL = 0x2
743 12:14:06.821387 BL = 0x2
744 12:14:06.821544 RPST = 0x0
745 12:14:06.824714 RD_PRE = 0x0
746 12:14:06.824870 WR_PRE = 0x1
747 12:14:06.828040 WR_PST = 0x0
748 12:14:06.828196 DBI_WR = 0x0
749 12:14:06.831332 DBI_RD = 0x0
750 12:14:06.834947 OTF = 0x1
751 12:14:06.835105 ===================================
752 12:14:06.841553 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
753 12:14:06.846404 nWR fixed to 40
754 12:14:06.849804 [ModeRegInit_LP4] CH0 RK0
755 12:14:06.849970 [ModeRegInit_LP4] CH0 RK1
756 12:14:06.853157 [ModeRegInit_LP4] CH1 RK0
757 12:14:06.856519 [ModeRegInit_LP4] CH1 RK1
758 12:14:06.856721 match AC timing 13
759 12:14:06.863321 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
760 12:14:06.866420 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
761 12:14:06.869612 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
762 12:14:06.876590 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
763 12:14:06.880309 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
764 12:14:06.880468 [EMI DOE] emi_dcm 0
765 12:14:06.886469 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
766 12:14:06.886627 ==
767 12:14:06.889740 Dram Type= 6, Freq= 0, CH_0, rank 0
768 12:14:06.893365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
769 12:14:06.893524 ==
770 12:14:06.900187 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
771 12:14:06.903467 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
772 12:14:06.914238 [CA 0] Center 36 (6~67) winsize 62
773 12:14:06.917414 [CA 1] Center 36 (6~67) winsize 62
774 12:14:06.920494 [CA 2] Center 34 (4~65) winsize 62
775 12:14:06.924141 [CA 3] Center 33 (3~64) winsize 62
776 12:14:06.927319 [CA 4] Center 33 (3~64) winsize 62
777 12:14:06.931043 [CA 5] Center 32 (3~62) winsize 60
778 12:14:06.931477
779 12:14:06.934340 [CmdBusTrainingLP45] Vref(ca) range 1: 34
780 12:14:06.934775
781 12:14:06.937403 [CATrainingPosCal] consider 1 rank data
782 12:14:06.940545 u2DelayCellTimex100 = 270/100 ps
783 12:14:06.943825 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
784 12:14:06.947178 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
785 12:14:06.953893 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
786 12:14:06.957289 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
787 12:14:06.961051 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
788 12:14:06.963956 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
789 12:14:06.964092
790 12:14:06.967121 CA PerBit enable=1, Macro0, CA PI delay=32
791 12:14:06.967256
792 12:14:06.970189 [CBTSetCACLKResult] CA Dly = 32
793 12:14:06.970312 CS Dly: 4 (0~35)
794 12:14:06.970408 ==
795 12:14:06.973602 Dram Type= 6, Freq= 0, CH_0, rank 1
796 12:14:06.980176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
797 12:14:06.980321 ==
798 12:14:06.983734 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
799 12:14:06.990145 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
800 12:14:07.000022 [CA 0] Center 36 (6~67) winsize 62
801 12:14:07.003060 [CA 1] Center 36 (6~67) winsize 62
802 12:14:07.006906 [CA 2] Center 34 (3~65) winsize 63
803 12:14:07.010141 [CA 3] Center 34 (3~65) winsize 63
804 12:14:07.013317 [CA 4] Center 33 (3~64) winsize 62
805 12:14:07.016920 [CA 5] Center 32 (2~63) winsize 62
806 12:14:07.017026
807 12:14:07.020084 [CmdBusTrainingLP45] Vref(ca) range 1: 34
808 12:14:07.020189
809 12:14:07.023595 [CATrainingPosCal] consider 2 rank data
810 12:14:07.027377 u2DelayCellTimex100 = 270/100 ps
811 12:14:07.030715 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
812 12:14:07.033628 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
813 12:14:07.036782 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
814 12:14:07.043635 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
815 12:14:07.047071 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
816 12:14:07.050116 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
817 12:14:07.050243
818 12:14:07.053749 CA PerBit enable=1, Macro0, CA PI delay=32
819 12:14:07.053879
820 12:14:07.056724 [CBTSetCACLKResult] CA Dly = 32
821 12:14:07.056851 CS Dly: 5 (0~37)
822 12:14:07.056974
823 12:14:07.060708 ----->DramcWriteLeveling(PI) begin...
824 12:14:07.060839 ==
825 12:14:07.064556 Dram Type= 6, Freq= 0, CH_0, rank 0
826 12:14:07.067545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
827 12:14:07.071310 ==
828 12:14:07.071437 Write leveling (Byte 0): 33 => 33
829 12:14:07.075122 Write leveling (Byte 1): 29 => 29
830 12:14:07.078127 DramcWriteLeveling(PI) end<-----
831 12:14:07.078266
832 12:14:07.078377 ==
833 12:14:07.081663 Dram Type= 6, Freq= 0, CH_0, rank 0
834 12:14:07.084819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
835 12:14:07.084977 ==
836 12:14:07.088182 [Gating] SW mode calibration
837 12:14:07.095741 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
838 12:14:07.102440 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
839 12:14:07.105907 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
840 12:14:07.109389 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
841 12:14:07.115529 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
842 12:14:07.119283 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 12:14:07.122208 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 12:14:07.129039 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 12:14:07.132795 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 12:14:07.135778 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 12:14:07.143041 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 12:14:07.146071 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 12:14:07.148988 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 12:14:07.155744 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 12:14:07.159316 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 12:14:07.162829 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 12:14:07.165731 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 12:14:07.172704 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 12:14:07.175976 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 12:14:07.179102 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
857 12:14:07.185931 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
858 12:14:07.189522 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
859 12:14:07.192691 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:14:07.199824 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:14:07.203131 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:14:07.206027 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:14:07.212816 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:14:07.215972 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:14:07.219317 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
866 12:14:07.226117 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
867 12:14:07.229592 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
868 12:14:07.232605 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
869 12:14:07.239274 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
870 12:14:07.242474 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
871 12:14:07.246023 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
872 12:14:07.249217 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
873 12:14:07.255984 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
874 12:14:07.259356 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
875 12:14:07.262991 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 12:14:07.269747 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 12:14:07.272447 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 12:14:07.276197 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 12:14:07.282686 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 12:14:07.285999 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
881 12:14:07.289129 0 11 8 | B1->B0 | 2828 4040 | 0 0 | (1 1) (0 0)
882 12:14:07.295780 0 11 12 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
883 12:14:07.299652 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 12:14:07.302811 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
885 12:14:07.309995 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 12:14:07.313219 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
887 12:14:07.316540 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
888 12:14:07.319594 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
889 12:14:07.326598 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
890 12:14:07.329514 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
891 12:14:07.333012 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 12:14:07.340023 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 12:14:07.343067 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 12:14:07.346518 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 12:14:07.353008 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 12:14:07.356408 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 12:14:07.360103 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 12:14:07.366351 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 12:14:07.369756 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 12:14:07.373273 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 12:14:07.379613 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 12:14:07.382944 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 12:14:07.386595 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 12:14:07.392829 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:14:07.396281 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
906 12:14:07.399634 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
907 12:14:07.402963 Total UI for P1: 0, mck2ui 16
908 12:14:07.406108 best dqsien dly found for B0: ( 0, 14, 8)
909 12:14:07.409917 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
910 12:14:07.413106 Total UI for P1: 0, mck2ui 16
911 12:14:07.416741 best dqsien dly found for B1: ( 0, 14, 10)
912 12:14:07.420346 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
913 12:14:07.423452 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
914 12:14:07.423538
915 12:14:07.430198 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
916 12:14:07.433819 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
917 12:14:07.433911 [Gating] SW calibration Done
918 12:14:07.436753 ==
919 12:14:07.436846 Dram Type= 6, Freq= 0, CH_0, rank 0
920 12:14:07.443726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 12:14:07.443912 ==
922 12:14:07.444011 RX Vref Scan: 0
923 12:14:07.444099
924 12:14:07.447193 RX Vref 0 -> 0, step: 1
925 12:14:07.447369
926 12:14:07.450343 RX Delay -130 -> 252, step: 16
927 12:14:07.454166 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
928 12:14:07.457052 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
929 12:14:07.460524 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
930 12:14:07.466944 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
931 12:14:07.470375 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
932 12:14:07.473941 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
933 12:14:07.476942 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
934 12:14:07.480785 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
935 12:14:07.487234 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
936 12:14:07.490804 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
937 12:14:07.494339 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
938 12:14:07.497301 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
939 12:14:07.500916 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
940 12:14:07.507579 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
941 12:14:07.511090 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
942 12:14:07.514382 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
943 12:14:07.515173 ==
944 12:14:07.517383 Dram Type= 6, Freq= 0, CH_0, rank 0
945 12:14:07.521307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
946 12:14:07.521906 ==
947 12:14:07.524448 DQS Delay:
948 12:14:07.524915 DQS0 = 0, DQS1 = 0
949 12:14:07.527346 DQM Delay:
950 12:14:07.527776 DQM0 = 88, DQM1 = 84
951 12:14:07.528118 DQ Delay:
952 12:14:07.531229 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
953 12:14:07.534387 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
954 12:14:07.537133 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
955 12:14:07.540794 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
956 12:14:07.541242
957 12:14:07.541651
958 12:14:07.541974 ==
959 12:14:07.544342 Dram Type= 6, Freq= 0, CH_0, rank 0
960 12:14:07.551209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 12:14:07.551806 ==
962 12:14:07.552261
963 12:14:07.552792
964 12:14:07.553117 TX Vref Scan disable
965 12:14:07.554714 == TX Byte 0 ==
966 12:14:07.558270 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
967 12:14:07.561106 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
968 12:14:07.565056 == TX Byte 1 ==
969 12:14:07.567801 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
970 12:14:07.571066 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
971 12:14:07.575292 ==
972 12:14:07.578019 Dram Type= 6, Freq= 0, CH_0, rank 0
973 12:14:07.581211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 12:14:07.581639 ==
975 12:14:07.593868 TX Vref=22, minBit 7, minWin=27, winSum=447
976 12:14:07.597643 TX Vref=24, minBit 10, minWin=27, winSum=449
977 12:14:07.600806 TX Vref=26, minBit 8, minWin=28, winSum=458
978 12:14:07.603928 TX Vref=28, minBit 8, minWin=28, winSum=457
979 12:14:07.607616 TX Vref=30, minBit 6, minWin=28, winSum=459
980 12:14:07.611181 TX Vref=32, minBit 5, minWin=28, winSum=455
981 12:14:07.617820 [TxChooseVref] Worse bit 6, Min win 28, Win sum 459, Final Vref 30
982 12:14:07.618256
983 12:14:07.621012 Final TX Range 1 Vref 30
984 12:14:07.621537
985 12:14:07.621881 ==
986 12:14:07.623896 Dram Type= 6, Freq= 0, CH_0, rank 0
987 12:14:07.627443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 12:14:07.628001 ==
989 12:14:07.628392
990 12:14:07.630961
991 12:14:07.631593 TX Vref Scan disable
992 12:14:07.633851 == TX Byte 0 ==
993 12:14:07.637399 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
994 12:14:07.641223 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
995 12:14:07.643995 == TX Byte 1 ==
996 12:14:07.647634 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
997 12:14:07.650752 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
998 12:14:07.654621
999 12:14:07.655046 [DATLAT]
1000 12:14:07.655447 Freq=800, CH0 RK0
1001 12:14:07.655771
1002 12:14:07.657448 DATLAT Default: 0xa
1003 12:14:07.657878 0, 0xFFFF, sum = 0
1004 12:14:07.661359 1, 0xFFFF, sum = 0
1005 12:14:07.661848 2, 0xFFFF, sum = 0
1006 12:14:07.664610 3, 0xFFFF, sum = 0
1007 12:14:07.665045 4, 0xFFFF, sum = 0
1008 12:14:07.667318 5, 0xFFFF, sum = 0
1009 12:14:07.667786 6, 0xFFFF, sum = 0
1010 12:14:07.670875 7, 0xFFFF, sum = 0
1011 12:14:07.671315 8, 0xFFFF, sum = 0
1012 12:14:07.674031 9, 0x0, sum = 1
1013 12:14:07.674469 10, 0x0, sum = 2
1014 12:14:07.678102 11, 0x0, sum = 3
1015 12:14:07.678634 12, 0x0, sum = 4
1016 12:14:07.681476 best_step = 10
1017 12:14:07.682002
1018 12:14:07.682349 ==
1019 12:14:07.684584 Dram Type= 6, Freq= 0, CH_0, rank 0
1020 12:14:07.687666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1021 12:14:07.688094 ==
1022 12:14:07.690609 RX Vref Scan: 1
1023 12:14:07.691037
1024 12:14:07.691379 Set Vref Range= 32 -> 127
1025 12:14:07.691797
1026 12:14:07.694099 RX Vref 32 -> 127, step: 1
1027 12:14:07.694521
1028 12:14:07.697801 RX Delay -79 -> 252, step: 8
1029 12:14:07.698223
1030 12:14:07.701033 Set Vref, RX VrefLevel [Byte0]: 32
1031 12:14:07.704440 [Byte1]: 32
1032 12:14:07.704959
1033 12:14:07.708064 Set Vref, RX VrefLevel [Byte0]: 33
1034 12:14:07.711095 [Byte1]: 33
1035 12:14:07.714389
1036 12:14:07.714908 Set Vref, RX VrefLevel [Byte0]: 34
1037 12:14:07.717626 [Byte1]: 34
1038 12:14:07.722241
1039 12:14:07.722764 Set Vref, RX VrefLevel [Byte0]: 35
1040 12:14:07.725267 [Byte1]: 35
1041 12:14:07.729594
1042 12:14:07.730016 Set Vref, RX VrefLevel [Byte0]: 36
1043 12:14:07.733263 [Byte1]: 36
1044 12:14:07.737346
1045 12:14:07.737792 Set Vref, RX VrefLevel [Byte0]: 37
1046 12:14:07.740614 [Byte1]: 37
1047 12:14:07.744834
1048 12:14:07.745257 Set Vref, RX VrefLevel [Byte0]: 38
1049 12:14:07.748455 [Byte1]: 38
1050 12:14:07.752322
1051 12:14:07.752762 Set Vref, RX VrefLevel [Byte0]: 39
1052 12:14:07.755681 [Byte1]: 39
1053 12:14:07.760559
1054 12:14:07.760982 Set Vref, RX VrefLevel [Byte0]: 40
1055 12:14:07.763738 [Byte1]: 40
1056 12:14:07.766680
1057 12:14:07.767130 Set Vref, RX VrefLevel [Byte0]: 41
1058 12:14:07.770430 [Byte1]: 41
1059 12:14:07.774510
1060 12:14:07.775082 Set Vref, RX VrefLevel [Byte0]: 42
1061 12:14:07.778057 [Byte1]: 42
1062 12:14:07.782539
1063 12:14:07.783029 Set Vref, RX VrefLevel [Byte0]: 43
1064 12:14:07.785582 [Byte1]: 43
1065 12:14:07.790190
1066 12:14:07.790613 Set Vref, RX VrefLevel [Byte0]: 44
1067 12:14:07.793508 [Byte1]: 44
1068 12:14:07.797325
1069 12:14:07.797793 Set Vref, RX VrefLevel [Byte0]: 45
1070 12:14:07.800895 [Byte1]: 45
1071 12:14:07.805146
1072 12:14:07.805669 Set Vref, RX VrefLevel [Byte0]: 46
1073 12:14:07.808131 [Byte1]: 46
1074 12:14:07.812066
1075 12:14:07.812538 Set Vref, RX VrefLevel [Byte0]: 47
1076 12:14:07.815982 [Byte1]: 47
1077 12:14:07.819826
1078 12:14:07.820270 Set Vref, RX VrefLevel [Byte0]: 48
1079 12:14:07.823405 [Byte1]: 48
1080 12:14:07.827378
1081 12:14:07.827799 Set Vref, RX VrefLevel [Byte0]: 49
1082 12:14:07.830800 [Byte1]: 49
1083 12:14:07.834885
1084 12:14:07.835310 Set Vref, RX VrefLevel [Byte0]: 50
1085 12:14:07.838025 [Byte1]: 50
1086 12:14:07.842776
1087 12:14:07.843201 Set Vref, RX VrefLevel [Byte0]: 51
1088 12:14:07.846155 [Byte1]: 51
1089 12:14:07.850523
1090 12:14:07.851056 Set Vref, RX VrefLevel [Byte0]: 52
1091 12:14:07.853466 [Byte1]: 52
1092 12:14:07.857840
1093 12:14:07.858263 Set Vref, RX VrefLevel [Byte0]: 53
1094 12:14:07.861462 [Byte1]: 53
1095 12:14:07.865326
1096 12:14:07.865746 Set Vref, RX VrefLevel [Byte0]: 54
1097 12:14:07.868242 [Byte1]: 54
1098 12:14:07.873129
1099 12:14:07.873554 Set Vref, RX VrefLevel [Byte0]: 55
1100 12:14:07.876434 [Byte1]: 55
1101 12:14:07.880071
1102 12:14:07.880457 Set Vref, RX VrefLevel [Byte0]: 56
1103 12:14:07.883582 [Byte1]: 56
1104 12:14:07.888461
1105 12:14:07.888982 Set Vref, RX VrefLevel [Byte0]: 57
1106 12:14:07.891013 [Byte1]: 57
1107 12:14:07.895438
1108 12:14:07.895958 Set Vref, RX VrefLevel [Byte0]: 58
1109 12:14:07.898760 [Byte1]: 58
1110 12:14:07.903207
1111 12:14:07.903631 Set Vref, RX VrefLevel [Byte0]: 59
1112 12:14:07.906391 [Byte1]: 59
1113 12:14:07.910809
1114 12:14:07.911233 Set Vref, RX VrefLevel [Byte0]: 60
1115 12:14:07.913779 [Byte1]: 60
1116 12:14:07.918524
1117 12:14:07.918942 Set Vref, RX VrefLevel [Byte0]: 61
1118 12:14:07.921504 [Byte1]: 61
1119 12:14:07.926326
1120 12:14:07.926839 Set Vref, RX VrefLevel [Byte0]: 62
1121 12:14:07.929086 [Byte1]: 62
1122 12:14:07.933160
1123 12:14:07.933708 Set Vref, RX VrefLevel [Byte0]: 63
1124 12:14:07.936829 [Byte1]: 63
1125 12:14:07.941233
1126 12:14:07.941750 Set Vref, RX VrefLevel [Byte0]: 64
1127 12:14:07.944410 [Byte1]: 64
1128 12:14:07.948751
1129 12:14:07.949317 Set Vref, RX VrefLevel [Byte0]: 65
1130 12:14:07.951791 [Byte1]: 65
1131 12:14:07.955804
1132 12:14:07.956269 Set Vref, RX VrefLevel [Byte0]: 66
1133 12:14:07.959133 [Byte1]: 66
1134 12:14:07.963347
1135 12:14:07.963764 Set Vref, RX VrefLevel [Byte0]: 67
1136 12:14:07.966522 [Byte1]: 67
1137 12:14:07.971310
1138 12:14:07.971998 Set Vref, RX VrefLevel [Byte0]: 68
1139 12:14:07.974052 [Byte1]: 68
1140 12:14:07.978745
1141 12:14:07.979307 Set Vref, RX VrefLevel [Byte0]: 69
1142 12:14:07.981802 [Byte1]: 69
1143 12:14:07.986471
1144 12:14:07.987073 Set Vref, RX VrefLevel [Byte0]: 70
1145 12:14:07.989281 [Byte1]: 70
1146 12:14:07.994207
1147 12:14:07.994780 Set Vref, RX VrefLevel [Byte0]: 71
1148 12:14:07.996864 [Byte1]: 71
1149 12:14:08.001109
1150 12:14:08.001585 Set Vref, RX VrefLevel [Byte0]: 72
1151 12:14:08.004349 [Byte1]: 72
1152 12:14:08.008741
1153 12:14:08.009305 Set Vref, RX VrefLevel [Byte0]: 73
1154 12:14:08.012337 [Byte1]: 73
1155 12:14:08.016372
1156 12:14:08.016948 Set Vref, RX VrefLevel [Byte0]: 74
1157 12:14:08.019389 [Byte1]: 74
1158 12:14:08.023854
1159 12:14:08.024512 Set Vref, RX VrefLevel [Byte0]: 75
1160 12:14:08.027382 [Byte1]: 75
1161 12:14:08.031849
1162 12:14:08.032505 Set Vref, RX VrefLevel [Byte0]: 76
1163 12:14:08.035291 [Byte1]: 76
1164 12:14:08.038702
1165 12:14:08.039178 Set Vref, RX VrefLevel [Byte0]: 77
1166 12:14:08.042419 [Byte1]: 77
1167 12:14:08.046683
1168 12:14:08.047262 Final RX Vref Byte 0 = 59 to rank0
1169 12:14:08.049666 Final RX Vref Byte 1 = 54 to rank0
1170 12:14:08.053623 Final RX Vref Byte 0 = 59 to rank1
1171 12:14:08.056486 Final RX Vref Byte 1 = 54 to rank1==
1172 12:14:08.059711 Dram Type= 6, Freq= 0, CH_0, rank 0
1173 12:14:08.066647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1174 12:14:08.067116 ==
1175 12:14:08.067481 DQS Delay:
1176 12:14:08.067928 DQS0 = 0, DQS1 = 0
1177 12:14:08.069672 DQM Delay:
1178 12:14:08.070136 DQM0 = 92, DQM1 = 84
1179 12:14:08.073308 DQ Delay:
1180 12:14:08.076332 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1181 12:14:08.079982 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1182 12:14:08.080549 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1183 12:14:08.087000 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92
1184 12:14:08.087524
1185 12:14:08.087858
1186 12:14:08.092996 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c43, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1187 12:14:08.097004 CH0 RK0: MR19=606, MR18=4C43
1188 12:14:08.103124 CH0_RK0: MR19=0x606, MR18=0x4C43, DQSOSC=390, MR23=63, INC=97, DEC=64
1189 12:14:08.103670
1190 12:14:08.106853 ----->DramcWriteLeveling(PI) begin...
1191 12:14:08.107397 ==
1192 12:14:08.109979 Dram Type= 6, Freq= 0, CH_0, rank 1
1193 12:14:08.113476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1194 12:14:08.113933 ==
1195 12:14:08.117073 Write leveling (Byte 0): 35 => 35
1196 12:14:08.120438 Write leveling (Byte 1): 30 => 30
1197 12:14:08.123450 DramcWriteLeveling(PI) end<-----
1198 12:14:08.123968
1199 12:14:08.124349 ==
1200 12:14:08.126588 Dram Type= 6, Freq= 0, CH_0, rank 1
1201 12:14:08.130208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1202 12:14:08.130647 ==
1203 12:14:08.133347 [Gating] SW mode calibration
1204 12:14:08.177819 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1205 12:14:08.178570 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1206 12:14:08.178969 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1207 12:14:08.179695 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1208 12:14:08.180079 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1209 12:14:08.180475 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 12:14:08.180808 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 12:14:08.181122 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 12:14:08.181434 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 12:14:08.191447 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 12:14:08.192523 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 12:14:08.192933 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 12:14:08.195368 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 12:14:08.198167 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 12:14:08.201562 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 12:14:08.208375 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 12:14:08.212092 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 12:14:08.215161 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 12:14:08.222013 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 12:14:08.225419 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1224 12:14:08.228724 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1225 12:14:08.235210 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1226 12:14:08.238418 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:14:08.242113 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:14:08.244855 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:14:08.252110 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:14:08.255014 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 12:14:08.259150 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:14:08.265255 0 9 8 | B1->B0 | 2c2c 2727 | 1 1 | (1 1) (1 1)
1233 12:14:08.268228 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 12:14:08.272240 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1235 12:14:08.278820 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 12:14:08.281973 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 12:14:08.285320 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 12:14:08.291891 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 12:14:08.295206 0 10 4 | B1->B0 | 3232 3333 | 0 0 | (0 0) (0 0)
1240 12:14:08.298392 0 10 8 | B1->B0 | 2626 2828 | 0 1 | (0 0) (1 1)
1241 12:14:08.305670 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 12:14:08.309237 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 12:14:08.313192 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 12:14:08.316615 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 12:14:08.320178 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 12:14:08.327681 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 12:14:08.330482 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1248 12:14:08.334613 0 11 8 | B1->B0 | 3d3d 3f3f | 0 1 | (0 0) (0 0)
1249 12:14:08.338283 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 12:14:08.344742 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 12:14:08.348619 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 12:14:08.351639 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 12:14:08.358337 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 12:14:08.361578 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 12:14:08.365110 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 12:14:08.368168 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1257 12:14:08.374602 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 12:14:08.378182 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 12:14:08.381238 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 12:14:08.388167 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 12:14:08.391379 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 12:14:08.395040 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 12:14:08.401624 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 12:14:08.405236 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 12:14:08.408152 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 12:14:08.414841 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 12:14:08.418207 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 12:14:08.421788 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 12:14:08.428909 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 12:14:08.431944 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 12:14:08.435248 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1272 12:14:08.441646 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1273 12:14:08.444688 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 12:14:08.448483 Total UI for P1: 0, mck2ui 16
1275 12:14:08.451550 best dqsien dly found for B0: ( 0, 14, 8)
1276 12:14:08.455092 Total UI for P1: 0, mck2ui 16
1277 12:14:08.458609 best dqsien dly found for B1: ( 0, 14, 6)
1278 12:14:08.461805 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1279 12:14:08.465000 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1280 12:14:08.465468
1281 12:14:08.468459 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1282 12:14:08.471865 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1283 12:14:08.474822 [Gating] SW calibration Done
1284 12:14:08.475502 ==
1285 12:14:08.478723 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 12:14:08.481709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 12:14:08.482182 ==
1288 12:14:08.484883 RX Vref Scan: 0
1289 12:14:08.485353
1290 12:14:08.485731 RX Vref 0 -> 0, step: 1
1291 12:14:08.486044
1292 12:14:08.488399 RX Delay -130 -> 252, step: 16
1293 12:14:08.494800 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1294 12:14:08.497996 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1295 12:14:08.502061 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1296 12:14:08.505070 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1297 12:14:08.508041 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1298 12:14:08.511954 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1299 12:14:08.518252 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1300 12:14:08.521698 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1301 12:14:08.525001 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1302 12:14:08.528577 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1303 12:14:08.531598 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1304 12:14:08.538492 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1305 12:14:08.541793 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1306 12:14:08.545305 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1307 12:14:08.549199 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1308 12:14:08.552438 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1309 12:14:08.555516 ==
1310 12:14:08.558347 Dram Type= 6, Freq= 0, CH_0, rank 1
1311 12:14:08.562038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1312 12:14:08.562551 ==
1313 12:14:08.562929 DQS Delay:
1314 12:14:08.565049 DQS0 = 0, DQS1 = 0
1315 12:14:08.565519 DQM Delay:
1316 12:14:08.568729 DQM0 = 91, DQM1 = 82
1317 12:14:08.569195 DQ Delay:
1318 12:14:08.572225 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1319 12:14:08.575256 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1320 12:14:08.578435 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1321 12:14:08.581615 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1322 12:14:08.582082
1323 12:14:08.582455
1324 12:14:08.582800 ==
1325 12:14:08.584971 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 12:14:08.588218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 12:14:08.588738 ==
1328 12:14:08.589111
1329 12:14:08.589454
1330 12:14:08.591430 TX Vref Scan disable
1331 12:14:08.594918 == TX Byte 0 ==
1332 12:14:08.598395 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1333 12:14:08.601741 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1334 12:14:08.604989 == TX Byte 1 ==
1335 12:14:08.608995 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1336 12:14:08.612273 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1337 12:14:08.612849 ==
1338 12:14:08.615244 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 12:14:08.618706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 12:14:08.621472 ==
1341 12:14:08.633671 TX Vref=22, minBit 10, minWin=27, winSum=450
1342 12:14:08.637305 TX Vref=24, minBit 13, minWin=27, winSum=451
1343 12:14:08.640616 TX Vref=26, minBit 1, minWin=28, winSum=457
1344 12:14:08.643908 TX Vref=28, minBit 6, minWin=28, winSum=458
1345 12:14:08.647238 TX Vref=30, minBit 6, minWin=28, winSum=457
1346 12:14:08.653507 TX Vref=32, minBit 1, minWin=28, winSum=455
1347 12:14:08.656724 [TxChooseVref] Worse bit 6, Min win 28, Win sum 458, Final Vref 28
1348 12:14:08.657192
1349 12:14:08.660064 Final TX Range 1 Vref 28
1350 12:14:08.660602
1351 12:14:08.660979 ==
1352 12:14:08.663175 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 12:14:08.666917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 12:14:08.667382 ==
1355 12:14:08.670104
1356 12:14:08.670523
1357 12:14:08.670853 TX Vref Scan disable
1358 12:14:08.673796 == TX Byte 0 ==
1359 12:14:08.676819 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1360 12:14:08.680246 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1361 12:14:08.683941 == TX Byte 1 ==
1362 12:14:08.686940 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1363 12:14:08.693291 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1364 12:14:08.693638
1365 12:14:08.694021 [DATLAT]
1366 12:14:08.694266 Freq=800, CH0 RK1
1367 12:14:08.694490
1368 12:14:08.697074 DATLAT Default: 0xa
1369 12:14:08.697374 0, 0xFFFF, sum = 0
1370 12:14:08.700469 1, 0xFFFF, sum = 0
1371 12:14:08.700785 2, 0xFFFF, sum = 0
1372 12:14:08.703879 3, 0xFFFF, sum = 0
1373 12:14:08.704439 4, 0xFFFF, sum = 0
1374 12:14:08.706819 5, 0xFFFF, sum = 0
1375 12:14:08.707210 6, 0xFFFF, sum = 0
1376 12:14:08.710337 7, 0xFFFF, sum = 0
1377 12:14:08.713821 8, 0xFFFF, sum = 0
1378 12:14:08.714210 9, 0x0, sum = 1
1379 12:14:08.714518 10, 0x0, sum = 2
1380 12:14:08.716918 11, 0x0, sum = 3
1381 12:14:08.717311 12, 0x0, sum = 4
1382 12:14:08.720612 best_step = 10
1383 12:14:08.720995
1384 12:14:08.721294 ==
1385 12:14:08.723897 Dram Type= 6, Freq= 0, CH_0, rank 1
1386 12:14:08.727006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1387 12:14:08.727499 ==
1388 12:14:08.730845 RX Vref Scan: 0
1389 12:14:08.731337
1390 12:14:08.731648 RX Vref 0 -> 0, step: 1
1391 12:14:08.731936
1392 12:14:08.733933 RX Delay -79 -> 252, step: 8
1393 12:14:08.740214 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1394 12:14:08.744028 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1395 12:14:08.747407 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1396 12:14:08.750402 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1397 12:14:08.753895 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1398 12:14:08.760349 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1399 12:14:08.764069 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1400 12:14:08.767393 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1401 12:14:08.770489 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1402 12:14:08.773933 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
1403 12:14:08.780400 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1404 12:14:08.783963 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1405 12:14:08.787608 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1406 12:14:08.790991 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1407 12:14:08.793749 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1408 12:14:08.800282 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1409 12:14:08.800708 ==
1410 12:14:08.803756 Dram Type= 6, Freq= 0, CH_0, rank 1
1411 12:14:08.807242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 12:14:08.807630 ==
1413 12:14:08.807934 DQS Delay:
1414 12:14:08.810560 DQS0 = 0, DQS1 = 0
1415 12:14:08.810982 DQM Delay:
1416 12:14:08.814162 DQM0 = 93, DQM1 = 84
1417 12:14:08.814672 DQ Delay:
1418 12:14:08.817448 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1419 12:14:08.821159 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1420 12:14:08.824187 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1421 12:14:08.827418 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =88
1422 12:14:08.827814
1423 12:14:08.828114
1424 12:14:08.834442 [DQSOSCAuto] RK1, (LSB)MR18= 0x4415, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1425 12:14:08.837773 CH0 RK1: MR19=606, MR18=4415
1426 12:14:08.844150 CH0_RK1: MR19=0x606, MR18=0x4415, DQSOSC=392, MR23=63, INC=96, DEC=64
1427 12:14:08.847110 [RxdqsGatingPostProcess] freq 800
1428 12:14:08.854216 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1429 12:14:08.854708 Pre-setting of DQS Precalculation
1430 12:14:08.860634 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1431 12:14:08.861139 ==
1432 12:14:08.864086 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 12:14:08.867505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 12:14:08.868006 ==
1435 12:14:08.874342 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1436 12:14:08.880938 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1437 12:14:08.889241 [CA 0] Center 36 (6~67) winsize 62
1438 12:14:08.892242 [CA 1] Center 36 (6~67) winsize 62
1439 12:14:08.895997 [CA 2] Center 35 (5~66) winsize 62
1440 12:14:08.898485 [CA 3] Center 34 (4~65) winsize 62
1441 12:14:08.901871 [CA 4] Center 35 (5~65) winsize 61
1442 12:14:08.905281 [CA 5] Center 34 (4~65) winsize 62
1443 12:14:08.905746
1444 12:14:08.909031 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1445 12:14:08.909501
1446 12:14:08.912276 [CATrainingPosCal] consider 1 rank data
1447 12:14:08.915736 u2DelayCellTimex100 = 270/100 ps
1448 12:14:08.918603 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1449 12:14:08.921906 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1450 12:14:08.928637 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1451 12:14:08.931804 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1452 12:14:08.935508 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1453 12:14:08.939169 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1454 12:14:08.939919
1455 12:14:08.942110 CA PerBit enable=1, Macro0, CA PI delay=34
1456 12:14:08.942582
1457 12:14:08.945280 [CBTSetCACLKResult] CA Dly = 34
1458 12:14:08.945750 CS Dly: 6 (0~37)
1459 12:14:08.946118 ==
1460 12:14:08.948713 Dram Type= 6, Freq= 0, CH_1, rank 1
1461 12:14:08.955643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1462 12:14:08.956181 ==
1463 12:14:08.958530 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1464 12:14:08.965643 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1465 12:14:08.975241 [CA 0] Center 36 (6~67) winsize 62
1466 12:14:08.979072 [CA 1] Center 36 (6~67) winsize 62
1467 12:14:08.983485 [CA 2] Center 35 (4~66) winsize 63
1468 12:14:08.986705 [CA 3] Center 34 (4~65) winsize 62
1469 12:14:08.990473 [CA 4] Center 35 (5~66) winsize 62
1470 12:14:08.991021 [CA 5] Center 34 (4~65) winsize 62
1471 12:14:08.991394
1472 12:14:08.997726 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1473 12:14:08.998235
1474 12:14:09.001486 [CATrainingPosCal] consider 2 rank data
1475 12:14:09.001956 u2DelayCellTimex100 = 270/100 ps
1476 12:14:09.005489 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1477 12:14:09.008940 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1478 12:14:09.011849 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1479 12:14:09.015776 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1480 12:14:09.022352 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1481 12:14:09.025915 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1482 12:14:09.026478
1483 12:14:09.029299 CA PerBit enable=1, Macro0, CA PI delay=34
1484 12:14:09.029872
1485 12:14:09.032404 [CBTSetCACLKResult] CA Dly = 34
1486 12:14:09.032875 CS Dly: 6 (0~38)
1487 12:14:09.033249
1488 12:14:09.035808 ----->DramcWriteLeveling(PI) begin...
1489 12:14:09.036432 ==
1490 12:14:09.038626 Dram Type= 6, Freq= 0, CH_1, rank 0
1491 12:14:09.045605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1492 12:14:09.046183 ==
1493 12:14:09.049084 Write leveling (Byte 0): 28 => 28
1494 12:14:09.049572 Write leveling (Byte 1): 28 => 28
1495 12:14:09.052365 DramcWriteLeveling(PI) end<-----
1496 12:14:09.052948
1497 12:14:09.053321 ==
1498 12:14:09.055768 Dram Type= 6, Freq= 0, CH_1, rank 0
1499 12:14:09.062047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1500 12:14:09.062614 ==
1501 12:14:09.065771 [Gating] SW mode calibration
1502 12:14:09.072439 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1503 12:14:09.075623 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1504 12:14:09.082637 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1505 12:14:09.086063 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1506 12:14:09.089191 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 12:14:09.092555 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 12:14:09.099259 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 12:14:09.102739 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 12:14:09.105830 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 12:14:09.112923 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 12:14:09.115942 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 12:14:09.119214 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 12:14:09.125762 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 12:14:09.128985 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 12:14:09.132866 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 12:14:09.139954 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 12:14:09.143061 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 12:14:09.145852 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 12:14:09.149902 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1521 12:14:09.156270 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1522 12:14:09.159607 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 12:14:09.162388 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 12:14:09.169480 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 12:14:09.172832 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 12:14:09.176273 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 12:14:09.183357 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 12:14:09.186329 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 12:14:09.189259 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1530 12:14:09.196221 0 9 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1531 12:14:09.199457 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1532 12:14:09.202811 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 12:14:09.209228 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 12:14:09.212940 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 12:14:09.216306 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 12:14:09.223142 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1537 12:14:09.226490 0 10 4 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 0)
1538 12:14:09.229451 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
1539 12:14:09.232689 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 12:14:09.240348 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 12:14:09.242967 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 12:14:09.246201 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 12:14:09.253209 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 12:14:09.256372 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 12:14:09.259691 0 11 4 | B1->B0 | 2a2a 3434 | 0 0 | (0 0) (0 0)
1546 12:14:09.266345 0 11 8 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
1547 12:14:09.269471 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 12:14:09.272962 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 12:14:09.279835 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 12:14:09.283065 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 12:14:09.286453 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 12:14:09.293447 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1553 12:14:09.296496 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1554 12:14:09.299837 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 12:14:09.306127 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 12:14:09.309869 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 12:14:09.313149 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 12:14:09.316558 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 12:14:09.323677 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 12:14:09.326860 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 12:14:09.330156 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 12:14:09.336562 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 12:14:09.340264 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 12:14:09.343738 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 12:14:09.350005 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 12:14:09.353240 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 12:14:09.356709 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 12:14:09.363690 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 12:14:09.366665 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1570 12:14:09.369812 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1571 12:14:09.373188 Total UI for P1: 0, mck2ui 16
1572 12:14:09.376909 best dqsien dly found for B1: ( 0, 14, 4)
1573 12:14:09.380009 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 12:14:09.383373 Total UI for P1: 0, mck2ui 16
1575 12:14:09.386523 best dqsien dly found for B0: ( 0, 14, 8)
1576 12:14:09.391555 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1577 12:14:09.396599 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1578 12:14:09.397031
1579 12:14:09.399866 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1580 12:14:09.403580 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1581 12:14:09.407071 [Gating] SW calibration Done
1582 12:14:09.407504 ==
1583 12:14:09.409810 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 12:14:09.413042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 12:14:09.413477 ==
1586 12:14:09.413818 RX Vref Scan: 0
1587 12:14:09.414134
1588 12:14:09.417038 RX Vref 0 -> 0, step: 1
1589 12:14:09.417468
1590 12:14:09.420086 RX Delay -130 -> 252, step: 16
1591 12:14:09.423355 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1592 12:14:09.426472 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1593 12:14:09.433435 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1594 12:14:09.436568 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1595 12:14:09.440114 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1596 12:14:09.443611 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1597 12:14:09.446657 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1598 12:14:09.450302 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1599 12:14:09.457318 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1600 12:14:09.459983 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1601 12:14:09.463383 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1602 12:14:09.466735 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1603 12:14:09.470403 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1604 12:14:09.477324 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1605 12:14:09.480398 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1606 12:14:09.483530 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1607 12:14:09.483974 ==
1608 12:14:09.486877 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 12:14:09.490430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 12:14:09.490859 ==
1611 12:14:09.493483 DQS Delay:
1612 12:14:09.494082 DQS0 = 0, DQS1 = 0
1613 12:14:09.497168 DQM Delay:
1614 12:14:09.497593 DQM0 = 92, DQM1 = 87
1615 12:14:09.497929 DQ Delay:
1616 12:14:09.500199 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1617 12:14:09.503457 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1618 12:14:09.506791 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1619 12:14:09.510585 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1620 12:14:09.511007
1621 12:14:09.511342
1622 12:14:09.513668 ==
1623 12:14:09.516880 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 12:14:09.520486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 12:14:09.520909 ==
1626 12:14:09.521244
1627 12:14:09.521553
1628 12:14:09.523805 TX Vref Scan disable
1629 12:14:09.524227 == TX Byte 0 ==
1630 12:14:09.527064 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1631 12:14:09.533762 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1632 12:14:09.534196 == TX Byte 1 ==
1633 12:14:09.536993 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1634 12:14:09.543846 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1635 12:14:09.544269 ==
1636 12:14:09.547131 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 12:14:09.550290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 12:14:09.550710 ==
1639 12:14:09.563141 TX Vref=22, minBit 1, minWin=26, winSum=438
1640 12:14:09.566871 TX Vref=24, minBit 3, minWin=26, winSum=442
1641 12:14:09.569699 TX Vref=26, minBit 3, minWin=26, winSum=445
1642 12:14:09.573289 TX Vref=28, minBit 1, minWin=27, winSum=451
1643 12:14:09.577073 TX Vref=30, minBit 1, minWin=27, winSum=450
1644 12:14:09.580155 TX Vref=32, minBit 0, minWin=27, winSum=448
1645 12:14:09.586657 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 28
1646 12:14:09.587231
1647 12:14:09.589732 Final TX Range 1 Vref 28
1648 12:14:09.590159
1649 12:14:09.590493 ==
1650 12:14:09.593146 Dram Type= 6, Freq= 0, CH_1, rank 0
1651 12:14:09.596890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1652 12:14:09.597314 ==
1653 12:14:09.597647
1654 12:14:09.597951
1655 12:14:09.600007 TX Vref Scan disable
1656 12:14:09.603466 == TX Byte 0 ==
1657 12:14:09.606600 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1658 12:14:09.610346 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1659 12:14:09.613378 == TX Byte 1 ==
1660 12:14:09.616835 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1661 12:14:09.619893 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1662 12:14:09.620343
1663 12:14:09.623188 [DATLAT]
1664 12:14:09.623666 Freq=800, CH1 RK0
1665 12:14:09.624101
1666 12:14:09.626890 DATLAT Default: 0xa
1667 12:14:09.627401 0, 0xFFFF, sum = 0
1668 12:14:09.629818 1, 0xFFFF, sum = 0
1669 12:14:09.630313 2, 0xFFFF, sum = 0
1670 12:14:09.633596 3, 0xFFFF, sum = 0
1671 12:14:09.634024 4, 0xFFFF, sum = 0
1672 12:14:09.636628 5, 0xFFFF, sum = 0
1673 12:14:09.637057 6, 0xFFFF, sum = 0
1674 12:14:09.640477 7, 0xFFFF, sum = 0
1675 12:14:09.640905 8, 0xFFFF, sum = 0
1676 12:14:09.643594 9, 0x0, sum = 1
1677 12:14:09.644024 10, 0x0, sum = 2
1678 12:14:09.646662 11, 0x0, sum = 3
1679 12:14:09.647090 12, 0x0, sum = 4
1680 12:14:09.650334 best_step = 10
1681 12:14:09.650756
1682 12:14:09.651091 ==
1683 12:14:09.653541 Dram Type= 6, Freq= 0, CH_1, rank 0
1684 12:14:09.656566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1685 12:14:09.656989 ==
1686 12:14:09.660418 RX Vref Scan: 1
1687 12:14:09.660841
1688 12:14:09.661174 Set Vref Range= 32 -> 127
1689 12:14:09.661490
1690 12:14:09.663622 RX Vref 32 -> 127, step: 1
1691 12:14:09.664044
1692 12:14:09.666880 RX Delay -79 -> 252, step: 8
1693 12:14:09.667302
1694 12:14:09.670026 Set Vref, RX VrefLevel [Byte0]: 32
1695 12:14:09.673380 [Byte1]: 32
1696 12:14:09.673804
1697 12:14:09.676750 Set Vref, RX VrefLevel [Byte0]: 33
1698 12:14:09.679983 [Byte1]: 33
1699 12:14:09.683450
1700 12:14:09.683882 Set Vref, RX VrefLevel [Byte0]: 34
1701 12:14:09.686676 [Byte1]: 34
1702 12:14:09.690689
1703 12:14:09.691076 Set Vref, RX VrefLevel [Byte0]: 35
1704 12:14:09.694026 [Byte1]: 35
1705 12:14:09.698495
1706 12:14:09.698916 Set Vref, RX VrefLevel [Byte0]: 36
1707 12:14:09.701579 [Byte1]: 36
1708 12:14:09.706148
1709 12:14:09.706567 Set Vref, RX VrefLevel [Byte0]: 37
1710 12:14:09.709218 [Byte1]: 37
1711 12:14:09.713527
1712 12:14:09.713947 Set Vref, RX VrefLevel [Byte0]: 38
1713 12:14:09.717012 [Byte1]: 38
1714 12:14:09.721157
1715 12:14:09.721578 Set Vref, RX VrefLevel [Byte0]: 39
1716 12:14:09.724379 [Byte1]: 39
1717 12:14:09.728590
1718 12:14:09.729012 Set Vref, RX VrefLevel [Byte0]: 40
1719 12:14:09.731975 [Byte1]: 40
1720 12:14:09.736389
1721 12:14:09.736808 Set Vref, RX VrefLevel [Byte0]: 41
1722 12:14:09.739412 [Byte1]: 41
1723 12:14:09.743385
1724 12:14:09.743807 Set Vref, RX VrefLevel [Byte0]: 42
1725 12:14:09.746960 [Byte1]: 42
1726 12:14:09.751348
1727 12:14:09.751767 Set Vref, RX VrefLevel [Byte0]: 43
1728 12:14:09.754765 [Byte1]: 43
1729 12:14:09.758924
1730 12:14:09.759357 Set Vref, RX VrefLevel [Byte0]: 44
1731 12:14:09.762151 [Byte1]: 44
1732 12:14:09.766599
1733 12:14:09.767020 Set Vref, RX VrefLevel [Byte0]: 45
1734 12:14:09.769657 [Byte1]: 45
1735 12:14:09.774030
1736 12:14:09.774452 Set Vref, RX VrefLevel [Byte0]: 46
1737 12:14:09.777081 [Byte1]: 46
1738 12:14:09.781158
1739 12:14:09.781605 Set Vref, RX VrefLevel [Byte0]: 47
1740 12:14:09.784651 [Byte1]: 47
1741 12:14:09.789168
1742 12:14:09.789600 Set Vref, RX VrefLevel [Byte0]: 48
1743 12:14:09.792386 [Byte1]: 48
1744 12:14:09.796736
1745 12:14:09.797158 Set Vref, RX VrefLevel [Byte0]: 49
1746 12:14:09.799722 [Byte1]: 49
1747 12:14:09.803932
1748 12:14:09.804400 Set Vref, RX VrefLevel [Byte0]: 50
1749 12:14:09.807360 [Byte1]: 50
1750 12:14:09.811806
1751 12:14:09.812225 Set Vref, RX VrefLevel [Byte0]: 51
1752 12:14:09.814839 [Byte1]: 51
1753 12:14:09.819353
1754 12:14:09.819773 Set Vref, RX VrefLevel [Byte0]: 52
1755 12:14:09.822314 [Byte1]: 52
1756 12:14:09.826454
1757 12:14:09.826877 Set Vref, RX VrefLevel [Byte0]: 53
1758 12:14:09.830215 [Byte1]: 53
1759 12:14:09.834016
1760 12:14:09.834436 Set Vref, RX VrefLevel [Byte0]: 54
1761 12:14:09.837954 [Byte1]: 54
1762 12:14:09.842042
1763 12:14:09.842459 Set Vref, RX VrefLevel [Byte0]: 55
1764 12:14:09.845295 [Byte1]: 55
1765 12:14:09.849685
1766 12:14:09.850105 Set Vref, RX VrefLevel [Byte0]: 56
1767 12:14:09.852900 [Byte1]: 56
1768 12:14:09.856822
1769 12:14:09.857243 Set Vref, RX VrefLevel [Byte0]: 57
1770 12:14:09.860752 [Byte1]: 57
1771 12:14:09.864870
1772 12:14:09.865286 Set Vref, RX VrefLevel [Byte0]: 58
1773 12:14:09.867849 [Byte1]: 58
1774 12:14:09.872086
1775 12:14:09.872562 Set Vref, RX VrefLevel [Byte0]: 59
1776 12:14:09.875202 [Byte1]: 59
1777 12:14:09.879469
1778 12:14:09.879890 Set Vref, RX VrefLevel [Byte0]: 60
1779 12:14:09.883099 [Byte1]: 60
1780 12:14:09.886881
1781 12:14:09.887300 Set Vref, RX VrefLevel [Byte0]: 61
1782 12:14:09.890495 [Byte1]: 61
1783 12:14:09.894692
1784 12:14:09.895153 Set Vref, RX VrefLevel [Byte0]: 62
1785 12:14:09.898093 [Byte1]: 62
1786 12:14:09.902617
1787 12:14:09.903043 Set Vref, RX VrefLevel [Byte0]: 63
1788 12:14:09.905496 [Byte1]: 63
1789 12:14:09.909966
1790 12:14:09.910386 Set Vref, RX VrefLevel [Byte0]: 64
1791 12:14:09.913029 [Byte1]: 64
1792 12:14:09.917262
1793 12:14:09.917683 Set Vref, RX VrefLevel [Byte0]: 65
1794 12:14:09.920911 [Byte1]: 65
1795 12:14:09.925319
1796 12:14:09.925740 Set Vref, RX VrefLevel [Byte0]: 66
1797 12:14:09.928386 [Byte1]: 66
1798 12:14:09.932537
1799 12:14:09.932999 Set Vref, RX VrefLevel [Byte0]: 67
1800 12:14:09.935510 [Byte1]: 67
1801 12:14:09.939903
1802 12:14:09.940374 Set Vref, RX VrefLevel [Byte0]: 68
1803 12:14:09.943334 [Byte1]: 68
1804 12:14:09.947229
1805 12:14:09.947667 Set Vref, RX VrefLevel [Byte0]: 69
1806 12:14:09.951148 [Byte1]: 69
1807 12:14:09.955065
1808 12:14:09.955491 Set Vref, RX VrefLevel [Byte0]: 70
1809 12:14:09.958764 [Byte1]: 70
1810 12:14:09.962596
1811 12:14:09.963024 Set Vref, RX VrefLevel [Byte0]: 71
1812 12:14:09.965770 [Byte1]: 71
1813 12:14:09.970015
1814 12:14:09.970494 Set Vref, RX VrefLevel [Byte0]: 72
1815 12:14:09.973438 [Byte1]: 72
1816 12:14:09.977746
1817 12:14:09.978174 Final RX Vref Byte 0 = 57 to rank0
1818 12:14:09.980952 Final RX Vref Byte 1 = 59 to rank0
1819 12:14:09.984604 Final RX Vref Byte 0 = 57 to rank1
1820 12:14:09.987582 Final RX Vref Byte 1 = 59 to rank1==
1821 12:14:09.991332 Dram Type= 6, Freq= 0, CH_1, rank 0
1822 12:14:09.994362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1823 12:14:09.998009 ==
1824 12:14:09.998437 DQS Delay:
1825 12:14:09.998770 DQS0 = 0, DQS1 = 0
1826 12:14:10.001242 DQM Delay:
1827 12:14:10.001738 DQM0 = 95, DQM1 = 90
1828 12:14:10.004397 DQ Delay:
1829 12:14:10.004821 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1830 12:14:10.007689 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1831 12:14:10.011200 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1832 12:14:10.014565 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1833 12:14:10.018352
1834 12:14:10.018775
1835 12:14:10.024431 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c49, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1836 12:14:10.028132 CH1 RK0: MR19=606, MR18=2C49
1837 12:14:10.034584 CH1_RK0: MR19=0x606, MR18=0x2C49, DQSOSC=391, MR23=63, INC=96, DEC=64
1838 12:14:10.035019
1839 12:14:10.037940 ----->DramcWriteLeveling(PI) begin...
1840 12:14:10.038373 ==
1841 12:14:10.041524 Dram Type= 6, Freq= 0, CH_1, rank 1
1842 12:14:10.045028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1843 12:14:10.045511 ==
1844 12:14:10.048251 Write leveling (Byte 0): 27 => 27
1845 12:14:10.051582 Write leveling (Byte 1): 30 => 30
1846 12:14:10.055203 DramcWriteLeveling(PI) end<-----
1847 12:14:10.055630
1848 12:14:10.055970 ==
1849 12:14:10.058178 Dram Type= 6, Freq= 0, CH_1, rank 1
1850 12:14:10.061368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1851 12:14:10.061800 ==
1852 12:14:10.065069 [Gating] SW mode calibration
1853 12:14:10.071451 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1854 12:14:10.078307 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1855 12:14:10.081959 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1856 12:14:10.085124 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1857 12:14:10.091360 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 12:14:10.095016 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 12:14:10.098221 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 12:14:10.101836 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 12:14:10.108191 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 12:14:10.111387 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 12:14:10.115226 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 12:14:10.121416 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 12:14:10.124971 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 12:14:10.128280 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 12:14:10.134929 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 12:14:10.138386 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 12:14:10.141635 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 12:14:10.148861 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 12:14:10.151992 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1872 12:14:10.154885 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1873 12:14:10.161689 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 12:14:10.164798 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 12:14:10.168595 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 12:14:10.174783 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 12:14:10.178522 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 12:14:10.181579 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 12:14:10.188776 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 12:14:10.191944 0 9 4 | B1->B0 | 2828 2323 | 0 1 | (0 0) (0 0)
1881 12:14:10.194852 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1882 12:14:10.197790 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1883 12:14:10.205051 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1884 12:14:10.208401 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1885 12:14:10.211354 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1886 12:14:10.218450 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1887 12:14:10.221397 0 10 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1888 12:14:10.224592 0 10 4 | B1->B0 | 2828 3131 | 0 0 | (1 0) (0 1)
1889 12:14:10.231315 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1890 12:14:10.235152 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 12:14:10.238298 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 12:14:10.244877 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 12:14:10.248195 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 12:14:10.251782 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 12:14:10.257901 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 12:14:10.261752 0 11 4 | B1->B0 | 4141 2e2e | 0 0 | (1 1) (0 0)
1897 12:14:10.264931 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1898 12:14:10.271490 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1899 12:14:10.275193 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1900 12:14:10.278457 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1901 12:14:10.281468 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 12:14:10.288002 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 12:14:10.291256 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1904 12:14:10.294837 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1905 12:14:10.301682 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 12:14:10.304745 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 12:14:10.308343 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 12:14:10.314497 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 12:14:10.317954 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 12:14:10.321392 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 12:14:10.328764 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 12:14:10.331842 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 12:14:10.334622 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 12:14:10.341359 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 12:14:10.345253 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 12:14:10.348434 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 12:14:10.354698 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 12:14:10.358434 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 12:14:10.361563 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 12:14:10.364617 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1921 12:14:10.371322 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 12:14:10.375211 Total UI for P1: 0, mck2ui 16
1923 12:14:10.378395 best dqsien dly found for B0: ( 0, 14, 4)
1924 12:14:10.381641 Total UI for P1: 0, mck2ui 16
1925 12:14:10.384788 best dqsien dly found for B1: ( 0, 14, 4)
1926 12:14:10.388533 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1927 12:14:10.391656 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1928 12:14:10.391731
1929 12:14:10.395326 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1930 12:14:10.398277 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1931 12:14:10.401939 [Gating] SW calibration Done
1932 12:14:10.402039 ==
1933 12:14:10.405115 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 12:14:10.408295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 12:14:10.408402 ==
1936 12:14:10.411512 RX Vref Scan: 0
1937 12:14:10.411611
1938 12:14:10.411700 RX Vref 0 -> 0, step: 1
1939 12:14:10.411790
1940 12:14:10.415044 RX Delay -130 -> 252, step: 16
1941 12:14:10.418633 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1942 12:14:10.425298 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1943 12:14:10.428554 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1944 12:14:10.431653 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1945 12:14:10.434870 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1946 12:14:10.438349 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1947 12:14:10.445048 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1948 12:14:10.448478 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1949 12:14:10.451877 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1950 12:14:10.454926 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1951 12:14:10.458350 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1952 12:14:10.465123 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1953 12:14:10.468762 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1954 12:14:10.471952 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1955 12:14:10.474825 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1956 12:14:10.478608 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1957 12:14:10.481889 ==
1958 12:14:10.481989 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 12:14:10.488142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 12:14:10.488245 ==
1961 12:14:10.488374 DQS Delay:
1962 12:14:10.491440 DQS0 = 0, DQS1 = 0
1963 12:14:10.491533 DQM Delay:
1964 12:14:10.495176 DQM0 = 93, DQM1 = 88
1965 12:14:10.495271 DQ Delay:
1966 12:14:10.498172 DQ0 =101, DQ1 =93, DQ2 =77, DQ3 =85
1967 12:14:10.502053 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1968 12:14:10.505215 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1969 12:14:10.508125 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1970 12:14:10.508220
1971 12:14:10.508349
1972 12:14:10.508437 ==
1973 12:14:10.511892 Dram Type= 6, Freq= 0, CH_1, rank 1
1974 12:14:10.514947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1975 12:14:10.515045 ==
1976 12:14:10.515137
1977 12:14:10.515222
1978 12:14:10.518237 TX Vref Scan disable
1979 12:14:10.521629 == TX Byte 0 ==
1980 12:14:10.525112 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1981 12:14:10.528655 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1982 12:14:10.531636 == TX Byte 1 ==
1983 12:14:10.535512 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1984 12:14:10.538215 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1985 12:14:10.538312 ==
1986 12:14:10.541863 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 12:14:10.545005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 12:14:10.548174 ==
1989 12:14:10.559921 TX Vref=22, minBit 1, minWin=26, winSum=442
1990 12:14:10.563139 TX Vref=24, minBit 1, minWin=27, winSum=447
1991 12:14:10.566427 TX Vref=26, minBit 2, minWin=27, winSum=449
1992 12:14:10.569626 TX Vref=28, minBit 2, minWin=27, winSum=450
1993 12:14:10.573514 TX Vref=30, minBit 2, minWin=27, winSum=450
1994 12:14:10.576247 TX Vref=32, minBit 2, minWin=27, winSum=450
1995 12:14:10.583229 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 28
1996 12:14:10.583330
1997 12:14:10.586489 Final TX Range 1 Vref 28
1998 12:14:10.586592
1999 12:14:10.586681 ==
2000 12:14:10.589983 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 12:14:10.593090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 12:14:10.593164 ==
2003 12:14:10.593241
2004 12:14:10.593301
2005 12:14:10.596734 TX Vref Scan disable
2006 12:14:10.599958 == TX Byte 0 ==
2007 12:14:10.603847 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2008 12:14:10.606410 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2009 12:14:10.609955 == TX Byte 1 ==
2010 12:14:10.613611 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2011 12:14:10.616645 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2012 12:14:10.616733
2013 12:14:10.619752 [DATLAT]
2014 12:14:10.619854 Freq=800, CH1 RK1
2015 12:14:10.619947
2016 12:14:10.623455 DATLAT Default: 0xa
2017 12:14:10.623558 0, 0xFFFF, sum = 0
2018 12:14:10.626782 1, 0xFFFF, sum = 0
2019 12:14:10.626880 2, 0xFFFF, sum = 0
2020 12:14:10.630349 3, 0xFFFF, sum = 0
2021 12:14:10.630458 4, 0xFFFF, sum = 0
2022 12:14:10.633270 5, 0xFFFF, sum = 0
2023 12:14:10.633370 6, 0xFFFF, sum = 0
2024 12:14:10.636720 7, 0xFFFF, sum = 0
2025 12:14:10.636791 8, 0xFFFF, sum = 0
2026 12:14:10.639950 9, 0x0, sum = 1
2027 12:14:10.640055 10, 0x0, sum = 2
2028 12:14:10.643326 11, 0x0, sum = 3
2029 12:14:10.643426 12, 0x0, sum = 4
2030 12:14:10.646567 best_step = 10
2031 12:14:10.646635
2032 12:14:10.646695 ==
2033 12:14:10.650467 Dram Type= 6, Freq= 0, CH_1, rank 1
2034 12:14:10.653705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2035 12:14:10.653780 ==
2036 12:14:10.656650 RX Vref Scan: 0
2037 12:14:10.656719
2038 12:14:10.656778 RX Vref 0 -> 0, step: 1
2039 12:14:10.656835
2040 12:14:10.660397 RX Delay -79 -> 252, step: 8
2041 12:14:10.666684 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2042 12:14:10.670341 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2043 12:14:10.673380 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2044 12:14:10.677050 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2045 12:14:10.680209 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2046 12:14:10.683659 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2047 12:14:10.689998 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2048 12:14:10.693324 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2049 12:14:10.697193 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2050 12:14:10.700065 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2051 12:14:10.703714 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
2052 12:14:10.706742 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2053 12:14:10.713339 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2054 12:14:10.716613 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2055 12:14:10.720314 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2056 12:14:10.723474 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2057 12:14:10.723579 ==
2058 12:14:10.726587 Dram Type= 6, Freq= 0, CH_1, rank 1
2059 12:14:10.733502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2060 12:14:10.733612 ==
2061 12:14:10.733706 DQS Delay:
2062 12:14:10.736614 DQS0 = 0, DQS1 = 0
2063 12:14:10.736687 DQM Delay:
2064 12:14:10.736748 DQM0 = 97, DQM1 = 90
2065 12:14:10.740074 DQ Delay:
2066 12:14:10.743186 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2067 12:14:10.746758 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2068 12:14:10.750097 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =88
2069 12:14:10.753589 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2070 12:14:10.753669
2071 12:14:10.753746
2072 12:14:10.760111 [DQSOSCAuto] RK1, (LSB)MR18= 0x4711, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2073 12:14:10.763339 CH1 RK1: MR19=606, MR18=4711
2074 12:14:10.770229 CH1_RK1: MR19=0x606, MR18=0x4711, DQSOSC=392, MR23=63, INC=96, DEC=64
2075 12:14:10.773395 [RxdqsGatingPostProcess] freq 800
2076 12:14:10.776916 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2077 12:14:10.780428 Pre-setting of DQS Precalculation
2078 12:14:10.787130 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2079 12:14:10.793873 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2080 12:14:10.800048 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2081 12:14:10.800132
2082 12:14:10.800224
2083 12:14:10.803890 [Calibration Summary] 1600 Mbps
2084 12:14:10.803962 CH 0, Rank 0
2085 12:14:10.806944 SW Impedance : PASS
2086 12:14:10.810083 DUTY Scan : NO K
2087 12:14:10.810156 ZQ Calibration : PASS
2088 12:14:10.813621 Jitter Meter : NO K
2089 12:14:10.817060 CBT Training : PASS
2090 12:14:10.817130 Write leveling : PASS
2091 12:14:10.820445 RX DQS gating : PASS
2092 12:14:10.823503 RX DQ/DQS(RDDQC) : PASS
2093 12:14:10.823593 TX DQ/DQS : PASS
2094 12:14:10.826866 RX DATLAT : PASS
2095 12:14:10.826939 RX DQ/DQS(Engine): PASS
2096 12:14:10.830368 TX OE : NO K
2097 12:14:10.830438 All Pass.
2098 12:14:10.830498
2099 12:14:10.833703 CH 0, Rank 1
2100 12:14:10.833785 SW Impedance : PASS
2101 12:14:10.837155 DUTY Scan : NO K
2102 12:14:10.840125 ZQ Calibration : PASS
2103 12:14:10.840207 Jitter Meter : NO K
2104 12:14:10.843708 CBT Training : PASS
2105 12:14:10.847424 Write leveling : PASS
2106 12:14:10.847506 RX DQS gating : PASS
2107 12:14:10.850622 RX DQ/DQS(RDDQC) : PASS
2108 12:14:10.854301 TX DQ/DQS : PASS
2109 12:14:10.854384 RX DATLAT : PASS
2110 12:14:10.857425 RX DQ/DQS(Engine): PASS
2111 12:14:10.857507 TX OE : NO K
2112 12:14:10.860944 All Pass.
2113 12:14:10.861039
2114 12:14:10.861106 CH 1, Rank 0
2115 12:14:10.864033 SW Impedance : PASS
2116 12:14:10.864115 DUTY Scan : NO K
2117 12:14:10.867082 ZQ Calibration : PASS
2118 12:14:10.870275 Jitter Meter : NO K
2119 12:14:10.870358 CBT Training : PASS
2120 12:14:10.873965 Write leveling : PASS
2121 12:14:10.877101 RX DQS gating : PASS
2122 12:14:10.877175 RX DQ/DQS(RDDQC) : PASS
2123 12:14:10.880834 TX DQ/DQS : PASS
2124 12:14:10.884079 RX DATLAT : PASS
2125 12:14:10.884161 RX DQ/DQS(Engine): PASS
2126 12:14:10.887339 TX OE : NO K
2127 12:14:10.887421 All Pass.
2128 12:14:10.887486
2129 12:14:10.890488 CH 1, Rank 1
2130 12:14:10.890570 SW Impedance : PASS
2131 12:14:10.893665 DUTY Scan : NO K
2132 12:14:10.897441 ZQ Calibration : PASS
2133 12:14:10.897522 Jitter Meter : NO K
2134 12:14:10.900571 CBT Training : PASS
2135 12:14:10.900652 Write leveling : PASS
2136 12:14:10.903755 RX DQS gating : PASS
2137 12:14:10.907693 RX DQ/DQS(RDDQC) : PASS
2138 12:14:10.907775 TX DQ/DQS : PASS
2139 12:14:10.910854 RX DATLAT : PASS
2140 12:14:10.914024 RX DQ/DQS(Engine): PASS
2141 12:14:10.914107 TX OE : NO K
2142 12:14:10.917133 All Pass.
2143 12:14:10.917215
2144 12:14:10.917279 DramC Write-DBI off
2145 12:14:10.921024 PER_BANK_REFRESH: Hybrid Mode
2146 12:14:10.921106 TX_TRACKING: ON
2147 12:14:10.924181 [GetDramInforAfterCalByMRR] Vendor 6.
2148 12:14:10.930806 [GetDramInforAfterCalByMRR] Revision 606.
2149 12:14:10.933675 [GetDramInforAfterCalByMRR] Revision 2 0.
2150 12:14:10.933751 MR0 0x3b3b
2151 12:14:10.933845 MR8 0x5151
2152 12:14:10.937779 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2153 12:14:10.937878
2154 12:14:10.940431 MR0 0x3b3b
2155 12:14:10.940504 MR8 0x5151
2156 12:14:10.944091 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2157 12:14:10.944190
2158 12:14:10.953938 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2159 12:14:10.957301 [FAST_K] Save calibration result to emmc
2160 12:14:10.960366 [FAST_K] Save calibration result to emmc
2161 12:14:10.964125 dram_init: config_dvfs: 1
2162 12:14:10.967419 dramc_set_vcore_voltage set vcore to 662500
2163 12:14:10.970531 Read voltage for 1200, 2
2164 12:14:10.970612 Vio18 = 0
2165 12:14:10.970676 Vcore = 662500
2166 12:14:10.974154 Vdram = 0
2167 12:14:10.974235 Vddq = 0
2168 12:14:10.974300 Vmddr = 0
2169 12:14:10.980540 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2170 12:14:10.983836 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2171 12:14:10.987350 MEM_TYPE=3, freq_sel=15
2172 12:14:10.990869 sv_algorithm_assistance_LP4_1600
2173 12:14:10.994026 ============ PULL DRAM RESETB DOWN ============
2174 12:14:10.997417 ========== PULL DRAM RESETB DOWN end =========
2175 12:14:11.004029 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2176 12:14:11.007021 ===================================
2177 12:14:11.007103 LPDDR4 DRAM CONFIGURATION
2178 12:14:11.010811 ===================================
2179 12:14:11.014013 EX_ROW_EN[0] = 0x0
2180 12:14:11.017264 EX_ROW_EN[1] = 0x0
2181 12:14:11.017345 LP4Y_EN = 0x0
2182 12:14:11.020461 WORK_FSP = 0x0
2183 12:14:11.020543 WL = 0x4
2184 12:14:11.024209 RL = 0x4
2185 12:14:11.024347 BL = 0x2
2186 12:14:11.027497 RPST = 0x0
2187 12:14:11.027578 RD_PRE = 0x0
2188 12:14:11.030690 WR_PRE = 0x1
2189 12:14:11.030771 WR_PST = 0x0
2190 12:14:11.033801 DBI_WR = 0x0
2191 12:14:11.033882 DBI_RD = 0x0
2192 12:14:11.037664 OTF = 0x1
2193 12:14:11.040688 ===================================
2194 12:14:11.044447 ===================================
2195 12:14:11.044528 ANA top config
2196 12:14:11.047539 ===================================
2197 12:14:11.050490 DLL_ASYNC_EN = 0
2198 12:14:11.054208 ALL_SLAVE_EN = 0
2199 12:14:11.054289 NEW_RANK_MODE = 1
2200 12:14:11.057203 DLL_IDLE_MODE = 1
2201 12:14:11.060828 LP45_APHY_COMB_EN = 1
2202 12:14:11.064034 TX_ODT_DIS = 1
2203 12:14:11.067561 NEW_8X_MODE = 1
2204 12:14:11.071033 ===================================
2205 12:14:11.071143 ===================================
2206 12:14:11.074240 data_rate = 2400
2207 12:14:11.077306 CKR = 1
2208 12:14:11.080984 DQ_P2S_RATIO = 8
2209 12:14:11.083901 ===================================
2210 12:14:11.087893 CA_P2S_RATIO = 8
2211 12:14:11.090707 DQ_CA_OPEN = 0
2212 12:14:11.094100 DQ_SEMI_OPEN = 0
2213 12:14:11.094183 CA_SEMI_OPEN = 0
2214 12:14:11.097680 CA_FULL_RATE = 0
2215 12:14:11.100840 DQ_CKDIV4_EN = 0
2216 12:14:11.103919 CA_CKDIV4_EN = 0
2217 12:14:11.107690 CA_PREDIV_EN = 0
2218 12:14:11.107778 PH8_DLY = 17
2219 12:14:11.110632 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2220 12:14:11.114043 DQ_AAMCK_DIV = 4
2221 12:14:11.117238 CA_AAMCK_DIV = 4
2222 12:14:11.121075 CA_ADMCK_DIV = 4
2223 12:14:11.124060 DQ_TRACK_CA_EN = 0
2224 12:14:11.124168 CA_PICK = 1200
2225 12:14:11.127613 CA_MCKIO = 1200
2226 12:14:11.130774 MCKIO_SEMI = 0
2227 12:14:11.133970 PLL_FREQ = 2366
2228 12:14:11.137851 DQ_UI_PI_RATIO = 32
2229 12:14:11.140941 CA_UI_PI_RATIO = 0
2230 12:14:11.144640 ===================================
2231 12:14:11.147592 ===================================
2232 12:14:11.150790 memory_type:LPDDR4
2233 12:14:11.150884 GP_NUM : 10
2234 12:14:11.154593 SRAM_EN : 1
2235 12:14:11.154687 MD32_EN : 0
2236 12:14:11.157674 ===================================
2237 12:14:11.161342 [ANA_INIT] >>>>>>>>>>>>>>
2238 12:14:11.164546 <<<<<< [CONFIGURE PHASE]: ANA_TX
2239 12:14:11.167568 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2240 12:14:11.170899 ===================================
2241 12:14:11.174498 data_rate = 2400,PCW = 0X5b00
2242 12:14:11.177695 ===================================
2243 12:14:11.181213 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2244 12:14:11.184570 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2245 12:14:11.190822 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2246 12:14:11.194502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2247 12:14:11.197711 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2248 12:14:11.200985 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2249 12:14:11.204409 [ANA_INIT] flow start
2250 12:14:11.208226 [ANA_INIT] PLL >>>>>>>>
2251 12:14:11.208332 [ANA_INIT] PLL <<<<<<<<
2252 12:14:11.211218 [ANA_INIT] MIDPI >>>>>>>>
2253 12:14:11.214326 [ANA_INIT] MIDPI <<<<<<<<
2254 12:14:11.217652 [ANA_INIT] DLL >>>>>>>>
2255 12:14:11.217734 [ANA_INIT] DLL <<<<<<<<
2256 12:14:11.221244 [ANA_INIT] flow end
2257 12:14:11.224202 ============ LP4 DIFF to SE enter ============
2258 12:14:11.227783 ============ LP4 DIFF to SE exit ============
2259 12:14:11.231169 [ANA_INIT] <<<<<<<<<<<<<
2260 12:14:11.234355 [Flow] Enable top DCM control >>>>>
2261 12:14:11.237567 [Flow] Enable top DCM control <<<<<
2262 12:14:11.240956 Enable DLL master slave shuffle
2263 12:14:11.244704 ==============================================================
2264 12:14:11.247843 Gating Mode config
2265 12:14:11.254170 ==============================================================
2266 12:14:11.254252 Config description:
2267 12:14:11.264131 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2268 12:14:11.270878 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2269 12:14:11.277730 SELPH_MODE 0: By rank 1: By Phase
2270 12:14:11.280999 ==============================================================
2271 12:14:11.284071 GAT_TRACK_EN = 1
2272 12:14:11.287968 RX_GATING_MODE = 2
2273 12:14:11.291009 RX_GATING_TRACK_MODE = 2
2274 12:14:11.294158 SELPH_MODE = 1
2275 12:14:11.297947 PICG_EARLY_EN = 1
2276 12:14:11.300710 VALID_LAT_VALUE = 1
2277 12:14:11.304308 ==============================================================
2278 12:14:11.307694 Enter into Gating configuration >>>>
2279 12:14:11.310906 Exit from Gating configuration <<<<
2280 12:14:11.314118 Enter into DVFS_PRE_config >>>>>
2281 12:14:11.327742 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2282 12:14:11.327850 Exit from DVFS_PRE_config <<<<<
2283 12:14:11.331302 Enter into PICG configuration >>>>
2284 12:14:11.334396 Exit from PICG configuration <<<<
2285 12:14:11.337667 [RX_INPUT] configuration >>>>>
2286 12:14:11.340672 [RX_INPUT] configuration <<<<<
2287 12:14:11.347667 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2288 12:14:11.350886 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2289 12:14:11.357531 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2290 12:14:11.364141 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2291 12:14:11.371306 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2292 12:14:11.377735 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2293 12:14:11.380871 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2294 12:14:11.384530 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2295 12:14:11.387492 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2296 12:14:11.394400 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2297 12:14:11.397477 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2298 12:14:11.400765 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2299 12:14:11.404598 ===================================
2300 12:14:11.407705 LPDDR4 DRAM CONFIGURATION
2301 12:14:11.410936 ===================================
2302 12:14:11.411035 EX_ROW_EN[0] = 0x0
2303 12:14:11.414472 EX_ROW_EN[1] = 0x0
2304 12:14:11.417364 LP4Y_EN = 0x0
2305 12:14:11.417437 WORK_FSP = 0x0
2306 12:14:11.420697 WL = 0x4
2307 12:14:11.420766 RL = 0x4
2308 12:14:11.424194 BL = 0x2
2309 12:14:11.424296 RPST = 0x0
2310 12:14:11.427503 RD_PRE = 0x0
2311 12:14:11.427570 WR_PRE = 0x1
2312 12:14:11.431354 WR_PST = 0x0
2313 12:14:11.431447 DBI_WR = 0x0
2314 12:14:11.434392 DBI_RD = 0x0
2315 12:14:11.434489 OTF = 0x1
2316 12:14:11.437622 ===================================
2317 12:14:11.441260 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2318 12:14:11.447629 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2319 12:14:11.451450 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2320 12:14:11.454624 ===================================
2321 12:14:11.457801 LPDDR4 DRAM CONFIGURATION
2322 12:14:11.460869 ===================================
2323 12:14:11.460959 EX_ROW_EN[0] = 0x10
2324 12:14:11.464688 EX_ROW_EN[1] = 0x0
2325 12:14:11.464773 LP4Y_EN = 0x0
2326 12:14:11.467837 WORK_FSP = 0x0
2327 12:14:11.467956 WL = 0x4
2328 12:14:11.471098 RL = 0x4
2329 12:14:11.471208 BL = 0x2
2330 12:14:11.474727 RPST = 0x0
2331 12:14:11.474830 RD_PRE = 0x0
2332 12:14:11.477839 WR_PRE = 0x1
2333 12:14:11.477947 WR_PST = 0x0
2334 12:14:11.481053 DBI_WR = 0x0
2335 12:14:11.481137 DBI_RD = 0x0
2336 12:14:11.485160 OTF = 0x1
2337 12:14:11.487842 ===================================
2338 12:14:11.494443 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2339 12:14:11.494526 ==
2340 12:14:11.498026 Dram Type= 6, Freq= 0, CH_0, rank 0
2341 12:14:11.501003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2342 12:14:11.501086 ==
2343 12:14:11.504427 [Duty_Offset_Calibration]
2344 12:14:11.504534 B0:2 B1:1 CA:1
2345 12:14:11.504628
2346 12:14:11.507452 [DutyScan_Calibration_Flow] k_type=0
2347 12:14:11.518660
2348 12:14:11.518743 ==CLK 0==
2349 12:14:11.521770 Final CLK duty delay cell = 0
2350 12:14:11.525048 [0] MAX Duty = 5187%(X100), DQS PI = 24
2351 12:14:11.528204 [0] MIN Duty = 4875%(X100), DQS PI = 0
2352 12:14:11.532044 [0] AVG Duty = 5031%(X100)
2353 12:14:11.532126
2354 12:14:11.535048 CH0 CLK Duty spec in!! Max-Min= 312%
2355 12:14:11.538275 [DutyScan_Calibration_Flow] ====Done====
2356 12:14:11.538356
2357 12:14:11.541553 [DutyScan_Calibration_Flow] k_type=1
2358 12:14:11.557023
2359 12:14:11.557105 ==DQS 0 ==
2360 12:14:11.560100 Final DQS duty delay cell = -4
2361 12:14:11.563993 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2362 12:14:11.567010 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2363 12:14:11.570210 [-4] AVG Duty = 4937%(X100)
2364 12:14:11.570291
2365 12:14:11.570355 ==DQS 1 ==
2366 12:14:11.574190 Final DQS duty delay cell = 0
2367 12:14:11.577219 [0] MAX Duty = 5187%(X100), DQS PI = 62
2368 12:14:11.580152 [0] MIN Duty = 5000%(X100), DQS PI = 34
2369 12:14:11.583874 [0] AVG Duty = 5093%(X100)
2370 12:14:11.583955
2371 12:14:11.586801 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2372 12:14:11.586882
2373 12:14:11.590321 CH0 DQS 1 Duty spec in!! Max-Min= 187%
2374 12:14:11.593466 [DutyScan_Calibration_Flow] ====Done====
2375 12:14:11.593540
2376 12:14:11.597139 [DutyScan_Calibration_Flow] k_type=3
2377 12:14:11.613749
2378 12:14:11.613826 ==DQM 0 ==
2379 12:14:11.617550 Final DQM duty delay cell = 0
2380 12:14:11.620410 [0] MAX Duty = 5156%(X100), DQS PI = 30
2381 12:14:11.623730 [0] MIN Duty = 4938%(X100), DQS PI = 0
2382 12:14:11.623810 [0] AVG Duty = 5047%(X100)
2383 12:14:11.626925
2384 12:14:11.627002 ==DQM 1 ==
2385 12:14:11.630397 Final DQM duty delay cell = 0
2386 12:14:11.633929 [0] MAX Duty = 5093%(X100), DQS PI = 0
2387 12:14:11.637144 [0] MIN Duty = 5031%(X100), DQS PI = 14
2388 12:14:11.637226 [0] AVG Duty = 5062%(X100)
2389 12:14:11.640154
2390 12:14:11.643872 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2391 12:14:11.643953
2392 12:14:11.647147 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2393 12:14:11.650457 [DutyScan_Calibration_Flow] ====Done====
2394 12:14:11.650538
2395 12:14:11.653450 [DutyScan_Calibration_Flow] k_type=2
2396 12:14:11.670272
2397 12:14:11.670354 ==DQ 0 ==
2398 12:14:11.673535 Final DQ duty delay cell = 0
2399 12:14:11.677321 [0] MAX Duty = 5031%(X100), DQS PI = 24
2400 12:14:11.680474 [0] MIN Duty = 4875%(X100), DQS PI = 62
2401 12:14:11.680555 [0] AVG Duty = 4953%(X100)
2402 12:14:11.680619
2403 12:14:11.683510 ==DQ 1 ==
2404 12:14:11.687153 Final DQ duty delay cell = 0
2405 12:14:11.690375 [0] MAX Duty = 5093%(X100), DQS PI = 24
2406 12:14:11.694147 [0] MIN Duty = 4938%(X100), DQS PI = 36
2407 12:14:11.694229 [0] AVG Duty = 5015%(X100)
2408 12:14:11.694294
2409 12:14:11.697071 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2410 12:14:11.697153
2411 12:14:11.700100 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2412 12:14:11.706755 [DutyScan_Calibration_Flow] ====Done====
2413 12:14:11.706837 ==
2414 12:14:11.710626 Dram Type= 6, Freq= 0, CH_1, rank 0
2415 12:14:11.713815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2416 12:14:11.713898 ==
2417 12:14:11.717090 [Duty_Offset_Calibration]
2418 12:14:11.717172 B0:1 B1:0 CA:0
2419 12:14:11.717237
2420 12:14:11.720135 [DutyScan_Calibration_Flow] k_type=0
2421 12:14:11.729636
2422 12:14:11.729718 ==CLK 0==
2423 12:14:11.732571 Final CLK duty delay cell = -4
2424 12:14:11.736428 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2425 12:14:11.739599 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2426 12:14:11.742916 [-4] AVG Duty = 4953%(X100)
2427 12:14:11.742997
2428 12:14:11.746404 CH1 CLK Duty spec in!! Max-Min= 156%
2429 12:14:11.749401 [DutyScan_Calibration_Flow] ====Done====
2430 12:14:11.749484
2431 12:14:11.752830 [DutyScan_Calibration_Flow] k_type=1
2432 12:14:11.769199
2433 12:14:11.769279 ==DQS 0 ==
2434 12:14:11.772669 Final DQS duty delay cell = 0
2435 12:14:11.775511 [0] MAX Duty = 5062%(X100), DQS PI = 24
2436 12:14:11.779004 [0] MIN Duty = 4875%(X100), DQS PI = 0
2437 12:14:11.779086 [0] AVG Duty = 4968%(X100)
2438 12:14:11.782266
2439 12:14:11.782340 ==DQS 1 ==
2440 12:14:11.785670 Final DQS duty delay cell = 0
2441 12:14:11.789379 [0] MAX Duty = 5187%(X100), DQS PI = 20
2442 12:14:11.792604 [0] MIN Duty = 4969%(X100), DQS PI = 8
2443 12:14:11.792687 [0] AVG Duty = 5078%(X100)
2444 12:14:11.792752
2445 12:14:11.799281 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2446 12:14:11.799363
2447 12:14:11.802714 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2448 12:14:11.805886 [DutyScan_Calibration_Flow] ====Done====
2449 12:14:11.805968
2450 12:14:11.809092 [DutyScan_Calibration_Flow] k_type=3
2451 12:14:11.825363
2452 12:14:11.825444 ==DQM 0 ==
2453 12:14:11.829152 Final DQM duty delay cell = 0
2454 12:14:11.832270 [0] MAX Duty = 5156%(X100), DQS PI = 6
2455 12:14:11.835839 [0] MIN Duty = 5031%(X100), DQS PI = 0
2456 12:14:11.835921 [0] AVG Duty = 5093%(X100)
2457 12:14:11.835986
2458 12:14:11.839105 ==DQM 1 ==
2459 12:14:11.842202 Final DQM duty delay cell = 0
2460 12:14:11.845603 [0] MAX Duty = 5031%(X100), DQS PI = 26
2461 12:14:11.849157 [0] MIN Duty = 4875%(X100), DQS PI = 36
2462 12:14:11.849239 [0] AVG Duty = 4953%(X100)
2463 12:14:11.849313
2464 12:14:11.855609 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2465 12:14:11.855685
2466 12:14:11.858767 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2467 12:14:11.862452 [DutyScan_Calibration_Flow] ====Done====
2468 12:14:11.862524
2469 12:14:11.865831 [DutyScan_Calibration_Flow] k_type=2
2470 12:14:11.881261
2471 12:14:11.881341 ==DQ 0 ==
2472 12:14:11.884584 Final DQ duty delay cell = -4
2473 12:14:11.888071 [-4] MAX Duty = 5094%(X100), DQS PI = 10
2474 12:14:11.891083 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2475 12:14:11.894801 [-4] AVG Duty = 5000%(X100)
2476 12:14:11.894884
2477 12:14:11.894947 ==DQ 1 ==
2478 12:14:11.898175 Final DQ duty delay cell = 0
2479 12:14:11.901430 [0] MAX Duty = 5125%(X100), DQS PI = 20
2480 12:14:11.904432 [0] MIN Duty = 4938%(X100), DQS PI = 34
2481 12:14:11.908205 [0] AVG Duty = 5031%(X100)
2482 12:14:11.908345
2483 12:14:11.911193 CH1 DQ 0 Duty spec in!! Max-Min= 188%
2484 12:14:11.911276
2485 12:14:11.914528 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2486 12:14:11.917863 [DutyScan_Calibration_Flow] ====Done====
2487 12:14:11.921472 nWR fixed to 30
2488 12:14:11.921555 [ModeRegInit_LP4] CH0 RK0
2489 12:14:11.924695 [ModeRegInit_LP4] CH0 RK1
2490 12:14:11.927895 [ModeRegInit_LP4] CH1 RK0
2491 12:14:11.931674 [ModeRegInit_LP4] CH1 RK1
2492 12:14:11.931756 match AC timing 7
2493 12:14:11.937990 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2494 12:14:11.941716 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2495 12:14:11.944772 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2496 12:14:11.951540 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2497 12:14:11.954686 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2498 12:14:11.954760 ==
2499 12:14:11.957843 Dram Type= 6, Freq= 0, CH_0, rank 0
2500 12:14:11.961669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2501 12:14:11.961750 ==
2502 12:14:11.968098 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2503 12:14:11.974548 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2504 12:14:11.981516 [CA 0] Center 39 (8~70) winsize 63
2505 12:14:11.984843 [CA 1] Center 39 (8~70) winsize 63
2506 12:14:11.988748 [CA 2] Center 35 (4~66) winsize 63
2507 12:14:11.991726 [CA 3] Center 34 (4~65) winsize 62
2508 12:14:11.994829 [CA 4] Center 33 (3~64) winsize 62
2509 12:14:11.998202 [CA 5] Center 32 (3~62) winsize 60
2510 12:14:11.998283
2511 12:14:12.001313 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2512 12:14:12.001388
2513 12:14:12.005071 [CATrainingPosCal] consider 1 rank data
2514 12:14:12.008277 u2DelayCellTimex100 = 270/100 ps
2515 12:14:12.011629 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2516 12:14:12.015008 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2517 12:14:12.021484 CA2 delay=35 (4~66),Diff = 3 PI (14 cell)
2518 12:14:12.024990 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2519 12:14:12.028178 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2520 12:14:12.031463 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2521 12:14:12.031536
2522 12:14:12.035126 CA PerBit enable=1, Macro0, CA PI delay=32
2523 12:14:12.035208
2524 12:14:12.037960 [CBTSetCACLKResult] CA Dly = 32
2525 12:14:12.038041 CS Dly: 6 (0~37)
2526 12:14:12.041467 ==
2527 12:14:12.041548 Dram Type= 6, Freq= 0, CH_0, rank 1
2528 12:14:12.047854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2529 12:14:12.047940 ==
2530 12:14:12.051712 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2531 12:14:12.058188 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2532 12:14:12.067391 [CA 0] Center 38 (8~69) winsize 62
2533 12:14:12.070406 [CA 1] Center 38 (8~69) winsize 62
2534 12:14:12.073741 [CA 2] Center 35 (5~66) winsize 62
2535 12:14:12.077386 [CA 3] Center 34 (4~65) winsize 62
2536 12:14:12.080625 [CA 4] Center 33 (3~64) winsize 62
2537 12:14:12.084380 [CA 5] Center 32 (3~62) winsize 60
2538 12:14:12.084461
2539 12:14:12.087434 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2540 12:14:12.087515
2541 12:14:12.090722 [CATrainingPosCal] consider 2 rank data
2542 12:14:12.094459 u2DelayCellTimex100 = 270/100 ps
2543 12:14:12.097662 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2544 12:14:12.100778 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2545 12:14:12.107607 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2546 12:14:12.110804 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2547 12:14:12.113750 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2548 12:14:12.117756 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2549 12:14:12.117837
2550 12:14:12.120722 CA PerBit enable=1, Macro0, CA PI delay=32
2551 12:14:12.120807
2552 12:14:12.124021 [CBTSetCACLKResult] CA Dly = 32
2553 12:14:12.124128 CS Dly: 6 (0~38)
2554 12:14:12.124220
2555 12:14:12.127732 ----->DramcWriteLeveling(PI) begin...
2556 12:14:12.131051 ==
2557 12:14:12.131135 Dram Type= 6, Freq= 0, CH_0, rank 0
2558 12:14:12.137654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2559 12:14:12.137734 ==
2560 12:14:12.140660 Write leveling (Byte 0): 33 => 33
2561 12:14:12.144210 Write leveling (Byte 1): 27 => 27
2562 12:14:12.147350 DramcWriteLeveling(PI) end<-----
2563 12:14:12.147419
2564 12:14:12.147480 ==
2565 12:14:12.150812 Dram Type= 6, Freq= 0, CH_0, rank 0
2566 12:14:12.153967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2567 12:14:12.154049 ==
2568 12:14:12.157596 [Gating] SW mode calibration
2569 12:14:12.164009 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2570 12:14:12.168138 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2571 12:14:12.174245 0 15 0 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
2572 12:14:12.177441 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2573 12:14:12.180801 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2574 12:14:12.187389 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2575 12:14:12.191287 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2576 12:14:12.194519 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2577 12:14:12.200880 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2578 12:14:12.204661 0 15 28 | B1->B0 | 3434 2323 | 0 1 | (0 0) (1 1)
2579 12:14:12.207772 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
2580 12:14:12.214057 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2581 12:14:12.218131 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2582 12:14:12.220826 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2583 12:14:12.228519 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2584 12:14:12.231245 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 12:14:12.234283 1 0 24 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
2586 12:14:12.237984 1 0 28 | B1->B0 | 2a2a 4444 | 0 0 | (0 0) (0 0)
2587 12:14:12.244454 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2588 12:14:12.248115 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2589 12:14:12.251254 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2590 12:14:12.258217 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2591 12:14:12.261495 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 12:14:12.264941 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 12:14:12.271162 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 12:14:12.274401 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2595 12:14:12.277820 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2596 12:14:12.284555 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 12:14:12.287980 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 12:14:12.291234 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 12:14:12.298026 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 12:14:12.301064 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 12:14:12.305045 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 12:14:12.308039 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 12:14:12.314951 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 12:14:12.318021 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 12:14:12.321240 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 12:14:12.328492 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 12:14:12.331415 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 12:14:12.335101 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 12:14:12.341538 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 12:14:12.344688 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2611 12:14:12.347877 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2612 12:14:12.351319 Total UI for P1: 0, mck2ui 16
2613 12:14:12.354663 best dqsien dly found for B0: ( 1, 3, 28)
2614 12:14:12.361773 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 12:14:12.361848 Total UI for P1: 0, mck2ui 16
2616 12:14:12.364964 best dqsien dly found for B1: ( 1, 3, 30)
2617 12:14:12.371924 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2618 12:14:12.375152 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2619 12:14:12.375228
2620 12:14:12.378216 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2621 12:14:12.381367 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2622 12:14:12.385325 [Gating] SW calibration Done
2623 12:14:12.385396 ==
2624 12:14:12.388139 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 12:14:12.391722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 12:14:12.391826 ==
2627 12:14:12.394656 RX Vref Scan: 0
2628 12:14:12.394729
2629 12:14:12.394790 RX Vref 0 -> 0, step: 1
2630 12:14:12.394847
2631 12:14:12.398249 RX Delay -40 -> 252, step: 8
2632 12:14:12.401948 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2633 12:14:12.405040 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2634 12:14:12.411238 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2635 12:14:12.415349 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2636 12:14:12.418534 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2637 12:14:12.421519 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2638 12:14:12.425128 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2639 12:14:12.431668 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2640 12:14:12.435154 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2641 12:14:12.438315 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2642 12:14:12.441953 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2643 12:14:12.444969 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2644 12:14:12.451945 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2645 12:14:12.455132 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2646 12:14:12.458711 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2647 12:14:12.462016 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2648 12:14:12.462091 ==
2649 12:14:12.465154 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 12:14:12.468231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 12:14:12.472164 ==
2652 12:14:12.472253 DQS Delay:
2653 12:14:12.472342 DQS0 = 0, DQS1 = 0
2654 12:14:12.475075 DQM Delay:
2655 12:14:12.475154 DQM0 = 121, DQM1 = 113
2656 12:14:12.478447 DQ Delay:
2657 12:14:12.482205 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2658 12:14:12.485425 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2659 12:14:12.488662 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2660 12:14:12.491916 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2661 12:14:12.492001
2662 12:14:12.492066
2663 12:14:12.492126 ==
2664 12:14:12.495426 Dram Type= 6, Freq= 0, CH_0, rank 0
2665 12:14:12.498682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2666 12:14:12.498800 ==
2667 12:14:12.498918
2668 12:14:12.499035
2669 12:14:12.502006 TX Vref Scan disable
2670 12:14:12.505568 == TX Byte 0 ==
2671 12:14:12.508694 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2672 12:14:12.511760 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2673 12:14:12.515448 == TX Byte 1 ==
2674 12:14:12.518362 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2675 12:14:12.522053 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2676 12:14:12.522162 ==
2677 12:14:12.525660 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 12:14:12.528409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 12:14:12.532060 ==
2680 12:14:12.542622 TX Vref=22, minBit 10, minWin=24, winSum=404
2681 12:14:12.545751 TX Vref=24, minBit 0, minWin=25, winSum=408
2682 12:14:12.549490 TX Vref=26, minBit 13, minWin=25, winSum=418
2683 12:14:12.552825 TX Vref=28, minBit 1, minWin=26, winSum=421
2684 12:14:12.556066 TX Vref=30, minBit 10, minWin=25, winSum=423
2685 12:14:12.562658 TX Vref=32, minBit 10, minWin=25, winSum=417
2686 12:14:12.566001 [TxChooseVref] Worse bit 1, Min win 26, Win sum 421, Final Vref 28
2687 12:14:12.566080
2688 12:14:12.569251 Final TX Range 1 Vref 28
2689 12:14:12.569366
2690 12:14:12.569445 ==
2691 12:14:12.572664 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 12:14:12.575761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 12:14:12.575835 ==
2694 12:14:12.579093
2695 12:14:12.579165
2696 12:14:12.579227 TX Vref Scan disable
2697 12:14:12.582800 == TX Byte 0 ==
2698 12:14:12.585898 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2699 12:14:12.589291 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2700 12:14:12.592932 == TX Byte 1 ==
2701 12:14:12.596143 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2702 12:14:12.599095 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2703 12:14:12.602956
2704 12:14:12.603084 [DATLAT]
2705 12:14:12.603165 Freq=1200, CH0 RK0
2706 12:14:12.603291
2707 12:14:12.606137 DATLAT Default: 0xd
2708 12:14:12.606222 0, 0xFFFF, sum = 0
2709 12:14:12.609339 1, 0xFFFF, sum = 0
2710 12:14:12.609452 2, 0xFFFF, sum = 0
2711 12:14:12.612905 3, 0xFFFF, sum = 0
2712 12:14:12.613000 4, 0xFFFF, sum = 0
2713 12:14:12.616000 5, 0xFFFF, sum = 0
2714 12:14:12.619221 6, 0xFFFF, sum = 0
2715 12:14:12.619333 7, 0xFFFF, sum = 0
2716 12:14:12.622990 8, 0xFFFF, sum = 0
2717 12:14:12.623083 9, 0xFFFF, sum = 0
2718 12:14:12.625964 10, 0xFFFF, sum = 0
2719 12:14:12.626072 11, 0xFFFF, sum = 0
2720 12:14:12.629369 12, 0x0, sum = 1
2721 12:14:12.629478 13, 0x0, sum = 2
2722 12:14:12.632589 14, 0x0, sum = 3
2723 12:14:12.632698 15, 0x0, sum = 4
2724 12:14:12.632794 best_step = 13
2725 12:14:12.632870
2726 12:14:12.635738 ==
2727 12:14:12.639386 Dram Type= 6, Freq= 0, CH_0, rank 0
2728 12:14:12.642539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2729 12:14:12.642640 ==
2730 12:14:12.642738 RX Vref Scan: 1
2731 12:14:12.642813
2732 12:14:12.646045 Set Vref Range= 32 -> 127
2733 12:14:12.646149
2734 12:14:12.649059 RX Vref 32 -> 127, step: 1
2735 12:14:12.649149
2736 12:14:12.652889 RX Delay -13 -> 252, step: 4
2737 12:14:12.652979
2738 12:14:12.656144 Set Vref, RX VrefLevel [Byte0]: 32
2739 12:14:12.659264 [Byte1]: 32
2740 12:14:12.659353
2741 12:14:12.662669 Set Vref, RX VrefLevel [Byte0]: 33
2742 12:14:12.665861 [Byte1]: 33
2743 12:14:12.665976
2744 12:14:12.669242 Set Vref, RX VrefLevel [Byte0]: 34
2745 12:14:12.672725 [Byte1]: 34
2746 12:14:12.676683
2747 12:14:12.676776 Set Vref, RX VrefLevel [Byte0]: 35
2748 12:14:12.680467 [Byte1]: 35
2749 12:14:12.685639
2750 12:14:12.685756 Set Vref, RX VrefLevel [Byte0]: 36
2751 12:14:12.688530 [Byte1]: 36
2752 12:14:12.692598
2753 12:14:12.692709 Set Vref, RX VrefLevel [Byte0]: 37
2754 12:14:12.695805 [Byte1]: 37
2755 12:14:12.700533
2756 12:14:12.700638 Set Vref, RX VrefLevel [Byte0]: 38
2757 12:14:12.704179 [Byte1]: 38
2758 12:14:12.708727
2759 12:14:12.708808 Set Vref, RX VrefLevel [Byte0]: 39
2760 12:14:12.711722 [Byte1]: 39
2761 12:14:12.716114
2762 12:14:12.716189 Set Vref, RX VrefLevel [Byte0]: 40
2763 12:14:12.720021 [Byte1]: 40
2764 12:14:12.724471
2765 12:14:12.724541 Set Vref, RX VrefLevel [Byte0]: 41
2766 12:14:12.727394 [Byte1]: 41
2767 12:14:12.732415
2768 12:14:12.732493 Set Vref, RX VrefLevel [Byte0]: 42
2769 12:14:12.735466 [Byte1]: 42
2770 12:14:12.740077
2771 12:14:12.740163 Set Vref, RX VrefLevel [Byte0]: 43
2772 12:14:12.743175 [Byte1]: 43
2773 12:14:12.747617
2774 12:14:12.747696 Set Vref, RX VrefLevel [Byte0]: 44
2775 12:14:12.751132 [Byte1]: 44
2776 12:14:12.755596
2777 12:14:12.755689 Set Vref, RX VrefLevel [Byte0]: 45
2778 12:14:12.759195 [Byte1]: 45
2779 12:14:12.763756
2780 12:14:12.763829 Set Vref, RX VrefLevel [Byte0]: 46
2781 12:14:12.766884 [Byte1]: 46
2782 12:14:12.771765
2783 12:14:12.771851 Set Vref, RX VrefLevel [Byte0]: 47
2784 12:14:12.774745 [Byte1]: 47
2785 12:14:12.779760
2786 12:14:12.779836 Set Vref, RX VrefLevel [Byte0]: 48
2787 12:14:12.782968 [Byte1]: 48
2788 12:14:12.787275
2789 12:14:12.787350 Set Vref, RX VrefLevel [Byte0]: 49
2790 12:14:12.790578 [Byte1]: 49
2791 12:14:12.795532
2792 12:14:12.795600 Set Vref, RX VrefLevel [Byte0]: 50
2793 12:14:12.798725 [Byte1]: 50
2794 12:14:12.802851
2795 12:14:12.802920 Set Vref, RX VrefLevel [Byte0]: 51
2796 12:14:12.806500 [Byte1]: 51
2797 12:14:12.810894
2798 12:14:12.810965 Set Vref, RX VrefLevel [Byte0]: 52
2799 12:14:12.814374 [Byte1]: 52
2800 12:14:12.819000
2801 12:14:12.819072 Set Vref, RX VrefLevel [Byte0]: 53
2802 12:14:12.822081 [Byte1]: 53
2803 12:14:12.826622
2804 12:14:12.826702 Set Vref, RX VrefLevel [Byte0]: 54
2805 12:14:12.830192 [Byte1]: 54
2806 12:14:12.834722
2807 12:14:12.834800 Set Vref, RX VrefLevel [Byte0]: 55
2808 12:14:12.838275 [Byte1]: 55
2809 12:14:12.842637
2810 12:14:12.842707 Set Vref, RX VrefLevel [Byte0]: 56
2811 12:14:12.846150 [Byte1]: 56
2812 12:14:12.850388
2813 12:14:12.850467 Set Vref, RX VrefLevel [Byte0]: 57
2814 12:14:12.854079 [Byte1]: 57
2815 12:14:12.858314
2816 12:14:12.858386 Set Vref, RX VrefLevel [Byte0]: 58
2817 12:14:12.861516 [Byte1]: 58
2818 12:14:12.866672
2819 12:14:12.866753 Set Vref, RX VrefLevel [Byte0]: 59
2820 12:14:12.869305 [Byte1]: 59
2821 12:14:12.874431
2822 12:14:12.874526 Set Vref, RX VrefLevel [Byte0]: 60
2823 12:14:12.877676 [Byte1]: 60
2824 12:14:12.881825
2825 12:14:12.881896 Set Vref, RX VrefLevel [Byte0]: 61
2826 12:14:12.885051 [Byte1]: 61
2827 12:14:12.889899
2828 12:14:12.889978 Set Vref, RX VrefLevel [Byte0]: 62
2829 12:14:12.893067 [Byte1]: 62
2830 12:14:12.898241
2831 12:14:12.898309 Set Vref, RX VrefLevel [Byte0]: 63
2832 12:14:12.901327 [Byte1]: 63
2833 12:14:12.905902
2834 12:14:12.905971 Set Vref, RX VrefLevel [Byte0]: 64
2835 12:14:12.908988 [Byte1]: 64
2836 12:14:12.913395
2837 12:14:12.913472 Set Vref, RX VrefLevel [Byte0]: 65
2838 12:14:12.917061 [Byte1]: 65
2839 12:14:12.921951
2840 12:14:12.922030 Set Vref, RX VrefLevel [Byte0]: 66
2841 12:14:12.924700 [Byte1]: 66
2842 12:14:12.929704
2843 12:14:12.929786 Set Vref, RX VrefLevel [Byte0]: 67
2844 12:14:12.932643 [Byte1]: 67
2845 12:14:12.937302
2846 12:14:12.937410 Set Vref, RX VrefLevel [Byte0]: 68
2847 12:14:12.940572 [Byte1]: 68
2848 12:14:12.945153
2849 12:14:12.945261 Set Vref, RX VrefLevel [Byte0]: 69
2850 12:14:12.948593 [Byte1]: 69
2851 12:14:12.953074
2852 12:14:12.953156 Set Vref, RX VrefLevel [Byte0]: 70
2853 12:14:12.956269 [Byte1]: 70
2854 12:14:12.960750
2855 12:14:12.960832 Final RX Vref Byte 0 = 55 to rank0
2856 12:14:12.964551 Final RX Vref Byte 1 = 45 to rank0
2857 12:14:12.967409 Final RX Vref Byte 0 = 55 to rank1
2858 12:14:12.970809 Final RX Vref Byte 1 = 45 to rank1==
2859 12:14:12.974397 Dram Type= 6, Freq= 0, CH_0, rank 0
2860 12:14:12.980886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2861 12:14:12.981006 ==
2862 12:14:12.981075 DQS Delay:
2863 12:14:12.981136 DQS0 = 0, DQS1 = 0
2864 12:14:12.984436 DQM Delay:
2865 12:14:12.984522 DQM0 = 120, DQM1 = 110
2866 12:14:12.987667 DQ Delay:
2867 12:14:12.990920 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2868 12:14:12.994469 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2869 12:14:12.997841 DQ8 =96, DQ9 =98, DQ10 =112, DQ11 =102
2870 12:14:13.000832 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2871 12:14:13.000915
2872 12:14:13.000981
2873 12:14:13.007607 [DQSOSCAuto] RK0, (LSB)MR18= 0x130c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2874 12:14:13.010779 CH0 RK0: MR19=404, MR18=130C
2875 12:14:13.017751 CH0_RK0: MR19=0x404, MR18=0x130C, DQSOSC=402, MR23=63, INC=40, DEC=27
2876 12:14:13.017835
2877 12:14:13.020986 ----->DramcWriteLeveling(PI) begin...
2878 12:14:13.021070 ==
2879 12:14:13.024391 Dram Type= 6, Freq= 0, CH_0, rank 1
2880 12:14:13.027891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2881 12:14:13.031037 ==
2882 12:14:13.031112 Write leveling (Byte 0): 35 => 35
2883 12:14:13.034107 Write leveling (Byte 1): 30 => 30
2884 12:14:13.037944 DramcWriteLeveling(PI) end<-----
2885 12:14:13.038018
2886 12:14:13.038079 ==
2887 12:14:13.041218 Dram Type= 6, Freq= 0, CH_0, rank 1
2888 12:14:13.047770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2889 12:14:13.047848 ==
2890 12:14:13.047911 [Gating] SW mode calibration
2891 12:14:13.057372 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2892 12:14:13.061097 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2893 12:14:13.064116 0 15 0 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (1 0)
2894 12:14:13.071250 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 12:14:13.074097 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 12:14:13.077694 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 12:14:13.084871 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 12:14:13.087821 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 12:14:13.091045 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 12:14:13.097741 0 15 28 | B1->B0 | 2e2e 2d2d | 0 0 | (1 0) (0 1)
2901 12:14:13.101158 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2902 12:14:13.104493 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 12:14:13.111176 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 12:14:13.114265 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 12:14:13.118026 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 12:14:13.121123 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 12:14:13.128018 1 0 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
2908 12:14:13.130919 1 0 28 | B1->B0 | 3c3c 3c3c | 0 0 | (0 0) (0 0)
2909 12:14:13.137546 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 12:14:13.140856 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 12:14:13.144775 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 12:14:13.147778 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 12:14:13.154171 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 12:14:13.157851 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 12:14:13.161139 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 12:14:13.168122 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2917 12:14:13.171155 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 12:14:13.174147 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 12:14:13.180757 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 12:14:13.184490 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 12:14:13.187599 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 12:14:13.194574 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 12:14:13.197844 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 12:14:13.201087 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 12:14:13.207758 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 12:14:13.210896 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 12:14:13.214401 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 12:14:13.220879 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 12:14:13.224301 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 12:14:13.227785 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 12:14:13.234415 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 12:14:13.238001 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2933 12:14:13.240770 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2934 12:14:13.244575 Total UI for P1: 0, mck2ui 16
2935 12:14:13.247802 best dqsien dly found for B1: ( 1, 3, 28)
2936 12:14:13.250976 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 12:14:13.254270 Total UI for P1: 0, mck2ui 16
2938 12:14:13.257885 best dqsien dly found for B0: ( 1, 3, 30)
2939 12:14:13.261003 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2940 12:14:13.264209 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2941 12:14:13.267445
2942 12:14:13.270466 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2943 12:14:13.274246 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2944 12:14:13.277763 [Gating] SW calibration Done
2945 12:14:13.277844 ==
2946 12:14:13.280921 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 12:14:13.284099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 12:14:13.284173 ==
2949 12:14:13.284234 RX Vref Scan: 0
2950 12:14:13.287298
2951 12:14:13.287379 RX Vref 0 -> 0, step: 1
2952 12:14:13.287444
2953 12:14:13.291097 RX Delay -40 -> 252, step: 8
2954 12:14:13.294113 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2955 12:14:13.297864 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2956 12:14:13.304128 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2957 12:14:13.307647 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2958 12:14:13.311286 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2959 12:14:13.314352 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2960 12:14:13.317440 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2961 12:14:13.324235 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2962 12:14:13.327568 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2963 12:14:13.331496 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2964 12:14:13.334550 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2965 12:14:13.337943 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2966 12:14:13.341271 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2967 12:14:13.347720 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2968 12:14:13.351018 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2969 12:14:13.354087 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2970 12:14:13.354169 ==
2971 12:14:13.357966 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 12:14:13.361027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 12:14:13.364374 ==
2974 12:14:13.364456 DQS Delay:
2975 12:14:13.364522 DQS0 = 0, DQS1 = 0
2976 12:14:13.367471 DQM Delay:
2977 12:14:13.367552 DQM0 = 122, DQM1 = 112
2978 12:14:13.371394 DQ Delay:
2979 12:14:13.374587 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2980 12:14:13.377601 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2981 12:14:13.380880 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2982 12:14:13.384769 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2983 12:14:13.384851
2984 12:14:13.384916
2985 12:14:13.384975 ==
2986 12:14:13.388120 Dram Type= 6, Freq= 0, CH_0, rank 1
2987 12:14:13.390961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2988 12:14:13.391044 ==
2989 12:14:13.391109
2990 12:14:13.391168
2991 12:14:13.394521 TX Vref Scan disable
2992 12:14:13.398041 == TX Byte 0 ==
2993 12:14:13.401218 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2994 12:14:13.404464 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2995 12:14:13.407523 == TX Byte 1 ==
2996 12:14:13.411373 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2997 12:14:13.414611 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2998 12:14:13.414681 ==
2999 12:14:13.417679 Dram Type= 6, Freq= 0, CH_0, rank 1
3000 12:14:13.421438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3001 12:14:13.424550 ==
3002 12:14:13.434884 TX Vref=22, minBit 1, minWin=25, winSum=415
3003 12:14:13.438715 TX Vref=24, minBit 1, minWin=25, winSum=418
3004 12:14:13.441928 TX Vref=26, minBit 5, minWin=25, winSum=424
3005 12:14:13.445006 TX Vref=28, minBit 5, minWin=25, winSum=427
3006 12:14:13.448608 TX Vref=30, minBit 5, minWin=25, winSum=423
3007 12:14:13.451653 TX Vref=32, minBit 2, minWin=26, winSum=428
3008 12:14:13.458586 [TxChooseVref] Worse bit 2, Min win 26, Win sum 428, Final Vref 32
3009 12:14:13.458659
3010 12:14:13.461861 Final TX Range 1 Vref 32
3011 12:14:13.461932
3012 12:14:13.461994 ==
3013 12:14:13.465385 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 12:14:13.469013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 12:14:13.469090 ==
3016 12:14:13.469154
3017 12:14:13.469213
3018 12:14:13.472060 TX Vref Scan disable
3019 12:14:13.475563 == TX Byte 0 ==
3020 12:14:13.478701 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
3021 12:14:13.482234 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
3022 12:14:13.485503 == TX Byte 1 ==
3023 12:14:13.488583 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3024 12:14:13.491764 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3025 12:14:13.491832
3026 12:14:13.495448 [DATLAT]
3027 12:14:13.495515 Freq=1200, CH0 RK1
3028 12:14:13.495577
3029 12:14:13.498488 DATLAT Default: 0xd
3030 12:14:13.498562 0, 0xFFFF, sum = 0
3031 12:14:13.501800 1, 0xFFFF, sum = 0
3032 12:14:13.501871 2, 0xFFFF, sum = 0
3033 12:14:13.505292 3, 0xFFFF, sum = 0
3034 12:14:13.505361 4, 0xFFFF, sum = 0
3035 12:14:13.508834 5, 0xFFFF, sum = 0
3036 12:14:13.508911 6, 0xFFFF, sum = 0
3037 12:14:13.511890 7, 0xFFFF, sum = 0
3038 12:14:13.511989 8, 0xFFFF, sum = 0
3039 12:14:13.515733 9, 0xFFFF, sum = 0
3040 12:14:13.515808 10, 0xFFFF, sum = 0
3041 12:14:13.518787 11, 0xFFFF, sum = 0
3042 12:14:13.518872 12, 0x0, sum = 1
3043 12:14:13.521742 13, 0x0, sum = 2
3044 12:14:13.521831 14, 0x0, sum = 3
3045 12:14:13.525011 15, 0x0, sum = 4
3046 12:14:13.525086 best_step = 13
3047 12:14:13.525147
3048 12:14:13.525205 ==
3049 12:14:13.528663 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 12:14:13.535239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 12:14:13.535320 ==
3052 12:14:13.535384 RX Vref Scan: 0
3053 12:14:13.535444
3054 12:14:13.538868 RX Vref 0 -> 0, step: 1
3055 12:14:13.538942
3056 12:14:13.542118 RX Delay -13 -> 252, step: 4
3057 12:14:13.545307 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3058 12:14:13.549019 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3059 12:14:13.555243 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3060 12:14:13.558992 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3061 12:14:13.562189 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3062 12:14:13.565260 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3063 12:14:13.568841 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3064 12:14:13.575511 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3065 12:14:13.578593 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3066 12:14:13.581756 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3067 12:14:13.585221 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3068 12:14:13.588870 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3069 12:14:13.595677 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3070 12:14:13.599137 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3071 12:14:13.601833 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3072 12:14:13.605596 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3073 12:14:13.605673 ==
3074 12:14:13.608770 Dram Type= 6, Freq= 0, CH_0, rank 1
3075 12:14:13.611854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3076 12:14:13.615808 ==
3077 12:14:13.615880 DQS Delay:
3078 12:14:13.615941 DQS0 = 0, DQS1 = 0
3079 12:14:13.618760 DQM Delay:
3080 12:14:13.618829 DQM0 = 121, DQM1 = 109
3081 12:14:13.622403 DQ Delay:
3082 12:14:13.625605 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118
3083 12:14:13.628472 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3084 12:14:13.632091 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3085 12:14:13.635604 DQ12 =116, DQ13 =116, DQ14 =120, DQ15 =118
3086 12:14:13.635671
3087 12:14:13.635734
3088 12:14:13.642247 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 403 ps
3089 12:14:13.645443 CH0 RK1: MR19=403, MR18=10F1
3090 12:14:13.651838 CH0_RK1: MR19=0x403, MR18=0x10F1, DQSOSC=403, MR23=63, INC=40, DEC=26
3091 12:14:13.655575 [RxdqsGatingPostProcess] freq 1200
3092 12:14:13.661865 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3093 12:14:13.665676 best DQS0 dly(2T, 0.5T) = (0, 11)
3094 12:14:13.665749 best DQS1 dly(2T, 0.5T) = (0, 11)
3095 12:14:13.668746 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3096 12:14:13.671838 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3097 12:14:13.675614 best DQS0 dly(2T, 0.5T) = (0, 11)
3098 12:14:13.678800 best DQS1 dly(2T, 0.5T) = (0, 11)
3099 12:14:13.681876 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3100 12:14:13.685517 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3101 12:14:13.688794 Pre-setting of DQS Precalculation
3102 12:14:13.695335 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3103 12:14:13.695404 ==
3104 12:14:13.698559 Dram Type= 6, Freq= 0, CH_1, rank 0
3105 12:14:13.702579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 12:14:13.702653 ==
3107 12:14:13.708749 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3108 12:14:13.711859 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3109 12:14:13.721566 [CA 0] Center 37 (7~68) winsize 62
3110 12:14:13.724485 [CA 1] Center 37 (7~68) winsize 62
3111 12:14:13.728185 [CA 2] Center 35 (5~65) winsize 61
3112 12:14:13.731299 [CA 3] Center 34 (4~64) winsize 61
3113 12:14:13.734956 [CA 4] Center 34 (4~64) winsize 61
3114 12:14:13.738060 [CA 5] Center 33 (3~63) winsize 61
3115 12:14:13.738158
3116 12:14:13.741628 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3117 12:14:13.741697
3118 12:14:13.745177 [CATrainingPosCal] consider 1 rank data
3119 12:14:13.748037 u2DelayCellTimex100 = 270/100 ps
3120 12:14:13.751597 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3121 12:14:13.755229 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3122 12:14:13.758343 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3123 12:14:13.765075 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3124 12:14:13.768194 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3125 12:14:13.771478 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3126 12:14:13.771555
3127 12:14:13.775149 CA PerBit enable=1, Macro0, CA PI delay=33
3128 12:14:13.775232
3129 12:14:13.778182 [CBTSetCACLKResult] CA Dly = 33
3130 12:14:13.778251 CS Dly: 7 (0~38)
3131 12:14:13.778312 ==
3132 12:14:13.782106 Dram Type= 6, Freq= 0, CH_1, rank 1
3133 12:14:13.788087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3134 12:14:13.788162 ==
3135 12:14:13.791876 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3136 12:14:13.798232 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3137 12:14:13.806989 [CA 0] Center 37 (7~68) winsize 62
3138 12:14:13.810599 [CA 1] Center 37 (7~68) winsize 62
3139 12:14:13.813721 [CA 2] Center 35 (5~65) winsize 61
3140 12:14:13.816808 [CA 3] Center 34 (4~65) winsize 62
3141 12:14:13.820448 [CA 4] Center 34 (4~65) winsize 62
3142 12:14:13.824025 [CA 5] Center 33 (4~63) winsize 60
3143 12:14:13.824098
3144 12:14:13.826916 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3145 12:14:13.826986
3146 12:14:13.830802 [CATrainingPosCal] consider 2 rank data
3147 12:14:13.833690 u2DelayCellTimex100 = 270/100 ps
3148 12:14:13.837046 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3149 12:14:13.840390 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3150 12:14:13.843879 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3151 12:14:13.850448 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3152 12:14:13.853987 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3153 12:14:13.857540 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3154 12:14:13.857615
3155 12:14:13.861029 CA PerBit enable=1, Macro0, CA PI delay=33
3156 12:14:13.861098
3157 12:14:13.864037 [CBTSetCACLKResult] CA Dly = 33
3158 12:14:13.864112 CS Dly: 8 (0~41)
3159 12:14:13.864173
3160 12:14:13.867638 ----->DramcWriteLeveling(PI) begin...
3161 12:14:13.867705 ==
3162 12:14:13.870768 Dram Type= 6, Freq= 0, CH_1, rank 0
3163 12:14:13.877589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 12:14:13.877668 ==
3165 12:14:13.880883 Write leveling (Byte 0): 25 => 25
3166 12:14:13.884064 Write leveling (Byte 1): 26 => 26
3167 12:14:13.884163 DramcWriteLeveling(PI) end<-----
3168 12:14:13.884252
3169 12:14:13.887471 ==
3170 12:14:13.887543 Dram Type= 6, Freq= 0, CH_1, rank 0
3171 12:14:13.894312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3172 12:14:13.894388 ==
3173 12:14:13.897506 [Gating] SW mode calibration
3174 12:14:13.904214 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3175 12:14:13.907468 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3176 12:14:13.913847 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3177 12:14:13.917819 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 12:14:13.920884 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 12:14:13.927534 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 12:14:13.931044 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 12:14:13.934404 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 12:14:13.941183 0 15 24 | B1->B0 | 3232 2727 | 1 0 | (1 0) (0 0)
3183 12:14:13.944422 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3184 12:14:13.947252 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 12:14:13.953691 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 12:14:13.957144 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 12:14:13.960363 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 12:14:13.967545 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 12:14:13.970724 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 12:14:13.974062 1 0 24 | B1->B0 | 3333 4040 | 1 1 | (0 0) (0 0)
3191 12:14:13.977472 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 12:14:13.983897 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 12:14:13.987067 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 12:14:13.990648 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 12:14:13.997365 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 12:14:14.000980 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 12:14:14.003947 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 12:14:14.010872 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3199 12:14:14.013851 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3200 12:14:14.017810 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 12:14:14.023874 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 12:14:14.027133 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 12:14:14.030721 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 12:14:14.037182 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 12:14:14.040655 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 12:14:14.044254 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 12:14:14.050626 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 12:14:14.054180 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 12:14:14.057324 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 12:14:14.060788 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 12:14:14.067603 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 12:14:14.070820 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 12:14:14.074018 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 12:14:14.081151 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3215 12:14:14.084377 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3216 12:14:14.087472 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 12:14:14.090671 Total UI for P1: 0, mck2ui 16
3218 12:14:14.094440 best dqsien dly found for B0: ( 1, 3, 26)
3219 12:14:14.097637 Total UI for P1: 0, mck2ui 16
3220 12:14:14.100780 best dqsien dly found for B1: ( 1, 3, 26)
3221 12:14:14.104221 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3222 12:14:14.107781 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3223 12:14:14.107858
3224 12:14:14.111626 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3225 12:14:14.117975 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3226 12:14:14.118052 [Gating] SW calibration Done
3227 12:14:14.118114 ==
3228 12:14:14.121271 Dram Type= 6, Freq= 0, CH_1, rank 0
3229 12:14:14.127896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3230 12:14:14.127972 ==
3231 12:14:14.128035 RX Vref Scan: 0
3232 12:14:14.128098
3233 12:14:14.131067 RX Vref 0 -> 0, step: 1
3234 12:14:14.131136
3235 12:14:14.134155 RX Delay -40 -> 252, step: 8
3236 12:14:14.137773 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3237 12:14:14.141083 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3238 12:14:14.144036 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3239 12:14:14.150854 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3240 12:14:14.154416 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3241 12:14:14.158021 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3242 12:14:14.160975 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3243 12:14:14.164712 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3244 12:14:14.167870 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3245 12:14:14.174755 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3246 12:14:14.177759 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3247 12:14:14.181011 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3248 12:14:14.184991 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3249 12:14:14.191100 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3250 12:14:14.194697 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3251 12:14:14.197685 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3252 12:14:14.197779 ==
3253 12:14:14.201661 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 12:14:14.204837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 12:14:14.204924 ==
3256 12:14:14.207894 DQS Delay:
3257 12:14:14.207972 DQS0 = 0, DQS1 = 0
3258 12:14:14.211729 DQM Delay:
3259 12:14:14.211805 DQM0 = 120, DQM1 = 116
3260 12:14:14.211866 DQ Delay:
3261 12:14:14.214420 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3262 12:14:14.217834 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3263 12:14:14.224590 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3264 12:14:14.228008 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3265 12:14:14.228089
3266 12:14:14.228150
3267 12:14:14.228208 ==
3268 12:14:14.231462 Dram Type= 6, Freq= 0, CH_1, rank 0
3269 12:14:14.234517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3270 12:14:14.234591 ==
3271 12:14:14.234652
3272 12:14:14.234709
3273 12:14:14.238099 TX Vref Scan disable
3274 12:14:14.241093 == TX Byte 0 ==
3275 12:14:14.244458 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3276 12:14:14.247729 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3277 12:14:14.247812 == TX Byte 1 ==
3278 12:14:14.254720 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3279 12:14:14.257729 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3280 12:14:14.257812 ==
3281 12:14:14.261283 Dram Type= 6, Freq= 0, CH_1, rank 0
3282 12:14:14.264369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3283 12:14:14.264456 ==
3284 12:14:14.277380 TX Vref=22, minBit 11, minWin=24, winSum=412
3285 12:14:14.280681 TX Vref=24, minBit 3, minWin=25, winSum=414
3286 12:14:14.283766 TX Vref=26, minBit 1, minWin=26, winSum=424
3287 12:14:14.287116 TX Vref=28, minBit 9, minWin=25, winSum=429
3288 12:14:14.290862 TX Vref=30, minBit 2, minWin=26, winSum=426
3289 12:14:14.297003 TX Vref=32, minBit 10, minWin=26, winSum=428
3290 12:14:14.300449 [TxChooseVref] Worse bit 10, Min win 26, Win sum 428, Final Vref 32
3291 12:14:14.300553
3292 12:14:14.303754 Final TX Range 1 Vref 32
3293 12:14:14.303839
3294 12:14:14.303905 ==
3295 12:14:14.307382 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 12:14:14.310674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 12:14:14.310756 ==
3298 12:14:14.313675
3299 12:14:14.313749
3300 12:14:14.313810 TX Vref Scan disable
3301 12:14:14.317376 == TX Byte 0 ==
3302 12:14:14.320392 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3303 12:14:14.324136 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3304 12:14:14.327244 == TX Byte 1 ==
3305 12:14:14.330953 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3306 12:14:14.334064 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3307 12:14:14.337008
3308 12:14:14.337084 [DATLAT]
3309 12:14:14.337146 Freq=1200, CH1 RK0
3310 12:14:14.337210
3311 12:14:14.340604 DATLAT Default: 0xd
3312 12:14:14.340677 0, 0xFFFF, sum = 0
3313 12:14:14.343652 1, 0xFFFF, sum = 0
3314 12:14:14.343722 2, 0xFFFF, sum = 0
3315 12:14:14.347451 3, 0xFFFF, sum = 0
3316 12:14:14.347546 4, 0xFFFF, sum = 0
3317 12:14:14.350505 5, 0xFFFF, sum = 0
3318 12:14:14.353848 6, 0xFFFF, sum = 0
3319 12:14:14.353923 7, 0xFFFF, sum = 0
3320 12:14:14.357285 8, 0xFFFF, sum = 0
3321 12:14:14.357375 9, 0xFFFF, sum = 0
3322 12:14:14.360592 10, 0xFFFF, sum = 0
3323 12:14:14.360662 11, 0xFFFF, sum = 0
3324 12:14:14.363783 12, 0x0, sum = 1
3325 12:14:14.363852 13, 0x0, sum = 2
3326 12:14:14.367716 14, 0x0, sum = 3
3327 12:14:14.367790 15, 0x0, sum = 4
3328 12:14:14.367850 best_step = 13
3329 12:14:14.367906
3330 12:14:14.370522 ==
3331 12:14:14.373617 Dram Type= 6, Freq= 0, CH_1, rank 0
3332 12:14:14.377334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3333 12:14:14.377418 ==
3334 12:14:14.377482 RX Vref Scan: 1
3335 12:14:14.377541
3336 12:14:14.380832 Set Vref Range= 32 -> 127
3337 12:14:14.380912
3338 12:14:14.383925 RX Vref 32 -> 127, step: 1
3339 12:14:14.384020
3340 12:14:14.387121 RX Delay -5 -> 252, step: 4
3341 12:14:14.387190
3342 12:14:14.390872 Set Vref, RX VrefLevel [Byte0]: 32
3343 12:14:14.393587 [Byte1]: 32
3344 12:14:14.393656
3345 12:14:14.397051 Set Vref, RX VrefLevel [Byte0]: 33
3346 12:14:14.400810 [Byte1]: 33
3347 12:14:14.400880
3348 12:14:14.403987 Set Vref, RX VrefLevel [Byte0]: 34
3349 12:14:14.407424 [Byte1]: 34
3350 12:14:14.411317
3351 12:14:14.411392 Set Vref, RX VrefLevel [Byte0]: 35
3352 12:14:14.414252 [Byte1]: 35
3353 12:14:14.419191
3354 12:14:14.419267 Set Vref, RX VrefLevel [Byte0]: 36
3355 12:14:14.422202 [Byte1]: 36
3356 12:14:14.426985
3357 12:14:14.427057 Set Vref, RX VrefLevel [Byte0]: 37
3358 12:14:14.430039 [Byte1]: 37
3359 12:14:14.434719
3360 12:14:14.434790 Set Vref, RX VrefLevel [Byte0]: 38
3361 12:14:14.437889 [Byte1]: 38
3362 12:14:14.442960
3363 12:14:14.443032 Set Vref, RX VrefLevel [Byte0]: 39
3364 12:14:14.446022 [Byte1]: 39
3365 12:14:14.450710
3366 12:14:14.450783 Set Vref, RX VrefLevel [Byte0]: 40
3367 12:14:14.453601 [Byte1]: 40
3368 12:14:14.458653
3369 12:14:14.458720 Set Vref, RX VrefLevel [Byte0]: 41
3370 12:14:14.461677 [Byte1]: 41
3371 12:14:14.466128
3372 12:14:14.466195 Set Vref, RX VrefLevel [Byte0]: 42
3373 12:14:14.469740 [Byte1]: 42
3374 12:14:14.474143
3375 12:14:14.474216 Set Vref, RX VrefLevel [Byte0]: 43
3376 12:14:14.477216 [Byte1]: 43
3377 12:14:14.481733
3378 12:14:14.481803 Set Vref, RX VrefLevel [Byte0]: 44
3379 12:14:14.485590 [Byte1]: 44
3380 12:14:14.489714
3381 12:14:14.489787 Set Vref, RX VrefLevel [Byte0]: 45
3382 12:14:14.493255 [Byte1]: 45
3383 12:14:14.497746
3384 12:14:14.497832 Set Vref, RX VrefLevel [Byte0]: 46
3385 12:14:14.500786 [Byte1]: 46
3386 12:14:14.506052
3387 12:14:14.506133 Set Vref, RX VrefLevel [Byte0]: 47
3388 12:14:14.509121 [Byte1]: 47
3389 12:14:14.513238
3390 12:14:14.513318 Set Vref, RX VrefLevel [Byte0]: 48
3391 12:14:14.516589 [Byte1]: 48
3392 12:14:14.521173
3393 12:14:14.521254 Set Vref, RX VrefLevel [Byte0]: 49
3394 12:14:14.524441 [Byte1]: 49
3395 12:14:14.528880
3396 12:14:14.528961 Set Vref, RX VrefLevel [Byte0]: 50
3397 12:14:14.532529 [Byte1]: 50
3398 12:14:14.536976
3399 12:14:14.537057 Set Vref, RX VrefLevel [Byte0]: 51
3400 12:14:14.540162 [Byte1]: 51
3401 12:14:14.545043
3402 12:14:14.545123 Set Vref, RX VrefLevel [Byte0]: 52
3403 12:14:14.548091 [Byte1]: 52
3404 12:14:14.552508
3405 12:14:14.552589 Set Vref, RX VrefLevel [Byte0]: 53
3406 12:14:14.556167 [Byte1]: 53
3407 12:14:14.560523
3408 12:14:14.560604 Set Vref, RX VrefLevel [Byte0]: 54
3409 12:14:14.563849 [Byte1]: 54
3410 12:14:14.568184
3411 12:14:14.568265 Set Vref, RX VrefLevel [Byte0]: 55
3412 12:14:14.571933 [Byte1]: 55
3413 12:14:14.576276
3414 12:14:14.576413 Set Vref, RX VrefLevel [Byte0]: 56
3415 12:14:14.579385 [Byte1]: 56
3416 12:14:14.584000
3417 12:14:14.584099 Set Vref, RX VrefLevel [Byte0]: 57
3418 12:14:14.587132 [Byte1]: 57
3419 12:14:14.591806
3420 12:14:14.591888 Set Vref, RX VrefLevel [Byte0]: 58
3421 12:14:14.595321 [Byte1]: 58
3422 12:14:14.599690
3423 12:14:14.599772 Set Vref, RX VrefLevel [Byte0]: 59
3424 12:14:14.602971 [Byte1]: 59
3425 12:14:14.607685
3426 12:14:14.607766 Set Vref, RX VrefLevel [Byte0]: 60
3427 12:14:14.610999 [Byte1]: 60
3428 12:14:14.615594
3429 12:14:14.615675 Set Vref, RX VrefLevel [Byte0]: 61
3430 12:14:14.618755 [Byte1]: 61
3431 12:14:14.623385
3432 12:14:14.623466 Set Vref, RX VrefLevel [Byte0]: 62
3433 12:14:14.626702 [Byte1]: 62
3434 12:14:14.631126
3435 12:14:14.631207 Set Vref, RX VrefLevel [Byte0]: 63
3436 12:14:14.634681 [Byte1]: 63
3437 12:14:14.638718
3438 12:14:14.638798 Set Vref, RX VrefLevel [Byte0]: 64
3439 12:14:14.642098 [Byte1]: 64
3440 12:14:14.646844
3441 12:14:14.646924 Set Vref, RX VrefLevel [Byte0]: 65
3442 12:14:14.650243 [Byte1]: 65
3443 12:14:14.654995
3444 12:14:14.655075 Set Vref, RX VrefLevel [Byte0]: 66
3445 12:14:14.658064 [Byte1]: 66
3446 12:14:14.662691
3447 12:14:14.662798 Set Vref, RX VrefLevel [Byte0]: 67
3448 12:14:14.665835 [Byte1]: 67
3449 12:14:14.670581
3450 12:14:14.670666 Set Vref, RX VrefLevel [Byte0]: 68
3451 12:14:14.673726 [Byte1]: 68
3452 12:14:14.678080
3453 12:14:14.678164 Set Vref, RX VrefLevel [Byte0]: 69
3454 12:14:14.681282 [Byte1]: 69
3455 12:14:14.686222
3456 12:14:14.686307 Final RX Vref Byte 0 = 54 to rank0
3457 12:14:14.689310 Final RX Vref Byte 1 = 48 to rank0
3458 12:14:14.692646 Final RX Vref Byte 0 = 54 to rank1
3459 12:14:14.696490 Final RX Vref Byte 1 = 48 to rank1==
3460 12:14:14.699779 Dram Type= 6, Freq= 0, CH_1, rank 0
3461 12:14:14.702887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3462 12:14:14.706073 ==
3463 12:14:14.706158 DQS Delay:
3464 12:14:14.706244 DQS0 = 0, DQS1 = 0
3465 12:14:14.709825 DQM Delay:
3466 12:14:14.709910 DQM0 = 120, DQM1 = 116
3467 12:14:14.712790 DQ Delay:
3468 12:14:14.716219 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3469 12:14:14.719551 DQ4 =118, DQ5 =130, DQ6 =130, DQ7 =120
3470 12:14:14.722711 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3471 12:14:14.726265 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3472 12:14:14.726349
3473 12:14:14.726434
3474 12:14:14.733162 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3475 12:14:14.736088 CH1 RK0: MR19=404, MR18=13
3476 12:14:14.743152 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3477 12:14:14.743237
3478 12:14:14.746665 ----->DramcWriteLeveling(PI) begin...
3479 12:14:14.746751 ==
3480 12:14:14.750065 Dram Type= 6, Freq= 0, CH_1, rank 1
3481 12:14:14.753522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3482 12:14:14.753607 ==
3483 12:14:14.756290 Write leveling (Byte 0): 26 => 26
3484 12:14:14.759682 Write leveling (Byte 1): 29 => 29
3485 12:14:14.763105 DramcWriteLeveling(PI) end<-----
3486 12:14:14.763190
3487 12:14:14.763275 ==
3488 12:14:14.766248 Dram Type= 6, Freq= 0, CH_1, rank 1
3489 12:14:14.769897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3490 12:14:14.770019 ==
3491 12:14:14.772731 [Gating] SW mode calibration
3492 12:14:14.779419 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3493 12:14:14.786386 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3494 12:14:14.789524 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 12:14:14.796254 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 12:14:14.799900 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 12:14:14.802963 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3498 12:14:14.809454 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 12:14:14.813122 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3500 12:14:14.816246 0 15 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 0) (0 1)
3501 12:14:14.823000 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 12:14:14.825981 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 12:14:14.829652 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 12:14:14.832571 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 12:14:14.839629 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3506 12:14:14.843134 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 12:14:14.846111 1 0 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
3508 12:14:14.853127 1 0 24 | B1->B0 | 4646 3131 | 0 0 | (0 0) (0 0)
3509 12:14:14.856690 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 12:14:14.859342 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 12:14:14.866088 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 12:14:14.869589 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 12:14:14.872888 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 12:14:14.879113 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 12:14:14.882852 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3516 12:14:14.886005 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3517 12:14:14.892864 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 12:14:14.896065 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 12:14:14.899116 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 12:14:14.905905 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 12:14:14.909632 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 12:14:14.912774 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 12:14:14.919243 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 12:14:14.922748 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 12:14:14.925894 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 12:14:14.932192 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 12:14:14.935816 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 12:14:14.939017 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 12:14:14.945707 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 12:14:14.949092 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 12:14:14.952807 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 12:14:14.958759 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3533 12:14:14.962403 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3534 12:14:14.965755 Total UI for P1: 0, mck2ui 16
3535 12:14:14.969201 best dqsien dly found for B1: ( 1, 3, 24)
3536 12:14:14.972474 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 12:14:14.975479 Total UI for P1: 0, mck2ui 16
3538 12:14:14.978995 best dqsien dly found for B0: ( 1, 3, 26)
3539 12:14:14.982834 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3540 12:14:14.985624 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3541 12:14:14.985706
3542 12:14:14.989158 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3543 12:14:14.992116 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3544 12:14:14.995391 [Gating] SW calibration Done
3545 12:14:14.995474 ==
3546 12:14:14.999021 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 12:14:15.005553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 12:14:15.005636 ==
3549 12:14:15.005701 RX Vref Scan: 0
3550 12:14:15.005761
3551 12:14:15.009058 RX Vref 0 -> 0, step: 1
3552 12:14:15.009140
3553 12:14:15.012032 RX Delay -40 -> 252, step: 8
3554 12:14:15.015816 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3555 12:14:15.018888 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3556 12:14:15.022212 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3557 12:14:15.028952 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3558 12:14:15.032087 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3559 12:14:15.035332 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3560 12:14:15.038957 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3561 12:14:15.041982 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3562 12:14:15.045280 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3563 12:14:15.051764 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3564 12:14:15.055228 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3565 12:14:15.058877 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3566 12:14:15.061831 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3567 12:14:15.068648 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3568 12:14:15.071833 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3569 12:14:15.075256 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3570 12:14:15.075338 ==
3571 12:14:15.078745 Dram Type= 6, Freq= 0, CH_1, rank 1
3572 12:14:15.082167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3573 12:14:15.082252 ==
3574 12:14:15.085370 DQS Delay:
3575 12:14:15.085452 DQS0 = 0, DQS1 = 0
3576 12:14:15.085518 DQM Delay:
3577 12:14:15.088811 DQM0 = 120, DQM1 = 119
3578 12:14:15.088893 DQ Delay:
3579 12:14:15.091775 DQ0 =123, DQ1 =119, DQ2 =107, DQ3 =119
3580 12:14:15.095206 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3581 12:14:15.102111 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3582 12:14:15.105363 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =127
3583 12:14:15.105445
3584 12:14:15.105509
3585 12:14:15.105568 ==
3586 12:14:15.108236 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 12:14:15.112406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 12:14:15.112489 ==
3589 12:14:15.112554
3590 12:14:15.112614
3591 12:14:15.115308 TX Vref Scan disable
3592 12:14:15.118867 == TX Byte 0 ==
3593 12:14:15.122039 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3594 12:14:15.125105 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3595 12:14:15.128959 == TX Byte 1 ==
3596 12:14:15.132019 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3597 12:14:15.135115 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3598 12:14:15.135197 ==
3599 12:14:15.138740 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 12:14:15.141828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 12:14:15.141910 ==
3602 12:14:15.155070 TX Vref=22, minBit 1, minWin=26, winSum=424
3603 12:14:15.158551 TX Vref=24, minBit 0, minWin=26, winSum=425
3604 12:14:15.161625 TX Vref=26, minBit 10, minWin=25, winSum=432
3605 12:14:15.165309 TX Vref=28, minBit 9, minWin=26, winSum=432
3606 12:14:15.168605 TX Vref=30, minBit 1, minWin=27, winSum=439
3607 12:14:15.174716 TX Vref=32, minBit 9, minWin=26, winSum=434
3608 12:14:15.178114 [TxChooseVref] Worse bit 1, Min win 27, Win sum 439, Final Vref 30
3609 12:14:15.178199
3610 12:14:15.181709 Final TX Range 1 Vref 30
3611 12:14:15.181791
3612 12:14:15.181855 ==
3613 12:14:15.184646 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 12:14:15.188015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 12:14:15.191690 ==
3616 12:14:15.191772
3617 12:14:15.191836
3618 12:14:15.191895 TX Vref Scan disable
3619 12:14:15.194943 == TX Byte 0 ==
3620 12:14:15.198409 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3621 12:14:15.204490 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3622 12:14:15.204572 == TX Byte 1 ==
3623 12:14:15.208166 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3624 12:14:15.214581 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3625 12:14:15.214664
3626 12:14:15.214730 [DATLAT]
3627 12:14:15.214790 Freq=1200, CH1 RK1
3628 12:14:15.214847
3629 12:14:15.217810 DATLAT Default: 0xd
3630 12:14:15.217891 0, 0xFFFF, sum = 0
3631 12:14:15.221385 1, 0xFFFF, sum = 0
3632 12:14:15.224517 2, 0xFFFF, sum = 0
3633 12:14:15.224603 3, 0xFFFF, sum = 0
3634 12:14:15.227581 4, 0xFFFF, sum = 0
3635 12:14:15.227667 5, 0xFFFF, sum = 0
3636 12:14:15.231057 6, 0xFFFF, sum = 0
3637 12:14:15.231143 7, 0xFFFF, sum = 0
3638 12:14:15.234624 8, 0xFFFF, sum = 0
3639 12:14:15.234710 9, 0xFFFF, sum = 0
3640 12:14:15.237771 10, 0xFFFF, sum = 0
3641 12:14:15.237856 11, 0xFFFF, sum = 0
3642 12:14:15.241285 12, 0x0, sum = 1
3643 12:14:15.241371 13, 0x0, sum = 2
3644 12:14:15.244419 14, 0x0, sum = 3
3645 12:14:15.244505 15, 0x0, sum = 4
3646 12:14:15.247326 best_step = 13
3647 12:14:15.247410
3648 12:14:15.247495 ==
3649 12:14:15.251174 Dram Type= 6, Freq= 0, CH_1, rank 1
3650 12:14:15.254363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3651 12:14:15.254449 ==
3652 12:14:15.257486 RX Vref Scan: 0
3653 12:14:15.257570
3654 12:14:15.257656 RX Vref 0 -> 0, step: 1
3655 12:14:15.257736
3656 12:14:15.260559 RX Delay -5 -> 252, step: 4
3657 12:14:15.267548 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3658 12:14:15.270595 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3659 12:14:15.274154 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3660 12:14:15.277031 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3661 12:14:15.280724 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3662 12:14:15.287154 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3663 12:14:15.290422 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3664 12:14:15.294167 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3665 12:14:15.297090 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3666 12:14:15.300911 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3667 12:14:15.306902 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3668 12:14:15.310719 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3669 12:14:15.313690 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3670 12:14:15.316796 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3671 12:14:15.320671 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3672 12:14:15.326976 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3673 12:14:15.327061 ==
3674 12:14:15.330432 Dram Type= 6, Freq= 0, CH_1, rank 1
3675 12:14:15.333508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3676 12:14:15.333593 ==
3677 12:14:15.333680 DQS Delay:
3678 12:14:15.336759 DQS0 = 0, DQS1 = 0
3679 12:14:15.336844 DQM Delay:
3680 12:14:15.340570 DQM0 = 120, DQM1 = 116
3681 12:14:15.340655 DQ Delay:
3682 12:14:15.343317 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3683 12:14:15.346906 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3684 12:14:15.350009 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110
3685 12:14:15.353600 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3686 12:14:15.356715
3687 12:14:15.356798
3688 12:14:15.363514 [DQSOSCAuto] RK1, (LSB)MR18= 0xeeb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3689 12:14:15.366642 CH1 RK1: MR19=403, MR18=EEB
3690 12:14:15.373674 CH1_RK1: MR19=0x403, MR18=0xEEB, DQSOSC=404, MR23=63, INC=40, DEC=26
3691 12:14:15.373757 [RxdqsGatingPostProcess] freq 1200
3692 12:14:15.379852 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3693 12:14:15.383437 best DQS0 dly(2T, 0.5T) = (0, 11)
3694 12:14:15.386777 best DQS1 dly(2T, 0.5T) = (0, 11)
3695 12:14:15.390100 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3696 12:14:15.393317 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3697 12:14:15.396273 best DQS0 dly(2T, 0.5T) = (0, 11)
3698 12:14:15.400103 best DQS1 dly(2T, 0.5T) = (0, 11)
3699 12:14:15.403204 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3700 12:14:15.406927 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3701 12:14:15.410044 Pre-setting of DQS Precalculation
3702 12:14:15.413058 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3703 12:14:15.419793 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3704 12:14:15.426459 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3705 12:14:15.430196
3706 12:14:15.430278
3707 12:14:15.430344 [Calibration Summary] 2400 Mbps
3708 12:14:15.433271 CH 0, Rank 0
3709 12:14:15.433353 SW Impedance : PASS
3710 12:14:15.436408 DUTY Scan : NO K
3711 12:14:15.440194 ZQ Calibration : PASS
3712 12:14:15.440306 Jitter Meter : NO K
3713 12:14:15.443216 CBT Training : PASS
3714 12:14:15.446579 Write leveling : PASS
3715 12:14:15.446661 RX DQS gating : PASS
3716 12:14:15.449497 RX DQ/DQS(RDDQC) : PASS
3717 12:14:15.453244 TX DQ/DQS : PASS
3718 12:14:15.453327 RX DATLAT : PASS
3719 12:14:15.456134 RX DQ/DQS(Engine): PASS
3720 12:14:15.459453 TX OE : NO K
3721 12:14:15.459535 All Pass.
3722 12:14:15.459600
3723 12:14:15.459659 CH 0, Rank 1
3724 12:14:15.463038 SW Impedance : PASS
3725 12:14:15.466203 DUTY Scan : NO K
3726 12:14:15.466285 ZQ Calibration : PASS
3727 12:14:15.469918 Jitter Meter : NO K
3728 12:14:15.473216 CBT Training : PASS
3729 12:14:15.473298 Write leveling : PASS
3730 12:14:15.476328 RX DQS gating : PASS
3731 12:14:15.479484 RX DQ/DQS(RDDQC) : PASS
3732 12:14:15.479565 TX DQ/DQS : PASS
3733 12:14:15.483096 RX DATLAT : PASS
3734 12:14:15.483177 RX DQ/DQS(Engine): PASS
3735 12:14:15.486225 TX OE : NO K
3736 12:14:15.486307 All Pass.
3737 12:14:15.486372
3738 12:14:15.489330 CH 1, Rank 0
3739 12:14:15.489412 SW Impedance : PASS
3740 12:14:15.493405 DUTY Scan : NO K
3741 12:14:15.496247 ZQ Calibration : PASS
3742 12:14:15.496368 Jitter Meter : NO K
3743 12:14:15.499841 CBT Training : PASS
3744 12:14:15.503002 Write leveling : PASS
3745 12:14:15.503084 RX DQS gating : PASS
3746 12:14:15.505953 RX DQ/DQS(RDDQC) : PASS
3747 12:14:15.509583 TX DQ/DQS : PASS
3748 12:14:15.509666 RX DATLAT : PASS
3749 12:14:15.512787 RX DQ/DQS(Engine): PASS
3750 12:14:15.516036 TX OE : NO K
3751 12:14:15.516118 All Pass.
3752 12:14:15.516181
3753 12:14:15.516241 CH 1, Rank 1
3754 12:14:15.519827 SW Impedance : PASS
3755 12:14:15.522930 DUTY Scan : NO K
3756 12:14:15.523012 ZQ Calibration : PASS
3757 12:14:15.525908 Jitter Meter : NO K
3758 12:14:15.529519 CBT Training : PASS
3759 12:14:15.529602 Write leveling : PASS
3760 12:14:15.533104 RX DQS gating : PASS
3761 12:14:15.533186 RX DQ/DQS(RDDQC) : PASS
3762 12:14:15.536458 TX DQ/DQS : PASS
3763 12:14:15.539499 RX DATLAT : PASS
3764 12:14:15.539580 RX DQ/DQS(Engine): PASS
3765 12:14:15.542840 TX OE : NO K
3766 12:14:15.542921 All Pass.
3767 12:14:15.542986
3768 12:14:15.546140 DramC Write-DBI off
3769 12:14:15.549600 PER_BANK_REFRESH: Hybrid Mode
3770 12:14:15.549682 TX_TRACKING: ON
3771 12:14:15.559411 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3772 12:14:15.562442 [FAST_K] Save calibration result to emmc
3773 12:14:15.565951 dramc_set_vcore_voltage set vcore to 650000
3774 12:14:15.569330 Read voltage for 600, 5
3775 12:14:15.569412 Vio18 = 0
3776 12:14:15.569476 Vcore = 650000
3777 12:14:15.572681 Vdram = 0
3778 12:14:15.572762 Vddq = 0
3779 12:14:15.572826 Vmddr = 0
3780 12:14:15.579128 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3781 12:14:15.582785 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3782 12:14:15.585908 MEM_TYPE=3, freq_sel=19
3783 12:14:15.589089 sv_algorithm_assistance_LP4_1600
3784 12:14:15.592772 ============ PULL DRAM RESETB DOWN ============
3785 12:14:15.599078 ========== PULL DRAM RESETB DOWN end =========
3786 12:14:15.602223 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3787 12:14:15.605952 ===================================
3788 12:14:15.608868 LPDDR4 DRAM CONFIGURATION
3789 12:14:15.612507 ===================================
3790 12:14:15.612585 EX_ROW_EN[0] = 0x0
3791 12:14:15.615714 EX_ROW_EN[1] = 0x0
3792 12:14:15.615785 LP4Y_EN = 0x0
3793 12:14:15.619003 WORK_FSP = 0x0
3794 12:14:15.619085 WL = 0x2
3795 12:14:15.622820 RL = 0x2
3796 12:14:15.622901 BL = 0x2
3797 12:14:15.626092 RPST = 0x0
3798 12:14:15.626174 RD_PRE = 0x0
3799 12:14:15.629128 WR_PRE = 0x1
3800 12:14:15.629211 WR_PST = 0x0
3801 12:14:15.632738 DBI_WR = 0x0
3802 12:14:15.632820 DBI_RD = 0x0
3803 12:14:15.635993 OTF = 0x1
3804 12:14:15.639178 ===================================
3805 12:14:15.642377 ===================================
3806 12:14:15.642460 ANA top config
3807 12:14:15.646180 ===================================
3808 12:14:15.649166 DLL_ASYNC_EN = 0
3809 12:14:15.652279 ALL_SLAVE_EN = 1
3810 12:14:15.655349 NEW_RANK_MODE = 1
3811 12:14:15.658946 DLL_IDLE_MODE = 1
3812 12:14:15.659029 LP45_APHY_COMB_EN = 1
3813 12:14:15.662044 TX_ODT_DIS = 1
3814 12:14:15.665522 NEW_8X_MODE = 1
3815 12:14:15.669141 ===================================
3816 12:14:15.672172 ===================================
3817 12:14:15.675208 data_rate = 1200
3818 12:14:15.678538 CKR = 1
3819 12:14:15.678620 DQ_P2S_RATIO = 8
3820 12:14:15.682312 ===================================
3821 12:14:15.685703 CA_P2S_RATIO = 8
3822 12:14:15.688567 DQ_CA_OPEN = 0
3823 12:14:15.691939 DQ_SEMI_OPEN = 0
3824 12:14:15.695967 CA_SEMI_OPEN = 0
3825 12:14:15.698829 CA_FULL_RATE = 0
3826 12:14:15.698911 DQ_CKDIV4_EN = 1
3827 12:14:15.702545 CA_CKDIV4_EN = 1
3828 12:14:15.705562 CA_PREDIV_EN = 0
3829 12:14:15.709191 PH8_DLY = 0
3830 12:14:15.712491 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3831 12:14:15.712573 DQ_AAMCK_DIV = 4
3832 12:14:15.715525 CA_AAMCK_DIV = 4
3833 12:14:15.719190 CA_ADMCK_DIV = 4
3834 12:14:15.722033 DQ_TRACK_CA_EN = 0
3835 12:14:15.725690 CA_PICK = 600
3836 12:14:15.728699 CA_MCKIO = 600
3837 12:14:15.731881 MCKIO_SEMI = 0
3838 12:14:15.731963 PLL_FREQ = 2288
3839 12:14:15.735520 DQ_UI_PI_RATIO = 32
3840 12:14:15.738576 CA_UI_PI_RATIO = 0
3841 12:14:15.741703 ===================================
3842 12:14:15.745516 ===================================
3843 12:14:15.748547 memory_type:LPDDR4
3844 12:14:15.751710 GP_NUM : 10
3845 12:14:15.751792 SRAM_EN : 1
3846 12:14:15.755529 MD32_EN : 0
3847 12:14:15.758673 ===================================
3848 12:14:15.758755 [ANA_INIT] >>>>>>>>>>>>>>
3849 12:14:15.762380 <<<<<< [CONFIGURE PHASE]: ANA_TX
3850 12:14:15.765140 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3851 12:14:15.768519 ===================================
3852 12:14:15.771688 data_rate = 1200,PCW = 0X5800
3853 12:14:15.774974 ===================================
3854 12:14:15.778403 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3855 12:14:15.785109 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3856 12:14:15.791412 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3857 12:14:15.794921 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3858 12:14:15.798088 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3859 12:14:15.801459 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3860 12:14:15.804688 [ANA_INIT] flow start
3861 12:14:15.804771 [ANA_INIT] PLL >>>>>>>>
3862 12:14:15.808187 [ANA_INIT] PLL <<<<<<<<
3863 12:14:15.811945 [ANA_INIT] MIDPI >>>>>>>>
3864 12:14:15.812027 [ANA_INIT] MIDPI <<<<<<<<
3865 12:14:15.815196 [ANA_INIT] DLL >>>>>>>>
3866 12:14:15.818354 [ANA_INIT] flow end
3867 12:14:15.821466 ============ LP4 DIFF to SE enter ============
3868 12:14:15.825161 ============ LP4 DIFF to SE exit ============
3869 12:14:15.828129 [ANA_INIT] <<<<<<<<<<<<<
3870 12:14:15.831689 [Flow] Enable top DCM control >>>>>
3871 12:14:15.834741 [Flow] Enable top DCM control <<<<<
3872 12:14:15.837842 Enable DLL master slave shuffle
3873 12:14:15.841472 ==============================================================
3874 12:14:15.844521 Gating Mode config
3875 12:14:15.851706 ==============================================================
3876 12:14:15.851789 Config description:
3877 12:14:15.861349 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3878 12:14:15.868181 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3879 12:14:15.871296 SELPH_MODE 0: By rank 1: By Phase
3880 12:14:15.878206 ==============================================================
3881 12:14:15.881331 GAT_TRACK_EN = 1
3882 12:14:15.884471 RX_GATING_MODE = 2
3883 12:14:15.887737 RX_GATING_TRACK_MODE = 2
3884 12:14:15.891570 SELPH_MODE = 1
3885 12:14:15.894440 PICG_EARLY_EN = 1
3886 12:14:15.898241 VALID_LAT_VALUE = 1
3887 12:14:15.901745 ==============================================================
3888 12:14:15.904447 Enter into Gating configuration >>>>
3889 12:14:15.907691 Exit from Gating configuration <<<<
3890 12:14:15.911075 Enter into DVFS_PRE_config >>>>>
3891 12:14:15.924278 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3892 12:14:15.924404 Exit from DVFS_PRE_config <<<<<
3893 12:14:15.927789 Enter into PICG configuration >>>>
3894 12:14:15.931076 Exit from PICG configuration <<<<
3895 12:14:15.934242 [RX_INPUT] configuration >>>>>
3896 12:14:15.937839 [RX_INPUT] configuration <<<<<
3897 12:14:15.944270 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3898 12:14:15.947471 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3899 12:14:15.954446 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3900 12:14:15.960771 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3901 12:14:15.967745 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3902 12:14:15.973993 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3903 12:14:15.977763 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3904 12:14:15.980799 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3905 12:14:15.984065 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3906 12:14:15.990832 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3907 12:14:15.993976 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3908 12:14:15.997743 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3909 12:14:16.000941 ===================================
3910 12:14:16.003926 LPDDR4 DRAM CONFIGURATION
3911 12:14:16.007714 ===================================
3912 12:14:16.007789 EX_ROW_EN[0] = 0x0
3913 12:14:16.010859 EX_ROW_EN[1] = 0x0
3914 12:14:16.013913 LP4Y_EN = 0x0
3915 12:14:16.013990 WORK_FSP = 0x0
3916 12:14:16.017359 WL = 0x2
3917 12:14:16.017457 RL = 0x2
3918 12:14:16.020540 BL = 0x2
3919 12:14:16.020617 RPST = 0x0
3920 12:14:16.023879 RD_PRE = 0x0
3921 12:14:16.023951 WR_PRE = 0x1
3922 12:14:16.027814 WR_PST = 0x0
3923 12:14:16.027888 DBI_WR = 0x0
3924 12:14:16.030477 DBI_RD = 0x0
3925 12:14:16.030545 OTF = 0x1
3926 12:14:16.033977 ===================================
3927 12:14:16.037237 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3928 12:14:16.044106 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3929 12:14:16.047631 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3930 12:14:16.050385 ===================================
3931 12:14:16.053874 LPDDR4 DRAM CONFIGURATION
3932 12:14:16.057114 ===================================
3933 12:14:16.057213 EX_ROW_EN[0] = 0x10
3934 12:14:16.060332 EX_ROW_EN[1] = 0x0
3935 12:14:16.060415 LP4Y_EN = 0x0
3936 12:14:16.063650 WORK_FSP = 0x0
3937 12:14:16.067178 WL = 0x2
3938 12:14:16.067260 RL = 0x2
3939 12:14:16.070226 BL = 0x2
3940 12:14:16.070309 RPST = 0x0
3941 12:14:16.074162 RD_PRE = 0x0
3942 12:14:16.074246 WR_PRE = 0x1
3943 12:14:16.077276 WR_PST = 0x0
3944 12:14:16.077359 DBI_WR = 0x0
3945 12:14:16.080042 DBI_RD = 0x0
3946 12:14:16.080125 OTF = 0x1
3947 12:14:16.083874 ===================================
3948 12:14:16.090207 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3949 12:14:16.094542 nWR fixed to 30
3950 12:14:16.097686 [ModeRegInit_LP4] CH0 RK0
3951 12:14:16.097769 [ModeRegInit_LP4] CH0 RK1
3952 12:14:16.101549 [ModeRegInit_LP4] CH1 RK0
3953 12:14:16.104769 [ModeRegInit_LP4] CH1 RK1
3954 12:14:16.104852 match AC timing 17
3955 12:14:16.110969 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3956 12:14:16.114943 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3957 12:14:16.118081 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3958 12:14:16.124418 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3959 12:14:16.127764 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3960 12:14:16.127847 ==
3961 12:14:16.131195 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 12:14:16.134432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3963 12:14:16.134516 ==
3964 12:14:16.141075 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3965 12:14:16.147787 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3966 12:14:16.151243 [CA 0] Center 35 (5~66) winsize 62
3967 12:14:16.154604 [CA 1] Center 35 (5~66) winsize 62
3968 12:14:16.157602 [CA 2] Center 34 (3~65) winsize 63
3969 12:14:16.161355 [CA 3] Center 33 (2~64) winsize 63
3970 12:14:16.164214 [CA 4] Center 33 (2~64) winsize 63
3971 12:14:16.167862 [CA 5] Center 32 (2~63) winsize 62
3972 12:14:16.167960
3973 12:14:16.170951 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3974 12:14:16.171050
3975 12:14:16.174587 [CATrainingPosCal] consider 1 rank data
3976 12:14:16.177528 u2DelayCellTimex100 = 270/100 ps
3977 12:14:16.181071 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3978 12:14:16.184244 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3979 12:14:16.188154 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3980 12:14:16.191122 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3981 12:14:16.194228 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3982 12:14:16.197577 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3983 12:14:16.197681
3984 12:14:16.204096 CA PerBit enable=1, Macro0, CA PI delay=32
3985 12:14:16.204201
3986 12:14:16.207635 [CBTSetCACLKResult] CA Dly = 32
3987 12:14:16.207719 CS Dly: 4 (0~35)
3988 12:14:16.207784 ==
3989 12:14:16.210822 Dram Type= 6, Freq= 0, CH_0, rank 1
3990 12:14:16.214441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3991 12:14:16.214520 ==
3992 12:14:16.220768 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3993 12:14:16.227336 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3994 12:14:16.231274 [CA 0] Center 35 (5~66) winsize 62
3995 12:14:16.234463 [CA 1] Center 35 (5~66) winsize 62
3996 12:14:16.237259 [CA 2] Center 34 (3~65) winsize 63
3997 12:14:16.240545 [CA 3] Center 33 (3~64) winsize 62
3998 12:14:16.243874 [CA 4] Center 33 (2~64) winsize 63
3999 12:14:16.247064 [CA 5] Center 32 (1~63) winsize 63
4000 12:14:16.247135
4001 12:14:16.250687 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4002 12:14:16.250761
4003 12:14:16.253813 [CATrainingPosCal] consider 2 rank data
4004 12:14:16.256994 u2DelayCellTimex100 = 270/100 ps
4005 12:14:16.260577 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4006 12:14:16.263713 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4007 12:14:16.267527 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
4008 12:14:16.270389 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4009 12:14:16.277554 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4010 12:14:16.280631 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4011 12:14:16.280713
4012 12:14:16.283646 CA PerBit enable=1, Macro0, CA PI delay=32
4013 12:14:16.283725
4014 12:14:16.287382 [CBTSetCACLKResult] CA Dly = 32
4015 12:14:16.287465 CS Dly: 4 (0~36)
4016 12:14:16.287531
4017 12:14:16.290546 ----->DramcWriteLeveling(PI) begin...
4018 12:14:16.290630 ==
4019 12:14:16.294016 Dram Type= 6, Freq= 0, CH_0, rank 0
4020 12:14:16.300265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 12:14:16.300374 ==
4022 12:14:16.304147 Write leveling (Byte 0): 34 => 34
4023 12:14:16.304231 Write leveling (Byte 1): 31 => 31
4024 12:14:16.307317 DramcWriteLeveling(PI) end<-----
4025 12:14:16.307388
4026 12:14:16.310618 ==
4027 12:14:16.310698 Dram Type= 6, Freq= 0, CH_0, rank 0
4028 12:14:16.316663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4029 12:14:16.316747 ==
4030 12:14:16.320092 [Gating] SW mode calibration
4031 12:14:16.327486 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4032 12:14:16.330448 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4033 12:14:16.337242 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4034 12:14:16.340454 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4035 12:14:16.343725 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4036 12:14:16.350591 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
4037 12:14:16.353491 0 9 16 | B1->B0 | 3131 2323 | 1 0 | (0 1) (0 0)
4038 12:14:16.357205 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 12:14:16.363667 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 12:14:16.366709 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 12:14:16.370027 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 12:14:16.373770 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 12:14:16.380442 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 12:14:16.383504 0 10 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
4045 12:14:16.386915 0 10 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
4046 12:14:16.393472 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 12:14:16.396988 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 12:14:16.400073 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 12:14:16.406459 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 12:14:16.410392 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 12:14:16.413204 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 12:14:16.420113 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4053 12:14:16.423070 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4054 12:14:16.426578 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 12:14:16.433370 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 12:14:16.436474 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 12:14:16.440138 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 12:14:16.446612 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 12:14:16.449642 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 12:14:16.453355 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 12:14:16.459570 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 12:14:16.463375 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 12:14:16.466495 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 12:14:16.472952 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 12:14:16.476131 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 12:14:16.479434 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 12:14:16.486605 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 12:14:16.489334 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4069 12:14:16.493193 Total UI for P1: 0, mck2ui 16
4070 12:14:16.496262 best dqsien dly found for B0: ( 0, 13, 10)
4071 12:14:16.499800 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4072 12:14:16.506027 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 12:14:16.506105 Total UI for P1: 0, mck2ui 16
4074 12:14:16.509538 best dqsien dly found for B1: ( 0, 13, 16)
4075 12:14:16.516682 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4076 12:14:16.519659 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4077 12:14:16.519733
4078 12:14:16.522833 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4079 12:14:16.526448 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4080 12:14:16.529727 [Gating] SW calibration Done
4081 12:14:16.529799 ==
4082 12:14:16.532476 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 12:14:16.535849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 12:14:16.535920 ==
4085 12:14:16.539703 RX Vref Scan: 0
4086 12:14:16.539776
4087 12:14:16.539837 RX Vref 0 -> 0, step: 1
4088 12:14:16.539895
4089 12:14:16.542596 RX Delay -230 -> 252, step: 16
4090 12:14:16.549622 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4091 12:14:16.552281 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4092 12:14:16.555967 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4093 12:14:16.559219 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4094 12:14:16.562422 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4095 12:14:16.569296 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4096 12:14:16.572409 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4097 12:14:16.576207 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4098 12:14:16.579187 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4099 12:14:16.586279 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4100 12:14:16.589309 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4101 12:14:16.592562 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4102 12:14:16.596350 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4103 12:14:16.599416 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4104 12:14:16.606019 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4105 12:14:16.609400 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4106 12:14:16.609499 ==
4107 12:14:16.612245 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 12:14:16.615708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 12:14:16.615811 ==
4110 12:14:16.618880 DQS Delay:
4111 12:14:16.618957 DQS0 = 0, DQS1 = 0
4112 12:14:16.622220 DQM Delay:
4113 12:14:16.622305 DQM0 = 51, DQM1 = 46
4114 12:14:16.622371 DQ Delay:
4115 12:14:16.626060 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4116 12:14:16.629016 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4117 12:14:16.632731 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4118 12:14:16.635891 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4119 12:14:16.635965
4120 12:14:16.636060
4121 12:14:16.636138 ==
4122 12:14:16.638959 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 12:14:16.645600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 12:14:16.645685 ==
4125 12:14:16.645749
4126 12:14:16.645809
4127 12:14:16.645866 TX Vref Scan disable
4128 12:14:16.649939 == TX Byte 0 ==
4129 12:14:16.653025 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4130 12:14:16.656244 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4131 12:14:16.659622 == TX Byte 1 ==
4132 12:14:16.662964 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4133 12:14:16.669298 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4134 12:14:16.669381 ==
4135 12:14:16.672624 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 12:14:16.676200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 12:14:16.676283 ==
4138 12:14:16.676404
4139 12:14:16.676507
4140 12:14:16.679462 TX Vref Scan disable
4141 12:14:16.683052 == TX Byte 0 ==
4142 12:14:16.686010 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4143 12:14:16.689761 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4144 12:14:16.692603 == TX Byte 1 ==
4145 12:14:16.696346 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4146 12:14:16.699454 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4147 12:14:16.699536
4148 12:14:16.699600 [DATLAT]
4149 12:14:16.702510 Freq=600, CH0 RK0
4150 12:14:16.702593
4151 12:14:16.702657 DATLAT Default: 0x9
4152 12:14:16.705604 0, 0xFFFF, sum = 0
4153 12:14:16.709337 1, 0xFFFF, sum = 0
4154 12:14:16.709420 2, 0xFFFF, sum = 0
4155 12:14:16.712247 3, 0xFFFF, sum = 0
4156 12:14:16.712379 4, 0xFFFF, sum = 0
4157 12:14:16.715928 5, 0xFFFF, sum = 0
4158 12:14:16.716003 6, 0xFFFF, sum = 0
4159 12:14:16.719131 7, 0xFFFF, sum = 0
4160 12:14:16.719199 8, 0x0, sum = 1
4161 12:14:16.722714 9, 0x0, sum = 2
4162 12:14:16.722783 10, 0x0, sum = 3
4163 12:14:16.722844 11, 0x0, sum = 4
4164 12:14:16.725770 best_step = 9
4165 12:14:16.725838
4166 12:14:16.725900 ==
4167 12:14:16.729306 Dram Type= 6, Freq= 0, CH_0, rank 0
4168 12:14:16.732747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 12:14:16.732818 ==
4170 12:14:16.735980 RX Vref Scan: 1
4171 12:14:16.736079
4172 12:14:16.736142 RX Vref 0 -> 0, step: 1
4173 12:14:16.739475
4174 12:14:16.739541 RX Delay -163 -> 252, step: 8
4175 12:14:16.739600
4176 12:14:16.742428 Set Vref, RX VrefLevel [Byte0]: 55
4177 12:14:16.745742 [Byte1]: 45
4178 12:14:16.750201
4179 12:14:16.750277 Final RX Vref Byte 0 = 55 to rank0
4180 12:14:16.753529 Final RX Vref Byte 1 = 45 to rank0
4181 12:14:16.756885 Final RX Vref Byte 0 = 55 to rank1
4182 12:14:16.759960 Final RX Vref Byte 1 = 45 to rank1==
4183 12:14:16.763149 Dram Type= 6, Freq= 0, CH_0, rank 0
4184 12:14:16.769996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4185 12:14:16.770095 ==
4186 12:14:16.770160 DQS Delay:
4187 12:14:16.770224 DQS0 = 0, DQS1 = 0
4188 12:14:16.773598 DQM Delay:
4189 12:14:16.773672 DQM0 = 52, DQM1 = 45
4190 12:14:16.776831 DQ Delay:
4191 12:14:16.780080 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4192 12:14:16.780155 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =56
4193 12:14:16.783121 DQ8 =36, DQ9 =32, DQ10 =44, DQ11 =40
4194 12:14:16.789884 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4195 12:14:16.789964
4196 12:14:16.790027
4197 12:14:16.796527 [DQSOSCAuto] RK0, (LSB)MR18= 0x7063, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 388 ps
4198 12:14:16.800202 CH0 RK0: MR19=808, MR18=7063
4199 12:14:16.806354 CH0_RK0: MR19=0x808, MR18=0x7063, DQSOSC=388, MR23=63, INC=174, DEC=116
4200 12:14:16.806429
4201 12:14:16.809684 ----->DramcWriteLeveling(PI) begin...
4202 12:14:16.809756 ==
4203 12:14:16.813517 Dram Type= 6, Freq= 0, CH_0, rank 1
4204 12:14:16.816694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 12:14:16.816765 ==
4206 12:14:16.819661 Write leveling (Byte 0): 34 => 34
4207 12:14:16.823020 Write leveling (Byte 1): 30 => 30
4208 12:14:16.826275 DramcWriteLeveling(PI) end<-----
4209 12:14:16.826359
4210 12:14:16.826423 ==
4211 12:14:16.830054 Dram Type= 6, Freq= 0, CH_0, rank 1
4212 12:14:16.833461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 12:14:16.833543 ==
4214 12:14:16.836319 [Gating] SW mode calibration
4215 12:14:16.843307 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4216 12:14:16.850039 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4217 12:14:16.853706 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4218 12:14:16.856266 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4219 12:14:16.862899 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4220 12:14:16.866175 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
4221 12:14:16.869991 0 9 16 | B1->B0 | 2e2e 2424 | 0 0 | (1 1) (0 0)
4222 12:14:16.876528 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 12:14:16.879774 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 12:14:16.883059 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 12:14:16.889946 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 12:14:16.892896 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 12:14:16.896539 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 12:14:16.902812 0 10 12 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
4229 12:14:16.906604 0 10 16 | B1->B0 | 4444 4343 | 0 0 | (0 0) (0 0)
4230 12:14:16.909807 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 12:14:16.916552 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 12:14:16.919834 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 12:14:16.922782 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 12:14:16.929646 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 12:14:16.933130 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 12:14:16.936225 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4237 12:14:16.943051 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4238 12:14:16.946721 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 12:14:16.949884 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 12:14:16.952963 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 12:14:16.959934 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 12:14:16.962669 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 12:14:16.966344 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 12:14:16.972673 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 12:14:16.976505 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 12:14:16.979488 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 12:14:16.986432 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 12:14:16.989626 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 12:14:16.992818 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 12:14:16.999870 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 12:14:17.002934 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 12:14:17.006024 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4253 12:14:17.012836 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 12:14:17.012923 Total UI for P1: 0, mck2ui 16
4255 12:14:17.019355 best dqsien dly found for B0: ( 0, 13, 12)
4256 12:14:17.019440 Total UI for P1: 0, mck2ui 16
4257 12:14:17.026102 best dqsien dly found for B1: ( 0, 13, 12)
4258 12:14:17.029269 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4259 12:14:17.032586 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4260 12:14:17.032669
4261 12:14:17.035868 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4262 12:14:17.039129 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4263 12:14:17.042296 [Gating] SW calibration Done
4264 12:14:17.042405 ==
4265 12:14:17.045838 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 12:14:17.049025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 12:14:17.049110 ==
4268 12:14:17.052442 RX Vref Scan: 0
4269 12:14:17.052525
4270 12:14:17.052590 RX Vref 0 -> 0, step: 1
4271 12:14:17.052650
4272 12:14:17.055677 RX Delay -230 -> 252, step: 16
4273 12:14:17.062453 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4274 12:14:17.065800 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4275 12:14:17.068842 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4276 12:14:17.072248 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4277 12:14:17.075718 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4278 12:14:17.082411 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4279 12:14:17.086015 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4280 12:14:17.089117 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4281 12:14:17.092425 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4282 12:14:17.098713 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4283 12:14:17.102546 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4284 12:14:17.105735 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4285 12:14:17.108781 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4286 12:14:17.115245 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4287 12:14:17.118957 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4288 12:14:17.121960 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4289 12:14:17.122044 ==
4290 12:14:17.125170 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 12:14:17.129038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 12:14:17.129122 ==
4293 12:14:17.132135 DQS Delay:
4294 12:14:17.132217 DQS0 = 0, DQS1 = 0
4295 12:14:17.135310 DQM Delay:
4296 12:14:17.135392 DQM0 = 50, DQM1 = 43
4297 12:14:17.135457 DQ Delay:
4298 12:14:17.139104 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4299 12:14:17.142241 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4300 12:14:17.145310 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4301 12:14:17.148534 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4302 12:14:17.148619
4303 12:14:17.152080
4304 12:14:17.152168 ==
4305 12:14:17.155433 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 12:14:17.158737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 12:14:17.158820 ==
4308 12:14:17.158889
4309 12:14:17.158950
4310 12:14:17.161646 TX Vref Scan disable
4311 12:14:17.161740 == TX Byte 0 ==
4312 12:14:17.168497 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4313 12:14:17.171884 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4314 12:14:17.171967 == TX Byte 1 ==
4315 12:14:17.178953 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4316 12:14:17.181774 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4317 12:14:17.181858 ==
4318 12:14:17.185081 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 12:14:17.188535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 12:14:17.188619 ==
4321 12:14:17.188685
4322 12:14:17.188745
4323 12:14:17.191803 TX Vref Scan disable
4324 12:14:17.195355 == TX Byte 0 ==
4325 12:14:17.198454 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4326 12:14:17.201856 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4327 12:14:17.205278 == TX Byte 1 ==
4328 12:14:17.208728 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4329 12:14:17.211802 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4330 12:14:17.211884
4331 12:14:17.214997 [DATLAT]
4332 12:14:17.215080 Freq=600, CH0 RK1
4333 12:14:17.215146
4334 12:14:17.218764 DATLAT Default: 0x9
4335 12:14:17.218847 0, 0xFFFF, sum = 0
4336 12:14:17.221729 1, 0xFFFF, sum = 0
4337 12:14:17.221812 2, 0xFFFF, sum = 0
4338 12:14:17.225660 3, 0xFFFF, sum = 0
4339 12:14:17.225744 4, 0xFFFF, sum = 0
4340 12:14:17.228684 5, 0xFFFF, sum = 0
4341 12:14:17.228768 6, 0xFFFF, sum = 0
4342 12:14:17.231894 7, 0xFFFF, sum = 0
4343 12:14:17.231977 8, 0x0, sum = 1
4344 12:14:17.235046 9, 0x0, sum = 2
4345 12:14:17.235129 10, 0x0, sum = 3
4346 12:14:17.238210 11, 0x0, sum = 4
4347 12:14:17.238294 best_step = 9
4348 12:14:17.238358
4349 12:14:17.238417 ==
4350 12:14:17.241532 Dram Type= 6, Freq= 0, CH_0, rank 1
4351 12:14:17.245395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4352 12:14:17.248538 ==
4353 12:14:17.248620 RX Vref Scan: 0
4354 12:14:17.248685
4355 12:14:17.251667 RX Vref 0 -> 0, step: 1
4356 12:14:17.251748
4357 12:14:17.254804 RX Delay -163 -> 252, step: 8
4358 12:14:17.258655 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4359 12:14:17.261744 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4360 12:14:17.268404 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4361 12:14:17.272196 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4362 12:14:17.274916 iDelay=197, Bit 4, Center 52 (-91 ~ 196) 288
4363 12:14:17.278811 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4364 12:14:17.282111 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4365 12:14:17.285382 iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272
4366 12:14:17.292013 iDelay=197, Bit 8, Center 40 (-99 ~ 180) 280
4367 12:14:17.295030 iDelay=197, Bit 9, Center 32 (-107 ~ 172) 280
4368 12:14:17.298172 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4369 12:14:17.301983 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4370 12:14:17.308158 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4371 12:14:17.311443 iDelay=197, Bit 13, Center 48 (-91 ~ 188) 280
4372 12:14:17.315377 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4373 12:14:17.318374 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4374 12:14:17.318449 ==
4375 12:14:17.321434 Dram Type= 6, Freq= 0, CH_0, rank 1
4376 12:14:17.324999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4377 12:14:17.328256 ==
4378 12:14:17.328346 DQS Delay:
4379 12:14:17.328408 DQS0 = 0, DQS1 = 0
4380 12:14:17.331985 DQM Delay:
4381 12:14:17.332055 DQM0 = 53, DQM1 = 46
4382 12:14:17.335244 DQ Delay:
4383 12:14:17.337989 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4384 12:14:17.338061 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =60
4385 12:14:17.341881 DQ8 =40, DQ9 =32, DQ10 =48, DQ11 =40
4386 12:14:17.344934 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4387 12:14:17.348190
4388 12:14:17.348320
4389 12:14:17.354906 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f20, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4390 12:14:17.358144 CH0 RK1: MR19=808, MR18=5F20
4391 12:14:17.365129 CH0_RK1: MR19=0x808, MR18=0x5F20, DQSOSC=391, MR23=63, INC=171, DEC=114
4392 12:14:17.368065 [RxdqsGatingPostProcess] freq 600
4393 12:14:17.371270 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4394 12:14:17.375101 Pre-setting of DQS Precalculation
4395 12:14:17.381579 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4396 12:14:17.381658 ==
4397 12:14:17.384928 Dram Type= 6, Freq= 0, CH_1, rank 0
4398 12:14:17.387866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 12:14:17.387938 ==
4400 12:14:17.394558 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4401 12:14:17.397958 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4402 12:14:17.402217 [CA 0] Center 36 (5~67) winsize 63
4403 12:14:17.405465 [CA 1] Center 36 (6~67) winsize 62
4404 12:14:17.408568 [CA 2] Center 34 (4~65) winsize 62
4405 12:14:17.412107 [CA 3] Center 34 (4~65) winsize 62
4406 12:14:17.415341 [CA 4] Center 34 (4~65) winsize 62
4407 12:14:17.419056 [CA 5] Center 34 (3~65) winsize 63
4408 12:14:17.419133
4409 12:14:17.422383 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4410 12:14:17.422456
4411 12:14:17.425632 [CATrainingPosCal] consider 1 rank data
4412 12:14:17.428627 u2DelayCellTimex100 = 270/100 ps
4413 12:14:17.431776 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4414 12:14:17.438668 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4415 12:14:17.441748 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4416 12:14:17.445318 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4417 12:14:17.448616 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4418 12:14:17.452129 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4419 12:14:17.452227
4420 12:14:17.455860 CA PerBit enable=1, Macro0, CA PI delay=34
4421 12:14:17.455933
4422 12:14:17.458734 [CBTSetCACLKResult] CA Dly = 34
4423 12:14:17.458810 CS Dly: 4 (0~35)
4424 12:14:17.461935 ==
4425 12:14:17.462007 Dram Type= 6, Freq= 0, CH_1, rank 1
4426 12:14:17.468551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4427 12:14:17.468631 ==
4428 12:14:17.471960 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4429 12:14:17.478304 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4430 12:14:17.482224 [CA 0] Center 36 (6~67) winsize 62
4431 12:14:17.485332 [CA 1] Center 36 (6~67) winsize 62
4432 12:14:17.489054 [CA 2] Center 35 (5~66) winsize 62
4433 12:14:17.492000 [CA 3] Center 35 (4~66) winsize 63
4434 12:14:17.495542 [CA 4] Center 34 (4~65) winsize 62
4435 12:14:17.498612 [CA 5] Center 34 (4~65) winsize 62
4436 12:14:17.498686
4437 12:14:17.501962 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4438 12:14:17.502038
4439 12:14:17.505620 [CATrainingPosCal] consider 2 rank data
4440 12:14:17.508930 u2DelayCellTimex100 = 270/100 ps
4441 12:14:17.511877 CA0 delay=36 (6~67),Diff = 2 PI (19 cell)
4442 12:14:17.518778 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4443 12:14:17.522525 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4444 12:14:17.525503 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4445 12:14:17.528731 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4446 12:14:17.532264 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4447 12:14:17.532383
4448 12:14:17.535223 CA PerBit enable=1, Macro0, CA PI delay=34
4449 12:14:17.535296
4450 12:14:17.539105 [CBTSetCACLKResult] CA Dly = 34
4451 12:14:17.539180 CS Dly: 5 (0~38)
4452 12:14:17.539241
4453 12:14:17.542629 ----->DramcWriteLeveling(PI) begin...
4454 12:14:17.545694 ==
4455 12:14:17.548950 Dram Type= 6, Freq= 0, CH_1, rank 0
4456 12:14:17.552173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4457 12:14:17.552272 ==
4458 12:14:17.555177 Write leveling (Byte 0): 29 => 29
4459 12:14:17.559041 Write leveling (Byte 1): 29 => 29
4460 12:14:17.562168 DramcWriteLeveling(PI) end<-----
4461 12:14:17.562240
4462 12:14:17.562301 ==
4463 12:14:17.565147 Dram Type= 6, Freq= 0, CH_1, rank 0
4464 12:14:17.568745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4465 12:14:17.568820 ==
4466 12:14:17.571852 [Gating] SW mode calibration
4467 12:14:17.578494 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4468 12:14:17.585601 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4469 12:14:17.589051 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4470 12:14:17.591939 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4471 12:14:17.595182 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4472 12:14:17.602130 0 9 12 | B1->B0 | 3131 2d2d | 1 1 | (0 1) (0 0)
4473 12:14:17.605637 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 12:14:17.608403 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 12:14:17.615218 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 12:14:17.618568 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 12:14:17.622069 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 12:14:17.628573 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 12:14:17.632277 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 12:14:17.635338 0 10 12 | B1->B0 | 3535 3c3c | 0 0 | (1 1) (0 0)
4481 12:14:17.642035 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 12:14:17.645753 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 12:14:17.649032 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 12:14:17.655267 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 12:14:17.658510 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 12:14:17.662258 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 12:14:17.668674 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 12:14:17.672205 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4489 12:14:17.675335 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 12:14:17.681696 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 12:14:17.685513 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 12:14:17.688725 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 12:14:17.695461 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 12:14:17.698693 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 12:14:17.702162 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 12:14:17.708328 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 12:14:17.711688 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 12:14:17.714714 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 12:14:17.722056 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 12:14:17.725552 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 12:14:17.728271 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 12:14:17.731538 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 12:14:17.738120 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4504 12:14:17.741885 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4505 12:14:17.745144 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 12:14:17.748104 Total UI for P1: 0, mck2ui 16
4507 12:14:17.751828 best dqsien dly found for B0: ( 0, 13, 10)
4508 12:14:17.755468 Total UI for P1: 0, mck2ui 16
4509 12:14:17.758338 best dqsien dly found for B1: ( 0, 13, 10)
4510 12:14:17.761606 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4511 12:14:17.765322 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4512 12:14:17.765406
4513 12:14:17.771397 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4514 12:14:17.775063 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4515 12:14:17.778238 [Gating] SW calibration Done
4516 12:14:17.778323 ==
4517 12:14:17.781857 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 12:14:17.785141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 12:14:17.785224 ==
4520 12:14:17.785289 RX Vref Scan: 0
4521 12:14:17.785350
4522 12:14:17.788153 RX Vref 0 -> 0, step: 1
4523 12:14:17.788262
4524 12:14:17.792002 RX Delay -230 -> 252, step: 16
4525 12:14:17.795256 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4526 12:14:17.798151 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4527 12:14:17.805105 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4528 12:14:17.808337 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4529 12:14:17.811515 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4530 12:14:17.815310 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4531 12:14:17.821657 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4532 12:14:17.825066 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4533 12:14:17.828463 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4534 12:14:17.831495 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4535 12:14:17.834815 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4536 12:14:17.841225 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4537 12:14:17.844455 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4538 12:14:17.847987 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4539 12:14:17.854463 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4540 12:14:17.857841 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4541 12:14:17.857918 ==
4542 12:14:17.861185 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 12:14:17.864239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 12:14:17.864366 ==
4545 12:14:17.864429 DQS Delay:
4546 12:14:17.867885 DQS0 = 0, DQS1 = 0
4547 12:14:17.867962 DQM Delay:
4548 12:14:17.871165 DQM0 = 50, DQM1 = 45
4549 12:14:17.871242 DQ Delay:
4550 12:14:17.875029 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4551 12:14:17.878058 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4552 12:14:17.880955 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4553 12:14:17.884421 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4554 12:14:17.884495
4555 12:14:17.884561
4556 12:14:17.884619 ==
4557 12:14:17.887828 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 12:14:17.891153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 12:14:17.894020 ==
4560 12:14:17.894093
4561 12:14:17.894158
4562 12:14:17.894218 TX Vref Scan disable
4563 12:14:17.897662 == TX Byte 0 ==
4564 12:14:17.901059 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4565 12:14:17.904183 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4566 12:14:17.907326 == TX Byte 1 ==
4567 12:14:17.910634 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4568 12:14:17.917662 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4569 12:14:17.917742 ==
4570 12:14:17.920782 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 12:14:17.923905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 12:14:17.924002 ==
4573 12:14:17.924068
4574 12:14:17.924129
4575 12:14:17.927175 TX Vref Scan disable
4576 12:14:17.930851 == TX Byte 0 ==
4577 12:14:17.934096 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4578 12:14:17.937438 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4579 12:14:17.940494 == TX Byte 1 ==
4580 12:14:17.943953 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4581 12:14:17.947249 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4582 12:14:17.947353
4583 12:14:17.947459 [DATLAT]
4584 12:14:17.950520 Freq=600, CH1 RK0
4585 12:14:17.950607
4586 12:14:17.950673 DATLAT Default: 0x9
4587 12:14:17.953912 0, 0xFFFF, sum = 0
4588 12:14:17.957078 1, 0xFFFF, sum = 0
4589 12:14:17.957163 2, 0xFFFF, sum = 0
4590 12:14:17.960412 3, 0xFFFF, sum = 0
4591 12:14:17.960514 4, 0xFFFF, sum = 0
4592 12:14:17.963622 5, 0xFFFF, sum = 0
4593 12:14:17.963741 6, 0xFFFF, sum = 0
4594 12:14:17.967221 7, 0xFFFF, sum = 0
4595 12:14:17.967305 8, 0x0, sum = 1
4596 12:14:17.970715 9, 0x0, sum = 2
4597 12:14:17.970800 10, 0x0, sum = 3
4598 12:14:17.970867 11, 0x0, sum = 4
4599 12:14:17.973815 best_step = 9
4600 12:14:17.973898
4601 12:14:17.973981 ==
4602 12:14:17.976997 Dram Type= 6, Freq= 0, CH_1, rank 0
4603 12:14:17.980132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 12:14:17.980217 ==
4605 12:14:17.983916 RX Vref Scan: 1
4606 12:14:17.983999
4607 12:14:17.984065 RX Vref 0 -> 0, step: 1
4608 12:14:17.986921
4609 12:14:17.987004 RX Delay -163 -> 252, step: 8
4610 12:14:17.987069
4611 12:14:17.990658 Set Vref, RX VrefLevel [Byte0]: 54
4612 12:14:17.993731 [Byte1]: 48
4613 12:14:17.998278
4614 12:14:17.998361 Final RX Vref Byte 0 = 54 to rank0
4615 12:14:18.000977 Final RX Vref Byte 1 = 48 to rank0
4616 12:14:18.004806 Final RX Vref Byte 0 = 54 to rank1
4617 12:14:18.008041 Final RX Vref Byte 1 = 48 to rank1==
4618 12:14:18.011227 Dram Type= 6, Freq= 0, CH_1, rank 0
4619 12:14:18.017661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4620 12:14:18.017775 ==
4621 12:14:18.017871 DQS Delay:
4622 12:14:18.017961 DQS0 = 0, DQS1 = 0
4623 12:14:18.021341 DQM Delay:
4624 12:14:18.021420 DQM0 = 49, DQM1 = 44
4625 12:14:18.024924 DQ Delay:
4626 12:14:18.027600 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =48
4627 12:14:18.031309 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4628 12:14:18.031412 DQ8 =28, DQ9 =36, DQ10 =44, DQ11 =36
4629 12:14:18.037674 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4630 12:14:18.037778
4631 12:14:18.037869
4632 12:14:18.044196 [DQSOSCAuto] RK0, (LSB)MR18= 0x496f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4633 12:14:18.047911 CH1 RK0: MR19=808, MR18=496F
4634 12:14:18.054241 CH1_RK0: MR19=0x808, MR18=0x496F, DQSOSC=389, MR23=63, INC=173, DEC=115
4635 12:14:18.054320
4636 12:14:18.057931 ----->DramcWriteLeveling(PI) begin...
4637 12:14:18.058015 ==
4638 12:14:18.061483 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 12:14:18.064484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 12:14:18.064560 ==
4641 12:14:18.067862 Write leveling (Byte 0): 28 => 28
4642 12:14:18.071083 Write leveling (Byte 1): 29 => 29
4643 12:14:18.074113 DramcWriteLeveling(PI) end<-----
4644 12:14:18.074193
4645 12:14:18.074258 ==
4646 12:14:18.077642 Dram Type= 6, Freq= 0, CH_1, rank 1
4647 12:14:18.081113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 12:14:18.081218 ==
4649 12:14:18.084246 [Gating] SW mode calibration
4650 12:14:18.091154 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4651 12:14:18.097448 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4652 12:14:18.101435 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4653 12:14:18.107412 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4654 12:14:18.111089 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4655 12:14:18.114305 0 9 12 | B1->B0 | 2c2c 2e2e | 1 1 | (0 0) (1 1)
4656 12:14:18.117313 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
4657 12:14:18.123950 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 12:14:18.127373 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 12:14:18.130765 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 12:14:18.137674 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 12:14:18.140889 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 12:14:18.144350 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 12:14:18.150567 0 10 12 | B1->B0 | 3838 3939 | 0 0 | (0 0) (0 0)
4664 12:14:18.154236 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 12:14:18.157381 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 12:14:18.163880 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 12:14:18.167288 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 12:14:18.171036 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 12:14:18.177902 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 12:14:18.180932 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4671 12:14:18.184517 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4672 12:14:18.191062 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 12:14:18.194232 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 12:14:18.197403 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 12:14:18.203972 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 12:14:18.207888 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 12:14:18.210843 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 12:14:18.217657 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 12:14:18.220858 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 12:14:18.224093 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 12:14:18.227208 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 12:14:18.233814 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 12:14:18.237111 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 12:14:18.240807 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 12:14:18.247142 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 12:14:18.250401 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 12:14:18.253598 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4688 12:14:18.260331 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 12:14:18.263513 Total UI for P1: 0, mck2ui 16
4690 12:14:18.267411 best dqsien dly found for B0: ( 0, 13, 12)
4691 12:14:18.270543 Total UI for P1: 0, mck2ui 16
4692 12:14:18.273596 best dqsien dly found for B1: ( 0, 13, 12)
4693 12:14:18.277226 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4694 12:14:18.280767 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4695 12:14:18.280879
4696 12:14:18.283844 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4697 12:14:18.286753 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4698 12:14:18.290334 [Gating] SW calibration Done
4699 12:14:18.290446 ==
4700 12:14:18.293865 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 12:14:18.296923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 12:14:18.297028 ==
4703 12:14:18.300625 RX Vref Scan: 0
4704 12:14:18.300718
4705 12:14:18.303733 RX Vref 0 -> 0, step: 1
4706 12:14:18.303839
4707 12:14:18.303931 RX Delay -230 -> 252, step: 16
4708 12:14:18.310278 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4709 12:14:18.313981 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4710 12:14:18.317105 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4711 12:14:18.320376 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4712 12:14:18.324032 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4713 12:14:18.330293 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4714 12:14:18.334093 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4715 12:14:18.337310 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4716 12:14:18.340303 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4717 12:14:18.346886 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4718 12:14:18.350272 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4719 12:14:18.353557 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4720 12:14:18.357111 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4721 12:14:18.363751 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4722 12:14:18.367013 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4723 12:14:18.370024 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4724 12:14:18.370102 ==
4725 12:14:18.373786 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 12:14:18.377214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 12:14:18.377317 ==
4728 12:14:18.380153 DQS Delay:
4729 12:14:18.380277 DQS0 = 0, DQS1 = 0
4730 12:14:18.383437 DQM Delay:
4731 12:14:18.383513 DQM0 = 51, DQM1 = 48
4732 12:14:18.383576 DQ Delay:
4733 12:14:18.387068 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4734 12:14:18.390330 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4735 12:14:18.393370 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =49
4736 12:14:18.396682 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4737 12:14:18.396765
4738 12:14:18.396829
4739 12:14:18.400457 ==
4740 12:14:18.400541 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 12:14:18.406956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 12:14:18.407049 ==
4743 12:14:18.407114
4744 12:14:18.407174
4745 12:14:18.410339 TX Vref Scan disable
4746 12:14:18.410427 == TX Byte 0 ==
4747 12:14:18.413385 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4748 12:14:18.420215 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4749 12:14:18.420391 == TX Byte 1 ==
4750 12:14:18.423463 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4751 12:14:18.430116 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4752 12:14:18.430228 ==
4753 12:14:18.433412 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 12:14:18.436725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 12:14:18.436811 ==
4756 12:14:18.436878
4757 12:14:18.436939
4758 12:14:18.439985 TX Vref Scan disable
4759 12:14:18.443147 == TX Byte 0 ==
4760 12:14:18.446976 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4761 12:14:18.450020 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4762 12:14:18.453046 == TX Byte 1 ==
4763 12:14:18.456471 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4764 12:14:18.460283 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4765 12:14:18.460398
4766 12:14:18.463379 [DATLAT]
4767 12:14:18.463466 Freq=600, CH1 RK1
4768 12:14:18.463555
4769 12:14:18.466672 DATLAT Default: 0x9
4770 12:14:18.466759 0, 0xFFFF, sum = 0
4771 12:14:18.470161 1, 0xFFFF, sum = 0
4772 12:14:18.470248 2, 0xFFFF, sum = 0
4773 12:14:18.473311 3, 0xFFFF, sum = 0
4774 12:14:18.473411 4, 0xFFFF, sum = 0
4775 12:14:18.476861 5, 0xFFFF, sum = 0
4776 12:14:18.476945 6, 0xFFFF, sum = 0
4777 12:14:18.479760 7, 0xFFFF, sum = 0
4778 12:14:18.479860 8, 0x0, sum = 1
4779 12:14:18.483381 9, 0x0, sum = 2
4780 12:14:18.483467 10, 0x0, sum = 3
4781 12:14:18.486593 11, 0x0, sum = 4
4782 12:14:18.486727 best_step = 9
4783 12:14:18.486813
4784 12:14:18.486895 ==
4785 12:14:18.490090 Dram Type= 6, Freq= 0, CH_1, rank 1
4786 12:14:18.493331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4787 12:14:18.493418 ==
4788 12:14:18.496537 RX Vref Scan: 0
4789 12:14:18.496622
4790 12:14:18.499971 RX Vref 0 -> 0, step: 1
4791 12:14:18.500081
4792 12:14:18.500183 RX Delay -163 -> 252, step: 8
4793 12:14:18.507594 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4794 12:14:18.511395 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4795 12:14:18.514203 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4796 12:14:18.517427 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4797 12:14:18.524216 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4798 12:14:18.527524 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4799 12:14:18.531124 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4800 12:14:18.534322 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4801 12:14:18.537341 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4802 12:14:18.544152 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4803 12:14:18.547495 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4804 12:14:18.550427 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4805 12:14:18.554430 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4806 12:14:18.557473 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4807 12:14:18.563814 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4808 12:14:18.567614 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4809 12:14:18.567719 ==
4810 12:14:18.570694 Dram Type= 6, Freq= 0, CH_1, rank 1
4811 12:14:18.574012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4812 12:14:18.574154 ==
4813 12:14:18.577617 DQS Delay:
4814 12:14:18.577733 DQS0 = 0, DQS1 = 0
4815 12:14:18.577865 DQM Delay:
4816 12:14:18.580916 DQM0 = 50, DQM1 = 45
4817 12:14:18.581054 DQ Delay:
4818 12:14:18.583946 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =48
4819 12:14:18.587226 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4820 12:14:18.590661 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4821 12:14:18.593946 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4822 12:14:18.594029
4823 12:14:18.594094
4824 12:14:18.603965 [DQSOSCAuto] RK1, (LSB)MR18= 0x651c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4825 12:14:18.607102 CH1 RK1: MR19=808, MR18=651C
4826 12:14:18.610669 CH1_RK1: MR19=0x808, MR18=0x651C, DQSOSC=390, MR23=63, INC=172, DEC=114
4827 12:14:18.613905 [RxdqsGatingPostProcess] freq 600
4828 12:14:18.620582 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4829 12:14:18.623849 Pre-setting of DQS Precalculation
4830 12:14:18.626887 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4831 12:14:18.637031 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4832 12:14:18.643820 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4833 12:14:18.643987
4834 12:14:18.644133
4835 12:14:18.646988 [Calibration Summary] 1200 Mbps
4836 12:14:18.647104 CH 0, Rank 0
4837 12:14:18.650225 SW Impedance : PASS
4838 12:14:18.650320 DUTY Scan : NO K
4839 12:14:18.653261 ZQ Calibration : PASS
4840 12:14:18.657157 Jitter Meter : NO K
4841 12:14:18.657254 CBT Training : PASS
4842 12:14:18.660155 Write leveling : PASS
4843 12:14:18.663339 RX DQS gating : PASS
4844 12:14:18.663430 RX DQ/DQS(RDDQC) : PASS
4845 12:14:18.667065 TX DQ/DQS : PASS
4846 12:14:18.669929 RX DATLAT : PASS
4847 12:14:18.670024 RX DQ/DQS(Engine): PASS
4848 12:14:18.673931 TX OE : NO K
4849 12:14:18.674049 All Pass.
4850 12:14:18.674120
4851 12:14:18.676858 CH 0, Rank 1
4852 12:14:18.676942 SW Impedance : PASS
4853 12:14:18.680112 DUTY Scan : NO K
4854 12:14:18.680226 ZQ Calibration : PASS
4855 12:14:18.683427 Jitter Meter : NO K
4856 12:14:18.687034 CBT Training : PASS
4857 12:14:18.687123 Write leveling : PASS
4858 12:14:18.690142 RX DQS gating : PASS
4859 12:14:18.693516 RX DQ/DQS(RDDQC) : PASS
4860 12:14:18.693605 TX DQ/DQS : PASS
4861 12:14:18.696962 RX DATLAT : PASS
4862 12:14:18.700309 RX DQ/DQS(Engine): PASS
4863 12:14:18.700398 TX OE : NO K
4864 12:14:18.703755 All Pass.
4865 12:14:18.703844
4866 12:14:18.703933 CH 1, Rank 0
4867 12:14:18.706976 SW Impedance : PASS
4868 12:14:18.707065 DUTY Scan : NO K
4869 12:14:18.710159 ZQ Calibration : PASS
4870 12:14:18.713562 Jitter Meter : NO K
4871 12:14:18.713650 CBT Training : PASS
4872 12:14:18.716977 Write leveling : PASS
4873 12:14:18.719906 RX DQS gating : PASS
4874 12:14:18.719994 RX DQ/DQS(RDDQC) : PASS
4875 12:14:18.723504 TX DQ/DQS : PASS
4876 12:14:18.723589 RX DATLAT : PASS
4877 12:14:18.727191 RX DQ/DQS(Engine): PASS
4878 12:14:18.729963 TX OE : NO K
4879 12:14:18.730081 All Pass.
4880 12:14:18.730151
4881 12:14:18.730213 CH 1, Rank 1
4882 12:14:18.733129 SW Impedance : PASS
4883 12:14:18.736472 DUTY Scan : NO K
4884 12:14:18.736555 ZQ Calibration : PASS
4885 12:14:18.740259 Jitter Meter : NO K
4886 12:14:18.743457 CBT Training : PASS
4887 12:14:18.743540 Write leveling : PASS
4888 12:14:18.746603 RX DQS gating : PASS
4889 12:14:18.750085 RX DQ/DQS(RDDQC) : PASS
4890 12:14:18.750173 TX DQ/DQS : PASS
4891 12:14:18.752968 RX DATLAT : PASS
4892 12:14:18.756408 RX DQ/DQS(Engine): PASS
4893 12:14:18.756491 TX OE : NO K
4894 12:14:18.760016 All Pass.
4895 12:14:18.760101
4896 12:14:18.760168 DramC Write-DBI off
4897 12:14:18.763393 PER_BANK_REFRESH: Hybrid Mode
4898 12:14:18.763476 TX_TRACKING: ON
4899 12:14:18.773357 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4900 12:14:18.776393 [FAST_K] Save calibration result to emmc
4901 12:14:18.779883 dramc_set_vcore_voltage set vcore to 662500
4902 12:14:18.783405 Read voltage for 933, 3
4903 12:14:18.783488 Vio18 = 0
4904 12:14:18.786618 Vcore = 662500
4905 12:14:18.786700 Vdram = 0
4906 12:14:18.786836 Vddq = 0
4907 12:14:18.786914 Vmddr = 0
4908 12:14:18.793052 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4909 12:14:18.799850 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4910 12:14:18.799933 MEM_TYPE=3, freq_sel=17
4911 12:14:18.803204 sv_algorithm_assistance_LP4_1600
4912 12:14:18.806732 ============ PULL DRAM RESETB DOWN ============
4913 12:14:18.813053 ========== PULL DRAM RESETB DOWN end =========
4914 12:14:18.816946 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4915 12:14:18.819885 ===================================
4916 12:14:18.823218 LPDDR4 DRAM CONFIGURATION
4917 12:14:18.826363 ===================================
4918 12:14:18.826496 EX_ROW_EN[0] = 0x0
4919 12:14:18.830025 EX_ROW_EN[1] = 0x0
4920 12:14:18.830126 LP4Y_EN = 0x0
4921 12:14:18.833393 WORK_FSP = 0x0
4922 12:14:18.833475 WL = 0x3
4923 12:14:18.836235 RL = 0x3
4924 12:14:18.836357 BL = 0x2
4925 12:14:18.839434 RPST = 0x0
4926 12:14:18.843350 RD_PRE = 0x0
4927 12:14:18.843426 WR_PRE = 0x1
4928 12:14:18.846392 WR_PST = 0x0
4929 12:14:18.846477 DBI_WR = 0x0
4930 12:14:18.849685 DBI_RD = 0x0
4931 12:14:18.849766 OTF = 0x1
4932 12:14:18.853052 ===================================
4933 12:14:18.856158 ===================================
4934 12:14:18.856241 ANA top config
4935 12:14:18.859885 ===================================
4936 12:14:18.863110 DLL_ASYNC_EN = 0
4937 12:14:18.866046 ALL_SLAVE_EN = 1
4938 12:14:18.869464 NEW_RANK_MODE = 1
4939 12:14:18.872839 DLL_IDLE_MODE = 1
4940 12:14:18.872921 LP45_APHY_COMB_EN = 1
4941 12:14:18.876093 TX_ODT_DIS = 1
4942 12:14:18.879626 NEW_8X_MODE = 1
4943 12:14:18.882903 ===================================
4944 12:14:18.886012 ===================================
4945 12:14:18.889429 data_rate = 1866
4946 12:14:18.892889 CKR = 1
4947 12:14:18.892972 DQ_P2S_RATIO = 8
4948 12:14:18.896169 ===================================
4949 12:14:18.899397 CA_P2S_RATIO = 8
4950 12:14:18.903053 DQ_CA_OPEN = 0
4951 12:14:18.906427 DQ_SEMI_OPEN = 0
4952 12:14:18.910037 CA_SEMI_OPEN = 0
4953 12:14:18.913021 CA_FULL_RATE = 0
4954 12:14:18.913134 DQ_CKDIV4_EN = 1
4955 12:14:18.916389 CA_CKDIV4_EN = 1
4956 12:14:18.919879 CA_PREDIV_EN = 0
4957 12:14:18.922883 PH8_DLY = 0
4958 12:14:18.926668 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4959 12:14:18.929950 DQ_AAMCK_DIV = 4
4960 12:14:18.930032 CA_AAMCK_DIV = 4
4961 12:14:18.932900 CA_ADMCK_DIV = 4
4962 12:14:18.936652 DQ_TRACK_CA_EN = 0
4963 12:14:18.939738 CA_PICK = 933
4964 12:14:18.942968 CA_MCKIO = 933
4965 12:14:18.946196 MCKIO_SEMI = 0
4966 12:14:18.946278 PLL_FREQ = 3732
4967 12:14:18.949772 DQ_UI_PI_RATIO = 32
4968 12:14:18.953375 CA_UI_PI_RATIO = 0
4969 12:14:18.956272 ===================================
4970 12:14:18.959892 ===================================
4971 12:14:18.962793 memory_type:LPDDR4
4972 12:14:18.966227 GP_NUM : 10
4973 12:14:18.966319 SRAM_EN : 1
4974 12:14:18.969751 MD32_EN : 0
4975 12:14:18.973229 ===================================
4976 12:14:18.973311 [ANA_INIT] >>>>>>>>>>>>>>
4977 12:14:18.976487 <<<<<< [CONFIGURE PHASE]: ANA_TX
4978 12:14:18.979356 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4979 12:14:18.983016 ===================================
4980 12:14:18.986482 data_rate = 1866,PCW = 0X8f00
4981 12:14:18.989502 ===================================
4982 12:14:18.992964 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4983 12:14:18.999691 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4984 12:14:19.003094 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4985 12:14:19.010030 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4986 12:14:19.013035 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4987 12:14:19.016281 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4988 12:14:19.019448 [ANA_INIT] flow start
4989 12:14:19.019530 [ANA_INIT] PLL >>>>>>>>
4990 12:14:19.022941 [ANA_INIT] PLL <<<<<<<<
4991 12:14:19.026147 [ANA_INIT] MIDPI >>>>>>>>
4992 12:14:19.026230 [ANA_INIT] MIDPI <<<<<<<<
4993 12:14:19.029351 [ANA_INIT] DLL >>>>>>>>
4994 12:14:19.033226 [ANA_INIT] flow end
4995 12:14:19.036227 ============ LP4 DIFF to SE enter ============
4996 12:14:19.039338 ============ LP4 DIFF to SE exit ============
4997 12:14:19.042975 [ANA_INIT] <<<<<<<<<<<<<
4998 12:14:19.046531 [Flow] Enable top DCM control >>>>>
4999 12:14:19.049385 [Flow] Enable top DCM control <<<<<
5000 12:14:19.052598 Enable DLL master slave shuffle
5001 12:14:19.056227 ==============================================================
5002 12:14:19.059468 Gating Mode config
5003 12:14:19.062565 ==============================================================
5004 12:14:19.066106 Config description:
5005 12:14:19.075966 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5006 12:14:19.082853 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5007 12:14:19.085865 SELPH_MODE 0: By rank 1: By Phase
5008 12:14:19.092983 ==============================================================
5009 12:14:19.095745 GAT_TRACK_EN = 1
5010 12:14:19.099257 RX_GATING_MODE = 2
5011 12:14:19.102498 RX_GATING_TRACK_MODE = 2
5012 12:14:19.105943 SELPH_MODE = 1
5013 12:14:19.108897 PICG_EARLY_EN = 1
5014 12:14:19.112613 VALID_LAT_VALUE = 1
5015 12:14:19.116188 ==============================================================
5016 12:14:19.119277 Enter into Gating configuration >>>>
5017 12:14:19.122291 Exit from Gating configuration <<<<
5018 12:14:19.125852 Enter into DVFS_PRE_config >>>>>
5019 12:14:19.136126 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5020 12:14:19.139189 Exit from DVFS_PRE_config <<<<<
5021 12:14:19.142941 Enter into PICG configuration >>>>
5022 12:14:19.145934 Exit from PICG configuration <<<<
5023 12:14:19.149126 [RX_INPUT] configuration >>>>>
5024 12:14:19.152703 [RX_INPUT] configuration <<<<<
5025 12:14:19.156045 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5026 12:14:19.162523 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5027 12:14:19.168890 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5028 12:14:19.175937 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5029 12:14:19.182394 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5030 12:14:19.189008 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5031 12:14:19.192813 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5032 12:14:19.195912 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5033 12:14:19.199348 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5034 12:14:19.202217 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5035 12:14:19.209148 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5036 12:14:19.212601 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5037 12:14:19.215848 ===================================
5038 12:14:19.219193 LPDDR4 DRAM CONFIGURATION
5039 12:14:19.222537 ===================================
5040 12:14:19.222682 EX_ROW_EN[0] = 0x0
5041 12:14:19.225455 EX_ROW_EN[1] = 0x0
5042 12:14:19.225531 LP4Y_EN = 0x0
5043 12:14:19.229201 WORK_FSP = 0x0
5044 12:14:19.229307 WL = 0x3
5045 12:14:19.232205 RL = 0x3
5046 12:14:19.232281 BL = 0x2
5047 12:14:19.235678 RPST = 0x0
5048 12:14:19.238780 RD_PRE = 0x0
5049 12:14:19.238882 WR_PRE = 0x1
5050 12:14:19.242670 WR_PST = 0x0
5051 12:14:19.242770 DBI_WR = 0x0
5052 12:14:19.245523 DBI_RD = 0x0
5053 12:14:19.245600 OTF = 0x1
5054 12:14:19.249214 ===================================
5055 12:14:19.252313 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5056 12:14:19.259082 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5057 12:14:19.262328 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5058 12:14:19.265460 ===================================
5059 12:14:19.269074 LPDDR4 DRAM CONFIGURATION
5060 12:14:19.272211 ===================================
5061 12:14:19.272310 EX_ROW_EN[0] = 0x10
5062 12:14:19.275490 EX_ROW_EN[1] = 0x0
5063 12:14:19.275569 LP4Y_EN = 0x0
5064 12:14:19.279080 WORK_FSP = 0x0
5065 12:14:19.279157 WL = 0x3
5066 12:14:19.282328 RL = 0x3
5067 12:14:19.282410 BL = 0x2
5068 12:14:19.285533 RPST = 0x0
5069 12:14:19.285632 RD_PRE = 0x0
5070 12:14:19.288668 WR_PRE = 0x1
5071 12:14:19.288746 WR_PST = 0x0
5072 12:14:19.292276 DBI_WR = 0x0
5073 12:14:19.292372 DBI_RD = 0x0
5074 12:14:19.295740 OTF = 0x1
5075 12:14:19.298859 ===================================
5076 12:14:19.305706 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5077 12:14:19.308738 nWR fixed to 30
5078 12:14:19.312554 [ModeRegInit_LP4] CH0 RK0
5079 12:14:19.312640 [ModeRegInit_LP4] CH0 RK1
5080 12:14:19.315419 [ModeRegInit_LP4] CH1 RK0
5081 12:14:19.318761 [ModeRegInit_LP4] CH1 RK1
5082 12:14:19.318836 match AC timing 9
5083 12:14:19.325352 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5084 12:14:19.328937 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5085 12:14:19.332138 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5086 12:14:19.338872 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5087 12:14:19.342304 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5088 12:14:19.342419 ==
5089 12:14:19.345442 Dram Type= 6, Freq= 0, CH_0, rank 0
5090 12:14:19.348665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5091 12:14:19.348742 ==
5092 12:14:19.354974 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5093 12:14:19.362121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5094 12:14:19.365163 [CA 0] Center 37 (6~68) winsize 63
5095 12:14:19.368723 [CA 1] Center 37 (7~68) winsize 62
5096 12:14:19.372276 [CA 2] Center 34 (4~65) winsize 62
5097 12:14:19.375381 [CA 3] Center 34 (3~65) winsize 63
5098 12:14:19.379215 [CA 4] Center 33 (3~64) winsize 62
5099 12:14:19.382447 [CA 5] Center 32 (2~62) winsize 61
5100 12:14:19.382530
5101 12:14:19.385687 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5102 12:14:19.385770
5103 12:14:19.388772 [CATrainingPosCal] consider 1 rank data
5104 12:14:19.391885 u2DelayCellTimex100 = 270/100 ps
5105 12:14:19.395599 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5106 12:14:19.398672 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5107 12:14:19.402273 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5108 12:14:19.405511 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5109 12:14:19.408587 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5110 12:14:19.411986 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5111 12:14:19.412085
5112 12:14:19.418920 CA PerBit enable=1, Macro0, CA PI delay=32
5113 12:14:19.419029
5114 12:14:19.421738 [CBTSetCACLKResult] CA Dly = 32
5115 12:14:19.421820 CS Dly: 5 (0~36)
5116 12:14:19.421893 ==
5117 12:14:19.425222 Dram Type= 6, Freq= 0, CH_0, rank 1
5118 12:14:19.428717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5119 12:14:19.428801 ==
5120 12:14:19.435135 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5121 12:14:19.441860 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5122 12:14:19.445437 [CA 0] Center 37 (6~68) winsize 63
5123 12:14:19.449042 [CA 1] Center 37 (7~68) winsize 62
5124 12:14:19.451880 [CA 2] Center 34 (4~65) winsize 62
5125 12:14:19.455636 [CA 3] Center 34 (3~65) winsize 63
5126 12:14:19.458560 [CA 4] Center 33 (3~63) winsize 61
5127 12:14:19.461951 [CA 5] Center 32 (2~62) winsize 61
5128 12:14:19.462029
5129 12:14:19.465123 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5130 12:14:19.465201
5131 12:14:19.468178 [CATrainingPosCal] consider 2 rank data
5132 12:14:19.472062 u2DelayCellTimex100 = 270/100 ps
5133 12:14:19.474884 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5134 12:14:19.478691 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5135 12:14:19.481670 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5136 12:14:19.485157 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5137 12:14:19.488772 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5138 12:14:19.495040 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5139 12:14:19.495152
5140 12:14:19.498931 CA PerBit enable=1, Macro0, CA PI delay=32
5141 12:14:19.499047
5142 12:14:19.501711 [CBTSetCACLKResult] CA Dly = 32
5143 12:14:19.501794 CS Dly: 5 (0~37)
5144 12:14:19.501860
5145 12:14:19.505067 ----->DramcWriteLeveling(PI) begin...
5146 12:14:19.505151 ==
5147 12:14:19.508852 Dram Type= 6, Freq= 0, CH_0, rank 0
5148 12:14:19.511977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5149 12:14:19.515144 ==
5150 12:14:19.515225 Write leveling (Byte 0): 33 => 33
5151 12:14:19.518349 Write leveling (Byte 1): 28 => 28
5152 12:14:19.522109 DramcWriteLeveling(PI) end<-----
5153 12:14:19.522186
5154 12:14:19.522289 ==
5155 12:14:19.525230 Dram Type= 6, Freq= 0, CH_0, rank 0
5156 12:14:19.531498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5157 12:14:19.531578 ==
5158 12:14:19.531647 [Gating] SW mode calibration
5159 12:14:19.541354 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5160 12:14:19.544993 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5161 12:14:19.551764 0 14 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
5162 12:14:19.555167 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 12:14:19.557945 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 12:14:19.561273 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 12:14:19.568128 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 12:14:19.571217 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 12:14:19.574750 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5168 12:14:19.581586 0 14 28 | B1->B0 | 3434 2626 | 0 0 | (0 0) (1 0)
5169 12:14:19.584736 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (1 0)
5170 12:14:19.588116 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 12:14:19.594730 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 12:14:19.598495 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 12:14:19.601746 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 12:14:19.608025 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 12:14:19.611226 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 12:14:19.614866 0 15 28 | B1->B0 | 2a2a 3b3b | 0 0 | (1 1) (0 0)
5177 12:14:19.621597 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5178 12:14:19.624724 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 12:14:19.627884 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 12:14:19.634883 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 12:14:19.637922 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 12:14:19.641167 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 12:14:19.647877 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 12:14:19.651601 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5185 12:14:19.654616 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5186 12:14:19.661375 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 12:14:19.664419 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 12:14:19.667922 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 12:14:19.674751 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 12:14:19.677651 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 12:14:19.681390 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 12:14:19.684900 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 12:14:19.691179 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 12:14:19.694797 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 12:14:19.697912 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 12:14:19.704276 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 12:14:19.707649 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 12:14:19.711023 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 12:14:19.717973 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5200 12:14:19.721375 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5201 12:14:19.724275 Total UI for P1: 0, mck2ui 16
5202 12:14:19.728098 best dqsien dly found for B0: ( 1, 2, 24)
5203 12:14:19.731317 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5204 12:14:19.738247 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 12:14:19.738384 Total UI for P1: 0, mck2ui 16
5206 12:14:19.744264 best dqsien dly found for B1: ( 1, 2, 30)
5207 12:14:19.747598 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5208 12:14:19.751279 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5209 12:14:19.751357
5210 12:14:19.754071 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5211 12:14:19.757846 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5212 12:14:19.760851 [Gating] SW calibration Done
5213 12:14:19.760927 ==
5214 12:14:19.764681 Dram Type= 6, Freq= 0, CH_0, rank 0
5215 12:14:19.767910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5216 12:14:19.767988 ==
5217 12:14:19.770904 RX Vref Scan: 0
5218 12:14:19.770978
5219 12:14:19.771044 RX Vref 0 -> 0, step: 1
5220 12:14:19.771137
5221 12:14:19.774035 RX Delay -80 -> 252, step: 8
5222 12:14:19.777685 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5223 12:14:19.784508 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5224 12:14:19.787379 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5225 12:14:19.790889 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5226 12:14:19.794524 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5227 12:14:19.797504 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5228 12:14:19.801142 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5229 12:14:19.807867 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5230 12:14:19.810443 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5231 12:14:19.814027 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5232 12:14:19.817194 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5233 12:14:19.821052 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5234 12:14:19.824461 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5235 12:14:19.830573 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5236 12:14:19.834141 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5237 12:14:19.837838 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5238 12:14:19.837921 ==
5239 12:14:19.840717 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 12:14:19.844028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 12:14:19.847602 ==
5242 12:14:19.847711 DQS Delay:
5243 12:14:19.847800 DQS0 = 0, DQS1 = 0
5244 12:14:19.850689 DQM Delay:
5245 12:14:19.850771 DQM0 = 103, DQM1 = 95
5246 12:14:19.853773 DQ Delay:
5247 12:14:19.857275 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5248 12:14:19.860703 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5249 12:14:19.864223 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =91
5250 12:14:19.867329 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5251 12:14:19.867411
5252 12:14:19.867481
5253 12:14:19.867541 ==
5254 12:14:19.870429 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 12:14:19.873621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 12:14:19.873737 ==
5257 12:14:19.873827
5258 12:14:19.873910
5259 12:14:19.877263 TX Vref Scan disable
5260 12:14:19.877347 == TX Byte 0 ==
5261 12:14:19.884186 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5262 12:14:19.887330 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5263 12:14:19.887414 == TX Byte 1 ==
5264 12:14:19.893644 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5265 12:14:19.897226 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5266 12:14:19.897322 ==
5267 12:14:19.901069 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 12:14:19.903655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 12:14:19.903748 ==
5270 12:14:19.903873
5271 12:14:19.907024
5272 12:14:19.907097 TX Vref Scan disable
5273 12:14:19.910626 == TX Byte 0 ==
5274 12:14:19.913598 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5275 12:14:19.917070 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5276 12:14:19.920133 == TX Byte 1 ==
5277 12:14:19.923921 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5278 12:14:19.927055 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5279 12:14:19.930100
5280 12:14:19.930175 [DATLAT]
5281 12:14:19.930238 Freq=933, CH0 RK0
5282 12:14:19.930301
5283 12:14:19.933276 DATLAT Default: 0xd
5284 12:14:19.933343 0, 0xFFFF, sum = 0
5285 12:14:19.937035 1, 0xFFFF, sum = 0
5286 12:14:19.937106 2, 0xFFFF, sum = 0
5287 12:14:19.940164 3, 0xFFFF, sum = 0
5288 12:14:19.940238 4, 0xFFFF, sum = 0
5289 12:14:19.943635 5, 0xFFFF, sum = 0
5290 12:14:19.947074 6, 0xFFFF, sum = 0
5291 12:14:19.947148 7, 0xFFFF, sum = 0
5292 12:14:19.950056 8, 0xFFFF, sum = 0
5293 12:14:19.950132 9, 0xFFFF, sum = 0
5294 12:14:19.953722 10, 0x0, sum = 1
5295 12:14:19.953798 11, 0x0, sum = 2
5296 12:14:19.956947 12, 0x0, sum = 3
5297 12:14:19.957023 13, 0x0, sum = 4
5298 12:14:19.957089 best_step = 11
5299 12:14:19.957148
5300 12:14:19.960228 ==
5301 12:14:19.960393 Dram Type= 6, Freq= 0, CH_0, rank 0
5302 12:14:19.966684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 12:14:19.966781 ==
5304 12:14:19.966877 RX Vref Scan: 1
5305 12:14:19.966952
5306 12:14:19.970084 RX Vref 0 -> 0, step: 1
5307 12:14:19.970206
5308 12:14:19.973238 RX Delay -53 -> 252, step: 4
5309 12:14:19.973332
5310 12:14:19.976724 Set Vref, RX VrefLevel [Byte0]: 55
5311 12:14:19.979771 [Byte1]: 45
5312 12:14:19.979889
5313 12:14:19.983523 Final RX Vref Byte 0 = 55 to rank0
5314 12:14:19.986796 Final RX Vref Byte 1 = 45 to rank0
5315 12:14:19.989789 Final RX Vref Byte 0 = 55 to rank1
5316 12:14:19.993450 Final RX Vref Byte 1 = 45 to rank1==
5317 12:14:19.996719 Dram Type= 6, Freq= 0, CH_0, rank 0
5318 12:14:19.999831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5319 12:14:19.999958 ==
5320 12:14:20.003590 DQS Delay:
5321 12:14:20.003701 DQS0 = 0, DQS1 = 0
5322 12:14:20.006354 DQM Delay:
5323 12:14:20.006454 DQM0 = 104, DQM1 = 95
5324 12:14:20.009693 DQ Delay:
5325 12:14:20.012880 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5326 12:14:20.016202 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =108
5327 12:14:20.019754 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =90
5328 12:14:20.023190 DQ12 =100, DQ13 =98, DQ14 =106, DQ15 =102
5329 12:14:20.023292
5330 12:14:20.023389
5331 12:14:20.029596 [DQSOSCAuto] RK0, (LSB)MR18= 0x3129, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5332 12:14:20.032736 CH0 RK0: MR19=505, MR18=3129
5333 12:14:20.039576 CH0_RK0: MR19=0x505, MR18=0x3129, DQSOSC=406, MR23=63, INC=65, DEC=43
5334 12:14:20.039702
5335 12:14:20.042858 ----->DramcWriteLeveling(PI) begin...
5336 12:14:20.042959 ==
5337 12:14:20.046066 Dram Type= 6, Freq= 0, CH_0, rank 1
5338 12:14:20.049848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5339 12:14:20.049974 ==
5340 12:14:20.052843 Write leveling (Byte 0): 33 => 33
5341 12:14:20.056109 Write leveling (Byte 1): 28 => 28
5342 12:14:20.059971 DramcWriteLeveling(PI) end<-----
5343 12:14:20.060075
5344 12:14:20.060173 ==
5345 12:14:20.062915 Dram Type= 6, Freq= 0, CH_0, rank 1
5346 12:14:20.066491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 12:14:20.066574 ==
5348 12:14:20.069496 [Gating] SW mode calibration
5349 12:14:20.076102 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5350 12:14:20.082980 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5351 12:14:20.086175 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5352 12:14:20.092934 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 12:14:20.096036 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 12:14:20.099561 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 12:14:20.106579 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 12:14:20.109760 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 12:14:20.112705 0 14 24 | B1->B0 | 3232 3434 | 1 0 | (0 0) (0 0)
5358 12:14:20.119829 0 14 28 | B1->B0 | 2b2b 2d2d | 0 1 | (0 0) (1 0)
5359 12:14:20.122860 0 15 0 | B1->B0 | 2323 2b2b | 0 1 | (1 0) (1 0)
5360 12:14:20.126152 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 12:14:20.129663 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 12:14:20.136227 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 12:14:20.139708 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 12:14:20.142805 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 12:14:20.149811 0 15 24 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
5366 12:14:20.152807 0 15 28 | B1->B0 | 3939 3232 | 0 0 | (0 0) (0 0)
5367 12:14:20.155966 1 0 0 | B1->B0 | 4646 4444 | 0 1 | (0 0) (0 0)
5368 12:14:20.162692 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 12:14:20.165926 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 12:14:20.169180 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 12:14:20.176123 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 12:14:20.179371 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 12:14:20.182965 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 12:14:20.189794 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5375 12:14:20.192433 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 12:14:20.196320 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 12:14:20.202469 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 12:14:20.206167 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 12:14:20.209375 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 12:14:20.216215 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 12:14:20.219393 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 12:14:20.222445 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 12:14:20.229470 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 12:14:20.232976 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 12:14:20.235924 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 12:14:20.242720 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 12:14:20.245833 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 12:14:20.249199 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 12:14:20.252566 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 12:14:20.259489 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 12:14:20.262619 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 12:14:20.265623 Total UI for P1: 0, mck2ui 16
5393 12:14:20.269119 best dqsien dly found for B0: ( 1, 2, 30)
5394 12:14:20.272413 Total UI for P1: 0, mck2ui 16
5395 12:14:20.276089 best dqsien dly found for B1: ( 1, 2, 30)
5396 12:14:20.279265 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5397 12:14:20.282308 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5398 12:14:20.282391
5399 12:14:20.285332 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5400 12:14:20.289174 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5401 12:14:20.292275 [Gating] SW calibration Done
5402 12:14:20.292395 ==
5403 12:14:20.295570 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 12:14:20.301990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 12:14:20.302074 ==
5406 12:14:20.302141 RX Vref Scan: 0
5407 12:14:20.302241
5408 12:14:20.305440 RX Vref 0 -> 0, step: 1
5409 12:14:20.305523
5410 12:14:20.308834 RX Delay -80 -> 252, step: 8
5411 12:14:20.312027 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5412 12:14:20.315622 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5413 12:14:20.318735 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5414 12:14:20.322425 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5415 12:14:20.328709 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5416 12:14:20.331876 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5417 12:14:20.335768 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5418 12:14:20.338701 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5419 12:14:20.341889 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5420 12:14:20.348465 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5421 12:14:20.351751 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5422 12:14:20.355099 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5423 12:14:20.358561 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5424 12:14:20.362207 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5425 12:14:20.365569 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5426 12:14:20.371803 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5427 12:14:20.371887 ==
5428 12:14:20.375337 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 12:14:20.378409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 12:14:20.378531 ==
5431 12:14:20.378596 DQS Delay:
5432 12:14:20.381720 DQS0 = 0, DQS1 = 0
5433 12:14:20.381802 DQM Delay:
5434 12:14:20.385271 DQM0 = 104, DQM1 = 92
5435 12:14:20.385372 DQ Delay:
5436 12:14:20.388624 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5437 12:14:20.391686 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5438 12:14:20.395334 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =83
5439 12:14:20.398532 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5440 12:14:20.398633
5441 12:14:20.398731
5442 12:14:20.398806 ==
5443 12:14:20.401867 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 12:14:20.405607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 12:14:20.408608 ==
5446 12:14:20.408707
5447 12:14:20.408805
5448 12:14:20.408880 TX Vref Scan disable
5449 12:14:20.411971 == TX Byte 0 ==
5450 12:14:20.415101 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5451 12:14:20.418192 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5452 12:14:20.421624 == TX Byte 1 ==
5453 12:14:20.425478 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5454 12:14:20.428130 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5455 12:14:20.431696 ==
5456 12:14:20.431797 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 12:14:20.438089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 12:14:20.438191 ==
5459 12:14:20.438289
5460 12:14:20.438365
5461 12:14:20.441549 TX Vref Scan disable
5462 12:14:20.441649 == TX Byte 0 ==
5463 12:14:20.447837 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5464 12:14:20.451673 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5465 12:14:20.451774 == TX Byte 1 ==
5466 12:14:20.457823 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5467 12:14:20.461619 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5468 12:14:20.461719
5469 12:14:20.461819 [DATLAT]
5470 12:14:20.464607 Freq=933, CH0 RK1
5471 12:14:20.464690
5472 12:14:20.464755 DATLAT Default: 0xb
5473 12:14:20.468275 0, 0xFFFF, sum = 0
5474 12:14:20.468401 1, 0xFFFF, sum = 0
5475 12:14:20.471507 2, 0xFFFF, sum = 0
5476 12:14:20.471590 3, 0xFFFF, sum = 0
5477 12:14:20.474931 4, 0xFFFF, sum = 0
5478 12:14:20.475016 5, 0xFFFF, sum = 0
5479 12:14:20.477955 6, 0xFFFF, sum = 0
5480 12:14:20.478040 7, 0xFFFF, sum = 0
5481 12:14:20.481452 8, 0xFFFF, sum = 0
5482 12:14:20.484836 9, 0xFFFF, sum = 0
5483 12:14:20.484920 10, 0x0, sum = 1
5484 12:14:20.484987 11, 0x0, sum = 2
5485 12:14:20.487826 12, 0x0, sum = 3
5486 12:14:20.487911 13, 0x0, sum = 4
5487 12:14:20.491136 best_step = 11
5488 12:14:20.491251
5489 12:14:20.491316 ==
5490 12:14:20.494966 Dram Type= 6, Freq= 0, CH_0, rank 1
5491 12:14:20.498034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 12:14:20.498117 ==
5493 12:14:20.501161 RX Vref Scan: 0
5494 12:14:20.501246
5495 12:14:20.501327 RX Vref 0 -> 0, step: 1
5496 12:14:20.501388
5497 12:14:20.504872 RX Delay -53 -> 252, step: 4
5498 12:14:20.511833 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5499 12:14:20.514954 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5500 12:14:20.518144 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5501 12:14:20.521983 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5502 12:14:20.524987 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5503 12:14:20.531545 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5504 12:14:20.534899 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5505 12:14:20.538171 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5506 12:14:20.541479 iDelay=199, Bit 8, Center 84 (3 ~ 166) 164
5507 12:14:20.544673 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5508 12:14:20.551730 iDelay=199, Bit 10, Center 96 (15 ~ 178) 164
5509 12:14:20.555118 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5510 12:14:20.557996 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5511 12:14:20.561515 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5512 12:14:20.564691 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5513 12:14:20.571480 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5514 12:14:20.571564 ==
5515 12:14:20.574490 Dram Type= 6, Freq= 0, CH_0, rank 1
5516 12:14:20.578045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 12:14:20.578129 ==
5518 12:14:20.578209 DQS Delay:
5519 12:14:20.581723 DQS0 = 0, DQS1 = 0
5520 12:14:20.581805 DQM Delay:
5521 12:14:20.584779 DQM0 = 105, DQM1 = 94
5522 12:14:20.584862 DQ Delay:
5523 12:14:20.587938 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5524 12:14:20.591429 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5525 12:14:20.594567 DQ8 =84, DQ9 =82, DQ10 =96, DQ11 =88
5526 12:14:20.598016 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =102
5527 12:14:20.598113
5528 12:14:20.598180
5529 12:14:20.608165 [DQSOSCAuto] RK1, (LSB)MR18= 0x2902, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5530 12:14:20.611601 CH0 RK1: MR19=505, MR18=2902
5531 12:14:20.614916 CH0_RK1: MR19=0x505, MR18=0x2902, DQSOSC=408, MR23=63, INC=65, DEC=43
5532 12:14:20.617973 [RxdqsGatingPostProcess] freq 933
5533 12:14:20.624512 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5534 12:14:20.627674 best DQS0 dly(2T, 0.5T) = (0, 10)
5535 12:14:20.631185 best DQS1 dly(2T, 0.5T) = (0, 10)
5536 12:14:20.634221 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5537 12:14:20.637574 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5538 12:14:20.640854 best DQS0 dly(2T, 0.5T) = (0, 10)
5539 12:14:20.644471 best DQS1 dly(2T, 0.5T) = (0, 10)
5540 12:14:20.647661 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5541 12:14:20.651539 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5542 12:14:20.651621 Pre-setting of DQS Precalculation
5543 12:14:20.657820 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5544 12:14:20.657904 ==
5545 12:14:20.661049 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 12:14:20.664083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 12:14:20.664169 ==
5548 12:14:20.670926 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5549 12:14:20.677511 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5550 12:14:20.681178 [CA 0] Center 36 (6~67) winsize 62
5551 12:14:20.684516 [CA 1] Center 36 (6~67) winsize 62
5552 12:14:20.687940 [CA 2] Center 35 (5~65) winsize 61
5553 12:14:20.690792 [CA 3] Center 34 (4~65) winsize 62
5554 12:14:20.694157 [CA 4] Center 34 (4~64) winsize 61
5555 12:14:20.697609 [CA 5] Center 33 (3~64) winsize 62
5556 12:14:20.697691
5557 12:14:20.700687 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5558 12:14:20.700770
5559 12:14:20.704502 [CATrainingPosCal] consider 1 rank data
5560 12:14:20.707650 u2DelayCellTimex100 = 270/100 ps
5561 12:14:20.710837 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5562 12:14:20.714031 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5563 12:14:20.717420 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5564 12:14:20.720749 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5565 12:14:20.724144 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5566 12:14:20.727989 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5567 12:14:20.728071
5568 12:14:20.734380 CA PerBit enable=1, Macro0, CA PI delay=33
5569 12:14:20.734480
5570 12:14:20.737490 [CBTSetCACLKResult] CA Dly = 33
5571 12:14:20.737605 CS Dly: 7 (0~38)
5572 12:14:20.737670 ==
5573 12:14:20.741032 Dram Type= 6, Freq= 0, CH_1, rank 1
5574 12:14:20.744149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 12:14:20.744232 ==
5576 12:14:20.751004 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5577 12:14:20.757451 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5578 12:14:20.760998 [CA 0] Center 36 (6~67) winsize 62
5579 12:14:20.764349 [CA 1] Center 37 (6~68) winsize 63
5580 12:14:20.767345 [CA 2] Center 35 (5~65) winsize 61
5581 12:14:20.771010 [CA 3] Center 34 (4~65) winsize 62
5582 12:14:20.774369 [CA 4] Center 34 (4~65) winsize 62
5583 12:14:20.777307 [CA 5] Center 33 (3~64) winsize 62
5584 12:14:20.777392
5585 12:14:20.781242 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5586 12:14:20.781360
5587 12:14:20.784201 [CATrainingPosCal] consider 2 rank data
5588 12:14:20.787204 u2DelayCellTimex100 = 270/100 ps
5589 12:14:20.790613 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5590 12:14:20.794073 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5591 12:14:20.797180 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5592 12:14:20.800907 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5593 12:14:20.803740 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5594 12:14:20.810339 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5595 12:14:20.810438
5596 12:14:20.813767 CA PerBit enable=1, Macro0, CA PI delay=33
5597 12:14:20.813849
5598 12:14:20.816965 [CBTSetCACLKResult] CA Dly = 33
5599 12:14:20.817048 CS Dly: 8 (0~40)
5600 12:14:20.817114
5601 12:14:20.820238 ----->DramcWriteLeveling(PI) begin...
5602 12:14:20.820359 ==
5603 12:14:20.823734 Dram Type= 6, Freq= 0, CH_1, rank 0
5604 12:14:20.830248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 12:14:20.830332 ==
5606 12:14:20.833633 Write leveling (Byte 0): 28 => 28
5607 12:14:20.833716 Write leveling (Byte 1): 26 => 26
5608 12:14:20.836932 DramcWriteLeveling(PI) end<-----
5609 12:14:20.837014
5610 12:14:20.837079 ==
5611 12:14:20.840427 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 12:14:20.846846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 12:14:20.846955 ==
5614 12:14:20.850297 [Gating] SW mode calibration
5615 12:14:20.857153 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5616 12:14:20.860255 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5617 12:14:20.867184 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 12:14:20.870208 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 12:14:20.873859 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 12:14:20.880421 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 12:14:20.883341 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 12:14:20.886989 0 14 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5623 12:14:20.893334 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 0)
5624 12:14:20.897076 0 14 28 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (1 0)
5625 12:14:20.899936 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 12:14:20.906894 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 12:14:20.910123 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 12:14:20.913522 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 12:14:20.920143 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 12:14:20.923405 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 12:14:20.926695 0 15 24 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
5632 12:14:20.929810 0 15 28 | B1->B0 | 3c3c 4646 | 1 0 | (0 0) (0 0)
5633 12:14:20.936618 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 12:14:20.939700 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 12:14:20.942904 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 12:14:20.949426 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 12:14:20.953171 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 12:14:20.956276 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 12:14:20.962963 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5640 12:14:20.966045 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5641 12:14:20.969940 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 12:14:20.976273 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 12:14:20.979505 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 12:14:20.982835 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 12:14:20.989638 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 12:14:20.992785 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 12:14:20.996515 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 12:14:21.002768 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 12:14:21.006328 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 12:14:21.009816 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 12:14:21.016135 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 12:14:21.019780 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 12:14:21.022626 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 12:14:21.029490 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 12:14:21.032583 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5656 12:14:21.036153 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5657 12:14:21.039357 Total UI for P1: 0, mck2ui 16
5658 12:14:21.042548 best dqsien dly found for B0: ( 1, 2, 26)
5659 12:14:21.049451 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 12:14:21.049577 Total UI for P1: 0, mck2ui 16
5661 12:14:21.052793 best dqsien dly found for B1: ( 1, 2, 26)
5662 12:14:21.059302 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5663 12:14:21.062922 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5664 12:14:21.063005
5665 12:14:21.065832 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5666 12:14:21.069089 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5667 12:14:21.072827 [Gating] SW calibration Done
5668 12:14:21.072909 ==
5669 12:14:21.076052 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 12:14:21.079710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 12:14:21.079820 ==
5672 12:14:21.082931 RX Vref Scan: 0
5673 12:14:21.083050
5674 12:14:21.083115 RX Vref 0 -> 0, step: 1
5675 12:14:21.083176
5676 12:14:21.085688 RX Delay -80 -> 252, step: 8
5677 12:14:21.089039 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5678 12:14:21.095743 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5679 12:14:21.098880 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5680 12:14:21.102613 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5681 12:14:21.105732 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5682 12:14:21.108878 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5683 12:14:21.112593 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5684 12:14:21.116068 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5685 12:14:21.122336 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5686 12:14:21.125649 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5687 12:14:21.129295 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5688 12:14:21.132408 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5689 12:14:21.135601 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5690 12:14:21.142207 iDelay=208, Bit 13, Center 107 (24 ~ 191) 168
5691 12:14:21.145563 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5692 12:14:21.149126 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5693 12:14:21.149209 ==
5694 12:14:21.151990 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 12:14:21.156000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 12:14:21.156083 ==
5697 12:14:21.158857 DQS Delay:
5698 12:14:21.158939 DQS0 = 0, DQS1 = 0
5699 12:14:21.162157 DQM Delay:
5700 12:14:21.162239 DQM0 = 102, DQM1 = 98
5701 12:14:21.162304 DQ Delay:
5702 12:14:21.165431 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5703 12:14:21.168701 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5704 12:14:21.172482 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5705 12:14:21.179242 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =103
5706 12:14:21.179325
5707 12:14:21.179430
5708 12:14:21.179490 ==
5709 12:14:21.182496 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 12:14:21.185532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 12:14:21.185615 ==
5712 12:14:21.185696
5713 12:14:21.185778
5714 12:14:21.188584 TX Vref Scan disable
5715 12:14:21.188667 == TX Byte 0 ==
5716 12:14:21.195503 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5717 12:14:21.198434 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5718 12:14:21.198516 == TX Byte 1 ==
5719 12:14:21.205044 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5720 12:14:21.208863 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5721 12:14:21.208970 ==
5722 12:14:21.211819 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 12:14:21.215388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 12:14:21.215471 ==
5725 12:14:21.215573
5726 12:14:21.215634
5727 12:14:21.218354 TX Vref Scan disable
5728 12:14:21.222096 == TX Byte 0 ==
5729 12:14:21.225505 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5730 12:14:21.228712 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5731 12:14:21.231826 == TX Byte 1 ==
5732 12:14:21.235587 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5733 12:14:21.238553 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5734 12:14:21.238636
5735 12:14:21.241625 [DATLAT]
5736 12:14:21.241710 Freq=933, CH1 RK0
5737 12:14:21.241776
5738 12:14:21.245147 DATLAT Default: 0xd
5739 12:14:21.245229 0, 0xFFFF, sum = 0
5740 12:14:21.248754 1, 0xFFFF, sum = 0
5741 12:14:21.248838 2, 0xFFFF, sum = 0
5742 12:14:21.251926 3, 0xFFFF, sum = 0
5743 12:14:21.252009 4, 0xFFFF, sum = 0
5744 12:14:21.255063 5, 0xFFFF, sum = 0
5745 12:14:21.255147 6, 0xFFFF, sum = 0
5746 12:14:21.258200 7, 0xFFFF, sum = 0
5747 12:14:21.258283 8, 0xFFFF, sum = 0
5748 12:14:21.261803 9, 0xFFFF, sum = 0
5749 12:14:21.261917 10, 0x0, sum = 1
5750 12:14:21.265061 11, 0x0, sum = 2
5751 12:14:21.265150 12, 0x0, sum = 3
5752 12:14:21.269066 13, 0x0, sum = 4
5753 12:14:21.269149 best_step = 11
5754 12:14:21.269213
5755 12:14:21.269273 ==
5756 12:14:21.271569 Dram Type= 6, Freq= 0, CH_1, rank 0
5757 12:14:21.278524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5758 12:14:21.278607 ==
5759 12:14:21.278672 RX Vref Scan: 1
5760 12:14:21.278731
5761 12:14:21.281972 RX Vref 0 -> 0, step: 1
5762 12:14:21.282054
5763 12:14:21.285149 RX Delay -45 -> 252, step: 4
5764 12:14:21.285272
5765 12:14:21.288867 Set Vref, RX VrefLevel [Byte0]: 54
5766 12:14:21.291788 [Byte1]: 48
5767 12:14:21.291890
5768 12:14:21.294902 Final RX Vref Byte 0 = 54 to rank0
5769 12:14:21.298156 Final RX Vref Byte 1 = 48 to rank0
5770 12:14:21.301934 Final RX Vref Byte 0 = 54 to rank1
5771 12:14:21.305008 Final RX Vref Byte 1 = 48 to rank1==
5772 12:14:21.308160 Dram Type= 6, Freq= 0, CH_1, rank 0
5773 12:14:21.311385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5774 12:14:21.311458 ==
5775 12:14:21.314703 DQS Delay:
5776 12:14:21.314803 DQS0 = 0, DQS1 = 0
5777 12:14:21.318351 DQM Delay:
5778 12:14:21.318449 DQM0 = 103, DQM1 = 99
5779 12:14:21.318541 DQ Delay:
5780 12:14:21.321245 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =102
5781 12:14:21.324890 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =102
5782 12:14:21.327935 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =94
5783 12:14:21.334562 DQ12 =106, DQ13 =104, DQ14 =104, DQ15 =106
5784 12:14:21.334660
5785 12:14:21.334754
5786 12:14:21.341370 [DQSOSCAuto] RK0, (LSB)MR18= 0x132b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
5787 12:14:21.344395 CH1 RK0: MR19=505, MR18=132B
5788 12:14:21.351022 CH1_RK0: MR19=0x505, MR18=0x132B, DQSOSC=408, MR23=63, INC=65, DEC=43
5789 12:14:21.351180
5790 12:14:21.354572 ----->DramcWriteLeveling(PI) begin...
5791 12:14:21.354657 ==
5792 12:14:21.357988 Dram Type= 6, Freq= 0, CH_1, rank 1
5793 12:14:21.361114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5794 12:14:21.361197 ==
5795 12:14:21.364635 Write leveling (Byte 0): 28 => 28
5796 12:14:21.367681 Write leveling (Byte 1): 28 => 28
5797 12:14:21.371431 DramcWriteLeveling(PI) end<-----
5798 12:14:21.371513
5799 12:14:21.371615 ==
5800 12:14:21.375149 Dram Type= 6, Freq= 0, CH_1, rank 1
5801 12:14:21.378204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 12:14:21.378287 ==
5803 12:14:21.381599 [Gating] SW mode calibration
5804 12:14:21.387658 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5805 12:14:21.394362 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5806 12:14:21.398242 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 12:14:21.401391 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 12:14:21.407556 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 12:14:21.411208 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 12:14:21.414340 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 12:14:21.421315 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5812 12:14:21.424450 0 14 24 | B1->B0 | 2e2e 3030 | 1 1 | (1 0) (1 1)
5813 12:14:21.427744 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 12:14:21.434087 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 12:14:21.437621 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 12:14:21.440840 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 12:14:21.447894 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 12:14:21.450925 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 12:14:21.453934 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 12:14:21.460689 0 15 24 | B1->B0 | 3737 3030 | 0 0 | (0 0) (0 0)
5821 12:14:21.464149 0 15 28 | B1->B0 | 4646 4040 | 0 1 | (0 0) (0 0)
5822 12:14:21.467075 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 12:14:21.473928 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 12:14:21.477292 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 12:14:21.480714 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 12:14:21.487310 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 12:14:21.490659 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 12:14:21.493776 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5829 12:14:21.500882 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5830 12:14:21.503877 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 12:14:21.507338 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 12:14:21.514327 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 12:14:21.517232 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 12:14:21.521070 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 12:14:21.527342 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 12:14:21.530597 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 12:14:21.533747 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 12:14:21.540658 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 12:14:21.543853 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 12:14:21.546932 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 12:14:21.553262 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 12:14:21.557200 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 12:14:21.560270 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5844 12:14:21.566773 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5845 12:14:21.570531 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 12:14:21.573759 Total UI for P1: 0, mck2ui 16
5847 12:14:21.576913 best dqsien dly found for B0: ( 1, 2, 24)
5848 12:14:21.579970 Total UI for P1: 0, mck2ui 16
5849 12:14:21.583567 best dqsien dly found for B1: ( 1, 2, 22)
5850 12:14:21.586776 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5851 12:14:21.590355 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5852 12:14:21.590438
5853 12:14:21.593660 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5854 12:14:21.596972 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5855 12:14:21.600078 [Gating] SW calibration Done
5856 12:14:21.600160 ==
5857 12:14:21.603367 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 12:14:21.606385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 12:14:21.606468 ==
5860 12:14:21.609966 RX Vref Scan: 0
5861 12:14:21.610048
5862 12:14:21.612988 RX Vref 0 -> 0, step: 1
5863 12:14:21.613070
5864 12:14:21.613135 RX Delay -80 -> 252, step: 8
5865 12:14:21.619950 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5866 12:14:21.623596 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5867 12:14:21.626591 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5868 12:14:21.630315 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5869 12:14:21.633341 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5870 12:14:21.636673 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5871 12:14:21.643539 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5872 12:14:21.646614 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5873 12:14:21.650123 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5874 12:14:21.653051 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5875 12:14:21.656814 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5876 12:14:21.660062 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5877 12:14:21.666968 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5878 12:14:21.669987 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5879 12:14:21.673161 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5880 12:14:21.676352 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5881 12:14:21.676434 ==
5882 12:14:21.680203 Dram Type= 6, Freq= 0, CH_1, rank 1
5883 12:14:21.686340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5884 12:14:21.686424 ==
5885 12:14:21.686490 DQS Delay:
5886 12:14:21.690112 DQS0 = 0, DQS1 = 0
5887 12:14:21.690210 DQM Delay:
5888 12:14:21.690274 DQM0 = 104, DQM1 = 99
5889 12:14:21.693232 DQ Delay:
5890 12:14:21.696399 DQ0 =111, DQ1 =99, DQ2 =91, DQ3 =103
5891 12:14:21.700083 DQ4 =95, DQ5 =119, DQ6 =115, DQ7 =99
5892 12:14:21.703142 DQ8 =87, DQ9 =91, DQ10 =103, DQ11 =91
5893 12:14:21.706998 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5894 12:14:21.707080
5895 12:14:21.707144
5896 12:14:21.707210 ==
5897 12:14:21.710192 Dram Type= 6, Freq= 0, CH_1, rank 1
5898 12:14:21.713339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5899 12:14:21.713422 ==
5900 12:14:21.713487
5901 12:14:21.716681
5902 12:14:21.716792 TX Vref Scan disable
5903 12:14:21.719697 == TX Byte 0 ==
5904 12:14:21.723057 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5905 12:14:21.726733 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5906 12:14:21.729680 == TX Byte 1 ==
5907 12:14:21.732958 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5908 12:14:21.736425 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5909 12:14:21.736511 ==
5910 12:14:21.739772 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 12:14:21.746266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 12:14:21.746389 ==
5913 12:14:21.746482
5914 12:14:21.746570
5915 12:14:21.746656 TX Vref Scan disable
5916 12:14:21.750064 == TX Byte 0 ==
5917 12:14:21.753560 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5918 12:14:21.760191 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5919 12:14:21.760323 == TX Byte 1 ==
5920 12:14:21.763397 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5921 12:14:21.770387 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5922 12:14:21.770471
5923 12:14:21.770536 [DATLAT]
5924 12:14:21.770597 Freq=933, CH1 RK1
5925 12:14:21.770656
5926 12:14:21.773614 DATLAT Default: 0xb
5927 12:14:21.773734 0, 0xFFFF, sum = 0
5928 12:14:21.776756 1, 0xFFFF, sum = 0
5929 12:14:21.776840 2, 0xFFFF, sum = 0
5930 12:14:21.779900 3, 0xFFFF, sum = 0
5931 12:14:21.783799 4, 0xFFFF, sum = 0
5932 12:14:21.783887 5, 0xFFFF, sum = 0
5933 12:14:21.786703 6, 0xFFFF, sum = 0
5934 12:14:21.786790 7, 0xFFFF, sum = 0
5935 12:14:21.790280 8, 0xFFFF, sum = 0
5936 12:14:21.790364 9, 0xFFFF, sum = 0
5937 12:14:21.793244 10, 0x0, sum = 1
5938 12:14:21.793344 11, 0x0, sum = 2
5939 12:14:21.796827 12, 0x0, sum = 3
5940 12:14:21.796911 13, 0x0, sum = 4
5941 12:14:21.797001 best_step = 11
5942 12:14:21.797081
5943 12:14:21.800000 ==
5944 12:14:21.803387 Dram Type= 6, Freq= 0, CH_1, rank 1
5945 12:14:21.806388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5946 12:14:21.806486 ==
5947 12:14:21.806552 RX Vref Scan: 0
5948 12:14:21.806612
5949 12:14:21.810102 RX Vref 0 -> 0, step: 1
5950 12:14:21.810184
5951 12:14:21.813694 RX Delay -45 -> 252, step: 4
5952 12:14:21.816751 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5953 12:14:21.823252 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5954 12:14:21.826317 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5955 12:14:21.830012 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5956 12:14:21.833058 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5957 12:14:21.836838 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5958 12:14:21.842967 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5959 12:14:21.846289 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5960 12:14:21.850110 iDelay=203, Bit 8, Center 86 (-1 ~ 174) 176
5961 12:14:21.853672 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5962 12:14:21.856438 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5963 12:14:21.863134 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5964 12:14:21.866234 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5965 12:14:21.869761 iDelay=203, Bit 13, Center 104 (19 ~ 190) 172
5966 12:14:21.873489 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5967 12:14:21.876766 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5968 12:14:21.876848 ==
5969 12:14:21.880070 Dram Type= 6, Freq= 0, CH_1, rank 1
5970 12:14:21.886274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5971 12:14:21.886358 ==
5972 12:14:21.886427 DQS Delay:
5973 12:14:21.889948 DQS0 = 0, DQS1 = 0
5974 12:14:21.890031 DQM Delay:
5975 12:14:21.893388 DQM0 = 104, DQM1 = 99
5976 12:14:21.893470 DQ Delay:
5977 12:14:21.896703 DQ0 =110, DQ1 =102, DQ2 =94, DQ3 =100
5978 12:14:21.899475 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =102
5979 12:14:21.902712 DQ8 =86, DQ9 =88, DQ10 =98, DQ11 =94
5980 12:14:21.906233 DQ12 =108, DQ13 =104, DQ14 =106, DQ15 =110
5981 12:14:21.906316
5982 12:14:21.906381
5983 12:14:21.916132 [DQSOSCAuto] RK1, (LSB)MR18= 0x2afd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5984 12:14:21.916217 CH1 RK1: MR19=504, MR18=2AFD
5985 12:14:21.922993 CH1_RK1: MR19=0x504, MR18=0x2AFD, DQSOSC=408, MR23=63, INC=65, DEC=43
5986 12:14:21.926449 [RxdqsGatingPostProcess] freq 933
5987 12:14:21.932823 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5988 12:14:21.935967 best DQS0 dly(2T, 0.5T) = (0, 10)
5989 12:14:21.939527 best DQS1 dly(2T, 0.5T) = (0, 10)
5990 12:14:21.942703 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5991 12:14:21.946404 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5992 12:14:21.946486 best DQS0 dly(2T, 0.5T) = (0, 10)
5993 12:14:21.949704 best DQS1 dly(2T, 0.5T) = (0, 10)
5994 12:14:21.952751 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5995 12:14:21.956496 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5996 12:14:21.959487 Pre-setting of DQS Precalculation
5997 12:14:21.966485 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5998 12:14:21.972584 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5999 12:14:21.979129 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6000 12:14:21.979212
6001 12:14:21.979277
6002 12:14:21.982636 [Calibration Summary] 1866 Mbps
6003 12:14:21.982720 CH 0, Rank 0
6004 12:14:21.985986 SW Impedance : PASS
6005 12:14:21.989101 DUTY Scan : NO K
6006 12:14:21.989176 ZQ Calibration : PASS
6007 12:14:21.992910 Jitter Meter : NO K
6008 12:14:21.996093 CBT Training : PASS
6009 12:14:21.996161 Write leveling : PASS
6010 12:14:21.999175 RX DQS gating : PASS
6011 12:14:22.002898 RX DQ/DQS(RDDQC) : PASS
6012 12:14:22.002974 TX DQ/DQS : PASS
6013 12:14:22.006057 RX DATLAT : PASS
6014 12:14:22.009105 RX DQ/DQS(Engine): PASS
6015 12:14:22.009173 TX OE : NO K
6016 12:14:22.009237 All Pass.
6017 12:14:22.012608
6018 12:14:22.012678 CH 0, Rank 1
6019 12:14:22.015953 SW Impedance : PASS
6020 12:14:22.016031 DUTY Scan : NO K
6021 12:14:22.019023 ZQ Calibration : PASS
6022 12:14:22.022801 Jitter Meter : NO K
6023 12:14:22.022875 CBT Training : PASS
6024 12:14:22.025792 Write leveling : PASS
6025 12:14:22.025863 RX DQS gating : PASS
6026 12:14:22.029184 RX DQ/DQS(RDDQC) : PASS
6027 12:14:22.032495 TX DQ/DQS : PASS
6028 12:14:22.032571 RX DATLAT : PASS
6029 12:14:22.035670 RX DQ/DQS(Engine): PASS
6030 12:14:22.038911 TX OE : NO K
6031 12:14:22.038984 All Pass.
6032 12:14:22.039044
6033 12:14:22.039106 CH 1, Rank 0
6034 12:14:22.042280 SW Impedance : PASS
6035 12:14:22.045236 DUTY Scan : NO K
6036 12:14:22.045302 ZQ Calibration : PASS
6037 12:14:22.048711 Jitter Meter : NO K
6038 12:14:22.052205 CBT Training : PASS
6039 12:14:22.052280 Write leveling : PASS
6040 12:14:22.055600 RX DQS gating : PASS
6041 12:14:22.058551 RX DQ/DQS(RDDQC) : PASS
6042 12:14:22.058655 TX DQ/DQS : PASS
6043 12:14:22.062413 RX DATLAT : PASS
6044 12:14:22.065557 RX DQ/DQS(Engine): PASS
6045 12:14:22.065654 TX OE : NO K
6046 12:14:22.065746 All Pass.
6047 12:14:22.068540
6048 12:14:22.068640 CH 1, Rank 1
6049 12:14:22.071975 SW Impedance : PASS
6050 12:14:22.072068 DUTY Scan : NO K
6051 12:14:22.075520 ZQ Calibration : PASS
6052 12:14:22.078633 Jitter Meter : NO K
6053 12:14:22.078729 CBT Training : PASS
6054 12:14:22.082282 Write leveling : PASS
6055 12:14:22.082381 RX DQS gating : PASS
6056 12:14:22.085136 RX DQ/DQS(RDDQC) : PASS
6057 12:14:22.088391 TX DQ/DQS : PASS
6058 12:14:22.088475 RX DATLAT : PASS
6059 12:14:22.092188 RX DQ/DQS(Engine): PASS
6060 12:14:22.095368 TX OE : NO K
6061 12:14:22.095451 All Pass.
6062 12:14:22.095515
6063 12:14:22.098582 DramC Write-DBI off
6064 12:14:22.098664 PER_BANK_REFRESH: Hybrid Mode
6065 12:14:22.101628 TX_TRACKING: ON
6066 12:14:22.112037 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6067 12:14:22.115085 [FAST_K] Save calibration result to emmc
6068 12:14:22.118733 dramc_set_vcore_voltage set vcore to 650000
6069 12:14:22.118816 Read voltage for 400, 6
6070 12:14:22.121612 Vio18 = 0
6071 12:14:22.121694 Vcore = 650000
6072 12:14:22.121758 Vdram = 0
6073 12:14:22.124915 Vddq = 0
6074 12:14:22.124997 Vmddr = 0
6075 12:14:22.128756 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6076 12:14:22.135094 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6077 12:14:22.138231 MEM_TYPE=3, freq_sel=20
6078 12:14:22.141747 sv_algorithm_assistance_LP4_800
6079 12:14:22.144879 ============ PULL DRAM RESETB DOWN ============
6080 12:14:22.148000 ========== PULL DRAM RESETB DOWN end =========
6081 12:14:22.155079 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6082 12:14:22.158107 ===================================
6083 12:14:22.158193 LPDDR4 DRAM CONFIGURATION
6084 12:14:22.161485 ===================================
6085 12:14:22.165150 EX_ROW_EN[0] = 0x0
6086 12:14:22.165232 EX_ROW_EN[1] = 0x0
6087 12:14:22.168247 LP4Y_EN = 0x0
6088 12:14:22.171798 WORK_FSP = 0x0
6089 12:14:22.171882 WL = 0x2
6090 12:14:22.174545 RL = 0x2
6091 12:14:22.174631 BL = 0x2
6092 12:14:22.177993 RPST = 0x0
6093 12:14:22.178075 RD_PRE = 0x0
6094 12:14:22.181337 WR_PRE = 0x1
6095 12:14:22.181419 WR_PST = 0x0
6096 12:14:22.184545 DBI_WR = 0x0
6097 12:14:22.184628 DBI_RD = 0x0
6098 12:14:22.188264 OTF = 0x1
6099 12:14:22.191475 ===================================
6100 12:14:22.194395 ===================================
6101 12:14:22.194478 ANA top config
6102 12:14:22.197805 ===================================
6103 12:14:22.201015 DLL_ASYNC_EN = 0
6104 12:14:22.204776 ALL_SLAVE_EN = 1
6105 12:14:22.204859 NEW_RANK_MODE = 1
6106 12:14:22.207892 DLL_IDLE_MODE = 1
6107 12:14:22.211200 LP45_APHY_COMB_EN = 1
6108 12:14:22.214310 TX_ODT_DIS = 1
6109 12:14:22.218035 NEW_8X_MODE = 1
6110 12:14:22.221199 ===================================
6111 12:14:22.224210 ===================================
6112 12:14:22.224352 data_rate = 800
6113 12:14:22.228009 CKR = 1
6114 12:14:22.231039 DQ_P2S_RATIO = 4
6115 12:14:22.234061 ===================================
6116 12:14:22.237823 CA_P2S_RATIO = 4
6117 12:14:22.241086 DQ_CA_OPEN = 0
6118 12:14:22.244269 DQ_SEMI_OPEN = 1
6119 12:14:22.244392 CA_SEMI_OPEN = 1
6120 12:14:22.247579 CA_FULL_RATE = 0
6121 12:14:22.251216 DQ_CKDIV4_EN = 0
6122 12:14:22.254369 CA_CKDIV4_EN = 1
6123 12:14:22.257389 CA_PREDIV_EN = 0
6124 12:14:22.261193 PH8_DLY = 0
6125 12:14:22.261276 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6126 12:14:22.264305 DQ_AAMCK_DIV = 0
6127 12:14:22.267568 CA_AAMCK_DIV = 0
6128 12:14:22.271447 CA_ADMCK_DIV = 4
6129 12:14:22.274406 DQ_TRACK_CA_EN = 0
6130 12:14:22.277603 CA_PICK = 800
6131 12:14:22.277702 CA_MCKIO = 400
6132 12:14:22.281241 MCKIO_SEMI = 400
6133 12:14:22.284631 PLL_FREQ = 3016
6134 12:14:22.288000 DQ_UI_PI_RATIO = 32
6135 12:14:22.290847 CA_UI_PI_RATIO = 32
6136 12:14:22.293982 ===================================
6137 12:14:22.297095 ===================================
6138 12:14:22.300555 memory_type:LPDDR4
6139 12:14:22.300655 GP_NUM : 10
6140 12:14:22.304131 SRAM_EN : 1
6141 12:14:22.307380 MD32_EN : 0
6142 12:14:22.310666 ===================================
6143 12:14:22.310750 [ANA_INIT] >>>>>>>>>>>>>>
6144 12:14:22.314131 <<<<<< [CONFIGURE PHASE]: ANA_TX
6145 12:14:22.317613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6146 12:14:22.320876 ===================================
6147 12:14:22.323989 data_rate = 800,PCW = 0X7400
6148 12:14:22.327197 ===================================
6149 12:14:22.330927 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6150 12:14:22.337268 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6151 12:14:22.346814 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6152 12:14:22.350425 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6153 12:14:22.356995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6154 12:14:22.360222 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6155 12:14:22.360350 [ANA_INIT] flow start
6156 12:14:22.363494 [ANA_INIT] PLL >>>>>>>>
6157 12:14:22.366615 [ANA_INIT] PLL <<<<<<<<
6158 12:14:22.366698 [ANA_INIT] MIDPI >>>>>>>>
6159 12:14:22.370139 [ANA_INIT] MIDPI <<<<<<<<
6160 12:14:22.373826 [ANA_INIT] DLL >>>>>>>>
6161 12:14:22.373909 [ANA_INIT] flow end
6162 12:14:22.380159 ============ LP4 DIFF to SE enter ============
6163 12:14:22.383687 ============ LP4 DIFF to SE exit ============
6164 12:14:22.383773 [ANA_INIT] <<<<<<<<<<<<<
6165 12:14:22.386589 [Flow] Enable top DCM control >>>>>
6166 12:14:22.390592 [Flow] Enable top DCM control <<<<<
6167 12:14:22.393596 Enable DLL master slave shuffle
6168 12:14:22.400063 ==============================================================
6169 12:14:22.403051 Gating Mode config
6170 12:14:22.406569 ==============================================================
6171 12:14:22.409753 Config description:
6172 12:14:22.419947 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6173 12:14:22.426401 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6174 12:14:22.429722 SELPH_MODE 0: By rank 1: By Phase
6175 12:14:22.436643 ==============================================================
6176 12:14:22.439547 GAT_TRACK_EN = 0
6177 12:14:22.442981 RX_GATING_MODE = 2
6178 12:14:22.446144 RX_GATING_TRACK_MODE = 2
6179 12:14:22.446262 SELPH_MODE = 1
6180 12:14:22.450029 PICG_EARLY_EN = 1
6181 12:14:22.452807 VALID_LAT_VALUE = 1
6182 12:14:22.459935 ==============================================================
6183 12:14:22.463118 Enter into Gating configuration >>>>
6184 12:14:22.466183 Exit from Gating configuration <<<<
6185 12:14:22.469929 Enter into DVFS_PRE_config >>>>>
6186 12:14:22.479633 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6187 12:14:22.483058 Exit from DVFS_PRE_config <<<<<
6188 12:14:22.486181 Enter into PICG configuration >>>>
6189 12:14:22.489618 Exit from PICG configuration <<<<
6190 12:14:22.492838 [RX_INPUT] configuration >>>>>
6191 12:14:22.495961 [RX_INPUT] configuration <<<<<
6192 12:14:22.499618 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6193 12:14:22.506593 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6194 12:14:22.512920 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6195 12:14:22.519894 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6196 12:14:22.523106 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6197 12:14:22.529490 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6198 12:14:22.532986 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6199 12:14:22.539671 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6200 12:14:22.542658 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6201 12:14:22.546401 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6202 12:14:22.549631 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6203 12:14:22.556051 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6204 12:14:22.559308 ===================================
6205 12:14:22.562539 LPDDR4 DRAM CONFIGURATION
6206 12:14:22.565854 ===================================
6207 12:14:22.565938 EX_ROW_EN[0] = 0x0
6208 12:14:22.569206 EX_ROW_EN[1] = 0x0
6209 12:14:22.569290 LP4Y_EN = 0x0
6210 12:14:22.572769 WORK_FSP = 0x0
6211 12:14:22.572853 WL = 0x2
6212 12:14:22.577427 RL = 0x2
6213 12:14:22.577511 BL = 0x2
6214 12:14:22.579128 RPST = 0x0
6215 12:14:22.579211 RD_PRE = 0x0
6216 12:14:22.582620 WR_PRE = 0x1
6217 12:14:22.582703 WR_PST = 0x0
6218 12:14:22.585767 DBI_WR = 0x0
6219 12:14:22.585851 DBI_RD = 0x0
6220 12:14:22.589790 OTF = 0x1
6221 12:14:22.592319 ===================================
6222 12:14:22.595713 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6223 12:14:22.598946 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6224 12:14:22.605699 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6225 12:14:22.609139 ===================================
6226 12:14:22.609226 LPDDR4 DRAM CONFIGURATION
6227 12:14:22.612865 ===================================
6228 12:14:22.615639 EX_ROW_EN[0] = 0x10
6229 12:14:22.618806 EX_ROW_EN[1] = 0x0
6230 12:14:22.618889 LP4Y_EN = 0x0
6231 12:14:22.622731 WORK_FSP = 0x0
6232 12:14:22.622814 WL = 0x2
6233 12:14:22.625827 RL = 0x2
6234 12:14:22.625909 BL = 0x2
6235 12:14:22.629002 RPST = 0x0
6236 12:14:22.629085 RD_PRE = 0x0
6237 12:14:22.632039 WR_PRE = 0x1
6238 12:14:22.632121 WR_PST = 0x0
6239 12:14:22.635515 DBI_WR = 0x0
6240 12:14:22.635631 DBI_RD = 0x0
6241 12:14:22.638713 OTF = 0x1
6242 12:14:22.642569 ===================================
6243 12:14:22.648825 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6244 12:14:22.652706 nWR fixed to 30
6245 12:14:22.655642 [ModeRegInit_LP4] CH0 RK0
6246 12:14:22.655724 [ModeRegInit_LP4] CH0 RK1
6247 12:14:22.658903 [ModeRegInit_LP4] CH1 RK0
6248 12:14:22.662079 [ModeRegInit_LP4] CH1 RK1
6249 12:14:22.662161 match AC timing 19
6250 12:14:22.668974 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6251 12:14:22.672451 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6252 12:14:22.675786 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6253 12:14:22.681896 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6254 12:14:22.685763 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6255 12:14:22.685847 ==
6256 12:14:22.688895 Dram Type= 6, Freq= 0, CH_0, rank 0
6257 12:14:22.691979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6258 12:14:22.692089 ==
6259 12:14:22.698808 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6260 12:14:22.705167 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6261 12:14:22.708954 [CA 0] Center 36 (8~64) winsize 57
6262 12:14:22.712061 [CA 1] Center 36 (8~64) winsize 57
6263 12:14:22.712145 [CA 2] Center 36 (8~64) winsize 57
6264 12:14:22.715472 [CA 3] Center 36 (8~64) winsize 57
6265 12:14:22.718803 [CA 4] Center 36 (8~64) winsize 57
6266 12:14:22.721933 [CA 5] Center 36 (8~64) winsize 57
6267 12:14:22.722057
6268 12:14:22.724982 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6269 12:14:22.725107
6270 12:14:22.731581 [CATrainingPosCal] consider 1 rank data
6271 12:14:22.731680 u2DelayCellTimex100 = 270/100 ps
6272 12:14:22.738839 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 12:14:22.741461 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 12:14:22.745208 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 12:14:22.748445 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 12:14:22.752208 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 12:14:22.755428 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 12:14:22.755512
6279 12:14:22.758575 CA PerBit enable=1, Macro0, CA PI delay=36
6280 12:14:22.758661
6281 12:14:22.761815 [CBTSetCACLKResult] CA Dly = 36
6282 12:14:22.764878 CS Dly: 1 (0~32)
6283 12:14:22.764956 ==
6284 12:14:22.768663 Dram Type= 6, Freq= 0, CH_0, rank 1
6285 12:14:22.771905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6286 12:14:22.771988 ==
6287 12:14:22.778541 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6288 12:14:22.781945 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6289 12:14:22.785278 [CA 0] Center 36 (8~64) winsize 57
6290 12:14:22.788364 [CA 1] Center 36 (8~64) winsize 57
6291 12:14:22.792108 [CA 2] Center 36 (8~64) winsize 57
6292 12:14:22.795272 [CA 3] Center 36 (8~64) winsize 57
6293 12:14:22.798330 [CA 4] Center 36 (8~64) winsize 57
6294 12:14:22.801735 [CA 5] Center 36 (8~64) winsize 57
6295 12:14:22.801825
6296 12:14:22.805209 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6297 12:14:22.805292
6298 12:14:22.808277 [CATrainingPosCal] consider 2 rank data
6299 12:14:22.811980 u2DelayCellTimex100 = 270/100 ps
6300 12:14:22.814808 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 12:14:22.818649 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 12:14:22.821676 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 12:14:22.825008 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 12:14:22.831378 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 12:14:22.834956 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 12:14:22.835146
6307 12:14:22.838637 CA PerBit enable=1, Macro0, CA PI delay=36
6308 12:14:22.838723
6309 12:14:22.841736 [CBTSetCACLKResult] CA Dly = 36
6310 12:14:22.841821 CS Dly: 1 (0~32)
6311 12:14:22.841889
6312 12:14:22.845349 ----->DramcWriteLeveling(PI) begin...
6313 12:14:22.845435 ==
6314 12:14:22.848190 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 12:14:22.855186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 12:14:22.855274 ==
6317 12:14:22.858812 Write leveling (Byte 0): 40 => 8
6318 12:14:22.858898 Write leveling (Byte 1): 40 => 8
6319 12:14:22.861603 DramcWriteLeveling(PI) end<-----
6320 12:14:22.861688
6321 12:14:22.861756 ==
6322 12:14:22.864847 Dram Type= 6, Freq= 0, CH_0, rank 0
6323 12:14:22.871359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6324 12:14:22.871443 ==
6325 12:14:22.874712 [Gating] SW mode calibration
6326 12:14:22.881316 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6327 12:14:22.884807 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6328 12:14:22.891331 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6329 12:14:22.894236 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6330 12:14:22.897811 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6331 12:14:22.904601 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6332 12:14:22.907824 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6333 12:14:22.911043 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6334 12:14:22.917629 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6335 12:14:22.921372 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6336 12:14:22.924126 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6337 12:14:22.928017 Total UI for P1: 0, mck2ui 16
6338 12:14:22.931179 best dqsien dly found for B0: ( 0, 14, 24)
6339 12:14:22.934255 Total UI for P1: 0, mck2ui 16
6340 12:14:22.937512 best dqsien dly found for B1: ( 0, 14, 24)
6341 12:14:22.941091 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6342 12:14:22.944215 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6343 12:14:22.944317
6344 12:14:22.951193 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6345 12:14:22.954671 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6346 12:14:22.954783 [Gating] SW calibration Done
6347 12:14:22.957935 ==
6348 12:14:22.960992 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 12:14:22.964004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 12:14:22.964096 ==
6351 12:14:22.964163 RX Vref Scan: 0
6352 12:14:22.964224
6353 12:14:22.967910 RX Vref 0 -> 0, step: 1
6354 12:14:22.967993
6355 12:14:22.970932 RX Delay -410 -> 252, step: 16
6356 12:14:22.974210 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6357 12:14:22.977328 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6358 12:14:22.984044 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6359 12:14:22.987442 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6360 12:14:22.990811 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6361 12:14:22.994208 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6362 12:14:23.000791 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6363 12:14:23.003929 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6364 12:14:23.007294 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6365 12:14:23.010714 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6366 12:14:23.017424 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6367 12:14:23.020822 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6368 12:14:23.024056 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6369 12:14:23.027335 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6370 12:14:23.033854 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6371 12:14:23.037650 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6372 12:14:23.037731 ==
6373 12:14:23.041086 Dram Type= 6, Freq= 0, CH_0, rank 0
6374 12:14:23.043934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6375 12:14:23.044008 ==
6376 12:14:23.047197 DQS Delay:
6377 12:14:23.047275 DQS0 = 27, DQS1 = 35
6378 12:14:23.051007 DQM Delay:
6379 12:14:23.051077 DQM0 = 8, DQM1 = 12
6380 12:14:23.051145 DQ Delay:
6381 12:14:23.054293 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6382 12:14:23.057387 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6383 12:14:23.060909 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6384 12:14:23.064031 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6385 12:14:23.064109
6386 12:14:23.064179
6387 12:14:23.064237 ==
6388 12:14:23.067168 Dram Type= 6, Freq= 0, CH_0, rank 0
6389 12:14:23.073932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6390 12:14:23.074060 ==
6391 12:14:23.074132
6392 12:14:23.074192
6393 12:14:23.074249 TX Vref Scan disable
6394 12:14:23.077677 == TX Byte 0 ==
6395 12:14:23.080843 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6396 12:14:23.084195 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6397 12:14:23.087244 == TX Byte 1 ==
6398 12:14:23.090394 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6399 12:14:23.094188 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6400 12:14:23.094267 ==
6401 12:14:23.097178 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 12:14:23.103958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 12:14:23.104065 ==
6404 12:14:23.104157
6405 12:14:23.104252
6406 12:14:23.104363 TX Vref Scan disable
6407 12:14:23.107055 == TX Byte 0 ==
6408 12:14:23.110290 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6409 12:14:23.113787 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6410 12:14:23.117239 == TX Byte 1 ==
6411 12:14:23.120419 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6412 12:14:23.123709 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6413 12:14:23.123789
6414 12:14:23.127353 [DATLAT]
6415 12:14:23.127431 Freq=400, CH0 RK0
6416 12:14:23.127518
6417 12:14:23.130590 DATLAT Default: 0xf
6418 12:14:23.130667 0, 0xFFFF, sum = 0
6419 12:14:23.133729 1, 0xFFFF, sum = 0
6420 12:14:23.133816 2, 0xFFFF, sum = 0
6421 12:14:23.136975 3, 0xFFFF, sum = 0
6422 12:14:23.137061 4, 0xFFFF, sum = 0
6423 12:14:23.140202 5, 0xFFFF, sum = 0
6424 12:14:23.140336 6, 0xFFFF, sum = 0
6425 12:14:23.143500 7, 0xFFFF, sum = 0
6426 12:14:23.143584 8, 0xFFFF, sum = 0
6427 12:14:23.147114 9, 0xFFFF, sum = 0
6428 12:14:23.147205 10, 0xFFFF, sum = 0
6429 12:14:23.150306 11, 0xFFFF, sum = 0
6430 12:14:23.153460 12, 0xFFFF, sum = 0
6431 12:14:23.153539 13, 0x0, sum = 1
6432 12:14:23.156758 14, 0x0, sum = 2
6433 12:14:23.156835 15, 0x0, sum = 3
6434 12:14:23.156918 16, 0x0, sum = 4
6435 12:14:23.160473 best_step = 14
6436 12:14:23.160550
6437 12:14:23.160648 ==
6438 12:14:23.163806 Dram Type= 6, Freq= 0, CH_0, rank 0
6439 12:14:23.166931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6440 12:14:23.167018 ==
6441 12:14:23.170093 RX Vref Scan: 1
6442 12:14:23.170188
6443 12:14:23.170274 RX Vref 0 -> 0, step: 1
6444 12:14:23.173553
6445 12:14:23.173639 RX Delay -311 -> 252, step: 8
6446 12:14:23.173732
6447 12:14:23.176640 Set Vref, RX VrefLevel [Byte0]: 55
6448 12:14:23.180247 [Byte1]: 45
6449 12:14:23.185385
6450 12:14:23.185470 Final RX Vref Byte 0 = 55 to rank0
6451 12:14:23.188256 Final RX Vref Byte 1 = 45 to rank0
6452 12:14:23.191577 Final RX Vref Byte 0 = 55 to rank1
6453 12:14:23.194814 Final RX Vref Byte 1 = 45 to rank1==
6454 12:14:23.198613 Dram Type= 6, Freq= 0, CH_0, rank 0
6455 12:14:23.204764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 12:14:23.204856 ==
6457 12:14:23.204958 DQS Delay:
6458 12:14:23.208404 DQS0 = 28, DQS1 = 36
6459 12:14:23.208513 DQM Delay:
6460 12:14:23.208614 DQM0 = 11, DQM1 = 12
6461 12:14:23.211559 DQ Delay:
6462 12:14:23.215146 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6463 12:14:23.215281 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6464 12:14:23.218160 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6465 12:14:23.222028 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6466 12:14:23.222103
6467 12:14:23.225017
6468 12:14:23.231481 [DQSOSCAuto] RK0, (LSB)MR18= 0xcdb9, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6469 12:14:23.234784 CH0 RK0: MR19=C0C, MR18=CDB9
6470 12:14:23.241377 CH0_RK0: MR19=0xC0C, MR18=0xCDB9, DQSOSC=384, MR23=63, INC=400, DEC=267
6471 12:14:23.241459 ==
6472 12:14:23.245140 Dram Type= 6, Freq= 0, CH_0, rank 1
6473 12:14:23.248399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6474 12:14:23.248479 ==
6475 12:14:23.251442 [Gating] SW mode calibration
6476 12:14:23.258296 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6477 12:14:23.264511 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6478 12:14:23.268632 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6479 12:14:23.271714 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6480 12:14:23.278041 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6481 12:14:23.281519 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6482 12:14:23.284970 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6483 12:14:23.287977 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6484 12:14:23.294369 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6485 12:14:23.297835 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6486 12:14:23.301377 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6487 12:14:23.304777 Total UI for P1: 0, mck2ui 16
6488 12:14:23.307794 best dqsien dly found for B0: ( 0, 14, 24)
6489 12:14:23.311444 Total UI for P1: 0, mck2ui 16
6490 12:14:23.314511 best dqsien dly found for B1: ( 0, 14, 24)
6491 12:14:23.317747 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6492 12:14:23.324949 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6493 12:14:23.325034
6494 12:14:23.327771 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6495 12:14:23.331354 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6496 12:14:23.334502 [Gating] SW calibration Done
6497 12:14:23.334578 ==
6498 12:14:23.337900 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 12:14:23.341007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 12:14:23.341092 ==
6501 12:14:23.344233 RX Vref Scan: 0
6502 12:14:23.344356
6503 12:14:23.344439 RX Vref 0 -> 0, step: 1
6504 12:14:23.344519
6505 12:14:23.347950 RX Delay -410 -> 252, step: 16
6506 12:14:23.351084 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6507 12:14:23.357956 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6508 12:14:23.360834 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6509 12:14:23.364692 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6510 12:14:23.367885 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6511 12:14:23.374776 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6512 12:14:23.377868 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6513 12:14:23.380828 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6514 12:14:23.384747 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6515 12:14:23.391116 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6516 12:14:23.394173 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6517 12:14:23.397968 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6518 12:14:23.400773 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6519 12:14:23.407974 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6520 12:14:23.411108 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6521 12:14:23.414252 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6522 12:14:23.414332 ==
6523 12:14:23.417792 Dram Type= 6, Freq= 0, CH_0, rank 1
6524 12:14:23.421316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6525 12:14:23.424401 ==
6526 12:14:23.424484 DQS Delay:
6527 12:14:23.424566 DQS0 = 27, DQS1 = 35
6528 12:14:23.427521 DQM Delay:
6529 12:14:23.427603 DQM0 = 12, DQM1 = 12
6530 12:14:23.430825 DQ Delay:
6531 12:14:23.430901 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6532 12:14:23.434751 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6533 12:14:23.437546 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6534 12:14:23.441026 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6535 12:14:23.441113
6536 12:14:23.441197
6537 12:14:23.441277 ==
6538 12:14:23.444170 Dram Type= 6, Freq= 0, CH_0, rank 1
6539 12:14:23.450694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6540 12:14:23.450788 ==
6541 12:14:23.450872
6542 12:14:23.450954
6543 12:14:23.454150 TX Vref Scan disable
6544 12:14:23.454235 == TX Byte 0 ==
6545 12:14:23.457332 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6546 12:14:23.460752 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6547 12:14:23.464213 == TX Byte 1 ==
6548 12:14:23.467217 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6549 12:14:23.471145 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6550 12:14:23.474279 ==
6551 12:14:23.477277 Dram Type= 6, Freq= 0, CH_0, rank 1
6552 12:14:23.480543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6553 12:14:23.480645 ==
6554 12:14:23.480748
6555 12:14:23.480835
6556 12:14:23.484197 TX Vref Scan disable
6557 12:14:23.484327 == TX Byte 0 ==
6558 12:14:23.487255 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6559 12:14:23.493630 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6560 12:14:23.493709 == TX Byte 1 ==
6561 12:14:23.497561 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6562 12:14:23.504055 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6563 12:14:23.504156
6564 12:14:23.504245 [DATLAT]
6565 12:14:23.504406 Freq=400, CH0 RK1
6566 12:14:23.504501
6567 12:14:23.507452 DATLAT Default: 0xe
6568 12:14:23.507526 0, 0xFFFF, sum = 0
6569 12:14:23.510281 1, 0xFFFF, sum = 0
6570 12:14:23.510381 2, 0xFFFF, sum = 0
6571 12:14:23.513665 3, 0xFFFF, sum = 0
6572 12:14:23.516627 4, 0xFFFF, sum = 0
6573 12:14:23.516707 5, 0xFFFF, sum = 0
6574 12:14:23.520396 6, 0xFFFF, sum = 0
6575 12:14:23.520494 7, 0xFFFF, sum = 0
6576 12:14:23.523402 8, 0xFFFF, sum = 0
6577 12:14:23.523507 9, 0xFFFF, sum = 0
6578 12:14:23.527147 10, 0xFFFF, sum = 0
6579 12:14:23.527246 11, 0xFFFF, sum = 0
6580 12:14:23.529817 12, 0xFFFF, sum = 0
6581 12:14:23.529918 13, 0x0, sum = 1
6582 12:14:23.533502 14, 0x0, sum = 2
6583 12:14:23.533580 15, 0x0, sum = 3
6584 12:14:23.536614 16, 0x0, sum = 4
6585 12:14:23.536713 best_step = 14
6586 12:14:23.536801
6587 12:14:23.536864 ==
6588 12:14:23.539592 Dram Type= 6, Freq= 0, CH_0, rank 1
6589 12:14:23.546349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 12:14:23.546427 ==
6591 12:14:23.546497 RX Vref Scan: 0
6592 12:14:23.546574
6593 12:14:23.550092 RX Vref 0 -> 0, step: 1
6594 12:14:23.550166
6595 12:14:23.552906 RX Delay -311 -> 252, step: 8
6596 12:14:23.559593 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6597 12:14:23.562982 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6598 12:14:23.566600 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6599 12:14:23.569937 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6600 12:14:23.576699 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6601 12:14:23.579570 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6602 12:14:23.582843 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6603 12:14:23.586374 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6604 12:14:23.592457 iDelay=217, Bit 8, Center -32 (-247 ~ 184) 432
6605 12:14:23.596011 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6606 12:14:23.599207 iDelay=217, Bit 10, Center -24 (-239 ~ 192) 432
6607 12:14:23.603128 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6608 12:14:23.609313 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6609 12:14:23.612272 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6610 12:14:23.615652 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6611 12:14:23.622623 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6612 12:14:23.622701 ==
6613 12:14:23.625493 Dram Type= 6, Freq= 0, CH_0, rank 1
6614 12:14:23.628792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 12:14:23.628894 ==
6616 12:14:23.628985 DQS Delay:
6617 12:14:23.632633 DQS0 = 24, DQS1 = 36
6618 12:14:23.632710 DQM Delay:
6619 12:14:23.635839 DQM0 = 8, DQM1 = 12
6620 12:14:23.635938 DQ Delay:
6621 12:14:23.638954 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6622 12:14:23.642161 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6623 12:14:23.645693 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6624 12:14:23.649376 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6625 12:14:23.649452
6626 12:14:23.649517
6627 12:14:23.655812 [DQSOSCAuto] RK1, (LSB)MR18= 0xb758, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
6628 12:14:23.659291 CH0 RK1: MR19=C0C, MR18=B758
6629 12:14:23.665658 CH0_RK1: MR19=0xC0C, MR18=0xB758, DQSOSC=387, MR23=63, INC=394, DEC=262
6630 12:14:23.668948 [RxdqsGatingPostProcess] freq 400
6631 12:14:23.672080 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6632 12:14:23.675866 best DQS0 dly(2T, 0.5T) = (0, 10)
6633 12:14:23.679102 best DQS1 dly(2T, 0.5T) = (0, 10)
6634 12:14:23.682078 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6635 12:14:23.685652 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6636 12:14:23.688750 best DQS0 dly(2T, 0.5T) = (0, 10)
6637 12:14:23.692203 best DQS1 dly(2T, 0.5T) = (0, 10)
6638 12:14:23.695671 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6639 12:14:23.698773 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6640 12:14:23.702068 Pre-setting of DQS Precalculation
6641 12:14:23.705373 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6642 12:14:23.705446 ==
6643 12:14:23.709191 Dram Type= 6, Freq= 0, CH_1, rank 0
6644 12:14:23.715434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 12:14:23.715518 ==
6646 12:14:23.718801 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6647 12:14:23.725656 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6648 12:14:23.729096 [CA 0] Center 36 (8~64) winsize 57
6649 12:14:23.732126 [CA 1] Center 36 (8~64) winsize 57
6650 12:14:23.735936 [CA 2] Center 36 (8~64) winsize 57
6651 12:14:23.738956 [CA 3] Center 36 (8~64) winsize 57
6652 12:14:23.741905 [CA 4] Center 36 (8~64) winsize 57
6653 12:14:23.745614 [CA 5] Center 36 (8~64) winsize 57
6654 12:14:23.745695
6655 12:14:23.748887 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6656 12:14:23.748969
6657 12:14:23.752604 [CATrainingPosCal] consider 1 rank data
6658 12:14:23.755744 u2DelayCellTimex100 = 270/100 ps
6659 12:14:23.758866 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 12:14:23.762214 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 12:14:23.765327 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 12:14:23.769023 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 12:14:23.772180 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 12:14:23.775333 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 12:14:23.775415
6666 12:14:23.782313 CA PerBit enable=1, Macro0, CA PI delay=36
6667 12:14:23.782421
6668 12:14:23.785324 [CBTSetCACLKResult] CA Dly = 36
6669 12:14:23.785405 CS Dly: 1 (0~32)
6670 12:14:23.785469 ==
6671 12:14:23.788479 Dram Type= 6, Freq= 0, CH_1, rank 1
6672 12:14:23.792091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6673 12:14:23.792196 ==
6674 12:14:23.799108 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6675 12:14:23.805611 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6676 12:14:23.808863 [CA 0] Center 36 (8~64) winsize 57
6677 12:14:23.811777 [CA 1] Center 36 (8~64) winsize 57
6678 12:14:23.815587 [CA 2] Center 36 (8~64) winsize 57
6679 12:14:23.818773 [CA 3] Center 36 (8~64) winsize 57
6680 12:14:23.818854 [CA 4] Center 36 (8~64) winsize 57
6681 12:14:23.821710 [CA 5] Center 36 (8~64) winsize 57
6682 12:14:23.821825
6683 12:14:23.828274 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6684 12:14:23.828380
6685 12:14:23.832143 [CATrainingPosCal] consider 2 rank data
6686 12:14:23.835736 u2DelayCellTimex100 = 270/100 ps
6687 12:14:23.838522 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 12:14:23.842065 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 12:14:23.845555 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 12:14:23.848600 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 12:14:23.851555 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 12:14:23.854825 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 12:14:23.854910
6694 12:14:23.858545 CA PerBit enable=1, Macro0, CA PI delay=36
6695 12:14:23.858630
6696 12:14:23.861601 [CBTSetCACLKResult] CA Dly = 36
6697 12:14:23.865124 CS Dly: 1 (0~32)
6698 12:14:23.865206
6699 12:14:23.868154 ----->DramcWriteLeveling(PI) begin...
6700 12:14:23.868264 ==
6701 12:14:23.871718 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 12:14:23.874964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 12:14:23.875050 ==
6704 12:14:23.878813 Write leveling (Byte 0): 40 => 8
6705 12:14:23.881940 Write leveling (Byte 1): 40 => 8
6706 12:14:23.885125 DramcWriteLeveling(PI) end<-----
6707 12:14:23.885209
6708 12:14:23.885275 ==
6709 12:14:23.888743 Dram Type= 6, Freq= 0, CH_1, rank 0
6710 12:14:23.891847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6711 12:14:23.891949 ==
6712 12:14:23.894884 [Gating] SW mode calibration
6713 12:14:23.901825 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6714 12:14:23.908275 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6715 12:14:23.911671 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6716 12:14:23.914637 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6717 12:14:23.921704 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6718 12:14:23.924722 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6719 12:14:23.928426 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6720 12:14:23.934712 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6721 12:14:23.937888 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6722 12:14:23.941480 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6723 12:14:23.947879 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6724 12:14:23.951165 Total UI for P1: 0, mck2ui 16
6725 12:14:23.954877 best dqsien dly found for B0: ( 0, 14, 24)
6726 12:14:23.954962 Total UI for P1: 0, mck2ui 16
6727 12:14:23.961038 best dqsien dly found for B1: ( 0, 14, 24)
6728 12:14:23.964334 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6729 12:14:23.967878 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6730 12:14:23.968050
6731 12:14:23.971454 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6732 12:14:23.974715 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6733 12:14:23.977761 [Gating] SW calibration Done
6734 12:14:23.977843 ==
6735 12:14:23.981307 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 12:14:23.984404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 12:14:23.984502 ==
6738 12:14:23.987805 RX Vref Scan: 0
6739 12:14:23.987906
6740 12:14:23.987985 RX Vref 0 -> 0, step: 1
6741 12:14:23.988085
6742 12:14:23.991105 RX Delay -410 -> 252, step: 16
6743 12:14:23.998029 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6744 12:14:24.001315 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6745 12:14:24.005094 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6746 12:14:24.007875 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6747 12:14:24.014076 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6748 12:14:24.017778 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6749 12:14:24.021225 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6750 12:14:24.024803 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6751 12:14:24.030893 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6752 12:14:24.034508 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6753 12:14:24.037772 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6754 12:14:24.040727 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6755 12:14:24.047634 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6756 12:14:24.051327 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6757 12:14:24.054391 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6758 12:14:24.057418 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6759 12:14:24.061088 ==
6760 12:14:24.064099 Dram Type= 6, Freq= 0, CH_1, rank 0
6761 12:14:24.067518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6762 12:14:24.067606 ==
6763 12:14:24.067671 DQS Delay:
6764 12:14:24.071230 DQS0 = 35, DQS1 = 35
6765 12:14:24.071330 DQM Delay:
6766 12:14:24.074603 DQM0 = 17, DQM1 = 13
6767 12:14:24.074706 DQ Delay:
6768 12:14:24.077535 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6769 12:14:24.081151 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6770 12:14:24.084133 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6771 12:14:24.087596 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6772 12:14:24.087696
6773 12:14:24.087796
6774 12:14:24.087884 ==
6775 12:14:24.091010 Dram Type= 6, Freq= 0, CH_1, rank 0
6776 12:14:24.094126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6777 12:14:24.094237 ==
6778 12:14:24.094329
6779 12:14:24.094417
6780 12:14:24.097336 TX Vref Scan disable
6781 12:14:24.097408 == TX Byte 0 ==
6782 12:14:24.104023 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6783 12:14:24.107565 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6784 12:14:24.107640 == TX Byte 1 ==
6785 12:14:24.114278 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6786 12:14:24.117193 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6787 12:14:24.117274 ==
6788 12:14:24.120706 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 12:14:24.123900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 12:14:24.123982 ==
6791 12:14:24.124110
6792 12:14:24.124196
6793 12:14:24.127360 TX Vref Scan disable
6794 12:14:24.127441 == TX Byte 0 ==
6795 12:14:24.134296 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6796 12:14:24.137155 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6797 12:14:24.137263 == TX Byte 1 ==
6798 12:14:24.144136 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6799 12:14:24.147279 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6800 12:14:24.147361
6801 12:14:24.147426 [DATLAT]
6802 12:14:24.150956 Freq=400, CH1 RK0
6803 12:14:24.151038
6804 12:14:24.151102 DATLAT Default: 0xf
6805 12:14:24.154197 0, 0xFFFF, sum = 0
6806 12:14:24.154280 1, 0xFFFF, sum = 0
6807 12:14:24.157265 2, 0xFFFF, sum = 0
6808 12:14:24.157375 3, 0xFFFF, sum = 0
6809 12:14:24.160857 4, 0xFFFF, sum = 0
6810 12:14:24.160940 5, 0xFFFF, sum = 0
6811 12:14:24.163811 6, 0xFFFF, sum = 0
6812 12:14:24.163894 7, 0xFFFF, sum = 0
6813 12:14:24.167464 8, 0xFFFF, sum = 0
6814 12:14:24.167546 9, 0xFFFF, sum = 0
6815 12:14:24.170586 10, 0xFFFF, sum = 0
6816 12:14:24.174427 11, 0xFFFF, sum = 0
6817 12:14:24.174537 12, 0xFFFF, sum = 0
6818 12:14:24.177455 13, 0x0, sum = 1
6819 12:14:24.177537 14, 0x0, sum = 2
6820 12:14:24.177602 15, 0x0, sum = 3
6821 12:14:24.180692 16, 0x0, sum = 4
6822 12:14:24.180774 best_step = 14
6823 12:14:24.180838
6824 12:14:24.183952 ==
6825 12:14:24.184033 Dram Type= 6, Freq= 0, CH_1, rank 0
6826 12:14:24.190446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6827 12:14:24.190529 ==
6828 12:14:24.190595 RX Vref Scan: 1
6829 12:14:24.190683
6830 12:14:24.193703 RX Vref 0 -> 0, step: 1
6831 12:14:24.193784
6832 12:14:24.197153 RX Delay -311 -> 252, step: 8
6833 12:14:24.197234
6834 12:14:24.200847 Set Vref, RX VrefLevel [Byte0]: 54
6835 12:14:24.203858 [Byte1]: 48
6836 12:14:24.207056
6837 12:14:24.207138 Final RX Vref Byte 0 = 54 to rank0
6838 12:14:24.210266 Final RX Vref Byte 1 = 48 to rank0
6839 12:14:24.214141 Final RX Vref Byte 0 = 54 to rank1
6840 12:14:24.217215 Final RX Vref Byte 1 = 48 to rank1==
6841 12:14:24.220592 Dram Type= 6, Freq= 0, CH_1, rank 0
6842 12:14:24.226906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 12:14:24.226988 ==
6844 12:14:24.227053 DQS Delay:
6845 12:14:24.230388 DQS0 = 28, DQS1 = 32
6846 12:14:24.230496 DQM Delay:
6847 12:14:24.230588 DQM0 = 9, DQM1 = 11
6848 12:14:24.233638 DQ Delay:
6849 12:14:24.236927 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6850 12:14:24.237009 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6851 12:14:24.240215 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6852 12:14:24.243593 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6853 12:14:24.243675
6854 12:14:24.243739
6855 12:14:24.253479 [DQSOSCAuto] RK0, (LSB)MR18= 0x88c0, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 392 ps
6856 12:14:24.256845 CH1 RK0: MR19=C0C, MR18=88C0
6857 12:14:24.263610 CH1_RK0: MR19=0xC0C, MR18=0x88C0, DQSOSC=386, MR23=63, INC=396, DEC=264
6858 12:14:24.263692 ==
6859 12:14:24.266726 Dram Type= 6, Freq= 0, CH_1, rank 1
6860 12:14:24.270559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6861 12:14:24.270641 ==
6862 12:14:24.273580 [Gating] SW mode calibration
6863 12:14:24.280251 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6864 12:14:24.283469 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6865 12:14:24.290351 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6866 12:14:24.293560 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6867 12:14:24.296806 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6868 12:14:24.303670 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6869 12:14:24.306621 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6870 12:14:24.310466 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6871 12:14:24.316814 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6872 12:14:24.319884 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6873 12:14:24.323453 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6874 12:14:24.326436 Total UI for P1: 0, mck2ui 16
6875 12:14:24.330186 best dqsien dly found for B0: ( 0, 14, 24)
6876 12:14:24.333295 Total UI for P1: 0, mck2ui 16
6877 12:14:24.336458 best dqsien dly found for B1: ( 0, 14, 24)
6878 12:14:24.340242 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6879 12:14:24.343629 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6880 12:14:24.343711
6881 12:14:24.349876 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6882 12:14:24.352906 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6883 12:14:24.356495 [Gating] SW calibration Done
6884 12:14:24.356577 ==
6885 12:14:24.360050 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 12:14:24.363459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 12:14:24.363541 ==
6888 12:14:24.363606 RX Vref Scan: 0
6889 12:14:24.363666
6890 12:14:24.366419 RX Vref 0 -> 0, step: 1
6891 12:14:24.366501
6892 12:14:24.370339 RX Delay -410 -> 252, step: 16
6893 12:14:24.372897 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6894 12:14:24.379775 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6895 12:14:24.382863 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6896 12:14:24.386367 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6897 12:14:24.389415 iDelay=230, Bit 4, Center -11 (-234 ~ 213) 448
6898 12:14:24.396096 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6899 12:14:24.399656 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6900 12:14:24.403267 iDelay=230, Bit 7, Center -11 (-234 ~ 213) 448
6901 12:14:24.406471 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6902 12:14:24.410044 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6903 12:14:24.416915 iDelay=230, Bit 10, Center -11 (-234 ~ 213) 448
6904 12:14:24.419931 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6905 12:14:24.423101 iDelay=230, Bit 12, Center -3 (-234 ~ 229) 464
6906 12:14:24.426850 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6907 12:14:24.433007 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6908 12:14:24.436150 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6909 12:14:24.436231 ==
6910 12:14:24.439324 Dram Type= 6, Freq= 0, CH_1, rank 1
6911 12:14:24.442588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6912 12:14:24.442670 ==
6913 12:14:24.446081 DQS Delay:
6914 12:14:24.446188 DQS0 = 35, DQS1 = 35
6915 12:14:24.449567 DQM Delay:
6916 12:14:24.449649 DQM0 = 21, DQM1 = 18
6917 12:14:24.453147 DQ Delay:
6918 12:14:24.453228 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6919 12:14:24.456464 DQ4 =24, DQ5 =32, DQ6 =32, DQ7 =24
6920 12:14:24.459510 DQ8 =0, DQ9 =0, DQ10 =24, DQ11 =8
6921 12:14:24.462512 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6922 12:14:24.462594
6923 12:14:24.462658
6924 12:14:24.466257 ==
6925 12:14:24.466338 Dram Type= 6, Freq= 0, CH_1, rank 1
6926 12:14:24.472901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6927 12:14:24.472987 ==
6928 12:14:24.473052
6929 12:14:24.473112
6930 12:14:24.476128 TX Vref Scan disable
6931 12:14:24.476209 == TX Byte 0 ==
6932 12:14:24.479306 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6933 12:14:24.486257 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6934 12:14:24.486342 == TX Byte 1 ==
6935 12:14:24.489318 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6936 12:14:24.492899 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6937 12:14:24.496018 ==
6938 12:14:24.499389 Dram Type= 6, Freq= 0, CH_1, rank 1
6939 12:14:24.502452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6940 12:14:24.502551 ==
6941 12:14:24.502616
6942 12:14:24.502676
6943 12:14:24.505797 TX Vref Scan disable
6944 12:14:24.505879 == TX Byte 0 ==
6945 12:14:24.509442 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6946 12:14:24.515709 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6947 12:14:24.515796 == TX Byte 1 ==
6948 12:14:24.519044 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6949 12:14:24.525716 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6950 12:14:24.525799
6951 12:14:24.525864 [DATLAT]
6952 12:14:24.525924 Freq=400, CH1 RK1
6953 12:14:24.525986
6954 12:14:24.529369 DATLAT Default: 0xe
6955 12:14:24.529452 0, 0xFFFF, sum = 0
6956 12:14:24.532522 1, 0xFFFF, sum = 0
6957 12:14:24.532607 2, 0xFFFF, sum = 0
6958 12:14:24.535449 3, 0xFFFF, sum = 0
6959 12:14:24.539098 4, 0xFFFF, sum = 0
6960 12:14:24.539182 5, 0xFFFF, sum = 0
6961 12:14:24.542266 6, 0xFFFF, sum = 0
6962 12:14:24.542372 7, 0xFFFF, sum = 0
6963 12:14:24.545473 8, 0xFFFF, sum = 0
6964 12:14:24.545557 9, 0xFFFF, sum = 0
6965 12:14:24.548645 10, 0xFFFF, sum = 0
6966 12:14:24.548729 11, 0xFFFF, sum = 0
6967 12:14:24.552547 12, 0xFFFF, sum = 0
6968 12:14:24.552630 13, 0x0, sum = 1
6969 12:14:24.555516 14, 0x0, sum = 2
6970 12:14:24.555598 15, 0x0, sum = 3
6971 12:14:24.559140 16, 0x0, sum = 4
6972 12:14:24.559223 best_step = 14
6973 12:14:24.559288
6974 12:14:24.559348 ==
6975 12:14:24.561959 Dram Type= 6, Freq= 0, CH_1, rank 1
6976 12:14:24.565264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6977 12:14:24.565347 ==
6978 12:14:24.568906 RX Vref Scan: 0
6979 12:14:24.568987
6980 12:14:24.572065 RX Vref 0 -> 0, step: 1
6981 12:14:24.572146
6982 12:14:24.572211 RX Delay -311 -> 252, step: 8
6983 12:14:24.581320 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6984 12:14:24.584298 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6985 12:14:24.587559 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6986 12:14:24.591158 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6987 12:14:24.597394 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6988 12:14:24.600751 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6989 12:14:24.603967 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6990 12:14:24.607687 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6991 12:14:24.614111 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6992 12:14:24.617677 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6993 12:14:24.620859 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6994 12:14:24.624433 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6995 12:14:24.631158 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6996 12:14:24.634212 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6997 12:14:24.637300 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6998 12:14:24.643775 iDelay=217, Bit 15, Center -8 (-231 ~ 216) 448
6999 12:14:24.643863 ==
7000 12:14:24.647399 Dram Type= 6, Freq= 0, CH_1, rank 1
7001 12:14:24.651211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7002 12:14:24.651295 ==
7003 12:14:24.651361 DQS Delay:
7004 12:14:24.654312 DQS0 = 28, DQS1 = 36
7005 12:14:24.654395 DQM Delay:
7006 12:14:24.657542 DQM0 = 11, DQM1 = 15
7007 12:14:24.657624 DQ Delay:
7008 12:14:24.660606 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
7009 12:14:24.663890 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
7010 12:14:24.667259 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
7011 12:14:24.670463 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =28
7012 12:14:24.670547
7013 12:14:24.670611
7014 12:14:24.677119 [DQSOSCAuto] RK1, (LSB)MR18= 0xc456, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
7015 12:14:24.680891 CH1 RK1: MR19=C0C, MR18=C456
7016 12:14:24.686983 CH1_RK1: MR19=0xC0C, MR18=0xC456, DQSOSC=385, MR23=63, INC=398, DEC=265
7017 12:14:24.690829 [RxdqsGatingPostProcess] freq 400
7018 12:14:24.693744 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7019 12:14:24.697527 best DQS0 dly(2T, 0.5T) = (0, 10)
7020 12:14:24.700791 best DQS1 dly(2T, 0.5T) = (0, 10)
7021 12:14:24.703968 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7022 12:14:24.707261 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7023 12:14:24.710500 best DQS0 dly(2T, 0.5T) = (0, 10)
7024 12:14:24.714027 best DQS1 dly(2T, 0.5T) = (0, 10)
7025 12:14:24.717629 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7026 12:14:24.720343 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7027 12:14:24.723571 Pre-setting of DQS Precalculation
7028 12:14:24.727384 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7029 12:14:24.737531 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7030 12:14:24.744062 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7031 12:14:24.744148
7032 12:14:24.744215
7033 12:14:24.747325 [Calibration Summary] 800 Mbps
7034 12:14:24.747409 CH 0, Rank 0
7035 12:14:24.750591 SW Impedance : PASS
7036 12:14:24.750750 DUTY Scan : NO K
7037 12:14:24.753719 ZQ Calibration : PASS
7038 12:14:24.757338 Jitter Meter : NO K
7039 12:14:24.757422 CBT Training : PASS
7040 12:14:24.760360 Write leveling : PASS
7041 12:14:24.763609 RX DQS gating : PASS
7042 12:14:24.763693 RX DQ/DQS(RDDQC) : PASS
7043 12:14:24.767528 TX DQ/DQS : PASS
7044 12:14:24.770678 RX DATLAT : PASS
7045 12:14:24.770761 RX DQ/DQS(Engine): PASS
7046 12:14:24.774147 TX OE : NO K
7047 12:14:24.774230 All Pass.
7048 12:14:24.774296
7049 12:14:24.777032 CH 0, Rank 1
7050 12:14:24.777116 SW Impedance : PASS
7051 12:14:24.780528 DUTY Scan : NO K
7052 12:14:24.783349 ZQ Calibration : PASS
7053 12:14:24.783437 Jitter Meter : NO K
7054 12:14:24.787202 CBT Training : PASS
7055 12:14:24.787285 Write leveling : NO K
7056 12:14:24.790155 RX DQS gating : PASS
7057 12:14:24.793652 RX DQ/DQS(RDDQC) : PASS
7058 12:14:24.793737 TX DQ/DQS : PASS
7059 12:14:24.796885 RX DATLAT : PASS
7060 12:14:24.800203 RX DQ/DQS(Engine): PASS
7061 12:14:24.800311 TX OE : NO K
7062 12:14:24.803671 All Pass.
7063 12:14:24.803754
7064 12:14:24.803820 CH 1, Rank 0
7065 12:14:24.806792 SW Impedance : PASS
7066 12:14:24.806875 DUTY Scan : NO K
7067 12:14:24.809922 ZQ Calibration : PASS
7068 12:14:24.813852 Jitter Meter : NO K
7069 12:14:24.813935 CBT Training : PASS
7070 12:14:24.816918 Write leveling : PASS
7071 12:14:24.820003 RX DQS gating : PASS
7072 12:14:24.820088 RX DQ/DQS(RDDQC) : PASS
7073 12:14:24.823712 TX DQ/DQS : PASS
7074 12:14:24.826636 RX DATLAT : PASS
7075 12:14:24.826719 RX DQ/DQS(Engine): PASS
7076 12:14:24.830327 TX OE : NO K
7077 12:14:24.830427 All Pass.
7078 12:14:24.830494
7079 12:14:24.833850 CH 1, Rank 1
7080 12:14:24.833934 SW Impedance : PASS
7081 12:14:24.836879 DUTY Scan : NO K
7082 12:14:24.836962 ZQ Calibration : PASS
7083 12:14:24.840538 Jitter Meter : NO K
7084 12:14:24.843638 CBT Training : PASS
7085 12:14:24.843721 Write leveling : NO K
7086 12:14:24.846842 RX DQS gating : PASS
7087 12:14:24.850130 RX DQ/DQS(RDDQC) : PASS
7088 12:14:24.850240 TX DQ/DQS : PASS
7089 12:14:24.853716 RX DATLAT : PASS
7090 12:14:24.856823 RX DQ/DQS(Engine): PASS
7091 12:14:24.856906 TX OE : NO K
7092 12:14:24.860050 All Pass.
7093 12:14:24.860148
7094 12:14:24.860213 DramC Write-DBI off
7095 12:14:24.863170 PER_BANK_REFRESH: Hybrid Mode
7096 12:14:24.863254 TX_TRACKING: ON
7097 12:14:24.873276 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7098 12:14:24.876811 [FAST_K] Save calibration result to emmc
7099 12:14:24.880155 dramc_set_vcore_voltage set vcore to 725000
7100 12:14:24.883638 Read voltage for 1600, 0
7101 12:14:24.883741 Vio18 = 0
7102 12:14:24.887324 Vcore = 725000
7103 12:14:24.887410 Vdram = 0
7104 12:14:24.887477 Vddq = 0
7105 12:14:24.890099 Vmddr = 0
7106 12:14:24.893450 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7107 12:14:24.899746 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7108 12:14:24.899833 MEM_TYPE=3, freq_sel=13
7109 12:14:24.903367 sv_algorithm_assistance_LP4_3733
7110 12:14:24.909824 ============ PULL DRAM RESETB DOWN ============
7111 12:14:24.913466 ========== PULL DRAM RESETB DOWN end =========
7112 12:14:24.916578 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7113 12:14:24.919770 ===================================
7114 12:14:24.923565 LPDDR4 DRAM CONFIGURATION
7115 12:14:24.926577 ===================================
7116 12:14:24.926662 EX_ROW_EN[0] = 0x0
7117 12:14:24.929862 EX_ROW_EN[1] = 0x0
7118 12:14:24.933344 LP4Y_EN = 0x0
7119 12:14:24.933428 WORK_FSP = 0x1
7120 12:14:24.936104 WL = 0x5
7121 12:14:24.936187 RL = 0x5
7122 12:14:24.939838 BL = 0x2
7123 12:14:24.939922 RPST = 0x0
7124 12:14:24.943038 RD_PRE = 0x0
7125 12:14:24.943123 WR_PRE = 0x1
7126 12:14:24.946101 WR_PST = 0x1
7127 12:14:24.946185 DBI_WR = 0x0
7128 12:14:24.949467 DBI_RD = 0x0
7129 12:14:24.949551 OTF = 0x1
7130 12:14:24.953253 ===================================
7131 12:14:24.956234 ===================================
7132 12:14:24.959563 ANA top config
7133 12:14:24.963065 ===================================
7134 12:14:24.963152 DLL_ASYNC_EN = 0
7135 12:14:24.966299 ALL_SLAVE_EN = 0
7136 12:14:24.969657 NEW_RANK_MODE = 1
7137 12:14:24.972883 DLL_IDLE_MODE = 1
7138 12:14:24.976602 LP45_APHY_COMB_EN = 1
7139 12:14:24.976682 TX_ODT_DIS = 0
7140 12:14:24.979874 NEW_8X_MODE = 1
7141 12:14:24.983036 ===================================
7142 12:14:24.986391 ===================================
7143 12:14:24.989426 data_rate = 3200
7144 12:14:24.992945 CKR = 1
7145 12:14:24.996103 DQ_P2S_RATIO = 8
7146 12:14:24.999424 ===================================
7147 12:14:24.999510 CA_P2S_RATIO = 8
7148 12:14:25.002698 DQ_CA_OPEN = 0
7149 12:14:25.006390 DQ_SEMI_OPEN = 0
7150 12:14:25.009823 CA_SEMI_OPEN = 0
7151 12:14:25.013043 CA_FULL_RATE = 0
7152 12:14:25.016283 DQ_CKDIV4_EN = 0
7153 12:14:25.016408 CA_CKDIV4_EN = 0
7154 12:14:25.019329 CA_PREDIV_EN = 0
7155 12:14:25.022696 PH8_DLY = 12
7156 12:14:25.026160 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7157 12:14:25.029357 DQ_AAMCK_DIV = 4
7158 12:14:25.032681 CA_AAMCK_DIV = 4
7159 12:14:25.032771 CA_ADMCK_DIV = 4
7160 12:14:25.036211 DQ_TRACK_CA_EN = 0
7161 12:14:25.039456 CA_PICK = 1600
7162 12:14:25.042910 CA_MCKIO = 1600
7163 12:14:25.046355 MCKIO_SEMI = 0
7164 12:14:25.049188 PLL_FREQ = 3068
7165 12:14:25.053043 DQ_UI_PI_RATIO = 32
7166 12:14:25.053130 CA_UI_PI_RATIO = 0
7167 12:14:25.055978 ===================================
7168 12:14:25.059569 ===================================
7169 12:14:25.062896 memory_type:LPDDR4
7170 12:14:25.066328 GP_NUM : 10
7171 12:14:25.066411 SRAM_EN : 1
7172 12:14:25.069451 MD32_EN : 0
7173 12:14:25.072570 ===================================
7174 12:14:25.075873 [ANA_INIT] >>>>>>>>>>>>>>
7175 12:14:25.079047 <<<<<< [CONFIGURE PHASE]: ANA_TX
7176 12:14:25.082236 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7177 12:14:25.086058 ===================================
7178 12:14:25.089145 data_rate = 3200,PCW = 0X7600
7179 12:14:25.092405 ===================================
7180 12:14:25.095448 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7181 12:14:25.099113 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7182 12:14:25.105375 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7183 12:14:25.108826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7184 12:14:25.112070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7185 12:14:25.115373 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7186 12:14:25.118993 [ANA_INIT] flow start
7187 12:14:25.121904 [ANA_INIT] PLL >>>>>>>>
7188 12:14:25.121995 [ANA_INIT] PLL <<<<<<<<
7189 12:14:25.125674 [ANA_INIT] MIDPI >>>>>>>>
7190 12:14:25.128503 [ANA_INIT] MIDPI <<<<<<<<
7191 12:14:25.128597 [ANA_INIT] DLL >>>>>>>>
7192 12:14:25.132145 [ANA_INIT] DLL <<<<<<<<
7193 12:14:25.135470 [ANA_INIT] flow end
7194 12:14:25.138876 ============ LP4 DIFF to SE enter ============
7195 12:14:25.142288 ============ LP4 DIFF to SE exit ============
7196 12:14:25.145574 [ANA_INIT] <<<<<<<<<<<<<
7197 12:14:25.148771 [Flow] Enable top DCM control >>>>>
7198 12:14:25.152171 [Flow] Enable top DCM control <<<<<
7199 12:14:25.155336 Enable DLL master slave shuffle
7200 12:14:25.158582 ==============================================================
7201 12:14:25.161816 Gating Mode config
7202 12:14:25.168893 ==============================================================
7203 12:14:25.168990 Config description:
7204 12:14:25.178680 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7205 12:14:25.185061 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7206 12:14:25.189220 SELPH_MODE 0: By rank 1: By Phase
7207 12:14:25.195218 ==============================================================
7208 12:14:25.198994 GAT_TRACK_EN = 1
7209 12:14:25.202340 RX_GATING_MODE = 2
7210 12:14:25.205521 RX_GATING_TRACK_MODE = 2
7211 12:14:25.208615 SELPH_MODE = 1
7212 12:14:25.211808 PICG_EARLY_EN = 1
7213 12:14:25.215605 VALID_LAT_VALUE = 1
7214 12:14:25.218673 ==============================================================
7215 12:14:25.221770 Enter into Gating configuration >>>>
7216 12:14:25.225630 Exit from Gating configuration <<<<
7217 12:14:25.228274 Enter into DVFS_PRE_config >>>>>
7218 12:14:25.242014 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7219 12:14:25.242172 Exit from DVFS_PRE_config <<<<<
7220 12:14:25.245061 Enter into PICG configuration >>>>
7221 12:14:25.248265 Exit from PICG configuration <<<<
7222 12:14:25.251461 [RX_INPUT] configuration >>>>>
7223 12:14:25.255132 [RX_INPUT] configuration <<<<<
7224 12:14:25.261690 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7225 12:14:25.264749 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7226 12:14:25.271692 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7227 12:14:25.278120 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7228 12:14:25.284656 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7229 12:14:25.291300 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7230 12:14:25.294836 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7231 12:14:25.298455 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7232 12:14:25.301635 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7233 12:14:25.307962 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7234 12:14:25.311752 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7235 12:14:25.314962 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7236 12:14:25.318200 ===================================
7237 12:14:25.321356 LPDDR4 DRAM CONFIGURATION
7238 12:14:25.324902 ===================================
7239 12:14:25.328179 EX_ROW_EN[0] = 0x0
7240 12:14:25.328298 EX_ROW_EN[1] = 0x0
7241 12:14:25.331356 LP4Y_EN = 0x0
7242 12:14:25.331444 WORK_FSP = 0x1
7243 12:14:25.334568 WL = 0x5
7244 12:14:25.334652 RL = 0x5
7245 12:14:25.338248 BL = 0x2
7246 12:14:25.338333 RPST = 0x0
7247 12:14:25.341230 RD_PRE = 0x0
7248 12:14:25.341316 WR_PRE = 0x1
7249 12:14:25.344717 WR_PST = 0x1
7250 12:14:25.344803 DBI_WR = 0x0
7251 12:14:25.347961 DBI_RD = 0x0
7252 12:14:25.348047 OTF = 0x1
7253 12:14:25.351481 ===================================
7254 12:14:25.357876 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7255 12:14:25.361224 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7256 12:14:25.364828 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7257 12:14:25.368008 ===================================
7258 12:14:25.371084 LPDDR4 DRAM CONFIGURATION
7259 12:14:25.374716 ===================================
7260 12:14:25.374799 EX_ROW_EN[0] = 0x10
7261 12:14:25.377556 EX_ROW_EN[1] = 0x0
7262 12:14:25.381040 LP4Y_EN = 0x0
7263 12:14:25.381123 WORK_FSP = 0x1
7264 12:14:25.384598 WL = 0x5
7265 12:14:25.384688 RL = 0x5
7266 12:14:25.387485 BL = 0x2
7267 12:14:25.387568 RPST = 0x0
7268 12:14:25.391213 RD_PRE = 0x0
7269 12:14:25.391298 WR_PRE = 0x1
7270 12:14:25.394424 WR_PST = 0x1
7271 12:14:25.394508 DBI_WR = 0x0
7272 12:14:25.397634 DBI_RD = 0x0
7273 12:14:25.397717 OTF = 0x1
7274 12:14:25.400806 ===================================
7275 12:14:25.407603 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7276 12:14:25.407690 ==
7277 12:14:25.410751 Dram Type= 6, Freq= 0, CH_0, rank 0
7278 12:14:25.414204 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7279 12:14:25.417597 ==
7280 12:14:25.417682 [Duty_Offset_Calibration]
7281 12:14:25.421289 B0:2 B1:1 CA:1
7282 12:14:25.421373
7283 12:14:25.424567 [DutyScan_Calibration_Flow] k_type=0
7284 12:14:25.433368
7285 12:14:25.433457 ==CLK 0==
7286 12:14:25.436407 Final CLK duty delay cell = 0
7287 12:14:25.440227 [0] MAX Duty = 5156%(X100), DQS PI = 22
7288 12:14:25.443403 [0] MIN Duty = 4907%(X100), DQS PI = 0
7289 12:14:25.443489 [0] AVG Duty = 5031%(X100)
7290 12:14:25.446497
7291 12:14:25.449570 CH0 CLK Duty spec in!! Max-Min= 249%
7292 12:14:25.453143 [DutyScan_Calibration_Flow] ====Done====
7293 12:14:25.453229
7294 12:14:25.456226 [DutyScan_Calibration_Flow] k_type=1
7295 12:14:25.472193
7296 12:14:25.472407 ==DQS 0 ==
7297 12:14:25.475781 Final DQS duty delay cell = -4
7298 12:14:25.478737 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7299 12:14:25.481863 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7300 12:14:25.485387 [-4] AVG Duty = 4891%(X100)
7301 12:14:25.485483
7302 12:14:25.485550 ==DQS 1 ==
7303 12:14:25.488480 Final DQS duty delay cell = 0
7304 12:14:25.492387 [0] MAX Duty = 5187%(X100), DQS PI = 2
7305 12:14:25.495372 [0] MIN Duty = 5031%(X100), DQS PI = 52
7306 12:14:25.498963 [0] AVG Duty = 5109%(X100)
7307 12:14:25.499051
7308 12:14:25.502214 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7309 12:14:25.502298
7310 12:14:25.505148 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7311 12:14:25.509030 [DutyScan_Calibration_Flow] ====Done====
7312 12:14:25.509120
7313 12:14:25.512018 [DutyScan_Calibration_Flow] k_type=3
7314 12:14:25.528532
7315 12:14:25.528673 ==DQM 0 ==
7316 12:14:25.531843 Final DQM duty delay cell = 0
7317 12:14:25.535537 [0] MAX Duty = 5218%(X100), DQS PI = 34
7318 12:14:25.538502 [0] MIN Duty = 4907%(X100), DQS PI = 54
7319 12:14:25.541611 [0] AVG Duty = 5062%(X100)
7320 12:14:25.541708
7321 12:14:25.541775 ==DQM 1 ==
7322 12:14:25.544977 Final DQM duty delay cell = -4
7323 12:14:25.548668 [-4] MAX Duty = 4938%(X100), DQS PI = 0
7324 12:14:25.551664 [-4] MIN Duty = 4813%(X100), DQS PI = 14
7325 12:14:25.555089 [-4] AVG Duty = 4875%(X100)
7326 12:14:25.555185
7327 12:14:25.558131 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7328 12:14:25.558221
7329 12:14:25.562071 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7330 12:14:25.565150 [DutyScan_Calibration_Flow] ====Done====
7331 12:14:25.565242
7332 12:14:25.568693 [DutyScan_Calibration_Flow] k_type=2
7333 12:14:25.586283
7334 12:14:25.586436 ==DQ 0 ==
7335 12:14:25.589508 Final DQ duty delay cell = 0
7336 12:14:25.592826 [0] MAX Duty = 5062%(X100), DQS PI = 24
7337 12:14:25.595816 [0] MIN Duty = 4907%(X100), DQS PI = 0
7338 12:14:25.595901 [0] AVG Duty = 4984%(X100)
7339 12:14:25.599398
7340 12:14:25.599481 ==DQ 1 ==
7341 12:14:25.602363 Final DQ duty delay cell = 0
7342 12:14:25.605824 [0] MAX Duty = 5125%(X100), DQS PI = 6
7343 12:14:25.609582 [0] MIN Duty = 4938%(X100), DQS PI = 32
7344 12:14:25.609667 [0] AVG Duty = 5031%(X100)
7345 12:14:25.609734
7346 12:14:25.612810 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7347 12:14:25.615994
7348 12:14:25.619391 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7349 12:14:25.622661 [DutyScan_Calibration_Flow] ====Done====
7350 12:14:25.622745 ==
7351 12:14:25.625759 Dram Type= 6, Freq= 0, CH_1, rank 0
7352 12:14:25.629576 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7353 12:14:25.629659 ==
7354 12:14:25.632196 [Duty_Offset_Calibration]
7355 12:14:25.632277 B0:2 B1:0 CA:0
7356 12:14:25.632385
7357 12:14:25.635850 [DutyScan_Calibration_Flow] k_type=0
7358 12:14:25.645669
7359 12:14:25.645755 ==CLK 0==
7360 12:14:25.648614 Final CLK duty delay cell = -4
7361 12:14:25.652140 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7362 12:14:25.655860 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7363 12:14:25.658897 [-4] AVG Duty = 4906%(X100)
7364 12:14:25.658991
7365 12:14:25.662418 CH1 CLK Duty spec in!! Max-Min= 125%
7366 12:14:25.665165 [DutyScan_Calibration_Flow] ====Done====
7367 12:14:25.665254
7368 12:14:25.668821 [DutyScan_Calibration_Flow] k_type=1
7369 12:14:25.685604
7370 12:14:25.685756 ==DQS 0 ==
7371 12:14:25.689226 Final DQS duty delay cell = 0
7372 12:14:25.692309 [0] MAX Duty = 5093%(X100), DQS PI = 24
7373 12:14:25.695710 [0] MIN Duty = 4844%(X100), DQS PI = 44
7374 12:14:25.698797 [0] AVG Duty = 4968%(X100)
7375 12:14:25.698888
7376 12:14:25.698952 ==DQS 1 ==
7377 12:14:25.702168 Final DQS duty delay cell = 0
7378 12:14:25.705262 [0] MAX Duty = 5249%(X100), DQS PI = 16
7379 12:14:25.708441 [0] MIN Duty = 4969%(X100), DQS PI = 6
7380 12:14:25.711985 [0] AVG Duty = 5109%(X100)
7381 12:14:25.712067
7382 12:14:25.715218 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7383 12:14:25.715305
7384 12:14:25.718642 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7385 12:14:25.722118 [DutyScan_Calibration_Flow] ====Done====
7386 12:14:25.722219
7387 12:14:25.725163 [DutyScan_Calibration_Flow] k_type=3
7388 12:14:25.742763
7389 12:14:25.742855 ==DQM 0 ==
7390 12:14:25.745945 Final DQM duty delay cell = 0
7391 12:14:25.749200 [0] MAX Duty = 5187%(X100), DQS PI = 10
7392 12:14:25.752282 [0] MIN Duty = 4969%(X100), DQS PI = 48
7393 12:14:25.752369 [0] AVG Duty = 5078%(X100)
7394 12:14:25.755752
7395 12:14:25.755916 ==DQM 1 ==
7396 12:14:25.759224 Final DQM duty delay cell = 0
7397 12:14:25.762065 [0] MAX Duty = 5093%(X100), DQS PI = 16
7398 12:14:25.765664 [0] MIN Duty = 4876%(X100), DQS PI = 52
7399 12:14:25.768761 [0] AVG Duty = 4984%(X100)
7400 12:14:25.768847
7401 12:14:25.772480 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7402 12:14:25.772562
7403 12:14:25.775392 CH1 DQM 1 Duty spec in!! Max-Min= 217%
7404 12:14:25.778635 [DutyScan_Calibration_Flow] ====Done====
7405 12:14:25.778717
7406 12:14:25.782215 [DutyScan_Calibration_Flow] k_type=2
7407 12:14:25.798236
7408 12:14:25.798342 ==DQ 0 ==
7409 12:14:25.801784 Final DQ duty delay cell = -4
7410 12:14:25.804968 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7411 12:14:25.808361 [-4] MIN Duty = 4876%(X100), DQS PI = 46
7412 12:14:25.811933 [-4] AVG Duty = 4969%(X100)
7413 12:14:25.812015
7414 12:14:25.812079 ==DQ 1 ==
7415 12:14:25.815083 Final DQ duty delay cell = 0
7416 12:14:25.818164 [0] MAX Duty = 5124%(X100), DQS PI = 16
7417 12:14:25.821939 [0] MIN Duty = 4938%(X100), DQS PI = 8
7418 12:14:25.824864 [0] AVG Duty = 5031%(X100)
7419 12:14:25.824946
7420 12:14:25.828120 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7421 12:14:25.828227
7422 12:14:25.831376 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7423 12:14:25.835039 [DutyScan_Calibration_Flow] ====Done====
7424 12:14:25.838034 nWR fixed to 30
7425 12:14:25.841682 [ModeRegInit_LP4] CH0 RK0
7426 12:14:25.841765 [ModeRegInit_LP4] CH0 RK1
7427 12:14:25.844657 [ModeRegInit_LP4] CH1 RK0
7428 12:14:25.848406 [ModeRegInit_LP4] CH1 RK1
7429 12:14:25.848488 match AC timing 5
7430 12:14:25.855113 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7431 12:14:25.858217 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7432 12:14:25.861349 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7433 12:14:25.868306 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7434 12:14:25.871539 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7435 12:14:25.871622 [MiockJmeterHQA]
7436 12:14:25.871686
7437 12:14:25.875084 [DramcMiockJmeter] u1RxGatingPI = 0
7438 12:14:25.878177 0 : 4252, 4027
7439 12:14:25.878262 4 : 4252, 4026
7440 12:14:25.881637 8 : 4252, 4027
7441 12:14:25.881720 12 : 4252, 4027
7442 12:14:25.881787 16 : 4253, 4027
7443 12:14:25.884834 20 : 4252, 4027
7444 12:14:25.884916 24 : 4253, 4027
7445 12:14:25.888422 28 : 4363, 4137
7446 12:14:25.888506 32 : 4253, 4027
7447 12:14:25.891482 36 : 4363, 4137
7448 12:14:25.891564 40 : 4253, 4026
7449 12:14:25.894698 44 : 4252, 4027
7450 12:14:25.894782 48 : 4254, 4029
7451 12:14:25.894849 52 : 4253, 4027
7452 12:14:25.897990 56 : 4366, 4140
7453 12:14:25.898073 60 : 4363, 4140
7454 12:14:25.901255 64 : 4250, 4027
7455 12:14:25.901338 68 : 4252, 4029
7456 12:14:25.904896 72 : 4361, 4137
7457 12:14:25.904979 76 : 4250, 4027
7458 12:14:25.905053 80 : 4363, 4140
7459 12:14:25.908145 84 : 4250, 4027
7460 12:14:25.908254 88 : 4250, 165
7461 12:14:25.911356 92 : 4361, 0
7462 12:14:25.911439 96 : 4253, 0
7463 12:14:25.911505 100 : 4250, 0
7464 12:14:25.914974 104 : 4252, 0
7465 12:14:25.915057 108 : 4250, 0
7466 12:14:25.918287 112 : 4250, 0
7467 12:14:25.918366 116 : 4362, 0
7468 12:14:25.918445 120 : 4255, 0
7469 12:14:25.921393 124 : 4250, 0
7470 12:14:25.921476 128 : 4249, 0
7471 12:14:25.925156 132 : 4252, 0
7472 12:14:25.925239 136 : 4361, 0
7473 12:14:25.925305 140 : 4250, 0
7474 12:14:25.928176 144 : 4250, 0
7475 12:14:25.928295 148 : 4360, 0
7476 12:14:25.931431 152 : 4360, 0
7477 12:14:25.931513 156 : 4250, 0
7478 12:14:25.931578 160 : 4250, 0
7479 12:14:25.934984 164 : 4361, 0
7480 12:14:25.935066 168 : 4249, 0
7481 12:14:25.935131 172 : 4252, 0
7482 12:14:25.937899 176 : 4250, 0
7483 12:14:25.937981 180 : 4249, 0
7484 12:14:25.941047 184 : 4249, 0
7485 12:14:25.941130 188 : 4250, 0
7486 12:14:25.941195 192 : 4250, 0
7487 12:14:25.945139 196 : 4249, 0
7488 12:14:25.945221 200 : 4360, 0
7489 12:14:25.947892 204 : 4360, 1273
7490 12:14:25.947974 208 : 4250, 3965
7491 12:14:25.951676 212 : 4249, 4027
7492 12:14:25.951759 216 : 4249, 4027
7493 12:14:25.954667 220 : 4250, 4027
7494 12:14:25.954749 224 : 4250, 4027
7495 12:14:25.954815 228 : 4250, 4027
7496 12:14:25.958200 232 : 4250, 4027
7497 12:14:25.958310 236 : 4249, 4027
7498 12:14:25.961387 240 : 4361, 4138
7499 12:14:25.961469 244 : 4250, 4027
7500 12:14:25.964899 248 : 4250, 4027
7501 12:14:25.964981 252 : 4250, 4026
7502 12:14:25.968351 256 : 4363, 4140
7503 12:14:25.968443 260 : 4361, 4137
7504 12:14:25.970991 264 : 4250, 4027
7505 12:14:25.971073 268 : 4250, 4027
7506 12:14:25.974738 272 : 4252, 4029
7507 12:14:25.974820 276 : 4250, 4027
7508 12:14:25.974885 280 : 4250, 4026
7509 12:14:25.977827 284 : 4250, 4027
7510 12:14:25.977909 288 : 4252, 4029
7511 12:14:25.980976 292 : 4363, 4140
7512 12:14:25.981059 296 : 4250, 4027
7513 12:14:25.984600 300 : 4249, 4027
7514 12:14:25.984710 304 : 4252, 4030
7515 12:14:25.987730 308 : 4363, 4014
7516 12:14:25.987820 312 : 4361, 2114
7517 12:14:25.987883
7518 12:14:25.991357 MIOCK jitter meter ch=0
7519 12:14:25.991442
7520 12:14:25.994383 1T = (312-88) = 224 dly cells
7521 12:14:25.997795 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7522 12:14:26.001161 ==
7523 12:14:26.004833 Dram Type= 6, Freq= 0, CH_0, rank 0
7524 12:14:26.008208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7525 12:14:26.008355 ==
7526 12:14:26.011126 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7527 12:14:26.017968 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7528 12:14:26.021203 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7529 12:14:26.027833 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7530 12:14:26.036043 [CA 0] Center 42 (12~73) winsize 62
7531 12:14:26.039304 [CA 1] Center 42 (12~73) winsize 62
7532 12:14:26.043057 [CA 2] Center 37 (8~67) winsize 60
7533 12:14:26.046256 [CA 3] Center 37 (7~67) winsize 61
7534 12:14:26.049423 [CA 4] Center 36 (6~66) winsize 61
7535 12:14:26.053075 [CA 5] Center 34 (5~64) winsize 60
7536 12:14:26.053160
7537 12:14:26.056253 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7538 12:14:26.056352
7539 12:14:26.059386 [CATrainingPosCal] consider 1 rank data
7540 12:14:26.062655 u2DelayCellTimex100 = 290/100 ps
7541 12:14:26.066311 CA0 delay=42 (12~73),Diff = 8 PI (26 cell)
7542 12:14:26.072512 CA1 delay=42 (12~73),Diff = 8 PI (26 cell)
7543 12:14:26.075768 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
7544 12:14:26.079473 CA3 delay=37 (7~67),Diff = 3 PI (10 cell)
7545 12:14:26.082323 CA4 delay=36 (6~66),Diff = 2 PI (6 cell)
7546 12:14:26.085799 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
7547 12:14:26.085889
7548 12:14:26.089420 CA PerBit enable=1, Macro0, CA PI delay=34
7549 12:14:26.089506
7550 12:14:26.092653 [CBTSetCACLKResult] CA Dly = 34
7551 12:14:26.095809 CS Dly: 9 (0~40)
7552 12:14:26.099326 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7553 12:14:26.102783 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7554 12:14:26.102883 ==
7555 12:14:26.105713 Dram Type= 6, Freq= 0, CH_0, rank 1
7556 12:14:26.108978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7557 12:14:26.112297 ==
7558 12:14:26.115927 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7559 12:14:26.119029 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7560 12:14:26.125673 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7561 12:14:26.129234 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7562 12:14:26.139310 [CA 0] Center 42 (12~73) winsize 62
7563 12:14:26.142523 [CA 1] Center 42 (12~73) winsize 62
7564 12:14:26.146182 [CA 2] Center 38 (8~68) winsize 61
7565 12:14:26.149576 [CA 3] Center 37 (8~67) winsize 60
7566 12:14:26.152931 [CA 4] Center 36 (6~66) winsize 61
7567 12:14:26.156193 [CA 5] Center 35 (5~65) winsize 61
7568 12:14:26.156277
7569 12:14:26.159852 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7570 12:14:26.159935
7571 12:14:26.162988 [CATrainingPosCal] consider 2 rank data
7572 12:14:26.166171 u2DelayCellTimex100 = 290/100 ps
7573 12:14:26.169303 CA0 delay=42 (12~73),Diff = 8 PI (26 cell)
7574 12:14:26.176083 CA1 delay=42 (12~73),Diff = 8 PI (26 cell)
7575 12:14:26.179231 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
7576 12:14:26.182931 CA3 delay=37 (8~67),Diff = 3 PI (10 cell)
7577 12:14:26.186205 CA4 delay=36 (6~66),Diff = 2 PI (6 cell)
7578 12:14:26.189443 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
7579 12:14:26.189526
7580 12:14:26.192528 CA PerBit enable=1, Macro0, CA PI delay=34
7581 12:14:26.192612
7582 12:14:26.196228 [CBTSetCACLKResult] CA Dly = 34
7583 12:14:26.199230 CS Dly: 10 (0~42)
7584 12:14:26.202702 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7585 12:14:26.206092 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7586 12:14:26.206176
7587 12:14:26.209677 ----->DramcWriteLeveling(PI) begin...
7588 12:14:26.209762 ==
7589 12:14:26.212512 Dram Type= 6, Freq= 0, CH_0, rank 0
7590 12:14:26.219373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7591 12:14:26.219486 ==
7592 12:14:26.222509 Write leveling (Byte 0): 34 => 34
7593 12:14:26.222593 Write leveling (Byte 1): 28 => 28
7594 12:14:26.225830 DramcWriteLeveling(PI) end<-----
7595 12:14:26.225913
7596 12:14:26.225977 ==
7597 12:14:26.229015 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 12:14:26.235711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 12:14:26.235799 ==
7600 12:14:26.238970 [Gating] SW mode calibration
7601 12:14:26.246104 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7602 12:14:26.249038 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7603 12:14:26.255492 1 4 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7604 12:14:26.258835 1 4 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7605 12:14:26.262393 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7606 12:14:26.268906 1 4 12 | B1->B0 | 2323 302f | 0 1 | (0 0) (1 1)
7607 12:14:26.272097 1 4 16 | B1->B0 | 2424 3737 | 1 1 | (0 0) (1 1)
7608 12:14:26.275807 1 4 20 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7609 12:14:26.281934 1 4 24 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7610 12:14:26.285735 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7611 12:14:26.288906 1 5 0 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
7612 12:14:26.295293 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7613 12:14:26.298565 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 1)
7614 12:14:26.302208 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
7615 12:14:26.305487 1 5 16 | B1->B0 | 3333 2626 | 1 0 | (1 0) (0 0)
7616 12:14:26.312636 1 5 20 | B1->B0 | 2727 2625 | 1 1 | (1 0) (0 0)
7617 12:14:26.315450 1 5 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7618 12:14:26.318995 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7619 12:14:26.325174 1 6 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7620 12:14:26.328932 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7621 12:14:26.332069 1 6 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7622 12:14:26.338366 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7623 12:14:26.342146 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7624 12:14:26.345064 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7625 12:14:26.351728 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7626 12:14:26.355022 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 12:14:26.358619 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 12:14:26.364917 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 12:14:26.368457 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7630 12:14:26.371523 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7631 12:14:26.378183 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7632 12:14:26.381710 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7633 12:14:26.385349 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7634 12:14:26.391687 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 12:14:26.394780 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 12:14:26.398508 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 12:14:26.404927 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 12:14:26.408020 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 12:14:26.411915 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 12:14:26.418447 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 12:14:26.421255 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 12:14:26.424551 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 12:14:26.431340 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 12:14:26.434594 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 12:14:26.438262 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7646 12:14:26.444627 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7647 12:14:26.447805 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7648 12:14:26.451452 Total UI for P1: 0, mck2ui 16
7649 12:14:26.454311 best dqsien dly found for B0: ( 1, 9, 10)
7650 12:14:26.458218 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7651 12:14:26.461302 Total UI for P1: 0, mck2ui 16
7652 12:14:26.464371 best dqsien dly found for B1: ( 1, 9, 16)
7653 12:14:26.467936 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7654 12:14:26.471943 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
7655 12:14:26.472037
7656 12:14:26.474915 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7657 12:14:26.481424 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
7658 12:14:26.481505 [Gating] SW calibration Done
7659 12:14:26.481569 ==
7660 12:14:26.484855 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 12:14:26.491064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 12:14:26.491189 ==
7663 12:14:26.491253 RX Vref Scan: 0
7664 12:14:26.491312
7665 12:14:26.494397 RX Vref 0 -> 0, step: 1
7666 12:14:26.494477
7667 12:14:26.498063 RX Delay 0 -> 252, step: 8
7668 12:14:26.501001 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7669 12:14:26.504815 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7670 12:14:26.507981 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7671 12:14:26.514946 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7672 12:14:26.518070 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7673 12:14:26.521133 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7674 12:14:26.524228 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7675 12:14:26.528096 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7676 12:14:26.531054 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7677 12:14:26.537867 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7678 12:14:26.541120 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7679 12:14:26.544245 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7680 12:14:26.548045 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7681 12:14:26.554017 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7682 12:14:26.557758 iDelay=200, Bit 14, Center 143 (96 ~ 191) 96
7683 12:14:26.560999 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7684 12:14:26.561080 ==
7685 12:14:26.564448 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 12:14:26.567815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 12:14:26.567898 ==
7688 12:14:26.571096 DQS Delay:
7689 12:14:26.571178 DQS0 = 0, DQS1 = 0
7690 12:14:26.574182 DQM Delay:
7691 12:14:26.574264 DQM0 = 136, DQM1 = 130
7692 12:14:26.574329 DQ Delay:
7693 12:14:26.577458 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =131
7694 12:14:26.580951 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7695 12:14:26.587633 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7696 12:14:26.591552 DQ12 =131, DQ13 =139, DQ14 =143, DQ15 =135
7697 12:14:26.591635
7698 12:14:26.591699
7699 12:14:26.591759 ==
7700 12:14:26.594486 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 12:14:26.597535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 12:14:26.597618 ==
7703 12:14:26.597684
7704 12:14:26.597745
7705 12:14:26.601148 TX Vref Scan disable
7706 12:14:26.604143 == TX Byte 0 ==
7707 12:14:26.607654 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7708 12:14:26.610952 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7709 12:14:26.614477 == TX Byte 1 ==
7710 12:14:26.617463 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7711 12:14:26.620611 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7712 12:14:26.620694 ==
7713 12:14:26.624495 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 12:14:26.627449 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 12:14:26.630475 ==
7716 12:14:26.642177
7717 12:14:26.645506 TX Vref early break, caculate TX vref
7718 12:14:26.649061 TX Vref=16, minBit 0, minWin=23, winSum=378
7719 12:14:26.652349 TX Vref=18, minBit 1, minWin=23, winSum=391
7720 12:14:26.655437 TX Vref=20, minBit 0, minWin=24, winSum=398
7721 12:14:26.659060 TX Vref=22, minBit 4, minWin=24, winSum=410
7722 12:14:26.661971 TX Vref=24, minBit 0, minWin=25, winSum=420
7723 12:14:26.668877 TX Vref=26, minBit 1, minWin=25, winSum=426
7724 12:14:26.671932 TX Vref=28, minBit 6, minWin=24, winSum=423
7725 12:14:26.675698 TX Vref=30, minBit 6, minWin=24, winSum=411
7726 12:14:26.679283 TX Vref=32, minBit 8, minWin=23, winSum=407
7727 12:14:26.682359 TX Vref=34, minBit 1, minWin=23, winSum=398
7728 12:14:26.688735 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 26
7729 12:14:26.689068
7730 12:14:26.692141 Final TX Range 0 Vref 26
7731 12:14:26.692499
7732 12:14:26.692791 ==
7733 12:14:26.695595 Dram Type= 6, Freq= 0, CH_0, rank 0
7734 12:14:26.699034 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7735 12:14:26.699370 ==
7736 12:14:26.699631
7737 12:14:26.699765
7738 12:14:26.701736 TX Vref Scan disable
7739 12:14:26.708591 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7740 12:14:26.708674 == TX Byte 0 ==
7741 12:14:26.712236 u2DelayCellOfst[0]=13 cells (4 PI)
7742 12:14:26.715276 u2DelayCellOfst[1]=13 cells (4 PI)
7743 12:14:26.719132 u2DelayCellOfst[2]=10 cells (3 PI)
7744 12:14:26.721640 u2DelayCellOfst[3]=10 cells (3 PI)
7745 12:14:26.725641 u2DelayCellOfst[4]=6 cells (2 PI)
7746 12:14:26.728576 u2DelayCellOfst[5]=0 cells (0 PI)
7747 12:14:26.731759 u2DelayCellOfst[6]=16 cells (5 PI)
7748 12:14:26.731841 u2DelayCellOfst[7]=16 cells (5 PI)
7749 12:14:26.738854 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7750 12:14:26.741941 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7751 12:14:26.742023 == TX Byte 1 ==
7752 12:14:26.745306 u2DelayCellOfst[8]=0 cells (0 PI)
7753 12:14:26.748926 u2DelayCellOfst[9]=3 cells (1 PI)
7754 12:14:26.751771 u2DelayCellOfst[10]=6 cells (2 PI)
7755 12:14:26.755284 u2DelayCellOfst[11]=3 cells (1 PI)
7756 12:14:26.758425 u2DelayCellOfst[12]=10 cells (3 PI)
7757 12:14:26.761647 u2DelayCellOfst[13]=13 cells (4 PI)
7758 12:14:26.765318 u2DelayCellOfst[14]=16 cells (5 PI)
7759 12:14:26.768419 u2DelayCellOfst[15]=10 cells (3 PI)
7760 12:14:26.772015 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7761 12:14:26.778778 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7762 12:14:26.778860 DramC Write-DBI on
7763 12:14:26.778924 ==
7764 12:14:26.781747 Dram Type= 6, Freq= 0, CH_0, rank 0
7765 12:14:26.785203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7766 12:14:26.785288 ==
7767 12:14:26.788212
7768 12:14:26.788322
7769 12:14:26.788389 TX Vref Scan disable
7770 12:14:26.791950 == TX Byte 0 ==
7771 12:14:26.795064 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7772 12:14:26.798192 == TX Byte 1 ==
7773 12:14:26.801839 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7774 12:14:26.801921 DramC Write-DBI off
7775 12:14:26.805052
7776 12:14:26.805133 [DATLAT]
7777 12:14:26.805197 Freq=1600, CH0 RK0
7778 12:14:26.805257
7779 12:14:26.808558 DATLAT Default: 0xf
7780 12:14:26.808638 0, 0xFFFF, sum = 0
7781 12:14:26.811924 1, 0xFFFF, sum = 0
7782 12:14:26.814878 2, 0xFFFF, sum = 0
7783 12:14:26.814960 3, 0xFFFF, sum = 0
7784 12:14:26.818194 4, 0xFFFF, sum = 0
7785 12:14:26.818304 5, 0xFFFF, sum = 0
7786 12:14:26.821335 6, 0xFFFF, sum = 0
7787 12:14:26.821444 7, 0xFFFF, sum = 0
7788 12:14:26.824674 8, 0xFFFF, sum = 0
7789 12:14:26.824783 9, 0xFFFF, sum = 0
7790 12:14:26.828348 10, 0xFFFF, sum = 0
7791 12:14:26.828431 11, 0xFFFF, sum = 0
7792 12:14:26.831927 12, 0xFFFF, sum = 0
7793 12:14:26.832009 13, 0xFFFF, sum = 0
7794 12:14:26.834641 14, 0x0, sum = 1
7795 12:14:26.834724 15, 0x0, sum = 2
7796 12:14:26.838076 16, 0x0, sum = 3
7797 12:14:26.838158 17, 0x0, sum = 4
7798 12:14:26.841338 best_step = 15
7799 12:14:26.841437
7800 12:14:26.841533 ==
7801 12:14:26.845021 Dram Type= 6, Freq= 0, CH_0, rank 0
7802 12:14:26.847851 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7803 12:14:26.847959 ==
7804 12:14:26.851536 RX Vref Scan: 1
7805 12:14:26.851617
7806 12:14:26.851690 Set Vref Range= 24 -> 127
7807 12:14:26.851751
7808 12:14:26.854572 RX Vref 24 -> 127, step: 1
7809 12:14:26.854654
7810 12:14:26.857739 RX Delay 27 -> 252, step: 4
7811 12:14:26.857820
7812 12:14:26.861524 Set Vref, RX VrefLevel [Byte0]: 24
7813 12:14:26.864426 [Byte1]: 24
7814 12:14:26.864508
7815 12:14:26.867691 Set Vref, RX VrefLevel [Byte0]: 25
7816 12:14:26.871262 [Byte1]: 25
7817 12:14:26.871344
7818 12:14:26.874332 Set Vref, RX VrefLevel [Byte0]: 26
7819 12:14:26.877464 [Byte1]: 26
7820 12:14:26.881961
7821 12:14:26.882042 Set Vref, RX VrefLevel [Byte0]: 27
7822 12:14:26.884957 [Byte1]: 27
7823 12:14:26.889356
7824 12:14:26.889436 Set Vref, RX VrefLevel [Byte0]: 28
7825 12:14:26.892858 [Byte1]: 28
7826 12:14:26.896998
7827 12:14:26.897079 Set Vref, RX VrefLevel [Byte0]: 29
7828 12:14:26.900220 [Byte1]: 29
7829 12:14:26.904725
7830 12:14:26.904806 Set Vref, RX VrefLevel [Byte0]: 30
7831 12:14:26.907704 [Byte1]: 30
7832 12:14:26.912084
7833 12:14:26.912182 Set Vref, RX VrefLevel [Byte0]: 31
7834 12:14:26.915139 [Byte1]: 31
7835 12:14:26.919357
7836 12:14:26.919438 Set Vref, RX VrefLevel [Byte0]: 32
7837 12:14:26.922975 [Byte1]: 32
7838 12:14:26.927026
7839 12:14:26.927106 Set Vref, RX VrefLevel [Byte0]: 33
7840 12:14:26.930114 [Byte1]: 33
7841 12:14:26.934510
7842 12:14:26.934595 Set Vref, RX VrefLevel [Byte0]: 34
7843 12:14:26.937545 [Byte1]: 34
7844 12:14:26.942392
7845 12:14:26.942474 Set Vref, RX VrefLevel [Byte0]: 35
7846 12:14:26.945812 [Byte1]: 35
7847 12:14:26.949380
7848 12:14:26.949462 Set Vref, RX VrefLevel [Byte0]: 36
7849 12:14:26.953026 [Byte1]: 36
7850 12:14:26.957381
7851 12:14:26.957462 Set Vref, RX VrefLevel [Byte0]: 37
7852 12:14:26.960641 [Byte1]: 37
7853 12:14:26.964666
7854 12:14:26.964748 Set Vref, RX VrefLevel [Byte0]: 38
7855 12:14:26.967901 [Byte1]: 38
7856 12:14:26.971961
7857 12:14:26.972043 Set Vref, RX VrefLevel [Byte0]: 39
7858 12:14:26.975567 [Byte1]: 39
7859 12:14:26.980103
7860 12:14:26.980184 Set Vref, RX VrefLevel [Byte0]: 40
7861 12:14:26.982919 [Byte1]: 40
7862 12:14:26.987345
7863 12:14:26.987456 Set Vref, RX VrefLevel [Byte0]: 41
7864 12:14:26.990475 [Byte1]: 41
7865 12:14:26.994868
7866 12:14:26.997945 Set Vref, RX VrefLevel [Byte0]: 42
7867 12:14:26.998027 [Byte1]: 42
7868 12:14:27.002208
7869 12:14:27.002289 Set Vref, RX VrefLevel [Byte0]: 43
7870 12:14:27.005821 [Byte1]: 43
7871 12:14:27.009772
7872 12:14:27.009853 Set Vref, RX VrefLevel [Byte0]: 44
7873 12:14:27.013335 [Byte1]: 44
7874 12:14:27.017454
7875 12:14:27.017536 Set Vref, RX VrefLevel [Byte0]: 45
7876 12:14:27.020608 [Byte1]: 45
7877 12:14:27.024978
7878 12:14:27.025062 Set Vref, RX VrefLevel [Byte0]: 46
7879 12:14:27.028202 [Byte1]: 46
7880 12:14:27.032570
7881 12:14:27.032653 Set Vref, RX VrefLevel [Byte0]: 47
7882 12:14:27.035554 [Byte1]: 47
7883 12:14:27.039873
7884 12:14:27.039954 Set Vref, RX VrefLevel [Byte0]: 48
7885 12:14:27.043501 [Byte1]: 48
7886 12:14:27.047408
7887 12:14:27.047489 Set Vref, RX VrefLevel [Byte0]: 49
7888 12:14:27.050687 [Byte1]: 49
7889 12:14:27.055125
7890 12:14:27.055207 Set Vref, RX VrefLevel [Byte0]: 50
7891 12:14:27.058126 [Byte1]: 50
7892 12:14:27.062527
7893 12:14:27.062609 Set Vref, RX VrefLevel [Byte0]: 51
7894 12:14:27.066358 [Byte1]: 51
7895 12:14:27.070049
7896 12:14:27.070131 Set Vref, RX VrefLevel [Byte0]: 52
7897 12:14:27.073515 [Byte1]: 52
7898 12:14:27.077985
7899 12:14:27.078067 Set Vref, RX VrefLevel [Byte0]: 53
7900 12:14:27.081267 [Byte1]: 53
7901 12:14:27.085044
7902 12:14:27.085152 Set Vref, RX VrefLevel [Byte0]: 54
7903 12:14:27.088898 [Byte1]: 54
7904 12:14:27.092664
7905 12:14:27.092745 Set Vref, RX VrefLevel [Byte0]: 55
7906 12:14:27.095870 [Byte1]: 55
7907 12:14:27.100251
7908 12:14:27.100400 Set Vref, RX VrefLevel [Byte0]: 56
7909 12:14:27.103388 [Byte1]: 56
7910 12:14:27.107718
7911 12:14:27.107806 Set Vref, RX VrefLevel [Byte0]: 57
7912 12:14:27.111381 [Byte1]: 57
7913 12:14:27.115155
7914 12:14:27.115236 Set Vref, RX VrefLevel [Byte0]: 58
7915 12:14:27.118753 [Byte1]: 58
7916 12:14:27.123059
7917 12:14:27.123139 Set Vref, RX VrefLevel [Byte0]: 59
7918 12:14:27.125877 [Byte1]: 59
7919 12:14:27.130324
7920 12:14:27.130404 Set Vref, RX VrefLevel [Byte0]: 60
7921 12:14:27.133538 [Byte1]: 60
7922 12:14:27.138053
7923 12:14:27.138134 Set Vref, RX VrefLevel [Byte0]: 61
7924 12:14:27.141109 [Byte1]: 61
7925 12:14:27.145447
7926 12:14:27.145554 Set Vref, RX VrefLevel [Byte0]: 62
7927 12:14:27.148712 [Byte1]: 62
7928 12:14:27.153065
7929 12:14:27.153146 Set Vref, RX VrefLevel [Byte0]: 63
7930 12:14:27.156491 [Byte1]: 63
7931 12:14:27.160391
7932 12:14:27.160498 Set Vref, RX VrefLevel [Byte0]: 64
7933 12:14:27.163730 [Byte1]: 64
7934 12:14:27.167832
7935 12:14:27.167914 Set Vref, RX VrefLevel [Byte0]: 65
7936 12:14:27.171463 [Byte1]: 65
7937 12:14:27.175723
7938 12:14:27.175804 Set Vref, RX VrefLevel [Byte0]: 66
7939 12:14:27.178662 [Byte1]: 66
7940 12:14:27.182951
7941 12:14:27.183035 Set Vref, RX VrefLevel [Byte0]: 67
7942 12:14:27.186267 [Byte1]: 67
7943 12:14:27.190368
7944 12:14:27.190486 Set Vref, RX VrefLevel [Byte0]: 68
7945 12:14:27.194057 [Byte1]: 68
7946 12:14:27.198194
7947 12:14:27.198275 Set Vref, RX VrefLevel [Byte0]: 69
7948 12:14:27.201475 [Byte1]: 69
7949 12:14:27.205706
7950 12:14:27.205788 Set Vref, RX VrefLevel [Byte0]: 70
7951 12:14:27.208873 [Byte1]: 70
7952 12:14:27.213291
7953 12:14:27.213374 Set Vref, RX VrefLevel [Byte0]: 71
7954 12:14:27.216258 [Byte1]: 71
7955 12:14:27.221026
7956 12:14:27.221109 Set Vref, RX VrefLevel [Byte0]: 72
7957 12:14:27.224279 [Byte1]: 72
7958 12:14:27.228518
7959 12:14:27.228614 Set Vref, RX VrefLevel [Byte0]: 73
7960 12:14:27.231396 [Byte1]: 73
7961 12:14:27.235662
7962 12:14:27.235749 Set Vref, RX VrefLevel [Byte0]: 74
7963 12:14:27.239006 [Byte1]: 74
7964 12:14:27.243366
7965 12:14:27.243448 Final RX Vref Byte 0 = 57 to rank0
7966 12:14:27.246683 Final RX Vref Byte 1 = 65 to rank0
7967 12:14:27.249699 Final RX Vref Byte 0 = 57 to rank1
7968 12:14:27.253217 Final RX Vref Byte 1 = 65 to rank1==
7969 12:14:27.257032 Dram Type= 6, Freq= 0, CH_0, rank 0
7970 12:14:27.263274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7971 12:14:27.263358 ==
7972 12:14:27.263424 DQS Delay:
7973 12:14:27.263485 DQS0 = 0, DQS1 = 0
7974 12:14:27.266797 DQM Delay:
7975 12:14:27.266880 DQM0 = 134, DQM1 = 128
7976 12:14:27.270366 DQ Delay:
7977 12:14:27.273296 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7978 12:14:27.276784 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7979 12:14:27.280361 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
7980 12:14:27.283608 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7981 12:14:27.283691
7982 12:14:27.283757
7983 12:14:27.283816
7984 12:14:27.286816 [DramC_TX_OE_Calibration] TA2
7985 12:14:27.290023 Original DQ_B0 (3 6) =30, OEN = 27
7986 12:14:27.293282 Original DQ_B1 (3 6) =30, OEN = 27
7987 12:14:27.297108 24, 0x0, End_B0=24 End_B1=24
7988 12:14:27.297192 25, 0x0, End_B0=25 End_B1=25
7989 12:14:27.300160 26, 0x0, End_B0=26 End_B1=26
7990 12:14:27.303186 27, 0x0, End_B0=27 End_B1=27
7991 12:14:27.306389 28, 0x0, End_B0=28 End_B1=28
7992 12:14:27.306472 29, 0x0, End_B0=29 End_B1=29
7993 12:14:27.309848 30, 0x0, End_B0=30 End_B1=30
7994 12:14:27.313203 31, 0x5151, End_B0=30 End_B1=30
7995 12:14:27.316591 Byte0 end_step=30 best_step=27
7996 12:14:27.319886 Byte1 end_step=30 best_step=27
7997 12:14:27.323328 Byte0 TX OE(2T, 0.5T) = (3, 3)
7998 12:14:27.323411 Byte1 TX OE(2T, 0.5T) = (3, 3)
7999 12:14:27.326683
8000 12:14:27.326790
8001 12:14:27.332949 [DQSOSCAuto] RK0, (LSB)MR18= 0x221d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 392 ps
8002 12:14:27.336503 CH0 RK0: MR19=303, MR18=221D
8003 12:14:27.343329 CH0_RK0: MR19=0x303, MR18=0x221D, DQSOSC=392, MR23=63, INC=24, DEC=16
8004 12:14:27.343412
8005 12:14:27.346540 ----->DramcWriteLeveling(PI) begin...
8006 12:14:27.346624 ==
8007 12:14:27.349736 Dram Type= 6, Freq= 0, CH_0, rank 1
8008 12:14:27.353327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8009 12:14:27.353410 ==
8010 12:14:27.356395 Write leveling (Byte 0): 36 => 36
8011 12:14:27.359534 Write leveling (Byte 1): 28 => 28
8012 12:14:27.363369 DramcWriteLeveling(PI) end<-----
8013 12:14:27.363451
8014 12:14:27.363514 ==
8015 12:14:27.366544 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 12:14:27.369458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 12:14:27.369540 ==
8018 12:14:27.373118 [Gating] SW mode calibration
8019 12:14:27.379628 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8020 12:14:27.386529 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8021 12:14:27.389417 1 4 0 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
8022 12:14:27.392831 1 4 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8023 12:14:27.399673 1 4 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
8024 12:14:27.402924 1 4 12 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
8025 12:14:27.406146 1 4 16 | B1->B0 | 2d2d 3b3b | 1 0 | (1 1) (1 1)
8026 12:14:27.413119 1 4 20 | B1->B0 | 3434 3b3a | 1 1 | (1 1) (0 0)
8027 12:14:27.416183 1 4 24 | B1->B0 | 3434 3939 | 1 0 | (1 1) (0 0)
8028 12:14:27.419291 1 4 28 | B1->B0 | 3434 3837 | 1 1 | (1 1) (0 0)
8029 12:14:27.425812 1 5 0 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
8030 12:14:27.429594 1 5 4 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
8031 12:14:27.432733 1 5 8 | B1->B0 | 3434 3b3a | 1 1 | (1 1) (0 0)
8032 12:14:27.439588 1 5 12 | B1->B0 | 3434 3737 | 1 0 | (1 0) (1 0)
8033 12:14:27.442631 1 5 16 | B1->B0 | 3232 3232 | 1 0 | (1 0) (0 1)
8034 12:14:27.446103 1 5 20 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8035 12:14:27.452828 1 5 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8036 12:14:27.456009 1 5 28 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8037 12:14:27.459320 1 6 0 | B1->B0 | 2323 3635 | 0 1 | (0 0) (1 1)
8038 12:14:27.466189 1 6 4 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8039 12:14:27.469292 1 6 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
8040 12:14:27.472514 1 6 12 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
8041 12:14:27.479287 1 6 16 | B1->B0 | 3838 4645 | 0 1 | (0 0) (0 0)
8042 12:14:27.482425 1 6 20 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
8043 12:14:27.486104 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 12:14:27.492480 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8045 12:14:27.495742 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8046 12:14:27.498945 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 12:14:27.502500 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 12:14:27.508905 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8049 12:14:27.512778 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8050 12:14:27.516005 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 12:14:27.522865 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 12:14:27.525934 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 12:14:27.529095 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 12:14:27.535770 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 12:14:27.538940 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 12:14:27.542258 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 12:14:27.549257 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 12:14:27.552214 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 12:14:27.555747 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 12:14:27.562138 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 12:14:27.566074 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 12:14:27.569057 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 12:14:27.575488 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8064 12:14:27.578768 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8065 12:14:27.581990 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 12:14:27.585456 Total UI for P1: 0, mck2ui 16
8067 12:14:27.588885 best dqsien dly found for B0: ( 1, 9, 10)
8068 12:14:27.592301 Total UI for P1: 0, mck2ui 16
8069 12:14:27.595759 best dqsien dly found for B1: ( 1, 9, 12)
8070 12:14:27.598730 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8071 12:14:27.601890 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8072 12:14:27.601972
8073 12:14:27.608935 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8074 12:14:27.612400 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8075 12:14:27.615062 [Gating] SW calibration Done
8076 12:14:27.615144 ==
8077 12:14:27.618856 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 12:14:27.622030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 12:14:27.622112 ==
8080 12:14:27.622177 RX Vref Scan: 0
8081 12:14:27.622237
8082 12:14:27.625135 RX Vref 0 -> 0, step: 1
8083 12:14:27.625217
8084 12:14:27.629060 RX Delay 0 -> 252, step: 8
8085 12:14:27.632191 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8086 12:14:27.635447 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8087 12:14:27.638434 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8088 12:14:27.645282 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8089 12:14:27.648203 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8090 12:14:27.652111 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8091 12:14:27.655178 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8092 12:14:27.658723 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8093 12:14:27.664907 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8094 12:14:27.668138 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8095 12:14:27.671755 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8096 12:14:27.675005 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8097 12:14:27.681193 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8098 12:14:27.684754 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8099 12:14:27.688324 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8100 12:14:27.691384 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8101 12:14:27.691466 ==
8102 12:14:27.694470 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 12:14:27.701289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 12:14:27.701372 ==
8105 12:14:27.701438 DQS Delay:
8106 12:14:27.701499 DQS0 = 0, DQS1 = 0
8107 12:14:27.704849 DQM Delay:
8108 12:14:27.704931 DQM0 = 137, DQM1 = 128
8109 12:14:27.707819 DQ Delay:
8110 12:14:27.711502 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8111 12:14:27.714951 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8112 12:14:27.717784 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8113 12:14:27.721345 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8114 12:14:27.721428
8115 12:14:27.721493
8116 12:14:27.721553 ==
8117 12:14:27.724536 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 12:14:27.727853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 12:14:27.730893 ==
8120 12:14:27.730976
8121 12:14:27.731041
8122 12:14:27.731101 TX Vref Scan disable
8123 12:14:27.734230 == TX Byte 0 ==
8124 12:14:27.737889 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8125 12:14:27.740956 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8126 12:14:27.744772 == TX Byte 1 ==
8127 12:14:27.747810 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8128 12:14:27.750939 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8129 12:14:27.754290 ==
8130 12:14:27.754373 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 12:14:27.760804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 12:14:27.760887 ==
8133 12:14:27.773754
8134 12:14:27.777674 TX Vref early break, caculate TX vref
8135 12:14:27.780772 TX Vref=16, minBit 1, minWin=23, winSum=388
8136 12:14:27.784568 TX Vref=18, minBit 1, minWin=22, winSum=394
8137 12:14:27.787035 TX Vref=20, minBit 1, minWin=23, winSum=405
8138 12:14:27.790694 TX Vref=22, minBit 1, minWin=24, winSum=410
8139 12:14:27.794028 TX Vref=24, minBit 0, minWin=25, winSum=421
8140 12:14:27.800576 TX Vref=26, minBit 4, minWin=24, winSum=424
8141 12:14:27.804062 TX Vref=28, minBit 3, minWin=25, winSum=425
8142 12:14:27.807543 TX Vref=30, minBit 0, minWin=25, winSum=419
8143 12:14:27.810683 TX Vref=32, minBit 0, minWin=25, winSum=412
8144 12:14:27.814155 TX Vref=34, minBit 0, minWin=24, winSum=402
8145 12:14:27.820310 [TxChooseVref] Worse bit 3, Min win 25, Win sum 425, Final Vref 28
8146 12:14:27.820413
8147 12:14:27.824215 Final TX Range 0 Vref 28
8148 12:14:27.824340
8149 12:14:27.824409 ==
8150 12:14:27.827214 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 12:14:27.830742 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 12:14:27.830828 ==
8153 12:14:27.830913
8154 12:14:27.830994
8155 12:14:27.833958 TX Vref Scan disable
8156 12:14:27.840653 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8157 12:14:27.840737 == TX Byte 0 ==
8158 12:14:27.843711 u2DelayCellOfst[0]=13 cells (4 PI)
8159 12:14:27.846883 u2DelayCellOfst[1]=16 cells (5 PI)
8160 12:14:27.850701 u2DelayCellOfst[2]=13 cells (4 PI)
8161 12:14:27.853727 u2DelayCellOfst[3]=13 cells (4 PI)
8162 12:14:27.856934 u2DelayCellOfst[4]=13 cells (4 PI)
8163 12:14:27.860573 u2DelayCellOfst[5]=0 cells (0 PI)
8164 12:14:27.863445 u2DelayCellOfst[6]=20 cells (6 PI)
8165 12:14:27.867158 u2DelayCellOfst[7]=16 cells (5 PI)
8166 12:14:27.870406 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8167 12:14:27.874017 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8168 12:14:27.874099 == TX Byte 1 ==
8169 12:14:27.877046 u2DelayCellOfst[8]=0 cells (0 PI)
8170 12:14:27.880339 u2DelayCellOfst[9]=0 cells (0 PI)
8171 12:14:27.884143 u2DelayCellOfst[10]=6 cells (2 PI)
8172 12:14:27.887252 u2DelayCellOfst[11]=3 cells (1 PI)
8173 12:14:27.890300 u2DelayCellOfst[12]=10 cells (3 PI)
8174 12:14:27.893667 u2DelayCellOfst[13]=10 cells (3 PI)
8175 12:14:27.897446 u2DelayCellOfst[14]=16 cells (5 PI)
8176 12:14:27.900642 u2DelayCellOfst[15]=10 cells (3 PI)
8177 12:14:27.903640 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8178 12:14:27.907488 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8179 12:14:27.910482 DramC Write-DBI on
8180 12:14:27.910565 ==
8181 12:14:27.913821 Dram Type= 6, Freq= 0, CH_0, rank 1
8182 12:14:27.916823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8183 12:14:27.916931 ==
8184 12:14:27.920576
8185 12:14:27.920684
8186 12:14:27.920777 TX Vref Scan disable
8187 12:14:27.923398 == TX Byte 0 ==
8188 12:14:27.927160 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8189 12:14:27.930276 == TX Byte 1 ==
8190 12:14:27.933778 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8191 12:14:27.936749 DramC Write-DBI off
8192 12:14:27.936832
8193 12:14:27.936897 [DATLAT]
8194 12:14:27.936959 Freq=1600, CH0 RK1
8195 12:14:27.937018
8196 12:14:27.940303 DATLAT Default: 0xf
8197 12:14:27.940386 0, 0xFFFF, sum = 0
8198 12:14:27.943674 1, 0xFFFF, sum = 0
8199 12:14:27.946679 2, 0xFFFF, sum = 0
8200 12:14:27.946763 3, 0xFFFF, sum = 0
8201 12:14:27.950229 4, 0xFFFF, sum = 0
8202 12:14:27.950314 5, 0xFFFF, sum = 0
8203 12:14:27.953846 6, 0xFFFF, sum = 0
8204 12:14:27.953930 7, 0xFFFF, sum = 0
8205 12:14:27.956940 8, 0xFFFF, sum = 0
8206 12:14:27.957025 9, 0xFFFF, sum = 0
8207 12:14:27.960300 10, 0xFFFF, sum = 0
8208 12:14:27.960399 11, 0xFFFF, sum = 0
8209 12:14:27.963439 12, 0xFFFF, sum = 0
8210 12:14:27.963524 13, 0xFFFF, sum = 0
8211 12:14:27.966861 14, 0x0, sum = 1
8212 12:14:27.966942 15, 0x0, sum = 2
8213 12:14:27.970107 16, 0x0, sum = 3
8214 12:14:27.970187 17, 0x0, sum = 4
8215 12:14:27.973686 best_step = 15
8216 12:14:27.973767
8217 12:14:27.973831 ==
8218 12:14:27.976969 Dram Type= 6, Freq= 0, CH_0, rank 1
8219 12:14:27.980474 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8220 12:14:27.980558 ==
8221 12:14:27.980623 RX Vref Scan: 0
8222 12:14:27.983365
8223 12:14:27.983448 RX Vref 0 -> 0, step: 1
8224 12:14:27.983514
8225 12:14:27.987268 RX Delay 19 -> 252, step: 4
8226 12:14:27.989930 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8227 12:14:27.997103 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8228 12:14:28.000707 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8229 12:14:28.003804 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8230 12:14:28.006784 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8231 12:14:28.009987 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8232 12:14:28.013269 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8233 12:14:28.020206 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8234 12:14:28.023331 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8235 12:14:28.027019 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8236 12:14:28.030014 iDelay=191, Bit 10, Center 128 (79 ~ 178) 100
8237 12:14:28.037066 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8238 12:14:28.039860 iDelay=191, Bit 12, Center 132 (79 ~ 186) 108
8239 12:14:28.043503 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8240 12:14:28.046504 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8241 12:14:28.049675 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8242 12:14:28.049757 ==
8243 12:14:28.053289 Dram Type= 6, Freq= 0, CH_0, rank 1
8244 12:14:28.060035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8245 12:14:28.060119 ==
8246 12:14:28.060185 DQS Delay:
8247 12:14:28.063168 DQS0 = 0, DQS1 = 0
8248 12:14:28.063251 DQM Delay:
8249 12:14:28.066471 DQM0 = 134, DQM1 = 126
8250 12:14:28.066579 DQ Delay:
8251 12:14:28.069513 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8252 12:14:28.073308 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =140
8253 12:14:28.076544 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8254 12:14:28.079672 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =134
8255 12:14:28.079755
8256 12:14:28.079820
8257 12:14:28.079879
8258 12:14:28.083122 [DramC_TX_OE_Calibration] TA2
8259 12:14:28.086667 Original DQ_B0 (3 6) =30, OEN = 27
8260 12:14:28.089971 Original DQ_B1 (3 6) =30, OEN = 27
8261 12:14:28.093225 24, 0x0, End_B0=24 End_B1=24
8262 12:14:28.096561 25, 0x0, End_B0=25 End_B1=25
8263 12:14:28.096645 26, 0x0, End_B0=26 End_B1=26
8264 12:14:28.099573 27, 0x0, End_B0=27 End_B1=27
8265 12:14:28.103115 28, 0x0, End_B0=28 End_B1=28
8266 12:14:28.106771 29, 0x0, End_B0=29 End_B1=29
8267 12:14:28.106855 30, 0x0, End_B0=30 End_B1=30
8268 12:14:28.109983 31, 0x4141, End_B0=30 End_B1=30
8269 12:14:28.112964 Byte0 end_step=30 best_step=27
8270 12:14:28.116213 Byte1 end_step=30 best_step=27
8271 12:14:28.119457 Byte0 TX OE(2T, 0.5T) = (3, 3)
8272 12:14:28.122757 Byte1 TX OE(2T, 0.5T) = (3, 3)
8273 12:14:28.122840
8274 12:14:28.122905
8275 12:14:28.129699 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e05, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 394 ps
8276 12:14:28.133199 CH0 RK1: MR19=303, MR18=1E05
8277 12:14:28.139903 CH0_RK1: MR19=0x303, MR18=0x1E05, DQSOSC=394, MR23=63, INC=23, DEC=15
8278 12:14:28.143028 [RxdqsGatingPostProcess] freq 1600
8279 12:14:28.145966 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8280 12:14:28.149591 best DQS0 dly(2T, 0.5T) = (1, 1)
8281 12:14:28.153200 best DQS1 dly(2T, 0.5T) = (1, 1)
8282 12:14:28.156235 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8283 12:14:28.159254 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8284 12:14:28.162593 best DQS0 dly(2T, 0.5T) = (1, 1)
8285 12:14:28.166148 best DQS1 dly(2T, 0.5T) = (1, 1)
8286 12:14:28.169249 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8287 12:14:28.172484 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8288 12:14:28.175860 Pre-setting of DQS Precalculation
8289 12:14:28.179170 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8290 12:14:28.179272 ==
8291 12:14:28.182972 Dram Type= 6, Freq= 0, CH_1, rank 0
8292 12:14:28.189069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 12:14:28.189153 ==
8294 12:14:28.192922 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8295 12:14:28.196013 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8296 12:14:28.202416 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8297 12:14:28.209219 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8298 12:14:28.216621 [CA 0] Center 41 (12~71) winsize 60
8299 12:14:28.219570 [CA 1] Center 42 (13~71) winsize 59
8300 12:14:28.223071 [CA 2] Center 38 (9~68) winsize 60
8301 12:14:28.226687 [CA 3] Center 37 (8~66) winsize 59
8302 12:14:28.229803 [CA 4] Center 37 (8~67) winsize 60
8303 12:14:28.233102 [CA 5] Center 36 (7~66) winsize 60
8304 12:14:28.233184
8305 12:14:28.236250 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8306 12:14:28.236359
8307 12:14:28.240003 [CATrainingPosCal] consider 1 rank data
8308 12:14:28.243037 u2DelayCellTimex100 = 290/100 ps
8309 12:14:28.246237 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8310 12:14:28.252941 CA1 delay=42 (13~71),Diff = 6 PI (20 cell)
8311 12:14:28.256525 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8312 12:14:28.259559 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8313 12:14:28.262855 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8314 12:14:28.266154 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8315 12:14:28.266236
8316 12:14:28.269790 CA PerBit enable=1, Macro0, CA PI delay=36
8317 12:14:28.269871
8318 12:14:28.272968 [CBTSetCACLKResult] CA Dly = 36
8319 12:14:28.276031 CS Dly: 11 (0~42)
8320 12:14:28.279487 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8321 12:14:28.283154 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8322 12:14:28.283242 ==
8323 12:14:28.286201 Dram Type= 6, Freq= 0, CH_1, rank 1
8324 12:14:28.289313 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8325 12:14:28.293031 ==
8326 12:14:28.296050 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8327 12:14:28.299332 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8328 12:14:28.306423 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8329 12:14:28.309530 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8330 12:14:28.319501 [CA 0] Center 42 (13~72) winsize 60
8331 12:14:28.323108 [CA 1] Center 42 (13~72) winsize 60
8332 12:14:28.326410 [CA 2] Center 38 (9~68) winsize 60
8333 12:14:28.329734 [CA 3] Center 38 (8~68) winsize 61
8334 12:14:28.333178 [CA 4] Center 38 (8~68) winsize 61
8335 12:14:28.336439 [CA 5] Center 37 (8~67) winsize 60
8336 12:14:28.336526
8337 12:14:28.340167 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8338 12:14:28.340265
8339 12:14:28.342956 [CATrainingPosCal] consider 2 rank data
8340 12:14:28.346763 u2DelayCellTimex100 = 290/100 ps
8341 12:14:28.349647 CA0 delay=42 (13~71),Diff = 5 PI (16 cell)
8342 12:14:28.356498 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8343 12:14:28.360097 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8344 12:14:28.363239 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8345 12:14:28.366402 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8346 12:14:28.369376 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8347 12:14:28.369460
8348 12:14:28.372693 CA PerBit enable=1, Macro0, CA PI delay=37
8349 12:14:28.372775
8350 12:14:28.376270 [CBTSetCACLKResult] CA Dly = 37
8351 12:14:28.379567 CS Dly: 12 (0~44)
8352 12:14:28.382555 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8353 12:14:28.386186 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8354 12:14:28.386268
8355 12:14:28.389696 ----->DramcWriteLeveling(PI) begin...
8356 12:14:28.389778 ==
8357 12:14:28.392807 Dram Type= 6, Freq= 0, CH_1, rank 0
8358 12:14:28.399634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 12:14:28.399716 ==
8360 12:14:28.402312 Write leveling (Byte 0): 26 => 26
8361 12:14:28.402394 Write leveling (Byte 1): 29 => 29
8362 12:14:28.405814 DramcWriteLeveling(PI) end<-----
8363 12:14:28.405896
8364 12:14:28.409045 ==
8365 12:14:28.409126 Dram Type= 6, Freq= 0, CH_1, rank 0
8366 12:14:28.415429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8367 12:14:28.415510 ==
8368 12:14:28.419215 [Gating] SW mode calibration
8369 12:14:28.425364 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8370 12:14:28.429400 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8371 12:14:28.435672 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 12:14:28.438790 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 12:14:28.442203 1 4 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
8374 12:14:28.449223 1 4 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
8375 12:14:28.451988 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 12:14:28.455604 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 12:14:28.461996 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 12:14:28.465129 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 12:14:28.468513 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 12:14:28.474924 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 12:14:28.478482 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8382 12:14:28.482061 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
8383 12:14:28.488108 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8384 12:14:28.491467 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 12:14:28.495224 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 12:14:28.501572 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 12:14:28.504759 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 12:14:28.508696 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 12:14:28.514928 1 6 8 | B1->B0 | 2424 3c3c | 0 1 | (0 0) (0 0)
8390 12:14:28.518532 1 6 12 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
8391 12:14:28.521614 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 12:14:28.527977 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 12:14:28.531701 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 12:14:28.534873 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 12:14:28.541347 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 12:14:28.545081 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 12:14:28.548173 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8398 12:14:28.551692 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8399 12:14:28.557937 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 12:14:28.561867 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 12:14:28.565026 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 12:14:28.571440 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 12:14:28.574507 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 12:14:28.578129 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 12:14:28.584911 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 12:14:28.587700 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 12:14:28.591656 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 12:14:28.598040 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 12:14:28.601362 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 12:14:28.604605 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 12:14:28.611344 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 12:14:28.614578 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 12:14:28.617887 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8414 12:14:28.624776 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8415 12:14:28.628166 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 12:14:28.631275 Total UI for P1: 0, mck2ui 16
8417 12:14:28.634409 best dqsien dly found for B0: ( 1, 9, 10)
8418 12:14:28.637510 Total UI for P1: 0, mck2ui 16
8419 12:14:28.640779 best dqsien dly found for B1: ( 1, 9, 12)
8420 12:14:28.644128 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8421 12:14:28.647964 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8422 12:14:28.648049
8423 12:14:28.651020 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8424 12:14:28.654144 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8425 12:14:28.657556 [Gating] SW calibration Done
8426 12:14:28.657642 ==
8427 12:14:28.660831 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 12:14:28.664564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 12:14:28.668243 ==
8430 12:14:28.668339 RX Vref Scan: 0
8431 12:14:28.668425
8432 12:14:28.670764 RX Vref 0 -> 0, step: 1
8433 12:14:28.670849
8434 12:14:28.674715 RX Delay 0 -> 252, step: 8
8435 12:14:28.677751 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8436 12:14:28.680857 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8437 12:14:28.684387 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8438 12:14:28.687349 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8439 12:14:28.691023 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8440 12:14:28.697733 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8441 12:14:28.700970 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8442 12:14:28.704107 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8443 12:14:28.707737 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8444 12:14:28.710697 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8445 12:14:28.717224 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8446 12:14:28.720750 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8447 12:14:28.723860 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8448 12:14:28.727025 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8449 12:14:28.733980 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8450 12:14:28.736993 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8451 12:14:28.737088 ==
8452 12:14:28.740440 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 12:14:28.744089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 12:14:28.744175 ==
8455 12:14:28.744240 DQS Delay:
8456 12:14:28.747384 DQS0 = 0, DQS1 = 0
8457 12:14:28.747466 DQM Delay:
8458 12:14:28.750576 DQM0 = 137, DQM1 = 132
8459 12:14:28.750659 DQ Delay:
8460 12:14:28.753755 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8461 12:14:28.756986 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8462 12:14:28.760436 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8463 12:14:28.767299 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8464 12:14:28.767387
8465 12:14:28.767453
8466 12:14:28.767513 ==
8467 12:14:28.770619 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 12:14:28.773555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 12:14:28.773640 ==
8470 12:14:28.773705
8471 12:14:28.773765
8472 12:14:28.777417 TX Vref Scan disable
8473 12:14:28.777501 == TX Byte 0 ==
8474 12:14:28.783670 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8475 12:14:28.787337 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8476 12:14:28.787423 == TX Byte 1 ==
8477 12:14:28.793806 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8478 12:14:28.797367 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8479 12:14:28.797467 ==
8480 12:14:28.800490 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 12:14:28.803830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 12:14:28.803941 ==
8483 12:14:28.817527
8484 12:14:28.820555 TX Vref early break, caculate TX vref
8485 12:14:28.823938 TX Vref=16, minBit 1, minWin=21, winSum=372
8486 12:14:28.827048 TX Vref=18, minBit 0, minWin=23, winSum=382
8487 12:14:28.830932 TX Vref=20, minBit 0, minWin=23, winSum=392
8488 12:14:28.834539 TX Vref=22, minBit 1, minWin=23, winSum=399
8489 12:14:28.837121 TX Vref=24, minBit 1, minWin=24, winSum=413
8490 12:14:28.843845 TX Vref=26, minBit 1, minWin=25, winSum=421
8491 12:14:28.847238 TX Vref=28, minBit 2, minWin=25, winSum=427
8492 12:14:28.850429 TX Vref=30, minBit 0, minWin=25, winSum=417
8493 12:14:28.853934 TX Vref=32, minBit 2, minWin=23, winSum=408
8494 12:14:28.857371 TX Vref=34, minBit 0, minWin=23, winSum=396
8495 12:14:28.863656 [TxChooseVref] Worse bit 2, Min win 25, Win sum 427, Final Vref 28
8496 12:14:28.863770
8497 12:14:28.867237 Final TX Range 0 Vref 28
8498 12:14:28.867327
8499 12:14:28.867413 ==
8500 12:14:28.870515 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 12:14:28.874000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 12:14:28.874090 ==
8503 12:14:28.874176
8504 12:14:28.874256
8505 12:14:28.876970 TX Vref Scan disable
8506 12:14:28.883350 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8507 12:14:28.883450 == TX Byte 0 ==
8508 12:14:28.886457 u2DelayCellOfst[0]=16 cells (5 PI)
8509 12:14:28.890348 u2DelayCellOfst[1]=10 cells (3 PI)
8510 12:14:28.893506 u2DelayCellOfst[2]=0 cells (0 PI)
8511 12:14:28.896729 u2DelayCellOfst[3]=6 cells (2 PI)
8512 12:14:28.900152 u2DelayCellOfst[4]=10 cells (3 PI)
8513 12:14:28.903513 u2DelayCellOfst[5]=16 cells (5 PI)
8514 12:14:28.907015 u2DelayCellOfst[6]=20 cells (6 PI)
8515 12:14:28.909903 u2DelayCellOfst[7]=6 cells (2 PI)
8516 12:14:28.913232 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8517 12:14:28.916560 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8518 12:14:28.916674 == TX Byte 1 ==
8519 12:14:28.920074 u2DelayCellOfst[8]=0 cells (0 PI)
8520 12:14:28.923161 u2DelayCellOfst[9]=6 cells (2 PI)
8521 12:14:28.927147 u2DelayCellOfst[10]=10 cells (3 PI)
8522 12:14:28.930190 u2DelayCellOfst[11]=6 cells (2 PI)
8523 12:14:28.933404 u2DelayCellOfst[12]=13 cells (4 PI)
8524 12:14:28.936483 u2DelayCellOfst[13]=16 cells (5 PI)
8525 12:14:28.940281 u2DelayCellOfst[14]=16 cells (5 PI)
8526 12:14:28.943322 u2DelayCellOfst[15]=16 cells (5 PI)
8527 12:14:28.946532 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8528 12:14:28.953019 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8529 12:14:28.953118 DramC Write-DBI on
8530 12:14:28.953206 ==
8531 12:14:28.956531 Dram Type= 6, Freq= 0, CH_1, rank 0
8532 12:14:28.962522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8533 12:14:28.962617 ==
8534 12:14:28.962702
8535 12:14:28.962789
8536 12:14:28.962889 TX Vref Scan disable
8537 12:14:28.966860 == TX Byte 0 ==
8538 12:14:28.969839 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8539 12:14:28.972970 == TX Byte 1 ==
8540 12:14:28.977056 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8541 12:14:28.977145 DramC Write-DBI off
8542 12:14:28.980215
8543 12:14:28.980347 [DATLAT]
8544 12:14:28.980433 Freq=1600, CH1 RK0
8545 12:14:28.980518
8546 12:14:28.983099 DATLAT Default: 0xf
8547 12:14:28.983209 0, 0xFFFF, sum = 0
8548 12:14:28.986393 1, 0xFFFF, sum = 0
8549 12:14:28.986509 2, 0xFFFF, sum = 0
8550 12:14:28.990096 3, 0xFFFF, sum = 0
8551 12:14:28.990187 4, 0xFFFF, sum = 0
8552 12:14:28.993173 5, 0xFFFF, sum = 0
8553 12:14:28.996294 6, 0xFFFF, sum = 0
8554 12:14:28.996401 7, 0xFFFF, sum = 0
8555 12:14:29.000055 8, 0xFFFF, sum = 0
8556 12:14:29.000144 9, 0xFFFF, sum = 0
8557 12:14:29.003198 10, 0xFFFF, sum = 0
8558 12:14:29.003294 11, 0xFFFF, sum = 0
8559 12:14:29.006871 12, 0xFFFF, sum = 0
8560 12:14:29.006958 13, 0xFFFF, sum = 0
8561 12:14:29.010005 14, 0x0, sum = 1
8562 12:14:29.010093 15, 0x0, sum = 2
8563 12:14:29.013156 16, 0x0, sum = 3
8564 12:14:29.013244 17, 0x0, sum = 4
8565 12:14:29.016678 best_step = 15
8566 12:14:29.016765
8567 12:14:29.016849 ==
8568 12:14:29.019787 Dram Type= 6, Freq= 0, CH_1, rank 0
8569 12:14:29.023259 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8570 12:14:29.023347 ==
8571 12:14:29.023431 RX Vref Scan: 1
8572 12:14:29.023511
8573 12:14:29.026445 Set Vref Range= 24 -> 127
8574 12:14:29.026531
8575 12:14:29.029768 RX Vref 24 -> 127, step: 1
8576 12:14:29.029856
8577 12:14:29.032937 RX Delay 27 -> 252, step: 4
8578 12:14:29.033022
8579 12:14:29.036688 Set Vref, RX VrefLevel [Byte0]: 24
8580 12:14:29.039524 [Byte1]: 24
8581 12:14:29.039608
8582 12:14:29.043228 Set Vref, RX VrefLevel [Byte0]: 25
8583 12:14:29.046370 [Byte1]: 25
8584 12:14:29.046454
8585 12:14:29.049598 Set Vref, RX VrefLevel [Byte0]: 26
8586 12:14:29.053074 [Byte1]: 26
8587 12:14:29.056578
8588 12:14:29.056664 Set Vref, RX VrefLevel [Byte0]: 27
8589 12:14:29.060256 [Byte1]: 27
8590 12:14:29.064004
8591 12:14:29.064093 Set Vref, RX VrefLevel [Byte0]: 28
8592 12:14:29.067790 [Byte1]: 28
8593 12:14:29.072181
8594 12:14:29.072270 Set Vref, RX VrefLevel [Byte0]: 29
8595 12:14:29.075328 [Byte1]: 29
8596 12:14:29.079230
8597 12:14:29.079327 Set Vref, RX VrefLevel [Byte0]: 30
8598 12:14:29.082862 [Byte1]: 30
8599 12:14:29.086960
8600 12:14:29.087046 Set Vref, RX VrefLevel [Byte0]: 31
8601 12:14:29.090017 [Byte1]: 31
8602 12:14:29.094219
8603 12:14:29.094305 Set Vref, RX VrefLevel [Byte0]: 32
8604 12:14:29.097528 [Byte1]: 32
8605 12:14:29.101836
8606 12:14:29.101931 Set Vref, RX VrefLevel [Byte0]: 33
8607 12:14:29.105332 [Byte1]: 33
8608 12:14:29.109803
8609 12:14:29.109895 Set Vref, RX VrefLevel [Byte0]: 34
8610 12:14:29.112956 [Byte1]: 34
8611 12:14:29.117214
8612 12:14:29.117315 Set Vref, RX VrefLevel [Byte0]: 35
8613 12:14:29.120166 [Byte1]: 35
8614 12:14:29.124822
8615 12:14:29.124913 Set Vref, RX VrefLevel [Byte0]: 36
8616 12:14:29.127879 [Byte1]: 36
8617 12:14:29.132035
8618 12:14:29.132126 Set Vref, RX VrefLevel [Byte0]: 37
8619 12:14:29.135105 [Byte1]: 37
8620 12:14:29.139425
8621 12:14:29.139515 Set Vref, RX VrefLevel [Byte0]: 38
8622 12:14:29.142875 [Byte1]: 38
8623 12:14:29.147245
8624 12:14:29.147337 Set Vref, RX VrefLevel [Byte0]: 39
8625 12:14:29.150090 [Byte1]: 39
8626 12:14:29.154506
8627 12:14:29.154602 Set Vref, RX VrefLevel [Byte0]: 40
8628 12:14:29.157708 [Byte1]: 40
8629 12:14:29.161947
8630 12:14:29.162038 Set Vref, RX VrefLevel [Byte0]: 41
8631 12:14:29.165241 [Byte1]: 41
8632 12:14:29.169637
8633 12:14:29.169730 Set Vref, RX VrefLevel [Byte0]: 42
8634 12:14:29.173001 [Byte1]: 42
8635 12:14:29.177507
8636 12:14:29.177599 Set Vref, RX VrefLevel [Byte0]: 43
8637 12:14:29.180855 [Byte1]: 43
8638 12:14:29.185037
8639 12:14:29.185126 Set Vref, RX VrefLevel [Byte0]: 44
8640 12:14:29.188194 [Byte1]: 44
8641 12:14:29.192562
8642 12:14:29.192652 Set Vref, RX VrefLevel [Byte0]: 45
8643 12:14:29.195647 [Byte1]: 45
8644 12:14:29.200460
8645 12:14:29.200557 Set Vref, RX VrefLevel [Byte0]: 46
8646 12:14:29.203139 [Byte1]: 46
8647 12:14:29.207324
8648 12:14:29.207414 Set Vref, RX VrefLevel [Byte0]: 47
8649 12:14:29.210437 [Byte1]: 47
8650 12:14:29.215009
8651 12:14:29.215102 Set Vref, RX VrefLevel [Byte0]: 48
8652 12:14:29.218465 [Byte1]: 48
8653 12:14:29.222462
8654 12:14:29.222559 Set Vref, RX VrefLevel [Byte0]: 49
8655 12:14:29.225552 [Byte1]: 49
8656 12:14:29.229788
8657 12:14:29.229881 Set Vref, RX VrefLevel [Byte0]: 50
8658 12:14:29.233737 [Byte1]: 50
8659 12:14:29.237445
8660 12:14:29.237533 Set Vref, RX VrefLevel [Byte0]: 51
8661 12:14:29.241114 [Byte1]: 51
8662 12:14:29.244729
8663 12:14:29.244819 Set Vref, RX VrefLevel [Byte0]: 52
8664 12:14:29.248474 [Byte1]: 52
8665 12:14:29.252472
8666 12:14:29.252565 Set Vref, RX VrefLevel [Byte0]: 53
8667 12:14:29.255690 [Byte1]: 53
8668 12:14:29.260234
8669 12:14:29.260377 Set Vref, RX VrefLevel [Byte0]: 54
8670 12:14:29.263671 [Byte1]: 54
8671 12:14:29.267594
8672 12:14:29.267686 Set Vref, RX VrefLevel [Byte0]: 55
8673 12:14:29.271219 [Byte1]: 55
8674 12:14:29.275391
8675 12:14:29.275486 Set Vref, RX VrefLevel [Byte0]: 56
8676 12:14:29.278353 [Byte1]: 56
8677 12:14:29.282865
8678 12:14:29.282957 Set Vref, RX VrefLevel [Byte0]: 57
8679 12:14:29.286150 [Byte1]: 57
8680 12:14:29.290478
8681 12:14:29.290573 Set Vref, RX VrefLevel [Byte0]: 58
8682 12:14:29.293670 [Byte1]: 58
8683 12:14:29.297535
8684 12:14:29.297630 Set Vref, RX VrefLevel [Byte0]: 59
8685 12:14:29.301254 [Byte1]: 59
8686 12:14:29.305562
8687 12:14:29.305655 Set Vref, RX VrefLevel [Byte0]: 60
8688 12:14:29.308769 [Byte1]: 60
8689 12:14:29.313131
8690 12:14:29.313221 Set Vref, RX VrefLevel [Byte0]: 61
8691 12:14:29.316157 [Byte1]: 61
8692 12:14:29.320676
8693 12:14:29.320770 Set Vref, RX VrefLevel [Byte0]: 62
8694 12:14:29.323549 [Byte1]: 62
8695 12:14:29.327779
8696 12:14:29.327874 Set Vref, RX VrefLevel [Byte0]: 63
8697 12:14:29.330996 [Byte1]: 63
8698 12:14:29.335604
8699 12:14:29.335700 Set Vref, RX VrefLevel [Byte0]: 64
8700 12:14:29.338733 [Byte1]: 64
8701 12:14:29.343139
8702 12:14:29.343231 Set Vref, RX VrefLevel [Byte0]: 65
8703 12:14:29.346458 [Byte1]: 65
8704 12:14:29.350445
8705 12:14:29.350539 Set Vref, RX VrefLevel [Byte0]: 66
8706 12:14:29.353546 [Byte1]: 66
8707 12:14:29.358067
8708 12:14:29.358161 Set Vref, RX VrefLevel [Byte0]: 67
8709 12:14:29.361371 [Byte1]: 67
8710 12:14:29.365636
8711 12:14:29.365724 Set Vref, RX VrefLevel [Byte0]: 68
8712 12:14:29.368768 [Byte1]: 68
8713 12:14:29.373352
8714 12:14:29.373445 Set Vref, RX VrefLevel [Byte0]: 69
8715 12:14:29.376809 [Byte1]: 69
8716 12:14:29.380541
8717 12:14:29.380634 Set Vref, RX VrefLevel [Byte0]: 70
8718 12:14:29.384145 [Byte1]: 70
8719 12:14:29.388254
8720 12:14:29.388389 Set Vref, RX VrefLevel [Byte0]: 71
8721 12:14:29.391505 [Byte1]: 71
8722 12:14:29.395789
8723 12:14:29.395885 Set Vref, RX VrefLevel [Byte0]: 72
8724 12:14:29.399139 [Byte1]: 72
8725 12:14:29.403488
8726 12:14:29.403583 Set Vref, RX VrefLevel [Byte0]: 73
8727 12:14:29.406738 [Byte1]: 73
8728 12:14:29.410911
8729 12:14:29.411006 Final RX Vref Byte 0 = 58 to rank0
8730 12:14:29.414073 Final RX Vref Byte 1 = 58 to rank0
8731 12:14:29.417076 Final RX Vref Byte 0 = 58 to rank1
8732 12:14:29.420984 Final RX Vref Byte 1 = 58 to rank1==
8733 12:14:29.423669 Dram Type= 6, Freq= 0, CH_1, rank 0
8734 12:14:29.430492 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8735 12:14:29.430598 ==
8736 12:14:29.430667 DQS Delay:
8737 12:14:29.434105 DQS0 = 0, DQS1 = 0
8738 12:14:29.434193 DQM Delay:
8739 12:14:29.434259 DQM0 = 134, DQM1 = 131
8740 12:14:29.437234 DQ Delay:
8741 12:14:29.440571 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8742 12:14:29.443998 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8743 12:14:29.446877 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8744 12:14:29.450120 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8745 12:14:29.450210
8746 12:14:29.450277
8747 12:14:29.450338
8748 12:14:29.453986 [DramC_TX_OE_Calibration] TA2
8749 12:14:29.457067 Original DQ_B0 (3 6) =30, OEN = 27
8750 12:14:29.460479 Original DQ_B1 (3 6) =30, OEN = 27
8751 12:14:29.463595 24, 0x0, End_B0=24 End_B1=24
8752 12:14:29.463684 25, 0x0, End_B0=25 End_B1=25
8753 12:14:29.466811 26, 0x0, End_B0=26 End_B1=26
8754 12:14:29.470632 27, 0x0, End_B0=27 End_B1=27
8755 12:14:29.473865 28, 0x0, End_B0=28 End_B1=28
8756 12:14:29.476798 29, 0x0, End_B0=29 End_B1=29
8757 12:14:29.476891 30, 0x0, End_B0=30 End_B1=30
8758 12:14:29.480329 31, 0x4141, End_B0=30 End_B1=30
8759 12:14:29.483789 Byte0 end_step=30 best_step=27
8760 12:14:29.487143 Byte1 end_step=30 best_step=27
8761 12:14:29.490513 Byte0 TX OE(2T, 0.5T) = (3, 3)
8762 12:14:29.493623 Byte1 TX OE(2T, 0.5T) = (3, 3)
8763 12:14:29.493718
8764 12:14:29.493784
8765 12:14:29.500677 [DQSOSCAuto] RK0, (LSB)MR18= 0x1825, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
8766 12:14:29.504101 CH1 RK0: MR19=303, MR18=1825
8767 12:14:29.510269 CH1_RK0: MR19=0x303, MR18=0x1825, DQSOSC=391, MR23=63, INC=24, DEC=16
8768 12:14:29.510381
8769 12:14:29.513466 ----->DramcWriteLeveling(PI) begin...
8770 12:14:29.513555 ==
8771 12:14:29.517156 Dram Type= 6, Freq= 0, CH_1, rank 1
8772 12:14:29.520253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8773 12:14:29.520382 ==
8774 12:14:29.524002 Write leveling (Byte 0): 26 => 26
8775 12:14:29.526884 Write leveling (Byte 1): 28 => 28
8776 12:14:29.530080 DramcWriteLeveling(PI) end<-----
8777 12:14:29.530171
8778 12:14:29.530239 ==
8779 12:14:29.534030 Dram Type= 6, Freq= 0, CH_1, rank 1
8780 12:14:29.537098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8781 12:14:29.537188 ==
8782 12:14:29.540064 [Gating] SW mode calibration
8783 12:14:29.547056 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8784 12:14:29.553862 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8785 12:14:29.557107 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 12:14:29.560147 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 12:14:29.566988 1 4 8 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8788 12:14:29.570019 1 4 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (0 0)
8789 12:14:29.573861 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 12:14:29.580547 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 12:14:29.583395 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 12:14:29.586679 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 12:14:29.593971 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 12:14:29.597192 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8795 12:14:29.600104 1 5 8 | B1->B0 | 2e2e 3434 | 0 1 | (0 1) (1 1)
8796 12:14:29.606834 1 5 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 1)
8797 12:14:29.609854 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8798 12:14:29.613601 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 12:14:29.620128 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 12:14:29.623059 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 12:14:29.626882 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 12:14:29.633615 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 12:14:29.637059 1 6 8 | B1->B0 | 4646 2323 | 0 0 | (0 0) (0 0)
8804 12:14:29.639849 1 6 12 | B1->B0 | 4646 3636 | 0 0 | (0 0) (0 0)
8805 12:14:29.646728 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 12:14:29.649970 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 12:14:29.653275 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 12:14:29.660156 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 12:14:29.663163 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 12:14:29.666340 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 12:14:29.670087 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8812 12:14:29.676439 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8813 12:14:29.680146 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8814 12:14:29.683311 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 12:14:29.689595 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 12:14:29.693564 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 12:14:29.696278 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 12:14:29.703056 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 12:14:29.706315 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 12:14:29.710108 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 12:14:29.716183 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 12:14:29.720031 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 12:14:29.723189 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 12:14:29.730084 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 12:14:29.733245 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 12:14:29.736221 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 12:14:29.743098 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8828 12:14:29.746606 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8829 12:14:29.749710 Total UI for P1: 0, mck2ui 16
8830 12:14:29.753885 best dqsien dly found for B1: ( 1, 9, 8)
8831 12:14:29.756543 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 12:14:29.759901 Total UI for P1: 0, mck2ui 16
8833 12:14:29.763098 best dqsien dly found for B0: ( 1, 9, 12)
8834 12:14:29.766351 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8835 12:14:29.770166 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8836 12:14:29.770265
8837 12:14:29.773192 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8838 12:14:29.779861 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8839 12:14:29.779962 [Gating] SW calibration Done
8840 12:14:29.782753 ==
8841 12:14:29.782840 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 12:14:29.789836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 12:14:29.789934 ==
8844 12:14:29.790000 RX Vref Scan: 0
8845 12:14:29.790061
8846 12:14:29.793065 RX Vref 0 -> 0, step: 1
8847 12:14:29.793150
8848 12:14:29.796207 RX Delay 0 -> 252, step: 8
8849 12:14:29.799183 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8850 12:14:29.803168 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8851 12:14:29.805970 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8852 12:14:29.812998 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8853 12:14:29.816257 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8854 12:14:29.819184 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8855 12:14:29.822477 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8856 12:14:29.825676 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8857 12:14:29.832411 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8858 12:14:29.835687 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8859 12:14:29.839179 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8860 12:14:29.842470 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8861 12:14:29.845759 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8862 12:14:29.852220 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8863 12:14:29.855908 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8864 12:14:29.859206 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8865 12:14:29.859297 ==
8866 12:14:29.862365 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 12:14:29.865981 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 12:14:29.866069 ==
8869 12:14:29.869284 DQS Delay:
8870 12:14:29.869372 DQS0 = 0, DQS1 = 0
8871 12:14:29.872435 DQM Delay:
8872 12:14:29.872524 DQM0 = 136, DQM1 = 133
8873 12:14:29.875642 DQ Delay:
8874 12:14:29.879186 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8875 12:14:29.882660 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8876 12:14:29.885477 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8877 12:14:29.888902 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8878 12:14:29.888995
8879 12:14:29.889061
8880 12:14:29.889122 ==
8881 12:14:29.892434 Dram Type= 6, Freq= 0, CH_1, rank 1
8882 12:14:29.895876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8883 12:14:29.895967 ==
8884 12:14:29.896034
8885 12:14:29.896094
8886 12:14:29.899420 TX Vref Scan disable
8887 12:14:29.902442 == TX Byte 0 ==
8888 12:14:29.905627 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8889 12:14:29.909521 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8890 12:14:29.912433 == TX Byte 1 ==
8891 12:14:29.915432 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8892 12:14:29.919107 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8893 12:14:29.919201 ==
8894 12:14:29.922303 Dram Type= 6, Freq= 0, CH_1, rank 1
8895 12:14:29.928559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8896 12:14:29.928659 ==
8897 12:14:29.941236
8898 12:14:29.944252 TX Vref early break, caculate TX vref
8899 12:14:29.947713 TX Vref=16, minBit 0, minWin=23, winSum=381
8900 12:14:29.951110 TX Vref=18, minBit 2, minWin=22, winSum=390
8901 12:14:29.953915 TX Vref=20, minBit 0, minWin=23, winSum=398
8902 12:14:29.957794 TX Vref=22, minBit 0, minWin=24, winSum=406
8903 12:14:29.960958 TX Vref=24, minBit 0, minWin=25, winSum=417
8904 12:14:29.967631 TX Vref=26, minBit 1, minWin=25, winSum=426
8905 12:14:29.970734 TX Vref=28, minBit 1, minWin=26, winSum=430
8906 12:14:29.974166 TX Vref=30, minBit 0, minWin=25, winSum=420
8907 12:14:29.977411 TX Vref=32, minBit 0, minWin=25, winSum=414
8908 12:14:29.980259 TX Vref=34, minBit 1, minWin=24, winSum=409
8909 12:14:29.987347 TX Vref=36, minBit 0, minWin=23, winSum=397
8910 12:14:29.990417 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 28
8911 12:14:29.990514
8912 12:14:29.994203 Final TX Range 0 Vref 28
8913 12:14:29.994297
8914 12:14:29.994364 ==
8915 12:14:29.997020 Dram Type= 6, Freq= 0, CH_1, rank 1
8916 12:14:30.000748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8917 12:14:30.000844 ==
8918 12:14:30.003681
8919 12:14:30.003778
8920 12:14:30.003845 TX Vref Scan disable
8921 12:14:30.010479 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8922 12:14:30.010619 == TX Byte 0 ==
8923 12:14:30.013787 u2DelayCellOfst[0]=20 cells (6 PI)
8924 12:14:30.017209 u2DelayCellOfst[1]=13 cells (4 PI)
8925 12:14:30.020951 u2DelayCellOfst[2]=0 cells (0 PI)
8926 12:14:30.023645 u2DelayCellOfst[3]=10 cells (3 PI)
8927 12:14:30.027146 u2DelayCellOfst[4]=10 cells (3 PI)
8928 12:14:30.030156 u2DelayCellOfst[5]=20 cells (6 PI)
8929 12:14:30.033570 u2DelayCellOfst[6]=20 cells (6 PI)
8930 12:14:30.037282 u2DelayCellOfst[7]=6 cells (2 PI)
8931 12:14:30.040488 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8932 12:14:30.043721 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8933 12:14:30.046999 == TX Byte 1 ==
8934 12:14:30.050448 u2DelayCellOfst[8]=0 cells (0 PI)
8935 12:14:30.053686 u2DelayCellOfst[9]=3 cells (1 PI)
8936 12:14:30.057235 u2DelayCellOfst[10]=10 cells (3 PI)
8937 12:14:30.057330 u2DelayCellOfst[11]=3 cells (1 PI)
8938 12:14:30.060672 u2DelayCellOfst[12]=13 cells (4 PI)
8939 12:14:30.063451 u2DelayCellOfst[13]=13 cells (4 PI)
8940 12:14:30.067121 u2DelayCellOfst[14]=16 cells (5 PI)
8941 12:14:30.070102 u2DelayCellOfst[15]=16 cells (5 PI)
8942 12:14:30.076770 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8943 12:14:30.079904 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8944 12:14:30.080002 DramC Write-DBI on
8945 12:14:30.080068 ==
8946 12:14:30.083960 Dram Type= 6, Freq= 0, CH_1, rank 1
8947 12:14:30.090167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8948 12:14:30.090277 ==
8949 12:14:30.090344
8950 12:14:30.090404
8951 12:14:30.090461 TX Vref Scan disable
8952 12:14:30.094558 == TX Byte 0 ==
8953 12:14:30.097934 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8954 12:14:30.100822 == TX Byte 1 ==
8955 12:14:30.104463 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8956 12:14:30.104563 DramC Write-DBI off
8957 12:14:30.107600
8958 12:14:30.107687 [DATLAT]
8959 12:14:30.107753 Freq=1600, CH1 RK1
8960 12:14:30.107814
8961 12:14:30.111177 DATLAT Default: 0xf
8962 12:14:30.111263 0, 0xFFFF, sum = 0
8963 12:14:30.114290 1, 0xFFFF, sum = 0
8964 12:14:30.117867 2, 0xFFFF, sum = 0
8965 12:14:30.117961 3, 0xFFFF, sum = 0
8966 12:14:30.121028 4, 0xFFFF, sum = 0
8967 12:14:30.121118 5, 0xFFFF, sum = 0
8968 12:14:30.123993 6, 0xFFFF, sum = 0
8969 12:14:30.124079 7, 0xFFFF, sum = 0
8970 12:14:30.127247 8, 0xFFFF, sum = 0
8971 12:14:30.127337 9, 0xFFFF, sum = 0
8972 12:14:30.131091 10, 0xFFFF, sum = 0
8973 12:14:30.131184 11, 0xFFFF, sum = 0
8974 12:14:30.134148 12, 0xFFFF, sum = 0
8975 12:14:30.134237 13, 0xFFFF, sum = 0
8976 12:14:30.137481 14, 0x0, sum = 1
8977 12:14:30.137585 15, 0x0, sum = 2
8978 12:14:30.140764 16, 0x0, sum = 3
8979 12:14:30.140853 17, 0x0, sum = 4
8980 12:14:30.143994 best_step = 15
8981 12:14:30.144081
8982 12:14:30.144147 ==
8983 12:14:30.147159 Dram Type= 6, Freq= 0, CH_1, rank 1
8984 12:14:30.150908 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8985 12:14:30.150999 ==
8986 12:14:30.154030 RX Vref Scan: 0
8987 12:14:30.154118
8988 12:14:30.154183 RX Vref 0 -> 0, step: 1
8989 12:14:30.154243
8990 12:14:30.157278 RX Delay 19 -> 252, step: 4
8991 12:14:30.160635 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8992 12:14:30.167206 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8993 12:14:30.170776 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8994 12:14:30.174175 iDelay=195, Bit 3, Center 128 (79 ~ 178) 100
8995 12:14:30.177534 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8996 12:14:30.180477 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8997 12:14:30.187396 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8998 12:14:30.190391 iDelay=195, Bit 7, Center 132 (79 ~ 186) 108
8999 12:14:30.193973 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9000 12:14:30.197273 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9001 12:14:30.200605 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9002 12:14:30.203908 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9003 12:14:30.210872 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9004 12:14:30.214130 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9005 12:14:30.217639 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9006 12:14:30.220775 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9007 12:14:30.220868 ==
9008 12:14:30.223872 Dram Type= 6, Freq= 0, CH_1, rank 1
9009 12:14:30.230560 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9010 12:14:30.230675 ==
9011 12:14:30.230743 DQS Delay:
9012 12:14:30.234288 DQS0 = 0, DQS1 = 0
9013 12:14:30.234377 DQM Delay:
9014 12:14:30.237109 DQM0 = 133, DQM1 = 130
9015 12:14:30.237227 DQ Delay:
9016 12:14:30.240810 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =128
9017 12:14:30.243681 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =132
9018 12:14:30.247471 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9019 12:14:30.250842 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9020 12:14:30.250936
9021 12:14:30.251002
9022 12:14:30.251062
9023 12:14:30.254354 [DramC_TX_OE_Calibration] TA2
9024 12:14:30.256949 Original DQ_B0 (3 6) =30, OEN = 27
9025 12:14:30.260741 Original DQ_B1 (3 6) =30, OEN = 27
9026 12:14:30.263798 24, 0x0, End_B0=24 End_B1=24
9027 12:14:30.267510 25, 0x0, End_B0=25 End_B1=25
9028 12:14:30.267605 26, 0x0, End_B0=26 End_B1=26
9029 12:14:30.270527 27, 0x0, End_B0=27 End_B1=27
9030 12:14:30.273629 28, 0x0, End_B0=28 End_B1=28
9031 12:14:30.276805 29, 0x0, End_B0=29 End_B1=29
9032 12:14:30.276897 30, 0x0, End_B0=30 End_B1=30
9033 12:14:30.280587 31, 0x4141, End_B0=30 End_B1=30
9034 12:14:30.283863 Byte0 end_step=30 best_step=27
9035 12:14:30.287214 Byte1 end_step=30 best_step=27
9036 12:14:30.290478 Byte0 TX OE(2T, 0.5T) = (3, 3)
9037 12:14:30.293613 Byte1 TX OE(2T, 0.5T) = (3, 3)
9038 12:14:30.293711
9039 12:14:30.293778
9040 12:14:30.300448 [DQSOSCAuto] RK1, (LSB)MR18= 0x2208, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9041 12:14:30.303468 CH1 RK1: MR19=303, MR18=2208
9042 12:14:30.310027 CH1_RK1: MR19=0x303, MR18=0x2208, DQSOSC=392, MR23=63, INC=24, DEC=16
9043 12:14:30.313412 [RxdqsGatingPostProcess] freq 1600
9044 12:14:30.317431 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9045 12:14:30.320208 best DQS0 dly(2T, 0.5T) = (1, 1)
9046 12:14:30.323206 best DQS1 dly(2T, 0.5T) = (1, 1)
9047 12:14:30.326913 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9048 12:14:30.329916 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9049 12:14:30.333632 best DQS0 dly(2T, 0.5T) = (1, 1)
9050 12:14:30.336622 best DQS1 dly(2T, 0.5T) = (1, 1)
9051 12:14:30.340198 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9052 12:14:30.343461 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9053 12:14:30.346691 Pre-setting of DQS Precalculation
9054 12:14:30.350335 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9055 12:14:30.356570 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9056 12:14:30.366810 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9057 12:14:30.366935
9058 12:14:30.367003
9059 12:14:30.369905 [Calibration Summary] 3200 Mbps
9060 12:14:30.369998 CH 0, Rank 0
9061 12:14:30.373733 SW Impedance : PASS
9062 12:14:30.373821 DUTY Scan : NO K
9063 12:14:30.376854 ZQ Calibration : PASS
9064 12:14:30.376938 Jitter Meter : NO K
9065 12:14:30.379997 CBT Training : PASS
9066 12:14:30.383735 Write leveling : PASS
9067 12:14:30.383823 RX DQS gating : PASS
9068 12:14:30.387001 RX DQ/DQS(RDDQC) : PASS
9069 12:14:30.390015 TX DQ/DQS : PASS
9070 12:14:30.390102 RX DATLAT : PASS
9071 12:14:30.393032 RX DQ/DQS(Engine): PASS
9072 12:14:30.396553 TX OE : PASS
9073 12:14:30.396644 All Pass.
9074 12:14:30.396710
9075 12:14:30.396771 CH 0, Rank 1
9076 12:14:30.399808 SW Impedance : PASS
9077 12:14:30.403573 DUTY Scan : NO K
9078 12:14:30.403671 ZQ Calibration : PASS
9079 12:14:30.406730 Jitter Meter : NO K
9080 12:14:30.410289 CBT Training : PASS
9081 12:14:30.410381 Write leveling : PASS
9082 12:14:30.413454 RX DQS gating : PASS
9083 12:14:30.416633 RX DQ/DQS(RDDQC) : PASS
9084 12:14:30.416730 TX DQ/DQS : PASS
9085 12:14:30.419607 RX DATLAT : PASS
9086 12:14:30.423135 RX DQ/DQS(Engine): PASS
9087 12:14:30.423224 TX OE : PASS
9088 12:14:30.423291 All Pass.
9089 12:14:30.426314
9090 12:14:30.426401 CH 1, Rank 0
9091 12:14:30.430027 SW Impedance : PASS
9092 12:14:30.430114 DUTY Scan : NO K
9093 12:14:30.433520 ZQ Calibration : PASS
9094 12:14:30.433608 Jitter Meter : NO K
9095 12:14:30.436253 CBT Training : PASS
9096 12:14:30.439982 Write leveling : PASS
9097 12:14:30.440069 RX DQS gating : PASS
9098 12:14:30.442973 RX DQ/DQS(RDDQC) : PASS
9099 12:14:30.446627 TX DQ/DQS : PASS
9100 12:14:30.446717 RX DATLAT : PASS
9101 12:14:30.449723 RX DQ/DQS(Engine): PASS
9102 12:14:30.453453 TX OE : PASS
9103 12:14:30.453545 All Pass.
9104 12:14:30.453611
9105 12:14:30.453672 CH 1, Rank 1
9106 12:14:30.456570 SW Impedance : PASS
9107 12:14:30.459766 DUTY Scan : NO K
9108 12:14:30.459853 ZQ Calibration : PASS
9109 12:14:30.462964 Jitter Meter : NO K
9110 12:14:30.466778 CBT Training : PASS
9111 12:14:30.466865 Write leveling : PASS
9112 12:14:30.469914 RX DQS gating : PASS
9113 12:14:30.473093 RX DQ/DQS(RDDQC) : PASS
9114 12:14:30.473181 TX DQ/DQS : PASS
9115 12:14:30.476466 RX DATLAT : PASS
9116 12:14:30.476551 RX DQ/DQS(Engine): PASS
9117 12:14:30.479955 TX OE : PASS
9118 12:14:30.480043 All Pass.
9119 12:14:30.480109
9120 12:14:30.483113 DramC Write-DBI on
9121 12:14:30.486261 PER_BANK_REFRESH: Hybrid Mode
9122 12:14:30.486348 TX_TRACKING: ON
9123 12:14:30.496465 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9124 12:14:30.502839 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9125 12:14:30.512728 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9126 12:14:30.515888 [FAST_K] Save calibration result to emmc
9127 12:14:30.519613 sync common calibartion params.
9128 12:14:30.519709 sync cbt_mode0:1, 1:1
9129 12:14:30.522670 dram_init: ddr_geometry: 2
9130 12:14:30.526406 dram_init: ddr_geometry: 2
9131 12:14:30.526500 dram_init: ddr_geometry: 2
9132 12:14:30.529553 0:dram_rank_size:100000000
9133 12:14:30.533119 1:dram_rank_size:100000000
9134 12:14:30.536191 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9135 12:14:30.539470 DFS_SHUFFLE_HW_MODE: ON
9136 12:14:30.542509 dramc_set_vcore_voltage set vcore to 725000
9137 12:14:30.546312 Read voltage for 1600, 0
9138 12:14:30.546405 Vio18 = 0
9139 12:14:30.549274 Vcore = 725000
9140 12:14:30.549362 Vdram = 0
9141 12:14:30.549427 Vddq = 0
9142 12:14:30.549487 Vmddr = 0
9143 12:14:30.552485 switch to 3200 Mbps bootup
9144 12:14:30.556464 [DramcRunTimeConfig]
9145 12:14:30.556559 PHYPLL
9146 12:14:30.559313 DPM_CONTROL_AFTERK: ON
9147 12:14:30.559398 PER_BANK_REFRESH: ON
9148 12:14:30.562727 REFRESH_OVERHEAD_REDUCTION: ON
9149 12:14:30.566303 CMD_PICG_NEW_MODE: OFF
9150 12:14:30.566392 XRTWTW_NEW_MODE: ON
9151 12:14:30.569351 XRTRTR_NEW_MODE: ON
9152 12:14:30.569439 TX_TRACKING: ON
9153 12:14:30.573027 RDSEL_TRACKING: OFF
9154 12:14:30.573119 DQS Precalculation for DVFS: ON
9155 12:14:30.576235 RX_TRACKING: OFF
9156 12:14:30.576360 HW_GATING DBG: ON
9157 12:14:30.579457 ZQCS_ENABLE_LP4: ON
9158 12:14:30.582461 RX_PICG_NEW_MODE: ON
9159 12:14:30.582547 TX_PICG_NEW_MODE: ON
9160 12:14:30.585909 ENABLE_RX_DCM_DPHY: ON
9161 12:14:30.589245 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9162 12:14:30.589334 DUMMY_READ_FOR_TRACKING: OFF
9163 12:14:30.592722 !!! SPM_CONTROL_AFTERK: OFF
9164 12:14:30.595943 !!! SPM could not control APHY
9165 12:14:30.599812 IMPEDANCE_TRACKING: ON
9166 12:14:30.599903 TEMP_SENSOR: ON
9167 12:14:30.602975 HW_SAVE_FOR_SR: OFF
9168 12:14:30.603065 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9169 12:14:30.609252 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9170 12:14:30.609353 Read ODT Tracking: ON
9171 12:14:30.612506 Refresh Rate DeBounce: ON
9172 12:14:30.616242 DFS_NO_QUEUE_FLUSH: ON
9173 12:14:30.619406 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9174 12:14:30.619497 ENABLE_DFS_RUNTIME_MRW: OFF
9175 12:14:30.622967 DDR_RESERVE_NEW_MODE: ON
9176 12:14:30.625859 MR_CBT_SWITCH_FREQ: ON
9177 12:14:30.625949 =========================
9178 12:14:30.646065 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9179 12:14:30.648909 dram_init: ddr_geometry: 2
9180 12:14:30.667059 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9181 12:14:30.670536 dram_init: dram init end (result: 0)
9182 12:14:30.677622 DRAM-K: Full calibration passed in 24437 msecs
9183 12:14:30.680753 MRC: failed to locate region type 0.
9184 12:14:30.680848 DRAM rank0 size:0x100000000,
9185 12:14:30.683654 DRAM rank1 size=0x100000000
9186 12:14:30.693812 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9187 12:14:30.700305 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9188 12:14:30.707197 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9189 12:14:30.713507 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9190 12:14:30.716676 DRAM rank0 size:0x100000000,
9191 12:14:30.719855 DRAM rank1 size=0x100000000
9192 12:14:30.719946 CBMEM:
9193 12:14:30.723127 IMD: root @ 0xfffff000 254 entries.
9194 12:14:30.726835 IMD: root @ 0xffffec00 62 entries.
9195 12:14:30.729920 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9196 12:14:30.736898 WARNING: RO_VPD is uninitialized or empty.
9197 12:14:30.739824 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9198 12:14:30.747126 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9199 12:14:30.760175 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9200 12:14:30.771147 BS: romstage times (exec / console): total (unknown) / 23973 ms
9201 12:14:30.771288
9202 12:14:30.771355
9203 12:14:30.781233 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9204 12:14:30.784786 ARM64: Exception handlers installed.
9205 12:14:30.788252 ARM64: Testing exception
9206 12:14:30.790867 ARM64: Done test exception
9207 12:14:30.790957 Enumerating buses...
9208 12:14:30.794185 Show all devs... Before device enumeration.
9209 12:14:30.797646 Root Device: enabled 1
9210 12:14:30.800864 CPU_CLUSTER: 0: enabled 1
9211 12:14:30.800965 CPU: 00: enabled 1
9212 12:14:30.804025 Compare with tree...
9213 12:14:30.804099 Root Device: enabled 1
9214 12:14:30.807772 CPU_CLUSTER: 0: enabled 1
9215 12:14:30.810659 CPU: 00: enabled 1
9216 12:14:30.810746 Root Device scanning...
9217 12:14:30.814066 scan_static_bus for Root Device
9218 12:14:30.817425 CPU_CLUSTER: 0 enabled
9219 12:14:30.820575 scan_static_bus for Root Device done
9220 12:14:30.824323 scan_bus: bus Root Device finished in 8 msecs
9221 12:14:30.824429 done
9222 12:14:30.830657 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9223 12:14:30.833689 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9224 12:14:30.840653 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9225 12:14:30.843726 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9226 12:14:30.847375 Allocating resources...
9227 12:14:30.850545 Reading resources...
9228 12:14:30.853741 Root Device read_resources bus 0 link: 0
9229 12:14:30.856908 DRAM rank0 size:0x100000000,
9230 12:14:30.856996 DRAM rank1 size=0x100000000
9231 12:14:30.860531 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9232 12:14:30.863670 CPU: 00 missing read_resources
9233 12:14:30.870316 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9234 12:14:30.873453 Root Device read_resources bus 0 link: 0 done
9235 12:14:30.876707 Done reading resources.
9236 12:14:30.880565 Show resources in subtree (Root Device)...After reading.
9237 12:14:30.883906 Root Device child on link 0 CPU_CLUSTER: 0
9238 12:14:30.886914 CPU_CLUSTER: 0 child on link 0 CPU: 00
9239 12:14:30.896685 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9240 12:14:30.896816 CPU: 00
9241 12:14:30.900255 Root Device assign_resources, bus 0 link: 0
9242 12:14:30.903510 CPU_CLUSTER: 0 missing set_resources
9243 12:14:30.909803 Root Device assign_resources, bus 0 link: 0 done
9244 12:14:30.909908 Done setting resources.
9245 12:14:30.916500 Show resources in subtree (Root Device)...After assigning values.
9246 12:14:30.920112 Root Device child on link 0 CPU_CLUSTER: 0
9247 12:14:30.923667 CPU_CLUSTER: 0 child on link 0 CPU: 00
9248 12:14:30.933470 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9249 12:14:30.933582 CPU: 00
9250 12:14:30.936730 Done allocating resources.
9251 12:14:30.942901 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9252 12:14:30.942994 Enabling resources...
9253 12:14:30.943059 done.
9254 12:14:30.949656 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9255 12:14:30.953232 Initializing devices...
9256 12:14:30.953322 Root Device init
9257 12:14:30.956461 init hardware done!
9258 12:14:30.956547 0x00000018: ctrlr->caps
9259 12:14:30.959584 52.000 MHz: ctrlr->f_max
9260 12:14:30.962717 0.400 MHz: ctrlr->f_min
9261 12:14:30.962804 0x40ff8080: ctrlr->voltages
9262 12:14:30.966626 sclk: 390625
9263 12:14:30.966712 Bus Width = 1
9264 12:14:30.966777 sclk: 390625
9265 12:14:30.969721 Bus Width = 1
9266 12:14:30.969805 Early init status = 3
9267 12:14:30.976016 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9268 12:14:30.979481 in-header: 03 fc 00 00 01 00 00 00
9269 12:14:30.982875 in-data: 00
9270 12:14:30.986144 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9271 12:14:30.989802 in-header: 03 fd 00 00 00 00 00 00
9272 12:14:30.993370 in-data:
9273 12:14:30.996919 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9274 12:14:31.000281 in-header: 03 fc 00 00 01 00 00 00
9275 12:14:31.003538 in-data: 00
9276 12:14:31.006731 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9277 12:14:31.011559 in-header: 03 fd 00 00 00 00 00 00
9278 12:14:31.014717 in-data:
9279 12:14:31.017925 [SSUSB] Setting up USB HOST controller...
9280 12:14:31.021331 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9281 12:14:31.024502 [SSUSB] phy power-on done.
9282 12:14:31.027728 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9283 12:14:31.034427 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9284 12:14:31.037930 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9285 12:14:31.044580 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9286 12:14:31.051498 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9287 12:14:31.057684 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9288 12:14:31.064414 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9289 12:14:31.071044 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9290 12:14:31.074685 SPM: binary array size = 0x9dc
9291 12:14:31.077878 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9292 12:14:31.084177 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9293 12:14:31.090876 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9294 12:14:31.094473 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9295 12:14:31.100655 configure_display: Starting display init
9296 12:14:31.134471 anx7625_power_on_init: Init interface.
9297 12:14:31.137777 anx7625_disable_pd_protocol: Disabled PD feature.
9298 12:14:31.141557 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9299 12:14:31.169273 anx7625_start_dp_work: Secure OCM version=00
9300 12:14:31.172537 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9301 12:14:31.187209 sp_tx_get_edid_block: EDID Block = 1
9302 12:14:31.289969 Extracted contents:
9303 12:14:31.293043 header: 00 ff ff ff ff ff ff 00
9304 12:14:31.296168 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9305 12:14:31.300087 version: 01 04
9306 12:14:31.303084 basic params: 95 1f 11 78 0a
9307 12:14:31.306285 chroma info: 76 90 94 55 54 90 27 21 50 54
9308 12:14:31.309889 established: 00 00 00
9309 12:14:31.312864 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9310 12:14:31.319789 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9311 12:14:31.326564 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9312 12:14:31.332887 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9313 12:14:31.339572 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9314 12:14:31.343212 extensions: 00
9315 12:14:31.343311 checksum: fb
9316 12:14:31.343377
9317 12:14:31.346229 Manufacturer: IVO Model 57d Serial Number 0
9318 12:14:31.349259 Made week 0 of 2020
9319 12:14:31.349345 EDID version: 1.4
9320 12:14:31.352778 Digital display
9321 12:14:31.356306 6 bits per primary color channel
9322 12:14:31.356422 DisplayPort interface
9323 12:14:31.360059 Maximum image size: 31 cm x 17 cm
9324 12:14:31.362717 Gamma: 220%
9325 12:14:31.362803 Check DPMS levels
9326 12:14:31.365909 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9327 12:14:31.369731 First detailed timing is preferred timing
9328 12:14:31.372816 Established timings supported:
9329 12:14:31.375971 Standard timings supported:
9330 12:14:31.376059 Detailed timings
9331 12:14:31.382520 Hex of detail: 383680a07038204018303c0035ae10000019
9332 12:14:31.385826 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9333 12:14:31.393079 0780 0798 07c8 0820 hborder 0
9334 12:14:31.395580 0438 043b 0447 0458 vborder 0
9335 12:14:31.399596 -hsync -vsync
9336 12:14:31.399687 Did detailed timing
9337 12:14:31.402545 Hex of detail: 000000000000000000000000000000000000
9338 12:14:31.405667 Manufacturer-specified data, tag 0
9339 12:14:31.412808 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9340 12:14:31.412918 ASCII string: InfoVision
9341 12:14:31.418936 Hex of detail: 000000fe00523134304e574635205248200a
9342 12:14:31.422551 ASCII string: R140NWF5 RH
9343 12:14:31.422644 Checksum
9344 12:14:31.422709 Checksum: 0xfb (valid)
9345 12:14:31.429267 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9346 12:14:31.432279 DSI data_rate: 832800000 bps
9347 12:14:31.435841 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9348 12:14:31.439403 anx7625_parse_edid: pixelclock(138800).
9349 12:14:31.445805 hactive(1920), hsync(48), hfp(24), hbp(88)
9350 12:14:31.449242 vactive(1080), vsync(12), vfp(3), vbp(17)
9351 12:14:31.452828 anx7625_dsi_config: config dsi.
9352 12:14:31.459262 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9353 12:14:31.471613 anx7625_dsi_config: success to config DSI
9354 12:14:31.474900 anx7625_dp_start: MIPI phy setup OK.
9355 12:14:31.478623 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9356 12:14:31.481258 mtk_ddp_mode_set invalid vrefresh 60
9357 12:14:31.484635 main_disp_path_setup
9358 12:14:31.484723 ovl_layer_smi_id_en
9359 12:14:31.488139 ovl_layer_smi_id_en
9360 12:14:31.488225 ccorr_config
9361 12:14:31.488298 aal_config
9362 12:14:31.491732 gamma_config
9363 12:14:31.491819 postmask_config
9364 12:14:31.494922 dither_config
9365 12:14:31.498307 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9366 12:14:31.504898 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9367 12:14:31.508492 Root Device init finished in 551 msecs
9368 12:14:31.511560 CPU_CLUSTER: 0 init
9369 12:14:31.518487 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9370 12:14:31.521505 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9371 12:14:31.524438 APU_MBOX 0x190000b0 = 0x10001
9372 12:14:31.528430 APU_MBOX 0x190001b0 = 0x10001
9373 12:14:31.531916 APU_MBOX 0x190005b0 = 0x10001
9374 12:14:31.534902 APU_MBOX 0x190006b0 = 0x10001
9375 12:14:31.537972 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9376 12:14:31.550933 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9377 12:14:31.563363 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9378 12:14:31.569630 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9379 12:14:31.581149 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9380 12:14:31.590617 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9381 12:14:31.593660 CPU_CLUSTER: 0 init finished in 81 msecs
9382 12:14:31.597120 Devices initialized
9383 12:14:31.600800 Show all devs... After init.
9384 12:14:31.600902 Root Device: enabled 1
9385 12:14:31.603903 CPU_CLUSTER: 0: enabled 1
9386 12:14:31.606987 CPU: 00: enabled 1
9387 12:14:31.610575 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9388 12:14:31.613473 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9389 12:14:31.616811 ELOG: NV offset 0x57f000 size 0x1000
9390 12:14:31.623315 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9391 12:14:31.629980 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9392 12:14:31.633838 ELOG: Event(17) added with size 13 at 2024-01-31 12:11:48 UTC
9393 12:14:31.636956 out: cmd=0x121: 03 db 21 01 00 00 00 00
9394 12:14:31.640774 in-header: 03 f2 00 00 2c 00 00 00
9395 12:14:31.654112 in-data: 6d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9396 12:14:31.660952 ELOG: Event(A1) added with size 10 at 2024-01-31 12:11:48 UTC
9397 12:14:31.667577 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9398 12:14:31.671185 ELOG: Event(A0) added with size 9 at 2024-01-31 12:11:48 UTC
9399 12:14:31.677262 elog_add_boot_reason: Logged dev mode boot
9400 12:14:31.681022 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9401 12:14:31.684258 Finalize devices...
9402 12:14:31.684384 Devices finalized
9403 12:14:31.690486 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9404 12:14:31.694322 Writing coreboot table at 0xffe64000
9405 12:14:31.697432 0. 000000000010a000-0000000000113fff: RAMSTAGE
9406 12:14:31.700462 1. 0000000040000000-00000000400fffff: RAM
9407 12:14:31.703870 2. 0000000040100000-000000004032afff: RAMSTAGE
9408 12:14:31.710859 3. 000000004032b000-00000000545fffff: RAM
9409 12:14:31.713945 4. 0000000054600000-000000005465ffff: BL31
9410 12:14:31.717100 5. 0000000054660000-00000000ffe63fff: RAM
9411 12:14:31.721069 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9412 12:14:31.727051 7. 0000000100000000-000000023fffffff: RAM
9413 12:14:31.727155 Passing 5 GPIOs to payload:
9414 12:14:31.733878 NAME | PORT | POLARITY | VALUE
9415 12:14:31.736983 EC in RW | 0x000000aa | low | undefined
9416 12:14:31.743790 EC interrupt | 0x00000005 | low | undefined
9417 12:14:31.747001 TPM interrupt | 0x000000ab | high | undefined
9418 12:14:31.750209 SD card detect | 0x00000011 | high | undefined
9419 12:14:31.757051 speaker enable | 0x00000093 | high | undefined
9420 12:14:31.760889 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9421 12:14:31.763367 in-header: 03 f9 00 00 02 00 00 00
9422 12:14:31.763453 in-data: 02 00
9423 12:14:31.766866 ADC[4]: Raw value=904357 ID=7
9424 12:14:31.770714 ADC[3]: Raw value=213441 ID=1
9425 12:14:31.770800 RAM Code: 0x71
9426 12:14:31.773634 ADC[6]: Raw value=75332 ID=0
9427 12:14:31.777258 ADC[5]: Raw value=212703 ID=1
9428 12:14:31.777363 SKU Code: 0x1
9429 12:14:31.783396 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3c49
9430 12:14:31.786605 coreboot table: 964 bytes.
9431 12:14:31.790592 IMD ROOT 0. 0xfffff000 0x00001000
9432 12:14:31.793678 IMD SMALL 1. 0xffffe000 0x00001000
9433 12:14:31.796789 RO MCACHE 2. 0xffffc000 0x00001104
9434 12:14:31.800047 CONSOLE 3. 0xfff7c000 0x00080000
9435 12:14:31.803191 FMAP 4. 0xfff7b000 0x00000452
9436 12:14:31.807053 TIME STAMP 5. 0xfff7a000 0x00000910
9437 12:14:31.810032 VBOOT WORK 6. 0xfff66000 0x00014000
9438 12:14:31.813261 RAMOOPS 7. 0xffe66000 0x00100000
9439 12:14:31.817031 COREBOOT 8. 0xffe64000 0x00002000
9440 12:14:31.817117 IMD small region:
9441 12:14:31.819828 IMD ROOT 0. 0xffffec00 0x00000400
9442 12:14:31.823417 VPD 1. 0xffffeb80 0x0000006c
9443 12:14:31.826911 MMC STATUS 2. 0xffffeb60 0x00000004
9444 12:14:31.833471 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9445 12:14:31.836685 Probing TPM: done!
9446 12:14:31.839744 Connected to device vid:did:rid of 1ae0:0028:00
9447 12:14:31.849963 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9448 12:14:31.853273 Initialized TPM device CR50 revision 0
9449 12:14:31.857201 Checking cr50 for pending updates
9450 12:14:31.860394 Reading cr50 TPM mode
9451 12:14:31.868773 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9452 12:14:31.875533 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9453 12:14:31.915435 read SPI 0x3990ec 0x4f1b0: 34852 us, 9296 KB/s, 74.368 Mbps
9454 12:14:31.919273 Checking segment from ROM address 0x40100000
9455 12:14:31.922280 Checking segment from ROM address 0x4010001c
9456 12:14:31.928958 Loading segment from ROM address 0x40100000
9457 12:14:31.929072 code (compression=0)
9458 12:14:31.939158 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9459 12:14:31.945688 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9460 12:14:31.945808 it's not compressed!
9461 12:14:31.952403 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9462 12:14:31.955666 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9463 12:14:31.975908 Loading segment from ROM address 0x4010001c
9464 12:14:31.976060 Entry Point 0x80000000
9465 12:14:31.979536 Loaded segments
9466 12:14:31.982557 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9467 12:14:31.989136 Jumping to boot code at 0x80000000(0xffe64000)
9468 12:14:31.995929 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9469 12:14:32.002371 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9470 12:14:32.010511 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9471 12:14:32.013750 Checking segment from ROM address 0x40100000
9472 12:14:32.017106 Checking segment from ROM address 0x4010001c
9473 12:14:32.023396 Loading segment from ROM address 0x40100000
9474 12:14:32.023514 code (compression=1)
9475 12:14:32.030294 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9476 12:14:32.040215 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9477 12:14:32.040384 using LZMA
9478 12:14:32.049041 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9479 12:14:32.055769 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9480 12:14:32.058711 Loading segment from ROM address 0x4010001c
9481 12:14:32.058809 Entry Point 0x54601000
9482 12:14:32.061988 Loaded segments
9483 12:14:32.065533 NOTICE: MT8192 bl31_setup
9484 12:14:32.072406 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9485 12:14:32.076098 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9486 12:14:32.079068 WARNING: region 0:
9487 12:14:32.082295 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9488 12:14:32.082387 WARNING: region 1:
9489 12:14:32.088942 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9490 12:14:32.092566 WARNING: region 2:
9491 12:14:32.095934 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9492 12:14:32.099522 WARNING: region 3:
9493 12:14:32.102663 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9494 12:14:32.105954 WARNING: region 4:
9495 12:14:32.109590 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9496 12:14:32.112749 WARNING: region 5:
9497 12:14:32.116032 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9498 12:14:32.119615 WARNING: region 6:
9499 12:14:32.123020 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9500 12:14:32.123113 WARNING: region 7:
9501 12:14:32.129226 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9502 12:14:32.136322 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9503 12:14:32.139597 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9504 12:14:32.142862 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9505 12:14:32.149484 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9506 12:14:32.152547 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9507 12:14:32.156272 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9508 12:14:32.163101 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9509 12:14:32.166200 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9510 12:14:32.169788 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9511 12:14:32.176049 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9512 12:14:32.179883 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9513 12:14:32.182695 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9514 12:14:32.189734 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9515 12:14:32.192835 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9516 12:14:32.199306 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9517 12:14:32.202679 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9518 12:14:32.206496 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9519 12:14:32.213103 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9520 12:14:32.216295 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9521 12:14:32.219434 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9522 12:14:32.226301 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9523 12:14:32.229482 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9524 12:14:32.237056 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9525 12:14:32.239797 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9526 12:14:32.243389 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9527 12:14:32.249821 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9528 12:14:32.253101 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9529 12:14:32.256829 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9530 12:14:32.263384 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9531 12:14:32.266834 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9532 12:14:32.273124 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9533 12:14:32.276610 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9534 12:14:32.280152 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9535 12:14:32.286606 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9536 12:14:32.290365 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9537 12:14:32.293386 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9538 12:14:32.296558 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9539 12:14:32.302866 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9540 12:14:32.306662 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9541 12:14:32.309906 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9542 12:14:32.313640 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9543 12:14:32.316727 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9544 12:14:32.323232 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9545 12:14:32.326380 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9546 12:14:32.329978 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9547 12:14:32.336225 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9548 12:14:32.340054 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9549 12:14:32.343034 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9550 12:14:32.346739 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9551 12:14:32.353645 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9552 12:14:32.356885 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9553 12:14:32.363181 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9554 12:14:32.366899 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9555 12:14:32.373325 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9556 12:14:32.376630 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9557 12:14:32.379925 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9558 12:14:32.386593 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9559 12:14:32.389864 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9560 12:14:32.396645 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9561 12:14:32.399884 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9562 12:14:32.406688 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9563 12:14:32.410114 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9564 12:14:32.416727 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9565 12:14:32.420193 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9566 12:14:32.423358 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9567 12:14:32.430331 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9568 12:14:32.433513 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9569 12:14:32.440210 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9570 12:14:32.443386 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9571 12:14:32.447085 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9572 12:14:32.453609 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9573 12:14:32.456795 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9574 12:14:32.463883 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9575 12:14:32.466946 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9576 12:14:32.473505 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9577 12:14:32.477220 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9578 12:14:32.480732 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9579 12:14:32.486873 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9580 12:14:32.490487 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9581 12:14:32.497274 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9582 12:14:32.500160 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9583 12:14:32.507389 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9584 12:14:32.510474 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9585 12:14:32.513672 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9586 12:14:32.520496 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9587 12:14:32.523772 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9588 12:14:32.530775 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9589 12:14:32.534185 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9590 12:14:32.537290 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9591 12:14:32.543862 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9592 12:14:32.547651 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9593 12:14:32.553664 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9594 12:14:32.557132 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9595 12:14:32.563964 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9596 12:14:32.567328 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9597 12:14:32.573735 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9598 12:14:32.577514 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9599 12:14:32.580497 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9600 12:14:32.584054 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9601 12:14:32.590759 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9602 12:14:32.593880 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9603 12:14:32.597665 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9604 12:14:32.604492 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9605 12:14:32.607202 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9606 12:14:32.610738 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9607 12:14:32.617164 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9608 12:14:32.620883 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9609 12:14:32.627243 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9610 12:14:32.630754 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9611 12:14:32.634032 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9612 12:14:32.641136 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9613 12:14:32.644590 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9614 12:14:32.650539 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9615 12:14:32.654016 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9616 12:14:32.657667 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9617 12:14:32.664224 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9618 12:14:32.667403 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9619 12:14:32.670543 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9620 12:14:32.677411 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9621 12:14:32.681084 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9622 12:14:32.684176 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9623 12:14:32.687815 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9624 12:14:32.690744 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9625 12:14:32.697680 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9626 12:14:32.700827 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9627 12:14:32.707192 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9628 12:14:32.710451 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9629 12:14:32.714099 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9630 12:14:32.720464 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9631 12:14:32.724552 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9632 12:14:32.727256 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9633 12:14:32.733839 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9634 12:14:32.737686 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9635 12:14:32.744500 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9636 12:14:32.747595 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9637 12:14:32.750682 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9638 12:14:32.757582 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9639 12:14:32.760944 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9640 12:14:32.767568 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9641 12:14:32.770755 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9642 12:14:32.774069 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9643 12:14:32.781193 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9644 12:14:32.784681 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9645 12:14:32.787372 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9646 12:14:32.794179 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9647 12:14:32.797703 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9648 12:14:32.804521 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9649 12:14:32.807706 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9650 12:14:32.811013 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9651 12:14:32.817952 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9652 12:14:32.821075 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9653 12:14:32.824834 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9654 12:14:32.831295 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9655 12:14:32.834944 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9656 12:14:32.841625 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9657 12:14:32.844555 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9658 12:14:32.847856 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9659 12:14:32.854467 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9660 12:14:32.857938 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9661 12:14:32.864830 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9662 12:14:32.868052 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9663 12:14:32.871251 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9664 12:14:32.877894 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9665 12:14:32.881010 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9666 12:14:32.888038 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9667 12:14:32.890876 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9668 12:14:32.894107 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9669 12:14:32.900567 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9670 12:14:32.904036 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9671 12:14:32.907670 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9672 12:14:32.914232 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9673 12:14:32.917526 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9674 12:14:32.924184 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9675 12:14:32.927323 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9676 12:14:32.931225 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9677 12:14:32.937568 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9678 12:14:32.940772 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9679 12:14:32.947570 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9680 12:14:32.950739 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9681 12:14:32.954444 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9682 12:14:32.960887 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9683 12:14:32.964271 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9684 12:14:32.970591 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9685 12:14:32.973913 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9686 12:14:32.977437 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9687 12:14:32.983835 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9688 12:14:32.986885 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9689 12:14:32.993819 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9690 12:14:32.997088 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9691 12:14:33.000073 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9692 12:14:33.007003 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9693 12:14:33.010297 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9694 12:14:33.016805 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9695 12:14:33.019980 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9696 12:14:33.023745 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9697 12:14:33.029898 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9698 12:14:33.033662 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9699 12:14:33.039791 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9700 12:14:33.043724 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9701 12:14:33.049849 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9702 12:14:33.053482 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9703 12:14:33.056739 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9704 12:14:33.063569 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9705 12:14:33.066674 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9706 12:14:33.073148 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9707 12:14:33.076608 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9708 12:14:33.083216 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9709 12:14:33.086765 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9710 12:14:33.089704 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9711 12:14:33.096171 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9712 12:14:33.100170 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9713 12:14:33.106333 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9714 12:14:33.110060 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9715 12:14:33.113098 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9716 12:14:33.119841 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9717 12:14:33.122792 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9718 12:14:33.129436 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9719 12:14:33.132954 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9720 12:14:33.139664 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9721 12:14:33.143012 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9722 12:14:33.146176 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9723 12:14:33.152516 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9724 12:14:33.156239 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9725 12:14:33.162921 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9726 12:14:33.165998 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9727 12:14:33.172332 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9728 12:14:33.176133 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9729 12:14:33.179128 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9730 12:14:33.186029 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9731 12:14:33.189266 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9732 12:14:33.192860 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9733 12:14:33.195704 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9734 12:14:33.202463 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9735 12:14:33.206082 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9736 12:14:33.209637 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9737 12:14:33.216079 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9738 12:14:33.219709 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9739 12:14:33.222711 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9740 12:14:33.229326 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9741 12:14:33.232731 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9742 12:14:33.235704 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9743 12:14:33.242393 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9744 12:14:33.245425 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9745 12:14:33.249222 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9746 12:14:33.255699 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9747 12:14:33.259096 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9748 12:14:33.265754 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9749 12:14:33.268621 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9750 12:14:33.272208 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9751 12:14:33.278661 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9752 12:14:33.282288 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9753 12:14:33.288616 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9754 12:14:33.291787 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9755 12:14:33.295677 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9756 12:14:33.301801 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9757 12:14:33.305381 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9758 12:14:33.308654 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9759 12:14:33.315337 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9760 12:14:33.318367 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9761 12:14:33.321539 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9762 12:14:33.328425 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9763 12:14:33.331655 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9764 12:14:33.338450 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9765 12:14:33.341677 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9766 12:14:33.345382 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9767 12:14:33.351921 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9768 12:14:33.355119 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9769 12:14:33.358320 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9770 12:14:33.365285 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9771 12:14:33.368187 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9772 12:14:33.371834 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9773 12:14:33.374999 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9774 12:14:33.381267 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9775 12:14:33.384649 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9776 12:14:33.388219 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9777 12:14:33.391380 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9778 12:14:33.397934 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9779 12:14:33.401056 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9780 12:14:33.404794 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9781 12:14:33.407730 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9782 12:14:33.414961 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9783 12:14:33.417908 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9784 12:14:33.421208 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9785 12:14:33.428183 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9786 12:14:33.431028 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9787 12:14:33.437696 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9788 12:14:33.441254 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9789 12:14:33.444714 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9790 12:14:33.451507 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9791 12:14:33.454768 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9792 12:14:33.461091 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9793 12:14:33.464430 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9794 12:14:33.468252 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9795 12:14:33.474567 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9796 12:14:33.477668 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9797 12:14:33.484618 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9798 12:14:33.487686 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9799 12:14:33.490948 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9800 12:14:33.497930 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9801 12:14:33.501016 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9802 12:14:33.507250 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9803 12:14:33.511224 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9804 12:14:33.517721 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9805 12:14:33.520751 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9806 12:14:33.523957 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9807 12:14:33.530597 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9808 12:14:33.534315 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9809 12:14:33.540850 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9810 12:14:33.543978 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9811 12:14:33.548016 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9812 12:14:33.554440 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9813 12:14:33.557646 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9814 12:14:33.564200 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9815 12:14:33.567285 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9816 12:14:33.570785 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9817 12:14:33.577142 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9818 12:14:33.580594 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9819 12:14:33.587257 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9820 12:14:33.590507 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9821 12:14:33.597434 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9822 12:14:33.600674 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9823 12:14:33.603552 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9824 12:14:33.610629 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9825 12:14:33.613645 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9826 12:14:33.617290 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9827 12:14:33.623517 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9828 12:14:33.627122 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9829 12:14:33.633883 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9830 12:14:33.637326 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9831 12:14:33.640657 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9832 12:14:33.647002 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9833 12:14:33.650160 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9834 12:14:33.657411 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9835 12:14:33.660510 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9836 12:14:33.667330 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9837 12:14:33.670539 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9838 12:14:33.673653 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9839 12:14:33.680154 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9840 12:14:33.683456 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9841 12:14:33.690459 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9842 12:14:33.693718 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9843 12:14:33.697347 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9844 12:14:33.703586 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9845 12:14:33.706917 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9846 12:14:33.713534 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9847 12:14:33.716780 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9848 12:14:33.720430 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9849 12:14:33.726641 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9850 12:14:33.730462 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9851 12:14:33.737142 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9852 12:14:33.740228 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9853 12:14:33.746944 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9854 12:14:33.750054 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9855 12:14:33.753336 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9856 12:14:33.759773 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9857 12:14:33.763349 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9858 12:14:33.769772 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9859 12:14:33.773056 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9860 12:14:33.780006 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9861 12:14:33.783185 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9862 12:14:33.786848 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9863 12:14:33.793039 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9864 12:14:33.796471 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9865 12:14:33.803032 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9866 12:14:33.806226 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9867 12:14:33.813120 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9868 12:14:33.816757 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9869 12:14:33.820099 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9870 12:14:33.826291 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9871 12:14:33.829948 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9872 12:14:33.836574 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9873 12:14:33.839708 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9874 12:14:33.846428 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9875 12:14:33.850028 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9876 12:14:33.853086 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9877 12:14:33.859554 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9878 12:14:33.863061 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9879 12:14:33.869896 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9880 12:14:33.872907 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9881 12:14:33.879819 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9882 12:14:33.883041 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9883 12:14:33.886258 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9884 12:14:33.893041 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9885 12:14:33.896167 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9886 12:14:33.903037 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9887 12:14:33.906259 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9888 12:14:33.912642 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9889 12:14:33.916222 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9890 12:14:33.919353 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9891 12:14:33.926491 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9892 12:14:33.929627 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9893 12:14:33.936186 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9894 12:14:33.939458 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9895 12:14:33.945898 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9896 12:14:33.949199 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9897 12:14:33.952729 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9898 12:14:33.959217 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9899 12:14:33.962721 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9900 12:14:33.969651 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9901 12:14:33.972592 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9902 12:14:33.979157 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9903 12:14:33.982347 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9904 12:14:33.985617 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9905 12:14:33.992984 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9906 12:14:33.996011 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9907 12:14:34.002388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9908 12:14:34.006194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9909 12:14:34.012498 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9910 12:14:34.016104 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9911 12:14:34.022409 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9912 12:14:34.025414 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9913 12:14:34.032347 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9914 12:14:34.035745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9915 12:14:34.041964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9916 12:14:34.045865 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9917 12:14:34.052409 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9918 12:14:34.055479 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9919 12:14:34.062566 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9920 12:14:34.065182 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9921 12:14:34.068630 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9922 12:14:34.075322 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9923 12:14:34.078884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9924 12:14:34.085761 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9925 12:14:34.088857 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9926 12:14:34.095392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9927 12:14:34.099303 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9928 12:14:34.105231 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9929 12:14:34.108468 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9930 12:14:34.115331 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9931 12:14:34.122453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9932 12:14:34.124921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9933 12:14:34.132211 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9934 12:14:34.135332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9935 12:14:34.141484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9936 12:14:34.144679 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9937 12:14:34.144770 INFO: [APUAPC] vio 0
9938 12:14:34.152184 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9939 12:14:34.155799 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9940 12:14:34.159605 INFO: [APUAPC] D0_APC_0: 0x400510
9941 12:14:34.162942 INFO: [APUAPC] D0_APC_1: 0x0
9942 12:14:34.166110 INFO: [APUAPC] D0_APC_2: 0x1540
9943 12:14:34.169247 INFO: [APUAPC] D0_APC_3: 0x0
9944 12:14:34.172290 INFO: [APUAPC] D1_APC_0: 0xffffffff
9945 12:14:34.176143 INFO: [APUAPC] D1_APC_1: 0xffffffff
9946 12:14:34.179248 INFO: [APUAPC] D1_APC_2: 0x3fffff
9947 12:14:34.182481 INFO: [APUAPC] D1_APC_3: 0x0
9948 12:14:34.185952 INFO: [APUAPC] D2_APC_0: 0xffffffff
9949 12:14:34.189267 INFO: [APUAPC] D2_APC_1: 0xffffffff
9950 12:14:34.192523 INFO: [APUAPC] D2_APC_2: 0x3fffff
9951 12:14:34.195711 INFO: [APUAPC] D2_APC_3: 0x0
9952 12:14:34.198950 INFO: [APUAPC] D3_APC_0: 0xffffffff
9953 12:14:34.202231 INFO: [APUAPC] D3_APC_1: 0xffffffff
9954 12:14:34.205749 INFO: [APUAPC] D3_APC_2: 0x3fffff
9955 12:14:34.205844 INFO: [APUAPC] D3_APC_3: 0x0
9956 12:14:34.212749 INFO: [APUAPC] D4_APC_0: 0xffffffff
9957 12:14:34.215735 INFO: [APUAPC] D4_APC_1: 0xffffffff
9958 12:14:34.218836 INFO: [APUAPC] D4_APC_2: 0x3fffff
9959 12:14:34.218925 INFO: [APUAPC] D4_APC_3: 0x0
9960 12:14:34.222073 INFO: [APUAPC] D5_APC_0: 0xffffffff
9961 12:14:34.228489 INFO: [APUAPC] D5_APC_1: 0xffffffff
9962 12:14:34.231729 INFO: [APUAPC] D5_APC_2: 0x3fffff
9963 12:14:34.231821 INFO: [APUAPC] D5_APC_3: 0x0
9964 12:14:34.235044 INFO: [APUAPC] D6_APC_0: 0xffffffff
9965 12:14:34.238712 INFO: [APUAPC] D6_APC_1: 0xffffffff
9966 12:14:34.242090 INFO: [APUAPC] D6_APC_2: 0x3fffff
9967 12:14:34.245384 INFO: [APUAPC] D6_APC_3: 0x0
9968 12:14:34.248500 INFO: [APUAPC] D7_APC_0: 0xffffffff
9969 12:14:34.252300 INFO: [APUAPC] D7_APC_1: 0xffffffff
9970 12:14:34.255252 INFO: [APUAPC] D7_APC_2: 0x3fffff
9971 12:14:34.258218 INFO: [APUAPC] D7_APC_3: 0x0
9972 12:14:34.261301 INFO: [APUAPC] D8_APC_0: 0xffffffff
9973 12:14:34.264807 INFO: [APUAPC] D8_APC_1: 0xffffffff
9974 12:14:34.268430 INFO: [APUAPC] D8_APC_2: 0x3fffff
9975 12:14:34.271415 INFO: [APUAPC] D8_APC_3: 0x0
9976 12:14:34.275135 INFO: [APUAPC] D9_APC_0: 0xffffffff
9977 12:14:34.278235 INFO: [APUAPC] D9_APC_1: 0xffffffff
9978 12:14:34.281505 INFO: [APUAPC] D9_APC_2: 0x3fffff
9979 12:14:34.284567 INFO: [APUAPC] D9_APC_3: 0x0
9980 12:14:34.287823 INFO: [APUAPC] D10_APC_0: 0xffffffff
9981 12:14:34.291046 INFO: [APUAPC] D10_APC_1: 0xffffffff
9982 12:14:34.294490 INFO: [APUAPC] D10_APC_2: 0x3fffff
9983 12:14:34.298294 INFO: [APUAPC] D10_APC_3: 0x0
9984 12:14:34.301392 INFO: [APUAPC] D11_APC_0: 0xffffffff
9985 12:14:34.304751 INFO: [APUAPC] D11_APC_1: 0xffffffff
9986 12:14:34.308189 INFO: [APUAPC] D11_APC_2: 0x3fffff
9987 12:14:34.311312 INFO: [APUAPC] D11_APC_3: 0x0
9988 12:14:34.314760 INFO: [APUAPC] D12_APC_0: 0xffffffff
9989 12:14:34.318193 INFO: [APUAPC] D12_APC_1: 0xffffffff
9990 12:14:34.321363 INFO: [APUAPC] D12_APC_2: 0x3fffff
9991 12:14:34.324498 INFO: [APUAPC] D12_APC_3: 0x0
9992 12:14:34.327628 INFO: [APUAPC] D13_APC_0: 0xffffffff
9993 12:14:34.331503 INFO: [APUAPC] D13_APC_1: 0xffffffff
9994 12:14:34.334747 INFO: [APUAPC] D13_APC_2: 0x3fffff
9995 12:14:34.337578 INFO: [APUAPC] D13_APC_3: 0x0
9996 12:14:34.341220 INFO: [APUAPC] D14_APC_0: 0xffffffff
9997 12:14:34.344487 INFO: [APUAPC] D14_APC_1: 0xffffffff
9998 12:14:34.347734 INFO: [APUAPC] D14_APC_2: 0x3fffff
9999 12:14:34.350813 INFO: [APUAPC] D14_APC_3: 0x0
10000 12:14:34.354288 INFO: [APUAPC] D15_APC_0: 0xffffffff
10001 12:14:34.357887 INFO: [APUAPC] D15_APC_1: 0xffffffff
10002 12:14:34.360822 INFO: [APUAPC] D15_APC_2: 0x3fffff
10003 12:14:34.364382 INFO: [APUAPC] D15_APC_3: 0x0
10004 12:14:34.367483 INFO: [APUAPC] APC_CON: 0x4
10005 12:14:34.371387 INFO: [NOCDAPC] D0_APC_0: 0x0
10006 12:14:34.373877 INFO: [NOCDAPC] D0_APC_1: 0x0
10007 12:14:34.377679 INFO: [NOCDAPC] D1_APC_0: 0x0
10008 12:14:34.381077 INFO: [NOCDAPC] D1_APC_1: 0xfff
10009 12:14:34.384236 INFO: [NOCDAPC] D2_APC_0: 0x0
10010 12:14:34.387384 INFO: [NOCDAPC] D2_APC_1: 0xfff
10011 12:14:34.387476 INFO: [NOCDAPC] D3_APC_0: 0x0
10012 12:14:34.391170 INFO: [NOCDAPC] D3_APC_1: 0xfff
10013 12:14:34.394400 INFO: [NOCDAPC] D4_APC_0: 0x0
10014 12:14:34.397340 INFO: [NOCDAPC] D4_APC_1: 0xfff
10015 12:14:34.400951 INFO: [NOCDAPC] D5_APC_0: 0x0
10016 12:14:34.404093 INFO: [NOCDAPC] D5_APC_1: 0xfff
10017 12:14:34.407286 INFO: [NOCDAPC] D6_APC_0: 0x0
10018 12:14:34.410413 INFO: [NOCDAPC] D6_APC_1: 0xfff
10019 12:14:34.414113 INFO: [NOCDAPC] D7_APC_0: 0x0
10020 12:14:34.417140 INFO: [NOCDAPC] D7_APC_1: 0xfff
10021 12:14:34.420348 INFO: [NOCDAPC] D8_APC_0: 0x0
10022 12:14:34.424040 INFO: [NOCDAPC] D8_APC_1: 0xfff
10023 12:14:34.424152 INFO: [NOCDAPC] D9_APC_0: 0x0
10024 12:14:34.426781 INFO: [NOCDAPC] D9_APC_1: 0xfff
10025 12:14:34.430414 INFO: [NOCDAPC] D10_APC_0: 0x0
10026 12:14:34.434004 INFO: [NOCDAPC] D10_APC_1: 0xfff
10027 12:14:34.436946 INFO: [NOCDAPC] D11_APC_0: 0x0
10028 12:14:34.440200 INFO: [NOCDAPC] D11_APC_1: 0xfff
10029 12:14:34.443763 INFO: [NOCDAPC] D12_APC_0: 0x0
10030 12:14:34.446951 INFO: [NOCDAPC] D12_APC_1: 0xfff
10031 12:14:34.450072 INFO: [NOCDAPC] D13_APC_0: 0x0
10032 12:14:34.453873 INFO: [NOCDAPC] D13_APC_1: 0xfff
10033 12:14:34.456933 INFO: [NOCDAPC] D14_APC_0: 0x0
10034 12:14:34.460491 INFO: [NOCDAPC] D14_APC_1: 0xfff
10035 12:14:34.463471 INFO: [NOCDAPC] D15_APC_0: 0x0
10036 12:14:34.466689 INFO: [NOCDAPC] D15_APC_1: 0xfff
10037 12:14:34.466778 INFO: [NOCDAPC] APC_CON: 0x4
10038 12:14:34.469964 INFO: [APUAPC] set_apusys_apc done
10039 12:14:34.473333 INFO: [DEVAPC] devapc_init done
10040 12:14:34.480010 INFO: GICv3 without legacy support detected.
10041 12:14:34.483556 INFO: ARM GICv3 driver initialized in EL3
10042 12:14:34.486570 INFO: Maximum SPI INTID supported: 639
10043 12:14:34.489746 INFO: BL31: Initializing runtime services
10044 12:14:34.496407 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10045 12:14:34.499651 INFO: SPM: enable CPC mode
10046 12:14:34.503296 INFO: mcdi ready for mcusys-off-idle and system suspend
10047 12:14:34.510151 INFO: BL31: Preparing for EL3 exit to normal world
10048 12:14:34.513224 INFO: Entry point address = 0x80000000
10049 12:14:34.513321 INFO: SPSR = 0x8
10050 12:14:34.520414
10051 12:14:34.520512
10052 12:14:34.520578
10053 12:14:34.523555 Starting depthcharge on Spherion...
10054 12:14:34.523638
10055 12:14:34.523704 Wipe memory regions:
10056 12:14:34.523765
10057 12:14:34.524490 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10058 12:14:34.524591 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10059 12:14:34.524927 Setting prompt string to ['asurada:']
10060 12:14:34.525012 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10061 12:14:34.527060 [0x00000040000000, 0x00000054600000)
10062 12:14:34.649698
10063 12:14:34.649858 [0x00000054660000, 0x00000080000000)
10064 12:14:34.909758
10065 12:14:34.909918 [0x000000821a7280, 0x000000ffe64000)
10066 12:14:35.654604
10067 12:14:35.654761 [0x00000100000000, 0x00000240000000)
10068 12:14:37.544957
10069 12:14:37.547979 Initializing XHCI USB controller at 0x11200000.
10070 12:14:38.586516
10071 12:14:38.589498 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10072 12:14:38.589583
10073 12:14:38.589648
10074 12:14:38.589709
10075 12:14:38.589987 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10077 12:14:38.690380 asurada: tftpboot 192.168.201.1 12669535/tftp-deploy-ejgbvkr4/kernel/image.itb 12669535/tftp-deploy-ejgbvkr4/kernel/cmdline
10078 12:14:38.690565 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10079 12:14:38.690688 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10080 12:14:38.694914 tftpboot 192.168.201.1 12669535/tftp-deploy-ejgbvkr4/kernel/image.itp-deploy-ejgbvkr4/kernel/cmdline
10081 12:14:38.694998
10082 12:14:38.695093 Waiting for link
10083 12:14:38.855484
10084 12:14:38.855640 R8152: Initializing
10085 12:14:38.855709
10086 12:14:38.859061 Version 9 (ocp_data = 6010)
10087 12:14:38.859143
10088 12:14:38.862034 R8152: Done initializing
10089 12:14:38.862117
10090 12:14:38.862183 Adding net device
10091 12:14:40.808057
10092 12:14:40.808213 done.
10093 12:14:40.808280
10094 12:14:40.808349 MAC: 00:e0:4c:78:7a:aa
10095 12:14:40.808408
10096 12:14:40.811258 Sending DHCP discover... done.
10097 12:14:40.811342
10098 12:14:40.815148 Waiting for reply... done.
10099 12:14:40.815231
10100 12:14:40.817787 Sending DHCP request... done.
10101 12:14:40.817870
10102 12:14:40.821200 Waiting for reply... done.
10103 12:14:40.821284
10104 12:14:40.821349 My ip is 192.168.201.12
10105 12:14:40.821410
10106 12:14:40.824831 The DHCP server ip is 192.168.201.1
10107 12:14:40.824913
10108 12:14:40.831091 TFTP server IP predefined by user: 192.168.201.1
10109 12:14:40.831174
10110 12:14:40.837622 Bootfile predefined by user: 12669535/tftp-deploy-ejgbvkr4/kernel/image.itb
10111 12:14:40.837707
10112 12:14:40.837772 Sending tftp read request... done.
10113 12:14:40.841256
10114 12:14:40.844704 Waiting for the transfer...
10115 12:14:40.844786
10116 12:14:41.103251 00000000 ################################################################
10117 12:14:41.103386
10118 12:14:41.392267 00080000 ################################################################
10119 12:14:41.392460
10120 12:14:41.685645 00100000 ################################################################
10121 12:14:41.685792
10122 12:14:41.976233 00180000 ################################################################
10123 12:14:41.976417
10124 12:14:42.273081 00200000 ################################################################
10125 12:14:42.273222
10126 12:14:42.571875 00280000 ################################################################
10127 12:14:42.572016
10128 12:14:42.871740 00300000 ################################################################
10129 12:14:42.871886
10130 12:14:43.135015 00380000 ################################################################
10131 12:14:43.135156
10132 12:14:43.401111 00400000 ################################################################
10133 12:14:43.401249
10134 12:14:43.687918 00480000 ################################################################
10135 12:14:43.688067
10136 12:14:43.967824 00500000 ################################################################
10137 12:14:43.967961
10138 12:14:44.227313 00580000 ################################################################
10139 12:14:44.227447
10140 12:14:44.490162 00600000 ################################################################
10141 12:14:44.490296
10142 12:14:44.745515 00680000 ################################################################
10143 12:14:44.745645
10144 12:14:45.007044 00700000 ################################################################
10145 12:14:45.007194
10146 12:14:45.255927 00780000 ################################################################
10147 12:14:45.256102
10148 12:14:45.544208 00800000 ################################################################
10149 12:14:45.544397
10150 12:14:45.836756 00880000 ################################################################
10151 12:14:45.836894
10152 12:14:46.130501 00900000 ################################################################
10153 12:14:46.130634
10154 12:14:46.419622 00980000 ################################################################
10155 12:14:46.419775
10156 12:14:46.702787 00a00000 ################################################################
10157 12:14:46.703015
10158 12:14:46.978073 00a80000 ################################################################
10159 12:14:46.978219
10160 12:14:47.255480 00b00000 ################################################################
10161 12:14:47.255621
10162 12:14:47.533241 00b80000 ################################################################
10163 12:14:47.533377
10164 12:14:47.819172 00c00000 ################################################################
10165 12:14:47.819354
10166 12:14:48.079635 00c80000 ################################################################
10167 12:14:48.079769
10168 12:14:48.336034 00d00000 ################################################################
10169 12:14:48.336184
10170 12:14:48.595554 00d80000 ################################################################
10171 12:14:48.595687
10172 12:14:48.853823 00e00000 ################################################################
10173 12:14:48.853959
10174 12:14:49.117687 00e80000 ################################################################
10175 12:14:49.117822
10176 12:14:49.368128 00f00000 ################################################################
10177 12:14:49.368315
10178 12:14:49.624532 00f80000 ################################################################
10179 12:14:49.624673
10180 12:14:49.874366 01000000 ################################################################
10181 12:14:49.874515
10182 12:14:50.222474 01080000 ################################################################
10183 12:14:50.222636
10184 12:14:50.585663 01100000 ################################################################
10185 12:14:50.585813
10186 12:14:50.940551 01180000 ################################################################
10187 12:14:50.940746
10188 12:14:51.274582 01200000 ################################################################
10189 12:14:51.274729
10190 12:14:51.536240 01280000 ################################################################
10191 12:14:51.536446
10192 12:14:51.805200 01300000 ################################################################
10193 12:14:51.805345
10194 12:14:52.076405 01380000 ################################################################
10195 12:14:52.076571
10196 12:14:52.354791 01400000 ################################################################
10197 12:14:52.354931
10198 12:14:52.619595 01480000 ################################################################
10199 12:14:52.619738
10200 12:14:52.904458 01500000 ################################################################
10201 12:14:52.904594
10202 12:14:53.183309 01580000 ################################################################
10203 12:14:53.183467
10204 12:14:53.452201 01600000 ################################################################
10205 12:14:53.452387
10206 12:14:53.738581 01680000 ################################################################
10207 12:14:53.738727
10208 12:14:53.990105 01700000 ################################################################
10209 12:14:53.990241
10210 12:14:54.265470 01780000 ################################################################
10211 12:14:54.265613
10212 12:14:54.535175 01800000 ################################################################
10213 12:14:54.535311
10214 12:14:54.795309 01880000 ################################################################
10215 12:14:54.795473
10216 12:14:55.051324 01900000 ################################################################
10217 12:14:55.051482
10218 12:14:55.317229 01980000 ################################################################
10219 12:14:55.317378
10220 12:14:55.587019 01a00000 ################################################################
10221 12:14:55.587163
10222 12:14:55.843332 01a80000 ################################################################
10223 12:14:55.843478
10224 12:14:56.107977 01b00000 ################################################################
10225 12:14:56.108129
10226 12:14:56.367128 01b80000 ################################################################
10227 12:14:56.367273
10228 12:14:56.634788 01c00000 ################################################################
10229 12:14:56.634928
10230 12:14:56.639439 01c80000 ## done.
10231 12:14:56.639525
10232 12:14:56.642995 The bootfile was 29894954 bytes long.
10233 12:14:56.643081
10234 12:14:56.646038 Sending tftp read request... done.
10235 12:14:56.646126
10236 12:14:56.649210 Waiting for the transfer...
10237 12:14:56.649307
10238 12:14:56.649375 00000000 # done.
10239 12:14:56.649440
10240 12:14:56.659666 Command line loaded dynamically from TFTP file: 12669535/tftp-deploy-ejgbvkr4/kernel/cmdline
10241 12:14:56.659753
10242 12:14:56.679482 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12669535/extract-nfsrootfs-gf8v15sn,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10243 12:14:56.679574
10244 12:14:56.682633 Loading FIT.
10245 12:14:56.682715
10246 12:14:56.685723 Image ramdisk-1 has 17798360 bytes.
10247 12:14:56.685820
10248 12:14:56.685885 Image fdt-1 has 47278 bytes.
10249 12:14:56.685947
10250 12:14:56.689126 Image kernel-1 has 12047284 bytes.
10251 12:14:56.689209
10252 12:14:56.698927 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10253 12:14:56.699025
10254 12:14:56.716033 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10255 12:14:56.716158
10256 12:14:56.722603 Choosing best match conf-1 for compat google,spherion-rev2.
10257 12:14:56.726497
10258 12:14:56.730936 Connected to device vid:did:rid of 1ae0:0028:00
10259 12:14:56.739105
10260 12:14:56.742260 tpm_get_response: command 0x17b, return code 0x0
10261 12:14:56.742343
10262 12:14:56.745372 ec_init: CrosEC protocol v3 supported (256, 248)
10263 12:14:56.749786
10264 12:14:56.752806 tpm_cleanup: add release locality here.
10265 12:14:56.752888
10266 12:14:56.752953 Shutting down all USB controllers.
10267 12:14:56.756226
10268 12:14:56.756337 Removing current net device
10269 12:14:56.756435
10270 12:14:56.763002 Exiting depthcharge with code 4 at timestamp: 51497452
10271 12:14:56.763114
10272 12:14:56.766386 LZMA decompressing kernel-1 to 0x821a6718
10273 12:14:56.766468
10274 12:14:56.769566 LZMA decompressing kernel-1 to 0x40000000
10275 12:14:58.269685
10276 12:14:58.269825 jumping to kernel
10277 12:14:58.270280 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10278 12:14:58.270381 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10279 12:14:58.270458 Setting prompt string to ['Linux version [0-9]']
10280 12:14:58.270526 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10281 12:14:58.270595 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10282 12:14:58.351557
10283 12:14:58.354555 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10284 12:14:58.357907 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10285 12:14:58.357998 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10286 12:14:58.358103 Setting prompt string to []
10287 12:14:58.358179 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10288 12:14:58.358253 Using line separator: #'\n'#
10289 12:14:58.358326 No login prompt set.
10290 12:14:58.358432 Parsing kernel messages
10291 12:14:58.358487 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10292 12:14:58.358584 [login-action] Waiting for messages, (timeout 00:04:01)
10293 12:14:58.377723 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j93261-arm64-gcc-10-defconfig-arm64-chromebook-cwjwh) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024
10294 12:14:58.380956 [ 0.000000] random: crng init done
10295 12:14:58.387625 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10296 12:14:58.390716 [ 0.000000] efi: UEFI not found.
10297 12:14:58.397710 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10298 12:14:58.403859 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10299 12:14:58.413971 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10300 12:14:58.424144 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10301 12:14:58.431165 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10302 12:14:58.437575 [ 0.000000] printk: bootconsole [mtk8250] enabled
10303 12:14:58.443664 [ 0.000000] NUMA: No NUMA configuration found
10304 12:14:58.450556 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10305 12:14:58.453922 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10306 12:14:58.457089 [ 0.000000] Zone ranges:
10307 12:14:58.464014 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10308 12:14:58.467149 [ 0.000000] DMA32 empty
10309 12:14:58.473741 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10310 12:14:58.476942 [ 0.000000] Movable zone start for each node
10311 12:14:58.480225 [ 0.000000] Early memory node ranges
10312 12:14:58.487472 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10313 12:14:58.493762 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10314 12:14:58.500495 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10315 12:14:58.503791 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10316 12:14:58.510658 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10317 12:14:58.517093 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10318 12:14:58.575496 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10319 12:14:58.582155 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10320 12:14:58.588585 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10321 12:14:58.591980 [ 0.000000] psci: probing for conduit method from DT.
10322 12:14:58.598795 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10323 12:14:58.601911 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10324 12:14:58.608993 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10325 12:14:58.612240 [ 0.000000] psci: SMC Calling Convention v1.2
10326 12:14:58.618623 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10327 12:14:58.622268 [ 0.000000] Detected VIPT I-cache on CPU0
10328 12:14:58.628791 [ 0.000000] CPU features: detected: GIC system register CPU interface
10329 12:14:58.635158 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10330 12:14:58.641839 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10331 12:14:58.648522 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10332 12:14:58.655246 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10333 12:14:58.661941 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10334 12:14:58.668297 [ 0.000000] alternatives: applying boot alternatives
10335 12:14:58.672103 [ 0.000000] Fallback order for Node 0: 0
10336 12:14:58.678700 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10337 12:14:58.681828 [ 0.000000] Policy zone: Normal
10338 12:14:58.705182 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12669535/extract-nfsrootfs-gf8v15sn,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10339 12:14:58.714816 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10340 12:14:58.728092 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10341 12:14:58.738022 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10342 12:14:58.744540 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10343 12:14:58.747576 <6>[ 0.000000] software IO TLB: area num 8.
10344 12:14:58.804237 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10345 12:14:58.954142 <6>[ 0.000000] Memory: 7949872K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 402896K reserved, 32768K cma-reserved)
10346 12:14:58.960517 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10347 12:14:58.967188 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10348 12:14:58.970132 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10349 12:14:58.977266 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10350 12:14:58.984029 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10351 12:14:58.987154 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10352 12:14:58.997104 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10353 12:14:59.003601 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10354 12:14:59.009953 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10355 12:14:59.016600 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10356 12:14:59.020182 <6>[ 0.000000] GICv3: 608 SPIs implemented
10357 12:14:59.023532 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10358 12:14:59.029995 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10359 12:14:59.033107 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10360 12:14:59.040124 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10361 12:14:59.053078 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10362 12:14:59.066111 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10363 12:14:59.073014 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10364 12:14:59.080779 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10365 12:14:59.093960 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10366 12:14:59.100250 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10367 12:14:59.107254 <6>[ 0.009191] Console: colour dummy device 80x25
10368 12:14:59.117145 <6>[ 0.013919] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10369 12:14:59.123341 <6>[ 0.024361] pid_max: default: 32768 minimum: 301
10370 12:14:59.126900 <6>[ 0.029231] LSM: Security Framework initializing
10371 12:14:59.133206 <6>[ 0.034170] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10372 12:14:59.143427 <6>[ 0.042031] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10373 12:14:59.150068 <6>[ 0.051455] cblist_init_generic: Setting adjustable number of callback queues.
10374 12:14:59.156781 <6>[ 0.058898] cblist_init_generic: Setting shift to 3 and lim to 1.
10375 12:14:59.166515 <6>[ 0.065276] cblist_init_generic: Setting adjustable number of callback queues.
10376 12:14:59.173269 <6>[ 0.072704] cblist_init_generic: Setting shift to 3 and lim to 1.
10377 12:14:59.176547 <6>[ 0.079106] rcu: Hierarchical SRCU implementation.
10378 12:14:59.182754 <6>[ 0.084152] rcu: Max phase no-delay instances is 1000.
10379 12:14:59.189511 <6>[ 0.091209] EFI services will not be available.
10380 12:14:59.193007 <6>[ 0.096163] smp: Bringing up secondary CPUs ...
10381 12:14:59.201169 <6>[ 0.101240] Detected VIPT I-cache on CPU1
10382 12:14:59.207574 <6>[ 0.101310] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10383 12:14:59.214756 <6>[ 0.101341] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10384 12:14:59.217988 <6>[ 0.101674] Detected VIPT I-cache on CPU2
10385 12:14:59.227636 <6>[ 0.101722] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10386 12:14:59.234181 <6>[ 0.101737] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10387 12:14:59.237545 <6>[ 0.101994] Detected VIPT I-cache on CPU3
10388 12:14:59.244595 <6>[ 0.102041] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10389 12:14:59.251052 <6>[ 0.102056] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10390 12:14:59.254322 <6>[ 0.102362] CPU features: detected: Spectre-v4
10391 12:14:59.260970 <6>[ 0.102371] CPU features: detected: Spectre-BHB
10392 12:14:59.264161 <6>[ 0.102376] Detected PIPT I-cache on CPU4
10393 12:14:59.270850 <6>[ 0.102431] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10394 12:14:59.277423 <6>[ 0.102447] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10395 12:14:59.284334 <6>[ 0.102739] Detected PIPT I-cache on CPU5
10396 12:14:59.290784 <6>[ 0.102801] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10397 12:14:59.297679 <6>[ 0.102820] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10398 12:14:59.300711 <6>[ 0.103099] Detected PIPT I-cache on CPU6
10399 12:14:59.307315 <6>[ 0.103163] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10400 12:14:59.314242 <6>[ 0.103180] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10401 12:14:59.320799 <6>[ 0.103477] Detected PIPT I-cache on CPU7
10402 12:14:59.327775 <6>[ 0.103540] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10403 12:14:59.334327 <6>[ 0.103558] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10404 12:14:59.337374 <6>[ 0.103605] smp: Brought up 1 node, 8 CPUs
10405 12:14:59.340935 <6>[ 0.244971] SMP: Total of 8 processors activated.
10406 12:14:59.347709 <6>[ 0.249922] CPU features: detected: 32-bit EL0 Support
10407 12:14:59.357305 <6>[ 0.255284] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10408 12:14:59.364091 <6>[ 0.264139] CPU features: detected: Common not Private translations
10409 12:14:59.367372 <6>[ 0.270615] CPU features: detected: CRC32 instructions
10410 12:14:59.374284 <6>[ 0.275967] CPU features: detected: RCpc load-acquire (LDAPR)
10411 12:14:59.380908 <6>[ 0.281963] CPU features: detected: LSE atomic instructions
10412 12:14:59.387030 <6>[ 0.287744] CPU features: detected: Privileged Access Never
10413 12:14:59.390499 <6>[ 0.293524] CPU features: detected: RAS Extension Support
10414 12:14:59.400452 <6>[ 0.299133] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10415 12:14:59.403712 <6>[ 0.306352] CPU: All CPU(s) started at EL2
10416 12:14:59.410175 <6>[ 0.310696] alternatives: applying system-wide alternatives
10417 12:14:59.419029 <6>[ 0.321412] devtmpfs: initialized
10418 12:14:59.431491 <6>[ 0.330331] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10419 12:14:59.441272 <6>[ 0.340290] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10420 12:14:59.448009 <6>[ 0.348502] pinctrl core: initialized pinctrl subsystem
10421 12:14:59.450895 <6>[ 0.355148] DMI not present or invalid.
10422 12:14:59.458200 <6>[ 0.359561] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10423 12:14:59.467565 <6>[ 0.366449] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10424 12:14:59.474260 <6>[ 0.374019] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10425 12:14:59.483924 <6>[ 0.382252] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10426 12:14:59.487209 <6>[ 0.390492] audit: initializing netlink subsys (disabled)
10427 12:14:59.497065 <5>[ 0.396185] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10428 12:14:59.503825 <6>[ 0.396887] thermal_sys: Registered thermal governor 'step_wise'
10429 12:14:59.510463 <6>[ 0.404152] thermal_sys: Registered thermal governor 'power_allocator'
10430 12:14:59.513782 <6>[ 0.410409] cpuidle: using governor menu
10431 12:14:59.520637 <6>[ 0.421374] NET: Registered PF_QIPCRTR protocol family
10432 12:14:59.527274 <6>[ 0.426858] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10433 12:14:59.530772 <6>[ 0.433960] ASID allocator initialised with 32768 entries
10434 12:14:59.538142 <6>[ 0.440517] Serial: AMBA PL011 UART driver
10435 12:14:59.546939 <4>[ 0.449281] Trying to register duplicate clock ID: 134
10436 12:14:59.601060 <6>[ 0.506662] KASLR enabled
10437 12:14:59.615094 <6>[ 0.514398] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10438 12:14:59.622130 <6>[ 0.521412] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10439 12:14:59.628702 <6>[ 0.527903] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10440 12:14:59.635181 <6>[ 0.534907] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10441 12:14:59.642114 <6>[ 0.541392] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10442 12:14:59.648521 <6>[ 0.548398] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10443 12:14:59.655412 <6>[ 0.554885] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10444 12:14:59.662039 <6>[ 0.561888] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10445 12:14:59.665427 <6>[ 0.569402] ACPI: Interpreter disabled.
10446 12:14:59.673532 <6>[ 0.575770] iommu: Default domain type: Translated
10447 12:14:59.680156 <6>[ 0.580881] iommu: DMA domain TLB invalidation policy: strict mode
10448 12:14:59.683230 <5>[ 0.587541] SCSI subsystem initialized
10449 12:14:59.690168 <6>[ 0.591687] usbcore: registered new interface driver usbfs
10450 12:14:59.696614 <6>[ 0.597418] usbcore: registered new interface driver hub
10451 12:14:59.700075 <6>[ 0.602969] usbcore: registered new device driver usb
10452 12:14:59.706658 <6>[ 0.609059] pps_core: LinuxPPS API ver. 1 registered
10453 12:14:59.716687 <6>[ 0.614253] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10454 12:14:59.719816 <6>[ 0.623600] PTP clock support registered
10455 12:14:59.723009 <6>[ 0.627845] EDAC MC: Ver: 3.0.0
10456 12:14:59.731025 <6>[ 0.633010] FPGA manager framework
10457 12:14:59.737402 <6>[ 0.636693] Advanced Linux Sound Architecture Driver Initialized.
10458 12:14:59.740358 <6>[ 0.643468] vgaarb: loaded
10459 12:14:59.746792 <6>[ 0.646623] clocksource: Switched to clocksource arch_sys_counter
10460 12:14:59.750243 <5>[ 0.653064] VFS: Disk quotas dquot_6.6.0
10461 12:14:59.756884 <6>[ 0.657249] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10462 12:14:59.760592 <6>[ 0.664439] pnp: PnP ACPI: disabled
10463 12:14:59.768839 <6>[ 0.671145] NET: Registered PF_INET protocol family
10464 12:14:59.778489 <6>[ 0.676743] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10465 12:14:59.790674 <6>[ 0.689052] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10466 12:14:59.799831 <6>[ 0.697870] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10467 12:14:59.806757 <6>[ 0.705839] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10468 12:14:59.812960 <6>[ 0.714540] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10469 12:14:59.825177 <6>[ 0.724297] TCP: Hash tables configured (established 65536 bind 65536)
10470 12:14:59.832033 <6>[ 0.731162] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10471 12:14:59.838408 <6>[ 0.738362] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10472 12:14:59.845017 <6>[ 0.746063] NET: Registered PF_UNIX/PF_LOCAL protocol family
10473 12:14:59.852017 <6>[ 0.752216] RPC: Registered named UNIX socket transport module.
10474 12:14:59.854982 <6>[ 0.758370] RPC: Registered udp transport module.
10475 12:14:59.861650 <6>[ 0.763304] RPC: Registered tcp transport module.
10476 12:14:59.868718 <6>[ 0.768238] RPC: Registered tcp NFSv4.1 backchannel transport module.
10477 12:14:59.871989 <6>[ 0.774903] PCI: CLS 0 bytes, default 64
10478 12:14:59.875035 <6>[ 0.779220] Unpacking initramfs...
10479 12:14:59.892113 <6>[ 0.791188] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10480 12:14:59.902108 <6>[ 0.799845] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10481 12:14:59.905373 <6>[ 0.808702] kvm [1]: IPA Size Limit: 40 bits
10482 12:14:59.912010 <6>[ 0.813233] kvm [1]: GICv3: no GICV resource entry
10483 12:14:59.915069 <6>[ 0.818254] kvm [1]: disabling GICv2 emulation
10484 12:14:59.921825 <6>[ 0.822944] kvm [1]: GIC system register CPU interface enabled
10485 12:14:59.928494 <6>[ 0.830672] kvm [1]: vgic interrupt IRQ18
10486 12:14:59.931774 <6>[ 0.835050] kvm [1]: VHE mode initialized successfully
10487 12:14:59.939517 <5>[ 0.841481] Initialise system trusted keyrings
10488 12:14:59.945811 <6>[ 0.846285] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10489 12:14:59.954225 <6>[ 0.856475] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10490 12:14:59.960722 <5>[ 0.862889] NFS: Registering the id_resolver key type
10491 12:14:59.964002 <5>[ 0.868185] Key type id_resolver registered
10492 12:14:59.970643 <5>[ 0.872598] Key type id_legacy registered
10493 12:14:59.977018 <6>[ 0.876876] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10494 12:14:59.983621 <6>[ 0.883801] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10495 12:14:59.990236 <6>[ 0.891523] 9p: Installing v9fs 9p2000 file system support
10496 12:15:00.027347 <5>[ 0.929577] Key type asymmetric registered
10497 12:15:00.030668 <5>[ 0.933909] Asymmetric key parser 'x509' registered
10498 12:15:00.040252 <6>[ 0.939057] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10499 12:15:00.043541 <6>[ 0.946673] io scheduler mq-deadline registered
10500 12:15:00.046799 <6>[ 0.951435] io scheduler kyber registered
10501 12:15:00.066078 <6>[ 0.968588] EINJ: ACPI disabled.
10502 12:15:00.098174 <4>[ 0.993908] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10503 12:15:00.107914 <4>[ 1.004530] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10504 12:15:00.123082 <6>[ 1.025241] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10505 12:15:00.130867 <6>[ 1.033138] printk: console [ttyS0] disabled
10506 12:15:00.158766 <6>[ 1.057791] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10507 12:15:00.165493 <6>[ 1.067268] printk: console [ttyS0] enabled
10508 12:15:00.168530 <6>[ 1.067268] printk: console [ttyS0] enabled
10509 12:15:00.175450 <6>[ 1.076165] printk: bootconsole [mtk8250] disabled
10510 12:15:00.178475 <6>[ 1.076165] printk: bootconsole [mtk8250] disabled
10511 12:15:00.185653 <6>[ 1.087204] SuperH (H)SCI(F) driver initialized
10512 12:15:00.188578 <6>[ 1.092485] msm_serial: driver initialized
10513 12:15:00.202598 <6>[ 1.101395] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10514 12:15:00.212576 <6>[ 1.109953] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10515 12:15:00.218616 <6>[ 1.118499] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10516 12:15:00.229178 <6>[ 1.127132] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10517 12:15:00.235630 <6>[ 1.135840] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10518 12:15:00.245284 <6>[ 1.144554] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10519 12:15:00.255643 <6>[ 1.153094] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10520 12:15:00.262548 <6>[ 1.161886] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10521 12:15:00.272056 <6>[ 1.170429] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10522 12:15:00.283358 <6>[ 1.186049] loop: module loaded
10523 12:15:00.290132 <6>[ 1.192026] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10524 12:15:00.312864 <4>[ 1.215435] mtk-pmic-keys: Failed to locate of_node [id: -1]
10525 12:15:00.319614 <6>[ 1.222337] megasas: 07.719.03.00-rc1
10526 12:15:00.329839 <6>[ 1.232176] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10527 12:15:00.336222 <6>[ 1.234066] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10528 12:15:00.352230 <6>[ 1.254064] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10529 12:15:00.408189 <6>[ 1.304206] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10530 12:15:00.616418 <6>[ 1.518960] Freeing initrd memory: 17380K
10531 12:15:00.626539 <6>[ 1.529356] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10532 12:15:00.637751 <6>[ 1.540411] tun: Universal TUN/TAP device driver, 1.6
10533 12:15:00.640914 <6>[ 1.546473] thunder_xcv, ver 1.0
10534 12:15:00.644708 <6>[ 1.549978] thunder_bgx, ver 1.0
10535 12:15:00.648005 <6>[ 1.553476] nicpf, ver 1.0
10536 12:15:00.658387 <6>[ 1.557497] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10537 12:15:00.661853 <6>[ 1.564974] hns3: Copyright (c) 2017 Huawei Corporation.
10538 12:15:00.664809 <6>[ 1.570560] hclge is initializing
10539 12:15:00.672121 <6>[ 1.574135] e1000: Intel(R) PRO/1000 Network Driver
10540 12:15:00.678484 <6>[ 1.579265] e1000: Copyright (c) 1999-2006 Intel Corporation.
10541 12:15:00.682106 <6>[ 1.585282] e1000e: Intel(R) PRO/1000 Network Driver
10542 12:15:00.688552 <6>[ 1.590497] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10543 12:15:00.695443 <6>[ 1.596684] igb: Intel(R) Gigabit Ethernet Network Driver
10544 12:15:00.701800 <6>[ 1.602334] igb: Copyright (c) 2007-2014 Intel Corporation.
10545 12:15:00.708572 <6>[ 1.608169] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10546 12:15:00.711996 <6>[ 1.614688] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10547 12:15:00.719256 <6>[ 1.621150] sky2: driver version 1.30
10548 12:15:00.725652 <6>[ 1.626145] VFIO - User Level meta-driver version: 0.3
10549 12:15:00.732129 <6>[ 1.634367] usbcore: registered new interface driver usb-storage
10550 12:15:00.738992 <6>[ 1.640818] usbcore: registered new device driver onboard-usb-hub
10551 12:15:00.748052 <6>[ 1.649966] mt6397-rtc mt6359-rtc: registered as rtc0
10552 12:15:00.757552 <6>[ 1.655443] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-31T12:12:17 UTC (1706703137)
10553 12:15:00.761094 <6>[ 1.665028] i2c_dev: i2c /dev entries driver
10554 12:15:00.777653 <6>[ 1.676782] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10555 12:15:00.798359 <6>[ 1.700774] cpu cpu0: EM: created perf domain
10556 12:15:00.801700 <6>[ 1.705702] cpu cpu4: EM: created perf domain
10557 12:15:00.809189 <6>[ 1.711279] sdhci: Secure Digital Host Controller Interface driver
10558 12:15:00.815276 <6>[ 1.717712] sdhci: Copyright(c) Pierre Ossman
10559 12:15:00.822070 <6>[ 1.722669] Synopsys Designware Multimedia Card Interface Driver
10560 12:15:00.828521 <6>[ 1.729304] sdhci-pltfm: SDHCI platform and OF driver helper
10561 12:15:00.832376 <6>[ 1.729343] mmc0: CQHCI version 5.10
10562 12:15:00.838549 <6>[ 1.739253] ledtrig-cpu: registered to indicate activity on CPUs
10563 12:15:00.845776 <6>[ 1.746223] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10564 12:15:00.852137 <6>[ 1.753278] usbcore: registered new interface driver usbhid
10565 12:15:00.855557 <6>[ 1.759099] usbhid: USB HID core driver
10566 12:15:00.861939 <6>[ 1.763302] spi_master spi0: will run message pump with realtime priority
10567 12:15:00.905738 <6>[ 1.801610] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10568 12:15:00.925032 <6>[ 1.817679] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10569 12:15:00.928797 <6>[ 1.831297] mmc0: Command Queue Engine enabled
10570 12:15:00.935309 <6>[ 1.836113] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10571 12:15:00.941986 <6>[ 1.843407] mmcblk0: mmc0:0001 DA4128 116 GiB
10572 12:15:00.945221 <6>[ 1.848307] cros-ec-spi spi0.0: Chrome EC device registered
10573 12:15:00.951362 <6>[ 1.852264] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10574 12:15:00.959828 <6>[ 1.861972] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10575 12:15:00.966041 <6>[ 1.867918] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10576 12:15:00.972644 <6>[ 1.874083] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10577 12:15:00.992044 <6>[ 1.891158] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10578 12:15:00.999659 <6>[ 1.902139] NET: Registered PF_PACKET protocol family
10579 12:15:01.003001 <6>[ 1.907545] 9pnet: Installing 9P2000 support
10580 12:15:01.009604 <5>[ 1.912117] Key type dns_resolver registered
10581 12:15:01.013149 <6>[ 1.917138] registered taskstats version 1
10582 12:15:01.019589 <5>[ 1.921529] Loading compiled-in X.509 certificates
10583 12:15:01.049423 <4>[ 1.945332] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10584 12:15:01.059470 <4>[ 1.956063] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10585 12:15:01.066214 <3>[ 1.966605] debugfs: File 'uA_load' in directory '/' already present!
10586 12:15:01.072841 <3>[ 1.973310] debugfs: File 'min_uV' in directory '/' already present!
10587 12:15:01.079178 <3>[ 1.979917] debugfs: File 'max_uV' in directory '/' already present!
10588 12:15:01.086046 <3>[ 1.986523] debugfs: File 'constraint_flags' in directory '/' already present!
10589 12:15:01.096981 <3>[ 1.996298] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10590 12:15:01.109310 <6>[ 2.012032] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10591 12:15:01.116380 <6>[ 2.018801] xhci-mtk 11200000.usb: xHCI Host Controller
10592 12:15:01.123406 <6>[ 2.024340] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10593 12:15:01.133549 <6>[ 2.032289] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10594 12:15:01.140079 <6>[ 2.041722] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10595 12:15:01.146474 <6>[ 2.047808] xhci-mtk 11200000.usb: xHCI Host Controller
10596 12:15:01.153044 <6>[ 2.053287] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10597 12:15:01.159521 <6>[ 2.060937] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10598 12:15:01.166280 <6>[ 2.068748] hub 1-0:1.0: USB hub found
10599 12:15:01.169752 <6>[ 2.072777] hub 1-0:1.0: 1 port detected
10600 12:15:01.176147 <6>[ 2.077083] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10601 12:15:01.183244 <6>[ 2.085811] hub 2-0:1.0: USB hub found
10602 12:15:01.186670 <6>[ 2.089837] hub 2-0:1.0: 1 port detected
10603 12:15:01.194071 <6>[ 2.096757] mtk-msdc 11f70000.mmc: Got CD GPIO
10604 12:15:01.207176 <6>[ 2.106787] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10605 12:15:01.214201 <6>[ 2.114811] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10606 12:15:01.223966 <4>[ 2.122748] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10607 12:15:01.234240 <6>[ 2.132280] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10608 12:15:01.241038 <6>[ 2.140356] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10609 12:15:01.247401 <6>[ 2.148376] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10610 12:15:01.257576 <6>[ 2.156291] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10611 12:15:01.264016 <6>[ 2.164108] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10612 12:15:01.274161 <6>[ 2.171924] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10613 12:15:01.284244 <6>[ 2.182324] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10614 12:15:01.290978 <6>[ 2.190684] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10615 12:15:01.300449 <6>[ 2.199034] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10616 12:15:01.307126 <6>[ 2.207374] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10617 12:15:01.317584 <6>[ 2.215715] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10618 12:15:01.324387 <6>[ 2.224055] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10619 12:15:01.334532 <6>[ 2.232394] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10620 12:15:01.341161 <6>[ 2.240733] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10621 12:15:01.351093 <6>[ 2.249071] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10622 12:15:01.357637 <6>[ 2.257416] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10623 12:15:01.367566 <6>[ 2.265758] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10624 12:15:01.373970 <6>[ 2.274096] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10625 12:15:01.384208 <6>[ 2.282434] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10626 12:15:01.390458 <6>[ 2.290785] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10627 12:15:01.400439 <6>[ 2.299125] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10628 12:15:01.407172 <6>[ 2.307867] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10629 12:15:01.413694 <6>[ 2.315026] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10630 12:15:01.420548 <6>[ 2.321781] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10631 12:15:01.427330 <6>[ 2.328532] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10632 12:15:01.433639 <6>[ 2.335468] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10633 12:15:01.444118 <6>[ 2.342325] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10634 12:15:01.453345 <6>[ 2.351454] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10635 12:15:01.463478 <6>[ 2.360573] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10636 12:15:01.474011 <6>[ 2.369866] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10637 12:15:01.479750 <6>[ 2.379332] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10638 12:15:01.489673 <6>[ 2.388799] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10639 12:15:01.499847 <6>[ 2.397918] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10640 12:15:01.509531 <6>[ 2.407385] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10641 12:15:01.519952 <6>[ 2.416503] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10642 12:15:01.529521 <6>[ 2.425796] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10643 12:15:01.539577 <6>[ 2.435956] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10644 12:15:01.549132 <6>[ 2.447589] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10645 12:15:01.555728 <6>[ 2.457287] Trying to probe devices needed for running init ...
10646 12:15:01.595791 <6>[ 2.494899] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10647 12:15:01.750450 <6>[ 2.652761] hub 1-1:1.0: USB hub found
10648 12:15:01.753649 <6>[ 2.657288] hub 1-1:1.0: 4 ports detected
10649 12:15:01.763252 <6>[ 2.665838] hub 1-1:1.0: USB hub found
10650 12:15:01.766609 <6>[ 2.670187] hub 1-1:1.0: 4 ports detected
10651 12:15:01.876120 <6>[ 2.775252] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10652 12:15:01.901934 <6>[ 2.804675] hub 2-1:1.0: USB hub found
10653 12:15:01.905898 <6>[ 2.809172] hub 2-1:1.0: 3 ports detected
10654 12:15:01.914726 <6>[ 2.817310] hub 2-1:1.0: USB hub found
10655 12:15:01.917886 <6>[ 2.821794] hub 2-1:1.0: 3 ports detected
10656 12:15:02.091431 <6>[ 2.990945] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10657 12:15:02.223685 <6>[ 3.126324] hub 1-1.4:1.0: USB hub found
10658 12:15:02.226858 <6>[ 3.130916] hub 1-1.4:1.0: 2 ports detected
10659 12:15:02.235890 <6>[ 3.138332] hub 1-1.4:1.0: USB hub found
10660 12:15:02.238766 <6>[ 3.142932] hub 1-1.4:1.0: 2 ports detected
10661 12:15:02.303423 <6>[ 3.203143] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10662 12:15:02.535577 <6>[ 3.434935] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10663 12:15:02.727261 <6>[ 3.626921] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10664 12:15:13.829091 <6>[ 14.735904] ALSA device list:
10665 12:15:13.835482 <6>[ 14.739195] No soundcards found.
10666 12:15:13.843980 <6>[ 14.747180] Freeing unused kernel memory: 8448K
10667 12:15:13.847093 <6>[ 14.752196] Run /init as init process
10668 12:15:13.858223 Loading, please wait...
10669 12:15:13.879545 Starting version 247.3-7+deb11u2
10670 12:15:14.069778 <6>[ 14.969457] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10671 12:15:14.080832 <6>[ 14.980502] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10672 12:15:14.086956 <6>[ 14.988222] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10673 12:15:14.093543 <6>[ 14.992407] remoteproc remoteproc0: scp is available
10674 12:15:14.104069 <6>[ 14.996996] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10675 12:15:14.106876 <6>[ 15.002379] remoteproc remoteproc0: powering up scp
10676 12:15:14.116641 <3>[ 15.002867] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10677 12:15:14.124109 <3>[ 15.002881] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10678 12:15:14.129868 <3>[ 15.002887] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 12:15:14.140036 <3>[ 15.016944] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 12:15:14.147462 <6>[ 15.024088] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10681 12:15:14.153932 <6>[ 15.024106] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10682 12:15:14.163868 <3>[ 15.032184] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 12:15:14.170446 <3>[ 15.070562] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10684 12:15:14.173662 <6>[ 15.073155] mc: Linux media interface: v0.10
10685 12:15:14.184258 <4>[ 15.074207] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10686 12:15:14.187045 <6>[ 15.075204] usbcore: registered new device driver r8152-cfgselector
10687 12:15:14.196867 <4>[ 15.077946] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10688 12:15:14.203996 <3>[ 15.078663] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 12:15:14.213537 <3>[ 15.078669] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 12:15:14.220015 <3>[ 15.089015] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 12:15:14.226354 <6>[ 15.105023] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10692 12:15:14.236987 <3>[ 15.137032] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10693 12:15:14.243858 <3>[ 15.145374] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10694 12:15:14.253935 <6>[ 15.148134] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10695 12:15:14.260663 <3>[ 15.153846] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10696 12:15:14.267391 <3>[ 15.160112] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 12:15:14.274038 <6>[ 15.161190] pci_bus 0000:00: root bus resource [bus 00-ff]
10698 12:15:14.284394 <3>[ 15.169050] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10699 12:15:14.290559 <3>[ 15.169054] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10700 12:15:14.300625 <3>[ 15.169060] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 12:15:14.307442 <3>[ 15.169064] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10702 12:15:14.314069 <3>[ 15.169097] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10703 12:15:14.320147 <6>[ 15.169715] videodev: Linux video capture interface: v2.00
10704 12:15:14.330339 <6>[ 15.177234] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10705 12:15:14.337058 <6>[ 15.177237] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10706 12:15:14.343762 <6>[ 15.177538] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10707 12:15:14.353495 <6>[ 15.177546] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10708 12:15:14.360113 <6>[ 15.177591] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10709 12:15:14.367228 <6>[ 15.177614] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10710 12:15:14.370395 <6>[ 15.177747] pci 0000:00:00.0: supports D1 D2
10711 12:15:14.380454 <6>[ 15.177750] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10712 12:15:14.386974 <6>[ 15.179590] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10713 12:15:14.393589 <6>[ 15.179746] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10714 12:15:14.400453 <6>[ 15.179780] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10715 12:15:14.406762 <6>[ 15.179808] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10716 12:15:14.417226 <6>[ 15.179826] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10717 12:15:14.420781 <6>[ 15.179946] pci 0000:01:00.0: supports D1 D2
10718 12:15:14.427359 <6>[ 15.179950] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10719 12:15:14.438228 <6>[ 15.189243] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10720 12:15:14.441367 <6>[ 15.191150] remoteproc remoteproc0: remote processor scp is now up
10721 12:15:14.448605 <6>[ 15.191183] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10722 12:15:14.457859 <6>[ 15.191218] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10723 12:15:14.464820 <6>[ 15.191223] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10724 12:15:14.474533 <6>[ 15.191231] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10725 12:15:14.481173 <6>[ 15.191244] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10726 12:15:14.491257 <6>[ 15.191256] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10727 12:15:14.494711 <6>[ 15.191268] pci 0000:00:00.0: PCI bridge to [bus 01]
10728 12:15:14.504586 <6>[ 15.191273] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10729 12:15:14.507651 <6>[ 15.191405] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10730 12:15:14.514385 <6>[ 15.191888] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10731 12:15:14.520781 <6>[ 15.192292] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10732 12:15:14.530824 <6>[ 15.200702] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10733 12:15:14.541140 <6>[ 15.207895] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10734 12:15:14.547487 <6>[ 15.268208] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10735 12:15:14.557454 <6>[ 15.278179] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10736 12:15:14.564112 <6>[ 15.280378] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10737 12:15:14.573919 <4>[ 15.292824] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10738 12:15:14.578008 <4>[ 15.292824] Fallback method does not support PEC.
10739 12:15:14.587345 <4>[ 15.308398] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10740 12:15:14.597680 <5>[ 15.319763] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10741 12:15:14.604002 <4>[ 15.324330] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10742 12:15:14.613773 <3>[ 15.327139] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10743 12:15:14.617757 <6>[ 15.342022] Bluetooth: Core ver 2.22
10744 12:15:14.623892 <3>[ 15.350095] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10745 12:15:14.630446 <6>[ 15.351380] NET: Registered PF_BLUETOOTH protocol family
10746 12:15:14.637090 <6>[ 15.374649] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10747 12:15:14.643637 <5>[ 15.375068] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10748 12:15:14.653638 <5>[ 15.375397] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10749 12:15:14.660104 <4>[ 15.375465] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10750 12:15:14.667095 <6>[ 15.375472] cfg80211: failed to load regulatory.db
10751 12:15:14.673973 <6>[ 15.382231] Bluetooth: HCI device and connection manager initialized
10752 12:15:14.680736 <6>[ 15.384485] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10753 12:15:14.693403 <6>[ 15.392019] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10754 12:15:14.697025 <6>[ 15.394752] r8152 2-1.3:1.0 eth0: v1.12.13
10755 12:15:14.703483 <6>[ 15.394820] usbcore: registered new interface driver r8152
10756 12:15:14.706718 <6>[ 15.398324] Bluetooth: HCI socket layer initialized
10757 12:15:14.713636 <6>[ 15.403622] usbcore: registered new interface driver uvcvideo
10758 12:15:14.719990 <6>[ 15.411430] Bluetooth: L2CAP socket layer initialized
10759 12:15:14.726968 <6>[ 15.411796] usbcore: registered new interface driver cdc_ether
10760 12:15:14.730693 <6>[ 15.417942] usbcore: registered new interface driver r8153_ecm
10761 12:15:14.736892 <6>[ 15.423874] Bluetooth: SCO socket layer initialized
10762 12:15:14.743609 <6>[ 15.437921] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10763 12:15:14.750132 <6>[ 15.483516] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10764 12:15:14.756344 <6>[ 15.521866] usbcore: registered new interface driver btusb
10765 12:15:14.766386 <4>[ 15.522506] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10766 12:15:14.773235 <3>[ 15.522512] Bluetooth: hci0: Failed to load firmware file (-2)
10767 12:15:14.776254 <3>[ 15.522514] Bluetooth: hci0: Failed to set up firmware (-2)
10768 12:15:14.789537 <4>[ 15.522516] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10769 12:15:14.793271 <6>[ 15.525163] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10770 12:15:14.820507 <6>[ 15.723438] mt7921e 0000:01:00.0: ASIC revision: 79610010
10771 12:15:14.922497 <6>[ 15.822329] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10772 12:15:14.925353 <6>[ 15.822329]
10773 12:15:14.941277 Begin: Loading essential drivers ... done.
10774 12:15:14.944483 Begin: Running /scripts/init-premount ... done.
10775 12:15:14.951151 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10776 12:15:14.961167 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10777 12:15:14.964494 Device /sys/class/net/enx00e04c787aaa found
10778 12:15:14.965072 done.
10779 12:15:15.022559 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10780 12:15:15.192031 <6>[ 16.092132] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10781 12:15:16.037459 <6>[ 16.941306] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10782 12:15:16.081500 <6>[ 16.985548] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10783 12:15:16.252222 IP-Config: no response after 2 secs - giving up
10784 12:15:16.287512 IP-Config: wlp1s0 hardware address d8:f3:bc:78:17:6f mtu 1500 DHCP
10785 12:15:17.010804 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10786 12:15:17.013893 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10787 12:15:17.020335 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10788 12:15:17.030563 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10789 12:15:17.037016 host : mt8192-asurada-spherion-r0-cbg-0
10790 12:15:17.040454 domain : lava-rack
10791 12:15:17.047101 rootserver: 192.168.201.1 rootpath:
10792 12:15:17.047682 filename :
10793 12:15:17.217870 done.
10794 12:15:17.224732 Begin: Running /scripts/nfs-bottom ... done.
10795 12:15:17.244276 Begin: Running /scripts/init-bottom ... done.
10796 12:15:18.408407 <6>[ 19.312744] NET: Registered PF_INET6 protocol family
10797 12:15:18.415921 <6>[ 19.320164] Segment Routing with IPv6
10798 12:15:18.419330 <6>[ 19.324125] In-situ OAM (IOAM) with IPv6
10799 12:15:18.552456 <30>[ 19.439873] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10800 12:15:18.560394 <30>[ 19.464274] systemd[1]: Detected architecture arm64.
10801 12:15:18.581490
10802 12:15:18.584457 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10803 12:15:18.584983
10804 12:15:18.601796 <30>[ 19.505762] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10805 12:15:19.437151 <30>[ 20.337860] systemd[1]: Queued start job for default target Graphical Interface.
10806 12:15:19.469415 <30>[ 20.373278] systemd[1]: Created slice system-getty.slice.
10807 12:15:19.476422 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10808 12:15:19.492026 <30>[ 20.396250] systemd[1]: Created slice system-modprobe.slice.
10809 12:15:19.499222 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10810 12:15:19.516037 <30>[ 20.420136] systemd[1]: Created slice system-serial\x2dgetty.slice.
10811 12:15:19.526287 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10812 12:15:19.539747 <30>[ 20.444000] systemd[1]: Created slice User and Session Slice.
10813 12:15:19.546485 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10814 12:15:19.567719 <30>[ 20.467744] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10815 12:15:19.577021 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10816 12:15:19.595694 <30>[ 20.495714] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10817 12:15:19.601607 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10818 12:15:19.625670 <30>[ 20.523052] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10819 12:15:19.632464 <30>[ 20.535230] systemd[1]: Reached target Local Encrypted Volumes.
10820 12:15:19.639008 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10821 12:15:19.655325 <30>[ 20.559497] systemd[1]: Reached target Paths.
10822 12:15:19.662394 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10823 12:15:19.675081 <30>[ 20.578903] systemd[1]: Reached target Remote File Systems.
10824 12:15:19.681189 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10825 12:15:19.699060 <30>[ 20.602872] systemd[1]: Reached target Slices.
10826 12:15:19.705344 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10827 12:15:19.718768 <30>[ 20.622920] systemd[1]: Reached target Swap.
10828 12:15:19.722179 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10829 12:15:19.742802 <30>[ 20.643388] systemd[1]: Listening on initctl Compatibility Named Pipe.
10830 12:15:19.749154 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10831 12:15:19.755703 <30>[ 20.659610] systemd[1]: Listening on Journal Audit Socket.
10832 12:15:19.762709 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10833 12:15:19.780676 <30>[ 20.684303] systemd[1]: Listening on Journal Socket (/dev/log).
10834 12:15:19.786760 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10835 12:15:19.803864 <30>[ 20.707470] systemd[1]: Listening on Journal Socket.
10836 12:15:19.810025 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10837 12:15:19.827973 <30>[ 20.728429] systemd[1]: Listening on Network Service Netlink Socket.
10838 12:15:19.834624 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10839 12:15:19.850012 <30>[ 20.753871] systemd[1]: Listening on udev Control Socket.
10840 12:15:19.856359 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10841 12:15:19.871395 <30>[ 20.775351] systemd[1]: Listening on udev Kernel Socket.
10842 12:15:19.877907 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10843 12:15:19.934887 <30>[ 20.839078] systemd[1]: Mounting Huge Pages File System...
10844 12:15:19.941490 Mounting [0;1;39mHuge Pages File System[0m...
10845 12:15:19.959420 <30>[ 20.863658] systemd[1]: Mounting POSIX Message Queue File System...
10846 12:15:19.966443 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10847 12:15:19.987832 <30>[ 20.891967] systemd[1]: Mounting Kernel Debug File System...
10848 12:15:19.994763 Mounting [0;1;39mKernel Debug File System[0m...
10849 12:15:20.011134 <30>[ 20.911814] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10850 12:15:20.032263 <30>[ 20.933454] systemd[1]: Starting Create list of static device nodes for the current kernel...
10851 12:15:20.042344 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10852 12:15:20.058893 <30>[ 20.963272] systemd[1]: Starting Load Kernel Module configfs...
10853 12:15:20.065573 Starting [0;1;39mLoad Kernel Module configfs[0m...
10854 12:15:20.082599 <30>[ 20.986862] systemd[1]: Starting Load Kernel Module drm...
10855 12:15:20.089433 Starting [0;1;39mLoad Kernel Module drm[0m...
10856 12:15:20.107438 <30>[ 21.011774] systemd[1]: Starting Load Kernel Module fuse...
10857 12:15:20.114266 Starting [0;1;39mLoad Kernel Module fuse[0m...
10858 12:15:20.144439 <6>[ 21.048146] fuse: init (API version 7.37)
10859 12:15:20.153691 <30>[ 21.049730] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10860 12:15:20.191396 <30>[ 21.095412] systemd[1]: Starting Journal Service...
10861 12:15:20.197783 Starting [0;1;39mJournal Service[0m...
10862 12:15:20.218093 <30>[ 21.122428] systemd[1]: Starting Load Kernel Modules...
10863 12:15:20.225120 Starting [0;1;39mLoad Kernel Modules[0m...
10864 12:15:20.245486 <30>[ 21.146471] systemd[1]: Starting Remount Root and Kernel File Systems...
10865 12:15:20.252433 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10866 12:15:20.272339 <30>[ 21.176589] systemd[1]: Starting Coldplug All udev Devices...
10867 12:15:20.279337 Starting [0;1;39mColdplug All udev Devices[0m...
10868 12:15:20.300790 <30>[ 21.204764] systemd[1]: Mounted Huge Pages File System.
10869 12:15:20.306985 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10870 12:15:20.323436 <30>[ 21.227503] systemd[1]: Mounted POSIX Message Queue File System.
10871 12:15:20.329715 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10872 12:15:20.346998 <30>[ 21.251441] systemd[1]: Mounted Kernel Debug File System.
10873 12:15:20.354421 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10874 12:15:20.364227 <3>[ 21.265024] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 12:15:20.375020 <30>[ 21.275804] systemd[1]: Finished Create list of static device nodes for the current kernel.
10876 12:15:20.384909 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10877 12:15:20.391543 <3>[ 21.294068] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10878 12:15:20.400226 <30>[ 21.304371] systemd[1]: modprobe@configfs.service: Succeeded.
10879 12:15:20.423321 <30>[ 21.327405] systemd[1]: Finished Load Kernel Module configfs.
10880 12:15:20.433264 <3>[ 21.333120] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 12:15:20.440233 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10882 12:15:20.459618 <30>[ 21.363598] systemd[1]: modprobe@drm.service: Succeeded.
10883 12:15:20.469452 <3>[ 21.363657] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10884 12:15:20.476278 <30>[ 21.370571] systemd[1]: Finished Load Kernel Module drm.
10885 12:15:20.479475 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10886 12:15:20.496971 <30>[ 21.400442] systemd[1]: modprobe@fuse.service: Succeeded.
10887 12:15:20.507385 <3>[ 21.403634] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10888 12:15:20.510095 <30>[ 21.407534] systemd[1]: Finished Load Kernel Module fuse.
10889 12:15:20.517401 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10890 12:15:20.533322 <30>[ 21.436754] systemd[1]: Finished Load Kernel Modules.
10891 12:15:20.543412 <3>[ 21.440368] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 12:15:20.546449 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10893 12:15:20.565622 <30>[ 21.469002] systemd[1]: Finished Remount Root and Kernel File Systems.
10894 12:15:20.575749 <3>[ 21.475185] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 12:15:20.582154 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10896 12:15:20.607497 <3>[ 21.508136] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 12:15:20.633755 <30>[ 21.537405] systemd[1]: Mounting FUSE Control File System...
10898 12:15:20.643437 <3>[ 21.539964] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 12:15:20.650004 Mounting [0;1;39mFUSE Control File System[0m...
10900 12:15:20.665989 <30>[ 21.569932] systemd[1]: Mounting Kernel Configuration File System...
10901 12:15:20.676082 <3>[ 21.573674] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 12:15:20.682018 Mounting [0;1;39mKernel Configuration File System[0m...
10903 12:15:20.707376 <30>[ 21.608700] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10904 12:15:20.717365 <30>[ 21.618012] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10905 12:15:20.779893 <30>[ 21.683695] systemd[1]: Starting Load/Save Random Seed...
10906 12:15:20.786367 Starting [0;1;39mLoad/Save Random Seed[0m...
10907 12:15:20.810677 <4>[ 21.704715] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10908 12:15:20.817112 <30>[ 21.706025] systemd[1]: Starting Apply Kernel Variables...
10909 12:15:20.824231 <3>[ 21.720439] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10910 12:15:20.830740 Starting [0;1;39mApply Kernel Variables[0m...
10911 12:15:20.847196 <30>[ 21.751323] systemd[1]: Starting Create System Users...
10912 12:15:20.853513 Starting [0;1;39mCreate System Users[0m...
10913 12:15:20.869943 <30>[ 21.773993] systemd[1]: Started Journal Service.
10914 12:15:20.876428 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10915 12:15:20.900560 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10916 12:15:20.914543 See 'systemctl status systemd-udev-trigger.service' for details.
10917 12:15:20.931030 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10918 12:15:20.946975 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10919 12:15:20.964412 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10920 12:15:20.980644 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10921 12:15:20.989049 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10922 12:15:21.031568 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10923 12:15:21.050985 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10924 12:15:21.086329 <46>[ 21.987085] systemd-journald[306]: Received client request to flush runtime journal.
10925 12:15:22.129659 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10926 12:15:22.142870 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10927 12:15:22.158346 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10928 12:15:22.218257 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10929 12:15:22.498341 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10930 12:15:22.543385 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10931 12:15:22.608764 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10932 12:15:22.661460 Starting [0;1;39mNetwork Service[0m...
10933 12:15:22.853944 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10934 12:15:23.088458 Starting [0;1;39mNetwork Time Synchronization[0m...
10935 12:15:23.125915 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10936 12:15:23.244821 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10937 12:15:23.376999 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10938 12:15:23.391439 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10939 12:15:23.459219 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10940 12:15:23.474804 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10941 12:15:23.494064 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10942 12:15:23.534059 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10943 12:15:23.570305 Starting [0;1;39mNetwork Name Resolution[0m...
10944 12:15:23.588215 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10945 12:15:23.607931 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10946 12:15:23.623930 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10947 12:15:23.641840 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10948 12:15:23.654809 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10949 12:15:23.670703 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10950 12:15:23.695160 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10951 12:15:23.720700 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10952 12:15:23.752121 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10953 12:15:23.792431 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10954 12:15:23.805969 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10955 12:15:23.829359 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10956 12:15:23.841984 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10957 12:15:23.858548 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10958 12:15:23.923050 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10959 12:15:24.067186 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10960 12:15:24.166793 Starting [0;1;39mUser Login Management[0m...
10961 12:15:24.187753 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10962 12:15:24.242673 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10963 12:15:24.259319 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10964 12:15:24.277832 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10965 12:15:24.318859 Starting [0;1;39mPermit User Sessions[0m...
10966 12:15:24.379529 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10967 12:15:24.481283 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10968 12:15:24.539754 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10969 12:15:24.591216 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10970 12:15:24.607332 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10971 12:15:24.629758 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10972 12:15:24.645233 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10973 12:15:24.667627 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10974 12:15:24.682834 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10975 12:15:24.740369 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10976 12:15:24.809905 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10977 12:15:24.860219
10978 12:15:24.860864
10979 12:15:24.863163 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10980 12:15:24.863640
10981 12:15:24.866520 debian-bullseye-arm64 login: root (automatic login)
10982 12:15:24.867050
10983 12:15:24.867550
10984 12:15:25.173190 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024 aarch64
10985 12:15:25.173344
10986 12:15:25.179924 The programs included with the Debian GNU/Linux system are free software;
10987 12:15:25.186279 the exact distribution terms for each program are described in the
10988 12:15:25.189965 individual files in /usr/share/doc/*/copyright.
10989 12:15:25.190091
10990 12:15:25.196366 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10991 12:15:25.199662 permitted by applicable law.
10992 12:15:25.276546 Matched prompt #10: / #
10994 12:15:25.276804 Setting prompt string to ['/ #']
10995 12:15:25.276906 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10997 12:15:25.277116 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10998 12:15:25.277209 start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
10999 12:15:25.277284 Setting prompt string to ['/ #']
11000 12:15:25.277349 Forcing a shell prompt, looking for ['/ #']
11002 12:15:25.327753 / #
11003 12:15:25.328254 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11004 12:15:25.328616 Waiting using forced prompt support (timeout 00:02:30)
11005 12:15:25.333918
11006 12:15:25.334657 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11007 12:15:25.335098 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
11009 12:15:25.436204 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12669535/extract-nfsrootfs-gf8v15sn'
11010 12:15:25.442693 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12669535/extract-nfsrootfs-gf8v15sn'
11012 12:15:25.544083 / # export NFS_SERVER_IP='192.168.201.1'
11013 12:15:25.550018 export NFS_SERVER_IP='192.168.201.1'
11014 12:15:25.550628 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11015 12:15:25.550979 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
11016 12:15:25.551349 end: 2 depthcharge-action (duration 00:01:26) [common]
11017 12:15:25.551799 start: 3 lava-test-retry (timeout 00:01:00) [common]
11018 12:15:25.552119 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11019 12:15:25.552405 Using namespace: common
11021 12:15:25.653132 / # #
11022 12:15:25.653370 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11023 12:15:25.658897 #
11024 12:15:25.659259 Using /lava-12669535
11026 12:15:25.759722 / # export SHELL=/bin/sh
11027 12:15:25.765508 export SHELL=/bin/sh
11029 12:15:25.866328 / # . /lava-12669535/environment
11030 12:15:25.872142 . /lava-12669535/environment
11032 12:15:25.979575 / # /lava-12669535/bin/lava-test-runner /lava-12669535/0
11033 12:15:25.980108 Test shell timeout: 10s (minimum of the action and connection timeout)
11034 12:15:25.985608 /lava-12669535/bin/lava-test-runner /lava-12669535/0
11035 12:15:26.214429 + export TESTRUN_ID=0_dmesg
11036 12:15:26.217477 + cd /lava-12669535/0/tests/0_dmesg
11037 12:15:26.220678 + cat uuid
11038 12:15:26.231633 + UUID=12669535_<8>[ 27.133147] <LAVA_SIGNAL_STARTRUN 0_dmesg 12669535_1.6.2.3.1>
11039 12:15:26.231778 1.6.2.3.1
11040 12:15:26.231851 + set +x
11041 12:15:26.232128 Received signal: <STARTRUN> 0_dmesg 12669535_1.6.2.3.1
11042 12:15:26.232209 Starting test lava.0_dmesg (12669535_1.6.2.3.1)
11043 12:15:26.232314 Skipping test definition patterns.
11044 12:15:26.237638 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11045 12:15:26.313012 <8>[ 27.214763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11046 12:15:26.313718 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11048 12:15:26.386311 <8>[ 27.288258] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11049 12:15:26.387016 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11051 12:15:26.458507 <8>[ 27.360174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11052 12:15:26.459247 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11054 12:15:26.462523 + set +x
11055 12:15:26.465044 <8>[ 27.369757] <LAVA_SIGNAL_ENDRUN 0_dmesg 12669535_1.6.2.3.1>
11056 12:15:26.465825 Received signal: <ENDRUN> 0_dmesg 12669535_1.6.2.3.1
11057 12:15:26.466306 Ending use of test pattern.
11058 12:15:26.466645 Ending test lava.0_dmesg (12669535_1.6.2.3.1), duration 0.23
11060 12:15:26.472008 <LAVA_TEST_RUNNER EXIT>
11061 12:15:26.472752 ok: lava_test_shell seems to have completed
11062 12:15:26.473290 alert: pass
crit: pass
emerg: pass
11063 12:15:26.473702 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11064 12:15:26.474121 end: 3 lava-test-retry (duration 00:00:01) [common]
11065 12:15:26.474540 start: 4 lava-test-retry (timeout 00:01:00) [common]
11066 12:15:26.474957 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11067 12:15:26.475286 Using namespace: common
11069 12:15:26.576475 / # #
11070 12:15:26.577124 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11071 12:15:26.577734 Using /lava-12669535
11073 12:15:26.678887 export SHELL=/bin/sh
11074 12:15:26.679690 #
11076 12:15:26.781369 / # export SHELL=/bin/sh. /lava-12669535/environment
11077 12:15:26.782182
11079 12:15:26.884093 / # . /lava-12669535/environment/lava-12669535/bin/lava-test-runner /lava-12669535/1
11080 12:15:26.884792 Test shell timeout: 10s (minimum of the action and connection timeout)
11081 12:15:26.885545
11082 12:15:26.890339 / # /lava-12669535/bin/lava-test-runner /lava-12669535/1
11083 12:15:26.992668 + export TESTRUN_ID=1_bootrr
11084 12:15:26.996097 + cd /lava-12669535/1/tests/1_bootrr
11085 12:15:26.999572 + cat uuid
11086 12:15:27.009441 + UUID=12669535_1.<8>[ 27.911028] <LAVA_SIGNAL_STARTRUN 1_bootrr 12669535_1.6.2.3.5>
11087 12:15:27.009540 6.2.3.5
11088 12:15:27.009617 + set +x
11089 12:15:27.009868 Received signal: <STARTRUN> 1_bootrr 12669535_1.6.2.3.5
11090 12:15:27.009946 Starting test lava.1_bootrr (12669535_1.6.2.3.5)
11091 12:15:27.010047 Skipping test definition patterns.
11092 12:15:27.022500 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-12669535/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11093 12:15:27.025846 + cd /opt/bootrr/libexec/bootrr
11094 12:15:27.025971 + sh helpers/bootrr-auto
11095 12:15:27.074657 /lava-12669535/1/../bin/lava-test-case
11096 12:15:27.102770 <8>[ 28.004651] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11097 12:15:27.103141 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11099 12:15:27.137635 /lava-12669535/1/../bin/lava-test-case
11100 12:15:27.160654 <8>[ 28.062487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11101 12:15:27.161439 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11103 12:15:27.185439 /lava-12669535/1/../bin/lava-test-case
11104 12:15:27.212681 <8>[ 28.114095] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11105 12:15:27.213512 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11107 12:15:27.257980 /lava-12669535/1/../bin/lava-test-case
11108 12:15:27.279109 <8>[ 28.180914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11109 12:15:27.279914 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11111 12:15:27.321693 /lava-12669535/1/../bin/lava-test-case
11112 12:15:27.345497 <8>[ 28.247146] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11113 12:15:27.346427 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11115 12:15:27.380663 /lava-12669535/1/../bin/lava-test-case
11116 12:15:27.410796 <8>[ 28.312130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11117 12:15:27.411507 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11119 12:15:27.448343 /lava-12669535/1/../bin/lava-test-case
11120 12:15:27.480879 <8>[ 28.382269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11121 12:15:27.481592 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11123 12:15:27.519766 /lava-12669535/1/../bin/lava-test-case
11124 12:15:27.552791 <8>[ 28.454184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11125 12:15:27.553605 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11127 12:15:27.577858 /lava-12669535/1/../bin/lava-test-case
11128 12:15:27.609677 <8>[ 28.511547] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11129 12:15:27.610366 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11131 12:15:27.655562 /lava-12669535/1/../bin/lava-test-case
11132 12:15:27.688164 <8>[ 28.590270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11133 12:15:27.688959 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11135 12:15:27.711239 /lava-12669535/1/../bin/lava-test-case
11136 12:15:27.742360 <8>[ 28.644020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11137 12:15:27.743169 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11139 12:15:27.781474 /lava-12669535/1/../bin/lava-test-case
11140 12:15:27.808800 <8>[ 28.710501] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11141 12:15:27.809491 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11143 12:15:27.863100 /lava-12669535/1/../bin/lava-test-case
11144 12:15:27.888940 <8>[ 28.790691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11145 12:15:27.889648 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11147 12:15:27.925785 /lava-12669535/1/../bin/lava-test-case
11148 12:15:27.954556 <8>[ 28.856511] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11149 12:15:27.955009 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11151 12:15:27.999938 /lava-12669535/1/../bin/lava-test-case
11152 12:15:28.029650 <8>[ 28.931979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11153 12:15:28.030022 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11155 12:15:28.056171 /lava-12669535/1/../bin/lava-test-case
11156 12:15:28.081261 <8>[ 28.983143] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11157 12:15:28.081647 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11159 12:15:28.112173 /lava-12669535/1/../bin/lava-test-case
11160 12:15:28.135737 <8>[ 29.037598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11161 12:15:28.136398 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11163 12:15:28.158769 /lava-12669535/1/../bin/lava-test-case
11164 12:15:28.185766 <8>[ 29.087560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11165 12:15:28.186465 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11167 12:15:28.221997 /lava-12669535/1/../bin/lava-test-case
11168 12:15:28.247527 <8>[ 29.149309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11169 12:15:28.248348 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11171 12:15:28.271770 /lava-12669535/1/../bin/lava-test-case
11172 12:15:28.300749 <8>[ 29.202528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11173 12:15:28.301573 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11175 12:15:28.343740 /lava-12669535/1/../bin/lava-test-case
11176 12:15:28.376468 <8>[ 29.278186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11177 12:15:28.377232 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11179 12:15:28.400691 /lava-12669535/1/../bin/lava-test-case
11180 12:15:28.430162 <8>[ 29.331786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11181 12:15:28.430994 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11183 12:15:28.467949 /lava-12669535/1/../bin/lava-test-case
11184 12:15:28.499874 <8>[ 29.401675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11185 12:15:28.500687 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11187 12:15:28.523891 /lava-12669535/1/../bin/lava-test-case
11188 12:15:28.551859 <8>[ 29.453476] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11189 12:15:28.552609 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11191 12:15:28.583241 /lava-12669535/1/../bin/lava-test-case
11192 12:15:28.608628 <8>[ 29.511069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11193 12:15:28.608987 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11195 12:15:28.641740 /lava-12669535/1/../bin/lava-test-case
11196 12:15:28.668253 <8>[ 29.570227] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11197 12:15:28.668639 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11199 12:15:28.699308 /lava-12669535/1/../bin/lava-test-case
11200 12:15:28.725738 <8>[ 29.628038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11201 12:15:28.726016 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11203 12:15:28.758982 /lava-12669535/1/../bin/lava-test-case
11204 12:15:28.787638 <8>[ 29.689834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11205 12:15:28.788379 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11207 12:15:28.808828 /lava-12669535/1/../bin/lava-test-case
11208 12:15:28.839769 <8>[ 29.741785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11209 12:15:28.840477 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11211 12:15:28.876754 /lava-12669535/1/../bin/lava-test-case
11212 12:15:28.906283 <8>[ 29.807724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11213 12:15:28.906965 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11215 12:15:28.937553 /lava-12669535/1/../bin/lava-test-case
11216 12:15:28.961056 <8>[ 29.862781] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11217 12:15:28.961743 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11219 12:15:28.995382 /lava-12669535/1/../bin/lava-test-case
11220 12:15:29.018156 <8>[ 29.919992] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11221 12:15:29.018522 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11223 12:15:29.054054 /lava-12669535/1/../bin/lava-test-case
11224 12:15:29.079682 <8>[ 29.981704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11225 12:15:29.079961 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11227 12:15:29.102148 /lava-12669535/1/../bin/lava-test-case
11228 12:15:29.131495 <8>[ 30.033248] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11229 12:15:29.132189 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11231 12:15:29.169142 /lava-12669535/1/../bin/lava-test-case
11232 12:15:29.199940 <8>[ 30.101951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11233 12:15:29.200677 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11235 12:15:29.233406 /lava-12669535/1/../bin/lava-test-case
11236 12:15:29.256120 <8>[ 30.158225] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11237 12:15:29.256415 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11239 12:15:29.276635 /lava-12669535/1/../bin/lava-test-case
11240 12:15:29.296425 <8>[ 30.197923] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11241 12:15:29.297233 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11243 12:15:29.326734 /lava-12669535/1/../bin/lava-test-case
11244 12:15:29.354568 <8>[ 30.256694] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11245 12:15:29.355611 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11247 12:15:29.383769 /lava-12669535/1/../bin/lava-test-case
11248 12:15:29.408388 <8>[ 30.310728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11249 12:15:29.408662 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11251 12:15:29.442714 /lava-12669535/1/../bin/lava-test-case
11252 12:15:29.468479 <8>[ 30.370805] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11253 12:15:29.468847 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11255 12:15:29.491542 /lava-12669535/1/../bin/lava-test-case
11256 12:15:29.512434 <8>[ 30.414641] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11257 12:15:29.512708 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11259 12:15:29.543189 /lava-12669535/1/../bin/lava-test-case
11260 12:15:29.568170 <8>[ 30.470458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11261 12:15:29.568561 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11263 12:15:29.586847 /lava-12669535/1/../bin/lava-test-case
11264 12:15:29.610255 <8>[ 30.512615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11265 12:15:29.610528 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11267 12:15:29.641956 /lava-12669535/1/../bin/lava-test-case
11268 12:15:29.669074 <8>[ 30.571100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11269 12:15:29.669351 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11271 12:15:29.702965 /lava-12669535/1/../bin/lava-test-case
11272 12:15:29.722723 <8>[ 30.625015] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11273 12:15:29.723067 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11275 12:15:29.755010 /lava-12669535/1/../bin/lava-test-case
11276 12:15:29.780400 <8>[ 30.683049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11277 12:15:29.780680 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11279 12:15:29.799826 /lava-12669535/1/../bin/lava-test-case
11280 12:15:29.820937 <8>[ 30.722857] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11281 12:15:29.821493 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11283 12:15:29.852725 /lava-12669535/1/../bin/lava-test-case
11284 12:15:29.881670 <8>[ 30.783801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11285 12:15:29.882460 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11287 12:15:29.904606 /lava-12669535/1/../bin/lava-test-case
11288 12:15:29.930334 <8>[ 30.832184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11289 12:15:29.931022 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11291 12:15:29.964591 /lava-12669535/1/../bin/lava-test-case
11292 12:15:29.992064 <8>[ 30.893544] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11293 12:15:29.992952 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11295 12:15:30.032693 /lava-12669535/1/../bin/lava-test-case
11296 12:15:30.060959 <8>[ 30.963127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11297 12:15:30.061651 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11299 12:15:30.087129 /lava-12669535/1/../bin/lava-test-case
11300 12:15:30.120913 <8>[ 31.022452] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
11301 12:15:30.121735 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
11303 12:15:30.162163 /lava-12669535/1/../bin/lava-test-case
11304 12:15:30.193316 <8>[ 31.095047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
11305 12:15:30.194007 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
11307 12:15:30.215857 /lava-12669535/1/../bin/lava-test-case
11308 12:15:30.241515 <8>[ 31.143366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11309 12:15:30.242337 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11311 12:15:30.276372 /lava-12669535/1/../bin/lava-test-case
11312 12:15:30.301143 <8>[ 31.203361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11313 12:15:30.301516 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11315 12:15:30.339573 /lava-12669535/1/../bin/lava-test-case
11316 12:15:30.363062 <8>[ 31.265326] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11317 12:15:30.363434 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11319 12:15:30.394229 /lava-12669535/1/../bin/lava-test-case
11320 12:15:30.421386 <8>[ 31.323218] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11321 12:15:30.422188 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11323 12:15:30.460247 /lava-12669535/1/../bin/lava-test-case
11324 12:15:30.489111 <8>[ 31.391026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11325 12:15:30.489943 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11327 12:15:30.524450 /lava-12669535/1/../bin/lava-test-case
11328 12:15:30.554293 <8>[ 31.456268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11329 12:15:30.555376 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11331 12:15:30.576040 /lava-12669535/1/../bin/lava-test-case
11332 12:15:30.601988 <8>[ 31.503781] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11333 12:15:30.602796 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11335 12:15:30.634597 /lava-12669535/1/../bin/lava-test-case
11336 12:15:30.659167 <8>[ 31.561158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11337 12:15:30.659972 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11339 12:15:30.701221 /lava-12669535/1/../bin/lava-test-case
11340 12:15:30.726899 <8>[ 31.628614] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11341 12:15:30.727274 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11343 12:15:30.747624 /lava-12669535/1/../bin/lava-test-case
11344 12:15:30.771020 <8>[ 31.673433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11345 12:15:30.771379 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11347 12:15:30.800933 /lava-12669535/1/../bin/lava-test-case
11348 12:15:30.824083 <8>[ 31.726068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11349 12:15:30.824451 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11351 12:15:30.844135 /lava-12669535/1/../bin/lava-test-case
11352 12:15:30.866551 <8>[ 31.768865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11353 12:15:30.866906 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11355 12:15:30.902249 /lava-12669535/1/../bin/lava-test-case
11356 12:15:30.927719 <8>[ 31.830409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11357 12:15:30.928085 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11359 12:15:30.950907 /lava-12669535/1/../bin/lava-test-case
11360 12:15:30.975897 <8>[ 31.878131] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11361 12:15:30.976260 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11363 12:15:31.011095 /lava-12669535/1/../bin/lava-test-case
11364 12:15:31.036782 <8>[ 31.939182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11365 12:15:31.037164 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11367 12:15:31.075969 /lava-12669535/1/../bin/lava-test-case
11368 12:15:31.096634 <8>[ 31.998516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11369 12:15:31.097344 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11371 12:15:31.129123 /lava-12669535/1/../bin/lava-test-case
11372 12:15:31.150025 <8>[ 32.052776] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11373 12:15:31.150330 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11375 12:15:31.184655 /lava-12669535/1/../bin/lava-test-case
11376 12:15:31.214047 <8>[ 32.115963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11377 12:15:31.214819 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11379 12:15:31.252596 /lava-12669535/1/../bin/lava-test-case
11380 12:15:31.277541 <8>[ 32.179682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11381 12:15:31.278360 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11383 12:15:31.308384 /lava-12669535/1/../bin/lava-test-case
11384 12:15:31.331972 <8>[ 32.234105] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11385 12:15:31.332691 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11387 12:15:31.365351 /lava-12669535/1/../bin/lava-test-case
11388 12:15:31.387104 <8>[ 32.289792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11389 12:15:31.387478 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11391 12:15:31.427134 /lava-12669535/1/../bin/lava-test-case
11392 12:15:31.449379 <8>[ 32.351674] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11393 12:15:31.450171 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11395 12:15:31.480372 /lava-12669535/1/../bin/lava-test-case
11396 12:15:31.506880 <8>[ 32.408869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11397 12:15:31.507734 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11399 12:15:31.542538 /lava-12669535/1/../bin/lava-test-case
11400 12:15:31.567987 <8>[ 32.470340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11401 12:15:31.568914 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11403 12:15:31.602056 /lava-12669535/1/../bin/lava-test-case
11404 12:15:31.631185 <8>[ 32.533395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11405 12:15:31.632052 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11407 12:15:31.670109 /lava-12669535/1/../bin/lava-test-case
11408 12:15:31.698090 <8>[ 32.600739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11409 12:15:31.698536 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11411 12:15:31.731578 /lava-12669535/1/../bin/lava-test-case
11412 12:15:31.756193 <8>[ 32.658603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11413 12:15:31.757158 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11415 12:15:31.797668 /lava-12669535/1/../bin/lava-test-case
11416 12:15:31.828962 <8>[ 32.731363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11417 12:15:31.829693 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11419 12:15:31.867392 /lava-12669535/1/../bin/lava-test-case
11420 12:15:31.895750 <8>[ 32.797973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11421 12:15:31.896755 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11423 12:15:31.918480 /lava-12669535/1/../bin/lava-test-case
11424 12:15:31.949694 <8>[ 32.851858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11425 12:15:31.950506 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11427 12:15:31.988078 /lava-12669535/1/../bin/lava-test-case
11428 12:15:32.017643 <8>[ 32.919715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11429 12:15:32.018518 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11431 12:15:32.045577 /lava-12669535/1/../bin/lava-test-case
11432 12:15:32.076971 <8>[ 32.979247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11433 12:15:32.077836 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11435 12:15:32.115353 /lava-12669535/1/../bin/lava-test-case
11436 12:15:32.140979 <8>[ 33.043747] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11437 12:15:32.141336 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11439 12:15:32.167377 /lava-12669535/1/../bin/lava-test-case
11440 12:15:32.198481 <8>[ 33.100383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11441 12:15:32.199180 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11443 12:15:32.236063 /lava-12669535/1/../bin/lava-test-case
11444 12:15:32.266234 <8>[ 33.168145] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11445 12:15:32.266916 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11447 12:15:32.288707 /lava-12669535/1/../bin/lava-test-case
11448 12:15:32.316856 <8>[ 33.219070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11449 12:15:32.317729 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11451 12:15:32.357340 /lava-12669535/1/../bin/lava-test-case
11452 12:15:32.385685 <8>[ 33.287478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11453 12:15:32.386472 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11455 12:15:32.407972 /lava-12669535/1/../bin/lava-test-case
11456 12:15:32.432648 <8>[ 33.334701] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11457 12:15:32.433557 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11459 12:15:32.462979 /lava-12669535/1/../bin/lava-test-case
11460 12:15:32.488076 <8>[ 33.390275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11461 12:15:32.488985 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11463 12:15:32.519749 /lava-12669535/1/../bin/lava-test-case
11464 12:15:32.547368 <8>[ 33.449771] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11465 12:15:32.548393 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11467 12:15:32.582862 /lava-12669535/1/../bin/lava-test-case
11468 12:15:32.607416 <8>[ 33.509205] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11469 12:15:32.608431 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11471 12:15:32.645554 /lava-12669535/1/../bin/lava-test-case
11472 12:15:32.678047 <8>[ 33.580038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11473 12:15:32.678848 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11475 12:15:32.703576 /lava-12669535/1/../bin/lava-test-case
11476 12:15:32.729191 <8>[ 33.632044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11477 12:15:32.729564 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11479 12:15:32.759404 /lava-12669535/1/../bin/lava-test-case
11480 12:15:32.780228 <8>[ 33.682793] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11481 12:15:32.780532 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11483 12:15:32.798928 /lava-12669535/1/../bin/lava-test-case
11484 12:15:32.823043 <8>[ 33.725633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11485 12:15:32.823302 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11487 12:15:32.852947 /lava-12669535/1/../bin/lava-test-case
11488 12:15:32.871899 <8>[ 33.774329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11489 12:15:32.872307 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11491 12:15:32.892702 /lava-12669535/1/../bin/lava-test-case
11492 12:15:32.914960 <8>[ 33.817474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11493 12:15:32.915345 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11495 12:15:33.963291 /lava-12669535/1/../bin/lava-test-case
11496 12:15:33.994310 <8>[ 34.896736] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11497 12:15:33.995201 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11499 12:15:34.016335 /lava-12669535/1/../bin/lava-test-case
11500 12:15:34.047388 <8>[ 34.949816] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11501 12:15:34.048219 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11503 12:15:35.091867 /lava-12669535/1/../bin/lava-test-case
11504 12:15:35.119840 <8>[ 36.022801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11505 12:15:35.120278 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11507 12:15:35.143929 /lava-12669535/1/../bin/lava-test-case
11508 12:15:35.176563 <8>[ 36.078884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11509 12:15:35.177384 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11511 12:15:36.227431 /lava-12669535/1/../bin/lava-test-case
11512 12:15:36.261239 <8>[ 37.163917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11513 12:15:36.262247 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11515 12:15:36.287395 /lava-12669535/1/../bin/lava-test-case
11516 12:15:36.312793 <8>[ 37.215278] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11517 12:15:36.313812 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11519 12:15:37.352216 /lava-12669535/1/../bin/lava-test-case
11520 12:15:37.382397 <8>[ 38.285457] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11521 12:15:37.383452 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11523 12:15:37.404714 /lava-12669535/1/../bin/lava-test-case
11524 12:15:37.432277 <8>[ 38.335046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11525 12:15:37.433041 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11527 12:15:38.478727 /lava-12669535/1/../bin/lava-test-case
11528 12:15:38.511583 <8>[ 39.414904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11529 12:15:38.512466 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11531 12:15:38.533356 /lava-12669535/1/../bin/lava-test-case
11532 12:15:38.561840 <8>[ 39.464537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11533 12:15:38.562734 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11535 12:15:39.606254 /lava-12669535/1/../bin/lava-test-case
11536 12:15:39.637538 <8>[ 40.540064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11537 12:15:39.638288 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11539 12:15:39.659623 /lava-12669535/1/../bin/lava-test-case
11540 12:15:39.681719 <8>[ 40.584930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11541 12:15:39.681978 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11543 12:15:40.716170 /lava-12669535/1/../bin/lava-test-case
11544 12:15:40.745583 <8>[ 41.648843] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11545 12:15:40.746294 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11547 12:15:40.766318 /lava-12669535/1/../bin/lava-test-case
11548 12:15:40.792321 <8>[ 41.695324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11549 12:15:40.793059 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11551 12:15:40.817057 /lava-12669535/1/../bin/lava-test-case
11552 12:15:40.844029 <8>[ 41.747617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11553 12:15:40.844770 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11555 12:15:41.888617 /lava-12669535/1/../bin/lava-test-case
11556 12:15:41.919744 <8>[ 42.823326] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11557 12:15:41.920586 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11559 12:15:41.941994 /lava-12669535/1/../bin/lava-test-case
11560 12:15:41.968238 <8>[ 42.871486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11561 12:15:41.968991 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11563 12:15:42.000872 /lava-12669535/1/../bin/lava-test-case
11564 12:15:42.028368 <8>[ 42.931742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11565 12:15:42.029198 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11567 12:15:42.049688 /lava-12669535/1/../bin/lava-test-case
11568 12:15:42.072506 <8>[ 42.976345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11569 12:15:42.072768 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11571 12:15:42.098727 /lava-12669535/1/../bin/lava-test-case
11572 12:15:42.124585 <8>[ 43.028496] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11573 12:15:42.124852 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11575 12:15:42.159935 /lava-12669535/1/../bin/lava-test-case
11576 12:15:42.186316 <8>[ 43.089841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11577 12:15:42.186599 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11579 12:15:42.230961 /lava-12669535/1/../bin/lava-test-case
11580 12:15:42.260426 <8>[ 43.163746] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11581 12:15:42.260712 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11583 12:15:42.282863 /lava-12669535/1/../bin/lava-test-case
11584 12:15:42.308204 <8>[ 43.212374] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11585 12:15:42.308539 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11587 12:15:42.339258 /lava-12669535/1/../bin/lava-test-case
11588 12:15:42.364158 <8>[ 43.268096] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11589 12:15:42.364439 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11591 12:15:42.395796 /lava-12669535/1/../bin/lava-test-case
11592 12:15:42.418718 <8>[ 43.322626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11593 12:15:42.418992 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11595 12:15:42.445895 /lava-12669535/1/../bin/lava-test-case
11596 12:15:42.469897 <8>[ 43.373738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11597 12:15:42.470185 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11599 12:15:42.504351 /lava-12669535/1/../bin/lava-test-case
11600 12:15:42.528073 <8>[ 43.431521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11601 12:15:42.528359 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11603 12:15:42.554009 /lava-12669535/1/../bin/lava-test-case
11604 12:15:42.577504 <8>[ 43.481297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11605 12:15:42.577786 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11607 12:15:42.609655 /lava-12669535/1/../bin/lava-test-case
11608 12:15:42.634292 <8>[ 43.537894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11609 12:15:42.634578 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11611 12:15:42.654680 /lava-12669535/1/../bin/lava-test-case
11612 12:15:42.678847 <8>[ 43.582478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11613 12:15:42.679123 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11615 12:15:42.710260 /lava-12669535/1/../bin/lava-test-case
11616 12:15:42.735496 <8>[ 43.639032] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11617 12:15:42.735804 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11619 12:15:42.756926 /lava-12669535/1/../bin/lava-test-case
11620 12:15:42.785427 <8>[ 43.689415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11621 12:15:42.785691 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11623 12:15:42.821954 /lava-12669535/1/../bin/lava-test-case
11624 12:15:42.847605 <8>[ 43.751078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11625 12:15:42.847900 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11627 12:15:42.873908 /lava-12669535/1/../bin/lava-test-case
11628 12:15:42.903731 <8>[ 43.806978] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11629 12:15:42.904669 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11631 12:15:42.942903 /lava-12669535/1/../bin/lava-test-case
11632 12:15:42.966881 <8>[ 43.870949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11633 12:15:42.967185 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11635 12:15:42.986525 /lava-12669535/1/../bin/lava-test-case
11636 12:15:43.011526 <8>[ 43.915705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11637 12:15:43.011791 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11639 12:15:44.058703 /lava-12669535/1/../bin/lava-test-case
11640 12:15:44.087455 <8>[ 44.991740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11641 12:15:44.087911 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11643 12:15:45.127662 /lava-12669535/1/../bin/lava-test-case
11644 12:15:45.155046 <8>[ 46.058557] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11645 12:15:45.155788 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11647 12:15:45.176896 /lava-12669535/1/../bin/lava-test-case
11648 12:15:45.201285 <8>[ 46.105192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11649 12:15:45.202020 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11651 12:15:45.232658 /lava-12669535/1/../bin/lava-test-case
11652 12:15:45.252705 <6>[ 46.162811] vpu: disabling
11653 12:15:45.255926 <6>[ 46.165906] vproc2: disabling
11654 12:15:45.259855 <6>[ 46.169952] vproc1: disabling
11655 12:15:45.263609 <6>[ 46.173624] vaud18: disabling
11656 12:15:45.273216 <8>[ 46.177121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11657 12:15:45.273976 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11659 12:15:45.276489 <6>[ 46.177671] vsram_others: disabling
11660 12:15:45.280098 <6>[ 46.189070] va09: disabling
11661 12:15:45.283151 <6>[ 46.192374] vsram_md: disabling
11662 12:15:45.286524 <6>[ 46.196061] Vgpu: disabling
11663 12:15:45.310306 /lava-12669535/1/../bin/lava-test-case
11664 12:15:45.340258 <8>[ 46.244134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11665 12:15:45.341001 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11667 12:15:45.374930 /lava-12669535/1/../bin/lava-test-case
11668 12:15:45.400347 <8>[ 46.303868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11669 12:15:45.401041 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11671 12:15:45.421667 /lava-12669535/1/../bin/lava-test-case
11672 12:15:45.447065 <8>[ 46.350797] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11673 12:15:45.447774 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11675 12:15:45.492067 /lava-12669535/1/../bin/lava-test-case
11676 12:15:45.514298 <8>[ 46.417997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11677 12:15:45.515050 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11679 12:15:45.534242 /lava-12669535/1/../bin/lava-test-case
11680 12:15:45.560789 <8>[ 46.464560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11681 12:15:45.561543 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11683 12:15:45.593180 /lava-12669535/1/../bin/lava-test-case
11684 12:15:45.618793 <8>[ 46.522510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11685 12:15:45.619499 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11687 12:15:45.643306 /lava-12669535/1/../bin/lava-test-case
11688 12:15:45.673116 <8>[ 46.576551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11689 12:15:45.673820 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11691 12:15:45.705787 /lava-12669535/1/../bin/lava-test-case
11692 12:15:45.730353 <8>[ 46.634398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11693 12:15:45.731188 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11695 12:15:45.753269 /lava-12669535/1/../bin/lava-test-case
11696 12:15:45.781685 <8>[ 46.685519] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11697 12:15:45.782374 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11699 12:15:45.821336 /lava-12669535/1/../bin/lava-test-case
11700 12:15:45.851167 <8>[ 46.754676] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11701 12:15:45.851984 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11703 12:15:45.873017 /lava-12669535/1/../bin/lava-test-case
11704 12:15:45.898979 <8>[ 46.802698] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11705 12:15:45.899744 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11707 12:15:45.930873 /lava-12669535/1/../bin/lava-test-case
11708 12:15:45.954107 <8>[ 46.858277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11709 12:15:45.954368 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11711 12:15:45.972466 /lava-12669535/1/../bin/lava-test-case
11712 12:15:45.991477 <8>[ 46.895416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11713 12:15:45.991762 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11715 12:15:46.019948 /lava-12669535/1/../bin/lava-test-case
11716 12:15:46.037451 <8>[ 46.941442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11717 12:15:46.037717 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11719 12:15:46.053529 /lava-12669535/1/../bin/lava-test-case
11720 12:15:46.072996 <8>[ 46.976764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11721 12:15:46.073277 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11723 12:15:46.098966 /lava-12669535/1/../bin/lava-test-case
11724 12:15:46.121847 <8>[ 47.026123] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11725 12:15:46.122325 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11727 12:15:46.147976 /lava-12669535/1/../bin/lava-test-case
11728 12:15:46.167123 <8>[ 47.071425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11729 12:15:46.167392 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11731 12:15:46.199587 /lava-12669535/1/../bin/lava-test-case
11732 12:15:46.224927 <8>[ 47.129022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11733 12:15:46.225593 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11735 12:15:47.261619 /lava-12669535/1/../bin/lava-test-case
11736 12:15:47.293789 <8>[ 48.197281] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11737 12:15:47.294504 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11739 12:15:48.325697 /lava-12669535/1/../bin/lava-test-case
11740 12:15:48.359688 <8>[ 49.263368] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11741 12:15:48.360413 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11742 12:15:48.360882 Bad test result: blocked
11743 12:15:48.383020 /lava-12669535/1/../bin/lava-test-case
11744 12:15:48.407157 <8>[ 49.311133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11745 12:15:48.407879 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11747 12:15:49.447677 /lava-12669535/1/../bin/lava-test-case
11748 12:15:49.477445 <8>[ 50.381480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11749 12:15:49.478201 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11751 12:15:49.497095 /lava-12669535/1/../bin/lava-test-case
11752 12:15:49.525450 <8>[ 50.429989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11753 12:15:49.525711 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11755 12:15:49.553188 /lava-12669535/1/../bin/lava-test-case
11756 12:15:49.573339 <8>[ 50.478311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11757 12:15:49.573599 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11759 12:15:49.597844 /lava-12669535/1/../bin/lava-test-case
11760 12:15:49.613263 <8>[ 50.518190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11761 12:15:49.613519 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11763 12:15:49.633237 /lava-12669535/1/../bin/lava-test-case
11764 12:15:49.656867 <8>[ 50.561531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11765 12:15:49.657130 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11767 12:15:49.686377 /lava-12669535/1/../bin/lava-test-case
11768 12:15:49.706393 <8>[ 50.610968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11769 12:15:49.706692 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11771 12:15:49.724920 /lava-12669535/1/../bin/lava-test-case
11772 12:15:49.746249 <8>[ 50.650881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11773 12:15:49.746533 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11775 12:15:50.795472 /lava-12669535/1/../bin/lava-test-case
11776 12:15:50.828089 <8>[ 51.732774] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11777 12:15:50.828867 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11779 12:15:50.852677 /lava-12669535/1/../bin/lava-test-case
11780 12:15:50.879942 <8>[ 51.783980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11781 12:15:50.880829 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11783 12:15:51.930667 /lava-12669535/1/../bin/lava-test-case
11784 12:15:51.956576 <8>[ 52.861328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11785 12:15:51.956872 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11787 12:15:51.975406 /lava-12669535/1/../bin/lava-test-case
11788 12:15:51.997140 <8>[ 52.902188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11789 12:15:51.997493 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11791 12:15:53.034139 /lava-12669535/1/../bin/lava-test-case
11792 12:15:53.060204 <8>[ 53.965379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11793 12:15:53.060481 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11795 12:15:53.078381 /lava-12669535/1/../bin/lava-test-case
11796 12:15:53.103009 <8>[ 54.007926] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11797 12:15:53.103570 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11799 12:15:54.155646 /lava-12669535/1/../bin/lava-test-case
11800 12:15:54.187383 <8>[ 55.091737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11801 12:15:54.187705 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11803 12:15:54.207955 /lava-12669535/1/../bin/lava-test-case
11804 12:15:54.232809 <8>[ 55.137514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11805 12:15:54.233125 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11807 12:15:54.263241 /lava-12669535/1/../bin/lava-test-case
11808 12:15:54.284254 <8>[ 55.189386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11809 12:15:54.284597 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11811 12:15:54.313807 /lava-12669535/1/../bin/lava-test-case
11812 12:15:54.338725 <8>[ 55.243715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11813 12:15:54.339042 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11815 12:15:54.359790 /lava-12669535/1/../bin/lava-test-case
11816 12:15:54.384538 <8>[ 55.289900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11817 12:15:54.384813 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11819 12:15:54.417858 /lava-12669535/1/../bin/lava-test-case
11820 12:15:54.445980 <8>[ 55.350763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11821 12:15:54.446939 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11823 12:15:54.477400 /lava-12669535/1/../bin/lava-test-case
11824 12:15:54.503143 <8>[ 55.407868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11825 12:15:54.503511 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11827 12:15:54.534283 /lava-12669535/1/../bin/lava-test-case
11828 12:15:54.565791 <8>[ 55.470522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11829 12:15:54.566706 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11831 12:15:54.589034 /lava-12669535/1/../bin/lava-test-case
11832 12:15:54.616066 <8>[ 55.521034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11833 12:15:54.616434 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11835 12:15:54.649106 /lava-12669535/1/../bin/lava-test-case
11836 12:15:54.674307 <8>[ 55.579065] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11837 12:15:54.675078 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11839 12:15:54.679976 + set +x
11840 12:15:54.683577 Received signal: <ENDRUN> 1_bootrr 12669535_1.6.2.3.5
11841 12:15:54.684133 Ending use of test pattern.
11842 12:15:54.684565 Ending test lava.1_bootrr (12669535_1.6.2.3.5), duration 27.67
11844 12:15:54.686274 <8>[ 55.591397] <LAVA_SIGNAL_ENDRUN 1_bootrr 12669535_1.6.2.3.5>
11845 12:15:54.692788 <LAVA_TEST_RUNNER EXIT>
11846 12:15:54.693562 ok: lava_test_shell seems to have completed
11847 12:15:54.698746 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11848 12:15:54.699455 end: 4.1 lava-test-shell (duration 00:00:28) [common]
11849 12:15:54.699990 end: 4 lava-test-retry (duration 00:00:28) [common]
11850 12:15:54.700701 start: 5 finalize (timeout 00:07:38) [common]
11851 12:15:54.701193 start: 5.1 power-off (timeout 00:00:30) [common]
11852 12:15:54.701941 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11853 12:15:54.821056 >> Command sent successfully.
11854 12:15:54.824599 Returned 0 in 0 seconds
11855 12:15:54.925500 end: 5.1 power-off (duration 00:00:00) [common]
11857 12:15:54.927071 start: 5.2 read-feedback (timeout 00:07:38) [common]
11858 12:15:54.928480 Listened to connection for namespace 'common' for up to 1s
11859 12:15:55.928832 Finalising connection for namespace 'common'
11860 12:15:55.929001 Disconnecting from shell: Finalise
11861 12:15:55.929083 / #
11862 12:15:56.029419 end: 5.2 read-feedback (duration 00:00:01) [common]
11863 12:15:56.029612 end: 5 finalize (duration 00:00:01) [common]
11864 12:15:56.029752 Cleaning after the job
11865 12:15:56.029888 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669535/tftp-deploy-ejgbvkr4/ramdisk
11866 12:15:56.032737 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669535/tftp-deploy-ejgbvkr4/kernel
11867 12:15:56.046402 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669535/tftp-deploy-ejgbvkr4/dtb
11868 12:15:56.046593 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669535/tftp-deploy-ejgbvkr4/nfsrootfs
11869 12:15:56.120411 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669535/tftp-deploy-ejgbvkr4/modules
11870 12:15:56.127701 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12669535
11871 12:15:56.514507 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12669535
11872 12:15:56.514693 Job finished correctly