Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 16
- Kernel Errors: 31
1 12:09:31.498389 lava-dispatcher, installed at version: 2023.10
2 12:09:31.498605 start: 0 validate
3 12:09:31.498753 Start time: 2024-01-31 12:09:31.498741+00:00 (UTC)
4 12:09:31.498873 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:09:31.499006 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:09:31.774476 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:09:31.775228 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:09:32.043136 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:09:32.043926 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:10:32.378991 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:10:32.379777 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:10:32.920818 validate duration: 61.42
14 12:10:32.921087 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:10:32.921185 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:10:32.921270 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:10:32.921387 Not decompressing ramdisk as can be used compressed.
18 12:10:32.921470 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 12:10:32.921538 saving as /var/lib/lava/dispatcher/tmp/12669492/tftp-deploy-mt3j961u/ramdisk/rootfs.cpio.gz
20 12:10:32.921602 total size: 43284872 (41 MB)
21 12:10:37.135171 progress 0 % (0 MB)
22 12:10:37.181721 progress 5 % (2 MB)
23 12:10:37.198441 progress 10 % (4 MB)
24 12:10:37.210613 progress 15 % (6 MB)
25 12:10:37.221679 progress 20 % (8 MB)
26 12:10:37.232779 progress 25 % (10 MB)
27 12:10:37.244036 progress 30 % (12 MB)
28 12:10:37.255337 progress 35 % (14 MB)
29 12:10:37.266653 progress 40 % (16 MB)
30 12:10:37.277802 progress 45 % (18 MB)
31 12:10:37.288908 progress 50 % (20 MB)
32 12:10:37.300009 progress 55 % (22 MB)
33 12:10:37.310988 progress 60 % (24 MB)
34 12:10:37.321952 progress 65 % (26 MB)
35 12:10:37.332951 progress 70 % (28 MB)
36 12:10:37.344231 progress 75 % (30 MB)
37 12:10:37.355525 progress 80 % (33 MB)
38 12:10:37.366712 progress 85 % (35 MB)
39 12:10:37.377905 progress 90 % (37 MB)
40 12:10:37.388699 progress 95 % (39 MB)
41 12:10:37.399452 progress 100 % (41 MB)
42 12:10:37.399691 41 MB downloaded in 4.48 s (9.22 MB/s)
43 12:10:37.399838 end: 1.1.1 http-download (duration 00:00:04) [common]
45 12:10:37.400074 end: 1.1 download-retry (duration 00:00:04) [common]
46 12:10:37.400158 start: 1.2 download-retry (timeout 00:09:56) [common]
47 12:10:37.400239 start: 1.2.1 http-download (timeout 00:09:56) [common]
48 12:10:37.400390 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:10:37.400481 saving as /var/lib/lava/dispatcher/tmp/12669492/tftp-deploy-mt3j961u/kernel/Image
50 12:10:37.400541 total size: 51532288 (49 MB)
51 12:10:37.400600 No compression specified
52 12:10:54.407295 progress 0 % (0 MB)
53 12:10:54.423538 progress 5 % (2 MB)
54 12:10:54.436785 progress 10 % (4 MB)
55 12:10:54.449890 progress 15 % (7 MB)
56 12:10:54.463059 progress 20 % (9 MB)
57 12:10:54.476328 progress 25 % (12 MB)
58 12:10:54.489420 progress 30 % (14 MB)
59 12:10:54.502632 progress 35 % (17 MB)
60 12:10:54.515763 progress 40 % (19 MB)
61 12:10:54.528805 progress 45 % (22 MB)
62 12:10:54.541964 progress 50 % (24 MB)
63 12:10:54.555118 progress 55 % (27 MB)
64 12:10:54.568256 progress 60 % (29 MB)
65 12:10:54.581384 progress 65 % (31 MB)
66 12:10:54.594683 progress 70 % (34 MB)
67 12:10:54.608036 progress 75 % (36 MB)
68 12:10:54.621388 progress 80 % (39 MB)
69 12:10:54.634352 progress 85 % (41 MB)
70 12:10:54.647477 progress 90 % (44 MB)
71 12:10:54.660886 progress 95 % (46 MB)
72 12:10:54.673653 progress 100 % (49 MB)
73 12:10:54.673851 49 MB downloaded in 17.27 s (2.85 MB/s)
74 12:10:54.673998 end: 1.2.1 http-download (duration 00:00:17) [common]
76 12:10:54.674220 end: 1.2 download-retry (duration 00:00:17) [common]
77 12:10:54.674311 start: 1.3 download-retry (timeout 00:09:38) [common]
78 12:10:54.674393 start: 1.3.1 http-download (timeout 00:09:38) [common]
79 12:10:54.674532 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:10:54.674604 saving as /var/lib/lava/dispatcher/tmp/12669492/tftp-deploy-mt3j961u/dtb/mt8192-asurada-spherion-r0.dtb
81 12:10:54.674664 total size: 47278 (0 MB)
82 12:10:54.674724 No compression specified
83 12:10:54.941335 progress 69 % (0 MB)
84 12:10:54.942963 progress 100 % (0 MB)
85 12:10:54.943852 0 MB downloaded in 0.27 s (0.17 MB/s)
86 12:10:54.944561 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:10:54.945848 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:10:54.946321 start: 1.4 download-retry (timeout 00:09:38) [common]
90 12:10:54.946782 start: 1.4.1 http-download (timeout 00:09:38) [common]
91 12:10:54.947494 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:10:54.948062 saving as /var/lib/lava/dispatcher/tmp/12669492/tftp-deploy-mt3j961u/modules/modules.tar
93 12:10:54.948432 total size: 8639916 (8 MB)
94 12:10:54.948802 Using unxz to decompress xz
95 12:10:55.235753 progress 0 % (0 MB)
96 12:10:55.261268 progress 5 % (0 MB)
97 12:10:55.285639 progress 10 % (0 MB)
98 12:10:55.308892 progress 15 % (1 MB)
99 12:10:55.331833 progress 20 % (1 MB)
100 12:10:55.355885 progress 25 % (2 MB)
101 12:10:55.382984 progress 30 % (2 MB)
102 12:10:55.407023 progress 35 % (2 MB)
103 12:10:55.430011 progress 40 % (3 MB)
104 12:10:55.454228 progress 45 % (3 MB)
105 12:10:55.479791 progress 50 % (4 MB)
106 12:10:55.506119 progress 55 % (4 MB)
107 12:10:55.530783 progress 60 % (4 MB)
108 12:10:55.556269 progress 65 % (5 MB)
109 12:10:55.581490 progress 70 % (5 MB)
110 12:10:55.605134 progress 75 % (6 MB)
111 12:10:55.632161 progress 80 % (6 MB)
112 12:10:55.659711 progress 85 % (7 MB)
113 12:10:55.684507 progress 90 % (7 MB)
114 12:10:55.714287 progress 95 % (7 MB)
115 12:10:55.742178 progress 100 % (8 MB)
116 12:10:55.748098 8 MB downloaded in 0.80 s (10.30 MB/s)
117 12:10:55.748388 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:10:55.748649 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:10:55.748777 start: 1.5 prepare-tftp-overlay (timeout 00:09:37) [common]
121 12:10:55.748884 start: 1.5.1 extract-nfsrootfs (timeout 00:09:37) [common]
122 12:10:55.748968 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:10:55.749055 start: 1.5.2 lava-overlay (timeout 00:09:37) [common]
124 12:10:55.749278 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n
125 12:10:55.749420 makedir: /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin
126 12:10:55.749525 makedir: /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/tests
127 12:10:55.749623 makedir: /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/results
128 12:10:55.749736 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-add-keys
129 12:10:55.749885 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-add-sources
130 12:10:55.750016 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-background-process-start
131 12:10:55.750144 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-background-process-stop
132 12:10:55.750271 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-common-functions
133 12:10:55.750397 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-echo-ipv4
134 12:10:55.750523 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-install-packages
135 12:10:55.750648 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-installed-packages
136 12:10:55.750772 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-os-build
137 12:10:55.750896 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-probe-channel
138 12:10:55.751020 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-probe-ip
139 12:10:55.751144 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-target-ip
140 12:10:55.751268 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-target-mac
141 12:10:55.751392 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-target-storage
142 12:10:55.751520 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-test-case
143 12:10:55.751647 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-test-event
144 12:10:55.751771 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-test-feedback
145 12:10:55.751895 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-test-raise
146 12:10:55.752020 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-test-reference
147 12:10:55.752152 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-test-runner
148 12:10:55.752322 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-test-set
149 12:10:55.752455 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-test-shell
150 12:10:55.752585 Updating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-install-packages (oe)
151 12:10:55.752772 Updating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/bin/lava-installed-packages (oe)
152 12:10:55.752911 Creating /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/environment
153 12:10:55.753010 LAVA metadata
154 12:10:55.753081 - LAVA_JOB_ID=12669492
155 12:10:55.753146 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:10:55.753247 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:37) [common]
157 12:10:55.753313 skipped lava-vland-overlay
158 12:10:55.753385 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:10:55.753463 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:37) [common]
160 12:10:55.753525 skipped lava-multinode-overlay
161 12:10:55.753596 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:10:55.753686 start: 1.5.2.3 test-definition (timeout 00:09:37) [common]
163 12:10:55.753759 Loading test definitions
164 12:10:55.753849 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:37) [common]
165 12:10:55.753922 Using /lava-12669492 at stage 0
166 12:10:55.754235 uuid=12669492_1.5.2.3.1 testdef=None
167 12:10:55.754323 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:10:55.754406 start: 1.5.2.3.2 test-overlay (timeout 00:09:37) [common]
169 12:10:55.755031 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:10:55.755249 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:37) [common]
172 12:10:55.755867 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:10:55.756093 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:37) [common]
175 12:10:55.756687 runner path: /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/0/tests/0_igt-gpu-panfrost test_uuid 12669492_1.5.2.3.1
176 12:10:55.756890 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:10:55.757096 Creating lava-test-runner.conf files
179 12:10:55.757158 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12669492/lava-overlay-6ain6c2n/lava-12669492/0 for stage 0
180 12:10:55.757246 - 0_igt-gpu-panfrost
181 12:10:55.757341 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:10:55.757425 start: 1.5.2.4 compress-overlay (timeout 00:09:37) [common]
183 12:10:55.763990 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:10:55.764093 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
185 12:10:55.764176 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:10:55.764259 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:10:55.764342 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
188 12:10:57.167505 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:10:57.167902 start: 1.5.4 extract-modules (timeout 00:09:36) [common]
190 12:10:57.168022 extracting modules file /var/lib/lava/dispatcher/tmp/12669492/tftp-deploy-mt3j961u/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12669492/extract-overlay-ramdisk-ilw7782j/ramdisk
191 12:10:57.401962 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:10:57.402135 start: 1.5.5 apply-overlay-tftp (timeout 00:09:36) [common]
193 12:10:57.402231 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12669492/compress-overlay-nmxf96vc/overlay-1.5.2.4.tar.gz to ramdisk
194 12:10:57.402305 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12669492/compress-overlay-nmxf96vc/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12669492/extract-overlay-ramdisk-ilw7782j/ramdisk
195 12:10:57.408895 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:10:57.409004 start: 1.5.6 configure-preseed-file (timeout 00:09:36) [common]
197 12:10:57.409089 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:10:57.409176 start: 1.5.7 compress-ramdisk (timeout 00:09:36) [common]
199 12:10:57.409250 Building ramdisk /var/lib/lava/dispatcher/tmp/12669492/extract-overlay-ramdisk-ilw7782j/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12669492/extract-overlay-ramdisk-ilw7782j/ramdisk
200 12:10:58.441298 >> 369992 blocks
201 12:11:04.186664 rename /var/lib/lava/dispatcher/tmp/12669492/extract-overlay-ramdisk-ilw7782j/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12669492/tftp-deploy-mt3j961u/ramdisk/ramdisk.cpio.gz
202 12:11:04.187124 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 12:11:04.187251 start: 1.5.8 prepare-kernel (timeout 00:09:29) [common]
204 12:11:04.187354 start: 1.5.8.1 prepare-fit (timeout 00:09:29) [common]
205 12:11:04.187466 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12669492/tftp-deploy-mt3j961u/kernel/Image'
206 12:11:16.972161 Returned 0 in 12 seconds
207 12:11:17.073268 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12669492/tftp-deploy-mt3j961u/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12669492/tftp-deploy-mt3j961u/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12669492/tftp-deploy-mt3j961u/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12669492/tftp-deploy-mt3j961u/kernel/image.itb
208 12:11:17.947192 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:11:17.947581 output: Created: Wed Jan 31 12:11:17 2024
210 12:11:17.947660 output: Image 0 (kernel-1)
211 12:11:17.947729 output: Description:
212 12:11:17.947796 output: Created: Wed Jan 31 12:11:17 2024
213 12:11:17.947859 output: Type: Kernel Image
214 12:11:17.947919 output: Compression: lzma compressed
215 12:11:17.947978 output: Data Size: 12047284 Bytes = 11764.93 KiB = 11.49 MiB
216 12:11:17.948037 output: Architecture: AArch64
217 12:11:17.948093 output: OS: Linux
218 12:11:17.948147 output: Load Address: 0x00000000
219 12:11:17.948203 output: Entry Point: 0x00000000
220 12:11:17.948268 output: Hash algo: crc32
221 12:11:17.948327 output: Hash value: 5a47eb78
222 12:11:17.948387 output: Image 1 (fdt-1)
223 12:11:17.948446 output: Description: mt8192-asurada-spherion-r0
224 12:11:17.948503 output: Created: Wed Jan 31 12:11:17 2024
225 12:11:17.948557 output: Type: Flat Device Tree
226 12:11:17.948611 output: Compression: uncompressed
227 12:11:17.948664 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 12:11:17.948742 output: Architecture: AArch64
229 12:11:17.948812 output: Hash algo: crc32
230 12:11:17.948864 output: Hash value: cc4352de
231 12:11:17.948916 output: Image 2 (ramdisk-1)
232 12:11:17.948969 output: Description: unavailable
233 12:11:17.949021 output: Created: Wed Jan 31 12:11:17 2024
234 12:11:17.949075 output: Type: RAMDisk Image
235 12:11:17.949128 output: Compression: Unknown Compression
236 12:11:17.949180 output: Data Size: 56431759 Bytes = 55109.14 KiB = 53.82 MiB
237 12:11:17.949234 output: Architecture: AArch64
238 12:11:17.949286 output: OS: Linux
239 12:11:17.949339 output: Load Address: unavailable
240 12:11:17.949392 output: Entry Point: unavailable
241 12:11:17.949446 output: Hash algo: crc32
242 12:11:17.949499 output: Hash value: 648673d0
243 12:11:17.949551 output: Default Configuration: 'conf-1'
244 12:11:17.949604 output: Configuration 0 (conf-1)
245 12:11:17.949656 output: Description: mt8192-asurada-spherion-r0
246 12:11:17.949709 output: Kernel: kernel-1
247 12:11:17.949762 output: Init Ramdisk: ramdisk-1
248 12:11:17.949815 output: FDT: fdt-1
249 12:11:17.949869 output: Loadables: kernel-1
250 12:11:17.949921 output:
251 12:11:17.950124 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 12:11:17.950218 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 12:11:17.950324 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 12:11:17.950416 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:15) [common]
255 12:11:17.950493 No LXC device requested
256 12:11:17.950571 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:11:17.950657 start: 1.7 deploy-device-env (timeout 00:09:15) [common]
258 12:11:17.950734 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:11:17.950804 Checking files for TFTP limit of 4294967296 bytes.
260 12:11:17.951309 end: 1 tftp-deploy (duration 00:00:45) [common]
261 12:11:17.951414 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:11:17.951505 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:11:17.951625 substitutions:
264 12:11:17.951696 - {DTB}: 12669492/tftp-deploy-mt3j961u/dtb/mt8192-asurada-spherion-r0.dtb
265 12:11:17.951760 - {INITRD}: 12669492/tftp-deploy-mt3j961u/ramdisk/ramdisk.cpio.gz
266 12:11:17.951819 - {KERNEL}: 12669492/tftp-deploy-mt3j961u/kernel/Image
267 12:11:17.951876 - {LAVA_MAC}: None
268 12:11:17.951933 - {PRESEED_CONFIG}: None
269 12:11:17.951988 - {PRESEED_LOCAL}: None
270 12:11:17.952043 - {RAMDISK}: 12669492/tftp-deploy-mt3j961u/ramdisk/ramdisk.cpio.gz
271 12:11:17.952098 - {ROOT_PART}: None
272 12:11:17.952152 - {ROOT}: None
273 12:11:17.952205 - {SERVER_IP}: 192.168.201.1
274 12:11:17.952259 - {TEE}: None
275 12:11:17.952313 Parsed boot commands:
276 12:11:17.952368 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:11:17.952550 Parsed boot commands: tftpboot 192.168.201.1 12669492/tftp-deploy-mt3j961u/kernel/image.itb 12669492/tftp-deploy-mt3j961u/kernel/cmdline
278 12:11:17.952641 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:11:17.952757 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:11:17.952863 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:11:17.952950 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:11:17.953020 Not connected, no need to disconnect.
283 12:11:17.953093 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:11:17.953171 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:11:17.953237 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 12:11:17.957267 Setting prompt string to ['lava-test: # ']
287 12:11:17.957643 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:11:17.957753 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:11:17.957855 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:11:17.957945 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:11:17.958178 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
292 12:11:23.108083 >> Command sent successfully.
293 12:11:23.120170 Returned 0 in 5 seconds
294 12:11:23.221472 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:11:23.224409 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:11:23.225190 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:11:23.225808 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:11:23.226395 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:11:23.227050 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:11:23.228768 [Enter `^Ec?' for help]
302 12:11:23.394846
303 12:11:23.395388
304 12:11:23.395761 F0: 102B 0000
305 12:11:23.396137
306 12:11:23.396632 F3: 1001 0000 [0200]
307 12:11:23.397168
308 12:11:23.398466 F3: 1001 0000
309 12:11:23.398956
310 12:11:23.399328 F7: 102D 0000
311 12:11:23.399676
312 12:11:23.400008 F1: 0000 0000
313 12:11:23.400338
314 12:11:23.402364 V0: 0000 0000 [0001]
315 12:11:23.402836
316 12:11:23.403210 00: 0007 8000
317 12:11:23.403583
318 12:11:23.406529 01: 0000 0000
319 12:11:23.407007
320 12:11:23.407388 BP: 0C00 0209 [0000]
321 12:11:23.407835
322 12:11:23.409285 G0: 1182 0000
323 12:11:23.409757
324 12:11:23.410132 EC: 0000 0021 [4000]
325 12:11:23.410482
326 12:11:23.414116 S7: 0000 0000 [0000]
327 12:11:23.414586
328 12:11:23.415033 CC: 0000 0000 [0001]
329 12:11:23.415390
330 12:11:23.418026 T0: 0000 0040 [010F]
331 12:11:23.418498
332 12:11:23.418965 Jump to BL
333 12:11:23.419325
334 12:11:23.441691
335 12:11:23.442122
336 12:11:23.442460
337 12:11:23.449181 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:11:23.451758 ARM64: Exception handlers installed.
339 12:11:23.455711 ARM64: Testing exception
340 12:11:23.459345 ARM64: Done test exception
341 12:11:23.465280 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:11:23.475747 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:11:23.482011 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:11:23.492766 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:11:23.498619 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:11:23.510031 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:11:23.520575 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:11:23.526117 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:11:23.544548 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:11:23.548117 WDT: Last reset was cold boot
351 12:11:23.551425 SPI1(PAD0) initialized at 2873684 Hz
352 12:11:23.554712 SPI5(PAD0) initialized at 992727 Hz
353 12:11:23.558069 VBOOT: Loading verstage.
354 12:11:23.564486 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:11:23.567531 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:11:23.571033 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:11:23.574255 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:11:23.581826 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:11:23.588831 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:11:23.600488 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
361 12:11:23.601109
362 12:11:23.601485
363 12:11:23.609237 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:11:23.613728 ARM64: Exception handlers installed.
365 12:11:23.617058 ARM64: Testing exception
366 12:11:23.617639 ARM64: Done test exception
367 12:11:23.623145 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:11:23.625947 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:11:23.640143 Probing TPM: . done!
370 12:11:23.640641 TPM ready after 0 ms
371 12:11:23.647014 Connected to device vid:did:rid of 1ae0:0028:00
372 12:11:23.653797 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
373 12:11:23.697128 Initialized TPM device CR50 revision 0
374 12:11:23.706872 tlcl_send_startup: Startup return code is 0
375 12:11:23.707443 TPM: setup succeeded
376 12:11:23.718617 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:11:23.727936 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:11:23.738113 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:11:23.746404 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:11:23.749699 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:11:23.753236 in-header: 03 07 00 00 08 00 00 00
382 12:11:23.756757 in-data: aa e4 47 04 13 02 00 00
383 12:11:23.760196 Chrome EC: UHEPI supported
384 12:11:23.766591 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:11:23.769582 in-header: 03 9d 00 00 08 00 00 00
386 12:11:23.773273 in-data: 10 20 20 08 00 00 00 00
387 12:11:23.773769 Phase 1
388 12:11:23.779458 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:11:23.782851 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:11:23.790186 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:11:23.793384 Recovery requested (1009000e)
392 12:11:23.797349 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:11:23.806649 tlcl_extend: response is 0
394 12:11:23.814261 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:11:23.819552 tlcl_extend: response is 0
396 12:11:23.826249 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:11:23.846622 read SPI 0x210d4 0x2173b: 15143 us, 9048 KB/s, 72.384 Mbps
398 12:11:23.853566 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:11:23.854161
400 12:11:23.854536
401 12:11:23.863405 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:11:23.866352 ARM64: Exception handlers installed.
403 12:11:23.869877 ARM64: Testing exception
404 12:11:23.870347 ARM64: Done test exception
405 12:11:23.892895 pmic_efuse_setting: Set efuses in 11 msecs
406 12:11:23.895825 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:11:23.902599 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:11:23.906880 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:11:23.910243 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:11:23.917339 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:11:23.920485 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:11:23.924497 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:11:23.931269 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:11:23.934173 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:11:23.941968 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:11:23.944813 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:11:23.947991 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:11:23.954862 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:11:23.958169 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:11:23.964248 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:11:23.971273 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:11:23.974125 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:11:23.980964 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:11:23.988681 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:11:23.992203 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:11:23.999271 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:11:24.005671 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:11:24.008934 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:11:24.015429 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:11:24.021672 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:11:24.025963 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:11:24.032445 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:11:24.035353 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:11:24.042365 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:11:24.046124 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:11:24.052457 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:11:24.056084 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:11:24.062139 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:11:24.065367 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:11:24.072176 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:11:24.076664 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:11:24.082057 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:11:24.086022 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:11:24.091595 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:11:24.095447 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:11:24.098736 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:11:24.105284 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:11:24.108925 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:11:24.111898 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:11:24.118542 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:11:24.121983 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:11:24.124875 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:11:24.131875 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:11:24.135512 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:11:24.138926 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:11:24.142158 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:11:24.149352 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:11:24.155458 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:11:24.165251 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:11:24.168761 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:11:24.175450 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:11:24.184960 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:11:24.188789 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:11:24.195563 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:11:24.199042 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:11:24.205356 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x15
467 12:11:24.211786 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:11:24.215735 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 12:11:24.219420 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:11:24.229851 [RTC]rtc_get_frequency_meter,154: input=15, output=764
471 12:11:24.238587 [RTC]rtc_get_frequency_meter,154: input=23, output=948
472 12:11:24.248531 [RTC]rtc_get_frequency_meter,154: input=19, output=856
473 12:11:24.258804 [RTC]rtc_get_frequency_meter,154: input=17, output=811
474 12:11:24.268084 [RTC]rtc_get_frequency_meter,154: input=16, output=786
475 12:11:24.277052 [RTC]rtc_get_frequency_meter,154: input=16, output=787
476 12:11:24.286864 [RTC]rtc_get_frequency_meter,154: input=17, output=811
477 12:11:24.290663 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 12:11:24.297247 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 12:11:24.301193 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 12:11:24.303914 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 12:11:24.310166 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 12:11:24.313769 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 12:11:24.317107 ADC[4]: Raw value=671168 ID=5
484 12:11:24.317585 ADC[3]: Raw value=212549 ID=1
485 12:11:24.320535 RAM Code: 0x51
486 12:11:24.324139 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 12:11:24.330559 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 12:11:24.337210 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 12:11:24.344025 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 12:11:24.348057 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 12:11:24.350513 in-header: 03 07 00 00 08 00 00 00
492 12:11:24.353724 in-data: aa e4 47 04 13 02 00 00
493 12:11:24.357408 Chrome EC: UHEPI supported
494 12:11:24.363992 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 12:11:24.367182 in-header: 03 d5 00 00 08 00 00 00
496 12:11:24.370834 in-data: 98 20 60 08 00 00 00 00
497 12:11:24.374279 MRC: failed to locate region type 0.
498 12:11:24.380680 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 12:11:24.381314 DRAM-K: Running full calibration
500 12:11:24.387228 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 12:11:24.390473 header.status = 0x0
502 12:11:24.394282 header.version = 0x6 (expected: 0x6)
503 12:11:24.397181 header.size = 0xd00 (expected: 0xd00)
504 12:11:24.397767 header.flags = 0x0
505 12:11:24.404187 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 12:11:24.421783 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
507 12:11:24.428626 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 12:11:24.431965 dram_init: ddr_geometry: 0
509 12:11:24.435786 [EMI] MDL number = 0
510 12:11:24.436437 [EMI] Get MDL freq = 0
511 12:11:24.438240 dram_init: ddr_type: 0
512 12:11:24.438795 is_discrete_lpddr4: 1
513 12:11:24.442118 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 12:11:24.442593
515 12:11:24.442973
516 12:11:24.446068 [Bian_co] ETT version 0.0.0.1
517 12:11:24.449388 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 12:11:24.449970
519 12:11:24.456230 dramc_set_vcore_voltage set vcore to 650000
520 12:11:24.456859 Read voltage for 800, 4
521 12:11:24.459429 Vio18 = 0
522 12:11:24.459999 Vcore = 650000
523 12:11:24.460380 Vdram = 0
524 12:11:24.460788 Vddq = 0
525 12:11:24.462734 Vmddr = 0
526 12:11:24.463209 dram_init: config_dvfs: 1
527 12:11:24.469284 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 12:11:24.476318 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 12:11:24.479673 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 12:11:24.483034 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 12:11:24.485823 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 12:11:24.489335 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 12:11:24.493160 MEM_TYPE=3, freq_sel=18
534 12:11:24.495868 sv_algorithm_assistance_LP4_1600
535 12:11:24.499774 ============ PULL DRAM RESETB DOWN ============
536 12:11:24.502677 ========== PULL DRAM RESETB DOWN end =========
537 12:11:24.509556 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 12:11:24.513887 ===================================
539 12:11:24.514461 LPDDR4 DRAM CONFIGURATION
540 12:11:24.516268 ===================================
541 12:11:24.519394 EX_ROW_EN[0] = 0x0
542 12:11:24.519964 EX_ROW_EN[1] = 0x0
543 12:11:24.522783 LP4Y_EN = 0x0
544 12:11:24.526403 WORK_FSP = 0x0
545 12:11:24.526881 WL = 0x2
546 12:11:24.528955 RL = 0x2
547 12:11:24.529435 BL = 0x2
548 12:11:24.532676 RPST = 0x0
549 12:11:24.533202 RD_PRE = 0x0
550 12:11:24.535905 WR_PRE = 0x1
551 12:11:24.536479 WR_PST = 0x0
552 12:11:24.539542 DBI_WR = 0x0
553 12:11:24.540109 DBI_RD = 0x0
554 12:11:24.543082 OTF = 0x1
555 12:11:24.546764 ===================================
556 12:11:24.549795 ===================================
557 12:11:24.550275 ANA top config
558 12:11:24.552355 ===================================
559 12:11:24.556250 DLL_ASYNC_EN = 0
560 12:11:24.559849 ALL_SLAVE_EN = 1
561 12:11:24.560325 NEW_RANK_MODE = 1
562 12:11:24.562441 DLL_IDLE_MODE = 1
563 12:11:24.566174 LP45_APHY_COMB_EN = 1
564 12:11:24.570515 TX_ODT_DIS = 1
565 12:11:24.570994 NEW_8X_MODE = 1
566 12:11:24.572825 ===================================
567 12:11:24.576224 ===================================
568 12:11:24.578961 data_rate = 1600
569 12:11:24.582614 CKR = 1
570 12:11:24.585407 DQ_P2S_RATIO = 8
571 12:11:24.589241 ===================================
572 12:11:24.592460 CA_P2S_RATIO = 8
573 12:11:24.596211 DQ_CA_OPEN = 0
574 12:11:24.596892 DQ_SEMI_OPEN = 0
575 12:11:24.599769 CA_SEMI_OPEN = 0
576 12:11:24.603074 CA_FULL_RATE = 0
577 12:11:24.606224 DQ_CKDIV4_EN = 1
578 12:11:24.610080 CA_CKDIV4_EN = 1
579 12:11:24.612620 CA_PREDIV_EN = 0
580 12:11:24.613246 PH8_DLY = 0
581 12:11:24.616406 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 12:11:24.619944 DQ_AAMCK_DIV = 4
583 12:11:24.622493 CA_AAMCK_DIV = 4
584 12:11:24.625795 CA_ADMCK_DIV = 4
585 12:11:24.629804 DQ_TRACK_CA_EN = 0
586 12:11:24.630332 CA_PICK = 800
587 12:11:24.632472 CA_MCKIO = 800
588 12:11:24.635651 MCKIO_SEMI = 0
589 12:11:24.639467 PLL_FREQ = 3068
590 12:11:24.643027 DQ_UI_PI_RATIO = 32
591 12:11:24.645780 CA_UI_PI_RATIO = 0
592 12:11:24.648985 ===================================
593 12:11:24.652661 ===================================
594 12:11:24.655776 memory_type:LPDDR4
595 12:11:24.656375 GP_NUM : 10
596 12:11:24.659319 SRAM_EN : 1
597 12:11:24.659888 MD32_EN : 0
598 12:11:24.661875 ===================================
599 12:11:24.666502 [ANA_INIT] >>>>>>>>>>>>>>
600 12:11:24.669378 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 12:11:24.672031 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 12:11:24.675539 ===================================
603 12:11:24.678606 data_rate = 1600,PCW = 0X7600
604 12:11:24.682467 ===================================
605 12:11:24.685824 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 12:11:24.689279 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 12:11:24.695438 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 12:11:24.699152 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 12:11:24.702553 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 12:11:24.709053 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 12:11:24.709610 [ANA_INIT] flow start
612 12:11:24.712483 [ANA_INIT] PLL >>>>>>>>
613 12:11:24.713001 [ANA_INIT] PLL <<<<<<<<
614 12:11:24.715679 [ANA_INIT] MIDPI >>>>>>>>
615 12:11:24.719671 [ANA_INIT] MIDPI <<<<<<<<
616 12:11:24.722508 [ANA_INIT] DLL >>>>>>>>
617 12:11:24.723076 [ANA_INIT] flow end
618 12:11:24.725644 ============ LP4 DIFF to SE enter ============
619 12:11:24.732375 ============ LP4 DIFF to SE exit ============
620 12:11:24.732890 [ANA_INIT] <<<<<<<<<<<<<
621 12:11:24.735736 [Flow] Enable top DCM control >>>>>
622 12:11:24.739450 [Flow] Enable top DCM control <<<<<
623 12:11:24.742848 Enable DLL master slave shuffle
624 12:11:24.748669 ==============================================================
625 12:11:24.749257 Gating Mode config
626 12:11:24.756087 ==============================================================
627 12:11:24.759322 Config description:
628 12:11:24.768679 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 12:11:24.775462 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 12:11:24.778632 SELPH_MODE 0: By rank 1: By Phase
631 12:11:24.785673 ==============================================================
632 12:11:24.788789 GAT_TRACK_EN = 1
633 12:11:24.789427 RX_GATING_MODE = 2
634 12:11:24.792205 RX_GATING_TRACK_MODE = 2
635 12:11:24.795665 SELPH_MODE = 1
636 12:11:24.799093 PICG_EARLY_EN = 1
637 12:11:24.802336 VALID_LAT_VALUE = 1
638 12:11:24.808613 ==============================================================
639 12:11:24.812343 Enter into Gating configuration >>>>
640 12:11:24.815366 Exit from Gating configuration <<<<
641 12:11:24.819272 Enter into DVFS_PRE_config >>>>>
642 12:11:24.828576 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 12:11:24.832164 Exit from DVFS_PRE_config <<<<<
644 12:11:24.835059 Enter into PICG configuration >>>>
645 12:11:24.839673 Exit from PICG configuration <<<<
646 12:11:24.842449 [RX_INPUT] configuration >>>>>
647 12:11:24.843017 [RX_INPUT] configuration <<<<<
648 12:11:24.848901 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 12:11:24.855691 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 12:11:24.859063 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 12:11:24.865422 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 12:11:24.872873 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 12:11:24.878983 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 12:11:24.882428 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 12:11:24.886533 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 12:11:24.893498 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 12:11:24.895918 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 12:11:24.899453 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 12:11:24.906298 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 12:11:24.906874 ===================================
661 12:11:24.909131 LPDDR4 DRAM CONFIGURATION
662 12:11:24.912669 ===================================
663 12:11:24.915609 EX_ROW_EN[0] = 0x0
664 12:11:24.916180 EX_ROW_EN[1] = 0x0
665 12:11:24.918608 LP4Y_EN = 0x0
666 12:11:24.919301 WORK_FSP = 0x0
667 12:11:24.922736 WL = 0x2
668 12:11:24.923309 RL = 0x2
669 12:11:24.925271 BL = 0x2
670 12:11:24.925745 RPST = 0x0
671 12:11:24.928631 RD_PRE = 0x0
672 12:11:24.931784 WR_PRE = 0x1
673 12:11:24.932258 WR_PST = 0x0
674 12:11:24.935864 DBI_WR = 0x0
675 12:11:24.936339 DBI_RD = 0x0
676 12:11:24.939195 OTF = 0x1
677 12:11:24.942288 ===================================
678 12:11:24.946132 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 12:11:24.949019 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 12:11:24.951657 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 12:11:24.955815 ===================================
682 12:11:24.958795 LPDDR4 DRAM CONFIGURATION
683 12:11:24.963080 ===================================
684 12:11:24.965392 EX_ROW_EN[0] = 0x10
685 12:11:24.965866 EX_ROW_EN[1] = 0x0
686 12:11:24.968540 LP4Y_EN = 0x0
687 12:11:24.969061 WORK_FSP = 0x0
688 12:11:24.972500 WL = 0x2
689 12:11:24.973116 RL = 0x2
690 12:11:24.975404 BL = 0x2
691 12:11:24.976108 RPST = 0x0
692 12:11:24.979219 RD_PRE = 0x0
693 12:11:24.979790 WR_PRE = 0x1
694 12:11:24.982242 WR_PST = 0x0
695 12:11:24.982713 DBI_WR = 0x0
696 12:11:24.985356 DBI_RD = 0x0
697 12:11:24.985927 OTF = 0x1
698 12:11:24.989083 ===================================
699 12:11:24.995929 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 12:11:25.000297 nWR fixed to 40
701 12:11:25.003947 [ModeRegInit_LP4] CH0 RK0
702 12:11:25.004510 [ModeRegInit_LP4] CH0 RK1
703 12:11:25.007782 [ModeRegInit_LP4] CH1 RK0
704 12:11:25.010224 [ModeRegInit_LP4] CH1 RK1
705 12:11:25.010700 match AC timing 12
706 12:11:25.017657 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 12:11:25.020578 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 12:11:25.023645 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 12:11:25.030360 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 12:11:25.033367 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 12:11:25.033866 [EMI DOE] emi_dcm 0
712 12:11:25.040264 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 12:11:25.040887 ==
714 12:11:25.044241 Dram Type= 6, Freq= 0, CH_0, rank 0
715 12:11:25.046995 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 12:11:25.047584 ==
717 12:11:25.054102 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 12:11:25.060411 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 12:11:25.067843 [CA 0] Center 37 (7~68) winsize 62
720 12:11:25.071340 [CA 1] Center 37 (7~68) winsize 62
721 12:11:25.074793 [CA 2] Center 35 (5~66) winsize 62
722 12:11:25.078066 [CA 3] Center 35 (4~66) winsize 63
723 12:11:25.081333 [CA 4] Center 34 (4~65) winsize 62
724 12:11:25.084807 [CA 5] Center 34 (4~64) winsize 61
725 12:11:25.085376
726 12:11:25.087770 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 12:11:25.088338
728 12:11:25.091063 [CATrainingPosCal] consider 1 rank data
729 12:11:25.094414 u2DelayCellTimex100 = 270/100 ps
730 12:11:25.098161 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
731 12:11:25.102329 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
732 12:11:25.107363 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
733 12:11:25.111153 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
734 12:11:25.116927 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
735 12:11:25.117888 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
736 12:11:25.118592
737 12:11:25.121546 CA PerBit enable=1, Macro0, CA PI delay=34
738 12:11:25.122128
739 12:11:25.124982 [CBTSetCACLKResult] CA Dly = 34
740 12:11:25.125547 CS Dly: 6 (0~37)
741 12:11:25.125925 ==
742 12:11:25.127397 Dram Type= 6, Freq= 0, CH_0, rank 1
743 12:11:25.134786 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 12:11:25.135359 ==
745 12:11:25.137607 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 12:11:25.144269 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 12:11:25.153217 [CA 0] Center 37 (6~68) winsize 63
748 12:11:25.157345 [CA 1] Center 37 (6~68) winsize 63
749 12:11:25.160377 [CA 2] Center 35 (4~66) winsize 63
750 12:11:25.163284 [CA 3] Center 34 (4~65) winsize 62
751 12:11:25.167006 [CA 4] Center 33 (3~64) winsize 62
752 12:11:25.170257 [CA 5] Center 33 (3~64) winsize 62
753 12:11:25.170859
754 12:11:25.173788 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 12:11:25.174262
756 12:11:25.177038 [CATrainingPosCal] consider 2 rank data
757 12:11:25.180170 u2DelayCellTimex100 = 270/100 ps
758 12:11:25.183406 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
759 12:11:25.186865 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
760 12:11:25.193746 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
761 12:11:25.196870 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
762 12:11:25.201188 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
763 12:11:25.204469 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
764 12:11:25.205137
765 12:11:25.207225 CA PerBit enable=1, Macro0, CA PI delay=34
766 12:11:25.207802
767 12:11:25.209835 [CBTSetCACLKResult] CA Dly = 34
768 12:11:25.210311 CS Dly: 6 (0~38)
769 12:11:25.210690
770 12:11:25.213671 ----->DramcWriteLeveling(PI) begin...
771 12:11:25.214252 ==
772 12:11:25.217945 Dram Type= 6, Freq= 0, CH_0, rank 0
773 12:11:25.223311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 12:11:25.223793 ==
775 12:11:25.226647 Write leveling (Byte 0): 31 => 31
776 12:11:25.230386 Write leveling (Byte 1): 28 => 28
777 12:11:25.230860 DramcWriteLeveling(PI) end<-----
778 12:11:25.233758
779 12:11:25.234227 ==
780 12:11:25.237126 Dram Type= 6, Freq= 0, CH_0, rank 0
781 12:11:25.240850 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 12:11:25.241419 ==
783 12:11:25.244080 [Gating] SW mode calibration
784 12:11:25.250545 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 12:11:25.254139 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 12:11:25.260552 0 6 0 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (1 0)
787 12:11:25.264153 0 6 4 | B1->B0 | 2828 2424 | 1 0 | (1 0) (1 0)
788 12:11:25.267594 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 12:11:25.273247 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:11:25.276858 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:11:25.280402 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:11:25.286780 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:11:25.291094 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:11:25.293538 0 7 0 | B1->B0 | 2929 2e2e | 0 0 | (0 0) (0 0)
795 12:11:25.300635 0 7 4 | B1->B0 | 3a3a 4343 | 0 1 | (0 0) (0 0)
796 12:11:25.303600 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 12:11:25.307304 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 12:11:25.313905 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 12:11:25.317103 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 12:11:25.320318 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 12:11:25.323738 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 12:11:25.330092 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
803 12:11:25.334504 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 12:11:25.337087 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 12:11:25.344456 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 12:11:25.346972 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 12:11:25.350564 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 12:11:25.356896 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 12:11:25.360243 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 12:11:25.364162 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 12:11:25.370530 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 12:11:25.373397 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 12:11:25.377243 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 12:11:25.383850 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 12:11:25.387030 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 12:11:25.391360 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 12:11:25.397630 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
818 12:11:25.400608 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
819 12:11:25.405085 Total UI for P1: 0, mck2ui 16
820 12:11:25.407244 best dqsien dly found for B1: ( 0, 9, 30)
821 12:11:25.410435 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
822 12:11:25.414388 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
823 12:11:25.416738 Total UI for P1: 0, mck2ui 16
824 12:11:25.420757 best dqsien dly found for B0: ( 0, 10, 2)
825 12:11:25.423994 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
826 12:11:25.430065 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
827 12:11:25.430632
828 12:11:25.433685 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
829 12:11:25.436635 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
830 12:11:25.440818 [Gating] SW calibration Done
831 12:11:25.441393 ==
832 12:11:25.444335 Dram Type= 6, Freq= 0, CH_0, rank 0
833 12:11:25.447326 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
834 12:11:25.447804 ==
835 12:11:25.448182 RX Vref Scan: 0
836 12:11:25.448536
837 12:11:25.450810 RX Vref 0 -> 0, step: 1
838 12:11:25.451280
839 12:11:25.454066 RX Delay -130 -> 252, step: 16
840 12:11:25.457288 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
841 12:11:25.461367 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
842 12:11:25.464529 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
843 12:11:25.471936 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
844 12:11:25.474693 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
845 12:11:25.477850 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
846 12:11:25.480887 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
847 12:11:25.484278 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
848 12:11:25.491425 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
849 12:11:25.495157 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
850 12:11:25.497201 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
851 12:11:25.501398 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
852 12:11:25.504241 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
853 12:11:25.511896 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
854 12:11:25.514211 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
855 12:11:25.517606 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
856 12:11:25.518106 ==
857 12:11:25.521150 Dram Type= 6, Freq= 0, CH_0, rank 0
858 12:11:25.524645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
859 12:11:25.529315 ==
860 12:11:25.529887 DQS Delay:
861 12:11:25.530265 DQS0 = 0, DQS1 = 0
862 12:11:25.531049 DQM Delay:
863 12:11:25.531428 DQM0 = 82, DQM1 = 72
864 12:11:25.531770 DQ Delay:
865 12:11:25.534330 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
866 12:11:25.538671 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
867 12:11:25.540933 DQ8 =53, DQ9 =53, DQ10 =69, DQ11 =69
868 12:11:25.544062 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
869 12:11:25.544567
870 12:11:25.544998
871 12:11:25.547911 ==
872 12:11:25.551811 Dram Type= 6, Freq= 0, CH_0, rank 0
873 12:11:25.554275 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
874 12:11:25.554914 ==
875 12:11:25.555301
876 12:11:25.555650
877 12:11:25.558029 TX Vref Scan disable
878 12:11:25.558797 == TX Byte 0 ==
879 12:11:25.561047 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
880 12:11:25.568256 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
881 12:11:25.568860 == TX Byte 1 ==
882 12:11:25.571595 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
883 12:11:25.577751 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
884 12:11:25.578373 ==
885 12:11:25.581176 Dram Type= 6, Freq= 0, CH_0, rank 0
886 12:11:25.584328 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
887 12:11:25.584939 ==
888 12:11:25.597854 TX Vref=22, minBit 0, minWin=27, winSum=442
889 12:11:25.600844 TX Vref=24, minBit 2, minWin=28, winSum=453
890 12:11:25.604507 TX Vref=26, minBit 4, minWin=28, winSum=457
891 12:11:25.607548 TX Vref=28, minBit 0, minWin=28, winSum=456
892 12:11:25.610435 TX Vref=30, minBit 0, minWin=28, winSum=455
893 12:11:25.617921 TX Vref=32, minBit 0, minWin=28, winSum=454
894 12:11:25.620808 [TxChooseVref] Worse bit 4, Min win 28, Win sum 457, Final Vref 26
895 12:11:25.621401
896 12:11:25.624342 Final TX Range 1 Vref 26
897 12:11:25.624962
898 12:11:25.625343 ==
899 12:11:25.627309 Dram Type= 6, Freq= 0, CH_0, rank 0
900 12:11:25.631492 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
901 12:11:25.631969 ==
902 12:11:25.632414
903 12:11:25.634383
904 12:11:25.634850 TX Vref Scan disable
905 12:11:25.638423 == TX Byte 0 ==
906 12:11:25.641210 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
907 12:11:25.644467 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
908 12:11:25.648392 == TX Byte 1 ==
909 12:11:25.651445 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
910 12:11:25.653981 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
911 12:11:25.654460
912 12:11:25.658406 [DATLAT]
913 12:11:25.658976 Freq=800, CH0 RK0
914 12:11:25.659356
915 12:11:25.661166 DATLAT Default: 0xa
916 12:11:25.661639 0, 0xFFFF, sum = 0
917 12:11:25.664634 1, 0xFFFF, sum = 0
918 12:11:25.665181 2, 0xFFFF, sum = 0
919 12:11:25.667750 3, 0xFFFF, sum = 0
920 12:11:25.668228 4, 0xFFFF, sum = 0
921 12:11:25.671536 5, 0xFFFF, sum = 0
922 12:11:25.672200 6, 0xFFFF, sum = 0
923 12:11:25.674614 7, 0xFFFF, sum = 0
924 12:11:25.675101 8, 0x0, sum = 1
925 12:11:25.677665 9, 0x0, sum = 2
926 12:11:25.678147 10, 0x0, sum = 3
927 12:11:25.681309 11, 0x0, sum = 4
928 12:11:25.681789 best_step = 9
929 12:11:25.682165
930 12:11:25.682512 ==
931 12:11:25.683913 Dram Type= 6, Freq= 0, CH_0, rank 0
932 12:11:25.691242 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
933 12:11:25.691812 ==
934 12:11:25.692192 RX Vref Scan: 1
935 12:11:25.692544
936 12:11:25.694548 Set Vref Range= 32 -> 127
937 12:11:25.695123
938 12:11:25.697996 RX Vref 32 -> 127, step: 1
939 12:11:25.698567
940 12:11:25.698948 RX Delay -111 -> 252, step: 8
941 12:11:25.699302
942 12:11:25.700942 Set Vref, RX VrefLevel [Byte0]: 32
943 12:11:25.704598 [Byte1]: 32
944 12:11:25.708518
945 12:11:25.709157 Set Vref, RX VrefLevel [Byte0]: 33
946 12:11:25.711481 [Byte1]: 33
947 12:11:25.716423
948 12:11:25.717043 Set Vref, RX VrefLevel [Byte0]: 34
949 12:11:25.719631 [Byte1]: 34
950 12:11:25.723829
951 12:11:25.724404 Set Vref, RX VrefLevel [Byte0]: 35
952 12:11:25.727481 [Byte1]: 35
953 12:11:25.731273
954 12:11:25.731969 Set Vref, RX VrefLevel [Byte0]: 36
955 12:11:25.734805 [Byte1]: 36
956 12:11:25.739405
957 12:11:25.739977 Set Vref, RX VrefLevel [Byte0]: 37
958 12:11:25.742227 [Byte1]: 37
959 12:11:25.747184
960 12:11:25.747755 Set Vref, RX VrefLevel [Byte0]: 38
961 12:11:25.749900 [Byte1]: 38
962 12:11:25.755295
963 12:11:25.755866 Set Vref, RX VrefLevel [Byte0]: 39
964 12:11:25.757693 [Byte1]: 39
965 12:11:25.762271
966 12:11:25.763054 Set Vref, RX VrefLevel [Byte0]: 40
967 12:11:25.765754 [Byte1]: 40
968 12:11:25.769819
969 12:11:25.770390 Set Vref, RX VrefLevel [Byte0]: 41
970 12:11:25.773123 [Byte1]: 41
971 12:11:25.777687
972 12:11:25.781005 Set Vref, RX VrefLevel [Byte0]: 42
973 12:11:25.781575 [Byte1]: 42
974 12:11:25.785103
975 12:11:25.785665 Set Vref, RX VrefLevel [Byte0]: 43
976 12:11:25.788328 [Byte1]: 43
977 12:11:25.792382
978 12:11:25.793033 Set Vref, RX VrefLevel [Byte0]: 44
979 12:11:25.795634 [Byte1]: 44
980 12:11:25.800179
981 12:11:25.800769 Set Vref, RX VrefLevel [Byte0]: 45
982 12:11:25.804267 [Byte1]: 45
983 12:11:25.808360
984 12:11:25.808994 Set Vref, RX VrefLevel [Byte0]: 46
985 12:11:25.811196 [Byte1]: 46
986 12:11:25.815379
987 12:11:25.815943 Set Vref, RX VrefLevel [Byte0]: 47
988 12:11:25.819120 [Byte1]: 47
989 12:11:25.823113
990 12:11:25.823677 Set Vref, RX VrefLevel [Byte0]: 48
991 12:11:25.826173 [Byte1]: 48
992 12:11:25.831769
993 12:11:25.832366 Set Vref, RX VrefLevel [Byte0]: 49
994 12:11:25.834193 [Byte1]: 49
995 12:11:25.838301
996 12:11:25.838835 Set Vref, RX VrefLevel [Byte0]: 50
997 12:11:25.841671 [Byte1]: 50
998 12:11:25.846078
999 12:11:25.846646 Set Vref, RX VrefLevel [Byte0]: 51
1000 12:11:25.848868 [Byte1]: 51
1001 12:11:25.854008
1002 12:11:25.854576 Set Vref, RX VrefLevel [Byte0]: 52
1003 12:11:25.857280 [Byte1]: 52
1004 12:11:25.864049
1005 12:11:25.864633 Set Vref, RX VrefLevel [Byte0]: 53
1006 12:11:25.865075 [Byte1]: 53
1007 12:11:25.869560
1008 12:11:25.870180 Set Vref, RX VrefLevel [Byte0]: 54
1009 12:11:25.873158 [Byte1]: 54
1010 12:11:25.876639
1011 12:11:25.877168 Set Vref, RX VrefLevel [Byte0]: 55
1012 12:11:25.880142 [Byte1]: 55
1013 12:11:25.884495
1014 12:11:25.885109 Set Vref, RX VrefLevel [Byte0]: 56
1015 12:11:25.887361 [Byte1]: 56
1016 12:11:25.892286
1017 12:11:25.892912 Set Vref, RX VrefLevel [Byte0]: 57
1018 12:11:25.895599 [Byte1]: 57
1019 12:11:25.899408
1020 12:11:25.899976 Set Vref, RX VrefLevel [Byte0]: 58
1021 12:11:25.903279 [Byte1]: 58
1022 12:11:25.907566
1023 12:11:25.908136 Set Vref, RX VrefLevel [Byte0]: 59
1024 12:11:25.910610 [Byte1]: 59
1025 12:11:25.915698
1026 12:11:25.916259 Set Vref, RX VrefLevel [Byte0]: 60
1027 12:11:25.918630 [Byte1]: 60
1028 12:11:25.922592
1029 12:11:25.923168 Set Vref, RX VrefLevel [Byte0]: 61
1030 12:11:25.925758 [Byte1]: 61
1031 12:11:25.930065
1032 12:11:25.930653 Set Vref, RX VrefLevel [Byte0]: 62
1033 12:11:25.933137 [Byte1]: 62
1034 12:11:25.937734
1035 12:11:25.938204 Set Vref, RX VrefLevel [Byte0]: 63
1036 12:11:25.940914 [Byte1]: 63
1037 12:11:25.945383
1038 12:11:25.945846 Set Vref, RX VrefLevel [Byte0]: 64
1039 12:11:25.948664 [Byte1]: 64
1040 12:11:25.955023
1041 12:11:25.955582 Set Vref, RX VrefLevel [Byte0]: 65
1042 12:11:25.956318 [Byte1]: 65
1043 12:11:25.961503
1044 12:11:25.962062 Set Vref, RX VrefLevel [Byte0]: 66
1045 12:11:25.964487 [Byte1]: 66
1046 12:11:25.968529
1047 12:11:25.969143 Set Vref, RX VrefLevel [Byte0]: 67
1048 12:11:25.972128 [Byte1]: 67
1049 12:11:25.975829
1050 12:11:25.976389 Set Vref, RX VrefLevel [Byte0]: 68
1051 12:11:25.979597 [Byte1]: 68
1052 12:11:25.983573
1053 12:11:25.984134 Set Vref, RX VrefLevel [Byte0]: 69
1054 12:11:25.987268 [Byte1]: 69
1055 12:11:25.991276
1056 12:11:25.991839 Set Vref, RX VrefLevel [Byte0]: 70
1057 12:11:25.995193 [Byte1]: 70
1058 12:11:25.999210
1059 12:11:25.999769 Set Vref, RX VrefLevel [Byte0]: 71
1060 12:11:26.002586 [Byte1]: 71
1061 12:11:26.006840
1062 12:11:26.007434 Set Vref, RX VrefLevel [Byte0]: 72
1063 12:11:26.010099 [Byte1]: 72
1064 12:11:26.014273
1065 12:11:26.014835 Set Vref, RX VrefLevel [Byte0]: 73
1066 12:11:26.017637 [Byte1]: 73
1067 12:11:26.022007
1068 12:11:26.022568 Set Vref, RX VrefLevel [Byte0]: 74
1069 12:11:26.025327 [Byte1]: 74
1070 12:11:26.030047
1071 12:11:26.030609 Final RX Vref Byte 0 = 52 to rank0
1072 12:11:26.033121 Final RX Vref Byte 1 = 57 to rank0
1073 12:11:26.036040 Final RX Vref Byte 0 = 52 to rank1
1074 12:11:26.040125 Final RX Vref Byte 1 = 57 to rank1==
1075 12:11:26.042826 Dram Type= 6, Freq= 0, CH_0, rank 0
1076 12:11:26.049828 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1077 12:11:26.050415 ==
1078 12:11:26.050794 DQS Delay:
1079 12:11:26.051163 DQS0 = 0, DQS1 = 0
1080 12:11:26.052608 DQM Delay:
1081 12:11:26.053170 DQM0 = 83, DQM1 = 73
1082 12:11:26.056062 DQ Delay:
1083 12:11:26.059816 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1084 12:11:26.062792 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1085 12:11:26.066618 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1086 12:11:26.069559 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1087 12:11:26.070126
1088 12:11:26.070521
1089 12:11:26.076919 [DQSOSCAuto] RK0, (LSB)MR18= 0x3a3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1090 12:11:26.079220 CH0 RK0: MR19=606, MR18=3A3A
1091 12:11:26.086574 CH0_RK0: MR19=0x606, MR18=0x3A3A, DQSOSC=395, MR23=63, INC=94, DEC=63
1092 12:11:26.087141
1093 12:11:26.089583 ----->DramcWriteLeveling(PI) begin...
1094 12:11:26.090152 ==
1095 12:11:26.093161 Dram Type= 6, Freq= 0, CH_0, rank 1
1096 12:11:26.095983 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1097 12:11:26.096548 ==
1098 12:11:26.099912 Write leveling (Byte 0): 28 => 28
1099 12:11:26.102735 Write leveling (Byte 1): 28 => 28
1100 12:11:26.106320 DramcWriteLeveling(PI) end<-----
1101 12:11:26.106880
1102 12:11:26.107256 ==
1103 12:11:26.109218 Dram Type= 6, Freq= 0, CH_0, rank 1
1104 12:11:26.112824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1105 12:11:26.113386 ==
1106 12:11:26.117154 [Gating] SW mode calibration
1107 12:11:26.123640 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1108 12:11:26.129812 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1109 12:11:26.132608 0 6 0 | B1->B0 | 2f2f 3030 | 1 1 | (1 0) (1 0)
1110 12:11:26.137067 0 6 4 | B1->B0 | 2424 2424 | 0 0 | (1 0) (1 0)
1111 12:11:26.142691 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1112 12:11:26.146264 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1113 12:11:26.149216 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1114 12:11:26.156418 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1115 12:11:26.159441 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1116 12:11:26.162948 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1117 12:11:26.171723 0 7 0 | B1->B0 | 2c2c 2c2c | 0 1 | (0 0) (0 0)
1118 12:11:26.173306 0 7 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1119 12:11:26.176462 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1120 12:11:26.180013 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1121 12:11:26.187150 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1122 12:11:26.189753 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1123 12:11:26.193166 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1124 12:11:26.200075 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1125 12:11:26.203501 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1126 12:11:26.206534 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1127 12:11:26.213226 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1128 12:11:26.216325 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1129 12:11:26.220097 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1130 12:11:26.226273 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 12:11:26.229875 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 12:11:26.232541 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 12:11:26.239937 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 12:11:26.242837 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 12:11:26.246578 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 12:11:26.252758 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 12:11:26.256323 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 12:11:26.259645 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 12:11:26.266034 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 12:11:26.269638 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1141 12:11:26.272260 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1142 12:11:26.279373 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1143 12:11:26.279979 Total UI for P1: 0, mck2ui 16
1144 12:11:26.286049 best dqsien dly found for B1: ( 0, 10, 0)
1145 12:11:26.289461 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1146 12:11:26.292869 Total UI for P1: 0, mck2ui 16
1147 12:11:26.296651 best dqsien dly found for B0: ( 0, 10, 2)
1148 12:11:26.300050 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1149 12:11:26.302897 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1150 12:11:26.303472
1151 12:11:26.306474 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1152 12:11:26.309462 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1153 12:11:26.312880 [Gating] SW calibration Done
1154 12:11:26.313453 ==
1155 12:11:26.315987 Dram Type= 6, Freq= 0, CH_0, rank 1
1156 12:11:26.319747 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1157 12:11:26.320332 ==
1158 12:11:26.364607 RX Vref Scan: 0
1159 12:11:26.365231
1160 12:11:26.365822 RX Vref 0 -> 0, step: 1
1161 12:11:26.366260
1162 12:11:26.367029 RX Delay -130 -> 252, step: 16
1163 12:11:26.367413 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1164 12:11:26.367761 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1165 12:11:26.368097 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1166 12:11:26.368425 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1167 12:11:26.368814 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1168 12:11:26.369227 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1169 12:11:26.369565 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1170 12:11:26.369888 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1171 12:11:26.370204 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1172 12:11:26.384471 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1173 12:11:26.385070 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1174 12:11:26.385454 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1175 12:11:26.386154 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1176 12:11:26.388549 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1177 12:11:26.391743 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1178 12:11:26.392208 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1179 12:11:26.392581 ==
1180 12:11:26.395203 Dram Type= 6, Freq= 0, CH_0, rank 1
1181 12:11:26.398480 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1182 12:11:26.398951 ==
1183 12:11:26.401802 DQS Delay:
1184 12:11:26.402360 DQS0 = 0, DQS1 = 0
1185 12:11:26.404841 DQM Delay:
1186 12:11:26.405306 DQM0 = 82, DQM1 = 74
1187 12:11:26.405677 DQ Delay:
1188 12:11:26.408762 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1189 12:11:26.411681 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1190 12:11:26.414979 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1191 12:11:26.417733 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1192 12:11:26.418219
1193 12:11:26.418715
1194 12:11:26.419178 ==
1195 12:11:26.422242 Dram Type= 6, Freq= 0, CH_0, rank 1
1196 12:11:26.428509 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1197 12:11:26.429131 ==
1198 12:11:26.429634
1199 12:11:26.430100
1200 12:11:26.430555 TX Vref Scan disable
1201 12:11:26.432071 == TX Byte 0 ==
1202 12:11:26.434871 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1203 12:11:26.438629 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1204 12:11:26.441468 == TX Byte 1 ==
1205 12:11:26.445292 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1206 12:11:26.449571 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1207 12:11:26.452046 ==
1208 12:11:26.454976 Dram Type= 6, Freq= 0, CH_0, rank 1
1209 12:11:26.458426 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1210 12:11:26.459021 ==
1211 12:11:26.471204 TX Vref=22, minBit 0, minWin=27, winSum=446
1212 12:11:26.474272 TX Vref=24, minBit 0, minWin=28, winSum=452
1213 12:11:26.477880 TX Vref=26, minBit 2, minWin=28, winSum=453
1214 12:11:26.481291 TX Vref=28, minBit 2, minWin=28, winSum=457
1215 12:11:26.483956 TX Vref=30, minBit 2, minWin=28, winSum=460
1216 12:11:26.487501 TX Vref=32, minBit 2, minWin=28, winSum=460
1217 12:11:26.494147 [TxChooseVref] Worse bit 2, Min win 28, Win sum 460, Final Vref 30
1218 12:11:26.494715
1219 12:11:26.497086 Final TX Range 1 Vref 30
1220 12:11:26.497551
1221 12:11:26.497917 ==
1222 12:11:26.501016 Dram Type= 6, Freq= 0, CH_0, rank 1
1223 12:11:26.504871 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1224 12:11:26.505435 ==
1225 12:11:26.505809
1226 12:11:26.506148
1227 12:11:26.509198 TX Vref Scan disable
1228 12:11:26.511684 == TX Byte 0 ==
1229 12:11:26.514638 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1230 12:11:26.517767 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1231 12:11:26.521693 == TX Byte 1 ==
1232 12:11:26.525049 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1233 12:11:26.527751 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1234 12:11:26.528311
1235 12:11:26.531221 [DATLAT]
1236 12:11:26.531682 Freq=800, CH0 RK1
1237 12:11:26.532070
1238 12:11:26.534020 DATLAT Default: 0x9
1239 12:11:26.534423 0, 0xFFFF, sum = 0
1240 12:11:26.537780 1, 0xFFFF, sum = 0
1241 12:11:26.538249 2, 0xFFFF, sum = 0
1242 12:11:26.540635 3, 0xFFFF, sum = 0
1243 12:11:26.541172 4, 0xFFFF, sum = 0
1244 12:11:26.544678 5, 0xFFFF, sum = 0
1245 12:11:26.545295 6, 0xFFFF, sum = 0
1246 12:11:26.547727 7, 0xFFFF, sum = 0
1247 12:11:26.548196 8, 0x0, sum = 1
1248 12:11:26.550966 9, 0x0, sum = 2
1249 12:11:26.551497 10, 0x0, sum = 3
1250 12:11:26.554889 11, 0x0, sum = 4
1251 12:11:26.555463 best_step = 9
1252 12:11:26.555835
1253 12:11:26.556176 ==
1254 12:11:26.558103 Dram Type= 6, Freq= 0, CH_0, rank 1
1255 12:11:26.561049 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1256 12:11:26.564542 ==
1257 12:11:26.565165 RX Vref Scan: 0
1258 12:11:26.565546
1259 12:11:26.567407 RX Vref 0 -> 0, step: 1
1260 12:11:26.568029
1261 12:11:26.570903 RX Delay -111 -> 252, step: 8
1262 12:11:26.574693 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1263 12:11:26.577849 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1264 12:11:26.581480 iDelay=217, Bit 2, Center 88 (-31 ~ 208) 240
1265 12:11:26.587943 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1266 12:11:26.590478 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1267 12:11:26.594348 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1268 12:11:26.597343 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1269 12:11:26.600531 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1270 12:11:26.607212 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1271 12:11:26.611136 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1272 12:11:26.614479 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1273 12:11:26.617436 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1274 12:11:26.621602 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1275 12:11:26.627290 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1276 12:11:26.631494 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1277 12:11:26.634190 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1278 12:11:26.634682 ==
1279 12:11:26.637614 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 12:11:26.641237 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1281 12:11:26.645583 ==
1282 12:11:26.646148 DQS Delay:
1283 12:11:26.646520 DQS0 = 0, DQS1 = 0
1284 12:11:26.648089 DQM Delay:
1285 12:11:26.648549 DQM0 = 87, DQM1 = 74
1286 12:11:26.648975 DQ Delay:
1287 12:11:26.651263 DQ0 =84, DQ1 =88, DQ2 =88, DQ3 =84
1288 12:11:26.653987 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1289 12:11:26.657417 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1290 12:11:26.661350 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
1291 12:11:26.661911
1292 12:11:26.662282
1293 12:11:26.671426 [DQSOSCAuto] RK1, (LSB)MR18= 0x4747, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1294 12:11:26.673835 CH0 RK1: MR19=606, MR18=4747
1295 12:11:26.680877 CH0_RK1: MR19=0x606, MR18=0x4747, DQSOSC=392, MR23=63, INC=96, DEC=64
1296 12:11:26.681345 [RxdqsGatingPostProcess] freq 800
1297 12:11:26.687837 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1298 12:11:26.690264 Pre-setting of DQS Precalculation
1299 12:11:26.694078 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1300 12:11:26.694377 ==
1301 12:11:26.696814 Dram Type= 6, Freq= 0, CH_1, rank 0
1302 12:11:26.703926 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1303 12:11:26.704340 ==
1304 12:11:26.708429 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1305 12:11:26.713833 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1306 12:11:26.723556 [CA 0] Center 37 (6~68) winsize 63
1307 12:11:26.726979 [CA 1] Center 37 (6~68) winsize 63
1308 12:11:26.730372 [CA 2] Center 34 (4~65) winsize 62
1309 12:11:26.733068 [CA 3] Center 34 (4~65) winsize 62
1310 12:11:26.736961 [CA 4] Center 33 (3~64) winsize 62
1311 12:11:26.740383 [CA 5] Center 33 (3~64) winsize 62
1312 12:11:26.740988
1313 12:11:26.743583 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1314 12:11:26.744140
1315 12:11:26.746689 [CATrainingPosCal] consider 1 rank data
1316 12:11:26.750203 u2DelayCellTimex100 = 270/100 ps
1317 12:11:26.753680 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1318 12:11:26.756439 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1319 12:11:26.764158 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1320 12:11:26.766318 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1321 12:11:26.769847 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1322 12:11:26.774265 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1323 12:11:26.774824
1324 12:11:26.777082 CA PerBit enable=1, Macro0, CA PI delay=33
1325 12:11:26.777711
1326 12:11:26.780123 [CBTSetCACLKResult] CA Dly = 33
1327 12:11:26.780674 CS Dly: 4 (0~35)
1328 12:11:26.781098 ==
1329 12:11:26.783236 Dram Type= 6, Freq= 0, CH_1, rank 1
1330 12:11:26.790254 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1331 12:11:26.790868 ==
1332 12:11:26.794546 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1333 12:11:26.800375 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1334 12:11:26.809468 [CA 0] Center 36 (6~67) winsize 62
1335 12:11:26.812481 [CA 1] Center 37 (6~68) winsize 63
1336 12:11:26.815653 [CA 2] Center 34 (4~65) winsize 62
1337 12:11:26.820124 [CA 3] Center 34 (4~65) winsize 62
1338 12:11:26.822660 [CA 4] Center 33 (3~64) winsize 62
1339 12:11:26.826477 [CA 5] Center 33 (2~64) winsize 63
1340 12:11:26.827067
1341 12:11:26.828922 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1342 12:11:26.829408
1343 12:11:26.832527 [CATrainingPosCal] consider 2 rank data
1344 12:11:26.836097 u2DelayCellTimex100 = 270/100 ps
1345 12:11:26.839360 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1346 12:11:26.843084 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1347 12:11:26.848910 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1348 12:11:26.852140 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1349 12:11:26.855863 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1350 12:11:26.859663 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1351 12:11:26.860214
1352 12:11:26.863048 CA PerBit enable=1, Macro0, CA PI delay=33
1353 12:11:26.863605
1354 12:11:26.865365 [CBTSetCACLKResult] CA Dly = 33
1355 12:11:26.865826 CS Dly: 4 (0~36)
1356 12:11:26.866193
1357 12:11:26.868873 ----->DramcWriteLeveling(PI) begin...
1358 12:11:26.872320 ==
1359 12:11:26.875567 Dram Type= 6, Freq= 0, CH_1, rank 0
1360 12:11:26.879401 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1361 12:11:26.879960 ==
1362 12:11:26.882069 Write leveling (Byte 0): 25 => 25
1363 12:11:26.885564 Write leveling (Byte 1): 25 => 25
1364 12:11:26.889271 DramcWriteLeveling(PI) end<-----
1365 12:11:26.889830
1366 12:11:26.890198 ==
1367 12:11:26.892941 Dram Type= 6, Freq= 0, CH_1, rank 0
1368 12:11:26.895667 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1369 12:11:26.896224 ==
1370 12:11:26.898605 [Gating] SW mode calibration
1371 12:11:26.906147 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1372 12:11:26.908847 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1373 12:11:26.915608 0 6 0 | B1->B0 | 3030 2424 | 0 0 | (1 1) (0 0)
1374 12:11:26.919356 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1375 12:11:26.922396 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1376 12:11:26.929181 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1377 12:11:26.932601 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1378 12:11:26.936169 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1379 12:11:26.942209 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1380 12:11:26.945312 0 6 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1381 12:11:26.948826 0 7 0 | B1->B0 | 2d2d 4444 | 1 0 | (0 0) (0 0)
1382 12:11:26.956154 0 7 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1383 12:11:26.959210 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1384 12:11:26.962555 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1385 12:11:26.968942 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1386 12:11:26.972194 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1387 12:11:26.975980 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1388 12:11:26.982322 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1389 12:11:26.985568 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1390 12:11:26.988377 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1391 12:11:26.995873 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 12:11:26.998429 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 12:11:27.002501 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 12:11:27.009055 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 12:11:27.011838 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 12:11:27.014829 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 12:11:27.022018 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 12:11:27.024612 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 12:11:27.028370 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 12:11:27.034887 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 12:11:27.038356 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 12:11:27.040862 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1403 12:11:27.047672 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1404 12:11:27.051096 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1405 12:11:27.054278 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1406 12:11:27.057608 Total UI for P1: 0, mck2ui 16
1407 12:11:27.061384 best dqsien dly found for B0: ( 0, 9, 30)
1408 12:11:27.065285 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1409 12:11:27.067858 Total UI for P1: 0, mck2ui 16
1410 12:11:27.071307 best dqsien dly found for B1: ( 0, 10, 0)
1411 12:11:27.074860 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1412 12:11:27.081363 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1413 12:11:27.081826
1414 12:11:27.084041 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1415 12:11:27.087979 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1416 12:11:27.091139 [Gating] SW calibration Done
1417 12:11:27.091412 ==
1418 12:11:27.094793 Dram Type= 6, Freq= 0, CH_1, rank 0
1419 12:11:27.097746 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1420 12:11:27.097995 ==
1421 12:11:27.101508 RX Vref Scan: 0
1422 12:11:27.101719
1423 12:11:27.101896 RX Vref 0 -> 0, step: 1
1424 12:11:27.102074
1425 12:11:27.104558 RX Delay -130 -> 252, step: 16
1426 12:11:27.108346 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1427 12:11:27.114101 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1428 12:11:27.117355 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1429 12:11:27.121638 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1430 12:11:27.123967 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1431 12:11:27.127129 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1432 12:11:27.130816 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1433 12:11:27.137327 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1434 12:11:27.141090 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1435 12:11:27.144273 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1436 12:11:27.147063 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1437 12:11:27.151319 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1438 12:11:27.157487 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1439 12:11:27.160955 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1440 12:11:27.163813 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1441 12:11:27.167306 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1442 12:11:27.167497 ==
1443 12:11:27.170938 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 12:11:27.176850 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1445 12:11:27.177000 ==
1446 12:11:27.177137 DQS Delay:
1447 12:11:27.180714 DQS0 = 0, DQS1 = 0
1448 12:11:27.180854 DQM Delay:
1449 12:11:27.180979 DQM0 = 81, DQM1 = 73
1450 12:11:27.184347 DQ Delay:
1451 12:11:27.187412 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1452 12:11:27.190635 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1453 12:11:27.194514 DQ8 =53, DQ9 =69, DQ10 =77, DQ11 =69
1454 12:11:27.197741 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1455 12:11:27.198275
1456 12:11:27.198781
1457 12:11:27.199264 ==
1458 12:11:27.200598 Dram Type= 6, Freq= 0, CH_1, rank 0
1459 12:11:27.204691 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1460 12:11:27.205427 ==
1461 12:11:27.206074
1462 12:11:27.206692
1463 12:11:27.207942 TX Vref Scan disable
1464 12:11:27.208619 == TX Byte 0 ==
1465 12:11:27.214574 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1466 12:11:27.217756 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1467 12:11:27.218098 == TX Byte 1 ==
1468 12:11:27.224075 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1469 12:11:27.227440 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1470 12:11:27.227678 ==
1471 12:11:27.231397 Dram Type= 6, Freq= 0, CH_1, rank 0
1472 12:11:27.234300 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1473 12:11:27.234479 ==
1474 12:11:27.247704 TX Vref=22, minBit 3, minWin=27, winSum=447
1475 12:11:27.251068 TX Vref=24, minBit 3, minWin=27, winSum=451
1476 12:11:27.254346 TX Vref=26, minBit 3, minWin=27, winSum=452
1477 12:11:27.257785 TX Vref=28, minBit 0, minWin=28, winSum=458
1478 12:11:27.261235 TX Vref=30, minBit 0, minWin=28, winSum=460
1479 12:11:27.264155 TX Vref=32, minBit 0, minWin=28, winSum=457
1480 12:11:27.271344 [TxChooseVref] Worse bit 0, Min win 28, Win sum 460, Final Vref 30
1481 12:11:27.271529
1482 12:11:27.274323 Final TX Range 1 Vref 30
1483 12:11:27.274463
1484 12:11:27.274586 ==
1485 12:11:27.278425 Dram Type= 6, Freq= 0, CH_1, rank 0
1486 12:11:27.281166 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1487 12:11:27.281272 ==
1488 12:11:27.281365
1489 12:11:27.284812
1490 12:11:27.284911 TX Vref Scan disable
1491 12:11:27.287913 == TX Byte 0 ==
1492 12:11:27.291285 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1493 12:11:27.294945 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1494 12:11:27.298003 == TX Byte 1 ==
1495 12:11:27.301111 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1496 12:11:27.304387 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1497 12:11:27.304469
1498 12:11:27.308129 [DATLAT]
1499 12:11:27.308287 Freq=800, CH1 RK0
1500 12:11:27.308365
1501 12:11:27.311207 DATLAT Default: 0xa
1502 12:11:27.311306 0, 0xFFFF, sum = 0
1503 12:11:27.314397 1, 0xFFFF, sum = 0
1504 12:11:27.314486 2, 0xFFFF, sum = 0
1505 12:11:27.318326 3, 0xFFFF, sum = 0
1506 12:11:27.318414 4, 0xFFFF, sum = 0
1507 12:11:27.321345 5, 0xFFFF, sum = 0
1508 12:11:27.321441 6, 0xFFFF, sum = 0
1509 12:11:27.324671 7, 0xFFFF, sum = 0
1510 12:11:27.324780 8, 0x0, sum = 1
1511 12:11:27.328879 9, 0x0, sum = 2
1512 12:11:27.329068 10, 0x0, sum = 3
1513 12:11:27.331798 11, 0x0, sum = 4
1514 12:11:27.331990 best_step = 9
1515 12:11:27.332089
1516 12:11:27.332177 ==
1517 12:11:27.335021 Dram Type= 6, Freq= 0, CH_1, rank 0
1518 12:11:27.341406 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1519 12:11:27.341648 ==
1520 12:11:27.341804 RX Vref Scan: 1
1521 12:11:27.341952
1522 12:11:27.344848 Set Vref Range= 32 -> 127
1523 12:11:27.345004
1524 12:11:27.348307 RX Vref 32 -> 127, step: 1
1525 12:11:27.348542
1526 12:11:27.348685 RX Delay -111 -> 252, step: 8
1527 12:11:27.351475
1528 12:11:27.351731 Set Vref, RX VrefLevel [Byte0]: 32
1529 12:11:27.355099 [Byte1]: 32
1530 12:11:27.359719
1531 12:11:27.360049 Set Vref, RX VrefLevel [Byte0]: 33
1532 12:11:27.362921 [Byte1]: 33
1533 12:11:27.367104
1534 12:11:27.367554 Set Vref, RX VrefLevel [Byte0]: 34
1535 12:11:27.370279 [Byte1]: 34
1536 12:11:27.374671
1537 12:11:27.375239 Set Vref, RX VrefLevel [Byte0]: 35
1538 12:11:27.378204 [Byte1]: 35
1539 12:11:27.383030
1540 12:11:27.383591 Set Vref, RX VrefLevel [Byte0]: 36
1541 12:11:27.386009 [Byte1]: 36
1542 12:11:27.390080
1543 12:11:27.390641 Set Vref, RX VrefLevel [Byte0]: 37
1544 12:11:27.392824 [Byte1]: 37
1545 12:11:27.398089
1546 12:11:27.398649 Set Vref, RX VrefLevel [Byte0]: 38
1547 12:11:27.400641 [Byte1]: 38
1548 12:11:27.405142
1549 12:11:27.405704 Set Vref, RX VrefLevel [Byte0]: 39
1550 12:11:27.408685 [Byte1]: 39
1551 12:11:27.413614
1552 12:11:27.414147 Set Vref, RX VrefLevel [Byte0]: 40
1553 12:11:27.416159 [Byte1]: 40
1554 12:11:27.420448
1555 12:11:27.420987 Set Vref, RX VrefLevel [Byte0]: 41
1556 12:11:27.423661 [Byte1]: 41
1557 12:11:27.427656
1558 12:11:27.427739 Set Vref, RX VrefLevel [Byte0]: 42
1559 12:11:27.430736 [Byte1]: 42
1560 12:11:27.435812
1561 12:11:27.435938 Set Vref, RX VrefLevel [Byte0]: 43
1562 12:11:27.438300 [Byte1]: 43
1563 12:11:27.443537
1564 12:11:27.443644 Set Vref, RX VrefLevel [Byte0]: 44
1565 12:11:27.446471 [Byte1]: 44
1566 12:11:27.450258
1567 12:11:27.450405 Set Vref, RX VrefLevel [Byte0]: 45
1568 12:11:27.453880 [Byte1]: 45
1569 12:11:27.457781
1570 12:11:27.457858 Set Vref, RX VrefLevel [Byte0]: 46
1571 12:11:27.461728 [Byte1]: 46
1572 12:11:27.465939
1573 12:11:27.466016 Set Vref, RX VrefLevel [Byte0]: 47
1574 12:11:27.468924 [Byte1]: 47
1575 12:11:27.473818
1576 12:11:27.473896 Set Vref, RX VrefLevel [Byte0]: 48
1577 12:11:27.476465 [Byte1]: 48
1578 12:11:27.481138
1579 12:11:27.481215 Set Vref, RX VrefLevel [Byte0]: 49
1580 12:11:27.484183 [Byte1]: 49
1581 12:11:27.490122
1582 12:11:27.490196 Set Vref, RX VrefLevel [Byte0]: 50
1583 12:11:27.491770 [Byte1]: 50
1584 12:11:27.496688
1585 12:11:27.496826 Set Vref, RX VrefLevel [Byte0]: 51
1586 12:11:27.499600 [Byte1]: 51
1587 12:11:27.504137
1588 12:11:27.504214 Set Vref, RX VrefLevel [Byte0]: 52
1589 12:11:27.507053 [Byte1]: 52
1590 12:11:27.511825
1591 12:11:27.511900 Set Vref, RX VrefLevel [Byte0]: 53
1592 12:11:27.515113 [Byte1]: 53
1593 12:11:27.519945
1594 12:11:27.520020 Set Vref, RX VrefLevel [Byte0]: 54
1595 12:11:27.522831 [Byte1]: 54
1596 12:11:27.527524
1597 12:11:27.527596 Set Vref, RX VrefLevel [Byte0]: 55
1598 12:11:27.529967 [Byte1]: 55
1599 12:11:27.535432
1600 12:11:27.535511 Set Vref, RX VrefLevel [Byte0]: 56
1601 12:11:27.537531 [Byte1]: 56
1602 12:11:27.543232
1603 12:11:27.543309 Set Vref, RX VrefLevel [Byte0]: 57
1604 12:11:27.545139 [Byte1]: 57
1605 12:11:27.549744
1606 12:11:27.549815 Set Vref, RX VrefLevel [Byte0]: 58
1607 12:11:27.552763 [Byte1]: 58
1608 12:11:27.558084
1609 12:11:27.558160 Set Vref, RX VrefLevel [Byte0]: 59
1610 12:11:27.561189 [Byte1]: 59
1611 12:11:27.565193
1612 12:11:27.565269 Set Vref, RX VrefLevel [Byte0]: 60
1613 12:11:27.568549 [Byte1]: 60
1614 12:11:27.573402
1615 12:11:27.573475 Set Vref, RX VrefLevel [Byte0]: 61
1616 12:11:27.576076 [Byte1]: 61
1617 12:11:27.580524
1618 12:11:27.580601 Set Vref, RX VrefLevel [Byte0]: 62
1619 12:11:27.583799 [Byte1]: 62
1620 12:11:27.588080
1621 12:11:27.588157 Set Vref, RX VrefLevel [Byte0]: 63
1622 12:11:27.591693 [Byte1]: 63
1623 12:11:27.595587
1624 12:11:27.595669 Set Vref, RX VrefLevel [Byte0]: 64
1625 12:11:27.599037 [Byte1]: 64
1626 12:11:27.604667
1627 12:11:27.604753 Set Vref, RX VrefLevel [Byte0]: 65
1628 12:11:27.607697 [Byte1]: 65
1629 12:11:27.611108
1630 12:11:27.611226 Set Vref, RX VrefLevel [Byte0]: 66
1631 12:11:27.614225 [Byte1]: 66
1632 12:11:27.618791
1633 12:11:27.618873 Set Vref, RX VrefLevel [Byte0]: 67
1634 12:11:27.622151 [Byte1]: 67
1635 12:11:27.626244
1636 12:11:27.626327 Set Vref, RX VrefLevel [Byte0]: 68
1637 12:11:27.630558 [Byte1]: 68
1638 12:11:27.633798
1639 12:11:27.633880 Set Vref, RX VrefLevel [Byte0]: 69
1640 12:11:27.637104 [Byte1]: 69
1641 12:11:27.642130
1642 12:11:27.642213 Set Vref, RX VrefLevel [Byte0]: 70
1643 12:11:27.644728 [Byte1]: 70
1644 12:11:27.649281
1645 12:11:27.649364 Set Vref, RX VrefLevel [Byte0]: 71
1646 12:11:27.652901 [Byte1]: 71
1647 12:11:27.656928
1648 12:11:27.657010 Set Vref, RX VrefLevel [Byte0]: 72
1649 12:11:27.660198 [Byte1]: 72
1650 12:11:27.664887
1651 12:11:27.664969 Set Vref, RX VrefLevel [Byte0]: 73
1652 12:11:27.667836 [Byte1]: 73
1653 12:11:27.672132
1654 12:11:27.672232 Set Vref, RX VrefLevel [Byte0]: 74
1655 12:11:27.675530 [Byte1]: 74
1656 12:11:27.680045
1657 12:11:27.680144 Set Vref, RX VrefLevel [Byte0]: 75
1658 12:11:27.683004 [Byte1]: 75
1659 12:11:27.687542
1660 12:11:27.687617 Set Vref, RX VrefLevel [Byte0]: 76
1661 12:11:27.690390 [Byte1]: 76
1662 12:11:27.694728
1663 12:11:27.694804 Set Vref, RX VrefLevel [Byte0]: 77
1664 12:11:27.698866 [Byte1]: 77
1665 12:11:27.702573
1666 12:11:27.702675 Final RX Vref Byte 0 = 57 to rank0
1667 12:11:27.706056 Final RX Vref Byte 1 = 56 to rank0
1668 12:11:27.709398 Final RX Vref Byte 0 = 57 to rank1
1669 12:11:27.713285 Final RX Vref Byte 1 = 56 to rank1==
1670 12:11:27.716549 Dram Type= 6, Freq= 0, CH_1, rank 0
1671 12:11:27.722971 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1672 12:11:27.723050 ==
1673 12:11:27.723122 DQS Delay:
1674 12:11:27.723190 DQS0 = 0, DQS1 = 0
1675 12:11:27.725848 DQM Delay:
1676 12:11:27.725945 DQM0 = 81, DQM1 = 74
1677 12:11:27.730630 DQ Delay:
1678 12:11:27.732945 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1679 12:11:27.733043 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =76
1680 12:11:27.736233 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1681 12:11:27.739368 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
1682 12:11:27.742858
1683 12:11:27.742932
1684 12:11:27.749287 [DQSOSCAuto] RK0, (LSB)MR18= 0x5454, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
1685 12:11:27.752862 CH1 RK0: MR19=606, MR18=5454
1686 12:11:27.760484 CH1_RK0: MR19=0x606, MR18=0x5454, DQSOSC=388, MR23=63, INC=98, DEC=65
1687 12:11:27.760559
1688 12:11:27.762760 ----->DramcWriteLeveling(PI) begin...
1689 12:11:27.762839 ==
1690 12:11:27.767047 Dram Type= 6, Freq= 0, CH_1, rank 1
1691 12:11:27.769607 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1692 12:11:27.769683 ==
1693 12:11:27.773149 Write leveling (Byte 0): 25 => 25
1694 12:11:27.776970 Write leveling (Byte 1): 24 => 24
1695 12:11:27.779970 DramcWriteLeveling(PI) end<-----
1696 12:11:27.780044
1697 12:11:27.780106 ==
1698 12:11:27.782936 Dram Type= 6, Freq= 0, CH_1, rank 1
1699 12:11:27.786842 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1700 12:11:27.786916 ==
1701 12:11:27.789789 [Gating] SW mode calibration
1702 12:11:27.796223 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1703 12:11:27.802704 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1704 12:11:27.807305 0 6 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
1705 12:11:27.809789 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1706 12:11:27.816169 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1707 12:11:27.819727 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1708 12:11:27.822654 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1709 12:11:27.829947 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1710 12:11:27.832963 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1711 12:11:27.835734 0 6 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
1712 12:11:27.843274 0 7 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
1713 12:11:27.845893 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1714 12:11:27.849545 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1715 12:11:27.856129 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1716 12:11:27.859195 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1717 12:11:27.862723 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1718 12:11:27.869150 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1719 12:11:27.872368 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1720 12:11:27.875576 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1721 12:11:27.882524 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 12:11:27.886833 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 12:11:27.889120 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 12:11:27.896254 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1725 12:11:27.900092 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 12:11:27.902165 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 12:11:27.905274 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 12:11:27.911808 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1729 12:11:27.915675 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1730 12:11:27.919091 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1731 12:11:27.925943 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1732 12:11:27.928939 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1733 12:11:27.932935 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1734 12:11:27.939031 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1735 12:11:27.942671 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1736 12:11:27.945971 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1737 12:11:27.948880 Total UI for P1: 0, mck2ui 16
1738 12:11:27.951893 best dqsien dly found for B0: ( 0, 9, 28)
1739 12:11:27.955895 Total UI for P1: 0, mck2ui 16
1740 12:11:27.958591 best dqsien dly found for B1: ( 0, 9, 30)
1741 12:11:27.961996 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1742 12:11:27.965598 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1743 12:11:27.965706
1744 12:11:27.971956 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1745 12:11:27.975438 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1746 12:11:27.978373 [Gating] SW calibration Done
1747 12:11:27.978445 ==
1748 12:11:27.981741 Dram Type= 6, Freq= 0, CH_1, rank 1
1749 12:11:27.985225 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1750 12:11:27.985296 ==
1751 12:11:27.985358 RX Vref Scan: 0
1752 12:11:27.985419
1753 12:11:27.989290 RX Vref 0 -> 0, step: 1
1754 12:11:27.989356
1755 12:11:27.992326 RX Delay -130 -> 252, step: 16
1756 12:11:27.995417 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1757 12:11:27.998619 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1758 12:11:28.005073 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1759 12:11:28.008696 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1760 12:11:28.012036 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1761 12:11:28.015429 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1762 12:11:28.018794 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1763 12:11:28.025742 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1764 12:11:28.028559 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1765 12:11:28.032197 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1766 12:11:28.035964 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1767 12:11:28.038496 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1768 12:11:28.046039 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1769 12:11:28.049051 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1770 12:11:28.052719 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1771 12:11:28.055339 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1772 12:11:28.055422 ==
1773 12:11:28.058996 Dram Type= 6, Freq= 0, CH_1, rank 1
1774 12:11:28.062135 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1775 12:11:28.065590 ==
1776 12:11:28.065690 DQS Delay:
1777 12:11:28.065758 DQS0 = 0, DQS1 = 0
1778 12:11:28.069221 DQM Delay:
1779 12:11:28.069319 DQM0 = 85, DQM1 = 75
1780 12:11:28.071822 DQ Delay:
1781 12:11:28.075541 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1782 12:11:28.075623 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1783 12:11:28.079369 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1784 12:11:28.082131 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1785 12:11:28.085826
1786 12:11:28.085908
1787 12:11:28.085974 ==
1788 12:11:28.089569 Dram Type= 6, Freq= 0, CH_1, rank 1
1789 12:11:28.092378 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1790 12:11:28.092461 ==
1791 12:11:28.092527
1792 12:11:28.092587
1793 12:11:28.096184 TX Vref Scan disable
1794 12:11:28.096267 == TX Byte 0 ==
1795 12:11:28.102001 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1796 12:11:28.105273 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1797 12:11:28.105356 == TX Byte 1 ==
1798 12:11:28.111933 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1799 12:11:28.115064 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1800 12:11:28.115139 ==
1801 12:11:28.118697 Dram Type= 6, Freq= 0, CH_1, rank 1
1802 12:11:28.122240 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1803 12:11:28.122340 ==
1804 12:11:28.135673 TX Vref=22, minBit 8, minWin=27, winSum=449
1805 12:11:28.139499 TX Vref=24, minBit 8, minWin=27, winSum=453
1806 12:11:28.142273 TX Vref=26, minBit 8, minWin=27, winSum=456
1807 12:11:28.145333 TX Vref=28, minBit 0, minWin=28, winSum=456
1808 12:11:28.149375 TX Vref=30, minBit 9, minWin=27, winSum=456
1809 12:11:28.156204 TX Vref=32, minBit 9, minWin=27, winSum=453
1810 12:11:28.158667 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 28
1811 12:11:28.158741
1812 12:11:28.163344 Final TX Range 1 Vref 28
1813 12:11:28.163442
1814 12:11:28.163532 ==
1815 12:11:28.165412 Dram Type= 6, Freq= 0, CH_1, rank 1
1816 12:11:28.168886 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1817 12:11:28.168961 ==
1818 12:11:28.169023
1819 12:11:28.172241
1820 12:11:28.172314 TX Vref Scan disable
1821 12:11:28.176077 == TX Byte 0 ==
1822 12:11:28.178684 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1823 12:11:28.183206 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1824 12:11:28.185383 == TX Byte 1 ==
1825 12:11:28.189307 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1826 12:11:28.191940 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1827 12:11:28.195612
1828 12:11:28.195711 [DATLAT]
1829 12:11:28.195803 Freq=800, CH1 RK1
1830 12:11:28.195892
1831 12:11:28.198809 DATLAT Default: 0x9
1832 12:11:28.198902 0, 0xFFFF, sum = 0
1833 12:11:28.202355 1, 0xFFFF, sum = 0
1834 12:11:28.202453 2, 0xFFFF, sum = 0
1835 12:11:28.205306 3, 0xFFFF, sum = 0
1836 12:11:28.205374 4, 0xFFFF, sum = 0
1837 12:11:28.208483 5, 0xFFFF, sum = 0
1838 12:11:28.208550 6, 0xFFFF, sum = 0
1839 12:11:28.212758 7, 0xFFFF, sum = 0
1840 12:11:28.212826 8, 0x0, sum = 1
1841 12:11:28.216075 9, 0x0, sum = 2
1842 12:11:28.216143 10, 0x0, sum = 3
1843 12:11:28.218561 11, 0x0, sum = 4
1844 12:11:28.218656 best_step = 9
1845 12:11:28.218744
1846 12:11:28.218829 ==
1847 12:11:28.222518 Dram Type= 6, Freq= 0, CH_1, rank 1
1848 12:11:28.229308 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1849 12:11:28.229383 ==
1850 12:11:28.229445 RX Vref Scan: 0
1851 12:11:28.229507
1852 12:11:28.232283 RX Vref 0 -> 0, step: 1
1853 12:11:28.232367
1854 12:11:28.236008 RX Delay -111 -> 252, step: 8
1855 12:11:28.238807 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1856 12:11:28.242252 iDelay=217, Bit 1, Center 76 (-39 ~ 192) 232
1857 12:11:28.248797 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1858 12:11:28.251771 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1859 12:11:28.255872 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1860 12:11:28.258701 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1861 12:11:28.262137 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1862 12:11:28.265496 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1863 12:11:28.272686 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1864 12:11:28.276106 iDelay=217, Bit 9, Center 64 (-55 ~ 184) 240
1865 12:11:28.279053 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1866 12:11:28.281808 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1867 12:11:28.288407 iDelay=217, Bit 12, Center 88 (-31 ~ 208) 240
1868 12:11:28.292244 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1869 12:11:28.295770 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1870 12:11:28.298390 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1871 12:11:28.298463 ==
1872 12:11:28.301767 Dram Type= 6, Freq= 0, CH_1, rank 1
1873 12:11:28.308585 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1874 12:11:28.308725 ==
1875 12:11:28.308826 DQS Delay:
1876 12:11:28.308887 DQS0 = 0, DQS1 = 0
1877 12:11:28.312732 DQM Delay:
1878 12:11:28.312815 DQM0 = 84, DQM1 = 75
1879 12:11:28.315072 DQ Delay:
1880 12:11:28.318863 DQ0 =84, DQ1 =76, DQ2 =76, DQ3 =84
1881 12:11:28.318946 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =80
1882 12:11:28.322108 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1883 12:11:28.324883 DQ12 =88, DQ13 =84, DQ14 =80, DQ15 =84
1884 12:11:28.328915
1885 12:11:28.328997
1886 12:11:28.335365 [DQSOSCAuto] RK1, (LSB)MR18= 0x3636, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1887 12:11:28.338649 CH1 RK1: MR19=606, MR18=3636
1888 12:11:28.345765 CH1_RK1: MR19=0x606, MR18=0x3636, DQSOSC=396, MR23=63, INC=94, DEC=62
1889 12:11:28.348457 [RxdqsGatingPostProcess] freq 800
1890 12:11:28.351766 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1891 12:11:28.354896 Pre-setting of DQS Precalculation
1892 12:11:28.362075 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1893 12:11:28.368830 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1894 12:11:28.375397 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1895 12:11:28.375482
1896 12:11:28.375548
1897 12:11:28.378355 [Calibration Summary] 1600 Mbps
1898 12:11:28.378439 CH 0, Rank 0
1899 12:11:28.381908 SW Impedance : PASS
1900 12:11:28.381992 DUTY Scan : NO K
1901 12:11:28.386056 ZQ Calibration : PASS
1902 12:11:28.388183 Jitter Meter : NO K
1903 12:11:28.388265 CBT Training : PASS
1904 12:11:28.391799 Write leveling : PASS
1905 12:11:28.395826 RX DQS gating : PASS
1906 12:11:28.395916 RX DQ/DQS(RDDQC) : PASS
1907 12:11:28.398616 TX DQ/DQS : PASS
1908 12:11:28.402333 RX DATLAT : PASS
1909 12:11:28.402416 RX DQ/DQS(Engine): PASS
1910 12:11:28.405318 TX OE : NO K
1911 12:11:28.405401 All Pass.
1912 12:11:28.405467
1913 12:11:28.408640 CH 0, Rank 1
1914 12:11:28.408763 SW Impedance : PASS
1915 12:11:28.412001 DUTY Scan : NO K
1916 12:11:28.414810 ZQ Calibration : PASS
1917 12:11:28.414893 Jitter Meter : NO K
1918 12:11:28.418496 CBT Training : PASS
1919 12:11:28.418578 Write leveling : PASS
1920 12:11:28.421601 RX DQS gating : PASS
1921 12:11:28.425114 RX DQ/DQS(RDDQC) : PASS
1922 12:11:28.425197 TX DQ/DQS : PASS
1923 12:11:28.429049 RX DATLAT : PASS
1924 12:11:28.431895 RX DQ/DQS(Engine): PASS
1925 12:11:28.431978 TX OE : NO K
1926 12:11:28.435151 All Pass.
1927 12:11:28.435233
1928 12:11:28.435299 CH 1, Rank 0
1929 12:11:28.439220 SW Impedance : PASS
1930 12:11:28.439303 DUTY Scan : NO K
1931 12:11:28.441493 ZQ Calibration : PASS
1932 12:11:28.445104 Jitter Meter : NO K
1933 12:11:28.445187 CBT Training : PASS
1934 12:11:28.448246 Write leveling : PASS
1935 12:11:28.452347 RX DQS gating : PASS
1936 12:11:28.452429 RX DQ/DQS(RDDQC) : PASS
1937 12:11:28.455136 TX DQ/DQS : PASS
1938 12:11:28.458230 RX DATLAT : PASS
1939 12:11:28.458312 RX DQ/DQS(Engine): PASS
1940 12:11:28.462130 TX OE : NO K
1941 12:11:28.462210 All Pass.
1942 12:11:28.462278
1943 12:11:28.465195 CH 1, Rank 1
1944 12:11:28.465296 SW Impedance : PASS
1945 12:11:28.468874 DUTY Scan : NO K
1946 12:11:28.468973 ZQ Calibration : PASS
1947 12:11:28.471957 Jitter Meter : NO K
1948 12:11:28.475598 CBT Training : PASS
1949 12:11:28.475702 Write leveling : PASS
1950 12:11:28.478723 RX DQS gating : PASS
1951 12:11:28.482701 RX DQ/DQS(RDDQC) : PASS
1952 12:11:28.482786 TX DQ/DQS : PASS
1953 12:11:28.486572 RX DATLAT : PASS
1954 12:11:28.488762 RX DQ/DQS(Engine): PASS
1955 12:11:28.488845 TX OE : NO K
1956 12:11:28.492163 All Pass.
1957 12:11:28.492244
1958 12:11:28.492308 DramC Write-DBI off
1959 12:11:28.495074 PER_BANK_REFRESH: Hybrid Mode
1960 12:11:28.495155 TX_TRACKING: ON
1961 12:11:28.498609 [GetDramInforAfterCalByMRR] Vendor 6.
1962 12:11:28.505913 [GetDramInforAfterCalByMRR] Revision 606.
1963 12:11:28.508286 [GetDramInforAfterCalByMRR] Revision 2 0.
1964 12:11:28.508367 MR0 0x3939
1965 12:11:28.508432 MR8 0x1111
1966 12:11:28.512447 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1967 12:11:28.512555
1968 12:11:28.515836 MR0 0x3939
1969 12:11:28.515937 MR8 0x1111
1970 12:11:28.518326 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1971 12:11:28.518408
1972 12:11:28.528745 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1973 12:11:28.531984 [FAST_K] Save calibration result to emmc
1974 12:11:28.535981 [FAST_K] Save calibration result to emmc
1975 12:11:28.538152 dram_init: config_dvfs: 1
1976 12:11:28.541694 dramc_set_vcore_voltage set vcore to 662500
1977 12:11:28.545438 Read voltage for 1200, 2
1978 12:11:28.545519 Vio18 = 0
1979 12:11:28.545584 Vcore = 662500
1980 12:11:28.548653 Vdram = 0
1981 12:11:28.548757 Vddq = 0
1982 12:11:28.548822 Vmddr = 0
1983 12:11:28.554978 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1984 12:11:28.558676 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1985 12:11:28.562087 MEM_TYPE=3, freq_sel=15
1986 12:11:28.565565 sv_algorithm_assistance_LP4_1600
1987 12:11:28.568665 ============ PULL DRAM RESETB DOWN ============
1988 12:11:28.572572 ========== PULL DRAM RESETB DOWN end =========
1989 12:11:28.578283 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1990 12:11:28.583137 ===================================
1991 12:11:28.583218 LPDDR4 DRAM CONFIGURATION
1992 12:11:28.585229 ===================================
1993 12:11:28.588389 EX_ROW_EN[0] = 0x0
1994 12:11:28.592609 EX_ROW_EN[1] = 0x0
1995 12:11:28.592690 LP4Y_EN = 0x0
1996 12:11:28.594871 WORK_FSP = 0x0
1997 12:11:28.594952 WL = 0x4
1998 12:11:28.598756 RL = 0x4
1999 12:11:28.598838 BL = 0x2
2000 12:11:28.602029 RPST = 0x0
2001 12:11:28.602110 RD_PRE = 0x0
2002 12:11:28.604826 WR_PRE = 0x1
2003 12:11:28.604907 WR_PST = 0x0
2004 12:11:28.608386 DBI_WR = 0x0
2005 12:11:28.608468 DBI_RD = 0x0
2006 12:11:28.611626 OTF = 0x1
2007 12:11:28.614911 ===================================
2008 12:11:28.618133 ===================================
2009 12:11:28.618215 ANA top config
2010 12:11:28.621755 ===================================
2011 12:11:28.625593 DLL_ASYNC_EN = 0
2012 12:11:28.628406 ALL_SLAVE_EN = 0
2013 12:11:28.628487 NEW_RANK_MODE = 1
2014 12:11:28.631780 DLL_IDLE_MODE = 1
2015 12:11:28.634661 LP45_APHY_COMB_EN = 1
2016 12:11:28.638442 TX_ODT_DIS = 1
2017 12:11:28.641401 NEW_8X_MODE = 1
2018 12:11:28.644924 ===================================
2019 12:11:28.648325 ===================================
2020 12:11:28.648409 data_rate = 2400
2021 12:11:28.651194 CKR = 1
2022 12:11:28.655357 DQ_P2S_RATIO = 8
2023 12:11:28.658266 ===================================
2024 12:11:28.661999 CA_P2S_RATIO = 8
2025 12:11:28.665804 DQ_CA_OPEN = 0
2026 12:11:28.668671 DQ_SEMI_OPEN = 0
2027 12:11:28.668807 CA_SEMI_OPEN = 0
2028 12:11:28.671901 CA_FULL_RATE = 0
2029 12:11:28.675368 DQ_CKDIV4_EN = 0
2030 12:11:28.678668 CA_CKDIV4_EN = 0
2031 12:11:28.683043 CA_PREDIV_EN = 0
2032 12:11:28.685036 PH8_DLY = 17
2033 12:11:28.685120 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2034 12:11:28.688231 DQ_AAMCK_DIV = 4
2035 12:11:28.692322 CA_AAMCK_DIV = 4
2036 12:11:28.695545 CA_ADMCK_DIV = 4
2037 12:11:28.698675 DQ_TRACK_CA_EN = 0
2038 12:11:28.702138 CA_PICK = 1200
2039 12:11:28.704944 CA_MCKIO = 1200
2040 12:11:28.705025 MCKIO_SEMI = 0
2041 12:11:28.708353 PLL_FREQ = 2366
2042 12:11:28.711759 DQ_UI_PI_RATIO = 32
2043 12:11:28.714877 CA_UI_PI_RATIO = 0
2044 12:11:28.718249 ===================================
2045 12:11:28.721591 ===================================
2046 12:11:28.724697 memory_type:LPDDR4
2047 12:11:28.724803 GP_NUM : 10
2048 12:11:28.728260 SRAM_EN : 1
2049 12:11:28.731623 MD32_EN : 0
2050 12:11:28.734689 ===================================
2051 12:11:28.734772 [ANA_INIT] >>>>>>>>>>>>>>
2052 12:11:28.737942 <<<<<< [CONFIGURE PHASE]: ANA_TX
2053 12:11:28.741448 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2054 12:11:28.744809 ===================================
2055 12:11:28.748380 data_rate = 2400,PCW = 0X5b00
2056 12:11:28.751505 ===================================
2057 12:11:28.755632 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2058 12:11:28.761564 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2059 12:11:28.764936 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2060 12:11:28.771281 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2061 12:11:28.775133 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2062 12:11:28.778398 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2063 12:11:28.778481 [ANA_INIT] flow start
2064 12:11:28.781282 [ANA_INIT] PLL >>>>>>>>
2065 12:11:28.784459 [ANA_INIT] PLL <<<<<<<<
2066 12:11:28.784545 [ANA_INIT] MIDPI >>>>>>>>
2067 12:11:28.788038 [ANA_INIT] MIDPI <<<<<<<<
2068 12:11:28.791361 [ANA_INIT] DLL >>>>>>>>
2069 12:11:28.791443 [ANA_INIT] DLL <<<<<<<<
2070 12:11:28.794870 [ANA_INIT] flow end
2071 12:11:28.798109 ============ LP4 DIFF to SE enter ============
2072 12:11:28.801252 ============ LP4 DIFF to SE exit ============
2073 12:11:28.805018 [ANA_INIT] <<<<<<<<<<<<<
2074 12:11:28.807721 [Flow] Enable top DCM control >>>>>
2075 12:11:28.811286 [Flow] Enable top DCM control <<<<<
2076 12:11:28.814789 Enable DLL master slave shuffle
2077 12:11:28.821030 ==============================================================
2078 12:11:28.821107 Gating Mode config
2079 12:11:28.828075 ==============================================================
2080 12:11:28.831157 Config description:
2081 12:11:28.837940 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2082 12:11:28.844669 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2083 12:11:28.851049 SELPH_MODE 0: By rank 1: By Phase
2084 12:11:28.857371 ==============================================================
2085 12:11:28.857448 GAT_TRACK_EN = 1
2086 12:11:28.861457 RX_GATING_MODE = 2
2087 12:11:28.865080 RX_GATING_TRACK_MODE = 2
2088 12:11:28.867732 SELPH_MODE = 1
2089 12:11:28.871173 PICG_EARLY_EN = 1
2090 12:11:28.874183 VALID_LAT_VALUE = 1
2091 12:11:28.881612 ==============================================================
2092 12:11:28.884142 Enter into Gating configuration >>>>
2093 12:11:28.887720 Exit from Gating configuration <<<<
2094 12:11:28.890942 Enter into DVFS_PRE_config >>>>>
2095 12:11:28.901386 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2096 12:11:28.904924 Exit from DVFS_PRE_config <<<<<
2097 12:11:28.907956 Enter into PICG configuration >>>>
2098 12:11:28.911982 Exit from PICG configuration <<<<
2099 12:11:28.914494 [RX_INPUT] configuration >>>>>
2100 12:11:28.914567 [RX_INPUT] configuration <<<<<
2101 12:11:28.920612 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2102 12:11:28.927440 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2103 12:11:28.930955 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2104 12:11:28.937474 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2105 12:11:28.944162 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2106 12:11:28.950859 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2107 12:11:28.954228 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2108 12:11:28.957780 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2109 12:11:28.964173 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2110 12:11:28.967943 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2111 12:11:28.971232 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2112 12:11:28.974306 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2113 12:11:28.978566 ===================================
2114 12:11:28.981109 LPDDR4 DRAM CONFIGURATION
2115 12:11:28.984232 ===================================
2116 12:11:28.987540 EX_ROW_EN[0] = 0x0
2117 12:11:28.987638 EX_ROW_EN[1] = 0x0
2118 12:11:28.990867 LP4Y_EN = 0x0
2119 12:11:28.990963 WORK_FSP = 0x0
2120 12:11:28.994493 WL = 0x4
2121 12:11:28.994590 RL = 0x4
2122 12:11:28.997843 BL = 0x2
2123 12:11:28.997922 RPST = 0x0
2124 12:11:29.000756 RD_PRE = 0x0
2125 12:11:29.000829 WR_PRE = 0x1
2126 12:11:29.004885 WR_PST = 0x0
2127 12:11:29.004953 DBI_WR = 0x0
2128 12:11:29.007588 DBI_RD = 0x0
2129 12:11:29.011148 OTF = 0x1
2130 12:11:29.011224 ===================================
2131 12:11:29.017441 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2132 12:11:29.021834 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2133 12:11:29.024300 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2134 12:11:29.028065 ===================================
2135 12:11:29.031039 LPDDR4 DRAM CONFIGURATION
2136 12:11:29.034673 ===================================
2137 12:11:29.038522 EX_ROW_EN[0] = 0x10
2138 12:11:29.038625 EX_ROW_EN[1] = 0x0
2139 12:11:29.040988 LP4Y_EN = 0x0
2140 12:11:29.041063 WORK_FSP = 0x0
2141 12:11:29.044487 WL = 0x4
2142 12:11:29.044581 RL = 0x4
2143 12:11:29.047930 BL = 0x2
2144 12:11:29.047998 RPST = 0x0
2145 12:11:29.050839 RD_PRE = 0x0
2146 12:11:29.050936 WR_PRE = 0x1
2147 12:11:29.054029 WR_PST = 0x0
2148 12:11:29.054122 DBI_WR = 0x0
2149 12:11:29.057235 DBI_RD = 0x0
2150 12:11:29.057303 OTF = 0x1
2151 12:11:29.061155 ===================================
2152 12:11:29.067634 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2153 12:11:29.067720 ==
2154 12:11:29.070800 Dram Type= 6, Freq= 0, CH_0, rank 0
2155 12:11:29.077902 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2156 12:11:29.077986 ==
2157 12:11:29.078052 [Duty_Offset_Calibration]
2158 12:11:29.080832 B0:0 B1:2 CA:1
2159 12:11:29.080915
2160 12:11:29.084730 [DutyScan_Calibration_Flow] k_type=0
2161 12:11:29.093133
2162 12:11:29.093218 ==CLK 0==
2163 12:11:29.095872 Final CLK duty delay cell = 0
2164 12:11:29.099814 [0] MAX Duty = 5093%(X100), DQS PI = 12
2165 12:11:29.102879 [0] MIN Duty = 4938%(X100), DQS PI = 52
2166 12:11:29.102963 [0] AVG Duty = 5015%(X100)
2167 12:11:29.106443
2168 12:11:29.109370 CH0 CLK Duty spec in!! Max-Min= 155%
2169 12:11:29.112904 [DutyScan_Calibration_Flow] ====Done====
2170 12:11:29.112987
2171 12:11:29.115673 [DutyScan_Calibration_Flow] k_type=1
2172 12:11:29.132129
2173 12:11:29.132211 ==DQS 0 ==
2174 12:11:29.135807 Final DQS duty delay cell = 0
2175 12:11:29.139274 [0] MAX Duty = 5125%(X100), DQS PI = 28
2176 12:11:29.142230 [0] MIN Duty = 5031%(X100), DQS PI = 6
2177 12:11:29.142313 [0] AVG Duty = 5078%(X100)
2178 12:11:29.146027
2179 12:11:29.146109 ==DQS 1 ==
2180 12:11:29.149197 Final DQS duty delay cell = 0
2181 12:11:29.152261 [0] MAX Duty = 5031%(X100), DQS PI = 54
2182 12:11:29.155873 [0] MIN Duty = 4906%(X100), DQS PI = 16
2183 12:11:29.155957 [0] AVG Duty = 4968%(X100)
2184 12:11:29.159134
2185 12:11:29.163039 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2186 12:11:29.163123
2187 12:11:29.165963 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2188 12:11:29.168821 [DutyScan_Calibration_Flow] ====Done====
2189 12:11:29.168903
2190 12:11:29.171974 [DutyScan_Calibration_Flow] k_type=3
2191 12:11:29.189212
2192 12:11:29.189299 ==DQM 0 ==
2193 12:11:29.193020 Final DQM duty delay cell = 0
2194 12:11:29.196372 [0] MAX Duty = 5156%(X100), DQS PI = 22
2195 12:11:29.199310 [0] MIN Duty = 4969%(X100), DQS PI = 54
2196 12:11:29.199381 [0] AVG Duty = 5062%(X100)
2197 12:11:29.202635
2198 12:11:29.202706 ==DQM 1 ==
2199 12:11:29.205841 Final DQM duty delay cell = 4
2200 12:11:29.209082 [4] MAX Duty = 5187%(X100), DQS PI = 54
2201 12:11:29.212204 [4] MIN Duty = 5000%(X100), DQS PI = 18
2202 12:11:29.215681 [4] AVG Duty = 5093%(X100)
2203 12:11:29.215797
2204 12:11:29.219726 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2205 12:11:29.219801
2206 12:11:29.222451 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2207 12:11:29.225914 [DutyScan_Calibration_Flow] ====Done====
2208 12:11:29.226012
2209 12:11:29.229918 [DutyScan_Calibration_Flow] k_type=2
2210 12:11:29.244298
2211 12:11:29.244404 ==DQ 0 ==
2212 12:11:29.248784 Final DQ duty delay cell = -4
2213 12:11:29.251023 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2214 12:11:29.255133 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2215 12:11:29.257626 [-4] AVG Duty = 4937%(X100)
2216 12:11:29.257704
2217 12:11:29.257767 ==DQ 1 ==
2218 12:11:29.261203 Final DQ duty delay cell = -4
2219 12:11:29.264086 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2220 12:11:29.267908 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2221 12:11:29.271049 [-4] AVG Duty = 4969%(X100)
2222 12:11:29.271150
2223 12:11:29.274023 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2224 12:11:29.274121
2225 12:11:29.278092 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2226 12:11:29.280696 [DutyScan_Calibration_Flow] ====Done====
2227 12:11:29.280792 ==
2228 12:11:29.284052 Dram Type= 6, Freq= 0, CH_1, rank 0
2229 12:11:29.287388 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2230 12:11:29.287485 ==
2231 12:11:29.290607 [Duty_Offset_Calibration]
2232 12:11:29.290707 B0:0 B1:4 CA:-5
2233 12:11:29.290797
2234 12:11:29.293841 [DutyScan_Calibration_Flow] k_type=0
2235 12:11:29.304623
2236 12:11:29.304746 ==CLK 0==
2237 12:11:29.307974 Final CLK duty delay cell = 0
2238 12:11:29.311864 [0] MAX Duty = 5094%(X100), DQS PI = 24
2239 12:11:29.314431 [0] MIN Duty = 4875%(X100), DQS PI = 48
2240 12:11:29.314528 [0] AVG Duty = 4984%(X100)
2241 12:11:29.318262
2242 12:11:29.321563 CH1 CLK Duty spec in!! Max-Min= 219%
2243 12:11:29.324511 [DutyScan_Calibration_Flow] ====Done====
2244 12:11:29.324606
2245 12:11:29.327668 [DutyScan_Calibration_Flow] k_type=1
2246 12:11:29.343185
2247 12:11:29.343289 ==DQS 0 ==
2248 12:11:29.346596 Final DQS duty delay cell = 0
2249 12:11:29.349522 [0] MAX Duty = 5125%(X100), DQS PI = 16
2250 12:11:29.353362 [0] MIN Duty = 4875%(X100), DQS PI = 40
2251 12:11:29.356636 [0] AVG Duty = 5000%(X100)
2252 12:11:29.356768
2253 12:11:29.356837 ==DQS 1 ==
2254 12:11:29.360216 Final DQS duty delay cell = -4
2255 12:11:29.363339 [-4] MAX Duty = 5000%(X100), DQS PI = 4
2256 12:11:29.366303 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2257 12:11:29.369765 [-4] AVG Duty = 4953%(X100)
2258 12:11:29.369860
2259 12:11:29.372883 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2260 12:11:29.372979
2261 12:11:29.377224 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2262 12:11:29.379675 [DutyScan_Calibration_Flow] ====Done====
2263 12:11:29.379776
2264 12:11:29.382740 [DutyScan_Calibration_Flow] k_type=3
2265 12:11:29.398203
2266 12:11:29.398280 ==DQM 0 ==
2267 12:11:29.401519 Final DQM duty delay cell = -4
2268 12:11:29.404635 [-4] MAX Duty = 5094%(X100), DQS PI = 30
2269 12:11:29.408603 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2270 12:11:29.411497 [-4] AVG Duty = 4969%(X100)
2271 12:11:29.411579
2272 12:11:29.411644 ==DQM 1 ==
2273 12:11:29.415115 Final DQM duty delay cell = -4
2274 12:11:29.417978 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2275 12:11:29.421422 [-4] MIN Duty = 4875%(X100), DQS PI = 60
2276 12:11:29.425011 [-4] AVG Duty = 4968%(X100)
2277 12:11:29.425093
2278 12:11:29.428481 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2279 12:11:29.428563
2280 12:11:29.431703 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2281 12:11:29.435255 [DutyScan_Calibration_Flow] ====Done====
2282 12:11:29.435336
2283 12:11:29.437767 [DutyScan_Calibration_Flow] k_type=2
2284 12:11:29.455898
2285 12:11:29.455983 ==DQ 0 ==
2286 12:11:29.458757 Final DQ duty delay cell = 0
2287 12:11:29.461773 [0] MAX Duty = 5062%(X100), DQS PI = 0
2288 12:11:29.466065 [0] MIN Duty = 4938%(X100), DQS PI = 44
2289 12:11:29.466141 [0] AVG Duty = 5000%(X100)
2290 12:11:29.466205
2291 12:11:29.468613 ==DQ 1 ==
2292 12:11:29.472658 Final DQ duty delay cell = 0
2293 12:11:29.475451 [0] MAX Duty = 5000%(X100), DQS PI = 8
2294 12:11:29.480081 [0] MIN Duty = 4875%(X100), DQS PI = 0
2295 12:11:29.480178 [0] AVG Duty = 4937%(X100)
2296 12:11:29.480275
2297 12:11:29.482957 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2298 12:11:29.483055
2299 12:11:29.485689 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2300 12:11:29.492211 [DutyScan_Calibration_Flow] ====Done====
2301 12:11:29.495680 nWR fixed to 30
2302 12:11:29.495753 [ModeRegInit_LP4] CH0 RK0
2303 12:11:29.499455 [ModeRegInit_LP4] CH0 RK1
2304 12:11:29.501893 [ModeRegInit_LP4] CH1 RK0
2305 12:11:29.501964 [ModeRegInit_LP4] CH1 RK1
2306 12:11:29.505319 match AC timing 6
2307 12:11:29.508423 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2308 12:11:29.512345 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2309 12:11:29.518985 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2310 12:11:29.521751 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2311 12:11:29.528874 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2312 12:11:29.528949 ==
2313 12:11:29.531863 Dram Type= 6, Freq= 0, CH_0, rank 0
2314 12:11:29.535099 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2315 12:11:29.535173 ==
2316 12:11:29.541844 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2317 12:11:29.545503 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2318 12:11:29.555331 [CA 0] Center 39 (9~70) winsize 62
2319 12:11:29.557960 [CA 1] Center 39 (8~70) winsize 63
2320 12:11:29.561331 [CA 2] Center 36 (5~67) winsize 63
2321 12:11:29.565133 [CA 3] Center 35 (4~66) winsize 63
2322 12:11:29.568332 [CA 4] Center 34 (3~65) winsize 63
2323 12:11:29.571858 [CA 5] Center 33 (3~64) winsize 62
2324 12:11:29.571941
2325 12:11:29.575233 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2326 12:11:29.575340
2327 12:11:29.579071 [CATrainingPosCal] consider 1 rank data
2328 12:11:29.582233 u2DelayCellTimex100 = 270/100 ps
2329 12:11:29.585334 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2330 12:11:29.588485 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2331 12:11:29.591704 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2332 12:11:29.598543 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2333 12:11:29.601628 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2334 12:11:29.605625 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2335 12:11:29.605727
2336 12:11:29.608689 CA PerBit enable=1, Macro0, CA PI delay=33
2337 12:11:29.608795
2338 12:11:29.612059 [CBTSetCACLKResult] CA Dly = 33
2339 12:11:29.612165 CS Dly: 7 (0~38)
2340 12:11:29.612257 ==
2341 12:11:29.615558 Dram Type= 6, Freq= 0, CH_0, rank 1
2342 12:11:29.622163 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2343 12:11:29.622269 ==
2344 12:11:29.625633 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2345 12:11:29.631945 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2346 12:11:29.640318 [CA 0] Center 39 (8~70) winsize 63
2347 12:11:29.643559 [CA 1] Center 39 (8~70) winsize 63
2348 12:11:29.647068 [CA 2] Center 36 (5~67) winsize 63
2349 12:11:29.650010 [CA 3] Center 35 (4~66) winsize 63
2350 12:11:29.653774 [CA 4] Center 33 (3~64) winsize 62
2351 12:11:29.656893 [CA 5] Center 34 (3~65) winsize 63
2352 12:11:29.656965
2353 12:11:29.660001 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2354 12:11:29.660097
2355 12:11:29.663555 [CATrainingPosCal] consider 2 rank data
2356 12:11:29.667144 u2DelayCellTimex100 = 270/100 ps
2357 12:11:29.670797 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2358 12:11:29.673598 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2359 12:11:29.680149 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2360 12:11:29.683355 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2361 12:11:29.686973 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2362 12:11:29.690524 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2363 12:11:29.690605
2364 12:11:29.694020 CA PerBit enable=1, Macro0, CA PI delay=33
2365 12:11:29.694101
2366 12:11:29.697657 [CBTSetCACLKResult] CA Dly = 33
2367 12:11:29.697737 CS Dly: 7 (0~39)
2368 12:11:29.697802
2369 12:11:29.700251 ----->DramcWriteLeveling(PI) begin...
2370 12:11:29.704003 ==
2371 12:11:29.706991 Dram Type= 6, Freq= 0, CH_0, rank 0
2372 12:11:29.710457 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2373 12:11:29.710538 ==
2374 12:11:29.713477 Write leveling (Byte 0): 28 => 28
2375 12:11:29.716658 Write leveling (Byte 1): 25 => 25
2376 12:11:29.720481 DramcWriteLeveling(PI) end<-----
2377 12:11:29.720561
2378 12:11:29.720625 ==
2379 12:11:29.723863 Dram Type= 6, Freq= 0, CH_0, rank 0
2380 12:11:29.727086 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2381 12:11:29.727167 ==
2382 12:11:29.729966 [Gating] SW mode calibration
2383 12:11:29.736679 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2384 12:11:29.743398 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2385 12:11:29.747398 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2386 12:11:29.750176 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2387 12:11:29.756975 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2388 12:11:29.759774 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2389 12:11:29.763249 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2390 12:11:29.766714 0 11 20 | B1->B0 | 2d2d 2c2c | 1 0 | (1 0) (0 0)
2391 12:11:29.773475 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2392 12:11:29.776682 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2393 12:11:29.780618 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2394 12:11:29.786612 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2395 12:11:29.790081 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2396 12:11:29.792991 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2397 12:11:29.800369 0 12 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2398 12:11:29.804050 0 12 20 | B1->B0 | 3434 3a3a | 0 0 | (0 0) (0 0)
2399 12:11:29.807184 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2400 12:11:29.813176 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2401 12:11:29.816672 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2402 12:11:29.820312 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2403 12:11:29.826428 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2404 12:11:29.829882 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2405 12:11:29.833335 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2406 12:11:29.840600 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2407 12:11:29.843569 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 12:11:29.847097 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 12:11:29.853047 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 12:11:29.856452 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 12:11:29.859893 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 12:11:29.866469 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 12:11:29.869856 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 12:11:29.873194 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 12:11:29.880176 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2416 12:11:29.883219 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2417 12:11:29.886416 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2418 12:11:29.889513 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2419 12:11:29.897274 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2420 12:11:29.900603 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2421 12:11:29.902951 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2422 12:11:29.910144 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2423 12:11:29.913174 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2424 12:11:29.916672 Total UI for P1: 0, mck2ui 16
2425 12:11:29.919952 best dqsien dly found for B0: ( 0, 15, 20)
2426 12:11:29.923089 Total UI for P1: 0, mck2ui 16
2427 12:11:29.926526 best dqsien dly found for B1: ( 0, 15, 20)
2428 12:11:29.930118 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2429 12:11:29.933239 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2430 12:11:29.933322
2431 12:11:29.936859 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2432 12:11:29.939861 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2433 12:11:29.943085 [Gating] SW calibration Done
2434 12:11:29.943168 ==
2435 12:11:29.947157 Dram Type= 6, Freq= 0, CH_0, rank 0
2436 12:11:29.949868 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2437 12:11:29.953731 ==
2438 12:11:29.953814 RX Vref Scan: 0
2439 12:11:29.953881
2440 12:11:29.956734 RX Vref 0 -> 0, step: 1
2441 12:11:29.956860
2442 12:11:29.960108 RX Delay -40 -> 252, step: 8
2443 12:11:29.963651 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2444 12:11:29.967095 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2445 12:11:29.970562 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2446 12:11:29.973342 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2447 12:11:29.980043 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2448 12:11:29.982939 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2449 12:11:29.986456 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2450 12:11:29.989638 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2451 12:11:29.993728 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2452 12:11:29.997087 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2453 12:11:30.003936 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2454 12:11:30.007016 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2455 12:11:30.010233 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2456 12:11:30.013272 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2457 12:11:30.020322 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2458 12:11:30.023578 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2459 12:11:30.023661 ==
2460 12:11:30.027067 Dram Type= 6, Freq= 0, CH_0, rank 0
2461 12:11:30.029685 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2462 12:11:30.029769 ==
2463 12:11:30.029835 DQS Delay:
2464 12:11:30.032916 DQS0 = 0, DQS1 = 0
2465 12:11:30.032999 DQM Delay:
2466 12:11:30.036255 DQM0 = 115, DQM1 = 106
2467 12:11:30.036339 DQ Delay:
2468 12:11:30.040329 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2469 12:11:30.043205 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2470 12:11:30.046925 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2471 12:11:30.049809 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2472 12:11:30.049892
2473 12:11:30.053097
2474 12:11:30.053179 ==
2475 12:11:30.056325 Dram Type= 6, Freq= 0, CH_0, rank 0
2476 12:11:30.060099 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2477 12:11:30.060182 ==
2478 12:11:30.060248
2479 12:11:30.060309
2480 12:11:30.063313 TX Vref Scan disable
2481 12:11:30.063414 == TX Byte 0 ==
2482 12:11:30.069846 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2483 12:11:30.073543 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2484 12:11:30.073626 == TX Byte 1 ==
2485 12:11:30.079784 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2486 12:11:30.084054 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2487 12:11:30.084138 ==
2488 12:11:30.086401 Dram Type= 6, Freq= 0, CH_0, rank 0
2489 12:11:30.089942 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2490 12:11:30.090026 ==
2491 12:11:30.101866 TX Vref=22, minBit 8, minWin=24, winSum=413
2492 12:11:30.105378 TX Vref=24, minBit 8, minWin=24, winSum=425
2493 12:11:30.109041 TX Vref=26, minBit 9, minWin=25, winSum=427
2494 12:11:30.111848 TX Vref=28, minBit 8, minWin=26, winSum=432
2495 12:11:30.114985 TX Vref=30, minBit 9, minWin=26, winSum=435
2496 12:11:30.121737 TX Vref=32, minBit 9, minWin=26, winSum=433
2497 12:11:30.125294 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
2498 12:11:30.125377
2499 12:11:30.128758 Final TX Range 1 Vref 30
2500 12:11:30.128842
2501 12:11:30.128908 ==
2502 12:11:30.131873 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 12:11:30.135206 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2504 12:11:30.135290 ==
2505 12:11:30.138045
2506 12:11:30.138159
2507 12:11:30.138257 TX Vref Scan disable
2508 12:11:30.142520 == TX Byte 0 ==
2509 12:11:30.145179 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2510 12:11:30.152141 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2511 12:11:30.152225 == TX Byte 1 ==
2512 12:11:30.154742 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2513 12:11:30.161635 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2514 12:11:30.161719
2515 12:11:30.161785 [DATLAT]
2516 12:11:30.161847 Freq=1200, CH0 RK0
2517 12:11:30.161907
2518 12:11:30.164852 DATLAT Default: 0xd
2519 12:11:30.164935 0, 0xFFFF, sum = 0
2520 12:11:30.167908 1, 0xFFFF, sum = 0
2521 12:11:30.171577 2, 0xFFFF, sum = 0
2522 12:11:30.171661 3, 0xFFFF, sum = 0
2523 12:11:30.174800 4, 0xFFFF, sum = 0
2524 12:11:30.174884 5, 0xFFFF, sum = 0
2525 12:11:30.177886 6, 0xFFFF, sum = 0
2526 12:11:30.177970 7, 0xFFFF, sum = 0
2527 12:11:30.181681 8, 0xFFFF, sum = 0
2528 12:11:30.181765 9, 0xFFFF, sum = 0
2529 12:11:30.184784 10, 0xFFFF, sum = 0
2530 12:11:30.184869 11, 0x0, sum = 1
2531 12:11:30.188880 12, 0x0, sum = 2
2532 12:11:30.188964 13, 0x0, sum = 3
2533 12:11:30.191344 14, 0x0, sum = 4
2534 12:11:30.191428 best_step = 12
2535 12:11:30.191494
2536 12:11:30.191555 ==
2537 12:11:30.195298 Dram Type= 6, Freq= 0, CH_0, rank 0
2538 12:11:30.198172 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2539 12:11:30.198256 ==
2540 12:11:30.201349 RX Vref Scan: 1
2541 12:11:30.201464
2542 12:11:30.204952 Set Vref Range= 32 -> 127
2543 12:11:30.205035
2544 12:11:30.205101 RX Vref 32 -> 127, step: 1
2545 12:11:30.205162
2546 12:11:30.208457 RX Delay -21 -> 252, step: 4
2547 12:11:30.208571
2548 12:11:30.211513 Set Vref, RX VrefLevel [Byte0]: 32
2549 12:11:30.215384 [Byte1]: 32
2550 12:11:30.219020
2551 12:11:30.219102 Set Vref, RX VrefLevel [Byte0]: 33
2552 12:11:30.222047 [Byte1]: 33
2553 12:11:30.227158
2554 12:11:30.227244 Set Vref, RX VrefLevel [Byte0]: 34
2555 12:11:30.229717 [Byte1]: 34
2556 12:11:30.234464
2557 12:11:30.234546 Set Vref, RX VrefLevel [Byte0]: 35
2558 12:11:30.237616 [Byte1]: 35
2559 12:11:30.242849
2560 12:11:30.242932 Set Vref, RX VrefLevel [Byte0]: 36
2561 12:11:30.245455 [Byte1]: 36
2562 12:11:30.251062
2563 12:11:30.251145 Set Vref, RX VrefLevel [Byte0]: 37
2564 12:11:30.254161 [Byte1]: 37
2565 12:11:30.258303
2566 12:11:30.258385 Set Vref, RX VrefLevel [Byte0]: 38
2567 12:11:30.261821 [Byte1]: 38
2568 12:11:30.266438
2569 12:11:30.266521 Set Vref, RX VrefLevel [Byte0]: 39
2570 12:11:30.269644 [Byte1]: 39
2571 12:11:30.273597
2572 12:11:30.273680 Set Vref, RX VrefLevel [Byte0]: 40
2573 12:11:30.278552 [Byte1]: 40
2574 12:11:30.281852
2575 12:11:30.281935 Set Vref, RX VrefLevel [Byte0]: 41
2576 12:11:30.285414 [Byte1]: 41
2577 12:11:30.289703
2578 12:11:30.289785 Set Vref, RX VrefLevel [Byte0]: 42
2579 12:11:30.293734 [Byte1]: 42
2580 12:11:30.297987
2581 12:11:30.298069 Set Vref, RX VrefLevel [Byte0]: 43
2582 12:11:30.300834 [Byte1]: 43
2583 12:11:30.306048
2584 12:11:30.306130 Set Vref, RX VrefLevel [Byte0]: 44
2585 12:11:30.309085 [Byte1]: 44
2586 12:11:30.313692
2587 12:11:30.313774 Set Vref, RX VrefLevel [Byte0]: 45
2588 12:11:30.317057 [Byte1]: 45
2589 12:11:30.321875
2590 12:11:30.321958 Set Vref, RX VrefLevel [Byte0]: 46
2591 12:11:30.325252 [Byte1]: 46
2592 12:11:30.329604
2593 12:11:30.329687 Set Vref, RX VrefLevel [Byte0]: 47
2594 12:11:30.332895 [Byte1]: 47
2595 12:11:30.337014
2596 12:11:30.337099 Set Vref, RX VrefLevel [Byte0]: 48
2597 12:11:30.340334 [Byte1]: 48
2598 12:11:30.345552
2599 12:11:30.345655 Set Vref, RX VrefLevel [Byte0]: 49
2600 12:11:30.348749 [Byte1]: 49
2601 12:11:30.353244
2602 12:11:30.353342 Set Vref, RX VrefLevel [Byte0]: 50
2603 12:11:30.356057 [Byte1]: 50
2604 12:11:30.360854
2605 12:11:30.360936 Set Vref, RX VrefLevel [Byte0]: 51
2606 12:11:30.364962 [Byte1]: 51
2607 12:11:30.369064
2608 12:11:30.369163 Set Vref, RX VrefLevel [Byte0]: 52
2609 12:11:30.372695 [Byte1]: 52
2610 12:11:30.377205
2611 12:11:30.377288 Set Vref, RX VrefLevel [Byte0]: 53
2612 12:11:30.380355 [Byte1]: 53
2613 12:11:30.385142
2614 12:11:30.385225 Set Vref, RX VrefLevel [Byte0]: 54
2615 12:11:30.387980 [Byte1]: 54
2616 12:11:30.392738
2617 12:11:30.392820 Set Vref, RX VrefLevel [Byte0]: 55
2618 12:11:30.395722 [Byte1]: 55
2619 12:11:30.400521
2620 12:11:30.400604 Set Vref, RX VrefLevel [Byte0]: 56
2621 12:11:30.404284 [Byte1]: 56
2622 12:11:30.408533
2623 12:11:30.408617 Set Vref, RX VrefLevel [Byte0]: 57
2624 12:11:30.411929 [Byte1]: 57
2625 12:11:30.416767
2626 12:11:30.416852 Set Vref, RX VrefLevel [Byte0]: 58
2627 12:11:30.419664 [Byte1]: 58
2628 12:11:30.424777
2629 12:11:30.424875 Set Vref, RX VrefLevel [Byte0]: 59
2630 12:11:30.428309 [Byte1]: 59
2631 12:11:30.433097
2632 12:11:30.433179 Set Vref, RX VrefLevel [Byte0]: 60
2633 12:11:30.435617 [Byte1]: 60
2634 12:11:30.439956
2635 12:11:30.440038 Set Vref, RX VrefLevel [Byte0]: 61
2636 12:11:30.443566 [Byte1]: 61
2637 12:11:30.447989
2638 12:11:30.448071 Set Vref, RX VrefLevel [Byte0]: 62
2639 12:11:30.452000 [Byte1]: 62
2640 12:11:30.456224
2641 12:11:30.456306 Set Vref, RX VrefLevel [Byte0]: 63
2642 12:11:30.459863 [Byte1]: 63
2643 12:11:30.464200
2644 12:11:30.464283 Set Vref, RX VrefLevel [Byte0]: 64
2645 12:11:30.467671 [Byte1]: 64
2646 12:11:30.472422
2647 12:11:30.472505 Set Vref, RX VrefLevel [Byte0]: 65
2648 12:11:30.475224 [Byte1]: 65
2649 12:11:30.479758
2650 12:11:30.479841 Set Vref, RX VrefLevel [Byte0]: 66
2651 12:11:30.483250 [Byte1]: 66
2652 12:11:30.488098
2653 12:11:30.488181 Final RX Vref Byte 0 = 46 to rank0
2654 12:11:30.492113 Final RX Vref Byte 1 = 47 to rank0
2655 12:11:30.494754 Final RX Vref Byte 0 = 46 to rank1
2656 12:11:30.497633 Final RX Vref Byte 1 = 47 to rank1==
2657 12:11:30.501174 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 12:11:30.507861 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2659 12:11:30.507945 ==
2660 12:11:30.508011 DQS Delay:
2661 12:11:30.508072 DQS0 = 0, DQS1 = 0
2662 12:11:30.511263 DQM Delay:
2663 12:11:30.511346 DQM0 = 114, DQM1 = 105
2664 12:11:30.514542 DQ Delay:
2665 12:11:30.518014 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2666 12:11:30.521160 DQ4 =118, DQ5 =106, DQ6 =124, DQ7 =120
2667 12:11:30.524243 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =96
2668 12:11:30.527576 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2669 12:11:30.527661
2670 12:11:30.527727
2671 12:11:30.534437 [DQSOSCAuto] RK0, (LSB)MR18= 0x707, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2672 12:11:30.537559 CH0 RK0: MR19=404, MR18=707
2673 12:11:30.544093 CH0_RK0: MR19=0x404, MR18=0x707, DQSOSC=407, MR23=63, INC=39, DEC=26
2674 12:11:30.544177
2675 12:11:30.548197 ----->DramcWriteLeveling(PI) begin...
2676 12:11:30.548282 ==
2677 12:11:30.551399 Dram Type= 6, Freq= 0, CH_0, rank 1
2678 12:11:30.556107 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2679 12:11:30.556190 ==
2680 12:11:30.557402 Write leveling (Byte 0): 28 => 28
2681 12:11:30.560900 Write leveling (Byte 1): 23 => 23
2682 12:11:30.564033 DramcWriteLeveling(PI) end<-----
2683 12:11:30.564116
2684 12:11:30.564181 ==
2685 12:11:30.567696 Dram Type= 6, Freq= 0, CH_0, rank 1
2686 12:11:30.574326 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2687 12:11:30.574409 ==
2688 12:11:30.574475 [Gating] SW mode calibration
2689 12:11:30.584294 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2690 12:11:30.587347 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2691 12:11:30.591112 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2692 12:11:30.597734 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2693 12:11:30.601076 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2694 12:11:30.604027 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2695 12:11:30.610707 0 11 16 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
2696 12:11:30.613931 0 11 20 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
2697 12:11:30.617176 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2698 12:11:30.624011 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2699 12:11:30.627261 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2700 12:11:30.630826 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2701 12:11:30.637140 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2702 12:11:30.640619 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2703 12:11:30.644047 0 12 16 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
2704 12:11:30.650177 0 12 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2705 12:11:30.653567 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2706 12:11:30.657009 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2707 12:11:30.664122 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2708 12:11:30.667913 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2709 12:11:30.670567 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2710 12:11:30.677115 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2711 12:11:30.680296 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2712 12:11:30.684356 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2713 12:11:30.690621 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2714 12:11:30.693342 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2715 12:11:30.697770 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2716 12:11:30.704023 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2717 12:11:30.707450 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2718 12:11:30.710739 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2719 12:11:30.713481 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2720 12:11:30.720363 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2721 12:11:30.723779 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2722 12:11:30.727428 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2723 12:11:30.733698 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2724 12:11:30.736695 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2725 12:11:30.740606 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2726 12:11:30.746848 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2727 12:11:30.750763 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2728 12:11:30.754768 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2729 12:11:30.757265 Total UI for P1: 0, mck2ui 16
2730 12:11:30.760906 best dqsien dly found for B0: ( 0, 15, 16)
2731 12:11:30.763855 Total UI for P1: 0, mck2ui 16
2732 12:11:30.767432 best dqsien dly found for B1: ( 0, 15, 16)
2733 12:11:30.770540 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
2734 12:11:30.773399 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
2735 12:11:30.773482
2736 12:11:30.780234 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
2737 12:11:30.783276 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
2738 12:11:30.787310 [Gating] SW calibration Done
2739 12:11:30.787393 ==
2740 12:11:30.790214 Dram Type= 6, Freq= 0, CH_0, rank 1
2741 12:11:30.793675 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2742 12:11:30.793758 ==
2743 12:11:30.793824 RX Vref Scan: 0
2744 12:11:30.793886
2745 12:11:30.796931 RX Vref 0 -> 0, step: 1
2746 12:11:30.797014
2747 12:11:30.800474 RX Delay -40 -> 252, step: 8
2748 12:11:30.803625 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2749 12:11:30.807076 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2750 12:11:30.813503 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2751 12:11:30.817066 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2752 12:11:30.820857 iDelay=200, Bit 4, Center 119 (40 ~ 199) 160
2753 12:11:30.823242 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2754 12:11:30.827012 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2755 12:11:30.833500 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2756 12:11:30.837396 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2757 12:11:30.840599 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2758 12:11:30.843710 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2759 12:11:30.847218 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2760 12:11:30.850552 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2761 12:11:30.857226 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2762 12:11:30.859718 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2763 12:11:30.863271 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2764 12:11:30.863354 ==
2765 12:11:30.867088 Dram Type= 6, Freq= 0, CH_0, rank 1
2766 12:11:30.870586 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2767 12:11:30.870669 ==
2768 12:11:30.874042 DQS Delay:
2769 12:11:30.874125 DQS0 = 0, DQS1 = 0
2770 12:11:30.877171 DQM Delay:
2771 12:11:30.877254 DQM0 = 115, DQM1 = 106
2772 12:11:30.880031 DQ Delay:
2773 12:11:30.883609 DQ0 =107, DQ1 =115, DQ2 =115, DQ3 =111
2774 12:11:30.886783 DQ4 =119, DQ5 =107, DQ6 =123, DQ7 =123
2775 12:11:30.890191 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2776 12:11:30.893496 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2777 12:11:30.893579
2778 12:11:30.893645
2779 12:11:30.893706 ==
2780 12:11:30.896571 Dram Type= 6, Freq= 0, CH_0, rank 1
2781 12:11:30.900298 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2782 12:11:30.900381 ==
2783 12:11:30.900447
2784 12:11:30.900507
2785 12:11:30.903185 TX Vref Scan disable
2786 12:11:30.906361 == TX Byte 0 ==
2787 12:11:30.909819 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2788 12:11:30.913607 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2789 12:11:30.917013 == TX Byte 1 ==
2790 12:11:30.920092 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2791 12:11:30.922970 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2792 12:11:30.923053 ==
2793 12:11:30.926760 Dram Type= 6, Freq= 0, CH_0, rank 1
2794 12:11:30.929978 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2795 12:11:30.933530 ==
2796 12:11:30.943484 TX Vref=22, minBit 8, minWin=25, winSum=418
2797 12:11:30.947038 TX Vref=24, minBit 8, minWin=25, winSum=423
2798 12:11:30.950146 TX Vref=26, minBit 8, minWin=25, winSum=427
2799 12:11:30.953759 TX Vref=28, minBit 8, minWin=25, winSum=429
2800 12:11:30.957278 TX Vref=30, minBit 8, minWin=25, winSum=435
2801 12:11:30.963414 TX Vref=32, minBit 10, minWin=25, winSum=433
2802 12:11:30.967493 [TxChooseVref] Worse bit 8, Min win 25, Win sum 435, Final Vref 30
2803 12:11:30.967577
2804 12:11:30.970766 Final TX Range 1 Vref 30
2805 12:11:30.970849
2806 12:11:30.970914 ==
2807 12:11:30.973729 Dram Type= 6, Freq= 0, CH_0, rank 1
2808 12:11:30.977247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2809 12:11:30.977332 ==
2810 12:11:30.980351
2811 12:11:30.980432
2812 12:11:30.980498 TX Vref Scan disable
2813 12:11:30.983578 == TX Byte 0 ==
2814 12:11:30.986774 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2815 12:11:30.990087 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2816 12:11:30.993504 == TX Byte 1 ==
2817 12:11:30.997353 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
2818 12:11:31.000093 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
2819 12:11:31.003975
2820 12:11:31.004058 [DATLAT]
2821 12:11:31.004123 Freq=1200, CH0 RK1
2822 12:11:31.004184
2823 12:11:31.007089 DATLAT Default: 0xc
2824 12:11:31.007171 0, 0xFFFF, sum = 0
2825 12:11:31.010088 1, 0xFFFF, sum = 0
2826 12:11:31.010172 2, 0xFFFF, sum = 0
2827 12:11:31.013646 3, 0xFFFF, sum = 0
2828 12:11:31.016673 4, 0xFFFF, sum = 0
2829 12:11:31.016780 5, 0xFFFF, sum = 0
2830 12:11:31.020052 6, 0xFFFF, sum = 0
2831 12:11:31.020176 7, 0xFFFF, sum = 0
2832 12:11:31.023410 8, 0xFFFF, sum = 0
2833 12:11:31.023494 9, 0xFFFF, sum = 0
2834 12:11:31.027259 10, 0xFFFF, sum = 0
2835 12:11:31.027342 11, 0x0, sum = 1
2836 12:11:31.030668 12, 0x0, sum = 2
2837 12:11:31.030752 13, 0x0, sum = 3
2838 12:11:31.034146 14, 0x0, sum = 4
2839 12:11:31.034229 best_step = 12
2840 12:11:31.034295
2841 12:11:31.034356 ==
2842 12:11:31.036537 Dram Type= 6, Freq= 0, CH_0, rank 1
2843 12:11:31.040210 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2844 12:11:31.040308 ==
2845 12:11:31.043634 RX Vref Scan: 0
2846 12:11:31.043716
2847 12:11:31.043781 RX Vref 0 -> 0, step: 1
2848 12:11:31.046988
2849 12:11:31.047070 RX Delay -21 -> 252, step: 4
2850 12:11:31.054512 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2851 12:11:31.057629 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2852 12:11:31.060875 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2853 12:11:31.064420 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2854 12:11:31.067668 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2855 12:11:31.074320 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2856 12:11:31.077188 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2857 12:11:31.081042 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
2858 12:11:31.084494 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2859 12:11:31.087104 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2860 12:11:31.094204 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
2861 12:11:31.097017 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2862 12:11:31.100750 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
2863 12:11:31.104397 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2864 12:11:31.107804 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2865 12:11:31.113891 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2866 12:11:31.113975 ==
2867 12:11:31.117363 Dram Type= 6, Freq= 0, CH_0, rank 1
2868 12:11:31.120595 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2869 12:11:31.120678 ==
2870 12:11:31.120752 DQS Delay:
2871 12:11:31.123587 DQS0 = 0, DQS1 = 0
2872 12:11:31.123673 DQM Delay:
2873 12:11:31.126999 DQM0 = 115, DQM1 = 105
2874 12:11:31.127082 DQ Delay:
2875 12:11:31.130536 DQ0 =110, DQ1 =116, DQ2 =112, DQ3 =108
2876 12:11:31.133453 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =124
2877 12:11:31.137179 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2878 12:11:31.140149 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
2879 12:11:31.140232
2880 12:11:31.140297
2881 12:11:31.150223 [DQSOSCAuto] RK1, (LSB)MR18= 0x1313, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
2882 12:11:31.153647 CH0 RK1: MR19=404, MR18=1313
2883 12:11:31.156660 CH0_RK1: MR19=0x404, MR18=0x1313, DQSOSC=402, MR23=63, INC=40, DEC=27
2884 12:11:31.160424 [RxdqsGatingPostProcess] freq 1200
2885 12:11:31.167485 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2886 12:11:31.170235 Pre-setting of DQS Precalculation
2887 12:11:31.173706 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2888 12:11:31.177181 ==
2889 12:11:31.180493 Dram Type= 6, Freq= 0, CH_1, rank 0
2890 12:11:31.183862 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2891 12:11:31.183946 ==
2892 12:11:31.187306 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2893 12:11:31.193743 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2894 12:11:31.202390 [CA 0] Center 37 (7~68) winsize 62
2895 12:11:31.206451 [CA 1] Center 37 (7~68) winsize 62
2896 12:11:31.210087 [CA 2] Center 34 (4~65) winsize 62
2897 12:11:31.214038 [CA 3] Center 33 (3~64) winsize 62
2898 12:11:31.215923 [CA 4] Center 32 (1~63) winsize 63
2899 12:11:31.219225 [CA 5] Center 32 (2~63) winsize 62
2900 12:11:31.219307
2901 12:11:31.222249 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2902 12:11:31.222332
2903 12:11:31.226043 [CATrainingPosCal] consider 1 rank data
2904 12:11:31.229065 u2DelayCellTimex100 = 270/100 ps
2905 12:11:31.233185 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2906 12:11:31.236220 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2907 12:11:31.242662 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2908 12:11:31.246260 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2909 12:11:31.248969 CA4 delay=32 (1~63),Diff = 0 PI (0 cell)
2910 12:11:31.252253 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2911 12:11:31.252336
2912 12:11:31.255782 CA PerBit enable=1, Macro0, CA PI delay=32
2913 12:11:31.255865
2914 12:11:31.258995 [CBTSetCACLKResult] CA Dly = 32
2915 12:11:31.259078 CS Dly: 5 (0~36)
2916 12:11:31.259144 ==
2917 12:11:31.262691 Dram Type= 6, Freq= 0, CH_1, rank 1
2918 12:11:31.269376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2919 12:11:31.269460 ==
2920 12:11:31.272451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2921 12:11:31.279634 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2922 12:11:31.287806 [CA 0] Center 37 (6~68) winsize 63
2923 12:11:31.291029 [CA 1] Center 37 (6~68) winsize 63
2924 12:11:31.294586 [CA 2] Center 34 (3~65) winsize 63
2925 12:11:31.298311 [CA 3] Center 33 (3~64) winsize 62
2926 12:11:31.301270 [CA 4] Center 32 (2~63) winsize 62
2927 12:11:31.304898 [CA 5] Center 32 (1~63) winsize 63
2928 12:11:31.304981
2929 12:11:31.308265 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2930 12:11:31.308347
2931 12:11:31.311069 [CATrainingPosCal] consider 2 rank data
2932 12:11:31.314419 u2DelayCellTimex100 = 270/100 ps
2933 12:11:31.317554 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2934 12:11:31.324901 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2935 12:11:31.327582 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2936 12:11:31.331803 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2937 12:11:31.333960 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2938 12:11:31.337642 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2939 12:11:31.337725
2940 12:11:31.340861 CA PerBit enable=1, Macro0, CA PI delay=32
2941 12:11:31.340972
2942 12:11:31.343862 [CBTSetCACLKResult] CA Dly = 32
2943 12:11:31.343945 CS Dly: 6 (0~38)
2944 12:11:31.344010
2945 12:11:31.351190 ----->DramcWriteLeveling(PI) begin...
2946 12:11:31.351286 ==
2947 12:11:31.354260 Dram Type= 6, Freq= 0, CH_1, rank 0
2948 12:11:31.357612 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2949 12:11:31.357695 ==
2950 12:11:31.360633 Write leveling (Byte 0): 19 => 19
2951 12:11:31.364056 Write leveling (Byte 1): 21 => 21
2952 12:11:31.367607 DramcWriteLeveling(PI) end<-----
2953 12:11:31.367716
2954 12:11:31.367814 ==
2955 12:11:31.370569 Dram Type= 6, Freq= 0, CH_1, rank 0
2956 12:11:31.374291 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2957 12:11:31.374392 ==
2958 12:11:31.377618 [Gating] SW mode calibration
2959 12:11:31.384409 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2960 12:11:31.391012 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2961 12:11:31.393925 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2962 12:11:31.397474 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2963 12:11:31.404677 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2964 12:11:31.407253 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2965 12:11:31.410844 0 11 16 | B1->B0 | 3232 2626 | 0 0 | (0 0) (0 1)
2966 12:11:31.414339 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2967 12:11:31.420727 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2968 12:11:31.424106 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2969 12:11:31.428037 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2970 12:11:31.434029 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2971 12:11:31.438163 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2972 12:11:31.440326 0 12 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2973 12:11:31.447471 0 12 16 | B1->B0 | 3434 4444 | 0 0 | (0 0) (0 0)
2974 12:11:31.451066 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2975 12:11:31.454704 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2976 12:11:31.460718 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2977 12:11:31.463964 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2978 12:11:31.467417 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2979 12:11:31.474109 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 12:11:31.477336 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2981 12:11:31.480558 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2982 12:11:31.487921 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2983 12:11:31.490593 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 12:11:31.493980 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 12:11:31.500788 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 12:11:31.503604 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 12:11:31.507574 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 12:11:31.514312 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 12:11:31.517496 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 12:11:31.521159 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 12:11:31.523903 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 12:11:31.530951 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 12:11:31.534151 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 12:11:31.537495 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 12:11:31.543805 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 12:11:31.547523 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2997 12:11:31.550377 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2998 12:11:31.557386 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2999 12:11:31.560556 Total UI for P1: 0, mck2ui 16
3000 12:11:31.563863 best dqsien dly found for B0: ( 0, 15, 14)
3001 12:11:31.567169 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3002 12:11:31.571237 Total UI for P1: 0, mck2ui 16
3003 12:11:31.573716 best dqsien dly found for B1: ( 0, 15, 20)
3004 12:11:31.576939 best DQS0 dly(MCK, UI, PI) = (0, 15, 14)
3005 12:11:31.580724 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
3006 12:11:31.580807
3007 12:11:31.584442 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 14)
3008 12:11:31.586861 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
3009 12:11:31.590951 [Gating] SW calibration Done
3010 12:11:31.591033 ==
3011 12:11:31.593637 Dram Type= 6, Freq= 0, CH_1, rank 0
3012 12:11:31.600126 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3013 12:11:31.600224 ==
3014 12:11:31.600297 RX Vref Scan: 0
3015 12:11:31.600360
3016 12:11:31.603511 RX Vref 0 -> 0, step: 1
3017 12:11:31.603583
3018 12:11:31.606931 RX Delay -40 -> 252, step: 8
3019 12:11:31.610148 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3020 12:11:31.613434 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3021 12:11:31.616883 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3022 12:11:31.620115 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3023 12:11:31.627279 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3024 12:11:31.630480 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3025 12:11:31.634061 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3026 12:11:31.637582 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3027 12:11:31.640113 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3028 12:11:31.646743 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3029 12:11:31.650389 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3030 12:11:31.653963 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3031 12:11:31.656924 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3032 12:11:31.660536 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3033 12:11:31.666950 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3034 12:11:31.670465 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3035 12:11:31.670544 ==
3036 12:11:31.673527 Dram Type= 6, Freq= 0, CH_1, rank 0
3037 12:11:31.676805 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3038 12:11:31.676885 ==
3039 12:11:31.680374 DQS Delay:
3040 12:11:31.680453 DQS0 = 0, DQS1 = 0
3041 12:11:31.680519 DQM Delay:
3042 12:11:31.683512 DQM0 = 116, DQM1 = 109
3043 12:11:31.683589 DQ Delay:
3044 12:11:31.687308 DQ0 =123, DQ1 =107, DQ2 =107, DQ3 =115
3045 12:11:31.690296 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3046 12:11:31.693248 DQ8 =87, DQ9 =99, DQ10 =111, DQ11 =103
3047 12:11:31.700789 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3048 12:11:31.700868
3049 12:11:31.700936
3050 12:11:31.700997 ==
3051 12:11:31.703674 Dram Type= 6, Freq= 0, CH_1, rank 0
3052 12:11:31.707024 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3053 12:11:31.707104 ==
3054 12:11:31.707168
3055 12:11:31.707231
3056 12:11:31.710366 TX Vref Scan disable
3057 12:11:31.710450 == TX Byte 0 ==
3058 12:11:31.717620 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3059 12:11:31.720111 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3060 12:11:31.720194 == TX Byte 1 ==
3061 12:11:31.728202 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3062 12:11:31.730315 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3063 12:11:31.730399 ==
3064 12:11:31.733507 Dram Type= 6, Freq= 0, CH_1, rank 0
3065 12:11:31.736860 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3066 12:11:31.736944 ==
3067 12:11:31.749108 TX Vref=22, minBit 0, minWin=25, winSum=414
3068 12:11:31.753074 TX Vref=24, minBit 1, minWin=25, winSum=415
3069 12:11:31.756276 TX Vref=26, minBit 9, minWin=25, winSum=422
3070 12:11:31.759105 TX Vref=28, minBit 7, minWin=26, winSum=430
3071 12:11:31.762330 TX Vref=30, minBit 0, minWin=26, winSum=429
3072 12:11:31.765842 TX Vref=32, minBit 3, minWin=26, winSum=429
3073 12:11:31.772307 [TxChooseVref] Worse bit 7, Min win 26, Win sum 430, Final Vref 28
3074 12:11:31.772407
3075 12:11:31.775678 Final TX Range 1 Vref 28
3076 12:11:31.775754
3077 12:11:31.775816 ==
3078 12:11:31.779139 Dram Type= 6, Freq= 0, CH_1, rank 0
3079 12:11:31.782547 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3080 12:11:31.782653 ==
3081 12:11:31.782743
3082 12:11:31.786342
3083 12:11:31.786418 TX Vref Scan disable
3084 12:11:31.789260 == TX Byte 0 ==
3085 12:11:31.793149 Update DQ dly =835 (3 ,1, 35) DQ OEN =(2 ,6)
3086 12:11:31.796006 Update DQM dly =835 (3 ,1, 35) DQM OEN =(2 ,6)
3087 12:11:31.799082 == TX Byte 1 ==
3088 12:11:31.802711 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3089 12:11:31.806724 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3090 12:11:31.806794
3091 12:11:31.808793 [DATLAT]
3092 12:11:31.808861 Freq=1200, CH1 RK0
3093 12:11:31.808928
3094 12:11:31.812181 DATLAT Default: 0xd
3095 12:11:31.812248 0, 0xFFFF, sum = 0
3096 12:11:31.815966 1, 0xFFFF, sum = 0
3097 12:11:31.816036 2, 0xFFFF, sum = 0
3098 12:11:31.819326 3, 0xFFFF, sum = 0
3099 12:11:31.819401 4, 0xFFFF, sum = 0
3100 12:11:31.822220 5, 0xFFFF, sum = 0
3101 12:11:31.822295 6, 0xFFFF, sum = 0
3102 12:11:31.826511 7, 0xFFFF, sum = 0
3103 12:11:31.829426 8, 0xFFFF, sum = 0
3104 12:11:31.829496 9, 0xFFFF, sum = 0
3105 12:11:31.835654 10, 0xFFFF, sum = 0
3106 12:11:31.835725 11, 0x0, sum = 1
3107 12:11:31.835786 12, 0x0, sum = 2
3108 12:11:31.836068 13, 0x0, sum = 3
3109 12:11:31.836133 14, 0x0, sum = 4
3110 12:11:31.839866 best_step = 12
3111 12:11:31.839936
3112 12:11:31.840002 ==
3113 12:11:31.843366 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 12:11:31.845672 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3115 12:11:31.845818 ==
3116 12:11:31.849343 RX Vref Scan: 1
3117 12:11:31.849426
3118 12:11:31.849492 Set Vref Range= 32 -> 127
3119 12:11:31.853182
3120 12:11:31.853264 RX Vref 32 -> 127, step: 1
3121 12:11:31.853329
3122 12:11:31.855958 RX Delay -29 -> 252, step: 4
3123 12:11:31.856041
3124 12:11:31.860544 Set Vref, RX VrefLevel [Byte0]: 32
3125 12:11:31.863097 [Byte1]: 32
3126 12:11:31.863180
3127 12:11:31.866239 Set Vref, RX VrefLevel [Byte0]: 33
3128 12:11:31.869116 [Byte1]: 33
3129 12:11:31.873706
3130 12:11:31.873789 Set Vref, RX VrefLevel [Byte0]: 34
3131 12:11:31.877136 [Byte1]: 34
3132 12:11:31.881506
3133 12:11:31.881588 Set Vref, RX VrefLevel [Byte0]: 35
3134 12:11:31.884580 [Byte1]: 35
3135 12:11:31.889964
3136 12:11:31.890046 Set Vref, RX VrefLevel [Byte0]: 36
3137 12:11:31.893107 [Byte1]: 36
3138 12:11:31.897169
3139 12:11:31.897252 Set Vref, RX VrefLevel [Byte0]: 37
3140 12:11:31.900894 [Byte1]: 37
3141 12:11:31.905477
3142 12:11:31.905560 Set Vref, RX VrefLevel [Byte0]: 38
3143 12:11:31.908440 [Byte1]: 38
3144 12:11:31.913521
3145 12:11:31.913604 Set Vref, RX VrefLevel [Byte0]: 39
3146 12:11:31.916591 [Byte1]: 39
3147 12:11:31.921140
3148 12:11:31.921223 Set Vref, RX VrefLevel [Byte0]: 40
3149 12:11:31.924588 [Byte1]: 40
3150 12:11:31.929705
3151 12:11:31.929788 Set Vref, RX VrefLevel [Byte0]: 41
3152 12:11:31.932743 [Byte1]: 41
3153 12:11:31.937049
3154 12:11:31.937131 Set Vref, RX VrefLevel [Byte0]: 42
3155 12:11:31.940788 [Byte1]: 42
3156 12:11:31.945449
3157 12:11:31.945532 Set Vref, RX VrefLevel [Byte0]: 43
3158 12:11:31.950046 [Byte1]: 43
3159 12:11:31.954008
3160 12:11:31.954090 Set Vref, RX VrefLevel [Byte0]: 44
3161 12:11:31.956909 [Byte1]: 44
3162 12:11:31.961377
3163 12:11:31.961460 Set Vref, RX VrefLevel [Byte0]: 45
3164 12:11:31.964576 [Byte1]: 45
3165 12:11:31.969508
3166 12:11:31.969590 Set Vref, RX VrefLevel [Byte0]: 46
3167 12:11:31.972481 [Byte1]: 46
3168 12:11:31.977283
3169 12:11:31.977365 Set Vref, RX VrefLevel [Byte0]: 47
3170 12:11:31.980919 [Byte1]: 47
3171 12:11:31.985155
3172 12:11:31.985237 Set Vref, RX VrefLevel [Byte0]: 48
3173 12:11:31.988596 [Byte1]: 48
3174 12:11:31.993121
3175 12:11:31.993204 Set Vref, RX VrefLevel [Byte0]: 49
3176 12:11:31.996412 [Byte1]: 49
3177 12:11:32.001307
3178 12:11:32.001389 Set Vref, RX VrefLevel [Byte0]: 50
3179 12:11:32.004037 [Byte1]: 50
3180 12:11:32.008945
3181 12:11:32.009028 Set Vref, RX VrefLevel [Byte0]: 51
3182 12:11:32.012236 [Byte1]: 51
3183 12:11:32.017101
3184 12:11:32.017183 Set Vref, RX VrefLevel [Byte0]: 52
3185 12:11:32.020385 [Byte1]: 52
3186 12:11:32.024846
3187 12:11:32.024928 Set Vref, RX VrefLevel [Byte0]: 53
3188 12:11:32.028417 [Byte1]: 53
3189 12:11:32.032679
3190 12:11:32.032830 Set Vref, RX VrefLevel [Byte0]: 54
3191 12:11:32.036322 [Byte1]: 54
3192 12:11:32.040625
3193 12:11:32.040772 Set Vref, RX VrefLevel [Byte0]: 55
3194 12:11:32.043888 [Byte1]: 55
3195 12:11:32.048949
3196 12:11:32.049032 Set Vref, RX VrefLevel [Byte0]: 56
3197 12:11:32.051715 [Byte1]: 56
3198 12:11:32.056663
3199 12:11:32.056797 Set Vref, RX VrefLevel [Byte0]: 57
3200 12:11:32.060027 [Byte1]: 57
3201 12:11:32.064582
3202 12:11:32.064691 Set Vref, RX VrefLevel [Byte0]: 58
3203 12:11:32.067775 [Byte1]: 58
3204 12:11:32.072306
3205 12:11:32.072388 Set Vref, RX VrefLevel [Byte0]: 59
3206 12:11:32.076516 [Byte1]: 59
3207 12:11:32.080323
3208 12:11:32.080406 Set Vref, RX VrefLevel [Byte0]: 60
3209 12:11:32.083560 [Byte1]: 60
3210 12:11:32.088634
3211 12:11:32.088779 Set Vref, RX VrefLevel [Byte0]: 61
3212 12:11:32.091338 [Byte1]: 61
3213 12:11:32.097015
3214 12:11:32.097097 Set Vref, RX VrefLevel [Byte0]: 62
3215 12:11:32.099973 [Byte1]: 62
3216 12:11:32.104835
3217 12:11:32.104917 Set Vref, RX VrefLevel [Byte0]: 63
3218 12:11:32.107859 [Byte1]: 63
3219 12:11:32.112312
3220 12:11:32.112395 Set Vref, RX VrefLevel [Byte0]: 64
3221 12:11:32.115662 [Byte1]: 64
3222 12:11:32.120221
3223 12:11:32.120304 Set Vref, RX VrefLevel [Byte0]: 65
3224 12:11:32.124304 [Byte1]: 65
3225 12:11:32.128212
3226 12:11:32.128295 Set Vref, RX VrefLevel [Byte0]: 66
3227 12:11:32.131713 [Byte1]: 66
3228 12:11:32.136463
3229 12:11:32.136545 Final RX Vref Byte 0 = 53 to rank0
3230 12:11:32.140244 Final RX Vref Byte 1 = 50 to rank0
3231 12:11:32.143160 Final RX Vref Byte 0 = 53 to rank1
3232 12:11:32.146257 Final RX Vref Byte 1 = 50 to rank1==
3233 12:11:32.149352 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 12:11:32.156372 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3235 12:11:32.156457 ==
3236 12:11:32.156523 DQS Delay:
3237 12:11:32.156585 DQS0 = 0, DQS1 = 0
3238 12:11:32.159293 DQM Delay:
3239 12:11:32.159375 DQM0 = 115, DQM1 = 105
3240 12:11:32.162763 DQ Delay:
3241 12:11:32.166083 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3242 12:11:32.169876 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =114
3243 12:11:32.172622 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3244 12:11:32.176028 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =116
3245 12:11:32.176111
3246 12:11:32.176177
3247 12:11:32.182269 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
3248 12:11:32.186306 CH1 RK0: MR19=404, MR18=1515
3249 12:11:32.192814 CH1_RK0: MR19=0x404, MR18=0x1515, DQSOSC=401, MR23=63, INC=40, DEC=27
3250 12:11:32.192898
3251 12:11:32.196760 ----->DramcWriteLeveling(PI) begin...
3252 12:11:32.196845 ==
3253 12:11:32.200265 Dram Type= 6, Freq= 0, CH_1, rank 1
3254 12:11:32.202758 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3255 12:11:32.205955 ==
3256 12:11:32.206037 Write leveling (Byte 0): 22 => 22
3257 12:11:32.209550 Write leveling (Byte 1): 22 => 22
3258 12:11:32.212859 DramcWriteLeveling(PI) end<-----
3259 12:11:32.212942
3260 12:11:32.213008 ==
3261 12:11:32.216734 Dram Type= 6, Freq= 0, CH_1, rank 1
3262 12:11:32.222292 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3263 12:11:32.222376 ==
3264 12:11:32.222442 [Gating] SW mode calibration
3265 12:11:32.232502 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3266 12:11:32.235473 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3267 12:11:32.242316 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3268 12:11:32.245527 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3269 12:11:32.249588 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3270 12:11:32.252884 0 11 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
3271 12:11:32.259336 0 11 16 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
3272 12:11:32.262788 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3273 12:11:32.265447 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3274 12:11:32.272651 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3275 12:11:32.275472 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3276 12:11:32.278731 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3277 12:11:32.285868 0 12 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3278 12:11:32.288645 0 12 12 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
3279 12:11:32.292278 0 12 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
3280 12:11:32.298986 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3281 12:11:32.301827 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3282 12:11:32.305862 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3283 12:11:32.312406 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3284 12:11:32.315786 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3285 12:11:32.318876 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3286 12:11:32.325847 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3287 12:11:32.329415 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3288 12:11:32.332236 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3289 12:11:32.339046 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3290 12:11:32.342170 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 12:11:32.345519 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 12:11:32.352461 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3293 12:11:32.355502 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3294 12:11:32.359431 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3295 12:11:32.365152 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3296 12:11:32.368960 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3297 12:11:32.371836 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3298 12:11:32.375235 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3299 12:11:32.382865 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3300 12:11:32.386839 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3301 12:11:32.388651 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3302 12:11:32.395092 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3303 12:11:32.398919 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3304 12:11:32.401935 Total UI for P1: 0, mck2ui 16
3305 12:11:32.405367 best dqsien dly found for B0: ( 0, 15, 12)
3306 12:11:32.408493 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3307 12:11:32.411741 Total UI for P1: 0, mck2ui 16
3308 12:11:32.415438 best dqsien dly found for B1: ( 0, 15, 14)
3309 12:11:32.418576 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3310 12:11:32.422684 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3311 12:11:32.425972
3312 12:11:32.428565 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3313 12:11:32.432344 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3314 12:11:32.435573 [Gating] SW calibration Done
3315 12:11:32.435697 ==
3316 12:11:32.439068 Dram Type= 6, Freq= 0, CH_1, rank 1
3317 12:11:32.442025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3318 12:11:32.442156 ==
3319 12:11:32.442274 RX Vref Scan: 0
3320 12:11:32.442366
3321 12:11:32.446023 RX Vref 0 -> 0, step: 1
3322 12:11:32.446099
3323 12:11:32.448366 RX Delay -40 -> 252, step: 8
3324 12:11:32.452300 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3325 12:11:32.455433 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
3326 12:11:32.461880 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3327 12:11:32.465315 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3328 12:11:32.468627 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3329 12:11:32.471631 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3330 12:11:32.475216 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3331 12:11:32.482496 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3332 12:11:32.485197 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3333 12:11:32.489052 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3334 12:11:32.491594 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3335 12:11:32.495500 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3336 12:11:32.499738 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3337 12:11:32.505609 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3338 12:11:32.508260 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3339 12:11:32.511467 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3340 12:11:32.511548 ==
3341 12:11:32.515771 Dram Type= 6, Freq= 0, CH_1, rank 1
3342 12:11:32.518592 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3343 12:11:32.521726 ==
3344 12:11:32.521798 DQS Delay:
3345 12:11:32.521859 DQS0 = 0, DQS1 = 0
3346 12:11:32.524965 DQM Delay:
3347 12:11:32.525032 DQM0 = 115, DQM1 = 106
3348 12:11:32.528202 DQ Delay:
3349 12:11:32.531703 DQ0 =115, DQ1 =115, DQ2 =107, DQ3 =115
3350 12:11:32.535259 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =115
3351 12:11:32.538947 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =103
3352 12:11:32.541766 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3353 12:11:32.541848
3354 12:11:32.541911
3355 12:11:32.541970 ==
3356 12:11:32.544826 Dram Type= 6, Freq= 0, CH_1, rank 1
3357 12:11:32.548375 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3358 12:11:32.548456 ==
3359 12:11:32.548518
3360 12:11:32.548577
3361 12:11:32.551806 TX Vref Scan disable
3362 12:11:32.555324 == TX Byte 0 ==
3363 12:11:32.558751 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3364 12:11:32.561630 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3365 12:11:32.564901 == TX Byte 1 ==
3366 12:11:32.568720 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3367 12:11:32.571766 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3368 12:11:32.571841 ==
3369 12:11:32.574677 Dram Type= 6, Freq= 0, CH_1, rank 1
3370 12:11:32.581701 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3371 12:11:32.581779 ==
3372 12:11:32.591690 TX Vref=22, minBit 9, minWin=25, winSum=423
3373 12:11:32.595570 TX Vref=24, minBit 0, minWin=26, winSum=426
3374 12:11:32.598774 TX Vref=26, minBit 8, minWin=26, winSum=432
3375 12:11:32.602126 TX Vref=28, minBit 8, minWin=26, winSum=429
3376 12:11:32.604974 TX Vref=30, minBit 9, minWin=26, winSum=432
3377 12:11:32.609160 TX Vref=32, minBit 0, minWin=26, winSum=428
3378 12:11:32.616007 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 26
3379 12:11:32.616090
3380 12:11:32.618192 Final TX Range 1 Vref 26
3381 12:11:32.618272
3382 12:11:32.618334 ==
3383 12:11:32.622134 Dram Type= 6, Freq= 0, CH_1, rank 1
3384 12:11:32.625008 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3385 12:11:32.625092 ==
3386 12:11:32.625156
3387 12:11:32.628805
3388 12:11:32.628877 TX Vref Scan disable
3389 12:11:32.631908 == TX Byte 0 ==
3390 12:11:32.635092 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3391 12:11:32.638110 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3392 12:11:32.641292 == TX Byte 1 ==
3393 12:11:32.644588 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3394 12:11:32.648360 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3395 12:11:32.648468
3396 12:11:32.651320 [DATLAT]
3397 12:11:32.651398 Freq=1200, CH1 RK1
3398 12:11:32.651469
3399 12:11:32.654618 DATLAT Default: 0xc
3400 12:11:32.654692 0, 0xFFFF, sum = 0
3401 12:11:32.658114 1, 0xFFFF, sum = 0
3402 12:11:32.658192 2, 0xFFFF, sum = 0
3403 12:11:32.661593 3, 0xFFFF, sum = 0
3404 12:11:32.661674 4, 0xFFFF, sum = 0
3405 12:11:32.664721 5, 0xFFFF, sum = 0
3406 12:11:32.664836 6, 0xFFFF, sum = 0
3407 12:11:32.668325 7, 0xFFFF, sum = 0
3408 12:11:32.668425 8, 0xFFFF, sum = 0
3409 12:11:32.672337 9, 0xFFFF, sum = 0
3410 12:11:32.674706 10, 0xFFFF, sum = 0
3411 12:11:32.674781 11, 0x0, sum = 1
3412 12:11:32.674851 12, 0x0, sum = 2
3413 12:11:32.678341 13, 0x0, sum = 3
3414 12:11:32.678418 14, 0x0, sum = 4
3415 12:11:32.681802 best_step = 12
3416 12:11:32.681875
3417 12:11:32.681944 ==
3418 12:11:32.685091 Dram Type= 6, Freq= 0, CH_1, rank 1
3419 12:11:32.687877 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3420 12:11:32.687951 ==
3421 12:11:32.692096 RX Vref Scan: 0
3422 12:11:32.692175
3423 12:11:32.692237 RX Vref 0 -> 0, step: 1
3424 12:11:32.692294
3425 12:11:32.694926 RX Delay -29 -> 252, step: 4
3426 12:11:32.702098 iDelay=199, Bit 0, Center 114 (43 ~ 186) 144
3427 12:11:32.705734 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3428 12:11:32.708664 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3429 12:11:32.712298 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3430 12:11:32.715626 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3431 12:11:32.722329 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3432 12:11:32.725162 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3433 12:11:32.728611 iDelay=199, Bit 7, Center 112 (39 ~ 186) 148
3434 12:11:32.731950 iDelay=199, Bit 8, Center 88 (19 ~ 158) 140
3435 12:11:32.737319 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3436 12:11:32.741552 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3437 12:11:32.744744 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3438 12:11:32.748425 iDelay=199, Bit 12, Center 114 (43 ~ 186) 144
3439 12:11:32.751867 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3440 12:11:32.754763 iDelay=199, Bit 14, Center 116 (47 ~ 186) 140
3441 12:11:32.761861 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3442 12:11:32.761937 ==
3443 12:11:32.764876 Dram Type= 6, Freq= 0, CH_1, rank 1
3444 12:11:32.768189 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3445 12:11:32.768271 ==
3446 12:11:32.768335 DQS Delay:
3447 12:11:32.771707 DQS0 = 0, DQS1 = 0
3448 12:11:32.771807 DQM Delay:
3449 12:11:32.775205 DQM0 = 114, DQM1 = 104
3450 12:11:32.775289 DQ Delay:
3451 12:11:32.778537 DQ0 =114, DQ1 =110, DQ2 =108, DQ3 =112
3452 12:11:32.782324 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3453 12:11:32.785046 DQ8 =88, DQ9 =92, DQ10 =106, DQ11 =98
3454 12:11:32.788474 DQ12 =114, DQ13 =110, DQ14 =116, DQ15 =110
3455 12:11:32.788545
3456 12:11:32.788606
3457 12:11:32.798394 [DQSOSCAuto] RK1, (LSB)MR18= 0xb0b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3458 12:11:32.801889 CH1 RK1: MR19=404, MR18=B0B
3459 12:11:32.805141 CH1_RK1: MR19=0x404, MR18=0xB0B, DQSOSC=405, MR23=63, INC=39, DEC=26
3460 12:11:32.808350 [RxdqsGatingPostProcess] freq 1200
3461 12:11:32.815448 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3462 12:11:32.818609 Pre-setting of DQS Precalculation
3463 12:11:32.821411 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3464 12:11:32.831910 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3465 12:11:32.838068 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3466 12:11:32.838142
3467 12:11:32.838211
3468 12:11:32.841361 [Calibration Summary] 2400 Mbps
3469 12:11:32.841443 CH 0, Rank 0
3470 12:11:32.845779 SW Impedance : PASS
3471 12:11:32.845850 DUTY Scan : NO K
3472 12:11:32.848672 ZQ Calibration : PASS
3473 12:11:32.852499 Jitter Meter : NO K
3474 12:11:32.852601 CBT Training : PASS
3475 12:11:32.854726 Write leveling : PASS
3476 12:11:32.858197 RX DQS gating : PASS
3477 12:11:32.858269 RX DQ/DQS(RDDQC) : PASS
3478 12:11:32.861852 TX DQ/DQS : PASS
3479 12:11:32.865320 RX DATLAT : PASS
3480 12:11:32.865389 RX DQ/DQS(Engine): PASS
3481 12:11:32.868194 TX OE : NO K
3482 12:11:32.868270 All Pass.
3483 12:11:32.868330
3484 12:11:32.871478 CH 0, Rank 1
3485 12:11:32.871545 SW Impedance : PASS
3486 12:11:32.874705 DUTY Scan : NO K
3487 12:11:32.874776 ZQ Calibration : PASS
3488 12:11:32.878160 Jitter Meter : NO K
3489 12:11:32.881614 CBT Training : PASS
3490 12:11:32.881683 Write leveling : PASS
3491 12:11:32.884675 RX DQS gating : PASS
3492 12:11:32.888378 RX DQ/DQS(RDDQC) : PASS
3493 12:11:32.888452 TX DQ/DQS : PASS
3494 12:11:32.891345 RX DATLAT : PASS
3495 12:11:32.894538 RX DQ/DQS(Engine): PASS
3496 12:11:32.894608 TX OE : NO K
3497 12:11:32.898328 All Pass.
3498 12:11:32.898403
3499 12:11:32.898464 CH 1, Rank 0
3500 12:11:32.901343 SW Impedance : PASS
3501 12:11:32.901410 DUTY Scan : NO K
3502 12:11:32.904696 ZQ Calibration : PASS
3503 12:11:32.908561 Jitter Meter : NO K
3504 12:11:32.908644 CBT Training : PASS
3505 12:11:32.911460 Write leveling : PASS
3506 12:11:32.915889 RX DQS gating : PASS
3507 12:11:32.915963 RX DQ/DQS(RDDQC) : PASS
3508 12:11:32.917934 TX DQ/DQS : PASS
3509 12:11:32.918030 RX DATLAT : PASS
3510 12:11:32.921188 RX DQ/DQS(Engine): PASS
3511 12:11:32.924858 TX OE : NO K
3512 12:11:32.924926 All Pass.
3513 12:11:32.924986
3514 12:11:32.925044 CH 1, Rank 1
3515 12:11:32.928365 SW Impedance : PASS
3516 12:11:32.932124 DUTY Scan : NO K
3517 12:11:32.932191 ZQ Calibration : PASS
3518 12:11:32.934713 Jitter Meter : NO K
3519 12:11:32.938654 CBT Training : PASS
3520 12:11:32.938722 Write leveling : PASS
3521 12:11:32.942127 RX DQS gating : PASS
3522 12:11:32.945383 RX DQ/DQS(RDDQC) : PASS
3523 12:11:32.945453 TX DQ/DQS : PASS
3524 12:11:32.948700 RX DATLAT : PASS
3525 12:11:32.951989 RX DQ/DQS(Engine): PASS
3526 12:11:32.952073 TX OE : NO K
3527 12:11:32.954897 All Pass.
3528 12:11:32.954978
3529 12:11:32.955043 DramC Write-DBI off
3530 12:11:32.958487 PER_BANK_REFRESH: Hybrid Mode
3531 12:11:32.958569 TX_TRACKING: ON
3532 12:11:32.968360 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3533 12:11:32.971911 [FAST_K] Save calibration result to emmc
3534 12:11:32.975854 dramc_set_vcore_voltage set vcore to 650000
3535 12:11:32.977873 Read voltage for 600, 5
3536 12:11:32.977955 Vio18 = 0
3537 12:11:32.981920 Vcore = 650000
3538 12:11:32.982002 Vdram = 0
3539 12:11:32.982068 Vddq = 0
3540 12:11:32.982128 Vmddr = 0
3541 12:11:32.988215 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3542 12:11:32.991727 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3543 12:11:32.995145 MEM_TYPE=3, freq_sel=19
3544 12:11:32.998266 sv_algorithm_assistance_LP4_1600
3545 12:11:33.001627 ============ PULL DRAM RESETB DOWN ============
3546 12:11:33.008625 ========== PULL DRAM RESETB DOWN end =========
3547 12:11:33.011296 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3548 12:11:33.015313 ===================================
3549 12:11:33.017942 LPDDR4 DRAM CONFIGURATION
3550 12:11:33.021511 ===================================
3551 12:11:33.021594 EX_ROW_EN[0] = 0x0
3552 12:11:33.024957 EX_ROW_EN[1] = 0x0
3553 12:11:33.025039 LP4Y_EN = 0x0
3554 12:11:33.027934 WORK_FSP = 0x0
3555 12:11:33.028027 WL = 0x2
3556 12:11:33.032419 RL = 0x2
3557 12:11:33.032501 BL = 0x2
3558 12:11:33.034765 RPST = 0x0
3559 12:11:33.034847 RD_PRE = 0x0
3560 12:11:33.038653 WR_PRE = 0x1
3561 12:11:33.041450 WR_PST = 0x0
3562 12:11:33.041532 DBI_WR = 0x0
3563 12:11:33.044739 DBI_RD = 0x0
3564 12:11:33.044839 OTF = 0x1
3565 12:11:33.047622 ===================================
3566 12:11:33.051456 ===================================
3567 12:11:33.054429 ANA top config
3568 12:11:33.054508 ===================================
3569 12:11:33.058887 DLL_ASYNC_EN = 0
3570 12:11:33.061949 ALL_SLAVE_EN = 1
3571 12:11:33.064794 NEW_RANK_MODE = 1
3572 12:11:33.067509 DLL_IDLE_MODE = 1
3573 12:11:33.067578 LP45_APHY_COMB_EN = 1
3574 12:11:33.071290 TX_ODT_DIS = 1
3575 12:11:33.074155 NEW_8X_MODE = 1
3576 12:11:33.077884 ===================================
3577 12:11:33.081394 ===================================
3578 12:11:33.084393 data_rate = 1200
3579 12:11:33.087606 CKR = 1
3580 12:11:33.091212 DQ_P2S_RATIO = 8
3581 12:11:33.094021 ===================================
3582 12:11:33.094097 CA_P2S_RATIO = 8
3583 12:11:33.097476 DQ_CA_OPEN = 0
3584 12:11:33.100978 DQ_SEMI_OPEN = 0
3585 12:11:33.104246 CA_SEMI_OPEN = 0
3586 12:11:33.107164 CA_FULL_RATE = 0
3587 12:11:33.110737 DQ_CKDIV4_EN = 1
3588 12:11:33.110813 CA_CKDIV4_EN = 1
3589 12:11:33.113903 CA_PREDIV_EN = 0
3590 12:11:33.118112 PH8_DLY = 0
3591 12:11:33.120631 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3592 12:11:33.123783 DQ_AAMCK_DIV = 4
3593 12:11:33.126953 CA_AAMCK_DIV = 4
3594 12:11:33.127028 CA_ADMCK_DIV = 4
3595 12:11:33.130904 DQ_TRACK_CA_EN = 0
3596 12:11:33.133801 CA_PICK = 600
3597 12:11:33.137386 CA_MCKIO = 600
3598 12:11:33.140440 MCKIO_SEMI = 0
3599 12:11:33.143488 PLL_FREQ = 2288
3600 12:11:33.146903 DQ_UI_PI_RATIO = 32
3601 12:11:33.146977 CA_UI_PI_RATIO = 0
3602 12:11:33.150738 ===================================
3603 12:11:33.155495 ===================================
3604 12:11:33.157413 memory_type:LPDDR4
3605 12:11:33.160236 GP_NUM : 10
3606 12:11:33.160306 SRAM_EN : 1
3607 12:11:33.164196 MD32_EN : 0
3608 12:11:33.166890 ===================================
3609 12:11:33.170094 [ANA_INIT] >>>>>>>>>>>>>>
3610 12:11:33.173854 <<<<<< [CONFIGURE PHASE]: ANA_TX
3611 12:11:33.176379 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3612 12:11:33.180282 ===================================
3613 12:11:33.180351 data_rate = 1200,PCW = 0X5800
3614 12:11:33.183068 ===================================
3615 12:11:33.189919 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3616 12:11:33.194619 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3617 12:11:33.199781 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3618 12:11:33.203323 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3619 12:11:33.206833 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3620 12:11:33.210004 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3621 12:11:33.213389 [ANA_INIT] flow start
3622 12:11:33.216664 [ANA_INIT] PLL >>>>>>>>
3623 12:11:33.216754 [ANA_INIT] PLL <<<<<<<<
3624 12:11:33.220125 [ANA_INIT] MIDPI >>>>>>>>
3625 12:11:33.223193 [ANA_INIT] MIDPI <<<<<<<<
3626 12:11:33.223263 [ANA_INIT] DLL >>>>>>>>
3627 12:11:33.226017 [ANA_INIT] flow end
3628 12:11:33.230463 ============ LP4 DIFF to SE enter ============
3629 12:11:33.233025 ============ LP4 DIFF to SE exit ============
3630 12:11:33.236036 [ANA_INIT] <<<<<<<<<<<<<
3631 12:11:33.239161 [Flow] Enable top DCM control >>>>>
3632 12:11:33.242551 [Flow] Enable top DCM control <<<<<
3633 12:11:33.246524 Enable DLL master slave shuffle
3634 12:11:33.252774 ==============================================================
3635 12:11:33.252859 Gating Mode config
3636 12:11:33.260116 ==============================================================
3637 12:11:33.262583 Config description:
3638 12:11:33.269101 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3639 12:11:33.276198 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3640 12:11:33.282790 SELPH_MODE 0: By rank 1: By Phase
3641 12:11:33.286397 ==============================================================
3642 12:11:33.289479 GAT_TRACK_EN = 1
3643 12:11:33.292848 RX_GATING_MODE = 2
3644 12:11:33.296318 RX_GATING_TRACK_MODE = 2
3645 12:11:33.299256 SELPH_MODE = 1
3646 12:11:33.302609 PICG_EARLY_EN = 1
3647 12:11:33.306166 VALID_LAT_VALUE = 1
3648 12:11:33.312990 ==============================================================
3649 12:11:33.316093 Enter into Gating configuration >>>>
3650 12:11:33.319458 Exit from Gating configuration <<<<
3651 12:11:33.322611 Enter into DVFS_PRE_config >>>>>
3652 12:11:33.332998 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3653 12:11:33.335636 Exit from DVFS_PRE_config <<<<<
3654 12:11:33.339812 Enter into PICG configuration >>>>
3655 12:11:33.342702 Exit from PICG configuration <<<<
3656 12:11:33.345675 [RX_INPUT] configuration >>>>>
3657 12:11:33.345752 [RX_INPUT] configuration <<<<<
3658 12:11:33.352013 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3659 12:11:33.358867 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3660 12:11:33.362053 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3661 12:11:33.369227 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3662 12:11:33.375338 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3663 12:11:33.382801 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3664 12:11:33.385254 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3665 12:11:33.388592 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3666 12:11:33.395385 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3667 12:11:33.398522 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3668 12:11:33.402298 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3669 12:11:33.408994 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3670 12:11:33.411543 ===================================
3671 12:11:33.411613 LPDDR4 DRAM CONFIGURATION
3672 12:11:33.415739 ===================================
3673 12:11:33.418993 EX_ROW_EN[0] = 0x0
3674 12:11:33.422126 EX_ROW_EN[1] = 0x0
3675 12:11:33.422202 LP4Y_EN = 0x0
3676 12:11:33.424975 WORK_FSP = 0x0
3677 12:11:33.425049 WL = 0x2
3678 12:11:33.428484 RL = 0x2
3679 12:11:33.428557 BL = 0x2
3680 12:11:33.431831 RPST = 0x0
3681 12:11:33.431904 RD_PRE = 0x0
3682 12:11:33.434648 WR_PRE = 0x1
3683 12:11:33.434724 WR_PST = 0x0
3684 12:11:33.438558 DBI_WR = 0x0
3685 12:11:33.438631 DBI_RD = 0x0
3686 12:11:33.441925 OTF = 0x1
3687 12:11:33.445941 ===================================
3688 12:11:33.448688 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3689 12:11:33.451954 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3690 12:11:33.458872 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3691 12:11:33.461991 ===================================
3692 12:11:33.462073 LPDDR4 DRAM CONFIGURATION
3693 12:11:33.465281 ===================================
3694 12:11:33.468420 EX_ROW_EN[0] = 0x10
3695 12:11:33.468502 EX_ROW_EN[1] = 0x0
3696 12:11:33.471237 LP4Y_EN = 0x0
3697 12:11:33.471319 WORK_FSP = 0x0
3698 12:11:33.475054 WL = 0x2
3699 12:11:33.478451 RL = 0x2
3700 12:11:33.478533 BL = 0x2
3701 12:11:33.481855 RPST = 0x0
3702 12:11:33.481937 RD_PRE = 0x0
3703 12:11:33.485457 WR_PRE = 0x1
3704 12:11:33.485538 WR_PST = 0x0
3705 12:11:33.488106 DBI_WR = 0x0
3706 12:11:33.488187 DBI_RD = 0x0
3707 12:11:33.491974 OTF = 0x1
3708 12:11:33.494976 ===================================
3709 12:11:33.501521 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3710 12:11:33.504695 nWR fixed to 30
3711 12:11:33.504805 [ModeRegInit_LP4] CH0 RK0
3712 12:11:33.507868 [ModeRegInit_LP4] CH0 RK1
3713 12:11:33.511173 [ModeRegInit_LP4] CH1 RK0
3714 12:11:33.514681 [ModeRegInit_LP4] CH1 RK1
3715 12:11:33.514762 match AC timing 16
3716 12:11:33.517726 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3717 12:11:33.524309 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3718 12:11:33.527883 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3719 12:11:33.531321 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3720 12:11:33.537345 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3721 12:11:33.537431 ==
3722 12:11:33.540779 Dram Type= 6, Freq= 0, CH_0, rank 0
3723 12:11:33.544384 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3724 12:11:33.544466 ==
3725 12:11:33.550570 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3726 12:11:33.557614 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3727 12:11:33.560549 [CA 0] Center 36 (6~66) winsize 61
3728 12:11:33.564495 [CA 1] Center 35 (5~66) winsize 62
3729 12:11:33.567598 [CA 2] Center 34 (4~65) winsize 62
3730 12:11:33.570944 [CA 3] Center 34 (4~65) winsize 62
3731 12:11:33.574915 [CA 4] Center 33 (3~64) winsize 62
3732 12:11:33.577237 [CA 5] Center 33 (3~64) winsize 62
3733 12:11:33.577307
3734 12:11:33.581207 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3735 12:11:33.581275
3736 12:11:33.584242 [CATrainingPosCal] consider 1 rank data
3737 12:11:33.587003 u2DelayCellTimex100 = 270/100 ps
3738 12:11:33.590353 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3739 12:11:33.594111 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3740 12:11:33.597034 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3741 12:11:33.600605 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3742 12:11:33.603953 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3743 12:11:33.607119 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3744 12:11:33.607193
3745 12:11:33.614353 CA PerBit enable=1, Macro0, CA PI delay=33
3746 12:11:33.614436
3747 12:11:33.614501 [CBTSetCACLKResult] CA Dly = 33
3748 12:11:33.617125 CS Dly: 5 (0~36)
3749 12:11:33.617207 ==
3750 12:11:33.620590 Dram Type= 6, Freq= 0, CH_0, rank 1
3751 12:11:33.623755 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3752 12:11:33.623837 ==
3753 12:11:33.630251 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3754 12:11:33.636971 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3755 12:11:33.640406 [CA 0] Center 35 (5~66) winsize 62
3756 12:11:33.643693 [CA 1] Center 35 (5~66) winsize 62
3757 12:11:33.646894 [CA 2] Center 34 (4~65) winsize 62
3758 12:11:33.650130 [CA 3] Center 34 (3~65) winsize 63
3759 12:11:33.653858 [CA 4] Center 33 (3~64) winsize 62
3760 12:11:33.656853 [CA 5] Center 33 (3~64) winsize 62
3761 12:11:33.656935
3762 12:11:33.660145 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3763 12:11:33.660226
3764 12:11:33.663184 [CATrainingPosCal] consider 2 rank data
3765 12:11:33.666662 u2DelayCellTimex100 = 270/100 ps
3766 12:11:33.670659 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3767 12:11:33.673807 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3768 12:11:33.676660 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3769 12:11:33.679552 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3770 12:11:33.683013 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3771 12:11:33.689970 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3772 12:11:33.690046
3773 12:11:33.692972 CA PerBit enable=1, Macro0, CA PI delay=33
3774 12:11:33.693051
3775 12:11:33.696125 [CBTSetCACLKResult] CA Dly = 33
3776 12:11:33.696193 CS Dly: 4 (0~35)
3777 12:11:33.696254
3778 12:11:33.700254 ----->DramcWriteLeveling(PI) begin...
3779 12:11:33.700323 ==
3780 12:11:33.703686 Dram Type= 6, Freq= 0, CH_0, rank 0
3781 12:11:33.706855 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3782 12:11:33.709579 ==
3783 12:11:33.713431 Write leveling (Byte 0): 31 => 31
3784 12:11:33.713501 Write leveling (Byte 1): 28 => 28
3785 12:11:33.716687 DramcWriteLeveling(PI) end<-----
3786 12:11:33.716791
3787 12:11:33.716899 ==
3788 12:11:33.720052 Dram Type= 6, Freq= 0, CH_0, rank 0
3789 12:11:33.725908 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3790 12:11:33.725982 ==
3791 12:11:33.729309 [Gating] SW mode calibration
3792 12:11:33.736116 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3793 12:11:33.739116 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3794 12:11:33.747227 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3795 12:11:33.749319 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3796 12:11:33.753511 0 5 8 | B1->B0 | 3333 3030 | 0 1 | (0 0) (1 1)
3797 12:11:33.759221 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3798 12:11:33.762981 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3799 12:11:33.766099 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3800 12:11:33.772457 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3801 12:11:33.775727 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3802 12:11:33.779086 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3803 12:11:33.783134 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3804 12:11:33.789705 0 6 8 | B1->B0 | 2c2c 2f2f | 1 0 | (0 0) (0 0)
3805 12:11:33.793135 0 6 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3806 12:11:33.796481 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3807 12:11:33.802704 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3808 12:11:33.806985 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3809 12:11:33.810007 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3810 12:11:33.816200 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3811 12:11:33.819785 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3812 12:11:33.822483 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3813 12:11:33.829146 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3814 12:11:33.832637 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 12:11:33.835815 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 12:11:33.842247 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 12:11:33.845863 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 12:11:33.848952 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 12:11:33.855549 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 12:11:33.859449 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 12:11:33.862744 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 12:11:33.869010 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 12:11:33.872297 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3824 12:11:33.875492 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3825 12:11:33.882041 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3826 12:11:33.885603 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3827 12:11:33.888780 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3828 12:11:33.895186 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3829 12:11:33.898523 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3830 12:11:33.902274 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3831 12:11:33.905318 Total UI for P1: 0, mck2ui 16
3832 12:11:33.908212 best dqsien dly found for B0: ( 0, 9, 10)
3833 12:11:33.912084 Total UI for P1: 0, mck2ui 16
3834 12:11:33.915740 best dqsien dly found for B1: ( 0, 9, 10)
3835 12:11:33.918937 best DQS0 dly(MCK, UI, PI) = (0, 9, 10)
3836 12:11:33.922218 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3837 12:11:33.922290
3838 12:11:33.928088 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 10)
3839 12:11:33.932034 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3840 12:11:33.935548 [Gating] SW calibration Done
3841 12:11:33.935650 ==
3842 12:11:33.938817 Dram Type= 6, Freq= 0, CH_0, rank 0
3843 12:11:33.941188 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3844 12:11:33.941259 ==
3845 12:11:33.941320 RX Vref Scan: 0
3846 12:11:33.941386
3847 12:11:33.945023 RX Vref 0 -> 0, step: 1
3848 12:11:33.945105
3849 12:11:33.948572 RX Delay -230 -> 252, step: 16
3850 12:11:33.951357 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3851 12:11:33.954645 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
3852 12:11:33.961620 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
3853 12:11:33.964583 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3854 12:11:33.968379 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3855 12:11:33.971601 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
3856 12:11:33.978265 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3857 12:11:33.982039 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3858 12:11:33.984487 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3859 12:11:33.987724 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3860 12:11:33.991725 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3861 12:11:33.997776 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3862 12:11:34.001599 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3863 12:11:34.004441 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3864 12:11:34.007893 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3865 12:11:34.014996 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3866 12:11:34.015079 ==
3867 12:11:34.017850 Dram Type= 6, Freq= 0, CH_0, rank 0
3868 12:11:34.021860 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3869 12:11:34.021943 ==
3870 12:11:34.022008 DQS Delay:
3871 12:11:34.024519 DQS0 = 0, DQS1 = 0
3872 12:11:34.024601 DQM Delay:
3873 12:11:34.027942 DQM0 = 41, DQM1 = 33
3874 12:11:34.028024 DQ Delay:
3875 12:11:34.031012 DQ0 =33, DQ1 =41, DQ2 =41, DQ3 =33
3876 12:11:34.034167 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
3877 12:11:34.037972 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3878 12:11:34.041624 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3879 12:11:34.041707
3880 12:11:34.041772
3881 12:11:34.041831 ==
3882 12:11:34.044313 Dram Type= 6, Freq= 0, CH_0, rank 0
3883 12:11:34.048025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3884 12:11:34.050970 ==
3885 12:11:34.051052
3886 12:11:34.051116
3887 12:11:34.051176 TX Vref Scan disable
3888 12:11:34.054605 == TX Byte 0 ==
3889 12:11:34.058133 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3890 12:11:34.061253 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3891 12:11:34.063900 == TX Byte 1 ==
3892 12:11:34.067905 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
3893 12:11:34.074594 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
3894 12:11:34.074676 ==
3895 12:11:34.078080 Dram Type= 6, Freq= 0, CH_0, rank 0
3896 12:11:34.081600 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3897 12:11:34.081683 ==
3898 12:11:34.081748
3899 12:11:34.081808
3900 12:11:34.083987 TX Vref Scan disable
3901 12:11:34.087534 == TX Byte 0 ==
3902 12:11:34.090831 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3903 12:11:34.094333 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3904 12:11:34.097363 == TX Byte 1 ==
3905 12:11:34.100538 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3906 12:11:34.104310 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3907 12:11:34.104392
3908 12:11:34.104457 [DATLAT]
3909 12:11:34.107082 Freq=600, CH0 RK0
3910 12:11:34.107164
3911 12:11:34.107228 DATLAT Default: 0x9
3912 12:11:34.111502 0, 0xFFFF, sum = 0
3913 12:11:34.111591 1, 0xFFFF, sum = 0
3914 12:11:34.114129 2, 0xFFFF, sum = 0
3915 12:11:34.117680 3, 0xFFFF, sum = 0
3916 12:11:34.117763 4, 0xFFFF, sum = 0
3917 12:11:34.121064 5, 0xFFFF, sum = 0
3918 12:11:34.121147 6, 0xFFFF, sum = 0
3919 12:11:34.124011 7, 0x0, sum = 1
3920 12:11:34.124094 8, 0x0, sum = 2
3921 12:11:34.124160 9, 0x0, sum = 3
3922 12:11:34.127651 10, 0x0, sum = 4
3923 12:11:34.127748 best_step = 8
3924 12:11:34.127814
3925 12:11:34.127874 ==
3926 12:11:34.130919 Dram Type= 6, Freq= 0, CH_0, rank 0
3927 12:11:34.137411 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3928 12:11:34.137494 ==
3929 12:11:34.137559 RX Vref Scan: 1
3930 12:11:34.137620
3931 12:11:34.140591 RX Vref 0 -> 0, step: 1
3932 12:11:34.140673
3933 12:11:34.143853 RX Delay -195 -> 252, step: 8
3934 12:11:34.143935
3935 12:11:34.147513 Set Vref, RX VrefLevel [Byte0]: 46
3936 12:11:34.150972 [Byte1]: 47
3937 12:11:34.151054
3938 12:11:34.154314 Final RX Vref Byte 0 = 46 to rank0
3939 12:11:34.157041 Final RX Vref Byte 1 = 47 to rank0
3940 12:11:34.161637 Final RX Vref Byte 0 = 46 to rank1
3941 12:11:34.163924 Final RX Vref Byte 1 = 47 to rank1==
3942 12:11:34.167210 Dram Type= 6, Freq= 0, CH_0, rank 0
3943 12:11:34.170800 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3944 12:11:34.170883 ==
3945 12:11:34.174162 DQS Delay:
3946 12:11:34.174244 DQS0 = 0, DQS1 = 0
3947 12:11:34.178403 DQM Delay:
3948 12:11:34.178485 DQM0 = 40, DQM1 = 30
3949 12:11:34.178550 DQ Delay:
3950 12:11:34.181041 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
3951 12:11:34.183470 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
3952 12:11:34.187492 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =24
3953 12:11:34.190747 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
3954 12:11:34.190829
3955 12:11:34.190893
3956 12:11:34.201369 [DQSOSCAuto] RK0, (LSB)MR18= 0x5454, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
3957 12:11:34.203966 CH0 RK0: MR19=808, MR18=5454
3958 12:11:34.207474 CH0_RK0: MR19=0x808, MR18=0x5454, DQSOSC=393, MR23=63, INC=169, DEC=113
3959 12:11:34.209939
3960 12:11:34.213498 ----->DramcWriteLeveling(PI) begin...
3961 12:11:34.213581 ==
3962 12:11:34.216925 Dram Type= 6, Freq= 0, CH_0, rank 1
3963 12:11:34.220533 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3964 12:11:34.220616 ==
3965 12:11:34.223282 Write leveling (Byte 0): 30 => 30
3966 12:11:34.226750 Write leveling (Byte 1): 30 => 30
3967 12:11:34.229957 DramcWriteLeveling(PI) end<-----
3968 12:11:34.230039
3969 12:11:34.230104 ==
3970 12:11:34.233662 Dram Type= 6, Freq= 0, CH_0, rank 1
3971 12:11:34.237196 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3972 12:11:34.237278 ==
3973 12:11:34.239950 [Gating] SW mode calibration
3974 12:11:34.246593 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3975 12:11:34.254589 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3976 12:11:34.256909 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 12:11:34.259966 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 12:11:34.266833 0 5 8 | B1->B0 | 3232 3030 | 1 1 | (1 1) (1 0)
3979 12:11:34.269935 0 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
3980 12:11:34.273343 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 12:11:34.279701 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 12:11:34.283685 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 12:11:34.286452 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 12:11:34.293225 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 12:11:34.296304 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 12:11:34.299598 0 6 8 | B1->B0 | 2a2a 3232 | 0 0 | (0 0) (0 0)
3987 12:11:34.307079 0 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3988 12:11:34.309411 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 12:11:34.312948 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 12:11:34.319491 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 12:11:34.323389 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 12:11:34.327059 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 12:11:34.329961 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 12:11:34.336530 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3995 12:11:34.340117 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 12:11:34.343137 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 12:11:34.350134 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 12:11:34.352639 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 12:11:34.356633 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 12:11:34.362590 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 12:11:34.365860 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 12:11:34.369169 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 12:11:34.375811 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 12:11:34.379385 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 12:11:34.382501 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 12:11:34.390042 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 12:11:34.392313 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 12:11:34.395913 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 12:11:34.403094 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 12:11:34.405905 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4011 12:11:34.409776 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 12:11:34.412257 Total UI for P1: 0, mck2ui 16
4013 12:11:34.415965 best dqsien dly found for B0: ( 0, 9, 8)
4014 12:11:34.419631 Total UI for P1: 0, mck2ui 16
4015 12:11:34.422640 best dqsien dly found for B1: ( 0, 9, 8)
4016 12:11:34.425375 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4017 12:11:34.428957 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4018 12:11:34.429039
4019 12:11:34.435596 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4020 12:11:34.439176 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4021 12:11:34.439258 [Gating] SW calibration Done
4022 12:11:34.442643 ==
4023 12:11:34.445089 Dram Type= 6, Freq= 0, CH_0, rank 1
4024 12:11:34.449215 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4025 12:11:34.449298 ==
4026 12:11:34.449363 RX Vref Scan: 0
4027 12:11:34.449425
4028 12:11:34.452203 RX Vref 0 -> 0, step: 1
4029 12:11:34.452317
4030 12:11:34.455353 RX Delay -230 -> 252, step: 16
4031 12:11:34.459161 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4032 12:11:34.462178 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4033 12:11:34.468893 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4034 12:11:34.472155 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4035 12:11:34.475020 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4036 12:11:34.478442 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4037 12:11:34.485037 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4038 12:11:34.489868 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4039 12:11:34.491875 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4040 12:11:34.495040 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4041 12:11:34.498612 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4042 12:11:34.505300 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4043 12:11:34.508698 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4044 12:11:34.512118 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4045 12:11:34.515136 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4046 12:11:34.521334 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4047 12:11:34.521416 ==
4048 12:11:34.524857 Dram Type= 6, Freq= 0, CH_0, rank 1
4049 12:11:34.528105 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4050 12:11:34.528191 ==
4051 12:11:34.528256 DQS Delay:
4052 12:11:34.531850 DQS0 = 0, DQS1 = 0
4053 12:11:34.531931 DQM Delay:
4054 12:11:34.535170 DQM0 = 40, DQM1 = 31
4055 12:11:34.535251 DQ Delay:
4056 12:11:34.538316 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4057 12:11:34.541655 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4058 12:11:34.544813 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4059 12:11:34.547760 DQ12 =41, DQ13 =33, DQ14 =33, DQ15 =41
4060 12:11:34.547847
4061 12:11:34.547912
4062 12:11:34.547981 ==
4063 12:11:34.551791 Dram Type= 6, Freq= 0, CH_0, rank 1
4064 12:11:34.554890 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4065 12:11:34.557724 ==
4066 12:11:34.557796
4067 12:11:34.557865
4068 12:11:34.557924 TX Vref Scan disable
4069 12:11:34.561316 == TX Byte 0 ==
4070 12:11:34.564761 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4071 12:11:34.567884 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4072 12:11:34.571296 == TX Byte 1 ==
4073 12:11:34.574605 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4074 12:11:34.581066 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4075 12:11:34.581142 ==
4076 12:11:34.584395 Dram Type= 6, Freq= 0, CH_0, rank 1
4077 12:11:34.588381 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4078 12:11:34.588453 ==
4079 12:11:34.588514
4080 12:11:34.588578
4081 12:11:34.591201 TX Vref Scan disable
4082 12:11:34.594188 == TX Byte 0 ==
4083 12:11:34.597825 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4084 12:11:34.600478 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4085 12:11:34.604017 == TX Byte 1 ==
4086 12:11:34.607419 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4087 12:11:34.610547 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4088 12:11:34.610616
4089 12:11:34.610676 [DATLAT]
4090 12:11:34.613981 Freq=600, CH0 RK1
4091 12:11:34.614047
4092 12:11:34.617118 DATLAT Default: 0x8
4093 12:11:34.617196 0, 0xFFFF, sum = 0
4094 12:11:34.620405 1, 0xFFFF, sum = 0
4095 12:11:34.620479 2, 0xFFFF, sum = 0
4096 12:11:34.624297 3, 0xFFFF, sum = 0
4097 12:11:34.624367 4, 0xFFFF, sum = 0
4098 12:11:34.626866 5, 0xFFFF, sum = 0
4099 12:11:34.626934 6, 0xFFFF, sum = 0
4100 12:11:34.630613 7, 0x0, sum = 1
4101 12:11:34.630681 8, 0x0, sum = 2
4102 12:11:34.633634 9, 0x0, sum = 3
4103 12:11:34.633708 10, 0x0, sum = 4
4104 12:11:34.633769 best_step = 8
4105 12:11:34.633826
4106 12:11:34.638822 ==
4107 12:11:34.638889 Dram Type= 6, Freq= 0, CH_0, rank 1
4108 12:11:34.643875 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4109 12:11:34.643948 ==
4110 12:11:34.644010 RX Vref Scan: 0
4111 12:11:34.644069
4112 12:11:34.647287 RX Vref 0 -> 0, step: 1
4113 12:11:34.647361
4114 12:11:34.650247 RX Delay -195 -> 252, step: 8
4115 12:11:34.657249 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4116 12:11:34.660955 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4117 12:11:34.663211 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4118 12:11:34.667138 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4119 12:11:34.670641 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4120 12:11:34.676790 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4121 12:11:34.680811 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4122 12:11:34.683489 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4123 12:11:34.686548 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4124 12:11:34.693448 iDelay=205, Bit 9, Center 16 (-131 ~ 164) 296
4125 12:11:34.697469 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4126 12:11:34.699546 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4127 12:11:34.703836 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4128 12:11:34.710250 iDelay=205, Bit 13, Center 36 (-115 ~ 188) 304
4129 12:11:34.713161 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4130 12:11:34.716303 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4131 12:11:34.716409 ==
4132 12:11:34.719707 Dram Type= 6, Freq= 0, CH_0, rank 1
4133 12:11:34.723367 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4134 12:11:34.723438 ==
4135 12:11:34.727364 DQS Delay:
4136 12:11:34.727433 DQS0 = 0, DQS1 = 0
4137 12:11:34.729504 DQM Delay:
4138 12:11:34.729587 DQM0 = 41, DQM1 = 32
4139 12:11:34.729652 DQ Delay:
4140 12:11:34.733289 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4141 12:11:34.736711 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4142 12:11:34.739912 DQ8 =20, DQ9 =16, DQ10 =32, DQ11 =24
4143 12:11:34.742988 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4144 12:11:34.743059
4145 12:11:34.746130
4146 12:11:34.753890 [DQSOSCAuto] RK1, (LSB)MR18= 0x6262, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4147 12:11:34.755925 CH0 RK1: MR19=808, MR18=6262
4148 12:11:34.762595 CH0_RK1: MR19=0x808, MR18=0x6262, DQSOSC=391, MR23=63, INC=171, DEC=114
4149 12:11:34.766384 [RxdqsGatingPostProcess] freq 600
4150 12:11:34.769092 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4151 12:11:34.772242 Pre-setting of DQS Precalculation
4152 12:11:34.779560 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4153 12:11:34.779636 ==
4154 12:11:34.782087 Dram Type= 6, Freq= 0, CH_1, rank 0
4155 12:11:34.785686 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4156 12:11:34.785757 ==
4157 12:11:34.793853 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4158 12:11:34.796162 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4159 12:11:34.800013 [CA 0] Center 35 (5~66) winsize 62
4160 12:11:34.802926 [CA 1] Center 35 (5~66) winsize 62
4161 12:11:34.807093 [CA 2] Center 33 (3~64) winsize 62
4162 12:11:34.809519 [CA 3] Center 33 (3~64) winsize 62
4163 12:11:34.813799 [CA 4] Center 33 (2~64) winsize 63
4164 12:11:34.816692 [CA 5] Center 32 (2~63) winsize 62
4165 12:11:34.816769
4166 12:11:34.819835 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4167 12:11:34.819906
4168 12:11:34.823647 [CATrainingPosCal] consider 1 rank data
4169 12:11:34.826723 u2DelayCellTimex100 = 270/100 ps
4170 12:11:34.829527 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4171 12:11:34.836198 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4172 12:11:34.839542 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4173 12:11:34.842938 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4174 12:11:34.846136 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4175 12:11:34.849823 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4176 12:11:34.849898
4177 12:11:34.853113 CA PerBit enable=1, Macro0, CA PI delay=32
4178 12:11:34.853214
4179 12:11:34.856511 [CBTSetCACLKResult] CA Dly = 32
4180 12:11:34.859043 CS Dly: 4 (0~35)
4181 12:11:34.859120 ==
4182 12:11:34.862625 Dram Type= 6, Freq= 0, CH_1, rank 1
4183 12:11:34.866432 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4184 12:11:34.866503 ==
4185 12:11:34.872913 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4186 12:11:34.875628 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4187 12:11:34.880238 [CA 0] Center 35 (4~66) winsize 63
4188 12:11:34.883448 [CA 1] Center 34 (4~65) winsize 62
4189 12:11:34.886675 [CA 2] Center 33 (3~64) winsize 62
4190 12:11:34.889617 [CA 3] Center 33 (3~64) winsize 62
4191 12:11:34.893194 [CA 4] Center 32 (2~63) winsize 62
4192 12:11:34.896873 [CA 5] Center 32 (2~63) winsize 62
4193 12:11:34.896943
4194 12:11:34.900029 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4195 12:11:34.900129
4196 12:11:34.903230 [CATrainingPosCal] consider 2 rank data
4197 12:11:34.906236 u2DelayCellTimex100 = 270/100 ps
4198 12:11:34.909279 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4199 12:11:34.916850 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4200 12:11:34.920305 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4201 12:11:34.922529 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4202 12:11:34.926737 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4203 12:11:34.930073 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4204 12:11:34.930154
4205 12:11:34.932943 CA PerBit enable=1, Macro0, CA PI delay=32
4206 12:11:34.933013
4207 12:11:34.936134 [CBTSetCACLKResult] CA Dly = 32
4208 12:11:34.936209 CS Dly: 4 (0~35)
4209 12:11:34.939483
4210 12:11:34.942670 ----->DramcWriteLeveling(PI) begin...
4211 12:11:34.942751 ==
4212 12:11:34.946026 Dram Type= 6, Freq= 0, CH_1, rank 0
4213 12:11:34.949776 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4214 12:11:34.949852 ==
4215 12:11:34.952973 Write leveling (Byte 0): 25 => 25
4216 12:11:34.955778 Write leveling (Byte 1): 28 => 28
4217 12:11:34.959199 DramcWriteLeveling(PI) end<-----
4218 12:11:34.959270
4219 12:11:34.959339 ==
4220 12:11:34.962510 Dram Type= 6, Freq= 0, CH_1, rank 0
4221 12:11:34.966025 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4222 12:11:34.966100 ==
4223 12:11:34.969339 [Gating] SW mode calibration
4224 12:11:34.976517 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4225 12:11:34.982898 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4226 12:11:34.985684 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4227 12:11:34.989209 0 5 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
4228 12:11:34.996579 0 5 8 | B1->B0 | 3030 2727 | 0 0 | (0 1) (1 1)
4229 12:11:34.998936 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 12:11:35.001925 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 12:11:35.008855 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 12:11:35.012933 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 12:11:35.015618 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 12:11:35.022254 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 12:11:35.025342 0 6 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
4236 12:11:35.028948 0 6 8 | B1->B0 | 3636 3f3f | 1 0 | (0 0) (0 0)
4237 12:11:35.036336 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 12:11:35.038849 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 12:11:35.042034 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 12:11:35.045328 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 12:11:35.052069 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 12:11:35.055441 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 12:11:35.059474 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4244 12:11:35.065605 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4245 12:11:35.068809 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 12:11:35.072379 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 12:11:35.078724 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 12:11:35.081692 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 12:11:35.085359 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 12:11:35.091983 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 12:11:35.095056 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 12:11:35.098827 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 12:11:35.104818 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 12:11:35.108582 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 12:11:35.111623 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 12:11:35.118261 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 12:11:35.121461 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 12:11:35.124606 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 12:11:35.131450 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4260 12:11:35.134662 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4261 12:11:35.137759 Total UI for P1: 0, mck2ui 16
4262 12:11:35.141691 best dqsien dly found for B0: ( 0, 9, 4)
4263 12:11:35.144826 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 12:11:35.147808 Total UI for P1: 0, mck2ui 16
4265 12:11:35.152053 best dqsien dly found for B1: ( 0, 9, 8)
4266 12:11:35.154990 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4267 12:11:35.157569 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4268 12:11:35.157642
4269 12:11:35.164980 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4270 12:11:35.168618 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4271 12:11:35.171114 [Gating] SW calibration Done
4272 12:11:35.171191 ==
4273 12:11:35.174609 Dram Type= 6, Freq= 0, CH_1, rank 0
4274 12:11:35.178116 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4275 12:11:35.178189 ==
4276 12:11:35.178258 RX Vref Scan: 0
4277 12:11:35.178316
4278 12:11:35.182781 RX Vref 0 -> 0, step: 1
4279 12:11:35.182854
4280 12:11:35.184753 RX Delay -230 -> 252, step: 16
4281 12:11:35.188576 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4282 12:11:35.191226 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4283 12:11:35.197940 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4284 12:11:35.201805 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4285 12:11:35.204658 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4286 12:11:35.207632 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4287 12:11:35.213975 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4288 12:11:35.217521 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4289 12:11:35.220816 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4290 12:11:35.223997 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4291 12:11:35.227906 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4292 12:11:35.234042 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4293 12:11:35.237327 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4294 12:11:35.241000 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4295 12:11:35.244430 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4296 12:11:35.250703 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4297 12:11:35.250783 ==
4298 12:11:35.254145 Dram Type= 6, Freq= 0, CH_1, rank 0
4299 12:11:35.257330 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4300 12:11:35.257403 ==
4301 12:11:35.257474 DQS Delay:
4302 12:11:35.260821 DQS0 = 0, DQS1 = 0
4303 12:11:35.260891 DQM Delay:
4304 12:11:35.263903 DQM0 = 42, DQM1 = 35
4305 12:11:35.263981 DQ Delay:
4306 12:11:35.266894 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4307 12:11:35.270277 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =41
4308 12:11:35.273493 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4309 12:11:35.277098 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4310 12:11:35.277171
4311 12:11:35.277238
4312 12:11:35.277296 ==
4313 12:11:35.280243 Dram Type= 6, Freq= 0, CH_1, rank 0
4314 12:11:35.284161 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4315 12:11:35.287202 ==
4316 12:11:35.287277
4317 12:11:35.287336
4318 12:11:35.287393 TX Vref Scan disable
4319 12:11:35.291290 == TX Byte 0 ==
4320 12:11:35.293660 Update DQ dly =570 (2 ,1, 26) DQ OEN =(1 ,6)
4321 12:11:35.299928 Update DQM dly =570 (2 ,1, 26) DQM OEN =(1 ,6)
4322 12:11:35.300001 == TX Byte 1 ==
4323 12:11:35.303135 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4324 12:11:35.310316 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4325 12:11:35.310399 ==
4326 12:11:35.313445 Dram Type= 6, Freq= 0, CH_1, rank 0
4327 12:11:35.317353 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4328 12:11:35.317430 ==
4329 12:11:35.317492
4330 12:11:35.317549
4331 12:11:35.319744 TX Vref Scan disable
4332 12:11:35.323942 == TX Byte 0 ==
4333 12:11:35.326914 Update DQ dly =569 (2 ,1, 25) DQ OEN =(1 ,6)
4334 12:11:35.329997 Update DQM dly =569 (2 ,1, 25) DQM OEN =(1 ,6)
4335 12:11:35.333687 == TX Byte 1 ==
4336 12:11:35.336650 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4337 12:11:35.339758 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4338 12:11:35.339841
4339 12:11:35.339904 [DATLAT]
4340 12:11:35.343087 Freq=600, CH1 RK0
4341 12:11:35.343156
4342 12:11:35.347165 DATLAT Default: 0x9
4343 12:11:35.347244 0, 0xFFFF, sum = 0
4344 12:11:35.350793 1, 0xFFFF, sum = 0
4345 12:11:35.350872 2, 0xFFFF, sum = 0
4346 12:11:35.353538 3, 0xFFFF, sum = 0
4347 12:11:35.353619 4, 0xFFFF, sum = 0
4348 12:11:35.357530 5, 0xFFFF, sum = 0
4349 12:11:35.357605 6, 0xFFFF, sum = 0
4350 12:11:35.360239 7, 0x0, sum = 1
4351 12:11:35.360309 8, 0x0, sum = 2
4352 12:11:35.363158 9, 0x0, sum = 3
4353 12:11:35.363228 10, 0x0, sum = 4
4354 12:11:35.363289 best_step = 8
4355 12:11:35.363353
4356 12:11:35.366397 ==
4357 12:11:35.369376 Dram Type= 6, Freq= 0, CH_1, rank 0
4358 12:11:35.372943 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4359 12:11:35.373018 ==
4360 12:11:35.373080 RX Vref Scan: 1
4361 12:11:35.373145
4362 12:11:35.377104 RX Vref 0 -> 0, step: 1
4363 12:11:35.377174
4364 12:11:35.379767 RX Delay -195 -> 252, step: 8
4365 12:11:35.379835
4366 12:11:35.382660 Set Vref, RX VrefLevel [Byte0]: 53
4367 12:11:35.386412 [Byte1]: 50
4368 12:11:35.386514
4369 12:11:35.389851 Final RX Vref Byte 0 = 53 to rank0
4370 12:11:35.393868 Final RX Vref Byte 1 = 50 to rank0
4371 12:11:35.396432 Final RX Vref Byte 0 = 53 to rank1
4372 12:11:35.399344 Final RX Vref Byte 1 = 50 to rank1==
4373 12:11:35.402591 Dram Type= 6, Freq= 0, CH_1, rank 0
4374 12:11:35.409131 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4375 12:11:35.409235 ==
4376 12:11:35.409326 DQS Delay:
4377 12:11:35.409408 DQS0 = 0, DQS1 = 0
4378 12:11:35.412405 DQM Delay:
4379 12:11:35.412472 DQM0 = 37, DQM1 = 30
4380 12:11:35.415603 DQ Delay:
4381 12:11:35.418881 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4382 12:11:35.423165 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4383 12:11:35.425534 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =24
4384 12:11:35.428666 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4385 12:11:35.428788
4386 12:11:35.428850
4387 12:11:35.436304 [DQSOSCAuto] RK0, (LSB)MR18= 0x7272, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4388 12:11:35.439367 CH1 RK0: MR19=808, MR18=7272
4389 12:11:35.445474 CH1_RK0: MR19=0x808, MR18=0x7272, DQSOSC=388, MR23=63, INC=174, DEC=116
4390 12:11:35.445556
4391 12:11:35.449216 ----->DramcWriteLeveling(PI) begin...
4392 12:11:35.449292 ==
4393 12:11:35.452465 Dram Type= 6, Freq= 0, CH_1, rank 1
4394 12:11:35.455551 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4395 12:11:35.455626 ==
4396 12:11:35.459303 Write leveling (Byte 0): 27 => 27
4397 12:11:35.461823 Write leveling (Byte 1): 27 => 27
4398 12:11:35.465376 DramcWriteLeveling(PI) end<-----
4399 12:11:35.465450
4400 12:11:35.465512 ==
4401 12:11:35.468829 Dram Type= 6, Freq= 0, CH_1, rank 1
4402 12:11:35.472072 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4403 12:11:35.472154 ==
4404 12:11:35.475307 [Gating] SW mode calibration
4405 12:11:35.481777 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4406 12:11:35.488331 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4407 12:11:35.491791 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4408 12:11:35.498615 0 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4409 12:11:35.502056 0 5 8 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
4410 12:11:35.504857 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 12:11:35.511930 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 12:11:35.514854 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 12:11:35.517872 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 12:11:35.525255 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 12:11:35.528395 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 12:11:35.531515 0 6 4 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
4417 12:11:35.537771 0 6 8 | B1->B0 | 3434 4343 | 1 0 | (0 0) (0 0)
4418 12:11:35.541466 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 12:11:35.544655 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 12:11:35.551354 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 12:11:35.554849 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 12:11:35.557661 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 12:11:35.564406 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 12:11:35.568464 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 12:11:35.570740 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 12:11:35.577842 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 12:11:35.581439 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 12:11:35.584323 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 12:11:35.591065 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 12:11:35.594362 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 12:11:35.597366 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 12:11:35.604023 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 12:11:35.607755 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 12:11:35.610976 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 12:11:35.617881 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 12:11:35.621003 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 12:11:35.624434 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 12:11:35.630435 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 12:11:35.634098 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 12:11:35.637210 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4441 12:11:35.640603 Total UI for P1: 0, mck2ui 16
4442 12:11:35.643820 best dqsien dly found for B0: ( 0, 9, 2)
4443 12:11:35.647061 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4444 12:11:35.653940 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4445 12:11:35.657187 Total UI for P1: 0, mck2ui 16
4446 12:11:35.660126 best dqsien dly found for B1: ( 0, 9, 6)
4447 12:11:35.663874 best DQS0 dly(MCK, UI, PI) = (0, 9, 2)
4448 12:11:35.667137 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4449 12:11:35.667209
4450 12:11:35.670357 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 2)
4451 12:11:35.674167 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4452 12:11:35.677065 [Gating] SW calibration Done
4453 12:11:35.677136 ==
4454 12:11:35.680001 Dram Type= 6, Freq= 0, CH_1, rank 1
4455 12:11:35.684187 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4456 12:11:35.684259 ==
4457 12:11:35.688412 RX Vref Scan: 0
4458 12:11:35.688492
4459 12:11:35.688554 RX Vref 0 -> 0, step: 1
4460 12:11:35.688612
4461 12:11:35.689961 RX Delay -230 -> 252, step: 16
4462 12:11:35.697076 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4463 12:11:35.699844 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4464 12:11:35.704309 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4465 12:11:35.706539 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4466 12:11:35.713505 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4467 12:11:35.716362 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4468 12:11:35.719798 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4469 12:11:35.723228 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4470 12:11:35.726451 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4471 12:11:35.733225 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4472 12:11:35.736508 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4473 12:11:35.740075 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4474 12:11:35.742762 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4475 12:11:35.749854 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4476 12:11:35.752854 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4477 12:11:35.756071 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4478 12:11:35.756146 ==
4479 12:11:35.759530 Dram Type= 6, Freq= 0, CH_1, rank 1
4480 12:11:35.767293 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4481 12:11:35.767403 ==
4482 12:11:35.767494 DQS Delay:
4483 12:11:35.769617 DQS0 = 0, DQS1 = 0
4484 12:11:35.769687 DQM Delay:
4485 12:11:35.769748 DQM0 = 40, DQM1 = 33
4486 12:11:35.772691 DQ Delay:
4487 12:11:35.776325 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4488 12:11:35.779655 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33
4489 12:11:35.783058 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4490 12:11:35.786387 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4491 12:11:35.786478
4492 12:11:35.786542
4493 12:11:35.786601 ==
4494 12:11:35.788711 Dram Type= 6, Freq= 0, CH_1, rank 1
4495 12:11:35.792199 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4496 12:11:35.792281 ==
4497 12:11:35.792344
4498 12:11:35.792402
4499 12:11:35.795753 TX Vref Scan disable
4500 12:11:35.798863 == TX Byte 0 ==
4501 12:11:35.801971 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4502 12:11:35.806219 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4503 12:11:35.808699 == TX Byte 1 ==
4504 12:11:35.812310 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4505 12:11:35.815872 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4506 12:11:35.815948 ==
4507 12:11:35.818924 Dram Type= 6, Freq= 0, CH_1, rank 1
4508 12:11:35.821986 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4509 12:11:35.825147 ==
4510 12:11:35.825222
4511 12:11:35.825290
4512 12:11:35.825348 TX Vref Scan disable
4513 12:11:35.828643 == TX Byte 0 ==
4514 12:11:35.832022 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4515 12:11:35.835611 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4516 12:11:35.838906 == TX Byte 1 ==
4517 12:11:35.842555 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4518 12:11:35.849221 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4519 12:11:35.849295
4520 12:11:35.849379 [DATLAT]
4521 12:11:35.849479 Freq=600, CH1 RK1
4522 12:11:35.849567
4523 12:11:35.852178 DATLAT Default: 0x8
4524 12:11:35.852273 0, 0xFFFF, sum = 0
4525 12:11:35.855482 1, 0xFFFF, sum = 0
4526 12:11:35.855561 2, 0xFFFF, sum = 0
4527 12:11:35.859185 3, 0xFFFF, sum = 0
4528 12:11:35.862218 4, 0xFFFF, sum = 0
4529 12:11:35.862300 5, 0xFFFF, sum = 0
4530 12:11:35.866045 6, 0xFFFF, sum = 0
4531 12:11:35.866129 7, 0x0, sum = 1
4532 12:11:35.866194 8, 0x0, sum = 2
4533 12:11:35.868573 9, 0x0, sum = 3
4534 12:11:35.868669 10, 0x0, sum = 4
4535 12:11:35.872450 best_step = 8
4536 12:11:35.872524
4537 12:11:35.872591 ==
4538 12:11:35.875618 Dram Type= 6, Freq= 0, CH_1, rank 1
4539 12:11:35.878922 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4540 12:11:35.879001 ==
4541 12:11:35.882143 RX Vref Scan: 0
4542 12:11:35.882218
4543 12:11:35.882278 RX Vref 0 -> 0, step: 1
4544 12:11:35.882335
4545 12:11:35.885450 RX Delay -195 -> 252, step: 8
4546 12:11:35.892631 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4547 12:11:35.896410 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4548 12:11:35.899468 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4549 12:11:35.902620 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4550 12:11:35.910156 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4551 12:11:35.912652 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4552 12:11:35.916399 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4553 12:11:35.919620 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4554 12:11:35.925359 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4555 12:11:35.929133 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4556 12:11:35.932551 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4557 12:11:35.935965 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4558 12:11:35.939588 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4559 12:11:35.946046 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4560 12:11:35.948806 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4561 12:11:35.952218 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4562 12:11:35.952295 ==
4563 12:11:35.955555 Dram Type= 6, Freq= 0, CH_1, rank 1
4564 12:11:35.962756 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4565 12:11:35.962832 ==
4566 12:11:35.962896 DQS Delay:
4567 12:11:35.962961 DQS0 = 0, DQS1 = 0
4568 12:11:35.965233 DQM Delay:
4569 12:11:35.965334 DQM0 = 37, DQM1 = 29
4570 12:11:35.968722 DQ Delay:
4571 12:11:35.971744 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4572 12:11:35.975177 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4573 12:11:35.975249 DQ8 =16, DQ9 =12, DQ10 =28, DQ11 =20
4574 12:11:35.982174 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4575 12:11:35.982257
4576 12:11:35.982322
4577 12:11:35.988580 [DQSOSCAuto] RK1, (LSB)MR18= 0x5555, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4578 12:11:35.992876 CH1 RK1: MR19=808, MR18=5555
4579 12:11:35.998382 CH1_RK1: MR19=0x808, MR18=0x5555, DQSOSC=393, MR23=63, INC=169, DEC=113
4580 12:11:36.002248 [RxdqsGatingPostProcess] freq 600
4581 12:11:36.005258 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4582 12:11:36.008632 Pre-setting of DQS Precalculation
4583 12:11:36.014874 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4584 12:11:36.022360 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4585 12:11:36.029361 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4586 12:11:36.029434
4587 12:11:36.029496
4588 12:11:36.031923 [Calibration Summary] 1200 Mbps
4589 12:11:36.031990 CH 0, Rank 0
4590 12:11:36.035242 SW Impedance : PASS
4591 12:11:36.038298 DUTY Scan : NO K
4592 12:11:36.038372 ZQ Calibration : PASS
4593 12:11:36.042542 Jitter Meter : NO K
4594 12:11:36.044848 CBT Training : PASS
4595 12:11:36.044925 Write leveling : PASS
4596 12:11:36.048261 RX DQS gating : PASS
4597 12:11:36.051862 RX DQ/DQS(RDDQC) : PASS
4598 12:11:36.051941 TX DQ/DQS : PASS
4599 12:11:36.055397 RX DATLAT : PASS
4600 12:11:36.055483 RX DQ/DQS(Engine): PASS
4601 12:11:36.058296 TX OE : NO K
4602 12:11:36.058370 All Pass.
4603 12:11:36.058432
4604 12:11:36.061261 CH 0, Rank 1
4605 12:11:36.061332 SW Impedance : PASS
4606 12:11:36.065110 DUTY Scan : NO K
4607 12:11:36.068334 ZQ Calibration : PASS
4608 12:11:36.068430 Jitter Meter : NO K
4609 12:11:36.072295 CBT Training : PASS
4610 12:11:36.074885 Write leveling : PASS
4611 12:11:36.074955 RX DQS gating : PASS
4612 12:11:36.078156 RX DQ/DQS(RDDQC) : PASS
4613 12:11:36.081446 TX DQ/DQS : PASS
4614 12:11:36.081517 RX DATLAT : PASS
4615 12:11:36.085291 RX DQ/DQS(Engine): PASS
4616 12:11:36.088517 TX OE : NO K
4617 12:11:36.088592 All Pass.
4618 12:11:36.088655
4619 12:11:36.088738 CH 1, Rank 0
4620 12:11:36.092100 SW Impedance : PASS
4621 12:11:36.094742 DUTY Scan : NO K
4622 12:11:36.094817 ZQ Calibration : PASS
4623 12:11:36.099932 Jitter Meter : NO K
4624 12:11:36.103623 CBT Training : PASS
4625 12:11:36.103697 Write leveling : PASS
4626 12:11:36.105217 RX DQS gating : PASS
4627 12:11:36.107833 RX DQ/DQS(RDDQC) : PASS
4628 12:11:36.107908 TX DQ/DQS : PASS
4629 12:11:36.111138 RX DATLAT : PASS
4630 12:11:36.111211 RX DQ/DQS(Engine): PASS
4631 12:11:36.114341 TX OE : NO K
4632 12:11:36.114418 All Pass.
4633 12:11:36.114488
4634 12:11:36.117830 CH 1, Rank 1
4635 12:11:36.117902 SW Impedance : PASS
4636 12:11:36.121399 DUTY Scan : NO K
4637 12:11:36.124832 ZQ Calibration : PASS
4638 12:11:36.124909 Jitter Meter : NO K
4639 12:11:36.127642 CBT Training : PASS
4640 12:11:36.131189 Write leveling : PASS
4641 12:11:36.131258 RX DQS gating : PASS
4642 12:11:36.134053 RX DQ/DQS(RDDQC) : PASS
4643 12:11:36.137293 TX DQ/DQS : PASS
4644 12:11:36.137362 RX DATLAT : PASS
4645 12:11:36.141049 RX DQ/DQS(Engine): PASS
4646 12:11:36.144430 TX OE : NO K
4647 12:11:36.144499 All Pass.
4648 12:11:36.144559
4649 12:11:36.147575 DramC Write-DBI off
4650 12:11:36.147641 PER_BANK_REFRESH: Hybrid Mode
4651 12:11:36.150963 TX_TRACKING: ON
4652 12:11:36.160536 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4653 12:11:36.164695 [FAST_K] Save calibration result to emmc
4654 12:11:36.167308 dramc_set_vcore_voltage set vcore to 662500
4655 12:11:36.167379 Read voltage for 933, 3
4656 12:11:36.170463 Vio18 = 0
4657 12:11:36.170532 Vcore = 662500
4658 12:11:36.170593 Vdram = 0
4659 12:11:36.174053 Vddq = 0
4660 12:11:36.174125 Vmddr = 0
4661 12:11:36.177070 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4662 12:11:36.183562 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4663 12:11:36.187023 MEM_TYPE=3, freq_sel=17
4664 12:11:36.190491 sv_algorithm_assistance_LP4_1600
4665 12:11:36.193524 ============ PULL DRAM RESETB DOWN ============
4666 12:11:36.197663 ========== PULL DRAM RESETB DOWN end =========
4667 12:11:36.203910 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4668 12:11:36.207568 ===================================
4669 12:11:36.207642 LPDDR4 DRAM CONFIGURATION
4670 12:11:36.210722 ===================================
4671 12:11:36.213555 EX_ROW_EN[0] = 0x0
4672 12:11:36.213626 EX_ROW_EN[1] = 0x0
4673 12:11:36.216697 LP4Y_EN = 0x0
4674 12:11:36.220906 WORK_FSP = 0x0
4675 12:11:36.220984 WL = 0x3
4676 12:11:36.224325 RL = 0x3
4677 12:11:36.224400 BL = 0x2
4678 12:11:36.227553 RPST = 0x0
4679 12:11:36.227622 RD_PRE = 0x0
4680 12:11:36.230041 WR_PRE = 0x1
4681 12:11:36.230114 WR_PST = 0x0
4682 12:11:36.234143 DBI_WR = 0x0
4683 12:11:36.234210 DBI_RD = 0x0
4684 12:11:36.237181 OTF = 0x1
4685 12:11:36.240465 ===================================
4686 12:11:36.243591 ===================================
4687 12:11:36.243659 ANA top config
4688 12:11:36.246716 ===================================
4689 12:11:36.250928 DLL_ASYNC_EN = 0
4690 12:11:36.253331 ALL_SLAVE_EN = 1
4691 12:11:36.253401 NEW_RANK_MODE = 1
4692 12:11:36.256600 DLL_IDLE_MODE = 1
4693 12:11:36.260457 LP45_APHY_COMB_EN = 1
4694 12:11:36.263145 TX_ODT_DIS = 1
4695 12:11:36.266605 NEW_8X_MODE = 1
4696 12:11:36.270359 ===================================
4697 12:11:36.274074 ===================================
4698 12:11:36.274144 data_rate = 1866
4699 12:11:36.276273 CKR = 1
4700 12:11:36.280173 DQ_P2S_RATIO = 8
4701 12:11:36.283444 ===================================
4702 12:11:36.287015 CA_P2S_RATIO = 8
4703 12:11:36.289982 DQ_CA_OPEN = 0
4704 12:11:36.292866 DQ_SEMI_OPEN = 0
4705 12:11:36.292962 CA_SEMI_OPEN = 0
4706 12:11:36.296276 CA_FULL_RATE = 0
4707 12:11:36.299932 DQ_CKDIV4_EN = 1
4708 12:11:36.303550 CA_CKDIV4_EN = 1
4709 12:11:36.306130 CA_PREDIV_EN = 0
4710 12:11:36.309636 PH8_DLY = 0
4711 12:11:36.309732 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4712 12:11:36.312903 DQ_AAMCK_DIV = 4
4713 12:11:36.316746 CA_AAMCK_DIV = 4
4714 12:11:36.319405 CA_ADMCK_DIV = 4
4715 12:11:36.322844 DQ_TRACK_CA_EN = 0
4716 12:11:36.326539 CA_PICK = 933
4717 12:11:36.329463 CA_MCKIO = 933
4718 12:11:36.329534 MCKIO_SEMI = 0
4719 12:11:36.333626 PLL_FREQ = 3732
4720 12:11:36.336123 DQ_UI_PI_RATIO = 32
4721 12:11:36.339853 CA_UI_PI_RATIO = 0
4722 12:11:36.343256 ===================================
4723 12:11:36.346468 ===================================
4724 12:11:36.349844 memory_type:LPDDR4
4725 12:11:36.349911 GP_NUM : 10
4726 12:11:36.352864 SRAM_EN : 1
4727 12:11:36.355906 MD32_EN : 0
4728 12:11:36.359053 ===================================
4729 12:11:36.359130 [ANA_INIT] >>>>>>>>>>>>>>
4730 12:11:36.362539 <<<<<< [CONFIGURE PHASE]: ANA_TX
4731 12:11:36.366228 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4732 12:11:36.369690 ===================================
4733 12:11:36.372652 data_rate = 1866,PCW = 0X8f00
4734 12:11:36.375581 ===================================
4735 12:11:36.379470 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4736 12:11:36.386671 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4737 12:11:36.389456 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4738 12:11:36.395890 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4739 12:11:36.398906 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4740 12:11:36.402469 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4741 12:11:36.402552 [ANA_INIT] flow start
4742 12:11:36.405416 [ANA_INIT] PLL >>>>>>>>
4743 12:11:36.408950 [ANA_INIT] PLL <<<<<<<<
4744 12:11:36.412264 [ANA_INIT] MIDPI >>>>>>>>
4745 12:11:36.412346 [ANA_INIT] MIDPI <<<<<<<<
4746 12:11:36.416013 [ANA_INIT] DLL >>>>>>>>
4747 12:11:36.416095 [ANA_INIT] flow end
4748 12:11:36.422248 ============ LP4 DIFF to SE enter ============
4749 12:11:36.425767 ============ LP4 DIFF to SE exit ============
4750 12:11:36.429061 [ANA_INIT] <<<<<<<<<<<<<
4751 12:11:36.431793 [Flow] Enable top DCM control >>>>>
4752 12:11:36.435662 [Flow] Enable top DCM control <<<<<
4753 12:11:36.438595 Enable DLL master slave shuffle
4754 12:11:36.441985 ==============================================================
4755 12:11:36.445718 Gating Mode config
4756 12:11:36.449601 ==============================================================
4757 12:11:36.452683 Config description:
4758 12:11:36.462245 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4759 12:11:36.468619 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4760 12:11:36.471851 SELPH_MODE 0: By rank 1: By Phase
4761 12:11:36.478721 ==============================================================
4762 12:11:36.481866 GAT_TRACK_EN = 1
4763 12:11:36.486574 RX_GATING_MODE = 2
4764 12:11:36.488357 RX_GATING_TRACK_MODE = 2
4765 12:11:36.491622 SELPH_MODE = 1
4766 12:11:36.494819 PICG_EARLY_EN = 1
4767 12:11:36.498634 VALID_LAT_VALUE = 1
4768 12:11:36.501502 ==============================================================
4769 12:11:36.504764 Enter into Gating configuration >>>>
4770 12:11:36.508210 Exit from Gating configuration <<<<
4771 12:11:36.511594 Enter into DVFS_PRE_config >>>>>
4772 12:11:36.524761 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4773 12:11:36.524844 Exit from DVFS_PRE_config <<<<<
4774 12:11:36.527740 Enter into PICG configuration >>>>
4775 12:11:36.531305 Exit from PICG configuration <<<<
4776 12:11:36.535132 [RX_INPUT] configuration >>>>>
4777 12:11:36.538761 [RX_INPUT] configuration <<<<<
4778 12:11:36.544268 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4779 12:11:36.547409 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4780 12:11:36.554475 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4781 12:11:36.561132 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4782 12:11:36.567908 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4783 12:11:36.574530 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4784 12:11:36.577124 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4785 12:11:36.580533 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4786 12:11:36.585071 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4787 12:11:36.590729 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4788 12:11:36.594137 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4789 12:11:36.596983 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4790 12:11:36.600354 ===================================
4791 12:11:36.604033 LPDDR4 DRAM CONFIGURATION
4792 12:11:36.606865 ===================================
4793 12:11:36.610783 EX_ROW_EN[0] = 0x0
4794 12:11:36.610865 EX_ROW_EN[1] = 0x0
4795 12:11:36.613866 LP4Y_EN = 0x0
4796 12:11:36.613965 WORK_FSP = 0x0
4797 12:11:36.617056 WL = 0x3
4798 12:11:36.617138 RL = 0x3
4799 12:11:36.620301 BL = 0x2
4800 12:11:36.620383 RPST = 0x0
4801 12:11:36.624014 RD_PRE = 0x0
4802 12:11:36.624096 WR_PRE = 0x1
4803 12:11:36.627154 WR_PST = 0x0
4804 12:11:36.627236 DBI_WR = 0x0
4805 12:11:36.630097 DBI_RD = 0x0
4806 12:11:36.630179 OTF = 0x1
4807 12:11:36.634208 ===================================
4808 12:11:36.640188 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4809 12:11:36.643827 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4810 12:11:36.646790 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4811 12:11:36.650034 ===================================
4812 12:11:36.653933 LPDDR4 DRAM CONFIGURATION
4813 12:11:36.656863 ===================================
4814 12:11:36.660085 EX_ROW_EN[0] = 0x10
4815 12:11:36.660167 EX_ROW_EN[1] = 0x0
4816 12:11:36.663694 LP4Y_EN = 0x0
4817 12:11:36.663775 WORK_FSP = 0x0
4818 12:11:36.666787 WL = 0x3
4819 12:11:36.666869 RL = 0x3
4820 12:11:36.669726 BL = 0x2
4821 12:11:36.669808 RPST = 0x0
4822 12:11:36.673304 RD_PRE = 0x0
4823 12:11:36.673386 WR_PRE = 0x1
4824 12:11:36.676689 WR_PST = 0x0
4825 12:11:36.676811 DBI_WR = 0x0
4826 12:11:36.680059 DBI_RD = 0x0
4827 12:11:36.680140 OTF = 0x1
4828 12:11:36.683024 ===================================
4829 12:11:36.689585 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4830 12:11:36.694541 nWR fixed to 30
4831 12:11:36.698144 [ModeRegInit_LP4] CH0 RK0
4832 12:11:36.698226 [ModeRegInit_LP4] CH0 RK1
4833 12:11:36.701666 [ModeRegInit_LP4] CH1 RK0
4834 12:11:36.704674 [ModeRegInit_LP4] CH1 RK1
4835 12:11:36.704771 match AC timing 8
4836 12:11:36.711244 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4837 12:11:36.714661 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4838 12:11:36.717705 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4839 12:11:36.724477 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4840 12:11:36.727819 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4841 12:11:36.727901 ==
4842 12:11:36.731365 Dram Type= 6, Freq= 0, CH_0, rank 0
4843 12:11:36.734265 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4844 12:11:36.734348 ==
4845 12:11:36.741192 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4846 12:11:36.748076 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4847 12:11:36.751434 [CA 0] Center 38 (8~69) winsize 62
4848 12:11:36.754536 [CA 1] Center 38 (8~69) winsize 62
4849 12:11:36.757771 [CA 2] Center 36 (5~67) winsize 63
4850 12:11:36.760991 [CA 3] Center 35 (5~66) winsize 62
4851 12:11:36.764026 [CA 4] Center 34 (4~65) winsize 62
4852 12:11:36.767268 [CA 5] Center 34 (4~64) winsize 61
4853 12:11:36.767350
4854 12:11:36.771336 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4855 12:11:36.771419
4856 12:11:36.774669 [CATrainingPosCal] consider 1 rank data
4857 12:11:36.777256 u2DelayCellTimex100 = 270/100 ps
4858 12:11:36.780893 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4859 12:11:36.783941 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4860 12:11:36.787865 CA2 delay=36 (5~67),Diff = 2 PI (12 cell)
4861 12:11:36.790439 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4862 12:11:36.794176 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4863 12:11:36.800334 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4864 12:11:36.800416
4865 12:11:36.803898 CA PerBit enable=1, Macro0, CA PI delay=34
4866 12:11:36.803980
4867 12:11:36.808939 [CBTSetCACLKResult] CA Dly = 34
4868 12:11:36.809033 CS Dly: 7 (0~38)
4869 12:11:36.809099 ==
4870 12:11:36.811388 Dram Type= 6, Freq= 0, CH_0, rank 1
4871 12:11:36.817189 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4872 12:11:36.817271 ==
4873 12:11:36.820338 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4874 12:11:36.826982 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4875 12:11:36.830020 [CA 0] Center 38 (8~69) winsize 62
4876 12:11:36.833246 [CA 1] Center 38 (8~69) winsize 62
4877 12:11:36.836792 [CA 2] Center 35 (5~66) winsize 62
4878 12:11:36.840277 [CA 3] Center 35 (5~66) winsize 62
4879 12:11:36.843886 [CA 4] Center 34 (4~65) winsize 62
4880 12:11:36.846588 [CA 5] Center 34 (4~65) winsize 62
4881 12:11:36.846670
4882 12:11:36.850300 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4883 12:11:36.850382
4884 12:11:36.853999 [CATrainingPosCal] consider 2 rank data
4885 12:11:36.857214 u2DelayCellTimex100 = 270/100 ps
4886 12:11:36.860391 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4887 12:11:36.863886 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4888 12:11:36.867394 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
4889 12:11:36.872941 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4890 12:11:36.876742 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4891 12:11:36.879718 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4892 12:11:36.879793
4893 12:11:36.883088 CA PerBit enable=1, Macro0, CA PI delay=34
4894 12:11:36.883160
4895 12:11:36.886798 [CBTSetCACLKResult] CA Dly = 34
4896 12:11:36.886870 CS Dly: 7 (0~39)
4897 12:11:36.886931
4898 12:11:36.890469 ----->DramcWriteLeveling(PI) begin...
4899 12:11:36.890543 ==
4900 12:11:36.893459 Dram Type= 6, Freq= 0, CH_0, rank 0
4901 12:11:36.900464 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4902 12:11:36.900540 ==
4903 12:11:36.903681 Write leveling (Byte 0): 30 => 30
4904 12:11:36.906876 Write leveling (Byte 1): 28 => 28
4905 12:11:36.906976 DramcWriteLeveling(PI) end<-----
4906 12:11:36.907065
4907 12:11:36.909860 ==
4908 12:11:36.913160 Dram Type= 6, Freq= 0, CH_0, rank 0
4909 12:11:36.916503 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4910 12:11:36.916581 ==
4911 12:11:36.920617 [Gating] SW mode calibration
4912 12:11:36.927144 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4913 12:11:36.929807 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4914 12:11:36.936410 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4915 12:11:36.939696 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4916 12:11:36.943110 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4917 12:11:36.949527 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4918 12:11:36.953992 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4919 12:11:36.955973 0 10 20 | B1->B0 | 3232 2f2f | 0 0 | (0 1) (0 1)
4920 12:11:36.962538 0 10 24 | B1->B0 | 2e2e 2525 | 0 0 | (0 0) (0 0)
4921 12:11:36.966461 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4922 12:11:36.969813 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4923 12:11:36.976671 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4924 12:11:36.979289 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4925 12:11:36.982844 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4926 12:11:36.989018 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4927 12:11:36.992581 0 11 20 | B1->B0 | 2626 3131 | 0 0 | (0 0) (0 0)
4928 12:11:36.996030 0 11 24 | B1->B0 | 4040 4545 | 0 0 | (0 0) (0 0)
4929 12:11:37.002648 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4930 12:11:37.005656 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4931 12:11:37.009563 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4932 12:11:37.015896 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4933 12:11:37.019572 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4934 12:11:37.022923 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4935 12:11:37.029046 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4936 12:11:37.032114 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4937 12:11:37.035463 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4938 12:11:37.042275 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4939 12:11:37.046412 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4940 12:11:37.050538 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 12:11:37.057692 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4942 12:11:37.059018 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 12:11:37.062157 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 12:11:37.069288 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 12:11:37.071671 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4946 12:11:37.076058 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4947 12:11:37.081575 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4948 12:11:37.085030 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4949 12:11:37.088624 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4950 12:11:37.095155 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4951 12:11:37.098353 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4952 12:11:37.101671 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4953 12:11:37.104524 Total UI for P1: 0, mck2ui 16
4954 12:11:37.107942 best dqsien dly found for B0: ( 0, 14, 22)
4955 12:11:37.114842 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4956 12:11:37.114915 Total UI for P1: 0, mck2ui 16
4957 12:11:37.121786 best dqsien dly found for B1: ( 0, 14, 22)
4958 12:11:37.125206 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
4959 12:11:37.127925 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
4960 12:11:37.127995
4961 12:11:37.131900 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
4962 12:11:37.134504 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
4963 12:11:37.137942 [Gating] SW calibration Done
4964 12:11:37.138012 ==
4965 12:11:37.141107 Dram Type= 6, Freq= 0, CH_0, rank 0
4966 12:11:37.144220 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4967 12:11:37.144290 ==
4968 12:11:37.147894 RX Vref Scan: 0
4969 12:11:37.147973
4970 12:11:37.148035 RX Vref 0 -> 0, step: 1
4971 12:11:37.148093
4972 12:11:37.151598 RX Delay -80 -> 252, step: 8
4973 12:11:37.157891 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4974 12:11:37.161063 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4975 12:11:37.168172 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4976 12:11:37.168851 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
4977 12:11:37.171542 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
4978 12:11:37.175460 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4979 12:11:37.178194 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
4980 12:11:37.183975 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4981 12:11:37.187733 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
4982 12:11:37.190870 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4983 12:11:37.194209 iDelay=208, Bit 10, Center 79 (-16 ~ 175) 192
4984 12:11:37.200916 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4985 12:11:37.205251 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
4986 12:11:37.207147 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
4987 12:11:37.211053 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
4988 12:11:37.213795 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
4989 12:11:37.213878 ==
4990 12:11:37.216962 Dram Type= 6, Freq= 0, CH_0, rank 0
4991 12:11:37.224412 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4992 12:11:37.224496 ==
4993 12:11:37.224561 DQS Delay:
4994 12:11:37.227300 DQS0 = 0, DQS1 = 0
4995 12:11:37.227382 DQM Delay:
4996 12:11:37.227446 DQM0 = 95, DQM1 = 85
4997 12:11:37.230371 DQ Delay:
4998 12:11:37.233284 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
4999 12:11:37.236824 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5000 12:11:37.241144 DQ8 =75, DQ9 =71, DQ10 =79, DQ11 =79
5001 12:11:37.243616 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5002 12:11:37.243698
5003 12:11:37.243762
5004 12:11:37.243821 ==
5005 12:11:37.246624 Dram Type= 6, Freq= 0, CH_0, rank 0
5006 12:11:37.250901 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5007 12:11:37.250983 ==
5008 12:11:37.251048
5009 12:11:37.251108
5010 12:11:37.253265 TX Vref Scan disable
5011 12:11:37.253347 == TX Byte 0 ==
5012 12:11:37.260485 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5013 12:11:37.263475 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5014 12:11:37.266675 == TX Byte 1 ==
5015 12:11:37.270354 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5016 12:11:37.273570 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5017 12:11:37.273652 ==
5018 12:11:37.276952 Dram Type= 6, Freq= 0, CH_0, rank 0
5019 12:11:37.279782 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5020 12:11:37.283619 ==
5021 12:11:37.283701
5022 12:11:37.283766
5023 12:11:37.283827 TX Vref Scan disable
5024 12:11:37.286552 == TX Byte 0 ==
5025 12:11:37.290154 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5026 12:11:37.297333 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5027 12:11:37.297416 == TX Byte 1 ==
5028 12:11:37.299971 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5029 12:11:37.307035 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5030 12:11:37.307117
5031 12:11:37.307181 [DATLAT]
5032 12:11:37.307268 Freq=933, CH0 RK0
5033 12:11:37.307350
5034 12:11:37.309712 DATLAT Default: 0xd
5035 12:11:37.309794 0, 0xFFFF, sum = 0
5036 12:11:37.312943 1, 0xFFFF, sum = 0
5037 12:11:37.316151 2, 0xFFFF, sum = 0
5038 12:11:37.316233 3, 0xFFFF, sum = 0
5039 12:11:37.319668 4, 0xFFFF, sum = 0
5040 12:11:37.319751 5, 0xFFFF, sum = 0
5041 12:11:37.322885 6, 0xFFFF, sum = 0
5042 12:11:37.322968 7, 0xFFFF, sum = 0
5043 12:11:37.326333 8, 0xFFFF, sum = 0
5044 12:11:37.326417 9, 0xFFFF, sum = 0
5045 12:11:37.330357 10, 0x0, sum = 1
5046 12:11:37.330439 11, 0x0, sum = 2
5047 12:11:37.333515 12, 0x0, sum = 3
5048 12:11:37.333598 13, 0x0, sum = 4
5049 12:11:37.333665 best_step = 11
5050 12:11:37.333725
5051 12:11:37.336619 ==
5052 12:11:37.339513 Dram Type= 6, Freq= 0, CH_0, rank 0
5053 12:11:37.342710 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5054 12:11:37.342793 ==
5055 12:11:37.342858 RX Vref Scan: 1
5056 12:11:37.342918
5057 12:11:37.346862 RX Vref 0 -> 0, step: 1
5058 12:11:37.346943
5059 12:11:37.349803 RX Delay -69 -> 252, step: 4
5060 12:11:37.349884
5061 12:11:37.352683 Set Vref, RX VrefLevel [Byte0]: 46
5062 12:11:37.356487 [Byte1]: 47
5063 12:11:37.356569
5064 12:11:37.359770 Final RX Vref Byte 0 = 46 to rank0
5065 12:11:37.362928 Final RX Vref Byte 1 = 47 to rank0
5066 12:11:37.366188 Final RX Vref Byte 0 = 46 to rank1
5067 12:11:37.369134 Final RX Vref Byte 1 = 47 to rank1==
5068 12:11:37.373110 Dram Type= 6, Freq= 0, CH_0, rank 0
5069 12:11:37.376199 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5070 12:11:37.379367 ==
5071 12:11:37.379449 DQS Delay:
5072 12:11:37.379514 DQS0 = 0, DQS1 = 0
5073 12:11:37.382723 DQM Delay:
5074 12:11:37.382805 DQM0 = 97, DQM1 = 86
5075 12:11:37.386520 DQ Delay:
5076 12:11:37.388973 DQ0 =94, DQ1 =100, DQ2 =96, DQ3 =94
5077 12:11:37.392450 DQ4 =100, DQ5 =90, DQ6 =104, DQ7 =104
5078 12:11:37.395969 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =80
5079 12:11:37.399682 DQ12 =94, DQ13 =94, DQ14 =96, DQ15 =96
5080 12:11:37.399765
5081 12:11:37.399829
5082 12:11:37.406178 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5083 12:11:37.409836 CH0 RK0: MR19=505, MR18=1E1E
5084 12:11:37.416201 CH0_RK0: MR19=0x505, MR18=0x1E1E, DQSOSC=412, MR23=63, INC=63, DEC=42
5085 12:11:37.416283
5086 12:11:37.419112 ----->DramcWriteLeveling(PI) begin...
5087 12:11:37.419195 ==
5088 12:11:37.422426 Dram Type= 6, Freq= 0, CH_0, rank 1
5089 12:11:37.425758 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5090 12:11:37.425841 ==
5091 12:11:37.429008 Write leveling (Byte 0): 31 => 31
5092 12:11:37.432500 Write leveling (Byte 1): 28 => 28
5093 12:11:37.435827 DramcWriteLeveling(PI) end<-----
5094 12:11:37.435909
5095 12:11:37.435974 ==
5096 12:11:37.439242 Dram Type= 6, Freq= 0, CH_0, rank 1
5097 12:11:37.442097 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5098 12:11:37.442180 ==
5099 12:11:37.445984 [Gating] SW mode calibration
5100 12:11:37.452054 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5101 12:11:37.459314 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5102 12:11:37.462881 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 12:11:37.468875 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 12:11:37.472930 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 12:11:37.475841 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 12:11:37.482215 0 10 16 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5107 12:11:37.486033 0 10 20 | B1->B0 | 3131 2d2d | 1 1 | (1 0) (1 1)
5108 12:11:37.488373 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 12:11:37.495595 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 12:11:37.499210 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 12:11:37.501987 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 12:11:37.509109 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 12:11:37.511776 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 12:11:37.515405 0 11 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5115 12:11:37.518163 0 11 20 | B1->B0 | 2f2f 3535 | 0 1 | (0 0) (0 0)
5116 12:11:37.525505 0 11 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5117 12:11:37.528222 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 12:11:37.531985 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 12:11:37.538121 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 12:11:37.542088 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 12:11:37.545580 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 12:11:37.551516 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 12:11:37.555005 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5124 12:11:37.558356 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5125 12:11:37.564550 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 12:11:37.567806 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 12:11:37.571161 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 12:11:37.577908 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 12:11:37.581088 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 12:11:37.584576 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 12:11:37.591930 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 12:11:37.594475 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 12:11:37.597710 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 12:11:37.605724 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 12:11:37.607820 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 12:11:37.611159 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 12:11:37.618410 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 12:11:37.621170 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5139 12:11:37.624777 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5140 12:11:37.631930 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5141 12:11:37.634657 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5142 12:11:37.637907 Total UI for P1: 0, mck2ui 16
5143 12:11:37.641157 best dqsien dly found for B0: ( 0, 14, 22)
5144 12:11:37.644322 Total UI for P1: 0, mck2ui 16
5145 12:11:37.648001 best dqsien dly found for B1: ( 0, 14, 20)
5146 12:11:37.651009 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5147 12:11:37.654276 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5148 12:11:37.654358
5149 12:11:37.657467 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5150 12:11:37.661031 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5151 12:11:37.664393 [Gating] SW calibration Done
5152 12:11:37.664475 ==
5153 12:11:37.667735 Dram Type= 6, Freq= 0, CH_0, rank 1
5154 12:11:37.674506 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5155 12:11:37.674589 ==
5156 12:11:37.674654 RX Vref Scan: 0
5157 12:11:37.674715
5158 12:11:37.677751 RX Vref 0 -> 0, step: 1
5159 12:11:37.677833
5160 12:11:37.680494 RX Delay -80 -> 252, step: 8
5161 12:11:37.684391 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5162 12:11:37.687179 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5163 12:11:37.690731 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5164 12:11:37.694067 iDelay=208, Bit 3, Center 91 (0 ~ 183) 184
5165 12:11:37.697707 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5166 12:11:37.703995 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5167 12:11:37.707337 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5168 12:11:37.710281 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5169 12:11:37.713685 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5170 12:11:37.717714 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5171 12:11:37.724553 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5172 12:11:37.727199 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5173 12:11:37.730130 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5174 12:11:37.733838 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5175 12:11:37.737512 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5176 12:11:37.740936 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5177 12:11:37.743390 ==
5178 12:11:37.746985 Dram Type= 6, Freq= 0, CH_0, rank 1
5179 12:11:37.750372 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5180 12:11:37.750446 ==
5181 12:11:37.750515 DQS Delay:
5182 12:11:37.753393 DQS0 = 0, DQS1 = 0
5183 12:11:37.753465 DQM Delay:
5184 12:11:37.757613 DQM0 = 96, DQM1 = 87
5185 12:11:37.757697 DQ Delay:
5186 12:11:37.761083 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =91
5187 12:11:37.763102 DQ4 =99, DQ5 =91, DQ6 =103, DQ7 =107
5188 12:11:37.767044 DQ8 =75, DQ9 =71, DQ10 =95, DQ11 =75
5189 12:11:37.770817 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5190 12:11:37.770888
5191 12:11:37.770957
5192 12:11:37.771015 ==
5193 12:11:37.773906 Dram Type= 6, Freq= 0, CH_0, rank 1
5194 12:11:37.777153 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5195 12:11:37.777225 ==
5196 12:11:37.777285
5197 12:11:37.777342
5198 12:11:37.780165 TX Vref Scan disable
5199 12:11:37.783572 == TX Byte 0 ==
5200 12:11:37.786799 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5201 12:11:37.790210 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5202 12:11:37.793187 == TX Byte 1 ==
5203 12:11:37.796328 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5204 12:11:37.800206 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5205 12:11:37.800281 ==
5206 12:11:37.803171 Dram Type= 6, Freq= 0, CH_0, rank 1
5207 12:11:37.810138 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5208 12:11:37.810236 ==
5209 12:11:37.810326
5210 12:11:37.810419
5211 12:11:37.810504 TX Vref Scan disable
5212 12:11:37.813716 == TX Byte 0 ==
5213 12:11:37.817237 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5214 12:11:37.820302 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5215 12:11:37.823517 == TX Byte 1 ==
5216 12:11:37.827451 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5217 12:11:37.833599 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5218 12:11:37.833676
5219 12:11:37.833750 [DATLAT]
5220 12:11:37.833810 Freq=933, CH0 RK1
5221 12:11:37.833868
5222 12:11:37.838672 DATLAT Default: 0xb
5223 12:11:37.838739 0, 0xFFFF, sum = 0
5224 12:11:37.840951 1, 0xFFFF, sum = 0
5225 12:11:37.841033 2, 0xFFFF, sum = 0
5226 12:11:37.843352 3, 0xFFFF, sum = 0
5227 12:11:37.847240 4, 0xFFFF, sum = 0
5228 12:11:37.847314 5, 0xFFFF, sum = 0
5229 12:11:37.850256 6, 0xFFFF, sum = 0
5230 12:11:37.850340 7, 0xFFFF, sum = 0
5231 12:11:37.853613 8, 0xFFFF, sum = 0
5232 12:11:37.853696 9, 0xFFFF, sum = 0
5233 12:11:37.857311 10, 0x0, sum = 1
5234 12:11:37.857394 11, 0x0, sum = 2
5235 12:11:37.860614 12, 0x0, sum = 3
5236 12:11:37.860697 13, 0x0, sum = 4
5237 12:11:37.860803 best_step = 11
5238 12:11:37.860865
5239 12:11:37.863679 ==
5240 12:11:37.866438 Dram Type= 6, Freq= 0, CH_0, rank 1
5241 12:11:37.870532 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5242 12:11:37.870615 ==
5243 12:11:37.870680 RX Vref Scan: 0
5244 12:11:37.870740
5245 12:11:37.873455 RX Vref 0 -> 0, step: 1
5246 12:11:37.873536
5247 12:11:37.876981 RX Delay -69 -> 252, step: 4
5248 12:11:37.883845 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5249 12:11:37.887072 iDelay=199, Bit 1, Center 100 (7 ~ 194) 188
5250 12:11:37.889614 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5251 12:11:37.893802 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5252 12:11:37.897092 iDelay=199, Bit 4, Center 104 (15 ~ 194) 180
5253 12:11:37.899685 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5254 12:11:37.907135 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5255 12:11:37.909702 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5256 12:11:37.913449 iDelay=199, Bit 8, Center 74 (-13 ~ 162) 176
5257 12:11:37.916983 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5258 12:11:37.920013 iDelay=199, Bit 10, Center 90 (-1 ~ 182) 184
5259 12:11:37.926105 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5260 12:11:37.929963 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5261 12:11:37.933081 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5262 12:11:37.936698 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5263 12:11:37.939844 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5264 12:11:37.939927 ==
5265 12:11:37.943105 Dram Type= 6, Freq= 0, CH_0, rank 1
5266 12:11:37.950877 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5267 12:11:37.950959 ==
5268 12:11:37.951024 DQS Delay:
5269 12:11:37.954607 DQS0 = 0, DQS1 = 0
5270 12:11:37.954689 DQM Delay:
5271 12:11:37.954754 DQM0 = 97, DQM1 = 86
5272 12:11:37.956865 DQ Delay:
5273 12:11:37.959250 DQ0 =92, DQ1 =100, DQ2 =94, DQ3 =92
5274 12:11:37.962711 DQ4 =104, DQ5 =88, DQ6 =104, DQ7 =106
5275 12:11:37.965826 DQ8 =74, DQ9 =72, DQ10 =90, DQ11 =78
5276 12:11:37.969187 DQ12 =96, DQ13 =90, DQ14 =96, DQ15 =94
5277 12:11:37.969269
5278 12:11:37.969334
5279 12:11:37.975872 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a2a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5280 12:11:37.980546 CH0 RK1: MR19=505, MR18=2A2A
5281 12:11:37.986030 CH0_RK1: MR19=0x505, MR18=0x2A2A, DQSOSC=408, MR23=63, INC=65, DEC=43
5282 12:11:37.989782 [RxdqsGatingPostProcess] freq 933
5283 12:11:37.992470 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5284 12:11:37.995741 Pre-setting of DQS Precalculation
5285 12:11:38.003102 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5286 12:11:38.003185 ==
5287 12:11:38.006748 Dram Type= 6, Freq= 0, CH_1, rank 0
5288 12:11:38.009738 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5289 12:11:38.009821 ==
5290 12:11:38.015777 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5291 12:11:38.022268 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5292 12:11:38.026255 [CA 0] Center 37 (7~68) winsize 62
5293 12:11:38.029304 [CA 1] Center 37 (6~68) winsize 63
5294 12:11:38.032546 [CA 2] Center 34 (4~65) winsize 62
5295 12:11:38.036021 [CA 3] Center 34 (4~65) winsize 62
5296 12:11:38.038989 [CA 4] Center 33 (3~64) winsize 62
5297 12:11:38.042735 [CA 5] Center 33 (3~64) winsize 62
5298 12:11:38.042816
5299 12:11:38.045633 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5300 12:11:38.045714
5301 12:11:38.049041 [CATrainingPosCal] consider 1 rank data
5302 12:11:38.052304 u2DelayCellTimex100 = 270/100 ps
5303 12:11:38.055626 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5304 12:11:38.058763 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5305 12:11:38.062355 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5306 12:11:38.065546 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5307 12:11:38.069100 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5308 12:11:38.072351 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5309 12:11:38.072432
5310 12:11:38.078736 CA PerBit enable=1, Macro0, CA PI delay=33
5311 12:11:38.078818
5312 12:11:38.078883 [CBTSetCACLKResult] CA Dly = 33
5313 12:11:38.082103 CS Dly: 5 (0~36)
5314 12:11:38.082190 ==
5315 12:11:38.085156 Dram Type= 6, Freq= 0, CH_1, rank 1
5316 12:11:38.088703 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5317 12:11:38.088820 ==
5318 12:11:38.095017 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5319 12:11:38.102429 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5320 12:11:38.105303 [CA 0] Center 37 (6~68) winsize 63
5321 12:11:38.108764 [CA 1] Center 37 (6~68) winsize 63
5322 12:11:38.111815 [CA 2] Center 34 (4~65) winsize 62
5323 12:11:38.114654 [CA 3] Center 33 (3~64) winsize 62
5324 12:11:38.118439 [CA 4] Center 33 (2~64) winsize 63
5325 12:11:38.121975 [CA 5] Center 32 (2~63) winsize 62
5326 12:11:38.122049
5327 12:11:38.124745 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5328 12:11:38.124817
5329 12:11:38.128320 [CATrainingPosCal] consider 2 rank data
5330 12:11:38.132023 u2DelayCellTimex100 = 270/100 ps
5331 12:11:38.134655 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5332 12:11:38.138548 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5333 12:11:38.141725 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5334 12:11:38.145167 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5335 12:11:38.147796 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5336 12:11:38.154576 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5337 12:11:38.154657
5338 12:11:38.158315 CA PerBit enable=1, Macro0, CA PI delay=33
5339 12:11:38.158397
5340 12:11:38.161549 [CBTSetCACLKResult] CA Dly = 33
5341 12:11:38.161631 CS Dly: 5 (0~37)
5342 12:11:38.161695
5343 12:11:38.164703 ----->DramcWriteLeveling(PI) begin...
5344 12:11:38.164825 ==
5345 12:11:38.168367 Dram Type= 6, Freq= 0, CH_1, rank 0
5346 12:11:38.171865 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5347 12:11:38.174725 ==
5348 12:11:38.174806 Write leveling (Byte 0): 23 => 23
5349 12:11:38.178373 Write leveling (Byte 1): 26 => 26
5350 12:11:38.181833 DramcWriteLeveling(PI) end<-----
5351 12:11:38.181915
5352 12:11:38.181978 ==
5353 12:11:38.184650 Dram Type= 6, Freq= 0, CH_1, rank 0
5354 12:11:38.191368 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5355 12:11:38.191449 ==
5356 12:11:38.195221 [Gating] SW mode calibration
5357 12:11:38.201705 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5358 12:11:38.204444 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5359 12:11:38.212071 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 12:11:38.214584 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 12:11:38.217869 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 12:11:38.224271 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 12:11:38.227805 0 10 16 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5364 12:11:38.231263 0 10 20 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
5365 12:11:38.238259 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 12:11:38.241817 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 12:11:38.244421 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 12:11:38.251435 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 12:11:38.254639 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 12:11:38.257696 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 12:11:38.260649 0 11 16 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5372 12:11:38.267600 0 11 20 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
5373 12:11:38.270577 0 11 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5374 12:11:38.274459 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 12:11:38.282401 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 12:11:38.283977 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 12:11:38.288498 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 12:11:38.294447 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 12:11:38.297478 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5380 12:11:38.300933 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5381 12:11:38.307722 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 12:11:38.310604 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 12:11:38.313982 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 12:11:38.320483 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 12:11:38.324195 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 12:11:38.327785 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 12:11:38.333906 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 12:11:38.337966 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 12:11:38.340381 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 12:11:38.347337 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 12:11:38.350906 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 12:11:38.353994 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 12:11:38.361269 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 12:11:38.364599 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 12:11:38.367220 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5396 12:11:38.373629 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5397 12:11:38.376921 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 12:11:38.379965 Total UI for P1: 0, mck2ui 16
5399 12:11:38.383268 best dqsien dly found for B0: ( 0, 14, 18)
5400 12:11:38.387152 Total UI for P1: 0, mck2ui 16
5401 12:11:38.389879 best dqsien dly found for B1: ( 0, 14, 18)
5402 12:11:38.393980 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5403 12:11:38.396895 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5404 12:11:38.396973
5405 12:11:38.399921 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5406 12:11:38.404053 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5407 12:11:38.407056 [Gating] SW calibration Done
5408 12:11:38.407127 ==
5409 12:11:38.410103 Dram Type= 6, Freq= 0, CH_1, rank 0
5410 12:11:38.413892 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5411 12:11:38.416877 ==
5412 12:11:38.416953 RX Vref Scan: 0
5413 12:11:38.417015
5414 12:11:38.420289 RX Vref 0 -> 0, step: 1
5415 12:11:38.420382
5416 12:11:38.420486 RX Delay -80 -> 252, step: 8
5417 12:11:38.427565 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5418 12:11:38.430219 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5419 12:11:38.433857 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5420 12:11:38.437569 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5421 12:11:38.440635 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5422 12:11:38.446536 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5423 12:11:38.449908 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5424 12:11:38.453059 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5425 12:11:38.456862 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5426 12:11:38.460351 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5427 12:11:38.466682 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5428 12:11:38.469451 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5429 12:11:38.472823 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5430 12:11:38.476148 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5431 12:11:38.479506 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5432 12:11:38.482945 iDelay=208, Bit 15, Center 95 (-8 ~ 199) 208
5433 12:11:38.486279 ==
5434 12:11:38.489731 Dram Type= 6, Freq= 0, CH_1, rank 0
5435 12:11:38.492966 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5436 12:11:38.493040 ==
5437 12:11:38.493108 DQS Delay:
5438 12:11:38.497271 DQS0 = 0, DQS1 = 0
5439 12:11:38.497347 DQM Delay:
5440 12:11:38.500309 DQM0 = 94, DQM1 = 88
5441 12:11:38.500380 DQ Delay:
5442 12:11:38.503305 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =91
5443 12:11:38.506235 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =95
5444 12:11:38.509251 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5445 12:11:38.512763 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =95
5446 12:11:38.512846
5447 12:11:38.512911
5448 12:11:38.512972 ==
5449 12:11:38.516173 Dram Type= 6, Freq= 0, CH_1, rank 0
5450 12:11:38.519331 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5451 12:11:38.519414 ==
5452 12:11:38.519479
5453 12:11:38.522716
5454 12:11:38.522797 TX Vref Scan disable
5455 12:11:38.526470 == TX Byte 0 ==
5456 12:11:38.529548 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5457 12:11:38.532445 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5458 12:11:38.536048 == TX Byte 1 ==
5459 12:11:38.539182 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5460 12:11:38.542416 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5461 12:11:38.542498 ==
5462 12:11:38.546034 Dram Type= 6, Freq= 0, CH_1, rank 0
5463 12:11:38.552553 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5464 12:11:38.552636 ==
5465 12:11:38.552701
5466 12:11:38.552804
5467 12:11:38.552862 TX Vref Scan disable
5468 12:11:38.556618 == TX Byte 0 ==
5469 12:11:38.559901 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5470 12:11:38.567414 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5471 12:11:38.567496 == TX Byte 1 ==
5472 12:11:38.570316 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5473 12:11:38.576410 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5474 12:11:38.576508
5475 12:11:38.576597 [DATLAT]
5476 12:11:38.576689 Freq=933, CH1 RK0
5477 12:11:38.576798
5478 12:11:38.579972 DATLAT Default: 0xd
5479 12:11:38.580040 0, 0xFFFF, sum = 0
5480 12:11:38.583212 1, 0xFFFF, sum = 0
5481 12:11:38.583281 2, 0xFFFF, sum = 0
5482 12:11:38.586857 3, 0xFFFF, sum = 0
5483 12:11:38.590069 4, 0xFFFF, sum = 0
5484 12:11:38.590142 5, 0xFFFF, sum = 0
5485 12:11:38.593413 6, 0xFFFF, sum = 0
5486 12:11:38.593482 7, 0xFFFF, sum = 0
5487 12:11:38.597101 8, 0xFFFF, sum = 0
5488 12:11:38.597173 9, 0xFFFF, sum = 0
5489 12:11:38.600570 10, 0x0, sum = 1
5490 12:11:38.600638 11, 0x0, sum = 2
5491 12:11:38.602883 12, 0x0, sum = 3
5492 12:11:38.602953 13, 0x0, sum = 4
5493 12:11:38.603013 best_step = 11
5494 12:11:38.603076
5495 12:11:38.606380 ==
5496 12:11:38.610858 Dram Type= 6, Freq= 0, CH_1, rank 0
5497 12:11:38.614268 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5498 12:11:38.614350 ==
5499 12:11:38.614415 RX Vref Scan: 1
5500 12:11:38.614476
5501 12:11:38.616679 RX Vref 0 -> 0, step: 1
5502 12:11:38.616801
5503 12:11:38.619487 RX Delay -61 -> 252, step: 4
5504 12:11:38.619569
5505 12:11:38.622988 Set Vref, RX VrefLevel [Byte0]: 53
5506 12:11:38.626955 [Byte1]: 50
5507 12:11:38.627036
5508 12:11:38.629933 Final RX Vref Byte 0 = 53 to rank0
5509 12:11:38.633071 Final RX Vref Byte 1 = 50 to rank0
5510 12:11:38.636986 Final RX Vref Byte 0 = 53 to rank1
5511 12:11:38.640442 Final RX Vref Byte 1 = 50 to rank1==
5512 12:11:38.642986 Dram Type= 6, Freq= 0, CH_1, rank 0
5513 12:11:38.646100 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5514 12:11:38.649710 ==
5515 12:11:38.649792 DQS Delay:
5516 12:11:38.649856 DQS0 = 0, DQS1 = 0
5517 12:11:38.653278 DQM Delay:
5518 12:11:38.653360 DQM0 = 94, DQM1 = 88
5519 12:11:38.655985 DQ Delay:
5520 12:11:38.656093 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =92
5521 12:11:38.659724 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =92
5522 12:11:38.662850 DQ8 =70, DQ9 =80, DQ10 =92, DQ11 =80
5523 12:11:38.669816 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =98
5524 12:11:38.669898
5525 12:11:38.669963
5526 12:11:38.675967 [DQSOSCAuto] RK0, (LSB)MR18= 0x3232, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5527 12:11:38.679638 CH1 RK0: MR19=505, MR18=3232
5528 12:11:38.686084 CH1_RK0: MR19=0x505, MR18=0x3232, DQSOSC=406, MR23=63, INC=65, DEC=43
5529 12:11:38.686167
5530 12:11:38.689448 ----->DramcWriteLeveling(PI) begin...
5531 12:11:38.689531 ==
5532 12:11:38.692947 Dram Type= 6, Freq= 0, CH_1, rank 1
5533 12:11:38.695757 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5534 12:11:38.695839 ==
5535 12:11:38.699684 Write leveling (Byte 0): 24 => 24
5536 12:11:38.703318 Write leveling (Byte 1): 25 => 25
5537 12:11:38.705944 DramcWriteLeveling(PI) end<-----
5538 12:11:38.706026
5539 12:11:38.706090 ==
5540 12:11:38.709758 Dram Type= 6, Freq= 0, CH_1, rank 1
5541 12:11:38.712446 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5542 12:11:38.712528 ==
5543 12:11:38.716008 [Gating] SW mode calibration
5544 12:11:38.724148 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5545 12:11:38.729450 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5546 12:11:38.733023 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5547 12:11:38.738691 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5548 12:11:38.742197 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 12:11:38.745624 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 12:11:38.752114 0 10 16 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 1)
5551 12:11:38.755942 0 10 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5552 12:11:38.758793 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5553 12:11:38.762054 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5554 12:11:38.768630 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5555 12:11:38.771458 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5556 12:11:38.775985 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 12:11:38.781548 0 11 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5558 12:11:38.785275 0 11 16 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
5559 12:11:38.788313 0 11 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5560 12:11:38.795182 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5561 12:11:38.798206 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5562 12:11:38.802179 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5563 12:11:38.808711 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 12:11:38.812144 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 12:11:38.814486 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 12:11:38.821571 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5567 12:11:38.825420 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5568 12:11:38.828101 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 12:11:38.835110 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 12:11:38.837867 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 12:11:38.841286 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 12:11:38.848272 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 12:11:38.851979 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 12:11:38.857111 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 12:11:38.861863 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 12:11:38.864420 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 12:11:38.868899 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 12:11:38.874063 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 12:11:38.878604 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 12:11:38.881208 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 12:11:38.887849 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 12:11:38.891206 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5583 12:11:38.894098 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5584 12:11:38.897812 Total UI for P1: 0, mck2ui 16
5585 12:11:38.901218 best dqsien dly found for B0: ( 0, 14, 16)
5586 12:11:38.907413 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 12:11:38.907497 Total UI for P1: 0, mck2ui 16
5588 12:11:38.914301 best dqsien dly found for B1: ( 0, 14, 20)
5589 12:11:38.917476 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5590 12:11:38.920902 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5591 12:11:38.920985
5592 12:11:38.924256 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5593 12:11:38.927335 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5594 12:11:38.930690 [Gating] SW calibration Done
5595 12:11:38.930773 ==
5596 12:11:38.934273 Dram Type= 6, Freq= 0, CH_1, rank 1
5597 12:11:38.937093 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5598 12:11:38.937177 ==
5599 12:11:38.940990 RX Vref Scan: 0
5600 12:11:38.941072
5601 12:11:38.944116 RX Vref 0 -> 0, step: 1
5602 12:11:38.944198
5603 12:11:38.944263 RX Delay -80 -> 252, step: 8
5604 12:11:38.950367 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5605 12:11:38.953900 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5606 12:11:38.956709 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5607 12:11:38.960650 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5608 12:11:38.963780 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5609 12:11:38.966479 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5610 12:11:38.973761 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5611 12:11:38.976516 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5612 12:11:38.979676 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5613 12:11:38.983528 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5614 12:11:38.987091 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5615 12:11:38.989984 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5616 12:11:38.996424 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5617 12:11:38.999949 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5618 12:11:39.003331 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5619 12:11:39.006883 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5620 12:11:39.006965 ==
5621 12:11:39.010025 Dram Type= 6, Freq= 0, CH_1, rank 1
5622 12:11:39.013345 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5623 12:11:39.016518 ==
5624 12:11:39.016600 DQS Delay:
5625 12:11:39.016666 DQS0 = 0, DQS1 = 0
5626 12:11:39.020119 DQM Delay:
5627 12:11:39.020202 DQM0 = 97, DQM1 = 89
5628 12:11:39.022850 DQ Delay:
5629 12:11:39.026763 DQ0 =95, DQ1 =91, DQ2 =91, DQ3 =95
5630 12:11:39.030072 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5631 12:11:39.033148 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5632 12:11:39.036393 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5633 12:11:39.036475
5634 12:11:39.036540
5635 12:11:39.036602 ==
5636 12:11:39.040306 Dram Type= 6, Freq= 0, CH_1, rank 1
5637 12:11:39.042837 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5638 12:11:39.042920 ==
5639 12:11:39.042985
5640 12:11:39.043045
5641 12:11:39.046092 TX Vref Scan disable
5642 12:11:39.046174 == TX Byte 0 ==
5643 12:11:39.053683 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5644 12:11:39.056206 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5645 12:11:39.056289 == TX Byte 1 ==
5646 12:11:39.062828 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5647 12:11:39.066420 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5648 12:11:39.066503 ==
5649 12:11:39.069981 Dram Type= 6, Freq= 0, CH_1, rank 1
5650 12:11:39.073119 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5651 12:11:39.073202 ==
5652 12:11:39.073267
5653 12:11:39.073328
5654 12:11:39.076130 TX Vref Scan disable
5655 12:11:39.079369 == TX Byte 0 ==
5656 12:11:39.083476 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5657 12:11:39.086083 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5658 12:11:39.089312 == TX Byte 1 ==
5659 12:11:39.092408 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5660 12:11:39.096007 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5661 12:11:39.096090
5662 12:11:39.099308 [DATLAT]
5663 12:11:39.099391 Freq=933, CH1 RK1
5664 12:11:39.099457
5665 12:11:39.102448 DATLAT Default: 0xb
5666 12:11:39.102530 0, 0xFFFF, sum = 0
5667 12:11:39.105761 1, 0xFFFF, sum = 0
5668 12:11:39.105845 2, 0xFFFF, sum = 0
5669 12:11:39.109010 3, 0xFFFF, sum = 0
5670 12:11:39.109093 4, 0xFFFF, sum = 0
5671 12:11:39.112249 5, 0xFFFF, sum = 0
5672 12:11:39.112333 6, 0xFFFF, sum = 0
5673 12:11:39.116048 7, 0xFFFF, sum = 0
5674 12:11:39.119005 8, 0xFFFF, sum = 0
5675 12:11:39.119089 9, 0xFFFF, sum = 0
5676 12:11:39.119156 10, 0x0, sum = 1
5677 12:11:39.122488 11, 0x0, sum = 2
5678 12:11:39.122572 12, 0x0, sum = 3
5679 12:11:39.125705 13, 0x0, sum = 4
5680 12:11:39.125789 best_step = 11
5681 12:11:39.125855
5682 12:11:39.125915 ==
5683 12:11:39.128920 Dram Type= 6, Freq= 0, CH_1, rank 1
5684 12:11:39.135699 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5685 12:11:39.135782 ==
5686 12:11:39.135848 RX Vref Scan: 0
5687 12:11:39.135909
5688 12:11:39.138892 RX Vref 0 -> 0, step: 1
5689 12:11:39.138974
5690 12:11:39.142140 RX Delay -69 -> 252, step: 4
5691 12:11:39.146301 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5692 12:11:39.151932 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5693 12:11:39.155345 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5694 12:11:39.159847 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5695 12:11:39.162667 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5696 12:11:39.165790 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5697 12:11:39.168605 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5698 12:11:39.175128 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5699 12:11:39.178546 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5700 12:11:39.181901 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5701 12:11:39.185389 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5702 12:11:39.188472 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5703 12:11:39.195296 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5704 12:11:39.198586 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5705 12:11:39.201830 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5706 12:11:39.204852 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5707 12:11:39.204935 ==
5708 12:11:39.208318 Dram Type= 6, Freq= 0, CH_1, rank 1
5709 12:11:39.212397 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5710 12:11:39.214759 ==
5711 12:11:39.214842 DQS Delay:
5712 12:11:39.214907 DQS0 = 0, DQS1 = 0
5713 12:11:39.218815 DQM Delay:
5714 12:11:39.218898 DQM0 = 96, DQM1 = 87
5715 12:11:39.221568 DQ Delay:
5716 12:11:39.221650 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =92
5717 12:11:39.224882 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5718 12:11:39.227944 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5719 12:11:39.231769 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5720 12:11:39.234490
5721 12:11:39.234572
5722 12:11:39.241383 [DQSOSCAuto] RK1, (LSB)MR18= 0x2727, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5723 12:11:39.244644 CH1 RK1: MR19=505, MR18=2727
5724 12:11:39.251239 CH1_RK1: MR19=0x505, MR18=0x2727, DQSOSC=409, MR23=63, INC=64, DEC=43
5725 12:11:39.254500 [RxdqsGatingPostProcess] freq 933
5726 12:11:39.258104 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5727 12:11:39.261324 Pre-setting of DQS Precalculation
5728 12:11:39.268099 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5729 12:11:39.275087 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5730 12:11:39.281203 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5731 12:11:39.281286
5732 12:11:39.281352
5733 12:11:39.283924 [Calibration Summary] 1866 Mbps
5734 12:11:39.284006 CH 0, Rank 0
5735 12:11:39.287553 SW Impedance : PASS
5736 12:11:39.290751 DUTY Scan : NO K
5737 12:11:39.290834 ZQ Calibration : PASS
5738 12:11:39.294782 Jitter Meter : NO K
5739 12:11:39.298006 CBT Training : PASS
5740 12:11:39.298088 Write leveling : PASS
5741 12:11:39.300781 RX DQS gating : PASS
5742 12:11:39.304829 RX DQ/DQS(RDDQC) : PASS
5743 12:11:39.304911 TX DQ/DQS : PASS
5744 12:11:39.308096 RX DATLAT : PASS
5745 12:11:39.310559 RX DQ/DQS(Engine): PASS
5746 12:11:39.310641 TX OE : NO K
5747 12:11:39.313728 All Pass.
5748 12:11:39.313810
5749 12:11:39.313876 CH 0, Rank 1
5750 12:11:39.317029 SW Impedance : PASS
5751 12:11:39.317112 DUTY Scan : NO K
5752 12:11:39.320833 ZQ Calibration : PASS
5753 12:11:39.324340 Jitter Meter : NO K
5754 12:11:39.324422 CBT Training : PASS
5755 12:11:39.327598 Write leveling : PASS
5756 12:11:39.327681 RX DQS gating : PASS
5757 12:11:39.330889 RX DQ/DQS(RDDQC) : PASS
5758 12:11:39.334289 TX DQ/DQS : PASS
5759 12:11:39.334372 RX DATLAT : PASS
5760 12:11:39.337671 RX DQ/DQS(Engine): PASS
5761 12:11:39.340692 TX OE : NO K
5762 12:11:39.340781 All Pass.
5763 12:11:39.340847
5764 12:11:39.340908 CH 1, Rank 0
5765 12:11:39.343795 SW Impedance : PASS
5766 12:11:39.347425 DUTY Scan : NO K
5767 12:11:39.347507 ZQ Calibration : PASS
5768 12:11:39.350664 Jitter Meter : NO K
5769 12:11:39.354208 CBT Training : PASS
5770 12:11:39.354291 Write leveling : PASS
5771 12:11:39.357109 RX DQS gating : PASS
5772 12:11:39.360655 RX DQ/DQS(RDDQC) : PASS
5773 12:11:39.360779 TX DQ/DQS : PASS
5774 12:11:39.364135 RX DATLAT : PASS
5775 12:11:39.367471 RX DQ/DQS(Engine): PASS
5776 12:11:39.367554 TX OE : NO K
5777 12:11:39.367620 All Pass.
5778 12:11:39.370503
5779 12:11:39.370585 CH 1, Rank 1
5780 12:11:39.373953 SW Impedance : PASS
5781 12:11:39.374036 DUTY Scan : NO K
5782 12:11:39.376927 ZQ Calibration : PASS
5783 12:11:39.381200 Jitter Meter : NO K
5784 12:11:39.381282 CBT Training : PASS
5785 12:11:39.383749 Write leveling : PASS
5786 12:11:39.383832 RX DQS gating : PASS
5787 12:11:39.386965 RX DQ/DQS(RDDQC) : PASS
5788 12:11:39.390740 TX DQ/DQS : PASS
5789 12:11:39.390823 RX DATLAT : PASS
5790 12:11:39.394087 RX DQ/DQS(Engine): PASS
5791 12:11:39.397767 TX OE : NO K
5792 12:11:39.397851 All Pass.
5793 12:11:39.397916
5794 12:11:39.400386 DramC Write-DBI off
5795 12:11:39.400469 PER_BANK_REFRESH: Hybrid Mode
5796 12:11:39.403555 TX_TRACKING: ON
5797 12:11:39.413471 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5798 12:11:39.416884 [FAST_K] Save calibration result to emmc
5799 12:11:39.420417 dramc_set_vcore_voltage set vcore to 650000
5800 12:11:39.420500 Read voltage for 400, 6
5801 12:11:39.424003 Vio18 = 0
5802 12:11:39.424086 Vcore = 650000
5803 12:11:39.424152 Vdram = 0
5804 12:11:39.427217 Vddq = 0
5805 12:11:39.427300 Vmddr = 0
5806 12:11:39.430096 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5807 12:11:39.436449 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5808 12:11:39.440428 MEM_TYPE=3, freq_sel=20
5809 12:11:39.442996 sv_algorithm_assistance_LP4_800
5810 12:11:39.446449 ============ PULL DRAM RESETB DOWN ============
5811 12:11:39.450222 ========== PULL DRAM RESETB DOWN end =========
5812 12:11:39.456697 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5813 12:11:39.459738 ===================================
5814 12:11:39.459822 LPDDR4 DRAM CONFIGURATION
5815 12:11:39.463332 ===================================
5816 12:11:39.466922 EX_ROW_EN[0] = 0x0
5817 12:11:39.467005 EX_ROW_EN[1] = 0x0
5818 12:11:39.470277 LP4Y_EN = 0x0
5819 12:11:39.470360 WORK_FSP = 0x0
5820 12:11:39.473656 WL = 0x2
5821 12:11:39.476854 RL = 0x2
5822 12:11:39.476936 BL = 0x2
5823 12:11:39.479847 RPST = 0x0
5824 12:11:39.479930 RD_PRE = 0x0
5825 12:11:39.483209 WR_PRE = 0x1
5826 12:11:39.483291 WR_PST = 0x0
5827 12:11:39.486745 DBI_WR = 0x0
5828 12:11:39.486827 DBI_RD = 0x0
5829 12:11:39.489602 OTF = 0x1
5830 12:11:39.492672 ===================================
5831 12:11:39.497021 ===================================
5832 12:11:39.497104 ANA top config
5833 12:11:39.500551 ===================================
5834 12:11:39.503238 DLL_ASYNC_EN = 0
5835 12:11:39.506992 ALL_SLAVE_EN = 1
5836 12:11:39.507074 NEW_RANK_MODE = 1
5837 12:11:39.509485 DLL_IDLE_MODE = 1
5838 12:11:39.512839 LP45_APHY_COMB_EN = 1
5839 12:11:39.515849 TX_ODT_DIS = 1
5840 12:11:39.519441 NEW_8X_MODE = 1
5841 12:11:39.522980 ===================================
5842 12:11:39.525664 ===================================
5843 12:11:39.528995 data_rate = 800
5844 12:11:39.529077 CKR = 1
5845 12:11:39.532791 DQ_P2S_RATIO = 4
5846 12:11:39.535806 ===================================
5847 12:11:39.539455 CA_P2S_RATIO = 4
5848 12:11:39.541899 DQ_CA_OPEN = 0
5849 12:11:39.546029 DQ_SEMI_OPEN = 1
5850 12:11:39.548688 CA_SEMI_OPEN = 1
5851 12:11:39.548809 CA_FULL_RATE = 0
5852 12:11:39.552022 DQ_CKDIV4_EN = 0
5853 12:11:39.555046 CA_CKDIV4_EN = 1
5854 12:11:39.558584 CA_PREDIV_EN = 0
5855 12:11:39.562240 PH8_DLY = 0
5856 12:11:39.565800 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5857 12:11:39.565883 DQ_AAMCK_DIV = 0
5858 12:11:39.569097 CA_AAMCK_DIV = 0
5859 12:11:39.572377 CA_ADMCK_DIV = 4
5860 12:11:39.575650 DQ_TRACK_CA_EN = 0
5861 12:11:39.579433 CA_PICK = 800
5862 12:11:39.581816 CA_MCKIO = 400
5863 12:11:39.585288 MCKIO_SEMI = 400
5864 12:11:39.585371 PLL_FREQ = 3016
5865 12:11:39.588372 DQ_UI_PI_RATIO = 32
5866 12:11:39.591831 CA_UI_PI_RATIO = 32
5867 12:11:39.594935 ===================================
5868 12:11:39.598330 ===================================
5869 12:11:39.602234 memory_type:LPDDR4
5870 12:11:39.605664 GP_NUM : 10
5871 12:11:39.605747 SRAM_EN : 1
5872 12:11:39.608161 MD32_EN : 0
5873 12:11:39.611978 ===================================
5874 12:11:39.612061 [ANA_INIT] >>>>>>>>>>>>>>
5875 12:11:39.614702 <<<<<< [CONFIGURE PHASE]: ANA_TX
5876 12:11:39.618430 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5877 12:11:39.621658 ===================================
5878 12:11:39.625139 data_rate = 800,PCW = 0X7400
5879 12:11:39.628262 ===================================
5880 12:11:39.632398 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5881 12:11:39.639009 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5882 12:11:39.648300 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5883 12:11:39.655881 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5884 12:11:39.658185 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5885 12:11:39.661729 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5886 12:11:39.661813 [ANA_INIT] flow start
5887 12:11:39.664293 [ANA_INIT] PLL >>>>>>>>
5888 12:11:39.668338 [ANA_INIT] PLL <<<<<<<<
5889 12:11:39.668421 [ANA_INIT] MIDPI >>>>>>>>
5890 12:11:39.672062 [ANA_INIT] MIDPI <<<<<<<<
5891 12:11:39.674511 [ANA_INIT] DLL >>>>>>>>
5892 12:11:39.674593 [ANA_INIT] flow end
5893 12:11:39.681046 ============ LP4 DIFF to SE enter ============
5894 12:11:39.685031 ============ LP4 DIFF to SE exit ============
5895 12:11:39.687756 [ANA_INIT] <<<<<<<<<<<<<
5896 12:11:39.691093 [Flow] Enable top DCM control >>>>>
5897 12:11:39.695043 [Flow] Enable top DCM control <<<<<
5898 12:11:39.697398 Enable DLL master slave shuffle
5899 12:11:39.701406 ==============================================================
5900 12:11:39.704208 Gating Mode config
5901 12:11:39.707895 ==============================================================
5902 12:11:39.711632 Config description:
5903 12:11:39.721342 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5904 12:11:39.727875 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5905 12:11:39.730603 SELPH_MODE 0: By rank 1: By Phase
5906 12:11:39.737724 ==============================================================
5907 12:11:39.741199 GAT_TRACK_EN = 0
5908 12:11:39.743706 RX_GATING_MODE = 2
5909 12:11:39.747647 RX_GATING_TRACK_MODE = 2
5910 12:11:39.750753 SELPH_MODE = 1
5911 12:11:39.753980 PICG_EARLY_EN = 1
5912 12:11:39.754063 VALID_LAT_VALUE = 1
5913 12:11:39.760786 ==============================================================
5914 12:11:39.764200 Enter into Gating configuration >>>>
5915 12:11:39.767642 Exit from Gating configuration <<<<
5916 12:11:39.770533 Enter into DVFS_PRE_config >>>>>
5917 12:11:39.780171 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5918 12:11:39.783553 Exit from DVFS_PRE_config <<<<<
5919 12:11:39.787685 Enter into PICG configuration >>>>
5920 12:11:39.790276 Exit from PICG configuration <<<<
5921 12:11:39.793197 [RX_INPUT] configuration >>>>>
5922 12:11:39.796591 [RX_INPUT] configuration <<<<<
5923 12:11:39.803317 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5924 12:11:39.807031 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5925 12:11:39.813362 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5926 12:11:39.819540 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5927 12:11:39.826341 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5928 12:11:39.833232 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5929 12:11:39.836101 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5930 12:11:39.839702 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5931 12:11:39.842395 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5932 12:11:39.849194 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5933 12:11:39.852527 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5934 12:11:39.856008 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5935 12:11:39.860290 ===================================
5936 12:11:39.862662 LPDDR4 DRAM CONFIGURATION
5937 12:11:39.866716 ===================================
5938 12:11:39.869362 EX_ROW_EN[0] = 0x0
5939 12:11:39.869445 EX_ROW_EN[1] = 0x0
5940 12:11:39.873265 LP4Y_EN = 0x0
5941 12:11:39.873348 WORK_FSP = 0x0
5942 12:11:39.876385 WL = 0x2
5943 12:11:39.876467 RL = 0x2
5944 12:11:39.879296 BL = 0x2
5945 12:11:39.879378 RPST = 0x0
5946 12:11:39.882415 RD_PRE = 0x0
5947 12:11:39.882497 WR_PRE = 0x1
5948 12:11:39.886109 WR_PST = 0x0
5949 12:11:39.886191 DBI_WR = 0x0
5950 12:11:39.889205 DBI_RD = 0x0
5951 12:11:39.889288 OTF = 0x1
5952 12:11:39.892271 ===================================
5953 12:11:39.899482 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5954 12:11:39.902969 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5955 12:11:39.905574 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5956 12:11:39.908883 ===================================
5957 12:11:39.912550 LPDDR4 DRAM CONFIGURATION
5958 12:11:39.915729 ===================================
5959 12:11:39.918871 EX_ROW_EN[0] = 0x10
5960 12:11:39.918954 EX_ROW_EN[1] = 0x0
5961 12:11:39.922344 LP4Y_EN = 0x0
5962 12:11:39.922427 WORK_FSP = 0x0
5963 12:11:39.925383 WL = 0x2
5964 12:11:39.925466 RL = 0x2
5965 12:11:39.928516 BL = 0x2
5966 12:11:39.928614 RPST = 0x0
5967 12:11:39.932123 RD_PRE = 0x0
5968 12:11:39.932206 WR_PRE = 0x1
5969 12:11:39.935906 WR_PST = 0x0
5970 12:11:39.935989 DBI_WR = 0x0
5971 12:11:39.938746 DBI_RD = 0x0
5972 12:11:39.938829 OTF = 0x1
5973 12:11:39.942153 ===================================
5974 12:11:39.948712 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5975 12:11:39.953634 nWR fixed to 30
5976 12:11:39.956527 [ModeRegInit_LP4] CH0 RK0
5977 12:11:39.956609 [ModeRegInit_LP4] CH0 RK1
5978 12:11:39.959825 [ModeRegInit_LP4] CH1 RK0
5979 12:11:39.963600 [ModeRegInit_LP4] CH1 RK1
5980 12:11:39.963682 match AC timing 18
5981 12:11:39.970376 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5982 12:11:39.973230 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5983 12:11:39.976995 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5984 12:11:39.982976 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5985 12:11:39.986375 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5986 12:11:39.986458 ==
5987 12:11:39.989571 Dram Type= 6, Freq= 0, CH_0, rank 0
5988 12:11:39.993293 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5989 12:11:39.993377 ==
5990 12:11:39.999974 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5991 12:11:40.006862 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5992 12:11:40.009699 [CA 0] Center 36 (8~64) winsize 57
5993 12:11:40.013108 [CA 1] Center 36 (8~64) winsize 57
5994 12:11:40.016583 [CA 2] Center 36 (8~64) winsize 57
5995 12:11:40.020476 [CA 3] Center 36 (8~64) winsize 57
5996 12:11:40.020559 [CA 4] Center 36 (8~64) winsize 57
5997 12:11:40.022814 [CA 5] Center 36 (8~64) winsize 57
5998 12:11:40.022897
5999 12:11:40.029553 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6000 12:11:40.029636
6001 12:11:40.034058 [CATrainingPosCal] consider 1 rank data
6002 12:11:40.036685 u2DelayCellTimex100 = 270/100 ps
6003 12:11:40.039937 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6004 12:11:40.043397 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6005 12:11:40.046391 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6006 12:11:40.049346 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6007 12:11:40.053137 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6008 12:11:40.056159 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6009 12:11:40.056276
6010 12:11:40.059851 CA PerBit enable=1, Macro0, CA PI delay=36
6011 12:11:40.059933
6012 12:11:40.063525 [CBTSetCACLKResult] CA Dly = 36
6013 12:11:40.067075 CS Dly: 1 (0~32)
6014 12:11:40.067158 ==
6015 12:11:40.069108 Dram Type= 6, Freq= 0, CH_0, rank 1
6016 12:11:40.072337 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6017 12:11:40.072420 ==
6018 12:11:40.079850 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6019 12:11:40.086192 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6020 12:11:40.086275 [CA 0] Center 36 (8~64) winsize 57
6021 12:11:40.089322 [CA 1] Center 36 (8~64) winsize 57
6022 12:11:40.092847 [CA 2] Center 36 (8~64) winsize 57
6023 12:11:40.096010 [CA 3] Center 36 (8~64) winsize 57
6024 12:11:40.099071 [CA 4] Center 36 (8~64) winsize 57
6025 12:11:40.103108 [CA 5] Center 36 (8~64) winsize 57
6026 12:11:40.103190
6027 12:11:40.106359 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6028 12:11:40.106442
6029 12:11:40.109570 [CATrainingPosCal] consider 2 rank data
6030 12:11:40.113203 u2DelayCellTimex100 = 270/100 ps
6031 12:11:40.115918 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6032 12:11:40.122402 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6033 12:11:40.125688 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6034 12:11:40.129189 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6035 12:11:40.132914 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6036 12:11:40.135352 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6037 12:11:40.135434
6038 12:11:40.138769 CA PerBit enable=1, Macro0, CA PI delay=36
6039 12:11:40.138851
6040 12:11:40.142923 [CBTSetCACLKResult] CA Dly = 36
6041 12:11:40.143043 CS Dly: 1 (0~32)
6042 12:11:40.146318
6043 12:11:40.148818 ----->DramcWriteLeveling(PI) begin...
6044 12:11:40.148902 ==
6045 12:11:40.153217 Dram Type= 6, Freq= 0, CH_0, rank 0
6046 12:11:40.155435 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6047 12:11:40.155518 ==
6048 12:11:40.159230 Write leveling (Byte 0): 32 => 0
6049 12:11:40.162258 Write leveling (Byte 1): 32 => 0
6050 12:11:40.165854 DramcWriteLeveling(PI) end<-----
6051 12:11:40.165937
6052 12:11:40.166002 ==
6053 12:11:40.168509 Dram Type= 6, Freq= 0, CH_0, rank 0
6054 12:11:40.172255 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6055 12:11:40.172339 ==
6056 12:11:40.175253 [Gating] SW mode calibration
6057 12:11:40.182696 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6058 12:11:40.188275 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6059 12:11:40.192844 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6060 12:11:40.195679 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6061 12:11:40.201786 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6062 12:11:40.205616 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6063 12:11:40.209301 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6064 12:11:40.214828 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6065 12:11:40.218689 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6066 12:11:40.221954 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6067 12:11:40.228827 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6068 12:11:40.228910 Total UI for P1: 0, mck2ui 16
6069 12:11:40.231524 best dqsien dly found for B0: ( 0, 10, 16)
6070 12:11:40.235596 Total UI for P1: 0, mck2ui 16
6071 12:11:40.238818 best dqsien dly found for B1: ( 0, 10, 16)
6072 12:11:40.245059 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6073 12:11:40.248269 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6074 12:11:40.248352
6075 12:11:40.252166 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6076 12:11:40.254898 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6077 12:11:40.258361 [Gating] SW calibration Done
6078 12:11:40.258444 ==
6079 12:11:40.261710 Dram Type= 6, Freq= 0, CH_0, rank 0
6080 12:11:40.266161 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6081 12:11:40.266245 ==
6082 12:11:40.267931 RX Vref Scan: 0
6083 12:11:40.268014
6084 12:11:40.268079 RX Vref 0 -> 0, step: 1
6085 12:11:40.268140
6086 12:11:40.271372 RX Delay -410 -> 252, step: 16
6087 12:11:40.277789 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6088 12:11:40.281390 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6089 12:11:40.285248 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6090 12:11:40.288328 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6091 12:11:40.294816 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6092 12:11:40.297811 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6093 12:11:40.301394 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6094 12:11:40.304238 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6095 12:11:40.311132 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6096 12:11:40.315158 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6097 12:11:40.317778 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6098 12:11:40.320977 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6099 12:11:40.327678 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6100 12:11:40.330744 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6101 12:11:40.333964 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6102 12:11:40.337569 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6103 12:11:40.340949 ==
6104 12:11:40.343764 Dram Type= 6, Freq= 0, CH_0, rank 0
6105 12:11:40.347854 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6106 12:11:40.347938 ==
6107 12:11:40.348004 DQS Delay:
6108 12:11:40.351203 DQS0 = 51, DQS1 = 59
6109 12:11:40.351285 DQM Delay:
6110 12:11:40.353814 DQM0 = 12, DQM1 = 14
6111 12:11:40.353896 DQ Delay:
6112 12:11:40.357337 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6113 12:11:40.361192 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6114 12:11:40.364912 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6115 12:11:40.367131 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6116 12:11:40.367214
6117 12:11:40.367279
6118 12:11:40.367340 ==
6119 12:11:40.370390 Dram Type= 6, Freq= 0, CH_0, rank 0
6120 12:11:40.374388 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6121 12:11:40.374472 ==
6122 12:11:40.374538
6123 12:11:40.374599
6124 12:11:40.378320 TX Vref Scan disable
6125 12:11:40.378403 == TX Byte 0 ==
6126 12:11:40.384973 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6127 12:11:40.388903 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6128 12:11:40.389012 == TX Byte 1 ==
6129 12:11:40.394102 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6130 12:11:40.397633 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6131 12:11:40.397716 ==
6132 12:11:40.400356 Dram Type= 6, Freq= 0, CH_0, rank 0
6133 12:11:40.404015 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6134 12:11:40.404099 ==
6135 12:11:40.404164
6136 12:11:40.404225
6137 12:11:40.407670 TX Vref Scan disable
6138 12:11:40.407753 == TX Byte 0 ==
6139 12:11:40.414298 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6140 12:11:40.417007 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6141 12:11:40.420957 == TX Byte 1 ==
6142 12:11:40.424334 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6143 12:11:40.427060 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6144 12:11:40.427171
6145 12:11:40.427265 [DATLAT]
6146 12:11:40.430855 Freq=400, CH0 RK0
6147 12:11:40.430938
6148 12:11:40.431003 DATLAT Default: 0xf
6149 12:11:40.434402 0, 0xFFFF, sum = 0
6150 12:11:40.434486 1, 0xFFFF, sum = 0
6151 12:11:40.437054 2, 0xFFFF, sum = 0
6152 12:11:40.440316 3, 0xFFFF, sum = 0
6153 12:11:40.440399 4, 0xFFFF, sum = 0
6154 12:11:40.444090 5, 0xFFFF, sum = 0
6155 12:11:40.444174 6, 0xFFFF, sum = 0
6156 12:11:40.447082 7, 0xFFFF, sum = 0
6157 12:11:40.447166 8, 0xFFFF, sum = 0
6158 12:11:40.450936 9, 0xFFFF, sum = 0
6159 12:11:40.451020 10, 0xFFFF, sum = 0
6160 12:11:40.453470 11, 0xFFFF, sum = 0
6161 12:11:40.453593 12, 0x0, sum = 1
6162 12:11:40.456595 13, 0x0, sum = 2
6163 12:11:40.456727 14, 0x0, sum = 3
6164 12:11:40.459844 15, 0x0, sum = 4
6165 12:11:40.459956 best_step = 13
6166 12:11:40.460049
6167 12:11:40.460149 ==
6168 12:11:40.463374 Dram Type= 6, Freq= 0, CH_0, rank 0
6169 12:11:40.466996 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6170 12:11:40.470292 ==
6171 12:11:40.470375 RX Vref Scan: 1
6172 12:11:40.470441
6173 12:11:40.473719 RX Vref 0 -> 0, step: 1
6174 12:11:40.473802
6175 12:11:40.476687 RX Delay -359 -> 252, step: 8
6176 12:11:40.476780
6177 12:11:40.480032 Set Vref, RX VrefLevel [Byte0]: 46
6178 12:11:40.483704 [Byte1]: 47
6179 12:11:40.483787
6180 12:11:40.486700 Final RX Vref Byte 0 = 46 to rank0
6181 12:11:40.489777 Final RX Vref Byte 1 = 47 to rank0
6182 12:11:40.493480 Final RX Vref Byte 0 = 46 to rank1
6183 12:11:40.496586 Final RX Vref Byte 1 = 47 to rank1==
6184 12:11:40.500083 Dram Type= 6, Freq= 0, CH_0, rank 0
6185 12:11:40.503264 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6186 12:11:40.503349 ==
6187 12:11:40.506263 DQS Delay:
6188 12:11:40.506345 DQS0 = 52, DQS1 = 68
6189 12:11:40.510510 DQM Delay:
6190 12:11:40.510592 DQM0 = 8, DQM1 = 16
6191 12:11:40.510658 DQ Delay:
6192 12:11:40.513729 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6193 12:11:40.516290 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6194 12:11:40.519961 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6195 12:11:40.523023 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6196 12:11:40.523105
6197 12:11:40.523171
6198 12:11:40.533934 [DQSOSCAuto] RK0, (LSB)MR18= 0xa4a4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6199 12:11:40.534017 CH0 RK0: MR19=C0C, MR18=A4A4
6200 12:11:40.540141 CH0_RK0: MR19=0xC0C, MR18=0xA4A4, DQSOSC=389, MR23=63, INC=390, DEC=260
6201 12:11:40.540225 ==
6202 12:11:40.543723 Dram Type= 6, Freq= 0, CH_0, rank 1
6203 12:11:40.549163 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6204 12:11:40.549247 ==
6205 12:11:40.552866 [Gating] SW mode calibration
6206 12:11:40.559168 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6207 12:11:40.562743 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6208 12:11:40.569088 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6209 12:11:40.573338 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6210 12:11:40.576318 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6211 12:11:40.582821 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6212 12:11:40.585752 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6213 12:11:40.589283 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6214 12:11:40.595693 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6215 12:11:40.599091 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6216 12:11:40.602236 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6217 12:11:40.606200 Total UI for P1: 0, mck2ui 16
6218 12:11:40.608865 best dqsien dly found for B0: ( 0, 10, 16)
6219 12:11:40.612712 Total UI for P1: 0, mck2ui 16
6220 12:11:40.615929 best dqsien dly found for B1: ( 0, 10, 16)
6221 12:11:40.618941 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6222 12:11:40.622351 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6223 12:11:40.622435
6224 12:11:40.629527 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6225 12:11:40.632275 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6226 12:11:40.635224 [Gating] SW calibration Done
6227 12:11:40.635307 ==
6228 12:11:40.638794 Dram Type= 6, Freq= 0, CH_0, rank 1
6229 12:11:40.642502 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6230 12:11:40.642585 ==
6231 12:11:40.642651 RX Vref Scan: 0
6232 12:11:40.642712
6233 12:11:40.646200 RX Vref 0 -> 0, step: 1
6234 12:11:40.646282
6235 12:11:40.648840 RX Delay -410 -> 252, step: 16
6236 12:11:40.651879 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6237 12:11:40.659096 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6238 12:11:40.661897 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6239 12:11:40.665365 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6240 12:11:40.668626 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6241 12:11:40.675717 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6242 12:11:40.678609 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6243 12:11:40.682048 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6244 12:11:40.684958 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6245 12:11:40.691760 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6246 12:11:40.695400 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6247 12:11:40.698249 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6248 12:11:40.702047 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6249 12:11:40.708813 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6250 12:11:40.711601 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6251 12:11:40.714991 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6252 12:11:40.715074 ==
6253 12:11:40.718244 Dram Type= 6, Freq= 0, CH_0, rank 1
6254 12:11:40.725178 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6255 12:11:40.725262 ==
6256 12:11:40.725328 DQS Delay:
6257 12:11:40.728178 DQS0 = 43, DQS1 = 59
6258 12:11:40.728261 DQM Delay:
6259 12:11:40.728327 DQM0 = 7, DQM1 = 14
6260 12:11:40.731658 DQ Delay:
6261 12:11:40.734610 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6262 12:11:40.734694 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6263 12:11:40.737852 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6264 12:11:40.741543 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6265 12:11:40.741625
6266 12:11:40.744991
6267 12:11:40.745073 ==
6268 12:11:40.747650 Dram Type= 6, Freq= 0, CH_0, rank 1
6269 12:11:40.751226 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6270 12:11:40.751309 ==
6271 12:11:40.751375
6272 12:11:40.751437
6273 12:11:40.754808 TX Vref Scan disable
6274 12:11:40.754891 == TX Byte 0 ==
6275 12:11:40.757652 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6276 12:11:40.764257 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6277 12:11:40.764340 == TX Byte 1 ==
6278 12:11:40.768046 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6279 12:11:40.774906 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6280 12:11:40.774989 ==
6281 12:11:40.777685 Dram Type= 6, Freq= 0, CH_0, rank 1
6282 12:11:40.780628 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6283 12:11:40.780735 ==
6284 12:11:40.780816
6285 12:11:40.780878
6286 12:11:40.784196 TX Vref Scan disable
6287 12:11:40.784279 == TX Byte 0 ==
6288 12:11:40.787451 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6289 12:11:40.793971 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6290 12:11:40.794054 == TX Byte 1 ==
6291 12:11:40.797607 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6292 12:11:40.804015 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6293 12:11:40.804098
6294 12:11:40.804163 [DATLAT]
6295 12:11:40.807455 Freq=400, CH0 RK1
6296 12:11:40.807537
6297 12:11:40.807602 DATLAT Default: 0xd
6298 12:11:40.810683 0, 0xFFFF, sum = 0
6299 12:11:40.810767 1, 0xFFFF, sum = 0
6300 12:11:40.814154 2, 0xFFFF, sum = 0
6301 12:11:40.814237 3, 0xFFFF, sum = 0
6302 12:11:40.817826 4, 0xFFFF, sum = 0
6303 12:11:40.817910 5, 0xFFFF, sum = 0
6304 12:11:40.821218 6, 0xFFFF, sum = 0
6305 12:11:40.821301 7, 0xFFFF, sum = 0
6306 12:11:40.824218 8, 0xFFFF, sum = 0
6307 12:11:40.824302 9, 0xFFFF, sum = 0
6308 12:11:40.827585 10, 0xFFFF, sum = 0
6309 12:11:40.827669 11, 0xFFFF, sum = 0
6310 12:11:40.830762 12, 0x0, sum = 1
6311 12:11:40.830845 13, 0x0, sum = 2
6312 12:11:40.834024 14, 0x0, sum = 3
6313 12:11:40.834107 15, 0x0, sum = 4
6314 12:11:40.837474 best_step = 13
6315 12:11:40.837556
6316 12:11:40.837620 ==
6317 12:11:40.840853 Dram Type= 6, Freq= 0, CH_0, rank 1
6318 12:11:40.843804 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6319 12:11:40.843886 ==
6320 12:11:40.848935 RX Vref Scan: 0
6321 12:11:40.849016
6322 12:11:40.849081 RX Vref 0 -> 0, step: 1
6323 12:11:40.849141
6324 12:11:40.851385 RX Delay -359 -> 252, step: 8
6325 12:11:40.858119 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6326 12:11:40.862098 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6327 12:11:40.865429 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6328 12:11:40.868400 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6329 12:11:40.875381 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6330 12:11:40.878225 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6331 12:11:40.881352 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6332 12:11:40.884583 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6333 12:11:40.891924 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6334 12:11:40.894691 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6335 12:11:40.898256 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6336 12:11:40.901884 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6337 12:11:40.908233 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6338 12:11:40.911172 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6339 12:11:40.914723 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6340 12:11:40.921484 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6341 12:11:40.921566 ==
6342 12:11:40.925268 Dram Type= 6, Freq= 0, CH_0, rank 1
6343 12:11:40.928109 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6344 12:11:40.928192 ==
6345 12:11:40.928257 DQS Delay:
6346 12:11:40.931345 DQS0 = 52, DQS1 = 60
6347 12:11:40.931426 DQM Delay:
6348 12:11:40.935218 DQM0 = 10, DQM1 = 10
6349 12:11:40.935300 DQ Delay:
6350 12:11:40.938174 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =4
6351 12:11:40.941212 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6352 12:11:40.944925 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6353 12:11:40.948121 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6354 12:11:40.948204
6355 12:11:40.948269
6356 12:11:40.955227 [DQSOSCAuto] RK1, (LSB)MR18= 0xc7c7, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6357 12:11:40.958181 CH0 RK1: MR19=C0C, MR18=C7C7
6358 12:11:40.964474 CH0_RK1: MR19=0xC0C, MR18=0xC7C7, DQSOSC=385, MR23=63, INC=398, DEC=265
6359 12:11:40.967877 [RxdqsGatingPostProcess] freq 400
6360 12:11:40.974651 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6361 12:11:40.977549 Pre-setting of DQS Precalculation
6362 12:11:40.980647 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6363 12:11:40.980753 ==
6364 12:11:40.984422 Dram Type= 6, Freq= 0, CH_1, rank 0
6365 12:11:40.987561 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6366 12:11:40.987644 ==
6367 12:11:40.994112 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6368 12:11:41.000875 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6369 12:11:41.004192 [CA 0] Center 36 (8~64) winsize 57
6370 12:11:41.007280 [CA 1] Center 36 (8~64) winsize 57
6371 12:11:41.010468 [CA 2] Center 36 (8~64) winsize 57
6372 12:11:41.013676 [CA 3] Center 36 (8~64) winsize 57
6373 12:11:41.017101 [CA 4] Center 36 (8~64) winsize 57
6374 12:11:41.020409 [CA 5] Center 36 (8~64) winsize 57
6375 12:11:41.020492
6376 12:11:41.023748 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6377 12:11:41.023830
6378 12:11:41.026897 [CATrainingPosCal] consider 1 rank data
6379 12:11:41.030456 u2DelayCellTimex100 = 270/100 ps
6380 12:11:41.034251 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6381 12:11:41.036997 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6382 12:11:41.040845 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6383 12:11:41.043923 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6384 12:11:41.047178 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6385 12:11:41.050219 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6386 12:11:41.050302
6387 12:11:41.053355 CA PerBit enable=1, Macro0, CA PI delay=36
6388 12:11:41.057889
6389 12:11:41.057971 [CBTSetCACLKResult] CA Dly = 36
6390 12:11:41.059993 CS Dly: 1 (0~32)
6391 12:11:41.060076 ==
6392 12:11:41.063786 Dram Type= 6, Freq= 0, CH_1, rank 1
6393 12:11:41.066680 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6394 12:11:41.066763 ==
6395 12:11:41.073203 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6396 12:11:41.079817 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6397 12:11:41.083428 [CA 0] Center 36 (8~64) winsize 57
6398 12:11:41.087102 [CA 1] Center 36 (8~64) winsize 57
6399 12:11:41.090226 [CA 2] Center 36 (8~64) winsize 57
6400 12:11:41.090309 [CA 3] Center 36 (8~64) winsize 57
6401 12:11:41.093246 [CA 4] Center 36 (8~64) winsize 57
6402 12:11:41.096907 [CA 5] Center 36 (8~64) winsize 57
6403 12:11:41.096990
6404 12:11:41.103032 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6405 12:11:41.103115
6406 12:11:41.107162 [CATrainingPosCal] consider 2 rank data
6407 12:11:41.109661 u2DelayCellTimex100 = 270/100 ps
6408 12:11:41.113112 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6409 12:11:41.116723 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6410 12:11:41.119659 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6411 12:11:41.122757 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6412 12:11:41.126208 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6413 12:11:41.129261 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6414 12:11:41.129344
6415 12:11:41.133353 CA PerBit enable=1, Macro0, CA PI delay=36
6416 12:11:41.133436
6417 12:11:41.136880 [CBTSetCACLKResult] CA Dly = 36
6418 12:11:41.140081 CS Dly: 1 (0~32)
6419 12:11:41.140163
6420 12:11:41.142857 ----->DramcWriteLeveling(PI) begin...
6421 12:11:41.142941 ==
6422 12:11:41.146653 Dram Type= 6, Freq= 0, CH_1, rank 0
6423 12:11:41.149607 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6424 12:11:41.149690 ==
6425 12:11:41.152570 Write leveling (Byte 0): 32 => 0
6426 12:11:41.155909 Write leveling (Byte 1): 32 => 0
6427 12:11:41.159490 DramcWriteLeveling(PI) end<-----
6428 12:11:41.159572
6429 12:11:41.159638 ==
6430 12:11:41.163532 Dram Type= 6, Freq= 0, CH_1, rank 0
6431 12:11:41.166490 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6432 12:11:41.166573 ==
6433 12:11:41.169401 [Gating] SW mode calibration
6434 12:11:41.176599 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6435 12:11:41.182809 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6436 12:11:41.185662 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6437 12:11:41.188764 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6438 12:11:41.195764 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 12:11:41.198925 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6440 12:11:41.202438 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 12:11:41.209461 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 12:11:41.212653 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 12:11:41.215748 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6444 12:11:41.222245 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6445 12:11:41.225369 Total UI for P1: 0, mck2ui 16
6446 12:11:41.228378 best dqsien dly found for B0: ( 0, 10, 16)
6447 12:11:41.228461 Total UI for P1: 0, mck2ui 16
6448 12:11:41.235378 best dqsien dly found for B1: ( 0, 10, 16)
6449 12:11:41.238414 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6450 12:11:41.241945 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6451 12:11:41.242027
6452 12:11:41.245815 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6453 12:11:41.248645 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6454 12:11:41.251963 [Gating] SW calibration Done
6455 12:11:41.252045 ==
6456 12:11:41.255429 Dram Type= 6, Freq= 0, CH_1, rank 0
6457 12:11:41.258923 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6458 12:11:41.259006 ==
6459 12:11:41.261736 RX Vref Scan: 0
6460 12:11:41.261819
6461 12:11:41.265724 RX Vref 0 -> 0, step: 1
6462 12:11:41.265807
6463 12:11:41.265872 RX Delay -410 -> 252, step: 16
6464 12:11:41.271532 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6465 12:11:41.275701 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6466 12:11:41.278766 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6467 12:11:41.281886 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6468 12:11:41.288807 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6469 12:11:41.291680 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6470 12:11:41.295215 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6471 12:11:41.298486 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6472 12:11:41.304613 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6473 12:11:41.308659 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6474 12:11:41.311581 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6475 12:11:41.315495 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6476 12:11:41.321715 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6477 12:11:41.325277 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6478 12:11:41.328205 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6479 12:11:41.334939 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6480 12:11:41.335022 ==
6481 12:11:41.338294 Dram Type= 6, Freq= 0, CH_1, rank 0
6482 12:11:41.341445 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6483 12:11:41.341531 ==
6484 12:11:41.341597 DQS Delay:
6485 12:11:41.344432 DQS0 = 43, DQS1 = 59
6486 12:11:41.344514 DQM Delay:
6487 12:11:41.348003 DQM0 = 6, DQM1 = 15
6488 12:11:41.348085 DQ Delay:
6489 12:11:41.351377 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6490 12:11:41.354832 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6491 12:11:41.358171 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6492 12:11:41.361000 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6493 12:11:41.361104
6494 12:11:41.361199
6495 12:11:41.361288 ==
6496 12:11:41.364418 Dram Type= 6, Freq= 0, CH_1, rank 0
6497 12:11:41.367590 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6498 12:11:41.367674 ==
6499 12:11:41.367739
6500 12:11:41.367800
6501 12:11:41.371633 TX Vref Scan disable
6502 12:11:41.371715 == TX Byte 0 ==
6503 12:11:41.377938 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6504 12:11:41.381128 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6505 12:11:41.381212 == TX Byte 1 ==
6506 12:11:41.388001 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6507 12:11:41.391132 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6508 12:11:41.391215 ==
6509 12:11:41.394654 Dram Type= 6, Freq= 0, CH_1, rank 0
6510 12:11:41.397724 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6511 12:11:41.397811 ==
6512 12:11:41.400809
6513 12:11:41.400891
6514 12:11:41.400957 TX Vref Scan disable
6515 12:11:41.404596 == TX Byte 0 ==
6516 12:11:41.408047 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6517 12:11:41.411063 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6518 12:11:41.414099 == TX Byte 1 ==
6519 12:11:41.417994 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6520 12:11:41.421536 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6521 12:11:41.421622
6522 12:11:41.424090 [DATLAT]
6523 12:11:41.424172 Freq=400, CH1 RK0
6524 12:11:41.424238
6525 12:11:41.427065 DATLAT Default: 0xf
6526 12:11:41.427147 0, 0xFFFF, sum = 0
6527 12:11:41.431565 1, 0xFFFF, sum = 0
6528 12:11:41.431649 2, 0xFFFF, sum = 0
6529 12:11:41.433879 3, 0xFFFF, sum = 0
6530 12:11:41.433963 4, 0xFFFF, sum = 0
6531 12:11:41.437809 5, 0xFFFF, sum = 0
6532 12:11:41.437893 6, 0xFFFF, sum = 0
6533 12:11:41.440425 7, 0xFFFF, sum = 0
6534 12:11:41.440509 8, 0xFFFF, sum = 0
6535 12:11:41.444537 9, 0xFFFF, sum = 0
6536 12:11:41.444621 10, 0xFFFF, sum = 0
6537 12:11:41.446913 11, 0xFFFF, sum = 0
6538 12:11:41.446997 12, 0x0, sum = 1
6539 12:11:41.450808 13, 0x0, sum = 2
6540 12:11:41.450892 14, 0x0, sum = 3
6541 12:11:41.454099 15, 0x0, sum = 4
6542 12:11:41.454183 best_step = 13
6543 12:11:41.454249
6544 12:11:41.454311 ==
6545 12:11:41.457483 Dram Type= 6, Freq= 0, CH_1, rank 0
6546 12:11:41.464097 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6547 12:11:41.464181 ==
6548 12:11:41.464247 RX Vref Scan: 1
6549 12:11:41.464309
6550 12:11:41.467269 RX Vref 0 -> 0, step: 1
6551 12:11:41.467352
6552 12:11:41.470474 RX Delay -359 -> 252, step: 8
6553 12:11:41.470557
6554 12:11:41.473601 Set Vref, RX VrefLevel [Byte0]: 53
6555 12:11:41.476781 [Byte1]: 50
6556 12:11:41.480188
6557 12:11:41.480273 Final RX Vref Byte 0 = 53 to rank0
6558 12:11:41.483261 Final RX Vref Byte 1 = 50 to rank0
6559 12:11:41.486787 Final RX Vref Byte 0 = 53 to rank1
6560 12:11:41.489714 Final RX Vref Byte 1 = 50 to rank1==
6561 12:11:41.493301 Dram Type= 6, Freq= 0, CH_1, rank 0
6562 12:11:41.500370 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6563 12:11:41.500454 ==
6564 12:11:41.500520 DQS Delay:
6565 12:11:41.503799 DQS0 = 48, DQS1 = 64
6566 12:11:41.503882 DQM Delay:
6567 12:11:41.503948 DQM0 = 8, DQM1 = 15
6568 12:11:41.506403 DQ Delay:
6569 12:11:41.510192 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6570 12:11:41.510275 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6571 12:11:41.513090 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6572 12:11:41.516851 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6573 12:11:41.516934
6574 12:11:41.516999
6575 12:11:41.526269 [DQSOSCAuto] RK0, (LSB)MR18= 0xd9d9, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 383 ps
6576 12:11:41.529940 CH1 RK0: MR19=C0C, MR18=D9D9
6577 12:11:41.536129 CH1_RK0: MR19=0xC0C, MR18=0xD9D9, DQSOSC=383, MR23=63, INC=402, DEC=268
6578 12:11:41.536213 ==
6579 12:11:41.539408 Dram Type= 6, Freq= 0, CH_1, rank 1
6580 12:11:41.543352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6581 12:11:41.543435 ==
6582 12:11:41.546932 [Gating] SW mode calibration
6583 12:11:41.553388 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6584 12:11:41.559662 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6585 12:11:41.562656 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6586 12:11:41.566256 0 7 16 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
6587 12:11:41.572451 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6588 12:11:41.575991 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6589 12:11:41.579903 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6590 12:11:41.585881 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6591 12:11:41.589029 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6592 12:11:41.593719 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6593 12:11:41.595990 Total UI for P1: 0, mck2ui 16
6594 12:11:41.598960 best dqsien dly found for B0: ( 0, 10, 8)
6595 12:11:41.602243 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6596 12:11:41.605732 Total UI for P1: 0, mck2ui 16
6597 12:11:41.609264 best dqsien dly found for B1: ( 0, 10, 16)
6598 12:11:41.612900 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6599 12:11:41.618940 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6600 12:11:41.619023
6601 12:11:41.622404 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6602 12:11:41.625174 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6603 12:11:41.629060 [Gating] SW calibration Done
6604 12:11:41.629143 ==
6605 12:11:41.632465 Dram Type= 6, Freq= 0, CH_1, rank 1
6606 12:11:41.635265 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6607 12:11:41.635349 ==
6608 12:11:41.638888 RX Vref Scan: 0
6609 12:11:41.638971
6610 12:11:41.639037 RX Vref 0 -> 0, step: 1
6611 12:11:41.639098
6612 12:11:41.641595 RX Delay -410 -> 252, step: 16
6613 12:11:41.649186 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6614 12:11:41.652171 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6615 12:11:41.655377 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6616 12:11:41.659122 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6617 12:11:41.666243 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6618 12:11:41.668615 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6619 12:11:41.672066 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6620 12:11:41.674821 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6621 12:11:41.681963 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6622 12:11:41.685432 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6623 12:11:41.688506 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6624 12:11:41.691802 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6625 12:11:41.698627 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6626 12:11:41.701251 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6627 12:11:41.704577 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6628 12:11:41.711186 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6629 12:11:41.711270 ==
6630 12:11:41.714990 Dram Type= 6, Freq= 0, CH_1, rank 1
6631 12:11:41.718053 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6632 12:11:41.718137 ==
6633 12:11:41.718203 DQS Delay:
6634 12:11:41.721601 DQS0 = 43, DQS1 = 59
6635 12:11:41.721684 DQM Delay:
6636 12:11:41.724588 DQM0 = 10, DQM1 = 16
6637 12:11:41.724696 DQ Delay:
6638 12:11:41.728115 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6639 12:11:41.731094 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6640 12:11:41.735003 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6641 12:11:41.737601 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6642 12:11:41.737684
6643 12:11:41.737748
6644 12:11:41.737808 ==
6645 12:11:41.740760 Dram Type= 6, Freq= 0, CH_1, rank 1
6646 12:11:41.744220 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6647 12:11:41.744303 ==
6648 12:11:41.744369
6649 12:11:41.744430
6650 12:11:41.747950 TX Vref Scan disable
6651 12:11:41.748033 == TX Byte 0 ==
6652 12:11:41.754922 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6653 12:11:41.757640 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6654 12:11:41.757723 == TX Byte 1 ==
6655 12:11:41.764680 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6656 12:11:41.767670 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6657 12:11:41.767753 ==
6658 12:11:41.770589 Dram Type= 6, Freq= 0, CH_1, rank 1
6659 12:11:41.774340 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6660 12:11:41.774424 ==
6661 12:11:41.774489
6662 12:11:41.774551
6663 12:11:41.777520 TX Vref Scan disable
6664 12:11:41.777603 == TX Byte 0 ==
6665 12:11:41.784548 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6666 12:11:41.787134 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6667 12:11:41.787218 == TX Byte 1 ==
6668 12:11:41.793582 Update DQ dly =576 (4 ,2, 0) DQ OEN =(3 ,3)
6669 12:11:41.797196 Update DQM dly =576 (4 ,2, 0) DQM OEN =(3 ,3)
6670 12:11:41.797279
6671 12:11:41.797344 [DATLAT]
6672 12:11:41.800491 Freq=400, CH1 RK1
6673 12:11:41.800574
6674 12:11:41.800639 DATLAT Default: 0xd
6675 12:11:41.803675 0, 0xFFFF, sum = 0
6676 12:11:41.803760 1, 0xFFFF, sum = 0
6677 12:11:41.807810 2, 0xFFFF, sum = 0
6678 12:11:41.807894 3, 0xFFFF, sum = 0
6679 12:11:41.811085 4, 0xFFFF, sum = 0
6680 12:11:41.811169 5, 0xFFFF, sum = 0
6681 12:11:41.813521 6, 0xFFFF, sum = 0
6682 12:11:41.817650 7, 0xFFFF, sum = 0
6683 12:11:41.817734 8, 0xFFFF, sum = 0
6684 12:11:41.820656 9, 0xFFFF, sum = 0
6685 12:11:41.820779 10, 0xFFFF, sum = 0
6686 12:11:41.823949 11, 0xFFFF, sum = 0
6687 12:11:41.824033 12, 0x0, sum = 1
6688 12:11:41.827024 13, 0x0, sum = 2
6689 12:11:41.827108 14, 0x0, sum = 3
6690 12:11:41.831117 15, 0x0, sum = 4
6691 12:11:41.831201 best_step = 13
6692 12:11:41.831266
6693 12:11:41.831327 ==
6694 12:11:41.833935 Dram Type= 6, Freq= 0, CH_1, rank 1
6695 12:11:41.836601 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6696 12:11:41.836684 ==
6697 12:11:41.841024 RX Vref Scan: 0
6698 12:11:41.841108
6699 12:11:41.843741 RX Vref 0 -> 0, step: 1
6700 12:11:41.843823
6701 12:11:41.843888 RX Delay -359 -> 252, step: 8
6702 12:11:41.852421 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6703 12:11:41.855555 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6704 12:11:41.859084 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6705 12:11:41.866092 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6706 12:11:41.869258 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6707 12:11:41.872927 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6708 12:11:41.875822 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6709 12:11:41.882412 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6710 12:11:41.885135 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6711 12:11:41.889168 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6712 12:11:41.892271 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6713 12:11:41.899450 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6714 12:11:41.902182 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6715 12:11:41.905564 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6716 12:11:41.908098 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6717 12:11:41.915035 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6718 12:11:41.915118 ==
6719 12:11:41.919532 Dram Type= 6, Freq= 0, CH_1, rank 1
6720 12:11:41.921736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6721 12:11:41.921819 ==
6722 12:11:41.921885 DQS Delay:
6723 12:11:41.925187 DQS0 = 48, DQS1 = 64
6724 12:11:41.925271 DQM Delay:
6725 12:11:41.929065 DQM0 = 9, DQM1 = 15
6726 12:11:41.929149 DQ Delay:
6727 12:11:41.931712 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6728 12:11:41.934881 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
6729 12:11:41.938296 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6730 12:11:41.941250 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6731 12:11:41.941333
6732 12:11:41.941398
6733 12:11:41.947989 [DQSOSCAuto] RK1, (LSB)MR18= 0xb3b3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6734 12:11:41.951373 CH1 RK1: MR19=C0C, MR18=B3B3
6735 12:11:41.958066 CH1_RK1: MR19=0xC0C, MR18=0xB3B3, DQSOSC=387, MR23=63, INC=394, DEC=262
6736 12:11:41.961969 [RxdqsGatingPostProcess] freq 400
6737 12:11:41.967587 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6738 12:11:41.971137 Pre-setting of DQS Precalculation
6739 12:11:41.974880 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6740 12:11:41.981165 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6741 12:11:41.987681 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6742 12:11:41.987764
6743 12:11:41.991450
6744 12:11:41.991532 [Calibration Summary] 800 Mbps
6745 12:11:41.994869 CH 0, Rank 0
6746 12:11:41.994952 SW Impedance : PASS
6747 12:11:41.997870 DUTY Scan : NO K
6748 12:11:42.001004 ZQ Calibration : PASS
6749 12:11:42.001087 Jitter Meter : NO K
6750 12:11:42.004190 CBT Training : PASS
6751 12:11:42.007975 Write leveling : PASS
6752 12:11:42.008058 RX DQS gating : PASS
6753 12:11:42.011332 RX DQ/DQS(RDDQC) : PASS
6754 12:11:42.014401 TX DQ/DQS : PASS
6755 12:11:42.014483 RX DATLAT : PASS
6756 12:11:42.017724 RX DQ/DQS(Engine): PASS
6757 12:11:42.021897 TX OE : NO K
6758 12:11:42.021979 All Pass.
6759 12:11:42.022045
6760 12:11:42.022106 CH 0, Rank 1
6761 12:11:42.024615 SW Impedance : PASS
6762 12:11:42.027923 DUTY Scan : NO K
6763 12:11:42.028006 ZQ Calibration : PASS
6764 12:11:42.030662 Jitter Meter : NO K
6765 12:11:42.030745 CBT Training : PASS
6766 12:11:42.034631 Write leveling : NO K
6767 12:11:42.038372 RX DQS gating : PASS
6768 12:11:42.038455 RX DQ/DQS(RDDQC) : PASS
6769 12:11:42.040678 TX DQ/DQS : PASS
6770 12:11:42.043898 RX DATLAT : PASS
6771 12:11:42.043980 RX DQ/DQS(Engine): PASS
6772 12:11:42.047625 TX OE : NO K
6773 12:11:42.047708 All Pass.
6774 12:11:42.047773
6775 12:11:42.051348 CH 1, Rank 0
6776 12:11:42.051431 SW Impedance : PASS
6777 12:11:42.054165 DUTY Scan : NO K
6778 12:11:42.057349 ZQ Calibration : PASS
6779 12:11:42.057431 Jitter Meter : NO K
6780 12:11:42.060967 CBT Training : PASS
6781 12:11:42.064281 Write leveling : PASS
6782 12:11:42.064364 RX DQS gating : PASS
6783 12:11:42.067327 RX DQ/DQS(RDDQC) : PASS
6784 12:11:42.070697 TX DQ/DQS : PASS
6785 12:11:42.070780 RX DATLAT : PASS
6786 12:11:42.073951 RX DQ/DQS(Engine): PASS
6787 12:11:42.077960 TX OE : NO K
6788 12:11:42.078043 All Pass.
6789 12:11:42.078109
6790 12:11:42.078170 CH 1, Rank 1
6791 12:11:42.080558 SW Impedance : PASS
6792 12:11:42.084413 DUTY Scan : NO K
6793 12:11:42.084496 ZQ Calibration : PASS
6794 12:11:42.087733 Jitter Meter : NO K
6795 12:11:42.091138 CBT Training : PASS
6796 12:11:42.091221 Write leveling : NO K
6797 12:11:42.093862 RX DQS gating : PASS
6798 12:11:42.093945 RX DQ/DQS(RDDQC) : PASS
6799 12:11:42.097671 TX DQ/DQS : PASS
6800 12:11:42.100647 RX DATLAT : PASS
6801 12:11:42.100750 RX DQ/DQS(Engine): PASS
6802 12:11:42.103841 TX OE : NO K
6803 12:11:42.103928 All Pass.
6804 12:11:42.103993
6805 12:11:42.107591 DramC Write-DBI off
6806 12:11:42.110584 PER_BANK_REFRESH: Hybrid Mode
6807 12:11:42.110667 TX_TRACKING: ON
6808 12:11:42.121098 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6809 12:11:42.124158 [FAST_K] Save calibration result to emmc
6810 12:11:42.127876 dramc_set_vcore_voltage set vcore to 725000
6811 12:11:42.131179 Read voltage for 1600, 0
6812 12:11:42.131262 Vio18 = 0
6813 12:11:42.131328 Vcore = 725000
6814 12:11:42.133839 Vdram = 0
6815 12:11:42.133921 Vddq = 0
6816 12:11:42.133987 Vmddr = 0
6817 12:11:42.140209 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6818 12:11:42.146971 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6819 12:11:42.147054 MEM_TYPE=3, freq_sel=13
6820 12:11:42.150078 sv_algorithm_assistance_LP4_3733
6821 12:11:42.153698 ============ PULL DRAM RESETB DOWN ============
6822 12:11:42.160207 ========== PULL DRAM RESETB DOWN end =========
6823 12:11:42.163427 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6824 12:11:42.166804 ===================================
6825 12:11:42.170437 LPDDR4 DRAM CONFIGURATION
6826 12:11:42.173775 ===================================
6827 12:11:42.173858 EX_ROW_EN[0] = 0x0
6828 12:11:42.176410 EX_ROW_EN[1] = 0x0
6829 12:11:42.176492 LP4Y_EN = 0x0
6830 12:11:42.179853 WORK_FSP = 0x1
6831 12:11:42.179935 WL = 0x5
6832 12:11:42.183313 RL = 0x5
6833 12:11:42.186518 BL = 0x2
6834 12:11:42.186601 RPST = 0x0
6835 12:11:42.190204 RD_PRE = 0x0
6836 12:11:42.190286 WR_PRE = 0x1
6837 12:11:42.192649 WR_PST = 0x1
6838 12:11:42.192741 DBI_WR = 0x0
6839 12:11:42.196473 DBI_RD = 0x0
6840 12:11:42.196555 OTF = 0x1
6841 12:11:42.199803 ===================================
6842 12:11:42.202839 ===================================
6843 12:11:42.206307 ANA top config
6844 12:11:42.210634 ===================================
6845 12:11:42.210717 DLL_ASYNC_EN = 0
6846 12:11:42.212893 ALL_SLAVE_EN = 0
6847 12:11:42.216660 NEW_RANK_MODE = 1
6848 12:11:42.219346 DLL_IDLE_MODE = 1
6849 12:11:42.219429 LP45_APHY_COMB_EN = 1
6850 12:11:42.222737 TX_ODT_DIS = 0
6851 12:11:42.226389 NEW_8X_MODE = 1
6852 12:11:42.229655 ===================================
6853 12:11:42.232607 ===================================
6854 12:11:42.235803 data_rate = 3200
6855 12:11:42.239549 CKR = 1
6856 12:11:42.242987 DQ_P2S_RATIO = 8
6857 12:11:42.246440 ===================================
6858 12:11:42.246523 CA_P2S_RATIO = 8
6859 12:11:42.249608 DQ_CA_OPEN = 0
6860 12:11:42.252200 DQ_SEMI_OPEN = 0
6861 12:11:42.255588 CA_SEMI_OPEN = 0
6862 12:11:42.259144 CA_FULL_RATE = 0
6863 12:11:42.262086 DQ_CKDIV4_EN = 0
6864 12:11:42.262169 CA_CKDIV4_EN = 0
6865 12:11:42.266141 CA_PREDIV_EN = 0
6866 12:11:42.269058 PH8_DLY = 12
6867 12:11:42.272242 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6868 12:11:42.275666 DQ_AAMCK_DIV = 4
6869 12:11:42.279083 CA_AAMCK_DIV = 4
6870 12:11:42.279166 CA_ADMCK_DIV = 4
6871 12:11:42.282146 DQ_TRACK_CA_EN = 0
6872 12:11:42.285288 CA_PICK = 1600
6873 12:11:42.289258 CA_MCKIO = 1600
6874 12:11:42.292106 MCKIO_SEMI = 0
6875 12:11:42.295346 PLL_FREQ = 3068
6876 12:11:42.298671 DQ_UI_PI_RATIO = 32
6877 12:11:42.302361 CA_UI_PI_RATIO = 0
6878 12:11:42.305129 ===================================
6879 12:11:42.308939 ===================================
6880 12:11:42.309022 memory_type:LPDDR4
6881 12:11:42.313350 GP_NUM : 10
6882 12:11:42.315291 SRAM_EN : 1
6883 12:11:42.315373 MD32_EN : 0
6884 12:11:42.318729 ===================================
6885 12:11:42.321607 [ANA_INIT] >>>>>>>>>>>>>>
6886 12:11:42.325683 <<<<<< [CONFIGURE PHASE]: ANA_TX
6887 12:11:42.328748 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6888 12:11:42.331611 ===================================
6889 12:11:42.335428 data_rate = 3200,PCW = 0X7600
6890 12:11:42.338252 ===================================
6891 12:11:42.341985 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6892 12:11:42.345368 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6893 12:11:42.351473 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6894 12:11:42.355277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6895 12:11:42.357946 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6896 12:11:42.361950 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6897 12:11:42.364870 [ANA_INIT] flow start
6898 12:11:42.368581 [ANA_INIT] PLL >>>>>>>>
6899 12:11:42.368684 [ANA_INIT] PLL <<<<<<<<
6900 12:11:42.371251 [ANA_INIT] MIDPI >>>>>>>>
6901 12:11:42.374593 [ANA_INIT] MIDPI <<<<<<<<
6902 12:11:42.377797 [ANA_INIT] DLL >>>>>>>>
6903 12:11:42.377874 [ANA_INIT] DLL <<<<<<<<
6904 12:11:42.381286 [ANA_INIT] flow end
6905 12:11:42.384464 ============ LP4 DIFF to SE enter ============
6906 12:11:42.388327 ============ LP4 DIFF to SE exit ============
6907 12:11:42.392067 [ANA_INIT] <<<<<<<<<<<<<
6908 12:11:42.394277 [Flow] Enable top DCM control >>>>>
6909 12:11:42.397738 [Flow] Enable top DCM control <<<<<
6910 12:11:42.401113 Enable DLL master slave shuffle
6911 12:11:42.407553 ==============================================================
6912 12:11:42.407656 Gating Mode config
6913 12:11:42.414375 ==============================================================
6914 12:11:42.414480 Config description:
6915 12:11:42.425317 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6916 12:11:42.431170 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6917 12:11:42.437650 SELPH_MODE 0: By rank 1: By Phase
6918 12:11:42.440898 ==============================================================
6919 12:11:42.444173 GAT_TRACK_EN = 1
6920 12:11:42.447171 RX_GATING_MODE = 2
6921 12:11:42.450538 RX_GATING_TRACK_MODE = 2
6922 12:11:42.454301 SELPH_MODE = 1
6923 12:11:42.457372 PICG_EARLY_EN = 1
6924 12:11:42.460540 VALID_LAT_VALUE = 1
6925 12:11:42.467733 ==============================================================
6926 12:11:42.470402 Enter into Gating configuration >>>>
6927 12:11:42.473603 Exit from Gating configuration <<<<
6928 12:11:42.477301 Enter into DVFS_PRE_config >>>>>
6929 12:11:42.487291 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6930 12:11:42.490832 Exit from DVFS_PRE_config <<<<<
6931 12:11:42.493887 Enter into PICG configuration >>>>
6932 12:11:42.497833 Exit from PICG configuration <<<<
6933 12:11:42.500416 [RX_INPUT] configuration >>>>>
6934 12:11:42.500499 [RX_INPUT] configuration <<<<<
6935 12:11:42.507334 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6936 12:11:42.513802 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6937 12:11:42.520345 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6938 12:11:42.523703 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6939 12:11:42.531067 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6940 12:11:42.536382 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6941 12:11:42.539731 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6942 12:11:42.542925 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6943 12:11:42.549531 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6944 12:11:42.553679 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6945 12:11:42.556234 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6946 12:11:42.562519 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6947 12:11:42.566317 ===================================
6948 12:11:42.566400 LPDDR4 DRAM CONFIGURATION
6949 12:11:42.570133 ===================================
6950 12:11:42.573305 EX_ROW_EN[0] = 0x0
6951 12:11:42.575866 EX_ROW_EN[1] = 0x0
6952 12:11:42.575949 LP4Y_EN = 0x0
6953 12:11:42.579939 WORK_FSP = 0x1
6954 12:11:42.580022 WL = 0x5
6955 12:11:42.582753 RL = 0x5
6956 12:11:42.582836 BL = 0x2
6957 12:11:42.586806 RPST = 0x0
6958 12:11:42.586888 RD_PRE = 0x0
6959 12:11:42.589812 WR_PRE = 0x1
6960 12:11:42.589894 WR_PST = 0x1
6961 12:11:42.592329 DBI_WR = 0x0
6962 12:11:42.592411 DBI_RD = 0x0
6963 12:11:42.595800 OTF = 0x1
6964 12:11:42.599744 ===================================
6965 12:11:42.602766 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6966 12:11:42.605661 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6967 12:11:42.612066 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6968 12:11:42.616432 ===================================
6969 12:11:42.616515 LPDDR4 DRAM CONFIGURATION
6970 12:11:42.618971 ===================================
6971 12:11:42.622934 EX_ROW_EN[0] = 0x10
6972 12:11:42.625928 EX_ROW_EN[1] = 0x0
6973 12:11:42.626011 LP4Y_EN = 0x0
6974 12:11:42.629151 WORK_FSP = 0x1
6975 12:11:42.629234 WL = 0x5
6976 12:11:42.631973 RL = 0x5
6977 12:11:42.632081 BL = 0x2
6978 12:11:42.635552 RPST = 0x0
6979 12:11:42.635635 RD_PRE = 0x0
6980 12:11:42.638792 WR_PRE = 0x1
6981 12:11:42.638875 WR_PST = 0x1
6982 12:11:42.642264 DBI_WR = 0x0
6983 12:11:42.642347 DBI_RD = 0x0
6984 12:11:42.646221 OTF = 0x1
6985 12:11:42.650040 ===================================
6986 12:11:42.655746 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6987 12:11:42.655830 ==
6988 12:11:42.658767 Dram Type= 6, Freq= 0, CH_0, rank 0
6989 12:11:42.662301 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6990 12:11:42.662385 ==
6991 12:11:42.665725 [Duty_Offset_Calibration]
6992 12:11:42.665864 B0:0 B1:2 CA:1
6993 12:11:42.665976
6994 12:11:42.668443 [DutyScan_Calibration_Flow] k_type=0
6995 12:11:42.679414
6996 12:11:42.679497 ==CLK 0==
6997 12:11:42.682230 Final CLK duty delay cell = 0
6998 12:11:42.685572 [0] MAX Duty = 5156%(X100), DQS PI = 22
6999 12:11:42.688671 [0] MIN Duty = 4938%(X100), DQS PI = 54
7000 12:11:42.692151 [0] AVG Duty = 5047%(X100)
7001 12:11:42.692248
7002 12:11:42.695621 CH0 CLK Duty spec in!! Max-Min= 218%
7003 12:11:42.699116 [DutyScan_Calibration_Flow] ====Done====
7004 12:11:42.699199
7005 12:11:42.701893 [DutyScan_Calibration_Flow] k_type=1
7006 12:11:42.719966
7007 12:11:42.720063 ==DQS 0 ==
7008 12:11:42.722108 Final DQS duty delay cell = 0
7009 12:11:42.725925 [0] MAX Duty = 5125%(X100), DQS PI = 22
7010 12:11:42.729322 [0] MIN Duty = 5031%(X100), DQS PI = 8
7011 12:11:42.729405 [0] AVG Duty = 5078%(X100)
7012 12:11:42.732236
7013 12:11:42.732319 ==DQS 1 ==
7014 12:11:42.735997 Final DQS duty delay cell = 0
7015 12:11:42.739580 [0] MAX Duty = 5031%(X100), DQS PI = 6
7016 12:11:42.742173 [0] MIN Duty = 4876%(X100), DQS PI = 16
7017 12:11:42.742256 [0] AVG Duty = 4953%(X100)
7018 12:11:42.746058
7019 12:11:42.749335 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7020 12:11:42.749418
7021 12:11:42.752588 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7022 12:11:42.755572 [DutyScan_Calibration_Flow] ====Done====
7023 12:11:42.755654
7024 12:11:42.758737 [DutyScan_Calibration_Flow] k_type=3
7025 12:11:42.775962
7026 12:11:42.776045 ==DQM 0 ==
7027 12:11:42.779407 Final DQM duty delay cell = 0
7028 12:11:42.783190 [0] MAX Duty = 5187%(X100), DQS PI = 24
7029 12:11:42.786133 [0] MIN Duty = 4907%(X100), DQS PI = 56
7030 12:11:42.789532 [0] AVG Duty = 5047%(X100)
7031 12:11:42.789616
7032 12:11:42.789682 ==DQM 1 ==
7033 12:11:42.792559 Final DQM duty delay cell = 0
7034 12:11:42.795920 [0] MAX Duty = 5000%(X100), DQS PI = 2
7035 12:11:42.798952 [0] MIN Duty = 4782%(X100), DQS PI = 14
7036 12:11:42.802817 [0] AVG Duty = 4891%(X100)
7037 12:11:42.802900
7038 12:11:42.805781 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7039 12:11:42.805864
7040 12:11:42.808936 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7041 12:11:42.812386 [DutyScan_Calibration_Flow] ====Done====
7042 12:11:42.812469
7043 12:11:42.815847 [DutyScan_Calibration_Flow] k_type=2
7044 12:11:42.832070
7045 12:11:42.832177 ==DQ 0 ==
7046 12:11:42.835660 Final DQ duty delay cell = 0
7047 12:11:42.838828 [0] MAX Duty = 5218%(X100), DQS PI = 18
7048 12:11:42.843024 [0] MIN Duty = 4938%(X100), DQS PI = 54
7049 12:11:42.843107 [0] AVG Duty = 5078%(X100)
7050 12:11:42.846193
7051 12:11:42.846275 ==DQ 1 ==
7052 12:11:42.849309 Final DQ duty delay cell = -4
7053 12:11:42.852281 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7054 12:11:42.855906 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7055 12:11:42.858942 [-4] AVG Duty = 4953%(X100)
7056 12:11:42.859028
7057 12:11:42.862253 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7058 12:11:42.862336
7059 12:11:42.865712 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7060 12:11:42.869039 [DutyScan_Calibration_Flow] ====Done====
7061 12:11:42.869122 ==
7062 12:11:42.872273 Dram Type= 6, Freq= 0, CH_1, rank 0
7063 12:11:42.875537 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7064 12:11:42.875626 ==
7065 12:11:42.878937 [Duty_Offset_Calibration]
7066 12:11:42.879020 B0:0 B1:4 CA:-5
7067 12:11:42.879086
7068 12:11:42.882268 [DutyScan_Calibration_Flow] k_type=0
7069 12:11:42.892904
7070 12:11:42.893007 ==CLK 0==
7071 12:11:42.896541 Final CLK duty delay cell = 0
7072 12:11:42.899217 [0] MAX Duty = 5156%(X100), DQS PI = 20
7073 12:11:42.903132 [0] MIN Duty = 4906%(X100), DQS PI = 50
7074 12:11:42.906113 [0] AVG Duty = 5031%(X100)
7075 12:11:42.906196
7076 12:11:42.909855 CH1 CLK Duty spec in!! Max-Min= 250%
7077 12:11:42.912911 [DutyScan_Calibration_Flow] ====Done====
7078 12:11:42.912994
7079 12:11:42.915866 [DutyScan_Calibration_Flow] k_type=1
7080 12:11:42.931984
7081 12:11:42.932067 ==DQS 0 ==
7082 12:11:42.935040 Final DQS duty delay cell = 0
7083 12:11:42.938543 [0] MAX Duty = 5187%(X100), DQS PI = 20
7084 12:11:42.941930 [0] MIN Duty = 4876%(X100), DQS PI = 42
7085 12:11:42.942013 [0] AVG Duty = 5031%(X100)
7086 12:11:42.945571
7087 12:11:42.945654 ==DQS 1 ==
7088 12:11:42.948946 Final DQS duty delay cell = -4
7089 12:11:42.952313 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7090 12:11:42.955120 [-4] MIN Duty = 4875%(X100), DQS PI = 38
7091 12:11:42.958475 [-4] AVG Duty = 4937%(X100)
7092 12:11:42.958583
7093 12:11:42.961881 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7094 12:11:42.961964
7095 12:11:42.965057 CH1 DQS 1 Duty spec in!! Max-Min= 125%
7096 12:11:42.968357 [DutyScan_Calibration_Flow] ====Done====
7097 12:11:42.968439
7098 12:11:42.971451 [DutyScan_Calibration_Flow] k_type=3
7099 12:11:42.988234
7100 12:11:42.988317 ==DQM 0 ==
7101 12:11:42.990824 Final DQM duty delay cell = -4
7102 12:11:42.994277 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7103 12:11:42.997255 [-4] MIN Duty = 4782%(X100), DQS PI = 44
7104 12:11:43.000762 [-4] AVG Duty = 4937%(X100)
7105 12:11:43.000845
7106 12:11:43.000911 ==DQM 1 ==
7107 12:11:43.004580 Final DQM duty delay cell = -4
7108 12:11:43.007050 [-4] MAX Duty = 5062%(X100), DQS PI = 2
7109 12:11:43.010973 [-4] MIN Duty = 4907%(X100), DQS PI = 36
7110 12:11:43.013658 [-4] AVG Duty = 4984%(X100)
7111 12:11:43.013741
7112 12:11:43.017081 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7113 12:11:43.017165
7114 12:11:43.020411 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7115 12:11:43.023934 [DutyScan_Calibration_Flow] ====Done====
7116 12:11:43.024016
7117 12:11:43.027377 [DutyScan_Calibration_Flow] k_type=2
7118 12:11:43.044954
7119 12:11:43.045036 ==DQ 0 ==
7120 12:11:43.048046 Final DQ duty delay cell = 0
7121 12:11:43.051462 [0] MAX Duty = 5093%(X100), DQS PI = 34
7122 12:11:43.055055 [0] MIN Duty = 4938%(X100), DQS PI = 46
7123 12:11:43.055138 [0] AVG Duty = 5015%(X100)
7124 12:11:43.058022
7125 12:11:43.058104 ==DQ 1 ==
7126 12:11:43.061849 Final DQ duty delay cell = 0
7127 12:11:43.064885 [0] MAX Duty = 5031%(X100), DQS PI = 2
7128 12:11:43.068099 [0] MIN Duty = 4876%(X100), DQS PI = 28
7129 12:11:43.068182 [0] AVG Duty = 4953%(X100)
7130 12:11:43.071729
7131 12:11:43.074832 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7132 12:11:43.074915
7133 12:11:43.077702 CH1 DQ 1 Duty spec in!! Max-Min= 155%
7134 12:11:43.081445 [DutyScan_Calibration_Flow] ====Done====
7135 12:11:43.084916 nWR fixed to 30
7136 12:11:43.085000 [ModeRegInit_LP4] CH0 RK0
7137 12:11:43.088107 [ModeRegInit_LP4] CH0 RK1
7138 12:11:43.091434 [ModeRegInit_LP4] CH1 RK0
7139 12:11:43.095035 [ModeRegInit_LP4] CH1 RK1
7140 12:11:43.095118 match AC timing 4
7141 12:11:43.100801 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7142 12:11:43.104675 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7143 12:11:43.108025 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7144 12:11:43.114625 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7145 12:11:43.117741 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7146 12:11:43.117825 [MiockJmeterHQA]
7147 12:11:43.117891
7148 12:11:43.121060 [DramcMiockJmeter] u1RxGatingPI = 0
7149 12:11:43.124549 0 : 4255, 4027
7150 12:11:43.124633 4 : 4253, 4026
7151 12:11:43.128305 8 : 4363, 4138
7152 12:11:43.128389 12 : 4253, 4026
7153 12:11:43.128456 16 : 4252, 4027
7154 12:11:43.131284 20 : 4363, 4137
7155 12:11:43.131368 24 : 4252, 4027
7156 12:11:43.134042 28 : 4252, 4027
7157 12:11:43.134127 32 : 4253, 4027
7158 12:11:43.137152 36 : 4252, 4027
7159 12:11:43.137236 40 : 4366, 4140
7160 12:11:43.140655 44 : 4255, 4030
7161 12:11:43.140777 48 : 4252, 4029
7162 12:11:43.140845 52 : 4253, 4027
7163 12:11:43.144051 56 : 4253, 4027
7164 12:11:43.144135 60 : 4250, 4026
7165 12:11:43.147393 64 : 4252, 4027
7166 12:11:43.147477 68 : 4253, 4029
7167 12:11:43.151030 72 : 4250, 4026
7168 12:11:43.151115 76 : 4363, 4140
7169 12:11:43.154305 80 : 4363, 4139
7170 12:11:43.154389 84 : 4250, 4027
7171 12:11:43.154456 88 : 4250, 4027
7172 12:11:43.157246 92 : 4250, 4026
7173 12:11:43.157331 96 : 4252, 4030
7174 12:11:43.160636 100 : 4363, 2322
7175 12:11:43.160758 104 : 4360, 0
7176 12:11:43.163850 108 : 4250, 0
7177 12:11:43.163934 112 : 4250, 0
7178 12:11:43.164002 116 : 4361, 0
7179 12:11:43.167143 120 : 4360, 0
7180 12:11:43.167227 124 : 4247, 0
7181 12:11:43.170740 128 : 4361, 0
7182 12:11:43.170824 132 : 4250, 0
7183 12:11:43.170892 136 : 4255, 0
7184 12:11:43.173850 140 : 4255, 0
7185 12:11:43.173934 144 : 4250, 0
7186 12:11:43.174000 148 : 4250, 0
7187 12:11:43.177818 152 : 4253, 0
7188 12:11:43.177902 156 : 4250, 0
7189 12:11:43.180626 160 : 4250, 0
7190 12:11:43.180716 164 : 4255, 0
7191 12:11:43.180817 168 : 4252, 0
7192 12:11:43.183864 172 : 4360, 0
7193 12:11:43.183947 176 : 4253, 0
7194 12:11:43.188239 180 : 4255, 0
7195 12:11:43.188323 184 : 4360, 0
7196 12:11:43.188391 188 : 4250, 0
7197 12:11:43.190186 192 : 4250, 0
7198 12:11:43.190270 196 : 4250, 0
7199 12:11:43.193932 200 : 4365, 0
7200 12:11:43.194016 204 : 4250, 0
7201 12:11:43.194084 208 : 4250, 0
7202 12:11:43.197302 212 : 4250, 0
7203 12:11:43.197386 216 : 4253, 0
7204 12:11:43.200245 220 : 4250, 805
7205 12:11:43.200328 224 : 4250, 4007
7206 12:11:43.203793 228 : 4250, 4027
7207 12:11:43.203877 232 : 4250, 4027
7208 12:11:43.203945 236 : 4252, 4029
7209 12:11:43.207231 240 : 4253, 4029
7210 12:11:43.207316 244 : 4250, 4026
7211 12:11:43.210508 248 : 4360, 4137
7212 12:11:43.210592 252 : 4250, 4027
7213 12:11:43.214259 256 : 4250, 4027
7214 12:11:43.214343 260 : 4250, 4026
7215 12:11:43.217013 264 : 4250, 4027
7216 12:11:43.217097 268 : 4250, 4026
7217 12:11:43.220425 272 : 4250, 4027
7218 12:11:43.220510 276 : 4252, 4029
7219 12:11:43.223306 280 : 4253, 4030
7220 12:11:43.223391 284 : 4250, 4026
7221 12:11:43.226491 288 : 4250, 4027
7222 12:11:43.226576 292 : 4250, 4027
7223 12:11:43.229769 296 : 4252, 4030
7224 12:11:43.229853 300 : 4250, 4027
7225 12:11:43.229920 304 : 4250, 4026
7226 12:11:43.233606 308 : 4250, 4027
7227 12:11:43.233691 312 : 4361, 4138
7228 12:11:43.236830 316 : 4252, 4029
7229 12:11:43.236933 320 : 4360, 4137
7230 12:11:43.239928 324 : 4250, 4027
7231 12:11:43.240012 328 : 4360, 4137
7232 12:11:43.243070 332 : 4250, 4026
7233 12:11:43.243153 336 : 4255, 3592
7234 12:11:43.246736 340 : 4250, 1958
7235 12:11:43.246820
7236 12:11:43.246887 MIOCK jitter meter ch=0
7237 12:11:43.246949
7238 12:11:43.249771 1T = (340-104) = 236 dly cells
7239 12:11:43.256253 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7240 12:11:43.256337 ==
7241 12:11:43.259721 Dram Type= 6, Freq= 0, CH_0, rank 0
7242 12:11:43.262921 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7243 12:11:43.263041 ==
7244 12:11:43.269536 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7245 12:11:43.273008 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7246 12:11:43.280367 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7247 12:11:43.283229 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7248 12:11:43.292364 [CA 0] Center 42 (12~72) winsize 61
7249 12:11:43.295529 [CA 1] Center 41 (11~72) winsize 62
7250 12:11:43.299876 [CA 2] Center 37 (7~68) winsize 62
7251 12:11:43.302579 [CA 3] Center 37 (7~67) winsize 61
7252 12:11:43.305775 [CA 4] Center 35 (5~66) winsize 62
7253 12:11:43.308831 [CA 5] Center 35 (5~65) winsize 61
7254 12:11:43.308915
7255 12:11:43.312288 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7256 12:11:43.312371
7257 12:11:43.315442 [CATrainingPosCal] consider 1 rank data
7258 12:11:43.318928 u2DelayCellTimex100 = 275/100 ps
7259 12:11:43.322189 CA0 delay=42 (12~72),Diff = 7 PI (24 cell)
7260 12:11:43.329308 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7261 12:11:43.332176 CA2 delay=37 (7~68),Diff = 2 PI (7 cell)
7262 12:11:43.335560 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7263 12:11:43.338649 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
7264 12:11:43.341755 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7265 12:11:43.341838
7266 12:11:43.345522 CA PerBit enable=1, Macro0, CA PI delay=35
7267 12:11:43.345606
7268 12:11:43.349355 [CBTSetCACLKResult] CA Dly = 35
7269 12:11:43.352519 CS Dly: 11 (0~42)
7270 12:11:43.355748 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7271 12:11:43.358320 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7272 12:11:43.358404 ==
7273 12:11:43.361884 Dram Type= 6, Freq= 0, CH_0, rank 1
7274 12:11:43.365961 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7275 12:11:43.368398 ==
7276 12:11:43.371881 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7277 12:11:43.375131 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7278 12:11:43.381842 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7279 12:11:43.385567 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7280 12:11:43.395078 [CA 0] Center 42 (12~73) winsize 62
7281 12:11:43.398268 [CA 1] Center 41 (11~72) winsize 62
7282 12:11:43.402269 [CA 2] Center 38 (8~68) winsize 61
7283 12:11:43.405218 [CA 3] Center 37 (7~67) winsize 61
7284 12:11:43.408203 [CA 4] Center 35 (5~65) winsize 61
7285 12:11:43.411184 [CA 5] Center 35 (5~66) winsize 62
7286 12:11:43.411268
7287 12:11:43.414870 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7288 12:11:43.414954
7289 12:11:43.417911 [CATrainingPosCal] consider 2 rank data
7290 12:11:43.420832 u2DelayCellTimex100 = 275/100 ps
7291 12:11:43.427913 CA0 delay=42 (12~72),Diff = 7 PI (24 cell)
7292 12:11:43.431442 CA1 delay=41 (11~72),Diff = 6 PI (21 cell)
7293 12:11:43.434118 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7294 12:11:43.437557 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7295 12:11:43.440893 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
7296 12:11:43.444047 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7297 12:11:43.444128
7298 12:11:43.447707 CA PerBit enable=1, Macro0, CA PI delay=35
7299 12:11:43.447789
7300 12:11:43.451598 [CBTSetCACLKResult] CA Dly = 35
7301 12:11:43.454494 CS Dly: 11 (0~43)
7302 12:11:43.457595 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7303 12:11:43.460919 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7304 12:11:43.461001
7305 12:11:43.464607 ----->DramcWriteLeveling(PI) begin...
7306 12:11:43.464690 ==
7307 12:11:43.468298 Dram Type= 6, Freq= 0, CH_0, rank 0
7308 12:11:43.473972 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7309 12:11:43.474055 ==
7310 12:11:43.477257 Write leveling (Byte 0): 30 => 30
7311 12:11:43.480996 Write leveling (Byte 1): 27 => 27
7312 12:11:43.481079 DramcWriteLeveling(PI) end<-----
7313 12:11:43.481145
7314 12:11:43.484258 ==
7315 12:11:43.487411 Dram Type= 6, Freq= 0, CH_0, rank 0
7316 12:11:43.490419 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7317 12:11:43.490501 ==
7318 12:11:43.493747 [Gating] SW mode calibration
7319 12:11:43.500486 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7320 12:11:43.503891 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7321 12:11:43.510293 0 12 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7322 12:11:43.514186 0 12 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
7323 12:11:43.516665 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7324 12:11:43.524017 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7325 12:11:43.526982 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7326 12:11:43.530561 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7327 12:11:43.536857 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7328 12:11:43.540261 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7329 12:11:43.543468 0 13 0 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
7330 12:11:43.550306 0 13 4 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (1 0)
7331 12:11:43.553818 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7332 12:11:43.556280 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7333 12:11:43.563687 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7334 12:11:43.566627 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7335 12:11:43.569359 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7336 12:11:43.576523 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7337 12:11:43.579934 0 14 0 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7338 12:11:43.583214 0 14 4 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
7339 12:11:43.589871 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7340 12:11:43.592873 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7341 12:11:43.596141 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7342 12:11:43.603316 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7343 12:11:43.605775 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7344 12:11:43.609721 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7345 12:11:43.615648 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7346 12:11:43.619011 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7347 12:11:43.622819 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7348 12:11:43.628846 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7349 12:11:43.633024 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7350 12:11:43.635646 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7351 12:11:43.642729 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7352 12:11:43.645550 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7353 12:11:43.649020 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7354 12:11:43.655263 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7355 12:11:43.658422 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7356 12:11:43.662061 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7357 12:11:43.668701 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7358 12:11:43.672029 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7359 12:11:43.675583 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7360 12:11:43.681690 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7361 12:11:43.685374 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7362 12:11:43.688655 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7363 12:11:43.691682 Total UI for P1: 0, mck2ui 16
7364 12:11:43.695303 best dqsien dly found for B0: ( 1, 0, 30)
7365 12:11:43.701976 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7366 12:11:43.702060 Total UI for P1: 0, mck2ui 16
7367 12:11:43.708368 best dqsien dly found for B1: ( 1, 1, 4)
7368 12:11:43.711466 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7369 12:11:43.714959 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7370 12:11:43.715041
7371 12:11:43.718035 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7372 12:11:43.721283 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7373 12:11:43.724741 [Gating] SW calibration Done
7374 12:11:43.724838 ==
7375 12:11:43.728526 Dram Type= 6, Freq= 0, CH_0, rank 0
7376 12:11:43.731420 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7377 12:11:43.731503 ==
7378 12:11:43.734628 RX Vref Scan: 0
7379 12:11:43.734711
7380 12:11:43.734781 RX Vref 0 -> 0, step: 1
7381 12:11:43.737914
7382 12:11:43.738029 RX Delay 0 -> 252, step: 8
7383 12:11:43.741091 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7384 12:11:43.748578 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7385 12:11:43.751020 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7386 12:11:43.754535 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7387 12:11:43.757557 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7388 12:11:43.761163 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7389 12:11:43.767339 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7390 12:11:43.771340 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7391 12:11:43.774114 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7392 12:11:43.778312 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7393 12:11:43.781529 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7394 12:11:43.787578 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7395 12:11:43.790492 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7396 12:11:43.794286 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7397 12:11:43.797211 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7398 12:11:43.803531 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7399 12:11:43.803615 ==
7400 12:11:43.807353 Dram Type= 6, Freq= 0, CH_0, rank 0
7401 12:11:43.810416 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7402 12:11:43.810500 ==
7403 12:11:43.810566 DQS Delay:
7404 12:11:43.814532 DQS0 = 0, DQS1 = 0
7405 12:11:43.814614 DQM Delay:
7406 12:11:43.817519 DQM0 = 130, DQM1 = 124
7407 12:11:43.817601 DQ Delay:
7408 12:11:43.820632 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7409 12:11:43.824158 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7410 12:11:43.827296 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7411 12:11:43.830243 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7412 12:11:43.833705
7413 12:11:43.833788
7414 12:11:43.833854 ==
7415 12:11:43.837053 Dram Type= 6, Freq= 0, CH_0, rank 0
7416 12:11:43.841003 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7417 12:11:43.841087 ==
7418 12:11:43.841153
7419 12:11:43.841214
7420 12:11:43.844197 TX Vref Scan disable
7421 12:11:43.844280 == TX Byte 0 ==
7422 12:11:43.850236 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7423 12:11:43.853479 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7424 12:11:43.853563 == TX Byte 1 ==
7425 12:11:43.860538 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7426 12:11:43.864475 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7427 12:11:43.864560 ==
7428 12:11:43.866625 Dram Type= 6, Freq= 0, CH_0, rank 0
7429 12:11:43.870230 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7430 12:11:43.870314 ==
7431 12:11:43.884926
7432 12:11:43.887955 TX Vref early break, caculate TX vref
7433 12:11:43.891836 TX Vref=16, minBit 9, minWin=21, winSum=372
7434 12:11:43.895335 TX Vref=18, minBit 8, minWin=22, winSum=380
7435 12:11:43.898266 TX Vref=20, minBit 8, minWin=23, winSum=390
7436 12:11:43.901425 TX Vref=22, minBit 8, minWin=24, winSum=395
7437 12:11:43.904613 TX Vref=24, minBit 8, minWin=23, winSum=407
7438 12:11:43.911044 TX Vref=26, minBit 7, minWin=24, winSum=411
7439 12:11:43.914758 TX Vref=28, minBit 8, minWin=24, winSum=411
7440 12:11:43.917561 TX Vref=30, minBit 6, minWin=24, winSum=411
7441 12:11:43.920764 TX Vref=32, minBit 1, minWin=24, winSum=401
7442 12:11:43.924671 TX Vref=34, minBit 6, minWin=23, winSum=392
7443 12:11:43.927757 TX Vref=36, minBit 0, minWin=23, winSum=384
7444 12:11:43.934183 [TxChooseVref] Worse bit 7, Min win 24, Win sum 411, Final Vref 26
7445 12:11:43.934266
7446 12:11:43.937750 Final TX Range 0 Vref 26
7447 12:11:43.937833
7448 12:11:43.937898 ==
7449 12:11:43.940994 Dram Type= 6, Freq= 0, CH_0, rank 0
7450 12:11:43.944424 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7451 12:11:43.944507 ==
7452 12:11:43.944573
7453 12:11:43.948172
7454 12:11:43.948255 TX Vref Scan disable
7455 12:11:43.954291 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7456 12:11:43.954374 == TX Byte 0 ==
7457 12:11:43.957276 u2DelayCellOfst[0]=14 cells (4 PI)
7458 12:11:43.961621 u2DelayCellOfst[1]=21 cells (6 PI)
7459 12:11:43.964872 u2DelayCellOfst[2]=17 cells (5 PI)
7460 12:11:43.967157 u2DelayCellOfst[3]=14 cells (4 PI)
7461 12:11:43.970970 u2DelayCellOfst[4]=10 cells (3 PI)
7462 12:11:43.975075 u2DelayCellOfst[5]=0 cells (0 PI)
7463 12:11:43.978523 u2DelayCellOfst[6]=21 cells (6 PI)
7464 12:11:43.981422 u2DelayCellOfst[7]=21 cells (6 PI)
7465 12:11:43.984803 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7466 12:11:43.987215 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7467 12:11:43.991348 == TX Byte 1 ==
7468 12:11:43.994110 u2DelayCellOfst[8]=3 cells (1 PI)
7469 12:11:43.997774 u2DelayCellOfst[9]=0 cells (0 PI)
7470 12:11:44.001020 u2DelayCellOfst[10]=14 cells (4 PI)
7471 12:11:44.004204 u2DelayCellOfst[11]=7 cells (2 PI)
7472 12:11:44.004287 u2DelayCellOfst[12]=17 cells (5 PI)
7473 12:11:44.007485 u2DelayCellOfst[13]=17 cells (5 PI)
7474 12:11:44.010152 u2DelayCellOfst[14]=17 cells (5 PI)
7475 12:11:44.013458 u2DelayCellOfst[15]=17 cells (5 PI)
7476 12:11:44.020374 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7477 12:11:44.023714 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7478 12:11:44.023798 DramC Write-DBI on
7479 12:11:44.026741 ==
7480 12:11:44.026824 Dram Type= 6, Freq= 0, CH_0, rank 0
7481 12:11:44.034169 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7482 12:11:44.034253 ==
7483 12:11:44.034319
7484 12:11:44.034380
7485 12:11:44.036812 TX Vref Scan disable
7486 12:11:44.036895 == TX Byte 0 ==
7487 12:11:44.043759 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7488 12:11:44.043843 == TX Byte 1 ==
7489 12:11:44.046431 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7490 12:11:44.050690 DramC Write-DBI off
7491 12:11:44.050773
7492 12:11:44.050839 [DATLAT]
7493 12:11:44.053191 Freq=1600, CH0 RK0
7494 12:11:44.053273
7495 12:11:44.053339 DATLAT Default: 0xf
7496 12:11:44.056509 0, 0xFFFF, sum = 0
7497 12:11:44.056594 1, 0xFFFF, sum = 0
7498 12:11:44.060047 2, 0xFFFF, sum = 0
7499 12:11:44.060131 3, 0xFFFF, sum = 0
7500 12:11:44.063497 4, 0xFFFF, sum = 0
7501 12:11:44.063582 5, 0xFFFF, sum = 0
7502 12:11:44.066825 6, 0xFFFF, sum = 0
7503 12:11:44.066909 7, 0xFFFF, sum = 0
7504 12:11:44.070238 8, 0xFFFF, sum = 0
7505 12:11:44.070322 9, 0xFFFF, sum = 0
7506 12:11:44.073891 10, 0xFFFF, sum = 0
7507 12:11:44.077021 11, 0xFFFF, sum = 0
7508 12:11:44.077105 12, 0xFFF, sum = 0
7509 12:11:44.080490 13, 0x0, sum = 1
7510 12:11:44.080574 14, 0x0, sum = 2
7511 12:11:44.083009 15, 0x0, sum = 3
7512 12:11:44.083093 16, 0x0, sum = 4
7513 12:11:44.083161 best_step = 14
7514 12:11:44.083223
7515 12:11:44.086542 ==
7516 12:11:44.090314 Dram Type= 6, Freq= 0, CH_0, rank 0
7517 12:11:44.093330 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7518 12:11:44.093414 ==
7519 12:11:44.093480 RX Vref Scan: 1
7520 12:11:44.093542
7521 12:11:44.096659 Set Vref Range= 24 -> 127
7522 12:11:44.096781
7523 12:11:44.099536 RX Vref 24 -> 127, step: 1
7524 12:11:44.099619
7525 12:11:44.102809 RX Delay 11 -> 252, step: 4
7526 12:11:44.102892
7527 12:11:44.106076 Set Vref, RX VrefLevel [Byte0]: 24
7528 12:11:44.109665 [Byte1]: 24
7529 12:11:44.109748
7530 12:11:44.112946 Set Vref, RX VrefLevel [Byte0]: 25
7531 12:11:44.116046 [Byte1]: 25
7532 12:11:44.116130
7533 12:11:44.119238 Set Vref, RX VrefLevel [Byte0]: 26
7534 12:11:44.122586 [Byte1]: 26
7535 12:11:44.126277
7536 12:11:44.126359 Set Vref, RX VrefLevel [Byte0]: 27
7537 12:11:44.129826 [Byte1]: 27
7538 12:11:44.134687
7539 12:11:44.134770 Set Vref, RX VrefLevel [Byte0]: 28
7540 12:11:44.137287 [Byte1]: 28
7541 12:11:44.141646
7542 12:11:44.141728 Set Vref, RX VrefLevel [Byte0]: 29
7543 12:11:44.145785 [Byte1]: 29
7544 12:11:44.150117
7545 12:11:44.150200 Set Vref, RX VrefLevel [Byte0]: 30
7546 12:11:44.152374 [Byte1]: 30
7547 12:11:44.156701
7548 12:11:44.156824 Set Vref, RX VrefLevel [Byte0]: 31
7549 12:11:44.161919 [Byte1]: 31
7550 12:11:44.164924
7551 12:11:44.165007 Set Vref, RX VrefLevel [Byte0]: 32
7552 12:11:44.168829 [Byte1]: 32
7553 12:11:44.172790
7554 12:11:44.172873 Set Vref, RX VrefLevel [Byte0]: 33
7555 12:11:44.175973 [Byte1]: 33
7556 12:11:44.179824
7557 12:11:44.179906 Set Vref, RX VrefLevel [Byte0]: 34
7558 12:11:44.182960 [Byte1]: 34
7559 12:11:44.187553
7560 12:11:44.187636 Set Vref, RX VrefLevel [Byte0]: 35
7561 12:11:44.191133 [Byte1]: 35
7562 12:11:44.195131
7563 12:11:44.195213 Set Vref, RX VrefLevel [Byte0]: 36
7564 12:11:44.199368 [Byte1]: 36
7565 12:11:44.202954
7566 12:11:44.203036 Set Vref, RX VrefLevel [Byte0]: 37
7567 12:11:44.206318 [Byte1]: 37
7568 12:11:44.210587
7569 12:11:44.210670 Set Vref, RX VrefLevel [Byte0]: 38
7570 12:11:44.213368 [Byte1]: 38
7571 12:11:44.217669
7572 12:11:44.217752 Set Vref, RX VrefLevel [Byte0]: 39
7573 12:11:44.221212 [Byte1]: 39
7574 12:11:44.225366
7575 12:11:44.225449 Set Vref, RX VrefLevel [Byte0]: 40
7576 12:11:44.229604 [Byte1]: 40
7577 12:11:44.233174
7578 12:11:44.233256 Set Vref, RX VrefLevel [Byte0]: 41
7579 12:11:44.236550 [Byte1]: 41
7580 12:11:44.241057
7581 12:11:44.241140 Set Vref, RX VrefLevel [Byte0]: 42
7582 12:11:44.244025 [Byte1]: 42
7583 12:11:44.248326
7584 12:11:44.248408 Set Vref, RX VrefLevel [Byte0]: 43
7585 12:11:44.251311 [Byte1]: 43
7586 12:11:44.256100
7587 12:11:44.256185 Set Vref, RX VrefLevel [Byte0]: 44
7588 12:11:44.259148 [Byte1]: 44
7589 12:11:44.263796
7590 12:11:44.263879 Set Vref, RX VrefLevel [Byte0]: 45
7591 12:11:44.267085 [Byte1]: 45
7592 12:11:44.271214
7593 12:11:44.271297 Set Vref, RX VrefLevel [Byte0]: 46
7594 12:11:44.274860 [Byte1]: 46
7595 12:11:44.278518
7596 12:11:44.278600 Set Vref, RX VrefLevel [Byte0]: 47
7597 12:11:44.281831 [Byte1]: 47
7598 12:11:44.286560
7599 12:11:44.286643 Set Vref, RX VrefLevel [Byte0]: 48
7600 12:11:44.289471 [Byte1]: 48
7601 12:11:44.293898
7602 12:11:44.293981 Set Vref, RX VrefLevel [Byte0]: 49
7603 12:11:44.297182 [Byte1]: 49
7604 12:11:44.302215
7605 12:11:44.302297 Set Vref, RX VrefLevel [Byte0]: 50
7606 12:11:44.304932 [Byte1]: 50
7607 12:11:44.309236
7608 12:11:44.309318 Set Vref, RX VrefLevel [Byte0]: 51
7609 12:11:44.312589 [Byte1]: 51
7610 12:11:44.316417
7611 12:11:44.316500 Set Vref, RX VrefLevel [Byte0]: 52
7612 12:11:44.320260 [Byte1]: 52
7613 12:11:44.326176
7614 12:11:44.326262 Set Vref, RX VrefLevel [Byte0]: 53
7615 12:11:44.327557 [Byte1]: 53
7616 12:11:44.331735
7617 12:11:44.331818 Set Vref, RX VrefLevel [Byte0]: 54
7618 12:11:44.335162 [Byte1]: 54
7619 12:11:44.339870
7620 12:11:44.339952 Set Vref, RX VrefLevel [Byte0]: 55
7621 12:11:44.342946 [Byte1]: 55
7622 12:11:44.347452
7623 12:11:44.347535 Set Vref, RX VrefLevel [Byte0]: 56
7624 12:11:44.350266 [Byte1]: 56
7625 12:11:44.354826
7626 12:11:44.354909 Set Vref, RX VrefLevel [Byte0]: 57
7627 12:11:44.358304 [Byte1]: 57
7628 12:11:44.362578
7629 12:11:44.362660 Set Vref, RX VrefLevel [Byte0]: 58
7630 12:11:44.365740 [Byte1]: 58
7631 12:11:44.370092
7632 12:11:44.370175 Set Vref, RX VrefLevel [Byte0]: 59
7633 12:11:44.373520 [Byte1]: 59
7634 12:11:44.378368
7635 12:11:44.378451 Set Vref, RX VrefLevel [Byte0]: 60
7636 12:11:44.381319 [Byte1]: 60
7637 12:11:44.385545
7638 12:11:44.385628 Set Vref, RX VrefLevel [Byte0]: 61
7639 12:11:44.388958 [Byte1]: 61
7640 12:11:44.393101
7641 12:11:44.393184 Set Vref, RX VrefLevel [Byte0]: 62
7642 12:11:44.396547 [Byte1]: 62
7643 12:11:44.401538
7644 12:11:44.401620 Set Vref, RX VrefLevel [Byte0]: 63
7645 12:11:44.403992 [Byte1]: 63
7646 12:11:44.408043
7647 12:11:44.408125 Set Vref, RX VrefLevel [Byte0]: 64
7648 12:11:44.415107 [Byte1]: 64
7649 12:11:44.415190
7650 12:11:44.417998 Set Vref, RX VrefLevel [Byte0]: 65
7651 12:11:44.421744 [Byte1]: 65
7652 12:11:44.421830
7653 12:11:44.424821 Set Vref, RX VrefLevel [Byte0]: 66
7654 12:11:44.428415 [Byte1]: 66
7655 12:11:44.431132
7656 12:11:44.431215 Set Vref, RX VrefLevel [Byte0]: 67
7657 12:11:44.434505 [Byte1]: 67
7658 12:11:44.438830
7659 12:11:44.438913 Set Vref, RX VrefLevel [Byte0]: 68
7660 12:11:44.442068 [Byte1]: 68
7661 12:11:44.446257
7662 12:11:44.446339 Set Vref, RX VrefLevel [Byte0]: 69
7663 12:11:44.449538 [Byte1]: 69
7664 12:11:44.454169
7665 12:11:44.454252 Set Vref, RX VrefLevel [Byte0]: 70
7666 12:11:44.456873 [Byte1]: 70
7667 12:11:44.461345
7668 12:11:44.461428 Set Vref, RX VrefLevel [Byte0]: 71
7669 12:11:44.465001 [Byte1]: 71
7670 12:11:44.468960
7671 12:11:44.469043 Set Vref, RX VrefLevel [Byte0]: 72
7672 12:11:44.472538 [Byte1]: 72
7673 12:11:44.476921
7674 12:11:44.477005 Final RX Vref Byte 0 = 53 to rank0
7675 12:11:44.479679 Final RX Vref Byte 1 = 55 to rank0
7676 12:11:44.483687 Final RX Vref Byte 0 = 53 to rank1
7677 12:11:44.486412 Final RX Vref Byte 1 = 55 to rank1==
7678 12:11:44.490063 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 12:11:44.496511 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7680 12:11:44.496595 ==
7681 12:11:44.496662 DQS Delay:
7682 12:11:44.500019 DQS0 = 0, DQS1 = 0
7683 12:11:44.500103 DQM Delay:
7684 12:11:44.500169 DQM0 = 126, DQM1 = 121
7685 12:11:44.503437 DQ Delay:
7686 12:11:44.506368 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7687 12:11:44.509434 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7688 12:11:44.513252 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7689 12:11:44.516837 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7690 12:11:44.516921
7691 12:11:44.516987
7692 12:11:44.517048
7693 12:11:44.519931 [DramC_TX_OE_Calibration] TA2
7694 12:11:44.523645 Original DQ_B0 (3 6) =30, OEN = 27
7695 12:11:44.526733 Original DQ_B1 (3 6) =30, OEN = 27
7696 12:11:44.529732 24, 0x0, End_B0=24 End_B1=24
7697 12:11:44.529817 25, 0x0, End_B0=25 End_B1=25
7698 12:11:44.534178 26, 0x0, End_B0=26 End_B1=26
7699 12:11:44.536420 27, 0x0, End_B0=27 End_B1=27
7700 12:11:44.539527 28, 0x0, End_B0=28 End_B1=28
7701 12:11:44.542714 29, 0x0, End_B0=29 End_B1=29
7702 12:11:44.542799 30, 0x0, End_B0=30 End_B1=30
7703 12:11:44.546555 31, 0x4141, End_B0=30 End_B1=30
7704 12:11:44.549669 Byte0 end_step=30 best_step=27
7705 12:11:44.552387 Byte1 end_step=30 best_step=27
7706 12:11:44.555973 Byte0 TX OE(2T, 0.5T) = (3, 3)
7707 12:11:44.559486 Byte1 TX OE(2T, 0.5T) = (3, 3)
7708 12:11:44.559573
7709 12:11:44.559639
7710 12:11:44.566171 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7711 12:11:44.569248 CH0 RK0: MR19=303, MR18=1A1A
7712 12:11:44.575831 CH0_RK0: MR19=0x303, MR18=0x1A1A, DQSOSC=396, MR23=63, INC=23, DEC=15
7713 12:11:44.575915
7714 12:11:44.579361 ----->DramcWriteLeveling(PI) begin...
7715 12:11:44.579445 ==
7716 12:11:44.582189 Dram Type= 6, Freq= 0, CH_0, rank 1
7717 12:11:44.586499 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7718 12:11:44.586583 ==
7719 12:11:44.589077 Write leveling (Byte 0): 28 => 28
7720 12:11:44.592082 Write leveling (Byte 1): 28 => 28
7721 12:11:44.595513 DramcWriteLeveling(PI) end<-----
7722 12:11:44.595611
7723 12:11:44.595694 ==
7724 12:11:44.598968 Dram Type= 6, Freq= 0, CH_0, rank 1
7725 12:11:44.602829 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7726 12:11:44.602930 ==
7727 12:11:44.605258 [Gating] SW mode calibration
7728 12:11:44.612042 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7729 12:11:44.618889 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7730 12:11:44.622495 0 12 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
7731 12:11:44.629458 0 12 4 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7732 12:11:44.632767 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7733 12:11:44.635587 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7734 12:11:44.642294 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7735 12:11:44.645583 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7736 12:11:44.649479 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7737 12:11:44.655417 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7738 12:11:44.659193 0 13 0 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (1 0)
7739 12:11:44.661732 0 13 4 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
7740 12:11:44.669031 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7741 12:11:44.672143 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7742 12:11:44.675330 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7743 12:11:44.681920 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7744 12:11:44.685554 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7745 12:11:44.688019 0 13 28 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7746 12:11:44.695189 0 14 0 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7747 12:11:44.698294 0 14 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7748 12:11:44.701515 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7749 12:11:44.707774 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7750 12:11:44.711991 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7751 12:11:44.714656 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7752 12:11:44.721461 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7753 12:11:44.724500 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7754 12:11:44.728107 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7755 12:11:44.735222 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7756 12:11:44.738283 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7757 12:11:44.741703 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7758 12:11:44.748232 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7759 12:11:44.751401 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7760 12:11:44.754365 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7761 12:11:44.760592 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7762 12:11:44.764299 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7763 12:11:44.768618 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7764 12:11:44.774310 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7765 12:11:44.777557 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7766 12:11:44.780914 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7767 12:11:44.784431 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7768 12:11:44.791484 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7769 12:11:44.794046 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7770 12:11:44.797371 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7771 12:11:44.804192 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7772 12:11:44.807353 Total UI for P1: 0, mck2ui 16
7773 12:11:44.810741 best dqsien dly found for B0: ( 1, 0, 28)
7774 12:11:44.813941 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7775 12:11:44.817124 Total UI for P1: 0, mck2ui 16
7776 12:11:44.821150 best dqsien dly found for B1: ( 1, 1, 4)
7777 12:11:44.823720 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7778 12:11:44.827113 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7779 12:11:44.827259
7780 12:11:44.830367 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7781 12:11:44.833940 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7782 12:11:44.837240 [Gating] SW calibration Done
7783 12:11:44.837352 ==
7784 12:11:44.840535 Dram Type= 6, Freq= 0, CH_0, rank 1
7785 12:11:44.847320 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7786 12:11:44.847404 ==
7787 12:11:44.847470 RX Vref Scan: 0
7788 12:11:44.847533
7789 12:11:44.850722 RX Vref 0 -> 0, step: 1
7790 12:11:44.850804
7791 12:11:44.853710 RX Delay 0 -> 252, step: 8
7792 12:11:44.857655 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7793 12:11:44.860385 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7794 12:11:44.863815 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7795 12:11:44.867370 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7796 12:11:44.873648 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7797 12:11:44.877424 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7798 12:11:44.880975 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7799 12:11:44.883805 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7800 12:11:44.887286 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7801 12:11:44.894350 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7802 12:11:44.897006 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7803 12:11:44.900159 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7804 12:11:44.903506 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7805 12:11:44.910750 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7806 12:11:44.914745 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
7807 12:11:44.917060 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7808 12:11:44.917534 ==
7809 12:11:44.920174 Dram Type= 6, Freq= 0, CH_0, rank 1
7810 12:11:44.923265 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7811 12:11:44.923739 ==
7812 12:11:44.927023 DQS Delay:
7813 12:11:44.927497 DQS0 = 0, DQS1 = 0
7814 12:11:44.930463 DQM Delay:
7815 12:11:44.930934 DQM0 = 131, DQM1 = 123
7816 12:11:44.931313 DQ Delay:
7817 12:11:44.937214 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =127
7818 12:11:44.940380 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =143
7819 12:11:44.943126 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7820 12:11:44.946625 DQ12 =131, DQ13 =131, DQ14 =131, DQ15 =131
7821 12:11:44.947095
7822 12:11:44.947472
7823 12:11:44.947823 ==
7824 12:11:44.949773 Dram Type= 6, Freq= 0, CH_0, rank 1
7825 12:11:44.953996 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7826 12:11:44.954476 ==
7827 12:11:44.954853
7828 12:11:44.955200
7829 12:11:44.956903 TX Vref Scan disable
7830 12:11:44.959755 == TX Byte 0 ==
7831 12:11:44.963616 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7832 12:11:44.966809 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7833 12:11:44.970294 == TX Byte 1 ==
7834 12:11:44.974193 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7835 12:11:44.977339 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7836 12:11:44.977829 ==
7837 12:11:44.979858 Dram Type= 6, Freq= 0, CH_0, rank 1
7838 12:11:44.986190 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7839 12:11:44.986746 ==
7840 12:11:44.998869
7841 12:11:45.002378 TX Vref early break, caculate TX vref
7842 12:11:45.004653 TX Vref=16, minBit 9, minWin=22, winSum=381
7843 12:11:45.008320 TX Vref=18, minBit 6, minWin=23, winSum=391
7844 12:11:45.012086 TX Vref=20, minBit 9, minWin=23, winSum=399
7845 12:11:45.015195 TX Vref=22, minBit 1, minWin=24, winSum=402
7846 12:11:45.018799 TX Vref=24, minBit 1, minWin=25, winSum=414
7847 12:11:45.025029 TX Vref=26, minBit 0, minWin=26, winSum=423
7848 12:11:45.028288 TX Vref=28, minBit 8, minWin=25, winSum=420
7849 12:11:45.032419 TX Vref=30, minBit 0, minWin=25, winSum=419
7850 12:11:45.036190 TX Vref=32, minBit 0, minWin=25, winSum=410
7851 12:11:45.038956 TX Vref=34, minBit 8, minWin=23, winSum=401
7852 12:11:45.042128 TX Vref=36, minBit 8, minWin=23, winSum=392
7853 12:11:45.048117 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 26
7854 12:11:45.048689
7855 12:11:45.051827 Final TX Range 0 Vref 26
7856 12:11:45.052406
7857 12:11:45.052824 ==
7858 12:11:45.055372 Dram Type= 6, Freq= 0, CH_0, rank 1
7859 12:11:45.057822 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7860 12:11:45.058305 ==
7861 12:11:45.058685
7862 12:11:45.059032
7863 12:11:45.061380 TX Vref Scan disable
7864 12:11:45.068029 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7865 12:11:45.068754 == TX Byte 0 ==
7866 12:11:45.072015 u2DelayCellOfst[0]=14 cells (4 PI)
7867 12:11:45.075030 u2DelayCellOfst[1]=17 cells (5 PI)
7868 12:11:45.078878 u2DelayCellOfst[2]=14 cells (4 PI)
7869 12:11:45.081434 u2DelayCellOfst[3]=10 cells (3 PI)
7870 12:11:45.084102 u2DelayCellOfst[4]=10 cells (3 PI)
7871 12:11:45.088012 u2DelayCellOfst[5]=0 cells (0 PI)
7872 12:11:45.091049 u2DelayCellOfst[6]=17 cells (5 PI)
7873 12:11:45.095175 u2DelayCellOfst[7]=17 cells (5 PI)
7874 12:11:45.097672 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7875 12:11:45.100972 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7876 12:11:45.104932 == TX Byte 1 ==
7877 12:11:45.107327 u2DelayCellOfst[8]=3 cells (1 PI)
7878 12:11:45.111021 u2DelayCellOfst[9]=0 cells (0 PI)
7879 12:11:45.114212 u2DelayCellOfst[10]=10 cells (3 PI)
7880 12:11:45.117968 u2DelayCellOfst[11]=7 cells (2 PI)
7881 12:11:45.118539 u2DelayCellOfst[12]=14 cells (4 PI)
7882 12:11:45.121410 u2DelayCellOfst[13]=14 cells (4 PI)
7883 12:11:45.124864 u2DelayCellOfst[14]=17 cells (5 PI)
7884 12:11:45.127435 u2DelayCellOfst[15]=14 cells (4 PI)
7885 12:11:45.134010 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7886 12:11:45.137871 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7887 12:11:45.138438 DramC Write-DBI on
7888 12:11:45.141469 ==
7889 12:11:45.142039 Dram Type= 6, Freq= 0, CH_0, rank 1
7890 12:11:45.147757 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7891 12:11:45.148329 ==
7892 12:11:45.148759
7893 12:11:45.149131
7894 12:11:45.151090 TX Vref Scan disable
7895 12:11:45.151657 == TX Byte 0 ==
7896 12:11:45.157377 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7897 12:11:45.157969 == TX Byte 1 ==
7898 12:11:45.161216 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7899 12:11:45.164239 DramC Write-DBI off
7900 12:11:45.164741
7901 12:11:45.165134 [DATLAT]
7902 12:11:45.167547 Freq=1600, CH0 RK1
7903 12:11:45.168020
7904 12:11:45.168396 DATLAT Default: 0xe
7905 12:11:45.170698 0, 0xFFFF, sum = 0
7906 12:11:45.171179 1, 0xFFFF, sum = 0
7907 12:11:45.173737 2, 0xFFFF, sum = 0
7908 12:11:45.174215 3, 0xFFFF, sum = 0
7909 12:11:45.177193 4, 0xFFFF, sum = 0
7910 12:11:45.177672 5, 0xFFFF, sum = 0
7911 12:11:45.180481 6, 0xFFFF, sum = 0
7912 12:11:45.181018 7, 0xFFFF, sum = 0
7913 12:11:45.184385 8, 0xFFFF, sum = 0
7914 12:11:45.185023 9, 0xFFFF, sum = 0
7915 12:11:45.186999 10, 0xFFFF, sum = 0
7916 12:11:45.190202 11, 0xFFFF, sum = 0
7917 12:11:45.190683 12, 0x8FFF, sum = 0
7918 12:11:45.194000 13, 0x0, sum = 1
7919 12:11:45.194573 14, 0x0, sum = 2
7920 12:11:45.197412 15, 0x0, sum = 3
7921 12:11:45.197890 16, 0x0, sum = 4
7922 12:11:45.198274 best_step = 14
7923 12:11:45.198623
7924 12:11:45.200831 ==
7925 12:11:45.204336 Dram Type= 6, Freq= 0, CH_0, rank 1
7926 12:11:45.207398 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7927 12:11:45.207968 ==
7928 12:11:45.208345 RX Vref Scan: 0
7929 12:11:45.208694
7930 12:11:45.210251 RX Vref 0 -> 0, step: 1
7931 12:11:45.210724
7932 12:11:45.214042 RX Delay 11 -> 252, step: 4
7933 12:11:45.216786 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7934 12:11:45.220471 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
7935 12:11:45.226907 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7936 12:11:45.230210 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7937 12:11:45.234125 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7938 12:11:45.237318 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
7939 12:11:45.240821 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7940 12:11:45.246575 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7941 12:11:45.249880 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7942 12:11:45.253623 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7943 12:11:45.257065 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
7944 12:11:45.260351 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7945 12:11:45.267098 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7946 12:11:45.269867 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7947 12:11:45.273568 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
7948 12:11:45.276342 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7949 12:11:45.276856 ==
7950 12:11:45.279852 Dram Type= 6, Freq= 0, CH_0, rank 1
7951 12:11:45.286333 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7952 12:11:45.286813 ==
7953 12:11:45.287196 DQS Delay:
7954 12:11:45.289432 DQS0 = 0, DQS1 = 0
7955 12:11:45.289904 DQM Delay:
7956 12:11:45.294392 DQM0 = 128, DQM1 = 120
7957 12:11:45.294957 DQ Delay:
7958 12:11:45.296146 DQ0 =124, DQ1 =130, DQ2 =126, DQ3 =124
7959 12:11:45.300460 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
7960 12:11:45.303443 DQ8 =108, DQ9 =106, DQ10 =122, DQ11 =112
7961 12:11:45.306980 DQ12 =126, DQ13 =128, DQ14 =130, DQ15 =130
7962 12:11:45.307453
7963 12:11:45.307825
7964 12:11:45.308167
7965 12:11:45.310445 [DramC_TX_OE_Calibration] TA2
7966 12:11:45.313156 Original DQ_B0 (3 6) =30, OEN = 27
7967 12:11:45.316279 Original DQ_B1 (3 6) =30, OEN = 27
7968 12:11:45.320317 24, 0x0, End_B0=24 End_B1=24
7969 12:11:45.322968 25, 0x0, End_B0=25 End_B1=25
7970 12:11:45.323544 26, 0x0, End_B0=26 End_B1=26
7971 12:11:45.326441 27, 0x0, End_B0=27 End_B1=27
7972 12:11:45.329928 28, 0x0, End_B0=28 End_B1=28
7973 12:11:45.333330 29, 0x0, End_B0=29 End_B1=29
7974 12:11:45.333909 30, 0x0, End_B0=30 End_B1=30
7975 12:11:45.336248 31, 0x4141, End_B0=30 End_B1=30
7976 12:11:45.339566 Byte0 end_step=30 best_step=27
7977 12:11:45.342752 Byte1 end_step=30 best_step=27
7978 12:11:45.346271 Byte0 TX OE(2T, 0.5T) = (3, 3)
7979 12:11:45.349906 Byte1 TX OE(2T, 0.5T) = (3, 3)
7980 12:11:45.350482
7981 12:11:45.350860
7982 12:11:45.356626 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
7983 12:11:45.359159 CH0 RK1: MR19=303, MR18=2121
7984 12:11:45.366462 CH0_RK1: MR19=0x303, MR18=0x2121, DQSOSC=393, MR23=63, INC=23, DEC=15
7985 12:11:45.369210 [RxdqsGatingPostProcess] freq 1600
7986 12:11:45.375652 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7987 12:11:45.376222 Pre-setting of DQS Precalculation
7988 12:11:45.382627 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7989 12:11:45.383199 ==
7990 12:11:45.386097 Dram Type= 6, Freq= 0, CH_1, rank 0
7991 12:11:45.389229 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7992 12:11:45.389705 ==
7993 12:11:45.395892 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7994 12:11:45.400559 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7995 12:11:45.405770 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7996 12:11:45.408452 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7997 12:11:45.418417 [CA 0] Center 41 (11~71) winsize 61
7998 12:11:45.421929 [CA 1] Center 41 (11~72) winsize 62
7999 12:11:45.425554 [CA 2] Center 37 (8~67) winsize 60
8000 12:11:45.428402 [CA 3] Center 36 (7~66) winsize 60
8001 12:11:45.431137 [CA 4] Center 34 (4~64) winsize 61
8002 12:11:45.434864 [CA 5] Center 34 (4~64) winsize 61
8003 12:11:45.435439
8004 12:11:45.437638 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8005 12:11:45.438185
8006 12:11:45.441248 [CATrainingPosCal] consider 1 rank data
8007 12:11:45.445078 u2DelayCellTimex100 = 275/100 ps
8008 12:11:45.448236 CA0 delay=41 (11~71),Diff = 7 PI (24 cell)
8009 12:11:45.454297 CA1 delay=41 (11~72),Diff = 7 PI (24 cell)
8010 12:11:45.457778 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8011 12:11:45.460608 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8012 12:11:45.466102 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8013 12:11:45.467352 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
8014 12:11:45.467820
8015 12:11:45.470775 CA PerBit enable=1, Macro0, CA PI delay=34
8016 12:11:45.471250
8017 12:11:45.474720 [CBTSetCACLKResult] CA Dly = 34
8018 12:11:45.478204 CS Dly: 8 (0~39)
8019 12:11:45.481246 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8020 12:11:45.484326 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8021 12:11:45.484944 ==
8022 12:11:45.488354 Dram Type= 6, Freq= 0, CH_1, rank 1
8023 12:11:45.491677 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8024 12:11:45.493947 ==
8025 12:11:45.497533 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8026 12:11:45.500606 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8027 12:11:45.508044 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8028 12:11:45.510570 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8029 12:11:45.520939 [CA 0] Center 40 (10~70) winsize 61
8030 12:11:45.524047 [CA 1] Center 39 (9~70) winsize 62
8031 12:11:45.527131 [CA 2] Center 35 (6~65) winsize 60
8032 12:11:45.530072 [CA 3] Center 35 (5~65) winsize 61
8033 12:11:45.533376 [CA 4] Center 33 (4~63) winsize 60
8034 12:11:45.536988 [CA 5] Center 33 (3~63) winsize 61
8035 12:11:45.537560
8036 12:11:45.540055 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8037 12:11:45.540635
8038 12:11:45.543455 [CATrainingPosCal] consider 2 rank data
8039 12:11:45.547470 u2DelayCellTimex100 = 275/100 ps
8040 12:11:45.550120 CA0 delay=40 (11~70),Diff = 7 PI (24 cell)
8041 12:11:45.556956 CA1 delay=40 (11~70),Diff = 7 PI (24 cell)
8042 12:11:45.559567 CA2 delay=36 (8~65),Diff = 3 PI (10 cell)
8043 12:11:45.563220 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8044 12:11:45.566733 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8045 12:11:45.569558 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8046 12:11:45.570038
8047 12:11:45.573181 CA PerBit enable=1, Macro0, CA PI delay=33
8048 12:11:45.573994
8049 12:11:45.576148 [CBTSetCACLKResult] CA Dly = 33
8050 12:11:45.580005 CS Dly: 9 (0~41)
8051 12:11:45.583193 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8052 12:11:45.586789 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8053 12:11:45.587363
8054 12:11:45.591436 ----->DramcWriteLeveling(PI) begin...
8055 12:11:45.592026 ==
8056 12:11:45.593135 Dram Type= 6, Freq= 0, CH_1, rank 0
8057 12:11:45.600539 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8058 12:11:45.601179 ==
8059 12:11:45.604013 Write leveling (Byte 0): 22 => 22
8060 12:11:45.604588 Write leveling (Byte 1): 21 => 21
8061 12:11:45.606413 DramcWriteLeveling(PI) end<-----
8062 12:11:45.606892
8063 12:11:45.607268 ==
8064 12:11:45.609991 Dram Type= 6, Freq= 0, CH_1, rank 0
8065 12:11:45.616961 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8066 12:11:45.617548 ==
8067 12:11:45.619287 [Gating] SW mode calibration
8068 12:11:45.626159 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8069 12:11:45.629347 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8070 12:11:45.637079 0 12 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
8071 12:11:45.639953 0 12 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8072 12:11:45.642805 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 12:11:45.649921 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 12:11:45.653108 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8075 12:11:45.656302 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8076 12:11:45.662879 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8077 12:11:45.665850 0 12 28 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
8078 12:11:45.669120 0 13 0 | B1->B0 | 2a2a 2323 | 1 0 | (1 1) (0 0)
8079 12:11:45.676294 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8080 12:11:45.679520 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 12:11:45.682466 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 12:11:45.689266 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 12:11:45.692751 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8084 12:11:45.696082 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8085 12:11:45.702454 0 13 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
8086 12:11:45.706459 0 14 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8087 12:11:45.709099 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 12:11:45.715586 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 12:11:45.719198 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 12:11:45.722006 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8091 12:11:45.726706 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8092 12:11:45.732572 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8093 12:11:45.735368 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8094 12:11:45.738810 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8095 12:11:45.745688 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8096 12:11:45.749376 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8097 12:11:45.751933 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 12:11:45.758643 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 12:11:45.762339 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 12:11:45.768286 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 12:11:45.772154 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 12:11:45.775211 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 12:11:45.778400 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 12:11:45.785675 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 12:11:45.788771 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 12:11:45.791545 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 12:11:45.798132 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 12:11:45.801560 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8109 12:11:45.804569 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8110 12:11:45.811653 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8111 12:11:45.814933 Total UI for P1: 0, mck2ui 16
8112 12:11:45.818008 best dqsien dly found for B0: ( 1, 0, 26)
8113 12:11:45.821113 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8114 12:11:45.824303 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8115 12:11:45.827938 Total UI for P1: 0, mck2ui 16
8116 12:11:45.831329 best dqsien dly found for B1: ( 1, 1, 2)
8117 12:11:45.834590 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8118 12:11:45.841330 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8119 12:11:45.841921
8120 12:11:45.844482 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8121 12:11:45.847607 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8122 12:11:45.851281 [Gating] SW calibration Done
8123 12:11:45.851853 ==
8124 12:11:45.854673 Dram Type= 6, Freq= 0, CH_1, rank 0
8125 12:11:45.857583 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8126 12:11:45.858056 ==
8127 12:11:45.858498 RX Vref Scan: 0
8128 12:11:45.861403
8129 12:11:45.861869 RX Vref 0 -> 0, step: 1
8130 12:11:45.862241
8131 12:11:45.864215 RX Delay 0 -> 252, step: 8
8132 12:11:45.867738 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8133 12:11:45.870307 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8134 12:11:45.878144 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8135 12:11:45.880686 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8136 12:11:45.884382 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8137 12:11:45.887242 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8138 12:11:45.890943 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8139 12:11:45.897052 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8140 12:11:45.901289 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8141 12:11:45.903856 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8142 12:11:45.907299 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8143 12:11:45.911034 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8144 12:11:45.917429 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8145 12:11:45.920760 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8146 12:11:45.924214 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8147 12:11:45.927553 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8148 12:11:45.928024 ==
8149 12:11:45.930437 Dram Type= 6, Freq= 0, CH_1, rank 0
8150 12:11:45.937022 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8151 12:11:45.937517 ==
8152 12:11:45.937898 DQS Delay:
8153 12:11:45.940531 DQS0 = 0, DQS1 = 0
8154 12:11:45.941057 DQM Delay:
8155 12:11:45.941437 DQM0 = 129, DQM1 = 126
8156 12:11:45.944073 DQ Delay:
8157 12:11:45.946972 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8158 12:11:45.950116 DQ4 =127, DQ5 =139, DQ6 =135, DQ7 =127
8159 12:11:45.953614 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =115
8160 12:11:45.957800 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8161 12:11:45.958408
8162 12:11:45.958803
8163 12:11:45.959215 ==
8164 12:11:45.959915 Dram Type= 6, Freq= 0, CH_1, rank 0
8165 12:11:45.966568 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8166 12:11:45.967045 ==
8167 12:11:45.967423
8168 12:11:45.967771
8169 12:11:45.968119 TX Vref Scan disable
8170 12:11:45.970229 == TX Byte 0 ==
8171 12:11:45.972964 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8172 12:11:45.980144 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8173 12:11:45.980703 == TX Byte 1 ==
8174 12:11:45.983605 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8175 12:11:45.989461 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8176 12:11:45.990011 ==
8177 12:11:45.993317 Dram Type= 6, Freq= 0, CH_1, rank 0
8178 12:11:45.997327 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8179 12:11:45.997897 ==
8180 12:11:46.009689
8181 12:11:46.012925 TX Vref early break, caculate TX vref
8182 12:11:46.016586 TX Vref=16, minBit 3, minWin=21, winSum=366
8183 12:11:46.018858 TX Vref=18, minBit 3, minWin=21, winSum=374
8184 12:11:46.022863 TX Vref=20, minBit 0, minWin=23, winSum=387
8185 12:11:46.025717 TX Vref=22, minBit 3, minWin=23, winSum=394
8186 12:11:46.029338 TX Vref=24, minBit 0, minWin=24, winSum=403
8187 12:11:46.036522 TX Vref=26, minBit 3, minWin=24, winSum=412
8188 12:11:46.039621 TX Vref=28, minBit 3, minWin=24, winSum=411
8189 12:11:46.043201 TX Vref=30, minBit 1, minWin=24, winSum=405
8190 12:11:46.045436 TX Vref=32, minBit 1, minWin=23, winSum=398
8191 12:11:46.049385 TX Vref=34, minBit 1, minWin=23, winSum=391
8192 12:11:46.052825 TX Vref=36, minBit 1, minWin=22, winSum=380
8193 12:11:46.058801 [TxChooseVref] Worse bit 3, Min win 24, Win sum 412, Final Vref 26
8194 12:11:46.059385
8195 12:11:46.062066 Final TX Range 0 Vref 26
8196 12:11:46.062534
8197 12:11:46.062968 ==
8198 12:11:46.065286 Dram Type= 6, Freq= 0, CH_1, rank 0
8199 12:11:46.072463 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8200 12:11:46.073082 ==
8201 12:11:46.073466
8202 12:11:46.073816
8203 12:11:46.074147 TX Vref Scan disable
8204 12:11:46.078975 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8205 12:11:46.079560 == TX Byte 0 ==
8206 12:11:46.082205 u2DelayCellOfst[0]=17 cells (5 PI)
8207 12:11:46.086422 u2DelayCellOfst[1]=10 cells (3 PI)
8208 12:11:46.089091 u2DelayCellOfst[2]=0 cells (0 PI)
8209 12:11:46.092070 u2DelayCellOfst[3]=7 cells (2 PI)
8210 12:11:46.095163 u2DelayCellOfst[4]=10 cells (3 PI)
8211 12:11:46.098411 u2DelayCellOfst[5]=17 cells (5 PI)
8212 12:11:46.101569 u2DelayCellOfst[6]=17 cells (5 PI)
8213 12:11:46.105286 u2DelayCellOfst[7]=7 cells (2 PI)
8214 12:11:46.108465 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8215 12:11:46.111964 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8216 12:11:46.115383 == TX Byte 1 ==
8217 12:11:46.118130 u2DelayCellOfst[8]=0 cells (0 PI)
8218 12:11:46.121684 u2DelayCellOfst[9]=7 cells (2 PI)
8219 12:11:46.125386 u2DelayCellOfst[10]=10 cells (3 PI)
8220 12:11:46.125954 u2DelayCellOfst[11]=7 cells (2 PI)
8221 12:11:46.128957 u2DelayCellOfst[12]=17 cells (5 PI)
8222 12:11:46.132122 u2DelayCellOfst[13]=21 cells (6 PI)
8223 12:11:46.134794 u2DelayCellOfst[14]=21 cells (6 PI)
8224 12:11:46.138902 u2DelayCellOfst[15]=17 cells (5 PI)
8225 12:11:46.144617 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8226 12:11:46.148465 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8227 12:11:46.149082 DramC Write-DBI on
8228 12:11:46.152319 ==
8229 12:11:46.154651 Dram Type= 6, Freq= 0, CH_1, rank 0
8230 12:11:46.157981 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8231 12:11:46.158568 ==
8232 12:11:46.158959
8233 12:11:46.159308
8234 12:11:46.161404 TX Vref Scan disable
8235 12:11:46.161872 == TX Byte 0 ==
8236 12:11:46.168841 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8237 12:11:46.169474 == TX Byte 1 ==
8238 12:11:46.171425 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8239 12:11:46.174685 DramC Write-DBI off
8240 12:11:46.175270
8241 12:11:46.175759 [DATLAT]
8242 12:11:46.177926 Freq=1600, CH1 RK0
8243 12:11:46.178455
8244 12:11:46.178830 DATLAT Default: 0xf
8245 12:11:46.181587 0, 0xFFFF, sum = 0
8246 12:11:46.182066 1, 0xFFFF, sum = 0
8247 12:11:46.184121 2, 0xFFFF, sum = 0
8248 12:11:46.184595 3, 0xFFFF, sum = 0
8249 12:11:46.187592 4, 0xFFFF, sum = 0
8250 12:11:46.188064 5, 0xFFFF, sum = 0
8251 12:11:46.191093 6, 0xFFFF, sum = 0
8252 12:11:46.194795 7, 0xFFFF, sum = 0
8253 12:11:46.195290 8, 0xFFFF, sum = 0
8254 12:11:46.198168 9, 0xFFFF, sum = 0
8255 12:11:46.198639 10, 0xFFFF, sum = 0
8256 12:11:46.201066 11, 0xFFFF, sum = 0
8257 12:11:46.201538 12, 0x8F7F, sum = 0
8258 12:11:46.204041 13, 0x0, sum = 1
8259 12:11:46.204613 14, 0x0, sum = 2
8260 12:11:46.207920 15, 0x0, sum = 3
8261 12:11:46.208495 16, 0x0, sum = 4
8262 12:11:46.210775 best_step = 14
8263 12:11:46.211352
8264 12:11:46.211730 ==
8265 12:11:46.214094 Dram Type= 6, Freq= 0, CH_1, rank 0
8266 12:11:46.217577 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8267 12:11:46.218049 ==
8268 12:11:46.218422 RX Vref Scan: 1
8269 12:11:46.218772
8270 12:11:46.220766 Set Vref Range= 24 -> 127
8271 12:11:46.221341
8272 12:11:46.224661 RX Vref 24 -> 127, step: 1
8273 12:11:46.225271
8274 12:11:46.227659 RX Delay 11 -> 252, step: 4
8275 12:11:46.228217
8276 12:11:46.231210 Set Vref, RX VrefLevel [Byte0]: 24
8277 12:11:46.234469 [Byte1]: 24
8278 12:11:46.235036
8279 12:11:46.237564 Set Vref, RX VrefLevel [Byte0]: 25
8280 12:11:46.241118 [Byte1]: 25
8281 12:11:46.241682
8282 12:11:46.244141 Set Vref, RX VrefLevel [Byte0]: 26
8283 12:11:46.247286 [Byte1]: 26
8284 12:11:46.251612
8285 12:11:46.252171 Set Vref, RX VrefLevel [Byte0]: 27
8286 12:11:46.254439 [Byte1]: 27
8287 12:11:46.258762
8288 12:11:46.259330 Set Vref, RX VrefLevel [Byte0]: 28
8289 12:11:46.262197 [Byte1]: 28
8290 12:11:46.266431
8291 12:11:46.267047 Set Vref, RX VrefLevel [Byte0]: 29
8292 12:11:46.270347 [Byte1]: 29
8293 12:11:46.274065
8294 12:11:46.274528 Set Vref, RX VrefLevel [Byte0]: 30
8295 12:11:46.277303 [Byte1]: 30
8296 12:11:46.281731
8297 12:11:46.282189 Set Vref, RX VrefLevel [Byte0]: 31
8298 12:11:46.284831 [Byte1]: 31
8299 12:11:46.288890
8300 12:11:46.289358 Set Vref, RX VrefLevel [Byte0]: 32
8301 12:11:46.292392 [Byte1]: 32
8302 12:11:46.297313
8303 12:11:46.297755 Set Vref, RX VrefLevel [Byte0]: 33
8304 12:11:46.300179 [Byte1]: 33
8305 12:11:46.303882
8306 12:11:46.304257 Set Vref, RX VrefLevel [Byte0]: 34
8307 12:11:46.308488 [Byte1]: 34
8308 12:11:46.312144
8309 12:11:46.312561 Set Vref, RX VrefLevel [Byte0]: 35
8310 12:11:46.315113 [Byte1]: 35
8311 12:11:46.319828
8312 12:11:46.320287 Set Vref, RX VrefLevel [Byte0]: 36
8313 12:11:46.322909 [Byte1]: 36
8314 12:11:46.327276
8315 12:11:46.327695 Set Vref, RX VrefLevel [Byte0]: 37
8316 12:11:46.331223 [Byte1]: 37
8317 12:11:46.334551
8318 12:11:46.334969 Set Vref, RX VrefLevel [Byte0]: 38
8319 12:11:46.337875 [Byte1]: 38
8320 12:11:46.342338
8321 12:11:46.342851 Set Vref, RX VrefLevel [Byte0]: 39
8322 12:11:46.346029 [Byte1]: 39
8323 12:11:46.350650
8324 12:11:46.351170 Set Vref, RX VrefLevel [Byte0]: 40
8325 12:11:46.353784 [Byte1]: 40
8326 12:11:46.358138
8327 12:11:46.358803 Set Vref, RX VrefLevel [Byte0]: 41
8328 12:11:46.360624 [Byte1]: 41
8329 12:11:46.366070
8330 12:11:46.366599 Set Vref, RX VrefLevel [Byte0]: 42
8331 12:11:46.368349 [Byte1]: 42
8332 12:11:46.372340
8333 12:11:46.372743 Set Vref, RX VrefLevel [Byte0]: 43
8334 12:11:46.376457 [Byte1]: 43
8335 12:11:46.381373
8336 12:11:46.381890 Set Vref, RX VrefLevel [Byte0]: 44
8337 12:11:46.383933 [Byte1]: 44
8338 12:11:46.388769
8339 12:11:46.389285 Set Vref, RX VrefLevel [Byte0]: 45
8340 12:11:46.391707 [Byte1]: 45
8341 12:11:46.395902
8342 12:11:46.396426 Set Vref, RX VrefLevel [Byte0]: 46
8343 12:11:46.399500 [Byte1]: 46
8344 12:11:46.403099
8345 12:11:46.403517 Set Vref, RX VrefLevel [Byte0]: 47
8346 12:11:46.406928 [Byte1]: 47
8347 12:11:46.412013
8348 12:11:46.412543 Set Vref, RX VrefLevel [Byte0]: 48
8349 12:11:46.414894 [Byte1]: 48
8350 12:11:46.418894
8351 12:11:46.419316 Set Vref, RX VrefLevel [Byte0]: 49
8352 12:11:46.421798 [Byte1]: 49
8353 12:11:46.426424
8354 12:11:46.426941 Set Vref, RX VrefLevel [Byte0]: 50
8355 12:11:46.429925 [Byte1]: 50
8356 12:11:46.434079
8357 12:11:46.434593 Set Vref, RX VrefLevel [Byte0]: 51
8358 12:11:46.436786 [Byte1]: 51
8359 12:11:46.441295
8360 12:11:46.441712 Set Vref, RX VrefLevel [Byte0]: 52
8361 12:11:46.445118 [Byte1]: 52
8362 12:11:46.449627
8363 12:11:46.450157 Set Vref, RX VrefLevel [Byte0]: 53
8364 12:11:46.452056 [Byte1]: 53
8365 12:11:46.456920
8366 12:11:46.457474 Set Vref, RX VrefLevel [Byte0]: 54
8367 12:11:46.460128 [Byte1]: 54
8368 12:11:46.464518
8369 12:11:46.465153 Set Vref, RX VrefLevel [Byte0]: 55
8370 12:11:46.467727 [Byte1]: 55
8371 12:11:46.471598
8372 12:11:46.472098 Set Vref, RX VrefLevel [Byte0]: 56
8373 12:11:46.474895 [Byte1]: 56
8374 12:11:46.479158
8375 12:11:46.479627 Set Vref, RX VrefLevel [Byte0]: 57
8376 12:11:46.482628 [Byte1]: 57
8377 12:11:46.487120
8378 12:11:46.487694 Set Vref, RX VrefLevel [Byte0]: 58
8379 12:11:46.490628 [Byte1]: 58
8380 12:11:46.494905
8381 12:11:46.495500 Set Vref, RX VrefLevel [Byte0]: 59
8382 12:11:46.498361 [Byte1]: 59
8383 12:11:46.502350
8384 12:11:46.502867 Set Vref, RX VrefLevel [Byte0]: 60
8385 12:11:46.505286 [Byte1]: 60
8386 12:11:46.509727
8387 12:11:46.510300 Set Vref, RX VrefLevel [Byte0]: 61
8388 12:11:46.513221 [Byte1]: 61
8389 12:11:46.517755
8390 12:11:46.518223 Set Vref, RX VrefLevel [Byte0]: 62
8391 12:11:46.522131 [Byte1]: 62
8392 12:11:46.526515
8393 12:11:46.526984 Set Vref, RX VrefLevel [Byte0]: 63
8394 12:11:46.530262 [Byte1]: 63
8395 12:11:46.532922
8396 12:11:46.533390 Set Vref, RX VrefLevel [Byte0]: 64
8397 12:11:46.535584 [Byte1]: 64
8398 12:11:46.540449
8399 12:11:46.540952 Set Vref, RX VrefLevel [Byte0]: 65
8400 12:11:46.543298 [Byte1]: 65
8401 12:11:46.548402
8402 12:11:46.549032 Set Vref, RX VrefLevel [Byte0]: 66
8403 12:11:46.551245 [Byte1]: 66
8404 12:11:46.555609
8405 12:11:46.556172 Set Vref, RX VrefLevel [Byte0]: 67
8406 12:11:46.558737 [Byte1]: 67
8407 12:11:46.563106
8408 12:11:46.563576 Set Vref, RX VrefLevel [Byte0]: 68
8409 12:11:46.566130 [Byte1]: 68
8410 12:11:46.570503
8411 12:11:46.571077 Set Vref, RX VrefLevel [Byte0]: 69
8412 12:11:46.574676 [Byte1]: 69
8413 12:11:46.578367
8414 12:11:46.578925 Set Vref, RX VrefLevel [Byte0]: 70
8415 12:11:46.582451 [Byte1]: 70
8416 12:11:46.585938
8417 12:11:46.586409 Set Vref, RX VrefLevel [Byte0]: 71
8418 12:11:46.589445 [Byte1]: 71
8419 12:11:46.593337
8420 12:11:46.593806 Set Vref, RX VrefLevel [Byte0]: 72
8421 12:11:46.596849 [Byte1]: 72
8422 12:11:46.600869
8423 12:11:46.601410 Set Vref, RX VrefLevel [Byte0]: 73
8424 12:11:46.604606 [Byte1]: 73
8425 12:11:46.609224
8426 12:11:46.609932 Set Vref, RX VrefLevel [Byte0]: 74
8427 12:11:46.611766 [Byte1]: 74
8428 12:11:46.616582
8429 12:11:46.617102 Set Vref, RX VrefLevel [Byte0]: 75
8430 12:11:46.619650 [Byte1]: 75
8431 12:11:46.623923
8432 12:11:46.624466 Final RX Vref Byte 0 = 62 to rank0
8433 12:11:46.627724 Final RX Vref Byte 1 = 55 to rank0
8434 12:11:46.631460 Final RX Vref Byte 0 = 62 to rank1
8435 12:11:46.634217 Final RX Vref Byte 1 = 55 to rank1==
8436 12:11:46.637138 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 12:11:46.644329 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8438 12:11:46.644906 ==
8439 12:11:46.645366 DQS Delay:
8440 12:11:46.645747 DQS0 = 0, DQS1 = 0
8441 12:11:46.648263 DQM Delay:
8442 12:11:46.648795 DQM0 = 128, DQM1 = 123
8443 12:11:46.650362 DQ Delay:
8444 12:11:46.654040 DQ0 =132, DQ1 =122, DQ2 =116, DQ3 =126
8445 12:11:46.657181 DQ4 =128, DQ5 =138, DQ6 =138, DQ7 =126
8446 12:11:46.660302 DQ8 =106, DQ9 =114, DQ10 =124, DQ11 =114
8447 12:11:46.664191 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8448 12:11:46.664675
8449 12:11:46.665215
8450 12:11:46.665583
8451 12:11:46.667203 [DramC_TX_OE_Calibration] TA2
8452 12:11:46.670202 Original DQ_B0 (3 6) =30, OEN = 27
8453 12:11:46.673358 Original DQ_B1 (3 6) =30, OEN = 27
8454 12:11:46.677305 24, 0x0, End_B0=24 End_B1=24
8455 12:11:46.677785 25, 0x0, End_B0=25 End_B1=25
8456 12:11:46.680604 26, 0x0, End_B0=26 End_B1=26
8457 12:11:46.683740 27, 0x0, End_B0=27 End_B1=27
8458 12:11:46.687267 28, 0x0, End_B0=28 End_B1=28
8459 12:11:46.691312 29, 0x0, End_B0=29 End_B1=29
8460 12:11:46.691792 30, 0x0, End_B0=30 End_B1=30
8461 12:11:46.693458 31, 0x4141, End_B0=30 End_B1=30
8462 12:11:46.697427 Byte0 end_step=30 best_step=27
8463 12:11:46.700616 Byte1 end_step=30 best_step=27
8464 12:11:46.703467 Byte0 TX OE(2T, 0.5T) = (3, 3)
8465 12:11:46.706961 Byte1 TX OE(2T, 0.5T) = (3, 3)
8466 12:11:46.707435
8467 12:11:46.707808
8468 12:11:46.713687 [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8469 12:11:46.717151 CH1 RK0: MR19=303, MR18=2626
8470 12:11:46.723983 CH1_RK0: MR19=0x303, MR18=0x2626, DQSOSC=390, MR23=63, INC=24, DEC=16
8471 12:11:46.724650
8472 12:11:46.727142 ----->DramcWriteLeveling(PI) begin...
8473 12:11:46.727802 ==
8474 12:11:46.730483 Dram Type= 6, Freq= 0, CH_1, rank 1
8475 12:11:46.733637 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8476 12:11:46.734148 ==
8477 12:11:46.736453 Write leveling (Byte 0): 23 => 23
8478 12:11:46.739956 Write leveling (Byte 1): 21 => 21
8479 12:11:46.743240 DramcWriteLeveling(PI) end<-----
8480 12:11:46.743851
8481 12:11:46.744298 ==
8482 12:11:46.746224 Dram Type= 6, Freq= 0, CH_1, rank 1
8483 12:11:46.750253 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8484 12:11:46.750899 ==
8485 12:11:46.753209 [Gating] SW mode calibration
8486 12:11:46.760099 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8487 12:11:46.766888 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8488 12:11:46.769619 0 12 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8489 12:11:46.775877 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8490 12:11:46.779827 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8491 12:11:46.783021 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8492 12:11:46.789559 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8493 12:11:46.793230 0 12 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8494 12:11:46.795936 0 12 24 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
8495 12:11:46.803256 0 12 28 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8496 12:11:46.806005 0 13 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8497 12:11:46.809165 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8498 12:11:46.815640 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8499 12:11:46.819582 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8500 12:11:46.823234 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8501 12:11:46.829501 0 13 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8502 12:11:46.832375 0 13 24 | B1->B0 | 2323 4040 | 0 0 | (0 0) (1 1)
8503 12:11:46.835838 0 13 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8504 12:11:46.842754 0 14 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8505 12:11:46.846011 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8506 12:11:46.849132 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8507 12:11:46.855674 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8508 12:11:46.859195 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8509 12:11:46.861993 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8510 12:11:46.868967 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8511 12:11:46.872215 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8512 12:11:46.875401 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8513 12:11:46.882038 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8514 12:11:46.885025 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8515 12:11:46.888682 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8516 12:11:46.891614 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8517 12:11:46.898670 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8518 12:11:46.901880 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8519 12:11:46.905495 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8520 12:11:46.912007 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8521 12:11:46.915615 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8522 12:11:46.918172 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8523 12:11:46.925054 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8524 12:11:46.928350 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8525 12:11:46.932210 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8526 12:11:46.938125 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8527 12:11:46.941873 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8528 12:11:46.945205 Total UI for P1: 0, mck2ui 16
8529 12:11:46.948502 best dqsien dly found for B0: ( 1, 0, 22)
8530 12:11:46.952023 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8531 12:11:46.958218 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8532 12:11:46.958867 Total UI for P1: 0, mck2ui 16
8533 12:11:46.965774 best dqsien dly found for B1: ( 1, 0, 30)
8534 12:11:46.967877 best DQS0 dly(MCK, UI, PI) = (1, 0, 22)
8535 12:11:46.972833 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8536 12:11:46.973308
8537 12:11:46.975175 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 22)
8538 12:11:46.978548 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8539 12:11:46.981683 [Gating] SW calibration Done
8540 12:11:46.982151 ==
8541 12:11:46.984976 Dram Type= 6, Freq= 0, CH_1, rank 1
8542 12:11:46.988184 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8543 12:11:46.988653 ==
8544 12:11:46.991181 RX Vref Scan: 0
8545 12:11:46.991644
8546 12:11:46.992010 RX Vref 0 -> 0, step: 1
8547 12:11:46.992361
8548 12:11:46.995311 RX Delay 0 -> 252, step: 8
8549 12:11:46.998168 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8550 12:11:47.004836 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8551 12:11:47.008471 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8552 12:11:47.011453 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8553 12:11:47.015478 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8554 12:11:47.018195 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8555 12:11:47.024490 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8556 12:11:47.028556 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8557 12:11:47.031926 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8558 12:11:47.035254 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8559 12:11:47.037998 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8560 12:11:47.044809 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8561 12:11:47.048153 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8562 12:11:47.051604 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8563 12:11:47.054720 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8564 12:11:47.061712 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8565 12:11:47.062207 ==
8566 12:11:47.064699 Dram Type= 6, Freq= 0, CH_1, rank 1
8567 12:11:47.067637 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8568 12:11:47.068135 ==
8569 12:11:47.068509 DQS Delay:
8570 12:11:47.070988 DQS0 = 0, DQS1 = 0
8571 12:11:47.071494 DQM Delay:
8572 12:11:47.074218 DQM0 = 131, DQM1 = 125
8573 12:11:47.074709 DQ Delay:
8574 12:11:47.078217 DQ0 =131, DQ1 =131, DQ2 =119, DQ3 =127
8575 12:11:47.081048 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =131
8576 12:11:47.084036 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8577 12:11:47.087488 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =135
8578 12:11:47.088082
8579 12:11:47.088461
8580 12:11:47.091721 ==
8581 12:11:47.094944 Dram Type= 6, Freq= 0, CH_1, rank 1
8582 12:11:47.097327 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8583 12:11:47.097795 ==
8584 12:11:47.098195
8585 12:11:47.098578
8586 12:11:47.100797 TX Vref Scan disable
8587 12:11:47.101324 == TX Byte 0 ==
8588 12:11:47.104012 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8589 12:11:47.110560 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8590 12:11:47.111184 == TX Byte 1 ==
8591 12:11:47.113934 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8592 12:11:47.120914 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8593 12:11:47.121387 ==
8594 12:11:47.123931 Dram Type= 6, Freq= 0, CH_1, rank 1
8595 12:11:47.126907 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8596 12:11:47.127428 ==
8597 12:11:47.141527
8598 12:11:47.144923 TX Vref early break, caculate TX vref
8599 12:11:47.147956 TX Vref=16, minBit 0, minWin=21, winSum=378
8600 12:11:47.151409 TX Vref=18, minBit 0, minWin=22, winSum=383
8601 12:11:47.154929 TX Vref=20, minBit 0, minWin=23, winSum=392
8602 12:11:47.157373 TX Vref=22, minBit 6, minWin=23, winSum=403
8603 12:11:47.161294 TX Vref=24, minBit 0, minWin=24, winSum=413
8604 12:11:47.167667 TX Vref=26, minBit 0, minWin=24, winSum=418
8605 12:11:47.171351 TX Vref=28, minBit 0, minWin=24, winSum=416
8606 12:11:47.175006 TX Vref=30, minBit 0, minWin=23, winSum=414
8607 12:11:47.177865 TX Vref=32, minBit 0, minWin=22, winSum=411
8608 12:11:47.181799 TX Vref=34, minBit 0, minWin=22, winSum=400
8609 12:11:47.183950 TX Vref=36, minBit 0, minWin=21, winSum=388
8610 12:11:47.192559 [TxChooseVref] Worse bit 0, Min win 24, Win sum 418, Final Vref 26
8611 12:11:47.193104
8612 12:11:47.194660 Final TX Range 0 Vref 26
8613 12:11:47.195149
8614 12:11:47.195514 ==
8615 12:11:47.197771 Dram Type= 6, Freq= 0, CH_1, rank 1
8616 12:11:47.200666 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8617 12:11:47.201193 ==
8618 12:11:47.201598
8619 12:11:47.201944
8620 12:11:47.204590 TX Vref Scan disable
8621 12:11:47.211566 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8622 12:11:47.212142 == TX Byte 0 ==
8623 12:11:47.214780 u2DelayCellOfst[0]=14 cells (4 PI)
8624 12:11:47.217150 u2DelayCellOfst[1]=7 cells (2 PI)
8625 12:11:47.220584 u2DelayCellOfst[2]=0 cells (0 PI)
8626 12:11:47.224927 u2DelayCellOfst[3]=7 cells (2 PI)
8627 12:11:47.227248 u2DelayCellOfst[4]=7 cells (2 PI)
8628 12:11:47.230283 u2DelayCellOfst[5]=14 cells (4 PI)
8629 12:11:47.233748 u2DelayCellOfst[6]=14 cells (4 PI)
8630 12:11:47.237557 u2DelayCellOfst[7]=3 cells (1 PI)
8631 12:11:47.240418 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8632 12:11:47.244168 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8633 12:11:47.246728 == TX Byte 1 ==
8634 12:11:47.251001 u2DelayCellOfst[8]=0 cells (0 PI)
8635 12:11:47.251526 u2DelayCellOfst[9]=3 cells (1 PI)
8636 12:11:47.253851 u2DelayCellOfst[10]=10 cells (3 PI)
8637 12:11:47.257561 u2DelayCellOfst[11]=3 cells (1 PI)
8638 12:11:47.260358 u2DelayCellOfst[12]=14 cells (4 PI)
8639 12:11:47.263969 u2DelayCellOfst[13]=17 cells (5 PI)
8640 12:11:47.267415 u2DelayCellOfst[14]=17 cells (5 PI)
8641 12:11:47.270061 u2DelayCellOfst[15]=14 cells (4 PI)
8642 12:11:47.276843 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8643 12:11:47.280336 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8644 12:11:47.280879 DramC Write-DBI on
8645 12:11:47.281369 ==
8646 12:11:47.283007 Dram Type= 6, Freq= 0, CH_1, rank 1
8647 12:11:47.289494 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8648 12:11:47.289961 ==
8649 12:11:47.290331
8650 12:11:47.290673
8651 12:11:47.291035 TX Vref Scan disable
8652 12:11:47.293969 == TX Byte 0 ==
8653 12:11:47.297528 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8654 12:11:47.302218 == TX Byte 1 ==
8655 12:11:47.304340 Update DQM dly =716 (2 ,6, 12) DQM OEN =(3 ,3)
8656 12:11:47.308043 DramC Write-DBI off
8657 12:11:47.308503
8658 12:11:47.308923 [DATLAT]
8659 12:11:47.309274 Freq=1600, CH1 RK1
8660 12:11:47.309609
8661 12:11:47.310652 DATLAT Default: 0xe
8662 12:11:47.311116 0, 0xFFFF, sum = 0
8663 12:11:47.314777 1, 0xFFFF, sum = 0
8664 12:11:47.317837 2, 0xFFFF, sum = 0
8665 12:11:47.318310 3, 0xFFFF, sum = 0
8666 12:11:47.320544 4, 0xFFFF, sum = 0
8667 12:11:47.321104 5, 0xFFFF, sum = 0
8668 12:11:47.324118 6, 0xFFFF, sum = 0
8669 12:11:47.324772 7, 0xFFFF, sum = 0
8670 12:11:47.327699 8, 0xFFFF, sum = 0
8671 12:11:47.328275 9, 0xFFFF, sum = 0
8672 12:11:47.330653 10, 0xFFFF, sum = 0
8673 12:11:47.331124 11, 0xFFFF, sum = 0
8674 12:11:47.334214 12, 0xF7F, sum = 0
8675 12:11:47.334694 13, 0x0, sum = 1
8676 12:11:47.336782 14, 0x0, sum = 2
8677 12:11:47.337287 15, 0x0, sum = 3
8678 12:11:47.341085 16, 0x0, sum = 4
8679 12:11:47.341654 best_step = 14
8680 12:11:47.342032
8681 12:11:47.342598 ==
8682 12:11:47.344011 Dram Type= 6, Freq= 0, CH_1, rank 1
8683 12:11:47.347199 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8684 12:11:47.350708 ==
8685 12:11:47.351328 RX Vref Scan: 0
8686 12:11:47.351751
8687 12:11:47.353414 RX Vref 0 -> 0, step: 1
8688 12:11:47.353875
8689 12:11:47.354319 RX Delay 3 -> 252, step: 4
8690 12:11:47.360982 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8691 12:11:47.364786 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8692 12:11:47.367466 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8693 12:11:47.370688 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8694 12:11:47.374672 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8695 12:11:47.380847 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8696 12:11:47.383845 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8697 12:11:47.387844 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8698 12:11:47.391195 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8699 12:11:47.397363 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
8700 12:11:47.401094 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8701 12:11:47.403484 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8702 12:11:47.407256 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8703 12:11:47.411118 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8704 12:11:47.416889 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8705 12:11:47.420920 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8706 12:11:47.421450 ==
8707 12:11:47.423928 Dram Type= 6, Freq= 0, CH_1, rank 1
8708 12:11:47.427077 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8709 12:11:47.427654 ==
8710 12:11:47.430484 DQS Delay:
8711 12:11:47.431034 DQS0 = 0, DQS1 = 0
8712 12:11:47.431417 DQM Delay:
8713 12:11:47.433824 DQM0 = 127, DQM1 = 122
8714 12:11:47.434291 DQ Delay:
8715 12:11:47.437081 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =124
8716 12:11:47.440385 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8717 12:11:47.447363 DQ8 =106, DQ9 =108, DQ10 =124, DQ11 =114
8718 12:11:47.450383 DQ12 =132, DQ13 =132, DQ14 =134, DQ15 =132
8719 12:11:47.450860
8720 12:11:47.451233
8721 12:11:47.451575
8722 12:11:47.453902 [DramC_TX_OE_Calibration] TA2
8723 12:11:47.456869 Original DQ_B0 (3 6) =30, OEN = 27
8724 12:11:47.457434 Original DQ_B1 (3 6) =30, OEN = 27
8725 12:11:47.460433 24, 0x0, End_B0=24 End_B1=24
8726 12:11:47.463241 25, 0x0, End_B0=25 End_B1=25
8727 12:11:47.468189 26, 0x0, End_B0=26 End_B1=26
8728 12:11:47.470530 27, 0x0, End_B0=27 End_B1=27
8729 12:11:47.471114 28, 0x0, End_B0=28 End_B1=28
8730 12:11:47.473216 29, 0x0, End_B0=29 End_B1=29
8731 12:11:47.477100 30, 0x0, End_B0=30 End_B1=30
8732 12:11:47.479954 31, 0x4545, End_B0=30 End_B1=30
8733 12:11:47.483887 Byte0 end_step=30 best_step=27
8734 12:11:47.484363 Byte1 end_step=30 best_step=27
8735 12:11:47.487406 Byte0 TX OE(2T, 0.5T) = (3, 3)
8736 12:11:47.490206 Byte1 TX OE(2T, 0.5T) = (3, 3)
8737 12:11:47.490676
8738 12:11:47.491048
8739 12:11:47.500107 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8740 12:11:47.503347 CH1 RK1: MR19=303, MR18=1F1F
8741 12:11:47.506762 CH1_RK1: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
8742 12:11:47.510065 [RxdqsGatingPostProcess] freq 1600
8743 12:11:47.516338 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8744 12:11:47.519789 Pre-setting of DQS Precalculation
8745 12:11:47.524117 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8746 12:11:47.533138 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8747 12:11:47.539961 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8748 12:11:47.540501
8749 12:11:47.540917
8750 12:11:47.543163 [Calibration Summary] 3200 Mbps
8751 12:11:47.543735 CH 0, Rank 0
8752 12:11:47.546187 SW Impedance : PASS
8753 12:11:47.546655 DUTY Scan : NO K
8754 12:11:47.550716 ZQ Calibration : PASS
8755 12:11:47.552548 Jitter Meter : NO K
8756 12:11:47.553042 CBT Training : PASS
8757 12:11:47.555886 Write leveling : PASS
8758 12:11:47.559179 RX DQS gating : PASS
8759 12:11:47.559648 RX DQ/DQS(RDDQC) : PASS
8760 12:11:47.563028 TX DQ/DQS : PASS
8761 12:11:47.566433 RX DATLAT : PASS
8762 12:11:47.566904 RX DQ/DQS(Engine): PASS
8763 12:11:47.569456 TX OE : PASS
8764 12:11:47.569923 All Pass.
8765 12:11:47.570292
8766 12:11:47.572746 CH 0, Rank 1
8767 12:11:47.573276 SW Impedance : PASS
8768 12:11:47.576190 DUTY Scan : NO K
8769 12:11:47.579318 ZQ Calibration : PASS
8770 12:11:47.579787 Jitter Meter : NO K
8771 12:11:47.582687 CBT Training : PASS
8772 12:11:47.585865 Write leveling : PASS
8773 12:11:47.586334 RX DQS gating : PASS
8774 12:11:47.589370 RX DQ/DQS(RDDQC) : PASS
8775 12:11:47.589874 TX DQ/DQS : PASS
8776 12:11:47.592263 RX DATLAT : PASS
8777 12:11:47.595827 RX DQ/DQS(Engine): PASS
8778 12:11:47.596367 TX OE : PASS
8779 12:11:47.599154 All Pass.
8780 12:11:47.599625
8781 12:11:47.599996 CH 1, Rank 0
8782 12:11:47.602394 SW Impedance : PASS
8783 12:11:47.602866 DUTY Scan : NO K
8784 12:11:47.605478 ZQ Calibration : PASS
8785 12:11:47.608948 Jitter Meter : NO K
8786 12:11:47.609421 CBT Training : PASS
8787 12:11:47.612044 Write leveling : PASS
8788 12:11:47.615738 RX DQS gating : PASS
8789 12:11:47.616207 RX DQ/DQS(RDDQC) : PASS
8790 12:11:47.619253 TX DQ/DQS : PASS
8791 12:11:47.622094 RX DATLAT : PASS
8792 12:11:47.622566 RX DQ/DQS(Engine): PASS
8793 12:11:47.625387 TX OE : PASS
8794 12:11:47.625857 All Pass.
8795 12:11:47.626229
8796 12:11:47.628690 CH 1, Rank 1
8797 12:11:47.629197 SW Impedance : PASS
8798 12:11:47.632113 DUTY Scan : NO K
8799 12:11:47.636252 ZQ Calibration : PASS
8800 12:11:47.636794 Jitter Meter : NO K
8801 12:11:47.638760 CBT Training : PASS
8802 12:11:47.641874 Write leveling : PASS
8803 12:11:47.642348 RX DQS gating : PASS
8804 12:11:47.645344 RX DQ/DQS(RDDQC) : PASS
8805 12:11:47.648612 TX DQ/DQS : PASS
8806 12:11:47.649228 RX DATLAT : PASS
8807 12:11:47.652127 RX DQ/DQS(Engine): PASS
8808 12:11:47.652597 TX OE : PASS
8809 12:11:47.655757 All Pass.
8810 12:11:47.656315
8811 12:11:47.656693 DramC Write-DBI on
8812 12:11:47.658830 PER_BANK_REFRESH: Hybrid Mode
8813 12:11:47.661719 TX_TRACKING: ON
8814 12:11:47.668340 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8815 12:11:47.678848 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8816 12:11:47.684893 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8817 12:11:47.688107 [FAST_K] Save calibration result to emmc
8818 12:11:47.692119 sync common calibartion params.
8819 12:11:47.692698 sync cbt_mode0:0, 1:0
8820 12:11:47.695639 dram_init: ddr_geometry: 0
8821 12:11:47.698091 dram_init: ddr_geometry: 0
8822 12:11:47.701123 dram_init: ddr_geometry: 0
8823 12:11:47.701592 0:dram_rank_size:80000000
8824 12:11:47.704522 1:dram_rank_size:80000000
8825 12:11:47.711674 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8826 12:11:47.712143 DFS_SHUFFLE_HW_MODE: ON
8827 12:11:47.718754 dramc_set_vcore_voltage set vcore to 725000
8828 12:11:47.719223 Read voltage for 1600, 0
8829 12:11:47.719595 Vio18 = 0
8830 12:11:47.721507 Vcore = 725000
8831 12:11:47.722050 Vdram = 0
8832 12:11:47.722433 Vddq = 0
8833 12:11:47.724798 Vmddr = 0
8834 12:11:47.725269 switch to 3200 Mbps bootup
8835 12:11:47.728197 [DramcRunTimeConfig]
8836 12:11:47.728663 PHYPLL
8837 12:11:47.731495 DPM_CONTROL_AFTERK: ON
8838 12:11:47.731961 PER_BANK_REFRESH: ON
8839 12:11:47.734905 REFRESH_OVERHEAD_REDUCTION: ON
8840 12:11:47.738683 CMD_PICG_NEW_MODE: OFF
8841 12:11:47.739149 XRTWTW_NEW_MODE: ON
8842 12:11:47.741325 XRTRTR_NEW_MODE: ON
8843 12:11:47.741908 TX_TRACKING: ON
8844 12:11:47.744828 RDSEL_TRACKING: OFF
8845 12:11:47.748091 DQS Precalculation for DVFS: ON
8846 12:11:47.748559 RX_TRACKING: OFF
8847 12:11:47.751045 HW_GATING DBG: ON
8848 12:11:47.751511 ZQCS_ENABLE_LP4: ON
8849 12:11:47.754633 RX_PICG_NEW_MODE: ON
8850 12:11:47.758014 TX_PICG_NEW_MODE: ON
8851 12:11:47.758484 ENABLE_RX_DCM_DPHY: ON
8852 12:11:47.761397 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8853 12:11:47.764097 DUMMY_READ_FOR_TRACKING: OFF
8854 12:11:47.767559 !!! SPM_CONTROL_AFTERK: OFF
8855 12:11:47.767823 !!! SPM could not control APHY
8856 12:11:47.771544 IMPEDANCE_TRACKING: ON
8857 12:11:47.774266 TEMP_SENSOR: ON
8858 12:11:47.774509 HW_SAVE_FOR_SR: OFF
8859 12:11:47.777519 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8860 12:11:47.780556 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8861 12:11:47.784291 Read ODT Tracking: ON
8862 12:11:47.784533 Refresh Rate DeBounce: ON
8863 12:11:47.787450 DFS_NO_QUEUE_FLUSH: ON
8864 12:11:47.790418 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8865 12:11:47.793797 ENABLE_DFS_RUNTIME_MRW: OFF
8866 12:11:47.794040 DDR_RESERVE_NEW_MODE: ON
8867 12:11:47.796845 MR_CBT_SWITCH_FREQ: ON
8868 12:11:47.801225 =========================
8869 12:11:47.818610 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8870 12:11:47.821519 dram_init: ddr_geometry: 0
8871 12:11:47.839990 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8872 12:11:47.843313 dram_init: dram init end (result: 0)
8873 12:11:47.850614 DRAM-K: Full calibration passed in 23456 msecs
8874 12:11:47.853141 MRC: failed to locate region type 0.
8875 12:11:47.853719 DRAM rank0 size:0x80000000,
8876 12:11:47.856497 DRAM rank1 size=0x80000000
8877 12:11:47.866369 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8878 12:11:47.873090 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8879 12:11:47.880561 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8880 12:11:47.886416 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8881 12:11:47.890129 DRAM rank0 size:0x80000000,
8882 12:11:47.893538 DRAM rank1 size=0x80000000
8883 12:11:47.894079 CBMEM:
8884 12:11:47.895879 IMD: root @ 0xfffff000 254 entries.
8885 12:11:47.899007 IMD: root @ 0xffffec00 62 entries.
8886 12:11:47.902885 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8887 12:11:47.906334 WARNING: RO_VPD is uninitialized or empty.
8888 12:11:47.913179 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8889 12:11:47.919653 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8890 12:11:47.932253 read SPI 0x42894 0xe01e: 6223 us, 9219 KB/s, 73.752 Mbps
8891 12:11:47.944481 BS: romstage times (exec / console): total (unknown) / 22991 ms
8892 12:11:47.945105
8893 12:11:47.945487
8894 12:11:47.953578 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8895 12:11:47.956948 ARM64: Exception handlers installed.
8896 12:11:47.961175 ARM64: Testing exception
8897 12:11:47.963889 ARM64: Done test exception
8898 12:11:47.964355 Enumerating buses...
8899 12:11:47.967654 Show all devs... Before device enumeration.
8900 12:11:47.970730 Root Device: enabled 1
8901 12:11:47.973891 CPU_CLUSTER: 0: enabled 1
8902 12:11:47.974462 CPU: 00: enabled 1
8903 12:11:47.976874 Compare with tree...
8904 12:11:47.977434 Root Device: enabled 1
8905 12:11:47.980445 CPU_CLUSTER: 0: enabled 1
8906 12:11:47.984041 CPU: 00: enabled 1
8907 12:11:47.984856 Root Device scanning...
8908 12:11:47.986863 scan_static_bus for Root Device
8909 12:11:47.990529 CPU_CLUSTER: 0 enabled
8910 12:11:47.993962 scan_static_bus for Root Device done
8911 12:11:47.996762 scan_bus: bus Root Device finished in 8 msecs
8912 12:11:47.997243 done
8913 12:11:48.003667 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8914 12:11:48.006763 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8915 12:11:48.013157 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8916 12:11:48.016328 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8917 12:11:48.019879 Allocating resources...
8918 12:11:48.023596 Reading resources...
8919 12:11:48.026536 Root Device read_resources bus 0 link: 0
8920 12:11:48.027102 DRAM rank0 size:0x80000000,
8921 12:11:48.030239 DRAM rank1 size=0x80000000
8922 12:11:48.032815 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8923 12:11:48.036625 CPU: 00 missing read_resources
8924 12:11:48.039810 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8925 12:11:48.046301 Root Device read_resources bus 0 link: 0 done
8926 12:11:48.046884 Done reading resources.
8927 12:11:48.053276 Show resources in subtree (Root Device)...After reading.
8928 12:11:48.056193 Root Device child on link 0 CPU_CLUSTER: 0
8929 12:11:48.059379 CPU_CLUSTER: 0 child on link 0 CPU: 00
8930 12:11:48.069288 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8931 12:11:48.069765 CPU: 00
8932 12:11:48.075424 Root Device assign_resources, bus 0 link: 0
8933 12:11:48.076481 CPU_CLUSTER: 0 missing set_resources
8934 12:11:48.082723 Root Device assign_resources, bus 0 link: 0 done
8935 12:11:48.083372 Done setting resources.
8936 12:11:48.089795 Show resources in subtree (Root Device)...After assigning values.
8937 12:11:48.092780 Root Device child on link 0 CPU_CLUSTER: 0
8938 12:11:48.095369 CPU_CLUSTER: 0 child on link 0 CPU: 00
8939 12:11:48.105738 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8940 12:11:48.106680 CPU: 00
8941 12:11:48.109362 Done allocating resources.
8942 12:11:48.115248 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8943 12:11:48.115787 Enabling resources...
8944 12:11:48.116160 done.
8945 12:11:48.122133 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8946 12:11:48.122660 Initializing devices...
8947 12:11:48.125452 Root Device init
8948 12:11:48.125918 init hardware done!
8949 12:11:48.128555 0x00000018: ctrlr->caps
8950 12:11:48.131828 52.000 MHz: ctrlr->f_max
8951 12:11:48.132306 0.400 MHz: ctrlr->f_min
8952 12:11:48.135062 0x40ff8080: ctrlr->voltages
8953 12:11:48.139293 sclk: 390625
8954 12:11:48.139865 Bus Width = 1
8955 12:11:48.140241 sclk: 390625
8956 12:11:48.141744 Bus Width = 1
8957 12:11:48.142212 Early init status = 3
8958 12:11:48.148406 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8959 12:11:48.151959 in-header: 03 fc 00 00 01 00 00 00
8960 12:11:48.155678 in-data: 00
8961 12:11:48.158691 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8962 12:11:48.163116 in-header: 03 fd 00 00 00 00 00 00
8963 12:11:48.165732 in-data:
8964 12:11:48.169294 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8965 12:11:48.172596 in-header: 03 fc 00 00 01 00 00 00
8966 12:11:48.175826 in-data: 00
8967 12:11:48.179328 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8968 12:11:48.183695 in-header: 03 fd 00 00 00 00 00 00
8969 12:11:48.187433 in-data:
8970 12:11:48.190009 [SSUSB] Setting up USB HOST controller...
8971 12:11:48.195374 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8972 12:11:48.197222 [SSUSB] phy power-on done.
8973 12:11:48.200426 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8974 12:11:48.207539 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8975 12:11:48.211989 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8976 12:11:48.216748 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8977 12:11:48.223361 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
8978 12:11:48.230179 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8979 12:11:48.237013 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8980 12:11:48.243261 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8981 12:11:48.246707 SPM: binary array size = 0x9dc
8982 12:11:48.251061 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8983 12:11:48.257586 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8984 12:11:48.263842 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8985 12:11:48.270142 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8986 12:11:48.273304 configure_display: Starting display init
8987 12:11:48.307317 anx7625_power_on_init: Init interface.
8988 12:11:48.310282 anx7625_disable_pd_protocol: Disabled PD feature.
8989 12:11:48.313243 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8990 12:11:48.341216 anx7625_start_dp_work: Secure OCM version=00
8991 12:11:48.344920 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8992 12:11:48.359465 sp_tx_get_edid_block: EDID Block = 1
8993 12:11:48.461943 Extracted contents:
8994 12:11:48.465424 header: 00 ff ff ff ff ff ff 00
8995 12:11:48.468267 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8996 12:11:48.471816 version: 01 04
8997 12:11:48.475035 basic params: 95 1f 11 78 0a
8998 12:11:48.478549 chroma info: 76 90 94 55 54 90 27 21 50 54
8999 12:11:48.481540 established: 00 00 00
9000 12:11:48.488249 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9001 12:11:48.491901 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9002 12:11:48.498558 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9003 12:11:48.505406 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9004 12:11:48.512245 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9005 12:11:48.515159 extensions: 00
9006 12:11:48.515621 checksum: fb
9007 12:11:48.515987
9008 12:11:48.520911 Manufacturer: IVO Model 57d Serial Number 0
9009 12:11:48.521463 Made week 0 of 2020
9010 12:11:48.524530 EDID version: 1.4
9011 12:11:48.525035 Digital display
9012 12:11:48.528232 6 bits per primary color channel
9013 12:11:48.528704 DisplayPort interface
9014 12:11:48.531022 Maximum image size: 31 cm x 17 cm
9015 12:11:48.534470 Gamma: 220%
9016 12:11:48.535025 Check DPMS levels
9017 12:11:48.541228 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9018 12:11:48.544504 First detailed timing is preferred timing
9019 12:11:48.545014 Established timings supported:
9020 12:11:48.548251 Standard timings supported:
9021 12:11:48.550997 Detailed timings
9022 12:11:48.554325 Hex of detail: 383680a07038204018303c0035ae10000019
9023 12:11:48.561375 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9024 12:11:48.566203 0780 0798 07c8 0820 hborder 0
9025 12:11:48.568884 0438 043b 0447 0458 vborder 0
9026 12:11:48.572165 -hsync -vsync
9027 12:11:48.572626 Did detailed timing
9028 12:11:48.577198 Hex of detail: 000000000000000000000000000000000000
9029 12:11:48.580893 Manufacturer-specified data, tag 0
9030 12:11:48.583957 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9031 12:11:48.587256 ASCII string: InfoVision
9032 12:11:48.590172 Hex of detail: 000000fe00523134304e574635205248200a
9033 12:11:48.593783 ASCII string: R140NWF5 RH
9034 12:11:48.594252 Checksum
9035 12:11:48.597171 Checksum: 0xfb (valid)
9036 12:11:48.600407 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9037 12:11:48.603904 DSI data_rate: 832800000 bps
9038 12:11:48.610242 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9039 12:11:48.613525 anx7625_parse_edid: pixelclock(138800).
9040 12:11:48.617409 hactive(1920), hsync(48), hfp(24), hbp(88)
9041 12:11:48.620235 vactive(1080), vsync(12), vfp(3), vbp(17)
9042 12:11:48.624221 anx7625_dsi_config: config dsi.
9043 12:11:48.630700 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9044 12:11:48.644636 anx7625_dsi_config: success to config DSI
9045 12:11:48.647561 anx7625_dp_start: MIPI phy setup OK.
9046 12:11:48.651383 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9047 12:11:48.654606 mtk_ddp_mode_set invalid vrefresh 60
9048 12:11:48.657648 main_disp_path_setup
9049 12:11:48.658216 ovl_layer_smi_id_en
9050 12:11:48.661170 ovl_layer_smi_id_en
9051 12:11:48.661743 ccorr_config
9052 12:11:48.662118 aal_config
9053 12:11:48.664186 gamma_config
9054 12:11:48.664654 postmask_config
9055 12:11:48.667960 dither_config
9056 12:11:48.670671 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9057 12:11:48.677457 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9058 12:11:48.680834 Root Device init finished in 551 msecs
9059 12:11:48.684151 CPU_CLUSTER: 0 init
9060 12:11:48.690293 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9061 12:11:48.696933 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9062 12:11:48.697397 APU_MBOX 0x190000b0 = 0x10001
9063 12:11:48.700826 APU_MBOX 0x190001b0 = 0x10001
9064 12:11:48.703614 APU_MBOX 0x190005b0 = 0x10001
9065 12:11:48.707754 APU_MBOX 0x190006b0 = 0x10001
9066 12:11:48.710348 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9067 12:11:48.723347 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9068 12:11:48.735459 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9069 12:11:48.742499 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9070 12:11:48.754462 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9071 12:11:48.763115 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9072 12:11:48.766299 CPU_CLUSTER: 0 init finished in 81 msecs
9073 12:11:48.770365 Devices initialized
9074 12:11:48.772913 Show all devs... After init.
9075 12:11:48.773531 Root Device: enabled 1
9076 12:11:48.776429 CPU_CLUSTER: 0: enabled 1
9077 12:11:48.780575 CPU: 00: enabled 1
9078 12:11:48.782733 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9079 12:11:48.788049 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9080 12:11:48.789375 ELOG: NV offset 0x57f000 size 0x1000
9081 12:11:48.795701 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9082 12:11:48.802919 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9083 12:11:48.806834 ELOG: Event(17) added with size 13 at 2024-01-31 12:11:52 UTC
9084 12:11:48.812628 out: cmd=0x121: 03 db 21 01 00 00 00 00
9085 12:11:48.815630 in-header: 03 dd 00 00 2c 00 00 00
9086 12:11:48.825221 in-data: 86 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9087 12:11:48.832749 ELOG: Event(A1) added with size 10 at 2024-01-31 12:11:52 UTC
9088 12:11:48.838862 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9089 12:11:48.845226 ELOG: Event(A0) added with size 9 at 2024-01-31 12:11:52 UTC
9090 12:11:48.848948 elog_add_boot_reason: Logged dev mode boot
9091 12:11:48.855685 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9092 12:11:48.856235 Finalize devices...
9093 12:11:48.858652 Devices finalized
9094 12:11:48.862266 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9095 12:11:48.865070 Writing coreboot table at 0xffe64000
9096 12:11:48.868840 0. 000000000010a000-0000000000113fff: RAMSTAGE
9097 12:11:48.871677 1. 0000000040000000-00000000400fffff: RAM
9098 12:11:48.878565 2. 0000000040100000-000000004032afff: RAMSTAGE
9099 12:11:48.882123 3. 000000004032b000-00000000545fffff: RAM
9100 12:11:48.885557 4. 0000000054600000-000000005465ffff: BL31
9101 12:11:48.889219 5. 0000000054660000-00000000ffe63fff: RAM
9102 12:11:48.895020 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9103 12:11:48.898580 7. 0000000100000000-000000013fffffff: RAM
9104 12:11:48.901673 Passing 5 GPIOs to payload:
9105 12:11:48.905192 NAME | PORT | POLARITY | VALUE
9106 12:11:48.908510 EC in RW | 0x000000aa | low | undefined
9107 12:11:48.915443 EC interrupt | 0x00000005 | low | undefined
9108 12:11:48.918170 TPM interrupt | 0x000000ab | high | undefined
9109 12:11:48.925325 SD card detect | 0x00000011 | high | undefined
9110 12:11:48.929171 speaker enable | 0x00000093 | high | undefined
9111 12:11:48.932113 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9112 12:11:48.935465 in-header: 03 f8 00 00 02 00 00 00
9113 12:11:48.938791 in-data: 03 00
9114 12:11:48.939369 ADC[4]: Raw value=669695 ID=5
9115 12:11:48.941382 ADC[3]: Raw value=212917 ID=1
9116 12:11:48.945170 RAM Code: 0x51
9117 12:11:48.948346 ADC[6]: Raw value=74778 ID=0
9118 12:11:48.949004 ADC[5]: Raw value=211812 ID=1
9119 12:11:48.951493 SKU Code: 0x1
9120 12:11:48.955132 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum dd72
9121 12:11:48.957956 coreboot table: 964 bytes.
9122 12:11:48.961359 IMD ROOT 0. 0xfffff000 0x00001000
9123 12:11:48.964595 IMD SMALL 1. 0xffffe000 0x00001000
9124 12:11:48.967747 RO MCACHE 2. 0xffffc000 0x00001104
9125 12:11:48.971885 CONSOLE 3. 0xfff7c000 0x00080000
9126 12:11:48.974751 FMAP 4. 0xfff7b000 0x00000452
9127 12:11:48.977822 TIME STAMP 5. 0xfff7a000 0x00000910
9128 12:11:48.981691 VBOOT WORK 6. 0xfff66000 0x00014000
9129 12:11:48.984630 RAMOOPS 7. 0xffe66000 0x00100000
9130 12:11:48.988470 COREBOOT 8. 0xffe64000 0x00002000
9131 12:11:48.991989 IMD small region:
9132 12:11:48.994536 IMD ROOT 0. 0xffffec00 0x00000400
9133 12:11:48.998854 VPD 1. 0xffffeb80 0x0000006c
9134 12:11:49.001533 MMC STATUS 2. 0xffffeb60 0x00000004
9135 12:11:49.004652 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9136 12:11:49.007821 Probing TPM: done!
9137 12:11:49.011225 Connected to device vid:did:rid of 1ae0:0028:00
9138 12:11:49.021972 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9139 12:11:49.024980 Initialized TPM device CR50 revision 0
9140 12:11:49.028456 Checking cr50 for pending updates
9141 12:11:49.032492 Reading cr50 TPM mode
9142 12:11:49.041209 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9143 12:11:49.047769 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9144 12:11:49.087876 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9145 12:11:49.091553 Checking segment from ROM address 0x40100000
9146 12:11:49.094111 Checking segment from ROM address 0x4010001c
9147 12:11:49.101589 Loading segment from ROM address 0x40100000
9148 12:11:49.102057 code (compression=0)
9149 12:11:49.112102 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9150 12:11:49.117927 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9151 12:11:49.118491 it's not compressed!
9152 12:11:49.124538 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9153 12:11:49.128121 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9154 12:11:49.148228 Loading segment from ROM address 0x4010001c
9155 12:11:49.148814 Entry Point 0x80000000
9156 12:11:49.151586 Loaded segments
9157 12:11:49.155507 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9158 12:11:49.161392 Jumping to boot code at 0x80000000(0xffe64000)
9159 12:11:49.168600 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9160 12:11:49.174797 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9161 12:11:49.182120 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9162 12:11:49.186696 Checking segment from ROM address 0x40100000
9163 12:11:49.189301 Checking segment from ROM address 0x4010001c
9164 12:11:49.196227 Loading segment from ROM address 0x40100000
9165 12:11:49.196917 code (compression=1)
9166 12:11:49.202432 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9167 12:11:49.213213 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9168 12:11:49.213690 using LZMA
9169 12:11:49.220806 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9170 12:11:49.228484 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9171 12:11:49.230564 Loading segment from ROM address 0x4010001c
9172 12:11:49.231035 Entry Point 0x54601000
9173 12:11:49.234137 Loaded segments
9174 12:11:49.237194 NOTICE: MT8192 bl31_setup
9175 12:11:49.244447 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9176 12:11:49.248034 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9177 12:11:49.251997 WARNING: region 0:
9178 12:11:49.254959 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9179 12:11:49.255515 WARNING: region 1:
9180 12:11:49.260923 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9181 12:11:49.264106 WARNING: region 2:
9182 12:11:49.267656 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9183 12:11:49.271130 WARNING: region 3:
9184 12:11:49.273993 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9185 12:11:49.277412 WARNING: region 4:
9186 12:11:49.285030 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9187 12:11:49.285537 WARNING: region 5:
9188 12:11:49.287677 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9189 12:11:49.290497 WARNING: region 6:
9190 12:11:49.294421 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9191 12:11:49.297500 WARNING: region 7:
9192 12:11:49.300739 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9193 12:11:49.306954 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9194 12:11:49.310731 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9195 12:11:49.317399 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9196 12:11:49.320700 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9197 12:11:49.323826 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9198 12:11:49.330780 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9199 12:11:49.334187 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9200 12:11:49.337173 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9201 12:11:49.344616 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9202 12:11:49.347253 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9203 12:11:49.354595 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9204 12:11:49.357098 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9205 12:11:49.360935 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9206 12:11:49.367967 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9207 12:11:49.371120 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9208 12:11:49.373709 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9209 12:11:49.380634 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9210 12:11:49.383596 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9211 12:11:49.386608 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9212 12:11:49.393105 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9213 12:11:49.396821 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9214 12:11:49.403355 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9215 12:11:49.407640 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9216 12:11:49.410135 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9217 12:11:49.417359 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9218 12:11:49.420594 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9219 12:11:49.427725 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9220 12:11:49.430122 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9221 12:11:49.434261 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9222 12:11:49.440700 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9223 12:11:49.443990 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9224 12:11:49.450501 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9225 12:11:49.453724 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9226 12:11:49.457725 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9227 12:11:49.460806 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9228 12:11:49.467373 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9229 12:11:49.470719 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9230 12:11:49.473604 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9231 12:11:49.477006 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9232 12:11:49.483985 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9233 12:11:49.486584 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9234 12:11:49.490135 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9235 12:11:49.493615 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9236 12:11:49.500655 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9237 12:11:49.504417 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9238 12:11:49.508006 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9239 12:11:49.511478 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9240 12:11:49.516646 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9241 12:11:49.520925 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9242 12:11:49.524146 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9243 12:11:49.531440 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9244 12:11:49.533986 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9245 12:11:49.540773 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9246 12:11:49.543899 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9247 12:11:49.550000 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9248 12:11:49.554131 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9249 12:11:49.556697 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9250 12:11:49.563629 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9251 12:11:49.566518 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9252 12:11:49.573416 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9253 12:11:49.576826 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9254 12:11:49.583302 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9255 12:11:49.586839 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9256 12:11:49.594245 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9257 12:11:49.597502 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9258 12:11:49.600580 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9259 12:11:49.607171 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9260 12:11:49.610037 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9261 12:11:49.616771 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9262 12:11:49.620248 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9263 12:11:49.627107 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9264 12:11:49.629560 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9265 12:11:49.633051 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9266 12:11:49.640088 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9267 12:11:49.643603 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9268 12:11:49.649705 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9269 12:11:49.653743 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9270 12:11:49.660202 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9271 12:11:49.663957 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9272 12:11:49.669648 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9273 12:11:49.673218 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9274 12:11:49.676191 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9275 12:11:49.682891 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9276 12:11:49.686356 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9277 12:11:49.693053 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9278 12:11:49.697037 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9279 12:11:49.703053 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9280 12:11:49.707530 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9281 12:11:49.709330 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9282 12:11:49.716166 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9283 12:11:49.719998 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9284 12:11:49.725878 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9285 12:11:49.729976 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9286 12:11:49.736544 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9287 12:11:49.739427 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9288 12:11:49.746015 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9289 12:11:49.749935 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9290 12:11:49.752796 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9291 12:11:49.756702 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9292 12:11:49.762707 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9293 12:11:49.766406 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9294 12:11:49.769920 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9295 12:11:49.775698 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9296 12:11:49.778838 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9297 12:11:49.782389 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9298 12:11:49.788924 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9299 12:11:49.792478 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9300 12:11:49.799262 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9301 12:11:49.802608 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9302 12:11:49.805969 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9303 12:11:49.812350 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9304 12:11:49.816300 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9305 12:11:49.822714 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9306 12:11:49.825622 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9307 12:11:49.829140 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9308 12:11:49.836463 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9309 12:11:49.839419 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9310 12:11:49.842831 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9311 12:11:49.850138 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9312 12:11:49.852822 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9313 12:11:49.856195 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9314 12:11:49.859212 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9315 12:11:49.866742 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9316 12:11:49.869084 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9317 12:11:49.873730 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9318 12:11:49.878853 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9319 12:11:49.882911 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9320 12:11:49.885882 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9321 12:11:49.892451 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9322 12:11:49.895796 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9323 12:11:49.902797 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9324 12:11:49.906020 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9325 12:11:49.908851 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9326 12:11:49.915920 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9327 12:11:49.918894 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9328 12:11:49.925860 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9329 12:11:49.929323 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9330 12:11:49.932596 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9331 12:11:49.939114 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9332 12:11:49.942678 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9333 12:11:49.946542 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9334 12:11:49.952369 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9335 12:11:49.955278 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9336 12:11:49.963009 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9337 12:11:49.965831 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9338 12:11:49.968995 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9339 12:11:49.976233 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9340 12:11:49.979082 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9341 12:11:49.985394 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9342 12:11:49.989161 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9343 12:11:49.993012 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9344 12:11:49.999569 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9345 12:11:50.001966 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9346 12:11:50.006114 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9347 12:11:50.011971 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9348 12:11:50.015368 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9349 12:11:50.022612 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9350 12:11:50.025544 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9351 12:11:50.028640 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9352 12:11:50.035709 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9353 12:11:50.038738 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9354 12:11:50.045539 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9355 12:11:50.048865 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9356 12:11:50.052540 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9357 12:11:50.059058 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9358 12:11:50.061963 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9359 12:11:50.068111 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9360 12:11:50.071425 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9361 12:11:50.074637 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9362 12:11:50.081558 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9363 12:11:50.085192 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9364 12:11:50.091840 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9365 12:11:50.094368 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9366 12:11:50.098542 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9367 12:11:50.104612 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9368 12:11:50.108446 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9369 12:11:50.115070 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9370 12:11:50.117916 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9371 12:11:50.122033 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9372 12:11:50.128140 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9373 12:11:50.131278 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9374 12:11:50.137636 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9375 12:11:50.141216 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9376 12:11:50.144550 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9377 12:11:50.151432 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9378 12:11:50.155542 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9379 12:11:50.161222 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9380 12:11:50.164746 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9381 12:11:50.168310 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9382 12:11:50.174311 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9383 12:11:50.177746 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9384 12:11:50.184417 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9385 12:11:50.187745 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9386 12:11:50.193827 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9387 12:11:50.197321 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9388 12:11:50.201311 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9389 12:11:50.208318 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9390 12:11:50.211131 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9391 12:11:50.217587 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9392 12:11:50.220408 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9393 12:11:50.223894 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9394 12:11:50.230122 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9395 12:11:50.234259 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9396 12:11:50.241969 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9397 12:11:50.244252 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9398 12:11:50.251070 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9399 12:11:50.253842 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9400 12:11:50.257091 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9401 12:11:50.263286 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9402 12:11:50.266475 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9403 12:11:50.273766 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9404 12:11:50.276368 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9405 12:11:50.283602 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9406 12:11:50.286846 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9407 12:11:50.289707 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9408 12:11:50.297624 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9409 12:11:50.301058 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9410 12:11:50.306461 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9411 12:11:50.310445 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9412 12:11:50.316471 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9413 12:11:50.320016 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9414 12:11:50.323729 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9415 12:11:50.329760 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9416 12:11:50.333086 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9417 12:11:50.339484 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9418 12:11:50.342499 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9419 12:11:50.349449 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9420 12:11:50.353014 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9421 12:11:50.356138 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9422 12:11:50.362492 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9423 12:11:50.366528 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9424 12:11:50.369042 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9425 12:11:50.372748 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9426 12:11:50.376380 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9427 12:11:50.383577 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9428 12:11:50.385987 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9429 12:11:50.392203 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9430 12:11:50.397499 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9431 12:11:50.399240 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9432 12:11:50.405720 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9433 12:11:50.410385 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9434 12:11:50.417524 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9435 12:11:50.418400 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9436 12:11:50.422095 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9437 12:11:50.428783 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9438 12:11:50.432008 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9439 12:11:50.435356 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9440 12:11:50.441792 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9441 12:11:50.445399 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9442 12:11:50.449379 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9443 12:11:50.455416 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9444 12:11:50.458747 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9445 12:11:50.464932 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9446 12:11:50.468431 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9447 12:11:50.471847 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9448 12:11:50.478286 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9449 12:11:50.481640 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9450 12:11:50.488410 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9451 12:11:50.491414 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9452 12:11:50.494636 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9453 12:11:50.501131 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9454 12:11:50.504841 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9455 12:11:50.508012 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9456 12:11:50.514536 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9457 12:11:50.518264 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9458 12:11:50.521292 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9459 12:11:50.527469 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9460 12:11:50.532102 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9461 12:11:50.537576 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9462 12:11:50.540662 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9463 12:11:50.544285 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9464 12:11:50.547782 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9465 12:11:50.550807 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9466 12:11:50.557305 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9467 12:11:50.561101 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9468 12:11:50.563831 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9469 12:11:50.566925 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9470 12:11:50.574163 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9471 12:11:50.577555 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9472 12:11:50.581099 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9473 12:11:50.584258 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9474 12:11:50.590526 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9475 12:11:50.594240 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9476 12:11:50.601057 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9477 12:11:50.604452 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9478 12:11:50.611433 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9479 12:11:50.613324 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9480 12:11:50.617682 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9481 12:11:50.623482 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9482 12:11:50.626602 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9483 12:11:50.634081 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9484 12:11:50.636290 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9485 12:11:50.640338 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9486 12:11:50.646286 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9487 12:11:50.650360 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9488 12:11:50.656582 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9489 12:11:50.659590 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9490 12:11:50.662776 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9491 12:11:50.669902 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9492 12:11:50.672789 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9493 12:11:50.679570 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9494 12:11:50.682834 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9495 12:11:50.690068 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9496 12:11:50.692936 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9497 12:11:50.699181 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9498 12:11:50.702200 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9499 12:11:50.706062 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9500 12:11:50.712457 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9501 12:11:50.716279 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9502 12:11:50.722240 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9503 12:11:50.725937 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9504 12:11:50.728920 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9505 12:11:50.736014 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9506 12:11:50.738815 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9507 12:11:50.745650 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9508 12:11:50.749631 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9509 12:11:50.752606 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9510 12:11:50.759066 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9511 12:11:50.762032 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9512 12:11:50.769161 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9513 12:11:50.771950 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9514 12:11:50.775182 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9515 12:11:50.782556 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9516 12:11:50.785345 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9517 12:11:50.791943 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9518 12:11:50.794608 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9519 12:11:50.801085 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9520 12:11:50.805241 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9521 12:11:50.811622 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9522 12:11:50.815007 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9523 12:11:50.818014 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9524 12:11:50.824964 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9525 12:11:50.827552 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9526 12:11:50.834801 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9527 12:11:50.837669 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9528 12:11:50.840888 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9529 12:11:50.848066 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9530 12:11:50.851092 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9531 12:11:50.857921 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9532 12:11:50.860859 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9533 12:11:50.864197 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9534 12:11:50.870834 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9535 12:11:50.874543 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9536 12:11:50.880535 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9537 12:11:50.884584 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9538 12:11:50.890160 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9539 12:11:50.893664 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9540 12:11:50.897311 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9541 12:11:50.903587 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9542 12:11:50.906908 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9543 12:11:50.913635 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9544 12:11:50.917201 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9545 12:11:50.923452 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9546 12:11:50.926733 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9547 12:11:50.930249 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9548 12:11:50.937173 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9549 12:11:50.940550 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9550 12:11:50.947490 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9551 12:11:50.950517 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9552 12:11:50.957076 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9553 12:11:50.960306 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9554 12:11:50.963496 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9555 12:11:50.969932 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9556 12:11:50.972863 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9557 12:11:50.981476 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9558 12:11:50.984291 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9559 12:11:50.989807 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9560 12:11:50.993020 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9561 12:11:50.999180 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9562 12:11:51.002999 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9563 12:11:51.006788 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9564 12:11:51.013674 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9565 12:11:51.016771 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9566 12:11:51.022690 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9567 12:11:51.025674 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9568 12:11:51.032345 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9569 12:11:51.035869 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9570 12:11:51.039203 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9571 12:11:51.045857 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9572 12:11:51.049242 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9573 12:11:51.056046 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9574 12:11:51.059119 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9575 12:11:51.065986 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9576 12:11:51.069642 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9577 12:11:51.075915 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9578 12:11:51.079278 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9579 12:11:51.081832 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9580 12:11:51.089373 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9581 12:11:51.091636 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9582 12:11:51.098215 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9583 12:11:51.101742 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9584 12:11:51.108482 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9585 12:11:51.112156 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9586 12:11:51.118784 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9587 12:11:51.122071 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9588 12:11:51.125076 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9589 12:11:51.132026 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9590 12:11:51.135018 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9591 12:11:51.141207 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9592 12:11:51.144500 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9593 12:11:51.151605 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9594 12:11:51.154602 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9595 12:11:51.158482 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9596 12:11:51.164289 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9597 12:11:51.168666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9598 12:11:51.174667 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9599 12:11:51.177262 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9600 12:11:51.184666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9601 12:11:51.188072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9602 12:11:51.194282 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9603 12:11:51.197564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9604 12:11:51.204552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9605 12:11:51.208300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9606 12:11:51.214186 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9607 12:11:51.216916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9608 12:11:51.224038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9609 12:11:51.227801 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9610 12:11:51.233786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9611 12:11:51.236932 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9612 12:11:51.244307 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9613 12:11:51.246805 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9614 12:11:51.254155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9615 12:11:51.256969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9616 12:11:51.263313 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9617 12:11:51.266789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9618 12:11:51.273134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9619 12:11:51.276741 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9620 12:11:51.283799 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9621 12:11:51.286921 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9622 12:11:51.293349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9623 12:11:51.296990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9624 12:11:51.304564 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9625 12:11:51.306653 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9626 12:11:51.312754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9627 12:11:51.316215 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9628 12:11:51.319504 INFO: [APUAPC] vio 0
9629 12:11:51.323065 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9630 12:11:51.329246 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9631 12:11:51.332735 INFO: [APUAPC] D0_APC_0: 0x400510
9632 12:11:51.335974 INFO: [APUAPC] D0_APC_1: 0x0
9633 12:11:51.336440 INFO: [APUAPC] D0_APC_2: 0x1540
9634 12:11:51.339643 INFO: [APUAPC] D0_APC_3: 0x0
9635 12:11:51.343198 INFO: [APUAPC] D1_APC_0: 0xffffffff
9636 12:11:51.345984 INFO: [APUAPC] D1_APC_1: 0xffffffff
9637 12:11:51.349247 INFO: [APUAPC] D1_APC_2: 0x3fffff
9638 12:11:51.352280 INFO: [APUAPC] D1_APC_3: 0x0
9639 12:11:51.356486 INFO: [APUAPC] D2_APC_0: 0xffffffff
9640 12:11:51.359250 INFO: [APUAPC] D2_APC_1: 0xffffffff
9641 12:11:51.362454 INFO: [APUAPC] D2_APC_2: 0x3fffff
9642 12:11:51.366354 INFO: [APUAPC] D2_APC_3: 0x0
9643 12:11:51.368984 INFO: [APUAPC] D3_APC_0: 0xffffffff
9644 12:11:51.372185 INFO: [APUAPC] D3_APC_1: 0xffffffff
9645 12:11:51.375806 INFO: [APUAPC] D3_APC_2: 0x3fffff
9646 12:11:51.378690 INFO: [APUAPC] D3_APC_3: 0x0
9647 12:11:51.382352 INFO: [APUAPC] D4_APC_0: 0xffffffff
9648 12:11:51.385308 INFO: [APUAPC] D4_APC_1: 0xffffffff
9649 12:11:51.389060 INFO: [APUAPC] D4_APC_2: 0x3fffff
9650 12:11:51.392581 INFO: [APUAPC] D4_APC_3: 0x0
9651 12:11:51.395511 INFO: [APUAPC] D5_APC_0: 0xffffffff
9652 12:11:51.398624 INFO: [APUAPC] D5_APC_1: 0xffffffff
9653 12:11:51.402108 INFO: [APUAPC] D5_APC_2: 0x3fffff
9654 12:11:51.404881 INFO: [APUAPC] D5_APC_3: 0x0
9655 12:11:51.408645 INFO: [APUAPC] D6_APC_0: 0xffffffff
9656 12:11:51.412145 INFO: [APUAPC] D6_APC_1: 0xffffffff
9657 12:11:51.415165 INFO: [APUAPC] D6_APC_2: 0x3fffff
9658 12:11:51.419095 INFO: [APUAPC] D6_APC_3: 0x0
9659 12:11:51.422260 INFO: [APUAPC] D7_APC_0: 0xffffffff
9660 12:11:51.425924 INFO: [APUAPC] D7_APC_1: 0xffffffff
9661 12:11:51.428378 INFO: [APUAPC] D7_APC_2: 0x3fffff
9662 12:11:51.432381 INFO: [APUAPC] D7_APC_3: 0x0
9663 12:11:51.435657 INFO: [APUAPC] D8_APC_0: 0xffffffff
9664 12:11:51.438218 INFO: [APUAPC] D8_APC_1: 0xffffffff
9665 12:11:51.441663 INFO: [APUAPC] D8_APC_2: 0x3fffff
9666 12:11:51.444866 INFO: [APUAPC] D8_APC_3: 0x0
9667 12:11:51.448368 INFO: [APUAPC] D9_APC_0: 0xffffffff
9668 12:11:51.451766 INFO: [APUAPC] D9_APC_1: 0xffffffff
9669 12:11:51.454874 INFO: [APUAPC] D9_APC_2: 0x3fffff
9670 12:11:51.458354 INFO: [APUAPC] D9_APC_3: 0x0
9671 12:11:51.461375 INFO: [APUAPC] D10_APC_0: 0xffffffff
9672 12:11:51.465233 INFO: [APUAPC] D10_APC_1: 0xffffffff
9673 12:11:51.469119 INFO: [APUAPC] D10_APC_2: 0x3fffff
9674 12:11:51.471335 INFO: [APUAPC] D10_APC_3: 0x0
9675 12:11:51.475119 INFO: [APUAPC] D11_APC_0: 0xffffffff
9676 12:11:51.477775 INFO: [APUAPC] D11_APC_1: 0xffffffff
9677 12:11:51.480949 INFO: [APUAPC] D11_APC_2: 0x3fffff
9678 12:11:51.484928 INFO: [APUAPC] D11_APC_3: 0x0
9679 12:11:51.488452 INFO: [APUAPC] D12_APC_0: 0xffffffff
9680 12:11:51.491640 INFO: [APUAPC] D12_APC_1: 0xffffffff
9681 12:11:51.494443 INFO: [APUAPC] D12_APC_2: 0x3fffff
9682 12:11:51.497696 INFO: [APUAPC] D12_APC_3: 0x0
9683 12:11:51.500762 INFO: [APUAPC] D13_APC_0: 0xffffffff
9684 12:11:51.505329 INFO: [APUAPC] D13_APC_1: 0xffffffff
9685 12:11:51.508559 INFO: [APUAPC] D13_APC_2: 0x3fffff
9686 12:11:51.511505 INFO: [APUAPC] D13_APC_3: 0x0
9687 12:11:51.514257 INFO: [APUAPC] D14_APC_0: 0xffffffff
9688 12:11:51.518279 INFO: [APUAPC] D14_APC_1: 0xffffffff
9689 12:11:51.520869 INFO: [APUAPC] D14_APC_2: 0x3fffff
9690 12:11:51.524297 INFO: [APUAPC] D14_APC_3: 0x0
9691 12:11:51.527526 INFO: [APUAPC] D15_APC_0: 0xffffffff
9692 12:11:51.532413 INFO: [APUAPC] D15_APC_1: 0xffffffff
9693 12:11:51.533939 INFO: [APUAPC] D15_APC_2: 0x3fffff
9694 12:11:51.537349 INFO: [APUAPC] D15_APC_3: 0x0
9695 12:11:51.540829 INFO: [APUAPC] APC_CON: 0x4
9696 12:11:51.544076 INFO: [NOCDAPC] D0_APC_0: 0x0
9697 12:11:51.547077 INFO: [NOCDAPC] D0_APC_1: 0x0
9698 12:11:51.551087 INFO: [NOCDAPC] D1_APC_0: 0x0
9699 12:11:51.553972 INFO: [NOCDAPC] D1_APC_1: 0xfff
9700 12:11:51.554614 INFO: [NOCDAPC] D2_APC_0: 0x0
9701 12:11:51.556830 INFO: [NOCDAPC] D2_APC_1: 0xfff
9702 12:11:51.560005 INFO: [NOCDAPC] D3_APC_0: 0x0
9703 12:11:51.564199 INFO: [NOCDAPC] D3_APC_1: 0xfff
9704 12:11:51.567480 INFO: [NOCDAPC] D4_APC_0: 0x0
9705 12:11:51.570080 INFO: [NOCDAPC] D4_APC_1: 0xfff
9706 12:11:51.573411 INFO: [NOCDAPC] D5_APC_0: 0x0
9707 12:11:51.577156 INFO: [NOCDAPC] D5_APC_1: 0xfff
9708 12:11:51.580560 INFO: [NOCDAPC] D6_APC_0: 0x0
9709 12:11:51.583507 INFO: [NOCDAPC] D6_APC_1: 0xfff
9710 12:11:51.586788 INFO: [NOCDAPC] D7_APC_0: 0x0
9711 12:11:51.587354 INFO: [NOCDAPC] D7_APC_1: 0xfff
9712 12:11:51.590707 INFO: [NOCDAPC] D8_APC_0: 0x0
9713 12:11:51.593668 INFO: [NOCDAPC] D8_APC_1: 0xfff
9714 12:11:51.596964 INFO: [NOCDAPC] D9_APC_0: 0x0
9715 12:11:51.600044 INFO: [NOCDAPC] D9_APC_1: 0xfff
9716 12:11:51.603513 INFO: [NOCDAPC] D10_APC_0: 0x0
9717 12:11:51.607735 INFO: [NOCDAPC] D10_APC_1: 0xfff
9718 12:11:51.610953 INFO: [NOCDAPC] D11_APC_0: 0x0
9719 12:11:51.613105 INFO: [NOCDAPC] D11_APC_1: 0xfff
9720 12:11:51.616530 INFO: [NOCDAPC] D12_APC_0: 0x0
9721 12:11:51.620401 INFO: [NOCDAPC] D12_APC_1: 0xfff
9722 12:11:51.624013 INFO: [NOCDAPC] D13_APC_0: 0x0
9723 12:11:51.626272 INFO: [NOCDAPC] D13_APC_1: 0xfff
9724 12:11:51.629544 INFO: [NOCDAPC] D14_APC_0: 0x0
9725 12:11:51.630016 INFO: [NOCDAPC] D14_APC_1: 0xfff
9726 12:11:51.633368 INFO: [NOCDAPC] D15_APC_0: 0x0
9727 12:11:51.636657 INFO: [NOCDAPC] D15_APC_1: 0xfff
9728 12:11:51.641038 INFO: [NOCDAPC] APC_CON: 0x4
9729 12:11:51.644172 INFO: [APUAPC] set_apusys_apc done
9730 12:11:51.646642 INFO: [DEVAPC] devapc_init done
9731 12:11:51.652596 INFO: GICv3 without legacy support detected.
9732 12:11:51.656360 INFO: ARM GICv3 driver initialized in EL3
9733 12:11:51.659809 INFO: Maximum SPI INTID supported: 639
9734 12:11:51.662734 INFO: BL31: Initializing runtime services
9735 12:11:51.669680 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9736 12:11:51.672362 INFO: SPM: enable CPC mode
9737 12:11:51.675464 INFO: mcdi ready for mcusys-off-idle and system suspend
9738 12:11:51.682843 INFO: BL31: Preparing for EL3 exit to normal world
9739 12:11:51.685595 INFO: Entry point address = 0x80000000
9740 12:11:51.686113 INFO: SPSR = 0x8
9741 12:11:51.692545
9742 12:11:51.693163
9743 12:11:51.693543
9744 12:11:51.696603 Starting depthcharge on Spherion...
9745 12:11:51.697256
9746 12:11:51.697640 Wipe memory regions:
9747 12:11:51.697992
9748 12:11:51.700579 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9749 12:11:51.701176 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9750 12:11:51.701628 Setting prompt string to ['asurada:']
9751 12:11:51.702082 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9752 12:11:51.702831 [0x00000040000000, 0x00000054600000)
9753 12:11:51.821358
9754 12:11:51.821926 [0x00000054660000, 0x00000080000000)
9755 12:11:52.082277
9756 12:11:52.082838 [0x000000821a7280, 0x000000ffe64000)
9757 12:11:52.826831
9758 12:11:52.827384 [0x00000100000000, 0x00000140000000)
9759 12:11:53.208119
9760 12:11:53.211444 Initializing XHCI USB controller at 0x11200000.
9761 12:11:54.249186
9762 12:11:54.252846 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9763 12:11:54.253404
9764 12:11:54.253783
9765 12:11:54.254134
9766 12:11:54.254960 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9768 12:11:54.356355 asurada: tftpboot 192.168.201.1 12669492/tftp-deploy-mt3j961u/kernel/image.itb 12669492/tftp-deploy-mt3j961u/kernel/cmdline
9769 12:11:54.357064 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9770 12:11:54.357586 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9771 12:11:54.362297 tftpboot 192.168.201.1 12669492/tftp-deploy-mt3j961u/kernel/image.ittp-deploy-mt3j961u/kernel/cmdline
9772 12:11:54.362872
9773 12:11:54.363249 Waiting for link
9774 12:11:54.523111
9775 12:11:54.523676 R8152: Initializing
9776 12:11:54.524057
9777 12:11:54.526467 Version 9 (ocp_data = 6010)
9778 12:11:54.527030
9779 12:11:54.529591 R8152: Done initializing
9780 12:11:54.530082
9781 12:11:54.530461 Adding net device
9782 12:11:56.468329
9783 12:11:56.469262 done.
9784 12:11:56.469949
9785 12:11:56.470417 MAC: 00:e0:4c:68:03:bd
9786 12:11:56.470786
9787 12:11:56.471459 Sending DHCP discover... done.
9788 12:11:56.471817
9789 12:11:56.473517 Waiting for reply... done.
9790 12:11:56.473974
9791 12:11:56.476668 Sending DHCP request... done.
9792 12:11:56.476811
9793 12:11:56.483926 Waiting for reply... done.
9794 12:11:56.484088
9795 12:11:56.484179 My ip is 192.168.201.16
9796 12:11:56.484259
9797 12:11:56.485481 The DHCP server ip is 192.168.201.1
9798 12:11:56.485581
9799 12:11:56.492589 TFTP server IP predefined by user: 192.168.201.1
9800 12:11:56.492733
9801 12:11:56.498740 Bootfile predefined by user: 12669492/tftp-deploy-mt3j961u/kernel/image.itb
9802 12:11:56.498932
9803 12:11:56.499033 Sending tftp read request... done.
9804 12:11:56.502353
9805 12:11:56.506171 Waiting for the transfer...
9806 12:11:56.506405
9807 12:11:56.804583 00000000 ################################################################
9808 12:11:56.804746
9809 12:11:57.095803 00080000 ################################################################
9810 12:11:57.095941
9811 12:11:57.394218 00100000 ################################################################
9812 12:11:57.394359
9813 12:11:57.693586 00180000 ################################################################
9814 12:11:57.693722
9815 12:11:57.991380 00200000 ################################################################
9816 12:11:57.991526
9817 12:11:58.291530 00280000 ################################################################
9818 12:11:58.291669
9819 12:11:58.592681 00300000 ################################################################
9820 12:11:58.592830
9821 12:11:58.887540 00380000 ################################################################
9822 12:11:58.887681
9823 12:11:59.184668 00400000 ################################################################
9824 12:11:59.184831
9825 12:11:59.477964 00480000 ################################################################
9826 12:11:59.478107
9827 12:11:59.861076 00500000 ################################################################
9828 12:11:59.861644
9829 12:12:00.245235 00580000 ################################################################
9830 12:12:00.245759
9831 12:12:00.627636 00600000 ################################################################
9832 12:12:00.628164
9833 12:12:01.014330 00680000 ################################################################
9834 12:12:01.014843
9835 12:12:01.401236 00700000 ################################################################
9836 12:12:01.401756
9837 12:12:01.732297 00780000 ################################################################
9838 12:12:01.732442
9839 12:12:02.017734 00800000 ################################################################
9840 12:12:02.017869
9841 12:12:02.304815 00880000 ################################################################
9842 12:12:02.304949
9843 12:12:02.605696 00900000 ################################################################
9844 12:12:02.605828
9845 12:12:02.888903 00980000 ################################################################
9846 12:12:02.889037
9847 12:12:03.194505 00a00000 ################################################################
9848 12:12:03.194713
9849 12:12:03.562526 00a80000 ################################################################
9850 12:12:03.563021
9851 12:12:03.906657 00b00000 ################################################################
9852 12:12:03.906788
9853 12:12:04.194203 00b80000 ################################################################
9854 12:12:04.194334
9855 12:12:04.480087 00c00000 ################################################################
9856 12:12:04.480223
9857 12:12:04.769636 00c80000 ################################################################
9858 12:12:04.769779
9859 12:12:05.059551 00d00000 ################################################################
9860 12:12:05.059679
9861 12:12:05.351900 00d80000 ################################################################
9862 12:12:05.352039
9863 12:12:05.637600 00e00000 ################################################################
9864 12:12:05.637743
9865 12:12:05.904932 00e80000 ################################################################
9866 12:12:05.905086
9867 12:12:06.157570 00f00000 ################################################################
9868 12:12:06.157712
9869 12:12:06.408279 00f80000 ################################################################
9870 12:12:06.408413
9871 12:12:06.659172 01000000 ################################################################
9872 12:12:06.659318
9873 12:12:06.910189 01080000 ################################################################
9874 12:12:06.910351
9875 12:12:07.183034 01100000 ################################################################
9876 12:12:07.183185
9877 12:12:07.483101 01180000 ################################################################
9878 12:12:07.483240
9879 12:12:07.819114 01200000 ################################################################
9880 12:12:07.819632
9881 12:12:08.125627 01280000 ################################################################
9882 12:12:08.125768
9883 12:12:08.427483 01300000 ################################################################
9884 12:12:08.427627
9885 12:12:08.722478 01380000 ################################################################
9886 12:12:08.722623
9887 12:12:09.003019 01400000 ################################################################
9888 12:12:09.003156
9889 12:12:09.355410 01480000 ################################################################
9890 12:12:09.355984
9891 12:12:09.736116 01500000 ################################################################
9892 12:12:09.736636
9893 12:12:10.047907 01580000 ################################################################
9894 12:12:10.048062
9895 12:12:10.329093 01600000 ################################################################
9896 12:12:10.329235
9897 12:12:10.609988 01680000 ################################################################
9898 12:12:10.610129
9899 12:12:10.890199 01700000 ################################################################
9900 12:12:10.890340
9901 12:12:11.176505 01780000 ################################################################
9902 12:12:11.176643
9903 12:12:11.463613 01800000 ################################################################
9904 12:12:11.463760
9905 12:12:11.779315 01880000 ################################################################
9906 12:12:11.779598
9907 12:12:12.122014 01900000 ################################################################
9908 12:12:12.122512
9909 12:12:12.501715 01980000 ################################################################
9910 12:12:12.502264
9911 12:12:12.883003 01a00000 ################################################################
9912 12:12:12.883607
9913 12:12:13.217630 01a80000 ################################################################
9914 12:12:13.217777
9915 12:12:13.509112 01b00000 ################################################################
9916 12:12:13.509256
9917 12:12:13.773496 01b80000 ################################################################
9918 12:12:13.773641
9919 12:12:14.024340 01c00000 ################################################################
9920 12:12:14.024485
9921 12:12:14.275491 01c80000 ################################################################
9922 12:12:14.275657
9923 12:12:14.526359 01d00000 ################################################################
9924 12:12:14.526504
9925 12:12:14.811068 01d80000 ################################################################
9926 12:12:14.811212
9927 12:12:15.106041 01e00000 ################################################################
9928 12:12:15.106219
9929 12:12:15.377417 01e80000 ################################################################
9930 12:12:15.377566
9931 12:12:15.634814 01f00000 ################################################################
9932 12:12:15.634963
9933 12:12:15.926463 01f80000 ################################################################
9934 12:12:15.926607
9935 12:12:16.211266 02000000 ################################################################
9936 12:12:16.211415
9937 12:12:16.493575 02080000 ################################################################
9938 12:12:16.493726
9939 12:12:16.784260 02100000 ################################################################
9940 12:12:16.784410
9941 12:12:17.038809 02180000 ################################################################
9942 12:12:17.038958
9943 12:12:17.309419 02200000 ################################################################
9944 12:12:17.309573
9945 12:12:17.589943 02280000 ################################################################
9946 12:12:17.590086
9947 12:12:17.869373 02300000 ################################################################
9948 12:12:17.869522
9949 12:12:18.162779 02380000 ################################################################
9950 12:12:18.162946
9951 12:12:18.455960 02400000 ################################################################
9952 12:12:18.456106
9953 12:12:18.710792 02480000 ################################################################
9954 12:12:18.710949
9955 12:12:18.962663 02500000 ################################################################
9956 12:12:18.962812
9957 12:12:19.217321 02580000 ################################################################
9958 12:12:19.217474
9959 12:12:19.489557 02600000 ################################################################
9960 12:12:19.489705
9961 12:12:19.749087 02680000 ################################################################
9962 12:12:19.749235
9963 12:12:20.003282 02700000 ################################################################
9964 12:12:20.003430
9965 12:12:20.272967 02780000 ################################################################
9966 12:12:20.273111
9967 12:12:20.563073 02800000 ################################################################
9968 12:12:20.563222
9969 12:12:20.851342 02880000 ################################################################
9970 12:12:20.851497
9971 12:12:21.147185 02900000 ################################################################
9972 12:12:21.147334
9973 12:12:21.443603 02980000 ################################################################
9974 12:12:21.443756
9975 12:12:21.733771 02a00000 ################################################################
9976 12:12:21.733910
9977 12:12:21.977969 02a80000 ################################################################
9978 12:12:21.978123
9979 12:12:22.251787 02b00000 ################################################################
9980 12:12:22.251998
9981 12:12:22.532118 02b80000 ################################################################
9982 12:12:22.532265
9983 12:12:22.797258 02c00000 ################################################################
9984 12:12:22.797401
9985 12:12:23.089514 02c80000 ################################################################
9986 12:12:23.089715
9987 12:12:23.365784 02d00000 ################################################################
9988 12:12:23.365928
9989 12:12:23.637938 02d80000 ################################################################
9990 12:12:23.638143
9991 12:12:23.935460 02e00000 ################################################################
9992 12:12:23.935666
9993 12:12:24.209436 02e80000 ################################################################
9994 12:12:24.209583
9995 12:12:24.497472 02f00000 ################################################################
9996 12:12:24.497622
9997 12:12:24.785535 02f80000 ################################################################
9998 12:12:24.785688
9999 12:12:25.072137 03000000 ################################################################
10000 12:12:25.072283
10001 12:12:25.357766 03080000 ################################################################
10002 12:12:25.357917
10003 12:12:25.656876 03100000 ################################################################
10004 12:12:25.657026
10005 12:12:25.951838 03180000 ################################################################
10006 12:12:25.952033
10007 12:12:26.234803 03200000 ################################################################
10008 12:12:26.234951
10009 12:12:26.528152 03280000 ################################################################
10010 12:12:26.528321
10011 12:12:26.823743 03300000 ################################################################
10012 12:12:26.823887
10013 12:12:27.088182 03380000 ################################################################
10014 12:12:27.088332
10015 12:12:27.338323 03400000 ################################################################
10016 12:12:27.338470
10017 12:12:27.592604 03480000 ################################################################
10018 12:12:27.592812
10019 12:12:27.844436 03500000 ################################################################
10020 12:12:27.844585
10021 12:12:28.097140 03580000 ################################################################
10022 12:12:28.097289
10023 12:12:28.357621 03600000 ################################################################
10024 12:12:28.357774
10025 12:12:28.607119 03680000 ################################################################
10026 12:12:28.607288
10027 12:12:28.860487 03700000 ################################################################
10028 12:12:28.860661
10029 12:12:29.110142 03780000 ################################################################
10030 12:12:29.110291
10031 12:12:29.371501 03800000 ################################################################
10032 12:12:29.371673
10033 12:12:29.620546 03880000 ################################################################
10034 12:12:29.620740
10035 12:12:29.871159 03900000 ################################################################
10036 12:12:29.871311
10037 12:12:30.117716 03980000 ################################################################
10038 12:12:30.117867
10039 12:12:30.365232 03a00000 ################################################################
10040 12:12:30.365386
10041 12:12:30.612126 03a80000 ################################################################
10042 12:12:30.612279
10043 12:12:30.869615 03b00000 ################################################################
10044 12:12:30.869765
10045 12:12:31.120475 03b80000 ################################################################
10046 12:12:31.120617
10047 12:12:31.374484 03c00000 ################################################################
10048 12:12:31.374631
10049 12:12:31.622881 03c80000 ################################################################
10050 12:12:31.623050
10051 12:12:31.871956 03d00000 ################################################################
10052 12:12:31.872142
10053 12:12:32.123999 03d80000 ################################################################
10054 12:12:32.124177
10055 12:12:32.371603 03e00000 ################################################################
10056 12:12:32.371746
10057 12:12:32.626741 03e80000 ################################################################
10058 12:12:32.626913
10059 12:12:32.879419 03f00000 ################################################################
10060 12:12:32.879567
10061 12:12:33.136664 03f80000 ################################################################
10062 12:12:33.136849
10063 12:12:33.397209 04000000 ################################################################
10064 12:12:33.397356
10065 12:12:33.649635 04080000 ################################################################
10066 12:12:33.649785
10067 12:12:33.828489 04100000 ############################################## done.
10068 12:12:33.828633
10069 12:12:33.832199 The bootfile was 68528354 bytes long.
10070 12:12:33.832285
10071 12:12:33.834373 Sending tftp read request... done.
10072 12:12:33.834456
10073 12:12:33.837756 Waiting for the transfer...
10074 12:12:33.837845
10075 12:12:33.837915 00000000 # done.
10076 12:12:33.837983
10077 12:12:33.848003 Command line loaded dynamically from TFTP file: 12669492/tftp-deploy-mt3j961u/kernel/cmdline
10078 12:12:33.848173
10079 12:12:33.861133 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10080 12:12:33.861272
10081 12:12:33.861380 Loading FIT.
10082 12:12:33.861481
10083 12:12:33.864724 Image ramdisk-1 has 56431759 bytes.
10084 12:12:33.864889
10085 12:12:33.867765 Image fdt-1 has 47278 bytes.
10086 12:12:33.867917
10087 12:12:33.871909 Image kernel-1 has 12047284 bytes.
10088 12:12:33.872172
10089 12:12:33.880626 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10090 12:12:33.880781
10091 12:12:33.897552 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10092 12:12:33.898036
10093 12:12:33.901518 Choosing best match conf-1 for compat google,spherion-rev3.
10094 12:12:33.907080
10095 12:12:33.911260 Connected to device vid:did:rid of 1ae0:0028:00
10096 12:12:33.918313
10097 12:12:33.921216 tpm_get_response: command 0x17b, return code 0x0
10098 12:12:33.921641
10099 12:12:33.924275 ec_init: CrosEC protocol v3 supported (256, 248)
10100 12:12:33.929036
10101 12:12:33.932332 tpm_cleanup: add release locality here.
10102 12:12:33.933045
10103 12:12:33.933606 Shutting down all USB controllers.
10104 12:12:33.937096
10105 12:12:33.937484 Removing current net device
10106 12:12:33.937831
10107 12:12:33.942509 Exiting depthcharge with code 4 at timestamp: 70497168
10108 12:12:33.942983
10109 12:12:33.945873 LZMA decompressing kernel-1 to 0x821a6718
10110 12:12:33.946390
10111 12:12:33.948861 LZMA decompressing kernel-1 to 0x40000000
10112 12:12:35.446327
10113 12:12:35.446526 jumping to kernel
10114 12:12:35.447323 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10115 12:12:35.447464 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10116 12:12:35.447581 Setting prompt string to ['Linux version [0-9]']
10117 12:12:35.447688 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10118 12:12:35.447792 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10119 12:12:35.496583
10120 12:12:35.500157 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10121 12:12:35.504963 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10122 12:12:35.505154 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10123 12:12:35.505294 Setting prompt string to []
10124 12:12:35.505448 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10125 12:12:35.505588 Using line separator: #'\n'#
10126 12:12:35.505705 No login prompt set.
10127 12:12:35.505823 Parsing kernel messages
10128 12:12:35.505931 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10129 12:12:35.506118 [login-action] Waiting for messages, (timeout 00:03:42)
10130 12:12:35.523131 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j93261-arm64-gcc-10-defconfig-arm64-chromebook-cwjwh) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024
10131 12:12:35.526247 [ 0.000000] random: crng init done
10132 12:12:35.532536 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10133 12:12:35.536116 [ 0.000000] efi: UEFI not found.
10134 12:12:35.542924 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10135 12:12:35.553063 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10136 12:12:35.563373 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10137 12:12:35.569348 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10138 12:12:35.575579 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10139 12:12:35.582465 [ 0.000000] printk: bootconsole [mtk8250] enabled
10140 12:12:35.588615 [ 0.000000] NUMA: No NUMA configuration found
10141 12:12:35.595751 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10142 12:12:35.603080 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10143 12:12:35.603169 [ 0.000000] Zone ranges:
10144 12:12:35.608886 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10145 12:12:35.611764 [ 0.000000] DMA32 empty
10146 12:12:35.620720 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10147 12:12:35.621720 [ 0.000000] Movable zone start for each node
10148 12:12:35.624733 [ 0.000000] Early memory node ranges
10149 12:12:35.631701 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10150 12:12:35.638030 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10151 12:12:35.644684 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10152 12:12:35.651053 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10153 12:12:35.657893 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10154 12:12:35.664256 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10155 12:12:35.695542 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10156 12:12:35.702294 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10157 12:12:35.709825 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10158 12:12:35.712617 [ 0.000000] psci: probing for conduit method from DT.
10159 12:12:35.718550 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10160 12:12:35.723188 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10161 12:12:35.728315 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10162 12:12:35.731498 [ 0.000000] psci: SMC Calling Convention v1.2
10163 12:12:35.738558 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10164 12:12:35.741493 [ 0.000000] Detected VIPT I-cache on CPU0
10165 12:12:35.748900 [ 0.000000] CPU features: detected: GIC system register CPU interface
10166 12:12:35.755008 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10167 12:12:35.761664 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10168 12:12:35.768166 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10169 12:12:35.774588 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10170 12:12:35.784544 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10171 12:12:35.787691 [ 0.000000] alternatives: applying boot alternatives
10172 12:12:35.794291 [ 0.000000] Fallback order for Node 0: 0
10173 12:12:35.800956 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10174 12:12:35.804956 [ 0.000000] Policy zone: Normal
10175 12:12:35.817255 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10176 12:12:35.829354 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10177 12:12:35.838032 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10178 12:12:35.847917 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10179 12:12:35.855253 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10180 12:12:35.857685 <6>[ 0.000000] software IO TLB: area num 8.
10181 12:12:35.913434 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10182 12:12:35.993757 <6>[ 0.000000] Memory: 3797732K/4191232K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 360732K reserved, 32768K cma-reserved)
10183 12:12:36.000756 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10184 12:12:36.007375 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10185 12:12:36.010117 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10186 12:12:36.017017 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10187 12:12:36.023610 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10188 12:12:36.026584 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10189 12:12:36.036887 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10190 12:12:36.044955 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10191 12:12:36.050073 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10192 12:12:36.056594 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10193 12:12:36.060109 <6>[ 0.000000] GICv3: 608 SPIs implemented
10194 12:12:36.063070 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10195 12:12:36.069760 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10196 12:12:36.073051 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10197 12:12:36.079570 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10198 12:12:36.092649 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10199 12:12:36.106038 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10200 12:12:36.113606 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10201 12:12:36.120299 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10202 12:12:36.133806 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10203 12:12:36.140537 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10204 12:12:36.146900 <6>[ 0.009182] Console: colour dummy device 80x25
10205 12:12:36.157693 <6>[ 0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10206 12:12:36.163410 <6>[ 0.024348] pid_max: default: 32768 minimum: 301
10207 12:12:36.166762 <6>[ 0.029249] LSM: Security Framework initializing
10208 12:12:36.173932 <6>[ 0.034192] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10209 12:12:36.184658 <6>[ 0.041798] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10210 12:12:36.190159 <6>[ 0.051020] cblist_init_generic: Setting adjustable number of callback queues.
10211 12:12:36.196809 <6>[ 0.058462] cblist_init_generic: Setting shift to 3 and lim to 1.
10212 12:12:36.206310 <6>[ 0.064800] cblist_init_generic: Setting adjustable number of callback queues.
10213 12:12:36.210110 <6>[ 0.072272] cblist_init_generic: Setting shift to 3 and lim to 1.
10214 12:12:36.216209 <6>[ 0.078673] rcu: Hierarchical SRCU implementation.
10215 12:12:36.222858 <6>[ 0.083688] rcu: Max phase no-delay instances is 1000.
10216 12:12:36.229418 <6>[ 0.090712] EFI services will not be available.
10217 12:12:36.232891 <6>[ 0.095664] smp: Bringing up secondary CPUs ...
10218 12:12:36.240633 <6>[ 0.100738] Detected VIPT I-cache on CPU1
10219 12:12:36.246994 <6>[ 0.100805] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10220 12:12:36.254086 <6>[ 0.100838] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10221 12:12:36.258720 <6>[ 0.101164] Detected VIPT I-cache on CPU2
10222 12:12:36.267173 <6>[ 0.101211] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10223 12:12:36.273484 <6>[ 0.101226] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10224 12:12:36.276670 <6>[ 0.101483] Detected VIPT I-cache on CPU3
10225 12:12:36.283639 <6>[ 0.101529] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10226 12:12:36.289885 <6>[ 0.101543] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10227 12:12:36.296955 <6>[ 0.101844] CPU features: detected: Spectre-v4
10228 12:12:36.300007 <6>[ 0.101851] CPU features: detected: Spectre-BHB
10229 12:12:36.303349 <6>[ 0.101855] Detected PIPT I-cache on CPU4
10230 12:12:36.309875 <6>[ 0.101912] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10231 12:12:36.319854 <6>[ 0.101928] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10232 12:12:36.322797 <6>[ 0.102219] Detected PIPT I-cache on CPU5
10233 12:12:36.329815 <6>[ 0.102280] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10234 12:12:36.336247 <6>[ 0.102299] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10235 12:12:36.339474 <6>[ 0.102578] Detected PIPT I-cache on CPU6
10236 12:12:36.349754 <6>[ 0.102637] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10237 12:12:36.356218 <6>[ 0.102656] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10238 12:12:36.359093 <6>[ 0.102954] Detected PIPT I-cache on CPU7
10239 12:12:36.366277 <6>[ 0.103017] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10240 12:12:36.372536 <6>[ 0.103034] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10241 12:12:36.375955 <6>[ 0.103081] smp: Brought up 1 node, 8 CPUs
10242 12:12:36.382061 <6>[ 0.244332] SMP: Total of 8 processors activated.
10243 12:12:36.389306 <6>[ 0.249283] CPU features: detected: 32-bit EL0 Support
10244 12:12:36.395675 <6>[ 0.254679] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10245 12:12:36.401848 <6>[ 0.263534] CPU features: detected: Common not Private translations
10246 12:12:36.408750 <6>[ 0.270012] CPU features: detected: CRC32 instructions
10247 12:12:36.415533 <6>[ 0.275363] CPU features: detected: RCpc load-acquire (LDAPR)
10248 12:12:36.418446 <6>[ 0.281323] CPU features: detected: LSE atomic instructions
10249 12:12:36.425645 <6>[ 0.287105] CPU features: detected: Privileged Access Never
10250 12:12:36.431533 <6>[ 0.292884] CPU features: detected: RAS Extension Support
10251 12:12:36.439068 <6>[ 0.298493] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10252 12:12:36.441734 <6>[ 0.305711] CPU: All CPU(s) started at EL2
10253 12:12:36.449335 <6>[ 0.310028] alternatives: applying system-wide alternatives
10254 12:12:36.457559 <6>[ 0.319943] devtmpfs: initialized
10255 12:12:36.472241 <6>[ 0.328231] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10256 12:12:36.480057 <6>[ 0.338190] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10257 12:12:36.483453 <6>[ 0.345825] pinctrl core: initialized pinctrl subsystem
10258 12:12:36.490599 <6>[ 0.352468] DMI not present or invalid.
10259 12:12:36.496891 <6>[ 0.356873] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10260 12:12:36.504546 <6>[ 0.363743] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10261 12:12:36.513393 <6>[ 0.371194] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10262 12:12:36.519753 <6>[ 0.379281] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10263 12:12:36.526406 <6>[ 0.387434] audit: initializing netlink subsys (disabled)
10264 12:12:36.533259 <5>[ 0.393130] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10265 12:12:36.539632 <6>[ 0.393821] thermal_sys: Registered thermal governor 'step_wise'
10266 12:12:36.546143 <6>[ 0.401095] thermal_sys: Registered thermal governor 'power_allocator'
10267 12:12:36.549362 <6>[ 0.407349] cpuidle: using governor menu
10268 12:12:36.556853 <6>[ 0.418311] NET: Registered PF_QIPCRTR protocol family
10269 12:12:36.563397 <6>[ 0.423788] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10270 12:12:36.570571 <6>[ 0.430890] ASID allocator initialised with 32768 entries
10271 12:12:36.576150 <6>[ 0.437433] Serial: AMBA PL011 UART driver
10272 12:12:36.584155 <4>[ 0.446152] Trying to register duplicate clock ID: 134
10273 12:12:36.637684 <6>[ 0.503675] KASLR enabled
10274 12:12:36.652488 <6>[ 0.511485] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10275 12:12:36.659209 <6>[ 0.518499] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10276 12:12:36.666230 <6>[ 0.524987] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10277 12:12:36.672053 <6>[ 0.531993] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10278 12:12:36.678536 <6>[ 0.538480] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10279 12:12:36.685785 <6>[ 0.545483] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10280 12:12:36.693178 <6>[ 0.551970] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10281 12:12:36.699280 <6>[ 0.558973] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10282 12:12:36.701689 <6>[ 0.566479] ACPI: Interpreter disabled.
10283 12:12:36.710373 <6>[ 0.572881] iommu: Default domain type: Translated
10284 12:12:36.717194 <6>[ 0.577993] iommu: DMA domain TLB invalidation policy: strict mode
10285 12:12:36.720119 <5>[ 0.584651] SCSI subsystem initialized
10286 12:12:36.726890 <6>[ 0.588814] usbcore: registered new interface driver usbfs
10287 12:12:36.734085 <6>[ 0.594547] usbcore: registered new interface driver hub
10288 12:12:36.736897 <6>[ 0.600097] usbcore: registered new device driver usb
10289 12:12:36.743773 <6>[ 0.606198] pps_core: LinuxPPS API ver. 1 registered
10290 12:12:36.753852 <6>[ 0.611391] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10291 12:12:36.758579 <6>[ 0.620737] PTP clock support registered
10292 12:12:36.760853 <6>[ 0.624978] EDAC MC: Ver: 3.0.0
10293 12:12:36.767564 <6>[ 0.630125] FPGA manager framework
10294 12:12:36.774518 <6>[ 0.633804] Advanced Linux Sound Architecture Driver Initialized.
10295 12:12:36.778467 <6>[ 0.640584] vgaarb: loaded
10296 12:12:36.784107 <6>[ 0.643731] clocksource: Switched to clocksource arch_sys_counter
10297 12:12:36.787338 <5>[ 0.650170] VFS: Disk quotas dquot_6.6.0
10298 12:12:36.794140 <6>[ 0.654355] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10299 12:12:36.798604 <6>[ 0.661545] pnp: PnP ACPI: disabled
10300 12:12:36.806432 <6>[ 0.668277] NET: Registered PF_INET protocol family
10301 12:12:36.812323 <6>[ 0.673655] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10302 12:12:36.824436 <6>[ 0.683672] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10303 12:12:36.834418 <6>[ 0.692455] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10304 12:12:36.841080 <6>[ 0.700420] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10305 12:12:36.847434 <6>[ 0.708821] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10306 12:12:36.859870 <6>[ 0.717478] TCP: Hash tables configured (established 32768 bind 32768)
10307 12:12:36.865000 <6>[ 0.724338] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10308 12:12:36.872037 <6>[ 0.731358] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10309 12:12:36.878189 <6>[ 0.738876] NET: Registered PF_UNIX/PF_LOCAL protocol family
10310 12:12:36.884642 <6>[ 0.745012] RPC: Registered named UNIX socket transport module.
10311 12:12:36.887919 <6>[ 0.751165] RPC: Registered udp transport module.
10312 12:12:36.894498 <6>[ 0.756097] RPC: Registered tcp transport module.
10313 12:12:36.902391 <6>[ 0.761030] RPC: Registered tcp NFSv4.1 backchannel transport module.
10314 12:12:36.904164 <6>[ 0.767698] PCI: CLS 0 bytes, default 64
10315 12:12:36.907721 <6>[ 0.772093] Unpacking initramfs...
10316 12:12:36.918171 <6>[ 0.775819] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10317 12:12:36.924317 <6>[ 0.784463] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10318 12:12:36.930879 <6>[ 0.793302] kvm [1]: IPA Size Limit: 40 bits
10319 12:12:36.934450 <6>[ 0.797827] kvm [1]: GICv3: no GICV resource entry
10320 12:12:36.940801 <6>[ 0.802849] kvm [1]: disabling GICv2 emulation
10321 12:12:36.947511 <6>[ 0.807536] kvm [1]: GIC system register CPU interface enabled
10322 12:12:36.951247 <6>[ 0.813704] kvm [1]: vgic interrupt IRQ18
10323 12:12:36.957592 <6>[ 0.819780] kvm [1]: VHE mode initialized successfully
10324 12:12:36.964006 <5>[ 0.826180] Initialise system trusted keyrings
10325 12:12:36.971157 <6>[ 0.831010] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10326 12:12:36.978920 <6>[ 0.841010] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10327 12:12:36.985314 <5>[ 0.847382] NFS: Registering the id_resolver key type
10328 12:12:36.988657 <5>[ 0.852691] Key type id_resolver registered
10329 12:12:36.995124 <5>[ 0.857110] Key type id_legacy registered
10330 12:12:37.001871 <6>[ 0.861395] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10331 12:12:37.008405 <6>[ 0.868314] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10332 12:12:37.014720 <6>[ 0.876047] 9p: Installing v9fs 9p2000 file system support
10333 12:12:37.051040 <5>[ 0.913490] Key type asymmetric registered
10334 12:12:37.054155 <5>[ 0.917824] Asymmetric key parser 'x509' registered
10335 12:12:37.064089 <6>[ 0.922968] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10336 12:12:37.067919 <6>[ 0.930584] io scheduler mq-deadline registered
10337 12:12:37.070729 <6>[ 0.935345] io scheduler kyber registered
10338 12:12:37.090327 <6>[ 0.952629] EINJ: ACPI disabled.
10339 12:12:37.122181 <4>[ 0.978094] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10340 12:12:37.132454 <4>[ 0.988712] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10341 12:12:37.146983 <6>[ 1.009195] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10342 12:12:37.154740 <6>[ 1.017160] printk: console [ttyS0] disabled
10343 12:12:37.182857 <6>[ 1.041835] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10344 12:12:37.189227 <6>[ 1.051315] printk: console [ttyS0] enabled
10345 12:12:37.192430 <6>[ 1.051315] printk: console [ttyS0] enabled
10346 12:12:37.199673 <6>[ 1.060233] printk: bootconsole [mtk8250] disabled
10347 12:12:37.203077 <6>[ 1.060233] printk: bootconsole [mtk8250] disabled
10348 12:12:37.209429 <6>[ 1.071539] SuperH (H)SCI(F) driver initialized
10349 12:12:37.212680 <6>[ 1.076819] msm_serial: driver initialized
10350 12:12:37.227230 <6>[ 1.085791] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10351 12:12:37.236662 <6>[ 1.094344] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10352 12:12:37.243793 <6>[ 1.102887] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10353 12:12:37.253552 <6>[ 1.111516] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10354 12:12:37.260509 <6>[ 1.120227] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10355 12:12:37.270738 <6>[ 1.128940] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10356 12:12:37.280486 <6>[ 1.137481] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10357 12:12:37.286491 <6>[ 1.146284] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10358 12:12:37.296181 <6>[ 1.154827] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10359 12:12:37.307654 <6>[ 1.170339] loop: module loaded
10360 12:12:37.314912 <6>[ 1.176331] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10361 12:12:37.336998 <4>[ 1.199486] mtk-pmic-keys: Failed to locate of_node [id: -1]
10362 12:12:37.344773 <6>[ 1.206318] megasas: 07.719.03.00-rc1
10363 12:12:37.354095 <6>[ 1.215873] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10364 12:12:37.361584 <6>[ 1.223132] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10365 12:12:37.377471 <6>[ 1.239077] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10366 12:12:37.433020 <6>[ 1.288308] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10367 12:12:39.308392 <6>[ 3.170481] Freeing initrd memory: 55108K
10368 12:12:39.318532 <6>[ 3.181101] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10369 12:12:39.329032 <6>[ 3.191992] tun: Universal TUN/TAP device driver, 1.6
10370 12:12:39.332784 <6>[ 3.198045] thunder_xcv, ver 1.0
10371 12:12:39.336369 <6>[ 3.201551] thunder_bgx, ver 1.0
10372 12:12:39.339220 <6>[ 3.205070] nicpf, ver 1.0
10373 12:12:39.350763 <6>[ 3.209078] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10374 12:12:39.353035 <6>[ 3.216554] hns3: Copyright (c) 2017 Huawei Corporation.
10375 12:12:39.359714 <6>[ 3.222140] hclge is initializing
10376 12:12:39.362815 <6>[ 3.225718] e1000: Intel(R) PRO/1000 Network Driver
10377 12:12:39.369849 <6>[ 3.230847] e1000: Copyright (c) 1999-2006 Intel Corporation.
10378 12:12:39.373281 <6>[ 3.236860] e1000e: Intel(R) PRO/1000 Network Driver
10379 12:12:39.379248 <6>[ 3.242076] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10380 12:12:39.385940 <6>[ 3.248264] igb: Intel(R) Gigabit Ethernet Network Driver
10381 12:12:39.393369 <6>[ 3.253914] igb: Copyright (c) 2007-2014 Intel Corporation.
10382 12:12:39.399518 <6>[ 3.259753] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10383 12:12:39.405839 <6>[ 3.266271] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10384 12:12:39.409539 <6>[ 3.272731] sky2: driver version 1.30
10385 12:12:39.419483 <6>[ 3.277707] VFIO - User Level meta-driver version: 0.3
10386 12:12:39.423664 <6>[ 3.285939] usbcore: registered new interface driver usb-storage
10387 12:12:39.430238 <6>[ 3.292384] usbcore: registered new device driver onboard-usb-hub
10388 12:12:39.439184 <6>[ 3.301500] mt6397-rtc mt6359-rtc: registered as rtc0
10389 12:12:39.448884 <6>[ 3.306972] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-31T12:12:42 UTC (1706703162)
10390 12:12:39.452560 <6>[ 3.316530] i2c_dev: i2c /dev entries driver
10391 12:12:39.468925 <6>[ 3.328238] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10392 12:12:39.488485 <6>[ 3.351219] cpu cpu0: EM: created perf domain
10393 12:12:39.491836 <6>[ 3.356119] cpu cpu4: EM: created perf domain
10394 12:12:39.498611 <6>[ 3.361632] sdhci: Secure Digital Host Controller Interface driver
10395 12:12:39.505453 <6>[ 3.368065] sdhci: Copyright(c) Pierre Ossman
10396 12:12:39.512621 <6>[ 3.372976] Synopsys Designware Multimedia Card Interface Driver
10397 12:12:39.518867 <6>[ 3.379573] sdhci-pltfm: SDHCI platform and OF driver helper
10398 12:12:39.522696 <6>[ 3.379735] mmc0: CQHCI version 5.10
10399 12:12:39.529147 <6>[ 3.389572] ledtrig-cpu: registered to indicate activity on CPUs
10400 12:12:39.536353 <6>[ 3.396556] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10401 12:12:39.542040 <6>[ 3.403592] usbcore: registered new interface driver usbhid
10402 12:12:39.545595 <6>[ 3.409413] usbhid: USB HID core driver
10403 12:12:39.552000 <6>[ 3.413612] spi_master spi0: will run message pump with realtime priority
10404 12:12:39.593276 <6>[ 3.448957] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10405 12:12:39.611392 <6>[ 3.464291] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10406 12:12:39.618874 <6>[ 3.479050] cros-ec-spi spi0.0: Chrome EC device registered
10407 12:12:39.622075 <6>[ 3.485065] mmc0: Command Queue Engine enabled
10408 12:12:39.629839 <6>[ 3.489803] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10409 12:12:39.638462 <6>[ 3.496495] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10410 12:12:39.642190 <6>[ 3.496979] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10411 12:12:39.649465 <6>[ 3.506715] NET: Registered PF_PACKET protocol family
10412 12:12:39.652374 <6>[ 3.515977] 9pnet: Installing 9P2000 support
10413 12:12:39.658214 <6>[ 3.516625] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10414 12:12:39.661871 <5>[ 3.520545] Key type dns_resolver registered
10415 12:12:39.668366 <6>[ 3.527692] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10416 12:12:39.671450 <6>[ 3.531318] registered taskstats version 1
10417 12:12:39.678569 <6>[ 3.536829] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10418 12:12:39.681353 <5>[ 3.540536] Loading compiled-in X.509 certificates
10419 12:12:39.687998 <6>[ 3.546345] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10420 12:12:39.710169 <4>[ 3.566287] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10421 12:12:39.720813 <4>[ 3.576971] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10422 12:12:39.726704 <3>[ 3.587497] debugfs: File 'uA_load' in directory '/' already present!
10423 12:12:39.733066 <3>[ 3.594196] debugfs: File 'min_uV' in directory '/' already present!
10424 12:12:39.739963 <3>[ 3.600803] debugfs: File 'max_uV' in directory '/' already present!
10425 12:12:39.746300 <3>[ 3.607416] debugfs: File 'constraint_flags' in directory '/' already present!
10426 12:12:39.757300 <3>[ 3.616919] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10427 12:12:39.766449 <6>[ 3.629350] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10428 12:12:39.773187 <6>[ 3.636073] xhci-mtk 11200000.usb: xHCI Host Controller
10429 12:12:39.779713 <6>[ 3.641562] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10430 12:12:39.789774 <6>[ 3.649391] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10431 12:12:39.796363 <6>[ 3.658809] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10432 12:12:39.803682 <6>[ 3.664860] xhci-mtk 11200000.usb: xHCI Host Controller
10433 12:12:39.809953 <6>[ 3.670334] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10434 12:12:39.816633 <6>[ 3.677977] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10435 12:12:39.823115 <6>[ 3.685628] hub 1-0:1.0: USB hub found
10436 12:12:39.826878 <6>[ 3.689637] hub 1-0:1.0: 1 port detected
10437 12:12:39.832581 <6>[ 3.693895] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10438 12:12:39.839532 <6>[ 3.702435] hub 2-0:1.0: USB hub found
10439 12:12:39.843020 <6>[ 3.706439] hub 2-0:1.0: 1 port detected
10440 12:12:39.851082 <6>[ 3.713906] mtk-msdc 11f70000.mmc: Got CD GPIO
10441 12:12:39.861856 <6>[ 3.720994] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10442 12:12:39.868348 <6>[ 3.729010] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10443 12:12:39.878069 <4>[ 3.736913] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10444 12:12:39.887749 <6>[ 3.746429] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10445 12:12:39.894931 <6>[ 3.754506] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10446 12:12:39.901196 <6>[ 3.762511] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10447 12:12:39.911829 <6>[ 3.770425] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10448 12:12:39.917649 <6>[ 3.778244] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10449 12:12:39.927841 <6>[ 3.786061] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10450 12:12:39.937967 <6>[ 3.796515] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10451 12:12:39.944031 <6>[ 3.804880] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10452 12:12:39.954041 <6>[ 3.813220] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10453 12:12:39.960363 <6>[ 3.821559] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10454 12:12:39.970315 <6>[ 3.829896] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10455 12:12:39.980678 <6>[ 3.838234] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10456 12:12:39.987468 <6>[ 3.846572] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10457 12:12:39.997277 <6>[ 3.854911] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10458 12:12:40.003353 <6>[ 3.863248] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10459 12:12:40.013415 <6>[ 3.871596] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10460 12:12:40.019745 <6>[ 3.879937] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10461 12:12:40.030836 <6>[ 3.888274] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10462 12:12:40.037012 <6>[ 3.896612] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10463 12:12:40.047622 <6>[ 3.904949] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10464 12:12:40.053487 <6>[ 3.913289] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10465 12:12:40.060561 <6>[ 3.922030] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10466 12:12:40.066057 <6>[ 3.929170] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10467 12:12:40.074000 <6>[ 3.935910] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10468 12:12:40.083068 <6>[ 3.942640] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10469 12:12:40.089737 <6>[ 3.949548] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10470 12:12:40.096582 <6>[ 3.956404] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10471 12:12:40.107118 <6>[ 3.965531] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10472 12:12:40.116404 <6>[ 3.974650] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10473 12:12:40.126075 <6>[ 3.983945] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10474 12:12:40.136928 <6>[ 3.993430] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10475 12:12:40.145589 <6>[ 4.002898] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10476 12:12:40.152337 <6>[ 4.012016] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10477 12:12:40.162220 <6>[ 4.021482] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10478 12:12:40.172143 <6>[ 4.030601] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10479 12:12:40.182510 <6>[ 4.039893] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10480 12:12:40.192905 <6>[ 4.050052] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10481 12:12:40.202354 <6>[ 4.061599] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10482 12:12:40.232902 <6>[ 4.092264] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10483 12:12:40.261004 <6>[ 4.123576] hub 2-1:1.0: USB hub found
10484 12:12:40.263923 <6>[ 4.128036] hub 2-1:1.0: 3 ports detected
10485 12:12:40.272594 <6>[ 4.134959] hub 2-1:1.0: USB hub found
10486 12:12:40.276044 <6>[ 4.139285] hub 2-1:1.0: 3 ports detected
10487 12:12:40.384753 <6>[ 4.243949] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10488 12:12:40.539261 <6>[ 4.401853] hub 1-1:1.0: USB hub found
10489 12:12:40.542982 <6>[ 4.406313] hub 1-1:1.0: 4 ports detected
10490 12:12:40.552963 <6>[ 4.415319] hub 1-1:1.0: USB hub found
10491 12:12:40.556212 <6>[ 4.419690] hub 1-1:1.0: 4 ports detected
10492 12:12:40.617277 <6>[ 4.476255] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10493 12:12:40.876253 <6>[ 4.736042] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10494 12:12:41.009026 <6>[ 4.871911] hub 1-1.4:1.0: USB hub found
10495 12:12:41.012544 <6>[ 4.876590] hub 1-1.4:1.0: 2 ports detected
10496 12:12:41.021936 <6>[ 4.884652] hub 1-1.4:1.0: USB hub found
10497 12:12:41.024887 <6>[ 4.889256] hub 1-1.4:1.0: 2 ports detected
10498 12:12:41.320500 <6>[ 5.180013] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10499 12:12:41.513475 <6>[ 5.372010] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10500 12:12:52.473506 <6>[ 16.341065] ALSA device list:
10501 12:12:52.479730 <6>[ 16.344361] No soundcards found.
10502 12:12:52.487895 <6>[ 16.352217] Freeing unused kernel memory: 8448K
10503 12:12:52.491750 <6>[ 16.357205] Run /init as init process
10504 12:12:52.537511 <6>[ 16.401782] NET: Registered PF_INET6 protocol family
10505 12:12:52.541371 <6>[ 16.407800] Segment Routing with IPv6
10506 12:12:52.547528 <6>[ 16.411737] In-situ OAM (IOAM) with IPv6
10507 12:12:52.581306 <30>[ 16.425571] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10508 12:12:52.584496 <30>[ 16.449374] systemd[1]: Detected architecture arm64.
10509 12:12:52.584596
10510 12:12:52.590878 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10511 12:12:52.591004
10512 12:12:52.603956 <30>[ 16.467988] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10513 12:12:52.736245 <30>[ 16.596764] systemd[1]: Queued start job for default target Graphical Interface.
10514 12:12:52.772635 <30>[ 16.636837] systemd[1]: Created slice system-getty.slice.
10515 12:12:52.779283 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10516 12:12:52.796156 <30>[ 16.660654] systemd[1]: Created slice system-modprobe.slice.
10517 12:12:52.802873 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10518 12:12:52.821482 <30>[ 16.685324] systemd[1]: Created slice system-serial\x2dgetty.slice.
10519 12:12:52.831122 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10520 12:12:52.844547 <30>[ 16.708579] systemd[1]: Created slice User and Session Slice.
10521 12:12:52.851267 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10522 12:12:52.871920 <30>[ 16.732672] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10523 12:12:52.881330 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10524 12:12:52.899645 <30>[ 16.760720] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10525 12:12:52.906564 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10526 12:12:52.930805 <30>[ 16.788512] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10527 12:12:52.937964 <30>[ 16.800826] systemd[1]: Reached target Local Encrypted Volumes.
10528 12:12:52.944324 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10529 12:12:52.960027 <30>[ 16.824506] systemd[1]: Reached target Paths.
10530 12:12:52.963557 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10531 12:12:52.979689 <30>[ 16.844031] systemd[1]: Reached target Remote File Systems.
10532 12:12:52.986213 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10533 12:12:53.000449 <30>[ 16.864025] systemd[1]: Reached target Slices.
10534 12:12:53.003109 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10535 12:12:53.019606 <30>[ 16.884061] systemd[1]: Reached target Swap.
10536 12:12:53.023404 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10537 12:12:53.043229 <30>[ 16.904524] systemd[1]: Listening on initctl Compatibility Named Pipe.
10538 12:12:53.049835 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10539 12:12:53.064940 <30>[ 16.928935] systemd[1]: Listening on Journal Audit Socket.
10540 12:12:53.071127 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10541 12:12:53.089239 <30>[ 16.953171] systemd[1]: Listening on Journal Socket (/dev/log).
10542 12:12:53.095515 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10543 12:12:53.113284 <30>[ 16.977220] systemd[1]: Listening on Journal Socket.
10544 12:12:53.119814 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10545 12:12:53.132395 <30>[ 16.996612] systemd[1]: Listening on udev Control Socket.
10546 12:12:53.139523 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10547 12:12:53.156655 <30>[ 17.021060] systemd[1]: Listening on udev Kernel Socket.
10548 12:12:53.164368 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10549 12:12:53.216527 <30>[ 17.080357] systemd[1]: Mounting Huge Pages File System...
10550 12:12:53.223324 Mounting [0;1;39mHuge Pages File System[0m...
10551 12:12:53.238771 <30>[ 17.102982] systemd[1]: Mounting POSIX Message Queue File System...
10552 12:12:53.245397 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10553 12:12:53.263303 <30>[ 17.127269] systemd[1]: Mounting Kernel Debug File System...
10554 12:12:53.270152 Mounting [0;1;39mKernel Debug File System[0m...
10555 12:12:53.286955 <30>[ 17.148279] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10556 12:12:53.319405 <30>[ 17.180504] systemd[1]: Starting Create list of static device nodes for the current kernel...
10557 12:12:53.325900 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10558 12:12:53.348029 <30>[ 17.212406] systemd[1]: Starting Load Kernel Module configfs...
10559 12:12:53.354813 Starting [0;1;39mLoad Kernel Module configfs[0m...
10560 12:12:53.372077 <30>[ 17.236308] systemd[1]: Starting Load Kernel Module drm...
10561 12:12:53.378512 Starting [0;1;39mLoad Kernel Module drm[0m...
10562 12:12:53.395064 <30>[ 17.256376] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10563 12:12:53.448438 <30>[ 17.312761] systemd[1]: Starting Journal Service...
10564 12:12:53.451556 Starting [0;1;39mJournal Service[0m...
10565 12:12:53.473157 <30>[ 17.337064] systemd[1]: Starting Load Kernel Modules...
10566 12:12:53.480003 Starting [0;1;39mLoad Kernel Modules[0m...
10567 12:12:53.498398 <30>[ 17.359185] systemd[1]: Starting Remount Root and Kernel File Systems...
10568 12:12:53.505267 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10569 12:12:53.523138 <30>[ 17.387540] systemd[1]: Starting Coldplug All udev Devices...
10570 12:12:53.529517 Starting [0;1;39mColdplug All udev Devices[0m...
10571 12:12:53.546469 <30>[ 17.410602] systemd[1]: Started Journal Service.
10572 12:12:53.553973 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10573 12:12:53.571828 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10574 12:12:53.590255 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10575 12:12:53.604672 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10576 12:12:53.625910 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10577 12:12:53.641827 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10578 12:12:53.667430 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10579 12:12:53.690051 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10580 12:12:53.714312 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10581 12:12:53.732200 See 'systemctl status systemd-remount-fs.service' for details.
10582 12:12:53.769997 Mounting [0;1;39mKernel Configuration File System[0m...
10583 12:12:53.786449 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10584 12:12:53.804118 <46>[ 17.665124] systemd-journald[176]: Received client request to flush runtime journal.
10585 12:12:53.815240 Starting [0;1;39mLoad/Save Random Seed[0m...
10586 12:12:53.836936 Starting [0;1;39mApply Kernel Variables[0m...
10587 12:12:53.861275 Starting [0;1;39mCreate System Users[0m...
10588 12:12:53.882429 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10589 12:12:53.901677 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10590 12:12:53.920533 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10591 12:12:53.933666 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10592 12:12:53.949408 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10593 12:12:53.966081 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10594 12:12:54.008362 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10595 12:12:54.029660 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10596 12:12:54.048294 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10597 12:12:54.064058 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10598 12:12:54.110123 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10599 12:12:54.135370 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10600 12:12:54.153937 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10601 12:12:54.171998 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10602 12:12:54.231503 Starting [0;1;39mNetwork Time Synchronization[0m...
10603 12:12:54.256480 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10604 12:12:54.300605 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System B<6>[ 18.162933] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10605 12:12:54.313959 oot/Shutdown[0m<6>[ 18.172023] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10606 12:12:54.314084 .
10607 12:12:54.323944 [[0;32m OK [<6>[ 18.184289] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10608 12:12:54.333524 0m] Started [0;<3>[ 18.193656] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10609 12:12:54.343615 1;39mNetwork Tim<3>[ 18.204363] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10610 12:12:54.353555 e Synchronizatio<3>[ 18.213472] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10611 12:12:54.353717 n[0m.
10612 12:12:54.369075 <3>[ 18.230352] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10613 12:12:54.376213 <6>[ 18.235445] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10614 12:12:54.385757 <3>[ 18.238779] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10615 12:12:54.392975 <3>[ 18.253988] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10616 12:12:54.402347 <3>[ 18.262078] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10617 12:12:54.409044 <4>[ 18.264220] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10618 12:12:54.415471 <3>[ 18.270165] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10619 12:12:54.422037 <6>[ 18.271661] remoteproc remoteproc0: scp is available
10620 12:12:54.425415 <6>[ 18.271713] remoteproc remoteproc0: powering up scp
10621 12:12:54.435240 <6>[ 18.271717] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10622 12:12:54.441967 [[0;32m OK [<6>[ 18.271752] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10623 12:12:54.448421 <4>[ 18.277536] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10624 12:12:54.458200 <3>[ 18.285572] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10625 12:12:54.469556 0m] Found device [0;1;39m/dev/t<3>[ 18.328265] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10626 12:12:54.469718 tyS0[0m.
10627 12:12:54.474976 <6>[ 18.328520] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10628 12:12:54.483537 <6>[ 18.330146] usbcore: registered new device driver r8152-cfgselector
10629 12:12:54.488992 <6>[ 18.331606] mc: Linux media interface: v0.10
10630 12:12:54.494693 <3>[ 18.337596] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10631 12:12:54.504851 <3>[ 18.337602] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10632 12:12:54.511524 <6>[ 18.339470] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10633 12:12:54.518520 <3>[ 18.342848] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10634 12:12:54.528814 <3>[ 18.342865] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10635 12:12:54.534767 <3>[ 18.342868] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10636 12:12:54.544580 <3>[ 18.342873] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10637 12:12:54.551626 <3>[ 18.342875] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10638 12:12:54.558065 <6>[ 18.345818] pci_bus 0000:00: root bus resource [bus 00-ff]
10639 12:12:54.564240 <3>[ 18.358043] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10640 12:12:54.571752 <6>[ 18.365643] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10641 12:12:54.577771 <6>[ 18.374112] videodev: Linux video capture interface: v2.00
10642 12:12:54.589474 <6>[ 18.380833] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10643 12:12:54.594697 <6>[ 18.458146] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10644 12:12:54.604059 <6>[ 18.458156] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10645 12:12:54.611745 <6>[ 18.458170] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10646 12:12:54.620692 [[0;32m OK [<6>[ 18.459548] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10647 12:12:54.627519 <6>[ 18.465397] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10648 12:12:54.637319 <6>[ 18.465895] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10649 12:12:54.647049 0m] Created slic<6>[ 18.473150] remoteproc remoteproc0: remote processor scp is now up
10650 12:12:54.654081 e [0;1;39msyste<6>[ 18.480379] pci 0000:00:00.0: supports D1 D2
10651 12:12:54.664355 m-systemd\x2dbac<6>[ 18.480636] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10652 12:12:54.667570 klight.slice[0m<6>[ 18.509291] Bluetooth: Core ver 2.22
10653 12:12:54.667689 .
10654 12:12:54.674161 <6>[ 18.516230] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10655 12:12:54.685128 <6>[ 18.522297] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10656 12:12:54.690742 <4>[ 18.523893] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10657 12:12:54.697433 <4>[ 18.523893] Fallback method does not support PEC.
10658 12:12:54.704267 <6>[ 18.533282] NET: Registered PF_BLUETOOTH protocol family
10659 12:12:54.710874 <3>[ 18.538432] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10660 12:12:54.718364 <6>[ 18.539238] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10661 12:12:54.725152 <6>[ 18.539278] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10662 12:12:54.734903 <6>[ 18.539299] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10663 12:12:54.741636 <6>[ 18.539317] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10664 12:12:54.745008 <6>[ 18.539443] pci 0000:01:00.0: supports D1 D2
10665 12:12:54.752878 <6>[ 18.539447] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10666 12:12:54.759194 <6>[ 18.545995] Bluetooth: HCI device and connection manager initialized
10667 12:12:54.768883 <6>[ 18.556239] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10668 12:12:54.776451 <6>[ 18.556257] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10669 12:12:54.782702 <6>[ 18.556306] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10670 12:12:54.789366 <6>[ 18.556310] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10671 12:12:54.799406 <6>[ 18.556321] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10672 12:12:54.806364 <6>[ 18.556334] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10673 12:12:54.815812 <6>[ 18.556346] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10674 12:12:54.819134 <6>[ 18.556358] pci 0000:00:00.0: PCI bridge to [bus 01]
10675 12:12:54.826718 <6>[ 18.556363] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10676 12:12:54.834172 <6>[ 18.556574] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10677 12:12:54.839915 <6>[ 18.567475] Bluetooth: HCI socket layer initialized
10678 12:12:54.847653 <3>[ 18.593251] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10679 12:12:54.855231 <6>[ 18.596635] Bluetooth: L2CAP socket layer initialized
10680 12:12:54.861212 <6>[ 18.598286] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10681 12:12:54.873933 <6>[ 18.607678] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10682 12:12:54.880868 <4>[ 18.609543] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10683 12:12:54.891657 <4>[ 18.609550] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10684 12:12:54.894772 <6>[ 18.610629] Bluetooth: SCO socket layer initialized
10685 12:12:54.901142 <6>[ 18.616637] usbcore: registered new interface driver uvcvideo
10686 12:12:54.908149 <6>[ 18.618561] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10687 12:12:54.914334 <6>[ 18.622034] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10688 12:12:54.920788 <6>[ 18.623154] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10689 12:12:54.928016 <6>[ 18.623984] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10690 12:12:54.938071 <6>[ 18.626865] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10691 12:12:54.945655 <3>[ 18.647147] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10692 12:12:54.955006 <3>[ 18.647761] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6
10693 12:12:54.961994 <3>[ 18.659839] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10694 12:12:54.971896 <3>[ 18.660657] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6
10695 12:12:54.978551 <5>[ 18.670878] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10696 12:12:54.985409 <6>[ 18.677127] usbcore: registered new interface driver btusb
10697 12:12:54.997387 <4>[ 18.677904] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10698 12:12:55.002674 <3>[ 18.677913] Bluetooth: hci0: Failed to load firmware file (-2)
10699 12:12:55.007861 <3>[ 18.677915] Bluetooth: hci0: Failed to set up firmware (-2)
10700 12:12:55.016699 <4>[ 18.677918] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10701 12:12:55.023274 <6>[ 18.679872] r8152 2-1.3:1.0 eth0: v1.12.13
10702 12:12:55.027110 <6>[ 18.679934] usbcore: registered new interface driver r8152
10703 12:12:55.033610 <5>[ 18.693041] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10704 12:12:55.042718 <3>[ 18.696914] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10705 12:12:55.049715 <6>[ 18.704260] usbcore: registered new interface driver cdc_ether
10706 12:12:55.055981 <5>[ 18.709261] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10707 12:12:55.066226 <3>[ 18.715473] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10708 12:12:55.073637 <6>[ 18.723287] usbcore: registered new interface driver r8153_ecm
10709 12:12:55.082429 <4>[ 18.730159] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10710 12:12:55.089109 <3>[ 18.733743] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10711 12:12:55.099543 <3>[ 18.752457] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10712 12:12:55.102482 <6>[ 18.759649] cfg80211: failed to load regulatory.db
10713 12:12:55.108854 <6>[ 18.795094] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10714 12:12:55.116630 <6>[ 18.833031] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10715 12:12:55.122629 <6>[ 18.986657] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10716 12:12:55.128829 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10717 12:12:55.147204 [[0;32m OK [0m] Reached target [0;1;39mSyst<6>[ 19.012035] mt7921e 0000:01:00.0: ASIC revision: 79610010
10718 12:12:55.150124 em Time Synchronized[0m.
10719 12:12:55.187802 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10720 12:12:55.213446 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10721 12:12:55.250968 <6>[ 19.111792] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10722 12:12:55.253457 <6>[ 19.111792]
10723 12:12:55.352160 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10724 12:12:55.367636 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10725 12:12:55.387682 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10726 12:12:55.402544 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10727 12:12:55.419829 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10728 12:12:55.443444 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10729 12:12:55.459531 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10730 12:12:55.475473 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10731 12:12:55.495569 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10732 12:12:55.521356 <6>[ 19.382692] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10733 12:12:55.544318 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10734 12:12:55.576328 Starting [0;1;39mUser Login Management[0m...
10735 12:12:55.597084 Starting [0;1;39mPermit User Sessions[0m...
10736 12:12:55.616741 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10737 12:12:55.664423 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10738 12:12:55.684388 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10739 12:12:55.700132 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10740 12:12:55.719010 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10741 12:12:55.736672 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10742 12:12:55.753072 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10743 12:12:55.769633 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10744 12:12:55.789454 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10745 12:12:55.832994 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10746 12:12:55.865464 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10747 12:12:55.917652
10748 12:12:55.917807
10749 12:12:55.921112 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10750 12:12:55.921197
10751 12:12:55.924522 debian-bullseye-arm64 login: root (automatic login)
10752 12:12:55.924605
10753 12:12:55.924669
10754 12:12:55.950788 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024 aarch64
10755 12:12:55.950933
10756 12:12:55.956415 The programs included with the Debian GNU/Linux system are free software;
10757 12:12:55.963222 the exact distribution terms for each program are described in the
10758 12:12:55.966536 individual files in /usr/share/doc/*/copyright.
10759 12:12:55.966622
10760 12:12:55.973860 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10761 12:12:55.976531 permitted by applicable law.
10762 12:12:55.976920 Matched prompt #10: / #
10764 12:12:55.977156 Setting prompt string to ['/ #']
10765 12:12:55.977248 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10767 12:12:55.977441 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
10768 12:12:55.977530 start: 2.2.6 expect-shell-connection (timeout 00:03:22) [common]
10769 12:12:55.977599 Setting prompt string to ['/ #']
10770 12:12:55.977660 Forcing a shell prompt, looking for ['/ #']
10772 12:12:56.027892 / #
10773 12:12:56.028083 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10774 12:12:56.028168 Waiting using forced prompt support (timeout 00:02:30)
10775 12:12:56.033209
10776 12:12:56.033500 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10777 12:12:56.033601 start: 2.2.7 export-device-env (timeout 00:03:22) [common]
10778 12:12:56.033695 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10779 12:12:56.033781 end: 2.2 depthcharge-retry (duration 00:01:38) [common]
10780 12:12:56.033865 end: 2 depthcharge-action (duration 00:01:38) [common]
10781 12:12:56.033952 start: 3 lava-test-retry (timeout 00:07:37) [common]
10782 12:12:56.034040 start: 3.1 lava-test-shell (timeout 00:07:37) [common]
10783 12:12:56.034115 Using namespace: common
10785 12:12:56.134490 / # #
10786 12:12:56.134675 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10787 12:12:56.140179 #
10788 12:12:56.140456 Using /lava-12669492
10790 12:12:56.240817 / # export SHELL=/bin/sh
10791 12:12:56.246960 export SHELL=/bin/sh
10793 12:12:56.347530 / # . /lava-12669492/environment
10794 12:12:56.353372 . /lava-12669492/environment
10796 12:12:56.453990 / # /lava-12669492/bin/lava-test-runner /lava-12669492/0
10797 12:12:56.454160 Test shell timeout: 10s (minimum of the action and connection timeout)
10798 12:12:56.454557 <6>[ 20.234740] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10799 12:12:56.459935 /lava-12669492/bin/lava-test-runner /lava-12669492/0
10800 12:12:56.500952 + export TESTRUN_ID=0_igt-gpu-pa<8>[ 20.349174] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 12669492_1.5.2.3.1>
10801 12:12:56.501112 nfrost
10802 12:12:56.501182 + cd /lava-12669492/0/tests/0_igt-gpu-panfrost
10803 12:12:56.501244 + cat uuid
10804 12:12:56.501305 + UUID=12669492_1.5.2.3.1
10805 12:12:56.501364 + set +x
10806 12:12:56.501610 Received signal: <STARTRUN> 0_igt-gpu-panfrost 12669492_1.5.2.3.1
10807 12:12:56.501680 Starting test lava.0_igt-gpu-panfrost (12669492_1.5.2.3.1)
10808 12:12:56.501766 Skipping test definition patterns.
10809 12:12:56.508536 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new pan<8>[ 20.371588] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
10810 12:12:56.508797 Received signal: <TESTSET> START panfrost_gem_new
10811 12:12:56.508918 Starting test_set panfrost_gem_new
10812 12:12:56.512012 frost_get_param panfrost_prime panfrost_submit
10813 12:12:56.526603 <14>[ 20.390850] [IGT] panfrost_gem_new: executing
10814 12:12:56.533161 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.397468] [IGT] panfrost_gem_new: exiting, ret=77
10815 12:12:56.536758 rch64) (Linux: 6.1.72-cip13 aarch64)
10816 12:12:56.549314 Test requirement not met in function drm_open_driver, file<8>[ 20.411267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
10817 12:12:56.549621 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
10819 12:12:56.552185 ../lib/drmtest.c:621:
10820 12:12:56.552268 Test requirement: !(fd<0)
10821 12:12:56.559154 No known gpu found for chipset flags 0x32 (panfrost)
10822 12:12:56.562519 Last errno: 2, No such file or directory
10823 12:12:56.566022 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
10824 12:12:56.576667 <14>[ 20.441514] [IGT] panfrost_gem_new: executing
10825 12:12:56.586697 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.449457] [IGT] panfrost_gem_new: exiting, ret=77
10826 12:12:56.586798 .1.72-cip13 aarch64)
10827 12:12:56.600341 Test requirement not met in function drm_open_driver, file ../lib/drmtest.<8>[ 20.463177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
10828 12:12:56.600637 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
10830 12:12:56.603235 c:621:
10831 12:12:56.603319 Test requirement: !(fd<0)
10832 12:12:56.609756 No known gpu found for chipset flags 0x32 (panfrost)
10833 12:12:56.616507 Last errno: 2, No such file or director<14>[ 20.481842] [IGT] panfrost_gem_new: executing
10834 12:12:56.616599 y
10835 12:12:56.626060 [1mSubtest gem-new-0: SKIP (<14>[ 20.488578] [IGT] panfrost_gem_new: exiting, ret=77
10836 12:12:56.626153 0.000s)[0m
10837 12:12:56.636092 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
10839 12:12:56.639238 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.<8>[ 20.499202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
10840 12:12:56.639327 72-cip13 aarch64)
10841 12:12:56.646372 Test requirem<8>[ 20.508907] <LAVA_SIGNAL_TESTSET STOP>
10842 12:12:56.646638 Received signal: <TESTSET> STOP
10843 12:12:56.646715 Closing test_set panfrost_gem_new
10844 12:12:56.649780 ent not met in function drm_open_driver, file ../lib/drmtest.c:621:
10845 12:12:56.652925 Test requirement: !(fd<0)
10846 12:12:56.658923 No known gpu found for chipset flags 0x32 (panfrost)
10847 12:12:56.662315 Last errno: 2, No such file or directory
10848 12:12:56.669719 [1mSubtest gem-<8>[ 20.531963] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
10849 12:12:56.669983 Received signal: <TESTSET> START panfrost_get_param
10850 12:12:56.670059 Starting test_set panfrost_get_param
10851 12:12:56.672045 new-zeroed: SKIP (0.000s)[0m
10852 12:12:56.688872 <14>[ 20.553591] [IGT] panfrost_get_param: executing
10853 12:12:56.698664 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.560516] [IGT] panfrost_get_param: exiting, ret=77
10854 12:12:56.701979 rch64) (Linux: 6.1.72-cip13 aarch64)
10855 12:12:56.712284 Test requirement not met in function drm_o<8>[ 20.573367] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
10856 12:12:56.712566 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
10858 12:12:56.715800 pen_driver, file ../lib/drmtest.c:621:
10859 12:12:56.715886 Test requirement: !(fd<0)
10860 12:12:56.722331 No known gpu found for chipset flags 0x32 (panfrost)
10861 12:12:56.728931 Last errno: 2, No such <14>[ 20.591921] [IGT] panfrost_get_param: executing
10862 12:12:56.729026 file or directory
10863 12:12:56.735323 [1mSubtest b<14>[ 20.599937] [IGT] panfrost_get_param: exiting, ret=77
10864 12:12:56.738332 ase-params: SKIP (0.000s)[0m
10865 12:12:56.751496 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.<8>[ 20.612115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
10866 12:12:56.751602 1.72-cip13 aarch64)
10867 12:12:56.751852 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
10869 12:12:56.757944 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10870 12:12:56.762378 Test requirement: !(fd<0)
10871 12:12:56.768045 No known gpu f<14>[ 20.631955] [IGT] panfrost_get_param: executing
10872 12:12:56.778427 ound for chipset flags 0x32 (pan<14>[ 20.639603] [IGT] panfrost_get_param: exiting, ret=77
10873 12:12:56.778522 frost)
10874 12:12:56.781377 Last errno: 2, No such file or directory
10875 12:12:56.790980 [1mSubtest get-bad-param: SKI<8>[ 20.652682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
10876 12:12:56.791070 P (0.000s)[0m
10877 12:12:56.791315 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
10879 12:12:56.798436 IGT-Version: 1.2<8>[ 20.662131] <LAVA_SIGNAL_TESTSET STOP>
10880 12:12:56.798695 Received signal: <TESTSET> STOP
10881 12:12:56.798769 Closing test_set panfrost_get_param
10882 12:12:56.801095 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
10883 12:12:56.807499 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10884 12:12:56.811122 Test requirement: !(fd<0)
10885 12:12:56.821144 No known gpu found for chipse<8>[ 20.683497] <LAVA_SIGNAL_TESTSET START panfrost_prime>
10886 12:12:56.821240 t flags 0x32 (panfrost)
10887 12:12:56.821483 Received signal: <TESTSET> START panfrost_prime
10888 12:12:56.821552 Starting test_set panfrost_prime
10889 12:12:56.824761 Last errno: 2, No such file or directory
10890 12:12:56.831597 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
10891 12:12:56.838240 <14>[ 20.702270] [IGT] panfrost_prime: executing
10892 12:12:56.844161 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.708515] [IGT] panfrost_prime: exiting, ret=77
10893 12:12:56.847516 rch64) (Linux: 6.1.72-cip13 aarch64)
10894 12:12:56.860963 Test requirement not met in function drm_open_driver, file<8>[ 20.721876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
10895 12:12:56.861224 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
10897 12:12:56.864272 ../lib/drmtest.c:621:
10898 12:12:56.868231 Test req<8>[ 20.732264] <LAVA_SIGNAL_TESTSET STOP>
10899 12:12:56.868486 Received signal: <TESTSET> STOP
10900 12:12:56.868556 Closing test_set panfrost_prime
10901 12:12:56.871731 uirement: !(fd<0)
10902 12:12:56.875856 No known gpu found for chipset flags 0x32 (panfrost)
10903 12:12:56.877200 Last errno: 2, No such file or directory
10904 12:12:56.881061 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
10905 12:12:56.898144 <8>[ 20.762449] <LAVA_SIGNAL_TESTSET START panfrost_submit>
10906 12:12:56.898401 Received signal: <TESTSET> START panfrost_submit
10907 12:12:56.898472 Starting test_set panfrost_submit
10908 12:12:56.922475 <14>[ 20.787332] [IGT] panfrost_submit: executing
10909 12:12:56.929375 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 20.795051] [IGT] panfrost_submit: exiting, ret=77
10910 12:12:56.932530 rch64) (Linux: 6.1.72-cip13 aarch64)
10911 12:12:56.943146 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
10913 12:12:56.946296 Test requirement not met in function drm_o<8>[ 20.806375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
10914 12:12:56.949088 pen_driver, file ../lib/drmtest.c:621:
10915 12:12:56.949171 Test requirement: !(fd<0)
10916 12:12:56.956980 No known gpu found for chipset flags 0x32 (panfrost)
10917 12:12:56.959139 Last errno: 2, No such file or directory
10918 12:12:56.962229 [1mSubtest pan-submit: SKIP (0.000s)[0m
10919 12:12:56.971386 <14>[ 20.835701] [IGT] panfrost_submit: executing
10920 12:12:56.982132 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.843782] [IGT] panfrost_submit: exiting, ret=77
10921 12:12:56.982222 .1.72-cip13 aarch64)
10922 12:12:56.987903 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10923 12:12:56.997877 Test req<8>[ 20.858833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
10924 12:12:56.998138 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
10926 12:12:57.000693 uirement: !(fd<0)
10927 12:12:57.004249 No known gpu found for chipset flags 0x32 (panfrost)
10928 12:12:57.007473 Last errno: 2, No such file or directory
10929 12:12:57.015587 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
10930 12:12:57.026300 <14>[ 20.890182] [IGT] panfrost_submit: executing
10931 12:12:57.035155 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.898062] [IGT] panfrost_submit: exiting, ret=77
10932 12:12:57.035241 .1.72-cip13 aarch64)
10933 12:12:57.045371 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10934 12:12:57.052240 Test req<8>[ 20.913763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
10935 12:12:57.052506 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
10937 12:12:57.055257 uirement: !(fd<0)
10938 12:12:57.058628 No known gpu found for chipset flags 0x32 (panfrost)
10939 12:12:57.061836 Last errno: 2, No such file or directory
10940 12:12:57.068607 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
10941 12:12:57.080381 <14>[ 20.945353] [IGT] panfrost_submit: executing
10942 12:12:57.092723 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 20.953054] [IGT] panfrost_submit: exiting, ret=77
10943 12:12:57.092835 .1.72-cip13 aarch64)
10944 12:12:57.107760 Test requirement not met in function drm_open_driver, file ../lib/drmtest.<8>[ 20.966828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
10945 12:12:57.107850 c:621:
10946 12:12:57.108091 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
10948 12:12:57.110794 Test requirement: !(fd<0)
10949 12:12:57.113766 No known gpu found for chipset flags 0x32 (panfrost)
10950 12:12:57.116923 Last errno: 2, No such file or directory
10951 12:12:57.123258 [1mSubtest p<14>[ 20.988280] [IGT] panfrost_submit: executing
10952 12:12:57.133407 an-submit-error-bad-bo-handles: <14>[ 20.995302] [IGT] panfrost_submit: exiting, ret=77
10953 12:12:57.133492 SKIP (0.000s)[0m
10954 12:12:57.147002 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 a<8>[ 21.007442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
10955 12:12:57.147267 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
10957 12:12:57.149976 arch64)
10958 12:12:57.157141 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10959 12:12:57.157227 Test requirement: !(fd<0)
10960 12:12:57.163281 No known gpu found for chi<14>[ 21.029713] [IGT] panfrost_submit: executing
10961 12:12:57.166834 pset flags 0x32 (panfrost)
10962 12:12:57.173274 Last<14>[ 21.036545] [IGT] panfrost_submit: exiting, ret=77
10963 12:12:57.176833 errno: 2, No such file or directory
10964 12:12:57.189955 [1mSubtest pan-submit-error-bad-requireme<8>[ 21.048554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
10965 12:12:57.190043 nts: SKIP (0.000s)[0m
10966 12:12:57.190287 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
10968 12:12:57.197616 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
10969 12:12:57.202827 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10970 12:12:57.206459 Test requirement: !(fd<0)
10971 12:12:57.209620 No known gpu found for chipset flags 0x32 (panfrost)
10972 12:12:57.216499 <14>[ 21.079364] [IGT] panfrost_submit: executing
10973 12:12:57.216586
10974 12:12:57.219570 Last errno: 2, No such file or directory
10975 12:12:57.222835 [1mS<14>[ 21.087945] [IGT] panfrost_submit: exiting, ret=77
10976 12:12:57.229927 ubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
10977 12:12:57.239481 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-c<8>[ 21.102853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
10978 12:12:57.239745 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
10980 12:12:57.243139 ip13 aarch64)
10981 12:12:57.249797 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10982 12:12:57.253003 Test requirement: !(fd<0)
10983 12:12:57.255967 No known gpu found for chipset flags 0x32 (panfrost)
10984 12:12:57.259408 Last errno: 2, No such file or directory
10985 12:12:57.262437 [1mSubtest pan-reset: SKIP (0.000s)[0m
10986 12:12:57.269660 <14>[ 21.134352] [IGT] panfrost_submit: executing
10987 12:12:57.279745 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[ 21.142182] [IGT] panfrost_submit: exiting, ret=77
10988 12:12:57.279835 .1.72-cip13 aarch64)
10989 12:12:57.289906 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:
10990 12:12:57.296197 Test req<8>[ 21.158055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
10991 12:12:57.296459 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
10993 12:12:57.299309 uirement: !(fd<0)
10994 12:12:57.302646 No known gpu found for chipset flags 0x32 (panfrost)
10995 12:12:57.306307 Last errno: 2, No such file or directory
10996 12:12:57.309315 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
10997 12:12:57.324020 <14>[ 21.188616] [IGT] panfrost_submit: executing
10998 12:12:57.331129 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 21.196280] [IGT] panfrost_submit: exiting, ret=77
10999 12:12:57.334677 rch64) (Linux: 6.1.72-cip13 aarch64)
11000 12:12:57.350407 Test requirement not met in function drm_open_driver, file ../lib/drmtest.<8>[ 21.210723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11001 12:12:57.350503 c:621:
11002 12:12:57.350748 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11004 12:12:57.357475 Test requirement: !(fd<0<8>[ 21.221227] <LAVA_SIGNAL_TESTSET STOP>
11005 12:12:57.357560 )
11006 12:12:57.357797 Received signal: <TESTSET> STOP
11007 12:12:57.357864 Closing test_set panfrost_submit
11008 12:12:57.363293 No known gpu <8>[ 21.226777] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 12669492_1.5.2.3.1>
11009 12:12:57.363549 Received signal: <ENDRUN> 0_igt-gpu-panfrost 12669492_1.5.2.3.1
11010 12:12:57.363634 Ending use of test pattern.
11011 12:12:57.363698 Ending test lava.0_igt-gpu-panfrost (12669492_1.5.2.3.1), duration 0.86
11013 12:12:57.366823 found for chipset flags 0x32 (panfrost)
11014 12:12:57.370396 Last errno: 2, No such file or directory
11015 12:12:57.376921 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11016 12:12:57.377004 + set +x
11017 12:12:57.380012 <LAVA_TEST_RUNNER EXIT>
11018 12:12:57.380267 ok: lava_test_shell seems to have completed
11019 12:12:57.380579 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11020 12:12:57.380683 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11021 12:12:57.380815 end: 3 lava-test-retry (duration 00:00:01) [common]
11022 12:12:57.380904 start: 4 finalize (timeout 00:07:36) [common]
11023 12:12:57.380989 start: 4.1 power-off (timeout 00:00:30) [common]
11024 12:12:57.381140 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
11025 12:12:57.455833 >> Command sent successfully.
11026 12:12:57.458342 Returned 0 in 0 seconds
11027 12:12:57.558767 end: 4.1 power-off (duration 00:00:00) [common]
11029 12:12:57.559113 start: 4.2 read-feedback (timeout 00:07:35) [common]
11030 12:12:57.559381 Listened to connection for namespace 'common' for up to 1s
11031 12:12:58.560318 Finalising connection for namespace 'common'
11032 12:12:58.560527 Disconnecting from shell: Finalise
11033 12:12:58.560666 / #
11034 12:12:58.661074 end: 4.2 read-feedback (duration 00:00:01) [common]
11035 12:12:58.661294 end: 4 finalize (duration 00:00:01) [common]
11036 12:12:58.661439 Cleaning after the job
11037 12:12:58.661568 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669492/tftp-deploy-mt3j961u/ramdisk
11038 12:12:58.669746 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669492/tftp-deploy-mt3j961u/kernel
11039 12:12:58.678998 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669492/tftp-deploy-mt3j961u/dtb
11040 12:12:58.679203 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669492/tftp-deploy-mt3j961u/modules
11041 12:12:58.686772 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12669492
11042 12:12:58.817018 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12669492
11043 12:12:58.817203 Job finished correctly