Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 17
- Kernel Errors: 34
1 12:11:17.167529 lava-dispatcher, installed at version: 2023.10
2 12:11:17.167746 start: 0 validate
3 12:11:17.167876 Start time: 2024-01-31 12:11:17.167868+00:00 (UTC)
4 12:11:17.167993 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:11:17.168129 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 12:11:17.443047 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:11:17.443209 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:11:17.712108 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:11:17.712273 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:11:17.985230 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:11:17.985412 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:11:18.522471 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:11:18.522696 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:11:18.799057 validate duration: 1.63
16 12:11:18.799325 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:11:18.799472 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:11:18.799590 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:11:18.799724 Not decompressing ramdisk as can be used compressed.
20 12:11:18.799811 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 12:11:18.799874 saving as /var/lib/lava/dispatcher/tmp/12669504/tftp-deploy-_dcldchd/ramdisk/initrd.cpio.gz
22 12:11:18.799937 total size: 4665395 (4 MB)
23 12:11:18.801034 progress 0 % (0 MB)
24 12:11:18.802734 progress 5 % (0 MB)
25 12:11:18.804642 progress 10 % (0 MB)
26 12:11:18.806130 progress 15 % (0 MB)
27 12:11:18.807564 progress 20 % (0 MB)
28 12:11:18.808857 progress 25 % (1 MB)
29 12:11:18.810479 progress 30 % (1 MB)
30 12:11:18.811984 progress 35 % (1 MB)
31 12:11:18.813512 progress 40 % (1 MB)
32 12:11:18.815086 progress 45 % (2 MB)
33 12:11:18.816563 progress 50 % (2 MB)
34 12:11:18.818119 progress 55 % (2 MB)
35 12:11:18.819344 progress 60 % (2 MB)
36 12:11:18.820878 progress 65 % (2 MB)
37 12:11:18.822340 progress 70 % (3 MB)
38 12:11:18.823974 progress 75 % (3 MB)
39 12:11:18.825328 progress 80 % (3 MB)
40 12:11:18.826841 progress 85 % (3 MB)
41 12:11:18.828234 progress 90 % (4 MB)
42 12:11:18.829545 progress 95 % (4 MB)
43 12:11:18.830909 progress 100 % (4 MB)
44 12:11:18.831114 4 MB downloaded in 0.03 s (142.72 MB/s)
45 12:11:18.831308 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:11:18.831642 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:11:18.831766 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:11:18.831876 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:11:18.832005 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:11:18.832076 saving as /var/lib/lava/dispatcher/tmp/12669504/tftp-deploy-_dcldchd/kernel/Image
52 12:11:18.832136 total size: 51532288 (49 MB)
53 12:11:18.832209 No compression specified
54 12:11:18.833418 progress 0 % (0 MB)
55 12:11:18.847029 progress 5 % (2 MB)
56 12:11:18.860510 progress 10 % (4 MB)
57 12:11:18.873752 progress 15 % (7 MB)
58 12:11:18.887366 progress 20 % (9 MB)
59 12:11:18.900704 progress 25 % (12 MB)
60 12:11:18.913875 progress 30 % (14 MB)
61 12:11:18.927457 progress 35 % (17 MB)
62 12:11:18.940884 progress 40 % (19 MB)
63 12:11:18.954097 progress 45 % (22 MB)
64 12:11:18.967536 progress 50 % (24 MB)
65 12:11:18.980683 progress 55 % (27 MB)
66 12:11:18.994171 progress 60 % (29 MB)
67 12:11:19.007466 progress 65 % (31 MB)
68 12:11:19.020873 progress 70 % (34 MB)
69 12:11:19.034199 progress 75 % (36 MB)
70 12:11:19.047608 progress 80 % (39 MB)
71 12:11:19.060875 progress 85 % (41 MB)
72 12:11:19.074281 progress 90 % (44 MB)
73 12:11:19.087547 progress 95 % (46 MB)
74 12:11:19.100555 progress 100 % (49 MB)
75 12:11:19.100766 49 MB downloaded in 0.27 s (182.95 MB/s)
76 12:11:19.100916 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:11:19.101154 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:11:19.101241 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:11:19.101330 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:11:19.101469 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:11:19.101538 saving as /var/lib/lava/dispatcher/tmp/12669504/tftp-deploy-_dcldchd/dtb/mt8192-asurada-spherion-r0.dtb
83 12:11:19.101599 total size: 47278 (0 MB)
84 12:11:19.101661 No compression specified
85 12:11:19.102795 progress 69 % (0 MB)
86 12:11:19.103067 progress 100 % (0 MB)
87 12:11:19.103221 0 MB downloaded in 0.00 s (27.83 MB/s)
88 12:11:19.103344 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:11:19.103607 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:11:19.103695 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:11:19.103778 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:11:19.103891 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 12:11:19.103958 saving as /var/lib/lava/dispatcher/tmp/12669504/tftp-deploy-_dcldchd/nfsrootfs/full.rootfs.tar
95 12:11:19.104017 total size: 200813988 (191 MB)
96 12:11:19.104077 Using unxz to decompress xz
97 12:11:19.108460 progress 0 % (0 MB)
98 12:11:19.641168 progress 5 % (9 MB)
99 12:11:20.167447 progress 10 % (19 MB)
100 12:11:20.757660 progress 15 % (28 MB)
101 12:11:21.136177 progress 20 % (38 MB)
102 12:11:21.467350 progress 25 % (47 MB)
103 12:11:22.076441 progress 30 % (57 MB)
104 12:11:22.633276 progress 35 % (67 MB)
105 12:11:23.229370 progress 40 % (76 MB)
106 12:11:23.789752 progress 45 % (86 MB)
107 12:11:24.378572 progress 50 % (95 MB)
108 12:11:25.009570 progress 55 % (105 MB)
109 12:11:25.683190 progress 60 % (114 MB)
110 12:11:25.801598 progress 65 % (124 MB)
111 12:11:25.950290 progress 70 % (134 MB)
112 12:11:26.058907 progress 75 % (143 MB)
113 12:11:26.130262 progress 80 % (153 MB)
114 12:11:26.199307 progress 85 % (162 MB)
115 12:11:26.301424 progress 90 % (172 MB)
116 12:11:26.588512 progress 95 % (181 MB)
117 12:11:27.175946 progress 100 % (191 MB)
118 12:11:27.181254 191 MB downloaded in 8.08 s (23.71 MB/s)
119 12:11:27.181545 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:11:27.181817 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:11:27.181908 start: 1.5 download-retry (timeout 00:09:52) [common]
123 12:11:27.181994 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 12:11:27.182153 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:11:27.182227 saving as /var/lib/lava/dispatcher/tmp/12669504/tftp-deploy-_dcldchd/modules/modules.tar
126 12:11:27.182291 total size: 8639916 (8 MB)
127 12:11:27.182357 Using unxz to decompress xz
128 12:11:27.186837 progress 0 % (0 MB)
129 12:11:27.208073 progress 5 % (0 MB)
130 12:11:27.232226 progress 10 % (0 MB)
131 12:11:27.256447 progress 15 % (1 MB)
132 12:11:27.280454 progress 20 % (1 MB)
133 12:11:27.305119 progress 25 % (2 MB)
134 12:11:27.333566 progress 30 % (2 MB)
135 12:11:27.358526 progress 35 % (2 MB)
136 12:11:27.382081 progress 40 % (3 MB)
137 12:11:27.406995 progress 45 % (3 MB)
138 12:11:27.433817 progress 50 % (4 MB)
139 12:11:27.460934 progress 55 % (4 MB)
140 12:11:27.486757 progress 60 % (4 MB)
141 12:11:27.512951 progress 65 % (5 MB)
142 12:11:27.538636 progress 70 % (5 MB)
143 12:11:27.562556 progress 75 % (6 MB)
144 12:11:27.590109 progress 80 % (6 MB)
145 12:11:27.618589 progress 85 % (7 MB)
146 12:11:27.644430 progress 90 % (7 MB)
147 12:11:27.674318 progress 95 % (7 MB)
148 12:11:27.702627 progress 100 % (8 MB)
149 12:11:27.708608 8 MB downloaded in 0.53 s (15.66 MB/s)
150 12:11:27.708895 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:11:27.709165 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:11:27.709259 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:11:27.709352 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:11:31.293694 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12669504/extract-nfsrootfs-y7wd4bc_
156 12:11:31.293902 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 12:11:31.294004 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 12:11:31.294180 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a
159 12:11:31.294315 makedir: /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin
160 12:11:31.294419 makedir: /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/tests
161 12:11:31.294519 makedir: /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/results
162 12:11:31.294622 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-add-keys
163 12:11:31.294830 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-add-sources
164 12:11:31.294978 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-background-process-start
165 12:11:31.295108 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-background-process-stop
166 12:11:31.295236 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-common-functions
167 12:11:31.295540 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-echo-ipv4
168 12:11:31.295673 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-install-packages
169 12:11:31.295800 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-installed-packages
170 12:11:31.295927 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-os-build
171 12:11:31.296052 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-probe-channel
172 12:11:31.296178 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-probe-ip
173 12:11:31.296305 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-target-ip
174 12:11:31.296431 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-target-mac
175 12:11:31.296555 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-target-storage
176 12:11:31.296684 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-test-case
177 12:11:31.296813 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-test-event
178 12:11:31.296940 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-test-feedback
179 12:11:31.297065 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-test-raise
180 12:11:31.297192 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-test-reference
181 12:11:31.297317 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-test-runner
182 12:11:31.297443 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-test-set
183 12:11:31.297568 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-test-shell
184 12:11:31.297696 Updating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-add-keys (debian)
185 12:11:31.297851 Updating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-add-sources (debian)
186 12:11:31.297992 Updating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-install-packages (debian)
187 12:11:31.298132 Updating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-installed-packages (debian)
188 12:11:31.298271 Updating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/bin/lava-os-build (debian)
189 12:11:31.298393 Creating /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/environment
190 12:11:31.298492 LAVA metadata
191 12:11:31.298563 - LAVA_JOB_ID=12669504
192 12:11:31.298627 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:11:31.298734 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 12:11:31.298846 skipped lava-vland-overlay
195 12:11:31.298922 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:11:31.299000 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 12:11:31.299060 skipped lava-multinode-overlay
198 12:11:31.299132 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:11:31.299223 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 12:11:31.299299 Loading test definitions
201 12:11:31.299437 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 12:11:31.299510 Using /lava-12669504 at stage 0
203 12:11:31.299803 uuid=12669504_1.6.2.3.1 testdef=None
204 12:11:31.299892 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:11:31.299978 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 12:11:31.300432 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:11:31.300655 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 12:11:31.301216 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:11:31.301447 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 12:11:31.301991 runner path: /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/0/tests/0_timesync-off test_uuid 12669504_1.6.2.3.1
213 12:11:31.302146 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:11:31.302372 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 12:11:31.302445 Using /lava-12669504 at stage 0
217 12:11:31.302543 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:11:31.302623 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/0/tests/1_kselftest-arm64'
219 12:11:38.327411 Running '/usr/bin/git checkout kernelci.org
220 12:11:38.477655 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 12:11:38.478453 uuid=12669504_1.6.2.3.5 testdef=None
222 12:11:38.478621 end: 1.6.2.3.5 git-repo-action (duration 00:00:07) [common]
224 12:11:38.478879 start: 1.6.2.3.6 test-overlay (timeout 00:09:40) [common]
225 12:11:38.479822 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:11:38.480052 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:40) [common]
228 12:11:38.481086 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:11:38.481322 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:40) [common]
231 12:11:38.482338 runner path: /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/0/tests/1_kselftest-arm64 test_uuid 12669504_1.6.2.3.5
232 12:11:38.482432 BOARD='mt8192-asurada-spherion-r0'
233 12:11:38.482526 BRANCH='cip-gitlab'
234 12:11:38.482592 SKIPFILE='/dev/null'
235 12:11:38.482653 SKIP_INSTALL='True'
236 12:11:38.482711 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:11:38.482769 TST_CASENAME=''
238 12:11:38.482824 TST_CMDFILES='arm64'
239 12:11:38.482968 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:11:38.483333 Creating lava-test-runner.conf files
242 12:11:38.483463 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12669504/lava-overlay-eb40a29a/lava-12669504/0 for stage 0
243 12:11:38.483599 - 0_timesync-off
244 12:11:38.483707 - 1_kselftest-arm64
245 12:11:38.483818 end: 1.6.2.3 test-definition (duration 00:00:07) [common]
246 12:11:38.483908 start: 1.6.2.4 compress-overlay (timeout 00:09:40) [common]
247 12:11:45.984301 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 12:11:45.984454 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:33) [common]
249 12:11:45.984547 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:11:45.984646 end: 1.6.2 lava-overlay (duration 00:00:15) [common]
251 12:11:45.984740 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:33) [common]
252 12:11:46.106014 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:11:46.106404 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
254 12:11:46.106522 extracting modules file /var/lib/lava/dispatcher/tmp/12669504/tftp-deploy-_dcldchd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12669504/extract-nfsrootfs-y7wd4bc_
255 12:11:46.337571 extracting modules file /var/lib/lava/dispatcher/tmp/12669504/tftp-deploy-_dcldchd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12669504/extract-overlay-ramdisk-ull4k4fe/ramdisk
256 12:11:46.569096 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 12:11:46.569257 start: 1.6.5 apply-overlay-tftp (timeout 00:09:32) [common]
258 12:11:46.569355 [common] Applying overlay to NFS
259 12:11:46.569425 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12669504/compress-overlay-epc_fhyw/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12669504/extract-nfsrootfs-y7wd4bc_
260 12:11:47.498478 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:11:47.498646 start: 1.6.6 configure-preseed-file (timeout 00:09:31) [common]
262 12:11:47.498741 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:11:47.498835 start: 1.6.7 compress-ramdisk (timeout 00:09:31) [common]
264 12:11:47.498914 Building ramdisk /var/lib/lava/dispatcher/tmp/12669504/extract-overlay-ramdisk-ull4k4fe/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12669504/extract-overlay-ramdisk-ull4k4fe/ramdisk
265 12:11:47.830596 >> 119414 blocks
266 12:11:49.767371 rename /var/lib/lava/dispatcher/tmp/12669504/extract-overlay-ramdisk-ull4k4fe/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12669504/tftp-deploy-_dcldchd/ramdisk/ramdisk.cpio.gz
267 12:11:49.767869 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:11:49.767987 start: 1.6.8 prepare-kernel (timeout 00:09:29) [common]
269 12:11:49.768087 start: 1.6.8.1 prepare-fit (timeout 00:09:29) [common]
270 12:11:49.768197 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12669504/tftp-deploy-_dcldchd/kernel/Image'
271 12:12:02.447158 Returned 0 in 12 seconds
272 12:12:02.547858 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12669504/tftp-deploy-_dcldchd/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12669504/tftp-deploy-_dcldchd/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12669504/tftp-deploy-_dcldchd/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12669504/tftp-deploy-_dcldchd/kernel/image.itb
273 12:12:02.915230 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:12:02.915671 output: Created: Wed Jan 31 12:12:02 2024
275 12:12:02.915748 output: Image 0 (kernel-1)
276 12:12:02.915812 output: Description:
277 12:12:02.915872 output: Created: Wed Jan 31 12:12:02 2024
278 12:12:02.915934 output: Type: Kernel Image
279 12:12:02.915992 output: Compression: lzma compressed
280 12:12:02.916049 output: Data Size: 12047284 Bytes = 11764.93 KiB = 11.49 MiB
281 12:12:02.916108 output: Architecture: AArch64
282 12:12:02.916164 output: OS: Linux
283 12:12:02.916234 output: Load Address: 0x00000000
284 12:12:02.916289 output: Entry Point: 0x00000000
285 12:12:02.916347 output: Hash algo: crc32
286 12:12:02.916407 output: Hash value: 5a47eb78
287 12:12:02.916467 output: Image 1 (fdt-1)
288 12:12:02.916521 output: Description: mt8192-asurada-spherion-r0
289 12:12:02.916581 output: Created: Wed Jan 31 12:12:02 2024
290 12:12:02.916669 output: Type: Flat Device Tree
291 12:12:02.916756 output: Compression: uncompressed
292 12:12:02.916838 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 12:12:02.916907 output: Architecture: AArch64
294 12:12:02.916963 output: Hash algo: crc32
295 12:12:02.917017 output: Hash value: cc4352de
296 12:12:02.917070 output: Image 2 (ramdisk-1)
297 12:12:02.917123 output: Description: unavailable
298 12:12:02.917175 output: Created: Wed Jan 31 12:12:02 2024
299 12:12:02.917228 output: Type: RAMDisk Image
300 12:12:02.917280 output: Compression: Unknown Compression
301 12:12:02.917333 output: Data Size: 17793533 Bytes = 17376.50 KiB = 16.97 MiB
302 12:12:02.917387 output: Architecture: AArch64
303 12:12:02.917439 output: OS: Linux
304 12:12:02.917492 output: Load Address: unavailable
305 12:12:02.917545 output: Entry Point: unavailable
306 12:12:02.917597 output: Hash algo: crc32
307 12:12:02.917649 output: Hash value: dd06722d
308 12:12:02.917701 output: Default Configuration: 'conf-1'
309 12:12:02.917753 output: Configuration 0 (conf-1)
310 12:12:02.917805 output: Description: mt8192-asurada-spherion-r0
311 12:12:02.917858 output: Kernel: kernel-1
312 12:12:02.917910 output: Init Ramdisk: ramdisk-1
313 12:12:02.917962 output: FDT: fdt-1
314 12:12:02.918014 output: Loadables: kernel-1
315 12:12:02.918066 output:
316 12:12:02.918268 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 12:12:02.918371 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 12:12:02.918485 end: 1.6 prepare-tftp-overlay (duration 00:00:35) [common]
319 12:12:02.918580 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 12:12:02.918657 No LXC device requested
321 12:12:02.918738 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:12:02.918819 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 12:12:02.918900 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:12:02.918972 Checking files for TFTP limit of 4294967296 bytes.
325 12:12:02.919516 end: 1 tftp-deploy (duration 00:00:44) [common]
326 12:12:02.919620 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:12:02.919743 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:12:02.919915 substitutions:
329 12:12:02.919987 - {DTB}: 12669504/tftp-deploy-_dcldchd/dtb/mt8192-asurada-spherion-r0.dtb
330 12:12:02.920055 - {INITRD}: 12669504/tftp-deploy-_dcldchd/ramdisk/ramdisk.cpio.gz
331 12:12:02.920115 - {KERNEL}: 12669504/tftp-deploy-_dcldchd/kernel/Image
332 12:12:02.920174 - {LAVA_MAC}: None
333 12:12:02.920263 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12669504/extract-nfsrootfs-y7wd4bc_
334 12:12:02.920352 - {NFS_SERVER_IP}: 192.168.201.1
335 12:12:02.920439 - {PRESEED_CONFIG}: None
336 12:12:02.920517 - {PRESEED_LOCAL}: None
337 12:12:02.920575 - {RAMDISK}: 12669504/tftp-deploy-_dcldchd/ramdisk/ramdisk.cpio.gz
338 12:12:02.920632 - {ROOT_PART}: None
339 12:12:02.920687 - {ROOT}: None
340 12:12:02.920742 - {SERVER_IP}: 192.168.201.1
341 12:12:02.920796 - {TEE}: None
342 12:12:02.920850 Parsed boot commands:
343 12:12:02.920904 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:12:02.921095 Parsed boot commands: tftpboot 192.168.201.1 12669504/tftp-deploy-_dcldchd/kernel/image.itb 12669504/tftp-deploy-_dcldchd/kernel/cmdline
345 12:12:02.921186 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:12:02.921276 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:12:02.921372 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:12:02.921458 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:12:02.921532 Not connected, no need to disconnect.
350 12:12:02.921605 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:12:02.921684 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:12:02.921752 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 12:12:02.925844 Setting prompt string to ['lava-test: # ']
354 12:12:02.926231 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:12:02.926340 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:12:02.926442 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:12:02.926533 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:12:02.926747 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
359 12:12:08.060666 >> Command sent successfully.
360 12:12:08.063048 Returned 0 in 5 seconds
361 12:12:08.163431 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:12:08.163761 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:12:08.163865 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:12:08.163956 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:12:08.164022 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:12:08.164090 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:12:08.164359 [Enter `^Ec?' for help]
369 12:12:08.337408
370 12:12:08.337564
371 12:12:08.337634 F0: 102B 0000
372 12:12:08.337700
373 12:12:08.337760 F3: 1001 0000 [0200]
374 12:12:08.340805
375 12:12:08.340888 F3: 1001 0000
376 12:12:08.340956
377 12:12:08.341018 F7: 102D 0000
378 12:12:08.341078
379 12:12:08.343851 F1: 0000 0000
380 12:12:08.343935
381 12:12:08.344002 V0: 0000 0000 [0001]
382 12:12:08.344067
383 12:12:08.347525 00: 0007 8000
384 12:12:08.347613
385 12:12:08.347679 01: 0000 0000
386 12:12:08.347746
387 12:12:08.350463 BP: 0C00 0209 [0000]
388 12:12:08.350546
389 12:12:08.350612 G0: 1182 0000
390 12:12:08.350674
391 12:12:08.354489 EC: 0000 0021 [4000]
392 12:12:08.354573
393 12:12:08.354639 S7: 0000 0000 [0000]
394 12:12:08.354701
395 12:12:08.357607 CC: 0000 0000 [0001]
396 12:12:08.357690
397 12:12:08.357757 T0: 0000 0040 [010F]
398 12:12:08.357820
399 12:12:08.357878 Jump to BL
400 12:12:08.357937
401 12:12:08.384414
402 12:12:08.384501
403 12:12:08.384568
404 12:12:08.391235 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:12:08.394854 ARM64: Exception handlers installed.
406 12:12:08.398957 ARM64: Testing exception
407 12:12:08.401832 ARM64: Done test exception
408 12:12:08.408699 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:12:08.419003 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:12:08.425146 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:12:08.436846 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:12:08.441759 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:12:08.452021 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:12:08.462830 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:12:08.468927 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:12:08.487420 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:12:08.490674 WDT: Last reset was cold boot
418 12:12:08.494107 SPI1(PAD0) initialized at 2873684 Hz
419 12:12:08.497124 SPI5(PAD0) initialized at 992727 Hz
420 12:12:08.500856 VBOOT: Loading verstage.
421 12:12:08.507024 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:12:08.510745 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:12:08.513700 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:12:08.517025 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:12:08.525188 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:12:08.531205 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:12:08.542360 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 12:12:08.542498
429 12:12:08.542593
430 12:12:08.552144 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:12:08.555590 ARM64: Exception handlers installed.
432 12:12:08.558692 ARM64: Testing exception
433 12:12:08.558793 ARM64: Done test exception
434 12:12:08.565857 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:12:08.569108 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:12:08.583768 Probing TPM: . done!
437 12:12:08.583921 TPM ready after 0 ms
438 12:12:08.591774 Connected to device vid:did:rid of 1ae0:0028:00
439 12:12:08.598838 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 12:12:08.655210 Initialized TPM device CR50 revision 0
441 12:12:08.667455 tlcl_send_startup: Startup return code is 0
442 12:12:08.667689 TPM: setup succeeded
443 12:12:08.678919 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:12:08.687879 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:12:08.698674 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:12:08.708424 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:12:08.711443 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:12:08.721661 in-header: 03 07 00 00 08 00 00 00
449 12:12:08.725087 in-data: aa e4 47 04 13 02 00 00
450 12:12:08.728871 Chrome EC: UHEPI supported
451 12:12:08.736244 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:12:08.740016 in-header: 03 95 00 00 08 00 00 00
453 12:12:08.740171 in-data: 18 20 20 08 00 00 00 00
454 12:12:08.743507 Phase 1
455 12:12:08.747923 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:12:08.750918 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:12:08.758478 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:12:08.761941 Recovery requested (1009000e)
459 12:12:08.769128 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:12:08.774461 tlcl_extend: response is 0
461 12:12:08.783835 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:12:08.789676 tlcl_extend: response is 0
463 12:12:08.796119 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:12:08.816622 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 12:12:08.823544 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:12:08.823649
467 12:12:08.823734
468 12:12:08.833295 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:12:08.836132 ARM64: Exception handlers installed.
470 12:12:08.839581 ARM64: Testing exception
471 12:12:08.839663 ARM64: Done test exception
472 12:12:08.861611 pmic_efuse_setting: Set efuses in 11 msecs
473 12:12:08.865235 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:12:08.872164 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:12:08.875079 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:12:08.882245 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:12:08.885765 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:12:08.889199 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:12:08.896986 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:12:08.900396 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:12:08.904056 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:12:08.907459 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:12:08.914985 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:12:08.918499 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:12:08.922752 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:12:08.926439 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:12:08.934075 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:12:08.940971 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:12:08.944600 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:12:08.951921 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:12:08.955548 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:12:08.962686 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:12:08.966717 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:12:08.974055 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:12:08.977565 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:12:08.985021 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:12:08.988463 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:12:08.996576 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:12:09.003324 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:12:09.007123 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:12:09.010707 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:12:09.017760 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:12:09.021728 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:12:09.025462 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:12:09.032309 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:12:09.035740 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:12:09.039134 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:12:09.046944 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:12:09.050206 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:12:09.057762 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:12:09.060764 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:12:09.064390 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:12:09.068169 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:12:09.075256 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:12:09.078879 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:12:09.082653 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:12:09.086629 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:12:09.090313 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:12:09.097344 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:12:09.101312 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:12:09.104858 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:12:09.108608 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:12:09.112469 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:12:09.116210 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:12:09.126605 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:12:09.134092 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:12:09.138104 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:12:09.145017 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:12:09.155935 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:12:09.159603 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:12:09.162972 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:12:09.167242 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:12:09.174998 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
534 12:12:09.178863 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:12:09.187502 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 12:12:09.190967 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:12:09.199346 [RTC]rtc_get_frequency_meter,154: input=15, output=851
538 12:12:09.209278 [RTC]rtc_get_frequency_meter,154: input=7, output=724
539 12:12:09.218646 [RTC]rtc_get_frequency_meter,154: input=11, output=789
540 12:12:09.227680 [RTC]rtc_get_frequency_meter,154: input=13, output=820
541 12:12:09.238182 [RTC]rtc_get_frequency_meter,154: input=12, output=805
542 12:12:09.247181 [RTC]rtc_get_frequency_meter,154: input=11, output=788
543 12:12:09.256060 [RTC]rtc_get_frequency_meter,154: input=12, output=804
544 12:12:09.259257 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 12:12:09.267125 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 12:12:09.270682 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 12:12:09.274782 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 12:12:09.277853 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 12:12:09.281797 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 12:12:09.285431 ADC[4]: Raw value=903325 ID=7
551 12:12:09.289298 ADC[3]: Raw value=213916 ID=1
552 12:12:09.289401 RAM Code: 0x71
553 12:12:09.292856 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 12:12:09.299999 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 12:12:09.307977 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 12:12:09.314909 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 12:12:09.318843 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 12:12:09.322744 in-header: 03 07 00 00 08 00 00 00
559 12:12:09.325599 in-data: aa e4 47 04 13 02 00 00
560 12:12:09.325693 Chrome EC: UHEPI supported
561 12:12:09.333226 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 12:12:09.336717 in-header: 03 95 00 00 08 00 00 00
563 12:12:09.340802 in-data: 18 20 20 08 00 00 00 00
564 12:12:09.344101 MRC: failed to locate region type 0.
565 12:12:09.352197 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 12:12:09.352328 DRAM-K: Running full calibration
567 12:12:09.359398 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 12:12:09.359513 header.status = 0x0
569 12:12:09.363639 header.version = 0x6 (expected: 0x6)
570 12:12:09.366516 header.size = 0xd00 (expected: 0xd00)
571 12:12:09.370728 header.flags = 0x0
572 12:12:09.374103 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 12:12:09.393859 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 12:12:09.400976 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 12:12:09.404837 dram_init: ddr_geometry: 2
576 12:12:09.404955 [EMI] MDL number = 2
577 12:12:09.408341 [EMI] Get MDL freq = 0
578 12:12:09.408441 dram_init: ddr_type: 0
579 12:12:09.411692 is_discrete_lpddr4: 1
580 12:12:09.415554 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 12:12:09.415648
582 12:12:09.415714
583 12:12:09.419115 [Bian_co] ETT version 0.0.0.1
584 12:12:09.423711 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 12:12:09.423804
586 12:12:09.426816 dramc_set_vcore_voltage set vcore to 650000
587 12:12:09.426896 Read voltage for 800, 4
588 12:12:09.430299 Vio18 = 0
589 12:12:09.430377 Vcore = 650000
590 12:12:09.430448 Vdram = 0
591 12:12:09.430509 Vddq = 0
592 12:12:09.434372 Vmddr = 0
593 12:12:09.434454 dram_init: config_dvfs: 1
594 12:12:09.441940 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 12:12:09.445120 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 12:12:09.448238 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 12:12:09.454900 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 12:12:09.458522 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 12:12:09.461776 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 12:12:09.461877 MEM_TYPE=3, freq_sel=18
601 12:12:09.464824 sv_algorithm_assistance_LP4_1600
602 12:12:09.469214 ============ PULL DRAM RESETB DOWN ============
603 12:12:09.476260 ========== PULL DRAM RESETB DOWN end =========
604 12:12:09.479882 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 12:12:09.483730 ===================================
606 12:12:09.483830 LPDDR4 DRAM CONFIGURATION
607 12:12:09.487278 ===================================
608 12:12:09.490433 EX_ROW_EN[0] = 0x0
609 12:12:09.490556 EX_ROW_EN[1] = 0x0
610 12:12:09.493978 LP4Y_EN = 0x0
611 12:12:09.494067 WORK_FSP = 0x0
612 12:12:09.497568 WL = 0x2
613 12:12:09.497656 RL = 0x2
614 12:12:09.500465 BL = 0x2
615 12:12:09.504008 RPST = 0x0
616 12:12:09.504098 RD_PRE = 0x0
617 12:12:09.506941 WR_PRE = 0x1
618 12:12:09.507043 WR_PST = 0x0
619 12:12:09.510244 DBI_WR = 0x0
620 12:12:09.510335 DBI_RD = 0x0
621 12:12:09.513645 OTF = 0x1
622 12:12:09.517383 ===================================
623 12:12:09.520803 ===================================
624 12:12:09.520897 ANA top config
625 12:12:09.523725 ===================================
626 12:12:09.527130 DLL_ASYNC_EN = 0
627 12:12:09.530786 ALL_SLAVE_EN = 1
628 12:12:09.530877 NEW_RANK_MODE = 1
629 12:12:09.533606 DLL_IDLE_MODE = 1
630 12:12:09.537026 LP45_APHY_COMB_EN = 1
631 12:12:09.540746 TX_ODT_DIS = 1
632 12:12:09.540855 NEW_8X_MODE = 1
633 12:12:09.543877 ===================================
634 12:12:09.546978 ===================================
635 12:12:09.550314 data_rate = 1600
636 12:12:09.553426 CKR = 1
637 12:12:09.557042 DQ_P2S_RATIO = 8
638 12:12:09.560430 ===================================
639 12:12:09.563608 CA_P2S_RATIO = 8
640 12:12:09.567674 DQ_CA_OPEN = 0
641 12:12:09.567780 DQ_SEMI_OPEN = 0
642 12:12:09.571030 CA_SEMI_OPEN = 0
643 12:12:09.574158 CA_FULL_RATE = 0
644 12:12:09.577422 DQ_CKDIV4_EN = 1
645 12:12:09.580652 CA_CKDIV4_EN = 1
646 12:12:09.580745 CA_PREDIV_EN = 0
647 12:12:09.584092 PH8_DLY = 0
648 12:12:09.587242 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 12:12:09.590638 DQ_AAMCK_DIV = 4
650 12:12:09.593839 CA_AAMCK_DIV = 4
651 12:12:09.597581 CA_ADMCK_DIV = 4
652 12:12:09.597672 DQ_TRACK_CA_EN = 0
653 12:12:09.600636 CA_PICK = 800
654 12:12:09.604114 CA_MCKIO = 800
655 12:12:09.607647 MCKIO_SEMI = 0
656 12:12:09.611286 PLL_FREQ = 3068
657 12:12:09.615340 DQ_UI_PI_RATIO = 32
658 12:12:09.615467 CA_UI_PI_RATIO = 0
659 12:12:09.619061 ===================================
660 12:12:09.622887 ===================================
661 12:12:09.626550 memory_type:LPDDR4
662 12:12:09.626635 GP_NUM : 10
663 12:12:09.630110 SRAM_EN : 1
664 12:12:09.630188 MD32_EN : 0
665 12:12:09.634078 ===================================
666 12:12:09.637441 [ANA_INIT] >>>>>>>>>>>>>>
667 12:12:09.641506 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 12:12:09.644441 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 12:12:09.647667 ===================================
670 12:12:09.647747 data_rate = 1600,PCW = 0X7600
671 12:12:09.651406 ===================================
672 12:12:09.654420 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 12:12:09.661333 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 12:12:09.667569 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 12:12:09.670846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 12:12:09.674463 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 12:12:09.677882 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 12:12:09.681701 [ANA_INIT] flow start
679 12:12:09.681792 [ANA_INIT] PLL >>>>>>>>
680 12:12:09.684749 [ANA_INIT] PLL <<<<<<<<
681 12:12:09.687596 [ANA_INIT] MIDPI >>>>>>>>
682 12:12:09.691222 [ANA_INIT] MIDPI <<<<<<<<
683 12:12:09.691318 [ANA_INIT] DLL >>>>>>>>
684 12:12:09.694489 [ANA_INIT] flow end
685 12:12:09.697638 ============ LP4 DIFF to SE enter ============
686 12:12:09.701180 ============ LP4 DIFF to SE exit ============
687 12:12:09.704573 [ANA_INIT] <<<<<<<<<<<<<
688 12:12:09.707522 [Flow] Enable top DCM control >>>>>
689 12:12:09.710875 [Flow] Enable top DCM control <<<<<
690 12:12:09.714596 Enable DLL master slave shuffle
691 12:12:09.721094 ==============================================================
692 12:12:09.721323 Gating Mode config
693 12:12:09.727302 ==============================================================
694 12:12:09.727463 Config description:
695 12:12:09.737274 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 12:12:09.744128 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 12:12:09.750430 SELPH_MODE 0: By rank 1: By Phase
698 12:12:09.754015 ==============================================================
699 12:12:09.757340 GAT_TRACK_EN = 1
700 12:12:09.760405 RX_GATING_MODE = 2
701 12:12:09.764243 RX_GATING_TRACK_MODE = 2
702 12:12:09.767026 SELPH_MODE = 1
703 12:12:09.770184 PICG_EARLY_EN = 1
704 12:12:09.773753 VALID_LAT_VALUE = 1
705 12:12:09.780836 ==============================================================
706 12:12:09.783767 Enter into Gating configuration >>>>
707 12:12:09.787039 Exit from Gating configuration <<<<
708 12:12:09.790552 Enter into DVFS_PRE_config >>>>>
709 12:12:09.800389 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 12:12:09.803509 Exit from DVFS_PRE_config <<<<<
711 12:12:09.807030 Enter into PICG configuration >>>>
712 12:12:09.810701 Exit from PICG configuration <<<<
713 12:12:09.813613 [RX_INPUT] configuration >>>>>
714 12:12:09.813717 [RX_INPUT] configuration <<<<<
715 12:12:09.820063 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 12:12:09.827177 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 12:12:09.829834 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 12:12:09.836479 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 12:12:09.843252 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 12:12:09.849604 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 12:12:09.853528 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 12:12:09.856255 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 12:12:09.863048 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 12:12:09.866181 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 12:12:09.869598 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 12:12:09.876628 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 12:12:09.879611 ===================================
728 12:12:09.879737 LPDDR4 DRAM CONFIGURATION
729 12:12:09.883015 ===================================
730 12:12:09.886024 EX_ROW_EN[0] = 0x0
731 12:12:09.889257 EX_ROW_EN[1] = 0x0
732 12:12:09.889359 LP4Y_EN = 0x0
733 12:12:09.892900 WORK_FSP = 0x0
734 12:12:09.892989 WL = 0x2
735 12:12:09.895848 RL = 0x2
736 12:12:09.895935 BL = 0x2
737 12:12:09.899275 RPST = 0x0
738 12:12:09.899423 RD_PRE = 0x0
739 12:12:09.902838 WR_PRE = 0x1
740 12:12:09.902938 WR_PST = 0x0
741 12:12:09.906058 DBI_WR = 0x0
742 12:12:09.906145 DBI_RD = 0x0
743 12:12:09.909870 OTF = 0x1
744 12:12:09.912624 ===================================
745 12:12:09.916273 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 12:12:09.919712 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 12:12:09.925893 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 12:12:09.929154 ===================================
749 12:12:09.929249 LPDDR4 DRAM CONFIGURATION
750 12:12:09.932910 ===================================
751 12:12:09.935584 EX_ROW_EN[0] = 0x10
752 12:12:09.935703 EX_ROW_EN[1] = 0x0
753 12:12:09.939392 LP4Y_EN = 0x0
754 12:12:09.939529 WORK_FSP = 0x0
755 12:12:09.942712 WL = 0x2
756 12:12:09.942799 RL = 0x2
757 12:12:09.946069 BL = 0x2
758 12:12:09.949402 RPST = 0x0
759 12:12:09.949525 RD_PRE = 0x0
760 12:12:09.952359 WR_PRE = 0x1
761 12:12:09.952449 WR_PST = 0x0
762 12:12:09.955912 DBI_WR = 0x0
763 12:12:09.955998 DBI_RD = 0x0
764 12:12:09.959348 OTF = 0x1
765 12:12:09.963119 ===================================
766 12:12:09.965753 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 12:12:09.971181 nWR fixed to 40
768 12:12:09.975107 [ModeRegInit_LP4] CH0 RK0
769 12:12:09.975219 [ModeRegInit_LP4] CH0 RK1
770 12:12:09.977869 [ModeRegInit_LP4] CH1 RK0
771 12:12:09.981289 [ModeRegInit_LP4] CH1 RK1
772 12:12:09.981380 match AC timing 13
773 12:12:09.988298 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 12:12:09.991373 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 12:12:09.994984 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 12:12:10.001526 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 12:12:10.004626 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 12:12:10.004720 [EMI DOE] emi_dcm 0
779 12:12:10.011228 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 12:12:10.011377 ==
781 12:12:10.014591 Dram Type= 6, Freq= 0, CH_0, rank 0
782 12:12:10.017994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 12:12:10.018090 ==
784 12:12:10.024612 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 12:12:10.031261 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 12:12:10.038674 [CA 0] Center 38 (7~69) winsize 63
787 12:12:10.042074 [CA 1] Center 37 (7~68) winsize 62
788 12:12:10.045534 [CA 2] Center 35 (5~65) winsize 61
789 12:12:10.048660 [CA 3] Center 35 (4~66) winsize 63
790 12:12:10.052133 [CA 4] Center 34 (3~65) winsize 63
791 12:12:10.055686 [CA 5] Center 33 (3~64) winsize 62
792 12:12:10.055814
793 12:12:10.058795 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 12:12:10.058882
795 12:12:10.062372 [CATrainingPosCal] consider 1 rank data
796 12:12:10.065560 u2DelayCellTimex100 = 270/100 ps
797 12:12:10.069034 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
798 12:12:10.072024 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 12:12:10.079090 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
800 12:12:10.082019 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 12:12:10.085513 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
802 12:12:10.089060 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 12:12:10.089163
804 12:12:10.092148 CA PerBit enable=1, Macro0, CA PI delay=33
805 12:12:10.092256
806 12:12:10.095269 [CBTSetCACLKResult] CA Dly = 33
807 12:12:10.095398 CS Dly: 6 (0~37)
808 12:12:10.098819 ==
809 12:12:10.098899 Dram Type= 6, Freq= 0, CH_0, rank 1
810 12:12:10.105737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 12:12:10.105863 ==
812 12:12:10.108917 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 12:12:10.115197 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 12:12:10.125646 [CA 0] Center 38 (7~69) winsize 63
815 12:12:10.128454 [CA 1] Center 37 (7~68) winsize 62
816 12:12:10.131791 [CA 2] Center 35 (4~66) winsize 63
817 12:12:10.135024 [CA 3] Center 35 (4~66) winsize 63
818 12:12:10.138827 [CA 4] Center 34 (3~65) winsize 63
819 12:12:10.141475 [CA 5] Center 33 (3~64) winsize 62
820 12:12:10.141562
821 12:12:10.144783 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 12:12:10.144866
823 12:12:10.148381 [CATrainingPosCal] consider 2 rank data
824 12:12:10.151670 u2DelayCellTimex100 = 270/100 ps
825 12:12:10.155507 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
826 12:12:10.161528 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 12:12:10.164771 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
828 12:12:10.168032 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
829 12:12:10.171586 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
830 12:12:10.175279 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 12:12:10.175409
832 12:12:10.178073 CA PerBit enable=1, Macro0, CA PI delay=33
833 12:12:10.178160
834 12:12:10.181666 [CBTSetCACLKResult] CA Dly = 33
835 12:12:10.184907 CS Dly: 6 (0~38)
836 12:12:10.185028
837 12:12:10.188880 ----->DramcWriteLeveling(PI) begin...
838 12:12:10.188995 ==
839 12:12:10.192238 Dram Type= 6, Freq= 0, CH_0, rank 0
840 12:12:10.196210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 12:12:10.196309 ==
842 12:12:10.199664 Write leveling (Byte 0): 31 => 31
843 12:12:10.199801 Write leveling (Byte 1): 25 => 25
844 12:12:10.203282 DramcWriteLeveling(PI) end<-----
845 12:12:10.203423
846 12:12:10.203489 ==
847 12:12:10.207222 Dram Type= 6, Freq= 0, CH_0, rank 0
848 12:12:10.209849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 12:12:10.213317 ==
850 12:12:10.213415 [Gating] SW mode calibration
851 12:12:10.220336 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 12:12:10.227181 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 12:12:10.230330 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 12:12:10.234357 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 12:12:10.240540 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 12:12:10.244330 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:12:10.247668 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:12:10.253861 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:12:10.257110 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:12:10.260477 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:12:10.267241 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:12:10.270428 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:12:10.274016 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:12:10.280699 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:12:10.283609 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 12:12:10.286995 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 12:12:10.293609 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 12:12:10.297179 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 12:12:10.300424 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:12:10.306754 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 12:12:10.310311 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 12:12:10.313787 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 12:12:10.320707 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 12:12:10.323844 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 12:12:10.327132 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 12:12:10.333352 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 12:12:10.336652 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 12:12:10.339981 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 12:12:10.346398 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
880 12:12:10.350201 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
881 12:12:10.353512 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 12:12:10.360152 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 12:12:10.363323 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 12:12:10.366640 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 12:12:10.373123 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 12:12:10.376969 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
887 12:12:10.379789 0 10 8 | B1->B0 | 3333 2929 | 0 1 | (0 1) (1 0)
888 12:12:10.386393 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
889 12:12:10.389599 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 12:12:10.393185 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 12:12:10.399571 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 12:12:10.402655 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 12:12:10.406058 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 12:12:10.412907 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
895 12:12:10.415990 0 11 8 | B1->B0 | 2525 4242 | 0 0 | (0 0) (0 0)
896 12:12:10.419813 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
897 12:12:10.425872 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 12:12:10.429688 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 12:12:10.432859 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 12:12:10.435916 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 12:12:10.443003 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 12:12:10.446125 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 12:12:10.449162 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 12:12:10.456515 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:12:10.459250 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:12:10.462464 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:12:10.469144 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:12:10.472465 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:12:10.475838 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:12:10.482497 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:12:10.485751 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:12:10.488859 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 12:12:10.495626 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 12:12:10.498996 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 12:12:10.502385 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 12:12:10.508827 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 12:12:10.512195 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 12:12:10.515311 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 12:12:10.522256 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 12:12:10.525429 Total UI for P1: 0, mck2ui 16
921 12:12:10.528762 best dqsien dly found for B0: ( 0, 14, 4)
922 12:12:10.528845 Total UI for P1: 0, mck2ui 16
923 12:12:10.535532 best dqsien dly found for B1: ( 0, 14, 6)
924 12:12:10.538491 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
925 12:12:10.542408 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
926 12:12:10.542523
927 12:12:10.545639 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
928 12:12:10.549029 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 12:12:10.551921 [Gating] SW calibration Done
930 12:12:10.552105 ==
931 12:12:10.555714 Dram Type= 6, Freq= 0, CH_0, rank 0
932 12:12:10.558744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 12:12:10.558821 ==
934 12:12:10.562120 RX Vref Scan: 0
935 12:12:10.562230
936 12:12:10.562338 RX Vref 0 -> 0, step: 1
937 12:12:10.562421
938 12:12:10.566464 RX Delay -130 -> 252, step: 16
939 12:12:10.569297 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
940 12:12:10.572498 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
941 12:12:10.579045 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
942 12:12:10.582241 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
943 12:12:10.585743 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
944 12:12:10.588803 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
945 12:12:10.595616 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
946 12:12:10.599232 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
947 12:12:10.602156 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
948 12:12:10.605628 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
949 12:12:10.609033 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
950 12:12:10.615626 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
951 12:12:10.618834 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
952 12:12:10.622349 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
953 12:12:10.625526 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
954 12:12:10.628863 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
955 12:12:10.632254 ==
956 12:12:10.635262 Dram Type= 6, Freq= 0, CH_0, rank 0
957 12:12:10.638696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 12:12:10.638781 ==
959 12:12:10.638846 DQS Delay:
960 12:12:10.642152 DQS0 = 0, DQS1 = 0
961 12:12:10.642238 DQM Delay:
962 12:12:10.645389 DQM0 = 93, DQM1 = 78
963 12:12:10.645473 DQ Delay:
964 12:12:10.648517 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
965 12:12:10.652022 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
966 12:12:10.655656 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
967 12:12:10.658639 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
968 12:12:10.658733
969 12:12:10.658799
970 12:12:10.658859 ==
971 12:12:10.661853 Dram Type= 6, Freq= 0, CH_0, rank 0
972 12:12:10.664887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 12:12:10.664973 ==
974 12:12:10.665036
975 12:12:10.665095
976 12:12:10.668506 TX Vref Scan disable
977 12:12:10.672230 == TX Byte 0 ==
978 12:12:10.675218 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
979 12:12:10.678168 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
980 12:12:10.682380 == TX Byte 1 ==
981 12:12:10.685425 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
982 12:12:10.688378 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
983 12:12:10.688481 ==
984 12:12:10.691795 Dram Type= 6, Freq= 0, CH_0, rank 0
985 12:12:10.698264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
986 12:12:10.698391 ==
987 12:12:10.710471 TX Vref=22, minBit 0, minWin=27, winSum=437
988 12:12:10.713713 TX Vref=24, minBit 1, minWin=27, winSum=442
989 12:12:10.717164 TX Vref=26, minBit 2, minWin=27, winSum=446
990 12:12:10.720561 TX Vref=28, minBit 1, minWin=27, winSum=447
991 12:12:10.723950 TX Vref=30, minBit 0, minWin=28, winSum=450
992 12:12:10.727725 TX Vref=32, minBit 2, minWin=27, winSum=449
993 12:12:10.733739 [TxChooseVref] Worse bit 0, Min win 28, Win sum 450, Final Vref 30
994 12:12:10.733868
995 12:12:10.737370 Final TX Range 1 Vref 30
996 12:12:10.737472
997 12:12:10.737570 ==
998 12:12:10.740717 Dram Type= 6, Freq= 0, CH_0, rank 0
999 12:12:10.743783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1000 12:12:10.743886 ==
1001 12:12:10.747538
1002 12:12:10.747652
1003 12:12:10.747749 TX Vref Scan disable
1004 12:12:10.750600 == TX Byte 0 ==
1005 12:12:10.753928 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1006 12:12:10.757800 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1007 12:12:10.760942 == TX Byte 1 ==
1008 12:12:10.763679 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1009 12:12:10.770478 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1010 12:12:10.770618
1011 12:12:10.770688 [DATLAT]
1012 12:12:10.770784 Freq=800, CH0 RK0
1013 12:12:10.770877
1014 12:12:10.773749 DATLAT Default: 0xa
1015 12:12:10.773851 0, 0xFFFF, sum = 0
1016 12:12:10.776812 1, 0xFFFF, sum = 0
1017 12:12:10.780655 2, 0xFFFF, sum = 0
1018 12:12:10.780749 3, 0xFFFF, sum = 0
1019 12:12:10.783534 4, 0xFFFF, sum = 0
1020 12:12:10.783621 5, 0xFFFF, sum = 0
1021 12:12:10.787616 6, 0xFFFF, sum = 0
1022 12:12:10.787708 7, 0xFFFF, sum = 0
1023 12:12:10.790788 8, 0xFFFF, sum = 0
1024 12:12:10.790907 9, 0x0, sum = 1
1025 12:12:10.793626 10, 0x0, sum = 2
1026 12:12:10.793712 11, 0x0, sum = 3
1027 12:12:10.793777 12, 0x0, sum = 4
1028 12:12:10.796869 best_step = 10
1029 12:12:10.796952
1030 12:12:10.797017 ==
1031 12:12:10.800378 Dram Type= 6, Freq= 0, CH_0, rank 0
1032 12:12:10.803521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1033 12:12:10.803614 ==
1034 12:12:10.807078 RX Vref Scan: 1
1035 12:12:10.807161
1036 12:12:10.810276 Set Vref Range= 32 -> 127
1037 12:12:10.810404
1038 12:12:10.810471 RX Vref 32 -> 127, step: 1
1039 12:12:10.810534
1040 12:12:10.813600 RX Delay -95 -> 252, step: 8
1041 12:12:10.813682
1042 12:12:10.817248 Set Vref, RX VrefLevel [Byte0]: 32
1043 12:12:10.820149 [Byte1]: 32
1044 12:12:10.820232
1045 12:12:10.823269 Set Vref, RX VrefLevel [Byte0]: 33
1046 12:12:10.826822 [Byte1]: 33
1047 12:12:10.830813
1048 12:12:10.830930 Set Vref, RX VrefLevel [Byte0]: 34
1049 12:12:10.834167 [Byte1]: 34
1050 12:12:10.838409
1051 12:12:10.838502 Set Vref, RX VrefLevel [Byte0]: 35
1052 12:12:10.841970 [Byte1]: 35
1053 12:12:10.846523
1054 12:12:10.846618 Set Vref, RX VrefLevel [Byte0]: 36
1055 12:12:10.849123 [Byte1]: 36
1056 12:12:10.853788
1057 12:12:10.853878 Set Vref, RX VrefLevel [Byte0]: 37
1058 12:12:10.857319 [Byte1]: 37
1059 12:12:10.861882
1060 12:12:10.861980 Set Vref, RX VrefLevel [Byte0]: 38
1061 12:12:10.864800 [Byte1]: 38
1062 12:12:10.869688
1063 12:12:10.869789 Set Vref, RX VrefLevel [Byte0]: 39
1064 12:12:10.872801 [Byte1]: 39
1065 12:12:10.876800
1066 12:12:10.876898 Set Vref, RX VrefLevel [Byte0]: 40
1067 12:12:10.880108 [Byte1]: 40
1068 12:12:10.885131
1069 12:12:10.885238 Set Vref, RX VrefLevel [Byte0]: 41
1070 12:12:10.888470 [Byte1]: 41
1071 12:12:10.892044
1072 12:12:10.892152 Set Vref, RX VrefLevel [Byte0]: 42
1073 12:12:10.894837 [Byte1]: 42
1074 12:12:10.899079
1075 12:12:10.899173 Set Vref, RX VrefLevel [Byte0]: 43
1076 12:12:10.902675 [Byte1]: 43
1077 12:12:10.907010
1078 12:12:10.907109 Set Vref, RX VrefLevel [Byte0]: 44
1079 12:12:10.910096 [Byte1]: 44
1080 12:12:10.914543
1081 12:12:10.914638 Set Vref, RX VrefLevel [Byte0]: 45
1082 12:12:10.917676 [Byte1]: 45
1083 12:12:10.922023
1084 12:12:10.922115 Set Vref, RX VrefLevel [Byte0]: 46
1085 12:12:10.925387 [Byte1]: 46
1086 12:12:10.929726
1087 12:12:10.929821 Set Vref, RX VrefLevel [Byte0]: 47
1088 12:12:10.933269 [Byte1]: 47
1089 12:12:10.937197
1090 12:12:10.937289 Set Vref, RX VrefLevel [Byte0]: 48
1091 12:12:10.940746 [Byte1]: 48
1092 12:12:10.945092
1093 12:12:10.945187 Set Vref, RX VrefLevel [Byte0]: 49
1094 12:12:10.948123 [Byte1]: 49
1095 12:12:10.952661
1096 12:12:10.952754 Set Vref, RX VrefLevel [Byte0]: 50
1097 12:12:10.955974 [Byte1]: 50
1098 12:12:10.959722
1099 12:12:10.959811 Set Vref, RX VrefLevel [Byte0]: 51
1100 12:12:10.963187 [Byte1]: 51
1101 12:12:10.967620
1102 12:12:10.967714 Set Vref, RX VrefLevel [Byte0]: 52
1103 12:12:10.971120 [Byte1]: 52
1104 12:12:10.975040
1105 12:12:10.975133 Set Vref, RX VrefLevel [Byte0]: 53
1106 12:12:10.978511 [Byte1]: 53
1107 12:12:10.983215
1108 12:12:10.983337 Set Vref, RX VrefLevel [Byte0]: 54
1109 12:12:10.985945 [Byte1]: 54
1110 12:12:10.990577
1111 12:12:10.990701 Set Vref, RX VrefLevel [Byte0]: 55
1112 12:12:10.993869 [Byte1]: 55
1113 12:12:10.998042
1114 12:12:10.998140 Set Vref, RX VrefLevel [Byte0]: 56
1115 12:12:11.001292 [Byte1]: 56
1116 12:12:11.006251
1117 12:12:11.006345 Set Vref, RX VrefLevel [Byte0]: 57
1118 12:12:11.008909 [Byte1]: 57
1119 12:12:11.013512
1120 12:12:11.013614 Set Vref, RX VrefLevel [Byte0]: 58
1121 12:12:11.016427 [Byte1]: 58
1122 12:12:11.020572
1123 12:12:11.020682 Set Vref, RX VrefLevel [Byte0]: 59
1124 12:12:11.024186 [Byte1]: 59
1125 12:12:11.028707
1126 12:12:11.028798 Set Vref, RX VrefLevel [Byte0]: 60
1127 12:12:11.031850 [Byte1]: 60
1128 12:12:11.036200
1129 12:12:11.036292 Set Vref, RX VrefLevel [Byte0]: 61
1130 12:12:11.038980 [Byte1]: 61
1131 12:12:11.043556
1132 12:12:11.043646 Set Vref, RX VrefLevel [Byte0]: 62
1133 12:12:11.047634 [Byte1]: 62
1134 12:12:11.051318
1135 12:12:11.051458 Set Vref, RX VrefLevel [Byte0]: 63
1136 12:12:11.054319 [Byte1]: 63
1137 12:12:11.059259
1138 12:12:11.059419 Set Vref, RX VrefLevel [Byte0]: 64
1139 12:12:11.062376 [Byte1]: 64
1140 12:12:11.066335
1141 12:12:11.066422 Set Vref, RX VrefLevel [Byte0]: 65
1142 12:12:11.069410 [Byte1]: 65
1143 12:12:11.074129
1144 12:12:11.074247 Set Vref, RX VrefLevel [Byte0]: 66
1145 12:12:11.076961 [Byte1]: 66
1146 12:12:11.081262
1147 12:12:11.081354 Set Vref, RX VrefLevel [Byte0]: 67
1148 12:12:11.084986 [Byte1]: 67
1149 12:12:11.089311
1150 12:12:11.089404 Set Vref, RX VrefLevel [Byte0]: 68
1151 12:12:11.092143 [Byte1]: 68
1152 12:12:11.096832
1153 12:12:11.096933 Set Vref, RX VrefLevel [Byte0]: 69
1154 12:12:11.100286 [Byte1]: 69
1155 12:12:11.104312
1156 12:12:11.104403 Set Vref, RX VrefLevel [Byte0]: 70
1157 12:12:11.107481 [Byte1]: 70
1158 12:12:11.111996
1159 12:12:11.112101 Set Vref, RX VrefLevel [Byte0]: 71
1160 12:12:11.115550 [Byte1]: 71
1161 12:12:11.119783
1162 12:12:11.119891 Set Vref, RX VrefLevel [Byte0]: 72
1163 12:12:11.122808 [Byte1]: 72
1164 12:12:11.127102
1165 12:12:11.127195 Final RX Vref Byte 0 = 56 to rank0
1166 12:12:11.130258 Final RX Vref Byte 1 = 60 to rank0
1167 12:12:11.133746 Final RX Vref Byte 0 = 56 to rank1
1168 12:12:11.136685 Final RX Vref Byte 1 = 60 to rank1==
1169 12:12:11.140415 Dram Type= 6, Freq= 0, CH_0, rank 0
1170 12:12:11.147026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1171 12:12:11.147140 ==
1172 12:12:11.147211 DQS Delay:
1173 12:12:11.150340 DQS0 = 0, DQS1 = 0
1174 12:12:11.150425 DQM Delay:
1175 12:12:11.150490 DQM0 = 88, DQM1 = 76
1176 12:12:11.153458 DQ Delay:
1177 12:12:11.156961 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1178 12:12:11.159806 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1179 12:12:11.163167 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1180 12:12:11.167007 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1181 12:12:11.167101
1182 12:12:11.167167
1183 12:12:11.173193 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d26, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
1184 12:12:11.176420 CH0 RK0: MR19=606, MR18=2D26
1185 12:12:11.183576 CH0_RK0: MR19=0x606, MR18=0x2D26, DQSOSC=398, MR23=63, INC=93, DEC=62
1186 12:12:11.183693
1187 12:12:11.186482 ----->DramcWriteLeveling(PI) begin...
1188 12:12:11.186568 ==
1189 12:12:11.190044 Dram Type= 6, Freq= 0, CH_0, rank 1
1190 12:12:11.193031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1191 12:12:11.193118 ==
1192 12:12:11.196821 Write leveling (Byte 0): 31 => 31
1193 12:12:11.199639 Write leveling (Byte 1): 25 => 25
1194 12:12:11.203092 DramcWriteLeveling(PI) end<-----
1195 12:12:11.203180
1196 12:12:11.203246 ==
1197 12:12:11.206402 Dram Type= 6, Freq= 0, CH_0, rank 1
1198 12:12:11.209749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1199 12:12:11.209842 ==
1200 12:12:11.213354 [Gating] SW mode calibration
1201 12:12:11.219595 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1202 12:12:11.226355 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1203 12:12:11.229803 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1204 12:12:11.236452 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1205 12:12:11.239946 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1206 12:12:11.243232 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 12:12:11.246371 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 12:12:11.293431 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 12:12:11.293634 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 12:12:11.293941 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 12:12:11.294405 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 12:12:11.295162 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 12:12:11.295534 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 12:12:11.295618 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 12:12:11.296365 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 12:12:11.296633 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 12:12:11.297159 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 12:12:11.319713 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 12:12:11.319906 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 12:12:11.320607 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1221 12:12:11.320895 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1222 12:12:11.321285 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 12:12:11.324421 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 12:12:11.324506 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 12:12:11.327140 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:12:11.330301 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:12:11.337058 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:12:11.340302 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:12:11.343674 0 9 8 | B1->B0 | 2323 3434 | 1 0 | (1 1) (0 0)
1230 12:12:11.350688 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1231 12:12:11.353595 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1232 12:12:11.356808 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1233 12:12:11.363891 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1234 12:12:11.366671 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1235 12:12:11.370851 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 12:12:11.376999 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
1237 12:12:11.380419 0 10 8 | B1->B0 | 3131 2525 | 0 0 | (0 0) (0 0)
1238 12:12:11.383608 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1239 12:12:11.387211 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 12:12:11.393697 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 12:12:11.397056 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 12:12:11.400303 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 12:12:11.406914 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 12:12:11.410136 0 11 4 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
1245 12:12:11.413486 0 11 8 | B1->B0 | 3433 4646 | 1 0 | (0 0) (0 0)
1246 12:12:11.420002 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1247 12:12:11.423729 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1248 12:12:11.426650 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1249 12:12:11.433659 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1250 12:12:11.437241 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1251 12:12:11.440916 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 12:12:11.444505 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1253 12:12:11.452173 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1254 12:12:11.454791 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 12:12:11.458419 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 12:12:11.465606 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 12:12:11.468863 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 12:12:11.472055 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 12:12:11.475342 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 12:12:11.481836 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 12:12:11.485144 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 12:12:11.488647 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 12:12:11.495717 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 12:12:11.498977 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 12:12:11.501951 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 12:12:11.508880 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 12:12:11.511756 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1268 12:12:11.515642 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1269 12:12:11.522122 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 12:12:11.522248 Total UI for P1: 0, mck2ui 16
1271 12:12:11.525209 best dqsien dly found for B0: ( 0, 14, 2)
1272 12:12:11.528799 Total UI for P1: 0, mck2ui 16
1273 12:12:11.532151 best dqsien dly found for B1: ( 0, 14, 4)
1274 12:12:11.535331 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1275 12:12:11.539076 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1276 12:12:11.542052
1277 12:12:11.545337 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1278 12:12:11.548609 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1279 12:12:11.551769 [Gating] SW calibration Done
1280 12:12:11.551853 ==
1281 12:12:11.555387 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 12:12:11.558577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 12:12:11.558681 ==
1284 12:12:11.558778 RX Vref Scan: 0
1285 12:12:11.558856
1286 12:12:11.562319 RX Vref 0 -> 0, step: 1
1287 12:12:11.562425
1288 12:12:11.565479 RX Delay -130 -> 252, step: 16
1289 12:12:11.568686 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1290 12:12:11.572323 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1291 12:12:11.578682 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1292 12:12:11.581702 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1293 12:12:11.584970 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1294 12:12:11.588331 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1295 12:12:11.591670 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1296 12:12:11.598201 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1297 12:12:11.601773 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1298 12:12:11.604834 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1299 12:12:11.607995 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1300 12:12:11.615194 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1301 12:12:11.618094 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1302 12:12:11.621168 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1303 12:12:11.624751 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1304 12:12:11.627870 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1305 12:12:11.631177 ==
1306 12:12:11.631269 Dram Type= 6, Freq= 0, CH_0, rank 1
1307 12:12:11.637789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1308 12:12:11.637889 ==
1309 12:12:11.637957 DQS Delay:
1310 12:12:11.641246 DQS0 = 0, DQS1 = 0
1311 12:12:11.641331 DQM Delay:
1312 12:12:11.644470 DQM0 = 86, DQM1 = 77
1313 12:12:11.644554 DQ Delay:
1314 12:12:11.648384 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1315 12:12:11.651203 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1316 12:12:11.654853 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1317 12:12:11.658206 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1318 12:12:11.658296
1319 12:12:11.658363
1320 12:12:11.658424 ==
1321 12:12:11.661221 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 12:12:11.664164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 12:12:11.664250 ==
1324 12:12:11.664316
1325 12:12:11.664377
1326 12:12:11.667900 TX Vref Scan disable
1327 12:12:11.671339 == TX Byte 0 ==
1328 12:12:11.674278 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1329 12:12:11.678102 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1330 12:12:11.681039 == TX Byte 1 ==
1331 12:12:11.684259 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1332 12:12:11.687413 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1333 12:12:11.687503 ==
1334 12:12:11.690693 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 12:12:11.697191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 12:12:11.697291 ==
1337 12:12:11.709242 TX Vref=22, minBit 2, minWin=27, winSum=440
1338 12:12:11.712870 TX Vref=24, minBit 1, minWin=27, winSum=445
1339 12:12:11.715851 TX Vref=26, minBit 2, minWin=27, winSum=449
1340 12:12:11.719360 TX Vref=28, minBit 1, minWin=27, winSum=451
1341 12:12:11.722419 TX Vref=30, minBit 0, minWin=28, winSum=452
1342 12:12:11.729178 TX Vref=32, minBit 0, minWin=28, winSum=454
1343 12:12:11.732756 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 32
1344 12:12:11.732852
1345 12:12:11.735999 Final TX Range 1 Vref 32
1346 12:12:11.736086
1347 12:12:11.736152 ==
1348 12:12:11.739572 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 12:12:11.742651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 12:12:11.745973 ==
1351 12:12:11.746061
1352 12:12:11.746127
1353 12:12:11.746188 TX Vref Scan disable
1354 12:12:11.749463 == TX Byte 0 ==
1355 12:12:11.752731 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1356 12:12:11.759468 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1357 12:12:11.759577 == TX Byte 1 ==
1358 12:12:11.762696 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1359 12:12:11.769581 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1360 12:12:11.769739
1361 12:12:11.769806 [DATLAT]
1362 12:12:11.769867 Freq=800, CH0 RK1
1363 12:12:11.769925
1364 12:12:11.772664 DATLAT Default: 0xa
1365 12:12:11.772777 0, 0xFFFF, sum = 0
1366 12:12:11.776004 1, 0xFFFF, sum = 0
1367 12:12:11.779534 2, 0xFFFF, sum = 0
1368 12:12:11.779623 3, 0xFFFF, sum = 0
1369 12:12:11.782671 4, 0xFFFF, sum = 0
1370 12:12:11.782778 5, 0xFFFF, sum = 0
1371 12:12:11.786138 6, 0xFFFF, sum = 0
1372 12:12:11.786246 7, 0xFFFF, sum = 0
1373 12:12:11.789126 8, 0xFFFF, sum = 0
1374 12:12:11.789232 9, 0x0, sum = 1
1375 12:12:11.793151 10, 0x0, sum = 2
1376 12:12:11.793265 11, 0x0, sum = 3
1377 12:12:11.793359 12, 0x0, sum = 4
1378 12:12:11.795967 best_step = 10
1379 12:12:11.796068
1380 12:12:11.796159 ==
1381 12:12:11.799489 Dram Type= 6, Freq= 0, CH_0, rank 1
1382 12:12:11.802393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 12:12:11.802529 ==
1384 12:12:11.805772 RX Vref Scan: 0
1385 12:12:11.805876
1386 12:12:11.808871 RX Vref 0 -> 0, step: 1
1387 12:12:11.808975
1388 12:12:11.809066 RX Delay -95 -> 252, step: 8
1389 12:12:11.816488 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1390 12:12:11.819567 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1391 12:12:11.823089 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1392 12:12:11.825896 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1393 12:12:11.829234 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1394 12:12:11.835773 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1395 12:12:11.839534 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1396 12:12:11.842418 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1397 12:12:11.846383 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1398 12:12:11.849837 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1399 12:12:11.855800 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1400 12:12:11.858882 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1401 12:12:11.862709 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1402 12:12:11.865632 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1403 12:12:11.872160 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1404 12:12:11.875966 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1405 12:12:11.876092 ==
1406 12:12:11.879080 Dram Type= 6, Freq= 0, CH_0, rank 1
1407 12:12:11.882529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 12:12:11.882623 ==
1409 12:12:11.885842 DQS Delay:
1410 12:12:11.885929 DQS0 = 0, DQS1 = 0
1411 12:12:11.885995 DQM Delay:
1412 12:12:11.889016 DQM0 = 86, DQM1 = 77
1413 12:12:11.889101 DQ Delay:
1414 12:12:11.892614 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1415 12:12:11.895286 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1416 12:12:11.899044 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1417 12:12:11.903022 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1418 12:12:11.903119
1419 12:12:11.903185
1420 12:12:11.912129 [DQSOSCAuto] RK1, (LSB)MR18= 0x2824, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1421 12:12:11.912261 CH0 RK1: MR19=606, MR18=2824
1422 12:12:11.918603 CH0_RK1: MR19=0x606, MR18=0x2824, DQSOSC=399, MR23=63, INC=92, DEC=61
1423 12:12:11.921868 [RxdqsGatingPostProcess] freq 800
1424 12:12:11.928740 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1425 12:12:11.931841 Pre-setting of DQS Precalculation
1426 12:12:11.935043 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1427 12:12:11.935150 ==
1428 12:12:11.938313 Dram Type= 6, Freq= 0, CH_1, rank 0
1429 12:12:11.945233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1430 12:12:11.945351 ==
1431 12:12:11.948772 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1432 12:12:11.954844 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1433 12:12:11.965358 [CA 0] Center 37 (6~68) winsize 63
1434 12:12:11.968396 [CA 1] Center 37 (6~68) winsize 63
1435 12:12:11.971268 [CA 2] Center 35 (5~65) winsize 61
1436 12:12:11.974403 [CA 3] Center 34 (4~65) winsize 62
1437 12:12:11.977651 [CA 4] Center 34 (4~65) winsize 62
1438 12:12:11.981488 [CA 5] Center 34 (3~65) winsize 63
1439 12:12:11.981586
1440 12:12:11.984801 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1441 12:12:11.984891
1442 12:12:11.987485 [CATrainingPosCal] consider 1 rank data
1443 12:12:11.990837 u2DelayCellTimex100 = 270/100 ps
1444 12:12:11.994136 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1445 12:12:12.000976 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1446 12:12:12.004294 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1447 12:12:12.007509 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1448 12:12:12.011089 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1449 12:12:12.014222 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1450 12:12:12.014323
1451 12:12:12.017414 CA PerBit enable=1, Macro0, CA PI delay=34
1452 12:12:12.017502
1453 12:12:12.021247 [CBTSetCACLKResult] CA Dly = 34
1454 12:12:12.023913 CS Dly: 4 (0~35)
1455 12:12:12.024001 ==
1456 12:12:12.027528 Dram Type= 6, Freq= 0, CH_1, rank 1
1457 12:12:12.030730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1458 12:12:12.030819 ==
1459 12:12:12.033930 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1460 12:12:12.040514 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1461 12:12:12.050807 [CA 0] Center 36 (6~67) winsize 62
1462 12:12:12.053782 [CA 1] Center 36 (6~67) winsize 62
1463 12:12:12.057554 [CA 2] Center 34 (4~65) winsize 62
1464 12:12:12.060493 [CA 3] Center 34 (3~65) winsize 63
1465 12:12:12.064298 [CA 4] Center 34 (3~65) winsize 63
1466 12:12:12.067531 [CA 5] Center 34 (3~65) winsize 63
1467 12:12:12.067620
1468 12:12:12.070447 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1469 12:12:12.070533
1470 12:12:12.073572 [CATrainingPosCal] consider 2 rank data
1471 12:12:12.077031 u2DelayCellTimex100 = 270/100 ps
1472 12:12:12.080185 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1473 12:12:12.086749 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1474 12:12:12.090611 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1475 12:12:12.093633 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1476 12:12:12.097152 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1477 12:12:12.100597 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1478 12:12:12.100692
1479 12:12:12.104299 CA PerBit enable=1, Macro0, CA PI delay=34
1480 12:12:12.104390
1481 12:12:12.107966 [CBTSetCACLKResult] CA Dly = 34
1482 12:12:12.108056 CS Dly: 5 (0~37)
1483 12:12:12.108124
1484 12:12:12.111685 ----->DramcWriteLeveling(PI) begin...
1485 12:12:12.111841 ==
1486 12:12:12.115507 Dram Type= 6, Freq= 0, CH_1, rank 0
1487 12:12:12.119691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1488 12:12:12.119790 ==
1489 12:12:12.123130 Write leveling (Byte 0): 26 => 26
1490 12:12:12.126787 Write leveling (Byte 1): 25 => 25
1491 12:12:12.130038 DramcWriteLeveling(PI) end<-----
1492 12:12:12.130139
1493 12:12:12.130207 ==
1494 12:12:12.133763 Dram Type= 6, Freq= 0, CH_1, rank 0
1495 12:12:12.137362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1496 12:12:12.137456 ==
1497 12:12:12.140779 [Gating] SW mode calibration
1498 12:12:12.147252 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1499 12:12:12.150553 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1500 12:12:12.157298 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1501 12:12:12.160230 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1502 12:12:12.163820 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1503 12:12:12.170091 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 12:12:12.173481 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 12:12:12.176902 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 12:12:12.183285 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 12:12:12.186804 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 12:12:12.189857 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 12:12:12.196824 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 12:12:12.200168 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 12:12:12.203581 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 12:12:12.210052 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 12:12:12.213098 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 12:12:12.216683 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 12:12:12.223388 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 12:12:12.226509 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1517 12:12:12.229590 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1518 12:12:12.236534 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1519 12:12:12.239833 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 12:12:12.242728 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 12:12:12.249241 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 12:12:12.252616 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 12:12:12.256312 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 12:12:12.262832 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 12:12:12.266054 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1526 12:12:12.269638 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
1527 12:12:12.276022 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1528 12:12:12.279192 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1529 12:12:12.282477 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1530 12:12:12.289232 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1531 12:12:12.292285 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1532 12:12:12.295756 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1533 12:12:12.302238 0 10 4 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
1534 12:12:12.305856 0 10 8 | B1->B0 | 2626 2424 | 0 0 | (1 0) (0 0)
1535 12:12:12.308754 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 12:12:12.315539 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 12:12:12.319355 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 12:12:12.322050 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 12:12:12.328624 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 12:12:12.332003 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 12:12:12.335576 0 11 4 | B1->B0 | 2626 2e2e | 0 0 | (0 0) (0 0)
1542 12:12:12.342403 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1543 12:12:12.345716 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1544 12:12:12.349080 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1545 12:12:12.355301 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1546 12:12:12.359302 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 12:12:12.361980 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1548 12:12:12.369167 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1549 12:12:12.372065 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1550 12:12:12.375343 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1551 12:12:12.382257 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 12:12:12.385519 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 12:12:12.389028 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 12:12:12.395236 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 12:12:12.398333 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 12:12:12.401557 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 12:12:12.408652 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 12:12:12.411645 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 12:12:12.414978 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 12:12:12.421711 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 12:12:12.424973 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 12:12:12.428655 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 12:12:12.432077 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 12:12:12.438216 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1565 12:12:12.442238 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1566 12:12:12.444657 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1567 12:12:12.448177 Total UI for P1: 0, mck2ui 16
1568 12:12:12.451303 best dqsien dly found for B0: ( 0, 14, 2)
1569 12:12:12.458876 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 12:12:12.461464 Total UI for P1: 0, mck2ui 16
1571 12:12:12.464594 best dqsien dly found for B1: ( 0, 14, 6)
1572 12:12:12.468317 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1573 12:12:12.471641 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1574 12:12:12.471731
1575 12:12:12.474441 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1576 12:12:12.478118 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1577 12:12:12.481772 [Gating] SW calibration Done
1578 12:12:12.481861 ==
1579 12:12:12.484806 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 12:12:12.487834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 12:12:12.487921 ==
1582 12:12:12.491323 RX Vref Scan: 0
1583 12:12:12.491455
1584 12:12:12.491521 RX Vref 0 -> 0, step: 1
1585 12:12:12.494656
1586 12:12:12.494738 RX Delay -130 -> 252, step: 16
1587 12:12:12.501038 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1588 12:12:12.504264 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1589 12:12:12.508244 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1590 12:12:12.510808 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1591 12:12:12.514259 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1592 12:12:12.520767 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1593 12:12:12.524256 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1594 12:12:12.527815 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1595 12:12:12.530920 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1596 12:12:12.534001 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1597 12:12:12.541735 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1598 12:12:12.544147 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1599 12:12:12.547135 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1600 12:12:12.550892 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1601 12:12:12.557316 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1602 12:12:12.560860 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1603 12:12:12.560954 ==
1604 12:12:12.563850 Dram Type= 6, Freq= 0, CH_1, rank 0
1605 12:12:12.567658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1606 12:12:12.567748 ==
1607 12:12:12.567815 DQS Delay:
1608 12:12:12.570435 DQS0 = 0, DQS1 = 0
1609 12:12:12.570519 DQM Delay:
1610 12:12:12.573875 DQM0 = 88, DQM1 = 83
1611 12:12:12.573960 DQ Delay:
1612 12:12:12.577195 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1613 12:12:12.580504 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1614 12:12:12.583810 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1615 12:12:12.587573 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1616 12:12:12.587662
1617 12:12:12.587728
1618 12:12:12.587788 ==
1619 12:12:12.590847 Dram Type= 6, Freq= 0, CH_1, rank 0
1620 12:12:12.597134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1621 12:12:12.597229 ==
1622 12:12:12.597295
1623 12:12:12.597356
1624 12:12:12.597415 TX Vref Scan disable
1625 12:12:12.601195 == TX Byte 0 ==
1626 12:12:12.603950 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1627 12:12:12.607038 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1628 12:12:12.610728 == TX Byte 1 ==
1629 12:12:12.614304 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1630 12:12:12.620462 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1631 12:12:12.620569 ==
1632 12:12:12.623755 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 12:12:12.627314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 12:12:12.627455 ==
1635 12:12:12.639799 TX Vref=22, minBit 0, minWin=27, winSum=440
1636 12:12:12.643117 TX Vref=24, minBit 1, minWin=27, winSum=444
1637 12:12:12.646353 TX Vref=26, minBit 4, minWin=27, winSum=449
1638 12:12:12.649937 TX Vref=28, minBit 5, minWin=27, winSum=455
1639 12:12:12.653115 TX Vref=30, minBit 0, minWin=28, winSum=455
1640 12:12:12.656626 TX Vref=32, minBit 0, minWin=27, winSum=451
1641 12:12:12.662654 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
1642 12:12:12.662760
1643 12:12:12.666133 Final TX Range 1 Vref 30
1644 12:12:12.666220
1645 12:12:12.666285 ==
1646 12:12:12.669760 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 12:12:12.672884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 12:12:12.672971 ==
1649 12:12:12.676127
1650 12:12:12.676211
1651 12:12:12.676276 TX Vref Scan disable
1652 12:12:12.679620 == TX Byte 0 ==
1653 12:12:12.683936 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1654 12:12:12.687384 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1655 12:12:12.690244 == TX Byte 1 ==
1656 12:12:12.694170 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1657 12:12:12.697316 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1658 12:12:12.697406
1659 12:12:12.700094 [DATLAT]
1660 12:12:12.700177 Freq=800, CH1 RK0
1661 12:12:12.700243
1662 12:12:12.703339 DATLAT Default: 0xa
1663 12:12:12.703465 0, 0xFFFF, sum = 0
1664 12:12:12.706752 1, 0xFFFF, sum = 0
1665 12:12:12.706836 2, 0xFFFF, sum = 0
1666 12:12:12.710146 3, 0xFFFF, sum = 0
1667 12:12:12.710231 4, 0xFFFF, sum = 0
1668 12:12:12.713670 5, 0xFFFF, sum = 0
1669 12:12:12.713764 6, 0xFFFF, sum = 0
1670 12:12:12.717063 7, 0xFFFF, sum = 0
1671 12:12:12.717149 8, 0xFFFF, sum = 0
1672 12:12:12.720261 9, 0x0, sum = 1
1673 12:12:12.720347 10, 0x0, sum = 2
1674 12:12:12.723581 11, 0x0, sum = 3
1675 12:12:12.723667 12, 0x0, sum = 4
1676 12:12:12.726607 best_step = 10
1677 12:12:12.726692
1678 12:12:12.726757 ==
1679 12:12:12.729879 Dram Type= 6, Freq= 0, CH_1, rank 0
1680 12:12:12.733142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1681 12:12:12.733230 ==
1682 12:12:12.736720 RX Vref Scan: 1
1683 12:12:12.736804
1684 12:12:12.736870 Set Vref Range= 32 -> 127
1685 12:12:12.736931
1686 12:12:12.740155 RX Vref 32 -> 127, step: 1
1687 12:12:12.740240
1688 12:12:12.743232 RX Delay -95 -> 252, step: 8
1689 12:12:12.743317
1690 12:12:12.746830 Set Vref, RX VrefLevel [Byte0]: 32
1691 12:12:12.749953 [Byte1]: 32
1692 12:12:12.750039
1693 12:12:12.753548 Set Vref, RX VrefLevel [Byte0]: 33
1694 12:12:12.756343 [Byte1]: 33
1695 12:12:12.759867
1696 12:12:12.759955 Set Vref, RX VrefLevel [Byte0]: 34
1697 12:12:12.762948 [Byte1]: 34
1698 12:12:12.767815
1699 12:12:12.767907 Set Vref, RX VrefLevel [Byte0]: 35
1700 12:12:12.770872 [Byte1]: 35
1701 12:12:12.775090
1702 12:12:12.775179 Set Vref, RX VrefLevel [Byte0]: 36
1703 12:12:12.778676 [Byte1]: 36
1704 12:12:12.782661
1705 12:12:12.782750 Set Vref, RX VrefLevel [Byte0]: 37
1706 12:12:12.786000 [Byte1]: 37
1707 12:12:12.790577
1708 12:12:12.790670 Set Vref, RX VrefLevel [Byte0]: 38
1709 12:12:12.793609 [Byte1]: 38
1710 12:12:12.797769
1711 12:12:12.797857 Set Vref, RX VrefLevel [Byte0]: 39
1712 12:12:12.801530 [Byte1]: 39
1713 12:12:12.805592
1714 12:12:12.805682 Set Vref, RX VrefLevel [Byte0]: 40
1715 12:12:12.809223 [Byte1]: 40
1716 12:12:12.813735
1717 12:12:12.813831 Set Vref, RX VrefLevel [Byte0]: 41
1718 12:12:12.816376 [Byte1]: 41
1719 12:12:12.820453
1720 12:12:12.820541 Set Vref, RX VrefLevel [Byte0]: 42
1721 12:12:12.824002 [Byte1]: 42
1722 12:12:12.828447
1723 12:12:12.828536 Set Vref, RX VrefLevel [Byte0]: 43
1724 12:12:12.834603 [Byte1]: 43
1725 12:12:12.834695
1726 12:12:12.838393 Set Vref, RX VrefLevel [Byte0]: 44
1727 12:12:12.841053 [Byte1]: 44
1728 12:12:12.841139
1729 12:12:12.844340 Set Vref, RX VrefLevel [Byte0]: 45
1730 12:12:12.848010 [Byte1]: 45
1731 12:12:12.851006
1732 12:12:12.851093 Set Vref, RX VrefLevel [Byte0]: 46
1733 12:12:12.855169 [Byte1]: 46
1734 12:12:12.858616
1735 12:12:12.858703 Set Vref, RX VrefLevel [Byte0]: 47
1736 12:12:12.861917 [Byte1]: 47
1737 12:12:12.866087
1738 12:12:12.866176 Set Vref, RX VrefLevel [Byte0]: 48
1739 12:12:12.869635 [Byte1]: 48
1740 12:12:12.874059
1741 12:12:12.874149 Set Vref, RX VrefLevel [Byte0]: 49
1742 12:12:12.877038 [Byte1]: 49
1743 12:12:12.881202
1744 12:12:12.881292 Set Vref, RX VrefLevel [Byte0]: 50
1745 12:12:12.884775 [Byte1]: 50
1746 12:12:12.888853
1747 12:12:12.888942 Set Vref, RX VrefLevel [Byte0]: 51
1748 12:12:12.892598 [Byte1]: 51
1749 12:12:12.897048
1750 12:12:12.897138 Set Vref, RX VrefLevel [Byte0]: 52
1751 12:12:12.899772 [Byte1]: 52
1752 12:12:12.904247
1753 12:12:12.904335 Set Vref, RX VrefLevel [Byte0]: 53
1754 12:12:12.907234 [Byte1]: 53
1755 12:12:12.911916
1756 12:12:12.912006 Set Vref, RX VrefLevel [Byte0]: 54
1757 12:12:12.915041 [Byte1]: 54
1758 12:12:12.919251
1759 12:12:12.919374 Set Vref, RX VrefLevel [Byte0]: 55
1760 12:12:12.922731 [Byte1]: 55
1761 12:12:12.926897
1762 12:12:12.926996 Set Vref, RX VrefLevel [Byte0]: 56
1763 12:12:12.930150 [Byte1]: 56
1764 12:12:12.934553
1765 12:12:12.934643 Set Vref, RX VrefLevel [Byte0]: 57
1766 12:12:12.937883 [Byte1]: 57
1767 12:12:12.942161
1768 12:12:12.942268 Set Vref, RX VrefLevel [Byte0]: 58
1769 12:12:12.945964 [Byte1]: 58
1770 12:12:12.949880
1771 12:12:12.949972 Set Vref, RX VrefLevel [Byte0]: 59
1772 12:12:12.953169 [Byte1]: 59
1773 12:12:12.957100
1774 12:12:12.957191 Set Vref, RX VrefLevel [Byte0]: 60
1775 12:12:12.960738 [Byte1]: 60
1776 12:12:12.964861
1777 12:12:12.964956 Set Vref, RX VrefLevel [Byte0]: 61
1778 12:12:12.968037 [Byte1]: 61
1779 12:12:12.972439
1780 12:12:12.972534 Set Vref, RX VrefLevel [Byte0]: 62
1781 12:12:12.975654 [Byte1]: 62
1782 12:12:12.980391
1783 12:12:12.980486 Set Vref, RX VrefLevel [Byte0]: 63
1784 12:12:12.983309 [Byte1]: 63
1785 12:12:12.987384
1786 12:12:12.987492 Set Vref, RX VrefLevel [Byte0]: 64
1787 12:12:12.991431 [Byte1]: 64
1788 12:12:12.995640
1789 12:12:12.995737 Set Vref, RX VrefLevel [Byte0]: 65
1790 12:12:12.998473 [Byte1]: 65
1791 12:12:13.003136
1792 12:12:13.003226 Set Vref, RX VrefLevel [Byte0]: 66
1793 12:12:13.006584 [Byte1]: 66
1794 12:12:13.010749
1795 12:12:13.010836 Set Vref, RX VrefLevel [Byte0]: 67
1796 12:12:13.013775 [Byte1]: 67
1797 12:12:13.018235
1798 12:12:13.018331 Set Vref, RX VrefLevel [Byte0]: 68
1799 12:12:13.021303 [Byte1]: 68
1800 12:12:13.025741
1801 12:12:13.025830 Set Vref, RX VrefLevel [Byte0]: 69
1802 12:12:13.028868 [Byte1]: 69
1803 12:12:13.033424
1804 12:12:13.033511 Set Vref, RX VrefLevel [Byte0]: 70
1805 12:12:13.036606 [Byte1]: 70
1806 12:12:13.040925
1807 12:12:13.041014 Set Vref, RX VrefLevel [Byte0]: 71
1808 12:12:13.044438 [Byte1]: 71
1809 12:12:13.048972
1810 12:12:13.049064 Set Vref, RX VrefLevel [Byte0]: 72
1811 12:12:13.051794 [Byte1]: 72
1812 12:12:13.055876
1813 12:12:13.055966 Set Vref, RX VrefLevel [Byte0]: 73
1814 12:12:13.059333 [Byte1]: 73
1815 12:12:13.063565
1816 12:12:13.063655 Set Vref, RX VrefLevel [Byte0]: 74
1817 12:12:13.066787 [Byte1]: 74
1818 12:12:13.071574
1819 12:12:13.071668 Set Vref, RX VrefLevel [Byte0]: 75
1820 12:12:13.074296 [Byte1]: 75
1821 12:12:13.078918
1822 12:12:13.079010 Set Vref, RX VrefLevel [Byte0]: 76
1823 12:12:13.082219 [Byte1]: 76
1824 12:12:13.086758
1825 12:12:13.086856 Final RX Vref Byte 0 = 60 to rank0
1826 12:12:13.089782 Final RX Vref Byte 1 = 59 to rank0
1827 12:12:13.092898 Final RX Vref Byte 0 = 60 to rank1
1828 12:12:13.096446 Final RX Vref Byte 1 = 59 to rank1==
1829 12:12:13.099837 Dram Type= 6, Freq= 0, CH_1, rank 0
1830 12:12:13.106651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1831 12:12:13.106764 ==
1832 12:12:13.106832 DQS Delay:
1833 12:12:13.106893 DQS0 = 0, DQS1 = 0
1834 12:12:13.110248 DQM Delay:
1835 12:12:13.110335 DQM0 = 86, DQM1 = 81
1836 12:12:13.112819 DQ Delay:
1837 12:12:13.116502 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1838 12:12:13.119564 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1839 12:12:13.123059 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1840 12:12:13.126747 DQ12 =88, DQ13 =92, DQ14 =88, DQ15 =88
1841 12:12:13.126841
1842 12:12:13.126908
1843 12:12:13.132629 [DQSOSCAuto] RK0, (LSB)MR18= 0x1529, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
1844 12:12:13.136359 CH1 RK0: MR19=606, MR18=1529
1845 12:12:13.142917 CH1_RK0: MR19=0x606, MR18=0x1529, DQSOSC=399, MR23=63, INC=92, DEC=61
1846 12:12:13.143025
1847 12:12:13.146207 ----->DramcWriteLeveling(PI) begin...
1848 12:12:13.146295 ==
1849 12:12:13.149132 Dram Type= 6, Freq= 0, CH_1, rank 1
1850 12:12:13.152476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1851 12:12:13.152568 ==
1852 12:12:13.155680 Write leveling (Byte 0): 26 => 26
1853 12:12:13.159150 Write leveling (Byte 1): 28 => 28
1854 12:12:13.162297 DramcWriteLeveling(PI) end<-----
1855 12:12:13.162386
1856 12:12:13.162452 ==
1857 12:12:13.166366 Dram Type= 6, Freq= 0, CH_1, rank 1
1858 12:12:13.169023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1859 12:12:13.169110 ==
1860 12:12:13.172338 [Gating] SW mode calibration
1861 12:12:13.178976 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1862 12:12:13.185621 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1863 12:12:13.189222 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1864 12:12:13.195488 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1865 12:12:13.198987 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 12:12:13.201973 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 12:12:13.208779 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 12:12:13.212144 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 12:12:13.215675 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 12:12:13.222691 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 12:12:13.225477 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 12:12:13.228881 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 12:12:13.235541 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 12:12:13.238600 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 12:12:13.242254 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 12:12:13.245394 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 12:12:13.251926 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 12:12:13.255148 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 12:12:13.258679 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1880 12:12:13.265235 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1881 12:12:13.269015 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 12:12:13.272036 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 12:12:13.278493 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 12:12:13.282217 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 12:12:13.285471 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 12:12:13.291406 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 12:12:13.294859 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 12:12:13.298133 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
1889 12:12:13.305449 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1890 12:12:13.308466 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 12:12:13.311338 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 12:12:13.317934 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 12:12:13.322243 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 12:12:13.324831 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 12:12:13.331343 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1896 12:12:13.334565 0 10 4 | B1->B0 | 3232 2a2a | 0 1 | (0 0) (1 0)
1897 12:12:13.337851 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 12:12:13.344753 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 12:12:13.348020 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 12:12:13.351254 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 12:12:13.357635 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 12:12:13.360908 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 12:12:13.364966 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 12:12:13.371450 0 11 4 | B1->B0 | 2828 3c3c | 0 0 | (0 0) (0 0)
1905 12:12:13.374780 0 11 8 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
1906 12:12:13.377751 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 12:12:13.384400 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 12:12:13.387566 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 12:12:13.391063 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 12:12:13.397617 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 12:12:13.401006 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1912 12:12:13.404284 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1913 12:12:13.410842 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 12:12:13.414059 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 12:12:13.417476 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 12:12:13.424171 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 12:12:13.427527 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 12:12:13.430671 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 12:12:13.436954 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 12:12:13.440456 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 12:12:13.443608 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 12:12:13.450361 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 12:12:13.453861 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 12:12:13.456862 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 12:12:13.463850 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 12:12:13.467096 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 12:12:13.470789 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1928 12:12:13.477308 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1929 12:12:13.480412 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 12:12:13.483346 Total UI for P1: 0, mck2ui 16
1931 12:12:13.487215 best dqsien dly found for B0: ( 0, 14, 2)
1932 12:12:13.490118 Total UI for P1: 0, mck2ui 16
1933 12:12:13.493396 best dqsien dly found for B1: ( 0, 14, 6)
1934 12:12:13.497104 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1935 12:12:13.500030 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1936 12:12:13.500119
1937 12:12:13.503441 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1938 12:12:13.507173 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1939 12:12:13.509846 [Gating] SW calibration Done
1940 12:12:13.509934 ==
1941 12:12:13.513535 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 12:12:13.516638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 12:12:13.516730 ==
1944 12:12:13.520197 RX Vref Scan: 0
1945 12:12:13.520282
1946 12:12:13.523403 RX Vref 0 -> 0, step: 1
1947 12:12:13.523526
1948 12:12:13.523621 RX Delay -130 -> 252, step: 16
1949 12:12:13.530128 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1950 12:12:13.533173 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1951 12:12:13.536422 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1952 12:12:13.540242 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1953 12:12:13.543207 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1954 12:12:13.549901 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1955 12:12:13.553073 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1956 12:12:13.556342 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1957 12:12:13.559666 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1958 12:12:13.562844 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1959 12:12:13.569923 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1960 12:12:13.573100 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1961 12:12:13.576528 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1962 12:12:13.579933 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1963 12:12:13.586035 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1964 12:12:13.589302 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1965 12:12:13.589395 ==
1966 12:12:13.592679 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 12:12:13.595943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 12:12:13.596060 ==
1969 12:12:13.599184 DQS Delay:
1970 12:12:13.599268 DQS0 = 0, DQS1 = 0
1971 12:12:13.599333 DQM Delay:
1972 12:12:13.602730 DQM0 = 83, DQM1 = 80
1973 12:12:13.602817 DQ Delay:
1974 12:12:13.605978 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1975 12:12:13.609329 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1976 12:12:13.612674 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1977 12:12:13.615851 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1978 12:12:13.615946
1979 12:12:13.616011
1980 12:12:13.616070 ==
1981 12:12:13.619178 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 12:12:13.625951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 12:12:13.626053 ==
1984 12:12:13.626120
1985 12:12:13.626179
1986 12:12:13.626236 TX Vref Scan disable
1987 12:12:13.629118 == TX Byte 0 ==
1988 12:12:13.632787 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1989 12:12:13.639303 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1990 12:12:13.639448 == TX Byte 1 ==
1991 12:12:13.642440 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1992 12:12:13.649247 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1993 12:12:13.649348 ==
1994 12:12:13.652567 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 12:12:13.655337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 12:12:13.655433 ==
1997 12:12:13.668327 TX Vref=22, minBit 0, minWin=27, winSum=446
1998 12:12:13.671585 TX Vref=24, minBit 2, minWin=27, winSum=446
1999 12:12:13.675369 TX Vref=26, minBit 5, minWin=27, winSum=453
2000 12:12:13.678183 TX Vref=28, minBit 0, minWin=27, winSum=452
2001 12:12:13.681584 TX Vref=30, minBit 0, minWin=28, winSum=458
2002 12:12:13.685601 TX Vref=32, minBit 0, minWin=27, winSum=453
2003 12:12:13.691569 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 30
2004 12:12:13.691676
2005 12:12:13.695061 Final TX Range 1 Vref 30
2006 12:12:13.695148
2007 12:12:13.695213 ==
2008 12:12:13.698220 Dram Type= 6, Freq= 0, CH_1, rank 1
2009 12:12:13.701566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2010 12:12:13.701655 ==
2011 12:12:13.704592
2012 12:12:13.704676
2013 12:12:13.704741 TX Vref Scan disable
2014 12:12:13.708169 == TX Byte 0 ==
2015 12:12:13.711583 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2016 12:12:13.718654 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2017 12:12:13.718771 == TX Byte 1 ==
2018 12:12:13.721377 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2019 12:12:13.728133 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2020 12:12:13.728236
2021 12:12:13.728301 [DATLAT]
2022 12:12:13.728360 Freq=800, CH1 RK1
2023 12:12:13.728420
2024 12:12:13.731230 DATLAT Default: 0xa
2025 12:12:13.731339 0, 0xFFFF, sum = 0
2026 12:12:13.734802 1, 0xFFFF, sum = 0
2027 12:12:13.734888 2, 0xFFFF, sum = 0
2028 12:12:13.738445 3, 0xFFFF, sum = 0
2029 12:12:13.741395 4, 0xFFFF, sum = 0
2030 12:12:13.741481 5, 0xFFFF, sum = 0
2031 12:12:13.744625 6, 0xFFFF, sum = 0
2032 12:12:13.744709 7, 0xFFFF, sum = 0
2033 12:12:13.747737 8, 0xFFFF, sum = 0
2034 12:12:13.747821 9, 0x0, sum = 1
2035 12:12:13.751358 10, 0x0, sum = 2
2036 12:12:13.751482 11, 0x0, sum = 3
2037 12:12:13.751549 12, 0x0, sum = 4
2038 12:12:13.754824 best_step = 10
2039 12:12:13.754907
2040 12:12:13.754971 ==
2041 12:12:13.757972 Dram Type= 6, Freq= 0, CH_1, rank 1
2042 12:12:13.761244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2043 12:12:13.761329 ==
2044 12:12:13.764673 RX Vref Scan: 0
2045 12:12:13.764756
2046 12:12:13.764821 RX Vref 0 -> 0, step: 1
2047 12:12:13.767815
2048 12:12:13.767898 RX Delay -95 -> 252, step: 8
2049 12:12:13.775280 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2050 12:12:13.778112 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2051 12:12:13.781444 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2052 12:12:13.784668 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2053 12:12:13.787948 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2054 12:12:13.794933 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2055 12:12:13.798560 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2056 12:12:13.801966 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2057 12:12:13.804541 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2058 12:12:13.808177 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2059 12:12:13.814637 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2060 12:12:13.818503 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2061 12:12:13.821023 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2062 12:12:13.824573 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2063 12:12:13.831734 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2064 12:12:13.835223 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2065 12:12:13.835381 ==
2066 12:12:13.837928 Dram Type= 6, Freq= 0, CH_1, rank 1
2067 12:12:13.841497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2068 12:12:13.841584 ==
2069 12:12:13.845197 DQS Delay:
2070 12:12:13.845282 DQS0 = 0, DQS1 = 0
2071 12:12:13.845357 DQM Delay:
2072 12:12:13.847582 DQM0 = 86, DQM1 = 82
2073 12:12:13.847663 DQ Delay:
2074 12:12:13.851393 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2075 12:12:13.854267 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2076 12:12:13.857609 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
2077 12:12:13.861196 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2078 12:12:13.861283
2079 12:12:13.861348
2080 12:12:13.871171 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2081 12:12:13.871280 CH1 RK1: MR19=606, MR18=1E3A
2082 12:12:13.877837 CH1_RK1: MR19=0x606, MR18=0x1E3A, DQSOSC=395, MR23=63, INC=94, DEC=63
2083 12:12:13.880872 [RxdqsGatingPostProcess] freq 800
2084 12:12:13.887722 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2085 12:12:13.891091 Pre-setting of DQS Precalculation
2086 12:12:13.894928 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2087 12:12:13.901377 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2088 12:12:13.910730 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2089 12:12:13.910846
2090 12:12:13.910913
2091 12:12:13.914357 [Calibration Summary] 1600 Mbps
2092 12:12:13.914442 CH 0, Rank 0
2093 12:12:13.917552 SW Impedance : PASS
2094 12:12:13.917644 DUTY Scan : NO K
2095 12:12:13.920789 ZQ Calibration : PASS
2096 12:12:13.924325 Jitter Meter : NO K
2097 12:12:13.924415 CBT Training : PASS
2098 12:12:13.927723 Write leveling : PASS
2099 12:12:13.927807 RX DQS gating : PASS
2100 12:12:13.930844 RX DQ/DQS(RDDQC) : PASS
2101 12:12:13.934503 TX DQ/DQS : PASS
2102 12:12:13.934592 RX DATLAT : PASS
2103 12:12:13.937935 RX DQ/DQS(Engine): PASS
2104 12:12:13.941000 TX OE : NO K
2105 12:12:13.941088 All Pass.
2106 12:12:13.941164
2107 12:12:13.941256 CH 0, Rank 1
2108 12:12:13.944309 SW Impedance : PASS
2109 12:12:13.947612 DUTY Scan : NO K
2110 12:12:13.947698 ZQ Calibration : PASS
2111 12:12:13.950469 Jitter Meter : NO K
2112 12:12:13.953993 CBT Training : PASS
2113 12:12:13.954083 Write leveling : PASS
2114 12:12:13.957034 RX DQS gating : PASS
2115 12:12:13.960656 RX DQ/DQS(RDDQC) : PASS
2116 12:12:13.960748 TX DQ/DQS : PASS
2117 12:12:13.963968 RX DATLAT : PASS
2118 12:12:13.967388 RX DQ/DQS(Engine): PASS
2119 12:12:13.967475 TX OE : NO K
2120 12:12:13.967542 All Pass.
2121 12:12:13.970443
2122 12:12:13.970526 CH 1, Rank 0
2123 12:12:13.973904 SW Impedance : PASS
2124 12:12:13.973988 DUTY Scan : NO K
2125 12:12:13.976922 ZQ Calibration : PASS
2126 12:12:13.977006 Jitter Meter : NO K
2127 12:12:13.980315 CBT Training : PASS
2128 12:12:13.983854 Write leveling : PASS
2129 12:12:13.983942 RX DQS gating : PASS
2130 12:12:13.987222 RX DQ/DQS(RDDQC) : PASS
2131 12:12:13.990671 TX DQ/DQS : PASS
2132 12:12:13.990758 RX DATLAT : PASS
2133 12:12:13.993746 RX DQ/DQS(Engine): PASS
2134 12:12:13.997168 TX OE : NO K
2135 12:12:13.997255 All Pass.
2136 12:12:13.997320
2137 12:12:13.997380 CH 1, Rank 1
2138 12:12:14.000412 SW Impedance : PASS
2139 12:12:14.003528 DUTY Scan : NO K
2140 12:12:14.003628 ZQ Calibration : PASS
2141 12:12:14.006928 Jitter Meter : NO K
2142 12:12:14.010688 CBT Training : PASS
2143 12:12:14.010782 Write leveling : PASS
2144 12:12:14.014084 RX DQS gating : PASS
2145 12:12:14.016780 RX DQ/DQS(RDDQC) : PASS
2146 12:12:14.016872 TX DQ/DQS : PASS
2147 12:12:14.020139 RX DATLAT : PASS
2148 12:12:14.023525 RX DQ/DQS(Engine): PASS
2149 12:12:14.023611 TX OE : NO K
2150 12:12:14.023676 All Pass.
2151 12:12:14.026693
2152 12:12:14.026775 DramC Write-DBI off
2153 12:12:14.030128 PER_BANK_REFRESH: Hybrid Mode
2154 12:12:14.030214 TX_TRACKING: ON
2155 12:12:14.033265 [GetDramInforAfterCalByMRR] Vendor 6.
2156 12:12:14.036869 [GetDramInforAfterCalByMRR] Revision 606.
2157 12:12:14.043640 [GetDramInforAfterCalByMRR] Revision 2 0.
2158 12:12:14.043746 MR0 0x3b3b
2159 12:12:14.043812 MR8 0x5151
2160 12:12:14.046636 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2161 12:12:14.046721
2162 12:12:14.050449 MR0 0x3b3b
2163 12:12:14.050536 MR8 0x5151
2164 12:12:14.053465 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2165 12:12:14.053549
2166 12:12:14.063377 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2167 12:12:14.066709 [FAST_K] Save calibration result to emmc
2168 12:12:14.070094 [FAST_K] Save calibration result to emmc
2169 12:12:14.073770 dram_init: config_dvfs: 1
2170 12:12:14.076728 dramc_set_vcore_voltage set vcore to 662500
2171 12:12:14.080123 Read voltage for 1200, 2
2172 12:12:14.080212 Vio18 = 0
2173 12:12:14.080279 Vcore = 662500
2174 12:12:14.083839 Vdram = 0
2175 12:12:14.083924 Vddq = 0
2176 12:12:14.083988 Vmddr = 0
2177 12:12:14.090243 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2178 12:12:14.093319 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2179 12:12:14.096558 MEM_TYPE=3, freq_sel=15
2180 12:12:14.099913 sv_algorithm_assistance_LP4_1600
2181 12:12:14.103491 ============ PULL DRAM RESETB DOWN ============
2182 12:12:14.106574 ========== PULL DRAM RESETB DOWN end =========
2183 12:12:14.112916 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2184 12:12:14.116447 ===================================
2185 12:12:14.116563 LPDDR4 DRAM CONFIGURATION
2186 12:12:14.120109 ===================================
2187 12:12:14.123073 EX_ROW_EN[0] = 0x0
2188 12:12:14.126699 EX_ROW_EN[1] = 0x0
2189 12:12:14.126790 LP4Y_EN = 0x0
2190 12:12:14.129985 WORK_FSP = 0x0
2191 12:12:14.130084 WL = 0x4
2192 12:12:14.133108 RL = 0x4
2193 12:12:14.133193 BL = 0x2
2194 12:12:14.136368 RPST = 0x0
2195 12:12:14.136454 RD_PRE = 0x0
2196 12:12:14.139689 WR_PRE = 0x1
2197 12:12:14.139777 WR_PST = 0x0
2198 12:12:14.143184 DBI_WR = 0x0
2199 12:12:14.143268 DBI_RD = 0x0
2200 12:12:14.146498 OTF = 0x1
2201 12:12:14.149463 ===================================
2202 12:12:14.153528 ===================================
2203 12:12:14.153636 ANA top config
2204 12:12:14.156378 ===================================
2205 12:12:14.159677 DLL_ASYNC_EN = 0
2206 12:12:14.163014 ALL_SLAVE_EN = 0
2207 12:12:14.166902 NEW_RANK_MODE = 1
2208 12:12:14.166998 DLL_IDLE_MODE = 1
2209 12:12:14.169709 LP45_APHY_COMB_EN = 1
2210 12:12:14.172827 TX_ODT_DIS = 1
2211 12:12:14.176305 NEW_8X_MODE = 1
2212 12:12:14.179416 ===================================
2213 12:12:14.182771 ===================================
2214 12:12:14.182865 data_rate = 2400
2215 12:12:14.186231 CKR = 1
2216 12:12:14.189508 DQ_P2S_RATIO = 8
2217 12:12:14.193007 ===================================
2218 12:12:14.196235 CA_P2S_RATIO = 8
2219 12:12:14.199501 DQ_CA_OPEN = 0
2220 12:12:14.202932 DQ_SEMI_OPEN = 0
2221 12:12:14.203019 CA_SEMI_OPEN = 0
2222 12:12:14.206437 CA_FULL_RATE = 0
2223 12:12:14.209570 DQ_CKDIV4_EN = 0
2224 12:12:14.212599 CA_CKDIV4_EN = 0
2225 12:12:14.215916 CA_PREDIV_EN = 0
2226 12:12:14.219772 PH8_DLY = 17
2227 12:12:14.222570 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2228 12:12:14.222676 DQ_AAMCK_DIV = 4
2229 12:12:14.225649 CA_AAMCK_DIV = 4
2230 12:12:14.229166 CA_ADMCK_DIV = 4
2231 12:12:14.232481 DQ_TRACK_CA_EN = 0
2232 12:12:14.235568 CA_PICK = 1200
2233 12:12:14.239953 CA_MCKIO = 1200
2234 12:12:14.242525 MCKIO_SEMI = 0
2235 12:12:14.242616 PLL_FREQ = 2366
2236 12:12:14.246063 DQ_UI_PI_RATIO = 32
2237 12:12:14.248751 CA_UI_PI_RATIO = 0
2238 12:12:14.252419 ===================================
2239 12:12:14.255251 ===================================
2240 12:12:14.259012 memory_type:LPDDR4
2241 12:12:14.262393 GP_NUM : 10
2242 12:12:14.262482 SRAM_EN : 1
2243 12:12:14.265570 MD32_EN : 0
2244 12:12:14.268905 ===================================
2245 12:12:14.269009 [ANA_INIT] >>>>>>>>>>>>>>
2246 12:12:14.272174 <<<<<< [CONFIGURE PHASE]: ANA_TX
2247 12:12:14.275700 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2248 12:12:14.278646 ===================================
2249 12:12:14.281907 data_rate = 2400,PCW = 0X5b00
2250 12:12:14.285240 ===================================
2251 12:12:14.288906 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2252 12:12:14.295570 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2253 12:12:14.301647 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2254 12:12:14.305353 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2255 12:12:14.308484 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2256 12:12:14.312000 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2257 12:12:14.315230 [ANA_INIT] flow start
2258 12:12:14.315320 [ANA_INIT] PLL >>>>>>>>
2259 12:12:14.318496 [ANA_INIT] PLL <<<<<<<<
2260 12:12:14.321681 [ANA_INIT] MIDPI >>>>>>>>
2261 12:12:14.321770 [ANA_INIT] MIDPI <<<<<<<<
2262 12:12:14.325050 [ANA_INIT] DLL >>>>>>>>
2263 12:12:14.328493 [ANA_INIT] DLL <<<<<<<<
2264 12:12:14.328581 [ANA_INIT] flow end
2265 12:12:14.335241 ============ LP4 DIFF to SE enter ============
2266 12:12:14.338254 ============ LP4 DIFF to SE exit ============
2267 12:12:14.338346 [ANA_INIT] <<<<<<<<<<<<<
2268 12:12:14.341689 [Flow] Enable top DCM control >>>>>
2269 12:12:14.344938 [Flow] Enable top DCM control <<<<<
2270 12:12:14.348062 Enable DLL master slave shuffle
2271 12:12:14.354774 ==============================================================
2272 12:12:14.358284 Gating Mode config
2273 12:12:14.361582 ==============================================================
2274 12:12:14.364980 Config description:
2275 12:12:14.374698 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2276 12:12:14.380968 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2277 12:12:14.384732 SELPH_MODE 0: By rank 1: By Phase
2278 12:12:14.391246 ==============================================================
2279 12:12:14.394810 GAT_TRACK_EN = 1
2280 12:12:14.397823 RX_GATING_MODE = 2
2281 12:12:14.401452 RX_GATING_TRACK_MODE = 2
2282 12:12:14.404267 SELPH_MODE = 1
2283 12:12:14.404356 PICG_EARLY_EN = 1
2284 12:12:14.407664 VALID_LAT_VALUE = 1
2285 12:12:14.414467 ==============================================================
2286 12:12:14.417921 Enter into Gating configuration >>>>
2287 12:12:14.421059 Exit from Gating configuration <<<<
2288 12:12:14.424123 Enter into DVFS_PRE_config >>>>>
2289 12:12:14.434198 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2290 12:12:14.437889 Exit from DVFS_PRE_config <<<<<
2291 12:12:14.440993 Enter into PICG configuration >>>>
2292 12:12:14.444398 Exit from PICG configuration <<<<
2293 12:12:14.447853 [RX_INPUT] configuration >>>>>
2294 12:12:14.450939 [RX_INPUT] configuration <<<<<
2295 12:12:14.454082 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2296 12:12:14.460696 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2297 12:12:14.467839 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2298 12:12:14.473842 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2299 12:12:14.480617 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2300 12:12:14.487224 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2301 12:12:14.490479 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2302 12:12:14.494381 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2303 12:12:14.497427 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2304 12:12:14.500434 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2305 12:12:14.506934 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2306 12:12:14.510397 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2307 12:12:14.513628 ===================================
2308 12:12:14.516718 LPDDR4 DRAM CONFIGURATION
2309 12:12:14.520217 ===================================
2310 12:12:14.520313 EX_ROW_EN[0] = 0x0
2311 12:12:14.523818 EX_ROW_EN[1] = 0x0
2312 12:12:14.523906 LP4Y_EN = 0x0
2313 12:12:14.527109 WORK_FSP = 0x0
2314 12:12:14.527195 WL = 0x4
2315 12:12:14.530540 RL = 0x4
2316 12:12:14.530625 BL = 0x2
2317 12:12:14.533660 RPST = 0x0
2318 12:12:14.537113 RD_PRE = 0x0
2319 12:12:14.537201 WR_PRE = 0x1
2320 12:12:14.540344 WR_PST = 0x0
2321 12:12:14.540429 DBI_WR = 0x0
2322 12:12:14.543330 DBI_RD = 0x0
2323 12:12:14.543455 OTF = 0x1
2324 12:12:14.546866 ===================================
2325 12:12:14.550216 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2326 12:12:14.557359 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2327 12:12:14.560665 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2328 12:12:14.564802 ===================================
2329 12:12:14.566686 LPDDR4 DRAM CONFIGURATION
2330 12:12:14.569965 ===================================
2331 12:12:14.570055 EX_ROW_EN[0] = 0x10
2332 12:12:14.573249 EX_ROW_EN[1] = 0x0
2333 12:12:14.573335 LP4Y_EN = 0x0
2334 12:12:14.576407 WORK_FSP = 0x0
2335 12:12:14.576493 WL = 0x4
2336 12:12:14.579977 RL = 0x4
2337 12:12:14.580062 BL = 0x2
2338 12:12:14.583296 RPST = 0x0
2339 12:12:14.586522 RD_PRE = 0x0
2340 12:12:14.586609 WR_PRE = 0x1
2341 12:12:14.590314 WR_PST = 0x0
2342 12:12:14.590397 DBI_WR = 0x0
2343 12:12:14.593145 DBI_RD = 0x0
2344 12:12:14.593227 OTF = 0x1
2345 12:12:14.596287 ===================================
2346 12:12:14.602825 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2347 12:12:14.602947 ==
2348 12:12:14.606743 Dram Type= 6, Freq= 0, CH_0, rank 0
2349 12:12:14.609982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2350 12:12:14.610080 ==
2351 12:12:14.613285 [Duty_Offset_Calibration]
2352 12:12:14.616580 B0:2 B1:0 CA:4
2353 12:12:14.616665
2354 12:12:14.619851 [DutyScan_Calibration_Flow] k_type=0
2355 12:12:14.627164
2356 12:12:14.627274 ==CLK 0==
2357 12:12:14.630034 Final CLK duty delay cell = -4
2358 12:12:14.633258 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2359 12:12:14.636432 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2360 12:12:14.640409 [-4] AVG Duty = 4937%(X100)
2361 12:12:14.640510
2362 12:12:14.643596 CH0 CLK Duty spec in!! Max-Min= 187%
2363 12:12:14.647011 [DutyScan_Calibration_Flow] ====Done====
2364 12:12:14.647100
2365 12:12:14.650037 [DutyScan_Calibration_Flow] k_type=1
2366 12:12:14.666116
2367 12:12:14.666257 ==DQS 0 ==
2368 12:12:14.669332 Final DQS duty delay cell = 0
2369 12:12:14.672931 [0] MAX Duty = 5156%(X100), DQS PI = 18
2370 12:12:14.676380 [0] MIN Duty = 5093%(X100), DQS PI = 0
2371 12:12:14.676475 [0] AVG Duty = 5124%(X100)
2372 12:12:14.679730
2373 12:12:14.679815 ==DQS 1 ==
2374 12:12:14.682883 Final DQS duty delay cell = 0
2375 12:12:14.686573 [0] MAX Duty = 5125%(X100), DQS PI = 50
2376 12:12:14.689676 [0] MIN Duty = 5000%(X100), DQS PI = 0
2377 12:12:14.689768 [0] AVG Duty = 5062%(X100)
2378 12:12:14.692987
2379 12:12:14.696361 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2380 12:12:14.696449
2381 12:12:14.699656 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2382 12:12:14.702686 [DutyScan_Calibration_Flow] ====Done====
2383 12:12:14.702770
2384 12:12:14.706250 [DutyScan_Calibration_Flow] k_type=3
2385 12:12:14.722674
2386 12:12:14.722812 ==DQM 0 ==
2387 12:12:14.726204 Final DQM duty delay cell = 0
2388 12:12:14.729302 [0] MAX Duty = 5125%(X100), DQS PI = 20
2389 12:12:14.732559 [0] MIN Duty = 4844%(X100), DQS PI = 52
2390 12:12:14.736183 [0] AVG Duty = 4984%(X100)
2391 12:12:14.736274
2392 12:12:14.736339 ==DQM 1 ==
2393 12:12:14.738975 Final DQM duty delay cell = 0
2394 12:12:14.742288 [0] MAX Duty = 4969%(X100), DQS PI = 2
2395 12:12:14.745881 [0] MIN Duty = 4875%(X100), DQS PI = 14
2396 12:12:14.748854 [0] AVG Duty = 4922%(X100)
2397 12:12:14.748965
2398 12:12:14.752278 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2399 12:12:14.752361
2400 12:12:14.755664 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2401 12:12:14.758944 [DutyScan_Calibration_Flow] ====Done====
2402 12:12:14.759033
2403 12:12:14.762085 [DutyScan_Calibration_Flow] k_type=2
2404 12:12:14.779655
2405 12:12:14.779803 ==DQ 0 ==
2406 12:12:14.782675 Final DQ duty delay cell = 0
2407 12:12:14.785567 [0] MAX Duty = 5125%(X100), DQS PI = 18
2408 12:12:14.788802 [0] MIN Duty = 4969%(X100), DQS PI = 52
2409 12:12:14.788891 [0] AVG Duty = 5047%(X100)
2410 12:12:14.792364
2411 12:12:14.792446 ==DQ 1 ==
2412 12:12:14.795499 Final DQ duty delay cell = 0
2413 12:12:14.799137 [0] MAX Duty = 5156%(X100), DQS PI = 4
2414 12:12:14.802116 [0] MIN Duty = 4938%(X100), DQS PI = 16
2415 12:12:14.802202 [0] AVG Duty = 5047%(X100)
2416 12:12:14.802266
2417 12:12:14.805569 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2418 12:12:14.809018
2419 12:12:14.812713 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2420 12:12:14.815704 [DutyScan_Calibration_Flow] ====Done====
2421 12:12:14.815792 ==
2422 12:12:14.818829 Dram Type= 6, Freq= 0, CH_1, rank 0
2423 12:12:14.822612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2424 12:12:14.822704 ==
2425 12:12:14.825686 [Duty_Offset_Calibration]
2426 12:12:14.825769 B0:0 B1:-1 CA:3
2427 12:12:14.825842
2428 12:12:14.828814 [DutyScan_Calibration_Flow] k_type=0
2429 12:12:14.838249
2430 12:12:14.838360 ==CLK 0==
2431 12:12:14.841568 Final CLK duty delay cell = -4
2432 12:12:14.845055 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2433 12:12:14.848720 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2434 12:12:14.851663 [-4] AVG Duty = 4938%(X100)
2435 12:12:14.851749
2436 12:12:14.854872 CH1 CLK Duty spec in!! Max-Min= 124%
2437 12:12:14.858149 [DutyScan_Calibration_Flow] ====Done====
2438 12:12:14.858234
2439 12:12:14.861673 [DutyScan_Calibration_Flow] k_type=1
2440 12:12:14.877803
2441 12:12:14.877933 ==DQS 0 ==
2442 12:12:14.881511 Final DQS duty delay cell = 0
2443 12:12:14.884250 [0] MAX Duty = 5187%(X100), DQS PI = 18
2444 12:12:14.887912 [0] MIN Duty = 4907%(X100), DQS PI = 38
2445 12:12:14.891749 [0] AVG Duty = 5047%(X100)
2446 12:12:14.891846
2447 12:12:14.891911 ==DQS 1 ==
2448 12:12:14.894880 Final DQS duty delay cell = 0
2449 12:12:14.897840 [0] MAX Duty = 5156%(X100), DQS PI = 8
2450 12:12:14.901163 [0] MIN Duty = 5031%(X100), DQS PI = 22
2451 12:12:14.904360 [0] AVG Duty = 5093%(X100)
2452 12:12:14.904445
2453 12:12:14.907790 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2454 12:12:14.907874
2455 12:12:14.911452 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2456 12:12:14.914256 [DutyScan_Calibration_Flow] ====Done====
2457 12:12:14.914341
2458 12:12:14.917634 [DutyScan_Calibration_Flow] k_type=3
2459 12:12:14.934296
2460 12:12:14.934441 ==DQM 0 ==
2461 12:12:14.937472 Final DQM duty delay cell = 0
2462 12:12:14.940916 [0] MAX Duty = 5031%(X100), DQS PI = 26
2463 12:12:14.944568 [0] MIN Duty = 4813%(X100), DQS PI = 38
2464 12:12:14.944667 [0] AVG Duty = 4922%(X100)
2465 12:12:14.947694
2466 12:12:14.947783 ==DQM 1 ==
2467 12:12:14.950947 Final DQM duty delay cell = 0
2468 12:12:14.954508 [0] MAX Duty = 5000%(X100), DQS PI = 36
2469 12:12:14.957969 [0] MIN Duty = 4813%(X100), DQS PI = 0
2470 12:12:14.960734 [0] AVG Duty = 4906%(X100)
2471 12:12:14.960826
2472 12:12:14.964152 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2473 12:12:14.964240
2474 12:12:14.967695 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2475 12:12:14.971006 [DutyScan_Calibration_Flow] ====Done====
2476 12:12:14.971098
2477 12:12:14.974299 [DutyScan_Calibration_Flow] k_type=2
2478 12:12:14.991006
2479 12:12:14.991151 ==DQ 0 ==
2480 12:12:14.994433 Final DQ duty delay cell = -4
2481 12:12:14.997866 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2482 12:12:15.001128 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2483 12:12:15.004407 [-4] AVG Duty = 4922%(X100)
2484 12:12:15.004504
2485 12:12:15.004591 ==DQ 1 ==
2486 12:12:15.007693 Final DQ duty delay cell = 4
2487 12:12:15.011101 [4] MAX Duty = 5156%(X100), DQS PI = 10
2488 12:12:15.014047 [4] MIN Duty = 5062%(X100), DQS PI = 0
2489 12:12:15.014137 [4] AVG Duty = 5109%(X100)
2490 12:12:15.017703
2491 12:12:15.020694 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2492 12:12:15.020809
2493 12:12:15.023749 CH1 DQ 1 Duty spec in!! Max-Min= 94%
2494 12:12:15.027137 [DutyScan_Calibration_Flow] ====Done====
2495 12:12:15.030510 nWR fixed to 30
2496 12:12:15.030599 [ModeRegInit_LP4] CH0 RK0
2497 12:12:15.034167 [ModeRegInit_LP4] CH0 RK1
2498 12:12:15.037599 [ModeRegInit_LP4] CH1 RK0
2499 12:12:15.040881 [ModeRegInit_LP4] CH1 RK1
2500 12:12:15.040969 match AC timing 7
2501 12:12:15.043782 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2502 12:12:15.050509 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2503 12:12:15.053886 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2504 12:12:15.060519 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2505 12:12:15.064104 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2506 12:12:15.064198 ==
2507 12:12:15.067094 Dram Type= 6, Freq= 0, CH_0, rank 0
2508 12:12:15.070484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 12:12:15.070570 ==
2510 12:12:15.076784 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2511 12:12:15.083497 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2512 12:12:15.090845 [CA 0] Center 39 (9~70) winsize 62
2513 12:12:15.094488 [CA 1] Center 39 (9~69) winsize 61
2514 12:12:15.097514 [CA 2] Center 35 (5~66) winsize 62
2515 12:12:15.101111 [CA 3] Center 35 (5~66) winsize 62
2516 12:12:15.104465 [CA 4] Center 33 (3~64) winsize 62
2517 12:12:15.107763 [CA 5] Center 33 (3~63) winsize 61
2518 12:12:15.107855
2519 12:12:15.111178 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2520 12:12:15.111262
2521 12:12:15.114361 [CATrainingPosCal] consider 1 rank data
2522 12:12:15.117638 u2DelayCellTimex100 = 270/100 ps
2523 12:12:15.120516 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2524 12:12:15.127249 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2525 12:12:15.131508 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2526 12:12:15.134123 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2527 12:12:15.137908 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2528 12:12:15.140561 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2529 12:12:15.140647
2530 12:12:15.143880 CA PerBit enable=1, Macro0, CA PI delay=33
2531 12:12:15.143964
2532 12:12:15.147005 [CBTSetCACLKResult] CA Dly = 33
2533 12:12:15.150736 CS Dly: 7 (0~38)
2534 12:12:15.150826 ==
2535 12:12:15.153617 Dram Type= 6, Freq= 0, CH_0, rank 1
2536 12:12:15.157414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2537 12:12:15.157504 ==
2538 12:12:15.163884 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2539 12:12:15.166876 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2540 12:12:15.177070 [CA 0] Center 39 (9~70) winsize 62
2541 12:12:15.180236 [CA 1] Center 39 (9~70) winsize 62
2542 12:12:15.183991 [CA 2] Center 35 (5~66) winsize 62
2543 12:12:15.186622 [CA 3] Center 35 (5~66) winsize 62
2544 12:12:15.189931 [CA 4] Center 34 (4~65) winsize 62
2545 12:12:15.193014 [CA 5] Center 33 (3~64) winsize 62
2546 12:12:15.193105
2547 12:12:15.196863 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2548 12:12:15.196949
2549 12:12:15.199716 [CATrainingPosCal] consider 2 rank data
2550 12:12:15.202958 u2DelayCellTimex100 = 270/100 ps
2551 12:12:15.207154 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2552 12:12:15.213037 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2553 12:12:15.216510 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2554 12:12:15.219666 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2555 12:12:15.223294 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2556 12:12:15.226582 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2557 12:12:15.226715
2558 12:12:15.229974 CA PerBit enable=1, Macro0, CA PI delay=33
2559 12:12:15.230060
2560 12:12:15.233090 [CBTSetCACLKResult] CA Dly = 33
2561 12:12:15.236252 CS Dly: 8 (0~41)
2562 12:12:15.236338
2563 12:12:15.239547 ----->DramcWriteLeveling(PI) begin...
2564 12:12:15.239632 ==
2565 12:12:15.243097 Dram Type= 6, Freq= 0, CH_0, rank 0
2566 12:12:15.246072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2567 12:12:15.246157 ==
2568 12:12:15.249247 Write leveling (Byte 0): 32 => 32
2569 12:12:15.252537 Write leveling (Byte 1): 26 => 26
2570 12:12:15.256172 DramcWriteLeveling(PI) end<-----
2571 12:12:15.256259
2572 12:12:15.256325 ==
2573 12:12:15.258997 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 12:12:15.262905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 12:12:15.262991 ==
2576 12:12:15.265906 [Gating] SW mode calibration
2577 12:12:15.272566 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2578 12:12:15.279382 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2579 12:12:15.282456 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2580 12:12:15.285779 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
2581 12:12:15.292436 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 12:12:15.295820 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 12:12:15.299477 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 12:12:15.306152 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 12:12:15.309550 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2586 12:12:15.312445 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
2587 12:12:15.319116 1 0 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
2588 12:12:15.322650 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 12:12:15.325810 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 12:12:15.332406 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 12:12:15.336278 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 12:12:15.339002 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 12:12:15.345489 1 0 24 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
2594 12:12:15.349142 1 0 28 | B1->B0 | 2323 4242 | 0 1 | (0 0) (1 1)
2595 12:12:15.352215 1 1 0 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2596 12:12:15.355895 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2597 12:12:15.362244 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 12:12:15.365459 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 12:12:15.369111 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 12:12:15.375354 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 12:12:15.378687 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2602 12:12:15.382164 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2603 12:12:15.389333 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2604 12:12:15.392408 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2605 12:12:15.395227 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 12:12:15.401911 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 12:12:15.405317 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 12:12:15.408934 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 12:12:15.415626 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 12:12:15.418501 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 12:12:15.421976 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 12:12:15.428453 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 12:12:15.431664 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 12:12:15.435029 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 12:12:15.441723 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 12:12:15.445313 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 12:12:15.448504 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2618 12:12:15.455102 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2619 12:12:15.458451 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2620 12:12:15.461745 Total UI for P1: 0, mck2ui 16
2621 12:12:15.464926 best dqsien dly found for B0: ( 1, 3, 26)
2622 12:12:15.468701 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 12:12:15.471854 Total UI for P1: 0, mck2ui 16
2624 12:12:15.475253 best dqsien dly found for B1: ( 1, 4, 2)
2625 12:12:15.478103 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2626 12:12:15.481415 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2627 12:12:15.481496
2628 12:12:15.484797 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2629 12:12:15.491398 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2630 12:12:15.491479 [Gating] SW calibration Done
2631 12:12:15.491542 ==
2632 12:12:15.495184 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 12:12:15.501636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 12:12:15.501725 ==
2635 12:12:15.501790 RX Vref Scan: 0
2636 12:12:15.501850
2637 12:12:15.504922 RX Vref 0 -> 0, step: 1
2638 12:12:15.505003
2639 12:12:15.508395 RX Delay -40 -> 252, step: 8
2640 12:12:15.511769 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2641 12:12:15.515289 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2642 12:12:15.518244 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2643 12:12:15.525358 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2644 12:12:15.528501 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2645 12:12:15.531413 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2646 12:12:15.534665 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2647 12:12:15.538339 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2648 12:12:15.545162 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2649 12:12:15.548467 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2650 12:12:15.551319 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2651 12:12:15.554764 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2652 12:12:15.558422 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2653 12:12:15.564986 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2654 12:12:15.567634 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2655 12:12:15.570944 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2656 12:12:15.571030 ==
2657 12:12:15.574684 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 12:12:15.577855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 12:12:15.580856 ==
2660 12:12:15.580942 DQS Delay:
2661 12:12:15.581029 DQS0 = 0, DQS1 = 0
2662 12:12:15.584212 DQM Delay:
2663 12:12:15.584296 DQM0 = 117, DQM1 = 107
2664 12:12:15.587497 DQ Delay:
2665 12:12:15.591002 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2666 12:12:15.595021 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2667 12:12:15.597495 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2668 12:12:15.601019 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2669 12:12:15.601105
2670 12:12:15.601192
2671 12:12:15.601274 ==
2672 12:12:15.603964 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 12:12:15.607970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 12:12:15.608055 ==
2675 12:12:15.608141
2676 12:12:15.608222
2677 12:12:15.611179 TX Vref Scan disable
2678 12:12:15.614262 == TX Byte 0 ==
2679 12:12:15.617283 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2680 12:12:15.620650 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2681 12:12:15.623922 == TX Byte 1 ==
2682 12:12:15.627265 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2683 12:12:15.630566 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2684 12:12:15.630652 ==
2685 12:12:15.634214 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 12:12:15.640660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 12:12:15.640746 ==
2688 12:12:15.651433 TX Vref=22, minBit 5, minWin=25, winSum=413
2689 12:12:15.655025 TX Vref=24, minBit 8, minWin=25, winSum=419
2690 12:12:15.658494 TX Vref=26, minBit 10, minWin=25, winSum=422
2691 12:12:15.661434 TX Vref=28, minBit 4, minWin=26, winSum=431
2692 12:12:15.664615 TX Vref=30, minBit 5, minWin=26, winSum=430
2693 12:12:15.671742 TX Vref=32, minBit 5, minWin=26, winSum=432
2694 12:12:15.674969 [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 32
2695 12:12:15.675055
2696 12:12:15.677995 Final TX Range 1 Vref 32
2697 12:12:15.678081
2698 12:12:15.678167 ==
2699 12:12:15.681441 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 12:12:15.684727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 12:12:15.684809 ==
2702 12:12:15.687889
2703 12:12:15.687971
2704 12:12:15.688035 TX Vref Scan disable
2705 12:12:15.691298 == TX Byte 0 ==
2706 12:12:15.694440 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2707 12:12:15.701395 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2708 12:12:15.701477 == TX Byte 1 ==
2709 12:12:15.704461 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2710 12:12:15.711285 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2711 12:12:15.711392
2712 12:12:15.711471 [DATLAT]
2713 12:12:15.711531 Freq=1200, CH0 RK0
2714 12:12:15.711589
2715 12:12:15.714514 DATLAT Default: 0xd
2716 12:12:15.717705 0, 0xFFFF, sum = 0
2717 12:12:15.717787 1, 0xFFFF, sum = 0
2718 12:12:15.721164 2, 0xFFFF, sum = 0
2719 12:12:15.721246 3, 0xFFFF, sum = 0
2720 12:12:15.724397 4, 0xFFFF, sum = 0
2721 12:12:15.724480 5, 0xFFFF, sum = 0
2722 12:12:15.727631 6, 0xFFFF, sum = 0
2723 12:12:15.727713 7, 0xFFFF, sum = 0
2724 12:12:15.731276 8, 0xFFFF, sum = 0
2725 12:12:15.731423 9, 0xFFFF, sum = 0
2726 12:12:15.734086 10, 0xFFFF, sum = 0
2727 12:12:15.734168 11, 0xFFFF, sum = 0
2728 12:12:15.737496 12, 0x0, sum = 1
2729 12:12:15.737578 13, 0x0, sum = 2
2730 12:12:15.741154 14, 0x0, sum = 3
2731 12:12:15.741236 15, 0x0, sum = 4
2732 12:12:15.744383 best_step = 13
2733 12:12:15.744468
2734 12:12:15.744531 ==
2735 12:12:15.748068 Dram Type= 6, Freq= 0, CH_0, rank 0
2736 12:12:15.750808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2737 12:12:15.750889 ==
2738 12:12:15.750953 RX Vref Scan: 1
2739 12:12:15.754144
2740 12:12:15.754225 Set Vref Range= 32 -> 127
2741 12:12:15.754288
2742 12:12:15.757907 RX Vref 32 -> 127, step: 1
2743 12:12:15.757988
2744 12:12:15.760830 RX Delay -21 -> 252, step: 4
2745 12:12:15.760911
2746 12:12:15.764269 Set Vref, RX VrefLevel [Byte0]: 32
2747 12:12:15.767395 [Byte1]: 32
2748 12:12:15.767490
2749 12:12:15.770852 Set Vref, RX VrefLevel [Byte0]: 33
2750 12:12:15.774023 [Byte1]: 33
2751 12:12:15.777721
2752 12:12:15.777802 Set Vref, RX VrefLevel [Byte0]: 34
2753 12:12:15.780948 [Byte1]: 34
2754 12:12:15.785528
2755 12:12:15.785609 Set Vref, RX VrefLevel [Byte0]: 35
2756 12:12:15.788963 [Byte1]: 35
2757 12:12:15.793712
2758 12:12:15.793793 Set Vref, RX VrefLevel [Byte0]: 36
2759 12:12:15.797456 [Byte1]: 36
2760 12:12:15.801639
2761 12:12:15.801719 Set Vref, RX VrefLevel [Byte0]: 37
2762 12:12:15.805119 [Byte1]: 37
2763 12:12:15.809523
2764 12:12:15.809604 Set Vref, RX VrefLevel [Byte0]: 38
2765 12:12:15.812614 [Byte1]: 38
2766 12:12:15.817407
2767 12:12:15.817491 Set Vref, RX VrefLevel [Byte0]: 39
2768 12:12:15.821057 [Byte1]: 39
2769 12:12:15.825257
2770 12:12:15.825339 Set Vref, RX VrefLevel [Byte0]: 40
2771 12:12:15.828551 [Byte1]: 40
2772 12:12:15.833438
2773 12:12:15.833518 Set Vref, RX VrefLevel [Byte0]: 41
2774 12:12:15.837177 [Byte1]: 41
2775 12:12:15.841032
2776 12:12:15.841112 Set Vref, RX VrefLevel [Byte0]: 42
2777 12:12:15.844406 [Byte1]: 42
2778 12:12:15.849038
2779 12:12:15.849119 Set Vref, RX VrefLevel [Byte0]: 43
2780 12:12:15.852659 [Byte1]: 43
2781 12:12:15.857307
2782 12:12:15.857396 Set Vref, RX VrefLevel [Byte0]: 44
2783 12:12:15.860125 [Byte1]: 44
2784 12:12:15.864727
2785 12:12:15.864833 Set Vref, RX VrefLevel [Byte0]: 45
2786 12:12:15.868309 [Byte1]: 45
2787 12:12:15.872743
2788 12:12:15.872824 Set Vref, RX VrefLevel [Byte0]: 46
2789 12:12:15.876068 [Byte1]: 46
2790 12:12:15.880800
2791 12:12:15.880881 Set Vref, RX VrefLevel [Byte0]: 47
2792 12:12:15.884035 [Byte1]: 47
2793 12:12:15.888850
2794 12:12:15.888931 Set Vref, RX VrefLevel [Byte0]: 48
2795 12:12:15.891792 [Byte1]: 48
2796 12:12:15.896963
2797 12:12:15.897048 Set Vref, RX VrefLevel [Byte0]: 49
2798 12:12:15.900277 [Byte1]: 49
2799 12:12:15.904619
2800 12:12:15.904704 Set Vref, RX VrefLevel [Byte0]: 50
2801 12:12:15.907828 [Byte1]: 50
2802 12:12:15.912322
2803 12:12:15.912408 Set Vref, RX VrefLevel [Byte0]: 51
2804 12:12:15.915684 [Byte1]: 51
2805 12:12:15.920484
2806 12:12:15.920573 Set Vref, RX VrefLevel [Byte0]: 52
2807 12:12:15.923502 [Byte1]: 52
2808 12:12:15.928402
2809 12:12:15.928488 Set Vref, RX VrefLevel [Byte0]: 53
2810 12:12:15.931487 [Byte1]: 53
2811 12:12:15.936704
2812 12:12:15.936789 Set Vref, RX VrefLevel [Byte0]: 54
2813 12:12:15.939986 [Byte1]: 54
2814 12:12:15.944366
2815 12:12:15.944452 Set Vref, RX VrefLevel [Byte0]: 55
2816 12:12:15.947245 [Byte1]: 55
2817 12:12:15.952740
2818 12:12:15.952824 Set Vref, RX VrefLevel [Byte0]: 56
2819 12:12:15.955469 [Byte1]: 56
2820 12:12:15.960250
2821 12:12:15.960332 Set Vref, RX VrefLevel [Byte0]: 57
2822 12:12:15.963451 [Byte1]: 57
2823 12:12:15.968242
2824 12:12:15.968323 Set Vref, RX VrefLevel [Byte0]: 58
2825 12:12:15.971736 [Byte1]: 58
2826 12:12:15.975685
2827 12:12:15.975768 Set Vref, RX VrefLevel [Byte0]: 59
2828 12:12:15.979160 [Byte1]: 59
2829 12:12:15.984621
2830 12:12:15.984706 Set Vref, RX VrefLevel [Byte0]: 60
2831 12:12:15.987014 [Byte1]: 60
2832 12:12:15.991929
2833 12:12:15.992011 Set Vref, RX VrefLevel [Byte0]: 61
2834 12:12:15.995212 [Byte1]: 61
2835 12:12:15.999499
2836 12:12:15.999583 Set Vref, RX VrefLevel [Byte0]: 62
2837 12:12:16.003236 [Byte1]: 62
2838 12:12:16.007921
2839 12:12:16.008003 Set Vref, RX VrefLevel [Byte0]: 63
2840 12:12:16.010939 [Byte1]: 63
2841 12:12:16.015576
2842 12:12:16.015659 Set Vref, RX VrefLevel [Byte0]: 64
2843 12:12:16.019154 [Byte1]: 64
2844 12:12:16.023353
2845 12:12:16.023483 Set Vref, RX VrefLevel [Byte0]: 65
2846 12:12:16.026896 [Byte1]: 65
2847 12:12:16.031620
2848 12:12:16.031705 Set Vref, RX VrefLevel [Byte0]: 66
2849 12:12:16.034897 [Byte1]: 66
2850 12:12:16.039439
2851 12:12:16.039525 Set Vref, RX VrefLevel [Byte0]: 67
2852 12:12:16.042455 [Byte1]: 67
2853 12:12:16.047366
2854 12:12:16.047488 Set Vref, RX VrefLevel [Byte0]: 68
2855 12:12:16.050717 [Byte1]: 68
2856 12:12:16.055186
2857 12:12:16.055270 Final RX Vref Byte 0 = 54 to rank0
2858 12:12:16.059140 Final RX Vref Byte 1 = 59 to rank0
2859 12:12:16.062156 Final RX Vref Byte 0 = 54 to rank1
2860 12:12:16.065049 Final RX Vref Byte 1 = 59 to rank1==
2861 12:12:16.068341 Dram Type= 6, Freq= 0, CH_0, rank 0
2862 12:12:16.075030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2863 12:12:16.075119 ==
2864 12:12:16.075184 DQS Delay:
2865 12:12:16.075277 DQS0 = 0, DQS1 = 0
2866 12:12:16.078554 DQM Delay:
2867 12:12:16.078636 DQM0 = 117, DQM1 = 105
2868 12:12:16.082002 DQ Delay:
2869 12:12:16.085029 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2870 12:12:16.088634 DQ4 =120, DQ5 =110, DQ6 =124, DQ7 =122
2871 12:12:16.092227 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2872 12:12:16.094750 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =112
2873 12:12:16.094832
2874 12:12:16.094908
2875 12:12:16.101350 [DQSOSCAuto] RK0, (LSB)MR18= 0x1fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
2876 12:12:16.104763 CH0 RK0: MR19=403, MR18=1FC
2877 12:12:16.111573 CH0_RK0: MR19=0x403, MR18=0x1FC, DQSOSC=409, MR23=63, INC=39, DEC=26
2878 12:12:16.111667
2879 12:12:16.115042 ----->DramcWriteLeveling(PI) begin...
2880 12:12:16.115153 ==
2881 12:12:16.118335 Dram Type= 6, Freq= 0, CH_0, rank 1
2882 12:12:16.121734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2883 12:12:16.121821 ==
2884 12:12:16.125005 Write leveling (Byte 0): 32 => 32
2885 12:12:16.128265 Write leveling (Byte 1): 28 => 28
2886 12:12:16.131797 DramcWriteLeveling(PI) end<-----
2887 12:12:16.131879
2888 12:12:16.131943 ==
2889 12:12:16.134828 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 12:12:16.141567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 12:12:16.141664 ==
2892 12:12:16.141732 [Gating] SW mode calibration
2893 12:12:16.151250 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2894 12:12:16.154928 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2895 12:12:16.158093 0 15 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
2896 12:12:16.165246 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 12:12:16.168000 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 12:12:16.171729 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 12:12:16.177905 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 12:12:16.181788 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2901 12:12:16.184699 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2902 12:12:16.192116 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
2903 12:12:16.194519 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
2904 12:12:16.197907 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 12:12:16.204985 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 12:12:16.208023 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 12:12:16.211398 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 12:12:16.218167 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 12:12:16.221078 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2910 12:12:16.224361 1 0 28 | B1->B0 | 2727 4444 | 1 0 | (0 0) (0 0)
2911 12:12:16.230937 1 1 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2912 12:12:16.234385 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 12:12:16.237486 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 12:12:16.244166 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 12:12:16.247687 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 12:12:16.250715 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 12:12:16.257529 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2918 12:12:16.260536 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2919 12:12:16.264005 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2920 12:12:16.270603 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 12:12:16.274255 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 12:12:16.277127 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 12:12:16.283952 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 12:12:16.287135 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 12:12:16.290660 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 12:12:16.297244 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 12:12:16.300881 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 12:12:16.304103 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 12:12:16.310745 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 12:12:16.314512 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 12:12:16.317684 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 12:12:16.323774 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2933 12:12:16.327349 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2934 12:12:16.330285 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2935 12:12:16.333974 Total UI for P1: 0, mck2ui 16
2936 12:12:16.337192 best dqsien dly found for B0: ( 1, 3, 22)
2937 12:12:16.340654 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2938 12:12:16.347223 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 12:12:16.350252 Total UI for P1: 0, mck2ui 16
2940 12:12:16.353724 best dqsien dly found for B1: ( 1, 3, 30)
2941 12:12:16.357193 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
2942 12:12:16.360110 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2943 12:12:16.360199
2944 12:12:16.363615 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
2945 12:12:16.366816 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2946 12:12:16.370240 [Gating] SW calibration Done
2947 12:12:16.370324 ==
2948 12:12:16.373784 Dram Type= 6, Freq= 0, CH_0, rank 1
2949 12:12:16.376713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2950 12:12:16.376796 ==
2951 12:12:16.380205 RX Vref Scan: 0
2952 12:12:16.380288
2953 12:12:16.383444 RX Vref 0 -> 0, step: 1
2954 12:12:16.383526
2955 12:12:16.383590 RX Delay -40 -> 252, step: 8
2956 12:12:16.390257 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2957 12:12:16.392976 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2958 12:12:16.396230 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2959 12:12:16.400136 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2960 12:12:16.406565 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2961 12:12:16.409883 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2962 12:12:16.413960 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2963 12:12:16.416449 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2964 12:12:16.419586 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2965 12:12:16.423171 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2966 12:12:16.429871 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2967 12:12:16.432824 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2968 12:12:16.436524 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2969 12:12:16.439659 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2970 12:12:16.445968 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2971 12:12:16.449557 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2972 12:12:16.449641 ==
2973 12:12:16.452883 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 12:12:16.455892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 12:12:16.455974 ==
2976 12:12:16.456037 DQS Delay:
2977 12:12:16.459232 DQS0 = 0, DQS1 = 0
2978 12:12:16.459314 DQM Delay:
2979 12:12:16.462771 DQM0 = 117, DQM1 = 109
2980 12:12:16.462853 DQ Delay:
2981 12:12:16.465948 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =111
2982 12:12:16.469640 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2983 12:12:16.472929 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2984 12:12:16.476283 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =115
2985 12:12:16.479437
2986 12:12:16.479517
2987 12:12:16.479582 ==
2988 12:12:16.482749 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 12:12:16.485905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 12:12:16.485987 ==
2991 12:12:16.486050
2992 12:12:16.486110
2993 12:12:16.489520 TX Vref Scan disable
2994 12:12:16.489601 == TX Byte 0 ==
2995 12:12:16.496868 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2996 12:12:16.499682 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2997 12:12:16.499764 == TX Byte 1 ==
2998 12:12:16.505946 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2999 12:12:16.509133 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3000 12:12:16.509216 ==
3001 12:12:16.512842 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 12:12:16.515798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 12:12:16.515880 ==
3004 12:12:16.528418 TX Vref=22, minBit 2, minWin=25, winSum=417
3005 12:12:16.532302 TX Vref=24, minBit 13, minWin=25, winSum=422
3006 12:12:16.535617 TX Vref=26, minBit 3, minWin=26, winSum=427
3007 12:12:16.538625 TX Vref=28, minBit 2, minWin=26, winSum=428
3008 12:12:16.541932 TX Vref=30, minBit 2, minWin=26, winSum=433
3009 12:12:16.545080 TX Vref=32, minBit 5, minWin=26, winSum=432
3010 12:12:16.551881 [TxChooseVref] Worse bit 2, Min win 26, Win sum 433, Final Vref 30
3011 12:12:16.551980
3012 12:12:16.555227 Final TX Range 1 Vref 30
3013 12:12:16.555334
3014 12:12:16.555451 ==
3015 12:12:16.558434 Dram Type= 6, Freq= 0, CH_0, rank 1
3016 12:12:16.562040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3017 12:12:16.562126 ==
3018 12:12:16.565522
3019 12:12:16.565602
3020 12:12:16.565666 TX Vref Scan disable
3021 12:12:16.568930 == TX Byte 0 ==
3022 12:12:16.572013 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3023 12:12:16.575391 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3024 12:12:16.578724 == TX Byte 1 ==
3025 12:12:16.581515 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3026 12:12:16.588245 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3027 12:12:16.588328
3028 12:12:16.588393 [DATLAT]
3029 12:12:16.588452 Freq=1200, CH0 RK1
3030 12:12:16.588512
3031 12:12:16.591453 DATLAT Default: 0xd
3032 12:12:16.591533 0, 0xFFFF, sum = 0
3033 12:12:16.594697 1, 0xFFFF, sum = 0
3034 12:12:16.594779 2, 0xFFFF, sum = 0
3035 12:12:16.598542 3, 0xFFFF, sum = 0
3036 12:12:16.601378 4, 0xFFFF, sum = 0
3037 12:12:16.601459 5, 0xFFFF, sum = 0
3038 12:12:16.604711 6, 0xFFFF, sum = 0
3039 12:12:16.604793 7, 0xFFFF, sum = 0
3040 12:12:16.608549 8, 0xFFFF, sum = 0
3041 12:12:16.608632 9, 0xFFFF, sum = 0
3042 12:12:16.611962 10, 0xFFFF, sum = 0
3043 12:12:16.612046 11, 0xFFFF, sum = 0
3044 12:12:16.614969 12, 0x0, sum = 1
3045 12:12:16.615051 13, 0x0, sum = 2
3046 12:12:16.618103 14, 0x0, sum = 3
3047 12:12:16.618186 15, 0x0, sum = 4
3048 12:12:16.621533 best_step = 13
3049 12:12:16.621675
3050 12:12:16.621751 ==
3051 12:12:16.625051 Dram Type= 6, Freq= 0, CH_0, rank 1
3052 12:12:16.627870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3053 12:12:16.627952 ==
3054 12:12:16.628017 RX Vref Scan: 0
3055 12:12:16.628077
3056 12:12:16.631565 RX Vref 0 -> 0, step: 1
3057 12:12:16.631646
3058 12:12:16.634790 RX Delay -21 -> 252, step: 4
3059 12:12:16.641285 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
3060 12:12:16.644282 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3061 12:12:16.647754 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3062 12:12:16.650832 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3063 12:12:16.654495 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3064 12:12:16.660811 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3065 12:12:16.664563 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3066 12:12:16.667807 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3067 12:12:16.670799 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3068 12:12:16.674112 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3069 12:12:16.677927 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3070 12:12:16.684611 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3071 12:12:16.687964 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3072 12:12:16.691417 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3073 12:12:16.694663 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3074 12:12:16.701084 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3075 12:12:16.701169 ==
3076 12:12:16.704902 Dram Type= 6, Freq= 0, CH_0, rank 1
3077 12:12:16.707842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 12:12:16.707927 ==
3079 12:12:16.707991 DQS Delay:
3080 12:12:16.710848 DQS0 = 0, DQS1 = 0
3081 12:12:16.710929 DQM Delay:
3082 12:12:16.714831 DQM0 = 116, DQM1 = 106
3083 12:12:16.714912 DQ Delay:
3084 12:12:16.717937 DQ0 =112, DQ1 =116, DQ2 =112, DQ3 =112
3085 12:12:16.721062 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122
3086 12:12:16.724541 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102
3087 12:12:16.727493 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =112
3088 12:12:16.727576
3089 12:12:16.727639
3090 12:12:16.737409 [DQSOSCAuto] RK1, (LSB)MR18= 0xf9f7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
3091 12:12:16.740835 CH0 RK1: MR19=303, MR18=F9F7
3092 12:12:16.744333 CH0_RK1: MR19=0x303, MR18=0xF9F7, DQSOSC=412, MR23=63, INC=38, DEC=25
3093 12:12:16.747839 [RxdqsGatingPostProcess] freq 1200
3094 12:12:16.754217 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3095 12:12:16.757160 best DQS0 dly(2T, 0.5T) = (0, 11)
3096 12:12:16.760425 best DQS1 dly(2T, 0.5T) = (0, 12)
3097 12:12:16.764022 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3098 12:12:16.767223 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3099 12:12:16.770499 best DQS0 dly(2T, 0.5T) = (0, 11)
3100 12:12:16.773777 best DQS1 dly(2T, 0.5T) = (0, 11)
3101 12:12:16.776939 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3102 12:12:16.780637 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3103 12:12:16.783801 Pre-setting of DQS Precalculation
3104 12:12:16.787529 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3105 12:12:16.787610 ==
3106 12:12:16.791019 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 12:12:16.793956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 12:12:16.794038 ==
3109 12:12:16.800672 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3110 12:12:16.807128 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3111 12:12:16.814829 [CA 0] Center 38 (8~68) winsize 61
3112 12:12:16.818041 [CA 1] Center 37 (7~68) winsize 62
3113 12:12:16.821329 [CA 2] Center 35 (6~65) winsize 60
3114 12:12:16.825086 [CA 3] Center 34 (4~64) winsize 61
3115 12:12:16.828518 [CA 4] Center 34 (4~65) winsize 62
3116 12:12:16.831355 [CA 5] Center 33 (3~63) winsize 61
3117 12:12:16.831474
3118 12:12:16.834922 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3119 12:12:16.835002
3120 12:12:16.838287 [CATrainingPosCal] consider 1 rank data
3121 12:12:16.841398 u2DelayCellTimex100 = 270/100 ps
3122 12:12:16.844640 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3123 12:12:16.851614 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3124 12:12:16.854843 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3125 12:12:16.857936 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3126 12:12:16.861259 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3127 12:12:16.864509 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3128 12:12:16.864590
3129 12:12:16.868040 CA PerBit enable=1, Macro0, CA PI delay=33
3130 12:12:16.868146
3131 12:12:16.871149 [CBTSetCACLKResult] CA Dly = 33
3132 12:12:16.871230 CS Dly: 5 (0~36)
3133 12:12:16.874390 ==
3134 12:12:16.877888 Dram Type= 6, Freq= 0, CH_1, rank 1
3135 12:12:16.881436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 12:12:16.881517 ==
3137 12:12:16.884538 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3138 12:12:16.890917 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3139 12:12:16.901219 [CA 0] Center 37 (7~68) winsize 62
3140 12:12:16.903641 [CA 1] Center 38 (8~68) winsize 61
3141 12:12:16.907000 [CA 2] Center 35 (5~65) winsize 61
3142 12:12:16.910454 [CA 3] Center 34 (4~64) winsize 61
3143 12:12:16.913405 [CA 4] Center 34 (4~64) winsize 61
3144 12:12:16.916907 [CA 5] Center 33 (3~64) winsize 62
3145 12:12:16.916987
3146 12:12:16.920311 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3147 12:12:16.920392
3148 12:12:16.923604 [CATrainingPosCal] consider 2 rank data
3149 12:12:16.927355 u2DelayCellTimex100 = 270/100 ps
3150 12:12:16.930030 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3151 12:12:16.936726 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3152 12:12:16.940044 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3153 12:12:16.943236 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3154 12:12:16.947328 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3155 12:12:16.950216 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3156 12:12:16.950296
3157 12:12:16.953107 CA PerBit enable=1, Macro0, CA PI delay=33
3158 12:12:16.953187
3159 12:12:16.956972 [CBTSetCACLKResult] CA Dly = 33
3160 12:12:16.957053 CS Dly: 6 (0~39)
3161 12:12:16.960028
3162 12:12:16.963223 ----->DramcWriteLeveling(PI) begin...
3163 12:12:16.963330 ==
3164 12:12:16.966569 Dram Type= 6, Freq= 0, CH_1, rank 0
3165 12:12:16.969934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3166 12:12:16.970016 ==
3167 12:12:16.973203 Write leveling (Byte 0): 26 => 26
3168 12:12:16.976423 Write leveling (Byte 1): 27 => 27
3169 12:12:16.979975 DramcWriteLeveling(PI) end<-----
3170 12:12:16.980058
3171 12:12:16.980122 ==
3172 12:12:16.983068 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 12:12:16.986367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 12:12:16.986458 ==
3175 12:12:16.989822 [Gating] SW mode calibration
3176 12:12:16.996575 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3177 12:12:17.003163 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3178 12:12:17.006355 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
3179 12:12:17.009629 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 12:12:17.016532 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 12:12:17.019439 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 12:12:17.022596 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 12:12:17.029327 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 12:12:17.032857 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3185 12:12:17.036018 0 15 28 | B1->B0 | 3232 2828 | 0 0 | (0 0) (1 0)
3186 12:12:17.042633 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3187 12:12:17.046587 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 12:12:17.049196 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 12:12:17.055734 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 12:12:17.059541 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 12:12:17.062958 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 12:12:17.069246 1 0 24 | B1->B0 | 2424 3636 | 1 0 | (0 0) (0 0)
3193 12:12:17.072741 1 0 28 | B1->B0 | 3f3f 4646 | 0 0 | (1 1) (0 0)
3194 12:12:17.076069 1 1 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3195 12:12:17.082433 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 12:12:17.085932 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 12:12:17.089503 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 12:12:17.095641 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 12:12:17.098887 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 12:12:17.102207 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3201 12:12:17.108983 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3202 12:12:17.111957 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3203 12:12:17.115985 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 12:12:17.122288 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 12:12:17.125454 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 12:12:17.128968 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 12:12:17.132609 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 12:12:17.138644 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 12:12:17.141959 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 12:12:17.145320 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 12:12:17.152181 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 12:12:17.155343 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 12:12:17.158836 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 12:12:17.165482 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 12:12:17.168382 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 12:12:17.172127 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3217 12:12:17.178342 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3218 12:12:17.182343 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 12:12:17.185065 Total UI for P1: 0, mck2ui 16
3220 12:12:17.188768 best dqsien dly found for B0: ( 1, 3, 26)
3221 12:12:17.191616 Total UI for P1: 0, mck2ui 16
3222 12:12:17.195043 best dqsien dly found for B1: ( 1, 3, 28)
3223 12:12:17.198232 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3224 12:12:17.201652 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3225 12:12:17.201734
3226 12:12:17.205367 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3227 12:12:17.208090 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3228 12:12:17.211510 [Gating] SW calibration Done
3229 12:12:17.211593 ==
3230 12:12:17.214806 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 12:12:17.221208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 12:12:17.221294 ==
3233 12:12:17.221359 RX Vref Scan: 0
3234 12:12:17.221419
3235 12:12:17.224692 RX Vref 0 -> 0, step: 1
3236 12:12:17.224777
3237 12:12:17.227923 RX Delay -40 -> 252, step: 8
3238 12:12:17.231869 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3239 12:12:17.234770 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3240 12:12:17.237670 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3241 12:12:17.244297 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3242 12:12:17.247733 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3243 12:12:17.251994 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3244 12:12:17.254577 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3245 12:12:17.257592 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3246 12:12:17.264289 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3247 12:12:17.267391 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3248 12:12:17.270867 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3249 12:12:17.274514 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3250 12:12:17.277720 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3251 12:12:17.284440 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3252 12:12:17.287490 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3253 12:12:17.290621 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3254 12:12:17.290709 ==
3255 12:12:17.294101 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 12:12:17.297753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 12:12:17.297837 ==
3258 12:12:17.300604 DQS Delay:
3259 12:12:17.300691 DQS0 = 0, DQS1 = 0
3260 12:12:17.303909 DQM Delay:
3261 12:12:17.303990 DQM0 = 115, DQM1 = 112
3262 12:12:17.307381 DQ Delay:
3263 12:12:17.310615 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3264 12:12:17.313706 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3265 12:12:17.317263 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3266 12:12:17.320294 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3267 12:12:17.320375
3268 12:12:17.320439
3269 12:12:17.320499 ==
3270 12:12:17.323831 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 12:12:17.326984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 12:12:17.327066 ==
3273 12:12:17.327130
3274 12:12:17.327189
3275 12:12:17.330644 TX Vref Scan disable
3276 12:12:17.333594 == TX Byte 0 ==
3277 12:12:17.337448 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3278 12:12:17.340973 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3279 12:12:17.343607 == TX Byte 1 ==
3280 12:12:17.346750 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3281 12:12:17.350294 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3282 12:12:17.350378 ==
3283 12:12:17.354066 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 12:12:17.359984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 12:12:17.360069 ==
3286 12:12:17.370124 TX Vref=22, minBit 9, minWin=24, winSum=407
3287 12:12:17.373512 TX Vref=24, minBit 1, minWin=25, winSum=413
3288 12:12:17.377085 TX Vref=26, minBit 2, minWin=25, winSum=418
3289 12:12:17.380982 TX Vref=28, minBit 3, minWin=26, winSum=424
3290 12:12:17.383552 TX Vref=30, minBit 2, minWin=26, winSum=427
3291 12:12:17.390154 TX Vref=32, minBit 1, minWin=26, winSum=423
3292 12:12:17.393373 [TxChooseVref] Worse bit 2, Min win 26, Win sum 427, Final Vref 30
3293 12:12:17.393463
3294 12:12:17.396696 Final TX Range 1 Vref 30
3295 12:12:17.396796
3296 12:12:17.396861 ==
3297 12:12:17.400153 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 12:12:17.403542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 12:12:17.403631 ==
3300 12:12:17.406914
3301 12:12:17.406995
3302 12:12:17.407059 TX Vref Scan disable
3303 12:12:17.410218 == TX Byte 0 ==
3304 12:12:17.413274 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3305 12:12:17.419880 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3306 12:12:17.419968 == TX Byte 1 ==
3307 12:12:17.423424 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3308 12:12:17.429892 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3309 12:12:17.429985
3310 12:12:17.430072 [DATLAT]
3311 12:12:17.430154 Freq=1200, CH1 RK0
3312 12:12:17.430234
3313 12:12:17.433246 DATLAT Default: 0xd
3314 12:12:17.433332 0, 0xFFFF, sum = 0
3315 12:12:17.436531 1, 0xFFFF, sum = 0
3316 12:12:17.439827 2, 0xFFFF, sum = 0
3317 12:12:17.439914 3, 0xFFFF, sum = 0
3318 12:12:17.443382 4, 0xFFFF, sum = 0
3319 12:12:17.443482 5, 0xFFFF, sum = 0
3320 12:12:17.446578 6, 0xFFFF, sum = 0
3321 12:12:17.446665 7, 0xFFFF, sum = 0
3322 12:12:17.450171 8, 0xFFFF, sum = 0
3323 12:12:17.450261 9, 0xFFFF, sum = 0
3324 12:12:17.453401 10, 0xFFFF, sum = 0
3325 12:12:17.453488 11, 0xFFFF, sum = 0
3326 12:12:17.456314 12, 0x0, sum = 1
3327 12:12:17.456403 13, 0x0, sum = 2
3328 12:12:17.459516 14, 0x0, sum = 3
3329 12:12:17.459602 15, 0x0, sum = 4
3330 12:12:17.463211 best_step = 13
3331 12:12:17.463295
3332 12:12:17.463410 ==
3333 12:12:17.466126 Dram Type= 6, Freq= 0, CH_1, rank 0
3334 12:12:17.469660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3335 12:12:17.469746 ==
3336 12:12:17.469834 RX Vref Scan: 1
3337 12:12:17.473053
3338 12:12:17.473137 Set Vref Range= 32 -> 127
3339 12:12:17.473224
3340 12:12:17.476708 RX Vref 32 -> 127, step: 1
3341 12:12:17.476793
3342 12:12:17.479546 RX Delay -13 -> 252, step: 4
3343 12:12:17.479631
3344 12:12:17.482893 Set Vref, RX VrefLevel [Byte0]: 32
3345 12:12:17.485964 [Byte1]: 32
3346 12:12:17.486050
3347 12:12:17.489658 Set Vref, RX VrefLevel [Byte0]: 33
3348 12:12:17.493277 [Byte1]: 33
3349 12:12:17.496526
3350 12:12:17.496612 Set Vref, RX VrefLevel [Byte0]: 34
3351 12:12:17.499833 [Byte1]: 34
3352 12:12:17.504455
3353 12:12:17.504540 Set Vref, RX VrefLevel [Byte0]: 35
3354 12:12:17.507348 [Byte1]: 35
3355 12:12:17.512211
3356 12:12:17.512298 Set Vref, RX VrefLevel [Byte0]: 36
3357 12:12:17.515714 [Byte1]: 36
3358 12:12:17.519983
3359 12:12:17.520070 Set Vref, RX VrefLevel [Byte0]: 37
3360 12:12:17.523477 [Byte1]: 37
3361 12:12:17.528249
3362 12:12:17.528340 Set Vref, RX VrefLevel [Byte0]: 38
3363 12:12:17.531136 [Byte1]: 38
3364 12:12:17.535974
3365 12:12:17.536064 Set Vref, RX VrefLevel [Byte0]: 39
3366 12:12:17.539216 [Byte1]: 39
3367 12:12:17.543929
3368 12:12:17.544008 Set Vref, RX VrefLevel [Byte0]: 40
3369 12:12:17.546842 [Byte1]: 40
3370 12:12:17.551315
3371 12:12:17.551458 Set Vref, RX VrefLevel [Byte0]: 41
3372 12:12:17.554740 [Byte1]: 41
3373 12:12:17.559515
3374 12:12:17.559596 Set Vref, RX VrefLevel [Byte0]: 42
3375 12:12:17.562677 [Byte1]: 42
3376 12:12:17.567294
3377 12:12:17.567449 Set Vref, RX VrefLevel [Byte0]: 43
3378 12:12:17.570496 [Byte1]: 43
3379 12:12:17.575072
3380 12:12:17.575152 Set Vref, RX VrefLevel [Byte0]: 44
3381 12:12:17.578789 [Byte1]: 44
3382 12:12:17.583231
3383 12:12:17.583335 Set Vref, RX VrefLevel [Byte0]: 45
3384 12:12:17.586313 [Byte1]: 45
3385 12:12:17.590976
3386 12:12:17.591088 Set Vref, RX VrefLevel [Byte0]: 46
3387 12:12:17.594537 [Byte1]: 46
3388 12:12:17.598809
3389 12:12:17.598889 Set Vref, RX VrefLevel [Byte0]: 47
3390 12:12:17.602283 [Byte1]: 47
3391 12:12:17.606708
3392 12:12:17.606788 Set Vref, RX VrefLevel [Byte0]: 48
3393 12:12:17.609874 [Byte1]: 48
3394 12:12:17.614484
3395 12:12:17.614564 Set Vref, RX VrefLevel [Byte0]: 49
3396 12:12:17.618254 [Byte1]: 49
3397 12:12:17.622611
3398 12:12:17.622691 Set Vref, RX VrefLevel [Byte0]: 50
3399 12:12:17.625576 [Byte1]: 50
3400 12:12:17.630176
3401 12:12:17.630257 Set Vref, RX VrefLevel [Byte0]: 51
3402 12:12:17.633552 [Byte1]: 51
3403 12:12:17.638390
3404 12:12:17.638497 Set Vref, RX VrefLevel [Byte0]: 52
3405 12:12:17.641664 [Byte1]: 52
3406 12:12:17.646097
3407 12:12:17.646177 Set Vref, RX VrefLevel [Byte0]: 53
3408 12:12:17.649301 [Byte1]: 53
3409 12:12:17.654126
3410 12:12:17.654207 Set Vref, RX VrefLevel [Byte0]: 54
3411 12:12:17.657417 [Byte1]: 54
3412 12:12:17.661747
3413 12:12:17.661827 Set Vref, RX VrefLevel [Byte0]: 55
3414 12:12:17.664932 [Byte1]: 55
3415 12:12:17.669808
3416 12:12:17.669892 Set Vref, RX VrefLevel [Byte0]: 56
3417 12:12:17.673179 [Byte1]: 56
3418 12:12:17.677608
3419 12:12:17.677690 Set Vref, RX VrefLevel [Byte0]: 57
3420 12:12:17.680881 [Byte1]: 57
3421 12:12:17.685460
3422 12:12:17.685544 Set Vref, RX VrefLevel [Byte0]: 58
3423 12:12:17.688543 [Byte1]: 58
3424 12:12:17.693395
3425 12:12:17.693478 Set Vref, RX VrefLevel [Byte0]: 59
3426 12:12:17.696813 [Byte1]: 59
3427 12:12:17.701374
3428 12:12:17.701457 Set Vref, RX VrefLevel [Byte0]: 60
3429 12:12:17.705006 [Byte1]: 60
3430 12:12:17.708915
3431 12:12:17.708996 Set Vref, RX VrefLevel [Byte0]: 61
3432 12:12:17.712726 [Byte1]: 61
3433 12:12:17.717117
3434 12:12:17.717198 Set Vref, RX VrefLevel [Byte0]: 62
3435 12:12:17.720312 [Byte1]: 62
3436 12:12:17.725325
3437 12:12:17.725409 Set Vref, RX VrefLevel [Byte0]: 63
3438 12:12:17.728430 [Byte1]: 63
3439 12:12:17.733086
3440 12:12:17.733167 Set Vref, RX VrefLevel [Byte0]: 64
3441 12:12:17.736284 [Byte1]: 64
3442 12:12:17.741213
3443 12:12:17.741295 Final RX Vref Byte 0 = 52 to rank0
3444 12:12:17.743826 Final RX Vref Byte 1 = 51 to rank0
3445 12:12:17.747523 Final RX Vref Byte 0 = 52 to rank1
3446 12:12:17.750898 Final RX Vref Byte 1 = 51 to rank1==
3447 12:12:17.754620 Dram Type= 6, Freq= 0, CH_1, rank 0
3448 12:12:17.760428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3449 12:12:17.760517 ==
3450 12:12:17.760583 DQS Delay:
3451 12:12:17.760644 DQS0 = 0, DQS1 = 0
3452 12:12:17.763959 DQM Delay:
3453 12:12:17.764040 DQM0 = 114, DQM1 = 112
3454 12:12:17.766931 DQ Delay:
3455 12:12:17.770455 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3456 12:12:17.773730 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3457 12:12:17.777506 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3458 12:12:17.780681 DQ12 =122, DQ13 =120, DQ14 =118, DQ15 =120
3459 12:12:17.780764
3460 12:12:17.780828
3461 12:12:17.790691 [DQSOSCAuto] RK0, (LSB)MR18= 0xf3ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3462 12:12:17.790798 CH1 RK0: MR19=303, MR18=F3FF
3463 12:12:17.796909 CH1_RK0: MR19=0x303, MR18=0xF3FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3464 12:12:17.796994
3465 12:12:17.800160 ----->DramcWriteLeveling(PI) begin...
3466 12:12:17.800242 ==
3467 12:12:17.803880 Dram Type= 6, Freq= 0, CH_1, rank 1
3468 12:12:17.810401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3469 12:12:17.810484 ==
3470 12:12:17.813584 Write leveling (Byte 0): 25 => 25
3471 12:12:17.813666 Write leveling (Byte 1): 29 => 29
3472 12:12:17.816799 DramcWriteLeveling(PI) end<-----
3473 12:12:17.816883
3474 12:12:17.820442 ==
3475 12:12:17.820522 Dram Type= 6, Freq= 0, CH_1, rank 1
3476 12:12:17.826674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3477 12:12:17.826760 ==
3478 12:12:17.830432 [Gating] SW mode calibration
3479 12:12:17.836685 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3480 12:12:17.839991 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3481 12:12:17.846228 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3482 12:12:17.849618 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3483 12:12:17.852988 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 12:12:17.859769 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 12:12:17.862657 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 12:12:17.866086 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3487 12:12:17.873086 0 15 24 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
3488 12:12:17.875888 0 15 28 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
3489 12:12:17.879192 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3490 12:12:17.885848 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3491 12:12:17.889515 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 12:12:17.892947 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 12:12:17.899267 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 12:12:17.902721 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3495 12:12:17.906391 1 0 24 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
3496 12:12:17.912754 1 0 28 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
3497 12:12:17.915938 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3498 12:12:17.919137 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3499 12:12:17.925867 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 12:12:17.929268 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 12:12:17.932592 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 12:12:17.939500 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 12:12:17.942767 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3504 12:12:17.945686 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3505 12:12:17.952409 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3506 12:12:17.955740 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3507 12:12:17.959127 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 12:12:17.965427 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 12:12:17.968816 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 12:12:17.972261 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 12:12:17.978669 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 12:12:17.981900 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 12:12:17.985525 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 12:12:17.991924 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 12:12:17.994948 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 12:12:17.998653 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 12:12:18.005540 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 12:12:18.008508 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3519 12:12:18.011767 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3520 12:12:18.018154 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 12:12:18.018252 Total UI for P1: 0, mck2ui 16
3522 12:12:18.024707 best dqsien dly found for B0: ( 1, 3, 22)
3523 12:12:18.024851 Total UI for P1: 0, mck2ui 16
3524 12:12:18.031209 best dqsien dly found for B1: ( 1, 3, 24)
3525 12:12:18.034548 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3526 12:12:18.038062 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3527 12:12:18.038149
3528 12:12:18.041301 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3529 12:12:18.044812 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3530 12:12:18.047515 [Gating] SW calibration Done
3531 12:12:18.047597 ==
3532 12:12:18.051319 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 12:12:18.054203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 12:12:18.054286 ==
3535 12:12:18.057548 RX Vref Scan: 0
3536 12:12:18.057632
3537 12:12:18.057697 RX Vref 0 -> 0, step: 1
3538 12:12:18.057757
3539 12:12:18.061353 RX Delay -40 -> 252, step: 8
3540 12:12:18.067517 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3541 12:12:18.070766 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3542 12:12:18.074334 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3543 12:12:18.077233 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3544 12:12:18.080775 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3545 12:12:18.087470 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3546 12:12:18.090542 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3547 12:12:18.093997 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3548 12:12:18.097600 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3549 12:12:18.100375 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3550 12:12:18.107299 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3551 12:12:18.110630 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3552 12:12:18.113716 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3553 12:12:18.117115 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3554 12:12:18.120043 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3555 12:12:18.126692 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3556 12:12:18.126804 ==
3557 12:12:18.130266 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 12:12:18.133407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 12:12:18.133491 ==
3560 12:12:18.133557 DQS Delay:
3561 12:12:18.136710 DQS0 = 0, DQS1 = 0
3562 12:12:18.136792 DQM Delay:
3563 12:12:18.139865 DQM0 = 115, DQM1 = 111
3564 12:12:18.139947 DQ Delay:
3565 12:12:18.143400 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3566 12:12:18.146960 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3567 12:12:18.149691 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3568 12:12:18.153107 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3569 12:12:18.156857
3570 12:12:18.156942
3571 12:12:18.157006 ==
3572 12:12:18.159900 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 12:12:18.163200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 12:12:18.163282 ==
3575 12:12:18.163347
3576 12:12:18.163417
3577 12:12:18.166445 TX Vref Scan disable
3578 12:12:18.166537 == TX Byte 0 ==
3579 12:12:18.172862 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3580 12:12:18.176518 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3581 12:12:18.176600 == TX Byte 1 ==
3582 12:12:18.182902 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3583 12:12:18.186088 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3584 12:12:18.186174 ==
3585 12:12:18.189593 Dram Type= 6, Freq= 0, CH_1, rank 1
3586 12:12:18.192651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3587 12:12:18.192734 ==
3588 12:12:18.205982 TX Vref=22, minBit 3, minWin=25, winSum=420
3589 12:12:18.209089 TX Vref=24, minBit 2, minWin=25, winSum=422
3590 12:12:18.211882 TX Vref=26, minBit 2, minWin=26, winSum=429
3591 12:12:18.215276 TX Vref=28, minBit 2, minWin=26, winSum=435
3592 12:12:18.218667 TX Vref=30, minBit 7, minWin=26, winSum=434
3593 12:12:18.225162 TX Vref=32, minBit 13, minWin=26, winSum=434
3594 12:12:18.228366 [TxChooseVref] Worse bit 2, Min win 26, Win sum 435, Final Vref 28
3595 12:12:18.228457
3596 12:12:18.231831 Final TX Range 1 Vref 28
3597 12:12:18.231919
3598 12:12:18.232005 ==
3599 12:12:18.235009 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 12:12:18.238065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 12:12:18.241393 ==
3602 12:12:18.241481
3603 12:12:18.241568
3604 12:12:18.241649 TX Vref Scan disable
3605 12:12:18.245060 == TX Byte 0 ==
3606 12:12:18.248639 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3607 12:12:18.254942 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3608 12:12:18.255030 == TX Byte 1 ==
3609 12:12:18.258178 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3610 12:12:18.265235 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3611 12:12:18.265325
3612 12:12:18.265411 [DATLAT]
3613 12:12:18.265493 Freq=1200, CH1 RK1
3614 12:12:18.265572
3615 12:12:18.268012 DATLAT Default: 0xd
3616 12:12:18.271496 0, 0xFFFF, sum = 0
3617 12:12:18.271583 1, 0xFFFF, sum = 0
3618 12:12:18.274703 2, 0xFFFF, sum = 0
3619 12:12:18.274789 3, 0xFFFF, sum = 0
3620 12:12:18.278578 4, 0xFFFF, sum = 0
3621 12:12:18.278665 5, 0xFFFF, sum = 0
3622 12:12:18.281600 6, 0xFFFF, sum = 0
3623 12:12:18.281686 7, 0xFFFF, sum = 0
3624 12:12:18.285150 8, 0xFFFF, sum = 0
3625 12:12:18.285237 9, 0xFFFF, sum = 0
3626 12:12:18.287865 10, 0xFFFF, sum = 0
3627 12:12:18.287952 11, 0xFFFF, sum = 0
3628 12:12:18.291240 12, 0x0, sum = 1
3629 12:12:18.291327 13, 0x0, sum = 2
3630 12:12:18.294476 14, 0x0, sum = 3
3631 12:12:18.294558 15, 0x0, sum = 4
3632 12:12:18.297786 best_step = 13
3633 12:12:18.297865
3634 12:12:18.297929 ==
3635 12:12:18.301134 Dram Type= 6, Freq= 0, CH_1, rank 1
3636 12:12:18.304516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3637 12:12:18.304598 ==
3638 12:12:18.307550 RX Vref Scan: 0
3639 12:12:18.307631
3640 12:12:18.307695 RX Vref 0 -> 0, step: 1
3641 12:12:18.307754
3642 12:12:18.310820 RX Delay -13 -> 252, step: 4
3643 12:12:18.318035 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3644 12:12:18.320757 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3645 12:12:18.324204 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3646 12:12:18.327614 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3647 12:12:18.330650 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3648 12:12:18.337291 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3649 12:12:18.340770 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3650 12:12:18.343813 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3651 12:12:18.347354 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3652 12:12:18.353459 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3653 12:12:18.357116 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3654 12:12:18.360117 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3655 12:12:18.363247 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3656 12:12:18.366956 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3657 12:12:18.373630 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3658 12:12:18.377007 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3659 12:12:18.377112 ==
3660 12:12:18.380154 Dram Type= 6, Freq= 0, CH_1, rank 1
3661 12:12:18.383409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3662 12:12:18.383520 ==
3663 12:12:18.386777 DQS Delay:
3664 12:12:18.386861 DQS0 = 0, DQS1 = 0
3665 12:12:18.389929 DQM Delay:
3666 12:12:18.390012 DQM0 = 115, DQM1 = 112
3667 12:12:18.390098 DQ Delay:
3668 12:12:18.393434 DQ0 =116, DQ1 =112, DQ2 =108, DQ3 =114
3669 12:12:18.399938 DQ4 =112, DQ5 =124, DQ6 =122, DQ7 =112
3670 12:12:18.403059 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3671 12:12:18.406273 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =120
3672 12:12:18.406360
3673 12:12:18.406445
3674 12:12:18.413162 [DQSOSCAuto] RK1, (LSB)MR18= 0xf305, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
3675 12:12:18.416218 CH1 RK1: MR19=304, MR18=F305
3676 12:12:18.422665 CH1_RK1: MR19=0x304, MR18=0xF305, DQSOSC=408, MR23=63, INC=39, DEC=26
3677 12:12:18.426115 [RxdqsGatingPostProcess] freq 1200
3678 12:12:18.432836 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3679 12:12:18.432975 best DQS0 dly(2T, 0.5T) = (0, 11)
3680 12:12:18.436158 best DQS1 dly(2T, 0.5T) = (0, 11)
3681 12:12:18.440131 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3682 12:12:18.442523 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3683 12:12:18.445955 best DQS0 dly(2T, 0.5T) = (0, 11)
3684 12:12:18.449644 best DQS1 dly(2T, 0.5T) = (0, 11)
3685 12:12:18.452529 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3686 12:12:18.455786 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3687 12:12:18.459278 Pre-setting of DQS Precalculation
3688 12:12:18.465836 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3689 12:12:18.472393 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3690 12:12:18.479315 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3691 12:12:18.479441
3692 12:12:18.479507
3693 12:12:18.482177 [Calibration Summary] 2400 Mbps
3694 12:12:18.482257 CH 0, Rank 0
3695 12:12:18.486300 SW Impedance : PASS
3696 12:12:18.489306 DUTY Scan : NO K
3697 12:12:18.489386 ZQ Calibration : PASS
3698 12:12:18.492300 Jitter Meter : NO K
3699 12:12:18.495221 CBT Training : PASS
3700 12:12:18.495302 Write leveling : PASS
3701 12:12:18.499012 RX DQS gating : PASS
3702 12:12:18.502105 RX DQ/DQS(RDDQC) : PASS
3703 12:12:18.502186 TX DQ/DQS : PASS
3704 12:12:18.505218 RX DATLAT : PASS
3705 12:12:18.508831 RX DQ/DQS(Engine): PASS
3706 12:12:18.508911 TX OE : NO K
3707 12:12:18.512125 All Pass.
3708 12:12:18.512205
3709 12:12:18.512269 CH 0, Rank 1
3710 12:12:18.515481 SW Impedance : PASS
3711 12:12:18.515561 DUTY Scan : NO K
3712 12:12:18.518653 ZQ Calibration : PASS
3713 12:12:18.522125 Jitter Meter : NO K
3714 12:12:18.522204 CBT Training : PASS
3715 12:12:18.524916 Write leveling : PASS
3716 12:12:18.524996 RX DQS gating : PASS
3717 12:12:18.528543 RX DQ/DQS(RDDQC) : PASS
3718 12:12:18.531518 TX DQ/DQS : PASS
3719 12:12:18.531602 RX DATLAT : PASS
3720 12:12:18.534861 RX DQ/DQS(Engine): PASS
3721 12:12:18.538157 TX OE : NO K
3722 12:12:18.538239 All Pass.
3723 12:12:18.538303
3724 12:12:18.538362 CH 1, Rank 0
3725 12:12:18.541448 SW Impedance : PASS
3726 12:12:18.544767 DUTY Scan : NO K
3727 12:12:18.544885 ZQ Calibration : PASS
3728 12:12:18.548129 Jitter Meter : NO K
3729 12:12:18.551957 CBT Training : PASS
3730 12:12:18.552040 Write leveling : PASS
3731 12:12:18.554655 RX DQS gating : PASS
3732 12:12:18.557944 RX DQ/DQS(RDDQC) : PASS
3733 12:12:18.558026 TX DQ/DQS : PASS
3734 12:12:18.561366 RX DATLAT : PASS
3735 12:12:18.564530 RX DQ/DQS(Engine): PASS
3736 12:12:18.564611 TX OE : NO K
3737 12:12:18.568213 All Pass.
3738 12:12:18.568295
3739 12:12:18.568360 CH 1, Rank 1
3740 12:12:18.571004 SW Impedance : PASS
3741 12:12:18.571085 DUTY Scan : NO K
3742 12:12:18.574577 ZQ Calibration : PASS
3743 12:12:18.577898 Jitter Meter : NO K
3744 12:12:18.577980 CBT Training : PASS
3745 12:12:18.581092 Write leveling : PASS
3746 12:12:18.584432 RX DQS gating : PASS
3747 12:12:18.584514 RX DQ/DQS(RDDQC) : PASS
3748 12:12:18.587774 TX DQ/DQS : PASS
3749 12:12:18.591155 RX DATLAT : PASS
3750 12:12:18.591236 RX DQ/DQS(Engine): PASS
3751 12:12:18.594266 TX OE : NO K
3752 12:12:18.594347 All Pass.
3753 12:12:18.594412
3754 12:12:18.597529 DramC Write-DBI off
3755 12:12:18.600781 PER_BANK_REFRESH: Hybrid Mode
3756 12:12:18.600863 TX_TRACKING: ON
3757 12:12:18.610881 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3758 12:12:18.613877 [FAST_K] Save calibration result to emmc
3759 12:12:18.617146 dramc_set_vcore_voltage set vcore to 650000
3760 12:12:18.620654 Read voltage for 600, 5
3761 12:12:18.620736 Vio18 = 0
3762 12:12:18.620801 Vcore = 650000
3763 12:12:18.624100 Vdram = 0
3764 12:12:18.624182 Vddq = 0
3765 12:12:18.624247 Vmddr = 0
3766 12:12:18.630596 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3767 12:12:18.633667 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3768 12:12:18.637205 MEM_TYPE=3, freq_sel=19
3769 12:12:18.640622 sv_algorithm_assistance_LP4_1600
3770 12:12:18.643421 ============ PULL DRAM RESETB DOWN ============
3771 12:12:18.646639 ========== PULL DRAM RESETB DOWN end =========
3772 12:12:18.653337 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3773 12:12:18.656867 ===================================
3774 12:12:18.660704 LPDDR4 DRAM CONFIGURATION
3775 12:12:18.663198 ===================================
3776 12:12:18.663284 EX_ROW_EN[0] = 0x0
3777 12:12:18.666452 EX_ROW_EN[1] = 0x0
3778 12:12:18.666538 LP4Y_EN = 0x0
3779 12:12:18.669935 WORK_FSP = 0x0
3780 12:12:18.670021 WL = 0x2
3781 12:12:18.674019 RL = 0x2
3782 12:12:18.674104 BL = 0x2
3783 12:12:18.676663 RPST = 0x0
3784 12:12:18.676747 RD_PRE = 0x0
3785 12:12:18.680106 WR_PRE = 0x1
3786 12:12:18.683105 WR_PST = 0x0
3787 12:12:18.683190 DBI_WR = 0x0
3788 12:12:18.686502 DBI_RD = 0x0
3789 12:12:18.686587 OTF = 0x1
3790 12:12:18.689803 ===================================
3791 12:12:18.693188 ===================================
3792 12:12:18.693274 ANA top config
3793 12:12:18.696362 ===================================
3794 12:12:18.699653 DLL_ASYNC_EN = 0
3795 12:12:18.703358 ALL_SLAVE_EN = 1
3796 12:12:18.705977 NEW_RANK_MODE = 1
3797 12:12:18.709688 DLL_IDLE_MODE = 1
3798 12:12:18.709774 LP45_APHY_COMB_EN = 1
3799 12:12:18.712491 TX_ODT_DIS = 1
3800 12:12:18.715828 NEW_8X_MODE = 1
3801 12:12:18.719305 ===================================
3802 12:12:18.722780 ===================================
3803 12:12:18.725993 data_rate = 1200
3804 12:12:18.728868 CKR = 1
3805 12:12:18.732103 DQ_P2S_RATIO = 8
3806 12:12:18.736019 ===================================
3807 12:12:18.736101 CA_P2S_RATIO = 8
3808 12:12:18.739102 DQ_CA_OPEN = 0
3809 12:12:18.742381 DQ_SEMI_OPEN = 0
3810 12:12:18.745509 CA_SEMI_OPEN = 0
3811 12:12:18.748480 CA_FULL_RATE = 0
3812 12:12:18.751948 DQ_CKDIV4_EN = 1
3813 12:12:18.752050 CA_CKDIV4_EN = 1
3814 12:12:18.755312 CA_PREDIV_EN = 0
3815 12:12:18.758744 PH8_DLY = 0
3816 12:12:18.762238 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3817 12:12:18.765173 DQ_AAMCK_DIV = 4
3818 12:12:18.768635 CA_AAMCK_DIV = 4
3819 12:12:18.768720 CA_ADMCK_DIV = 4
3820 12:12:18.772270 DQ_TRACK_CA_EN = 0
3821 12:12:18.775314 CA_PICK = 600
3822 12:12:18.778586 CA_MCKIO = 600
3823 12:12:18.781736 MCKIO_SEMI = 0
3824 12:12:18.784836 PLL_FREQ = 2288
3825 12:12:18.788289 DQ_UI_PI_RATIO = 32
3826 12:12:18.791565 CA_UI_PI_RATIO = 0
3827 12:12:18.795277 ===================================
3828 12:12:18.798010 ===================================
3829 12:12:18.798094 memory_type:LPDDR4
3830 12:12:18.801533 GP_NUM : 10
3831 12:12:18.805117 SRAM_EN : 1
3832 12:12:18.805241 MD32_EN : 0
3833 12:12:18.807959 ===================================
3834 12:12:18.811230 [ANA_INIT] >>>>>>>>>>>>>>
3835 12:12:18.814627 <<<<<< [CONFIGURE PHASE]: ANA_TX
3836 12:12:18.818123 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3837 12:12:18.821260 ===================================
3838 12:12:18.824396 data_rate = 1200,PCW = 0X5800
3839 12:12:18.828076 ===================================
3840 12:12:18.831128 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3841 12:12:18.834206 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3842 12:12:18.841161 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3843 12:12:18.844192 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3844 12:12:18.847664 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3845 12:12:18.851306 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3846 12:12:18.854244 [ANA_INIT] flow start
3847 12:12:18.857652 [ANA_INIT] PLL >>>>>>>>
3848 12:12:18.857739 [ANA_INIT] PLL <<<<<<<<
3849 12:12:18.860785 [ANA_INIT] MIDPI >>>>>>>>
3850 12:12:18.864235 [ANA_INIT] MIDPI <<<<<<<<
3851 12:12:18.867057 [ANA_INIT] DLL >>>>>>>>
3852 12:12:18.867143 [ANA_INIT] flow end
3853 12:12:18.870651 ============ LP4 DIFF to SE enter ============
3854 12:12:18.877226 ============ LP4 DIFF to SE exit ============
3855 12:12:18.877312 [ANA_INIT] <<<<<<<<<<<<<
3856 12:12:18.880488 [Flow] Enable top DCM control >>>>>
3857 12:12:18.884422 [Flow] Enable top DCM control <<<<<
3858 12:12:18.887198 Enable DLL master slave shuffle
3859 12:12:18.893554 ==============================================================
3860 12:12:18.897168 Gating Mode config
3861 12:12:18.900056 ==============================================================
3862 12:12:18.903414 Config description:
3863 12:12:18.913402 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3864 12:12:18.920173 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3865 12:12:18.923369 SELPH_MODE 0: By rank 1: By Phase
3866 12:12:18.929601 ==============================================================
3867 12:12:18.933204 GAT_TRACK_EN = 1
3868 12:12:18.936267 RX_GATING_MODE = 2
3869 12:12:18.940198 RX_GATING_TRACK_MODE = 2
3870 12:12:18.942947 SELPH_MODE = 1
3871 12:12:18.943028 PICG_EARLY_EN = 1
3872 12:12:18.946300 VALID_LAT_VALUE = 1
3873 12:12:18.952697 ==============================================================
3874 12:12:18.956245 Enter into Gating configuration >>>>
3875 12:12:18.959117 Exit from Gating configuration <<<<
3876 12:12:18.962544 Enter into DVFS_PRE_config >>>>>
3877 12:12:18.972353 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3878 12:12:18.975815 Exit from DVFS_PRE_config <<<<<
3879 12:12:18.979401 Enter into PICG configuration >>>>
3880 12:12:18.982648 Exit from PICG configuration <<<<
3881 12:12:18.986032 [RX_INPUT] configuration >>>>>
3882 12:12:18.988964 [RX_INPUT] configuration <<<<<
3883 12:12:18.995685 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3884 12:12:18.998991 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3885 12:12:19.005327 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3886 12:12:19.011938 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3887 12:12:19.018587 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3888 12:12:19.025246 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3889 12:12:19.028721 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3890 12:12:19.032009 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3891 12:12:19.034706 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3892 12:12:19.041342 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3893 12:12:19.044673 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3894 12:12:19.048163 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3895 12:12:19.051816 ===================================
3896 12:12:19.054891 LPDDR4 DRAM CONFIGURATION
3897 12:12:19.058192 ===================================
3898 12:12:19.061829 EX_ROW_EN[0] = 0x0
3899 12:12:19.061912 EX_ROW_EN[1] = 0x0
3900 12:12:19.064965 LP4Y_EN = 0x0
3901 12:12:19.065048 WORK_FSP = 0x0
3902 12:12:19.068017 WL = 0x2
3903 12:12:19.068100 RL = 0x2
3904 12:12:19.071335 BL = 0x2
3905 12:12:19.071456 RPST = 0x0
3906 12:12:19.074325 RD_PRE = 0x0
3907 12:12:19.074411 WR_PRE = 0x1
3908 12:12:19.077608 WR_PST = 0x0
3909 12:12:19.077691 DBI_WR = 0x0
3910 12:12:19.081014 DBI_RD = 0x0
3911 12:12:19.081095 OTF = 0x1
3912 12:12:19.084732 ===================================
3913 12:12:19.090818 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3914 12:12:19.094349 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3915 12:12:19.098016 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3916 12:12:19.101088 ===================================
3917 12:12:19.103888 LPDDR4 DRAM CONFIGURATION
3918 12:12:19.107151 ===================================
3919 12:12:19.110431 EX_ROW_EN[0] = 0x10
3920 12:12:19.110513 EX_ROW_EN[1] = 0x0
3921 12:12:19.114062 LP4Y_EN = 0x0
3922 12:12:19.114143 WORK_FSP = 0x0
3923 12:12:19.117453 WL = 0x2
3924 12:12:19.117534 RL = 0x2
3925 12:12:19.120798 BL = 0x2
3926 12:12:19.120879 RPST = 0x0
3927 12:12:19.123928 RD_PRE = 0x0
3928 12:12:19.124009 WR_PRE = 0x1
3929 12:12:19.127141 WR_PST = 0x0
3930 12:12:19.127262 DBI_WR = 0x0
3931 12:12:19.130604 DBI_RD = 0x0
3932 12:12:19.130685 OTF = 0x1
3933 12:12:19.133768 ===================================
3934 12:12:19.140246 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3935 12:12:19.145191 nWR fixed to 30
3936 12:12:19.148690 [ModeRegInit_LP4] CH0 RK0
3937 12:12:19.148771 [ModeRegInit_LP4] CH0 RK1
3938 12:12:19.151979 [ModeRegInit_LP4] CH1 RK0
3939 12:12:19.155603 [ModeRegInit_LP4] CH1 RK1
3940 12:12:19.155685 match AC timing 17
3941 12:12:19.161839 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3942 12:12:19.164977 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3943 12:12:19.168429 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3944 12:12:19.174973 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3945 12:12:19.178021 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3946 12:12:19.178104 ==
3947 12:12:19.181521 Dram Type= 6, Freq= 0, CH_0, rank 0
3948 12:12:19.184636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3949 12:12:19.184718 ==
3950 12:12:19.191116 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3951 12:12:19.198072 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3952 12:12:19.201513 [CA 0] Center 36 (6~67) winsize 62
3953 12:12:19.204366 [CA 1] Center 36 (5~67) winsize 63
3954 12:12:19.207849 [CA 2] Center 34 (4~65) winsize 62
3955 12:12:19.211137 [CA 3] Center 34 (4~65) winsize 62
3956 12:12:19.214309 [CA 4] Center 33 (3~64) winsize 62
3957 12:12:19.217540 [CA 5] Center 33 (3~64) winsize 62
3958 12:12:19.217621
3959 12:12:19.220966 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3960 12:12:19.221047
3961 12:12:19.224738 [CATrainingPosCal] consider 1 rank data
3962 12:12:19.227567 u2DelayCellTimex100 = 270/100 ps
3963 12:12:19.231103 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3964 12:12:19.234416 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3965 12:12:19.237591 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3966 12:12:19.244080 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3967 12:12:19.247140 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3968 12:12:19.250616 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3969 12:12:19.250698
3970 12:12:19.254167 CA PerBit enable=1, Macro0, CA PI delay=33
3971 12:12:19.254249
3972 12:12:19.257037 [CBTSetCACLKResult] CA Dly = 33
3973 12:12:19.257118 CS Dly: 5 (0~36)
3974 12:12:19.257183 ==
3975 12:12:19.260933 Dram Type= 6, Freq= 0, CH_0, rank 1
3976 12:12:19.267042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3977 12:12:19.267125 ==
3978 12:12:19.270215 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3979 12:12:19.276701 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3980 12:12:19.280598 [CA 0] Center 36 (6~67) winsize 62
3981 12:12:19.284024 [CA 1] Center 36 (6~67) winsize 62
3982 12:12:19.287500 [CA 2] Center 34 (4~65) winsize 62
3983 12:12:19.290463 [CA 3] Center 34 (4~65) winsize 62
3984 12:12:19.294070 [CA 4] Center 33 (3~64) winsize 62
3985 12:12:19.297378 [CA 5] Center 33 (3~64) winsize 62
3986 12:12:19.297460
3987 12:12:19.300645 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3988 12:12:19.300728
3989 12:12:19.303652 [CATrainingPosCal] consider 2 rank data
3990 12:12:19.307409 u2DelayCellTimex100 = 270/100 ps
3991 12:12:19.310582 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3992 12:12:19.316868 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3993 12:12:19.320334 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3994 12:12:19.323453 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3995 12:12:19.326927 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3996 12:12:19.330311 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3997 12:12:19.330395
3998 12:12:19.333487 CA PerBit enable=1, Macro0, CA PI delay=33
3999 12:12:19.333569
4000 12:12:19.336997 [CBTSetCACLKResult] CA Dly = 33
4001 12:12:19.340230 CS Dly: 5 (0~37)
4002 12:12:19.340312
4003 12:12:19.343305 ----->DramcWriteLeveling(PI) begin...
4004 12:12:19.343449 ==
4005 12:12:19.346428 Dram Type= 6, Freq= 0, CH_0, rank 0
4006 12:12:19.350195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 12:12:19.350279 ==
4008 12:12:19.353114 Write leveling (Byte 0): 34 => 34
4009 12:12:19.356898 Write leveling (Byte 1): 29 => 29
4010 12:12:19.359876 DramcWriteLeveling(PI) end<-----
4011 12:12:19.359959
4012 12:12:19.360024 ==
4013 12:12:19.363157 Dram Type= 6, Freq= 0, CH_0, rank 0
4014 12:12:19.366082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4015 12:12:19.366165 ==
4016 12:12:19.369512 [Gating] SW mode calibration
4017 12:12:19.375949 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4018 12:12:19.382892 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4019 12:12:19.385943 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4020 12:12:19.389191 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4021 12:12:19.396167 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4022 12:12:19.399012 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4023 12:12:19.402317 0 9 16 | B1->B0 | 2f2f 2929 | 0 0 | (1 0) (1 1)
4024 12:12:19.409075 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4025 12:12:19.412477 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4026 12:12:19.415540 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4027 12:12:19.422127 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 12:12:19.425611 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 12:12:19.428898 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 12:12:19.435518 0 10 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4031 12:12:19.439301 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4032 12:12:19.442052 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4033 12:12:19.449001 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4034 12:12:19.451720 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4035 12:12:19.455617 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 12:12:19.462341 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 12:12:19.465350 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 12:12:19.468612 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 12:12:19.475095 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 12:12:19.478323 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4041 12:12:19.484579 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4042 12:12:19.488151 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4043 12:12:19.492131 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 12:12:19.497713 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 12:12:19.501375 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 12:12:19.504655 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 12:12:19.507810 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 12:12:19.514403 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 12:12:19.517733 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 12:12:19.524454 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 12:12:19.527949 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 12:12:19.531181 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 12:12:19.534145 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 12:12:19.541581 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 12:12:19.544586 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4056 12:12:19.547607 Total UI for P1: 0, mck2ui 16
4057 12:12:19.550946 best dqsien dly found for B0: ( 0, 13, 14)
4058 12:12:19.554112 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 12:12:19.557471 Total UI for P1: 0, mck2ui 16
4060 12:12:19.561212 best dqsien dly found for B1: ( 0, 13, 16)
4061 12:12:19.567633 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4062 12:12:19.571066 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4063 12:12:19.571152
4064 12:12:19.574267 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4065 12:12:19.577026 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4066 12:12:19.580521 [Gating] SW calibration Done
4067 12:12:19.580604 ==
4068 12:12:19.583651 Dram Type= 6, Freq= 0, CH_0, rank 0
4069 12:12:19.587312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4070 12:12:19.587440 ==
4071 12:12:19.590480 RX Vref Scan: 0
4072 12:12:19.590563
4073 12:12:19.590627 RX Vref 0 -> 0, step: 1
4074 12:12:19.590688
4075 12:12:19.594704 RX Delay -230 -> 252, step: 16
4076 12:12:19.600105 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4077 12:12:19.603263 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4078 12:12:19.607586 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4079 12:12:19.610246 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4080 12:12:19.613128 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4081 12:12:19.619972 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4082 12:12:19.623700 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4083 12:12:19.626347 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4084 12:12:19.629617 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4085 12:12:19.636011 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4086 12:12:19.639602 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4087 12:12:19.642797 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4088 12:12:19.646111 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4089 12:12:19.652957 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4090 12:12:19.656344 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4091 12:12:19.659622 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4092 12:12:19.659707 ==
4093 12:12:19.662618 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 12:12:19.665986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 12:12:19.669527 ==
4096 12:12:19.669611 DQS Delay:
4097 12:12:19.669677 DQS0 = 0, DQS1 = 0
4098 12:12:19.672612 DQM Delay:
4099 12:12:19.672695 DQM0 = 42, DQM1 = 35
4100 12:12:19.675893 DQ Delay:
4101 12:12:19.679555 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4102 12:12:19.679640 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4103 12:12:19.682258 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4104 12:12:19.685704 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4105 12:12:19.689091
4106 12:12:19.689173
4107 12:12:19.689238 ==
4108 12:12:19.692057 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 12:12:19.695671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 12:12:19.695758 ==
4111 12:12:19.695824
4112 12:12:19.695884
4113 12:12:19.699331 TX Vref Scan disable
4114 12:12:19.699466 == TX Byte 0 ==
4115 12:12:19.705971 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4116 12:12:19.708728 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4117 12:12:19.708812 == TX Byte 1 ==
4118 12:12:19.715744 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4119 12:12:19.718796 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4120 12:12:19.718878 ==
4121 12:12:19.722483 Dram Type= 6, Freq= 0, CH_0, rank 0
4122 12:12:19.725441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4123 12:12:19.725524 ==
4124 12:12:19.725589
4125 12:12:19.728659
4126 12:12:19.728742 TX Vref Scan disable
4127 12:12:19.732138 == TX Byte 0 ==
4128 12:12:19.735570 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4129 12:12:19.741922 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4130 12:12:19.742007 == TX Byte 1 ==
4131 12:12:19.746106 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4132 12:12:19.752298 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4133 12:12:19.752383
4134 12:12:19.752449 [DATLAT]
4135 12:12:19.752510 Freq=600, CH0 RK0
4136 12:12:19.752569
4137 12:12:19.755384 DATLAT Default: 0x9
4138 12:12:19.755494 0, 0xFFFF, sum = 0
4139 12:12:19.758694 1, 0xFFFF, sum = 0
4140 12:12:19.761904 2, 0xFFFF, sum = 0
4141 12:12:19.761987 3, 0xFFFF, sum = 0
4142 12:12:19.765399 4, 0xFFFF, sum = 0
4143 12:12:19.765483 5, 0xFFFF, sum = 0
4144 12:12:19.768479 6, 0xFFFF, sum = 0
4145 12:12:19.768562 7, 0xFFFF, sum = 0
4146 12:12:19.771377 8, 0x0, sum = 1
4147 12:12:19.771462 9, 0x0, sum = 2
4148 12:12:19.775092 10, 0x0, sum = 3
4149 12:12:19.775175 11, 0x0, sum = 4
4150 12:12:19.775241 best_step = 9
4151 12:12:19.775301
4152 12:12:19.778403 ==
4153 12:12:19.781623 Dram Type= 6, Freq= 0, CH_0, rank 0
4154 12:12:19.784739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 12:12:19.784826 ==
4156 12:12:19.784892 RX Vref Scan: 1
4157 12:12:19.784953
4158 12:12:19.788170 RX Vref 0 -> 0, step: 1
4159 12:12:19.788295
4160 12:12:19.791586 RX Delay -195 -> 252, step: 8
4161 12:12:19.791714
4162 12:12:19.794993 Set Vref, RX VrefLevel [Byte0]: 54
4163 12:12:19.798204 [Byte1]: 59
4164 12:12:19.798318
4165 12:12:19.802210 Final RX Vref Byte 0 = 54 to rank0
4166 12:12:19.804736 Final RX Vref Byte 1 = 59 to rank0
4167 12:12:19.807873 Final RX Vref Byte 0 = 54 to rank1
4168 12:12:19.812331 Final RX Vref Byte 1 = 59 to rank1==
4169 12:12:19.814270 Dram Type= 6, Freq= 0, CH_0, rank 0
4170 12:12:19.821128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 12:12:19.821237 ==
4172 12:12:19.821304 DQS Delay:
4173 12:12:19.821363 DQS0 = 0, DQS1 = 0
4174 12:12:19.824218 DQM Delay:
4175 12:12:19.824299 DQM0 = 41, DQM1 = 33
4176 12:12:19.827478 DQ Delay:
4177 12:12:19.830860 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4178 12:12:19.834746 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =44
4179 12:12:19.837379 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4180 12:12:19.840508 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4181 12:12:19.840590
4182 12:12:19.840654
4183 12:12:19.847141 [DQSOSCAuto] RK0, (LSB)MR18= 0x463d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
4184 12:12:19.850819 CH0 RK0: MR19=808, MR18=463D
4185 12:12:19.857244 CH0_RK0: MR19=0x808, MR18=0x463D, DQSOSC=396, MR23=63, INC=167, DEC=111
4186 12:12:19.857327
4187 12:12:19.860358 ----->DramcWriteLeveling(PI) begin...
4188 12:12:19.860441 ==
4189 12:12:19.863912 Dram Type= 6, Freq= 0, CH_0, rank 1
4190 12:12:19.867135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 12:12:19.867217 ==
4192 12:12:19.870275 Write leveling (Byte 0): 35 => 35
4193 12:12:19.873559 Write leveling (Byte 1): 31 => 31
4194 12:12:19.876952 DramcWriteLeveling(PI) end<-----
4195 12:12:19.877032
4196 12:12:19.877095 ==
4197 12:12:19.880086 Dram Type= 6, Freq= 0, CH_0, rank 1
4198 12:12:19.883238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4199 12:12:19.886914 ==
4200 12:12:19.886994 [Gating] SW mode calibration
4201 12:12:19.897263 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4202 12:12:19.899941 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4203 12:12:19.903102 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4204 12:12:19.909526 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4205 12:12:19.912791 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4206 12:12:19.916235 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4207 12:12:19.923022 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
4208 12:12:19.926037 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4209 12:12:19.929620 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4210 12:12:19.936184 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4211 12:12:19.939520 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 12:12:19.942917 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 12:12:19.949163 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 12:12:19.952299 0 10 12 | B1->B0 | 2424 3737 | 0 0 | (0 0) (0 0)
4215 12:12:19.955863 0 10 16 | B1->B0 | 3a3a 4444 | 1 0 | (0 0) (0 0)
4216 12:12:19.962548 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4217 12:12:19.965592 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4218 12:12:19.968881 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 12:12:19.975581 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 12:12:19.978845 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 12:12:19.982526 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 12:12:19.988727 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4223 12:12:19.991675 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4224 12:12:19.998562 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4225 12:12:20.002425 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4226 12:12:20.005203 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 12:12:20.012085 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 12:12:20.015181 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 12:12:20.018608 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 12:12:20.025402 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 12:12:20.028042 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 12:12:20.032079 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 12:12:20.037931 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 12:12:20.041787 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 12:12:20.044732 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 12:12:20.051179 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 12:12:20.054196 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 12:12:20.057521 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4239 12:12:20.060850 Total UI for P1: 0, mck2ui 16
4240 12:12:20.064869 best dqsien dly found for B0: ( 0, 13, 10)
4241 12:12:20.071377 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4242 12:12:20.074435 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 12:12:20.077856 Total UI for P1: 0, mck2ui 16
4244 12:12:20.080798 best dqsien dly found for B1: ( 0, 13, 14)
4245 12:12:20.084489 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4246 12:12:20.087399 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4247 12:12:20.087507
4248 12:12:20.090421 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4249 12:12:20.093675 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4250 12:12:20.097446 [Gating] SW calibration Done
4251 12:12:20.097529 ==
4252 12:12:20.100524 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 12:12:20.107020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 12:12:20.107115 ==
4255 12:12:20.107193 RX Vref Scan: 0
4256 12:12:20.107256
4257 12:12:20.110149 RX Vref 0 -> 0, step: 1
4258 12:12:20.110231
4259 12:12:20.113531 RX Delay -230 -> 252, step: 16
4260 12:12:20.117113 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4261 12:12:20.120285 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4262 12:12:20.123298 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4263 12:12:20.129876 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4264 12:12:20.132990 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4265 12:12:20.136286 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4266 12:12:20.139726 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4267 12:12:20.146358 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4268 12:12:20.149788 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4269 12:12:20.152938 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4270 12:12:20.157122 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4271 12:12:20.163104 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4272 12:12:20.166963 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4273 12:12:20.169943 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4274 12:12:20.173089 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4275 12:12:20.179212 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4276 12:12:20.179296 ==
4277 12:12:20.182648 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 12:12:20.186149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 12:12:20.186232 ==
4280 12:12:20.186298 DQS Delay:
4281 12:12:20.189456 DQS0 = 0, DQS1 = 0
4282 12:12:20.189539 DQM Delay:
4283 12:12:20.192865 DQM0 = 41, DQM1 = 33
4284 12:12:20.192947 DQ Delay:
4285 12:12:20.195863 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4286 12:12:20.199209 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4287 12:12:20.202593 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4288 12:12:20.206169 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4289 12:12:20.206252
4290 12:12:20.206317
4291 12:12:20.206377 ==
4292 12:12:20.208890 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 12:12:20.212390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 12:12:20.212473 ==
4295 12:12:20.215824
4296 12:12:20.215906
4297 12:12:20.215971 TX Vref Scan disable
4298 12:12:20.218777 == TX Byte 0 ==
4299 12:12:20.222144 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4300 12:12:20.225877 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4301 12:12:20.228601 == TX Byte 1 ==
4302 12:12:20.232176 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4303 12:12:20.235216 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4304 12:12:20.238529 ==
4305 12:12:20.242004 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 12:12:20.245265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 12:12:20.245348 ==
4308 12:12:20.245446
4309 12:12:20.245506
4310 12:12:20.249532 TX Vref Scan disable
4311 12:12:20.251808 == TX Byte 0 ==
4312 12:12:20.254894 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4313 12:12:20.257958 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4314 12:12:20.261283 == TX Byte 1 ==
4315 12:12:20.264992 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4316 12:12:20.268353 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4317 12:12:20.268436
4318 12:12:20.268501 [DATLAT]
4319 12:12:20.271344 Freq=600, CH0 RK1
4320 12:12:20.271451
4321 12:12:20.275014 DATLAT Default: 0x9
4322 12:12:20.275096 0, 0xFFFF, sum = 0
4323 12:12:20.278279 1, 0xFFFF, sum = 0
4324 12:12:20.278362 2, 0xFFFF, sum = 0
4325 12:12:20.281814 3, 0xFFFF, sum = 0
4326 12:12:20.281898 4, 0xFFFF, sum = 0
4327 12:12:20.284570 5, 0xFFFF, sum = 0
4328 12:12:20.284653 6, 0xFFFF, sum = 0
4329 12:12:20.287685 7, 0xFFFF, sum = 0
4330 12:12:20.287768 8, 0x0, sum = 1
4331 12:12:20.291600 9, 0x0, sum = 2
4332 12:12:20.291683 10, 0x0, sum = 3
4333 12:12:20.294520 11, 0x0, sum = 4
4334 12:12:20.294603 best_step = 9
4335 12:12:20.294667
4336 12:12:20.294727 ==
4337 12:12:20.297978 Dram Type= 6, Freq= 0, CH_0, rank 1
4338 12:12:20.301124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 12:12:20.301245 ==
4340 12:12:20.304343 RX Vref Scan: 0
4341 12:12:20.304427
4342 12:12:20.307421 RX Vref 0 -> 0, step: 1
4343 12:12:20.307507
4344 12:12:20.307593 RX Delay -195 -> 252, step: 8
4345 12:12:20.315354 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4346 12:12:20.318994 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4347 12:12:20.322399 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4348 12:12:20.325505 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4349 12:12:20.332350 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4350 12:12:20.336047 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4351 12:12:20.338671 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4352 12:12:20.342013 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4353 12:12:20.348458 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4354 12:12:20.351670 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4355 12:12:20.354991 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4356 12:12:20.358512 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4357 12:12:20.364809 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4358 12:12:20.368456 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4359 12:12:20.371511 iDelay=205, Bit 14, Center 48 (-107 ~ 204) 312
4360 12:12:20.374967 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4361 12:12:20.375052 ==
4362 12:12:20.378352 Dram Type= 6, Freq= 0, CH_0, rank 1
4363 12:12:20.384731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 12:12:20.384813 ==
4365 12:12:20.384877 DQS Delay:
4366 12:12:20.387860 DQS0 = 0, DQS1 = 0
4367 12:12:20.387940 DQM Delay:
4368 12:12:20.388004 DQM0 = 42, DQM1 = 34
4369 12:12:20.391310 DQ Delay:
4370 12:12:20.394473 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4371 12:12:20.398507 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4372 12:12:20.401334 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4373 12:12:20.404393 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =40
4374 12:12:20.404474
4375 12:12:20.404538
4376 12:12:20.411124 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b36, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
4377 12:12:20.414382 CH0 RK1: MR19=808, MR18=3B36
4378 12:12:20.421294 CH0_RK1: MR19=0x808, MR18=0x3B36, DQSOSC=398, MR23=63, INC=165, DEC=110
4379 12:12:20.425163 [RxdqsGatingPostProcess] freq 600
4380 12:12:20.427934 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4381 12:12:20.431144 Pre-setting of DQS Precalculation
4382 12:12:20.438017 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4383 12:12:20.438114 ==
4384 12:12:20.441037 Dram Type= 6, Freq= 0, CH_1, rank 0
4385 12:12:20.444149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4386 12:12:20.444230 ==
4387 12:12:20.450487 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4388 12:12:20.457019 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4389 12:12:20.460656 [CA 0] Center 36 (6~66) winsize 61
4390 12:12:20.464893 [CA 1] Center 35 (5~66) winsize 62
4391 12:12:20.466955 [CA 2] Center 34 (4~65) winsize 62
4392 12:12:20.471268 [CA 3] Center 33 (3~64) winsize 62
4393 12:12:20.473992 [CA 4] Center 34 (4~65) winsize 62
4394 12:12:20.476956 [CA 5] Center 33 (3~64) winsize 62
4395 12:12:20.477037
4396 12:12:20.480646 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4397 12:12:20.480727
4398 12:12:20.483554 [CATrainingPosCal] consider 1 rank data
4399 12:12:20.487657 u2DelayCellTimex100 = 270/100 ps
4400 12:12:20.490056 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4401 12:12:20.493460 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4402 12:12:20.497431 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4403 12:12:20.500467 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4404 12:12:20.503433 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4405 12:12:20.509808 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4406 12:12:20.509889
4407 12:12:20.513045 CA PerBit enable=1, Macro0, CA PI delay=33
4408 12:12:20.513126
4409 12:12:20.516627 [CBTSetCACLKResult] CA Dly = 33
4410 12:12:20.516708 CS Dly: 4 (0~35)
4411 12:12:20.516772 ==
4412 12:12:20.519686 Dram Type= 6, Freq= 0, CH_1, rank 1
4413 12:12:20.523484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 12:12:20.526497 ==
4415 12:12:20.529701 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4416 12:12:20.536486 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4417 12:12:20.539492 [CA 0] Center 35 (5~66) winsize 62
4418 12:12:20.542731 [CA 1] Center 35 (5~66) winsize 62
4419 12:12:20.546144 [CA 2] Center 34 (4~65) winsize 62
4420 12:12:20.550118 [CA 3] Center 34 (3~65) winsize 63
4421 12:12:20.552957 [CA 4] Center 34 (4~64) winsize 61
4422 12:12:20.556268 [CA 5] Center 33 (3~64) winsize 62
4423 12:12:20.556349
4424 12:12:20.559965 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4425 12:12:20.560048
4426 12:12:20.562945 [CATrainingPosCal] consider 2 rank data
4427 12:12:20.566014 u2DelayCellTimex100 = 270/100 ps
4428 12:12:20.569145 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4429 12:12:20.573187 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4430 12:12:20.579401 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4431 12:12:20.582379 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4432 12:12:20.585630 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4433 12:12:20.589174 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4434 12:12:20.589259
4435 12:12:20.592279 CA PerBit enable=1, Macro0, CA PI delay=33
4436 12:12:20.592383
4437 12:12:20.595841 [CBTSetCACLKResult] CA Dly = 33
4438 12:12:20.595923 CS Dly: 4 (0~36)
4439 12:12:20.595991
4440 12:12:20.599290 ----->DramcWriteLeveling(PI) begin...
4441 12:12:20.602405 ==
4442 12:12:20.605447 Dram Type= 6, Freq= 0, CH_1, rank 0
4443 12:12:20.608776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4444 12:12:20.608860 ==
4445 12:12:20.612342 Write leveling (Byte 0): 30 => 30
4446 12:12:20.615828 Write leveling (Byte 1): 30 => 30
4447 12:12:20.618614 DramcWriteLeveling(PI) end<-----
4448 12:12:20.618698
4449 12:12:20.618762 ==
4450 12:12:20.622207 Dram Type= 6, Freq= 0, CH_1, rank 0
4451 12:12:20.625479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 12:12:20.625561 ==
4453 12:12:20.629166 [Gating] SW mode calibration
4454 12:12:20.635564 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4455 12:12:20.642043 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4456 12:12:20.645269 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4457 12:12:20.648476 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4458 12:12:20.654970 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4459 12:12:20.658781 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 1) (1 1)
4460 12:12:20.661622 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4461 12:12:20.668301 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4462 12:12:20.671483 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 12:12:20.674826 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 12:12:20.681740 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 12:12:20.684590 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 12:12:20.688054 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4467 12:12:20.694697 0 10 12 | B1->B0 | 3434 3a3a | 0 0 | (0 0) (1 1)
4468 12:12:20.697948 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4469 12:12:20.701531 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4470 12:12:20.707969 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 12:12:20.711220 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 12:12:20.714262 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 12:12:20.720842 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 12:12:20.724016 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 12:12:20.728284 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4476 12:12:20.734340 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4477 12:12:20.737533 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 12:12:20.740463 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 12:12:20.747095 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 12:12:20.750536 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 12:12:20.753644 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 12:12:20.760010 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 12:12:20.763354 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 12:12:20.766712 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 12:12:20.773259 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 12:12:20.776624 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 12:12:20.779649 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 12:12:20.786899 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 12:12:20.789714 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 12:12:20.792943 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 12:12:20.799482 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4492 12:12:20.802803 Total UI for P1: 0, mck2ui 16
4493 12:12:20.806362 best dqsien dly found for B0: ( 0, 13, 10)
4494 12:12:20.809623 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 12:12:20.813238 Total UI for P1: 0, mck2ui 16
4496 12:12:20.816203 best dqsien dly found for B1: ( 0, 13, 12)
4497 12:12:20.819580 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4498 12:12:20.822640 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4499 12:12:20.822719
4500 12:12:20.826001 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4501 12:12:20.832878 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4502 12:12:20.832962 [Gating] SW calibration Done
4503 12:12:20.833026 ==
4504 12:12:20.835714 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 12:12:20.842455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 12:12:20.842546 ==
4507 12:12:20.842611 RX Vref Scan: 0
4508 12:12:20.842670
4509 12:12:20.845791 RX Vref 0 -> 0, step: 1
4510 12:12:20.845871
4511 12:12:20.849201 RX Delay -230 -> 252, step: 16
4512 12:12:20.852216 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4513 12:12:20.855795 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4514 12:12:20.862167 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4515 12:12:20.865453 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4516 12:12:20.868826 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4517 12:12:20.872587 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4518 12:12:20.875782 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4519 12:12:20.881766 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4520 12:12:20.885426 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4521 12:12:20.888719 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4522 12:12:20.891745 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4523 12:12:20.898755 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4524 12:12:20.902366 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4525 12:12:20.904996 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4526 12:12:20.908220 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4527 12:12:20.914699 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4528 12:12:20.914781 ==
4529 12:12:20.918002 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 12:12:20.921710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 12:12:20.921791 ==
4532 12:12:20.921854 DQS Delay:
4533 12:12:20.924793 DQS0 = 0, DQS1 = 0
4534 12:12:20.924873 DQM Delay:
4535 12:12:20.928019 DQM0 = 43, DQM1 = 39
4536 12:12:20.928099 DQ Delay:
4537 12:12:20.932098 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4538 12:12:20.934569 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4539 12:12:20.937509 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4540 12:12:20.941362 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4541 12:12:20.941442
4542 12:12:20.941505
4543 12:12:20.941564 ==
4544 12:12:20.944105 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 12:12:20.950640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 12:12:20.950722 ==
4547 12:12:20.950786
4548 12:12:20.950845
4549 12:12:20.950901 TX Vref Scan disable
4550 12:12:20.954407 == TX Byte 0 ==
4551 12:12:20.957789 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4552 12:12:20.964629 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4553 12:12:20.964709 == TX Byte 1 ==
4554 12:12:20.967829 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4555 12:12:20.974164 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4556 12:12:20.974244 ==
4557 12:12:20.977847 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 12:12:20.980837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 12:12:20.980923 ==
4560 12:12:20.980986
4561 12:12:20.981045
4562 12:12:20.984203 TX Vref Scan disable
4563 12:12:20.987090 == TX Byte 0 ==
4564 12:12:20.990654 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4565 12:12:20.993983 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4566 12:12:20.997351 == TX Byte 1 ==
4567 12:12:21.000409 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4568 12:12:21.003694 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4569 12:12:21.003774
4570 12:12:21.007511 [DATLAT]
4571 12:12:21.007591 Freq=600, CH1 RK0
4572 12:12:21.007655
4573 12:12:21.010591 DATLAT Default: 0x9
4574 12:12:21.010671 0, 0xFFFF, sum = 0
4575 12:12:21.013525 1, 0xFFFF, sum = 0
4576 12:12:21.013607 2, 0xFFFF, sum = 0
4577 12:12:21.016922 3, 0xFFFF, sum = 0
4578 12:12:21.017004 4, 0xFFFF, sum = 0
4579 12:12:21.020424 5, 0xFFFF, sum = 0
4580 12:12:21.020505 6, 0xFFFF, sum = 0
4581 12:12:21.023564 7, 0xFFFF, sum = 0
4582 12:12:21.023645 8, 0x0, sum = 1
4583 12:12:21.026555 9, 0x0, sum = 2
4584 12:12:21.026637 10, 0x0, sum = 3
4585 12:12:21.030066 11, 0x0, sum = 4
4586 12:12:21.030148 best_step = 9
4587 12:12:21.030212
4588 12:12:21.030271 ==
4589 12:12:21.033223 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 12:12:21.036690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 12:12:21.040367 ==
4592 12:12:21.040448 RX Vref Scan: 1
4593 12:12:21.040512
4594 12:12:21.043031 RX Vref 0 -> 0, step: 1
4595 12:12:21.043113
4596 12:12:21.046377 RX Delay -179 -> 252, step: 8
4597 12:12:21.046460
4598 12:12:21.049635 Set Vref, RX VrefLevel [Byte0]: 52
4599 12:12:21.052766 [Byte1]: 51
4600 12:12:21.052855
4601 12:12:21.056095 Final RX Vref Byte 0 = 52 to rank0
4602 12:12:21.059574 Final RX Vref Byte 1 = 51 to rank0
4603 12:12:21.062974 Final RX Vref Byte 0 = 52 to rank1
4604 12:12:21.066170 Final RX Vref Byte 1 = 51 to rank1==
4605 12:12:21.069715 Dram Type= 6, Freq= 0, CH_1, rank 0
4606 12:12:21.072683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4607 12:12:21.072765 ==
4608 12:12:21.075913 DQS Delay:
4609 12:12:21.075995 DQS0 = 0, DQS1 = 0
4610 12:12:21.076061 DQM Delay:
4611 12:12:21.079176 DQM0 = 42, DQM1 = 35
4612 12:12:21.079258 DQ Delay:
4613 12:12:21.082555 DQ0 =52, DQ1 =40, DQ2 =32, DQ3 =40
4614 12:12:21.085714 DQ4 =36, DQ5 =48, DQ6 =56, DQ7 =36
4615 12:12:21.088920 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4616 12:12:21.092267 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4617 12:12:21.092349
4618 12:12:21.092414
4619 12:12:21.101927 [DQSOSCAuto] RK0, (LSB)MR18= 0x2944, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
4620 12:12:21.105384 CH1 RK0: MR19=808, MR18=2944
4621 12:12:21.111707 CH1_RK0: MR19=0x808, MR18=0x2944, DQSOSC=396, MR23=63, INC=167, DEC=111
4622 12:12:21.111789
4623 12:12:21.115577 ----->DramcWriteLeveling(PI) begin...
4624 12:12:21.115661 ==
4625 12:12:21.118197 Dram Type= 6, Freq= 0, CH_1, rank 1
4626 12:12:21.121600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4627 12:12:21.121684 ==
4628 12:12:21.124895 Write leveling (Byte 0): 32 => 32
4629 12:12:21.128445 Write leveling (Byte 1): 29 => 29
4630 12:12:21.131688 DramcWriteLeveling(PI) end<-----
4631 12:12:21.131772
4632 12:12:21.131837 ==
4633 12:12:21.134613 Dram Type= 6, Freq= 0, CH_1, rank 1
4634 12:12:21.138181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4635 12:12:21.138265 ==
4636 12:12:21.141395 [Gating] SW mode calibration
4637 12:12:21.148125 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4638 12:12:21.154719 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4639 12:12:21.158534 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4640 12:12:21.161743 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4641 12:12:21.167979 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4642 12:12:21.171043 0 9 12 | B1->B0 | 3131 2e2e | 1 1 | (1 0) (1 0)
4643 12:12:21.174695 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4644 12:12:21.180785 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 12:12:21.184399 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 12:12:21.191350 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 12:12:21.194233 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 12:12:21.197630 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 12:12:21.204068 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4650 12:12:21.207436 0 10 12 | B1->B0 | 3131 4444 | 0 0 | (0 0) (0 0)
4651 12:12:21.210566 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4652 12:12:21.217936 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 12:12:21.220490 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 12:12:21.223751 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 12:12:21.230600 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 12:12:21.234056 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 12:12:21.237620 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 12:12:21.244458 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4659 12:12:21.247147 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4660 12:12:21.249690 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 12:12:21.256604 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 12:12:21.259906 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 12:12:21.263651 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 12:12:21.269488 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 12:12:21.272784 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 12:12:21.275828 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 12:12:21.282366 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 12:12:21.285866 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 12:12:21.289192 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 12:12:21.295899 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 12:12:21.299279 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 12:12:21.302536 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 12:12:21.309058 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4674 12:12:21.312137 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4675 12:12:21.315871 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 12:12:21.318869 Total UI for P1: 0, mck2ui 16
4677 12:12:21.322476 best dqsien dly found for B0: ( 0, 13, 10)
4678 12:12:21.325640 Total UI for P1: 0, mck2ui 16
4679 12:12:21.328810 best dqsien dly found for B1: ( 0, 13, 12)
4680 12:12:21.332066 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4681 12:12:21.335340 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4682 12:12:21.335491
4683 12:12:21.342159 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4684 12:12:21.345243 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4685 12:12:21.348442 [Gating] SW calibration Done
4686 12:12:21.348543 ==
4687 12:12:21.352596 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 12:12:21.355189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 12:12:21.355278 ==
4690 12:12:21.355343 RX Vref Scan: 0
4691 12:12:21.355450
4692 12:12:21.358254 RX Vref 0 -> 0, step: 1
4693 12:12:21.358338
4694 12:12:21.361884 RX Delay -230 -> 252, step: 16
4695 12:12:21.364822 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4696 12:12:21.372228 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4697 12:12:21.375540 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4698 12:12:21.378809 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4699 12:12:21.381434 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4700 12:12:21.385166 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4701 12:12:21.391496 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4702 12:12:21.394552 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4703 12:12:21.397889 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4704 12:12:21.401481 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4705 12:12:21.408351 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4706 12:12:21.411453 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4707 12:12:21.414615 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4708 12:12:21.417906 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4709 12:12:21.425225 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4710 12:12:21.427613 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4711 12:12:21.427800 ==
4712 12:12:21.430775 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 12:12:21.434476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 12:12:21.434666 ==
4715 12:12:21.437787 DQS Delay:
4716 12:12:21.437974 DQS0 = 0, DQS1 = 0
4717 12:12:21.438123 DQM Delay:
4718 12:12:21.440811 DQM0 = 42, DQM1 = 39
4719 12:12:21.440998 DQ Delay:
4720 12:12:21.443843 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4721 12:12:21.448187 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4722 12:12:21.450858 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4723 12:12:21.454114 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4724 12:12:21.454387
4725 12:12:21.454604
4726 12:12:21.457427 ==
4727 12:12:21.457723 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 12:12:21.464462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 12:12:21.464737 ==
4730 12:12:21.464953
4731 12:12:21.465198
4732 12:12:21.467207 TX Vref Scan disable
4733 12:12:21.467507 == TX Byte 0 ==
4734 12:12:21.473612 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4735 12:12:21.477202 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4736 12:12:21.477412 == TX Byte 1 ==
4737 12:12:21.483424 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4738 12:12:21.486904 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4739 12:12:21.487048 ==
4740 12:12:21.489815 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 12:12:21.493456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 12:12:21.493582 ==
4743 12:12:21.493739
4744 12:12:21.493837
4745 12:12:21.496533 TX Vref Scan disable
4746 12:12:21.500073 == TX Byte 0 ==
4747 12:12:21.503156 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4748 12:12:21.506396 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4749 12:12:21.509794 == TX Byte 1 ==
4750 12:12:21.512705 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4751 12:12:21.516566 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4752 12:12:21.519812
4753 12:12:21.519892 [DATLAT]
4754 12:12:21.519956 Freq=600, CH1 RK1
4755 12:12:21.520016
4756 12:12:21.522729 DATLAT Default: 0x9
4757 12:12:21.522809 0, 0xFFFF, sum = 0
4758 12:12:21.526248 1, 0xFFFF, sum = 0
4759 12:12:21.526330 2, 0xFFFF, sum = 0
4760 12:12:21.529588 3, 0xFFFF, sum = 0
4761 12:12:21.533126 4, 0xFFFF, sum = 0
4762 12:12:21.533209 5, 0xFFFF, sum = 0
4763 12:12:21.536444 6, 0xFFFF, sum = 0
4764 12:12:21.536525 7, 0xFFFF, sum = 0
4765 12:12:21.539214 8, 0x0, sum = 1
4766 12:12:21.539322 9, 0x0, sum = 2
4767 12:12:21.539440 10, 0x0, sum = 3
4768 12:12:21.542353 11, 0x0, sum = 4
4769 12:12:21.542434 best_step = 9
4770 12:12:21.542499
4771 12:12:21.542559 ==
4772 12:12:21.545914 Dram Type= 6, Freq= 0, CH_1, rank 1
4773 12:12:21.552324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4774 12:12:21.552405 ==
4775 12:12:21.552469 RX Vref Scan: 0
4776 12:12:21.552528
4777 12:12:21.555612 RX Vref 0 -> 0, step: 1
4778 12:12:21.555694
4779 12:12:21.559149 RX Delay -179 -> 252, step: 8
4780 12:12:21.565372 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4781 12:12:21.568642 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4782 12:12:21.571955 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4783 12:12:21.575248 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4784 12:12:21.579259 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4785 12:12:21.585529 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4786 12:12:21.588467 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4787 12:12:21.592103 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4788 12:12:21.595057 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4789 12:12:21.602019 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4790 12:12:21.605081 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4791 12:12:21.608170 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4792 12:12:21.611710 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4793 12:12:21.618131 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4794 12:12:21.621545 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4795 12:12:21.624988 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4796 12:12:21.625069 ==
4797 12:12:21.628581 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 12:12:21.631452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 12:12:21.634451 ==
4800 12:12:21.634607 DQS Delay:
4801 12:12:21.634752 DQS0 = 0, DQS1 = 0
4802 12:12:21.637950 DQM Delay:
4803 12:12:21.638102 DQM0 = 38, DQM1 = 34
4804 12:12:21.641704 DQ Delay:
4805 12:12:21.641857 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4806 12:12:21.644906 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4807 12:12:21.647947 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4808 12:12:21.651043 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4809 12:12:21.654655
4810 12:12:21.654805
4811 12:12:21.661177 [DQSOSCAuto] RK1, (LSB)MR18= 0x3055, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4812 12:12:21.664229 CH1 RK1: MR19=808, MR18=3055
4813 12:12:21.670982 CH1_RK1: MR19=0x808, MR18=0x3055, DQSOSC=393, MR23=63, INC=169, DEC=113
4814 12:12:21.674212 [RxdqsGatingPostProcess] freq 600
4815 12:12:21.678080 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4816 12:12:21.680642 Pre-setting of DQS Precalculation
4817 12:12:21.687169 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4818 12:12:21.693883 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4819 12:12:21.700404 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4820 12:12:21.700562
4821 12:12:21.700702
4822 12:12:21.703999 [Calibration Summary] 1200 Mbps
4823 12:12:21.704149 CH 0, Rank 0
4824 12:12:21.706792 SW Impedance : PASS
4825 12:12:21.710156 DUTY Scan : NO K
4826 12:12:21.710316 ZQ Calibration : PASS
4827 12:12:21.713690 Jitter Meter : NO K
4828 12:12:21.717034 CBT Training : PASS
4829 12:12:21.717187 Write leveling : PASS
4830 12:12:21.720329 RX DQS gating : PASS
4831 12:12:21.723918 RX DQ/DQS(RDDQC) : PASS
4832 12:12:21.724070 TX DQ/DQS : PASS
4833 12:12:21.727133 RX DATLAT : PASS
4834 12:12:21.730130 RX DQ/DQS(Engine): PASS
4835 12:12:21.730284 TX OE : NO K
4836 12:12:21.733610 All Pass.
4837 12:12:21.733763
4838 12:12:21.733905 CH 0, Rank 1
4839 12:12:21.736964 SW Impedance : PASS
4840 12:12:21.737115 DUTY Scan : NO K
4841 12:12:21.739936 ZQ Calibration : PASS
4842 12:12:21.743325 Jitter Meter : NO K
4843 12:12:21.743515 CBT Training : PASS
4844 12:12:21.746903 Write leveling : PASS
4845 12:12:21.749880 RX DQS gating : PASS
4846 12:12:21.750032 RX DQ/DQS(RDDQC) : PASS
4847 12:12:21.753665 TX DQ/DQS : PASS
4848 12:12:21.756721 RX DATLAT : PASS
4849 12:12:21.756872 RX DQ/DQS(Engine): PASS
4850 12:12:21.759854 TX OE : NO K
4851 12:12:21.760008 All Pass.
4852 12:12:21.760145
4853 12:12:21.760283 CH 1, Rank 0
4854 12:12:21.762927 SW Impedance : PASS
4855 12:12:21.766263 DUTY Scan : NO K
4856 12:12:21.766412 ZQ Calibration : PASS
4857 12:12:21.769946 Jitter Meter : NO K
4858 12:12:21.773212 CBT Training : PASS
4859 12:12:21.773364 Write leveling : PASS
4860 12:12:21.776126 RX DQS gating : PASS
4861 12:12:21.779492 RX DQ/DQS(RDDQC) : PASS
4862 12:12:21.779623 TX DQ/DQS : PASS
4863 12:12:21.783295 RX DATLAT : PASS
4864 12:12:21.785942 RX DQ/DQS(Engine): PASS
4865 12:12:21.786099 TX OE : NO K
4866 12:12:21.789514 All Pass.
4867 12:12:21.789669
4868 12:12:21.789811 CH 1, Rank 1
4869 12:12:21.792707 SW Impedance : PASS
4870 12:12:21.792860 DUTY Scan : NO K
4871 12:12:21.795885 ZQ Calibration : PASS
4872 12:12:21.799620 Jitter Meter : NO K
4873 12:12:21.799775 CBT Training : PASS
4874 12:12:21.802491 Write leveling : PASS
4875 12:12:21.805743 RX DQS gating : PASS
4876 12:12:21.805899 RX DQ/DQS(RDDQC) : PASS
4877 12:12:21.810009 TX DQ/DQS : PASS
4878 12:12:21.812327 RX DATLAT : PASS
4879 12:12:21.812482 RX DQ/DQS(Engine): PASS
4880 12:12:21.815702 TX OE : NO K
4881 12:12:21.815856 All Pass.
4882 12:12:21.815997
4883 12:12:21.819093 DramC Write-DBI off
4884 12:12:21.822056 PER_BANK_REFRESH: Hybrid Mode
4885 12:12:21.822220 TX_TRACKING: ON
4886 12:12:21.831976 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4887 12:12:21.835637 [FAST_K] Save calibration result to emmc
4888 12:12:21.838663 dramc_set_vcore_voltage set vcore to 662500
4889 12:12:21.841659 Read voltage for 933, 3
4890 12:12:21.841816 Vio18 = 0
4891 12:12:21.841959 Vcore = 662500
4892 12:12:21.845332 Vdram = 0
4893 12:12:21.845483 Vddq = 0
4894 12:12:21.845625 Vmddr = 0
4895 12:12:21.851809 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4896 12:12:21.855124 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4897 12:12:21.858227 MEM_TYPE=3, freq_sel=17
4898 12:12:21.861800 sv_algorithm_assistance_LP4_1600
4899 12:12:21.864935 ============ PULL DRAM RESETB DOWN ============
4900 12:12:21.871350 ========== PULL DRAM RESETB DOWN end =========
4901 12:12:21.874814 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4902 12:12:21.878248 ===================================
4903 12:12:21.881102 LPDDR4 DRAM CONFIGURATION
4904 12:12:21.884903 ===================================
4905 12:12:21.885058 EX_ROW_EN[0] = 0x0
4906 12:12:21.887804 EX_ROW_EN[1] = 0x0
4907 12:12:21.887956 LP4Y_EN = 0x0
4908 12:12:21.891217 WORK_FSP = 0x0
4909 12:12:21.891398 WL = 0x3
4910 12:12:21.894598 RL = 0x3
4911 12:12:21.897444 BL = 0x2
4912 12:12:21.897596 RPST = 0x0
4913 12:12:21.900908 RD_PRE = 0x0
4914 12:12:21.901057 WR_PRE = 0x1
4915 12:12:21.904930 WR_PST = 0x0
4916 12:12:21.905080 DBI_WR = 0x0
4917 12:12:21.908008 DBI_RD = 0x0
4918 12:12:21.908160 OTF = 0x1
4919 12:12:21.911233 ===================================
4920 12:12:21.914257 ===================================
4921 12:12:21.917548 ANA top config
4922 12:12:21.921098 ===================================
4923 12:12:21.921252 DLL_ASYNC_EN = 0
4924 12:12:21.924127 ALL_SLAVE_EN = 1
4925 12:12:21.927209 NEW_RANK_MODE = 1
4926 12:12:21.930359 DLL_IDLE_MODE = 1
4927 12:12:21.934307 LP45_APHY_COMB_EN = 1
4928 12:12:21.934460 TX_ODT_DIS = 1
4929 12:12:21.937153 NEW_8X_MODE = 1
4930 12:12:21.940514 ===================================
4931 12:12:21.943651 ===================================
4932 12:12:21.946763 data_rate = 1866
4933 12:12:21.950564 CKR = 1
4934 12:12:21.953285 DQ_P2S_RATIO = 8
4935 12:12:21.956745 ===================================
4936 12:12:21.960558 CA_P2S_RATIO = 8
4937 12:12:21.960719 DQ_CA_OPEN = 0
4938 12:12:21.963397 DQ_SEMI_OPEN = 0
4939 12:12:21.966463 CA_SEMI_OPEN = 0
4940 12:12:21.970387 CA_FULL_RATE = 0
4941 12:12:21.973212 DQ_CKDIV4_EN = 1
4942 12:12:21.976277 CA_CKDIV4_EN = 1
4943 12:12:21.976431 CA_PREDIV_EN = 0
4944 12:12:21.980333 PH8_DLY = 0
4945 12:12:21.982818 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4946 12:12:21.986414 DQ_AAMCK_DIV = 4
4947 12:12:21.989601 CA_AAMCK_DIV = 4
4948 12:12:21.993086 CA_ADMCK_DIV = 4
4949 12:12:21.993242 DQ_TRACK_CA_EN = 0
4950 12:12:21.996035 CA_PICK = 933
4951 12:12:22.000322 CA_MCKIO = 933
4952 12:12:22.002614 MCKIO_SEMI = 0
4953 12:12:22.006180 PLL_FREQ = 3732
4954 12:12:22.009198 DQ_UI_PI_RATIO = 32
4955 12:12:22.012687 CA_UI_PI_RATIO = 0
4956 12:12:22.016203 ===================================
4957 12:12:22.019332 ===================================
4958 12:12:22.019476 memory_type:LPDDR4
4959 12:12:22.022275 GP_NUM : 10
4960 12:12:22.026001 SRAM_EN : 1
4961 12:12:22.026140 MD32_EN : 0
4962 12:12:22.028742 ===================================
4963 12:12:22.032568 [ANA_INIT] >>>>>>>>>>>>>>
4964 12:12:22.035412 <<<<<< [CONFIGURE PHASE]: ANA_TX
4965 12:12:22.038648 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4966 12:12:22.041841 ===================================
4967 12:12:22.045329 data_rate = 1866,PCW = 0X8f00
4968 12:12:22.048281 ===================================
4969 12:12:22.051682 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4970 12:12:22.059045 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4971 12:12:22.061937 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4972 12:12:22.068480 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4973 12:12:22.071358 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4974 12:12:22.074779 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4975 12:12:22.074858 [ANA_INIT] flow start
4976 12:12:22.077883 [ANA_INIT] PLL >>>>>>>>
4977 12:12:22.081421 [ANA_INIT] PLL <<<<<<<<
4978 12:12:22.081500 [ANA_INIT] MIDPI >>>>>>>>
4979 12:12:22.084616 [ANA_INIT] MIDPI <<<<<<<<
4980 12:12:22.087873 [ANA_INIT] DLL >>>>>>>>
4981 12:12:22.087952 [ANA_INIT] flow end
4982 12:12:22.094843 ============ LP4 DIFF to SE enter ============
4983 12:12:22.097557 ============ LP4 DIFF to SE exit ============
4984 12:12:22.101163 [ANA_INIT] <<<<<<<<<<<<<
4985 12:12:22.104233 [Flow] Enable top DCM control >>>>>
4986 12:12:22.107498 [Flow] Enable top DCM control <<<<<
4987 12:12:22.111201 Enable DLL master slave shuffle
4988 12:12:22.114149 ==============================================================
4989 12:12:22.117732 Gating Mode config
4990 12:12:22.120876 ==============================================================
4991 12:12:22.124011 Config description:
4992 12:12:22.133975 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4993 12:12:22.140467 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4994 12:12:22.143909 SELPH_MODE 0: By rank 1: By Phase
4995 12:12:22.150574 ==============================================================
4996 12:12:22.153573 GAT_TRACK_EN = 1
4997 12:12:22.156800 RX_GATING_MODE = 2
4998 12:12:22.160106 RX_GATING_TRACK_MODE = 2
4999 12:12:22.163565 SELPH_MODE = 1
5000 12:12:22.166554 PICG_EARLY_EN = 1
5001 12:12:22.170309 VALID_LAT_VALUE = 1
5002 12:12:22.173176 ==============================================================
5003 12:12:22.176470 Enter into Gating configuration >>>>
5004 12:12:22.179887 Exit from Gating configuration <<<<
5005 12:12:22.183732 Enter into DVFS_PRE_config >>>>>
5006 12:12:22.196235 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5007 12:12:22.200007 Exit from DVFS_PRE_config <<<<<
5008 12:12:22.203210 Enter into PICG configuration >>>>
5009 12:12:22.203404 Exit from PICG configuration <<<<
5010 12:12:22.206362 [RX_INPUT] configuration >>>>>
5011 12:12:22.210269 [RX_INPUT] configuration <<<<<
5012 12:12:22.216997 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5013 12:12:22.219437 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5014 12:12:22.225934 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5015 12:12:22.232603 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5016 12:12:22.239358 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5017 12:12:22.246247 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5018 12:12:22.249508 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5019 12:12:22.252689 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5020 12:12:22.259504 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5021 12:12:22.262604 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5022 12:12:22.265619 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5023 12:12:22.272289 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5024 12:12:22.275865 ===================================
5025 12:12:22.276247 LPDDR4 DRAM CONFIGURATION
5026 12:12:22.279137 ===================================
5027 12:12:22.282556 EX_ROW_EN[0] = 0x0
5028 12:12:22.283010 EX_ROW_EN[1] = 0x0
5029 12:12:22.285548 LP4Y_EN = 0x0
5030 12:12:22.285899 WORK_FSP = 0x0
5031 12:12:22.289180 WL = 0x3
5032 12:12:22.292565 RL = 0x3
5033 12:12:22.292995 BL = 0x2
5034 12:12:22.295536 RPST = 0x0
5035 12:12:22.295887 RD_PRE = 0x0
5036 12:12:22.298901 WR_PRE = 0x1
5037 12:12:22.299390 WR_PST = 0x0
5038 12:12:22.302741 DBI_WR = 0x0
5039 12:12:22.303222 DBI_RD = 0x0
5040 12:12:22.305209 OTF = 0x1
5041 12:12:22.308639 ===================================
5042 12:12:22.312327 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5043 12:12:22.315533 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5044 12:12:22.321968 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5045 12:12:22.324969 ===================================
5046 12:12:22.325370 LPDDR4 DRAM CONFIGURATION
5047 12:12:22.328501 ===================================
5048 12:12:22.331702 EX_ROW_EN[0] = 0x10
5049 12:12:22.334966 EX_ROW_EN[1] = 0x0
5050 12:12:22.335412 LP4Y_EN = 0x0
5051 12:12:22.338227 WORK_FSP = 0x0
5052 12:12:22.338603 WL = 0x3
5053 12:12:22.341578 RL = 0x3
5054 12:12:22.342180 BL = 0x2
5055 12:12:22.345052 RPST = 0x0
5056 12:12:22.345432 RD_PRE = 0x0
5057 12:12:22.347931 WR_PRE = 0x1
5058 12:12:22.348311 WR_PST = 0x0
5059 12:12:22.351242 DBI_WR = 0x0
5060 12:12:22.351692 DBI_RD = 0x0
5061 12:12:22.355244 OTF = 0x1
5062 12:12:22.358351 ===================================
5063 12:12:22.364400 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5064 12:12:22.368030 nWR fixed to 30
5065 12:12:22.371271 [ModeRegInit_LP4] CH0 RK0
5066 12:12:22.371798 [ModeRegInit_LP4] CH0 RK1
5067 12:12:22.374694 [ModeRegInit_LP4] CH1 RK0
5068 12:12:22.377676 [ModeRegInit_LP4] CH1 RK1
5069 12:12:22.378161 match AC timing 9
5070 12:12:22.384048 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5071 12:12:22.387608 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5072 12:12:22.390949 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5073 12:12:22.397400 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5074 12:12:22.400841 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5075 12:12:22.401221 ==
5076 12:12:22.404174 Dram Type= 6, Freq= 0, CH_0, rank 0
5077 12:12:22.407488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5078 12:12:22.407977 ==
5079 12:12:22.413858 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5080 12:12:22.420767 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5081 12:12:22.424297 [CA 0] Center 37 (7~68) winsize 62
5082 12:12:22.427318 [CA 1] Center 37 (7~68) winsize 62
5083 12:12:22.430330 [CA 2] Center 34 (4~64) winsize 61
5084 12:12:22.433713 [CA 3] Center 34 (3~65) winsize 63
5085 12:12:22.437080 [CA 4] Center 33 (3~63) winsize 61
5086 12:12:22.440973 [CA 5] Center 33 (3~63) winsize 61
5087 12:12:22.441460
5088 12:12:22.443441 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5089 12:12:22.443822
5090 12:12:22.446913 [CATrainingPosCal] consider 1 rank data
5091 12:12:22.450120 u2DelayCellTimex100 = 270/100 ps
5092 12:12:22.453569 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5093 12:12:22.457268 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5094 12:12:22.459818 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5095 12:12:22.463340 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5096 12:12:22.470113 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5097 12:12:22.473225 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5098 12:12:22.473607
5099 12:12:22.476262 CA PerBit enable=1, Macro0, CA PI delay=33
5100 12:12:22.476656
5101 12:12:22.479346 [CBTSetCACLKResult] CA Dly = 33
5102 12:12:22.479809 CS Dly: 5 (0~36)
5103 12:12:22.480131 ==
5104 12:12:22.483233 Dram Type= 6, Freq= 0, CH_0, rank 1
5105 12:12:22.489548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 12:12:22.490005 ==
5107 12:12:22.492976 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5108 12:12:22.499575 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5109 12:12:22.502916 [CA 0] Center 37 (7~68) winsize 62
5110 12:12:22.505806 [CA 1] Center 37 (7~68) winsize 62
5111 12:12:22.509109 [CA 2] Center 34 (4~65) winsize 62
5112 12:12:22.512820 [CA 3] Center 34 (4~65) winsize 62
5113 12:12:22.515857 [CA 4] Center 33 (3~64) winsize 62
5114 12:12:22.519333 [CA 5] Center 32 (2~63) winsize 62
5115 12:12:22.519879
5116 12:12:22.522356 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5117 12:12:22.522831
5118 12:12:22.525667 [CATrainingPosCal] consider 2 rank data
5119 12:12:22.529068 u2DelayCellTimex100 = 270/100 ps
5120 12:12:22.532623 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5121 12:12:22.535235 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5122 12:12:22.542510 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5123 12:12:22.545460 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5124 12:12:22.549034 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5125 12:12:22.551553 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5126 12:12:22.551942
5127 12:12:22.555086 CA PerBit enable=1, Macro0, CA PI delay=33
5128 12:12:22.555619
5129 12:12:22.558398 [CBTSetCACLKResult] CA Dly = 33
5130 12:12:22.562473 CS Dly: 6 (0~39)
5131 12:12:22.562971
5132 12:12:22.564966 ----->DramcWriteLeveling(PI) begin...
5133 12:12:22.565360 ==
5134 12:12:22.568656 Dram Type= 6, Freq= 0, CH_0, rank 0
5135 12:12:22.572531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5136 12:12:22.573032 ==
5137 12:12:22.574751 Write leveling (Byte 0): 31 => 31
5138 12:12:22.578536 Write leveling (Byte 1): 30 => 30
5139 12:12:22.582417 DramcWriteLeveling(PI) end<-----
5140 12:12:22.582900
5141 12:12:22.583203 ==
5142 12:12:22.585132 Dram Type= 6, Freq= 0, CH_0, rank 0
5143 12:12:22.588535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 12:12:22.589026 ==
5145 12:12:22.591590 [Gating] SW mode calibration
5146 12:12:22.598371 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5147 12:12:22.605308 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5148 12:12:22.608402 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
5149 12:12:22.611753 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5150 12:12:22.618290 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 12:12:22.621063 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 12:12:22.624255 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 12:12:22.631315 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 12:12:22.634419 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5155 12:12:22.638044 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
5156 12:12:22.644161 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (1 0)
5157 12:12:22.647806 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5158 12:12:22.651015 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 12:12:22.657278 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 12:12:22.660399 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 12:12:22.664029 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 12:12:22.670810 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5163 12:12:22.673881 0 15 28 | B1->B0 | 2424 3534 | 0 1 | (0 0) (0 0)
5164 12:12:22.677588 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5165 12:12:22.683756 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5166 12:12:22.687026 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 12:12:22.690680 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 12:12:22.697173 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 12:12:22.700341 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 12:12:22.703817 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 12:12:22.710115 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5172 12:12:22.713839 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5173 12:12:22.716536 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5174 12:12:22.723558 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 12:12:22.726790 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 12:12:22.729873 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 12:12:22.735964 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 12:12:22.739634 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 12:12:22.742854 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 12:12:22.749727 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 12:12:22.752771 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 12:12:22.756074 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 12:12:22.762343 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 12:12:22.765634 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 12:12:22.769076 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 12:12:22.775816 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 12:12:22.779032 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5188 12:12:22.782186 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5189 12:12:22.785798 Total UI for P1: 0, mck2ui 16
5190 12:12:22.789179 best dqsien dly found for B0: ( 1, 2, 28)
5191 12:12:22.795303 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 12:12:22.799213 Total UI for P1: 0, mck2ui 16
5193 12:12:22.801875 best dqsien dly found for B1: ( 1, 2, 30)
5194 12:12:22.805480 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5195 12:12:22.808849 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5196 12:12:22.809351
5197 12:12:22.811888 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5198 12:12:22.815475 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5199 12:12:22.818768 [Gating] SW calibration Done
5200 12:12:22.819263 ==
5201 12:12:22.821619 Dram Type= 6, Freq= 0, CH_0, rank 0
5202 12:12:22.824797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5203 12:12:22.828387 ==
5204 12:12:22.828880 RX Vref Scan: 0
5205 12:12:22.829192
5206 12:12:22.831930 RX Vref 0 -> 0, step: 1
5207 12:12:22.832319
5208 12:12:22.832628 RX Delay -80 -> 252, step: 8
5209 12:12:22.838107 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5210 12:12:22.841958 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5211 12:12:22.845106 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5212 12:12:22.848214 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5213 12:12:22.851422 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5214 12:12:22.858107 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5215 12:12:22.861504 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5216 12:12:22.864397 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5217 12:12:22.867942 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5218 12:12:22.871045 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5219 12:12:22.877655 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5220 12:12:22.880882 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5221 12:12:22.884444 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5222 12:12:22.887533 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5223 12:12:22.891514 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5224 12:12:22.894469 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5225 12:12:22.898000 ==
5226 12:12:22.900860 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 12:12:22.904216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 12:12:22.904646 ==
5229 12:12:22.905045 DQS Delay:
5230 12:12:22.907502 DQS0 = 0, DQS1 = 0
5231 12:12:22.908033 DQM Delay:
5232 12:12:22.911005 DQM0 = 100, DQM1 = 88
5233 12:12:22.911571 DQ Delay:
5234 12:12:22.914184 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5235 12:12:22.917510 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =107
5236 12:12:22.920586 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5237 12:12:22.924840 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5238 12:12:22.925376
5239 12:12:22.925887
5240 12:12:22.926309 ==
5241 12:12:22.927543 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 12:12:22.930639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 12:12:22.931114 ==
5244 12:12:22.934148
5245 12:12:22.934644
5246 12:12:22.935050 TX Vref Scan disable
5247 12:12:22.936950 == TX Byte 0 ==
5248 12:12:22.940381 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5249 12:12:22.943471 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5250 12:12:22.947043 == TX Byte 1 ==
5251 12:12:22.950424 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5252 12:12:22.953901 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5253 12:12:22.954433 ==
5254 12:12:22.957313 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 12:12:22.964232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 12:12:22.964761 ==
5257 12:12:22.965100
5258 12:12:22.965410
5259 12:12:22.965710 TX Vref Scan disable
5260 12:12:22.967662 == TX Byte 0 ==
5261 12:12:22.970785 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5262 12:12:22.978128 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5263 12:12:22.978721 == TX Byte 1 ==
5264 12:12:22.980683 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5265 12:12:22.987910 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5266 12:12:22.988430
5267 12:12:22.988770 [DATLAT]
5268 12:12:22.989084 Freq=933, CH0 RK0
5269 12:12:22.989383
5270 12:12:22.991144 DATLAT Default: 0xd
5271 12:12:22.991708 0, 0xFFFF, sum = 0
5272 12:12:22.994339 1, 0xFFFF, sum = 0
5273 12:12:22.997807 2, 0xFFFF, sum = 0
5274 12:12:22.998332 3, 0xFFFF, sum = 0
5275 12:12:23.001276 4, 0xFFFF, sum = 0
5276 12:12:23.001803 5, 0xFFFF, sum = 0
5277 12:12:23.004344 6, 0xFFFF, sum = 0
5278 12:12:23.004868 7, 0xFFFF, sum = 0
5279 12:12:23.007853 8, 0xFFFF, sum = 0
5280 12:12:23.008281 9, 0xFFFF, sum = 0
5281 12:12:23.010899 10, 0x0, sum = 1
5282 12:12:23.011468 11, 0x0, sum = 2
5283 12:12:23.014486 12, 0x0, sum = 3
5284 12:12:23.015016 13, 0x0, sum = 4
5285 12:12:23.015404 best_step = 11
5286 12:12:23.015739
5287 12:12:23.017412 ==
5288 12:12:23.021158 Dram Type= 6, Freq= 0, CH_0, rank 0
5289 12:12:23.025370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 12:12:23.025897 ==
5291 12:12:23.026262 RX Vref Scan: 1
5292 12:12:23.026576
5293 12:12:23.027289 RX Vref 0 -> 0, step: 1
5294 12:12:23.027761
5295 12:12:23.031118 RX Delay -61 -> 252, step: 4
5296 12:12:23.031693
5297 12:12:23.033906 Set Vref, RX VrefLevel [Byte0]: 54
5298 12:12:23.037108 [Byte1]: 59
5299 12:12:23.040278
5300 12:12:23.040699 Final RX Vref Byte 0 = 54 to rank0
5301 12:12:23.043840 Final RX Vref Byte 1 = 59 to rank0
5302 12:12:23.046784 Final RX Vref Byte 0 = 54 to rank1
5303 12:12:23.050458 Final RX Vref Byte 1 = 59 to rank1==
5304 12:12:23.054123 Dram Type= 6, Freq= 0, CH_0, rank 0
5305 12:12:23.059675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5306 12:12:23.060186 ==
5307 12:12:23.060582 DQS Delay:
5308 12:12:23.063099 DQS0 = 0, DQS1 = 0
5309 12:12:23.063563 DQM Delay:
5310 12:12:23.063906 DQM0 = 98, DQM1 = 88
5311 12:12:23.066646 DQ Delay:
5312 12:12:23.070507 DQ0 =100, DQ1 =100, DQ2 =92, DQ3 =94
5313 12:12:23.072861 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =104
5314 12:12:23.076565 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =84
5315 12:12:23.079794 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =94
5316 12:12:23.080181
5317 12:12:23.080504
5318 12:12:23.086399 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 412 ps
5319 12:12:23.090392 CH0 RK0: MR19=505, MR18=1C16
5320 12:12:23.095996 CH0_RK0: MR19=0x505, MR18=0x1C16, DQSOSC=412, MR23=63, INC=63, DEC=42
5321 12:12:23.096387
5322 12:12:23.099531 ----->DramcWriteLeveling(PI) begin...
5323 12:12:23.100019 ==
5324 12:12:23.103443 Dram Type= 6, Freq= 0, CH_0, rank 1
5325 12:12:23.106148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5326 12:12:23.106882 ==
5327 12:12:23.109760 Write leveling (Byte 0): 33 => 33
5328 12:12:23.112879 Write leveling (Byte 1): 30 => 30
5329 12:12:23.116361 DramcWriteLeveling(PI) end<-----
5330 12:12:23.116847
5331 12:12:23.117157 ==
5332 12:12:23.119490 Dram Type= 6, Freq= 0, CH_0, rank 1
5333 12:12:23.126123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5334 12:12:23.126613 ==
5335 12:12:23.126927 [Gating] SW mode calibration
5336 12:12:23.136185 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5337 12:12:23.138741 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5338 12:12:23.145381 0 14 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
5339 12:12:23.148821 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5340 12:12:23.152101 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 12:12:23.158850 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 12:12:23.161907 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 12:12:23.165579 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 12:12:23.171712 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 12:12:23.175144 0 14 28 | B1->B0 | 3333 2828 | 0 0 | (0 1) (0 0)
5346 12:12:23.178306 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
5347 12:12:23.185629 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5348 12:12:23.188255 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5349 12:12:23.192013 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 12:12:23.198238 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 12:12:23.202197 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 12:12:23.205473 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5353 12:12:23.211619 0 15 28 | B1->B0 | 2c2c 3e3e | 0 0 | (0 0) (1 1)
5354 12:12:23.215180 1 0 0 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
5355 12:12:23.218187 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5356 12:12:23.225159 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 12:12:23.228631 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 12:12:23.231430 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 12:12:23.237995 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 12:12:23.240966 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 12:12:23.244601 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5362 12:12:23.250555 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5363 12:12:23.254227 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 12:12:23.257485 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 12:12:23.263656 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 12:12:23.266874 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 12:12:23.270938 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 12:12:23.276844 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 12:12:23.280145 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 12:12:23.283252 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 12:12:23.290618 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 12:12:23.293870 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 12:12:23.296544 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 12:12:23.303548 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 12:12:23.306510 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 12:12:23.309914 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 12:12:23.316465 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5378 12:12:23.316885 Total UI for P1: 0, mck2ui 16
5379 12:12:23.323503 best dqsien dly found for B0: ( 1, 2, 26)
5380 12:12:23.326368 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5381 12:12:23.329939 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 12:12:23.333685 Total UI for P1: 0, mck2ui 16
5383 12:12:23.336390 best dqsien dly found for B1: ( 1, 2, 30)
5384 12:12:23.339717 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5385 12:12:23.343197 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5386 12:12:23.346057
5387 12:12:23.349845 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5388 12:12:23.352503 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5389 12:12:23.356606 [Gating] SW calibration Done
5390 12:12:23.357126 ==
5391 12:12:23.359637 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 12:12:23.362836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 12:12:23.363260 ==
5394 12:12:23.363659 RX Vref Scan: 0
5395 12:12:23.365907
5396 12:12:23.366326 RX Vref 0 -> 0, step: 1
5397 12:12:23.366662
5398 12:12:23.369342 RX Delay -80 -> 252, step: 8
5399 12:12:23.372495 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5400 12:12:23.375696 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5401 12:12:23.382893 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5402 12:12:23.385736 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5403 12:12:23.389217 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5404 12:12:23.392289 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5405 12:12:23.395243 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5406 12:12:23.398754 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5407 12:12:23.405305 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5408 12:12:23.408492 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5409 12:12:23.412003 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5410 12:12:23.415507 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5411 12:12:23.418851 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5412 12:12:23.425068 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5413 12:12:23.428141 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5414 12:12:23.432046 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5415 12:12:23.432567 ==
5416 12:12:23.435108 Dram Type= 6, Freq= 0, CH_0, rank 1
5417 12:12:23.438041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5418 12:12:23.438589 ==
5419 12:12:23.441362 DQS Delay:
5420 12:12:23.441882 DQS0 = 0, DQS1 = 0
5421 12:12:23.442220 DQM Delay:
5422 12:12:23.444615 DQM0 = 97, DQM1 = 91
5423 12:12:23.445035 DQ Delay:
5424 12:12:23.448127 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5425 12:12:23.451796 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5426 12:12:23.454936 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5427 12:12:23.458054 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =99
5428 12:12:23.458571
5429 12:12:23.458905
5430 12:12:23.461343 ==
5431 12:12:23.464515 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 12:12:23.467707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 12:12:23.468129 ==
5434 12:12:23.468541
5435 12:12:23.468859
5436 12:12:23.470814 TX Vref Scan disable
5437 12:12:23.471239 == TX Byte 0 ==
5438 12:12:23.474194 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5439 12:12:23.480778 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5440 12:12:23.481198 == TX Byte 1 ==
5441 12:12:23.487490 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5442 12:12:23.490848 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5443 12:12:23.491414 ==
5444 12:12:23.494334 Dram Type= 6, Freq= 0, CH_0, rank 1
5445 12:12:23.497392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5446 12:12:23.497826 ==
5447 12:12:23.498157
5448 12:12:23.498466
5449 12:12:23.501196 TX Vref Scan disable
5450 12:12:23.504246 == TX Byte 0 ==
5451 12:12:23.507499 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5452 12:12:23.510583 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5453 12:12:23.514406 == TX Byte 1 ==
5454 12:12:23.517752 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5455 12:12:23.520884 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5456 12:12:23.521407
5457 12:12:23.523694 [DATLAT]
5458 12:12:23.524111 Freq=933, CH0 RK1
5459 12:12:23.524442
5460 12:12:23.527049 DATLAT Default: 0xb
5461 12:12:23.527511 0, 0xFFFF, sum = 0
5462 12:12:23.530605 1, 0xFFFF, sum = 0
5463 12:12:23.531133 2, 0xFFFF, sum = 0
5464 12:12:23.533846 3, 0xFFFF, sum = 0
5465 12:12:23.534374 4, 0xFFFF, sum = 0
5466 12:12:23.537000 5, 0xFFFF, sum = 0
5467 12:12:23.537533 6, 0xFFFF, sum = 0
5468 12:12:23.540462 7, 0xFFFF, sum = 0
5469 12:12:23.540886 8, 0xFFFF, sum = 0
5470 12:12:23.543308 9, 0xFFFF, sum = 0
5471 12:12:23.543781 10, 0x0, sum = 1
5472 12:12:23.547332 11, 0x0, sum = 2
5473 12:12:23.547911 12, 0x0, sum = 3
5474 12:12:23.550038 13, 0x0, sum = 4
5475 12:12:23.550574 best_step = 11
5476 12:12:23.550907
5477 12:12:23.551217 ==
5478 12:12:23.553249 Dram Type= 6, Freq= 0, CH_0, rank 1
5479 12:12:23.560340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5480 12:12:23.560869 ==
5481 12:12:23.561209 RX Vref Scan: 0
5482 12:12:23.561523
5483 12:12:23.563239 RX Vref 0 -> 0, step: 1
5484 12:12:23.563702
5485 12:12:23.566301 RX Delay -53 -> 252, step: 4
5486 12:12:23.569727 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5487 12:12:23.576930 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5488 12:12:23.579686 iDelay=195, Bit 2, Center 94 (7 ~ 182) 176
5489 12:12:23.582850 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5490 12:12:23.586681 iDelay=195, Bit 4, Center 100 (11 ~ 190) 180
5491 12:12:23.589569 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5492 12:12:23.592582 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5493 12:12:23.599269 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5494 12:12:23.602751 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5495 12:12:23.606964 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5496 12:12:23.609381 iDelay=195, Bit 10, Center 92 (3 ~ 182) 180
5497 12:12:23.612442 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5498 12:12:23.619312 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5499 12:12:23.622174 iDelay=195, Bit 13, Center 96 (7 ~ 186) 180
5500 12:12:23.626403 iDelay=195, Bit 14, Center 98 (11 ~ 186) 176
5501 12:12:23.628898 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5502 12:12:23.629321 ==
5503 12:12:23.631920 Dram Type= 6, Freq= 0, CH_0, rank 1
5504 12:12:23.635814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5505 12:12:23.638665 ==
5506 12:12:23.639090 DQS Delay:
5507 12:12:23.639537 DQS0 = 0, DQS1 = 0
5508 12:12:23.642033 DQM Delay:
5509 12:12:23.642453 DQM0 = 97, DQM1 = 89
5510 12:12:23.645479 DQ Delay:
5511 12:12:23.648983 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5512 12:12:23.651836 DQ4 =100, DQ5 =86, DQ6 =106, DQ7 =104
5513 12:12:23.655440 DQ8 =80, DQ9 =76, DQ10 =92, DQ11 =84
5514 12:12:23.658839 DQ12 =94, DQ13 =96, DQ14 =98, DQ15 =94
5515 12:12:23.659353
5516 12:12:23.659764
5517 12:12:23.665440 [DQSOSCAuto] RK1, (LSB)MR18= 0x1310, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5518 12:12:23.668745 CH0 RK1: MR19=505, MR18=1310
5519 12:12:23.675410 CH0_RK1: MR19=0x505, MR18=0x1310, DQSOSC=415, MR23=63, INC=62, DEC=41
5520 12:12:23.678552 [RxdqsGatingPostProcess] freq 933
5521 12:12:23.681813 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5522 12:12:23.684874 best DQS0 dly(2T, 0.5T) = (0, 10)
5523 12:12:23.688238 best DQS1 dly(2T, 0.5T) = (0, 10)
5524 12:12:23.691738 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5525 12:12:23.695148 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5526 12:12:23.698713 best DQS0 dly(2T, 0.5T) = (0, 10)
5527 12:12:23.701081 best DQS1 dly(2T, 0.5T) = (0, 10)
5528 12:12:23.704742 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5529 12:12:23.708365 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5530 12:12:23.711609 Pre-setting of DQS Precalculation
5531 12:12:23.714632 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5532 12:12:23.717862 ==
5533 12:12:23.721223 Dram Type= 6, Freq= 0, CH_1, rank 0
5534 12:12:23.723943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 12:12:23.724374 ==
5536 12:12:23.730746 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5537 12:12:23.734469 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5538 12:12:23.738171 [CA 0] Center 36 (6~67) winsize 62
5539 12:12:23.740941 [CA 1] Center 36 (6~67) winsize 62
5540 12:12:23.744225 [CA 2] Center 34 (4~65) winsize 62
5541 12:12:23.747794 [CA 3] Center 34 (4~64) winsize 61
5542 12:12:23.751062 [CA 4] Center 34 (4~65) winsize 62
5543 12:12:23.754509 [CA 5] Center 33 (3~64) winsize 62
5544 12:12:23.755061
5545 12:12:23.757620 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5546 12:12:23.758040
5547 12:12:23.761607 [CATrainingPosCal] consider 1 rank data
5548 12:12:23.764037 u2DelayCellTimex100 = 270/100 ps
5549 12:12:23.767824 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5550 12:12:23.774438 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5551 12:12:23.777446 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5552 12:12:23.781030 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5553 12:12:23.784076 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5554 12:12:23.787465 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5555 12:12:23.787996
5556 12:12:23.791047 CA PerBit enable=1, Macro0, CA PI delay=33
5557 12:12:23.791610
5558 12:12:23.794601 [CBTSetCACLKResult] CA Dly = 33
5559 12:12:23.797319 CS Dly: 4 (0~35)
5560 12:12:23.797842 ==
5561 12:12:23.800904 Dram Type= 6, Freq= 0, CH_1, rank 1
5562 12:12:23.804229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 12:12:23.804753 ==
5564 12:12:23.810836 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5565 12:12:23.813562 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5566 12:12:23.818644 [CA 0] Center 36 (6~67) winsize 62
5567 12:12:23.821566 [CA 1] Center 36 (6~67) winsize 62
5568 12:12:23.824654 [CA 2] Center 34 (4~65) winsize 62
5569 12:12:23.828067 [CA 3] Center 33 (3~64) winsize 62
5570 12:12:23.830969 [CA 4] Center 33 (3~64) winsize 62
5571 12:12:23.834238 [CA 5] Center 33 (3~64) winsize 62
5572 12:12:23.834659
5573 12:12:23.838331 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5574 12:12:23.838848
5575 12:12:23.840602 [CATrainingPosCal] consider 2 rank data
5576 12:12:23.844411 u2DelayCellTimex100 = 270/100 ps
5577 12:12:23.847119 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5578 12:12:23.854478 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5579 12:12:23.857360 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5580 12:12:23.860532 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5581 12:12:23.863606 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5582 12:12:23.866844 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5583 12:12:23.867470
5584 12:12:23.870456 CA PerBit enable=1, Macro0, CA PI delay=33
5585 12:12:23.871020
5586 12:12:23.873809 [CBTSetCACLKResult] CA Dly = 33
5587 12:12:23.877004 CS Dly: 5 (0~38)
5588 12:12:23.877548
5589 12:12:23.880642 ----->DramcWriteLeveling(PI) begin...
5590 12:12:23.881072 ==
5591 12:12:23.883503 Dram Type= 6, Freq= 0, CH_1, rank 0
5592 12:12:23.886978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 12:12:23.887446 ==
5594 12:12:23.890379 Write leveling (Byte 0): 26 => 26
5595 12:12:23.893412 Write leveling (Byte 1): 27 => 27
5596 12:12:23.897068 DramcWriteLeveling(PI) end<-----
5597 12:12:23.897489
5598 12:12:23.897917 ==
5599 12:12:23.900541 Dram Type= 6, Freq= 0, CH_1, rank 0
5600 12:12:23.903284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5601 12:12:23.903754 ==
5602 12:12:23.906361 [Gating] SW mode calibration
5603 12:12:23.913192 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5604 12:12:23.920723 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5605 12:12:23.923979 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 12:12:23.929813 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 12:12:23.932914 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 12:12:23.936358 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 12:12:23.942440 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 12:12:23.946023 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 12:12:23.949657 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5612 12:12:23.956290 0 14 28 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
5613 12:12:23.959537 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5614 12:12:23.963290 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 12:12:23.970063 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 12:12:23.972346 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 12:12:23.975769 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 12:12:23.982200 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 12:12:23.986157 0 15 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5620 12:12:23.989089 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5621 12:12:23.995749 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 12:12:23.998894 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 12:12:24.002076 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 12:12:24.008687 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 12:12:24.011861 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 12:12:24.015302 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 12:12:24.021769 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5628 12:12:24.024811 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5629 12:12:24.028539 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5630 12:12:24.035495 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 12:12:24.038184 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 12:12:24.040963 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 12:12:24.048132 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 12:12:24.051960 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 12:12:24.054413 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 12:12:24.060811 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 12:12:24.064351 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 12:12:24.067539 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 12:12:24.074598 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 12:12:24.077417 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 12:12:24.080695 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 12:12:24.087577 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 12:12:24.090616 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5644 12:12:24.094418 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5645 12:12:24.100476 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 12:12:24.104255 Total UI for P1: 0, mck2ui 16
5647 12:12:24.107874 best dqsien dly found for B0: ( 1, 2, 26)
5648 12:12:24.108385 Total UI for P1: 0, mck2ui 16
5649 12:12:24.113886 best dqsien dly found for B1: ( 1, 2, 26)
5650 12:12:24.117342 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5651 12:12:24.120987 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5652 12:12:24.121502
5653 12:12:24.123908 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5654 12:12:24.127313 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5655 12:12:24.130504 [Gating] SW calibration Done
5656 12:12:24.131016 ==
5657 12:12:24.133654 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 12:12:24.137180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 12:12:24.137700 ==
5660 12:12:24.140135 RX Vref Scan: 0
5661 12:12:24.140554
5662 12:12:24.140884 RX Vref 0 -> 0, step: 1
5663 12:12:24.143475
5664 12:12:24.143894 RX Delay -80 -> 252, step: 8
5665 12:12:24.150150 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5666 12:12:24.153332 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5667 12:12:24.156618 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5668 12:12:24.160314 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5669 12:12:24.163606 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5670 12:12:24.166773 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5671 12:12:24.172862 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5672 12:12:24.176119 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5673 12:12:24.179647 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5674 12:12:24.182777 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5675 12:12:24.186004 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5676 12:12:24.192359 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5677 12:12:24.195914 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5678 12:12:24.199515 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5679 12:12:24.202485 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5680 12:12:24.205835 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5681 12:12:24.206255 ==
5682 12:12:24.208951 Dram Type= 6, Freq= 0, CH_1, rank 0
5683 12:12:24.215555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5684 12:12:24.215983 ==
5685 12:12:24.216321 DQS Delay:
5686 12:12:24.219339 DQS0 = 0, DQS1 = 0
5687 12:12:24.219907 DQM Delay:
5688 12:12:24.222402 DQM0 = 99, DQM1 = 95
5689 12:12:24.222822 DQ Delay:
5690 12:12:24.225194 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5691 12:12:24.229315 DQ4 =95, DQ5 =111, DQ6 =107, DQ7 =95
5692 12:12:24.232508 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5693 12:12:24.235684 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5694 12:12:24.236212
5695 12:12:24.236552
5696 12:12:24.236863 ==
5697 12:12:24.238756 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 12:12:24.242290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 12:12:24.242726 ==
5700 12:12:24.245349
5701 12:12:24.245879
5702 12:12:24.246215 TX Vref Scan disable
5703 12:12:24.248466 == TX Byte 0 ==
5704 12:12:24.252190 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5705 12:12:24.255457 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5706 12:12:24.258531 == TX Byte 1 ==
5707 12:12:24.261747 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5708 12:12:24.264798 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5709 12:12:24.265222 ==
5710 12:12:24.268519 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 12:12:24.274831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 12:12:24.275256 ==
5713 12:12:24.275697
5714 12:12:24.276023
5715 12:12:24.278012 TX Vref Scan disable
5716 12:12:24.278428 == TX Byte 0 ==
5717 12:12:24.284835 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5718 12:12:24.287672 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5719 12:12:24.288089 == TX Byte 1 ==
5720 12:12:24.294350 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5721 12:12:24.297552 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5722 12:12:24.297852
5723 12:12:24.298089 [DATLAT]
5724 12:12:24.301203 Freq=933, CH1 RK0
5725 12:12:24.301501
5726 12:12:24.301737 DATLAT Default: 0xd
5727 12:12:24.304335 0, 0xFFFF, sum = 0
5728 12:12:24.304637 1, 0xFFFF, sum = 0
5729 12:12:24.307749 2, 0xFFFF, sum = 0
5730 12:12:24.308049 3, 0xFFFF, sum = 0
5731 12:12:24.310729 4, 0xFFFF, sum = 0
5732 12:12:24.314124 5, 0xFFFF, sum = 0
5733 12:12:24.314425 6, 0xFFFF, sum = 0
5734 12:12:24.317375 7, 0xFFFF, sum = 0
5735 12:12:24.317780 8, 0xFFFF, sum = 0
5736 12:12:24.320645 9, 0xFFFF, sum = 0
5737 12:12:24.321049 10, 0x0, sum = 1
5738 12:12:24.324117 11, 0x0, sum = 2
5739 12:12:24.324524 12, 0x0, sum = 3
5740 12:12:24.324786 13, 0x0, sum = 4
5741 12:12:24.327460 best_step = 11
5742 12:12:24.327858
5743 12:12:24.328099 ==
5744 12:12:24.330954 Dram Type= 6, Freq= 0, CH_1, rank 0
5745 12:12:24.334047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 12:12:24.334564 ==
5747 12:12:24.337431 RX Vref Scan: 1
5748 12:12:24.337919
5749 12:12:24.340472 RX Vref 0 -> 0, step: 1
5750 12:12:24.340888
5751 12:12:24.341303 RX Delay -53 -> 252, step: 4
5752 12:12:24.341634
5753 12:12:24.343639 Set Vref, RX VrefLevel [Byte0]: 52
5754 12:12:24.347033 [Byte1]: 51
5755 12:12:24.351825
5756 12:12:24.352338 Final RX Vref Byte 0 = 52 to rank0
5757 12:12:24.355051 Final RX Vref Byte 1 = 51 to rank0
5758 12:12:24.358293 Final RX Vref Byte 0 = 52 to rank1
5759 12:12:24.361821 Final RX Vref Byte 1 = 51 to rank1==
5760 12:12:24.365176 Dram Type= 6, Freq= 0, CH_1, rank 0
5761 12:12:24.371400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 12:12:24.371953 ==
5763 12:12:24.372293 DQS Delay:
5764 12:12:24.374555 DQS0 = 0, DQS1 = 0
5765 12:12:24.375024 DQM Delay:
5766 12:12:24.375358 DQM0 = 98, DQM1 = 94
5767 12:12:24.377786 DQ Delay:
5768 12:12:24.381316 DQ0 =104, DQ1 =92, DQ2 =88, DQ3 =100
5769 12:12:24.384662 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
5770 12:12:24.388275 DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =88
5771 12:12:24.391865 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5772 12:12:24.392381
5773 12:12:24.392714
5774 12:12:24.397832 [DQSOSCAuto] RK0, (LSB)MR18= 0x818, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5775 12:12:24.401580 CH1 RK0: MR19=505, MR18=818
5776 12:12:24.408127 CH1_RK0: MR19=0x505, MR18=0x818, DQSOSC=414, MR23=63, INC=63, DEC=42
5777 12:12:24.408659
5778 12:12:24.411196 ----->DramcWriteLeveling(PI) begin...
5779 12:12:24.411643 ==
5780 12:12:24.414750 Dram Type= 6, Freq= 0, CH_1, rank 1
5781 12:12:24.418134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 12:12:24.418658 ==
5783 12:12:24.421117 Write leveling (Byte 0): 27 => 27
5784 12:12:24.424869 Write leveling (Byte 1): 27 => 27
5785 12:12:24.427910 DramcWriteLeveling(PI) end<-----
5786 12:12:24.428426
5787 12:12:24.428758 ==
5788 12:12:24.430826 Dram Type= 6, Freq= 0, CH_1, rank 1
5789 12:12:24.437991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5790 12:12:24.438655 ==
5791 12:12:24.439008 [Gating] SW mode calibration
5792 12:12:24.447321 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5793 12:12:24.450877 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5794 12:12:24.454085 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5795 12:12:24.460978 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5796 12:12:24.464032 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 12:12:24.470535 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 12:12:24.473861 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 12:12:24.477231 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 12:12:24.483674 0 14 24 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
5801 12:12:24.487210 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (1 0)
5802 12:12:24.490701 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5803 12:12:24.496682 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 12:12:24.500216 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 12:12:24.503820 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 12:12:24.509989 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 12:12:24.513396 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 12:12:24.516497 0 15 24 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
5809 12:12:24.523761 0 15 28 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5810 12:12:24.526566 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 12:12:24.529542 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 12:12:24.536304 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 12:12:24.539514 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 12:12:24.542834 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 12:12:24.549810 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 12:12:24.552723 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5817 12:12:24.555947 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5818 12:12:24.563177 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 12:12:24.566296 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 12:12:24.569563 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 12:12:24.575514 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 12:12:24.579888 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 12:12:24.582870 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 12:12:24.589075 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 12:12:24.593080 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 12:12:24.596026 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 12:12:24.602683 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 12:12:24.605282 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 12:12:24.609034 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 12:12:24.615924 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 12:12:24.618663 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 12:12:24.621865 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5833 12:12:24.628557 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5834 12:12:24.629073 Total UI for P1: 0, mck2ui 16
5835 12:12:24.635285 best dqsien dly found for B0: ( 1, 2, 24)
5836 12:12:24.638686 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5837 12:12:24.641520 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 12:12:24.645295 Total UI for P1: 0, mck2ui 16
5839 12:12:24.647984 best dqsien dly found for B1: ( 1, 2, 30)
5840 12:12:24.651958 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5841 12:12:24.654630 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5842 12:12:24.655071
5843 12:12:24.661848 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5844 12:12:24.664374 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5845 12:12:24.664793 [Gating] SW calibration Done
5846 12:12:24.668286 ==
5847 12:12:24.671655 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 12:12:24.674548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 12:12:24.674971 ==
5850 12:12:24.675304 RX Vref Scan: 0
5851 12:12:24.675717
5852 12:12:24.678042 RX Vref 0 -> 0, step: 1
5853 12:12:24.678458
5854 12:12:24.681371 RX Delay -80 -> 252, step: 8
5855 12:12:24.685001 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5856 12:12:24.687946 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5857 12:12:24.694410 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5858 12:12:24.697333 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5859 12:12:24.701114 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5860 12:12:24.704438 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5861 12:12:24.707502 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5862 12:12:24.710527 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5863 12:12:24.717216 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5864 12:12:24.720387 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5865 12:12:24.724383 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5866 12:12:24.727280 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5867 12:12:24.730255 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5868 12:12:24.736859 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5869 12:12:24.740050 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5870 12:12:24.743554 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5871 12:12:24.744069 ==
5872 12:12:24.747127 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 12:12:24.750337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 12:12:24.750850 ==
5875 12:12:24.753159 DQS Delay:
5876 12:12:24.753687 DQS0 = 0, DQS1 = 0
5877 12:12:24.756204 DQM Delay:
5878 12:12:24.756621 DQM0 = 97, DQM1 = 94
5879 12:12:24.756951 DQ Delay:
5880 12:12:24.759815 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5881 12:12:24.763056 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5882 12:12:24.766500 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5883 12:12:24.770081 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =103
5884 12:12:24.773259
5885 12:12:24.773680
5886 12:12:24.774012 ==
5887 12:12:24.776314 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 12:12:24.779744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 12:12:24.780260 ==
5890 12:12:24.780595
5891 12:12:24.780904
5892 12:12:24.783030 TX Vref Scan disable
5893 12:12:24.783490 == TX Byte 0 ==
5894 12:12:24.790014 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5895 12:12:24.792879 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5896 12:12:24.793397 == TX Byte 1 ==
5897 12:12:24.799474 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5898 12:12:24.803546 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5899 12:12:24.804064 ==
5900 12:12:24.806324 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 12:12:24.809189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 12:12:24.809737 ==
5903 12:12:24.810086
5904 12:12:24.810396
5905 12:12:24.812561 TX Vref Scan disable
5906 12:12:24.816218 == TX Byte 0 ==
5907 12:12:24.819055 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5908 12:12:24.822430 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5909 12:12:24.825906 == TX Byte 1 ==
5910 12:12:24.828613 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5911 12:12:24.832720 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5912 12:12:24.833290
5913 12:12:24.835716 [DATLAT]
5914 12:12:24.836228 Freq=933, CH1 RK1
5915 12:12:24.836566
5916 12:12:24.839041 DATLAT Default: 0xb
5917 12:12:24.839612 0, 0xFFFF, sum = 0
5918 12:12:24.842206 1, 0xFFFF, sum = 0
5919 12:12:24.842630 2, 0xFFFF, sum = 0
5920 12:12:24.845099 3, 0xFFFF, sum = 0
5921 12:12:24.845523 4, 0xFFFF, sum = 0
5922 12:12:24.848543 5, 0xFFFF, sum = 0
5923 12:12:24.851885 6, 0xFFFF, sum = 0
5924 12:12:24.852309 7, 0xFFFF, sum = 0
5925 12:12:24.855159 8, 0xFFFF, sum = 0
5926 12:12:24.855632 9, 0xFFFF, sum = 0
5927 12:12:24.858464 10, 0x0, sum = 1
5928 12:12:24.858885 11, 0x0, sum = 2
5929 12:12:24.859220 12, 0x0, sum = 3
5930 12:12:24.862348 13, 0x0, sum = 4
5931 12:12:24.862874 best_step = 11
5932 12:12:24.863207
5933 12:12:24.865336 ==
5934 12:12:24.868663 Dram Type= 6, Freq= 0, CH_1, rank 1
5935 12:12:24.871622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5936 12:12:24.872142 ==
5937 12:12:24.872482 RX Vref Scan: 0
5938 12:12:24.872797
5939 12:12:24.874875 RX Vref 0 -> 0, step: 1
5940 12:12:24.875442
5941 12:12:24.878866 RX Delay -53 -> 252, step: 4
5942 12:12:24.884878 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5943 12:12:24.888543 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5944 12:12:24.891397 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5945 12:12:24.895120 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5946 12:12:24.898357 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5947 12:12:24.901997 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5948 12:12:24.907917 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5949 12:12:24.910712 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5950 12:12:24.914986 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5951 12:12:24.917668 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5952 12:12:24.920759 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5953 12:12:24.927411 iDelay=199, Bit 11, Center 84 (-9 ~ 178) 188
5954 12:12:24.930842 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5955 12:12:24.933937 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5956 12:12:24.937245 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5957 12:12:24.940729 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5958 12:12:24.944012 ==
5959 12:12:24.947407 Dram Type= 6, Freq= 0, CH_1, rank 1
5960 12:12:24.950253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5961 12:12:24.950710 ==
5962 12:12:24.951042 DQS Delay:
5963 12:12:24.953560 DQS0 = 0, DQS1 = 0
5964 12:12:24.953981 DQM Delay:
5965 12:12:24.957354 DQM0 = 96, DQM1 = 91
5966 12:12:24.957775 DQ Delay:
5967 12:12:24.960399 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =92
5968 12:12:24.964044 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =92
5969 12:12:24.967481 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =84
5970 12:12:24.970533 DQ12 =100, DQ13 =100, DQ14 =96, DQ15 =100
5971 12:12:24.970955
5972 12:12:24.971285
5973 12:12:24.976924 [DQSOSCAuto] RK1, (LSB)MR18= 0xf26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 417 ps
5974 12:12:24.980893 CH1 RK1: MR19=505, MR18=F26
5975 12:12:24.986914 CH1_RK1: MR19=0x505, MR18=0xF26, DQSOSC=409, MR23=63, INC=64, DEC=43
5976 12:12:24.990910 [RxdqsGatingPostProcess] freq 933
5977 12:12:24.996685 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5978 12:12:24.999659 best DQS0 dly(2T, 0.5T) = (0, 10)
5979 12:12:25.003327 best DQS1 dly(2T, 0.5T) = (0, 10)
5980 12:12:25.006709 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5981 12:12:25.010075 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5982 12:12:25.010590 best DQS0 dly(2T, 0.5T) = (0, 10)
5983 12:12:25.013048 best DQS1 dly(2T, 0.5T) = (0, 10)
5984 12:12:25.016296 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5985 12:12:25.019886 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5986 12:12:25.023105 Pre-setting of DQS Precalculation
5987 12:12:25.029333 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5988 12:12:25.036466 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5989 12:12:25.043188 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5990 12:12:25.043753
5991 12:12:25.044094
5992 12:12:25.045859 [Calibration Summary] 1866 Mbps
5993 12:12:25.049362 CH 0, Rank 0
5994 12:12:25.049787 SW Impedance : PASS
5995 12:12:25.052527 DUTY Scan : NO K
5996 12:12:25.052949 ZQ Calibration : PASS
5997 12:12:25.055981 Jitter Meter : NO K
5998 12:12:25.059147 CBT Training : PASS
5999 12:12:25.059603 Write leveling : PASS
6000 12:12:25.062775 RX DQS gating : PASS
6001 12:12:25.066439 RX DQ/DQS(RDDQC) : PASS
6002 12:12:25.066973 TX DQ/DQS : PASS
6003 12:12:25.069118 RX DATLAT : PASS
6004 12:12:25.072411 RX DQ/DQS(Engine): PASS
6005 12:12:25.072839 TX OE : NO K
6006 12:12:25.075480 All Pass.
6007 12:12:25.075897
6008 12:12:25.076231 CH 0, Rank 1
6009 12:12:25.078820 SW Impedance : PASS
6010 12:12:25.079236 DUTY Scan : NO K
6011 12:12:25.082335 ZQ Calibration : PASS
6012 12:12:25.085280 Jitter Meter : NO K
6013 12:12:25.085698 CBT Training : PASS
6014 12:12:25.088895 Write leveling : PASS
6015 12:12:25.092161 RX DQS gating : PASS
6016 12:12:25.092578 RX DQ/DQS(RDDQC) : PASS
6017 12:12:25.095260 TX DQ/DQS : PASS
6018 12:12:25.098369 RX DATLAT : PASS
6019 12:12:25.098823 RX DQ/DQS(Engine): PASS
6020 12:12:25.101850 TX OE : NO K
6021 12:12:25.102271 All Pass.
6022 12:12:25.102604
6023 12:12:25.105243 CH 1, Rank 0
6024 12:12:25.105658 SW Impedance : PASS
6025 12:12:25.108370 DUTY Scan : NO K
6026 12:12:25.111628 ZQ Calibration : PASS
6027 12:12:25.112082 Jitter Meter : NO K
6028 12:12:25.115419 CBT Training : PASS
6029 12:12:25.118189 Write leveling : PASS
6030 12:12:25.118712 RX DQS gating : PASS
6031 12:12:25.121652 RX DQ/DQS(RDDQC) : PASS
6032 12:12:25.124935 TX DQ/DQS : PASS
6033 12:12:25.125461 RX DATLAT : PASS
6034 12:12:25.127915 RX DQ/DQS(Engine): PASS
6035 12:12:25.131235 TX OE : NO K
6036 12:12:25.131813 All Pass.
6037 12:12:25.132154
6038 12:12:25.132467 CH 1, Rank 1
6039 12:12:25.135098 SW Impedance : PASS
6040 12:12:25.137917 DUTY Scan : NO K
6041 12:12:25.138442 ZQ Calibration : PASS
6042 12:12:25.141785 Jitter Meter : NO K
6043 12:12:25.144718 CBT Training : PASS
6044 12:12:25.145239 Write leveling : PASS
6045 12:12:25.147712 RX DQS gating : PASS
6046 12:12:25.148376 RX DQ/DQS(RDDQC) : PASS
6047 12:12:25.150947 TX DQ/DQS : PASS
6048 12:12:25.154039 RX DATLAT : PASS
6049 12:12:25.154455 RX DQ/DQS(Engine): PASS
6050 12:12:25.157678 TX OE : NO K
6051 12:12:25.158233 All Pass.
6052 12:12:25.158578
6053 12:12:25.160938 DramC Write-DBI off
6054 12:12:25.164918 PER_BANK_REFRESH: Hybrid Mode
6055 12:12:25.165460 TX_TRACKING: ON
6056 12:12:25.174599 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6057 12:12:25.177835 [FAST_K] Save calibration result to emmc
6058 12:12:25.180608 dramc_set_vcore_voltage set vcore to 650000
6059 12:12:25.184299 Read voltage for 400, 6
6060 12:12:25.184824 Vio18 = 0
6061 12:12:25.187266 Vcore = 650000
6062 12:12:25.187750 Vdram = 0
6063 12:12:25.188088 Vddq = 0
6064 12:12:25.188396 Vmddr = 0
6065 12:12:25.194646 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6066 12:12:25.200552 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6067 12:12:25.201133 MEM_TYPE=3, freq_sel=20
6068 12:12:25.203985 sv_algorithm_assistance_LP4_800
6069 12:12:25.207188 ============ PULL DRAM RESETB DOWN ============
6070 12:12:25.214007 ========== PULL DRAM RESETB DOWN end =========
6071 12:12:25.216762 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6072 12:12:25.220323 ===================================
6073 12:12:25.223408 LPDDR4 DRAM CONFIGURATION
6074 12:12:25.226977 ===================================
6075 12:12:25.227605 EX_ROW_EN[0] = 0x0
6076 12:12:25.230291 EX_ROW_EN[1] = 0x0
6077 12:12:25.233731 LP4Y_EN = 0x0
6078 12:12:25.234255 WORK_FSP = 0x0
6079 12:12:25.236581 WL = 0x2
6080 12:12:25.237112 RL = 0x2
6081 12:12:25.240098 BL = 0x2
6082 12:12:25.240624 RPST = 0x0
6083 12:12:25.242986 RD_PRE = 0x0
6084 12:12:25.243441 WR_PRE = 0x1
6085 12:12:25.246668 WR_PST = 0x0
6086 12:12:25.247190 DBI_WR = 0x0
6087 12:12:25.250136 DBI_RD = 0x0
6088 12:12:25.250694 OTF = 0x1
6089 12:12:25.253068 ===================================
6090 12:12:25.256255 ===================================
6091 12:12:25.259870 ANA top config
6092 12:12:25.263180 ===================================
6093 12:12:25.263761 DLL_ASYNC_EN = 0
6094 12:12:25.266528 ALL_SLAVE_EN = 1
6095 12:12:25.269523 NEW_RANK_MODE = 1
6096 12:12:25.272705 DLL_IDLE_MODE = 1
6097 12:12:25.275926 LP45_APHY_COMB_EN = 1
6098 12:12:25.276345 TX_ODT_DIS = 1
6099 12:12:25.280037 NEW_8X_MODE = 1
6100 12:12:25.282564 ===================================
6101 12:12:25.285581 ===================================
6102 12:12:25.289199 data_rate = 800
6103 12:12:25.292353 CKR = 1
6104 12:12:25.296207 DQ_P2S_RATIO = 4
6105 12:12:25.299290 ===================================
6106 12:12:25.302852 CA_P2S_RATIO = 4
6107 12:12:25.303426 DQ_CA_OPEN = 0
6108 12:12:25.305706 DQ_SEMI_OPEN = 1
6109 12:12:25.308877 CA_SEMI_OPEN = 1
6110 12:12:25.312580 CA_FULL_RATE = 0
6111 12:12:25.315458 DQ_CKDIV4_EN = 0
6112 12:12:25.319088 CA_CKDIV4_EN = 1
6113 12:12:25.319654 CA_PREDIV_EN = 0
6114 12:12:25.322500 PH8_DLY = 0
6115 12:12:25.325920 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6116 12:12:25.328829 DQ_AAMCK_DIV = 0
6117 12:12:25.332066 CA_AAMCK_DIV = 0
6118 12:12:25.336167 CA_ADMCK_DIV = 4
6119 12:12:25.338639 DQ_TRACK_CA_EN = 0
6120 12:12:25.339161 CA_PICK = 800
6121 12:12:25.342153 CA_MCKIO = 400
6122 12:12:25.345172 MCKIO_SEMI = 400
6123 12:12:25.348845 PLL_FREQ = 3016
6124 12:12:25.351956 DQ_UI_PI_RATIO = 32
6125 12:12:25.355124 CA_UI_PI_RATIO = 32
6126 12:12:25.358520 ===================================
6127 12:12:25.361781 ===================================
6128 12:12:25.365248 memory_type:LPDDR4
6129 12:12:25.365800 GP_NUM : 10
6130 12:12:25.368088 SRAM_EN : 1
6131 12:12:25.368508 MD32_EN : 0
6132 12:12:25.371467 ===================================
6133 12:12:25.374960 [ANA_INIT] >>>>>>>>>>>>>>
6134 12:12:25.377956 <<<<<< [CONFIGURE PHASE]: ANA_TX
6135 12:12:25.381087 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6136 12:12:25.384788 ===================================
6137 12:12:25.387629 data_rate = 800,PCW = 0X7400
6138 12:12:25.391170 ===================================
6139 12:12:25.394751 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6140 12:12:25.400824 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6141 12:12:25.411229 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6142 12:12:25.414233 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6143 12:12:25.421165 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6144 12:12:25.423899 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6145 12:12:25.424323 [ANA_INIT] flow start
6146 12:12:25.427443 [ANA_INIT] PLL >>>>>>>>
6147 12:12:25.430395 [ANA_INIT] PLL <<<<<<<<
6148 12:12:25.430817 [ANA_INIT] MIDPI >>>>>>>>
6149 12:12:25.433997 [ANA_INIT] MIDPI <<<<<<<<
6150 12:12:25.437290 [ANA_INIT] DLL >>>>>>>>
6151 12:12:25.437811 [ANA_INIT] flow end
6152 12:12:25.443889 ============ LP4 DIFF to SE enter ============
6153 12:12:25.447419 ============ LP4 DIFF to SE exit ============
6154 12:12:25.447958 [ANA_INIT] <<<<<<<<<<<<<
6155 12:12:25.450153 [Flow] Enable top DCM control >>>>>
6156 12:12:25.454554 [Flow] Enable top DCM control <<<<<
6157 12:12:25.457374 Enable DLL master slave shuffle
6158 12:12:25.464209 ==============================================================
6159 12:12:25.467332 Gating Mode config
6160 12:12:25.471398 ==============================================================
6161 12:12:25.473401 Config description:
6162 12:12:25.483096 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6163 12:12:25.490307 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6164 12:12:25.493188 SELPH_MODE 0: By rank 1: By Phase
6165 12:12:25.499730 ==============================================================
6166 12:12:25.502936 GAT_TRACK_EN = 0
6167 12:12:25.506875 RX_GATING_MODE = 2
6168 12:12:25.510044 RX_GATING_TRACK_MODE = 2
6169 12:12:25.513741 SELPH_MODE = 1
6170 12:12:25.516348 PICG_EARLY_EN = 1
6171 12:12:25.516769 VALID_LAT_VALUE = 1
6172 12:12:25.523455 ==============================================================
6173 12:12:25.526145 Enter into Gating configuration >>>>
6174 12:12:25.529737 Exit from Gating configuration <<<<
6175 12:12:25.533402 Enter into DVFS_PRE_config >>>>>
6176 12:12:25.543160 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6177 12:12:25.546272 Exit from DVFS_PRE_config <<<<<
6178 12:12:25.549274 Enter into PICG configuration >>>>
6179 12:12:25.552992 Exit from PICG configuration <<<<
6180 12:12:25.555685 [RX_INPUT] configuration >>>>>
6181 12:12:25.559268 [RX_INPUT] configuration <<<<<
6182 12:12:25.565777 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6183 12:12:25.569069 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6184 12:12:25.576000 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6185 12:12:25.582534 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6186 12:12:25.588712 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6187 12:12:25.595263 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6188 12:12:25.598790 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6189 12:12:25.601882 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6190 12:12:25.605164 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6191 12:12:25.611661 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6192 12:12:25.615587 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6193 12:12:25.618640 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6194 12:12:25.622407 ===================================
6195 12:12:25.624995 LPDDR4 DRAM CONFIGURATION
6196 12:12:25.628054 ===================================
6197 12:12:25.631566 EX_ROW_EN[0] = 0x0
6198 12:12:25.632085 EX_ROW_EN[1] = 0x0
6199 12:12:25.634614 LP4Y_EN = 0x0
6200 12:12:25.635130 WORK_FSP = 0x0
6201 12:12:25.638366 WL = 0x2
6202 12:12:25.638789 RL = 0x2
6203 12:12:25.641416 BL = 0x2
6204 12:12:25.641932 RPST = 0x0
6205 12:12:25.644094 RD_PRE = 0x0
6206 12:12:25.644517 WR_PRE = 0x1
6207 12:12:25.647691 WR_PST = 0x0
6208 12:12:25.648148 DBI_WR = 0x0
6209 12:12:25.650833 DBI_RD = 0x0
6210 12:12:25.654443 OTF = 0x1
6211 12:12:25.658229 ===================================
6212 12:12:25.661026 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6213 12:12:25.664472 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6214 12:12:25.667491 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6215 12:12:25.670361 ===================================
6216 12:12:25.674289 LPDDR4 DRAM CONFIGURATION
6217 12:12:25.677831 ===================================
6218 12:12:25.680419 EX_ROW_EN[0] = 0x10
6219 12:12:25.680833 EX_ROW_EN[1] = 0x0
6220 12:12:25.683882 LP4Y_EN = 0x0
6221 12:12:25.684410 WORK_FSP = 0x0
6222 12:12:25.687499 WL = 0x2
6223 12:12:25.688016 RL = 0x2
6224 12:12:25.690590 BL = 0x2
6225 12:12:25.691113 RPST = 0x0
6226 12:12:25.694127 RD_PRE = 0x0
6227 12:12:25.694543 WR_PRE = 0x1
6228 12:12:25.697243 WR_PST = 0x0
6229 12:12:25.700243 DBI_WR = 0x0
6230 12:12:25.700674 DBI_RD = 0x0
6231 12:12:25.703911 OTF = 0x1
6232 12:12:25.707042 ===================================
6233 12:12:25.710599 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6234 12:12:25.715613 nWR fixed to 30
6235 12:12:25.718896 [ModeRegInit_LP4] CH0 RK0
6236 12:12:25.719480 [ModeRegInit_LP4] CH0 RK1
6237 12:12:25.722597 [ModeRegInit_LP4] CH1 RK0
6238 12:12:25.725688 [ModeRegInit_LP4] CH1 RK1
6239 12:12:25.726223 match AC timing 19
6240 12:12:25.731936 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6241 12:12:25.735340 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6242 12:12:25.738487 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6243 12:12:25.745821 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6244 12:12:25.748248 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6245 12:12:25.748669 ==
6246 12:12:25.751414 Dram Type= 6, Freq= 0, CH_0, rank 0
6247 12:12:25.755473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6248 12:12:25.755996 ==
6249 12:12:25.761598 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6250 12:12:25.768392 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6251 12:12:25.771249 [CA 0] Center 36 (8~64) winsize 57
6252 12:12:25.774950 [CA 1] Center 36 (8~64) winsize 57
6253 12:12:25.778052 [CA 2] Center 36 (8~64) winsize 57
6254 12:12:25.781470 [CA 3] Center 36 (8~64) winsize 57
6255 12:12:25.784534 [CA 4] Center 36 (8~64) winsize 57
6256 12:12:25.787946 [CA 5] Center 36 (8~64) winsize 57
6257 12:12:25.788368
6258 12:12:25.791657 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6259 12:12:25.792184
6260 12:12:25.794376 [CATrainingPosCal] consider 1 rank data
6261 12:12:25.797890 u2DelayCellTimex100 = 270/100 ps
6262 12:12:25.800854 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 12:12:25.804310 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 12:12:25.808326 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 12:12:25.811446 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 12:12:25.814000 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 12:12:25.817485 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 12:12:25.817906
6269 12:12:25.824417 CA PerBit enable=1, Macro0, CA PI delay=36
6270 12:12:25.824949
6271 12:12:25.825280 [CBTSetCACLKResult] CA Dly = 36
6272 12:12:25.827411 CS Dly: 1 (0~32)
6273 12:12:25.827827 ==
6274 12:12:25.830724 Dram Type= 6, Freq= 0, CH_0, rank 1
6275 12:12:25.834062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 12:12:25.834580 ==
6277 12:12:25.840621 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6278 12:12:25.847120 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6279 12:12:25.850618 [CA 0] Center 36 (8~64) winsize 57
6280 12:12:25.853795 [CA 1] Center 36 (8~64) winsize 57
6281 12:12:25.857086 [CA 2] Center 36 (8~64) winsize 57
6282 12:12:25.860849 [CA 3] Center 36 (8~64) winsize 57
6283 12:12:25.864030 [CA 4] Center 36 (8~64) winsize 57
6284 12:12:25.864562 [CA 5] Center 36 (8~64) winsize 57
6285 12:12:25.867182
6286 12:12:25.870056 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6287 12:12:25.870492
6288 12:12:25.873767 [CATrainingPosCal] consider 2 rank data
6289 12:12:25.876918 u2DelayCellTimex100 = 270/100 ps
6290 12:12:25.879763 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 12:12:25.883910 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 12:12:25.886351 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 12:12:25.890267 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 12:12:25.893805 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 12:12:25.896239 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 12:12:25.896667
6297 12:12:25.899700 CA PerBit enable=1, Macro0, CA PI delay=36
6298 12:12:25.903337
6299 12:12:25.903771 [CBTSetCACLKResult] CA Dly = 36
6300 12:12:25.906577 CS Dly: 1 (0~32)
6301 12:12:25.907097
6302 12:12:25.909866 ----->DramcWriteLeveling(PI) begin...
6303 12:12:25.910284 ==
6304 12:12:25.912834 Dram Type= 6, Freq= 0, CH_0, rank 0
6305 12:12:25.916619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 12:12:25.917141 ==
6307 12:12:25.919166 Write leveling (Byte 0): 40 => 8
6308 12:12:25.922995 Write leveling (Byte 1): 40 => 8
6309 12:12:25.926087 DramcWriteLeveling(PI) end<-----
6310 12:12:25.926501
6311 12:12:25.926960 ==
6312 12:12:25.929293 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 12:12:25.932551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 12:12:25.936189 ==
6315 12:12:25.936761 [Gating] SW mode calibration
6316 12:12:25.945858 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6317 12:12:25.949403 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6318 12:12:25.952360 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6319 12:12:25.959355 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6320 12:12:25.962587 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6321 12:12:25.965405 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6322 12:12:25.972535 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6323 12:12:25.975498 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6324 12:12:25.978489 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6325 12:12:25.985604 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 12:12:25.988480 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6327 12:12:25.992032 Total UI for P1: 0, mck2ui 16
6328 12:12:25.995145 best dqsien dly found for B0: ( 0, 14, 24)
6329 12:12:25.998503 Total UI for P1: 0, mck2ui 16
6330 12:12:26.001880 best dqsien dly found for B1: ( 0, 14, 24)
6331 12:12:26.005805 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6332 12:12:26.008366 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6333 12:12:26.008806
6334 12:12:26.012025 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6335 12:12:26.018240 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6336 12:12:26.018655 [Gating] SW calibration Done
6337 12:12:26.019015 ==
6338 12:12:26.021495 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 12:12:26.028512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 12:12:26.029200 ==
6341 12:12:26.029655 RX Vref Scan: 0
6342 12:12:26.029976
6343 12:12:26.031725 RX Vref 0 -> 0, step: 1
6344 12:12:26.032137
6345 12:12:26.035086 RX Delay -410 -> 252, step: 16
6346 12:12:26.037762 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6347 12:12:26.041348 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6348 12:12:26.047907 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6349 12:12:26.051446 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6350 12:12:26.054722 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6351 12:12:26.057783 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6352 12:12:26.064581 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6353 12:12:26.067704 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6354 12:12:26.071204 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6355 12:12:26.074156 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6356 12:12:26.080808 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6357 12:12:26.083953 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6358 12:12:26.087221 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6359 12:12:26.094016 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6360 12:12:26.097495 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6361 12:12:26.100061 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6362 12:12:26.100567 ==
6363 12:12:26.103679 Dram Type= 6, Freq= 0, CH_0, rank 0
6364 12:12:26.110356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6365 12:12:26.110952 ==
6366 12:12:26.111295 DQS Delay:
6367 12:12:26.113326 DQS0 = 35, DQS1 = 51
6368 12:12:26.113736 DQM Delay:
6369 12:12:26.114061 DQM0 = 4, DQM1 = 11
6370 12:12:26.116580 DQ Delay:
6371 12:12:26.120495 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6372 12:12:26.120907 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6373 12:12:26.123511 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6374 12:12:26.126792 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6375 12:12:26.127207
6376 12:12:26.127591
6377 12:12:26.129745 ==
6378 12:12:26.133352 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 12:12:26.136306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 12:12:26.136734 ==
6381 12:12:26.137066
6382 12:12:26.137371
6383 12:12:26.139742 TX Vref Scan disable
6384 12:12:26.140168 == TX Byte 0 ==
6385 12:12:26.143060 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6386 12:12:26.150005 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6387 12:12:26.150417 == TX Byte 1 ==
6388 12:12:26.153019 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6389 12:12:26.159727 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6390 12:12:26.160166 ==
6391 12:12:26.162728 Dram Type= 6, Freq= 0, CH_0, rank 0
6392 12:12:26.166220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6393 12:12:26.166632 ==
6394 12:12:26.166954
6395 12:12:26.167253
6396 12:12:26.169973 TX Vref Scan disable
6397 12:12:26.170499 == TX Byte 0 ==
6398 12:12:26.172634 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6399 12:12:26.179392 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6400 12:12:26.179823 == TX Byte 1 ==
6401 12:12:26.182968 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6402 12:12:26.189390 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6403 12:12:26.189896
6404 12:12:26.190226 [DATLAT]
6405 12:12:26.192832 Freq=400, CH0 RK0
6406 12:12:26.193373
6407 12:12:26.193705 DATLAT Default: 0xf
6408 12:12:26.195983 0, 0xFFFF, sum = 0
6409 12:12:26.196506 1, 0xFFFF, sum = 0
6410 12:12:26.199334 2, 0xFFFF, sum = 0
6411 12:12:26.199893 3, 0xFFFF, sum = 0
6412 12:12:26.202204 4, 0xFFFF, sum = 0
6413 12:12:26.202620 5, 0xFFFF, sum = 0
6414 12:12:26.205688 6, 0xFFFF, sum = 0
6415 12:12:26.206214 7, 0xFFFF, sum = 0
6416 12:12:26.209024 8, 0xFFFF, sum = 0
6417 12:12:26.209442 9, 0xFFFF, sum = 0
6418 12:12:26.212018 10, 0xFFFF, sum = 0
6419 12:12:26.212438 11, 0xFFFF, sum = 0
6420 12:12:26.215520 12, 0xFFFF, sum = 0
6421 12:12:26.219577 13, 0x0, sum = 1
6422 12:12:26.220101 14, 0x0, sum = 2
6423 12:12:26.220437 15, 0x0, sum = 3
6424 12:12:26.222247 16, 0x0, sum = 4
6425 12:12:26.222663 best_step = 14
6426 12:12:26.222991
6427 12:12:26.223299 ==
6428 12:12:26.225738 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 12:12:26.232342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 12:12:26.232861 ==
6431 12:12:26.233190 RX Vref Scan: 1
6432 12:12:26.233496
6433 12:12:26.235764 RX Vref 0 -> 0, step: 1
6434 12:12:26.236282
6435 12:12:26.238970 RX Delay -343 -> 252, step: 8
6436 12:12:26.239534
6437 12:12:26.242030 Set Vref, RX VrefLevel [Byte0]: 54
6438 12:12:26.245939 [Byte1]: 59
6439 12:12:26.249151
6440 12:12:26.249662 Final RX Vref Byte 0 = 54 to rank0
6441 12:12:26.252175 Final RX Vref Byte 1 = 59 to rank0
6442 12:12:26.255471 Final RX Vref Byte 0 = 54 to rank1
6443 12:12:26.258702 Final RX Vref Byte 1 = 59 to rank1==
6444 12:12:26.262454 Dram Type= 6, Freq= 0, CH_0, rank 0
6445 12:12:26.268986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6446 12:12:26.269524 ==
6447 12:12:26.269855 DQS Delay:
6448 12:12:26.271938 DQS0 = 44, DQS1 = 60
6449 12:12:26.272405 DQM Delay:
6450 12:12:26.272754 DQM0 = 10, DQM1 = 16
6451 12:12:26.275181 DQ Delay:
6452 12:12:26.278747 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6453 12:12:26.281666 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6454 12:12:26.285459 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6455 12:12:26.288619 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6456 12:12:26.289129
6457 12:12:26.289618
6458 12:12:26.295880 [DQSOSCAuto] RK0, (LSB)MR18= 0x9084, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
6459 12:12:26.298434 CH0 RK0: MR19=C0C, MR18=9084
6460 12:12:26.305492 CH0_RK0: MR19=0xC0C, MR18=0x9084, DQSOSC=391, MR23=63, INC=386, DEC=257
6461 12:12:26.306039 ==
6462 12:12:26.308088 Dram Type= 6, Freq= 0, CH_0, rank 1
6463 12:12:26.312106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6464 12:12:26.312523 ==
6465 12:12:26.315223 [Gating] SW mode calibration
6466 12:12:26.321763 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6467 12:12:26.328361 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6468 12:12:26.331871 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6469 12:12:26.334604 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6470 12:12:26.341933 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6471 12:12:26.344753 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6472 12:12:26.348775 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 12:12:26.354347 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6474 12:12:26.357566 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 12:12:26.361124 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 12:12:26.367313 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6477 12:12:26.370836 Total UI for P1: 0, mck2ui 16
6478 12:12:26.374229 best dqsien dly found for B0: ( 0, 14, 24)
6479 12:12:26.377305 Total UI for P1: 0, mck2ui 16
6480 12:12:26.380704 best dqsien dly found for B1: ( 0, 14, 24)
6481 12:12:26.384095 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6482 12:12:26.387573 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6483 12:12:26.387988
6484 12:12:26.390778 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6485 12:12:26.394400 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6486 12:12:26.397200 [Gating] SW calibration Done
6487 12:12:26.397730 ==
6488 12:12:26.400385 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 12:12:26.403736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 12:12:26.404151 ==
6491 12:12:26.407293 RX Vref Scan: 0
6492 12:12:26.407765
6493 12:12:26.410298 RX Vref 0 -> 0, step: 1
6494 12:12:26.410710
6495 12:12:26.411035 RX Delay -410 -> 252, step: 16
6496 12:12:26.417776 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6497 12:12:26.420622 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6498 12:12:26.424001 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6499 12:12:26.430250 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6500 12:12:26.434565 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6501 12:12:26.437209 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6502 12:12:26.440234 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6503 12:12:26.447176 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6504 12:12:26.449800 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6505 12:12:26.453363 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6506 12:12:26.457142 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6507 12:12:26.463508 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6508 12:12:26.466902 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6509 12:12:26.470075 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6510 12:12:26.472699 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6511 12:12:26.479187 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6512 12:12:26.479746 ==
6513 12:12:26.482818 Dram Type= 6, Freq= 0, CH_0, rank 1
6514 12:12:26.486062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6515 12:12:26.486608 ==
6516 12:12:26.489192 DQS Delay:
6517 12:12:26.489627 DQS0 = 35, DQS1 = 59
6518 12:12:26.490071 DQM Delay:
6519 12:12:26.493152 DQM0 = 7, DQM1 = 17
6520 12:12:26.493688 DQ Delay:
6521 12:12:26.496039 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6522 12:12:26.499858 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6523 12:12:26.502867 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6524 12:12:26.506309 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6525 12:12:26.506720
6526 12:12:26.507047
6527 12:12:26.507348 ==
6528 12:12:26.509258 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 12:12:26.512719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 12:12:26.515741 ==
6531 12:12:26.516203
6532 12:12:26.516537
6533 12:12:26.516843 TX Vref Scan disable
6534 12:12:26.519155 == TX Byte 0 ==
6535 12:12:26.522572 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6536 12:12:26.525209 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6537 12:12:26.528788 == TX Byte 1 ==
6538 12:12:26.531702 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6539 12:12:26.535531 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6540 12:12:26.536046 ==
6541 12:12:26.538672 Dram Type= 6, Freq= 0, CH_0, rank 1
6542 12:12:26.545296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6543 12:12:26.545848 ==
6544 12:12:26.546224
6545 12:12:26.546532
6546 12:12:26.546863 TX Vref Scan disable
6547 12:12:26.548808 == TX Byte 0 ==
6548 12:12:26.552151 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6549 12:12:26.555118 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6550 12:12:26.558559 == TX Byte 1 ==
6551 12:12:26.562241 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6552 12:12:26.565176 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6553 12:12:26.565694
6554 12:12:26.568493 [DATLAT]
6555 12:12:26.568902 Freq=400, CH0 RK1
6556 12:12:26.569231
6557 12:12:26.571439 DATLAT Default: 0xe
6558 12:12:26.571852 0, 0xFFFF, sum = 0
6559 12:12:26.575316 1, 0xFFFF, sum = 0
6560 12:12:26.575878 2, 0xFFFF, sum = 0
6561 12:12:26.578182 3, 0xFFFF, sum = 0
6562 12:12:26.578599 4, 0xFFFF, sum = 0
6563 12:12:26.581675 5, 0xFFFF, sum = 0
6564 12:12:26.582202 6, 0xFFFF, sum = 0
6565 12:12:26.584765 7, 0xFFFF, sum = 0
6566 12:12:26.585183 8, 0xFFFF, sum = 0
6567 12:12:26.588086 9, 0xFFFF, sum = 0
6568 12:12:26.588532 10, 0xFFFF, sum = 0
6569 12:12:26.591995 11, 0xFFFF, sum = 0
6570 12:12:26.594908 12, 0xFFFF, sum = 0
6571 12:12:26.595503 13, 0x0, sum = 1
6572 12:12:26.598490 14, 0x0, sum = 2
6573 12:12:26.599062 15, 0x0, sum = 3
6574 12:12:26.599606 16, 0x0, sum = 4
6575 12:12:26.601477 best_step = 14
6576 12:12:26.601907
6577 12:12:26.602354 ==
6578 12:12:26.604596 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 12:12:26.608074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 12:12:26.608614 ==
6581 12:12:26.611166 RX Vref Scan: 0
6582 12:12:26.611759
6583 12:12:26.614397 RX Vref 0 -> 0, step: 1
6584 12:12:26.614829
6585 12:12:26.615266 RX Delay -359 -> 252, step: 8
6586 12:12:26.623009 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6587 12:12:26.627017 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6588 12:12:26.629547 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6589 12:12:26.635941 iDelay=209, Bit 3, Center -40 (-279 ~ 200) 480
6590 12:12:26.639722 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6591 12:12:26.643112 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6592 12:12:26.646616 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6593 12:12:26.652977 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6594 12:12:26.656077 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6595 12:12:26.659603 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6596 12:12:26.662284 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6597 12:12:26.668991 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6598 12:12:26.671997 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6599 12:12:26.675234 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6600 12:12:26.682222 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6601 12:12:26.685810 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6602 12:12:26.686352 ==
6603 12:12:26.688565 Dram Type= 6, Freq= 0, CH_0, rank 1
6604 12:12:26.692824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 12:12:26.693364 ==
6606 12:12:26.696142 DQS Delay:
6607 12:12:26.696677 DQS0 = 44, DQS1 = 60
6608 12:12:26.697123 DQM Delay:
6609 12:12:26.699448 DQM0 = 9, DQM1 = 15
6610 12:12:26.700001 DQ Delay:
6611 12:12:26.702634 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6612 12:12:26.705531 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6613 12:12:26.709102 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6614 12:12:26.711658 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6615 12:12:26.712095
6616 12:12:26.712533
6617 12:12:26.722029 [DQSOSCAuto] RK1, (LSB)MR18= 0x837a, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6618 12:12:26.722575 CH0 RK1: MR19=C0C, MR18=837A
6619 12:12:26.728172 CH0_RK1: MR19=0xC0C, MR18=0x837A, DQSOSC=393, MR23=63, INC=382, DEC=254
6620 12:12:26.732038 [RxdqsGatingPostProcess] freq 400
6621 12:12:26.738430 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6622 12:12:26.741838 best DQS0 dly(2T, 0.5T) = (0, 10)
6623 12:12:26.744659 best DQS1 dly(2T, 0.5T) = (0, 10)
6624 12:12:26.747982 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6625 12:12:26.751475 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6626 12:12:26.754451 best DQS0 dly(2T, 0.5T) = (0, 10)
6627 12:12:26.758049 best DQS1 dly(2T, 0.5T) = (0, 10)
6628 12:12:26.761647 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6629 12:12:26.764476 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6630 12:12:26.764991 Pre-setting of DQS Precalculation
6631 12:12:26.770994 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6632 12:12:26.771456 ==
6633 12:12:26.774315 Dram Type= 6, Freq= 0, CH_1, rank 0
6634 12:12:26.777699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 12:12:26.778173 ==
6636 12:12:26.784299 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6637 12:12:26.791122 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6638 12:12:26.794228 [CA 0] Center 36 (8~64) winsize 57
6639 12:12:26.797226 [CA 1] Center 36 (8~64) winsize 57
6640 12:12:26.800871 [CA 2] Center 36 (8~64) winsize 57
6641 12:12:26.803982 [CA 3] Center 36 (8~64) winsize 57
6642 12:12:26.807901 [CA 4] Center 36 (8~64) winsize 57
6643 12:12:26.808553 [CA 5] Center 36 (8~64) winsize 57
6644 12:12:26.810622
6645 12:12:26.813586 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6646 12:12:26.814003
6647 12:12:26.817111 [CATrainingPosCal] consider 1 rank data
6648 12:12:26.820698 u2DelayCellTimex100 = 270/100 ps
6649 12:12:26.823862 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 12:12:26.826790 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 12:12:26.830495 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 12:12:26.833698 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 12:12:26.836892 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 12:12:26.840030 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 12:12:26.840578
6656 12:12:26.846557 CA PerBit enable=1, Macro0, CA PI delay=36
6657 12:12:26.847141
6658 12:12:26.847537 [CBTSetCACLKResult] CA Dly = 36
6659 12:12:26.849809 CS Dly: 1 (0~32)
6660 12:12:26.850323 ==
6661 12:12:26.854005 Dram Type= 6, Freq= 0, CH_1, rank 1
6662 12:12:26.856110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 12:12:26.856534 ==
6664 12:12:26.863125 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6665 12:12:26.869226 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6666 12:12:26.872551 [CA 0] Center 36 (8~64) winsize 57
6667 12:12:26.876492 [CA 1] Center 36 (8~64) winsize 57
6668 12:12:26.879345 [CA 2] Center 36 (8~64) winsize 57
6669 12:12:26.882456 [CA 3] Center 36 (8~64) winsize 57
6670 12:12:26.886014 [CA 4] Center 36 (8~64) winsize 57
6671 12:12:26.886525 [CA 5] Center 36 (8~64) winsize 57
6672 12:12:26.889003
6673 12:12:26.892227 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6674 12:12:26.892643
6675 12:12:26.896015 [CATrainingPosCal] consider 2 rank data
6676 12:12:26.899567 u2DelayCellTimex100 = 270/100 ps
6677 12:12:26.902479 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 12:12:26.905595 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 12:12:26.910143 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 12:12:26.912245 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 12:12:26.915772 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 12:12:26.919449 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 12:12:26.919862
6684 12:12:26.922477 CA PerBit enable=1, Macro0, CA PI delay=36
6685 12:12:26.925160
6686 12:12:26.925575 [CBTSetCACLKResult] CA Dly = 36
6687 12:12:26.929300 CS Dly: 1 (0~32)
6688 12:12:26.929811
6689 12:12:26.931993 ----->DramcWriteLeveling(PI) begin...
6690 12:12:26.932413 ==
6691 12:12:26.935037 Dram Type= 6, Freq= 0, CH_1, rank 0
6692 12:12:26.938964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 12:12:26.939674 ==
6694 12:12:26.942172 Write leveling (Byte 0): 40 => 8
6695 12:12:26.945786 Write leveling (Byte 1): 40 => 8
6696 12:12:26.948878 DramcWriteLeveling(PI) end<-----
6697 12:12:26.949417
6698 12:12:26.949755 ==
6699 12:12:26.952752 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 12:12:26.955742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 12:12:26.956257 ==
6702 12:12:26.958381 [Gating] SW mode calibration
6703 12:12:26.965393 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6704 12:12:26.972005 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6705 12:12:26.975143 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6706 12:12:26.981625 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6707 12:12:26.984840 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6708 12:12:26.988221 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6709 12:12:26.994660 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6710 12:12:26.998088 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6711 12:12:27.001435 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6712 12:12:27.008120 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 12:12:27.011268 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6714 12:12:27.014375 Total UI for P1: 0, mck2ui 16
6715 12:12:27.018143 best dqsien dly found for B0: ( 0, 14, 24)
6716 12:12:27.021501 Total UI for P1: 0, mck2ui 16
6717 12:12:27.024079 best dqsien dly found for B1: ( 0, 14, 24)
6718 12:12:27.027589 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6719 12:12:27.031326 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6720 12:12:27.031889
6721 12:12:27.034310 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6722 12:12:27.040584 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6723 12:12:27.041112 [Gating] SW calibration Done
6724 12:12:27.041446 ==
6725 12:12:27.044002 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 12:12:27.050760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 12:12:27.051266 ==
6728 12:12:27.051666 RX Vref Scan: 0
6729 12:12:27.052032
6730 12:12:27.053814 RX Vref 0 -> 0, step: 1
6731 12:12:27.054225
6732 12:12:27.057652 RX Delay -410 -> 252, step: 16
6733 12:12:27.060389 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6734 12:12:27.063789 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6735 12:12:27.070298 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6736 12:12:27.073489 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6737 12:12:27.077236 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6738 12:12:27.080192 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6739 12:12:27.087200 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6740 12:12:27.090747 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6741 12:12:27.093278 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6742 12:12:27.096595 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6743 12:12:27.103255 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6744 12:12:27.106094 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6745 12:12:27.109368 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6746 12:12:27.116362 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6747 12:12:27.119548 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6748 12:12:27.123329 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6749 12:12:27.123925 ==
6750 12:12:27.125905 Dram Type= 6, Freq= 0, CH_1, rank 0
6751 12:12:27.133455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6752 12:12:27.133976 ==
6753 12:12:27.134311 DQS Delay:
6754 12:12:27.136633 DQS0 = 35, DQS1 = 51
6755 12:12:27.137150 DQM Delay:
6756 12:12:27.137586 DQM0 = 6, DQM1 = 13
6757 12:12:27.139650 DQ Delay:
6758 12:12:27.143030 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6759 12:12:27.143979 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6760 12:12:27.145682 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6761 12:12:27.148890 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6762 12:12:27.149302
6763 12:12:27.152334
6764 12:12:27.152745 ==
6765 12:12:27.155474 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 12:12:27.159034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 12:12:27.159804 ==
6768 12:12:27.160374
6769 12:12:27.160708
6770 12:12:27.162343 TX Vref Scan disable
6771 12:12:27.163032 == TX Byte 0 ==
6772 12:12:27.165319 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6773 12:12:27.171707 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6774 12:12:27.172426 == TX Byte 1 ==
6775 12:12:27.175488 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6776 12:12:27.181959 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6777 12:12:27.182375 ==
6778 12:12:27.184957 Dram Type= 6, Freq= 0, CH_1, rank 0
6779 12:12:27.188348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6780 12:12:27.188925 ==
6781 12:12:27.189260
6782 12:12:27.189570
6783 12:12:27.191928 TX Vref Scan disable
6784 12:12:27.192338 == TX Byte 0 ==
6785 12:12:27.198731 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6786 12:12:27.201467 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6787 12:12:27.201883 == TX Byte 1 ==
6788 12:12:27.208220 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6789 12:12:27.211641 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6790 12:12:27.212054
6791 12:12:27.212378 [DATLAT]
6792 12:12:27.215564 Freq=400, CH1 RK0
6793 12:12:27.216083
6794 12:12:27.216421 DATLAT Default: 0xf
6795 12:12:27.217784 0, 0xFFFF, sum = 0
6796 12:12:27.218204 1, 0xFFFF, sum = 0
6797 12:12:27.221440 2, 0xFFFF, sum = 0
6798 12:12:27.221958 3, 0xFFFF, sum = 0
6799 12:12:27.224377 4, 0xFFFF, sum = 0
6800 12:12:27.224796 5, 0xFFFF, sum = 0
6801 12:12:27.227964 6, 0xFFFF, sum = 0
6802 12:12:27.228415 7, 0xFFFF, sum = 0
6803 12:12:27.231488 8, 0xFFFF, sum = 0
6804 12:12:27.232004 9, 0xFFFF, sum = 0
6805 12:12:27.234397 10, 0xFFFF, sum = 0
6806 12:12:27.237920 11, 0xFFFF, sum = 0
6807 12:12:27.238427 12, 0xFFFF, sum = 0
6808 12:12:27.241358 13, 0x0, sum = 1
6809 12:12:27.241884 14, 0x0, sum = 2
6810 12:12:27.244539 15, 0x0, sum = 3
6811 12:12:27.245057 16, 0x0, sum = 4
6812 12:12:27.245396 best_step = 14
6813 12:12:27.245702
6814 12:12:27.247774 ==
6815 12:12:27.250902 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 12:12:27.254319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 12:12:27.254741 ==
6818 12:12:27.255070 RX Vref Scan: 1
6819 12:12:27.255415
6820 12:12:27.257481 RX Vref 0 -> 0, step: 1
6821 12:12:27.258075
6822 12:12:27.260755 RX Delay -343 -> 252, step: 8
6823 12:12:27.261378
6824 12:12:27.263947 Set Vref, RX VrefLevel [Byte0]: 52
6825 12:12:27.267239 [Byte1]: 51
6826 12:12:27.270979
6827 12:12:27.271535 Final RX Vref Byte 0 = 52 to rank0
6828 12:12:27.274198 Final RX Vref Byte 1 = 51 to rank0
6829 12:12:27.278054 Final RX Vref Byte 0 = 52 to rank1
6830 12:12:27.281038 Final RX Vref Byte 1 = 51 to rank1==
6831 12:12:27.284981 Dram Type= 6, Freq= 0, CH_1, rank 0
6832 12:12:27.291110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6833 12:12:27.291586 ==
6834 12:12:27.291923 DQS Delay:
6835 12:12:27.294298 DQS0 = 44, DQS1 = 52
6836 12:12:27.294710 DQM Delay:
6837 12:12:27.295039 DQM0 = 10, DQM1 = 10
6838 12:12:27.297503 DQ Delay:
6839 12:12:27.301205 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6840 12:12:27.304190 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6841 12:12:27.304708 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6842 12:12:27.307823 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6843 12:12:27.310416
6844 12:12:27.310828
6845 12:12:27.317147 [DQSOSCAuto] RK0, (LSB)MR18= 0x668e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 396 ps
6846 12:12:27.320539 CH1 RK0: MR19=C0C, MR18=668E
6847 12:12:27.326749 CH1_RK0: MR19=0xC0C, MR18=0x668E, DQSOSC=392, MR23=63, INC=384, DEC=256
6848 12:12:27.327175 ==
6849 12:12:27.330162 Dram Type= 6, Freq= 0, CH_1, rank 1
6850 12:12:27.333752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6851 12:12:27.334255 ==
6852 12:12:27.337052 [Gating] SW mode calibration
6853 12:12:27.343138 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6854 12:12:27.350062 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6855 12:12:27.353340 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6856 12:12:27.356627 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6857 12:12:27.363471 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6858 12:12:27.366744 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6859 12:12:27.370301 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6860 12:12:27.376316 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6861 12:12:27.379468 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6862 12:12:27.383402 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 12:12:27.389820 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6864 12:12:27.392861 Total UI for P1: 0, mck2ui 16
6865 12:12:27.396528 best dqsien dly found for B0: ( 0, 14, 24)
6866 12:12:27.397088 Total UI for P1: 0, mck2ui 16
6867 12:12:27.402849 best dqsien dly found for B1: ( 0, 14, 24)
6868 12:12:27.406206 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6869 12:12:27.409680 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6870 12:12:27.410196
6871 12:12:27.412633 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6872 12:12:27.416103 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6873 12:12:27.419607 [Gating] SW calibration Done
6874 12:12:27.420136 ==
6875 12:12:27.422618 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 12:12:27.425962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 12:12:27.426379 ==
6878 12:12:27.429406 RX Vref Scan: 0
6879 12:12:27.429922
6880 12:12:27.432505 RX Vref 0 -> 0, step: 1
6881 12:12:27.433115
6882 12:12:27.433456 RX Delay -410 -> 252, step: 16
6883 12:12:27.439250 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6884 12:12:27.442532 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6885 12:12:27.446045 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6886 12:12:27.451999 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6887 12:12:27.455164 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6888 12:12:27.458908 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6889 12:12:27.461916 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6890 12:12:27.469197 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6891 12:12:27.471997 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6892 12:12:27.475473 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6893 12:12:27.478615 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6894 12:12:27.485260 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6895 12:12:27.488757 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6896 12:12:27.491810 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6897 12:12:27.498015 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6898 12:12:27.501750 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6899 12:12:27.502166 ==
6900 12:12:27.504889 Dram Type= 6, Freq= 0, CH_1, rank 1
6901 12:12:27.507932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6902 12:12:27.508412 ==
6903 12:12:27.511265 DQS Delay:
6904 12:12:27.511751 DQS0 = 43, DQS1 = 51
6905 12:12:27.512118 DQM Delay:
6906 12:12:27.514746 DQM0 = 9, DQM1 = 14
6907 12:12:27.515201 DQ Delay:
6908 12:12:27.517918 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6909 12:12:27.521148 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6910 12:12:27.524436 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6911 12:12:27.528573 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6912 12:12:27.529109
6913 12:12:27.529450
6914 12:12:27.529785 ==
6915 12:12:27.531106 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 12:12:27.534237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 12:12:27.538033 ==
6918 12:12:27.538455
6919 12:12:27.538798
6920 12:12:27.539105 TX Vref Scan disable
6921 12:12:27.540921 == TX Byte 0 ==
6922 12:12:27.544010 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6923 12:12:27.547483 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6924 12:12:27.550934 == TX Byte 1 ==
6925 12:12:27.554127 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6926 12:12:27.557710 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6927 12:12:27.558231 ==
6928 12:12:27.560471 Dram Type= 6, Freq= 0, CH_1, rank 1
6929 12:12:27.567169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6930 12:12:27.567819 ==
6931 12:12:27.568179
6932 12:12:27.568494
6933 12:12:27.568789 TX Vref Scan disable
6934 12:12:27.570341 == TX Byte 0 ==
6935 12:12:27.574277 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6936 12:12:27.577210 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6937 12:12:27.580150 == TX Byte 1 ==
6938 12:12:27.583640 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6939 12:12:27.587630 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6940 12:12:27.588144
6941 12:12:27.590100 [DATLAT]
6942 12:12:27.590514 Freq=400, CH1 RK1
6943 12:12:27.590845
6944 12:12:27.593669 DATLAT Default: 0xe
6945 12:12:27.594188 0, 0xFFFF, sum = 0
6946 12:12:27.597131 1, 0xFFFF, sum = 0
6947 12:12:27.597654 2, 0xFFFF, sum = 0
6948 12:12:27.600297 3, 0xFFFF, sum = 0
6949 12:12:27.600913 4, 0xFFFF, sum = 0
6950 12:12:27.603293 5, 0xFFFF, sum = 0
6951 12:12:27.603745 6, 0xFFFF, sum = 0
6952 12:12:27.606721 7, 0xFFFF, sum = 0
6953 12:12:27.607137 8, 0xFFFF, sum = 0
6954 12:12:27.609835 9, 0xFFFF, sum = 0
6955 12:12:27.613369 10, 0xFFFF, sum = 0
6956 12:12:27.613893 11, 0xFFFF, sum = 0
6957 12:12:27.616399 12, 0xFFFF, sum = 0
6958 12:12:27.616868 13, 0x0, sum = 1
6959 12:12:27.620036 14, 0x0, sum = 2
6960 12:12:27.620455 15, 0x0, sum = 3
6961 12:12:27.623022 16, 0x0, sum = 4
6962 12:12:27.623577 best_step = 14
6963 12:12:27.623912
6964 12:12:27.624221 ==
6965 12:12:27.626346 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 12:12:27.629586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 12:12:27.630115 ==
6968 12:12:27.633268 RX Vref Scan: 0
6969 12:12:27.633784
6970 12:12:27.635964 RX Vref 0 -> 0, step: 1
6971 12:12:27.636377
6972 12:12:27.636707 RX Delay -343 -> 252, step: 8
6973 12:12:27.645271 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6974 12:12:27.648483 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6975 12:12:27.651923 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6976 12:12:27.658579 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6977 12:12:27.661996 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6978 12:12:27.665194 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6979 12:12:27.668026 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6980 12:12:27.675102 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6981 12:12:27.677825 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6982 12:12:27.681145 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6983 12:12:27.684469 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6984 12:12:27.690946 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6985 12:12:27.695315 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6986 12:12:27.698144 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6987 12:12:27.701117 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6988 12:12:27.707445 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6989 12:12:27.707923 ==
6990 12:12:27.710799 Dram Type= 6, Freq= 0, CH_1, rank 1
6991 12:12:27.714950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6992 12:12:27.715415 ==
6993 12:12:27.717870 DQS Delay:
6994 12:12:27.718281 DQS0 = 48, DQS1 = 52
6995 12:12:27.718607 DQM Delay:
6996 12:12:27.720655 DQM0 = 11, DQM1 = 11
6997 12:12:27.721071 DQ Delay:
6998 12:12:27.724372 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6999 12:12:27.727276 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
7000 12:12:27.730958 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7001 12:12:27.733888 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
7002 12:12:27.734299
7003 12:12:27.734626
7004 12:12:27.743692 [DQSOSCAuto] RK1, (LSB)MR18= 0x6aa2, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
7005 12:12:27.744224 CH1 RK1: MR19=C0C, MR18=6AA2
7006 12:12:27.750519 CH1_RK1: MR19=0xC0C, MR18=0x6AA2, DQSOSC=389, MR23=63, INC=390, DEC=260
7007 12:12:27.753445 [RxdqsGatingPostProcess] freq 400
7008 12:12:27.760119 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7009 12:12:27.763835 best DQS0 dly(2T, 0.5T) = (0, 10)
7010 12:12:27.766388 best DQS1 dly(2T, 0.5T) = (0, 10)
7011 12:12:27.769869 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7012 12:12:27.773142 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7013 12:12:27.777744 best DQS0 dly(2T, 0.5T) = (0, 10)
7014 12:12:27.780242 best DQS1 dly(2T, 0.5T) = (0, 10)
7015 12:12:27.783356 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7016 12:12:27.786470 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7017 12:12:27.786981 Pre-setting of DQS Precalculation
7018 12:12:27.793219 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7019 12:12:27.799740 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7020 12:12:27.806040 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7021 12:12:27.806525
7022 12:12:27.806858
7023 12:12:27.809351 [Calibration Summary] 800 Mbps
7024 12:12:27.813411 CH 0, Rank 0
7025 12:12:27.813827 SW Impedance : PASS
7026 12:12:27.816050 DUTY Scan : NO K
7027 12:12:27.819415 ZQ Calibration : PASS
7028 12:12:27.819924 Jitter Meter : NO K
7029 12:12:27.822764 CBT Training : PASS
7030 12:12:27.825841 Write leveling : PASS
7031 12:12:27.826259 RX DQS gating : PASS
7032 12:12:27.829940 RX DQ/DQS(RDDQC) : PASS
7033 12:12:27.832873 TX DQ/DQS : PASS
7034 12:12:27.833392 RX DATLAT : PASS
7035 12:12:27.836062 RX DQ/DQS(Engine): PASS
7036 12:12:27.836593 TX OE : NO K
7037 12:12:27.839156 All Pass.
7038 12:12:27.839599
7039 12:12:27.839932 CH 0, Rank 1
7040 12:12:27.842868 SW Impedance : PASS
7041 12:12:27.843418 DUTY Scan : NO K
7042 12:12:27.846311 ZQ Calibration : PASS
7043 12:12:27.849009 Jitter Meter : NO K
7044 12:12:27.849428 CBT Training : PASS
7045 12:12:27.852074 Write leveling : NO K
7046 12:12:27.855975 RX DQS gating : PASS
7047 12:12:27.856533 RX DQ/DQS(RDDQC) : PASS
7048 12:12:27.858683 TX DQ/DQS : PASS
7049 12:12:27.862664 RX DATLAT : PASS
7050 12:12:27.863111 RX DQ/DQS(Engine): PASS
7051 12:12:27.866184 TX OE : NO K
7052 12:12:27.866600 All Pass.
7053 12:12:27.866931
7054 12:12:27.868985 CH 1, Rank 0
7055 12:12:27.869401 SW Impedance : PASS
7056 12:12:27.872309 DUTY Scan : NO K
7057 12:12:27.875943 ZQ Calibration : PASS
7058 12:12:27.876360 Jitter Meter : NO K
7059 12:12:27.878732 CBT Training : PASS
7060 12:12:27.882038 Write leveling : PASS
7061 12:12:27.882456 RX DQS gating : PASS
7062 12:12:27.885657 RX DQ/DQS(RDDQC) : PASS
7063 12:12:27.888700 TX DQ/DQS : PASS
7064 12:12:27.889221 RX DATLAT : PASS
7065 12:12:27.891863 RX DQ/DQS(Engine): PASS
7066 12:12:27.895748 TX OE : NO K
7067 12:12:27.896240 All Pass.
7068 12:12:27.896572
7069 12:12:27.896882 CH 1, Rank 1
7070 12:12:27.898361 SW Impedance : PASS
7071 12:12:27.901748 DUTY Scan : NO K
7072 12:12:27.902239 ZQ Calibration : PASS
7073 12:12:27.905227 Jitter Meter : NO K
7074 12:12:27.909149 CBT Training : PASS
7075 12:12:27.909668 Write leveling : NO K
7076 12:12:27.911753 RX DQS gating : PASS
7077 12:12:27.915332 RX DQ/DQS(RDDQC) : PASS
7078 12:12:27.915869 TX DQ/DQS : PASS
7079 12:12:27.918446 RX DATLAT : PASS
7080 12:12:27.918862 RX DQ/DQS(Engine): PASS
7081 12:12:27.921550 TX OE : NO K
7082 12:12:27.921970 All Pass.
7083 12:12:27.922298
7084 12:12:27.925446 DramC Write-DBI off
7085 12:12:27.928422 PER_BANK_REFRESH: Hybrid Mode
7086 12:12:27.928841 TX_TRACKING: ON
7087 12:12:27.938145 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7088 12:12:27.941002 [FAST_K] Save calibration result to emmc
7089 12:12:27.944396 dramc_set_vcore_voltage set vcore to 725000
7090 12:12:27.947967 Read voltage for 1600, 0
7091 12:12:27.948387 Vio18 = 0
7092 12:12:27.951238 Vcore = 725000
7093 12:12:27.951786 Vdram = 0
7094 12:12:27.952121 Vddq = 0
7095 12:12:27.954202 Vmddr = 0
7096 12:12:27.957380 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7097 12:12:27.963998 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7098 12:12:27.964419 MEM_TYPE=3, freq_sel=13
7099 12:12:27.967116 sv_algorithm_assistance_LP4_3733
7100 12:12:27.973543 ============ PULL DRAM RESETB DOWN ============
7101 12:12:27.977516 ========== PULL DRAM RESETB DOWN end =========
7102 12:12:27.980252 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7103 12:12:27.983586 ===================================
7104 12:12:27.987132 LPDDR4 DRAM CONFIGURATION
7105 12:12:27.990464 ===================================
7106 12:12:27.994069 EX_ROW_EN[0] = 0x0
7107 12:12:27.994595 EX_ROW_EN[1] = 0x0
7108 12:12:27.997601 LP4Y_EN = 0x0
7109 12:12:27.998267 WORK_FSP = 0x1
7110 12:12:28.000870 WL = 0x5
7111 12:12:28.001282 RL = 0x5
7112 12:12:28.004106 BL = 0x2
7113 12:12:28.004642 RPST = 0x0
7114 12:12:28.007038 RD_PRE = 0x0
7115 12:12:28.007592 WR_PRE = 0x1
7116 12:12:28.010355 WR_PST = 0x1
7117 12:12:28.010898 DBI_WR = 0x0
7118 12:12:28.013458 DBI_RD = 0x0
7119 12:12:28.013985 OTF = 0x1
7120 12:12:28.016877 ===================================
7121 12:12:28.020090 ===================================
7122 12:12:28.024045 ANA top config
7123 12:12:28.027174 ===================================
7124 12:12:28.030327 DLL_ASYNC_EN = 0
7125 12:12:28.030846 ALL_SLAVE_EN = 0
7126 12:12:28.033392 NEW_RANK_MODE = 1
7127 12:12:28.036239 DLL_IDLE_MODE = 1
7128 12:12:28.040127 LP45_APHY_COMB_EN = 1
7129 12:12:28.043271 TX_ODT_DIS = 0
7130 12:12:28.043910 NEW_8X_MODE = 1
7131 12:12:28.046229 ===================================
7132 12:12:28.049333 ===================================
7133 12:12:28.053468 data_rate = 3200
7134 12:12:28.056184 CKR = 1
7135 12:12:28.059757 DQ_P2S_RATIO = 8
7136 12:12:28.063281 ===================================
7137 12:12:28.066144 CA_P2S_RATIO = 8
7138 12:12:28.069382 DQ_CA_OPEN = 0
7139 12:12:28.069797 DQ_SEMI_OPEN = 0
7140 12:12:28.072917 CA_SEMI_OPEN = 0
7141 12:12:28.076208 CA_FULL_RATE = 0
7142 12:12:28.079188 DQ_CKDIV4_EN = 0
7143 12:12:28.082379 CA_CKDIV4_EN = 0
7144 12:12:28.085845 CA_PREDIV_EN = 0
7145 12:12:28.086415 PH8_DLY = 12
7146 12:12:28.089140 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7147 12:12:28.092715 DQ_AAMCK_DIV = 4
7148 12:12:28.095894 CA_AAMCK_DIV = 4
7149 12:12:28.099260 CA_ADMCK_DIV = 4
7150 12:12:28.102570 DQ_TRACK_CA_EN = 0
7151 12:12:28.105960 CA_PICK = 1600
7152 12:12:28.106396 CA_MCKIO = 1600
7153 12:12:28.109103 MCKIO_SEMI = 0
7154 12:12:28.112670 PLL_FREQ = 3068
7155 12:12:28.115244 DQ_UI_PI_RATIO = 32
7156 12:12:28.118553 CA_UI_PI_RATIO = 0
7157 12:12:28.122241 ===================================
7158 12:12:28.125157 ===================================
7159 12:12:28.128723 memory_type:LPDDR4
7160 12:12:28.129138 GP_NUM : 10
7161 12:12:28.131798 SRAM_EN : 1
7162 12:12:28.135501 MD32_EN : 0
7163 12:12:28.138589 ===================================
7164 12:12:28.139104 [ANA_INIT] >>>>>>>>>>>>>>
7165 12:12:28.142265 <<<<<< [CONFIGURE PHASE]: ANA_TX
7166 12:12:28.145186 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7167 12:12:28.148922 ===================================
7168 12:12:28.152132 data_rate = 3200,PCW = 0X7600
7169 12:12:28.155571 ===================================
7170 12:12:28.158413 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7171 12:12:28.164656 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7172 12:12:28.168092 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7173 12:12:28.174584 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7174 12:12:28.178266 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7175 12:12:28.181347 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7176 12:12:28.184729 [ANA_INIT] flow start
7177 12:12:28.185319 [ANA_INIT] PLL >>>>>>>>
7178 12:12:28.187929 [ANA_INIT] PLL <<<<<<<<
7179 12:12:28.191360 [ANA_INIT] MIDPI >>>>>>>>
7180 12:12:28.191957 [ANA_INIT] MIDPI <<<<<<<<
7181 12:12:28.195203 [ANA_INIT] DLL >>>>>>>>
7182 12:12:28.197899 [ANA_INIT] DLL <<<<<<<<
7183 12:12:28.198543 [ANA_INIT] flow end
7184 12:12:28.204511 ============ LP4 DIFF to SE enter ============
7185 12:12:28.207469 ============ LP4 DIFF to SE exit ============
7186 12:12:28.211158 [ANA_INIT] <<<<<<<<<<<<<
7187 12:12:28.214328 [Flow] Enable top DCM control >>>>>
7188 12:12:28.217302 [Flow] Enable top DCM control <<<<<
7189 12:12:28.217717 Enable DLL master slave shuffle
7190 12:12:28.224266 ==============================================================
7191 12:12:28.226837 Gating Mode config
7192 12:12:28.230471 ==============================================================
7193 12:12:28.233850 Config description:
7194 12:12:28.243775 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7195 12:12:28.249899 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7196 12:12:28.253457 SELPH_MODE 0: By rank 1: By Phase
7197 12:12:28.260159 ==============================================================
7198 12:12:28.263009 GAT_TRACK_EN = 1
7199 12:12:28.266627 RX_GATING_MODE = 2
7200 12:12:28.269884 RX_GATING_TRACK_MODE = 2
7201 12:12:28.273403 SELPH_MODE = 1
7202 12:12:28.276521 PICG_EARLY_EN = 1
7203 12:12:28.280200 VALID_LAT_VALUE = 1
7204 12:12:28.282809 ==============================================================
7205 12:12:28.286055 Enter into Gating configuration >>>>
7206 12:12:28.289576 Exit from Gating configuration <<<<
7207 12:12:28.292758 Enter into DVFS_PRE_config >>>>>
7208 12:12:28.306092 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7209 12:12:28.306517 Exit from DVFS_PRE_config <<<<<
7210 12:12:28.309500 Enter into PICG configuration >>>>
7211 12:12:28.312682 Exit from PICG configuration <<<<
7212 12:12:28.315757 [RX_INPUT] configuration >>>>>
7213 12:12:28.318897 [RX_INPUT] configuration <<<<<
7214 12:12:28.325690 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7215 12:12:28.328754 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7216 12:12:28.335527 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7217 12:12:28.342399 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7218 12:12:28.348989 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7219 12:12:28.355276 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7220 12:12:28.358542 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7221 12:12:28.361895 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7222 12:12:28.368661 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7223 12:12:28.371838 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7224 12:12:28.374827 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7225 12:12:28.378443 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7226 12:12:28.381730 ===================================
7227 12:12:28.385757 LPDDR4 DRAM CONFIGURATION
7228 12:12:28.388081 ===================================
7229 12:12:28.391410 EX_ROW_EN[0] = 0x0
7230 12:12:28.391831 EX_ROW_EN[1] = 0x0
7231 12:12:28.394774 LP4Y_EN = 0x0
7232 12:12:28.395291 WORK_FSP = 0x1
7233 12:12:28.398457 WL = 0x5
7234 12:12:28.398980 RL = 0x5
7235 12:12:28.401475 BL = 0x2
7236 12:12:28.401993 RPST = 0x0
7237 12:12:28.404536 RD_PRE = 0x0
7238 12:12:28.408199 WR_PRE = 0x1
7239 12:12:28.408719 WR_PST = 0x1
7240 12:12:28.411209 DBI_WR = 0x0
7241 12:12:28.411758 DBI_RD = 0x0
7242 12:12:28.414693 OTF = 0x1
7243 12:12:28.417971 ===================================
7244 12:12:28.421610 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7245 12:12:28.424294 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7246 12:12:28.427707 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7247 12:12:28.431401 ===================================
7248 12:12:28.434258 LPDDR4 DRAM CONFIGURATION
7249 12:12:28.437265 ===================================
7250 12:12:28.441060 EX_ROW_EN[0] = 0x10
7251 12:12:28.441583 EX_ROW_EN[1] = 0x0
7252 12:12:28.444506 LP4Y_EN = 0x0
7253 12:12:28.445141 WORK_FSP = 0x1
7254 12:12:28.447291 WL = 0x5
7255 12:12:28.450494 RL = 0x5
7256 12:12:28.450917 BL = 0x2
7257 12:12:28.453837 RPST = 0x0
7258 12:12:28.454353 RD_PRE = 0x0
7259 12:12:28.457058 WR_PRE = 0x1
7260 12:12:28.457474 WR_PST = 0x1
7261 12:12:28.460611 DBI_WR = 0x0
7262 12:12:28.461027 DBI_RD = 0x0
7263 12:12:28.463853 OTF = 0x1
7264 12:12:28.466786 ===================================
7265 12:12:28.474194 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7266 12:12:28.474708 ==
7267 12:12:28.477252 Dram Type= 6, Freq= 0, CH_0, rank 0
7268 12:12:28.480079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7269 12:12:28.480499 ==
7270 12:12:28.483184 [Duty_Offset_Calibration]
7271 12:12:28.483634 B0:2 B1:0 CA:4
7272 12:12:28.483968
7273 12:12:28.487046 [DutyScan_Calibration_Flow] k_type=0
7274 12:12:28.496363
7275 12:12:28.496877 ==CLK 0==
7276 12:12:28.500314 Final CLK duty delay cell = -4
7277 12:12:28.503470 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7278 12:12:28.506604 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7279 12:12:28.509614 [-4] AVG Duty = 4922%(X100)
7280 12:12:28.510033
7281 12:12:28.513361 CH0 CLK Duty spec in!! Max-Min= 218%
7282 12:12:28.516128 [DutyScan_Calibration_Flow] ====Done====
7283 12:12:28.516651
7284 12:12:28.519859 [DutyScan_Calibration_Flow] k_type=1
7285 12:12:28.536687
7286 12:12:28.537271 ==DQS 0 ==
7287 12:12:28.540295 Final DQS duty delay cell = 0
7288 12:12:28.543564 [0] MAX Duty = 5218%(X100), DQS PI = 20
7289 12:12:28.546486 [0] MIN Duty = 5093%(X100), DQS PI = 8
7290 12:12:28.550077 [0] AVG Duty = 5155%(X100)
7291 12:12:28.550641
7292 12:12:28.551005 ==DQS 1 ==
7293 12:12:28.553382 Final DQS duty delay cell = 0
7294 12:12:28.556229 [0] MAX Duty = 5187%(X100), DQS PI = 2
7295 12:12:28.560006 [0] MIN Duty = 4969%(X100), DQS PI = 10
7296 12:12:28.563396 [0] AVG Duty = 5078%(X100)
7297 12:12:28.563863
7298 12:12:28.566211 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7299 12:12:28.566765
7300 12:12:28.569984 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7301 12:12:28.572751 [DutyScan_Calibration_Flow] ====Done====
7302 12:12:28.573285
7303 12:12:28.576042 [DutyScan_Calibration_Flow] k_type=3
7304 12:12:28.593760
7305 12:12:28.594292 ==DQM 0 ==
7306 12:12:28.597169 Final DQM duty delay cell = 0
7307 12:12:28.600581 [0] MAX Duty = 5124%(X100), DQS PI = 20
7308 12:12:28.603287 [0] MIN Duty = 4875%(X100), DQS PI = 52
7309 12:12:28.606962 [0] AVG Duty = 4999%(X100)
7310 12:12:28.607424
7311 12:12:28.607773 ==DQM 1 ==
7312 12:12:28.610616 Final DQM duty delay cell = 0
7313 12:12:28.614399 [0] MAX Duty = 5000%(X100), DQS PI = 4
7314 12:12:28.616723 [0] MIN Duty = 4844%(X100), DQS PI = 10
7315 12:12:28.620104 [0] AVG Duty = 4922%(X100)
7316 12:12:28.620615
7317 12:12:28.623738 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7318 12:12:28.624254
7319 12:12:28.626806 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7320 12:12:28.629927 [DutyScan_Calibration_Flow] ====Done====
7321 12:12:28.630408
7322 12:12:28.633079 [DutyScan_Calibration_Flow] k_type=2
7323 12:12:28.651187
7324 12:12:28.651790 ==DQ 0 ==
7325 12:12:28.654109 Final DQ duty delay cell = 0
7326 12:12:28.658001 [0] MAX Duty = 5156%(X100), DQS PI = 22
7327 12:12:28.660730 [0] MIN Duty = 4969%(X100), DQS PI = 10
7328 12:12:28.664191 [0] AVG Duty = 5062%(X100)
7329 12:12:28.664619
7330 12:12:28.664956 ==DQ 1 ==
7331 12:12:28.667639 Final DQ duty delay cell = 0
7332 12:12:28.670793 [0] MAX Duty = 5187%(X100), DQS PI = 2
7333 12:12:28.673895 [0] MIN Duty = 4907%(X100), DQS PI = 34
7334 12:12:28.674319 [0] AVG Duty = 5047%(X100)
7335 12:12:28.676958
7336 12:12:28.680393 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7337 12:12:28.680815
7338 12:12:28.683729 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7339 12:12:28.687121 [DutyScan_Calibration_Flow] ====Done====
7340 12:12:28.687581 ==
7341 12:12:28.690553 Dram Type= 6, Freq= 0, CH_1, rank 0
7342 12:12:28.693746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7343 12:12:28.694215 ==
7344 12:12:28.696825 [Duty_Offset_Calibration]
7345 12:12:28.697456 B0:0 B1:-1 CA:3
7346 12:12:28.697962
7347 12:12:28.700259 [DutyScan_Calibration_Flow] k_type=0
7348 12:12:28.710144
7349 12:12:28.710769 ==CLK 0==
7350 12:12:28.713314 Final CLK duty delay cell = -4
7351 12:12:28.717607 [-4] MAX Duty = 5000%(X100), DQS PI = 6
7352 12:12:28.720142 [-4] MIN Duty = 4875%(X100), DQS PI = 10
7353 12:12:28.723209 [-4] AVG Duty = 4937%(X100)
7354 12:12:28.723783
7355 12:12:28.726781 CH1 CLK Duty spec in!! Max-Min= 125%
7356 12:12:28.730237 [DutyScan_Calibration_Flow] ====Done====
7357 12:12:28.730770
7358 12:12:28.733714 [DutyScan_Calibration_Flow] k_type=1
7359 12:12:28.749173
7360 12:12:28.749587 ==DQS 0 ==
7361 12:12:28.753021 Final DQS duty delay cell = 0
7362 12:12:28.756431 [0] MAX Duty = 5250%(X100), DQS PI = 30
7363 12:12:28.759312 [0] MIN Duty = 4938%(X100), DQS PI = 56
7364 12:12:28.763007 [0] AVG Duty = 5094%(X100)
7365 12:12:28.763473
7366 12:12:28.763814 ==DQS 1 ==
7367 12:12:28.766195 Final DQS duty delay cell = -4
7368 12:12:28.769053 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7369 12:12:28.772751 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7370 12:12:28.775840 [-4] AVG Duty = 4906%(X100)
7371 12:12:28.776372
7372 12:12:28.778985 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7373 12:12:28.779650
7374 12:12:28.782409 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7375 12:12:28.785398 [DutyScan_Calibration_Flow] ====Done====
7376 12:12:28.785818
7377 12:12:28.788947 [DutyScan_Calibration_Flow] k_type=3
7378 12:12:28.806515
7379 12:12:28.807062 ==DQM 0 ==
7380 12:12:28.810037 Final DQM duty delay cell = 0
7381 12:12:28.813332 [0] MAX Duty = 5062%(X100), DQS PI = 32
7382 12:12:28.816945 [0] MIN Duty = 4782%(X100), DQS PI = 38
7383 12:12:28.819682 [0] AVG Duty = 4922%(X100)
7384 12:12:28.820209
7385 12:12:28.820548 ==DQM 1 ==
7386 12:12:28.823214 Final DQM duty delay cell = 0
7387 12:12:28.826662 [0] MAX Duty = 5000%(X100), DQS PI = 32
7388 12:12:28.829934 [0] MIN Duty = 4813%(X100), DQS PI = 0
7389 12:12:28.833115 [0] AVG Duty = 4906%(X100)
7390 12:12:28.833548
7391 12:12:28.836646 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7392 12:12:28.837080
7393 12:12:28.840190 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7394 12:12:28.843152 [DutyScan_Calibration_Flow] ====Done====
7395 12:12:28.843693
7396 12:12:28.846776 [DutyScan_Calibration_Flow] k_type=2
7397 12:12:28.863190
7398 12:12:28.863717 ==DQ 0 ==
7399 12:12:28.866458 Final DQ duty delay cell = -4
7400 12:12:28.869485 [-4] MAX Duty = 4938%(X100), DQS PI = 0
7401 12:12:28.872766 [-4] MIN Duty = 4813%(X100), DQS PI = 22
7402 12:12:28.875965 [-4] AVG Duty = 4875%(X100)
7403 12:12:28.876404
7404 12:12:28.876871 ==DQ 1 ==
7405 12:12:28.879530 Final DQ duty delay cell = 0
7406 12:12:28.882445 [0] MAX Duty = 5062%(X100), DQS PI = 32
7407 12:12:28.885979 [0] MIN Duty = 4875%(X100), DQS PI = 58
7408 12:12:28.889252 [0] AVG Duty = 4968%(X100)
7409 12:12:28.889811
7410 12:12:28.892178 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7411 12:12:28.892598
7412 12:12:28.895411 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7413 12:12:28.899100 [DutyScan_Calibration_Flow] ====Done====
7414 12:12:28.902361 nWR fixed to 30
7415 12:12:28.905739 [ModeRegInit_LP4] CH0 RK0
7416 12:12:28.906326 [ModeRegInit_LP4] CH0 RK1
7417 12:12:28.909145 [ModeRegInit_LP4] CH1 RK0
7418 12:12:28.911928 [ModeRegInit_LP4] CH1 RK1
7419 12:12:28.912444 match AC timing 5
7420 12:12:28.918725 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7421 12:12:28.922317 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7422 12:12:28.925742 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7423 12:12:28.932296 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7424 12:12:28.935119 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7425 12:12:28.938324 [MiockJmeterHQA]
7426 12:12:28.938744
7427 12:12:28.941877 [DramcMiockJmeter] u1RxGatingPI = 0
7428 12:12:28.942401 0 : 4252, 4027
7429 12:12:28.942747 4 : 4363, 4137
7430 12:12:28.945189 8 : 4252, 4027
7431 12:12:28.945617 12 : 4252, 4027
7432 12:12:28.948259 16 : 4252, 4027
7433 12:12:28.948969 20 : 4253, 4027
7434 12:12:28.952012 24 : 4363, 4137
7435 12:12:28.952482 28 : 4252, 4027
7436 12:12:28.954674 32 : 4361, 4137
7437 12:12:28.955205 36 : 4253, 4026
7438 12:12:28.955633 40 : 4249, 4027
7439 12:12:28.958248 44 : 4250, 4026
7440 12:12:28.958674 48 : 4252, 4029
7441 12:12:28.961395 52 : 4249, 4027
7442 12:12:28.961948 56 : 4250, 4027
7443 12:12:28.965027 60 : 4363, 4140
7444 12:12:28.965453 64 : 4250, 4026
7445 12:12:28.968236 68 : 4252, 4030
7446 12:12:28.968665 72 : 4249, 4027
7447 12:12:28.969009 76 : 4361, 4137
7448 12:12:28.970903 80 : 4250, 4027
7449 12:12:28.971328 84 : 4360, 4137
7450 12:12:28.974630 88 : 4253, 4029
7451 12:12:28.975160 92 : 4250, 4027
7452 12:12:28.977929 96 : 4250, 3277
7453 12:12:28.978364 100 : 4252, 0
7454 12:12:28.978733 104 : 4250, 0
7455 12:12:28.980954 108 : 4250, 0
7456 12:12:28.981383 112 : 4250, 0
7457 12:12:28.984335 116 : 4250, 0
7458 12:12:28.984764 120 : 4250, 0
7459 12:12:28.985135 124 : 4253, 0
7460 12:12:28.987833 128 : 4252, 0
7461 12:12:28.988260 132 : 4361, 0
7462 12:12:28.991143 136 : 4360, 0
7463 12:12:28.991622 140 : 4363, 0
7464 12:12:28.991968 144 : 4250, 0
7465 12:12:28.994235 148 : 4250, 0
7466 12:12:28.994661 152 : 4250, 0
7467 12:12:28.997835 156 : 4250, 0
7468 12:12:28.998380 160 : 4249, 0
7469 12:12:28.998730 164 : 4250, 0
7470 12:12:29.000828 168 : 4252, 0
7471 12:12:29.001297 172 : 4250, 0
7472 12:12:29.004118 176 : 4250, 0
7473 12:12:29.004615 180 : 4252, 0
7474 12:12:29.005100 184 : 4363, 0
7475 12:12:29.007607 188 : 4360, 0
7476 12:12:29.008034 192 : 4363, 0
7477 12:12:29.008373 196 : 4250, 0
7478 12:12:29.011042 200 : 4250, 0
7479 12:12:29.011605 204 : 4250, 0
7480 12:12:29.014100 208 : 4250, 0
7481 12:12:29.014621 212 : 4250, 0
7482 12:12:29.014964 216 : 4250, 0
7483 12:12:29.017181 220 : 4252, 339
7484 12:12:29.017611 224 : 4360, 4023
7485 12:12:29.021177 228 : 4252, 4030
7486 12:12:29.021731 232 : 4250, 4026
7487 12:12:29.024157 236 : 4250, 4027
7488 12:12:29.024586 240 : 4252, 4029
7489 12:12:29.027971 244 : 4249, 4027
7490 12:12:29.028573 248 : 4250, 4026
7491 12:12:29.030765 252 : 4250, 4027
7492 12:12:29.031297 256 : 4252, 4030
7493 12:12:29.034544 260 : 4249, 4027
7494 12:12:29.035074 264 : 4361, 4138
7495 12:12:29.035470 268 : 4361, 4137
7496 12:12:29.037319 272 : 4250, 4027
7497 12:12:29.037822 276 : 4363, 4140
7498 12:12:29.040952 280 : 4361, 4137
7499 12:12:29.041483 284 : 4250, 4026
7500 12:12:29.044290 288 : 4250, 4027
7501 12:12:29.044816 292 : 4252, 4030
7502 12:12:29.046893 296 : 4250, 4026
7503 12:12:29.047469 300 : 4250, 4026
7504 12:12:29.050634 304 : 4250, 4027
7505 12:12:29.051060 308 : 4252, 4030
7506 12:12:29.053697 312 : 4250, 4027
7507 12:12:29.054229 316 : 4361, 4137
7508 12:12:29.057171 320 : 4361, 4137
7509 12:12:29.057754 324 : 4250, 4027
7510 12:12:29.060304 328 : 4363, 4140
7511 12:12:29.060769 332 : 4361, 4108
7512 12:12:29.063495 336 : 4250, 2058
7513 12:12:29.064061
7514 12:12:29.064407 MIOCK jitter meter ch=0
7515 12:12:29.064755
7516 12:12:29.066823 1T = (336-100) = 236 dly cells
7517 12:12:29.073817 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7518 12:12:29.074349 ==
7519 12:12:29.076655 Dram Type= 6, Freq= 0, CH_0, rank 0
7520 12:12:29.079978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7521 12:12:29.080425 ==
7522 12:12:29.087070 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7523 12:12:29.090131 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7524 12:12:29.092929 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7525 12:12:29.100072 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7526 12:12:29.109791 [CA 0] Center 44 (14~74) winsize 61
7527 12:12:29.113017 [CA 1] Center 43 (13~74) winsize 62
7528 12:12:29.116379 [CA 2] Center 39 (10~68) winsize 59
7529 12:12:29.119628 [CA 3] Center 38 (9~68) winsize 60
7530 12:12:29.122796 [CA 4] Center 36 (7~66) winsize 60
7531 12:12:29.125789 [CA 5] Center 36 (6~66) winsize 61
7532 12:12:29.126325
7533 12:12:29.129475 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7534 12:12:29.129991
7535 12:12:29.136335 [CATrainingPosCal] consider 1 rank data
7536 12:12:29.136870 u2DelayCellTimex100 = 275/100 ps
7537 12:12:29.142526 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7538 12:12:29.145836 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7539 12:12:29.149606 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7540 12:12:29.152107 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7541 12:12:29.155755 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7542 12:12:29.158850 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7543 12:12:29.159303
7544 12:12:29.162695 CA PerBit enable=1, Macro0, CA PI delay=36
7545 12:12:29.163244
7546 12:12:29.165676 [CBTSetCACLKResult] CA Dly = 36
7547 12:12:29.168682 CS Dly: 11 (0~42)
7548 12:12:29.172133 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7549 12:12:29.175296 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7550 12:12:29.175931 ==
7551 12:12:29.178439 Dram Type= 6, Freq= 0, CH_0, rank 1
7552 12:12:29.185235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7553 12:12:29.185693 ==
7554 12:12:29.188435 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7555 12:12:29.194907 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7556 12:12:29.198290 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7557 12:12:29.205214 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7558 12:12:29.213335 [CA 0] Center 44 (14~74) winsize 61
7559 12:12:29.216611 [CA 1] Center 43 (13~74) winsize 62
7560 12:12:29.219590 [CA 2] Center 38 (9~68) winsize 60
7561 12:12:29.223203 [CA 3] Center 38 (9~68) winsize 60
7562 12:12:29.226576 [CA 4] Center 37 (7~67) winsize 61
7563 12:12:29.229822 [CA 5] Center 36 (7~66) winsize 60
7564 12:12:29.230447
7565 12:12:29.233181 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7566 12:12:29.233873
7567 12:12:29.236350 [CATrainingPosCal] consider 2 rank data
7568 12:12:29.239757 u2DelayCellTimex100 = 275/100 ps
7569 12:12:29.245725 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7570 12:12:29.249432 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7571 12:12:29.252892 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7572 12:12:29.256845 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7573 12:12:29.259466 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7574 12:12:29.262632 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7575 12:12:29.263153
7576 12:12:29.266280 CA PerBit enable=1, Macro0, CA PI delay=36
7577 12:12:29.266808
7578 12:12:29.269278 [CBTSetCACLKResult] CA Dly = 36
7579 12:12:29.272137 CS Dly: 12 (0~44)
7580 12:12:29.275571 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7581 12:12:29.278926 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7582 12:12:29.279347
7583 12:12:29.282514 ----->DramcWriteLeveling(PI) begin...
7584 12:12:29.285781 ==
7585 12:12:29.286240 Dram Type= 6, Freq= 0, CH_0, rank 0
7586 12:12:29.291938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7587 12:12:29.292392 ==
7588 12:12:29.295260 Write leveling (Byte 0): 35 => 35
7589 12:12:29.298691 Write leveling (Byte 1): 25 => 25
7590 12:12:29.301883 DramcWriteLeveling(PI) end<-----
7591 12:12:29.302472
7592 12:12:29.302944 ==
7593 12:12:29.305868 Dram Type= 6, Freq= 0, CH_0, rank 0
7594 12:12:29.308346 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7595 12:12:29.308773 ==
7596 12:12:29.311571 [Gating] SW mode calibration
7597 12:12:29.318361 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7598 12:12:29.324903 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7599 12:12:29.328241 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 12:12:29.331600 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 12:12:29.338377 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 12:12:29.341472 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
7603 12:12:29.344359 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7604 12:12:29.351692 1 4 20 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
7605 12:12:29.354607 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7606 12:12:29.357918 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7607 12:12:29.365109 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7608 12:12:29.367501 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7609 12:12:29.371113 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7610 12:12:29.377321 1 5 12 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
7611 12:12:29.381201 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7612 12:12:29.384044 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
7613 12:12:29.390804 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 12:12:29.394107 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7615 12:12:29.397494 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 12:12:29.403863 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 12:12:29.407162 1 6 8 | B1->B0 | 2323 3332 | 0 1 | (0 0) (1 1)
7618 12:12:29.410503 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (1 1)
7619 12:12:29.417299 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7620 12:12:29.420622 1 6 20 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
7621 12:12:29.423495 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7622 12:12:29.430678 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 12:12:29.433339 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 12:12:29.437313 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 12:12:29.443434 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 12:12:29.446788 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7627 12:12:29.450331 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7628 12:12:29.456445 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7629 12:12:29.459836 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7630 12:12:29.463475 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 12:12:29.469692 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 12:12:29.473015 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 12:12:29.476701 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 12:12:29.482715 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 12:12:29.486271 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 12:12:29.489714 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 12:12:29.496006 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 12:12:29.500048 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 12:12:29.502871 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 12:12:29.509153 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7641 12:12:29.512795 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7642 12:12:29.516088 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7643 12:12:29.522305 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7644 12:12:29.522791 Total UI for P1: 0, mck2ui 16
7645 12:12:29.529569 best dqsien dly found for B0: ( 1, 9, 8)
7646 12:12:29.532616 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7647 12:12:29.536002 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7648 12:12:29.542148 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 12:12:29.542572 Total UI for P1: 0, mck2ui 16
7650 12:12:29.549025 best dqsien dly found for B1: ( 1, 9, 22)
7651 12:12:29.552088 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7652 12:12:29.556016 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7653 12:12:29.556439
7654 12:12:29.558715 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7655 12:12:29.562312 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7656 12:12:29.565576 [Gating] SW calibration Done
7657 12:12:29.566093 ==
7658 12:12:29.568504 Dram Type= 6, Freq= 0, CH_0, rank 0
7659 12:12:29.571880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7660 12:12:29.572304 ==
7661 12:12:29.575004 RX Vref Scan: 0
7662 12:12:29.575465
7663 12:12:29.575811 RX Vref 0 -> 0, step: 1
7664 12:12:29.576128
7665 12:12:29.578832 RX Delay 0 -> 252, step: 8
7666 12:12:29.581648 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7667 12:12:29.588715 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7668 12:12:29.592000 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7669 12:12:29.594875 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7670 12:12:29.598499 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7671 12:12:29.601972 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7672 12:12:29.608110 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7673 12:12:29.611349 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7674 12:12:29.614581 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7675 12:12:29.618551 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7676 12:12:29.621722 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7677 12:12:29.627750 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7678 12:12:29.631249 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7679 12:12:29.634703 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7680 12:12:29.637995 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7681 12:12:29.644564 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7682 12:12:29.645055 ==
7683 12:12:29.647666 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 12:12:29.650988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 12:12:29.651509 ==
7686 12:12:29.651855 DQS Delay:
7687 12:12:29.653828 DQS0 = 0, DQS1 = 0
7688 12:12:29.654380 DQM Delay:
7689 12:12:29.657648 DQM0 = 131, DQM1 = 127
7690 12:12:29.658070 DQ Delay:
7691 12:12:29.660501 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7692 12:12:29.663771 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7693 12:12:29.667704 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
7694 12:12:29.670631 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7695 12:12:29.673943
7696 12:12:29.674363
7697 12:12:29.674696 ==
7698 12:12:29.677471 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 12:12:29.680287 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 12:12:29.680711 ==
7701 12:12:29.681054
7702 12:12:29.681361
7703 12:12:29.684024 TX Vref Scan disable
7704 12:12:29.684440 == TX Byte 0 ==
7705 12:12:29.690592 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7706 12:12:29.693984 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7707 12:12:29.694402 == TX Byte 1 ==
7708 12:12:29.700349 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7709 12:12:29.703904 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7710 12:12:29.704323 ==
7711 12:12:29.707173 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 12:12:29.710505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 12:12:29.710922 ==
7714 12:12:29.725035
7715 12:12:29.728274 TX Vref early break, caculate TX vref
7716 12:12:29.731561 TX Vref=16, minBit 12, minWin=21, winSum=365
7717 12:12:29.735263 TX Vref=18, minBit 0, minWin=23, winSum=376
7718 12:12:29.738102 TX Vref=20, minBit 1, minWin=23, winSum=386
7719 12:12:29.741830 TX Vref=22, minBit 1, minWin=24, winSum=399
7720 12:12:29.744910 TX Vref=24, minBit 0, minWin=25, winSum=409
7721 12:12:29.751402 TX Vref=26, minBit 2, minWin=25, winSum=413
7722 12:12:29.754535 TX Vref=28, minBit 2, minWin=25, winSum=417
7723 12:12:29.758072 TX Vref=30, minBit 2, minWin=25, winSum=416
7724 12:12:29.761471 TX Vref=32, minBit 4, minWin=24, winSum=407
7725 12:12:29.764509 TX Vref=34, minBit 1, minWin=24, winSum=394
7726 12:12:29.770985 [TxChooseVref] Worse bit 2, Min win 25, Win sum 417, Final Vref 28
7727 12:12:29.771544
7728 12:12:29.774869 Final TX Range 0 Vref 28
7729 12:12:29.775291
7730 12:12:29.775682 ==
7731 12:12:29.777751 Dram Type= 6, Freq= 0, CH_0, rank 0
7732 12:12:29.780855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7733 12:12:29.781325 ==
7734 12:12:29.781774
7735 12:12:29.782194
7736 12:12:29.784588 TX Vref Scan disable
7737 12:12:29.790698 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7738 12:12:29.791137 == TX Byte 0 ==
7739 12:12:29.794324 u2DelayCellOfst[0]=10 cells (3 PI)
7740 12:12:29.797183 u2DelayCellOfst[1]=14 cells (4 PI)
7741 12:12:29.800524 u2DelayCellOfst[2]=10 cells (3 PI)
7742 12:12:29.804171 u2DelayCellOfst[3]=10 cells (3 PI)
7743 12:12:29.807346 u2DelayCellOfst[4]=7 cells (2 PI)
7744 12:12:29.810718 u2DelayCellOfst[5]=0 cells (0 PI)
7745 12:12:29.814196 u2DelayCellOfst[6]=17 cells (5 PI)
7746 12:12:29.817222 u2DelayCellOfst[7]=14 cells (4 PI)
7747 12:12:29.820689 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7748 12:12:29.823984 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7749 12:12:29.827045 == TX Byte 1 ==
7750 12:12:29.830332 u2DelayCellOfst[8]=0 cells (0 PI)
7751 12:12:29.833812 u2DelayCellOfst[9]=0 cells (0 PI)
7752 12:12:29.837123 u2DelayCellOfst[10]=3 cells (1 PI)
7753 12:12:29.840337 u2DelayCellOfst[11]=0 cells (0 PI)
7754 12:12:29.844292 u2DelayCellOfst[12]=7 cells (2 PI)
7755 12:12:29.844958 u2DelayCellOfst[13]=10 cells (3 PI)
7756 12:12:29.846876 u2DelayCellOfst[14]=14 cells (4 PI)
7757 12:12:29.850121 u2DelayCellOfst[15]=10 cells (3 PI)
7758 12:12:29.856300 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7759 12:12:29.860268 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7760 12:12:29.863832 DramC Write-DBI on
7761 12:12:29.864298 ==
7762 12:12:29.866319 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 12:12:29.870289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 12:12:29.870704 ==
7765 12:12:29.871120
7766 12:12:29.871627
7767 12:12:29.873017 TX Vref Scan disable
7768 12:12:29.873575 == TX Byte 0 ==
7769 12:12:29.879982 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7770 12:12:29.880450 == TX Byte 1 ==
7771 12:12:29.882796 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7772 12:12:29.886044 DramC Write-DBI off
7773 12:12:29.886454
7774 12:12:29.886827 [DATLAT]
7775 12:12:29.889465 Freq=1600, CH0 RK0
7776 12:12:29.889878
7777 12:12:29.890251 DATLAT Default: 0xf
7778 12:12:29.892919 0, 0xFFFF, sum = 0
7779 12:12:29.896455 1, 0xFFFF, sum = 0
7780 12:12:29.896873 2, 0xFFFF, sum = 0
7781 12:12:29.899307 3, 0xFFFF, sum = 0
7782 12:12:29.899777 4, 0xFFFF, sum = 0
7783 12:12:29.902730 5, 0xFFFF, sum = 0
7784 12:12:29.903150 6, 0xFFFF, sum = 0
7785 12:12:29.906306 7, 0xFFFF, sum = 0
7786 12:12:29.906825 8, 0xFFFF, sum = 0
7787 12:12:29.909087 9, 0xFFFF, sum = 0
7788 12:12:29.909507 10, 0xFFFF, sum = 0
7789 12:12:29.912495 11, 0xFFFF, sum = 0
7790 12:12:29.912911 12, 0xFFFF, sum = 0
7791 12:12:29.915942 13, 0xFFFF, sum = 0
7792 12:12:29.916361 14, 0x0, sum = 1
7793 12:12:29.919041 15, 0x0, sum = 2
7794 12:12:29.919503 16, 0x0, sum = 3
7795 12:12:29.922393 17, 0x0, sum = 4
7796 12:12:29.922829 best_step = 15
7797 12:12:29.923359
7798 12:12:29.923756 ==
7799 12:12:29.925363 Dram Type= 6, Freq= 0, CH_0, rank 0
7800 12:12:29.931940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7801 12:12:29.932391 ==
7802 12:12:29.932891 RX Vref Scan: 1
7803 12:12:29.933455
7804 12:12:29.936028 Set Vref Range= 24 -> 127
7805 12:12:29.936597
7806 12:12:29.939081 RX Vref 24 -> 127, step: 1
7807 12:12:29.939771
7808 12:12:29.942473 RX Delay 11 -> 252, step: 4
7809 12:12:29.943007
7810 12:12:29.945182 Set Vref, RX VrefLevel [Byte0]: 24
7811 12:12:29.948526 [Byte1]: 24
7812 12:12:29.949046
7813 12:12:29.952085 Set Vref, RX VrefLevel [Byte0]: 25
7814 12:12:29.955665 [Byte1]: 25
7815 12:12:29.956195
7816 12:12:29.958814 Set Vref, RX VrefLevel [Byte0]: 26
7817 12:12:29.961907 [Byte1]: 26
7818 12:12:29.965403
7819 12:12:29.965823 Set Vref, RX VrefLevel [Byte0]: 27
7820 12:12:29.968617 [Byte1]: 27
7821 12:12:29.972494
7822 12:12:29.972999 Set Vref, RX VrefLevel [Byte0]: 28
7823 12:12:29.975949 [Byte1]: 28
7824 12:12:29.980310
7825 12:12:29.980803 Set Vref, RX VrefLevel [Byte0]: 29
7826 12:12:29.983262 [Byte1]: 29
7827 12:12:29.987942
7828 12:12:29.988457 Set Vref, RX VrefLevel [Byte0]: 30
7829 12:12:29.991539 [Byte1]: 30
7830 12:12:29.995938
7831 12:12:29.996446 Set Vref, RX VrefLevel [Byte0]: 31
7832 12:12:29.998580 [Byte1]: 31
7833 12:12:30.003203
7834 12:12:30.003783 Set Vref, RX VrefLevel [Byte0]: 32
7835 12:12:30.006465 [Byte1]: 32
7836 12:12:30.011012
7837 12:12:30.011577 Set Vref, RX VrefLevel [Byte0]: 33
7838 12:12:30.014528 [Byte1]: 33
7839 12:12:30.018070
7840 12:12:30.018530 Set Vref, RX VrefLevel [Byte0]: 34
7841 12:12:30.021586 [Byte1]: 34
7842 12:12:30.026040
7843 12:12:30.026570 Set Vref, RX VrefLevel [Byte0]: 35
7844 12:12:30.029358 [Byte1]: 35
7845 12:12:30.033334
7846 12:12:30.033754 Set Vref, RX VrefLevel [Byte0]: 36
7847 12:12:30.037065 [Byte1]: 36
7848 12:12:30.040887
7849 12:12:30.041302 Set Vref, RX VrefLevel [Byte0]: 37
7850 12:12:30.045276 [Byte1]: 37
7851 12:12:30.049014
7852 12:12:30.049467 Set Vref, RX VrefLevel [Byte0]: 38
7853 12:12:30.051986 [Byte1]: 38
7854 12:12:30.056696
7855 12:12:30.057104 Set Vref, RX VrefLevel [Byte0]: 39
7856 12:12:30.059419 [Byte1]: 39
7857 12:12:30.063811
7858 12:12:30.064225 Set Vref, RX VrefLevel [Byte0]: 40
7859 12:12:30.067360 [Byte1]: 40
7860 12:12:30.071335
7861 12:12:30.071903 Set Vref, RX VrefLevel [Byte0]: 41
7862 12:12:30.074533 [Byte1]: 41
7863 12:12:30.079257
7864 12:12:30.079730 Set Vref, RX VrefLevel [Byte0]: 42
7865 12:12:30.082457 [Byte1]: 42
7866 12:12:30.086882
7867 12:12:30.087305 Set Vref, RX VrefLevel [Byte0]: 43
7868 12:12:30.089861 [Byte1]: 43
7869 12:12:30.094344
7870 12:12:30.094845 Set Vref, RX VrefLevel [Byte0]: 44
7871 12:12:30.097556 [Byte1]: 44
7872 12:12:30.101739
7873 12:12:30.102157 Set Vref, RX VrefLevel [Byte0]: 45
7874 12:12:30.105471 [Byte1]: 45
7875 12:12:30.109757
7876 12:12:30.110179 Set Vref, RX VrefLevel [Byte0]: 46
7877 12:12:30.112970 [Byte1]: 46
7878 12:12:30.118083
7879 12:12:30.118608 Set Vref, RX VrefLevel [Byte0]: 47
7880 12:12:30.120698 [Byte1]: 47
7881 12:12:30.124860
7882 12:12:30.125280 Set Vref, RX VrefLevel [Byte0]: 48
7883 12:12:30.128372 [Byte1]: 48
7884 12:12:30.132510
7885 12:12:30.133078 Set Vref, RX VrefLevel [Byte0]: 49
7886 12:12:30.135909 [Byte1]: 49
7887 12:12:30.140169
7888 12:12:30.140627 Set Vref, RX VrefLevel [Byte0]: 50
7889 12:12:30.143585 [Byte1]: 50
7890 12:12:30.147809
7891 12:12:30.148227 Set Vref, RX VrefLevel [Byte0]: 51
7892 12:12:30.150819 [Byte1]: 51
7893 12:12:30.155390
7894 12:12:30.155810 Set Vref, RX VrefLevel [Byte0]: 52
7895 12:12:30.159146 [Byte1]: 52
7896 12:12:30.162870
7897 12:12:30.163454 Set Vref, RX VrefLevel [Byte0]: 53
7898 12:12:30.166164 [Byte1]: 53
7899 12:12:30.170525
7900 12:12:30.171060 Set Vref, RX VrefLevel [Byte0]: 54
7901 12:12:30.174227 [Byte1]: 54
7902 12:12:30.177985
7903 12:12:30.178401 Set Vref, RX VrefLevel [Byte0]: 55
7904 12:12:30.181410 [Byte1]: 55
7905 12:12:30.186366
7906 12:12:30.186782 Set Vref, RX VrefLevel [Byte0]: 56
7907 12:12:30.188890 [Byte1]: 56
7908 12:12:30.193497
7909 12:12:30.193934 Set Vref, RX VrefLevel [Byte0]: 57
7910 12:12:30.196793 [Byte1]: 57
7911 12:12:30.200978
7912 12:12:30.201528 Set Vref, RX VrefLevel [Byte0]: 58
7913 12:12:30.204337 [Byte1]: 58
7914 12:12:30.208694
7915 12:12:30.209116 Set Vref, RX VrefLevel [Byte0]: 59
7916 12:12:30.211768 [Byte1]: 59
7917 12:12:30.216213
7918 12:12:30.216744 Set Vref, RX VrefLevel [Byte0]: 60
7919 12:12:30.219526 [Byte1]: 60
7920 12:12:30.223920
7921 12:12:30.224605 Set Vref, RX VrefLevel [Byte0]: 61
7922 12:12:30.227130 [Byte1]: 61
7923 12:12:30.231458
7924 12:12:30.232102 Set Vref, RX VrefLevel [Byte0]: 62
7925 12:12:30.234831 [Byte1]: 62
7926 12:12:30.239411
7927 12:12:30.239943 Set Vref, RX VrefLevel [Byte0]: 63
7928 12:12:30.242644 [Byte1]: 63
7929 12:12:30.246983
7930 12:12:30.247604 Set Vref, RX VrefLevel [Byte0]: 64
7931 12:12:30.250081 [Byte1]: 64
7932 12:12:30.254861
7933 12:12:30.255427 Set Vref, RX VrefLevel [Byte0]: 65
7934 12:12:30.257515 [Byte1]: 65
7935 12:12:30.262186
7936 12:12:30.262611 Set Vref, RX VrefLevel [Byte0]: 66
7937 12:12:30.265387 [Byte1]: 66
7938 12:12:30.269673
7939 12:12:30.270122 Set Vref, RX VrefLevel [Byte0]: 67
7940 12:12:30.272983 [Byte1]: 67
7941 12:12:30.277351
7942 12:12:30.277770 Set Vref, RX VrefLevel [Byte0]: 68
7943 12:12:30.280477 [Byte1]: 68
7944 12:12:30.285875
7945 12:12:30.286406 Set Vref, RX VrefLevel [Byte0]: 69
7946 12:12:30.287986 [Byte1]: 69
7947 12:12:30.293172
7948 12:12:30.293701 Set Vref, RX VrefLevel [Byte0]: 70
7949 12:12:30.295990 [Byte1]: 70
7950 12:12:30.300052
7951 12:12:30.300581 Set Vref, RX VrefLevel [Byte0]: 71
7952 12:12:30.303306 [Byte1]: 71
7953 12:12:30.307750
7954 12:12:30.308273 Set Vref, RX VrefLevel [Byte0]: 72
7955 12:12:30.310749 [Byte1]: 72
7956 12:12:30.315013
7957 12:12:30.315468 Set Vref, RX VrefLevel [Byte0]: 73
7958 12:12:30.318665 [Byte1]: 73
7959 12:12:30.322699
7960 12:12:30.323111 Set Vref, RX VrefLevel [Byte0]: 74
7961 12:12:30.326574 [Byte1]: 74
7962 12:12:30.330809
7963 12:12:30.331350 Final RX Vref Byte 0 = 56 to rank0
7964 12:12:30.333890 Final RX Vref Byte 1 = 60 to rank0
7965 12:12:30.337371 Final RX Vref Byte 0 = 56 to rank1
7966 12:12:30.341031 Final RX Vref Byte 1 = 60 to rank1==
7967 12:12:30.343543 Dram Type= 6, Freq= 0, CH_0, rank 0
7968 12:12:30.350100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7969 12:12:30.350644 ==
7970 12:12:30.350990 DQS Delay:
7971 12:12:30.353112 DQS0 = 0, DQS1 = 0
7972 12:12:30.353536 DQM Delay:
7973 12:12:30.356531 DQM0 = 128, DQM1 = 123
7974 12:12:30.357057 DQ Delay:
7975 12:12:30.360174 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7976 12:12:30.363175 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
7977 12:12:30.366758 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
7978 12:12:30.369521 DQ12 =130, DQ13 =128, DQ14 =132, DQ15 =130
7979 12:12:30.369959
7980 12:12:30.370295
7981 12:12:30.370604
7982 12:12:30.373432 [DramC_TX_OE_Calibration] TA2
7983 12:12:30.376247 Original DQ_B0 (3 6) =30, OEN = 27
7984 12:12:30.379415 Original DQ_B1 (3 6) =30, OEN = 27
7985 12:12:30.382900 24, 0x0, End_B0=24 End_B1=24
7986 12:12:30.386496 25, 0x0, End_B0=25 End_B1=25
7987 12:12:30.386927 26, 0x0, End_B0=26 End_B1=26
7988 12:12:30.389886 27, 0x0, End_B0=27 End_B1=27
7989 12:12:30.392527 28, 0x0, End_B0=28 End_B1=28
7990 12:12:30.396111 29, 0x0, End_B0=29 End_B1=29
7991 12:12:30.399099 30, 0x0, End_B0=30 End_B1=30
7992 12:12:30.399577 31, 0x4141, End_B0=30 End_B1=30
7993 12:12:30.402972 Byte0 end_step=30 best_step=27
7994 12:12:30.405537 Byte1 end_step=30 best_step=27
7995 12:12:30.409192 Byte0 TX OE(2T, 0.5T) = (3, 3)
7996 12:12:30.412492 Byte1 TX OE(2T, 0.5T) = (3, 3)
7997 12:12:30.412917
7998 12:12:30.413252
7999 12:12:30.418936 [DQSOSCAuto] RK0, (LSB)MR18= 0x1613, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
8000 12:12:30.422344 CH0 RK0: MR19=303, MR18=1613
8001 12:12:30.428743 CH0_RK0: MR19=0x303, MR18=0x1613, DQSOSC=398, MR23=63, INC=23, DEC=15
8002 12:12:30.429234
8003 12:12:30.431664 ----->DramcWriteLeveling(PI) begin...
8004 12:12:30.432091 ==
8005 12:12:30.435340 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 12:12:30.438680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 12:12:30.442560 ==
8008 12:12:30.442986 Write leveling (Byte 0): 34 => 34
8009 12:12:30.445412 Write leveling (Byte 1): 29 => 29
8010 12:12:30.448292 DramcWriteLeveling(PI) end<-----
8011 12:12:30.448716
8012 12:12:30.449052 ==
8013 12:12:30.451534 Dram Type= 6, Freq= 0, CH_0, rank 1
8014 12:12:30.458657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8015 12:12:30.459084 ==
8016 12:12:30.462602 [Gating] SW mode calibration
8017 12:12:30.468364 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8018 12:12:30.471499 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8019 12:12:30.478301 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 12:12:30.481479 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 12:12:30.484538 1 4 8 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
8022 12:12:30.491121 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8023 12:12:30.494926 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8024 12:12:30.497803 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8025 12:12:30.504274 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 12:12:30.507940 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 12:12:30.511519 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8028 12:12:30.518432 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8029 12:12:30.521241 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8030 12:12:30.524124 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
8031 12:12:30.530725 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8032 12:12:30.534082 1 5 20 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8033 12:12:30.537108 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 12:12:30.544114 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 12:12:30.547157 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 12:12:30.550532 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8037 12:12:30.556881 1 6 8 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
8038 12:12:30.560129 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8039 12:12:30.563404 1 6 16 | B1->B0 | 2a2a 4646 | 1 0 | (0 0) (0 0)
8040 12:12:30.569865 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8041 12:12:30.573694 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 12:12:30.577043 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 12:12:30.583141 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 12:12:30.586551 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8045 12:12:30.590336 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8046 12:12:30.596598 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8047 12:12:30.599885 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8048 12:12:30.603017 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8049 12:12:30.610350 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8050 12:12:30.613249 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 12:12:30.616525 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 12:12:30.623496 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 12:12:30.625949 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 12:12:30.629173 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 12:12:30.635859 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 12:12:30.639330 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 12:12:30.642747 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 12:12:30.648805 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 12:12:30.652585 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 12:12:30.655264 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 12:12:30.662060 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8062 12:12:30.665558 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8063 12:12:30.668624 Total UI for P1: 0, mck2ui 16
8064 12:12:30.671979 best dqsien dly found for B0: ( 1, 9, 8)
8065 12:12:30.675349 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8066 12:12:30.681790 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8067 12:12:30.685117 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 12:12:30.688477 Total UI for P1: 0, mck2ui 16
8069 12:12:30.691632 best dqsien dly found for B1: ( 1, 9, 18)
8070 12:12:30.695419 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8071 12:12:30.698235 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8072 12:12:30.698647
8073 12:12:30.701839 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8074 12:12:30.708676 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8075 12:12:30.709162 [Gating] SW calibration Done
8076 12:12:30.709492 ==
8077 12:12:30.711716 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 12:12:30.718400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 12:12:30.718912 ==
8080 12:12:30.719247 RX Vref Scan: 0
8081 12:12:30.719662
8082 12:12:30.721524 RX Vref 0 -> 0, step: 1
8083 12:12:30.721936
8084 12:12:30.724779 RX Delay 0 -> 252, step: 8
8085 12:12:30.727748 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8086 12:12:30.731554 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8087 12:12:30.734537 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8088 12:12:30.740965 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8089 12:12:30.744722 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8090 12:12:30.747966 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8091 12:12:30.750831 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8092 12:12:30.754364 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8093 12:12:30.760961 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8094 12:12:30.764072 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8095 12:12:30.767129 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8096 12:12:30.770883 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8097 12:12:30.774267 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8098 12:12:30.780680 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8099 12:12:30.783735 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8100 12:12:30.787222 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8101 12:12:30.787716 ==
8102 12:12:30.790407 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 12:12:30.797093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 12:12:30.797735 ==
8105 12:12:30.798089 DQS Delay:
8106 12:12:30.800110 DQS0 = 0, DQS1 = 0
8107 12:12:30.800532 DQM Delay:
8108 12:12:30.800872 DQM0 = 131, DQM1 = 124
8109 12:12:30.803358 DQ Delay:
8110 12:12:30.806900 DQ0 =127, DQ1 =135, DQ2 =127, DQ3 =127
8111 12:12:30.810004 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8112 12:12:30.813346 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =115
8113 12:12:30.817224 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8114 12:12:30.817717
8115 12:12:30.818047
8116 12:12:30.818353 ==
8117 12:12:30.819878 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 12:12:30.826793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 12:12:30.827228 ==
8120 12:12:30.827603
8121 12:12:30.827912
8122 12:12:30.828206 TX Vref Scan disable
8123 12:12:30.830063 == TX Byte 0 ==
8124 12:12:30.832884 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8125 12:12:30.839888 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8126 12:12:30.840305 == TX Byte 1 ==
8127 12:12:30.843178 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8128 12:12:30.849747 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8129 12:12:30.850170 ==
8130 12:12:30.852644 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 12:12:30.856760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 12:12:30.857295 ==
8133 12:12:30.869117
8134 12:12:30.872637 TX Vref early break, caculate TX vref
8135 12:12:30.875734 TX Vref=16, minBit 3, minWin=23, winSum=377
8136 12:12:30.879450 TX Vref=18, minBit 8, minWin=23, winSum=390
8137 12:12:30.882486 TX Vref=20, minBit 4, minWin=24, winSum=400
8138 12:12:30.885837 TX Vref=22, minBit 2, minWin=24, winSum=404
8139 12:12:30.889368 TX Vref=24, minBit 1, minWin=25, winSum=412
8140 12:12:30.896138 TX Vref=26, minBit 4, minWin=25, winSum=421
8141 12:12:30.898673 TX Vref=28, minBit 4, minWin=25, winSum=421
8142 12:12:30.902600 TX Vref=30, minBit 0, minWin=25, winSum=417
8143 12:12:30.905776 TX Vref=32, minBit 0, minWin=24, winSum=408
8144 12:12:30.908919 TX Vref=34, minBit 8, minWin=23, winSum=397
8145 12:12:30.915909 [TxChooseVref] Worse bit 4, Min win 25, Win sum 421, Final Vref 26
8146 12:12:30.916467
8147 12:12:30.918491 Final TX Range 0 Vref 26
8148 12:12:30.919047
8149 12:12:30.919450 ==
8150 12:12:30.922097 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 12:12:30.925425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 12:12:30.925989 ==
8153 12:12:30.926355
8154 12:12:30.926694
8155 12:12:30.928484 TX Vref Scan disable
8156 12:12:30.935187 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8157 12:12:30.935820 == TX Byte 0 ==
8158 12:12:30.938192 u2DelayCellOfst[0]=14 cells (4 PI)
8159 12:12:30.941446 u2DelayCellOfst[1]=17 cells (5 PI)
8160 12:12:30.945323 u2DelayCellOfst[2]=10 cells (3 PI)
8161 12:12:30.948321 u2DelayCellOfst[3]=14 cells (4 PI)
8162 12:12:30.951989 u2DelayCellOfst[4]=10 cells (3 PI)
8163 12:12:30.955163 u2DelayCellOfst[5]=0 cells (0 PI)
8164 12:12:30.958023 u2DelayCellOfst[6]=17 cells (5 PI)
8165 12:12:30.961782 u2DelayCellOfst[7]=17 cells (5 PI)
8166 12:12:30.965137 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8167 12:12:30.967965 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8168 12:12:30.971402 == TX Byte 1 ==
8169 12:12:30.974522 u2DelayCellOfst[8]=3 cells (1 PI)
8170 12:12:30.977962 u2DelayCellOfst[9]=0 cells (0 PI)
8171 12:12:30.981087 u2DelayCellOfst[10]=7 cells (2 PI)
8172 12:12:30.981566 u2DelayCellOfst[11]=7 cells (2 PI)
8173 12:12:30.984444 u2DelayCellOfst[12]=14 cells (4 PI)
8174 12:12:30.987804 u2DelayCellOfst[13]=14 cells (4 PI)
8175 12:12:30.990927 u2DelayCellOfst[14]=17 cells (5 PI)
8176 12:12:30.994568 u2DelayCellOfst[15]=14 cells (4 PI)
8177 12:12:31.000854 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8178 12:12:31.004264 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8179 12:12:31.004785 DramC Write-DBI on
8180 12:12:31.007267 ==
8181 12:12:31.011095 Dram Type= 6, Freq= 0, CH_0, rank 1
8182 12:12:31.014295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8183 12:12:31.014720 ==
8184 12:12:31.015140
8185 12:12:31.015511
8186 12:12:31.017406 TX Vref Scan disable
8187 12:12:31.017926 == TX Byte 0 ==
8188 12:12:31.024114 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8189 12:12:31.024648 == TX Byte 1 ==
8190 12:12:31.027464 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8191 12:12:31.030136 DramC Write-DBI off
8192 12:12:31.030557
8193 12:12:31.030891 [DATLAT]
8194 12:12:31.034035 Freq=1600, CH0 RK1
8195 12:12:31.034569
8196 12:12:31.034908 DATLAT Default: 0xf
8197 12:12:31.037235 0, 0xFFFF, sum = 0
8198 12:12:31.037662 1, 0xFFFF, sum = 0
8199 12:12:31.040682 2, 0xFFFF, sum = 0
8200 12:12:31.043954 3, 0xFFFF, sum = 0
8201 12:12:31.044385 4, 0xFFFF, sum = 0
8202 12:12:31.047311 5, 0xFFFF, sum = 0
8203 12:12:31.047864 6, 0xFFFF, sum = 0
8204 12:12:31.050510 7, 0xFFFF, sum = 0
8205 12:12:31.051032 8, 0xFFFF, sum = 0
8206 12:12:31.053523 9, 0xFFFF, sum = 0
8207 12:12:31.054054 10, 0xFFFF, sum = 0
8208 12:12:31.056875 11, 0xFFFF, sum = 0
8209 12:12:31.057303 12, 0xFFFF, sum = 0
8210 12:12:31.059805 13, 0xFFFF, sum = 0
8211 12:12:31.060235 14, 0x0, sum = 1
8212 12:12:31.063358 15, 0x0, sum = 2
8213 12:12:31.063916 16, 0x0, sum = 3
8214 12:12:31.067241 17, 0x0, sum = 4
8215 12:12:31.067813 best_step = 15
8216 12:12:31.068187
8217 12:12:31.068509 ==
8218 12:12:31.070267 Dram Type= 6, Freq= 0, CH_0, rank 1
8219 12:12:31.077177 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8220 12:12:31.077731 ==
8221 12:12:31.078079 RX Vref Scan: 0
8222 12:12:31.078392
8223 12:12:31.080020 RX Vref 0 -> 0, step: 1
8224 12:12:31.080445
8225 12:12:31.082847 RX Delay 11 -> 252, step: 4
8226 12:12:31.086215 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8227 12:12:31.090193 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8228 12:12:31.092740 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8229 12:12:31.099484 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8230 12:12:31.102451 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8231 12:12:31.105917 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8232 12:12:31.109337 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8233 12:12:31.115739 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8234 12:12:31.119148 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8235 12:12:31.122600 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8236 12:12:31.125744 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8237 12:12:31.128762 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8238 12:12:31.135506 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8239 12:12:31.138506 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8240 12:12:31.142029 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8241 12:12:31.145683 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8242 12:12:31.146235 ==
8243 12:12:31.148572 Dram Type= 6, Freq= 0, CH_0, rank 1
8244 12:12:31.155212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8245 12:12:31.155759 ==
8246 12:12:31.156096 DQS Delay:
8247 12:12:31.158294 DQS0 = 0, DQS1 = 0
8248 12:12:31.158709 DQM Delay:
8249 12:12:31.159040 DQM0 = 129, DQM1 = 123
8250 12:12:31.161765 DQ Delay:
8251 12:12:31.165434 DQ0 =126, DQ1 =132, DQ2 =124, DQ3 =126
8252 12:12:31.168253 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8253 12:12:31.171775 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8254 12:12:31.175538 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =132
8255 12:12:31.175955
8256 12:12:31.176405
8257 12:12:31.176746
8258 12:12:31.178310 [DramC_TX_OE_Calibration] TA2
8259 12:12:31.181808 Original DQ_B0 (3 6) =30, OEN = 27
8260 12:12:31.185062 Original DQ_B1 (3 6) =30, OEN = 27
8261 12:12:31.188112 24, 0x0, End_B0=24 End_B1=24
8262 12:12:31.192079 25, 0x0, End_B0=25 End_B1=25
8263 12:12:31.192507 26, 0x0, End_B0=26 End_B1=26
8264 12:12:31.194953 27, 0x0, End_B0=27 End_B1=27
8265 12:12:31.197861 28, 0x0, End_B0=28 End_B1=28
8266 12:12:31.201513 29, 0x0, End_B0=29 End_B1=29
8267 12:12:31.202046 30, 0x0, End_B0=30 End_B1=30
8268 12:12:31.205194 31, 0x4141, End_B0=30 End_B1=30
8269 12:12:31.207937 Byte0 end_step=30 best_step=27
8270 12:12:31.211586 Byte1 end_step=30 best_step=27
8271 12:12:31.214580 Byte0 TX OE(2T, 0.5T) = (3, 3)
8272 12:12:31.218184 Byte1 TX OE(2T, 0.5T) = (3, 3)
8273 12:12:31.218700
8274 12:12:31.219033
8275 12:12:31.225045 [DQSOSCAuto] RK1, (LSB)MR18= 0x1412, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8276 12:12:31.227457 CH0 RK1: MR19=303, MR18=1412
8277 12:12:31.234218 CH0_RK1: MR19=0x303, MR18=0x1412, DQSOSC=399, MR23=63, INC=23, DEC=15
8278 12:12:31.238251 [RxdqsGatingPostProcess] freq 1600
8279 12:12:31.244078 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8280 12:12:31.244502 best DQS0 dly(2T, 0.5T) = (1, 1)
8281 12:12:31.247913 best DQS1 dly(2T, 0.5T) = (1, 1)
8282 12:12:31.251249 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8283 12:12:31.254565 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8284 12:12:31.257698 best DQS0 dly(2T, 0.5T) = (1, 1)
8285 12:12:31.260874 best DQS1 dly(2T, 0.5T) = (1, 1)
8286 12:12:31.263811 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8287 12:12:31.267509 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8288 12:12:31.270657 Pre-setting of DQS Precalculation
8289 12:12:31.273544 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8290 12:12:31.277662 ==
8291 12:12:31.280099 Dram Type= 6, Freq= 0, CH_1, rank 0
8292 12:12:31.283953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 12:12:31.284515 ==
8294 12:12:31.286843 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8295 12:12:31.294122 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8296 12:12:31.297260 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8297 12:12:31.304196 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8298 12:12:31.311700 [CA 0] Center 42 (13~72) winsize 60
8299 12:12:31.315202 [CA 1] Center 42 (12~72) winsize 61
8300 12:12:31.318587 [CA 2] Center 38 (9~68) winsize 60
8301 12:12:31.321599 [CA 3] Center 37 (8~67) winsize 60
8302 12:12:31.325033 [CA 4] Center 38 (8~68) winsize 61
8303 12:12:31.328383 [CA 5] Center 36 (7~66) winsize 60
8304 12:12:31.328848
8305 12:12:31.331155 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8306 12:12:31.331668
8307 12:12:31.337932 [CATrainingPosCal] consider 1 rank data
8308 12:12:31.338586 u2DelayCellTimex100 = 275/100 ps
8309 12:12:31.345215 CA0 delay=42 (13~72),Diff = 6 PI (21 cell)
8310 12:12:31.347493 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8311 12:12:31.351020 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
8312 12:12:31.354861 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
8313 12:12:31.358438 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8314 12:12:31.361342 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8315 12:12:31.361930
8316 12:12:31.364938 CA PerBit enable=1, Macro0, CA PI delay=36
8317 12:12:31.365464
8318 12:12:31.367915 [CBTSetCACLKResult] CA Dly = 36
8319 12:12:31.371698 CS Dly: 8 (0~39)
8320 12:12:31.374293 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8321 12:12:31.377206 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8322 12:12:31.377606 ==
8323 12:12:31.381232 Dram Type= 6, Freq= 0, CH_1, rank 1
8324 12:12:31.387150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8325 12:12:31.387619 ==
8326 12:12:31.390803 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8327 12:12:31.396783 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8328 12:12:31.400536 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8329 12:12:31.407044 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8330 12:12:31.415287 [CA 0] Center 42 (12~72) winsize 61
8331 12:12:31.418768 [CA 1] Center 43 (14~72) winsize 59
8332 12:12:31.421460 [CA 2] Center 38 (9~68) winsize 60
8333 12:12:31.424884 [CA 3] Center 37 (8~66) winsize 59
8334 12:12:31.427956 [CA 4] Center 37 (7~68) winsize 62
8335 12:12:31.431210 [CA 5] Center 37 (8~67) winsize 60
8336 12:12:31.431719
8337 12:12:31.435086 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8338 12:12:31.435701
8339 12:12:31.438330 [CATrainingPosCal] consider 2 rank data
8340 12:12:31.441454 u2DelayCellTimex100 = 275/100 ps
8341 12:12:31.447850 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8342 12:12:31.451550 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8343 12:12:31.454362 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8344 12:12:31.457872 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8345 12:12:31.460836 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8346 12:12:31.464744 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8347 12:12:31.465278
8348 12:12:31.468188 CA PerBit enable=1, Macro0, CA PI delay=37
8349 12:12:31.468613
8350 12:12:31.470951 [CBTSetCACLKResult] CA Dly = 37
8351 12:12:31.473852 CS Dly: 10 (0~43)
8352 12:12:31.477306 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8353 12:12:31.480619 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8354 12:12:31.481290
8355 12:12:31.484098 ----->DramcWriteLeveling(PI) begin...
8356 12:12:31.484526 ==
8357 12:12:31.487423 Dram Type= 6, Freq= 0, CH_1, rank 0
8358 12:12:31.494050 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 12:12:31.494474 ==
8360 12:12:31.497123 Write leveling (Byte 0): 26 => 26
8361 12:12:31.500461 Write leveling (Byte 1): 28 => 28
8362 12:12:31.500954 DramcWriteLeveling(PI) end<-----
8363 12:12:31.504499
8364 12:12:31.504927 ==
8365 12:12:31.506932 Dram Type= 6, Freq= 0, CH_1, rank 0
8366 12:12:31.510349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8367 12:12:31.510769 ==
8368 12:12:31.513571 [Gating] SW mode calibration
8369 12:12:31.520373 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8370 12:12:31.523625 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8371 12:12:31.530898 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 12:12:31.533599 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 12:12:31.539869 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 12:12:31.543155 1 4 12 | B1->B0 | 2828 3232 | 0 0 | (0 0) (0 0)
8375 12:12:31.546759 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 12:12:31.552950 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 12:12:31.556154 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 12:12:31.559507 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 12:12:31.566219 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 12:12:31.569750 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 12:12:31.573110 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8382 12:12:31.579434 1 5 12 | B1->B0 | 3333 2525 | 0 0 | (0 1) (1 0)
8383 12:12:31.583101 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 12:12:31.586175 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 12:12:31.592303 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 12:12:31.595888 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 12:12:31.598921 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 12:12:31.605892 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 12:12:31.608918 1 6 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
8390 12:12:31.612188 1 6 12 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
8391 12:12:31.618957 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 12:12:31.622011 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 12:12:31.625606 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 12:12:31.631910 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 12:12:31.635818 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 12:12:31.639160 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 12:12:31.644999 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 12:12:31.648827 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8399 12:12:31.651867 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8400 12:12:31.658406 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 12:12:31.662013 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 12:12:31.665355 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 12:12:31.671441 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 12:12:31.674880 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 12:12:31.677859 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 12:12:31.684332 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 12:12:31.687842 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 12:12:31.690875 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 12:12:31.698063 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 12:12:31.701203 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 12:12:31.704768 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 12:12:31.710850 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 12:12:31.714320 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 12:12:31.718112 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8415 12:12:31.724300 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 12:12:31.724859 Total UI for P1: 0, mck2ui 16
8417 12:12:31.731028 best dqsien dly found for B0: ( 1, 9, 12)
8418 12:12:31.731665 Total UI for P1: 0, mck2ui 16
8419 12:12:31.737489 best dqsien dly found for B1: ( 1, 9, 12)
8420 12:12:31.741113 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8421 12:12:31.743687 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8422 12:12:31.744387
8423 12:12:31.747211 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8424 12:12:31.750295 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8425 12:12:31.753266 [Gating] SW calibration Done
8426 12:12:31.753687 ==
8427 12:12:31.757279 Dram Type= 6, Freq= 0, CH_1, rank 0
8428 12:12:31.760043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8429 12:12:31.760463 ==
8430 12:12:31.763105 RX Vref Scan: 0
8431 12:12:31.763583
8432 12:12:31.766687 RX Vref 0 -> 0, step: 1
8433 12:12:31.767184
8434 12:12:31.767569 RX Delay 0 -> 252, step: 8
8435 12:12:31.773301 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8436 12:12:31.776248 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8437 12:12:31.780063 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8438 12:12:31.782889 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8439 12:12:31.786370 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8440 12:12:31.792802 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8441 12:12:31.795952 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8442 12:12:31.799307 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8443 12:12:31.802513 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8444 12:12:31.805980 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8445 12:12:31.812951 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8446 12:12:31.815721 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8447 12:12:31.819031 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8448 12:12:31.822817 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8449 12:12:31.829036 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8450 12:12:31.832515 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8451 12:12:31.832936 ==
8452 12:12:31.836516 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 12:12:31.839139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 12:12:31.839593 ==
8455 12:12:31.842434 DQS Delay:
8456 12:12:31.842854 DQS0 = 0, DQS1 = 0
8457 12:12:31.843186 DQM Delay:
8458 12:12:31.845297 DQM0 = 135, DQM1 = 129
8459 12:12:31.845721 DQ Delay:
8460 12:12:31.848426 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8461 12:12:31.852608 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8462 12:12:31.858597 DQ8 =111, DQ9 =119, DQ10 =131, DQ11 =123
8463 12:12:31.861828 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8464 12:12:31.862228
8465 12:12:31.862568
8466 12:12:31.862887 ==
8467 12:12:31.865584 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 12:12:31.868430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 12:12:31.868814 ==
8470 12:12:31.869141
8471 12:12:31.869522
8472 12:12:31.871614 TX Vref Scan disable
8473 12:12:31.875094 == TX Byte 0 ==
8474 12:12:31.878683 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8475 12:12:31.881992 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8476 12:12:31.885291 == TX Byte 1 ==
8477 12:12:31.888398 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8478 12:12:31.891636 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8479 12:12:31.892083 ==
8480 12:12:31.894846 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 12:12:31.898201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 12:12:31.901338 ==
8483 12:12:31.912411
8484 12:12:31.915759 TX Vref early break, caculate TX vref
8485 12:12:31.919125 TX Vref=16, minBit 8, minWin=21, winSum=368
8486 12:12:31.922189 TX Vref=18, minBit 8, minWin=22, winSum=374
8487 12:12:31.925725 TX Vref=20, minBit 8, minWin=23, winSum=387
8488 12:12:31.928642 TX Vref=22, minBit 3, minWin=23, winSum=396
8489 12:12:31.932044 TX Vref=24, minBit 3, minWin=24, winSum=403
8490 12:12:31.939057 TX Vref=26, minBit 3, minWin=25, winSum=417
8491 12:12:31.942209 TX Vref=28, minBit 9, minWin=25, winSum=418
8492 12:12:31.945049 TX Vref=30, minBit 0, minWin=25, winSum=413
8493 12:12:31.948312 TX Vref=32, minBit 3, minWin=24, winSum=404
8494 12:12:31.951922 TX Vref=34, minBit 14, minWin=23, winSum=396
8495 12:12:31.958319 [TxChooseVref] Worse bit 9, Min win 25, Win sum 418, Final Vref 28
8496 12:12:31.958758
8497 12:12:31.961696 Final TX Range 0 Vref 28
8498 12:12:31.962117
8499 12:12:31.962447 ==
8500 12:12:31.965024 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 12:12:31.968363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 12:12:31.968789 ==
8503 12:12:31.969125
8504 12:12:31.971579
8505 12:12:31.972004 TX Vref Scan disable
8506 12:12:31.977909 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8507 12:12:31.978379 == TX Byte 0 ==
8508 12:12:31.981322 u2DelayCellOfst[0]=14 cells (4 PI)
8509 12:12:31.984973 u2DelayCellOfst[1]=10 cells (3 PI)
8510 12:12:31.988175 u2DelayCellOfst[2]=0 cells (0 PI)
8511 12:12:31.991138 u2DelayCellOfst[3]=7 cells (2 PI)
8512 12:12:31.994455 u2DelayCellOfst[4]=10 cells (3 PI)
8513 12:12:31.998245 u2DelayCellOfst[5]=17 cells (5 PI)
8514 12:12:32.001225 u2DelayCellOfst[6]=14 cells (4 PI)
8515 12:12:32.004889 u2DelayCellOfst[7]=7 cells (2 PI)
8516 12:12:32.008093 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8517 12:12:32.011414 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8518 12:12:32.014738 == TX Byte 1 ==
8519 12:12:32.018048 u2DelayCellOfst[8]=0 cells (0 PI)
8520 12:12:32.021080 u2DelayCellOfst[9]=3 cells (1 PI)
8521 12:12:32.024731 u2DelayCellOfst[10]=14 cells (4 PI)
8522 12:12:32.027502 u2DelayCellOfst[11]=3 cells (1 PI)
8523 12:12:32.027903 u2DelayCellOfst[12]=14 cells (4 PI)
8524 12:12:32.031042 u2DelayCellOfst[13]=14 cells (4 PI)
8525 12:12:32.034084 u2DelayCellOfst[14]=17 cells (5 PI)
8526 12:12:32.037256 u2DelayCellOfst[15]=21 cells (6 PI)
8527 12:12:32.044592 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8528 12:12:32.047442 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8529 12:12:32.050317 DramC Write-DBI on
8530 12:12:32.050705 ==
8531 12:12:32.053676 Dram Type= 6, Freq= 0, CH_1, rank 0
8532 12:12:32.057337 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8533 12:12:32.057745 ==
8534 12:12:32.058083
8535 12:12:32.058404
8536 12:12:32.060114 TX Vref Scan disable
8537 12:12:32.060513 == TX Byte 0 ==
8538 12:12:32.067345 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8539 12:12:32.067796 == TX Byte 1 ==
8540 12:12:32.070593 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8541 12:12:32.073972 DramC Write-DBI off
8542 12:12:32.074378
8543 12:12:32.074714 [DATLAT]
8544 12:12:32.077172 Freq=1600, CH1 RK0
8545 12:12:32.077627
8546 12:12:32.077961 DATLAT Default: 0xf
8547 12:12:32.080268 0, 0xFFFF, sum = 0
8548 12:12:32.080717 1, 0xFFFF, sum = 0
8549 12:12:32.083694 2, 0xFFFF, sum = 0
8550 12:12:32.086942 3, 0xFFFF, sum = 0
8551 12:12:32.087430 4, 0xFFFF, sum = 0
8552 12:12:32.089852 5, 0xFFFF, sum = 0
8553 12:12:32.090279 6, 0xFFFF, sum = 0
8554 12:12:32.093151 7, 0xFFFF, sum = 0
8555 12:12:32.093577 8, 0xFFFF, sum = 0
8556 12:12:32.097001 9, 0xFFFF, sum = 0
8557 12:12:32.097540 10, 0xFFFF, sum = 0
8558 12:12:32.099802 11, 0xFFFF, sum = 0
8559 12:12:32.100244 12, 0xFFFF, sum = 0
8560 12:12:32.103196 13, 0xFFFF, sum = 0
8561 12:12:32.103719 14, 0x0, sum = 1
8562 12:12:32.106520 15, 0x0, sum = 2
8563 12:12:32.106970 16, 0x0, sum = 3
8564 12:12:32.109582 17, 0x0, sum = 4
8565 12:12:32.110028 best_step = 15
8566 12:12:32.110365
8567 12:12:32.110693 ==
8568 12:12:32.113463 Dram Type= 6, Freq= 0, CH_1, rank 0
8569 12:12:32.119489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8570 12:12:32.119933 ==
8571 12:12:32.120288 RX Vref Scan: 1
8572 12:12:32.120743
8573 12:12:32.122991 Set Vref Range= 24 -> 127
8574 12:12:32.123521
8575 12:12:32.126233 RX Vref 24 -> 127, step: 1
8576 12:12:32.126683
8577 12:12:32.127036 RX Delay 11 -> 252, step: 4
8578 12:12:32.129437
8579 12:12:32.129892 Set Vref, RX VrefLevel [Byte0]: 24
8580 12:12:32.133263 [Byte1]: 24
8581 12:12:32.137000
8582 12:12:32.137478 Set Vref, RX VrefLevel [Byte0]: 25
8583 12:12:32.140172 [Byte1]: 25
8584 12:12:32.144359
8585 12:12:32.144813 Set Vref, RX VrefLevel [Byte0]: 26
8586 12:12:32.148105 [Byte1]: 26
8587 12:12:32.152349
8588 12:12:32.152849 Set Vref, RX VrefLevel [Byte0]: 27
8589 12:12:32.155840 [Byte1]: 27
8590 12:12:32.160042
8591 12:12:32.160545 Set Vref, RX VrefLevel [Byte0]: 28
8592 12:12:32.163037 [Byte1]: 28
8593 12:12:32.167284
8594 12:12:32.167835 Set Vref, RX VrefLevel [Byte0]: 29
8595 12:12:32.170878 [Byte1]: 29
8596 12:12:32.175090
8597 12:12:32.175569 Set Vref, RX VrefLevel [Byte0]: 30
8598 12:12:32.178182 [Byte1]: 30
8599 12:12:32.182370
8600 12:12:32.182807 Set Vref, RX VrefLevel [Byte0]: 31
8601 12:12:32.185937 [Byte1]: 31
8602 12:12:32.190115
8603 12:12:32.190555 Set Vref, RX VrefLevel [Byte0]: 32
8604 12:12:32.193829 [Byte1]: 32
8605 12:12:32.198306
8606 12:12:32.198744 Set Vref, RX VrefLevel [Byte0]: 33
8607 12:12:32.200960 [Byte1]: 33
8608 12:12:32.205447
8609 12:12:32.205883 Set Vref, RX VrefLevel [Byte0]: 34
8610 12:12:32.208736 [Byte1]: 34
8611 12:12:32.212831
8612 12:12:32.213268 Set Vref, RX VrefLevel [Byte0]: 35
8613 12:12:32.216448 [Byte1]: 35
8614 12:12:32.220887
8615 12:12:32.221328 Set Vref, RX VrefLevel [Byte0]: 36
8616 12:12:32.223887 [Byte1]: 36
8617 12:12:32.228553
8618 12:12:32.229087 Set Vref, RX VrefLevel [Byte0]: 37
8619 12:12:32.231636 [Byte1]: 37
8620 12:12:32.236190
8621 12:12:32.236629 Set Vref, RX VrefLevel [Byte0]: 38
8622 12:12:32.239404 [Byte1]: 38
8623 12:12:32.243484
8624 12:12:32.243936 Set Vref, RX VrefLevel [Byte0]: 39
8625 12:12:32.247084 [Byte1]: 39
8626 12:12:32.251441
8627 12:12:32.251901 Set Vref, RX VrefLevel [Byte0]: 40
8628 12:12:32.254629 [Byte1]: 40
8629 12:12:32.258622
8630 12:12:32.259078 Set Vref, RX VrefLevel [Byte0]: 41
8631 12:12:32.262305 [Byte1]: 41
8632 12:12:32.266625
8633 12:12:32.267068 Set Vref, RX VrefLevel [Byte0]: 42
8634 12:12:32.269480 [Byte1]: 42
8635 12:12:32.274237
8636 12:12:32.274708 Set Vref, RX VrefLevel [Byte0]: 43
8637 12:12:32.277016 [Byte1]: 43
8638 12:12:32.281502
8639 12:12:32.281976 Set Vref, RX VrefLevel [Byte0]: 44
8640 12:12:32.285695 [Byte1]: 44
8641 12:12:32.289048
8642 12:12:32.289506 Set Vref, RX VrefLevel [Byte0]: 45
8643 12:12:32.292329 [Byte1]: 45
8644 12:12:32.296877
8645 12:12:32.297317 Set Vref, RX VrefLevel [Byte0]: 46
8646 12:12:32.299888 [Byte1]: 46
8647 12:12:32.304355
8648 12:12:32.304795 Set Vref, RX VrefLevel [Byte0]: 47
8649 12:12:32.307968 [Byte1]: 47
8650 12:12:32.311872
8651 12:12:32.312327 Set Vref, RX VrefLevel [Byte0]: 48
8652 12:12:32.315292 [Byte1]: 48
8653 12:12:32.319649
8654 12:12:32.320086 Set Vref, RX VrefLevel [Byte0]: 49
8655 12:12:32.323629 [Byte1]: 49
8656 12:12:32.326973
8657 12:12:32.327459 Set Vref, RX VrefLevel [Byte0]: 50
8658 12:12:32.330928 [Byte1]: 50
8659 12:12:32.334928
8660 12:12:32.335561 Set Vref, RX VrefLevel [Byte0]: 51
8661 12:12:32.338152 [Byte1]: 51
8662 12:12:32.342245
8663 12:12:32.342698 Set Vref, RX VrefLevel [Byte0]: 52
8664 12:12:32.345797 [Byte1]: 52
8665 12:12:32.350071
8666 12:12:32.350525 Set Vref, RX VrefLevel [Byte0]: 53
8667 12:12:32.353364 [Byte1]: 53
8668 12:12:32.358049
8669 12:12:32.358588 Set Vref, RX VrefLevel [Byte0]: 54
8670 12:12:32.361199 [Byte1]: 54
8671 12:12:32.365324
8672 12:12:32.365779 Set Vref, RX VrefLevel [Byte0]: 55
8673 12:12:32.368523 [Byte1]: 55
8674 12:12:32.372819
8675 12:12:32.373255 Set Vref, RX VrefLevel [Byte0]: 56
8676 12:12:32.376193 [Byte1]: 56
8677 12:12:32.380529
8678 12:12:32.380983 Set Vref, RX VrefLevel [Byte0]: 57
8679 12:12:32.383735 [Byte1]: 57
8680 12:12:32.387959
8681 12:12:32.388401 Set Vref, RX VrefLevel [Byte0]: 58
8682 12:12:32.391592 [Byte1]: 58
8683 12:12:32.396235
8684 12:12:32.396679 Set Vref, RX VrefLevel [Byte0]: 59
8685 12:12:32.398803 [Byte1]: 59
8686 12:12:32.403203
8687 12:12:32.403717 Set Vref, RX VrefLevel [Byte0]: 60
8688 12:12:32.406687 [Byte1]: 60
8689 12:12:32.410911
8690 12:12:32.411395 Set Vref, RX VrefLevel [Byte0]: 61
8691 12:12:32.414436 [Byte1]: 61
8692 12:12:32.418382
8693 12:12:32.418864 Set Vref, RX VrefLevel [Byte0]: 62
8694 12:12:32.421641 [Byte1]: 62
8695 12:12:32.426280
8696 12:12:32.426793 Set Vref, RX VrefLevel [Byte0]: 63
8697 12:12:32.429467 [Byte1]: 63
8698 12:12:32.434393
8699 12:12:32.434904 Set Vref, RX VrefLevel [Byte0]: 64
8700 12:12:32.436862 [Byte1]: 64
8701 12:12:32.441348
8702 12:12:32.441790 Set Vref, RX VrefLevel [Byte0]: 65
8703 12:12:32.444525 [Byte1]: 65
8704 12:12:32.449000
8705 12:12:32.449448 Set Vref, RX VrefLevel [Byte0]: 66
8706 12:12:32.452594 [Byte1]: 66
8707 12:12:32.456699
8708 12:12:32.457264 Set Vref, RX VrefLevel [Byte0]: 67
8709 12:12:32.460388 [Byte1]: 67
8710 12:12:32.464118
8711 12:12:32.464562 Set Vref, RX VrefLevel [Byte0]: 68
8712 12:12:32.467439 [Byte1]: 68
8713 12:12:32.471782
8714 12:12:32.472159 Set Vref, RX VrefLevel [Byte0]: 69
8715 12:12:32.475324 [Byte1]: 69
8716 12:12:32.479334
8717 12:12:32.479897 Set Vref, RX VrefLevel [Byte0]: 70
8718 12:12:32.482597 [Byte1]: 70
8719 12:12:32.487410
8720 12:12:32.487916 Set Vref, RX VrefLevel [Byte0]: 71
8721 12:12:32.490419 [Byte1]: 71
8722 12:12:32.495012
8723 12:12:32.495643 Final RX Vref Byte 0 = 62 to rank0
8724 12:12:32.498314 Final RX Vref Byte 1 = 62 to rank0
8725 12:12:32.501286 Final RX Vref Byte 0 = 62 to rank1
8726 12:12:32.505028 Final RX Vref Byte 1 = 62 to rank1==
8727 12:12:32.508138 Dram Type= 6, Freq= 0, CH_1, rank 0
8728 12:12:32.514556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8729 12:12:32.515002 ==
8730 12:12:32.515356 DQS Delay:
8731 12:12:32.515773 DQS0 = 0, DQS1 = 0
8732 12:12:32.518250 DQM Delay:
8733 12:12:32.518665 DQM0 = 133, DQM1 = 128
8734 12:12:32.521445 DQ Delay:
8735 12:12:32.524919 DQ0 =140, DQ1 =132, DQ2 =118, DQ3 =132
8736 12:12:32.528429 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =130
8737 12:12:32.531453 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =120
8738 12:12:32.534766 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8739 12:12:32.535205
8740 12:12:32.535616
8741 12:12:32.535952
8742 12:12:32.538053 [DramC_TX_OE_Calibration] TA2
8743 12:12:32.541234 Original DQ_B0 (3 6) =30, OEN = 27
8744 12:12:32.544630 Original DQ_B1 (3 6) =30, OEN = 27
8745 12:12:32.548045 24, 0x0, End_B0=24 End_B1=24
8746 12:12:32.548593 25, 0x0, End_B0=25 End_B1=25
8747 12:12:32.551534 26, 0x0, End_B0=26 End_B1=26
8748 12:12:32.554900 27, 0x0, End_B0=27 End_B1=27
8749 12:12:32.557676 28, 0x0, End_B0=28 End_B1=28
8750 12:12:32.560804 29, 0x0, End_B0=29 End_B1=29
8751 12:12:32.561227 30, 0x0, End_B0=30 End_B1=30
8752 12:12:32.564120 31, 0x4141, End_B0=30 End_B1=30
8753 12:12:32.567208 Byte0 end_step=30 best_step=27
8754 12:12:32.570679 Byte1 end_step=30 best_step=27
8755 12:12:32.573586 Byte0 TX OE(2T, 0.5T) = (3, 3)
8756 12:12:32.577382 Byte1 TX OE(2T, 0.5T) = (3, 3)
8757 12:12:32.577463
8758 12:12:32.577527
8759 12:12:32.583270 [DQSOSCAuto] RK0, (LSB)MR18= 0xc16, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8760 12:12:32.587116 CH1 RK0: MR19=303, MR18=C16
8761 12:12:32.593229 CH1_RK0: MR19=0x303, MR18=0xC16, DQSOSC=398, MR23=63, INC=23, DEC=15
8762 12:12:32.593311
8763 12:12:32.596328 ----->DramcWriteLeveling(PI) begin...
8764 12:12:32.596411 ==
8765 12:12:32.599797 Dram Type= 6, Freq= 0, CH_1, rank 1
8766 12:12:32.602949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8767 12:12:32.603030 ==
8768 12:12:32.606358 Write leveling (Byte 0): 22 => 22
8769 12:12:32.609847 Write leveling (Byte 1): 26 => 26
8770 12:12:32.613110 DramcWriteLeveling(PI) end<-----
8771 12:12:32.613191
8772 12:12:32.613255 ==
8773 12:12:32.616392 Dram Type= 6, Freq= 0, CH_1, rank 1
8774 12:12:32.620068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 12:12:32.620149 ==
8776 12:12:32.623657 [Gating] SW mode calibration
8777 12:12:32.629490 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8778 12:12:32.636419 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8779 12:12:32.639894 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 12:12:32.646080 1 4 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8781 12:12:32.649530 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8782 12:12:32.652549 1 4 12 | B1->B0 | 2525 3434 | 0 1 | (1 1) (1 1)
8783 12:12:32.659526 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
8784 12:12:32.662645 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 12:12:32.665856 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 12:12:32.672370 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 12:12:32.675478 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 12:12:32.678836 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8789 12:12:32.685789 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 1)
8790 12:12:32.688842 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8791 12:12:32.692125 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8792 12:12:32.699022 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 12:12:32.702048 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 12:12:32.705058 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 12:12:32.711862 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 12:12:32.715084 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8797 12:12:32.718330 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8798 12:12:32.725120 1 6 12 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
8799 12:12:32.728446 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 12:12:32.731324 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 12:12:32.738451 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 12:12:32.741581 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 12:12:32.744990 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 12:12:32.751892 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 12:12:32.754897 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8806 12:12:32.757891 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8807 12:12:32.764547 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 12:12:32.767926 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 12:12:32.771930 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 12:12:32.778003 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 12:12:32.780927 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 12:12:32.784435 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 12:12:32.790625 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 12:12:32.794443 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 12:12:32.797959 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 12:12:32.804662 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 12:12:32.807263 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 12:12:32.810702 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 12:12:32.817056 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 12:12:32.821035 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8821 12:12:32.823467 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8822 12:12:32.830184 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8823 12:12:32.833993 Total UI for P1: 0, mck2ui 16
8824 12:12:32.836842 best dqsien dly found for B0: ( 1, 9, 6)
8825 12:12:32.840083 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 12:12:32.843808 Total UI for P1: 0, mck2ui 16
8827 12:12:32.847451 best dqsien dly found for B1: ( 1, 9, 12)
8828 12:12:32.849968 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8829 12:12:32.853131 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8830 12:12:32.853204
8831 12:12:32.856953 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8832 12:12:32.863119 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8833 12:12:32.863197 [Gating] SW calibration Done
8834 12:12:32.863261 ==
8835 12:12:32.866391 Dram Type= 6, Freq= 0, CH_1, rank 1
8836 12:12:32.872761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8837 12:12:32.872840 ==
8838 12:12:32.872905 RX Vref Scan: 0
8839 12:12:32.872965
8840 12:12:32.876188 RX Vref 0 -> 0, step: 1
8841 12:12:32.876265
8842 12:12:32.879968 RX Delay 0 -> 252, step: 8
8843 12:12:32.883419 iDelay=200, Bit 0, Center 139 (80 ~ 199) 120
8844 12:12:32.886351 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8845 12:12:32.889482 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8846 12:12:32.896110 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8847 12:12:32.899249 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8848 12:12:32.902516 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8849 12:12:32.905875 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8850 12:12:32.909342 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8851 12:12:32.916028 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8852 12:12:32.918997 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8853 12:12:32.922370 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8854 12:12:32.926072 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8855 12:12:32.928870 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8856 12:12:32.935859 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8857 12:12:32.938853 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8858 12:12:32.941900 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8859 12:12:32.941972 ==
8860 12:12:32.945714 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 12:12:32.948635 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 12:12:32.951916 ==
8863 12:12:32.951989 DQS Delay:
8864 12:12:32.952051 DQS0 = 0, DQS1 = 0
8865 12:12:32.955337 DQM Delay:
8866 12:12:32.955449 DQM0 = 134, DQM1 = 131
8867 12:12:32.958934 DQ Delay:
8868 12:12:32.962119 DQ0 =139, DQ1 =135, DQ2 =119, DQ3 =127
8869 12:12:32.965211 DQ4 =135, DQ5 =143, DQ6 =139, DQ7 =135
8870 12:12:32.968717 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8871 12:12:32.971747 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8872 12:12:32.971820
8873 12:12:32.971881
8874 12:12:32.971939 ==
8875 12:12:32.975140 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 12:12:32.978521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 12:12:32.981396 ==
8878 12:12:32.981468
8879 12:12:32.981530
8880 12:12:32.981587 TX Vref Scan disable
8881 12:12:32.985071 == TX Byte 0 ==
8882 12:12:32.988230 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8883 12:12:32.991519 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8884 12:12:32.994983 == TX Byte 1 ==
8885 12:12:32.998229 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8886 12:12:33.001482 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8887 12:12:33.004585 ==
8888 12:12:33.008099 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 12:12:33.011371 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 12:12:33.011461 ==
8891 12:12:33.026081
8892 12:12:33.029373 TX Vref early break, caculate TX vref
8893 12:12:33.032543 TX Vref=16, minBit 9, minWin=21, winSum=374
8894 12:12:33.035717 TX Vref=18, minBit 9, minWin=22, winSum=383
8895 12:12:33.039147 TX Vref=20, minBit 9, minWin=22, winSum=397
8896 12:12:33.042620 TX Vref=22, minBit 9, minWin=23, winSum=402
8897 12:12:33.045686 TX Vref=24, minBit 9, minWin=23, winSum=406
8898 12:12:33.052323 TX Vref=26, minBit 9, minWin=24, winSum=412
8899 12:12:33.055630 TX Vref=28, minBit 9, minWin=25, winSum=416
8900 12:12:33.058992 TX Vref=30, minBit 0, minWin=25, winSum=413
8901 12:12:33.062339 TX Vref=32, minBit 8, minWin=24, winSum=407
8902 12:12:33.065336 TX Vref=34, minBit 9, minWin=23, winSum=402
8903 12:12:33.071857 TX Vref=36, minBit 9, minWin=23, winSum=396
8904 12:12:33.075049 TX Vref=38, minBit 0, minWin=23, winSum=382
8905 12:12:33.081754 [TxChooseVref] Worse bit 9, Min win 25, Win sum 416, Final Vref 28
8906 12:12:33.081831
8907 12:12:33.081895 Final TX Range 0 Vref 28
8908 12:12:33.081956
8909 12:12:33.082017 ==
8910 12:12:33.084890 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 12:12:33.091939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 12:12:33.092019 ==
8913 12:12:33.092095
8914 12:12:33.092159
8915 12:12:33.092223 TX Vref Scan disable
8916 12:12:33.099116 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8917 12:12:33.099190 == TX Byte 0 ==
8918 12:12:33.102003 u2DelayCellOfst[0]=14 cells (4 PI)
8919 12:12:33.105378 u2DelayCellOfst[1]=10 cells (3 PI)
8920 12:12:33.108572 u2DelayCellOfst[2]=0 cells (0 PI)
8921 12:12:33.112177 u2DelayCellOfst[3]=7 cells (2 PI)
8922 12:12:33.115271 u2DelayCellOfst[4]=10 cells (3 PI)
8923 12:12:33.118898 u2DelayCellOfst[5]=14 cells (4 PI)
8924 12:12:33.121910 u2DelayCellOfst[6]=14 cells (4 PI)
8925 12:12:33.125563 u2DelayCellOfst[7]=7 cells (2 PI)
8926 12:12:33.128913 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8927 12:12:33.131683 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8928 12:12:33.135326 == TX Byte 1 ==
8929 12:12:33.138784 u2DelayCellOfst[8]=0 cells (0 PI)
8930 12:12:33.141512 u2DelayCellOfst[9]=7 cells (2 PI)
8931 12:12:33.144884 u2DelayCellOfst[10]=14 cells (4 PI)
8932 12:12:33.148846 u2DelayCellOfst[11]=10 cells (3 PI)
8933 12:12:33.151667 u2DelayCellOfst[12]=17 cells (5 PI)
8934 12:12:33.154903 u2DelayCellOfst[13]=17 cells (5 PI)
8935 12:12:33.158890 u2DelayCellOfst[14]=21 cells (6 PI)
8936 12:12:33.161481 u2DelayCellOfst[15]=21 cells (6 PI)
8937 12:12:33.164736 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8938 12:12:33.167925 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8939 12:12:33.171373 DramC Write-DBI on
8940 12:12:33.171474 ==
8941 12:12:33.175017 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 12:12:33.178438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 12:12:33.178511 ==
8944 12:12:33.178576
8945 12:12:33.178635
8946 12:12:33.181300 TX Vref Scan disable
8947 12:12:33.184708 == TX Byte 0 ==
8948 12:12:33.187564 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8949 12:12:33.187681 == TX Byte 1 ==
8950 12:12:33.194888 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8951 12:12:33.194968 DramC Write-DBI off
8952 12:12:33.195032
8953 12:12:33.195091 [DATLAT]
8954 12:12:33.197554 Freq=1600, CH1 RK1
8955 12:12:33.197625
8956 12:12:33.201145 DATLAT Default: 0xf
8957 12:12:33.201217 0, 0xFFFF, sum = 0
8958 12:12:33.204675 1, 0xFFFF, sum = 0
8959 12:12:33.204748 2, 0xFFFF, sum = 0
8960 12:12:33.207580 3, 0xFFFF, sum = 0
8961 12:12:33.207652 4, 0xFFFF, sum = 0
8962 12:12:33.210743 5, 0xFFFF, sum = 0
8963 12:12:33.210818 6, 0xFFFF, sum = 0
8964 12:12:33.214225 7, 0xFFFF, sum = 0
8965 12:12:33.214298 8, 0xFFFF, sum = 0
8966 12:12:33.217244 9, 0xFFFF, sum = 0
8967 12:12:33.217317 10, 0xFFFF, sum = 0
8968 12:12:33.220821 11, 0xFFFF, sum = 0
8969 12:12:33.220894 12, 0xFFFF, sum = 0
8970 12:12:33.224290 13, 0xFFFF, sum = 0
8971 12:12:33.224363 14, 0x0, sum = 1
8972 12:12:33.227343 15, 0x0, sum = 2
8973 12:12:33.227433 16, 0x0, sum = 3
8974 12:12:33.230781 17, 0x0, sum = 4
8975 12:12:33.230856 best_step = 15
8976 12:12:33.230918
8977 12:12:33.230981 ==
8978 12:12:33.233855 Dram Type= 6, Freq= 0, CH_1, rank 1
8979 12:12:33.240439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8980 12:12:33.240531 ==
8981 12:12:33.240595 RX Vref Scan: 0
8982 12:12:33.240655
8983 12:12:33.244600 RX Vref 0 -> 0, step: 1
8984 12:12:33.244674
8985 12:12:33.247589 RX Delay 11 -> 252, step: 4
8986 12:12:33.250608 iDelay=195, Bit 0, Center 136 (83 ~ 190) 108
8987 12:12:33.253863 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8988 12:12:33.260336 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8989 12:12:33.263709 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8990 12:12:33.267800 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8991 12:12:33.270745 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8992 12:12:33.273646 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8993 12:12:33.277266 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8994 12:12:33.283684 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8995 12:12:33.286947 iDelay=195, Bit 9, Center 116 (63 ~ 170) 108
8996 12:12:33.290365 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8997 12:12:33.293522 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8998 12:12:33.300724 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8999 12:12:33.303204 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9000 12:12:33.307016 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9001 12:12:33.310253 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9002 12:12:33.310330 ==
9003 12:12:33.313413 Dram Type= 6, Freq= 0, CH_1, rank 1
9004 12:12:33.319762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9005 12:12:33.319839 ==
9006 12:12:33.319902 DQS Delay:
9007 12:12:33.323324 DQS0 = 0, DQS1 = 0
9008 12:12:33.323435 DQM Delay:
9009 12:12:33.323500 DQM0 = 131, DQM1 = 127
9010 12:12:33.326532 DQ Delay:
9011 12:12:33.329964 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =128
9012 12:12:33.333391 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =128
9013 12:12:33.336159 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
9014 12:12:33.339489 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
9015 12:12:33.339570
9016 12:12:33.339634
9017 12:12:33.339693
9018 12:12:33.343118 [DramC_TX_OE_Calibration] TA2
9019 12:12:33.346509 Original DQ_B0 (3 6) =30, OEN = 27
9020 12:12:33.350010 Original DQ_B1 (3 6) =30, OEN = 27
9021 12:12:33.352896 24, 0x0, End_B0=24 End_B1=24
9022 12:12:33.356121 25, 0x0, End_B0=25 End_B1=25
9023 12:12:33.356203 26, 0x0, End_B0=26 End_B1=26
9024 12:12:33.359483 27, 0x0, End_B0=27 End_B1=27
9025 12:12:33.362537 28, 0x0, End_B0=28 End_B1=28
9026 12:12:33.366083 29, 0x0, End_B0=29 End_B1=29
9027 12:12:33.366165 30, 0x0, End_B0=30 End_B1=30
9028 12:12:33.369904 31, 0x4141, End_B0=30 End_B1=30
9029 12:12:33.373444 Byte0 end_step=30 best_step=27
9030 12:12:33.376539 Byte1 end_step=30 best_step=27
9031 12:12:33.379402 Byte0 TX OE(2T, 0.5T) = (3, 3)
9032 12:12:33.382354 Byte1 TX OE(2T, 0.5T) = (3, 3)
9033 12:12:33.382436
9034 12:12:33.382500
9035 12:12:33.389616 [DQSOSCAuto] RK1, (LSB)MR18= 0xd1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
9036 12:12:33.392578 CH1 RK1: MR19=303, MR18=D1B
9037 12:12:33.398854 CH1_RK1: MR19=0x303, MR18=0xD1B, DQSOSC=396, MR23=63, INC=23, DEC=15
9038 12:12:33.402138 [RxdqsGatingPostProcess] freq 1600
9039 12:12:33.405415 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9040 12:12:33.408610 best DQS0 dly(2T, 0.5T) = (1, 1)
9041 12:12:33.412560 best DQS1 dly(2T, 0.5T) = (1, 1)
9042 12:12:33.415558 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9043 12:12:33.418811 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9044 12:12:33.421790 best DQS0 dly(2T, 0.5T) = (1, 1)
9045 12:12:33.425190 best DQS1 dly(2T, 0.5T) = (1, 1)
9046 12:12:33.428350 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9047 12:12:33.431929 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9048 12:12:33.434960 Pre-setting of DQS Precalculation
9049 12:12:33.438104 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9050 12:12:33.448051 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9051 12:12:33.454645 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9052 12:12:33.454727
9053 12:12:33.454790
9054 12:12:33.457946 [Calibration Summary] 3200 Mbps
9055 12:12:33.458027 CH 0, Rank 0
9056 12:12:33.461319 SW Impedance : PASS
9057 12:12:33.461442 DUTY Scan : NO K
9058 12:12:33.464462 ZQ Calibration : PASS
9059 12:12:33.467944 Jitter Meter : NO K
9060 12:12:33.468025 CBT Training : PASS
9061 12:12:33.471265 Write leveling : PASS
9062 12:12:33.474347 RX DQS gating : PASS
9063 12:12:33.474428 RX DQ/DQS(RDDQC) : PASS
9064 12:12:33.477931 TX DQ/DQS : PASS
9065 12:12:33.481124 RX DATLAT : PASS
9066 12:12:33.481205 RX DQ/DQS(Engine): PASS
9067 12:12:33.484992 TX OE : PASS
9068 12:12:33.485073 All Pass.
9069 12:12:33.485137
9070 12:12:33.488201 CH 0, Rank 1
9071 12:12:33.488282 SW Impedance : PASS
9072 12:12:33.491571 DUTY Scan : NO K
9073 12:12:33.494417 ZQ Calibration : PASS
9074 12:12:33.494498 Jitter Meter : NO K
9075 12:12:33.497714 CBT Training : PASS
9076 12:12:33.501193 Write leveling : PASS
9077 12:12:33.501274 RX DQS gating : PASS
9078 12:12:33.504520 RX DQ/DQS(RDDQC) : PASS
9079 12:12:33.507871 TX DQ/DQS : PASS
9080 12:12:33.507952 RX DATLAT : PASS
9081 12:12:33.511126 RX DQ/DQS(Engine): PASS
9082 12:12:33.511207 TX OE : PASS
9083 12:12:33.514376 All Pass.
9084 12:12:33.514457
9085 12:12:33.514521 CH 1, Rank 0
9086 12:12:33.517659 SW Impedance : PASS
9087 12:12:33.521277 DUTY Scan : NO K
9088 12:12:33.521358 ZQ Calibration : PASS
9089 12:12:33.524356 Jitter Meter : NO K
9090 12:12:33.524437 CBT Training : PASS
9091 12:12:33.527201 Write leveling : PASS
9092 12:12:33.531131 RX DQS gating : PASS
9093 12:12:33.531212 RX DQ/DQS(RDDQC) : PASS
9094 12:12:33.533922 TX DQ/DQS : PASS
9095 12:12:33.537276 RX DATLAT : PASS
9096 12:12:33.537357 RX DQ/DQS(Engine): PASS
9097 12:12:33.540436 TX OE : PASS
9098 12:12:33.540518 All Pass.
9099 12:12:33.540582
9100 12:12:33.543967 CH 1, Rank 1
9101 12:12:33.544047 SW Impedance : PASS
9102 12:12:33.547265 DUTY Scan : NO K
9103 12:12:33.550688 ZQ Calibration : PASS
9104 12:12:33.550769 Jitter Meter : NO K
9105 12:12:33.553665 CBT Training : PASS
9106 12:12:33.556692 Write leveling : PASS
9107 12:12:33.556782 RX DQS gating : PASS
9108 12:12:33.560063 RX DQ/DQS(RDDQC) : PASS
9109 12:12:33.563487 TX DQ/DQS : PASS
9110 12:12:33.563601 RX DATLAT : PASS
9111 12:12:33.566632 RX DQ/DQS(Engine): PASS
9112 12:12:33.570013 TX OE : PASS
9113 12:12:33.570094 All Pass.
9114 12:12:33.570158
9115 12:12:33.573289 DramC Write-DBI on
9116 12:12:33.573370 PER_BANK_REFRESH: Hybrid Mode
9117 12:12:33.576748 TX_TRACKING: ON
9118 12:12:33.586417 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9119 12:12:33.593119 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9120 12:12:33.599479 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9121 12:12:33.602774 [FAST_K] Save calibration result to emmc
9122 12:12:33.606331 sync common calibartion params.
9123 12:12:33.609373 sync cbt_mode0:1, 1:1
9124 12:12:33.609454 dram_init: ddr_geometry: 2
9125 12:12:33.612421 dram_init: ddr_geometry: 2
9126 12:12:33.616171 dram_init: ddr_geometry: 2
9127 12:12:33.619382 0:dram_rank_size:100000000
9128 12:12:33.619466 1:dram_rank_size:100000000
9129 12:12:33.625642 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9130 12:12:33.629006 DFS_SHUFFLE_HW_MODE: ON
9131 12:12:33.632505 dramc_set_vcore_voltage set vcore to 725000
9132 12:12:33.635620 Read voltage for 1600, 0
9133 12:12:33.635723 Vio18 = 0
9134 12:12:33.635789 Vcore = 725000
9135 12:12:33.638853 Vdram = 0
9136 12:12:33.638933 Vddq = 0
9137 12:12:33.638997 Vmddr = 0
9138 12:12:33.642417 switch to 3200 Mbps bootup
9139 12:12:33.642499 [DramcRunTimeConfig]
9140 12:12:33.645787 PHYPLL
9141 12:12:33.645868 DPM_CONTROL_AFTERK: ON
9142 12:12:33.649115 PER_BANK_REFRESH: ON
9143 12:12:33.651792 REFRESH_OVERHEAD_REDUCTION: ON
9144 12:12:33.651873 CMD_PICG_NEW_MODE: OFF
9145 12:12:33.655117 XRTWTW_NEW_MODE: ON
9146 12:12:33.655198 XRTRTR_NEW_MODE: ON
9147 12:12:33.658937 TX_TRACKING: ON
9148 12:12:33.659026 RDSEL_TRACKING: OFF
9149 12:12:33.661980 DQS Precalculation for DVFS: ON
9150 12:12:33.665324 RX_TRACKING: OFF
9151 12:12:33.665447 HW_GATING DBG: ON
9152 12:12:33.668935 ZQCS_ENABLE_LP4: ON
9153 12:12:33.669015 RX_PICG_NEW_MODE: ON
9154 12:12:33.672103 TX_PICG_NEW_MODE: ON
9155 12:12:33.675410 ENABLE_RX_DCM_DPHY: ON
9156 12:12:33.678857 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9157 12:12:33.678938 DUMMY_READ_FOR_TRACKING: OFF
9158 12:12:33.682131 !!! SPM_CONTROL_AFTERK: OFF
9159 12:12:33.685285 !!! SPM could not control APHY
9160 12:12:33.688318 IMPEDANCE_TRACKING: ON
9161 12:12:33.688400 TEMP_SENSOR: ON
9162 12:12:33.691920 HW_SAVE_FOR_SR: OFF
9163 12:12:33.692001 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9164 12:12:33.698463 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9165 12:12:33.698548 Read ODT Tracking: ON
9166 12:12:33.701228 Refresh Rate DeBounce: ON
9167 12:12:33.705110 DFS_NO_QUEUE_FLUSH: ON
9168 12:12:33.705191 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9169 12:12:33.708036 ENABLE_DFS_RUNTIME_MRW: OFF
9170 12:12:33.711552 DDR_RESERVE_NEW_MODE: ON
9171 12:12:33.715095 MR_CBT_SWITCH_FREQ: ON
9172 12:12:33.715176 =========================
9173 12:12:33.734243 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9174 12:12:33.737875 dram_init: ddr_geometry: 2
9175 12:12:33.755931 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9176 12:12:33.758938 dram_init: dram init end (result: 0)
9177 12:12:33.766296 DRAM-K: Full calibration passed in 24401 msecs
9178 12:12:33.769163 MRC: failed to locate region type 0.
9179 12:12:33.769245 DRAM rank0 size:0x100000000,
9180 12:12:33.772343 DRAM rank1 size=0x100000000
9181 12:12:33.782088 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9182 12:12:33.789690 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9183 12:12:33.795704 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9184 12:12:33.805609 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9185 12:12:33.805690 DRAM rank0 size:0x100000000,
9186 12:12:33.808578 DRAM rank1 size=0x100000000
9187 12:12:33.808659 CBMEM:
9188 12:12:33.812046 IMD: root @ 0xfffff000 254 entries.
9189 12:12:33.815541 IMD: root @ 0xffffec00 62 entries.
9190 12:12:33.818583 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9191 12:12:33.825505 WARNING: RO_VPD is uninitialized or empty.
9192 12:12:33.828564 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9193 12:12:33.836537 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9194 12:12:33.848580 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9195 12:12:33.859972 BS: romstage times (exec / console): total (unknown) / 23932 ms
9196 12:12:33.860053
9197 12:12:33.860118
9198 12:12:33.869892 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9199 12:12:33.873345 ARM64: Exception handlers installed.
9200 12:12:33.876635 ARM64: Testing exception
9201 12:12:33.880016 ARM64: Done test exception
9202 12:12:33.880097 Enumerating buses...
9203 12:12:33.883349 Show all devs... Before device enumeration.
9204 12:12:33.886144 Root Device: enabled 1
9205 12:12:33.889455 CPU_CLUSTER: 0: enabled 1
9206 12:12:33.889537 CPU: 00: enabled 1
9207 12:12:33.893035 Compare with tree...
9208 12:12:33.893116 Root Device: enabled 1
9209 12:12:33.896354 CPU_CLUSTER: 0: enabled 1
9210 12:12:33.899693 CPU: 00: enabled 1
9211 12:12:33.899774 Root Device scanning...
9212 12:12:33.902708 scan_static_bus for Root Device
9213 12:12:33.906070 CPU_CLUSTER: 0 enabled
9214 12:12:33.909236 scan_static_bus for Root Device done
9215 12:12:33.912436 scan_bus: bus Root Device finished in 8 msecs
9216 12:12:33.912518 done
9217 12:12:33.918908 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9218 12:12:33.922683 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9219 12:12:33.928816 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9220 12:12:33.936103 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9221 12:12:33.936184 Allocating resources...
9222 12:12:33.938957 Reading resources...
9223 12:12:33.942351 Root Device read_resources bus 0 link: 0
9224 12:12:33.945829 DRAM rank0 size:0x100000000,
9225 12:12:33.945910 DRAM rank1 size=0x100000000
9226 12:12:33.952143 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9227 12:12:33.952224 CPU: 00 missing read_resources
9228 12:12:33.958620 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9229 12:12:33.962461 Root Device read_resources bus 0 link: 0 done
9230 12:12:33.965478 Done reading resources.
9231 12:12:33.969023 Show resources in subtree (Root Device)...After reading.
9232 12:12:33.972172 Root Device child on link 0 CPU_CLUSTER: 0
9233 12:12:33.975053 CPU_CLUSTER: 0 child on link 0 CPU: 00
9234 12:12:33.985503 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9235 12:12:33.985585 CPU: 00
9236 12:12:33.991959 Root Device assign_resources, bus 0 link: 0
9237 12:12:33.995007 CPU_CLUSTER: 0 missing set_resources
9238 12:12:33.998256 Root Device assign_resources, bus 0 link: 0 done
9239 12:12:34.001867 Done setting resources.
9240 12:12:34.005144 Show resources in subtree (Root Device)...After assigning values.
9241 12:12:34.008051 Root Device child on link 0 CPU_CLUSTER: 0
9242 12:12:34.014625 CPU_CLUSTER: 0 child on link 0 CPU: 00
9243 12:12:34.021639 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9244 12:12:34.024376 CPU: 00
9245 12:12:34.024458 Done allocating resources.
9246 12:12:34.031042 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9247 12:12:34.031124 Enabling resources...
9248 12:12:34.034175 done.
9249 12:12:34.037758 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9250 12:12:34.040851 Initializing devices...
9251 12:12:34.040932 Root Device init
9252 12:12:34.044722 init hardware done!
9253 12:12:34.044803 0x00000018: ctrlr->caps
9254 12:12:34.047563 52.000 MHz: ctrlr->f_max
9255 12:12:34.050762 0.400 MHz: ctrlr->f_min
9256 12:12:34.054333 0x40ff8080: ctrlr->voltages
9257 12:12:34.054416 sclk: 390625
9258 12:12:34.054480 Bus Width = 1
9259 12:12:34.057354 sclk: 390625
9260 12:12:34.057434 Bus Width = 1
9261 12:12:34.060698 Early init status = 3
9262 12:12:34.064272 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9263 12:12:34.068822 in-header: 03 fc 00 00 01 00 00 00
9264 12:12:34.071898 in-data: 00
9265 12:12:34.075148 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9266 12:12:34.079931 in-header: 03 fd 00 00 00 00 00 00
9267 12:12:34.083117 in-data:
9268 12:12:34.086562 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9269 12:12:34.090306 in-header: 03 fc 00 00 01 00 00 00
9270 12:12:34.093011 in-data: 00
9271 12:12:34.096330 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9272 12:12:34.101076 in-header: 03 fd 00 00 00 00 00 00
9273 12:12:34.104246 in-data:
9274 12:12:34.107333 [SSUSB] Setting up USB HOST controller...
9275 12:12:34.111150 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9276 12:12:34.113949 [SSUSB] phy power-on done.
9277 12:12:34.117287 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9278 12:12:34.124316 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9279 12:12:34.127276 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9280 12:12:34.134638 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9281 12:12:34.140527 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9282 12:12:34.147089 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9283 12:12:34.153796 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9284 12:12:34.160042 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9285 12:12:34.163537 SPM: binary array size = 0x9dc
9286 12:12:34.166514 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9287 12:12:34.173814 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9288 12:12:34.180248 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9289 12:12:34.186808 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9290 12:12:34.190066 configure_display: Starting display init
9291 12:12:34.224197 anx7625_power_on_init: Init interface.
9292 12:12:34.228285 anx7625_disable_pd_protocol: Disabled PD feature.
9293 12:12:34.230771 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9294 12:12:34.258606 anx7625_start_dp_work: Secure OCM version=00
9295 12:12:34.262007 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9296 12:12:34.276789 sp_tx_get_edid_block: EDID Block = 1
9297 12:12:34.379558 Extracted contents:
9298 12:12:34.382575 header: 00 ff ff ff ff ff ff 00
9299 12:12:34.386036 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9300 12:12:34.389390 version: 01 04
9301 12:12:34.393165 basic params: 95 1f 11 78 0a
9302 12:12:34.395692 chroma info: 76 90 94 55 54 90 27 21 50 54
9303 12:12:34.399566 established: 00 00 00
9304 12:12:34.405601 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9305 12:12:34.412363 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9306 12:12:34.415466 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9307 12:12:34.422190 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9308 12:12:34.428548 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9309 12:12:34.431657 extensions: 00
9310 12:12:34.431739 checksum: fb
9311 12:12:34.431804
9312 12:12:34.438248 Manufacturer: IVO Model 57d Serial Number 0
9313 12:12:34.438330 Made week 0 of 2020
9314 12:12:34.441803 EDID version: 1.4
9315 12:12:34.441884 Digital display
9316 12:12:34.445259 6 bits per primary color channel
9317 12:12:34.448429 DisplayPort interface
9318 12:12:34.448511 Maximum image size: 31 cm x 17 cm
9319 12:12:34.451993 Gamma: 220%
9320 12:12:34.452074 Check DPMS levels
9321 12:12:34.458479 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9322 12:12:34.461617 First detailed timing is preferred timing
9323 12:12:34.464626 Established timings supported:
9324 12:12:34.464707 Standard timings supported:
9325 12:12:34.468299 Detailed timings
9326 12:12:34.471417 Hex of detail: 383680a07038204018303c0035ae10000019
9327 12:12:34.477764 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9328 12:12:34.481532 0780 0798 07c8 0820 hborder 0
9329 12:12:34.484881 0438 043b 0447 0458 vborder 0
9330 12:12:34.487896 -hsync -vsync
9331 12:12:34.487973 Did detailed timing
9332 12:12:34.494730 Hex of detail: 000000000000000000000000000000000000
9333 12:12:34.497550 Manufacturer-specified data, tag 0
9334 12:12:34.500912 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9335 12:12:34.504164 ASCII string: InfoVision
9336 12:12:34.507525 Hex of detail: 000000fe00523134304e574635205248200a
9337 12:12:34.510580 ASCII string: R140NWF5 RH
9338 12:12:34.510697 Checksum
9339 12:12:34.514501 Checksum: 0xfb (valid)
9340 12:12:34.517435 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9341 12:12:34.521180 DSI data_rate: 832800000 bps
9342 12:12:34.527086 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9343 12:12:34.530646 anx7625_parse_edid: pixelclock(138800).
9344 12:12:34.534596 hactive(1920), hsync(48), hfp(24), hbp(88)
9345 12:12:34.537629 vactive(1080), vsync(12), vfp(3), vbp(17)
9346 12:12:34.540510 anx7625_dsi_config: config dsi.
9347 12:12:34.546867 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9348 12:12:34.561247 anx7625_dsi_config: success to config DSI
9349 12:12:34.564636 anx7625_dp_start: MIPI phy setup OK.
9350 12:12:34.567707 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9351 12:12:34.570948 mtk_ddp_mode_set invalid vrefresh 60
9352 12:12:34.574381 main_disp_path_setup
9353 12:12:34.574462 ovl_layer_smi_id_en
9354 12:12:34.577621 ovl_layer_smi_id_en
9355 12:12:34.577694 ccorr_config
9356 12:12:34.577763 aal_config
9357 12:12:34.581188 gamma_config
9358 12:12:34.581269 postmask_config
9359 12:12:34.584214 dither_config
9360 12:12:34.587766 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9361 12:12:34.594631 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9362 12:12:34.597784 Root Device init finished in 552 msecs
9363 12:12:34.600875 CPU_CLUSTER: 0 init
9364 12:12:34.607275 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9365 12:12:34.613839 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9366 12:12:34.613920 APU_MBOX 0x190000b0 = 0x10001
9367 12:12:34.617357 APU_MBOX 0x190001b0 = 0x10001
9368 12:12:34.620536 APU_MBOX 0x190005b0 = 0x10001
9369 12:12:34.623651 APU_MBOX 0x190006b0 = 0x10001
9370 12:12:34.630189 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9371 12:12:34.640123 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9372 12:12:34.652709 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9373 12:12:34.659029 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9374 12:12:34.671012 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9375 12:12:34.680267 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9376 12:12:34.683604 CPU_CLUSTER: 0 init finished in 81 msecs
9377 12:12:34.686463 Devices initialized
9378 12:12:34.689882 Show all devs... After init.
9379 12:12:34.689970 Root Device: enabled 1
9380 12:12:34.692983 CPU_CLUSTER: 0: enabled 1
9381 12:12:34.696286 CPU: 00: enabled 1
9382 12:12:34.699983 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9383 12:12:34.702797 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9384 12:12:34.706277 ELOG: NV offset 0x57f000 size 0x1000
9385 12:12:34.713117 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9386 12:12:34.720051 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9387 12:12:34.723140 ELOG: Event(17) added with size 13 at 2024-01-31 12:12:34 UTC
9388 12:12:34.729916 out: cmd=0x121: 03 db 21 01 00 00 00 00
9389 12:12:34.733006 in-header: 03 44 00 00 2c 00 00 00
9390 12:12:34.742982 in-data: 1b 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9391 12:12:34.749342 ELOG: Event(A1) added with size 10 at 2024-01-31 12:12:34 UTC
9392 12:12:34.756053 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9393 12:12:34.762834 ELOG: Event(A0) added with size 9 at 2024-01-31 12:12:34 UTC
9394 12:12:34.765939 elog_add_boot_reason: Logged dev mode boot
9395 12:12:34.772850 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9396 12:12:34.772930 Finalize devices...
9397 12:12:34.776000 Devices finalized
9398 12:12:34.779395 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9399 12:12:34.782378 Writing coreboot table at 0xffe64000
9400 12:12:34.785595 0. 000000000010a000-0000000000113fff: RAMSTAGE
9401 12:12:34.792571 1. 0000000040000000-00000000400fffff: RAM
9402 12:12:34.795892 2. 0000000040100000-000000004032afff: RAMSTAGE
9403 12:12:34.798889 3. 000000004032b000-00000000545fffff: RAM
9404 12:12:34.802747 4. 0000000054600000-000000005465ffff: BL31
9405 12:12:34.805535 5. 0000000054660000-00000000ffe63fff: RAM
9406 12:12:34.811962 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9407 12:12:34.815607 7. 0000000100000000-000000023fffffff: RAM
9408 12:12:34.818990 Passing 5 GPIOs to payload:
9409 12:12:34.822513 NAME | PORT | POLARITY | VALUE
9410 12:12:34.828577 EC in RW | 0x000000aa | low | undefined
9411 12:12:34.831980 EC interrupt | 0x00000005 | low | undefined
9412 12:12:34.835568 TPM interrupt | 0x000000ab | high | undefined
9413 12:12:34.842072 SD card detect | 0x00000011 | high | undefined
9414 12:12:34.845343 speaker enable | 0x00000093 | high | undefined
9415 12:12:34.848432 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9416 12:12:34.851308 in-header: 03 f9 00 00 02 00 00 00
9417 12:12:34.854939 in-data: 02 00
9418 12:12:34.858390 ADC[4]: Raw value=902216 ID=7
9419 12:12:34.861638 ADC[3]: Raw value=213916 ID=1
9420 12:12:34.861719 RAM Code: 0x71
9421 12:12:34.864563 ADC[6]: Raw value=74630 ID=0
9422 12:12:34.868432 ADC[5]: Raw value=213546 ID=1
9423 12:12:34.868543 SKU Code: 0x1
9424 12:12:34.874708 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 550f
9425 12:12:34.874783 coreboot table: 964 bytes.
9426 12:12:34.878029 IMD ROOT 0. 0xfffff000 0x00001000
9427 12:12:34.880901 IMD SMALL 1. 0xffffe000 0x00001000
9428 12:12:34.884815 RO MCACHE 2. 0xffffc000 0x00001104
9429 12:12:34.887612 CONSOLE 3. 0xfff7c000 0x00080000
9430 12:12:34.890946 FMAP 4. 0xfff7b000 0x00000452
9431 12:12:34.894689 TIME STAMP 5. 0xfff7a000 0x00000910
9432 12:12:34.897529 VBOOT WORK 6. 0xfff66000 0x00014000
9433 12:12:34.900921 RAMOOPS 7. 0xffe66000 0x00100000
9434 12:12:34.904536 COREBOOT 8. 0xffe64000 0x00002000
9435 12:12:34.907692 IMD small region:
9436 12:12:34.910807 IMD ROOT 0. 0xffffec00 0x00000400
9437 12:12:34.914393 VPD 1. 0xffffeb80 0x0000006c
9438 12:12:34.917564 MMC STATUS 2. 0xffffeb60 0x00000004
9439 12:12:34.924079 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9440 12:12:34.924159 Probing TPM: done!
9441 12:12:34.930938 Connected to device vid:did:rid of 1ae0:0028:00
9442 12:12:34.937556 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9443 12:12:34.940789 Initialized TPM device CR50 revision 0
9444 12:12:34.944162 Checking cr50 for pending updates
9445 12:12:34.949669 Reading cr50 TPM mode
9446 12:12:34.958795 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9447 12:12:34.965073 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9448 12:12:35.005731 read SPI 0x3990ec 0x4f1b0: 34845 us, 9298 KB/s, 74.384 Mbps
9449 12:12:35.008474 Checking segment from ROM address 0x40100000
9450 12:12:35.011823 Checking segment from ROM address 0x4010001c
9451 12:12:35.018522 Loading segment from ROM address 0x40100000
9452 12:12:35.018626 code (compression=0)
9453 12:12:35.028409 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9454 12:12:35.034649 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9455 12:12:35.034740 it's not compressed!
9456 12:12:35.041606 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9457 12:12:35.048027 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9458 12:12:35.065383 Loading segment from ROM address 0x4010001c
9459 12:12:35.065484 Entry Point 0x80000000
9460 12:12:35.068649 Loaded segments
9461 12:12:35.072141 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9462 12:12:35.078537 Jumping to boot code at 0x80000000(0xffe64000)
9463 12:12:35.085493 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9464 12:12:35.091899 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9465 12:12:35.099911 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9466 12:12:35.103452 Checking segment from ROM address 0x40100000
9467 12:12:35.106468 Checking segment from ROM address 0x4010001c
9468 12:12:35.113434 Loading segment from ROM address 0x40100000
9469 12:12:35.113559 code (compression=1)
9470 12:12:35.120235 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9471 12:12:35.129397 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9472 12:12:35.129529 using LZMA
9473 12:12:35.138516 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9474 12:12:35.144639 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9475 12:12:35.148774 Loading segment from ROM address 0x4010001c
9476 12:12:35.148846 Entry Point 0x54601000
9477 12:12:35.151264 Loaded segments
9478 12:12:35.155014 NOTICE: MT8192 bl31_setup
9479 12:12:35.162050 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9480 12:12:35.165232 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9481 12:12:35.168494 WARNING: region 0:
9482 12:12:35.171850 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 12:12:35.171918 WARNING: region 1:
9484 12:12:35.178376 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9485 12:12:35.181544 WARNING: region 2:
9486 12:12:35.184879 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9487 12:12:35.188452 WARNING: region 3:
9488 12:12:35.191736 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9489 12:12:35.195022 WARNING: region 4:
9490 12:12:35.201861 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9491 12:12:35.201944 WARNING: region 5:
9492 12:12:35.204795 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 12:12:35.208418 WARNING: region 6:
9494 12:12:35.211991 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 12:12:35.214852 WARNING: region 7:
9496 12:12:35.218219 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 12:12:35.224809 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9498 12:12:35.227948 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9499 12:12:35.231392 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9500 12:12:35.238582 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9501 12:12:35.241529 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9502 12:12:35.244834 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9503 12:12:35.251685 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9504 12:12:35.254685 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9505 12:12:35.261353 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9506 12:12:35.264757 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9507 12:12:35.267844 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9508 12:12:35.274433 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9509 12:12:35.278605 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9510 12:12:35.284384 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9511 12:12:35.287992 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9512 12:12:35.291279 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9513 12:12:35.297886 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9514 12:12:35.301318 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9515 12:12:35.305165 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9516 12:12:35.310863 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9517 12:12:35.314142 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9518 12:12:35.321090 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9519 12:12:35.324468 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9520 12:12:35.328156 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9521 12:12:35.334006 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9522 12:12:35.337437 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9523 12:12:35.344277 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9524 12:12:35.347516 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9525 12:12:35.351260 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9526 12:12:35.357375 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9527 12:12:35.360879 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9528 12:12:35.367260 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9529 12:12:35.371053 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9530 12:12:35.374362 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9531 12:12:35.377279 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9532 12:12:35.383912 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9533 12:12:35.387236 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9534 12:12:35.390655 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9535 12:12:35.394391 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9536 12:12:35.400762 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9537 12:12:35.403839 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9538 12:12:35.407189 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9539 12:12:35.410433 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9540 12:12:35.417022 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9541 12:12:35.420383 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9542 12:12:35.423548 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9543 12:12:35.430389 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9544 12:12:35.433688 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9545 12:12:35.437422 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9546 12:12:35.443330 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9547 12:12:35.446531 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9548 12:12:35.453437 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9549 12:12:35.457062 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9550 12:12:35.460076 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9551 12:12:35.466779 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9552 12:12:35.469947 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9553 12:12:35.476314 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9554 12:12:35.479991 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9555 12:12:35.486127 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9556 12:12:35.489631 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9557 12:12:35.496136 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9558 12:12:35.499894 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9559 12:12:35.502931 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9560 12:12:35.509482 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9561 12:12:35.512539 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9562 12:12:35.519308 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9563 12:12:35.523758 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9564 12:12:35.529409 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9565 12:12:35.532757 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9566 12:12:35.539336 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9567 12:12:35.542318 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9568 12:12:35.545986 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9569 12:12:35.552291 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9570 12:12:35.555561 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9571 12:12:35.562163 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9572 12:12:35.565691 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9573 12:12:35.572200 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9574 12:12:35.575813 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9575 12:12:35.582147 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9576 12:12:35.585489 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9577 12:12:35.591828 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9578 12:12:35.595064 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9579 12:12:35.598405 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9580 12:12:35.605360 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9581 12:12:35.608898 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9582 12:12:35.615576 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9583 12:12:35.618576 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9584 12:12:35.622108 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9585 12:12:35.628632 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9586 12:12:35.631831 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9587 12:12:35.638676 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9588 12:12:35.641957 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9589 12:12:35.648402 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9590 12:12:35.651623 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9591 12:12:35.658250 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9592 12:12:35.661724 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9593 12:12:35.665456 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9594 12:12:35.671541 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9595 12:12:35.674784 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9596 12:12:35.678814 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9597 12:12:35.681705 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9598 12:12:35.688592 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9599 12:12:35.691611 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9600 12:12:35.698416 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9601 12:12:35.701730 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9602 12:12:35.704714 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9603 12:12:35.711262 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9604 12:12:35.714886 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9605 12:12:35.721568 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9606 12:12:35.724913 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9607 12:12:35.727800 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9608 12:12:35.734658 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9609 12:12:35.737653 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9610 12:12:35.744253 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9611 12:12:35.747601 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9612 12:12:35.751233 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9613 12:12:35.757523 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9614 12:12:35.760826 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9615 12:12:35.764835 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9616 12:12:35.771381 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9617 12:12:35.774265 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9618 12:12:35.777773 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9619 12:12:35.780590 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9620 12:12:35.787461 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9621 12:12:35.790898 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9622 12:12:35.794248 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9623 12:12:35.801061 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9624 12:12:35.804227 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9625 12:12:35.810585 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9626 12:12:35.814037 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9627 12:12:35.817408 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9628 12:12:35.824080 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9629 12:12:35.827189 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9630 12:12:35.834234 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9631 12:12:35.837818 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9632 12:12:35.840910 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9633 12:12:35.847338 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9634 12:12:35.850416 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9635 12:12:35.853930 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9636 12:12:35.860657 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9637 12:12:35.863681 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9638 12:12:35.870199 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9639 12:12:35.873260 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9640 12:12:35.880201 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9641 12:12:35.883490 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9642 12:12:35.886811 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9643 12:12:35.893637 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9644 12:12:35.896647 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9645 12:12:35.900163 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9646 12:12:35.906710 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9647 12:12:35.909794 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9648 12:12:35.916903 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9649 12:12:35.920002 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9650 12:12:35.924145 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9651 12:12:35.929912 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9652 12:12:35.933309 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9653 12:12:35.939970 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9654 12:12:35.942873 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9655 12:12:35.946414 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9656 12:12:35.952941 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9657 12:12:35.956809 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9658 12:12:35.963026 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9659 12:12:35.965902 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9660 12:12:35.969250 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9661 12:12:35.976013 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9662 12:12:35.979297 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9663 12:12:35.985850 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9664 12:12:35.989538 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9665 12:12:35.992402 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9666 12:12:35.999035 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9667 12:12:36.002301 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9668 12:12:36.008711 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9669 12:12:36.012266 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9670 12:12:36.015368 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9671 12:12:36.022145 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9672 12:12:36.025384 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9673 12:12:36.031579 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9674 12:12:36.035188 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9675 12:12:36.041679 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9676 12:12:36.044997 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9677 12:12:36.048324 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9678 12:12:36.054690 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9679 12:12:36.058239 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9680 12:12:36.061939 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9681 12:12:36.068464 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9682 12:12:36.071260 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9683 12:12:36.078341 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9684 12:12:36.081217 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9685 12:12:36.087915 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9686 12:12:36.090964 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9687 12:12:36.094766 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9688 12:12:36.101096 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9689 12:12:36.103974 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9690 12:12:36.111126 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9691 12:12:36.113919 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9692 12:12:36.120899 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9693 12:12:36.124287 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9694 12:12:36.127284 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9695 12:12:36.133649 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9696 12:12:36.137043 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9697 12:12:36.143947 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9698 12:12:36.147060 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9699 12:12:36.153281 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9700 12:12:36.156544 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9701 12:12:36.160308 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9702 12:12:36.166739 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9703 12:12:36.169905 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9704 12:12:36.176469 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9705 12:12:36.180281 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9706 12:12:36.186109 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9707 12:12:36.189888 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9708 12:12:36.192935 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9709 12:12:36.199243 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9710 12:12:36.202941 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9711 12:12:36.209400 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9712 12:12:36.212284 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9713 12:12:36.219241 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9714 12:12:36.222186 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9715 12:12:36.229012 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9716 12:12:36.231931 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9717 12:12:36.235570 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9718 12:12:36.241937 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9719 12:12:36.245336 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9720 12:12:36.252504 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9721 12:12:36.255535 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9722 12:12:36.261900 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9723 12:12:36.264914 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9724 12:12:36.268370 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9725 12:12:36.275038 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9726 12:12:36.278651 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9727 12:12:36.282013 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9728 12:12:36.285285 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9729 12:12:36.292382 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9730 12:12:36.295012 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9731 12:12:36.297916 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9732 12:12:36.304879 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9733 12:12:36.308211 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9734 12:12:36.315009 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9735 12:12:36.318260 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9736 12:12:36.321426 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9737 12:12:36.327747 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9738 12:12:36.331255 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9739 12:12:36.334302 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9740 12:12:36.341401 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9741 12:12:36.344213 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9742 12:12:36.350483 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9743 12:12:36.354136 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9744 12:12:36.357510 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9745 12:12:36.363944 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9746 12:12:36.367191 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9747 12:12:36.370650 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9748 12:12:36.377120 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9749 12:12:36.380514 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9750 12:12:36.383576 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9751 12:12:36.391566 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9752 12:12:36.393917 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9753 12:12:36.400504 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9754 12:12:36.403479 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9755 12:12:36.407143 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9756 12:12:36.413375 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9757 12:12:36.416726 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9758 12:12:36.423115 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9759 12:12:36.426434 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9760 12:12:36.429785 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9761 12:12:36.436631 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9762 12:12:36.439663 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9763 12:12:36.442774 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9764 12:12:36.449199 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9765 12:12:36.452973 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9766 12:12:36.456388 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9767 12:12:36.462759 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9768 12:12:36.465781 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9769 12:12:36.469492 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9770 12:12:36.472570 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9771 12:12:36.479223 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9772 12:12:36.482367 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9773 12:12:36.485745 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9774 12:12:36.489021 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9775 12:12:36.495212 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9776 12:12:36.498793 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9777 12:12:36.502167 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9778 12:12:36.505565 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9779 12:12:36.511696 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9780 12:12:36.515228 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9781 12:12:36.521917 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9782 12:12:36.525237 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9783 12:12:36.531387 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9784 12:12:36.535026 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9785 12:12:36.541555 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9786 12:12:36.544979 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9787 12:12:36.547846 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9788 12:12:36.554664 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9789 12:12:36.557958 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9790 12:12:36.564675 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9791 12:12:36.567993 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9792 12:12:36.574428 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9793 12:12:36.577578 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9794 12:12:36.580854 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9795 12:12:36.587710 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9796 12:12:36.590642 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9797 12:12:36.597454 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9798 12:12:36.600512 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9799 12:12:36.604160 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9800 12:12:36.610643 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9801 12:12:36.614352 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9802 12:12:36.620409 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9803 12:12:36.623813 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9804 12:12:36.627324 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9805 12:12:36.633809 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9806 12:12:36.636826 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9807 12:12:36.643323 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9808 12:12:36.646699 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9809 12:12:36.653437 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9810 12:12:36.656643 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9811 12:12:36.660253 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9812 12:12:36.666677 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9813 12:12:36.670221 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9814 12:12:36.676889 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9815 12:12:36.679849 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9816 12:12:36.686667 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9817 12:12:36.689594 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9818 12:12:36.692815 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9819 12:12:36.699790 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9820 12:12:36.703029 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9821 12:12:36.709493 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9822 12:12:36.712861 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9823 12:12:36.719225 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9824 12:12:36.722406 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9825 12:12:36.725716 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9826 12:12:36.732583 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9827 12:12:36.735682 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9828 12:12:36.742317 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9829 12:12:36.745547 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9830 12:12:36.748838 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9831 12:12:36.755684 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9832 12:12:36.758637 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9833 12:12:36.765382 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9834 12:12:36.768262 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9835 12:12:36.775072 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9836 12:12:36.778062 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9837 12:12:36.781610 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9838 12:12:36.787885 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9839 12:12:36.791313 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9840 12:12:36.798661 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9841 12:12:36.801253 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9842 12:12:36.804759 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9843 12:12:36.810904 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9844 12:12:36.814146 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9845 12:12:36.821302 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9846 12:12:36.824212 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9847 12:12:36.830992 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9848 12:12:36.833823 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9849 12:12:36.840636 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9850 12:12:36.843931 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9851 12:12:36.847285 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9852 12:12:36.853818 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9853 12:12:36.857079 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9854 12:12:36.863789 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9855 12:12:36.866768 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9856 12:12:36.873654 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9857 12:12:36.876851 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9858 12:12:36.880084 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9859 12:12:36.887027 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9860 12:12:36.889832 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9861 12:12:36.896755 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9862 12:12:36.899785 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9863 12:12:36.906324 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9864 12:12:36.909981 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9865 12:12:36.916800 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9866 12:12:36.919522 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9867 12:12:36.923106 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9868 12:12:36.929304 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9869 12:12:36.932645 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9870 12:12:36.939035 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9871 12:12:36.942329 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9872 12:12:36.949052 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9873 12:12:36.952308 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9874 12:12:36.959376 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9875 12:12:36.962309 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9876 12:12:36.968925 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9877 12:12:36.972248 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9878 12:12:36.975690 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9879 12:12:36.982302 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9880 12:12:36.985437 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9881 12:12:36.991905 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9882 12:12:36.995587 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9883 12:12:37.001810 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9884 12:12:37.005177 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9885 12:12:37.011912 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9886 12:12:37.015243 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9887 12:12:37.021580 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9888 12:12:37.024908 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9889 12:12:37.027749 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9890 12:12:37.034902 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9891 12:12:37.038208 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9892 12:12:37.044536 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9893 12:12:37.048290 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9894 12:12:37.054784 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9895 12:12:37.057871 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9896 12:12:37.064453 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9897 12:12:37.067709 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9898 12:12:37.071677 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9899 12:12:37.077407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9900 12:12:37.080587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9901 12:12:37.087463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9902 12:12:37.091226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9903 12:12:37.097176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9904 12:12:37.100651 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9905 12:12:37.107648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9906 12:12:37.110937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9907 12:12:37.117107 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9908 12:12:37.120247 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9909 12:12:37.126828 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9910 12:12:37.130163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9911 12:12:37.136572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9912 12:12:37.140190 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9913 12:12:37.146415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9914 12:12:37.149627 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9915 12:12:37.156311 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9916 12:12:37.159587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9917 12:12:37.166481 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9918 12:12:37.169504 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9919 12:12:37.175982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9920 12:12:37.179350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9921 12:12:37.185970 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9922 12:12:37.189670 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9923 12:12:37.195898 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9924 12:12:37.199134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9925 12:12:37.205611 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9926 12:12:37.208914 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9927 12:12:37.215694 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9928 12:12:37.219112 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9929 12:12:37.225658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9930 12:12:37.228759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9931 12:12:37.235718 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9932 12:12:37.235799 INFO: [APUAPC] vio 0
9933 12:12:37.241987 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9934 12:12:37.244983 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9935 12:12:37.248493 INFO: [APUAPC] D0_APC_0: 0x400510
9936 12:12:37.251828 INFO: [APUAPC] D0_APC_1: 0x0
9937 12:12:37.254968 INFO: [APUAPC] D0_APC_2: 0x1540
9938 12:12:37.258104 INFO: [APUAPC] D0_APC_3: 0x0
9939 12:12:37.261329 INFO: [APUAPC] D1_APC_0: 0xffffffff
9940 12:12:37.264739 INFO: [APUAPC] D1_APC_1: 0xffffffff
9941 12:12:37.268266 INFO: [APUAPC] D1_APC_2: 0x3fffff
9942 12:12:37.271736 INFO: [APUAPC] D1_APC_3: 0x0
9943 12:12:37.274349 INFO: [APUAPC] D2_APC_0: 0xffffffff
9944 12:12:37.278100 INFO: [APUAPC] D2_APC_1: 0xffffffff
9945 12:12:37.281365 INFO: [APUAPC] D2_APC_2: 0x3fffff
9946 12:12:37.285016 INFO: [APUAPC] D2_APC_3: 0x0
9947 12:12:37.288589 INFO: [APUAPC] D3_APC_0: 0xffffffff
9948 12:12:37.291256 INFO: [APUAPC] D3_APC_1: 0xffffffff
9949 12:12:37.294287 INFO: [APUAPC] D3_APC_2: 0x3fffff
9950 12:12:37.297712 INFO: [APUAPC] D3_APC_3: 0x0
9951 12:12:37.300863 INFO: [APUAPC] D4_APC_0: 0xffffffff
9952 12:12:37.304111 INFO: [APUAPC] D4_APC_1: 0xffffffff
9953 12:12:37.307744 INFO: [APUAPC] D4_APC_2: 0x3fffff
9954 12:12:37.310563 INFO: [APUAPC] D4_APC_3: 0x0
9955 12:12:37.314573 INFO: [APUAPC] D5_APC_0: 0xffffffff
9956 12:12:37.317583 INFO: [APUAPC] D5_APC_1: 0xffffffff
9957 12:12:37.320597 INFO: [APUAPC] D5_APC_2: 0x3fffff
9958 12:12:37.324317 INFO: [APUAPC] D5_APC_3: 0x0
9959 12:12:37.327328 INFO: [APUAPC] D6_APC_0: 0xffffffff
9960 12:12:37.330772 INFO: [APUAPC] D6_APC_1: 0xffffffff
9961 12:12:37.333546 INFO: [APUAPC] D6_APC_2: 0x3fffff
9962 12:12:37.336907 INFO: [APUAPC] D6_APC_3: 0x0
9963 12:12:37.340087 INFO: [APUAPC] D7_APC_0: 0xffffffff
9964 12:12:37.343764 INFO: [APUAPC] D7_APC_1: 0xffffffff
9965 12:12:37.346669 INFO: [APUAPC] D7_APC_2: 0x3fffff
9966 12:12:37.350063 INFO: [APUAPC] D7_APC_3: 0x0
9967 12:12:37.353438 INFO: [APUAPC] D8_APC_0: 0xffffffff
9968 12:12:37.356746 INFO: [APUAPC] D8_APC_1: 0xffffffff
9969 12:12:37.360113 INFO: [APUAPC] D8_APC_2: 0x3fffff
9970 12:12:37.360187 INFO: [APUAPC] D8_APC_3: 0x0
9971 12:12:37.366604 INFO: [APUAPC] D9_APC_0: 0xffffffff
9972 12:12:37.370156 INFO: [APUAPC] D9_APC_1: 0xffffffff
9973 12:12:37.373500 INFO: [APUAPC] D9_APC_2: 0x3fffff
9974 12:12:37.373578 INFO: [APUAPC] D9_APC_3: 0x0
9975 12:12:37.377044 INFO: [APUAPC] D10_APC_0: 0xffffffff
9976 12:12:37.383339 INFO: [APUAPC] D10_APC_1: 0xffffffff
9977 12:12:37.386325 INFO: [APUAPC] D10_APC_2: 0x3fffff
9978 12:12:37.386403 INFO: [APUAPC] D10_APC_3: 0x0
9979 12:12:37.392977 INFO: [APUAPC] D11_APC_0: 0xffffffff
9980 12:12:37.396406 INFO: [APUAPC] D11_APC_1: 0xffffffff
9981 12:12:37.399742 INFO: [APUAPC] D11_APC_2: 0x3fffff
9982 12:12:37.403154 INFO: [APUAPC] D11_APC_3: 0x0
9983 12:12:37.406397 INFO: [APUAPC] D12_APC_0: 0xffffffff
9984 12:12:37.409795 INFO: [APUAPC] D12_APC_1: 0xffffffff
9985 12:12:37.412930 INFO: [APUAPC] D12_APC_2: 0x3fffff
9986 12:12:37.416268 INFO: [APUAPC] D12_APC_3: 0x0
9987 12:12:37.419027 INFO: [APUAPC] D13_APC_0: 0xffffffff
9988 12:12:37.422952 INFO: [APUAPC] D13_APC_1: 0xffffffff
9989 12:12:37.425896 INFO: [APUAPC] D13_APC_2: 0x3fffff
9990 12:12:37.429517 INFO: [APUAPC] D13_APC_3: 0x0
9991 12:12:37.432298 INFO: [APUAPC] D14_APC_0: 0xffffffff
9992 12:12:37.435885 INFO: [APUAPC] D14_APC_1: 0xffffffff
9993 12:12:37.439228 INFO: [APUAPC] D14_APC_2: 0x3fffff
9994 12:12:37.442432 INFO: [APUAPC] D14_APC_3: 0x0
9995 12:12:37.445304 INFO: [APUAPC] D15_APC_0: 0xffffffff
9996 12:12:37.448779 INFO: [APUAPC] D15_APC_1: 0xffffffff
9997 12:12:37.451874 INFO: [APUAPC] D15_APC_2: 0x3fffff
9998 12:12:37.455732 INFO: [APUAPC] D15_APC_3: 0x0
9999 12:12:37.458865 INFO: [APUAPC] APC_CON: 0x4
10000 12:12:37.461863 INFO: [NOCDAPC] D0_APC_0: 0x0
10001 12:12:37.461945 INFO: [NOCDAPC] D0_APC_1: 0x0
10002 12:12:37.465733 INFO: [NOCDAPC] D1_APC_0: 0x0
10003 12:12:37.468429 INFO: [NOCDAPC] D1_APC_1: 0xfff
10004 12:12:37.471814 INFO: [NOCDAPC] D2_APC_0: 0x0
10005 12:12:37.474789 INFO: [NOCDAPC] D2_APC_1: 0xfff
10006 12:12:37.478373 INFO: [NOCDAPC] D3_APC_0: 0x0
10007 12:12:37.481299 INFO: [NOCDAPC] D3_APC_1: 0xfff
10008 12:12:37.484986 INFO: [NOCDAPC] D4_APC_0: 0x0
10009 12:12:37.488464 INFO: [NOCDAPC] D4_APC_1: 0xfff
10010 12:12:37.491835 INFO: [NOCDAPC] D5_APC_0: 0x0
10011 12:12:37.494931 INFO: [NOCDAPC] D5_APC_1: 0xfff
10012 12:12:37.495030 INFO: [NOCDAPC] D6_APC_0: 0x0
10013 12:12:37.497970 INFO: [NOCDAPC] D6_APC_1: 0xfff
10014 12:12:37.501296 INFO: [NOCDAPC] D7_APC_0: 0x0
10015 12:12:37.505102 INFO: [NOCDAPC] D7_APC_1: 0xfff
10016 12:12:37.507892 INFO: [NOCDAPC] D8_APC_0: 0x0
10017 12:12:37.511251 INFO: [NOCDAPC] D8_APC_1: 0xfff
10018 12:12:37.515057 INFO: [NOCDAPC] D9_APC_0: 0x0
10019 12:12:37.517657 INFO: [NOCDAPC] D9_APC_1: 0xfff
10020 12:12:37.521448 INFO: [NOCDAPC] D10_APC_0: 0x0
10021 12:12:37.524554 INFO: [NOCDAPC] D10_APC_1: 0xfff
10022 12:12:37.527907 INFO: [NOCDAPC] D11_APC_0: 0x0
10023 12:12:37.531834 INFO: [NOCDAPC] D11_APC_1: 0xfff
10024 12:12:37.534685 INFO: [NOCDAPC] D12_APC_0: 0x0
10025 12:12:37.537405 INFO: [NOCDAPC] D12_APC_1: 0xfff
10026 12:12:37.540977 INFO: [NOCDAPC] D13_APC_0: 0x0
10027 12:12:37.544062 INFO: [NOCDAPC] D13_APC_1: 0xfff
10028 12:12:37.544175 INFO: [NOCDAPC] D14_APC_0: 0x0
10029 12:12:37.547474 INFO: [NOCDAPC] D14_APC_1: 0xfff
10030 12:12:37.550486 INFO: [NOCDAPC] D15_APC_0: 0x0
10031 12:12:37.553842 INFO: [NOCDAPC] D15_APC_1: 0xfff
10032 12:12:37.557273 INFO: [NOCDAPC] APC_CON: 0x4
10033 12:12:37.560949 INFO: [APUAPC] set_apusys_apc done
10034 12:12:37.563921 INFO: [DEVAPC] devapc_init done
10035 12:12:37.567105 INFO: GICv3 without legacy support detected.
10036 12:12:37.573914 INFO: ARM GICv3 driver initialized in EL3
10037 12:12:37.577058 INFO: Maximum SPI INTID supported: 639
10038 12:12:37.580485 INFO: BL31: Initializing runtime services
10039 12:12:37.586910 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10040 12:12:37.590017 INFO: SPM: enable CPC mode
10041 12:12:37.593124 INFO: mcdi ready for mcusys-off-idle and system suspend
10042 12:12:37.599893 INFO: BL31: Preparing for EL3 exit to normal world
10043 12:12:37.602934 INFO: Entry point address = 0x80000000
10044 12:12:37.603015 INFO: SPSR = 0x8
10045 12:12:37.610142
10046 12:12:37.610224
10047 12:12:37.610289
10048 12:12:37.612988 Starting depthcharge on Spherion...
10049 12:12:37.613070
10050 12:12:37.613135 Wipe memory regions:
10051 12:12:37.613195
10052 12:12:37.613865 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10053 12:12:37.613968 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10054 12:12:37.614052 Setting prompt string to ['asurada:']
10055 12:12:37.614131 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10056 12:12:37.616616 [0x00000040000000, 0x00000054600000)
10057 12:12:37.738772
10058 12:12:37.738897 [0x00000054660000, 0x00000080000000)
10059 12:12:37.999627
10060 12:12:37.999761 [0x000000821a7280, 0x000000ffe64000)
10061 12:12:38.744159
10062 12:12:38.744303 [0x00000100000000, 0x00000240000000)
10063 12:12:40.633600
10064 12:12:40.637415 Initializing XHCI USB controller at 0x11200000.
10065 12:12:41.674427
10066 12:12:41.677840 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10067 12:12:41.677925
10068 12:12:41.677988
10069 12:12:41.678048
10070 12:12:41.678334 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10072 12:12:41.778668 asurada: tftpboot 192.168.201.1 12669504/tftp-deploy-_dcldchd/kernel/image.itb 12669504/tftp-deploy-_dcldchd/kernel/cmdline
10073 12:12:41.778797 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10074 12:12:41.778878 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10075 12:12:41.783129 tftpboot 192.168.201.1 12669504/tftp-deploy-_dcldchd/kernel/image.ittp-deploy-_dcldchd/kernel/cmdline
10076 12:12:41.783211
10077 12:12:41.783275 Waiting for link
10078 12:12:41.944025
10079 12:12:41.944184 R8152: Initializing
10080 12:12:41.944253
10081 12:12:41.946789 Version 6 (ocp_data = 5c30)
10082 12:12:41.946859
10083 12:12:41.950487 R8152: Done initializing
10084 12:12:41.950558
10085 12:12:41.950622 Adding net device
10086 12:12:43.931343
10087 12:12:43.931516 done.
10088 12:12:43.931584
10089 12:12:43.931645 MAC: 00:24:32:30:7c:7b
10090 12:12:43.931703
10091 12:12:43.935067 Sending DHCP discover... done.
10092 12:12:43.935148
10093 12:12:43.937991 Waiting for reply... done.
10094 12:12:43.938073
10095 12:12:43.941779 Sending DHCP request... done.
10096 12:12:43.941861
10097 12:12:43.945542 Waiting for reply... done.
10098 12:12:43.945623
10099 12:12:43.945687 My ip is 192.168.201.14
10100 12:12:43.945747
10101 12:12:43.948968 The DHCP server ip is 192.168.201.1
10102 12:12:43.949050
10103 12:12:43.955330 TFTP server IP predefined by user: 192.168.201.1
10104 12:12:43.955451
10105 12:12:43.962037 Bootfile predefined by user: 12669504/tftp-deploy-_dcldchd/kernel/image.itb
10106 12:12:43.962143
10107 12:12:43.965233 Sending tftp read request... done.
10108 12:12:43.965314
10109 12:12:43.969139 Waiting for the transfer...
10110 12:12:43.969220
10111 12:12:44.504098 00000000 ################################################################
10112 12:12:44.504234
10113 12:12:45.064624 00080000 ################################################################
10114 12:12:45.064763
10115 12:12:45.595430 00100000 ################################################################
10116 12:12:45.595567
10117 12:12:46.130895 00180000 ################################################################
10118 12:12:46.131059
10119 12:12:46.670147 00200000 ################################################################
10120 12:12:46.670291
10121 12:12:47.219250 00280000 ################################################################
10122 12:12:47.219442
10123 12:12:47.770082 00300000 ################################################################
10124 12:12:47.770221
10125 12:12:48.315277 00380000 ################################################################
10126 12:12:48.315462
10127 12:12:48.852829 00400000 ################################################################
10128 12:12:48.852967
10129 12:12:49.401973 00480000 ################################################################
10130 12:12:49.402106
10131 12:12:49.923103 00500000 ################################################################
10132 12:12:49.923242
10133 12:12:50.471783 00580000 ################################################################
10134 12:12:50.471914
10135 12:12:51.012840 00600000 ################################################################
10136 12:12:51.012991
10137 12:12:51.532409 00680000 ################################################################
10138 12:12:51.532563
10139 12:12:52.050980 00700000 ################################################################
10140 12:12:52.051116
10141 12:12:52.591707 00780000 ################################################################
10142 12:12:52.591841
10143 12:12:53.118304 00800000 ################################################################
10144 12:12:53.118482
10145 12:12:53.659340 00880000 ################################################################
10146 12:12:53.659528
10147 12:12:54.210824 00900000 ################################################################
10148 12:12:54.210962
10149 12:12:54.744851 00980000 ################################################################
10150 12:12:54.744993
10151 12:12:55.267922 00a00000 ################################################################
10152 12:12:55.268060
10153 12:12:55.805916 00a80000 ################################################################
10154 12:12:55.806061
10155 12:12:56.333420 00b00000 ################################################################
10156 12:12:56.333581
10157 12:12:56.864028 00b80000 ################################################################
10158 12:12:56.864193
10159 12:12:57.409970 00c00000 ################################################################
10160 12:12:57.410114
10161 12:12:57.953696 00c80000 ################################################################
10162 12:12:57.953864
10163 12:12:58.486595 00d00000 ################################################################
10164 12:12:58.486730
10165 12:12:59.016148 00d80000 ################################################################
10166 12:12:59.016289
10167 12:12:59.547575 00e00000 ################################################################
10168 12:12:59.547721
10169 12:13:00.088452 00e80000 ################################################################
10170 12:13:00.088602
10171 12:13:00.619211 00f00000 ################################################################
10172 12:13:00.619385
10173 12:13:01.141504 00f80000 ################################################################
10174 12:13:01.141645
10175 12:13:01.662439 01000000 ################################################################
10176 12:13:01.662571
10177 12:13:02.189154 01080000 ################################################################
10178 12:13:02.189313
10179 12:13:02.720757 01100000 ################################################################
10180 12:13:02.720927
10181 12:13:03.244344 01180000 ################################################################
10182 12:13:03.244500
10183 12:13:03.783488 01200000 ################################################################
10184 12:13:03.783666
10185 12:13:04.328508 01280000 ################################################################
10186 12:13:04.328654
10187 12:13:04.857681 01300000 ################################################################
10188 12:13:04.857829
10189 12:13:05.399774 01380000 ################################################################
10190 12:13:05.399926
10191 12:13:05.931383 01400000 ################################################################
10192 12:13:05.931600
10193 12:13:06.477559 01480000 ################################################################
10194 12:13:06.477709
10195 12:13:07.006018 01500000 ################################################################
10196 12:13:07.006164
10197 12:13:07.571490 01580000 ################################################################
10198 12:13:07.571634
10199 12:13:08.110735 01600000 ################################################################
10200 12:13:08.110880
10201 12:13:08.790116 01680000 ################################################################
10202 12:13:08.790650
10203 12:13:09.519913 01700000 ################################################################
10204 12:13:09.520438
10205 12:13:10.244750 01780000 ################################################################
10206 12:13:10.245262
10207 12:13:10.944340 01800000 ################################################################
10208 12:13:10.944836
10209 12:13:11.622251 01880000 ################################################################
10210 12:13:11.622516
10211 12:13:12.323956 01900000 ################################################################
10212 12:13:12.324574
10213 12:13:13.048875 01980000 ################################################################
10214 12:13:13.049390
10215 12:13:13.762071 01a00000 ################################################################
10216 12:13:13.762564
10217 12:13:14.473480 01a80000 ################################################################
10218 12:13:14.474011
10219 12:13:15.166830 01b00000 ################################################################
10220 12:13:15.167399
10221 12:13:15.892395 01b80000 ################################################################
10222 12:13:15.892924
10223 12:13:16.615519 01c00000 ################################################################
10224 12:13:16.616070
10225 12:13:16.624027 01c80000 # done.
10226 12:13:16.624453
10227 12:13:16.627276 The bootfile was 29890130 bytes long.
10228 12:13:16.627835
10229 12:13:16.630387 Sending tftp read request... done.
10230 12:13:16.630809
10231 12:13:16.634784 Waiting for the transfer...
10232 12:13:16.635206
10233 12:13:16.635614 00000000 # done.
10234 12:13:16.635944
10235 12:13:16.641649 Command line loaded dynamically from TFTP file: 12669504/tftp-deploy-_dcldchd/kernel/cmdline
10236 12:13:16.644934
10237 12:13:16.664611 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12669504/extract-nfsrootfs-y7wd4bc_,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10238 12:13:16.665149
10239 12:13:16.665487 Loading FIT.
10240 12:13:16.665797
10241 12:13:16.667924 Image ramdisk-1 has 17793533 bytes.
10242 12:13:16.668343
10243 12:13:16.672052 Image fdt-1 has 47278 bytes.
10244 12:13:16.672473
10245 12:13:16.674734 Image kernel-1 has 12047284 bytes.
10246 12:13:16.675286
10247 12:13:16.684200 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10248 12:13:16.684624
10249 12:13:16.700822 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10250 12:13:16.701349
10251 12:13:16.707816 Choosing best match conf-1 for compat google,spherion-rev2.
10252 12:13:16.710856
10253 12:13:16.715565 Connected to device vid:did:rid of 1ae0:0028:00
10254 12:13:16.722768
10255 12:13:16.726603 tpm_get_response: command 0x17b, return code 0x0
10256 12:13:16.727126
10257 12:13:16.729560 ec_init: CrosEC protocol v3 supported (256, 248)
10258 12:13:16.734534
10259 12:13:16.737795 tpm_cleanup: add release locality here.
10260 12:13:16.738318
10261 12:13:16.738654 Shutting down all USB controllers.
10262 12:13:16.741343
10263 12:13:16.741858 Removing current net device
10264 12:13:16.742190
10265 12:13:16.747417 Exiting depthcharge with code 4 at timestamp: 68359078
10266 12:13:16.747834
10267 12:13:16.751022 LZMA decompressing kernel-1 to 0x821a6718
10268 12:13:16.751594
10269 12:13:16.754143 LZMA decompressing kernel-1 to 0x40000000
10270 12:13:18.253969
10271 12:13:18.254526 jumping to kernel
10272 12:13:18.256255 end: 2.2.4 bootloader-commands (duration 00:00:41) [common]
10273 12:13:18.256777 start: 2.2.5 auto-login-action (timeout 00:03:45) [common]
10274 12:13:18.257183 Setting prompt string to ['Linux version [0-9]']
10275 12:13:18.257553 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10276 12:13:18.257918 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10277 12:13:18.335792
10278 12:13:18.338963 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10279 12:13:18.342851 start: 2.2.5.1 login-action (timeout 00:03:45) [common]
10280 12:13:18.343456 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10281 12:13:18.343865 Setting prompt string to []
10282 12:13:18.344287 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10283 12:13:18.344683 Using line separator: #'\n'#
10284 12:13:18.345015 No login prompt set.
10285 12:13:18.345555 Parsing kernel messages
10286 12:13:18.345895 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10287 12:13:18.346453 [login-action] Waiting for messages, (timeout 00:03:45)
10288 12:13:18.361733 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j93261-arm64-gcc-10-defconfig-arm64-chromebook-cwjwh) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024
10289 12:13:18.365135 [ 0.000000] random: crng init done
10290 12:13:18.372294 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10291 12:13:18.374447 [ 0.000000] efi: UEFI not found.
10292 12:13:18.381334 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10293 12:13:18.390962 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10294 12:13:18.398272 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10295 12:13:18.407770 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10296 12:13:18.414719 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10297 12:13:18.421140 [ 0.000000] printk: bootconsole [mtk8250] enabled
10298 12:13:18.428008 [ 0.000000] NUMA: No NUMA configuration found
10299 12:13:18.434699 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10300 12:13:18.437522 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10301 12:13:18.441681 [ 0.000000] Zone ranges:
10302 12:13:18.447446 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10303 12:13:18.451184 [ 0.000000] DMA32 empty
10304 12:13:18.457499 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10305 12:13:18.461813 [ 0.000000] Movable zone start for each node
10306 12:13:18.464134 [ 0.000000] Early memory node ranges
10307 12:13:18.471527 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10308 12:13:18.477483 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10309 12:13:18.483912 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10310 12:13:18.490549 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10311 12:13:18.497293 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10312 12:13:18.503179 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10313 12:13:18.560001 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10314 12:13:18.566818 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10315 12:13:18.573248 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10316 12:13:18.576577 [ 0.000000] psci: probing for conduit method from DT.
10317 12:13:18.583473 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10318 12:13:18.587108 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10319 12:13:18.593084 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10320 12:13:18.595961 [ 0.000000] psci: SMC Calling Convention v1.2
10321 12:13:18.603412 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10322 12:13:18.607100 [ 0.000000] Detected VIPT I-cache on CPU0
10323 12:13:18.612819 [ 0.000000] CPU features: detected: GIC system register CPU interface
10324 12:13:18.619249 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10325 12:13:18.626475 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10326 12:13:18.632284 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10327 12:13:18.642206 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10328 12:13:18.648821 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10329 12:13:18.651885 [ 0.000000] alternatives: applying boot alternatives
10330 12:13:18.658901 [ 0.000000] Fallback order for Node 0: 0
10331 12:13:18.665617 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10332 12:13:18.668550 [ 0.000000] Policy zone: Normal
10333 12:13:18.691940 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12669504/extract-nfsrootfs-y7wd4bc_,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10334 12:13:18.702111 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10335 12:13:18.713053 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10336 12:13:18.722650 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10337 12:13:18.729488 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10338 12:13:18.733261 <6>[ 0.000000] software IO TLB: area num 8.
10339 12:13:18.789459 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10340 12:13:18.938265 <6>[ 0.000000] Memory: 7949876K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 402892K reserved, 32768K cma-reserved)
10341 12:13:18.944951 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10342 12:13:18.951730 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10343 12:13:18.954797 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10344 12:13:18.961073 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10345 12:13:18.967694 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10346 12:13:18.971067 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10347 12:13:18.980824 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10348 12:13:18.987732 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10349 12:13:18.993657 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10350 12:13:19.000748 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10351 12:13:19.003861 <6>[ 0.000000] GICv3: 608 SPIs implemented
10352 12:13:19.007108 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10353 12:13:19.013957 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10354 12:13:19.017373 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10355 12:13:19.023760 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10356 12:13:19.037163 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10357 12:13:19.050379 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10358 12:13:19.056649 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10359 12:13:19.065427 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10360 12:13:19.077704 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10361 12:13:19.084564 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10362 12:13:19.091435 <6>[ 0.009185] Console: colour dummy device 80x25
10363 12:13:19.100745 <6>[ 0.013911] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10364 12:13:19.107543 <6>[ 0.024353] pid_max: default: 32768 minimum: 301
10365 12:13:19.111004 <6>[ 0.029224] LSM: Security Framework initializing
10366 12:13:19.117331 <6>[ 0.034191] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10367 12:13:19.127225 <6>[ 0.042005] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10368 12:13:19.137053 <6>[ 0.051417] cblist_init_generic: Setting adjustable number of callback queues.
10369 12:13:19.143775 <6>[ 0.058861] cblist_init_generic: Setting shift to 3 and lim to 1.
10370 12:13:19.150207 <6>[ 0.065239] cblist_init_generic: Setting adjustable number of callback queues.
10371 12:13:19.157078 <6>[ 0.072712] cblist_init_generic: Setting shift to 3 and lim to 1.
10372 12:13:19.160238 <6>[ 0.079113] rcu: Hierarchical SRCU implementation.
10373 12:13:19.167182 <6>[ 0.084159] rcu: Max phase no-delay instances is 1000.
10374 12:13:19.174255 <6>[ 0.091182] EFI services will not be available.
10375 12:13:19.176561 <6>[ 0.096136] smp: Bringing up secondary CPUs ...
10376 12:13:19.185945 <6>[ 0.101213] Detected VIPT I-cache on CPU1
10377 12:13:19.192350 <6>[ 0.101282] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10378 12:13:19.199296 <6>[ 0.101313] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10379 12:13:19.202310 <6>[ 0.101654] Detected VIPT I-cache on CPU2
10380 12:13:19.208891 <6>[ 0.101706] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10381 12:13:19.218617 <6>[ 0.101724] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10382 12:13:19.221818 <6>[ 0.101982] Detected VIPT I-cache on CPU3
10383 12:13:19.229011 <6>[ 0.102029] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10384 12:13:19.235222 <6>[ 0.102043] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10385 12:13:19.238281 <6>[ 0.102347] CPU features: detected: Spectre-v4
10386 12:13:19.245023 <6>[ 0.102353] CPU features: detected: Spectre-BHB
10387 12:13:19.247910 <6>[ 0.102357] Detected PIPT I-cache on CPU4
10388 12:13:19.254632 <6>[ 0.102406] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10389 12:13:19.261423 <6>[ 0.102422] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10390 12:13:19.268098 <6>[ 0.102701] Detected PIPT I-cache on CPU5
10391 12:13:19.274742 <6>[ 0.102755] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10392 12:13:19.281208 <6>[ 0.102771] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10393 12:13:19.284044 <6>[ 0.103050] Detected PIPT I-cache on CPU6
10394 12:13:19.293904 <6>[ 0.103116] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10395 12:13:19.300588 <6>[ 0.103132] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10396 12:13:19.303721 <6>[ 0.103428] Detected PIPT I-cache on CPU7
10397 12:13:19.310613 <6>[ 0.103492] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10398 12:13:19.317387 <6>[ 0.103509] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10399 12:13:19.320391 <6>[ 0.103556] smp: Brought up 1 node, 8 CPUs
10400 12:13:19.327962 <6>[ 0.244752] SMP: Total of 8 processors activated.
10401 12:13:19.330517 <6>[ 0.249673] CPU features: detected: 32-bit EL0 Support
10402 12:13:19.340382 <6>[ 0.255069] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10403 12:13:19.347298 <6>[ 0.263869] CPU features: detected: Common not Private translations
10404 12:13:19.353817 <6>[ 0.270345] CPU features: detected: CRC32 instructions
10405 12:13:19.360220 <6>[ 0.275696] CPU features: detected: RCpc load-acquire (LDAPR)
10406 12:13:19.363497 <6>[ 0.281656] CPU features: detected: LSE atomic instructions
10407 12:13:19.370749 <6>[ 0.287437] CPU features: detected: Privileged Access Never
10408 12:13:19.376592 <6>[ 0.293217] CPU features: detected: RAS Extension Support
10409 12:13:19.383595 <6>[ 0.298826] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10410 12:13:19.387099 <6>[ 0.306088] CPU: All CPU(s) started at EL2
10411 12:13:19.393568 <6>[ 0.310432] alternatives: applying system-wide alternatives
10412 12:13:19.404343 <6>[ 0.321191] devtmpfs: initialized
10413 12:13:19.419122 <6>[ 0.330181] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10414 12:13:19.425589 <6>[ 0.340143] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10415 12:13:19.432121 <6>[ 0.348375] pinctrl core: initialized pinctrl subsystem
10416 12:13:19.435637 <6>[ 0.354997] DMI not present or invalid.
10417 12:13:19.442011 <6>[ 0.359409] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10418 12:13:19.452009 <6>[ 0.366287] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10419 12:13:19.458251 <6>[ 0.373874] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10420 12:13:19.468232 <6>[ 0.382106] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10421 12:13:19.471347 <6>[ 0.390347] audit: initializing netlink subsys (disabled)
10422 12:13:19.481627 <5>[ 0.396041] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10423 12:13:19.488107 <6>[ 0.396741] thermal_sys: Registered thermal governor 'step_wise'
10424 12:13:19.494218 <6>[ 0.404007] thermal_sys: Registered thermal governor 'power_allocator'
10425 12:13:19.498021 <6>[ 0.410264] cpuidle: using governor menu
10426 12:13:19.505184 <6>[ 0.421221] NET: Registered PF_QIPCRTR protocol family
10427 12:13:19.511064 <6>[ 0.426709] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10428 12:13:19.517821 <6>[ 0.433813] ASID allocator initialised with 32768 entries
10429 12:13:19.521080 <6>[ 0.440369] Serial: AMBA PL011 UART driver
10430 12:13:19.530798 <4>[ 0.449112] Trying to register duplicate clock ID: 134
10431 12:13:19.584898 <6>[ 0.506337] KASLR enabled
10432 12:13:19.599970 <6>[ 0.514110] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10433 12:13:19.606549 <6>[ 0.521124] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10434 12:13:19.612456 <6>[ 0.527613] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10435 12:13:19.619825 <6>[ 0.534618] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10436 12:13:19.626133 <6>[ 0.541105] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10437 12:13:19.632121 <6>[ 0.548108] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10438 12:13:19.638691 <6>[ 0.554594] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10439 12:13:19.645311 <6>[ 0.561599] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10440 12:13:19.648216 <6>[ 0.569115] ACPI: Interpreter disabled.
10441 12:13:19.657067 <6>[ 0.575538] iommu: Default domain type: Translated
10442 12:13:19.664096 <6>[ 0.580650] iommu: DMA domain TLB invalidation policy: strict mode
10443 12:13:19.667974 <5>[ 0.587307] SCSI subsystem initialized
10444 12:13:19.674094 <6>[ 0.591473] usbcore: registered new interface driver usbfs
10445 12:13:19.680406 <6>[ 0.597204] usbcore: registered new interface driver hub
10446 12:13:19.684045 <6>[ 0.602754] usbcore: registered new device driver usb
10447 12:13:19.690484 <6>[ 0.608855] pps_core: LinuxPPS API ver. 1 registered
10448 12:13:19.700496 <6>[ 0.614050] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10449 12:13:19.704235 <6>[ 0.623396] PTP clock support registered
10450 12:13:19.707093 <6>[ 0.627640] EDAC MC: Ver: 3.0.0
10451 12:13:19.715083 <6>[ 0.632804] FPGA manager framework
10452 12:13:19.721205 <6>[ 0.636482] Advanced Linux Sound Architecture Driver Initialized.
10453 12:13:19.724929 <6>[ 0.643258] vgaarb: loaded
10454 12:13:19.731349 <6>[ 0.646412] clocksource: Switched to clocksource arch_sys_counter
10455 12:13:19.734734 <5>[ 0.652849] VFS: Disk quotas dquot_6.6.0
10456 12:13:19.740952 <6>[ 0.657034] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10457 12:13:19.744147 <6>[ 0.664222] pnp: PnP ACPI: disabled
10458 12:13:19.753051 <6>[ 0.670946] NET: Registered PF_INET protocol family
10459 12:13:19.762726 <6>[ 0.676537] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10460 12:13:19.773699 <6>[ 0.688867] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10461 12:13:19.783499 <6>[ 0.697682] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10462 12:13:19.791130 <6>[ 0.705647] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10463 12:13:19.800667 <6>[ 0.714346] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10464 12:13:19.807130 <6>[ 0.724066] TCP: Hash tables configured (established 65536 bind 65536)
10465 12:13:19.814208 <6>[ 0.730926] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10466 12:13:19.823031 <6>[ 0.738128] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10467 12:13:19.829868 <6>[ 0.745824] NET: Registered PF_UNIX/PF_LOCAL protocol family
10468 12:13:19.836406 <6>[ 0.751972] RPC: Registered named UNIX socket transport module.
10469 12:13:19.839772 <6>[ 0.758125] RPC: Registered udp transport module.
10470 12:13:19.846111 <6>[ 0.763059] RPC: Registered tcp transport module.
10471 12:13:19.852935 <6>[ 0.767990] RPC: Registered tcp NFSv4.1 backchannel transport module.
10472 12:13:19.856409 <6>[ 0.774654] PCI: CLS 0 bytes, default 64
10473 12:13:19.860264 <6>[ 0.778987] Unpacking initramfs...
10474 12:13:19.877742 <6>[ 0.790998] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10475 12:13:19.886512 <6>[ 0.799658] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10476 12:13:19.889770 <6>[ 0.808519] kvm [1]: IPA Size Limit: 40 bits
10477 12:13:19.896128 <6>[ 0.813052] kvm [1]: GICv3: no GICV resource entry
10478 12:13:19.899458 <6>[ 0.818075] kvm [1]: disabling GICv2 emulation
10479 12:13:19.906504 <6>[ 0.822763] kvm [1]: GIC system register CPU interface enabled
10480 12:13:19.909593 <6>[ 0.828934] kvm [1]: vgic interrupt IRQ18
10481 12:13:19.915568 <6>[ 0.833291] kvm [1]: VHE mode initialized successfully
10482 12:13:19.923041 <5>[ 0.839819] Initialise system trusted keyrings
10483 12:13:19.929031 <6>[ 0.844636] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10484 12:13:19.937243 <6>[ 0.854695] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10485 12:13:19.943309 <5>[ 0.861060] NFS: Registering the id_resolver key type
10486 12:13:19.946657 <5>[ 0.866360] Key type id_resolver registered
10487 12:13:19.953508 <5>[ 0.870775] Key type id_legacy registered
10488 12:13:19.959676 <6>[ 0.875053] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10489 12:13:19.966125 <6>[ 0.881974] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10490 12:13:19.972920 <6>[ 0.889686] 9p: Installing v9fs 9p2000 file system support
10491 12:13:20.009223 <5>[ 0.927291] Key type asymmetric registered
10492 12:13:20.013451 <5>[ 0.931625] Asymmetric key parser 'x509' registered
10493 12:13:20.022912 <6>[ 0.936767] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10494 12:13:20.025330 <6>[ 0.944381] io scheduler mq-deadline registered
10495 12:13:20.029544 <6>[ 0.949156] io scheduler kyber registered
10496 12:13:20.048203 <6>[ 0.966187] EINJ: ACPI disabled.
10497 12:13:20.079747 <4>[ 0.991412] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10498 12:13:20.089431 <4>[ 1.002053] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10499 12:13:20.104741 <6>[ 1.023024] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10500 12:13:20.113248 <6>[ 1.031074] printk: console [ttyS0] disabled
10501 12:13:20.141284 <6>[ 1.055723] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10502 12:13:20.147426 <6>[ 1.065196] printk: console [ttyS0] enabled
10503 12:13:20.151359 <6>[ 1.065196] printk: console [ttyS0] enabled
10504 12:13:20.157519 <6>[ 1.074093] printk: bootconsole [mtk8250] disabled
10505 12:13:20.160883 <6>[ 1.074093] printk: bootconsole [mtk8250] disabled
10506 12:13:20.168107 <6>[ 1.085355] SuperH (H)SCI(F) driver initialized
10507 12:13:20.171623 <6>[ 1.090646] msm_serial: driver initialized
10508 12:13:20.185330 <6>[ 1.099577] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10509 12:13:20.194821 <6>[ 1.108123] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10510 12:13:20.201759 <6>[ 1.116673] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10511 12:13:20.211524 <6>[ 1.125305] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10512 12:13:20.221046 <6>[ 1.134024] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10513 12:13:20.227578 <6>[ 1.142745] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10514 12:13:20.238147 <6>[ 1.151285] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10515 12:13:20.244352 <6>[ 1.160088] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10516 12:13:20.254477 <6>[ 1.168630] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10517 12:13:20.265617 <6>[ 1.184173] loop: module loaded
10518 12:13:20.272771 <6>[ 1.190240] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10519 12:13:20.295305 <4>[ 1.213558] mtk-pmic-keys: Failed to locate of_node [id: -1]
10520 12:13:20.302571 <6>[ 1.220499] megasas: 07.719.03.00-rc1
10521 12:13:20.312290 <6>[ 1.230042] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10522 12:13:20.324005 <6>[ 1.241789] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10523 12:13:20.340309 <6>[ 1.258541] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10524 12:13:20.397157 <6>[ 1.308386] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10525 12:13:20.607171 <6>[ 1.525684] Freeing initrd memory: 17376K
10526 12:13:20.617404 <6>[ 1.536032] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10527 12:13:20.628745 <6>[ 1.546960] tun: Universal TUN/TAP device driver, 1.6
10528 12:13:20.632012 <6>[ 1.553020] thunder_xcv, ver 1.0
10529 12:13:20.635548 <6>[ 1.556527] thunder_bgx, ver 1.0
10530 12:13:20.638773 <6>[ 1.560024] nicpf, ver 1.0
10531 12:13:20.649202 <6>[ 1.564026] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10532 12:13:20.652590 <6>[ 1.571502] hns3: Copyright (c) 2017 Huawei Corporation.
10533 12:13:20.656093 <6>[ 1.577093] hclge is initializing
10534 12:13:20.662459 <6>[ 1.580677] e1000: Intel(R) PRO/1000 Network Driver
10535 12:13:20.668993 <6>[ 1.585807] e1000: Copyright (c) 1999-2006 Intel Corporation.
10536 12:13:20.672490 <6>[ 1.591820] e1000e: Intel(R) PRO/1000 Network Driver
10537 12:13:20.678691 <6>[ 1.597035] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10538 12:13:20.685792 <6>[ 1.603221] igb: Intel(R) Gigabit Ethernet Network Driver
10539 12:13:20.692538 <6>[ 1.608870] igb: Copyright (c) 2007-2014 Intel Corporation.
10540 12:13:20.698979 <6>[ 1.614706] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10541 12:13:20.706442 <6>[ 1.621224] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10542 12:13:20.708820 <6>[ 1.627685] sky2: driver version 1.30
10543 12:13:20.715522 <6>[ 1.632676] VFIO - User Level meta-driver version: 0.3
10544 12:13:20.722972 <6>[ 1.640901] usbcore: registered new interface driver usb-storage
10545 12:13:20.730273 <6>[ 1.647348] usbcore: registered new device driver onboard-usb-hub
10546 12:13:20.738145 <6>[ 1.656484] mt6397-rtc mt6359-rtc: registered as rtc0
10547 12:13:20.748136 <6>[ 1.661947] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-31T12:13:20 UTC (1706703200)
10548 12:13:20.751634 <6>[ 1.671526] i2c_dev: i2c /dev entries driver
10549 12:13:20.768642 <6>[ 1.683196] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10550 12:13:20.788224 <6>[ 1.706184] cpu cpu0: EM: created perf domain
10551 12:13:20.791528 <6>[ 1.711097] cpu cpu4: EM: created perf domain
10552 12:13:20.799087 <6>[ 1.716666] sdhci: Secure Digital Host Controller Interface driver
10553 12:13:20.804941 <6>[ 1.723098] sdhci: Copyright(c) Pierre Ossman
10554 12:13:20.811962 <6>[ 1.728048] Synopsys Designware Multimedia Card Interface Driver
10555 12:13:20.820094 <6>[ 1.734685] sdhci-pltfm: SDHCI platform and OF driver helper
10556 12:13:20.821851 <6>[ 1.734731] mmc0: CQHCI version 5.10
10557 12:13:20.828377 <6>[ 1.744819] ledtrig-cpu: registered to indicate activity on CPUs
10558 12:13:20.835342 <6>[ 1.751883] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10559 12:13:20.841466 <6>[ 1.758947] usbcore: registered new interface driver usbhid
10560 12:13:20.845102 <6>[ 1.764769] usbhid: USB HID core driver
10561 12:13:20.851563 <6>[ 1.768979] spi_master spi0: will run message pump with realtime priority
10562 12:13:20.898733 <6>[ 1.810232] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10563 12:13:20.917974 <6>[ 1.826028] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10564 12:13:20.924954 <6>[ 1.840944] cros-ec-spi spi0.0: Chrome EC device registered
10565 12:13:20.928388 <6>[ 1.847028] mmc0: Command Queue Engine enabled
10566 12:13:20.935289 <6>[ 1.851788] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10567 12:13:20.941651 <6>[ 1.859339] mmcblk0: mmc0:0001 DA4128 116 GiB
10568 12:13:20.952014 <6>[ 1.859866] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10569 12:13:20.955152 <6>[ 1.867712] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10570 12:13:20.961737 <6>[ 1.874464] NET: Registered PF_PACKET protocol family
10571 12:13:20.967862 <6>[ 1.880675] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10572 12:13:20.971417 <6>[ 1.884677] 9pnet: Installing 9P2000 support
10573 12:13:20.978426 <6>[ 1.890476] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10574 12:13:20.981400 <5>[ 1.894360] Key type dns_resolver registered
10575 12:13:20.988015 <6>[ 1.900235] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10576 12:13:20.990760 <6>[ 1.904609] registered taskstats version 1
10577 12:13:20.997713 <5>[ 1.915012] Loading compiled-in X.509 certificates
10578 12:13:21.025959 <4>[ 1.937551] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10579 12:13:21.036395 <4>[ 1.948281] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10580 12:13:21.043064 <3>[ 1.958829] debugfs: File 'uA_load' in directory '/' already present!
10581 12:13:21.049223 <3>[ 1.965535] debugfs: File 'min_uV' in directory '/' already present!
10582 12:13:21.056390 <3>[ 1.972193] debugfs: File 'max_uV' in directory '/' already present!
10583 12:13:21.062543 <3>[ 1.978803] debugfs: File 'constraint_flags' in directory '/' already present!
10584 12:13:21.073116 <3>[ 1.988385] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10585 12:13:21.083998 <6>[ 2.001894] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10586 12:13:21.091278 <6>[ 2.008850] xhci-mtk 11200000.usb: xHCI Host Controller
10587 12:13:21.097003 <6>[ 2.014354] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10588 12:13:21.107472 <6>[ 2.022199] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10589 12:13:21.114474 <6>[ 2.031621] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10590 12:13:21.121799 <6>[ 2.037701] xhci-mtk 11200000.usb: xHCI Host Controller
10591 12:13:21.127064 <6>[ 2.043184] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10592 12:13:21.134094 <6>[ 2.050833] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10593 12:13:21.140663 <6>[ 2.058602] hub 1-0:1.0: USB hub found
10594 12:13:21.144042 <6>[ 2.062614] hub 1-0:1.0: 1 port detected
10595 12:13:21.153634 <6>[ 2.066892] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10596 12:13:21.157197 <6>[ 2.075606] hub 2-0:1.0: USB hub found
10597 12:13:21.160342 <6>[ 2.079627] hub 2-0:1.0: 1 port detected
10598 12:13:21.170060 <6>[ 2.087979] mtk-msdc 11f70000.mmc: Got CD GPIO
10599 12:13:21.183017 <6>[ 2.097270] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10600 12:13:21.189634 <6>[ 2.105344] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10601 12:13:21.198806 <4>[ 2.113273] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10602 12:13:21.208865 <6>[ 2.122807] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10603 12:13:21.215192 <6>[ 2.130883] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10604 12:13:21.221845 <6>[ 2.138983] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10605 12:13:21.232048 <6>[ 2.146908] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10606 12:13:21.239728 <6>[ 2.154725] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10607 12:13:21.249058 <6>[ 2.162543] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10608 12:13:21.259113 <6>[ 2.173040] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10609 12:13:21.265138 <6>[ 2.181427] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10610 12:13:21.275826 <6>[ 2.189768] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10611 12:13:21.282148 <6>[ 2.198109] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10612 12:13:21.291912 <6>[ 2.206450] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10613 12:13:21.301507 <6>[ 2.214788] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10614 12:13:21.307947 <6>[ 2.223126] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10615 12:13:21.318027 <6>[ 2.231463] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10616 12:13:21.324781 <6>[ 2.239802] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10617 12:13:21.334599 <6>[ 2.248141] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10618 12:13:21.341330 <6>[ 2.256489] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10619 12:13:21.351313 <6>[ 2.264841] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10620 12:13:21.357735 <6>[ 2.273181] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10621 12:13:21.368245 <6>[ 2.281520] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10622 12:13:21.374905 <6>[ 2.289858] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10623 12:13:21.381147 <6>[ 2.298654] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10624 12:13:21.387513 <6>[ 2.305822] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10625 12:13:21.394435 <6>[ 2.312582] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10626 12:13:21.404038 <6>[ 2.319342] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10627 12:13:21.410963 <6>[ 2.326298] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10628 12:13:21.417259 <6>[ 2.333137] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10629 12:13:21.427787 <6>[ 2.342266] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10630 12:13:21.437276 <6>[ 2.351384] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10631 12:13:21.446992 <6>[ 2.360678] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10632 12:13:21.456929 <6>[ 2.370145] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10633 12:13:21.467249 <6>[ 2.379611] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10634 12:13:21.474056 <6>[ 2.388730] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10635 12:13:21.484175 <6>[ 2.398194] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10636 12:13:21.493146 <6>[ 2.407313] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10637 12:13:21.504139 <6>[ 2.416607] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10638 12:13:21.513781 <6>[ 2.426767] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10639 12:13:21.524342 <6>[ 2.438741] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10640 12:13:21.530591 <6>[ 2.448480] Trying to probe devices needed for running init ...
10641 12:13:21.551916 <6>[ 2.466745] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10642 12:13:21.580340 <6>[ 2.498342] hub 2-1:1.0: USB hub found
10643 12:13:21.583450 <6>[ 2.502866] hub 2-1:1.0: 3 ports detected
10644 12:13:21.591912 <6>[ 2.510015] hub 2-1:1.0: USB hub found
10645 12:13:21.595028 <6>[ 2.514323] hub 2-1:1.0: 3 ports detected
10646 12:13:21.703319 <6>[ 2.618690] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10647 12:13:21.857840 <6>[ 2.776517] hub 1-1:1.0: USB hub found
10648 12:13:21.861580 <6>[ 2.780959] hub 1-1:1.0: 4 ports detected
10649 12:13:21.871202 <6>[ 2.789595] hub 1-1:1.0: USB hub found
10650 12:13:21.874583 <6>[ 2.793991] hub 1-1:1.0: 4 ports detected
10651 12:13:21.944301 <6>[ 2.858962] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10652 12:13:22.195629 <6>[ 3.110728] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10653 12:13:22.328116 <6>[ 3.246688] hub 1-1.4:1.0: USB hub found
10654 12:13:22.331339 <6>[ 3.251365] hub 1-1.4:1.0: 2 ports detected
10655 12:13:22.341496 <6>[ 3.259689] hub 1-1.4:1.0: USB hub found
10656 12:13:22.345076 <6>[ 3.264294] hub 1-1.4:1.0: 2 ports detected
10657 12:13:22.643743 <6>[ 3.558699] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10658 12:13:22.835440 <6>[ 3.750700] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10659 12:13:33.812647 <6>[ 14.735699] ALSA device list:
10660 12:13:33.819520 <6>[ 14.738995] No soundcards found.
10661 12:13:33.827183 <6>[ 14.746991] Freeing unused kernel memory: 8448K
10662 12:13:33.830419 <6>[ 14.752005] Run /init as init process
10663 12:13:33.842100 Loading, please wait...
10664 12:13:33.862068 Starting version 247.3-7+deb11u2
10665 12:13:34.069301 <6>[ 14.985213] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10666 12:13:34.077248 <6>[ 14.997506] remoteproc remoteproc0: scp is available
10667 12:13:34.084878 <6>[ 15.001438] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10668 12:13:34.091199 <6>[ 15.003075] remoteproc remoteproc0: powering up scp
10669 12:13:34.101255 <6>[ 15.010457] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10670 12:13:34.107801 <6>[ 15.015707] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10671 12:13:34.118116 <6>[ 15.024477] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10672 12:13:34.124091 <6>[ 15.024909] usbcore: registered new device driver r8152-cfgselector
10673 12:13:34.127188 <6>[ 15.033293] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10674 12:13:34.138084 <3>[ 15.054244] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10675 12:13:34.141140 <6>[ 15.056250] mc: Linux media interface: v0.10
10676 12:13:34.151126 <3>[ 15.062463] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10677 12:13:34.158560 <6>[ 15.067847] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10678 12:13:34.165009 <4>[ 15.068200] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10679 12:13:34.174084 <4>[ 15.068312] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10680 12:13:34.180805 <3>[ 15.075288] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10681 12:13:34.190924 <3>[ 15.106177] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 12:13:34.197871 <4>[ 15.113120] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10683 12:13:34.204265 <4>[ 15.113120] Fallback method does not support PEC.
10684 12:13:34.210891 <3>[ 15.114471] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 12:13:34.220895 <3>[ 15.136183] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 12:13:34.228057 <3>[ 15.144426] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 12:13:34.238255 <3>[ 15.144658] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10688 12:13:34.244745 <6>[ 15.150771] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10689 12:13:34.254991 <3>[ 15.152571] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 12:13:34.261172 <6>[ 15.155605] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10691 12:13:34.271540 <6>[ 15.155971] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10692 12:13:34.278264 <6>[ 15.163847] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10693 12:13:34.287947 <3>[ 15.169658] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 12:13:34.291359 <6>[ 15.177701] pci_bus 0000:00: root bus resource [bus 00-ff]
10695 12:13:34.301270 <6>[ 15.179410] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10696 12:13:34.307881 <6>[ 15.179416] remoteproc remoteproc0: remote processor scp is now up
10697 12:13:34.314128 <6>[ 15.179434] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10698 12:13:34.323910 <4>[ 15.182355] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10699 12:13:34.330588 <4>[ 15.182366] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10700 12:13:34.340651 <6>[ 15.182941] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10701 12:13:34.351223 <3>[ 15.185362] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10702 12:13:34.357510 <3>[ 15.187853] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10703 12:13:34.364682 <6>[ 15.197383] videodev: Linux video capture interface: v2.00
10704 12:13:34.370972 <6>[ 15.199358] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10705 12:13:34.380173 <6>[ 15.200884] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10706 12:13:34.390382 <6>[ 15.200894] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10707 12:13:34.396974 <6>[ 15.200935] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10708 12:13:34.403511 <6>[ 15.200949] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10709 12:13:34.406774 <6>[ 15.201020] pci 0000:00:00.0: supports D1 D2
10710 12:13:34.413433 <6>[ 15.201022] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10711 12:13:34.423139 <6>[ 15.202088] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10712 12:13:34.429490 <6>[ 15.202182] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10713 12:13:34.436180 <6>[ 15.202207] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10714 12:13:34.443255 <6>[ 15.202223] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10715 12:13:34.449540 <6>[ 15.202238] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10716 12:13:34.456305 <6>[ 15.202347] pci 0000:01:00.0: supports D1 D2
10717 12:13:34.462648 <6>[ 15.202348] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10718 12:13:34.469996 <6>[ 15.203233] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10719 12:13:34.479472 <3>[ 15.203679] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10720 12:13:34.485805 <3>[ 15.203683] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10721 12:13:34.492616 <6>[ 15.214592] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10722 12:13:34.502981 <3>[ 15.217575] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 12:13:34.505595 <6>[ 15.218074] Bluetooth: Core ver 2.22
10724 12:13:34.512190 <6>[ 15.218131] NET: Registered PF_BLUETOOTH protocol family
10725 12:13:34.519207 <6>[ 15.218133] Bluetooth: HCI device and connection manager initialized
10726 12:13:34.522205 <6>[ 15.218164] Bluetooth: HCI socket layer initialized
10727 12:13:34.528638 <6>[ 15.218170] Bluetooth: L2CAP socket layer initialized
10728 12:13:34.532270 <6>[ 15.218179] Bluetooth: SCO socket layer initialized
10729 12:13:34.542151 <6>[ 15.226111] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10730 12:13:34.548872 <3>[ 15.232455] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10731 12:13:34.555820 <6>[ 15.234536] r8152 2-1.3:1.0 eth0: v1.12.13
10732 12:13:34.558837 <6>[ 15.234606] usbcore: registered new interface driver r8152
10733 12:13:34.568811 <6>[ 15.239847] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10734 12:13:34.575260 <3>[ 15.248526] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 12:13:34.584921 <3>[ 15.248534] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 12:13:34.591999 <6>[ 15.256891] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10737 12:13:34.598188 <6>[ 15.257079] usbcore: registered new interface driver cdc_ether
10738 12:13:34.606305 <3>[ 15.265915] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 12:13:34.612705 <6>[ 15.266419] usbcore: registered new interface driver r8153_ecm
10740 12:13:34.617723 <6>[ 15.267370] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10741 12:13:34.631155 <6>[ 15.268725] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10742 12:13:34.637856 <6>[ 15.268974] usbcore: registered new interface driver uvcvideo
10743 12:13:34.644945 <6>[ 15.274890] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10744 12:13:34.650999 <6>[ 15.281953] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10745 12:13:34.660671 <3>[ 15.282796] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10746 12:13:34.668101 <6>[ 15.283417] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10747 12:13:34.674566 <6>[ 15.288524] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10748 12:13:34.680703 <6>[ 15.288964] usbcore: registered new interface driver btusb
10749 12:13:34.691537 <4>[ 15.289595] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10750 12:13:34.697635 <3>[ 15.289603] Bluetooth: hci0: Failed to load firmware file (-2)
10751 12:13:34.700681 <3>[ 15.289607] Bluetooth: hci0: Failed to set up firmware (-2)
10752 12:13:34.714327 <4>[ 15.289610] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10753 12:13:34.717651 <6>[ 15.637295] pci 0000:00:00.0: PCI bridge to [bus 01]
10754 12:13:34.727037 <6>[ 15.642515] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10755 12:13:34.733496 <6>[ 15.650689] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10756 12:13:34.740124 <6>[ 15.657519] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10757 12:13:34.746783 <6>[ 15.664186] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10758 12:13:34.761370 <5>[ 15.678250] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10759 12:13:34.778564 <5>[ 15.694055] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10760 12:13:34.784183 <5>[ 15.701427] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10761 12:13:34.793942 <4>[ 15.709879] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10762 12:13:34.800818 <6>[ 15.718767] cfg80211: failed to load regulatory.db
10763 12:13:34.846125 <6>[ 15.762802] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10764 12:13:34.852606 <6>[ 15.770300] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10765 12:13:34.876842 <6>[ 15.796946] mt7921e 0000:01:00.0: ASIC revision: 79610010
10766 12:13:34.982032 <6>[ 15.898527] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10767 12:13:34.985758 <6>[ 15.898527]
10768 12:13:34.988676 Begin: Loading essential drivers ... done.
10769 12:13:34.992180 Begin: Running /scripts/init-premount ... done.
10770 12:13:34.998899 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10771 12:13:35.008336 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10772 12:13:35.011874 Device /sys/class/net/enx002432307c7b found
10773 12:13:35.012403 done.
10774 12:13:35.066145 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10775 12:13:35.254221 <6>[ 16.170148] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10776 12:13:35.957459 <6>[ 16.877221] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10777 12:13:36.094820 <6>[ 17.014451] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10778 12:13:36.241964 IP-Config: no response after 2 secs - giving up
10779 12:13:36.270913 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:a1 mtu 1500 DHCP
10780 12:13:36.998075 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10781 12:13:37.004133 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10782 12:13:37.010795 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10783 12:13:37.017610 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10784 12:13:37.024227 host : mt8192-asurada-spherion-r0-cbg-2
10785 12:13:37.030487 domain : lava-rack
10786 12:13:37.034117 rootserver: 192.168.201.1 rootpath:
10787 12:13:37.034635 filename :
10788 12:13:37.155527 done.
10789 12:13:37.164163 Begin: Running /scripts/nfs-bottom ... done.
10790 12:13:37.182084 Begin: Running /scripts/init-bottom ... done.
10791 12:13:38.434797 <6>[ 19.354340] NET: Registered PF_INET6 protocol family
10792 12:13:38.443403 <6>[ 19.361929] Segment Routing with IPv6
10793 12:13:38.444980 <6>[ 19.365898] In-situ OAM (IOAM) with IPv6
10794 12:13:38.586146 <30>[ 19.486568] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10795 12:13:38.592172 <30>[ 19.511072] systemd[1]: Detected architecture arm64.
10796 12:13:38.613660
10797 12:13:38.616779 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10798 12:13:38.617206
10799 12:13:38.633817 <30>[ 19.553853] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10800 12:13:39.536339 <30>[ 20.453131] systemd[1]: Queued start job for default target Graphical Interface.
10801 12:13:39.572455 <30>[ 20.493067] systemd[1]: Created slice system-getty.slice.
10802 12:13:39.578703 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10803 12:13:39.595272 <30>[ 20.516168] systemd[1]: Created slice system-modprobe.slice.
10804 12:13:39.602443 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10805 12:13:39.619275 <30>[ 20.540000] systemd[1]: Created slice system-serial\x2dgetty.slice.
10806 12:13:39.628937 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10807 12:13:39.642916 <30>[ 20.563753] systemd[1]: Created slice User and Session Slice.
10808 12:13:39.649215 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10809 12:13:39.669807 <30>[ 20.587550] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10810 12:13:39.681141 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10811 12:13:39.697926 <30>[ 20.615480] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10812 12:13:39.704357 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10813 12:13:39.729057 <30>[ 20.642867] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10814 12:13:39.735608 <30>[ 20.655035] systemd[1]: Reached target Local Encrypted Volumes.
10815 12:13:39.742339 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10816 12:13:39.758505 <30>[ 20.679284] systemd[1]: Reached target Paths.
10817 12:13:39.764873 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10818 12:13:39.777975 <30>[ 20.698711] systemd[1]: Reached target Remote File Systems.
10819 12:13:39.784277 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10820 12:13:39.801939 <30>[ 20.723072] systemd[1]: Reached target Slices.
10821 12:13:39.808744 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10822 12:13:39.821859 <30>[ 20.742726] systemd[1]: Reached target Swap.
10823 12:13:39.825140 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10824 12:13:39.845585 <30>[ 20.763194] systemd[1]: Listening on initctl Compatibility Named Pipe.
10825 12:13:39.852101 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10826 12:13:39.859075 <30>[ 20.779405] systemd[1]: Listening on Journal Audit Socket.
10827 12:13:39.865524 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10828 12:13:39.883304 <30>[ 20.804091] systemd[1]: Listening on Journal Socket (/dev/log).
10829 12:13:39.890018 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10830 12:13:39.906619 <30>[ 20.827275] systemd[1]: Listening on Journal Socket.
10831 12:13:39.913118 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10832 12:13:39.930516 <30>[ 20.848303] systemd[1]: Listening on Network Service Netlink Socket.
10833 12:13:39.937057 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10834 12:13:39.953131 <30>[ 20.873877] systemd[1]: Listening on udev Control Socket.
10835 12:13:39.959821 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10836 12:13:39.974423 <30>[ 20.895134] systemd[1]: Listening on udev Kernel Socket.
10837 12:13:39.980471 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10838 12:13:40.030251 <30>[ 20.951223] systemd[1]: Mounting Huge Pages File System...
10839 12:13:40.036896 Mounting [0;1;39mHuge Pages File System[0m...
10840 12:13:40.052230 <30>[ 20.973101] systemd[1]: Mounting POSIX Message Queue File System...
10841 12:13:40.058926 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10842 12:13:40.077706 <30>[ 20.998327] systemd[1]: Mounting Kernel Debug File System...
10843 12:13:40.084072 Mounting [0;1;39mKernel Debug File System[0m...
10844 12:13:40.101245 <30>[ 21.019217] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10845 12:13:40.124498 <30>[ 21.042026] systemd[1]: Starting Create list of static device nodes for the current kernel...
10846 12:13:40.131023 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10847 12:13:40.149367 <30>[ 21.069937] systemd[1]: Starting Load Kernel Module configfs...
10848 12:13:40.155447 Starting [0;1;39mLoad Kernel Module configfs[0m...
10849 12:13:40.175146 <30>[ 21.095884] systemd[1]: Starting Load Kernel Module drm...
10850 12:13:40.181311 Starting [0;1;39mLoad Kernel Module drm[0m...
10851 12:13:40.198899 <30>[ 21.119704] systemd[1]: Starting Load Kernel Module fuse...
10852 12:13:40.205047 Starting [0;1;39mLoad Kernel Module fuse[0m...
10853 12:13:40.242501 <30>[ 21.160028] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10854 12:13:40.249456 <6>[ 21.170201] fuse: init (API version 7.37)
10855 12:13:40.274553 <30>[ 21.195499] systemd[1]: Starting Journal Service...
10856 12:13:40.281114 Starting [0;1;39mJournal Service[0m...
10857 12:13:40.305267 <30>[ 21.225910] systemd[1]: Starting Load Kernel Modules...
10858 12:13:40.311984 Starting [0;1;39mLoad Kernel Modules[0m...
10859 12:13:40.334723 <30>[ 21.251797] systemd[1]: Starting Remount Root and Kernel File Systems...
10860 12:13:40.340667 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10861 12:13:40.361510 <30>[ 21.282002] systemd[1]: Starting Coldplug All udev Devices...
10862 12:13:40.368236 Starting [0;1;39mColdplug All udev Devices[0m...
10863 12:13:40.388488 <30>[ 21.309416] systemd[1]: Mounted Huge Pages File System.
10864 12:13:40.394838 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10865 12:13:40.410899 <30>[ 21.331137] systemd[1]: Mounted POSIX Message Queue File System.
10866 12:13:40.420696 <3>[ 21.335173] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10867 12:13:40.427700 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10868 12:13:40.442889 <30>[ 21.363119] systemd[1]: Mounted Kernel Debug File System.
10869 12:13:40.456783 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0<3>[ 21.373447] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10870 12:13:40.456889 m.
10871 12:13:40.478546 <30>[ 21.395588] systemd[1]: Finished Create list of static device nodes for the current kernel.
10872 12:13:40.511157 <3>[ 21.428273] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10873 12:13:40.520654 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10874 12:13:40.535775 <30>[ 21.456297] systemd[1]: modprobe@configfs.service: Succeeded.
10875 12:13:40.545624 <3>[ 21.461909] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10876 12:13:40.552584 <30>[ 21.464508] systemd[1]: Finished Load Kernel Module configfs.
10877 12:13:40.558775 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10878 12:13:40.574628 <3>[ 21.491637] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10879 12:13:40.581584 <30>[ 21.502241] systemd[1]: modprobe@drm.service: Succeeded.
10880 12:13:40.588613 <30>[ 21.509205] systemd[1]: Finished Load Kernel Module drm.
10881 12:13:40.595272 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10882 12:13:40.605100 <3>[ 21.521779] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 12:13:40.615601 <30>[ 21.536937] systemd[1]: modprobe@fuse.service: Succeeded.
10884 12:13:40.622899 <30>[ 21.543905] systemd[1]: Finished Load Kernel Module fuse.
10885 12:13:40.636651 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<3>[ 21.553918] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 12:13:40.640363 l Module fuse[0m.
10887 12:13:40.656326 <30>[ 21.576472] systemd[1]: Finished Load Kernel Modules.
10888 12:13:40.669651 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne<3>[ 21.586099] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 12:13:40.669750 l Modules[0m.
10890 12:13:40.687865 <30>[ 21.608434] systemd[1]: Finished Remount Root and Kernel File Systems.
10891 12:13:40.705280 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel Fi<3>[ 21.620048] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 12:13:40.705404 le Systems[0m.
10893 12:13:40.738313 <3>[ 21.656023] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 12:13:40.745112 <30>[ 21.658773] systemd[1]: Mounting FUSE Control File System...
10895 12:13:40.751285 Mounting [0;1;39mFUSE Control File System[0m...
10896 12:13:40.774486 <30>[ 21.692308] systemd[1]: Mounting Kernel Configuration File System...
10897 12:13:40.777624 Mounting [0;1;39mKernel Configuration File System[0m...
10898 12:13:40.803348 <30>[ 21.720993] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10899 12:13:40.813097 <30>[ 21.730064] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10900 12:13:40.821856 <30>[ 21.742823] systemd[1]: Starting Load/Save Random Seed...
10901 12:13:40.828562 Starting [0;1;39mLoad/Save Random Seed[0m...
10902 12:13:40.850231 <30>[ 21.771209] systemd[1]: Starting Apply Kernel Variables...
10903 12:13:40.856720 Starting [0;1;39mApply Kernel Variables[0m...
10904 12:13:40.874946 <30>[ 21.796144] systemd[1]: Starting Create System Users...
10905 12:13:40.881743 Starting [0;1;39mCreate System Users[0m...
10906 12:13:40.895921 <30>[ 21.816709] systemd[1]: Started Journal Service.
10907 12:13:40.899643 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10908 12:13:40.921559 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10909 12:13:40.946552 <4>[ 21.857487] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10910 12:13:40.956116 <3>[ 21.873187] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10911 12:13:40.963137 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10912 12:13:40.980192 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10913 12:13:41.002210 See 'systemctl status systemd-udev-trigger.service' for details.
10914 12:13:41.020338 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10915 12:13:41.039682 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10916 12:13:41.055639 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10917 12:13:41.098158 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10918 12:13:41.116053 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10919 12:13:41.151264 <46>[ 22.069085] systemd-journald[296]: Received client request to flush runtime journal.
10920 12:13:41.910492 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10921 12:13:41.922280 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10922 12:13:41.937659 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10923 12:13:41.989799 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10924 12:13:42.570299 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10925 12:13:42.606360 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10926 12:13:42.685404 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10927 12:13:42.748252 Starting [0;1;39mNetwork Service[0m...
10928 12:13:43.054417 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10929 12:13:43.075199 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10930 12:13:43.121959 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10931 12:13:43.465139 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10932 12:13:43.485609 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10933 12:13:43.502024 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10934 12:13:43.532287 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10935 12:13:43.546068 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10936 12:13:43.614837 Starting [0;1;39mNetwork Name Resolution[0m...
10937 12:13:43.634649 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10938 12:13:43.661548 Starting [0;1;39mNetwork Time Synchronization[0m...
10939 12:13:43.682499 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10940 12:13:43.724505 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10941 12:13:43.766626 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10942 12:13:44.154590 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10943 12:13:44.171312 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10944 12:13:44.189154 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10945 12:13:44.203674 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10946 12:13:44.218394 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10947 12:13:44.246753 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10948 12:13:44.267472 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10949 12:13:44.287590 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10950 12:13:44.307668 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10951 12:13:44.321853 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10952 12:13:44.348359 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10953 12:13:44.361495 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10954 12:13:44.377301 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10955 12:13:44.430277 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10956 12:13:44.538038 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10957 12:13:44.618751 Starting [0;1;39mUser Login Management[0m...
10958 12:13:44.637285 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10959 12:13:44.656674 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10960 12:13:44.673485 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10961 12:13:44.719851 Starting [0;1;39mPermit User Sessions[0m...
10962 12:13:44.828462 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10963 12:13:44.850371 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10964 12:13:44.899119 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10965 12:13:44.919093 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10966 12:13:44.933837 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10967 12:13:44.952339 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10968 12:13:44.961067 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10969 12:13:44.978679 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10970 12:13:45.038477 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10971 12:13:45.085439 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10972 12:13:45.194087
10973 12:13:45.194237
10974 12:13:45.197304 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10975 12:13:45.197386
10976 12:13:45.200563 debian-bullseye-arm64 login: root (automatic login)
10977 12:13:45.200645
10978 12:13:45.200709
10979 12:13:45.585863 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024 aarch64
10980 12:13:45.585999
10981 12:13:45.592544 The programs included with the Debian GNU/Linux system are free software;
10982 12:13:45.598947 the exact distribution terms for each program are described in the
10983 12:13:45.602329 individual files in /usr/share/doc/*/copyright.
10984 12:13:45.602411
10985 12:13:45.609035 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10986 12:13:45.611857 permitted by applicable law.
10987 12:13:46.495693 Matched prompt #10: / #
10989 12:13:46.495974 Setting prompt string to ['/ #']
10990 12:13:46.496068 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10992 12:13:46.496261 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10993 12:13:46.496350 start: 2.2.6 expect-shell-connection (timeout 00:03:16) [common]
10994 12:13:46.496418 Setting prompt string to ['/ #']
10995 12:13:46.496478 Forcing a shell prompt, looking for ['/ #']
10997 12:13:46.546707 / #
10998 12:13:46.546882 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10999 12:13:46.546965 Waiting using forced prompt support (timeout 00:02:30)
11000 12:13:46.551959
11001 12:13:46.552245 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11002 12:13:46.552344 start: 2.2.7 export-device-env (timeout 00:03:16) [common]
11004 12:13:46.652715 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12669504/extract-nfsrootfs-y7wd4bc_'
11005 12:13:46.658460 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12669504/extract-nfsrootfs-y7wd4bc_'
11007 12:13:46.759022 / # export NFS_SERVER_IP='192.168.201.1'
11008 12:13:46.763860 export NFS_SERVER_IP='192.168.201.1'
11009 12:13:46.764145 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11010 12:13:46.764248 end: 2.2 depthcharge-retry (duration 00:01:44) [common]
11011 12:13:46.764340 end: 2 depthcharge-action (duration 00:01:44) [common]
11012 12:13:46.764429 start: 3 lava-test-retry (timeout 00:07:32) [common]
11013 12:13:46.764515 start: 3.1 lava-test-shell (timeout 00:07:32) [common]
11014 12:13:46.764589 Using namespace: common
11016 12:13:46.864945 / # #
11017 12:13:46.865125 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11018 12:13:46.870398 #
11019 12:13:46.870664 Using /lava-12669504
11021 12:13:46.971024 / # export SHELL=/bin/bash
11022 12:13:46.976662 export SHELL=/bin/bash
11024 12:13:47.077216 / # . /lava-12669504/environment
11025 12:13:47.082400 . /lava-12669504/environment
11027 12:13:47.189569 / # /lava-12669504/bin/lava-test-runner /lava-12669504/0
11028 12:13:47.189738 Test shell timeout: 10s (minimum of the action and connection timeout)
11029 12:13:47.195635 /lava-12669504/bin/lava-test-runner /lava-12669504/0
11030 12:13:47.503528 + export TESTRUN_ID=0_timesync-off
11031 12:13:47.506005 + TESTRUN_ID=0_timesync-off
11032 12:13:47.509180 + cd /lava-12669504/0/tests/0_timesync-off
11033 12:13:47.512508 ++ cat uuid
11034 12:13:47.517185 + UUID=12669504_1.6.2.3.1
11035 12:13:47.517283 + set +x
11036 12:13:47.524087 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12669504_1.6.2.3.1>
11037 12:13:47.524366 Received signal: <STARTRUN> 0_timesync-off 12669504_1.6.2.3.1
11038 12:13:47.524476 Starting test lava.0_timesync-off (12669504_1.6.2.3.1)
11039 12:13:47.524565 Skipping test definition patterns.
11040 12:13:47.527223 + systemctl stop systemd-timesyncd
11041 12:13:47.576013 + set +x
11042 12:13:47.579706 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12669504_1.6.2.3.1>
11043 12:13:47.579964 Received signal: <ENDRUN> 0_timesync-off 12669504_1.6.2.3.1
11044 12:13:47.580050 Ending use of test pattern.
11045 12:13:47.580117 Ending test lava.0_timesync-off (12669504_1.6.2.3.1), duration 0.06
11047 12:13:47.660030 + export TESTRUN_ID=1_kselftest-arm64
11048 12:13:47.660238 + TESTRUN_ID=1_kselftest-arm64
11049 12:13:47.667534 + cd /lava-12669504/0/tests/1_kselftest-arm64
11050 12:13:47.667653 ++ cat uuid
11051 12:13:47.674100 + UUID=12669504_1.6.2.3.5
11052 12:13:47.674215 + set +x
11053 12:13:47.680754 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 12669504_1.6.2.3.5>
11054 12:13:47.681050 Received signal: <STARTRUN> 1_kselftest-arm64 12669504_1.6.2.3.5
11055 12:13:47.681157 Starting test lava.1_kselftest-arm64 (12669504_1.6.2.3.5)
11056 12:13:47.681288 Skipping test definition patterns.
11057 12:13:47.683793 + cd ./automated/linux/kselftest/
11058 12:13:47.713512 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11059 12:13:47.757159 INFO: install_deps skipped
11060 12:13:47.885143 --2024-01-31 12:13:47-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11061 12:13:47.907001 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11062 12:13:48.040181 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11063 12:13:48.173451 HTTP request sent, awaiting response... 200 OK
11064 12:13:48.176388 Length: 2966336 (2.8M) [application/octet-stream]
11065 12:13:48.180409 Saving to: 'kselftest.tar.xz'
11066 12:13:48.180525
11067 12:13:48.180633
11068 12:13:48.438798 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11069 12:13:48.704689 kselftest.tar.xz 1%[ ] 47.81K 177KB/s
11070 12:13:48.988988 kselftest.tar.xz 7%[> ] 214.67K 397KB/s
11071 12:13:49.240280 kselftest.tar.xz 22%[===> ] 637.47K 768KB/s
11072 12:13:49.506208 kselftest.tar.xz 49%[========> ] 1.40M 1.29MB/s
11073 12:13:49.730095 kselftest.tar.xz 71%[=============> ] 2.03M 1.49MB/s
11074 12:13:49.790877 kselftest.tar.xz 94%[=================> ] 2.67M 1.69MB/s
11075 12:13:49.797028 kselftest.tar.xz 100%[===================>] 2.83M 1.72MB/s in 1.6s
11076 12:13:49.797132
11077 12:13:50.055625 2024-01-31 12:13:49 (1.72 MB/s) - 'kselftest.tar.xz' saved [2966336/2966336]
11078 12:13:50.055782
11079 12:13:56.746813 skiplist:
11080 12:13:56.749934 ========================================
11081 12:13:56.753629 ========================================
11082 12:13:56.812968 arm64:tags_test
11083 12:13:56.816002 arm64:run_tags_test.sh
11084 12:13:56.816416 arm64:fake_sigreturn_bad_magic
11085 12:13:56.819345 arm64:fake_sigreturn_bad_size
11086 12:13:56.823218 arm64:fake_sigreturn_bad_size_for_magic0
11087 12:13:56.826239 arm64:fake_sigreturn_duplicated_fpsimd
11088 12:13:56.829648 arm64:fake_sigreturn_misaligned_sp
11089 12:13:56.832798 arm64:fake_sigreturn_missing_fpsimd
11090 12:13:56.835972 arm64:fake_sigreturn_sme_change_vl
11091 12:13:56.839257 arm64:fake_sigreturn_sve_change_vl
11092 12:13:56.843114 arm64:mangle_pstate_invalid_compat_toggle
11093 12:13:56.845652 arm64:mangle_pstate_invalid_daif_bits
11094 12:13:56.849443 arm64:mangle_pstate_invalid_mode_el1h
11095 12:13:56.852530 arm64:mangle_pstate_invalid_mode_el1t
11096 12:13:56.855705 arm64:mangle_pstate_invalid_mode_el2h
11097 12:13:56.859191 arm64:mangle_pstate_invalid_mode_el2t
11098 12:13:56.861933 arm64:mangle_pstate_invalid_mode_el3h
11099 12:13:56.868955 arm64:mangle_pstate_invalid_mode_el3t
11100 12:13:56.869035 arm64:sme_trap_no_sm
11101 12:13:56.871970 arm64:sme_trap_non_streaming
11102 12:13:56.872055 arm64:sme_trap_za
11103 12:13:56.875327 arm64:sme_vl
11104 12:13:56.875452 arm64:ssve_regs
11105 12:13:56.878227 arm64:sve_regs
11106 12:13:56.878339 arm64:sve_vl
11107 12:13:56.878431 arm64:za_no_regs
11108 12:13:56.881819 arm64:za_regs
11109 12:13:56.881901 arm64:pac
11110 12:13:56.884989 arm64:fp-stress
11111 12:13:56.885069 arm64:sve-ptrace
11112 12:13:56.888684 arm64:sve-probe-vls
11113 12:13:56.888797 arm64:vec-syscfg
11114 12:13:56.888864 arm64:za-fork
11115 12:13:56.891661 arm64:za-ptrace
11116 12:13:56.895468 arm64:check_buffer_fill
11117 12:13:56.895884 arm64:check_child_memory
11118 12:13:56.898855 arm64:check_gcr_el1_cswitch
11119 12:13:56.902085 arm64:check_ksm_options
11120 12:13:56.902599 arm64:check_mmap_options
11121 12:13:56.905563 arm64:check_prctl
11122 12:13:56.908755 arm64:check_tags_inclusion
11123 12:13:56.909248 arm64:check_user_mem
11124 12:13:56.911854 arm64:btitest
11125 12:13:56.912373 arm64:nobtitest
11126 12:13:56.912725 arm64:hwcap
11127 12:13:56.914981 arm64:ptrace
11128 12:13:56.915441 arm64:syscall-abi
11129 12:13:56.918174 arm64:tpidr2
11130 12:13:56.921760 ============== Tests to run ===============
11131 12:13:56.922179 arm64:tags_test
11132 12:13:56.925333 arm64:run_tags_test.sh
11133 12:13:56.928075 arm64:fake_sigreturn_bad_magic
11134 12:13:56.931427 arm64:fake_sigreturn_bad_size
11135 12:13:56.934793 arm64:fake_sigreturn_bad_size_for_magic0
11136 12:13:56.938261 arm64:fake_sigreturn_duplicated_fpsimd
11137 12:13:56.941308 arm64:fake_sigreturn_misaligned_sp
11138 12:13:56.944910 arm64:fake_sigreturn_missing_fpsimd
11139 12:13:56.948218 arm64:fake_sigreturn_sme_change_vl
11140 12:13:56.951954 arm64:fake_sigreturn_sve_change_vl
11141 12:13:56.956112 arm64:mangle_pstate_invalid_compat_toggle
11142 12:13:56.957731 arm64:mangle_pstate_invalid_daif_bits
11143 12:13:56.961373 arm64:mangle_pstate_invalid_mode_el1h
11144 12:13:56.964748 arm64:mangle_pstate_invalid_mode_el1t
11145 12:13:56.968103 arm64:mangle_pstate_invalid_mode_el2h
11146 12:13:56.971144 arm64:mangle_pstate_invalid_mode_el2t
11147 12:13:56.974426 arm64:mangle_pstate_invalid_mode_el3h
11148 12:13:56.977702 arm64:mangle_pstate_invalid_mode_el3t
11149 12:13:56.977997 arm64:sme_trap_no_sm
11150 12:13:56.981702 arm64:sme_trap_non_streaming
11151 12:13:56.984357 arm64:sme_trap_za
11152 12:13:56.984798 arm64:sme_vl
11153 12:13:56.985183 arm64:ssve_regs
11154 12:13:56.987337 arm64:sve_regs
11155 12:13:56.987741 arm64:sve_vl
11156 12:13:56.991330 arm64:za_no_regs
11157 12:13:56.991661 arm64:za_regs
11158 12:13:56.991899 arm64:pac
11159 12:13:56.994163 arm64:fp-stress
11160 12:13:56.994453 arm64:sve-ptrace
11161 12:13:56.997694 arm64:sve-probe-vls
11162 12:13:56.997987 arm64:vec-syscfg
11163 12:13:57.001380 arm64:za-fork
11164 12:13:57.001670 arm64:za-ptrace
11165 12:13:57.004402 arm64:check_buffer_fill
11166 12:13:57.007243 arm64:check_child_memory
11167 12:13:57.007686 arm64:check_gcr_el1_cswitch
11168 12:13:57.010969 arm64:check_ksm_options
11169 12:13:57.013961 arm64:check_mmap_options
11170 12:13:57.014253 arm64:check_prctl
11171 12:13:57.017264 arm64:check_tags_inclusion
11172 12:13:57.017555 arm64:check_user_mem
11173 12:13:57.020639 arm64:btitest
11174 12:13:57.020927 arm64:nobtitest
11175 12:13:57.023872 arm64:hwcap
11176 12:13:57.024163 arm64:ptrace
11177 12:13:57.027881 arm64:syscall-abi
11178 12:13:57.028173 arm64:tpidr2
11179 12:13:57.030318 ===========End Tests to run ===============
11180 12:13:57.033629 shardfile-arm64 pass
11181 12:13:57.374112 <12>[ 38.296881] kselftest: Running tests in arm64
11182 12:13:57.387532 TAP version 13
11183 12:13:57.403010 1..48
11184 12:13:57.424158 # selftests: arm64: tags_test
11185 12:13:57.889194 ok 1 selftests: arm64: tags_test
11186 12:13:57.906181 # selftests: arm64: run_tags_test.sh
11187 12:13:57.953673 # --------------------
11188 12:13:57.955740 # running tags test
11189 12:13:57.955825 # --------------------
11190 12:13:57.959295 # [PASS]
11191 12:13:57.963371 ok 2 selftests: arm64: run_tags_test.sh
11192 12:13:57.975395 # selftests: arm64: fake_sigreturn_bad_magic
11193 12:13:58.047222 # Registered handlers for all signals.
11194 12:13:58.047393 # Detected MINSTKSIGSZ:4720
11195 12:13:58.050477 # Testcase initialized.
11196 12:13:58.054122 # uc context validated.
11197 12:13:58.057507 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11198 12:13:58.060940 # Handled SIG_COPYCTX
11199 12:13:58.061024 # Available space:3568
11200 12:13:58.067143 # Using badly built context - ERR: BAD MAGIC !
11201 12:13:58.073800 # SIG_OK -- SP:0xFFFFF268D220 si_addr@:0xfffff268d220 si_code:2 token@:0xfffff268bfc0 offset:-4704
11202 12:13:58.078337 # ==>> completed. PASS(1)
11203 12:13:58.083494 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11204 12:13:58.090328 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF268BFC0
11205 12:13:58.097241 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11206 12:13:58.100647 # selftests: arm64: fake_sigreturn_bad_size
11207 12:13:58.128016 # Registered handlers for all signals.
11208 12:13:58.128161 # Detected MINSTKSIGSZ:4720
11209 12:13:58.131394 # Testcase initialized.
11210 12:13:58.135088 # uc context validated.
11211 12:13:58.138413 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11212 12:13:58.141604 # Handled SIG_COPYCTX
11213 12:13:58.141683 # Available space:3568
11214 12:13:58.144930 # uc context validated.
11215 12:13:58.152171 # Using badly built context - ERR: Bad size for esr_context
11216 12:13:58.157756 # SIG_OK -- SP:0xFFFFCD67A730 si_addr@:0xffffcd67a730 si_code:2 token@:0xffffcd6794d0 offset:-4704
11217 12:13:58.161308 # ==>> completed. PASS(1)
11218 12:13:58.167786 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11219 12:13:58.174356 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCD6794D0
11220 12:13:58.178134 ok 4 selftests: arm64: fake_sigreturn_bad_size
11221 12:13:58.184139 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11222 12:13:58.205106 # Registered handlers for all signals.
11223 12:13:58.205193 # Detected MINSTKSIGSZ:4720
11224 12:13:58.208283 # Testcase initialized.
11225 12:13:58.211582 # uc context validated.
11226 12:13:58.214722 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11227 12:13:58.217873 # Handled SIG_COPYCTX
11228 12:13:58.217953 # Available space:3568
11229 12:13:58.224638 # Using badly built context - ERR: Bad size for terminator
11230 12:13:58.234445 # SIG_OK -- SP:0xFFFFF98135D0 si_addr@:0xfffff98135d0 si_code:2 token@:0xfffff9812370 offset:-4704
11231 12:13:58.234531 # ==>> completed. PASS(1)
11232 12:13:58.244387 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11233 12:13:58.251587 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF9812370
11234 12:13:58.254272 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11235 12:13:58.260897 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11236 12:13:58.303783 # Registered handlers for all signals.
11237 12:13:58.303899 # Detected MINSTKSIGSZ:4720
11238 12:13:58.306938 # Testcase initialized.
11239 12:13:58.310544 # uc context validated.
11240 12:13:58.313565 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11241 12:13:58.316654 # Handled SIG_COPYCTX
11242 12:13:58.316735 # Available space:3568
11243 12:13:58.323147 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11244 12:13:58.333602 # SIG_OK -- SP:0xFFFFFF839200 si_addr@:0xffffff839200 si_code:2 token@:0xffffff837fa0 offset:-4704
11245 12:13:58.333713 # ==>> completed. PASS(1)
11246 12:13:58.343133 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11247 12:13:58.349840 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFF837FA0
11248 12:13:58.352981 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11249 12:13:58.356473 # selftests: arm64: fake_sigreturn_misaligned_sp
11250 12:13:58.392319 # Registered handlers for all signals.
11251 12:13:58.392402 # Detected MINSTKSIGSZ:4720
11252 12:13:58.395079 # Testcase initialized.
11253 12:13:58.398584 # uc context validated.
11254 12:13:58.401635 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11255 12:13:58.405462 # Handled SIG_COPYCTX
11256 12:13:58.411912 # SIG_OK -- SP:0xFFFFC66F9933 si_addr@:0xffffc66f9933 si_code:2 token@:0xffffc66f9933 offset:0
11257 12:13:58.414747 # ==>> completed. PASS(1)
11258 12:13:58.421580 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11259 12:13:58.428077 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC66F9933
11260 12:13:58.434677 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11261 12:13:58.437962 # selftests: arm64: fake_sigreturn_missing_fpsimd
11262 12:13:58.492388 # Registered handlers for all signals.
11263 12:13:58.492489 # Detected MINSTKSIGSZ:4720
11264 12:13:58.495747 # Testcase initialized.
11265 12:13:58.498591 # uc context validated.
11266 12:13:58.502052 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11267 12:13:58.505463 # Handled SIG_COPYCTX
11268 12:13:58.508445 # Mangling template header. Spare space:4096
11269 12:13:58.512575 # Using badly built context - ERR: Missing FPSIMD
11270 12:13:58.522251 # SIG_OK -- SP:0xFFFFFD1E5440 si_addr@:0xfffffd1e5440 si_code:2 token@:0xfffffd1e41e0 offset:-4704
11271 12:13:58.525140 # ==>> completed. PASS(1)
11272 12:13:58.531944 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11273 12:13:58.538263 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFD1E41E0
11274 12:13:58.542057 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11275 12:13:58.548375 # selftests: arm64: fake_sigreturn_sme_change_vl
11276 12:13:58.561146 # Registered handlers for all signals.
11277 12:13:58.561231 # Detected MINSTKSIGSZ:4720
11278 12:13:58.564545 # ==>> completed. SKIP.
11279 12:13:58.571218 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11280 12:13:58.574122 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11281 12:13:58.583801 # selftests: arm64: fake_sigreturn_sve_change_vl
11282 12:13:58.655493 # Registered handlers for all signals.
11283 12:13:58.655626 # Detected MINSTKSIGSZ:4720
11284 12:13:58.659326 # ==>> completed. SKIP.
11285 12:13:58.665617 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11286 12:13:58.668856 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11287 12:13:58.676072 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11288 12:13:58.732372 # Registered handlers for all signals.
11289 12:13:58.732471 # Detected MINSTKSIGSZ:4720
11290 12:13:58.735816 # Testcase initialized.
11291 12:13:58.738645 # uc context validated.
11292 12:13:58.738725 # Handled SIG_TRIG
11293 12:13:58.748608 # SIG_OK -- SP:0xFFFFE4BA6AC0 si_addr@:0xffffe4ba6ac0 si_code:2 token@:(nil) offset:-281474519165632
11294 12:13:58.752214 # ==>> completed. PASS(1)
11295 12:13:58.758601 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11296 12:13:58.764904 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11297 12:13:58.768961 # selftests: arm64: mangle_pstate_invalid_daif_bits
11298 12:13:58.827031 # Registered handlers for all signals.
11299 12:13:58.827132 # Detected MINSTKSIGSZ:4720
11300 12:13:58.830266 # Testcase initialized.
11301 12:13:58.834161 # uc context validated.
11302 12:13:58.834242 # Handled SIG_TRIG
11303 12:13:58.843577 # SIG_OK -- SP:0xFFFFF6D03350 si_addr@:0xfffff6d03350 si_code:2 token@:(nil) offset:-281474822583120
11304 12:13:58.846506 # ==>> completed. PASS(1)
11305 12:13:58.853309 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11306 12:13:58.856508 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11307 12:13:58.863273 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11308 12:13:58.934584 # Registered handlers for all signals.
11309 12:13:58.934705 # Detected MINSTKSIGSZ:4720
11310 12:13:58.937712 # Testcase initialized.
11311 12:13:58.941420 # uc context validated.
11312 12:13:58.941501 # Handled SIG_TRIG
11313 12:13:58.951234 # SIG_OK -- SP:0xFFFFCE922090 si_addr@:0xffffce922090 si_code:2 token@:(nil) offset:-281474147426448
11314 12:13:58.954854 # ==>> completed. PASS(1)
11315 12:13:58.961344 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11316 12:13:58.964894 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11317 12:13:58.970939 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11318 12:13:59.015664 # Registered handlers for all signals.
11319 12:13:59.015751 # Detected MINSTKSIGSZ:4720
11320 12:13:59.019148 # Testcase initialized.
11321 12:13:59.022756 # uc context validated.
11322 12:13:59.022837 # Handled SIG_TRIG
11323 12:13:59.032501 # SIG_OK -- SP:0xFFFFE9A81460 si_addr@:0xffffe9a81460 si_code:2 token@:(nil) offset:-281474601849952
11324 12:13:59.036334 # ==>> completed. PASS(1)
11325 12:13:59.042076 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11326 12:13:59.045957 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11327 12:13:59.051965 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11328 12:13:59.104929 # Registered handlers for all signals.
11329 12:13:59.105022 # Detected MINSTKSIGSZ:4720
11330 12:13:59.107939 # Testcase initialized.
11331 12:13:59.111761 # uc context validated.
11332 12:13:59.111846 # Handled SIG_TRIG
11333 12:13:59.121372 # SIG_OK -- SP:0xFFFFC34F6380 si_addr@:0xffffc34f6380 si_code:2 token@:(nil) offset:-281473958503296
11334 12:13:59.124872 # ==>> completed. PASS(1)
11335 12:13:59.131851 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11336 12:13:59.134876 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11337 12:13:59.141138 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11338 12:13:59.201033 # Registered handlers for all signals.
11339 12:13:59.201135 # Detected MINSTKSIGSZ:4720
11340 12:13:59.204215 # Testcase initialized.
11341 12:13:59.208105 # uc context validated.
11342 12:13:59.208185 # Handled SIG_TRIG
11343 12:13:59.217352 # SIG_OK -- SP:0xFFFFDEEB2AC0 si_addr@:0xffffdeeb2ac0 si_code:2 token@:(nil) offset:-281474421697216
11344 12:13:59.220818 # ==>> completed. PASS(1)
11345 12:13:59.227927 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11346 12:13:59.230781 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11347 12:13:59.236890 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11348 12:13:59.297603 # Registered handlers for all signals.
11349 12:13:59.297713 # Detected MINSTKSIGSZ:4720
11350 12:13:59.300941 # Testcase initialized.
11351 12:13:59.304277 # uc context validated.
11352 12:13:59.304358 # Handled SIG_TRIG
11353 12:13:59.313916 # SIG_OK -- SP:0xFFFFD37CBD80 si_addr@:0xffffd37cbd80 si_code:2 token@:(nil) offset:-281474229910912
11354 12:13:59.317527 # ==>> completed. PASS(1)
11355 12:13:59.324114 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11356 12:13:59.327240 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11357 12:13:59.333643 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11358 12:13:59.384703 # Registered handlers for all signals.
11359 12:13:59.384801 # Detected MINSTKSIGSZ:4720
11360 12:13:59.388223 # Testcase initialized.
11361 12:13:59.391425 # uc context validated.
11362 12:13:59.391506 # Handled SIG_TRIG
11363 12:13:59.401196 # SIG_OK -- SP:0xFFFFF7AE2230 si_addr@:0xfffff7ae2230 si_code:2 token@:(nil) offset:-281474837127728
11364 12:13:59.404592 # ==>> completed. PASS(1)
11365 12:13:59.411204 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11366 12:13:59.414497 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11367 12:13:59.417808 # selftests: arm64: sme_trap_no_sm
11368 12:13:59.469842 # Registered handlers for all signals.
11369 12:13:59.469934 # Detected MINSTKSIGSZ:4720
11370 12:13:59.472790 # ==>> completed. SKIP.
11371 12:13:59.482694 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11372 12:13:59.486072 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11373 12:13:59.492627 # selftests: arm64: sme_trap_non_streaming
11374 12:13:59.570898 # Registered handlers for all signals.
11375 12:13:59.571009 # Detected MINSTKSIGSZ:4720
11376 12:13:59.574358 # ==>> completed. SKIP.
11377 12:13:59.584753 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11378 12:13:59.591776 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11379 12:13:59.593877 # selftests: arm64: sme_trap_za
11380 12:13:59.665657 # Registered handlers for all signals.
11381 12:13:59.665769 # Detected MINSTKSIGSZ:4720
11382 12:13:59.668484 # Testcase initialized.
11383 12:13:59.679169 # SIG_OK -- SP:0xFFFFFBEBB6A0 si_addr@:0xaaaadc702510 si_code:1 token@:(nil) offset:-187650819499280
11384 12:13:59.679252 # ==>> completed. PASS(1)
11385 12:13:59.688826 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11386 12:13:59.692275 ok 21 selftests: arm64: sme_trap_za
11387 12:13:59.692352 # selftests: arm64: sme_vl
11388 12:13:59.756337 # Registered handlers for all signals.
11389 12:13:59.756487 # Detected MINSTKSIGSZ:4720
11390 12:13:59.759147 # ==>> completed. SKIP.
11391 12:13:59.765996 # # SME VL :: Check that we get the right SME VL reported
11392 12:13:59.769502 ok 22 selftests: arm64: sme_vl # SKIP
11393 12:13:59.775762 # selftests: arm64: ssve_regs
11394 12:13:59.849298 # Registered handlers for all signals.
11395 12:13:59.849395 # Detected MINSTKSIGSZ:4720
11396 12:13:59.853363 # ==>> completed. SKIP.
11397 12:13:59.862672 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11398 12:13:59.865997 ok 23 selftests: arm64: ssve_regs # SKIP
11399 12:13:59.870306 # selftests: arm64: sve_regs
11400 12:13:59.927984 # Registered handlers for all signals.
11401 12:13:59.928080 # Detected MINSTKSIGSZ:4720
11402 12:13:59.932134 # ==>> completed. SKIP.
11403 12:13:59.938340 # # SVE registers :: Check that we get the right SVE registers reported
11404 12:13:59.941352 ok 24 selftests: arm64: sve_regs # SKIP
11405 12:13:59.947217 # selftests: arm64: sve_vl
11406 12:14:00.013317 # Registered handlers for all signals.
11407 12:14:00.013413 # Detected MINSTKSIGSZ:4720
11408 12:14:00.016113 # ==>> completed. SKIP.
11409 12:14:00.022469 # # SVE VL :: Check that we get the right SVE VL reported
11410 12:14:00.025653 ok 25 selftests: arm64: sve_vl # SKIP
11411 12:14:00.031231 # selftests: arm64: za_no_regs
11412 12:14:00.106543 # Registered handlers for all signals.
11413 12:14:00.106648 # Detected MINSTKSIGSZ:4720
11414 12:14:00.110018 # ==>> completed. SKIP.
11415 12:14:00.116762 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11416 12:14:00.119940 ok 26 selftests: arm64: za_no_regs # SKIP
11417 12:14:00.125614 # selftests: arm64: za_regs
11418 12:14:00.188444 # Registered handlers for all signals.
11419 12:14:00.188542 # Detected MINSTKSIGSZ:4720
11420 12:14:00.190962 # ==>> completed. SKIP.
11421 12:14:00.198234 # # ZA register :: Check that we get the right ZA registers reported
11422 12:14:00.200972 ok 27 selftests: arm64: za_regs # SKIP
11423 12:14:00.205054 # selftests: arm64: pac
11424 12:14:00.259994 # TAP version 13
11425 12:14:00.260087 # 1..7
11426 12:14:00.263275 # # Starting 7 tests from 1 test cases.
11427 12:14:00.267005 # # RUN global.corrupt_pac ...
11428 12:14:00.269843 # # SKIP PAUTH not enabled
11429 12:14:00.273243 # # OK global.corrupt_pac
11430 12:14:00.276439 # ok 1 # SKIP PAUTH not enabled
11431 12:14:00.283370 # # RUN global.pac_instructions_not_nop ...
11432 12:14:00.287021 # # SKIP PAUTH not enabled
11433 12:14:00.289910 # # OK global.pac_instructions_not_nop
11434 12:14:00.293325 # ok 2 # SKIP PAUTH not enabled
11435 12:14:00.299550 # # RUN global.pac_instructions_not_nop_generic ...
11436 12:14:00.302902 # # SKIP Generic PAUTH not enabled
11437 12:14:00.306329 # # OK global.pac_instructions_not_nop_generic
11438 12:14:00.312683 # ok 3 # SKIP Generic PAUTH not enabled
11439 12:14:00.316351 # # RUN global.single_thread_different_keys ...
11440 12:14:00.319548 # # SKIP PAUTH not enabled
11441 12:14:00.326451 # # OK global.single_thread_different_keys
11442 12:14:00.326534 # ok 4 # SKIP PAUTH not enabled
11443 12:14:00.332501 # # RUN global.exec_changed_keys ...
11444 12:14:00.336593 # # SKIP PAUTH not enabled
11445 12:14:00.339111 # # OK global.exec_changed_keys
11446 12:14:00.342660 # ok 5 # SKIP PAUTH not enabled
11447 12:14:00.347176 # # RUN global.context_switch_keep_keys ...
11448 12:14:00.349112 # # SKIP PAUTH not enabled
11449 12:14:00.355688 # # OK global.context_switch_keep_keys
11450 12:14:00.359691 # ok 6 # SKIP PAUTH not enabled
11451 12:14:00.363220 # # RUN global.context_switch_keep_keys_generic ...
11452 12:14:00.366000 # # SKIP Generic PAUTH not enabled
11453 12:14:00.372128 # # OK global.context_switch_keep_keys_generic
11454 12:14:00.375632 # ok 7 # SKIP Generic PAUTH not enabled
11455 12:14:00.378913 # # PASSED: 7 / 7 tests passed.
11456 12:14:00.382291 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11457 12:14:00.385271 ok 28 selftests: arm64: pac
11458 12:14:00.389211 # selftests: arm64: fp-stress
11459 12:14:05.012487 <6>[ 45.939561] vpu: disabling
11460 12:14:05.016008 <6>[ 45.942612] vproc2: disabling
11461 12:14:05.019373 <6>[ 45.946195] vproc1: disabling
11462 12:14:05.022403 <6>[ 45.949480] vaud18: disabling
11463 12:14:05.029021 <6>[ 45.952913] vsram_others: disabling
11464 12:14:05.032301 <6>[ 45.956795] va09: disabling
11465 12:14:05.035531 <6>[ 45.959909] vsram_md: disabling
11466 12:14:05.039681 <6>[ 45.963399] Vgpu: disabling
11467 12:14:10.312567 # TAP version 13
11468 12:14:10.312711 # 1..16
11469 12:14:10.316272 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11470 12:14:10.319477 # # Will run for 10s
11471 12:14:10.319560 # # Started FPSIMD-0-0
11472 12:14:10.322916 # # Started FPSIMD-0-1
11473 12:14:10.326106 # # Started FPSIMD-1-0
11474 12:14:10.326189 # # Started FPSIMD-1-1
11475 12:14:10.329868 # # Started FPSIMD-2-0
11476 12:14:10.329996 # # Started FPSIMD-2-1
11477 12:14:10.332426 # # Started FPSIMD-3-0
11478 12:14:10.335885 # # Started FPSIMD-3-1
11479 12:14:10.335969 # # Started FPSIMD-4-0
11480 12:14:10.339066 # # Started FPSIMD-4-1
11481 12:14:10.342450 # # Started FPSIMD-5-0
11482 12:14:10.342542 # # Started FPSIMD-5-1
11483 12:14:10.345575 # # Started FPSIMD-6-0
11484 12:14:10.345659 # # Started FPSIMD-6-1
11485 12:14:10.349123 # # Started FPSIMD-7-0
11486 12:14:10.352123 # # Started FPSIMD-7-1
11487 12:14:10.355439 # # FPSIMD-0-1: Vector length: 128 bits
11488 12:14:10.359185 # # FPSIMD-0-1: PID: 1157
11489 12:14:10.362177 # # FPSIMD-1-0: Vector length: 128 bits
11490 12:14:10.362275 # # FPSIMD-1-0: PID: 1158
11491 12:14:10.365500 # # FPSIMD-1-1: Vector length: 128 bits
11492 12:14:10.368958 # # FPSIMD-1-1: PID: 1159
11493 12:14:10.372347 # # FPSIMD-3-0: Vector length: 128 bits
11494 12:14:10.375604 # # FPSIMD-3-0: PID: 1162
11495 12:14:10.379018 # # FPSIMD-3-1: Vector length: 128 bits
11496 12:14:10.382405 # # FPSIMD-3-1: PID: 1163
11497 12:14:10.385502 # # FPSIMD-5-0: Vector length: 128 bits
11498 12:14:10.388309 # # FPSIMD-5-0: PID: 1166
11499 12:14:10.391658 # # FPSIMD-5-1: Vector length: 128 bits
11500 12:14:10.391746 # # FPSIMD-5-1: PID: 1167
11501 12:14:10.394967 # # FPSIMD-6-0: Vector length: 128 bits
11502 12:14:10.398561 # # FPSIMD-6-0: PID: 1168
11503 12:14:10.401596 # # FPSIMD-2-1: Vector length: 128 bits
11504 12:14:10.405110 # # FPSIMD-2-1: PID: 1161
11505 12:14:10.408200 # # FPSIMD-0-0: Vector length: 128 bits
11506 12:14:10.411394 # # FPSIMD-0-0: PID: 1156
11507 12:14:10.415104 # # FPSIMD-4-0: Vector length: 128 bits
11508 12:14:10.415220 # # FPSIMD-4-0: PID: 1164
11509 12:14:10.421814 # # FPSIMD-4-1: Vector length: 128 bits
11510 12:14:10.421910 # # FPSIMD-4-1: PID: 1165
11511 12:14:10.424732 # # FPSIMD-6-1: Vector length: 128 bits
11512 12:14:10.428064 # # FPSIMD-6-1: PID: 1169
11513 12:14:10.431244 # # FPSIMD-7-1: Vector length: 128 bits
11514 12:14:10.434961 # # FPSIMD-7-1: PID: 1171
11515 12:14:10.438080 # # FPSIMD-2-0: Vector length: 128 bits
11516 12:14:10.441691 # # FPSIMD-2-0: PID: 1160
11517 12:14:10.444554 # # FPSIMD-7-0: Vector length: 128 bits
11518 12:14:10.444635 # # FPSIMD-7-0: PID: 1170
11519 12:14:10.447887 # # Finishing up...
11520 12:14:10.454169 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1155792, signals=10
11521 12:14:10.461006 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1312290, signals=10
11522 12:14:10.470843 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=1245292, signals=10
11523 12:14:10.477360 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1267490, signals=10
11524 12:14:10.483940 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1226011, signals=10
11525 12:14:10.491258 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1911431, signals=10
11526 12:14:10.497283 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1701913, signals=10
11527 12:14:10.500386 # ok 1 FPSIMD-0-0
11528 12:14:10.500481 # ok 2 FPSIMD-0-1
11529 12:14:10.503693 # ok 3 FPSIMD-1-0
11530 12:14:10.503779 # ok 4 FPSIMD-1-1
11531 12:14:10.507355 # ok 5 FPSIMD-2-0
11532 12:14:10.507490 # ok 6 FPSIMD-2-1
11533 12:14:10.510323 # ok 7 FPSIMD-3-0
11534 12:14:10.510401 # ok 8 FPSIMD-3-1
11535 12:14:10.513648 # ok 9 FPSIMD-4-0
11536 12:14:10.513725 # ok 10 FPSIMD-4-1
11537 12:14:10.516872 # ok 11 FPSIMD-5-0
11538 12:14:10.516946 # ok 12 FPSIMD-5-1
11539 12:14:10.520319 # ok 13 FPSIMD-6-0
11540 12:14:10.520395 # ok 14 FPSIMD-6-1
11541 12:14:10.523444 # ok 15 FPSIMD-7-0
11542 12:14:10.526509 # ok 16 FPSIMD-7-1
11543 12:14:10.534022 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1087211, signals=9
11544 12:14:10.540023 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=998432, signals=10
11545 12:14:10.546323 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=981204, signals=10
11546 12:14:10.552846 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1224148, signals=10
11547 12:14:10.559814 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1439734, signals=10
11548 12:14:10.569263 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1161800, signals=10
11549 12:14:10.576156 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1264081, signals=9
11550 12:14:10.582973 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1086996, signals=9
11551 12:14:10.589058 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1411819, signals=10
11552 12:14:10.595553 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11553 12:14:10.598985 ok 29 selftests: arm64: fp-stress
11554 12:14:10.599081 # selftests: arm64: sve-ptrace
11555 12:14:10.602262 # TAP version 13
11556 12:14:10.602351 # 1..4104
11557 12:14:10.605906 # ok 2 # SKIP SVE not available
11558 12:14:10.609162 # # Planned tests != run tests (4104 != 1)
11559 12:14:10.615615 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11560 12:14:10.618804 ok 30 selftests: arm64: sve-ptrace # SKIP
11561 12:14:10.622228 # selftests: arm64: sve-probe-vls
11562 12:14:10.622318 # TAP version 13
11563 12:14:10.622385 # 1..2
11564 12:14:10.625797 # ok 2 # SKIP SVE not available
11565 12:14:10.628847 # # Planned tests != run tests (2 != 1)
11566 12:14:10.635304 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11567 12:14:10.638712 ok 31 selftests: arm64: sve-probe-vls # SKIP
11568 12:14:10.642655 # selftests: arm64: vec-syscfg
11569 12:14:10.642756 # TAP version 13
11570 12:14:10.645288 # 1..20
11571 12:14:10.648774 # ok 1 # SKIP SVE not supported
11572 12:14:10.648864 # ok 2 # SKIP SVE not supported
11573 12:14:10.652161 # ok 3 # SKIP SVE not supported
11574 12:14:10.654899 # ok 4 # SKIP SVE not supported
11575 12:14:10.658697 # ok 5 # SKIP SVE not supported
11576 12:14:10.661765 # ok 6 # SKIP SVE not supported
11577 12:14:10.665083 # ok 7 # SKIP SVE not supported
11578 12:14:10.668171 # ok 8 # SKIP SVE not supported
11579 12:14:10.671693 # ok 9 # SKIP SVE not supported
11580 12:14:10.671799 # ok 10 # SKIP SVE not supported
11581 12:14:10.675141 # ok 11 # SKIP SME not supported
11582 12:14:10.678583 # ok 12 # SKIP SME not supported
11583 12:14:10.681431 # ok 13 # SKIP SME not supported
11584 12:14:10.684994 # ok 14 # SKIP SME not supported
11585 12:14:10.688087 # ok 15 # SKIP SME not supported
11586 12:14:10.691557 # ok 16 # SKIP SME not supported
11587 12:14:10.695206 # ok 17 # SKIP SME not supported
11588 12:14:10.698042 # ok 18 # SKIP SME not supported
11589 12:14:10.698130 # ok 19 # SKIP SME not supported
11590 12:14:10.701414 # ok 20 # SKIP SME not supported
11591 12:14:10.707636 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11592 12:14:10.711337 ok 32 selftests: arm64: vec-syscfg
11593 12:14:10.714404 # selftests: arm64: za-fork
11594 12:14:10.714494 # TAP version 13
11595 12:14:10.714560 # 1..1
11596 12:14:10.717823 # # PID: 1245
11597 12:14:10.717940 # # SME support not present
11598 12:14:10.721075 # ok 0 skipped
11599 12:14:10.724308 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11600 12:14:10.727352 ok 33 selftests: arm64: za-fork
11601 12:14:10.730875 # selftests: arm64: za-ptrace
11602 12:14:10.734394 # TAP version 13
11603 12:14:10.734490 # 1..1
11604 12:14:10.737744 # ok 2 # SKIP SME not available
11605 12:14:10.741029 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11606 12:14:10.743997 ok 34 selftests: arm64: za-ptrace # SKIP
11607 12:14:10.747483 # selftests: arm64: check_buffer_fill
11608 12:14:10.795188 # # SKIP: MTE features unavailable
11609 12:14:10.804778 ok 35 selftests: arm64: check_buffer_fill # SKIP
11610 12:14:10.821117 # selftests: arm64: check_child_memory
11611 12:14:10.881767 # # SKIP: MTE features unavailable
11612 12:14:10.889825 ok 36 selftests: arm64: check_child_memory # SKIP
11613 12:14:10.906782 # selftests: arm64: check_gcr_el1_cswitch
11614 12:14:10.947969 # # SKIP: MTE features unavailable
11615 12:14:10.955001 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11616 12:14:10.972815 # selftests: arm64: check_ksm_options
11617 12:14:11.021589 # # SKIP: MTE features unavailable
11618 12:14:11.028955 ok 38 selftests: arm64: check_ksm_options # SKIP
11619 12:14:11.046480 # selftests: arm64: check_mmap_options
11620 12:14:11.103844 # # SKIP: MTE features unavailable
11621 12:14:11.110310 ok 39 selftests: arm64: check_mmap_options # SKIP
11622 12:14:11.123010 # selftests: arm64: check_prctl
11623 12:14:11.182186 # TAP version 13
11624 12:14:11.182327 # 1..5
11625 12:14:11.185787 # ok 1 check_basic_read
11626 12:14:11.185875 # ok 2 NONE
11627 12:14:11.188843 # ok 3 # SKIP SYNC
11628 12:14:11.188929 # ok 4 # SKIP ASYNC
11629 12:14:11.192519 # ok 5 # SKIP SYNC+ASYNC
11630 12:14:11.195615 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11631 12:14:11.198973 ok 40 selftests: arm64: check_prctl
11632 12:14:11.206294 # selftests: arm64: check_tags_inclusion
11633 12:14:11.268888 # # SKIP: MTE features unavailable
11634 12:14:11.276749 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11635 12:14:11.289316 # selftests: arm64: check_user_mem
11636 12:14:11.367596 # # SKIP: MTE features unavailable
11637 12:14:11.375199 ok 42 selftests: arm64: check_user_mem # SKIP
11638 12:14:11.388333 # selftests: arm64: btitest
11639 12:14:11.444775 # TAP version 13
11640 12:14:11.444916 # 1..18
11641 12:14:11.447949 # # HWCAP_PACA not present
11642 12:14:11.452016 # # HWCAP2_BTI not present
11643 12:14:11.452106 # # Test binary built for BTI
11644 12:14:11.458173 # ok 1 nohint_func/call_using_br_x0 # SKIP
11645 12:14:11.461099 # ok 1 nohint_func/call_using_br_x16 # SKIP
11646 12:14:11.464457 # ok 1 nohint_func/call_using_blr # SKIP
11647 12:14:11.468112 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11648 12:14:11.471290 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11649 12:14:11.475072 # ok 1 bti_none_func/call_using_blr # SKIP
11650 12:14:11.482016 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11651 12:14:11.484837 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11652 12:14:11.487804 # ok 1 bti_c_func/call_using_blr # SKIP
11653 12:14:11.491327 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11654 12:14:11.494671 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11655 12:14:11.498388 # ok 1 bti_j_func/call_using_blr # SKIP
11656 12:14:11.501024 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11657 12:14:11.507810 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11658 12:14:11.511062 # ok 1 bti_jc_func/call_using_blr # SKIP
11659 12:14:11.514159 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11660 12:14:11.517441 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11661 12:14:11.521201 # ok 1 paciasp_func/call_using_blr # SKIP
11662 12:14:11.527344 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11663 12:14:11.531058 # # WARNING - EXPECTED TEST COUNT WRONG
11664 12:14:11.533757 ok 43 selftests: arm64: btitest
11665 12:14:11.537159 # selftests: arm64: nobtitest
11666 12:14:11.537250 # TAP version 13
11667 12:14:11.537326 # 1..18
11668 12:14:11.540468 # # HWCAP_PACA not present
11669 12:14:11.543896 # # HWCAP2_BTI not present
11670 12:14:11.546993 # # Test binary not built for BTI
11671 12:14:11.550491 # ok 1 nohint_func/call_using_br_x0 # SKIP
11672 12:14:11.553961 # ok 1 nohint_func/call_using_br_x16 # SKIP
11673 12:14:11.556923 # ok 1 nohint_func/call_using_blr # SKIP
11674 12:14:11.560526 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11675 12:14:11.566766 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11676 12:14:11.570289 # ok 1 bti_none_func/call_using_blr # SKIP
11677 12:14:11.573727 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11678 12:14:11.577470 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11679 12:14:11.580224 # ok 1 bti_c_func/call_using_blr # SKIP
11680 12:14:11.583422 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11681 12:14:11.586986 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11682 12:14:11.590372 # ok 1 bti_j_func/call_using_blr # SKIP
11683 12:14:11.597116 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11684 12:14:11.599922 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11685 12:14:11.602936 # ok 1 bti_jc_func/call_using_blr # SKIP
11686 12:14:11.606637 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11687 12:14:11.609810 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11688 12:14:11.613151 # ok 1 paciasp_func/call_using_blr # SKIP
11689 12:14:11.619684 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11690 12:14:11.623316 # # WARNING - EXPECTED TEST COUNT WRONG
11691 12:14:11.626331 ok 44 selftests: arm64: nobtitest
11692 12:14:11.629674 # selftests: arm64: hwcap
11693 12:14:11.629766 # TAP version 13
11694 12:14:11.629832 # 1..28
11695 12:14:11.633298 # ok 1 cpuinfo_match_RNG
11696 12:14:11.636633 # # SIGILL reported for RNG
11697 12:14:11.639815 # ok 2 # SKIP sigill_RNG
11698 12:14:11.639906 # ok 3 cpuinfo_match_SME
11699 12:14:11.642801 # ok 4 sigill_SME
11700 12:14:11.642897 # ok 5 cpuinfo_match_SVE
11701 12:14:11.646115 # ok 6 sigill_SVE
11702 12:14:11.649436 # ok 7 cpuinfo_match_SVE 2
11703 12:14:11.649541 # # SIGILL reported for SVE 2
11704 12:14:11.652943 # ok 8 # SKIP sigill_SVE 2
11705 12:14:11.656218 # ok 9 cpuinfo_match_SVE AES
11706 12:14:11.659084 # # SIGILL reported for SVE AES
11707 12:14:11.662687 # ok 10 # SKIP sigill_SVE AES
11708 12:14:11.665689 # ok 11 cpuinfo_match_SVE2 PMULL
11709 12:14:11.669582 # # SIGILL reported for SVE2 PMULL
11710 12:14:11.669690 # ok 12 # SKIP sigill_SVE2 PMULL
11711 12:14:11.672280 # ok 13 cpuinfo_match_SVE2 BITPERM
11712 12:14:11.675518 # # SIGILL reported for SVE2 BITPERM
11713 12:14:11.678861 # ok 14 # SKIP sigill_SVE2 BITPERM
11714 12:14:11.682465 # ok 15 cpuinfo_match_SVE2 SHA3
11715 12:14:11.685362 # # SIGILL reported for SVE2 SHA3
11716 12:14:11.688510 # ok 16 # SKIP sigill_SVE2 SHA3
11717 12:14:11.692379 # ok 17 cpuinfo_match_SVE2 SM4
11718 12:14:11.695596 # # SIGILL reported for SVE2 SM4
11719 12:14:11.698884 # ok 18 # SKIP sigill_SVE2 SM4
11720 12:14:11.698990 # ok 19 cpuinfo_match_SVE2 I8MM
11721 12:14:11.701879 # # SIGILL reported for SVE2 I8MM
11722 12:14:11.705340 # ok 20 # SKIP sigill_SVE2 I8MM
11723 12:14:11.708610 # ok 21 cpuinfo_match_SVE2 F32MM
11724 12:14:11.711984 # # SIGILL reported for SVE2 F32MM
11725 12:14:11.715268 # ok 22 # SKIP sigill_SVE2 F32MM
11726 12:14:11.718121 # ok 23 cpuinfo_match_SVE2 F64MM
11727 12:14:11.721654 # # SIGILL reported for SVE2 F64MM
11728 12:14:11.725147 # ok 24 # SKIP sigill_SVE2 F64MM
11729 12:14:11.728238 # ok 25 cpuinfo_match_SVE2 BF16
11730 12:14:11.728343 # # SIGILL reported for SVE2 BF16
11731 12:14:11.732016 # ok 26 # SKIP sigill_SVE2 BF16
11732 12:14:11.734889 # ok 27 cpuinfo_match_SVE2 EBF16
11733 12:14:11.738360 # ok 28 # SKIP sigill_SVE2 EBF16
11734 12:14:11.745016 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11735 12:14:11.747968 ok 45 selftests: arm64: hwcap
11736 12:14:11.748062 # selftests: arm64: ptrace
11737 12:14:11.751557 # TAP version 13
11738 12:14:11.751651 # 1..7
11739 12:14:11.755631 # # Parent is 1487, child is 1488
11740 12:14:11.755720 # ok 1 read_tpidr_one
11741 12:14:11.757988 # ok 2 write_tpidr_one
11742 12:14:11.761489 # ok 3 verify_tpidr_one
11743 12:14:11.761576 # ok 4 count_tpidrs
11744 12:14:11.764809 # ok 5 tpidr2_write
11745 12:14:11.764899 # ok 6 tpidr2_read
11746 12:14:11.767805 # ok 7 write_tpidr_only
11747 12:14:11.774502 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11748 12:14:11.774608 ok 46 selftests: arm64: ptrace
11749 12:14:11.777865 # selftests: arm64: syscall-abi
11750 12:14:11.781011 # TAP version 13
11751 12:14:11.781102 # 1..2
11752 12:14:11.784497 # ok 1 getpid() FPSIMD
11753 12:14:11.784589 # ok 2 sched_yield() FPSIMD
11754 12:14:11.790987 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11755 12:14:11.793998 ok 47 selftests: arm64: syscall-abi
11756 12:14:11.797522 # selftests: arm64: tpidr2
11757 12:14:11.834237 # TAP version 13
11758 12:14:11.834376 # 1..5
11759 12:14:11.837707 # # PID: 1524
11760 12:14:11.837801 # # SME support not present
11761 12:14:11.840781 # ok 0 skipped, TPIDR2 not supported
11762 12:14:11.844320 # ok 1 skipped, TPIDR2 not supported
11763 12:14:11.847460 # ok 2 skipped, TPIDR2 not supported
11764 12:14:11.850769 # ok 3 skipped, TPIDR2 not supported
11765 12:14:11.854576 # ok 4 skipped, TPIDR2 not supported
11766 12:14:11.860601 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11767 12:14:11.864055 ok 48 selftests: arm64: tpidr2
11768 12:14:12.520379 arm64_tags_test pass
11769 12:14:12.523672 arm64_run_tags_test_sh pass
11770 12:14:12.527060 arm64_fake_sigreturn_bad_magic pass
11771 12:14:12.530233 arm64_fake_sigreturn_bad_size pass
11772 12:14:12.533684 arm64_fake_sigreturn_bad_size_for_magic0 pass
11773 12:14:12.538023 arm64_fake_sigreturn_duplicated_fpsimd pass
11774 12:14:12.540468 arm64_fake_sigreturn_misaligned_sp pass
11775 12:14:12.544261 arm64_fake_sigreturn_missing_fpsimd pass
11776 12:14:12.546941 arm64_fake_sigreturn_sme_change_vl skip
11777 12:14:12.550026 arm64_fake_sigreturn_sve_change_vl skip
11778 12:14:12.556758 arm64_mangle_pstate_invalid_compat_toggle pass
11779 12:14:12.560444 arm64_mangle_pstate_invalid_daif_bits pass
11780 12:14:12.563630 arm64_mangle_pstate_invalid_mode_el1h pass
11781 12:14:12.566580 arm64_mangle_pstate_invalid_mode_el1t pass
11782 12:14:12.569858 arm64_mangle_pstate_invalid_mode_el2h pass
11783 12:14:12.576747 arm64_mangle_pstate_invalid_mode_el2t pass
11784 12:14:12.580162 arm64_mangle_pstate_invalid_mode_el3h pass
11785 12:14:12.583321 arm64_mangle_pstate_invalid_mode_el3t pass
11786 12:14:12.586515 arm64_sme_trap_no_sm skip
11787 12:14:12.586607 arm64_sme_trap_non_streaming skip
11788 12:14:12.589703 arm64_sme_trap_za pass
11789 12:14:12.593053 arm64_sme_vl skip
11790 12:14:12.593140 arm64_ssve_regs skip
11791 12:14:12.596435 arm64_sve_regs skip
11792 12:14:12.596519 arm64_sve_vl skip
11793 12:14:12.599663 arm64_za_no_regs skip
11794 12:14:12.599749 arm64_za_regs skip
11795 12:14:12.602849 arm64_pac_pauth_not_enabled skip
11796 12:14:12.606660 arm64_pac_pauth_not_enabled skip
11797 12:14:12.609983 arm64_pac_generic_pauth_not_enabled skip
11798 12:14:12.612880 arm64_pac_pauth_not_enabled skip
11799 12:14:12.616116 arm64_pac_pauth_not_enabled skip
11800 12:14:12.619660 arm64_pac_pauth_not_enabled skip
11801 12:14:12.622760 arm64_pac_generic_pauth_not_enabled skip
11802 12:14:12.622871 arm64_pac pass
11803 12:14:12.626752 arm64_fp-stress_FPSIMD-0-0 pass
11804 12:14:12.629357 arm64_fp-stress_FPSIMD-0-1 pass
11805 12:14:12.632786 arm64_fp-stress_FPSIMD-1-0 pass
11806 12:14:12.636004 arm64_fp-stress_FPSIMD-1-1 pass
11807 12:14:12.639298 arm64_fp-stress_FPSIMD-2-0 pass
11808 12:14:12.642560 arm64_fp-stress_FPSIMD-2-1 pass
11809 12:14:12.645997 arm64_fp-stress_FPSIMD-3-0 pass
11810 12:14:12.646084 arm64_fp-stress_FPSIMD-3-1 pass
11811 12:14:12.650257 arm64_fp-stress_FPSIMD-4-0 pass
11812 12:14:12.652836 arm64_fp-stress_FPSIMD-4-1 pass
11813 12:14:12.656019 arm64_fp-stress_FPSIMD-5-0 pass
11814 12:14:12.659035 arm64_fp-stress_FPSIMD-5-1 pass
11815 12:14:12.662467 arm64_fp-stress_FPSIMD-6-0 pass
11816 12:14:12.665598 arm64_fp-stress_FPSIMD-6-1 pass
11817 12:14:12.668909 arm64_fp-stress_FPSIMD-7-0 pass
11818 12:14:12.669001 arm64_fp-stress_FPSIMD-7-1 pass
11819 12:14:12.672384 arm64_fp-stress pass
11820 12:14:12.675278 arm64_sve-ptrace_sve_not_available skip
11821 12:14:12.678814 arm64_sve-ptrace skip
11822 12:14:12.681952 arm64_sve-probe-vls_sve_not_available skip
11823 12:14:12.685388 arm64_sve-probe-vls skip
11824 12:14:12.688762 arm64_vec-syscfg_sve_not_supported skip
11825 12:14:12.691771 arm64_vec-syscfg_sve_not_supported skip
11826 12:14:12.694968 arm64_vec-syscfg_sve_not_supported skip
11827 12:14:12.698264 arm64_vec-syscfg_sve_not_supported skip
11828 12:14:12.701751 arm64_vec-syscfg_sve_not_supported skip
11829 12:14:12.705294 arm64_vec-syscfg_sve_not_supported skip
11830 12:14:12.708116 arm64_vec-syscfg_sve_not_supported skip
11831 12:14:12.711779 arm64_vec-syscfg_sve_not_supported skip
11832 12:14:12.714718 arm64_vec-syscfg_sve_not_supported skip
11833 12:14:12.718526 arm64_vec-syscfg_sve_not_supported skip
11834 12:14:12.721785 arm64_vec-syscfg_sme_not_supported skip
11835 12:14:12.724886 arm64_vec-syscfg_sme_not_supported skip
11836 12:14:12.731310 arm64_vec-syscfg_sme_not_supported skip
11837 12:14:12.734929 arm64_vec-syscfg_sme_not_supported skip
11838 12:14:12.737901 arm64_vec-syscfg_sme_not_supported skip
11839 12:14:12.741041 arm64_vec-syscfg_sme_not_supported skip
11840 12:14:12.745064 arm64_vec-syscfg_sme_not_supported skip
11841 12:14:12.748426 arm64_vec-syscfg_sme_not_supported skip
11842 12:14:12.751345 arm64_vec-syscfg_sme_not_supported skip
11843 12:14:12.754734 arm64_vec-syscfg_sme_not_supported skip
11844 12:14:12.757832 arm64_vec-syscfg pass
11845 12:14:12.757948 arm64_za-fork_skipped pass
11846 12:14:12.761126 arm64_za-fork pass
11847 12:14:12.764425 arm64_za-ptrace_sme_not_available skip
11848 12:14:12.767407 arm64_za-ptrace skip
11849 12:14:12.767499 arm64_check_buffer_fill skip
11850 12:14:12.771038 arm64_check_child_memory skip
11851 12:14:12.774074 arm64_check_gcr_el1_cswitch skip
11852 12:14:12.777775 arm64_check_ksm_options skip
11853 12:14:12.780866 arm64_check_mmap_options skip
11854 12:14:12.784209 arm64_check_prctl_check_basic_read pass
11855 12:14:12.788378 arm64_check_prctl_NONE pass
11856 12:14:12.788495 arm64_check_prctl_sync skip
11857 12:14:12.790487 arm64_check_prctl_async skip
11858 12:14:12.794133 arm64_check_prctl_sync_async skip
11859 12:14:12.797192 arm64_check_prctl pass
11860 12:14:12.800725 arm64_check_tags_inclusion skip
11861 12:14:12.800815 arm64_check_user_mem skip
11862 12:14:12.807247 arm64_btitest_nohint_func_call_using_br_x0 skip
11863 12:14:12.810319 arm64_btitest_nohint_func_call_using_br_x16 skip
11864 12:14:12.813615 arm64_btitest_nohint_func_call_using_blr skip
11865 12:14:12.816820 arm64_btitest_bti_none_func_call_using_br_x0 skip
11866 12:14:12.823465 arm64_btitest_bti_none_func_call_using_br_x16 skip
11867 12:14:12.827730 arm64_btitest_bti_none_func_call_using_blr skip
11868 12:14:12.831055 arm64_btitest_bti_c_func_call_using_br_x0 skip
11869 12:14:12.836596 arm64_btitest_bti_c_func_call_using_br_x16 skip
11870 12:14:12.840228 arm64_btitest_bti_c_func_call_using_blr skip
11871 12:14:12.843548 arm64_btitest_bti_j_func_call_using_br_x0 skip
11872 12:14:12.846610 arm64_btitest_bti_j_func_call_using_br_x16 skip
11873 12:14:12.853519 arm64_btitest_bti_j_func_call_using_blr skip
11874 12:14:12.856499 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11875 12:14:12.860152 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11876 12:14:12.866466 arm64_btitest_bti_jc_func_call_using_blr skip
11877 12:14:12.869852 arm64_btitest_paciasp_func_call_using_br_x0 skip
11878 12:14:12.872972 arm64_btitest_paciasp_func_call_using_br_x16 skip
11879 12:14:12.876054 arm64_btitest_paciasp_func_call_using_blr skip
11880 12:14:12.880320 arm64_btitest pass
11881 12:14:12.882954 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11882 12:14:12.890765 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11883 12:14:12.892661 arm64_nobtitest_nohint_func_call_using_blr skip
11884 12:14:12.896299 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11885 12:14:12.902644 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11886 12:14:12.905978 arm64_nobtitest_bti_none_func_call_using_blr skip
11887 12:14:12.909378 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11888 12:14:12.916178 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11889 12:14:12.919237 arm64_nobtitest_bti_c_func_call_using_blr skip
11890 12:14:12.922637 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11891 12:14:12.930164 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11892 12:14:12.932541 arm64_nobtitest_bti_j_func_call_using_blr skip
11893 12:14:12.935560 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11894 12:14:12.942244 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11895 12:14:12.945806 arm64_nobtitest_bti_jc_func_call_using_blr skip
11896 12:14:12.948575 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11897 12:14:12.955655 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11898 12:14:12.958657 arm64_nobtitest_paciasp_func_call_using_blr skip
11899 12:14:12.961701 arm64_nobtitest pass
11900 12:14:12.965390 arm64_hwcap_cpuinfo_match_RNG pass
11901 12:14:12.965483 arm64_hwcap_sigill_rng skip
11902 12:14:12.968966 arm64_hwcap_cpuinfo_match_SME pass
11903 12:14:12.971900 arm64_hwcap_sigill_SME pass
11904 12:14:12.975768 arm64_hwcap_cpuinfo_match_SVE pass
11905 12:14:12.978603 arm64_hwcap_sigill_SVE pass
11906 12:14:12.981663 arm64_hwcap_cpuinfo_match_SVE_2 pass
11907 12:14:12.984848 arm64_hwcap_sigill_sve_2 skip
11908 12:14:12.988816 arm64_hwcap_cpuinfo_match_SVE_AES pass
11909 12:14:12.988911 arm64_hwcap_sigill_sve_aes skip
11910 12:14:12.995081 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11911 12:14:12.998182 arm64_hwcap_sigill_sve2_pmull skip
11912 12:14:13.001438 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11913 12:14:13.004892 arm64_hwcap_sigill_sve2_bitperm skip
11914 12:14:13.007961 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11915 12:14:13.011529 arm64_hwcap_sigill_sve2_sha3 skip
11916 12:14:13.015345 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11917 12:14:13.018194 arm64_hwcap_sigill_sve2_sm4 skip
11918 12:14:13.021740 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11919 12:14:13.025903 arm64_hwcap_sigill_sve2_i8mm skip
11920 12:14:13.028007 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11921 12:14:13.031146 arm64_hwcap_sigill_sve2_f32mm skip
11922 12:14:13.034348 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11923 12:14:13.038214 arm64_hwcap_sigill_sve2_f64mm skip
11924 12:14:13.041777 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11925 12:14:13.044396 arm64_hwcap_sigill_sve2_bf16 skip
11926 12:14:13.048051 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11927 12:14:13.051158 arm64_hwcap_sigill_sve2_ebf16 skip
11928 12:14:13.054446 arm64_hwcap pass
11929 12:14:13.054538 arm64_ptrace_read_tpidr_one pass
11930 12:14:13.057583 arm64_ptrace_write_tpidr_one pass
11931 12:14:13.060976 arm64_ptrace_verify_tpidr_one pass
11932 12:14:13.064883 arm64_ptrace_count_tpidrs pass
11933 12:14:13.067630 arm64_ptrace_tpidr2_write pass
11934 12:14:13.070606 arm64_ptrace_tpidr2_read pass
11935 12:14:13.074191 arm64_ptrace_write_tpidr_only pass
11936 12:14:13.074285 arm64_ptrace pass
11937 12:14:13.077181 arm64_syscall-abi_getpid_FPSIMD pass
11938 12:14:13.080502 arm64_syscall-abi_sched_yield_FPSIMD pass
11939 12:14:13.084462 arm64_syscall-abi pass
11940 12:14:13.087483 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11941 12:14:13.094213 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11942 12:14:13.097147 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11943 12:14:13.100329 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11944 12:14:13.104490 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11945 12:14:13.107065 arm64_tpidr2 pass
11946 12:14:13.110611 + ../../utils/send-to-lava.sh ./output/result.txt
11947 12:14:13.116648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11948 12:14:13.116975 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
11950 12:14:13.123772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11951 12:14:13.124040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11953 12:14:13.127072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11954 12:14:13.127321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11956 12:14:13.147750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11957 12:14:13.148055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11959 12:14:13.211117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11960 12:14:13.211389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11962 12:14:13.267222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11963 12:14:13.267526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11965 12:14:13.332052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11966 12:14:13.332369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
11968 12:14:13.396228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
11969 12:14:13.396555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
11971 12:14:13.460927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
11972 12:14:13.461236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
11974 12:14:13.526605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
11975 12:14:13.526930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
11977 12:14:13.593682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
11978 12:14:13.594013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
11980 12:14:13.663801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
11981 12:14:13.664130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
11983 12:14:13.734466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
11984 12:14:13.734788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
11986 12:14:13.804266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
11987 12:14:13.804575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
11989 12:14:13.866349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
11990 12:14:13.866679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
11992 12:14:13.936253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
11993 12:14:13.936579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
11995 12:14:13.998943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
11996 12:14:13.999274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
11998 12:14:14.063136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
11999 12:14:14.063456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12001 12:14:14.132912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12002 12:14:14.133238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12004 12:14:14.195265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12005 12:14:14.195647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12007 12:14:14.263063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12009 12:14:14.266140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12010 12:14:14.327213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12011 12:14:14.327573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12013 12:14:14.391779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12014 12:14:14.392101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12016 12:14:14.459951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12017 12:14:14.460276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12019 12:14:14.522764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12020 12:14:14.523095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12022 12:14:14.589221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12023 12:14:14.589546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12025 12:14:14.657138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12026 12:14:14.657458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12028 12:14:14.723918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12029 12:14:14.724240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12031 12:14:14.788312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12033 12:14:14.791099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12034 12:14:14.852843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12035 12:14:14.853168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12037 12:14:14.922630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12038 12:14:14.922963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12040 12:14:14.985222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12041 12:14:14.985552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12043 12:14:15.047339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12045 12:14:15.050928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12046 12:14:15.113825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12048 12:14:15.117180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12049 12:14:15.183132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12050 12:14:15.183462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12052 12:14:15.247171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12053 12:14:15.247522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12055 12:14:15.317602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12056 12:14:15.317929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12058 12:14:15.386825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12059 12:14:15.387153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12061 12:14:15.454681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12062 12:14:15.455017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12064 12:14:15.522980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12065 12:14:15.523311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12067 12:14:15.587334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12068 12:14:15.587684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12070 12:14:15.651419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12071 12:14:15.651745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12073 12:14:15.716051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12074 12:14:15.716371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12076 12:14:15.784153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12077 12:14:15.784484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12079 12:14:15.847736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12080 12:14:15.848064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12082 12:14:15.912971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12083 12:14:15.913297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12085 12:14:15.978624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12086 12:14:15.979058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12088 12:14:16.041267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12089 12:14:16.041600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12091 12:14:16.101866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12092 12:14:16.102196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12094 12:14:16.167249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12095 12:14:16.167632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12097 12:14:16.233051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12098 12:14:16.233379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12100 12:14:16.302161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12101 12:14:16.302489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12103 12:14:16.368277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12104 12:14:16.368576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12106 12:14:16.438661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip>
12107 12:14:16.438971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip
12109 12:14:16.498037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12110 12:14:16.498353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12112 12:14:16.567621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip>
12113 12:14:16.567939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip
12115 12:14:16.625483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12116 12:14:16.625782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12118 12:14:16.689834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12119 12:14:16.690157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12121 12:14:16.756778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12122 12:14:16.757100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12124 12:14:16.823131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12125 12:14:16.823457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12127 12:14:16.880109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12128 12:14:16.880438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12130 12:14:16.941254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12131 12:14:16.941583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12133 12:14:17.006928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12134 12:14:17.007255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12136 12:14:17.073870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12137 12:14:17.074195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12139 12:14:17.130440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12140 12:14:17.130813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12142 12:14:17.195675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12143 12:14:17.195999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12145 12:14:17.259703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12146 12:14:17.260029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12148 12:14:17.326683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12149 12:14:17.327008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12151 12:14:17.389989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12152 12:14:17.390332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12154 12:14:17.455392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12155 12:14:17.455731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12157 12:14:17.520363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12158 12:14:17.520691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12160 12:14:17.582278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12161 12:14:17.582607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12163 12:14:17.645802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12164 12:14:17.646127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12166 12:14:17.712196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12167 12:14:17.712517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12169 12:14:17.776970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12170 12:14:17.777289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12172 12:14:17.841900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12173 12:14:17.842222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12175 12:14:17.904642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12176 12:14:17.904967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12178 12:14:17.960856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12179 12:14:17.961184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12181 12:14:18.028573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12182 12:14:18.028920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12184 12:14:18.097560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12185 12:14:18.097889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12187 12:14:18.169495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip>
12188 12:14:18.169821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip
12190 12:14:18.236700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12191 12:14:18.237031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12193 12:14:18.308028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12194 12:14:18.308360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12196 12:14:18.372183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12197 12:14:18.372536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12199 12:14:18.437265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12201 12:14:18.440135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12202 12:14:18.498521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12203 12:14:18.498883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12205 12:14:18.561853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12206 12:14:18.562183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12208 12:14:18.629992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12209 12:14:18.630318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12211 12:14:18.691681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12212 12:14:18.692009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12214 12:14:18.762390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip>
12215 12:14:18.762718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip
12217 12:14:18.831974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_async RESULT=skip>
12218 12:14:18.832305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_async RESULT=skip
12220 12:14:18.901600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip
12222 12:14:18.904849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip>
12223 12:14:18.963539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12224 12:14:18.963857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12226 12:14:19.026941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12227 12:14:19.027263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12229 12:14:19.092966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12230 12:14:19.093289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12232 12:14:19.162127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12233 12:14:19.162448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12235 12:14:19.228075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12236 12:14:19.228402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12238 12:14:19.295499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12239 12:14:19.295852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12241 12:14:19.367287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12242 12:14:19.367666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12244 12:14:19.430537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12245 12:14:19.430858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12247 12:14:19.501014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12248 12:14:19.501332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12250 12:14:19.571828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12251 12:14:19.572150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12253 12:14:19.641509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12254 12:14:19.641836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12256 12:14:19.709462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12257 12:14:19.709786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12259 12:14:19.776670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12260 12:14:19.776990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12262 12:14:19.844548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12263 12:14:19.844862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12265 12:14:19.910740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12266 12:14:19.911052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12268 12:14:19.974672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12269 12:14:19.974996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12271 12:14:20.040298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12272 12:14:20.040684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12274 12:14:20.093585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12275 12:14:20.093898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12277 12:14:20.155291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12278 12:14:20.155635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12280 12:14:20.220801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12281 12:14:20.221122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12283 12:14:20.287328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12284 12:14:20.287671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12286 12:14:20.353387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12287 12:14:20.353729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12289 12:14:20.420325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12290 12:14:20.420652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12292 12:14:20.480591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12293 12:14:20.480924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12295 12:14:20.542171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12296 12:14:20.542499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12298 12:14:20.608784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12299 12:14:20.609098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12301 12:14:20.672582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12302 12:14:20.672902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12304 12:14:20.738630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12305 12:14:20.738951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12307 12:14:20.805433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12308 12:14:20.805745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12310 12:14:20.876774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12311 12:14:20.877103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12313 12:14:20.934309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12314 12:14:20.934634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12316 12:14:20.993585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12317 12:14:20.993915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12319 12:14:21.058254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12320 12:14:21.058581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12322 12:14:21.114035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12323 12:14:21.114362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12325 12:14:21.183018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12326 12:14:21.183342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12328 12:14:21.238034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12329 12:14:21.238350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12331 12:14:21.301431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12332 12:14:21.301759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12334 12:14:21.365082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12335 12:14:21.365410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12337 12:14:21.430295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12338 12:14:21.430619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12340 12:14:21.495927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12341 12:14:21.496237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12343 12:14:21.557115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12344 12:14:21.557438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12346 12:14:21.627742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12347 12:14:21.628068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12349 12:14:21.685959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip>
12350 12:14:21.686274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip
12352 12:14:21.758688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12353 12:14:21.759013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12355 12:14:21.821417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12356 12:14:21.821724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12358 12:14:21.889971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12359 12:14:21.890289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12361 12:14:21.950001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12362 12:14:21.950315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12364 12:14:22.008481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12365 12:14:22.008800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12367 12:14:22.073742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip>
12368 12:14:22.074360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip
12370 12:14:22.155247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12371 12:14:22.155620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12373 12:14:22.207310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip>
12374 12:14:22.207674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip
12376 12:14:22.280281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12377 12:14:22.280597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12379 12:14:22.335932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip>
12380 12:14:22.336243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip
12382 12:14:22.396546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12383 12:14:22.396864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12385 12:14:22.460326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip>
12386 12:14:22.460642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip
12388 12:14:22.515897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12389 12:14:22.516210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12391 12:14:22.574387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip
12393 12:14:22.577506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip>
12394 12:14:22.646357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12395 12:14:22.647015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12397 12:14:22.721948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip
12399 12:14:22.725441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip>
12400 12:14:22.806499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12401 12:14:22.807238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12403 12:14:22.887011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip
12405 12:14:22.889762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip>
12406 12:14:22.972194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12407 12:14:22.972904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12409 12:14:23.045339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip
12411 12:14:23.048055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip>
12412 12:14:23.128795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12413 12:14:23.129561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12415 12:14:23.208082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip>
12416 12:14:23.208925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip
12418 12:14:23.293992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12419 12:14:23.294769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12421 12:14:23.370806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip
12423 12:14:23.373167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip>
12424 12:14:23.450718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12425 12:14:23.451530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12427 12:14:23.532675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip>
12428 12:14:23.533476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip
12430 12:14:23.596900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12431 12:14:23.597236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12433 12:14:23.661247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12435 12:14:23.664079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12436 12:14:23.724993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12438 12:14:23.728373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12439 12:14:23.794274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12440 12:14:23.794946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12442 12:14:23.861963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12443 12:14:23.862414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12445 12:14:23.922402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12446 12:14:23.923142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12448 12:14:23.993107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12449 12:14:23.993438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12451 12:14:24.062312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12452 12:14:24.063054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12454 12:14:24.134869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12455 12:14:24.135795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12457 12:14:24.221186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12458 12:14:24.222018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12460 12:14:24.295639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12461 12:14:24.296436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12463 12:14:24.372697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12464 12:14:24.373494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12466 12:14:24.451800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12467 12:14:24.452578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12469 12:14:24.524133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12470 12:14:24.524885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12472 12:14:24.598984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12473 12:14:24.599774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12475 12:14:24.674410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12476 12:14:24.675136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12478 12:14:24.742208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12479 12:14:24.742924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12481 12:14:24.807241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12482 12:14:24.807790 + set +x
12483 12:14:24.808408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12485 12:14:24.813981 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 12669504_1.6.2.3.5>
12486 12:14:24.814661 Received signal: <ENDRUN> 1_kselftest-arm64 12669504_1.6.2.3.5
12487 12:14:24.815035 Ending use of test pattern.
12488 12:14:24.815355 Ending test lava.1_kselftest-arm64 (12669504_1.6.2.3.5), duration 37.13
12490 12:14:24.816988 <LAVA_TEST_RUNNER EXIT>
12491 12:14:24.817686 ok: lava_test_shell seems to have completed
12492 12:14:24.822580 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_async: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_prctl_sync: skip
arm64_check_prctl_sync_async: skip
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_rng: skip
arm64_hwcap_sigill_sve2_bf16: skip
arm64_hwcap_sigill_sve2_bitperm: skip
arm64_hwcap_sigill_sve2_ebf16: skip
arm64_hwcap_sigill_sve2_f32mm: skip
arm64_hwcap_sigill_sve2_f64mm: skip
arm64_hwcap_sigill_sve2_i8mm: skip
arm64_hwcap_sigill_sve2_pmull: skip
arm64_hwcap_sigill_sve2_sha3: skip
arm64_hwcap_sigill_sve2_sm4: skip
arm64_hwcap_sigill_sve_2: skip
arm64_hwcap_sigill_sve_aes: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_generic_pauth_not_enabled: skip
arm64_pac_pauth_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_sve_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_sve_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_sme_not_supported: skip
arm64_vec-syscfg_sve_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_sme_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12493 12:14:24.823282 end: 3.1 lava-test-shell (duration 00:00:38) [common]
12494 12:14:24.823738 end: 3 lava-test-retry (duration 00:00:38) [common]
12495 12:14:24.824174 start: 4 finalize (timeout 00:06:54) [common]
12496 12:14:24.824638 start: 4.1 power-off (timeout 00:00:30) [common]
12497 12:14:24.825380 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
12498 12:14:24.942995 >> Command sent successfully.
12499 12:14:24.946837 Returned 0 in 0 seconds
12500 12:14:25.047737 end: 4.1 power-off (duration 00:00:00) [common]
12502 12:14:25.049163 start: 4.2 read-feedback (timeout 00:06:54) [common]
12503 12:14:25.050400 Listened to connection for namespace 'common' for up to 1s
12504 12:14:26.051043 Finalising connection for namespace 'common'
12505 12:14:26.051733 Disconnecting from shell: Finalise
12506 12:14:26.052128 / #
12507 12:14:26.153214 end: 4.2 read-feedback (duration 00:00:01) [common]
12508 12:14:26.153995 end: 4 finalize (duration 00:00:01) [common]
12509 12:14:26.154622 Cleaning after the job
12510 12:14:26.155171 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669504/tftp-deploy-_dcldchd/ramdisk
12511 12:14:26.167468 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669504/tftp-deploy-_dcldchd/kernel
12512 12:14:26.203194 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669504/tftp-deploy-_dcldchd/dtb
12513 12:14:26.203492 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669504/tftp-deploy-_dcldchd/nfsrootfs
12514 12:14:26.295807 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669504/tftp-deploy-_dcldchd/modules
12515 12:14:26.302821 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12669504
12516 12:14:26.948046 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12669504
12517 12:14:26.948229 Job finished correctly