Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 17
- Kernel Errors: 38
1 12:17:32.793097 lava-dispatcher, installed at version: 2023.10
2 12:17:32.793281 start: 0 validate
3 12:17:32.793411 Start time: 2024-01-31 12:17:32.793403+00:00 (UTC)
4 12:17:32.793526 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:17:32.793655 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 12:17:33.061187 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:17:33.061963 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:17:33.342672 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:17:33.343504 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:17:33.611313 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:17:33.612066 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:17:33.879597 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:17:33.880379 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:17:34.152636 validate duration: 1.36
16 12:17:34.152896 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:17:34.152994 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:17:34.153083 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:17:34.153202 Not decompressing ramdisk as can be used compressed.
20 12:17:34.153287 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 12:17:34.153353 saving as /var/lib/lava/dispatcher/tmp/12669536/tftp-deploy-ij7nhhg4/ramdisk/initrd.cpio.gz
22 12:17:34.153415 total size: 4665395 (4 MB)
23 12:17:34.154555 progress 0 % (0 MB)
24 12:17:34.155870 progress 5 % (0 MB)
25 12:17:34.157076 progress 10 % (0 MB)
26 12:17:34.158295 progress 15 % (0 MB)
27 12:17:34.159487 progress 20 % (0 MB)
28 12:17:34.160708 progress 25 % (1 MB)
29 12:17:34.161887 progress 30 % (1 MB)
30 12:17:34.163106 progress 35 % (1 MB)
31 12:17:34.164277 progress 40 % (1 MB)
32 12:17:34.165638 progress 45 % (2 MB)
33 12:17:34.166805 progress 50 % (2 MB)
34 12:17:34.167970 progress 55 % (2 MB)
35 12:17:34.169141 progress 60 % (2 MB)
36 12:17:34.170355 progress 65 % (2 MB)
37 12:17:34.171521 progress 70 % (3 MB)
38 12:17:34.172681 progress 75 % (3 MB)
39 12:17:34.173848 progress 80 % (3 MB)
40 12:17:34.175173 progress 85 % (3 MB)
41 12:17:34.176341 progress 90 % (4 MB)
42 12:17:34.177510 progress 95 % (4 MB)
43 12:17:34.178730 progress 100 % (4 MB)
44 12:17:34.178878 4 MB downloaded in 0.03 s (174.74 MB/s)
45 12:17:34.179016 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:17:34.179245 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:17:34.179330 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:17:34.179411 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:17:34.179559 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:17:34.179629 saving as /var/lib/lava/dispatcher/tmp/12669536/tftp-deploy-ij7nhhg4/kernel/Image
52 12:17:34.179689 total size: 51532288 (49 MB)
53 12:17:34.179749 No compression specified
54 12:17:34.180741 progress 0 % (0 MB)
55 12:17:34.193429 progress 5 % (2 MB)
56 12:17:34.206208 progress 10 % (4 MB)
57 12:17:34.218885 progress 15 % (7 MB)
58 12:17:34.231773 progress 20 % (9 MB)
59 12:17:34.244657 progress 25 % (12 MB)
60 12:17:34.257493 progress 30 % (14 MB)
61 12:17:34.270253 progress 35 % (17 MB)
62 12:17:34.282986 progress 40 % (19 MB)
63 12:17:34.295492 progress 45 % (22 MB)
64 12:17:34.308083 progress 50 % (24 MB)
65 12:17:34.320697 progress 55 % (27 MB)
66 12:17:34.333574 progress 60 % (29 MB)
67 12:17:34.346448 progress 65 % (31 MB)
68 12:17:34.359198 progress 70 % (34 MB)
69 12:17:34.371947 progress 75 % (36 MB)
70 12:17:34.384675 progress 80 % (39 MB)
71 12:17:34.397265 progress 85 % (41 MB)
72 12:17:34.409909 progress 90 % (44 MB)
73 12:17:34.422838 progress 95 % (46 MB)
74 12:17:34.435355 progress 100 % (49 MB)
75 12:17:34.435566 49 MB downloaded in 0.26 s (192.07 MB/s)
76 12:17:34.435714 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:17:34.435946 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:17:34.436032 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:17:34.436118 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:17:34.436248 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:17:34.436317 saving as /var/lib/lava/dispatcher/tmp/12669536/tftp-deploy-ij7nhhg4/dtb/mt8192-asurada-spherion-r0.dtb
83 12:17:34.436377 total size: 47278 (0 MB)
84 12:17:34.436437 No compression specified
85 12:17:34.437549 progress 69 % (0 MB)
86 12:17:34.437816 progress 100 % (0 MB)
87 12:17:34.438028 0 MB downloaded in 0.00 s (27.35 MB/s)
88 12:17:34.438149 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:17:34.438366 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:17:34.438454 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:17:34.438535 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:17:34.438640 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 12:17:34.438706 saving as /var/lib/lava/dispatcher/tmp/12669536/tftp-deploy-ij7nhhg4/nfsrootfs/full.rootfs.tar
95 12:17:34.438768 total size: 200813988 (191 MB)
96 12:17:34.438828 Using unxz to decompress xz
97 12:17:34.442229 progress 0 % (0 MB)
98 12:17:34.955872 progress 5 % (9 MB)
99 12:17:35.458574 progress 10 % (19 MB)
100 12:17:36.025080 progress 15 % (28 MB)
101 12:17:36.390556 progress 20 % (38 MB)
102 12:17:36.705229 progress 25 % (47 MB)
103 12:17:37.278680 progress 30 % (57 MB)
104 12:17:37.820423 progress 35 % (67 MB)
105 12:17:38.400766 progress 40 % (76 MB)
106 12:17:38.945615 progress 45 % (86 MB)
107 12:17:39.516183 progress 50 % (95 MB)
108 12:17:40.126815 progress 55 % (105 MB)
109 12:17:40.773438 progress 60 % (114 MB)
110 12:17:40.891003 progress 65 % (124 MB)
111 12:17:41.035862 progress 70 % (134 MB)
112 12:17:41.137042 progress 75 % (143 MB)
113 12:17:41.212735 progress 80 % (153 MB)
114 12:17:41.287750 progress 85 % (162 MB)
115 12:17:41.390849 progress 90 % (172 MB)
116 12:17:41.662011 progress 95 % (181 MB)
117 12:17:42.221484 progress 100 % (191 MB)
118 12:17:42.226589 191 MB downloaded in 7.79 s (24.59 MB/s)
119 12:17:42.226826 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:17:42.227082 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:17:42.227171 start: 1.5 download-retry (timeout 00:09:52) [common]
123 12:17:42.227258 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 12:17:42.227411 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:17:42.227485 saving as /var/lib/lava/dispatcher/tmp/12669536/tftp-deploy-ij7nhhg4/modules/modules.tar
126 12:17:42.227554 total size: 8639916 (8 MB)
127 12:17:42.227624 Using unxz to decompress xz
128 12:17:42.231249 progress 0 % (0 MB)
129 12:17:42.252212 progress 5 % (0 MB)
130 12:17:42.277797 progress 10 % (0 MB)
131 12:17:42.300666 progress 15 % (1 MB)
132 12:17:42.323307 progress 20 % (1 MB)
133 12:17:42.347177 progress 25 % (2 MB)
134 12:17:42.374163 progress 30 % (2 MB)
135 12:17:42.397888 progress 35 % (2 MB)
136 12:17:42.420766 progress 40 % (3 MB)
137 12:17:42.444373 progress 45 % (3 MB)
138 12:17:42.469121 progress 50 % (4 MB)
139 12:17:42.494344 progress 55 % (4 MB)
140 12:17:42.518315 progress 60 % (4 MB)
141 12:17:42.543044 progress 65 % (5 MB)
142 12:17:42.567426 progress 70 % (5 MB)
143 12:17:42.589976 progress 75 % (6 MB)
144 12:17:42.617328 progress 80 % (6 MB)
145 12:17:42.644247 progress 85 % (7 MB)
146 12:17:42.669439 progress 90 % (7 MB)
147 12:17:42.697879 progress 95 % (7 MB)
148 12:17:42.724588 progress 100 % (8 MB)
149 12:17:42.730437 8 MB downloaded in 0.50 s (16.39 MB/s)
150 12:17:42.730671 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:17:42.730923 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:17:42.731017 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:17:42.731114 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:17:45.884533 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12669536/extract-nfsrootfs-heetpg7n
156 12:17:45.884742 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 12:17:45.884843 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 12:17:45.885003 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp
159 12:17:45.885128 makedir: /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin
160 12:17:45.885225 makedir: /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/tests
161 12:17:45.885318 makedir: /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/results
162 12:17:45.885416 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-add-keys
163 12:17:45.885549 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-add-sources
164 12:17:45.885668 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-background-process-start
165 12:17:45.885785 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-background-process-stop
166 12:17:45.885904 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-common-functions
167 12:17:45.886052 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-echo-ipv4
168 12:17:45.886173 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-install-packages
169 12:17:45.886298 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-installed-packages
170 12:17:45.886412 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-os-build
171 12:17:45.886526 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-probe-channel
172 12:17:45.886641 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-probe-ip
173 12:17:45.886755 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-target-ip
174 12:17:45.886867 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-target-mac
175 12:17:45.886979 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-target-storage
176 12:17:45.887094 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-test-case
177 12:17:45.887208 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-test-event
178 12:17:45.887321 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-test-feedback
179 12:17:45.887434 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-test-raise
180 12:17:45.887547 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-test-reference
181 12:17:45.887660 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-test-runner
182 12:17:45.887782 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-test-set
183 12:17:45.887897 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-test-shell
184 12:17:45.888014 Updating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-add-keys (debian)
185 12:17:45.888156 Updating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-add-sources (debian)
186 12:17:45.888285 Updating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-install-packages (debian)
187 12:17:45.888412 Updating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-installed-packages (debian)
188 12:17:45.888538 Updating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/bin/lava-os-build (debian)
189 12:17:45.888649 Creating /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/environment
190 12:17:45.888738 LAVA metadata
191 12:17:45.888803 - LAVA_JOB_ID=12669536
192 12:17:45.888863 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:17:45.888959 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 12:17:45.889022 skipped lava-vland-overlay
195 12:17:45.889093 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:17:45.889169 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 12:17:45.889227 skipped lava-multinode-overlay
198 12:17:45.889296 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:17:45.889371 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 12:17:45.889440 Loading test definitions
201 12:17:45.889524 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 12:17:45.889591 Using /lava-12669536 at stage 0
203 12:17:45.889850 uuid=12669536_1.6.2.3.1 testdef=None
204 12:17:45.889934 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:17:45.890206 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 12:17:45.890633 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:17:45.890848 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 12:17:45.891353 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:17:45.891577 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 12:17:45.892093 runner path: /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/0/tests/0_timesync-off test_uuid 12669536_1.6.2.3.1
213 12:17:45.892238 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:17:45.892452 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 12:17:45.892521 Using /lava-12669536 at stage 0
217 12:17:45.892612 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:17:45.892686 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/0/tests/1_kselftest-rtc'
219 12:17:51.211766 Running '/usr/bin/git checkout kernelci.org
220 12:17:51.350571 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 12:17:51.351243 uuid=12669536_1.6.2.3.5 testdef=None
222 12:17:51.351384 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 12:17:51.351623 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 12:17:51.352329 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:17:51.352605 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 12:17:51.353539 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:17:51.353764 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 12:17:51.354750 runner path: /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/0/tests/1_kselftest-rtc test_uuid 12669536_1.6.2.3.5
232 12:17:51.354840 BOARD='mt8192-asurada-spherion-r0'
233 12:17:51.354902 BRANCH='cip-gitlab'
234 12:17:51.354960 SKIPFILE='/dev/null'
235 12:17:51.355016 SKIP_INSTALL='True'
236 12:17:51.355069 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:17:51.355123 TST_CASENAME=''
238 12:17:51.355176 TST_CMDFILES='rtc'
239 12:17:51.355306 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:17:51.355497 Creating lava-test-runner.conf files
242 12:17:51.355559 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12669536/lava-overlay-b2nap7lp/lava-12669536/0 for stage 0
243 12:17:51.355645 - 0_timesync-off
244 12:17:51.355708 - 1_kselftest-rtc
245 12:17:51.355797 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 12:17:51.355879 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 12:17:58.811710 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 12:17:58.811874 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 12:17:58.811968 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:17:58.812068 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 12:17:58.812161 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 12:17:58.923689 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:17:58.924057 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 12:17:58.924170 extracting modules file /var/lib/lava/dispatcher/tmp/12669536/tftp-deploy-ij7nhhg4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12669536/extract-nfsrootfs-heetpg7n
255 12:17:59.125370 extracting modules file /var/lib/lava/dispatcher/tmp/12669536/tftp-deploy-ij7nhhg4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12669536/extract-overlay-ramdisk-mt9h_y3r/ramdisk
256 12:17:59.328985 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 12:17:59.329154 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 12:17:59.329254 [common] Applying overlay to NFS
259 12:17:59.329322 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12669536/compress-overlay-5intt6m8/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12669536/extract-nfsrootfs-heetpg7n
260 12:18:00.213396 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:18:00.213569 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 12:18:00.213668 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:18:00.213760 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 12:18:00.213840 Building ramdisk /var/lib/lava/dispatcher/tmp/12669536/extract-overlay-ramdisk-mt9h_y3r/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12669536/extract-overlay-ramdisk-mt9h_y3r/ramdisk
265 12:18:00.515648 >> 119414 blocks
266 12:18:02.438429 rename /var/lib/lava/dispatcher/tmp/12669536/extract-overlay-ramdisk-mt9h_y3r/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12669536/tftp-deploy-ij7nhhg4/ramdisk/ramdisk.cpio.gz
267 12:18:02.438845 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:18:02.438964 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 12:18:02.439066 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 12:18:02.439171 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12669536/tftp-deploy-ij7nhhg4/kernel/Image'
271 12:18:14.692792 Returned 0 in 12 seconds
272 12:18:14.793742 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12669536/tftp-deploy-ij7nhhg4/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12669536/tftp-deploy-ij7nhhg4/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12669536/tftp-deploy-ij7nhhg4/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12669536/tftp-deploy-ij7nhhg4/kernel/image.itb
273 12:18:15.170431 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:18:15.170780 output: Created: Wed Jan 31 12:18:15 2024
275 12:18:15.170854 output: Image 0 (kernel-1)
276 12:18:15.170919 output: Description:
277 12:18:15.170981 output: Created: Wed Jan 31 12:18:15 2024
278 12:18:15.171041 output: Type: Kernel Image
279 12:18:15.171097 output: Compression: lzma compressed
280 12:18:15.171156 output: Data Size: 12047284 Bytes = 11764.93 KiB = 11.49 MiB
281 12:18:15.171213 output: Architecture: AArch64
282 12:18:15.171269 output: OS: Linux
283 12:18:15.171325 output: Load Address: 0x00000000
284 12:18:15.171381 output: Entry Point: 0x00000000
285 12:18:15.171437 output: Hash algo: crc32
286 12:18:15.171494 output: Hash value: 5a47eb78
287 12:18:15.171550 output: Image 1 (fdt-1)
288 12:18:15.171605 output: Description: mt8192-asurada-spherion-r0
289 12:18:15.171658 output: Created: Wed Jan 31 12:18:15 2024
290 12:18:15.171710 output: Type: Flat Device Tree
291 12:18:15.171763 output: Compression: uncompressed
292 12:18:15.171815 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 12:18:15.171867 output: Architecture: AArch64
294 12:18:15.171918 output: Hash algo: crc32
295 12:18:15.171970 output: Hash value: cc4352de
296 12:18:15.172023 output: Image 2 (ramdisk-1)
297 12:18:15.172075 output: Description: unavailable
298 12:18:15.172126 output: Created: Wed Jan 31 12:18:15 2024
299 12:18:15.172178 output: Type: RAMDisk Image
300 12:18:15.172230 output: Compression: Unknown Compression
301 12:18:15.172282 output: Data Size: 17806045 Bytes = 17388.72 KiB = 16.98 MiB
302 12:18:15.172334 output: Architecture: AArch64
303 12:18:15.172386 output: OS: Linux
304 12:18:15.172437 output: Load Address: unavailable
305 12:18:15.172489 output: Entry Point: unavailable
306 12:18:15.172540 output: Hash algo: crc32
307 12:18:15.172591 output: Hash value: 4cd8d3c1
308 12:18:15.172643 output: Default Configuration: 'conf-1'
309 12:18:15.172694 output: Configuration 0 (conf-1)
310 12:18:15.172746 output: Description: mt8192-asurada-spherion-r0
311 12:18:15.172798 output: Kernel: kernel-1
312 12:18:15.172849 output: Init Ramdisk: ramdisk-1
313 12:18:15.172901 output: FDT: fdt-1
314 12:18:15.172952 output: Loadables: kernel-1
315 12:18:15.173003 output:
316 12:18:15.173221 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 12:18:15.173318 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 12:18:15.173420 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 12:18:15.173514 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 12:18:15.173589 No LXC device requested
321 12:18:15.173666 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:18:15.173748 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 12:18:15.173827 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:18:15.173894 Checking files for TFTP limit of 4294967296 bytes.
325 12:18:15.174367 end: 1 tftp-deploy (duration 00:00:41) [common]
326 12:18:15.174472 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:18:15.174567 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:18:15.174692 substitutions:
329 12:18:15.174758 - {DTB}: 12669536/tftp-deploy-ij7nhhg4/dtb/mt8192-asurada-spherion-r0.dtb
330 12:18:15.174821 - {INITRD}: 12669536/tftp-deploy-ij7nhhg4/ramdisk/ramdisk.cpio.gz
331 12:18:15.174880 - {KERNEL}: 12669536/tftp-deploy-ij7nhhg4/kernel/Image
332 12:18:15.174937 - {LAVA_MAC}: None
333 12:18:15.174992 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12669536/extract-nfsrootfs-heetpg7n
334 12:18:15.175048 - {NFS_SERVER_IP}: 192.168.201.1
335 12:18:15.175119 - {PRESEED_CONFIG}: None
336 12:18:15.175188 - {PRESEED_LOCAL}: None
337 12:18:15.175242 - {RAMDISK}: 12669536/tftp-deploy-ij7nhhg4/ramdisk/ramdisk.cpio.gz
338 12:18:15.175296 - {ROOT_PART}: None
339 12:18:15.175350 - {ROOT}: None
340 12:18:15.175404 - {SERVER_IP}: 192.168.201.1
341 12:18:15.175456 - {TEE}: None
342 12:18:15.175510 Parsed boot commands:
343 12:18:15.175563 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:18:15.175735 Parsed boot commands: tftpboot 192.168.201.1 12669536/tftp-deploy-ij7nhhg4/kernel/image.itb 12669536/tftp-deploy-ij7nhhg4/kernel/cmdline
345 12:18:15.175822 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:18:15.175905 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:18:15.175992 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:18:15.176079 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:18:15.176149 Not connected, no need to disconnect.
350 12:18:15.176222 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:18:15.176303 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:18:15.176369 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 12:18:15.179732 Setting prompt string to ['lava-test: # ']
354 12:18:15.180048 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:18:15.180154 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:18:15.180275 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:18:15.180393 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:18:15.180605 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
359 12:18:20.334512 >> Command sent successfully.
360 12:18:20.345336 Returned 0 in 5 seconds
361 12:18:20.446632 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:18:20.448163 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:18:20.448775 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:18:20.449248 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:18:20.449622 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:18:20.450048 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:18:20.451430 [Enter `^Ec?' for help]
369 12:18:20.612102
370 12:18:20.612708
371 12:18:20.613105 F0: 102B 0000
372 12:18:20.613474
373 12:18:20.613833 F3: 1001 0000 [0200]
374 12:18:20.615691
375 12:18:20.616271 F3: 1001 0000
376 12:18:20.616658
377 12:18:20.617018 F7: 102D 0000
378 12:18:20.617357
379 12:18:20.619292 F1: 0000 0000
380 12:18:20.619879
381 12:18:20.620266 V0: 0000 0000 [0001]
382 12:18:20.620624
383 12:18:20.622398 00: 0007 8000
384 12:18:20.622902
385 12:18:20.623282 01: 0000 0000
386 12:18:20.623646
387 12:18:20.625669 BP: 0C00 0209 [0000]
388 12:18:20.626311
389 12:18:20.626700 G0: 1182 0000
390 12:18:20.627055
391 12:18:20.629085 EC: 0000 0021 [4000]
392 12:18:20.629622
393 12:18:20.630213 S7: 0000 0000 [0000]
394 12:18:20.630733
395 12:18:20.632505 CC: 0000 0000 [0001]
396 12:18:20.633249
397 12:18:20.633757 T0: 0000 0040 [010F]
398 12:18:20.634198
399 12:18:20.634554 Jump to BL
400 12:18:20.634891
401 12:18:20.659634
402 12:18:20.660253
403 12:18:20.660630
404 12:18:20.666635 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:18:20.670341 ARM64: Exception handlers installed.
406 12:18:20.673844 ARM64: Testing exception
407 12:18:20.677067 ARM64: Done test exception
408 12:18:20.683760 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:18:20.694005 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:18:20.701012 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:18:20.710825 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:18:20.717394 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:18:20.724166 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:18:20.736002 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:18:20.742711 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:18:20.762080 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:18:20.765367 WDT: Last reset was cold boot
418 12:18:20.768600 SPI1(PAD0) initialized at 2873684 Hz
419 12:18:20.772374 SPI5(PAD0) initialized at 992727 Hz
420 12:18:20.775471 VBOOT: Loading verstage.
421 12:18:20.781920 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:18:20.785720 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:18:20.788749 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:18:20.792344 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:18:20.799548 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:18:20.806152 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:18:20.816963 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 12:18:20.817547
429 12:18:20.817918
430 12:18:20.827109 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:18:20.830797 ARM64: Exception handlers installed.
432 12:18:20.833680 ARM64: Testing exception
433 12:18:20.834512 ARM64: Done test exception
434 12:18:20.840281 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:18:20.844270 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:18:20.858580 Probing TPM: . done!
437 12:18:20.859165 TPM ready after 0 ms
438 12:18:20.864771 Connected to device vid:did:rid of 1ae0:0028:00
439 12:18:20.871844 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 12:18:20.928284 Initialized TPM device CR50 revision 0
441 12:18:20.939524 tlcl_send_startup: Startup return code is 0
442 12:18:20.940007 TPM: setup succeeded
443 12:18:20.951266 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:18:20.959774 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:18:20.969907 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:18:20.979642 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:18:20.982480 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:18:20.990920 in-header: 03 07 00 00 08 00 00 00
449 12:18:20.994880 in-data: aa e4 47 04 13 02 00 00
450 12:18:20.998174 Chrome EC: UHEPI supported
451 12:18:21.005776 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:18:21.009333 in-header: 03 ad 00 00 08 00 00 00
453 12:18:21.013303 in-data: 00 20 20 08 00 00 00 00
454 12:18:21.013887 Phase 1
455 12:18:21.017392 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:18:21.024384 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:18:21.027771 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:18:21.031497 Recovery requested (1009000e)
459 12:18:21.040398 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:18:21.045767 tlcl_extend: response is 0
461 12:18:21.055159 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:18:21.060435 tlcl_extend: response is 0
463 12:18:21.067409 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:18:21.088180 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 12:18:21.095153 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:18:21.095721
467 12:18:21.096097
468 12:18:21.105630 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:18:21.108475 ARM64: Exception handlers installed.
470 12:18:21.109049 ARM64: Testing exception
471 12:18:21.112179 ARM64: Done test exception
472 12:18:21.133762 pmic_efuse_setting: Set efuses in 11 msecs
473 12:18:21.137013 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:18:21.144189 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:18:21.147691 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:18:21.150717 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:18:21.158179 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:18:21.160874 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:18:21.168673 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:18:21.171879 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:18:21.175675 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:18:21.179544 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:18:21.186431 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:18:21.190378 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:18:21.194083 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:18:21.197225 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:18:21.204653 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:18:21.211425 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:18:21.218664 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:18:21.222085 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:18:21.229315 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:18:21.233167 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:18:21.239933 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:18:21.243784 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:18:21.250335 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:18:21.257452 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:18:21.260358 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:18:21.266994 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:18:21.273800 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:18:21.276768 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:18:21.284145 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:18:21.287072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:18:21.290093 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:18:21.296992 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:18:21.303880 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:18:21.307058 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:18:21.313719 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:18:21.317223 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:18:21.324372 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:18:21.326777 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:18:21.330713 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:18:21.337148 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:18:21.340615 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:18:21.343895 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:18:21.348181 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:18:21.354604 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:18:21.358471 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:18:21.361640 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:18:21.368389 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:18:21.371962 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:18:21.375083 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:18:21.378489 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:18:21.384884 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:18:21.388218 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:18:21.394839 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:18:21.404833 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:18:21.408309 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:18:21.418471 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:18:21.425150 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:18:21.431489 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:18:21.434901 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:18:21.437932 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:18:21.446025 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x28
534 12:18:21.452373 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:18:21.455766 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 12:18:21.459179 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:18:21.471031 [RTC]rtc_get_frequency_meter,154: input=15, output=770
538 12:18:21.479953 [RTC]rtc_get_frequency_meter,154: input=23, output=957
539 12:18:21.489665 [RTC]rtc_get_frequency_meter,154: input=19, output=863
540 12:18:21.498838 [RTC]rtc_get_frequency_meter,154: input=17, output=819
541 12:18:21.509070 [RTC]rtc_get_frequency_meter,154: input=16, output=795
542 12:18:21.512685 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 12:18:21.516726 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 12:18:21.520317 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
545 12:18:21.527493 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 12:18:21.530913 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
547 12:18:21.534433 ADC[4]: Raw value=903245 ID=7
548 12:18:21.534907 ADC[3]: Raw value=213179 ID=1
549 12:18:21.538386 RAM Code: 0x71
550 12:18:21.542370 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 12:18:21.545570 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 12:18:21.556064 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 12:18:21.562758 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 12:18:21.565884 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 12:18:21.569361 in-header: 03 07 00 00 08 00 00 00
556 12:18:21.572845 in-data: aa e4 47 04 13 02 00 00
557 12:18:21.573419 Chrome EC: UHEPI supported
558 12:18:21.578997 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 12:18:21.582449 in-header: 03 ed 00 00 08 00 00 00
560 12:18:21.586366 in-data: 80 20 60 08 00 00 00 00
561 12:18:21.589482 MRC: failed to locate region type 0.
562 12:18:21.596046 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 12:18:21.599737 DRAM-K: Running full calibration
564 12:18:21.607767 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 12:18:21.608250 header.status = 0x0
566 12:18:21.611312 header.version = 0x6 (expected: 0x6)
567 12:18:21.614898 header.size = 0xd00 (expected: 0xd00)
568 12:18:21.618397 header.flags = 0x0
569 12:18:21.621755 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 12:18:21.640008 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
571 12:18:21.646930 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 12:18:21.650078 dram_init: ddr_geometry: 2
573 12:18:21.653758 [EMI] MDL number = 2
574 12:18:21.654281 [EMI] Get MDL freq = 0
575 12:18:21.656972 dram_init: ddr_type: 0
576 12:18:21.657447 is_discrete_lpddr4: 1
577 12:18:21.660510 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 12:18:21.660980
579 12:18:21.661354
580 12:18:21.663383 [Bian_co] ETT version 0.0.0.1
581 12:18:21.670525 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 12:18:21.671107
583 12:18:21.673513 dramc_set_vcore_voltage set vcore to 650000
584 12:18:21.674002 Read voltage for 800, 4
585 12:18:21.676982 Vio18 = 0
586 12:18:21.677455 Vcore = 650000
587 12:18:21.677830 Vdram = 0
588 12:18:21.680183 Vddq = 0
589 12:18:21.680653 Vmddr = 0
590 12:18:21.683662 dram_init: config_dvfs: 1
591 12:18:21.687073 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 12:18:21.693667 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 12:18:21.696732 [SwImpedanceCal] DRVP=9, DRVN=15, ODTN=9
594 12:18:21.700582 freq_region=0, Reg: DRVP=9, DRVN=15, ODTN=9
595 12:18:21.703660 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 12:18:21.707085 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 12:18:21.709906 MEM_TYPE=3, freq_sel=18
598 12:18:21.713607 sv_algorithm_assistance_LP4_1600
599 12:18:21.717053 ============ PULL DRAM RESETB DOWN ============
600 12:18:21.720114 ========== PULL DRAM RESETB DOWN end =========
601 12:18:21.726943 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 12:18:21.730149 ===================================
603 12:18:21.730626 LPDDR4 DRAM CONFIGURATION
604 12:18:21.733534 ===================================
605 12:18:21.737035 EX_ROW_EN[0] = 0x0
606 12:18:21.740174 EX_ROW_EN[1] = 0x0
607 12:18:21.740649 LP4Y_EN = 0x0
608 12:18:21.743740 WORK_FSP = 0x0
609 12:18:21.744213 WL = 0x2
610 12:18:21.746761 RL = 0x2
611 12:18:21.747193 BL = 0x2
612 12:18:21.750577 RPST = 0x0
613 12:18:21.751004 RD_PRE = 0x0
614 12:18:21.753735 WR_PRE = 0x1
615 12:18:21.754210 WR_PST = 0x0
616 12:18:21.757054 DBI_WR = 0x0
617 12:18:21.757481 DBI_RD = 0x0
618 12:18:21.760504 OTF = 0x1
619 12:18:21.763830 ===================================
620 12:18:21.767373 ===================================
621 12:18:21.767804 ANA top config
622 12:18:21.770132 ===================================
623 12:18:21.773482 DLL_ASYNC_EN = 0
624 12:18:21.776959 ALL_SLAVE_EN = 1
625 12:18:21.780623 NEW_RANK_MODE = 1
626 12:18:21.781164 DLL_IDLE_MODE = 1
627 12:18:21.783803 LP45_APHY_COMB_EN = 1
628 12:18:21.786900 TX_ODT_DIS = 1
629 12:18:21.790172 NEW_8X_MODE = 1
630 12:18:21.793620 ===================================
631 12:18:21.796834 ===================================
632 12:18:21.797268 data_rate = 1600
633 12:18:21.800312 CKR = 1
634 12:18:21.803459 DQ_P2S_RATIO = 8
635 12:18:21.807010 ===================================
636 12:18:21.811083 CA_P2S_RATIO = 8
637 12:18:21.813725 DQ_CA_OPEN = 0
638 12:18:21.817057 DQ_SEMI_OPEN = 0
639 12:18:21.817489 CA_SEMI_OPEN = 0
640 12:18:21.820255 CA_FULL_RATE = 0
641 12:18:21.823590 DQ_CKDIV4_EN = 1
642 12:18:21.827106 CA_CKDIV4_EN = 1
643 12:18:21.830427 CA_PREDIV_EN = 0
644 12:18:21.833854 PH8_DLY = 0
645 12:18:21.834433 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 12:18:21.836992 DQ_AAMCK_DIV = 4
647 12:18:21.840207 CA_AAMCK_DIV = 4
648 12:18:21.843783 CA_ADMCK_DIV = 4
649 12:18:21.847210 DQ_TRACK_CA_EN = 0
650 12:18:21.850302 CA_PICK = 800
651 12:18:21.850732 CA_MCKIO = 800
652 12:18:21.853877 MCKIO_SEMI = 0
653 12:18:21.857037 PLL_FREQ = 3068
654 12:18:21.860921 DQ_UI_PI_RATIO = 32
655 12:18:21.864027 CA_UI_PI_RATIO = 0
656 12:18:21.867461 ===================================
657 12:18:21.870565 ===================================
658 12:18:21.873732 memory_type:LPDDR4
659 12:18:21.874199 GP_NUM : 10
660 12:18:21.877524 SRAM_EN : 1
661 12:18:21.878149 MD32_EN : 0
662 12:18:21.881112 ===================================
663 12:18:21.884665 [ANA_INIT] >>>>>>>>>>>>>>
664 12:18:21.888067 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 12:18:21.891891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 12:18:21.895334 ===================================
667 12:18:21.895815 data_rate = 1600,PCW = 0X7600
668 12:18:21.899340 ===================================
669 12:18:21.902656 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 12:18:21.910148 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 12:18:21.913865 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 12:18:21.917979 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 12:18:21.920912 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 12:18:21.924377 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 12:18:21.927538 [ANA_INIT] flow start
676 12:18:21.931046 [ANA_INIT] PLL >>>>>>>>
677 12:18:21.931476 [ANA_INIT] PLL <<<<<<<<
678 12:18:21.934820 [ANA_INIT] MIDPI >>>>>>>>
679 12:18:21.937856 [ANA_INIT] MIDPI <<<<<<<<
680 12:18:21.938487 [ANA_INIT] DLL >>>>>>>>
681 12:18:21.940947 [ANA_INIT] flow end
682 12:18:21.944587 ============ LP4 DIFF to SE enter ============
683 12:18:21.947544 ============ LP4 DIFF to SE exit ============
684 12:18:21.950833 [ANA_INIT] <<<<<<<<<<<<<
685 12:18:21.954856 [Flow] Enable top DCM control >>>>>
686 12:18:21.958031 [Flow] Enable top DCM control <<<<<
687 12:18:21.961277 Enable DLL master slave shuffle
688 12:18:21.968368 ==============================================================
689 12:18:21.968953 Gating Mode config
690 12:18:21.974729 ==============================================================
691 12:18:21.975315 Config description:
692 12:18:21.984862 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 12:18:21.991720 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 12:18:21.998278 SELPH_MODE 0: By rank 1: By Phase
695 12:18:22.001334 ==============================================================
696 12:18:22.004940 GAT_TRACK_EN = 1
697 12:18:22.008437 RX_GATING_MODE = 2
698 12:18:22.011704 RX_GATING_TRACK_MODE = 2
699 12:18:22.014806 SELPH_MODE = 1
700 12:18:22.018202 PICG_EARLY_EN = 1
701 12:18:22.021501 VALID_LAT_VALUE = 1
702 12:18:22.025065 ==============================================================
703 12:18:22.028245 Enter into Gating configuration >>>>
704 12:18:22.031579 Exit from Gating configuration <<<<
705 12:18:22.035451 Enter into DVFS_PRE_config >>>>>
706 12:18:22.046614 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 12:18:22.049875 Exit from DVFS_PRE_config <<<<<
708 12:18:22.053692 Enter into PICG configuration >>>>
709 12:18:22.057731 Exit from PICG configuration <<<<
710 12:18:22.058359 [RX_INPUT] configuration >>>>>
711 12:18:22.061085 [RX_INPUT] configuration <<<<<
712 12:18:22.068724 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 12:18:22.072011 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 12:18:22.079323 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 12:18:22.086243 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 12:18:22.090107 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 12:18:22.098024 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 12:18:22.101627 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 12:18:22.104781 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 12:18:22.108849 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 12:18:22.112853 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 12:18:22.116096 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 12:18:22.123971 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 12:18:22.127405 ===================================
725 12:18:22.127881 LPDDR4 DRAM CONFIGURATION
726 12:18:22.130997 ===================================
727 12:18:22.134528 EX_ROW_EN[0] = 0x0
728 12:18:22.135004 EX_ROW_EN[1] = 0x0
729 12:18:22.138587 LP4Y_EN = 0x0
730 12:18:22.139163 WORK_FSP = 0x0
731 12:18:22.142161 WL = 0x2
732 12:18:22.142647 RL = 0x2
733 12:18:22.143026 BL = 0x2
734 12:18:22.145807 RPST = 0x0
735 12:18:22.146431 RD_PRE = 0x0
736 12:18:22.149583 WR_PRE = 0x1
737 12:18:22.150348 WR_PST = 0x0
738 12:18:22.153385 DBI_WR = 0x0
739 12:18:22.154074 DBI_RD = 0x0
740 12:18:22.157114 OTF = 0x1
741 12:18:22.160753 ===================================
742 12:18:22.164596 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 12:18:22.168618 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 12:18:22.171469 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 12:18:22.175484 ===================================
746 12:18:22.179055 LPDDR4 DRAM CONFIGURATION
747 12:18:22.179639 ===================================
748 12:18:22.182955 EX_ROW_EN[0] = 0x10
749 12:18:22.183437 EX_ROW_EN[1] = 0x0
750 12:18:22.186581 LP4Y_EN = 0x0
751 12:18:22.187059 WORK_FSP = 0x0
752 12:18:22.190135 WL = 0x2
753 12:18:22.190618 RL = 0x2
754 12:18:22.193558 BL = 0x2
755 12:18:22.194185 RPST = 0x0
756 12:18:22.197718 RD_PRE = 0x0
757 12:18:22.198333 WR_PRE = 0x1
758 12:18:22.201466 WR_PST = 0x0
759 12:18:22.202081 DBI_WR = 0x0
760 12:18:22.204562 DBI_RD = 0x0
761 12:18:22.205042 OTF = 0x1
762 12:18:22.208378 ===================================
763 12:18:22.215149 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 12:18:22.218976 nWR fixed to 40
765 12:18:22.219456 [ModeRegInit_LP4] CH0 RK0
766 12:18:22.222778 [ModeRegInit_LP4] CH0 RK1
767 12:18:22.226660 [ModeRegInit_LP4] CH1 RK0
768 12:18:22.227139 [ModeRegInit_LP4] CH1 RK1
769 12:18:22.230473 match AC timing 13
770 12:18:22.234360 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 12:18:22.237695 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 12:18:22.241896 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 12:18:22.248607 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 12:18:22.252874 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 12:18:22.253356 [EMI DOE] emi_dcm 0
776 12:18:22.256245 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 12:18:22.259972 ==
778 12:18:22.260451 Dram Type= 6, Freq= 0, CH_0, rank 0
779 12:18:22.263871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 12:18:22.267566 ==
781 12:18:22.271330 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 12:18:22.278030 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 12:18:22.286705 [CA 0] Center 37 (7~68) winsize 62
784 12:18:22.289527 [CA 1] Center 38 (7~69) winsize 63
785 12:18:22.293619 [CA 2] Center 35 (5~66) winsize 62
786 12:18:22.297232 [CA 3] Center 35 (4~66) winsize 63
787 12:18:22.300355 [CA 4] Center 34 (4~65) winsize 62
788 12:18:22.303983 [CA 5] Center 33 (3~64) winsize 62
789 12:18:22.304466
790 12:18:22.308098 [CmdBusTrainingLP45] Vref(ca) range 1: 32
791 12:18:22.308675
792 12:18:22.310980 [CATrainingPosCal] consider 1 rank data
793 12:18:22.315148 u2DelayCellTimex100 = 270/100 ps
794 12:18:22.318681 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
795 12:18:22.322379 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
796 12:18:22.326563 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 12:18:22.329638 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
798 12:18:22.333671 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
799 12:18:22.337503 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 12:18:22.338117
801 12:18:22.340781 CA PerBit enable=1, Macro0, CA PI delay=33
802 12:18:22.341500
803 12:18:22.344030 [CBTSetCACLKResult] CA Dly = 33
804 12:18:22.344647 CS Dly: 5 (0~36)
805 12:18:22.345236 ==
806 12:18:22.347447 Dram Type= 6, Freq= 0, CH_0, rank 1
807 12:18:22.350617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 12:18:22.351096 ==
809 12:18:22.357854 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 12:18:22.364270 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 12:18:22.372701 [CA 0] Center 38 (7~69) winsize 63
812 12:18:22.376027 [CA 1] Center 38 (7~69) winsize 63
813 12:18:22.379091 [CA 2] Center 36 (6~67) winsize 62
814 12:18:22.382928 [CA 3] Center 35 (5~66) winsize 62
815 12:18:22.386146 [CA 4] Center 35 (4~66) winsize 63
816 12:18:22.389711 [CA 5] Center 34 (4~65) winsize 62
817 12:18:22.390322
818 12:18:22.392776 [CmdBusTrainingLP45] Vref(ca) range 1: 34
819 12:18:22.393353
820 12:18:22.396147 [CATrainingPosCal] consider 2 rank data
821 12:18:22.399590 u2DelayCellTimex100 = 270/100 ps
822 12:18:22.402869 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
823 12:18:22.406072 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
824 12:18:22.412755 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
825 12:18:22.416316 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 12:18:22.419717 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
827 12:18:22.422475 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
828 12:18:22.422960
829 12:18:22.425757 CA PerBit enable=1, Macro0, CA PI delay=34
830 12:18:22.426274
831 12:18:22.429568 [CBTSetCACLKResult] CA Dly = 34
832 12:18:22.430180 CS Dly: 6 (0~38)
833 12:18:22.430659
834 12:18:22.432702 ----->DramcWriteLeveling(PI) begin...
835 12:18:22.435779 ==
836 12:18:22.439143 Dram Type= 6, Freq= 0, CH_0, rank 0
837 12:18:22.442408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 12:18:22.442897 ==
839 12:18:22.446304 Write leveling (Byte 0): 33 => 33
840 12:18:22.449460 Write leveling (Byte 1): 29 => 29
841 12:18:22.452480 DramcWriteLeveling(PI) end<-----
842 12:18:22.452963
843 12:18:22.453343 ==
844 12:18:22.456084 Dram Type= 6, Freq= 0, CH_0, rank 0
845 12:18:22.459557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 12:18:22.460147 ==
847 12:18:22.462746 [Gating] SW mode calibration
848 12:18:22.470039 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 12:18:22.473492 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 12:18:22.477306 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
851 12:18:22.484262 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
852 12:18:22.487958 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
853 12:18:22.491367 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 12:18:22.494794 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 12:18:22.501988 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 12:18:22.505466 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:18:22.508561 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:18:22.515544 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:18:22.518530 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:18:22.521596 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:18:22.528526 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:18:22.531455 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:18:22.534977 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:18:22.538821 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:18:22.544916 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 12:18:22.548779 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
867 12:18:22.551962 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
868 12:18:22.558487 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
869 12:18:22.562156 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:18:22.565406 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 12:18:22.571814 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 12:18:22.574922 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 12:18:22.578404 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 12:18:22.585411 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 12:18:22.588619 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 12:18:22.592144 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
877 12:18:22.598488 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
878 12:18:22.602433 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 12:18:22.605122 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 12:18:22.612100 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 12:18:22.615190 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 12:18:22.618759 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 12:18:22.622334 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
884 12:18:22.628642 0 10 8 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
885 12:18:22.631820 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 12:18:22.635255 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 12:18:22.641887 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 12:18:22.645143 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 12:18:22.648604 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 12:18:22.655900 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 12:18:22.658779 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
892 12:18:22.662046 0 11 8 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
893 12:18:22.668712 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
894 12:18:22.672122 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 12:18:22.675506 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 12:18:22.682302 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 12:18:22.685502 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 12:18:22.689034 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 12:18:22.692468 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
900 12:18:22.699434 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
901 12:18:22.702551 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 12:18:22.706046 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 12:18:22.712395 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 12:18:22.715859 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:18:22.719328 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:18:22.725717 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:18:22.729085 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:18:22.732098 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:18:22.739160 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:18:22.742387 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:18:22.745812 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:18:22.752814 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 12:18:22.755565 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 12:18:22.758796 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 12:18:22.766205 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
916 12:18:22.769241 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
917 12:18:22.772466 Total UI for P1: 0, mck2ui 16
918 12:18:22.775635 best dqsien dly found for B0: ( 0, 14, 4)
919 12:18:22.778942 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 12:18:22.782552 Total UI for P1: 0, mck2ui 16
921 12:18:22.785372 best dqsien dly found for B1: ( 0, 14, 8)
922 12:18:22.789072 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
923 12:18:22.792333 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
924 12:18:22.792920
925 12:18:22.795963 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
926 12:18:22.799260 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
927 12:18:22.802289 [Gating] SW calibration Done
928 12:18:22.802891 ==
929 12:18:22.806040 Dram Type= 6, Freq= 0, CH_0, rank 0
930 12:18:22.809077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 12:18:22.812759 ==
932 12:18:22.813339 RX Vref Scan: 0
933 12:18:22.813725
934 12:18:22.815803 RX Vref 0 -> 0, step: 1
935 12:18:22.816388
936 12:18:22.818813 RX Delay -130 -> 252, step: 16
937 12:18:22.822642 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
938 12:18:22.826006 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
939 12:18:22.829014 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
940 12:18:22.832227 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
941 12:18:22.839350 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
942 12:18:22.843009 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
943 12:18:22.845547 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
944 12:18:22.849274 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
945 12:18:22.852665 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
946 12:18:22.859278 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
947 12:18:22.862652 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
948 12:18:22.865904 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
949 12:18:22.869321 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
950 12:18:22.872719 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
951 12:18:22.879384 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
952 12:18:22.882937 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
953 12:18:22.883417 ==
954 12:18:22.885704 Dram Type= 6, Freq= 0, CH_0, rank 0
955 12:18:22.889416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 12:18:22.890029 ==
957 12:18:22.892829 DQS Delay:
958 12:18:22.893418 DQS0 = 0, DQS1 = 0
959 12:18:22.893802 DQM Delay:
960 12:18:22.896102 DQM0 = 93, DQM1 = 83
961 12:18:22.896576 DQ Delay:
962 12:18:22.899493 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
963 12:18:22.902856 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
964 12:18:22.906315 DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =85
965 12:18:22.909483 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
966 12:18:22.910102
967 12:18:22.910485
968 12:18:22.910840 ==
969 12:18:22.913040 Dram Type= 6, Freq= 0, CH_0, rank 0
970 12:18:22.916061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 12:18:22.919625 ==
972 12:18:22.920209
973 12:18:22.920595
974 12:18:22.920949 TX Vref Scan disable
975 12:18:22.923095 == TX Byte 0 ==
976 12:18:22.926173 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
977 12:18:22.929323 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
978 12:18:22.933131 == TX Byte 1 ==
979 12:18:22.936241 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
980 12:18:22.939241 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
981 12:18:22.942802 ==
982 12:18:22.946555 Dram Type= 6, Freq= 0, CH_0, rank 0
983 12:18:22.949520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 12:18:22.950146 ==
985 12:18:22.962317 TX Vref=22, minBit 8, minWin=26, winSum=438
986 12:18:22.965551 TX Vref=24, minBit 8, minWin=26, winSum=441
987 12:18:22.968620 TX Vref=26, minBit 8, minWin=26, winSum=445
988 12:18:22.972422 TX Vref=28, minBit 12, minWin=27, winSum=449
989 12:18:22.975673 TX Vref=30, minBit 13, minWin=27, winSum=452
990 12:18:22.982308 TX Vref=32, minBit 13, minWin=27, winSum=452
991 12:18:22.985665 [TxChooseVref] Worse bit 13, Min win 27, Win sum 452, Final Vref 30
992 12:18:22.986172
993 12:18:22.989103 Final TX Range 1 Vref 30
994 12:18:22.989691
995 12:18:22.990103 ==
996 12:18:22.992437 Dram Type= 6, Freq= 0, CH_0, rank 0
997 12:18:22.995908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 12:18:22.996501 ==
999 12:18:22.999010
1000 12:18:22.999588
1001 12:18:22.999973 TX Vref Scan disable
1002 12:18:23.002329 == TX Byte 0 ==
1003 12:18:23.005900 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1004 12:18:23.012388 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1005 12:18:23.012967 == TX Byte 1 ==
1006 12:18:23.015878 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1007 12:18:23.022334 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1008 12:18:23.022914
1009 12:18:23.023295 [DATLAT]
1010 12:18:23.023646 Freq=800, CH0 RK0
1011 12:18:23.023989
1012 12:18:23.025516 DATLAT Default: 0xa
1013 12:18:23.026011 0, 0xFFFF, sum = 0
1014 12:18:23.028670 1, 0xFFFF, sum = 0
1015 12:18:23.029149 2, 0xFFFF, sum = 0
1016 12:18:23.032282 3, 0xFFFF, sum = 0
1017 12:18:23.032759 4, 0xFFFF, sum = 0
1018 12:18:23.035611 5, 0xFFFF, sum = 0
1019 12:18:23.038924 6, 0xFFFF, sum = 0
1020 12:18:23.039516 7, 0xFFFF, sum = 0
1021 12:18:23.042282 8, 0xFFFF, sum = 0
1022 12:18:23.042865 9, 0x0, sum = 1
1023 12:18:23.043266 10, 0x0, sum = 2
1024 12:18:23.045855 11, 0x0, sum = 3
1025 12:18:23.046512 12, 0x0, sum = 4
1026 12:18:23.049197 best_step = 10
1027 12:18:23.049776
1028 12:18:23.050209 ==
1029 12:18:23.052444 Dram Type= 6, Freq= 0, CH_0, rank 0
1030 12:18:23.055796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1031 12:18:23.056368 ==
1032 12:18:23.058687 RX Vref Scan: 1
1033 12:18:23.059154
1034 12:18:23.059532 Set Vref Range= 32 -> 127
1035 12:18:23.062715
1036 12:18:23.063285 RX Vref 32 -> 127, step: 1
1037 12:18:23.063766
1038 12:18:23.065603 RX Delay -79 -> 252, step: 8
1039 12:18:23.066104
1040 12:18:23.069088 Set Vref, RX VrefLevel [Byte0]: 32
1041 12:18:23.072144 [Byte1]: 32
1042 12:18:23.072614
1043 12:18:23.075356 Set Vref, RX VrefLevel [Byte0]: 33
1044 12:18:23.079412 [Byte1]: 33
1045 12:18:23.082530
1046 12:18:23.086165 Set Vref, RX VrefLevel [Byte0]: 34
1047 12:18:23.086739 [Byte1]: 34
1048 12:18:23.090372
1049 12:18:23.090939 Set Vref, RX VrefLevel [Byte0]: 35
1050 12:18:23.093613 [Byte1]: 35
1051 12:18:23.098115
1052 12:18:23.098687 Set Vref, RX VrefLevel [Byte0]: 36
1053 12:18:23.100841 [Byte1]: 36
1054 12:18:23.105350
1055 12:18:23.105990 Set Vref, RX VrefLevel [Byte0]: 37
1056 12:18:23.108628 [Byte1]: 37
1057 12:18:23.112976
1058 12:18:23.113441 Set Vref, RX VrefLevel [Byte0]: 38
1059 12:18:23.116625 [Byte1]: 38
1060 12:18:23.120253
1061 12:18:23.120718 Set Vref, RX VrefLevel [Byte0]: 39
1062 12:18:23.123708 [Byte1]: 39
1063 12:18:23.128059
1064 12:18:23.128643 Set Vref, RX VrefLevel [Byte0]: 40
1065 12:18:23.131649 [Byte1]: 40
1066 12:18:23.136705
1067 12:18:23.137280 Set Vref, RX VrefLevel [Byte0]: 41
1068 12:18:23.139189 [Byte1]: 41
1069 12:18:23.143979
1070 12:18:23.144545 Set Vref, RX VrefLevel [Byte0]: 42
1071 12:18:23.146964 [Byte1]: 42
1072 12:18:23.150977
1073 12:18:23.151453 Set Vref, RX VrefLevel [Byte0]: 43
1074 12:18:23.154941 [Byte1]: 43
1075 12:18:23.158425
1076 12:18:23.158890 Set Vref, RX VrefLevel [Byte0]: 44
1077 12:18:23.161819 [Byte1]: 44
1078 12:18:23.165589
1079 12:18:23.166089 Set Vref, RX VrefLevel [Byte0]: 45
1080 12:18:23.169144 [Byte1]: 45
1081 12:18:23.173125
1082 12:18:23.173591 Set Vref, RX VrefLevel [Byte0]: 46
1083 12:18:23.176204 [Byte1]: 46
1084 12:18:23.180852
1085 12:18:23.181420 Set Vref, RX VrefLevel [Byte0]: 47
1086 12:18:23.184166 [Byte1]: 47
1087 12:18:23.188728
1088 12:18:23.189300 Set Vref, RX VrefLevel [Byte0]: 48
1089 12:18:23.191768 [Byte1]: 48
1090 12:18:23.196379
1091 12:18:23.196946 Set Vref, RX VrefLevel [Byte0]: 49
1092 12:18:23.199294 [Byte1]: 49
1093 12:18:23.203586
1094 12:18:23.204156 Set Vref, RX VrefLevel [Byte0]: 50
1095 12:18:23.206548 [Byte1]: 50
1096 12:18:23.210868
1097 12:18:23.211430 Set Vref, RX VrefLevel [Byte0]: 51
1098 12:18:23.214232 [Byte1]: 51
1099 12:18:23.218288
1100 12:18:23.218758 Set Vref, RX VrefLevel [Byte0]: 52
1101 12:18:23.221819 [Byte1]: 52
1102 12:18:23.226116
1103 12:18:23.226680 Set Vref, RX VrefLevel [Byte0]: 53
1104 12:18:23.229831 [Byte1]: 53
1105 12:18:23.233924
1106 12:18:23.234544 Set Vref, RX VrefLevel [Byte0]: 54
1107 12:18:23.236989 [Byte1]: 54
1108 12:18:23.241118
1109 12:18:23.241684 Set Vref, RX VrefLevel [Byte0]: 55
1110 12:18:23.244466 [Byte1]: 55
1111 12:18:23.248885
1112 12:18:23.249515 Set Vref, RX VrefLevel [Byte0]: 56
1113 12:18:23.252255 [Byte1]: 56
1114 12:18:23.256001
1115 12:18:23.256564 Set Vref, RX VrefLevel [Byte0]: 57
1116 12:18:23.259612 [Byte1]: 57
1117 12:18:23.263981
1118 12:18:23.264567 Set Vref, RX VrefLevel [Byte0]: 58
1119 12:18:23.267185 [Byte1]: 58
1120 12:18:23.271426
1121 12:18:23.271994 Set Vref, RX VrefLevel [Byte0]: 59
1122 12:18:23.274445 [Byte1]: 59
1123 12:18:23.278654
1124 12:18:23.279121 Set Vref, RX VrefLevel [Byte0]: 60
1125 12:18:23.282009 [Byte1]: 60
1126 12:18:23.286726
1127 12:18:23.287299 Set Vref, RX VrefLevel [Byte0]: 61
1128 12:18:23.289775 [Byte1]: 61
1129 12:18:23.293779
1130 12:18:23.294390 Set Vref, RX VrefLevel [Byte0]: 62
1131 12:18:23.297297 [Byte1]: 62
1132 12:18:23.301232
1133 12:18:23.301698 Set Vref, RX VrefLevel [Byte0]: 63
1134 12:18:23.304885 [Byte1]: 63
1135 12:18:23.309443
1136 12:18:23.310064 Set Vref, RX VrefLevel [Byte0]: 64
1137 12:18:23.312405 [Byte1]: 64
1138 12:18:23.316708
1139 12:18:23.317275 Set Vref, RX VrefLevel [Byte0]: 65
1140 12:18:23.320029 [Byte1]: 65
1141 12:18:23.324461
1142 12:18:23.325025 Set Vref, RX VrefLevel [Byte0]: 66
1143 12:18:23.327591 [Byte1]: 66
1144 12:18:23.331517
1145 12:18:23.332082 Set Vref, RX VrefLevel [Byte0]: 67
1146 12:18:23.334652 [Byte1]: 67
1147 12:18:23.339364
1148 12:18:23.339940 Set Vref, RX VrefLevel [Byte0]: 68
1149 12:18:23.342501 [Byte1]: 68
1150 12:18:23.347153
1151 12:18:23.347721 Set Vref, RX VrefLevel [Byte0]: 69
1152 12:18:23.350450 [Byte1]: 69
1153 12:18:23.354703
1154 12:18:23.355276 Set Vref, RX VrefLevel [Byte0]: 70
1155 12:18:23.357838 [Byte1]: 70
1156 12:18:23.361884
1157 12:18:23.362497 Set Vref, RX VrefLevel [Byte0]: 71
1158 12:18:23.365052 [Byte1]: 71
1159 12:18:23.369571
1160 12:18:23.370189 Set Vref, RX VrefLevel [Byte0]: 72
1161 12:18:23.372842 [Byte1]: 72
1162 12:18:23.376620
1163 12:18:23.377091 Set Vref, RX VrefLevel [Byte0]: 73
1164 12:18:23.383494 [Byte1]: 73
1165 12:18:23.384072
1166 12:18:23.387472 Set Vref, RX VrefLevel [Byte0]: 74
1167 12:18:23.390232 [Byte1]: 74
1168 12:18:23.390805
1169 12:18:23.393663 Set Vref, RX VrefLevel [Byte0]: 75
1170 12:18:23.396633 [Byte1]: 75
1171 12:18:23.397111
1172 12:18:23.399930 Final RX Vref Byte 0 = 62 to rank0
1173 12:18:23.403603 Final RX Vref Byte 1 = 58 to rank0
1174 12:18:23.406608 Final RX Vref Byte 0 = 62 to rank1
1175 12:18:23.410206 Final RX Vref Byte 1 = 58 to rank1==
1176 12:18:23.413531 Dram Type= 6, Freq= 0, CH_0, rank 0
1177 12:18:23.417106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1178 12:18:23.417689 ==
1179 12:18:23.420145 DQS Delay:
1180 12:18:23.420726 DQS0 = 0, DQS1 = 0
1181 12:18:23.423758 DQM Delay:
1182 12:18:23.424331 DQM0 = 93, DQM1 = 83
1183 12:18:23.424706 DQ Delay:
1184 12:18:23.426754 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1185 12:18:23.429882 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1186 12:18:23.433755 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =80
1187 12:18:23.436688 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1188 12:18:23.437323
1189 12:18:23.437800
1190 12:18:23.446992 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e39, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1191 12:18:23.450289 CH0 RK0: MR19=606, MR18=3E39
1192 12:18:23.453440 CH0_RK0: MR19=0x606, MR18=0x3E39, DQSOSC=394, MR23=63, INC=95, DEC=63
1193 12:18:23.456566
1194 12:18:23.460218 ----->DramcWriteLeveling(PI) begin...
1195 12:18:23.460711 ==
1196 12:18:23.463507 Dram Type= 6, Freq= 0, CH_0, rank 1
1197 12:18:23.467128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1198 12:18:23.467595 ==
1199 12:18:23.470534 Write leveling (Byte 0): 31 => 31
1200 12:18:23.473525 Write leveling (Byte 1): 29 => 29
1201 12:18:23.476919 DramcWriteLeveling(PI) end<-----
1202 12:18:23.477384
1203 12:18:23.477751 ==
1204 12:18:23.480203 Dram Type= 6, Freq= 0, CH_0, rank 1
1205 12:18:23.484080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1206 12:18:23.484654 ==
1207 12:18:23.487842 [Gating] SW mode calibration
1208 12:18:23.493722 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1209 12:18:23.500335 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1210 12:18:23.504038 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1211 12:18:23.507036 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1212 12:18:23.510573 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1213 12:18:23.517152 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 12:18:23.520189 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 12:18:23.524225 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 12:18:23.530627 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 12:18:23.534032 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 12:18:23.537613 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 12:18:23.581391 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 12:18:23.582236 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 12:18:23.583010 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 12:18:23.583395 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 12:18:23.583748 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 12:18:23.584089 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 12:18:23.584418 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:18:23.584741 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:18:23.585059 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1228 12:18:23.585377 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:18:23.585897 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:18:23.592877 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 12:18:23.596080 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:18:23.599181 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 12:18:23.602513 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 12:18:23.609233 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 12:18:23.613149 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 12:18:23.615927 0 9 8 | B1->B0 | 3030 3434 | 0 0 | (0 0) (0 0)
1237 12:18:23.622707 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 12:18:23.626004 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 12:18:23.629064 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 12:18:23.636025 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 12:18:23.639418 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 12:18:23.642487 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1243 12:18:23.649868 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
1244 12:18:23.652664 0 10 8 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
1245 12:18:23.655975 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 12:18:23.662599 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 12:18:23.666146 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 12:18:23.669738 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 12:18:23.676524 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 12:18:23.679411 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 12:18:23.682759 0 11 4 | B1->B0 | 2424 3535 | 0 0 | (0 0) (0 0)
1252 12:18:23.686648 0 11 8 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
1253 12:18:23.693193 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 12:18:23.696171 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 12:18:23.699849 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 12:18:23.706107 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 12:18:23.709612 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 12:18:23.713547 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 12:18:23.716811 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1260 12:18:23.723665 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 12:18:23.727104 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 12:18:23.731122 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 12:18:23.734399 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 12:18:23.741192 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 12:18:23.745346 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 12:18:23.748592 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 12:18:23.754978 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 12:18:23.758463 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 12:18:23.762093 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 12:18:23.765760 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 12:18:23.772137 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 12:18:23.775660 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 12:18:23.778804 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 12:18:23.785934 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 12:18:23.789550 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1276 12:18:23.792508 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1277 12:18:23.798895 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 12:18:23.799460 Total UI for P1: 0, mck2ui 16
1279 12:18:23.806232 best dqsien dly found for B0: ( 0, 14, 6)
1280 12:18:23.806805 Total UI for P1: 0, mck2ui 16
1281 12:18:23.808993 best dqsien dly found for B1: ( 0, 14, 8)
1282 12:18:23.812414 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1283 12:18:23.818966 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1284 12:18:23.819431
1285 12:18:23.822456 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1286 12:18:23.826129 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1287 12:18:23.828912 [Gating] SW calibration Done
1288 12:18:23.829383 ==
1289 12:18:23.832296 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 12:18:23.835794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 12:18:23.836267 ==
1292 12:18:23.836640 RX Vref Scan: 0
1293 12:18:23.836985
1294 12:18:23.838968 RX Vref 0 -> 0, step: 1
1295 12:18:23.839437
1296 12:18:23.842712 RX Delay -130 -> 252, step: 16
1297 12:18:23.845891 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1298 12:18:23.849402 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1299 12:18:23.855536 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1300 12:18:23.859162 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1301 12:18:23.862291 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1302 12:18:23.866057 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1303 12:18:23.869269 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1304 12:18:23.876092 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1305 12:18:23.878891 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1306 12:18:23.882561 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1307 12:18:23.885412 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1308 12:18:23.889285 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1309 12:18:23.896112 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1310 12:18:23.899209 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1311 12:18:23.902679 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1312 12:18:23.906191 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1313 12:18:23.906799 ==
1314 12:18:23.909218 Dram Type= 6, Freq= 0, CH_0, rank 1
1315 12:18:23.915682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1316 12:18:23.916247 ==
1317 12:18:23.916624 DQS Delay:
1318 12:18:23.916969 DQS0 = 0, DQS1 = 0
1319 12:18:23.919421 DQM Delay:
1320 12:18:23.919993 DQM0 = 93, DQM1 = 81
1321 12:18:23.922685 DQ Delay:
1322 12:18:23.925876 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =77
1323 12:18:23.926496 DQ4 =93, DQ5 =77, DQ6 =109, DQ7 =109
1324 12:18:23.929235 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1325 12:18:23.935953 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
1326 12:18:23.936510
1327 12:18:23.936886
1328 12:18:23.937317 ==
1329 12:18:23.939313 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 12:18:23.942408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 12:18:23.942880 ==
1332 12:18:23.943277
1333 12:18:23.943632
1334 12:18:23.946004 TX Vref Scan disable
1335 12:18:23.946469 == TX Byte 0 ==
1336 12:18:23.952429 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1337 12:18:23.955777 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1338 12:18:23.956247 == TX Byte 1 ==
1339 12:18:23.962720 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1340 12:18:23.966113 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1341 12:18:23.966680 ==
1342 12:18:23.969387 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 12:18:23.972390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 12:18:23.972971 ==
1345 12:18:23.986690 TX Vref=22, minBit 13, minWin=26, winSum=439
1346 12:18:23.990368 TX Vref=24, minBit 8, minWin=27, winSum=446
1347 12:18:23.993413 TX Vref=26, minBit 8, minWin=27, winSum=450
1348 12:18:23.997000 TX Vref=28, minBit 8, minWin=27, winSum=452
1349 12:18:24.000077 TX Vref=30, minBit 9, minWin=27, winSum=453
1350 12:18:24.003217 TX Vref=32, minBit 8, minWin=27, winSum=453
1351 12:18:24.010468 [TxChooseVref] Worse bit 9, Min win 27, Win sum 453, Final Vref 30
1352 12:18:24.011046
1353 12:18:24.013564 Final TX Range 1 Vref 30
1354 12:18:24.014181
1355 12:18:24.014563 ==
1356 12:18:24.017019 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 12:18:24.019856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 12:18:24.020331 ==
1359 12:18:24.020703
1360 12:18:24.021041
1361 12:18:24.023724 TX Vref Scan disable
1362 12:18:24.026875 == TX Byte 0 ==
1363 12:18:24.029788 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1364 12:18:24.032945 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1365 12:18:24.036328 == TX Byte 1 ==
1366 12:18:24.039927 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1367 12:18:24.043198 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1368 12:18:24.043684
1369 12:18:24.046685 [DATLAT]
1370 12:18:24.047002 Freq=800, CH0 RK1
1371 12:18:24.047255
1372 12:18:24.050093 DATLAT Default: 0xa
1373 12:18:24.050508 0, 0xFFFF, sum = 0
1374 12:18:24.053144 1, 0xFFFF, sum = 0
1375 12:18:24.053472 2, 0xFFFF, sum = 0
1376 12:18:24.056588 3, 0xFFFF, sum = 0
1377 12:18:24.056914 4, 0xFFFF, sum = 0
1378 12:18:24.060146 5, 0xFFFF, sum = 0
1379 12:18:24.060480 6, 0xFFFF, sum = 0
1380 12:18:24.063825 7, 0xFFFF, sum = 0
1381 12:18:24.064253 8, 0xFFFF, sum = 0
1382 12:18:24.066693 9, 0x0, sum = 1
1383 12:18:24.067017 10, 0x0, sum = 2
1384 12:18:24.070028 11, 0x0, sum = 3
1385 12:18:24.070353 12, 0x0, sum = 4
1386 12:18:24.073440 best_step = 10
1387 12:18:24.073860
1388 12:18:24.074172 ==
1389 12:18:24.076873 Dram Type= 6, Freq= 0, CH_0, rank 1
1390 12:18:24.080087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1391 12:18:24.080512 ==
1392 12:18:24.083551 RX Vref Scan: 0
1393 12:18:24.084005
1394 12:18:24.084264 RX Vref 0 -> 0, step: 1
1395 12:18:24.084504
1396 12:18:24.086856 RX Delay -79 -> 252, step: 8
1397 12:18:24.090191 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1398 12:18:24.096953 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1399 12:18:24.101234 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1400 12:18:24.103978 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1401 12:18:24.106945 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1402 12:18:24.110308 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1403 12:18:24.117229 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1404 12:18:24.120567 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1405 12:18:24.124066 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1406 12:18:24.127232 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1407 12:18:24.130508 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1408 12:18:24.136864 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1409 12:18:24.140408 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1410 12:18:24.143586 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1411 12:18:24.147211 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1412 12:18:24.150369 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1413 12:18:24.153672 ==
1414 12:18:24.156751 Dram Type= 6, Freq= 0, CH_0, rank 1
1415 12:18:24.160285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1416 12:18:24.160746 ==
1417 12:18:24.161106 DQS Delay:
1418 12:18:24.164230 DQS0 = 0, DQS1 = 0
1419 12:18:24.164792 DQM Delay:
1420 12:18:24.167118 DQM0 = 91, DQM1 = 83
1421 12:18:24.167714 DQ Delay:
1422 12:18:24.170606 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =84
1423 12:18:24.173891 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1424 12:18:24.177405 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1425 12:18:24.180811 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1426 12:18:24.181368
1427 12:18:24.181731
1428 12:18:24.187845 [DQSOSCAuto] RK1, (LSB)MR18= 0x411c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1429 12:18:24.190216 CH0 RK1: MR19=606, MR18=411C
1430 12:18:24.197472 CH0_RK1: MR19=0x606, MR18=0x411C, DQSOSC=393, MR23=63, INC=95, DEC=63
1431 12:18:24.200526 [RxdqsGatingPostProcess] freq 800
1432 12:18:24.204121 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1433 12:18:24.206800 Pre-setting of DQS Precalculation
1434 12:18:24.213899 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1435 12:18:24.214498 ==
1436 12:18:24.217498 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 12:18:24.220547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 12:18:24.221105 ==
1439 12:18:24.227280 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1440 12:18:24.233901 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1441 12:18:24.241470 [CA 0] Center 36 (6~67) winsize 62
1442 12:18:24.244981 [CA 1] Center 36 (6~67) winsize 62
1443 12:18:24.247963 [CA 2] Center 34 (4~65) winsize 62
1444 12:18:24.251464 [CA 3] Center 34 (3~65) winsize 63
1445 12:18:24.254616 [CA 4] Center 34 (4~65) winsize 62
1446 12:18:24.258279 [CA 5] Center 33 (3~64) winsize 62
1447 12:18:24.258744
1448 12:18:24.261243 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1449 12:18:24.261892
1450 12:18:24.264844 [CATrainingPosCal] consider 1 rank data
1451 12:18:24.268177 u2DelayCellTimex100 = 270/100 ps
1452 12:18:24.271730 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1453 12:18:24.274645 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1454 12:18:24.281763 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1455 12:18:24.284828 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1456 12:18:24.288477 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1457 12:18:24.291675 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1458 12:18:24.292239
1459 12:18:24.295071 CA PerBit enable=1, Macro0, CA PI delay=33
1460 12:18:24.295639
1461 12:18:24.298597 [CBTSetCACLKResult] CA Dly = 33
1462 12:18:24.299170 CS Dly: 5 (0~36)
1463 12:18:24.299549 ==
1464 12:18:24.301509 Dram Type= 6, Freq= 0, CH_1, rank 1
1465 12:18:24.308295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1466 12:18:24.308853 ==
1467 12:18:24.311996 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1468 12:18:24.318106 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1469 12:18:24.327765 [CA 0] Center 36 (6~67) winsize 62
1470 12:18:24.330816 [CA 1] Center 37 (6~68) winsize 63
1471 12:18:24.334223 [CA 2] Center 35 (5~66) winsize 62
1472 12:18:24.337832 [CA 3] Center 34 (4~65) winsize 62
1473 12:18:24.341451 [CA 4] Center 34 (4~65) winsize 62
1474 12:18:24.343796 [CA 5] Center 34 (4~64) winsize 61
1475 12:18:24.344265
1476 12:18:24.347507 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1477 12:18:24.348086
1478 12:18:24.350614 [CATrainingPosCal] consider 2 rank data
1479 12:18:24.354163 u2DelayCellTimex100 = 270/100 ps
1480 12:18:24.357161 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1481 12:18:24.364142 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1482 12:18:24.367356 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1483 12:18:24.370791 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1484 12:18:24.373683 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1485 12:18:24.377351 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1486 12:18:24.377919
1487 12:18:24.381199 CA PerBit enable=1, Macro0, CA PI delay=34
1488 12:18:24.381773
1489 12:18:24.384642 [CBTSetCACLKResult] CA Dly = 34
1490 12:18:24.385217 CS Dly: 6 (0~38)
1491 12:18:24.385601
1492 12:18:24.388311 ----->DramcWriteLeveling(PI) begin...
1493 12:18:24.388905 ==
1494 12:18:24.391787 Dram Type= 6, Freq= 0, CH_1, rank 0
1495 12:18:24.396466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1496 12:18:24.397037 ==
1497 12:18:24.399602 Write leveling (Byte 0): 26 => 26
1498 12:18:24.403643 Write leveling (Byte 1): 28 => 28
1499 12:18:24.407405 DramcWriteLeveling(PI) end<-----
1500 12:18:24.408030
1501 12:18:24.408437 ==
1502 12:18:24.411232 Dram Type= 6, Freq= 0, CH_1, rank 0
1503 12:18:24.415142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1504 12:18:24.415708 ==
1505 12:18:24.418419 [Gating] SW mode calibration
1506 12:18:24.425036 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1507 12:18:24.427975 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1508 12:18:24.435077 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1509 12:18:24.438376 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1510 12:18:24.441835 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 12:18:24.445001 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 12:18:24.451890 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 12:18:24.454881 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 12:18:24.458391 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 12:18:24.465214 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 12:18:24.468287 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 12:18:24.471610 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 12:18:24.478429 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 12:18:24.481755 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 12:18:24.484870 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 12:18:24.491518 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 12:18:24.494758 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 12:18:24.498464 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 12:18:24.505591 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1525 12:18:24.508494 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1526 12:18:24.511914 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1527 12:18:24.518380 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 12:18:24.521839 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 12:18:24.525365 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 12:18:24.528121 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 12:18:24.535277 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 12:18:24.538426 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 12:18:24.542271 0 9 4 | B1->B0 | 2525 3231 | 0 1 | (0 0) (1 1)
1534 12:18:24.548643 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 12:18:24.551674 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 12:18:24.555344 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 12:18:24.561769 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 12:18:24.565287 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 12:18:24.568681 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 12:18:24.574646 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1541 12:18:24.578055 0 10 4 | B1->B0 | 2f2f 2a2a | 0 0 | (0 1) (1 1)
1542 12:18:24.581459 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 12:18:24.588243 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 12:18:24.591580 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 12:18:24.595107 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 12:18:24.601471 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 12:18:24.605158 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 12:18:24.608626 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 12:18:24.611751 0 11 4 | B1->B0 | 2e2e 3b3b | 0 0 | (0 0) (0 0)
1550 12:18:24.618638 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1551 12:18:24.622027 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 12:18:24.625238 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 12:18:24.631615 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 12:18:24.635262 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 12:18:24.638343 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 12:18:24.645036 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 12:18:24.648803 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1558 12:18:24.652074 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 12:18:24.658807 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 12:18:24.661934 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 12:18:24.665687 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 12:18:24.671920 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 12:18:24.675223 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 12:18:24.678574 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 12:18:24.685325 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 12:18:24.688754 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 12:18:24.691834 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 12:18:24.698567 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 12:18:24.702080 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 12:18:24.705207 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 12:18:24.708848 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 12:18:24.715224 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 12:18:24.718734 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 12:18:24.721843 Total UI for P1: 0, mck2ui 16
1575 12:18:24.725173 best dqsien dly found for B0: ( 0, 14, 2)
1576 12:18:24.728306 Total UI for P1: 0, mck2ui 16
1577 12:18:24.732154 best dqsien dly found for B1: ( 0, 14, 2)
1578 12:18:24.735371 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1579 12:18:24.738414 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1580 12:18:24.738885
1581 12:18:24.741807 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1582 12:18:24.745576 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1583 12:18:24.748963 [Gating] SW calibration Done
1584 12:18:24.749532 ==
1585 12:18:24.752104 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 12:18:24.755227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 12:18:24.758437 ==
1588 12:18:24.758912 RX Vref Scan: 0
1589 12:18:24.759281
1590 12:18:24.761855 RX Vref 0 -> 0, step: 1
1591 12:18:24.762354
1592 12:18:24.765197 RX Delay -130 -> 252, step: 16
1593 12:18:24.768740 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1594 12:18:24.771860 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1595 12:18:24.775213 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1596 12:18:24.778542 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1597 12:18:24.784989 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1598 12:18:24.788200 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1599 12:18:24.791964 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1600 12:18:24.795183 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1601 12:18:24.798436 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1602 12:18:24.805506 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1603 12:18:24.808885 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1604 12:18:24.811955 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1605 12:18:24.815133 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1606 12:18:24.819602 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1607 12:18:24.825578 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1608 12:18:24.828905 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1609 12:18:24.829498 ==
1610 12:18:24.831968 Dram Type= 6, Freq= 0, CH_1, rank 0
1611 12:18:24.835254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1612 12:18:24.835823 ==
1613 12:18:24.836200 DQS Delay:
1614 12:18:24.838678 DQS0 = 0, DQS1 = 0
1615 12:18:24.839149 DQM Delay:
1616 12:18:24.841976 DQM0 = 92, DQM1 = 80
1617 12:18:24.842415 DQ Delay:
1618 12:18:24.845500 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1619 12:18:24.848713 DQ4 =93, DQ5 =101, DQ6 =101, DQ7 =85
1620 12:18:24.852443 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1621 12:18:24.856090 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1622 12:18:24.856665
1623 12:18:24.857066
1624 12:18:24.857691 ==
1625 12:18:24.858615 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 12:18:24.865680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 12:18:24.866292 ==
1628 12:18:24.866681
1629 12:18:24.867030
1630 12:18:24.867368 TX Vref Scan disable
1631 12:18:24.868343 == TX Byte 0 ==
1632 12:18:24.872173 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1633 12:18:24.878793 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1634 12:18:24.879385 == TX Byte 1 ==
1635 12:18:24.882014 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1636 12:18:24.885375 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1637 12:18:24.888584 ==
1638 12:18:24.892462 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 12:18:24.895085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 12:18:24.895581 ==
1641 12:18:24.908136 TX Vref=22, minBit 8, minWin=27, winSum=449
1642 12:18:24.911407 TX Vref=24, minBit 10, minWin=27, winSum=451
1643 12:18:24.914701 TX Vref=26, minBit 10, minWin=27, winSum=456
1644 12:18:24.917608 TX Vref=28, minBit 15, minWin=27, winSum=457
1645 12:18:24.921120 TX Vref=30, minBit 8, minWin=28, winSum=459
1646 12:18:24.928048 TX Vref=32, minBit 11, minWin=27, winSum=458
1647 12:18:24.931648 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
1648 12:18:24.932141
1649 12:18:24.934660 Final TX Range 1 Vref 30
1650 12:18:24.935145
1651 12:18:24.935513 ==
1652 12:18:24.937681 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 12:18:24.941414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 12:18:24.944486 ==
1655 12:18:24.945096
1656 12:18:24.945474
1657 12:18:24.945819 TX Vref Scan disable
1658 12:18:24.947886 == TX Byte 0 ==
1659 12:18:24.951229 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1660 12:18:24.954859 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1661 12:18:24.957713 == TX Byte 1 ==
1662 12:18:24.961598 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1663 12:18:24.965238 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1664 12:18:24.965798
1665 12:18:24.968483 [DATLAT]
1666 12:18:24.969058 Freq=800, CH1 RK0
1667 12:18:24.969430
1668 12:18:24.972250 DATLAT Default: 0xa
1669 12:18:24.972810 0, 0xFFFF, sum = 0
1670 12:18:24.975576 1, 0xFFFF, sum = 0
1671 12:18:24.976148 2, 0xFFFF, sum = 0
1672 12:18:24.978495 3, 0xFFFF, sum = 0
1673 12:18:24.978986 4, 0xFFFF, sum = 0
1674 12:18:24.981872 5, 0xFFFF, sum = 0
1675 12:18:24.982364 6, 0xFFFF, sum = 0
1676 12:18:24.985634 7, 0xFFFF, sum = 0
1677 12:18:24.986248 8, 0xFFFF, sum = 0
1678 12:18:24.988610 9, 0x0, sum = 1
1679 12:18:24.989078 10, 0x0, sum = 2
1680 12:18:24.992397 11, 0x0, sum = 3
1681 12:18:24.992865 12, 0x0, sum = 4
1682 12:18:24.995596 best_step = 10
1683 12:18:24.996176
1684 12:18:24.996546 ==
1685 12:18:24.998919 Dram Type= 6, Freq= 0, CH_1, rank 0
1686 12:18:25.001902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1687 12:18:25.002405 ==
1688 12:18:25.002781 RX Vref Scan: 1
1689 12:18:25.003128
1690 12:18:25.005742 Set Vref Range= 32 -> 127
1691 12:18:25.006244
1692 12:18:25.008676 RX Vref 32 -> 127, step: 1
1693 12:18:25.009242
1694 12:18:25.011801 RX Delay -95 -> 252, step: 8
1695 12:18:25.012267
1696 12:18:25.015382 Set Vref, RX VrefLevel [Byte0]: 32
1697 12:18:25.018596 [Byte1]: 32
1698 12:18:25.019163
1699 12:18:25.022503 Set Vref, RX VrefLevel [Byte0]: 33
1700 12:18:25.025141 [Byte1]: 33
1701 12:18:25.025604
1702 12:18:25.028297 Set Vref, RX VrefLevel [Byte0]: 34
1703 12:18:25.031589 [Byte1]: 34
1704 12:18:25.035936
1705 12:18:25.036504 Set Vref, RX VrefLevel [Byte0]: 35
1706 12:18:25.038929 [Byte1]: 35
1707 12:18:25.043331
1708 12:18:25.043800 Set Vref, RX VrefLevel [Byte0]: 36
1709 12:18:25.046783 [Byte1]: 36
1710 12:18:25.051330
1711 12:18:25.051898 Set Vref, RX VrefLevel [Byte0]: 37
1712 12:18:25.054537 [Byte1]: 37
1713 12:18:25.058287
1714 12:18:25.058838 Set Vref, RX VrefLevel [Byte0]: 38
1715 12:18:25.062116 [Byte1]: 38
1716 12:18:25.066586
1717 12:18:25.067155 Set Vref, RX VrefLevel [Byte0]: 39
1718 12:18:25.069876 [Byte1]: 39
1719 12:18:25.073794
1720 12:18:25.074307 Set Vref, RX VrefLevel [Byte0]: 40
1721 12:18:25.077034 [Byte1]: 40
1722 12:18:25.081742
1723 12:18:25.082345 Set Vref, RX VrefLevel [Byte0]: 41
1724 12:18:25.084873 [Byte1]: 41
1725 12:18:25.089250
1726 12:18:25.089815 Set Vref, RX VrefLevel [Byte0]: 42
1727 12:18:25.092483 [Byte1]: 42
1728 12:18:25.096442
1729 12:18:25.096908 Set Vref, RX VrefLevel [Byte0]: 43
1730 12:18:25.099700 [Byte1]: 43
1731 12:18:25.104206
1732 12:18:25.104769 Set Vref, RX VrefLevel [Byte0]: 44
1733 12:18:25.107623 [Byte1]: 44
1734 12:18:25.112074
1735 12:18:25.112541 Set Vref, RX VrefLevel [Byte0]: 45
1736 12:18:25.114890 [Byte1]: 45
1737 12:18:25.119271
1738 12:18:25.119838 Set Vref, RX VrefLevel [Byte0]: 46
1739 12:18:25.122891 [Byte1]: 46
1740 12:18:25.126807
1741 12:18:25.127286 Set Vref, RX VrefLevel [Byte0]: 47
1742 12:18:25.130313 [Byte1]: 47
1743 12:18:25.134609
1744 12:18:25.135075 Set Vref, RX VrefLevel [Byte0]: 48
1745 12:18:25.141434 [Byte1]: 48
1746 12:18:25.142046
1747 12:18:25.144718 Set Vref, RX VrefLevel [Byte0]: 49
1748 12:18:25.148157 [Byte1]: 49
1749 12:18:25.148719
1750 12:18:25.150967 Set Vref, RX VrefLevel [Byte0]: 50
1751 12:18:25.154769 [Byte1]: 50
1752 12:18:25.155334
1753 12:18:25.157647 Set Vref, RX VrefLevel [Byte0]: 51
1754 12:18:25.161453 [Byte1]: 51
1755 12:18:25.165248
1756 12:18:25.165809 Set Vref, RX VrefLevel [Byte0]: 52
1757 12:18:25.168847 [Byte1]: 52
1758 12:18:25.172846
1759 12:18:25.173410 Set Vref, RX VrefLevel [Byte0]: 53
1760 12:18:25.175984 [Byte1]: 53
1761 12:18:25.180458
1762 12:18:25.180946 Set Vref, RX VrefLevel [Byte0]: 54
1763 12:18:25.183156 [Byte1]: 54
1764 12:18:25.187971
1765 12:18:25.188549 Set Vref, RX VrefLevel [Byte0]: 55
1766 12:18:25.191362 [Byte1]: 55
1767 12:18:25.195300
1768 12:18:25.195874 Set Vref, RX VrefLevel [Byte0]: 56
1769 12:18:25.198501 [Byte1]: 56
1770 12:18:25.203011
1771 12:18:25.203586 Set Vref, RX VrefLevel [Byte0]: 57
1772 12:18:25.206043 [Byte1]: 57
1773 12:18:25.210486
1774 12:18:25.210966 Set Vref, RX VrefLevel [Byte0]: 58
1775 12:18:25.214143 [Byte1]: 58
1776 12:18:25.218667
1777 12:18:25.219259 Set Vref, RX VrefLevel [Byte0]: 59
1778 12:18:25.221508 [Byte1]: 59
1779 12:18:25.225519
1780 12:18:25.226039 Set Vref, RX VrefLevel [Byte0]: 60
1781 12:18:25.229206 [Byte1]: 60
1782 12:18:25.233435
1783 12:18:25.233922 Set Vref, RX VrefLevel [Byte0]: 61
1784 12:18:25.239636 [Byte1]: 61
1785 12:18:25.240200
1786 12:18:25.243061 Set Vref, RX VrefLevel [Byte0]: 62
1787 12:18:25.246489 [Byte1]: 62
1788 12:18:25.247073
1789 12:18:25.249728 Set Vref, RX VrefLevel [Byte0]: 63
1790 12:18:25.253577 [Byte1]: 63
1791 12:18:25.254192
1792 12:18:25.256624 Set Vref, RX VrefLevel [Byte0]: 64
1793 12:18:25.259692 [Byte1]: 64
1794 12:18:25.263964
1795 12:18:25.264528 Set Vref, RX VrefLevel [Byte0]: 65
1796 12:18:25.267413 [Byte1]: 65
1797 12:18:25.271487
1798 12:18:25.272047 Set Vref, RX VrefLevel [Byte0]: 66
1799 12:18:25.274438 [Byte1]: 66
1800 12:18:25.279163
1801 12:18:25.279742 Set Vref, RX VrefLevel [Byte0]: 67
1802 12:18:25.282457 [Byte1]: 67
1803 12:18:25.286844
1804 12:18:25.287402 Set Vref, RX VrefLevel [Byte0]: 68
1805 12:18:25.289754 [Byte1]: 68
1806 12:18:25.294369
1807 12:18:25.294926 Set Vref, RX VrefLevel [Byte0]: 69
1808 12:18:25.297375 [Byte1]: 69
1809 12:18:25.301927
1810 12:18:25.302521 Set Vref, RX VrefLevel [Byte0]: 70
1811 12:18:25.305213 [Byte1]: 70
1812 12:18:25.309501
1813 12:18:25.310100 Set Vref, RX VrefLevel [Byte0]: 71
1814 12:18:25.312652 [Byte1]: 71
1815 12:18:25.316829
1816 12:18:25.317483 Set Vref, RX VrefLevel [Byte0]: 72
1817 12:18:25.319883 [Byte1]: 72
1818 12:18:25.324301
1819 12:18:25.324860 Set Vref, RX VrefLevel [Byte0]: 73
1820 12:18:25.327671 [Byte1]: 73
1821 12:18:25.332076
1822 12:18:25.332534 Set Vref, RX VrefLevel [Byte0]: 74
1823 12:18:25.335193 [Byte1]: 74
1824 12:18:25.339711
1825 12:18:25.340171 Set Vref, RX VrefLevel [Byte0]: 75
1826 12:18:25.343075 [Byte1]: 75
1827 12:18:25.347214
1828 12:18:25.347776 Set Vref, RX VrefLevel [Byte0]: 76
1829 12:18:25.350544 [Byte1]: 76
1830 12:18:25.354800
1831 12:18:25.355361 Set Vref, RX VrefLevel [Byte0]: 77
1832 12:18:25.358577 [Byte1]: 77
1833 12:18:25.362243
1834 12:18:25.362705 Set Vref, RX VrefLevel [Byte0]: 78
1835 12:18:25.365685 [Byte1]: 78
1836 12:18:25.370314
1837 12:18:25.370875 Set Vref, RX VrefLevel [Byte0]: 79
1838 12:18:25.373444 [Byte1]: 79
1839 12:18:25.377897
1840 12:18:25.378494 Set Vref, RX VrefLevel [Byte0]: 80
1841 12:18:25.381117 [Byte1]: 80
1842 12:18:25.385066
1843 12:18:25.385529 Final RX Vref Byte 0 = 52 to rank0
1844 12:18:25.388788 Final RX Vref Byte 1 = 61 to rank0
1845 12:18:25.392203 Final RX Vref Byte 0 = 52 to rank1
1846 12:18:25.395310 Final RX Vref Byte 1 = 61 to rank1==
1847 12:18:25.398752 Dram Type= 6, Freq= 0, CH_1, rank 0
1848 12:18:25.405206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1849 12:18:25.405779 ==
1850 12:18:25.406236 DQS Delay:
1851 12:18:25.406601 DQS0 = 0, DQS1 = 0
1852 12:18:25.408916 DQM Delay:
1853 12:18:25.409475 DQM0 = 93, DQM1 = 82
1854 12:18:25.412090 DQ Delay:
1855 12:18:25.415441 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1856 12:18:25.418502 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1857 12:18:25.422193 DQ8 =72, DQ9 =68, DQ10 =88, DQ11 =76
1858 12:18:25.425124 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1859 12:18:25.425688
1860 12:18:25.426107
1861 12:18:25.431646 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 399 ps
1862 12:18:25.435140 CH1 RK0: MR19=606, MR18=2A48
1863 12:18:25.442138 CH1_RK0: MR19=0x606, MR18=0x2A48, DQSOSC=391, MR23=63, INC=96, DEC=64
1864 12:18:25.442748
1865 12:18:25.445035 ----->DramcWriteLeveling(PI) begin...
1866 12:18:25.445508 ==
1867 12:18:25.448607 Dram Type= 6, Freq= 0, CH_1, rank 1
1868 12:18:25.452113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1869 12:18:25.452696 ==
1870 12:18:25.455134 Write leveling (Byte 0): 27 => 27
1871 12:18:25.458882 Write leveling (Byte 1): 33 => 33
1872 12:18:25.462063 DramcWriteLeveling(PI) end<-----
1873 12:18:25.462533
1874 12:18:25.462904 ==
1875 12:18:25.465670 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 12:18:25.468556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1877 12:18:25.469118 ==
1878 12:18:25.472144 [Gating] SW mode calibration
1879 12:18:25.478503 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1880 12:18:25.485473 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1881 12:18:25.488903 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1882 12:18:25.491869 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1883 12:18:25.498520 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1884 12:18:25.501833 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 12:18:25.505109 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 12:18:25.511696 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 12:18:25.515104 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 12:18:25.518437 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 12:18:25.525356 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 12:18:25.528243 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 12:18:25.531970 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 12:18:25.538537 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 12:18:25.541670 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 12:18:25.545221 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 12:18:25.549200 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 12:18:25.555063 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 12:18:25.558572 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 12:18:25.562267 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1899 12:18:25.568571 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1900 12:18:25.572091 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 12:18:25.575398 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 12:18:25.582162 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 12:18:25.585252 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 12:18:25.588833 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 12:18:25.595759 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 12:18:25.598775 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 12:18:25.602531 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1908 12:18:25.608860 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 12:18:25.611850 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 12:18:25.615292 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 12:18:25.621866 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 12:18:25.625323 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 12:18:25.628540 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 12:18:25.635411 0 10 4 | B1->B0 | 2f2f 3232 | 0 1 | (0 0) (1 0)
1915 12:18:25.638650 0 10 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 0)
1916 12:18:25.641859 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 12:18:25.645474 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 12:18:25.651887 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 12:18:25.655385 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 12:18:25.658959 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 12:18:25.665570 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 12:18:25.669089 0 11 4 | B1->B0 | 3333 3232 | 0 1 | (0 0) (0 0)
1923 12:18:25.672377 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 12:18:25.679051 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 12:18:25.682009 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 12:18:25.685658 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 12:18:25.692351 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 12:18:25.695711 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 12:18:25.699311 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 12:18:25.705532 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1931 12:18:25.708960 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1932 12:18:25.712064 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 12:18:25.715502 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 12:18:25.722482 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 12:18:25.725598 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 12:18:25.729111 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 12:18:25.735600 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 12:18:25.738867 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 12:18:25.742559 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 12:18:25.749070 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 12:18:25.752296 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 12:18:25.756371 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 12:18:25.762561 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 12:18:25.765820 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 12:18:25.769193 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 12:18:25.775905 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1947 12:18:25.779125 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1948 12:18:25.782344 Total UI for P1: 0, mck2ui 16
1949 12:18:25.786180 best dqsien dly found for B0: ( 0, 14, 4)
1950 12:18:25.790011 Total UI for P1: 0, mck2ui 16
1951 12:18:25.793104 best dqsien dly found for B1: ( 0, 14, 4)
1952 12:18:25.796061 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1953 12:18:25.799788 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1954 12:18:25.800363
1955 12:18:25.802581 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1956 12:18:25.806371 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1957 12:18:25.809372 [Gating] SW calibration Done
1958 12:18:25.809976 ==
1959 12:18:25.812888 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 12:18:25.816022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 12:18:25.816500 ==
1962 12:18:25.819212 RX Vref Scan: 0
1963 12:18:25.819779
1964 12:18:25.820154 RX Vref 0 -> 0, step: 1
1965 12:18:25.820508
1966 12:18:25.822756 RX Delay -130 -> 252, step: 16
1967 12:18:25.829622 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1968 12:18:25.832564 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1969 12:18:25.835843 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1970 12:18:25.839557 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1971 12:18:25.843070 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1972 12:18:25.846087 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1973 12:18:25.852669 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1974 12:18:25.856197 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1975 12:18:25.859336 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1976 12:18:25.862421 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1977 12:18:25.865745 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1978 12:18:25.872578 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1979 12:18:25.875801 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1980 12:18:25.879492 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1981 12:18:25.882670 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1982 12:18:25.886235 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1983 12:18:25.889221 ==
1984 12:18:25.892903 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 12:18:25.896015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 12:18:25.896553 ==
1987 12:18:25.896897 DQS Delay:
1988 12:18:25.899627 DQS0 = 0, DQS1 = 0
1989 12:18:25.900157 DQM Delay:
1990 12:18:25.902845 DQM0 = 89, DQM1 = 81
1991 12:18:25.903383 DQ Delay:
1992 12:18:25.906090 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1993 12:18:25.909660 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1994 12:18:25.912898 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1995 12:18:25.916259 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1996 12:18:25.916791
1997 12:18:25.917132
1998 12:18:25.917449 ==
1999 12:18:25.919381 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 12:18:25.922843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 12:18:25.923379 ==
2002 12:18:25.923723
2003 12:18:25.924039
2004 12:18:25.926139 TX Vref Scan disable
2005 12:18:25.929556 == TX Byte 0 ==
2006 12:18:25.932868 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2007 12:18:25.936398 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2008 12:18:25.939695 == TX Byte 1 ==
2009 12:18:25.943121 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
2010 12:18:25.946143 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
2011 12:18:25.946671 ==
2012 12:18:25.950032 Dram Type= 6, Freq= 0, CH_1, rank 1
2013 12:18:25.953308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2014 12:18:25.953840 ==
2015 12:18:25.968088 TX Vref=22, minBit 8, minWin=27, winSum=449
2016 12:18:25.971078 TX Vref=24, minBit 9, minWin=27, winSum=452
2017 12:18:25.974703 TX Vref=26, minBit 9, minWin=27, winSum=453
2018 12:18:25.978189 TX Vref=28, minBit 8, minWin=28, winSum=458
2019 12:18:25.981142 TX Vref=30, minBit 8, minWin=28, winSum=459
2020 12:18:25.984977 TX Vref=32, minBit 9, minWin=27, winSum=458
2021 12:18:25.991603 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
2022 12:18:25.992157
2023 12:18:25.994945 Final TX Range 1 Vref 30
2024 12:18:25.995510
2025 12:18:25.995884 ==
2026 12:18:25.998092 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 12:18:26.001682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 12:18:26.002288 ==
2029 12:18:26.002664
2030 12:18:26.003028
2031 12:18:26.005199 TX Vref Scan disable
2032 12:18:26.008258 == TX Byte 0 ==
2033 12:18:26.011456 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2034 12:18:26.014930 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2035 12:18:26.018573 == TX Byte 1 ==
2036 12:18:26.021503 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
2037 12:18:26.024804 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
2038 12:18:26.025368
2039 12:18:26.028126 [DATLAT]
2040 12:18:26.028594 Freq=800, CH1 RK1
2041 12:18:26.028969
2042 12:18:26.031493 DATLAT Default: 0xa
2043 12:18:26.032023 0, 0xFFFF, sum = 0
2044 12:18:26.035252 1, 0xFFFF, sum = 0
2045 12:18:26.035729 2, 0xFFFF, sum = 0
2046 12:18:26.038321 3, 0xFFFF, sum = 0
2047 12:18:26.038893 4, 0xFFFF, sum = 0
2048 12:18:26.041451 5, 0xFFFF, sum = 0
2049 12:18:26.041930 6, 0xFFFF, sum = 0
2050 12:18:26.045440 7, 0xFFFF, sum = 0
2051 12:18:26.046040 8, 0xFFFF, sum = 0
2052 12:18:26.048108 9, 0x0, sum = 1
2053 12:18:26.048587 10, 0x0, sum = 2
2054 12:18:26.052063 11, 0x0, sum = 3
2055 12:18:26.052652 12, 0x0, sum = 4
2056 12:18:26.054615 best_step = 10
2057 12:18:26.055081
2058 12:18:26.055447 ==
2059 12:18:26.058862 Dram Type= 6, Freq= 0, CH_1, rank 1
2060 12:18:26.061814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2061 12:18:26.062438 ==
2062 12:18:26.062824 RX Vref Scan: 0
2063 12:18:26.064828
2064 12:18:26.065286 RX Vref 0 -> 0, step: 1
2065 12:18:26.065672
2066 12:18:26.068657 RX Delay -95 -> 252, step: 8
2067 12:18:26.071479 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2068 12:18:26.078866 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2069 12:18:26.082004 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2070 12:18:26.084865 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2071 12:18:26.088205 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2072 12:18:26.091927 iDelay=209, Bit 5, Center 104 (1 ~ 208) 208
2073 12:18:26.098359 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2074 12:18:26.101837 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2075 12:18:26.105325 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2076 12:18:26.108364 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2077 12:18:26.112066 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2078 12:18:26.118804 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2079 12:18:26.122198 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2080 12:18:26.125338 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2081 12:18:26.128234 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2082 12:18:26.131867 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2083 12:18:26.132464 ==
2084 12:18:26.135172 Dram Type= 6, Freq= 0, CH_1, rank 1
2085 12:18:26.141918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2086 12:18:26.142539 ==
2087 12:18:26.142917 DQS Delay:
2088 12:18:26.145224 DQS0 = 0, DQS1 = 0
2089 12:18:26.145688 DQM Delay:
2090 12:18:26.146091 DQM0 = 91, DQM1 = 84
2091 12:18:26.148330 DQ Delay:
2092 12:18:26.151687 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2093 12:18:26.155161 DQ4 =92, DQ5 =104, DQ6 =96, DQ7 =88
2094 12:18:26.158418 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2095 12:18:26.161993 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96
2096 12:18:26.162563
2097 12:18:26.162935
2098 12:18:26.168442 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b0f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
2099 12:18:26.172241 CH1 RK1: MR19=606, MR18=3B0F
2100 12:18:26.178264 CH1_RK1: MR19=0x606, MR18=0x3B0F, DQSOSC=394, MR23=63, INC=95, DEC=63
2101 12:18:26.181579 [RxdqsGatingPostProcess] freq 800
2102 12:18:26.185441 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2103 12:18:26.188668 Pre-setting of DQS Precalculation
2104 12:18:26.195240 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2105 12:18:26.201673 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2106 12:18:26.208555 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2107 12:18:26.209149
2108 12:18:26.209525
2109 12:18:26.211950 [Calibration Summary] 1600 Mbps
2110 12:18:26.212515 CH 0, Rank 0
2111 12:18:26.215488 SW Impedance : PASS
2112 12:18:26.218345 DUTY Scan : NO K
2113 12:18:26.218913 ZQ Calibration : PASS
2114 12:18:26.221800 Jitter Meter : NO K
2115 12:18:26.225352 CBT Training : PASS
2116 12:18:26.225914 Write leveling : PASS
2117 12:18:26.228698 RX DQS gating : PASS
2118 12:18:26.231439 RX DQ/DQS(RDDQC) : PASS
2119 12:18:26.231904 TX DQ/DQS : PASS
2120 12:18:26.235059 RX DATLAT : PASS
2121 12:18:26.238685 RX DQ/DQS(Engine): PASS
2122 12:18:26.239254 TX OE : NO K
2123 12:18:26.239629 All Pass.
2124 12:18:26.239971
2125 12:18:26.241721 CH 0, Rank 1
2126 12:18:26.242229 SW Impedance : PASS
2127 12:18:26.245372 DUTY Scan : NO K
2128 12:18:26.248592 ZQ Calibration : PASS
2129 12:18:26.249162 Jitter Meter : NO K
2130 12:18:26.251813 CBT Training : PASS
2131 12:18:26.255157 Write leveling : PASS
2132 12:18:26.255726 RX DQS gating : PASS
2133 12:18:26.258516 RX DQ/DQS(RDDQC) : PASS
2134 12:18:26.262123 TX DQ/DQS : PASS
2135 12:18:26.262711 RX DATLAT : PASS
2136 12:18:26.264973 RX DQ/DQS(Engine): PASS
2137 12:18:26.268477 TX OE : NO K
2138 12:18:26.269038 All Pass.
2139 12:18:26.269404
2140 12:18:26.269745 CH 1, Rank 0
2141 12:18:26.272374 SW Impedance : PASS
2142 12:18:26.275217 DUTY Scan : NO K
2143 12:18:26.275716 ZQ Calibration : PASS
2144 12:18:26.278558 Jitter Meter : NO K
2145 12:18:26.281620 CBT Training : PASS
2146 12:18:26.282134 Write leveling : PASS
2147 12:18:26.285183 RX DQS gating : PASS
2148 12:18:26.285763 RX DQ/DQS(RDDQC) : PASS
2149 12:18:26.288661 TX DQ/DQS : PASS
2150 12:18:26.291605 RX DATLAT : PASS
2151 12:18:26.292081 RX DQ/DQS(Engine): PASS
2152 12:18:26.295158 TX OE : NO K
2153 12:18:26.295635 All Pass.
2154 12:18:26.296114
2155 12:18:26.298399 CH 1, Rank 1
2156 12:18:26.298874 SW Impedance : PASS
2157 12:18:26.302109 DUTY Scan : NO K
2158 12:18:26.305526 ZQ Calibration : PASS
2159 12:18:26.306146 Jitter Meter : NO K
2160 12:18:26.308680 CBT Training : PASS
2161 12:18:26.311987 Write leveling : PASS
2162 12:18:26.312462 RX DQS gating : PASS
2163 12:18:26.314978 RX DQ/DQS(RDDQC) : PASS
2164 12:18:26.318794 TX DQ/DQS : PASS
2165 12:18:26.319274 RX DATLAT : PASS
2166 12:18:26.322032 RX DQ/DQS(Engine): PASS
2167 12:18:26.322628 TX OE : NO K
2168 12:18:26.325136 All Pass.
2169 12:18:26.325608
2170 12:18:26.326187 DramC Write-DBI off
2171 12:18:26.328523 PER_BANK_REFRESH: Hybrid Mode
2172 12:18:26.331779 TX_TRACKING: ON
2173 12:18:26.335121 [GetDramInforAfterCalByMRR] Vendor 6.
2174 12:18:26.338842 [GetDramInforAfterCalByMRR] Revision 606.
2175 12:18:26.342253 [GetDramInforAfterCalByMRR] Revision 2 0.
2176 12:18:26.342781 MR0 0x3b3b
2177 12:18:26.343121 MR8 0x5151
2178 12:18:26.348701 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2179 12:18:26.349270
2180 12:18:26.349640 MR0 0x3b3b
2181 12:18:26.350006 MR8 0x5151
2182 12:18:26.352124 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2183 12:18:26.352703
2184 12:18:26.362009 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2185 12:18:26.365468 [FAST_K] Save calibration result to emmc
2186 12:18:26.368640 [FAST_K] Save calibration result to emmc
2187 12:18:26.371994 dram_init: config_dvfs: 1
2188 12:18:26.374964 dramc_set_vcore_voltage set vcore to 662500
2189 12:18:26.378613 Read voltage for 1200, 2
2190 12:18:26.379205 Vio18 = 0
2191 12:18:26.379592 Vcore = 662500
2192 12:18:26.381936 Vdram = 0
2193 12:18:26.382441 Vddq = 0
2194 12:18:26.382816 Vmddr = 0
2195 12:18:26.388655 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2196 12:18:26.392014 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2197 12:18:26.395447 MEM_TYPE=3, freq_sel=15
2198 12:18:26.398548 sv_algorithm_assistance_LP4_1600
2199 12:18:26.401914 ============ PULL DRAM RESETB DOWN ============
2200 12:18:26.405555 ========== PULL DRAM RESETB DOWN end =========
2201 12:18:26.411675 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2202 12:18:26.415148 ===================================
2203 12:18:26.418525 LPDDR4 DRAM CONFIGURATION
2204 12:18:26.421800 ===================================
2205 12:18:26.422414 EX_ROW_EN[0] = 0x0
2206 12:18:26.425508 EX_ROW_EN[1] = 0x0
2207 12:18:26.426140 LP4Y_EN = 0x0
2208 12:18:26.428636 WORK_FSP = 0x0
2209 12:18:26.429225 WL = 0x4
2210 12:18:26.431692 RL = 0x4
2211 12:18:26.432165 BL = 0x2
2212 12:18:26.435201 RPST = 0x0
2213 12:18:26.435668 RD_PRE = 0x0
2214 12:18:26.438494 WR_PRE = 0x1
2215 12:18:26.438963 WR_PST = 0x0
2216 12:18:26.441550 DBI_WR = 0x0
2217 12:18:26.442047 DBI_RD = 0x0
2218 12:18:26.445290 OTF = 0x1
2219 12:18:26.448798 ===================================
2220 12:18:26.452124 ===================================
2221 12:18:26.452699 ANA top config
2222 12:18:26.455650 ===================================
2223 12:18:26.458595 DLL_ASYNC_EN = 0
2224 12:18:26.462050 ALL_SLAVE_EN = 0
2225 12:18:26.465512 NEW_RANK_MODE = 1
2226 12:18:26.466131 DLL_IDLE_MODE = 1
2227 12:18:26.468666 LP45_APHY_COMB_EN = 1
2228 12:18:26.472360 TX_ODT_DIS = 1
2229 12:18:26.475422 NEW_8X_MODE = 1
2230 12:18:26.478583 ===================================
2231 12:18:26.482232 ===================================
2232 12:18:26.485113 data_rate = 2400
2233 12:18:26.485583 CKR = 1
2234 12:18:26.488938 DQ_P2S_RATIO = 8
2235 12:18:26.492230 ===================================
2236 12:18:26.495444 CA_P2S_RATIO = 8
2237 12:18:26.498698 DQ_CA_OPEN = 0
2238 12:18:26.502041 DQ_SEMI_OPEN = 0
2239 12:18:26.502600 CA_SEMI_OPEN = 0
2240 12:18:26.505423 CA_FULL_RATE = 0
2241 12:18:26.508428 DQ_CKDIV4_EN = 0
2242 12:18:26.512200 CA_CKDIV4_EN = 0
2243 12:18:26.515012 CA_PREDIV_EN = 0
2244 12:18:26.518995 PH8_DLY = 17
2245 12:18:26.519565 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2246 12:18:26.521765 DQ_AAMCK_DIV = 4
2247 12:18:26.524892 CA_AAMCK_DIV = 4
2248 12:18:26.528723 CA_ADMCK_DIV = 4
2249 12:18:26.531784 DQ_TRACK_CA_EN = 0
2250 12:18:26.535128 CA_PICK = 1200
2251 12:18:26.538851 CA_MCKIO = 1200
2252 12:18:26.539319 MCKIO_SEMI = 0
2253 12:18:26.541626 PLL_FREQ = 2366
2254 12:18:26.545010 DQ_UI_PI_RATIO = 32
2255 12:18:26.548429 CA_UI_PI_RATIO = 0
2256 12:18:26.551674 ===================================
2257 12:18:26.555081 ===================================
2258 12:18:26.558696 memory_type:LPDDR4
2259 12:18:26.559129 GP_NUM : 10
2260 12:18:26.561638 SRAM_EN : 1
2261 12:18:26.565203 MD32_EN : 0
2262 12:18:26.568183 ===================================
2263 12:18:26.568707 [ANA_INIT] >>>>>>>>>>>>>>
2264 12:18:26.571675 <<<<<< [CONFIGURE PHASE]: ANA_TX
2265 12:18:26.575908 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2266 12:18:26.579550 ===================================
2267 12:18:26.581819 data_rate = 2400,PCW = 0X5b00
2268 12:18:26.585783 ===================================
2269 12:18:26.588804 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2270 12:18:26.595914 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2271 12:18:26.598469 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2272 12:18:26.605545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2273 12:18:26.608834 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2274 12:18:26.611779 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2275 12:18:26.612209 [ANA_INIT] flow start
2276 12:18:26.615460 [ANA_INIT] PLL >>>>>>>>
2277 12:18:26.618426 [ANA_INIT] PLL <<<<<<<<
2278 12:18:26.618895 [ANA_INIT] MIDPI >>>>>>>>
2279 12:18:26.622639 [ANA_INIT] MIDPI <<<<<<<<
2280 12:18:26.625264 [ANA_INIT] DLL >>>>>>>>
2281 12:18:26.625761 [ANA_INIT] DLL <<<<<<<<
2282 12:18:26.628466 [ANA_INIT] flow end
2283 12:18:26.632361 ============ LP4 DIFF to SE enter ============
2284 12:18:26.635315 ============ LP4 DIFF to SE exit ============
2285 12:18:26.638583 [ANA_INIT] <<<<<<<<<<<<<
2286 12:18:26.641814 [Flow] Enable top DCM control >>>>>
2287 12:18:26.645612 [Flow] Enable top DCM control <<<<<
2288 12:18:26.648821 Enable DLL master slave shuffle
2289 12:18:26.655615 ==============================================================
2290 12:18:26.656192 Gating Mode config
2291 12:18:26.662337 ==============================================================
2292 12:18:26.662910 Config description:
2293 12:18:26.672719 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2294 12:18:26.678762 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2295 12:18:26.685755 SELPH_MODE 0: By rank 1: By Phase
2296 12:18:26.689275 ==============================================================
2297 12:18:26.692749 GAT_TRACK_EN = 1
2298 12:18:26.696013 RX_GATING_MODE = 2
2299 12:18:26.698904 RX_GATING_TRACK_MODE = 2
2300 12:18:26.702505 SELPH_MODE = 1
2301 12:18:26.705568 PICG_EARLY_EN = 1
2302 12:18:26.709373 VALID_LAT_VALUE = 1
2303 12:18:26.712494 ==============================================================
2304 12:18:26.715415 Enter into Gating configuration >>>>
2305 12:18:26.719153 Exit from Gating configuration <<<<
2306 12:18:26.722456 Enter into DVFS_PRE_config >>>>>
2307 12:18:26.735569 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2308 12:18:26.738970 Exit from DVFS_PRE_config <<<<<
2309 12:18:26.742061 Enter into PICG configuration >>>>
2310 12:18:26.742533 Exit from PICG configuration <<<<
2311 12:18:26.745724 [RX_INPUT] configuration >>>>>
2312 12:18:26.748997 [RX_INPUT] configuration <<<<<
2313 12:18:26.755788 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2314 12:18:26.759130 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2315 12:18:26.765923 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2316 12:18:26.772793 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2317 12:18:26.779158 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2318 12:18:26.785867 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2319 12:18:26.789233 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2320 12:18:26.793020 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2321 12:18:26.796096 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2322 12:18:26.802464 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2323 12:18:26.805768 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2324 12:18:26.809231 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2325 12:18:26.813041 ===================================
2326 12:18:26.815799 LPDDR4 DRAM CONFIGURATION
2327 12:18:26.819636 ===================================
2328 12:18:26.820215 EX_ROW_EN[0] = 0x0
2329 12:18:26.822384 EX_ROW_EN[1] = 0x0
2330 12:18:26.825544 LP4Y_EN = 0x0
2331 12:18:26.826057 WORK_FSP = 0x0
2332 12:18:26.829316 WL = 0x4
2333 12:18:26.829980 RL = 0x4
2334 12:18:26.832427 BL = 0x2
2335 12:18:26.832894 RPST = 0x0
2336 12:18:26.835815 RD_PRE = 0x0
2337 12:18:26.836287 WR_PRE = 0x1
2338 12:18:26.838987 WR_PST = 0x0
2339 12:18:26.839486 DBI_WR = 0x0
2340 12:18:26.842664 DBI_RD = 0x0
2341 12:18:26.843269 OTF = 0x1
2342 12:18:26.845612 ===================================
2343 12:18:26.849562 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2344 12:18:26.856271 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2345 12:18:26.859181 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2346 12:18:26.862671 ===================================
2347 12:18:26.865851 LPDDR4 DRAM CONFIGURATION
2348 12:18:26.869371 ===================================
2349 12:18:26.869845 EX_ROW_EN[0] = 0x10
2350 12:18:26.872850 EX_ROW_EN[1] = 0x0
2351 12:18:26.873416 LP4Y_EN = 0x0
2352 12:18:26.875768 WORK_FSP = 0x0
2353 12:18:26.876237 WL = 0x4
2354 12:18:26.879198 RL = 0x4
2355 12:18:26.879667 BL = 0x2
2356 12:18:26.882345 RPST = 0x0
2357 12:18:26.885997 RD_PRE = 0x0
2358 12:18:26.886469 WR_PRE = 0x1
2359 12:18:26.888909 WR_PST = 0x0
2360 12:18:26.889367 DBI_WR = 0x0
2361 12:18:26.892523 DBI_RD = 0x0
2362 12:18:26.892979 OTF = 0x1
2363 12:18:26.895606 ===================================
2364 12:18:26.902185 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2365 12:18:26.902649 ==
2366 12:18:26.905763 Dram Type= 6, Freq= 0, CH_0, rank 0
2367 12:18:26.908827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2368 12:18:26.909244 ==
2369 12:18:26.912565 [Duty_Offset_Calibration]
2370 12:18:26.912980 B0:2 B1:0 CA:1
2371 12:18:26.913309
2372 12:18:26.915836 [DutyScan_Calibration_Flow] k_type=0
2373 12:18:26.926059
2374 12:18:26.926459 ==CLK 0==
2375 12:18:26.929511 Final CLK duty delay cell = -4
2376 12:18:26.932834 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2377 12:18:26.936241 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2378 12:18:26.939757 [-4] AVG Duty = 4953%(X100)
2379 12:18:26.940146
2380 12:18:26.942741 CH0 CLK Duty spec in!! Max-Min= 156%
2381 12:18:26.945984 [DutyScan_Calibration_Flow] ====Done====
2382 12:18:26.946369
2383 12:18:26.949164 [DutyScan_Calibration_Flow] k_type=1
2384 12:18:26.965532
2385 12:18:26.966124 ==DQS 0 ==
2386 12:18:26.968321 Final DQS duty delay cell = 0
2387 12:18:26.971430 [0] MAX Duty = 5187%(X100), DQS PI = 28
2388 12:18:26.975178 [0] MIN Duty = 4938%(X100), DQS PI = 0
2389 12:18:26.975637 [0] AVG Duty = 5062%(X100)
2390 12:18:26.978508
2391 12:18:26.979059 ==DQS 1 ==
2392 12:18:26.981772 Final DQS duty delay cell = -4
2393 12:18:26.985183 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2394 12:18:26.988274 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2395 12:18:26.992302 [-4] AVG Duty = 5015%(X100)
2396 12:18:26.992853
2397 12:18:26.994777 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2398 12:18:26.995238
2399 12:18:26.998062 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2400 12:18:27.001517 [DutyScan_Calibration_Flow] ====Done====
2401 12:18:27.002003
2402 12:18:27.005106 [DutyScan_Calibration_Flow] k_type=3
2403 12:18:27.021721
2404 12:18:27.022308 ==DQM 0 ==
2405 12:18:27.025142 Final DQM duty delay cell = 0
2406 12:18:27.028947 [0] MAX Duty = 5031%(X100), DQS PI = 24
2407 12:18:27.031742 [0] MIN Duty = 4813%(X100), DQS PI = 0
2408 12:18:27.032208 [0] AVG Duty = 4922%(X100)
2409 12:18:27.034915
2410 12:18:27.035376 ==DQM 1 ==
2411 12:18:27.038569 Final DQM duty delay cell = 0
2412 12:18:27.041793 [0] MAX Duty = 5187%(X100), DQS PI = 48
2413 12:18:27.045557 [0] MIN Duty = 5000%(X100), DQS PI = 12
2414 12:18:27.046187 [0] AVG Duty = 5093%(X100)
2415 12:18:27.048611
2416 12:18:27.051852 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2417 12:18:27.052315
2418 12:18:27.055355 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2419 12:18:27.058813 [DutyScan_Calibration_Flow] ====Done====
2420 12:18:27.059362
2421 12:18:27.062074 [DutyScan_Calibration_Flow] k_type=2
2422 12:18:27.078594
2423 12:18:27.079141 ==DQ 0 ==
2424 12:18:27.082329 Final DQ duty delay cell = -4
2425 12:18:27.085086 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2426 12:18:27.088343 [-4] MIN Duty = 4875%(X100), DQS PI = 14
2427 12:18:27.092003 [-4] AVG Duty = 4953%(X100)
2428 12:18:27.092553
2429 12:18:27.092912 ==DQ 1 ==
2430 12:18:27.095056 Final DQ duty delay cell = 4
2431 12:18:27.098476 [4] MAX Duty = 5093%(X100), DQS PI = 4
2432 12:18:27.102126 [4] MIN Duty = 5031%(X100), DQS PI = 0
2433 12:18:27.102680 [4] AVG Duty = 5062%(X100)
2434 12:18:27.103043
2435 12:18:27.105019 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2436 12:18:27.108090
2437 12:18:27.111674 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2438 12:18:27.114999 [DutyScan_Calibration_Flow] ====Done====
2439 12:18:27.115553 ==
2440 12:18:27.118290 Dram Type= 6, Freq= 0, CH_1, rank 0
2441 12:18:27.122136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2442 12:18:27.122693 ==
2443 12:18:27.125251 [Duty_Offset_Calibration]
2444 12:18:27.125801 B0:0 B1:-1 CA:2
2445 12:18:27.126213
2446 12:18:27.128498 [DutyScan_Calibration_Flow] k_type=0
2447 12:18:27.138484
2448 12:18:27.139030 ==CLK 0==
2449 12:18:27.141984 Final CLK duty delay cell = 0
2450 12:18:27.145124 [0] MAX Duty = 5156%(X100), DQS PI = 16
2451 12:18:27.148934 [0] MIN Duty = 4938%(X100), DQS PI = 44
2452 12:18:27.149502 [0] AVG Duty = 5047%(X100)
2453 12:18:27.152127
2454 12:18:27.152689 CH1 CLK Duty spec in!! Max-Min= 218%
2455 12:18:27.158580 [DutyScan_Calibration_Flow] ====Done====
2456 12:18:27.159143
2457 12:18:27.161674 [DutyScan_Calibration_Flow] k_type=1
2458 12:18:27.177773
2459 12:18:27.178363 ==DQS 0 ==
2460 12:18:27.180955 Final DQS duty delay cell = 0
2461 12:18:27.184907 [0] MAX Duty = 5093%(X100), DQS PI = 22
2462 12:18:27.187574 [0] MIN Duty = 4969%(X100), DQS PI = 0
2463 12:18:27.188048 [0] AVG Duty = 5031%(X100)
2464 12:18:27.191582
2465 12:18:27.192149 ==DQS 1 ==
2466 12:18:27.194515 Final DQS duty delay cell = 0
2467 12:18:27.198064 [0] MAX Duty = 5156%(X100), DQS PI = 0
2468 12:18:27.201223 [0] MIN Duty = 4813%(X100), DQS PI = 36
2469 12:18:27.201789 [0] AVG Duty = 4984%(X100)
2470 12:18:27.202202
2471 12:18:27.207994 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2472 12:18:27.208558
2473 12:18:27.211105 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2474 12:18:27.214527 [DutyScan_Calibration_Flow] ====Done====
2475 12:18:27.215093
2476 12:18:27.217775 [DutyScan_Calibration_Flow] k_type=3
2477 12:18:27.234215
2478 12:18:27.234773 ==DQM 0 ==
2479 12:18:27.237485 Final DQM duty delay cell = 4
2480 12:18:27.241022 [4] MAX Duty = 5093%(X100), DQS PI = 6
2481 12:18:27.244096 [4] MIN Duty = 4969%(X100), DQS PI = 28
2482 12:18:27.244566 [4] AVG Duty = 5031%(X100)
2483 12:18:27.247575
2484 12:18:27.248037 ==DQM 1 ==
2485 12:18:27.251154 Final DQM duty delay cell = -4
2486 12:18:27.254575 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2487 12:18:27.258207 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2488 12:18:27.261144 [-4] AVG Duty = 4875%(X100)
2489 12:18:27.261706
2490 12:18:27.264284 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2491 12:18:27.264753
2492 12:18:27.267607 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2493 12:18:27.271082 [DutyScan_Calibration_Flow] ====Done====
2494 12:18:27.271785
2495 12:18:27.274359 [DutyScan_Calibration_Flow] k_type=2
2496 12:18:27.290850
2497 12:18:27.291407 ==DQ 0 ==
2498 12:18:27.294185 Final DQ duty delay cell = 0
2499 12:18:27.297922 [0] MAX Duty = 5062%(X100), DQS PI = 22
2500 12:18:27.301144 [0] MIN Duty = 4938%(X100), DQS PI = 0
2501 12:18:27.301708 [0] AVG Duty = 5000%(X100)
2502 12:18:27.302123
2503 12:18:27.304364 ==DQ 1 ==
2504 12:18:27.307969 Final DQ duty delay cell = 0
2505 12:18:27.311140 [0] MAX Duty = 5031%(X100), DQS PI = 2
2506 12:18:27.314661 [0] MIN Duty = 4813%(X100), DQS PI = 34
2507 12:18:27.315223 [0] AVG Duty = 4922%(X100)
2508 12:18:27.315596
2509 12:18:27.318168 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2510 12:18:27.318731
2511 12:18:27.321186 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2512 12:18:27.324808 [DutyScan_Calibration_Flow] ====Done====
2513 12:18:27.329988 nWR fixed to 30
2514 12:18:27.333304 [ModeRegInit_LP4] CH0 RK0
2515 12:18:27.333866 [ModeRegInit_LP4] CH0 RK1
2516 12:18:27.336568 [ModeRegInit_LP4] CH1 RK0
2517 12:18:27.340263 [ModeRegInit_LP4] CH1 RK1
2518 12:18:27.340820 match AC timing 7
2519 12:18:27.346609 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2520 12:18:27.350206 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2521 12:18:27.353491 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2522 12:18:27.360114 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2523 12:18:27.363028 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2524 12:18:27.363497 ==
2525 12:18:27.366519 Dram Type= 6, Freq= 0, CH_0, rank 0
2526 12:18:27.369768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2527 12:18:27.370408 ==
2528 12:18:27.377079 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2529 12:18:27.383239 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2530 12:18:27.390860 [CA 0] Center 38 (7~69) winsize 63
2531 12:18:27.393922 [CA 1] Center 38 (7~69) winsize 63
2532 12:18:27.397620 [CA 2] Center 34 (4~65) winsize 62
2533 12:18:27.400983 [CA 3] Center 34 (4~65) winsize 62
2534 12:18:27.404251 [CA 4] Center 34 (4~64) winsize 61
2535 12:18:27.407303 [CA 5] Center 32 (2~63) winsize 62
2536 12:18:27.407862
2537 12:18:27.410748 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2538 12:18:27.411306
2539 12:18:27.414175 [CATrainingPosCal] consider 1 rank data
2540 12:18:27.417610 u2DelayCellTimex100 = 270/100 ps
2541 12:18:27.421328 CA0 delay=38 (7~69),Diff = 6 PI (28 cell)
2542 12:18:27.424397 CA1 delay=38 (7~69),Diff = 6 PI (28 cell)
2543 12:18:27.430778 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2544 12:18:27.434114 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2545 12:18:27.437579 CA4 delay=34 (4~64),Diff = 2 PI (9 cell)
2546 12:18:27.440913 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2547 12:18:27.441474
2548 12:18:27.444052 CA PerBit enable=1, Macro0, CA PI delay=32
2549 12:18:27.444592
2550 12:18:27.447669 [CBTSetCACLKResult] CA Dly = 32
2551 12:18:27.448132 CS Dly: 6 (0~37)
2552 12:18:27.448503 ==
2553 12:18:27.450822 Dram Type= 6, Freq= 0, CH_0, rank 1
2554 12:18:27.457488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2555 12:18:27.458102 ==
2556 12:18:27.460999 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2557 12:18:27.467584 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2558 12:18:27.476204 [CA 0] Center 38 (8~69) winsize 62
2559 12:18:27.479526 [CA 1] Center 38 (8~69) winsize 62
2560 12:18:27.482867 [CA 2] Center 35 (5~66) winsize 62
2561 12:18:27.486247 [CA 3] Center 35 (4~66) winsize 63
2562 12:18:27.489549 [CA 4] Center 34 (4~65) winsize 62
2563 12:18:27.493211 [CA 5] Center 33 (3~64) winsize 62
2564 12:18:27.493780
2565 12:18:27.496007 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2566 12:18:27.496473
2567 12:18:27.499533 [CATrainingPosCal] consider 2 rank data
2568 12:18:27.503050 u2DelayCellTimex100 = 270/100 ps
2569 12:18:27.506330 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2570 12:18:27.509894 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2571 12:18:27.516333 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
2572 12:18:27.519582 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2573 12:18:27.522761 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2574 12:18:27.526529 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2575 12:18:27.527092
2576 12:18:27.529589 CA PerBit enable=1, Macro0, CA PI delay=33
2577 12:18:27.530198
2578 12:18:27.532722 [CBTSetCACLKResult] CA Dly = 33
2579 12:18:27.533190 CS Dly: 7 (0~39)
2580 12:18:27.533560
2581 12:18:27.536446 ----->DramcWriteLeveling(PI) begin...
2582 12:18:27.540168 ==
2583 12:18:27.540737 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 12:18:27.546503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 12:18:27.546977 ==
2586 12:18:27.550289 Write leveling (Byte 0): 34 => 34
2587 12:18:27.553535 Write leveling (Byte 1): 32 => 32
2588 12:18:27.554149 DramcWriteLeveling(PI) end<-----
2589 12:18:27.556521
2590 12:18:27.557085 ==
2591 12:18:27.560078 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 12:18:27.562966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 12:18:27.563442 ==
2594 12:18:27.566583 [Gating] SW mode calibration
2595 12:18:27.573256 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2596 12:18:27.576426 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2597 12:18:27.582994 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2598 12:18:27.586351 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
2599 12:18:27.589752 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 12:18:27.596258 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 12:18:27.599838 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 12:18:27.603343 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 12:18:27.609973 0 15 24 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
2604 12:18:27.613043 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2605 12:18:27.616791 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2606 12:18:27.623361 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2607 12:18:27.626285 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 12:18:27.629848 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 12:18:27.633512 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 12:18:27.640305 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 12:18:27.643333 1 0 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2612 12:18:27.646935 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2613 12:18:27.652984 1 1 0 | B1->B0 | 2e2e 4646 | 1 0 | (0 0) (0 0)
2614 12:18:27.656701 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 12:18:27.660066 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 12:18:27.666661 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 12:18:27.670117 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 12:18:27.673297 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 12:18:27.679992 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 12:18:27.683237 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2621 12:18:27.686581 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2622 12:18:27.693617 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 12:18:27.696591 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 12:18:27.700372 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 12:18:27.706677 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 12:18:27.710165 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 12:18:27.713159 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 12:18:27.720217 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 12:18:27.722991 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 12:18:27.726733 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 12:18:27.730058 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 12:18:27.736472 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 12:18:27.740480 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 12:18:27.743396 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 12:18:27.750368 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 12:18:27.753830 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2637 12:18:27.757047 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2638 12:18:27.760139 Total UI for P1: 0, mck2ui 16
2639 12:18:27.763356 best dqsien dly found for B0: ( 1, 3, 28)
2640 12:18:27.770306 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2641 12:18:27.770892 Total UI for P1: 0, mck2ui 16
2642 12:18:27.777008 best dqsien dly found for B1: ( 1, 4, 0)
2643 12:18:27.780121 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2644 12:18:27.783738 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2645 12:18:27.784302
2646 12:18:27.786703 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2647 12:18:27.790615 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2648 12:18:27.793579 [Gating] SW calibration Done
2649 12:18:27.794186 ==
2650 12:18:27.797147 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 12:18:27.800392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 12:18:27.800964 ==
2653 12:18:27.804061 RX Vref Scan: 0
2654 12:18:27.804635
2655 12:18:27.805012 RX Vref 0 -> 0, step: 1
2656 12:18:27.805355
2657 12:18:27.806793 RX Delay -40 -> 252, step: 8
2658 12:18:27.810772 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2659 12:18:27.813787 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2660 12:18:27.820636 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2661 12:18:27.823701 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2662 12:18:27.826729 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2663 12:18:27.830229 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2664 12:18:27.833585 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2665 12:18:27.840188 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2666 12:18:27.843269 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2667 12:18:27.846776 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2668 12:18:27.850808 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2669 12:18:27.853602 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2670 12:18:27.860116 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2671 12:18:27.864217 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2672 12:18:27.866664 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2673 12:18:27.870493 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2674 12:18:27.871078 ==
2675 12:18:27.873305 Dram Type= 6, Freq= 0, CH_0, rank 0
2676 12:18:27.880534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2677 12:18:27.881008 ==
2678 12:18:27.881382 DQS Delay:
2679 12:18:27.883559 DQS0 = 0, DQS1 = 0
2680 12:18:27.884126 DQM Delay:
2681 12:18:27.884499 DQM0 = 123, DQM1 = 110
2682 12:18:27.886571 DQ Delay:
2683 12:18:27.890219 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2684 12:18:27.893662 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2685 12:18:27.896837 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2686 12:18:27.900301 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2687 12:18:27.900866
2688 12:18:27.901239
2689 12:18:27.901584 ==
2690 12:18:27.903565 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 12:18:27.906722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 12:18:27.907195 ==
2693 12:18:27.910206
2694 12:18:27.910760
2695 12:18:27.911134 TX Vref Scan disable
2696 12:18:27.914273 == TX Byte 0 ==
2697 12:18:27.916780 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2698 12:18:27.920571 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2699 12:18:27.923517 == TX Byte 1 ==
2700 12:18:27.926907 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2701 12:18:27.930503 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2702 12:18:27.931084 ==
2703 12:18:27.933128 Dram Type= 6, Freq= 0, CH_0, rank 0
2704 12:18:27.939907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2705 12:18:27.940488 ==
2706 12:18:27.950675 TX Vref=22, minBit 0, minWin=23, winSum=394
2707 12:18:27.954097 TX Vref=24, minBit 0, minWin=24, winSum=397
2708 12:18:27.957816 TX Vref=26, minBit 3, minWin=24, winSum=408
2709 12:18:27.961181 TX Vref=28, minBit 0, minWin=25, winSum=412
2710 12:18:27.963742 TX Vref=30, minBit 0, minWin=25, winSum=410
2711 12:18:27.967107 TX Vref=32, minBit 0, minWin=25, winSum=411
2712 12:18:27.974319 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 28
2713 12:18:27.974898
2714 12:18:27.977127 Final TX Range 1 Vref 28
2715 12:18:27.977601
2716 12:18:27.978018 ==
2717 12:18:27.980563 Dram Type= 6, Freq= 0, CH_0, rank 0
2718 12:18:27.984226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2719 12:18:27.984809 ==
2720 12:18:27.985188
2721 12:18:27.985536
2722 12:18:27.987414 TX Vref Scan disable
2723 12:18:27.991152 == TX Byte 0 ==
2724 12:18:27.993921 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2725 12:18:27.997347 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2726 12:18:28.001056 == TX Byte 1 ==
2727 12:18:28.004125 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2728 12:18:28.007466 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2729 12:18:28.008042
2730 12:18:28.010776 [DATLAT]
2731 12:18:28.011354 Freq=1200, CH0 RK0
2732 12:18:28.011734
2733 12:18:28.013707 DATLAT Default: 0xd
2734 12:18:28.014213 0, 0xFFFF, sum = 0
2735 12:18:28.017383 1, 0xFFFF, sum = 0
2736 12:18:28.017862 2, 0xFFFF, sum = 0
2737 12:18:28.020710 3, 0xFFFF, sum = 0
2738 12:18:28.021290 4, 0xFFFF, sum = 0
2739 12:18:28.024133 5, 0xFFFF, sum = 0
2740 12:18:28.024716 6, 0xFFFF, sum = 0
2741 12:18:28.027400 7, 0xFFFF, sum = 0
2742 12:18:28.027880 8, 0xFFFF, sum = 0
2743 12:18:28.031033 9, 0xFFFF, sum = 0
2744 12:18:28.031630 10, 0xFFFF, sum = 0
2745 12:18:28.034160 11, 0xFFFF, sum = 0
2746 12:18:28.034637 12, 0x0, sum = 1
2747 12:18:28.037198 13, 0x0, sum = 2
2748 12:18:28.037674 14, 0x0, sum = 3
2749 12:18:28.040756 15, 0x0, sum = 4
2750 12:18:28.041340 best_step = 13
2751 12:18:28.041720
2752 12:18:28.042112 ==
2753 12:18:28.044249 Dram Type= 6, Freq= 0, CH_0, rank 0
2754 12:18:28.050834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2755 12:18:28.051309 ==
2756 12:18:28.051687 RX Vref Scan: 1
2757 12:18:28.052040
2758 12:18:28.054148 Set Vref Range= 32 -> 127
2759 12:18:28.054720
2760 12:18:28.057770 RX Vref 32 -> 127, step: 1
2761 12:18:28.058404
2762 12:18:28.058786 RX Delay -13 -> 252, step: 4
2763 12:18:28.060717
2764 12:18:28.061183 Set Vref, RX VrefLevel [Byte0]: 32
2765 12:18:28.063891 [Byte1]: 32
2766 12:18:28.068891
2767 12:18:28.069467 Set Vref, RX VrefLevel [Byte0]: 33
2768 12:18:28.072240 [Byte1]: 33
2769 12:18:28.076392
2770 12:18:28.076929 Set Vref, RX VrefLevel [Byte0]: 34
2771 12:18:28.080056 [Byte1]: 34
2772 12:18:28.084794
2773 12:18:28.085369 Set Vref, RX VrefLevel [Byte0]: 35
2774 12:18:28.087892 [Byte1]: 35
2775 12:18:28.092453
2776 12:18:28.093028 Set Vref, RX VrefLevel [Byte0]: 36
2777 12:18:28.095484 [Byte1]: 36
2778 12:18:28.100691
2779 12:18:28.101264 Set Vref, RX VrefLevel [Byte0]: 37
2780 12:18:28.103614 [Byte1]: 37
2781 12:18:28.108532
2782 12:18:28.109108 Set Vref, RX VrefLevel [Byte0]: 38
2783 12:18:28.111502 [Byte1]: 38
2784 12:18:28.116271
2785 12:18:28.116852 Set Vref, RX VrefLevel [Byte0]: 39
2786 12:18:28.119251 [Byte1]: 39
2787 12:18:28.124219
2788 12:18:28.124792 Set Vref, RX VrefLevel [Byte0]: 40
2789 12:18:28.127277 [Byte1]: 40
2790 12:18:28.132074
2791 12:18:28.132644 Set Vref, RX VrefLevel [Byte0]: 41
2792 12:18:28.134957 [Byte1]: 41
2793 12:18:28.139985
2794 12:18:28.140453 Set Vref, RX VrefLevel [Byte0]: 42
2795 12:18:28.143513 [Byte1]: 42
2796 12:18:28.148172
2797 12:18:28.148737 Set Vref, RX VrefLevel [Byte0]: 43
2798 12:18:28.150731 [Byte1]: 43
2799 12:18:28.155862
2800 12:18:28.156437 Set Vref, RX VrefLevel [Byte0]: 44
2801 12:18:28.158640 [Byte1]: 44
2802 12:18:28.163549
2803 12:18:28.164157 Set Vref, RX VrefLevel [Byte0]: 45
2804 12:18:28.166651 [Byte1]: 45
2805 12:18:28.171363
2806 12:18:28.171938 Set Vref, RX VrefLevel [Byte0]: 46
2807 12:18:28.174868 [Byte1]: 46
2808 12:18:28.179021
2809 12:18:28.179491 Set Vref, RX VrefLevel [Byte0]: 47
2810 12:18:28.182899 [Byte1]: 47
2811 12:18:28.187166
2812 12:18:28.187736 Set Vref, RX VrefLevel [Byte0]: 48
2813 12:18:28.190364 [Byte1]: 48
2814 12:18:28.195147
2815 12:18:28.195726 Set Vref, RX VrefLevel [Byte0]: 49
2816 12:18:28.198024 [Byte1]: 49
2817 12:18:28.203267
2818 12:18:28.203837 Set Vref, RX VrefLevel [Byte0]: 50
2819 12:18:28.206294 [Byte1]: 50
2820 12:18:28.210881
2821 12:18:28.211455 Set Vref, RX VrefLevel [Byte0]: 51
2822 12:18:28.214018 [Byte1]: 51
2823 12:18:28.218989
2824 12:18:28.219459 Set Vref, RX VrefLevel [Byte0]: 52
2825 12:18:28.222229 [Byte1]: 52
2826 12:18:28.226813
2827 12:18:28.227384 Set Vref, RX VrefLevel [Byte0]: 53
2828 12:18:28.230296 [Byte1]: 53
2829 12:18:28.234383
2830 12:18:28.234961 Set Vref, RX VrefLevel [Byte0]: 54
2831 12:18:28.237818 [Byte1]: 54
2832 12:18:28.242326
2833 12:18:28.242897 Set Vref, RX VrefLevel [Byte0]: 55
2834 12:18:28.245678 [Byte1]: 55
2835 12:18:28.250183
2836 12:18:28.250742 Set Vref, RX VrefLevel [Byte0]: 56
2837 12:18:28.253571 [Byte1]: 56
2838 12:18:28.258515
2839 12:18:28.259078 Set Vref, RX VrefLevel [Byte0]: 57
2840 12:18:28.261570 [Byte1]: 57
2841 12:18:28.265969
2842 12:18:28.266441 Set Vref, RX VrefLevel [Byte0]: 58
2843 12:18:28.269338 [Byte1]: 58
2844 12:18:28.274038
2845 12:18:28.274637 Set Vref, RX VrefLevel [Byte0]: 59
2846 12:18:28.277335 [Byte1]: 59
2847 12:18:28.282092
2848 12:18:28.282649 Set Vref, RX VrefLevel [Byte0]: 60
2849 12:18:28.285416 [Byte1]: 60
2850 12:18:28.290048
2851 12:18:28.290607 Set Vref, RX VrefLevel [Byte0]: 61
2852 12:18:28.293444 [Byte1]: 61
2853 12:18:28.297751
2854 12:18:28.298368 Set Vref, RX VrefLevel [Byte0]: 62
2855 12:18:28.301204 [Byte1]: 62
2856 12:18:28.305618
2857 12:18:28.306240 Set Vref, RX VrefLevel [Byte0]: 63
2858 12:18:28.308785 [Byte1]: 63
2859 12:18:28.313343
2860 12:18:28.314001 Set Vref, RX VrefLevel [Byte0]: 64
2861 12:18:28.316876 [Byte1]: 64
2862 12:18:28.321612
2863 12:18:28.322225 Set Vref, RX VrefLevel [Byte0]: 65
2864 12:18:28.324913 [Byte1]: 65
2865 12:18:28.329178
2866 12:18:28.329744 Set Vref, RX VrefLevel [Byte0]: 66
2867 12:18:28.332241 [Byte1]: 66
2868 12:18:28.337117
2869 12:18:28.337615 Set Vref, RX VrefLevel [Byte0]: 67
2870 12:18:28.340167 [Byte1]: 67
2871 12:18:28.345062
2872 12:18:28.345648 Set Vref, RX VrefLevel [Byte0]: 68
2873 12:18:28.348574 [Byte1]: 68
2874 12:18:28.353085
2875 12:18:28.353660 Set Vref, RX VrefLevel [Byte0]: 69
2876 12:18:28.356345 [Byte1]: 69
2877 12:18:28.360873
2878 12:18:28.361440 Final RX Vref Byte 0 = 59 to rank0
2879 12:18:28.363842 Final RX Vref Byte 1 = 49 to rank0
2880 12:18:28.367393 Final RX Vref Byte 0 = 59 to rank1
2881 12:18:28.370973 Final RX Vref Byte 1 = 49 to rank1==
2882 12:18:28.374286 Dram Type= 6, Freq= 0, CH_0, rank 0
2883 12:18:28.377586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2884 12:18:28.380608 ==
2885 12:18:28.381080 DQS Delay:
2886 12:18:28.381453 DQS0 = 0, DQS1 = 0
2887 12:18:28.384302 DQM Delay:
2888 12:18:28.384874 DQM0 = 122, DQM1 = 109
2889 12:18:28.387641 DQ Delay:
2890 12:18:28.390513 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2891 12:18:28.394207 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2892 12:18:28.397654 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2893 12:18:28.401169 DQ12 =114, DQ13 =110, DQ14 =122, DQ15 =116
2894 12:18:28.401741
2895 12:18:28.402178
2896 12:18:28.407404 [DQSOSCAuto] RK0, (LSB)MR18= 0xc09, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2897 12:18:28.410485 CH0 RK0: MR19=404, MR18=C09
2898 12:18:28.418092 CH0_RK0: MR19=0x404, MR18=0xC09, DQSOSC=405, MR23=63, INC=39, DEC=26
2899 12:18:28.418680
2900 12:18:28.420624 ----->DramcWriteLeveling(PI) begin...
2901 12:18:28.421101 ==
2902 12:18:28.424446 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 12:18:28.427811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 12:18:28.428381 ==
2905 12:18:28.431205 Write leveling (Byte 0): 33 => 33
2906 12:18:28.434301 Write leveling (Byte 1): 29 => 29
2907 12:18:28.437848 DramcWriteLeveling(PI) end<-----
2908 12:18:28.438361
2909 12:18:28.438736 ==
2910 12:18:28.440828 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 12:18:28.447308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 12:18:28.447874 ==
2913 12:18:28.448292 [Gating] SW mode calibration
2914 12:18:28.457400 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2915 12:18:28.460878 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2916 12:18:28.464501 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2917 12:18:28.470850 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2918 12:18:28.473896 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 12:18:28.477418 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 12:18:28.484253 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 12:18:28.487182 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 12:18:28.490399 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 12:18:28.497602 0 15 28 | B1->B0 | 3030 2929 | 1 0 | (0 0) (1 0)
2924 12:18:28.500779 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2925 12:18:28.504312 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 12:18:28.510930 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 12:18:28.514386 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 12:18:28.517829 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 12:18:28.520638 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 12:18:28.527421 1 0 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2931 12:18:28.531109 1 0 28 | B1->B0 | 3131 3e3e | 0 0 | (0 0) (0 0)
2932 12:18:28.534436 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 12:18:28.540740 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 12:18:28.544522 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 12:18:28.547360 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 12:18:28.554362 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 12:18:28.557587 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 12:18:28.561249 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 12:18:28.567598 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2940 12:18:28.570731 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 12:18:28.574849 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 12:18:28.580846 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 12:18:28.584478 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 12:18:28.587661 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 12:18:28.594181 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 12:18:28.597755 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 12:18:28.601024 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 12:18:28.604350 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 12:18:28.611076 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 12:18:28.614409 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 12:18:28.617700 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 12:18:28.624429 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 12:18:28.627640 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 12:18:28.631381 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2955 12:18:28.637548 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2956 12:18:28.638050 Total UI for P1: 0, mck2ui 16
2957 12:18:28.644915 best dqsien dly found for B0: ( 1, 3, 24)
2958 12:18:28.647650 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2959 12:18:28.651022 Total UI for P1: 0, mck2ui 16
2960 12:18:28.654797 best dqsien dly found for B1: ( 1, 3, 28)
2961 12:18:28.657929 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2962 12:18:28.661611 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2963 12:18:28.662225
2964 12:18:28.664610 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2965 12:18:28.668163 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2966 12:18:28.671183 [Gating] SW calibration Done
2967 12:18:28.671785 ==
2968 12:18:28.674732 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 12:18:28.678167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 12:18:28.678766 ==
2971 12:18:28.681118 RX Vref Scan: 0
2972 12:18:28.681588
2973 12:18:28.684796 RX Vref 0 -> 0, step: 1
2974 12:18:28.685372
2975 12:18:28.685914 RX Delay -40 -> 252, step: 8
2976 12:18:28.691115 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2977 12:18:28.695011 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2978 12:18:28.698062 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2979 12:18:28.701645 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2980 12:18:28.704809 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2981 12:18:28.711477 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2982 12:18:28.715114 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2983 12:18:28.718408 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2984 12:18:28.721507 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2985 12:18:28.725055 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2986 12:18:28.727991 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2987 12:18:28.735619 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2988 12:18:28.738108 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2989 12:18:28.741906 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2990 12:18:28.744830 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2991 12:18:28.748141 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2992 12:18:28.751405 ==
2993 12:18:28.755163 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 12:18:28.758328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 12:18:28.758907 ==
2996 12:18:28.759287 DQS Delay:
2997 12:18:28.761808 DQS0 = 0, DQS1 = 0
2998 12:18:28.762429 DQM Delay:
2999 12:18:28.765174 DQM0 = 120, DQM1 = 108
3000 12:18:28.765756 DQ Delay:
3001 12:18:28.768794 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3002 12:18:28.772026 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3003 12:18:28.775015 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3004 12:18:28.778597 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
3005 12:18:28.779284
3006 12:18:28.779886
3007 12:18:28.780496 ==
3008 12:18:28.781795 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 12:18:28.788824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 12:18:28.789409 ==
3011 12:18:28.789789
3012 12:18:28.790192
3013 12:18:28.790635 TX Vref Scan disable
3014 12:18:28.791541 == TX Byte 0 ==
3015 12:18:28.795583 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3016 12:18:28.798595 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3017 12:18:28.801685 == TX Byte 1 ==
3018 12:18:28.805722 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3019 12:18:28.808486 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3020 12:18:28.811849 ==
3021 12:18:28.812426 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 12:18:28.818389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 12:18:28.818973 ==
3024 12:18:28.829788 TX Vref=22, minBit 1, minWin=24, winSum=404
3025 12:18:28.833362 TX Vref=24, minBit 0, minWin=25, winSum=412
3026 12:18:28.836423 TX Vref=26, minBit 0, minWin=25, winSum=413
3027 12:18:28.839543 TX Vref=28, minBit 7, minWin=24, winSum=414
3028 12:18:28.842926 TX Vref=30, minBit 2, minWin=25, winSum=422
3029 12:18:28.846811 TX Vref=32, minBit 1, minWin=25, winSum=420
3030 12:18:28.853150 [TxChooseVref] Worse bit 2, Min win 25, Win sum 422, Final Vref 30
3031 12:18:28.853734
3032 12:18:28.856451 Final TX Range 1 Vref 30
3033 12:18:28.856926
3034 12:18:28.857298 ==
3035 12:18:28.859908 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 12:18:28.863881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 12:18:28.864462 ==
3038 12:18:28.864839
3039 12:18:28.866566
3040 12:18:28.867032 TX Vref Scan disable
3041 12:18:28.869899 == TX Byte 0 ==
3042 12:18:28.872995 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3043 12:18:28.876123 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3044 12:18:28.879812 == TX Byte 1 ==
3045 12:18:28.882848 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3046 12:18:28.886574 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3047 12:18:28.887046
3048 12:18:28.889383 [DATLAT]
3049 12:18:28.889851 Freq=1200, CH0 RK1
3050 12:18:28.890276
3051 12:18:28.892970 DATLAT Default: 0xd
3052 12:18:28.893438 0, 0xFFFF, sum = 0
3053 12:18:28.896256 1, 0xFFFF, sum = 0
3054 12:18:28.896734 2, 0xFFFF, sum = 0
3055 12:18:28.900146 3, 0xFFFF, sum = 0
3056 12:18:28.900737 4, 0xFFFF, sum = 0
3057 12:18:28.903078 5, 0xFFFF, sum = 0
3058 12:18:28.906135 6, 0xFFFF, sum = 0
3059 12:18:28.906615 7, 0xFFFF, sum = 0
3060 12:18:28.909412 8, 0xFFFF, sum = 0
3061 12:18:28.910021 9, 0xFFFF, sum = 0
3062 12:18:28.913283 10, 0xFFFF, sum = 0
3063 12:18:28.913865 11, 0xFFFF, sum = 0
3064 12:18:28.916359 12, 0x0, sum = 1
3065 12:18:28.916942 13, 0x0, sum = 2
3066 12:18:28.919730 14, 0x0, sum = 3
3067 12:18:28.920354 15, 0x0, sum = 4
3068 12:18:28.920752 best_step = 13
3069 12:18:28.921104
3070 12:18:28.922742 ==
3071 12:18:28.926269 Dram Type= 6, Freq= 0, CH_0, rank 1
3072 12:18:28.929916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 12:18:28.930526 ==
3074 12:18:28.930905 RX Vref Scan: 0
3075 12:18:28.931264
3076 12:18:28.933121 RX Vref 0 -> 0, step: 1
3077 12:18:28.933700
3078 12:18:28.936172 RX Delay -21 -> 252, step: 4
3079 12:18:28.939365 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3080 12:18:28.946256 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3081 12:18:28.949979 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3082 12:18:28.953028 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3083 12:18:28.956687 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3084 12:18:28.959915 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3085 12:18:28.962965 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3086 12:18:28.969813 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3087 12:18:28.973052 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3088 12:18:28.976332 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3089 12:18:28.979664 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3090 12:18:28.983165 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3091 12:18:28.989882 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3092 12:18:28.993168 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3093 12:18:28.996657 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3094 12:18:28.999749 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3095 12:18:29.000346 ==
3096 12:18:29.003241 Dram Type= 6, Freq= 0, CH_0, rank 1
3097 12:18:29.009829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 12:18:29.010458 ==
3099 12:18:29.010847 DQS Delay:
3100 12:18:29.011196 DQS0 = 0, DQS1 = 0
3101 12:18:29.013197 DQM Delay:
3102 12:18:29.013781 DQM0 = 119, DQM1 = 107
3103 12:18:29.016957 DQ Delay:
3104 12:18:29.019867 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =112
3105 12:18:29.022951 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3106 12:18:29.026883 DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =106
3107 12:18:29.030187 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3108 12:18:29.030764
3109 12:18:29.031141
3110 12:18:29.036457 [DQSOSCAuto] RK1, (LSB)MR18= 0xcf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3111 12:18:29.039405 CH0 RK1: MR19=403, MR18=CF4
3112 12:18:29.046455 CH0_RK1: MR19=0x403, MR18=0xCF4, DQSOSC=405, MR23=63, INC=39, DEC=26
3113 12:18:29.049651 [RxdqsGatingPostProcess] freq 1200
3114 12:18:29.056725 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3115 12:18:29.057308 best DQS0 dly(2T, 0.5T) = (0, 11)
3116 12:18:29.059925 best DQS1 dly(2T, 0.5T) = (0, 12)
3117 12:18:29.063063 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3118 12:18:29.066311 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3119 12:18:29.070114 best DQS0 dly(2T, 0.5T) = (0, 11)
3120 12:18:29.073243 best DQS1 dly(2T, 0.5T) = (0, 11)
3121 12:18:29.076537 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3122 12:18:29.079799 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3123 12:18:29.083266 Pre-setting of DQS Precalculation
3124 12:18:29.086367 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3125 12:18:29.090386 ==
3126 12:18:29.093715 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 12:18:29.096425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 12:18:29.097008 ==
3129 12:18:29.100150 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3130 12:18:29.106578 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3131 12:18:29.115888 [CA 0] Center 37 (7~68) winsize 62
3132 12:18:29.119142 [CA 1] Center 37 (7~68) winsize 62
3133 12:18:29.122327 [CA 2] Center 34 (4~65) winsize 62
3134 12:18:29.125634 [CA 3] Center 33 (3~64) winsize 62
3135 12:18:29.128999 [CA 4] Center 33 (3~64) winsize 62
3136 12:18:29.132530 [CA 5] Center 33 (3~63) winsize 61
3137 12:18:29.133110
3138 12:18:29.135395 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3139 12:18:29.135870
3140 12:18:29.139149 [CATrainingPosCal] consider 1 rank data
3141 12:18:29.142367 u2DelayCellTimex100 = 270/100 ps
3142 12:18:29.145740 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3143 12:18:29.149066 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3144 12:18:29.155554 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3145 12:18:29.159160 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3146 12:18:29.162538 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3147 12:18:29.165836 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3148 12:18:29.166560
3149 12:18:29.169187 CA PerBit enable=1, Macro0, CA PI delay=33
3150 12:18:29.169770
3151 12:18:29.172786 [CBTSetCACLKResult] CA Dly = 33
3152 12:18:29.173364 CS Dly: 5 (0~36)
3153 12:18:29.173744 ==
3154 12:18:29.175446 Dram Type= 6, Freq= 0, CH_1, rank 1
3155 12:18:29.182366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3156 12:18:29.182964 ==
3157 12:18:29.185986 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3158 12:18:29.193256 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3159 12:18:29.201364 [CA 0] Center 38 (8~68) winsize 61
3160 12:18:29.204727 [CA 1] Center 37 (7~68) winsize 62
3161 12:18:29.208114 [CA 2] Center 35 (4~66) winsize 63
3162 12:18:29.210993 [CA 3] Center 34 (4~65) winsize 62
3163 12:18:29.215069 [CA 4] Center 34 (4~64) winsize 61
3164 12:18:29.218504 [CA 5] Center 33 (3~63) winsize 61
3165 12:18:29.219079
3166 12:18:29.221338 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3167 12:18:29.221889
3168 12:18:29.224670 [CATrainingPosCal] consider 2 rank data
3169 12:18:29.228224 u2DelayCellTimex100 = 270/100 ps
3170 12:18:29.231331 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3171 12:18:29.234714 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3172 12:18:29.241081 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3173 12:18:29.244606 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3174 12:18:29.248392 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3175 12:18:29.251945 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3176 12:18:29.252526
3177 12:18:29.254830 CA PerBit enable=1, Macro0, CA PI delay=33
3178 12:18:29.255409
3179 12:18:29.258022 [CBTSetCACLKResult] CA Dly = 33
3180 12:18:29.258594 CS Dly: 6 (0~38)
3181 12:18:29.258991
3182 12:18:29.261223 ----->DramcWriteLeveling(PI) begin...
3183 12:18:29.264784 ==
3184 12:18:29.265356 Dram Type= 6, Freq= 0, CH_1, rank 0
3185 12:18:29.271410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3186 12:18:29.271990 ==
3187 12:18:29.274459 Write leveling (Byte 0): 23 => 23
3188 12:18:29.278134 Write leveling (Byte 1): 25 => 25
3189 12:18:29.278712 DramcWriteLeveling(PI) end<-----
3190 12:18:29.281239
3191 12:18:29.281809 ==
3192 12:18:29.284565 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 12:18:29.288073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 12:18:29.288665 ==
3195 12:18:29.291225 [Gating] SW mode calibration
3196 12:18:29.298101 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3197 12:18:29.301206 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3198 12:18:29.307865 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 12:18:29.311409 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 12:18:29.314538 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 12:18:29.321252 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 12:18:29.324764 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 12:18:29.328205 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 12:18:29.334577 0 15 24 | B1->B0 | 2e2e 2828 | 0 0 | (0 1) (0 1)
3205 12:18:29.337649 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3206 12:18:29.341365 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 12:18:29.348673 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 12:18:29.351003 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 12:18:29.354630 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 12:18:29.361259 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 12:18:29.364676 1 0 20 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
3212 12:18:29.367863 1 0 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3213 12:18:29.374764 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 12:18:29.378575 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 12:18:29.381732 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 12:18:29.384345 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 12:18:29.391342 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 12:18:29.394616 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 12:18:29.397993 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3220 12:18:29.404951 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3221 12:18:29.408170 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3222 12:18:29.411876 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 12:18:29.418415 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 12:18:29.421727 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 12:18:29.424962 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 12:18:29.432191 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 12:18:29.434964 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 12:18:29.438094 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 12:18:29.444749 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 12:18:29.448050 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 12:18:29.451573 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 12:18:29.454957 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 12:18:29.462063 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 12:18:29.465087 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 12:18:29.467968 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3236 12:18:29.475377 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3237 12:18:29.478579 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3238 12:18:29.482156 Total UI for P1: 0, mck2ui 16
3239 12:18:29.485058 best dqsien dly found for B0: ( 1, 3, 22)
3240 12:18:29.488482 Total UI for P1: 0, mck2ui 16
3241 12:18:29.491409 best dqsien dly found for B1: ( 1, 3, 24)
3242 12:18:29.494648 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3243 12:18:29.497995 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3244 12:18:29.498483
3245 12:18:29.501482 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3246 12:18:29.505054 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3247 12:18:29.508275 [Gating] SW calibration Done
3248 12:18:29.508840 ==
3249 12:18:29.511827 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 12:18:29.514920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 12:18:29.518381 ==
3252 12:18:29.518945 RX Vref Scan: 0
3253 12:18:29.519324
3254 12:18:29.521976 RX Vref 0 -> 0, step: 1
3255 12:18:29.522572
3256 12:18:29.524909 RX Delay -40 -> 252, step: 8
3257 12:18:29.528466 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3258 12:18:29.531366 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3259 12:18:29.535032 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3260 12:18:29.538510 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3261 12:18:29.545091 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3262 12:18:29.548193 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3263 12:18:29.551817 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3264 12:18:29.555279 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3265 12:18:29.559120 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3266 12:18:29.562143 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3267 12:18:29.568528 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3268 12:18:29.571986 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3269 12:18:29.575287 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3270 12:18:29.578791 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3271 12:18:29.582049 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3272 12:18:29.588603 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3273 12:18:29.589113 ==
3274 12:18:29.591587 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 12:18:29.595242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 12:18:29.595810 ==
3277 12:18:29.596226 DQS Delay:
3278 12:18:29.598825 DQS0 = 0, DQS1 = 0
3279 12:18:29.599289 DQM Delay:
3280 12:18:29.601879 DQM0 = 120, DQM1 = 113
3281 12:18:29.602505 DQ Delay:
3282 12:18:29.605336 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3283 12:18:29.608853 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3284 12:18:29.612244 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3285 12:18:29.615218 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3286 12:18:29.615682
3287 12:18:29.616051
3288 12:18:29.618858 ==
3289 12:18:29.619610 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 12:18:29.625246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 12:18:29.625718 ==
3292 12:18:29.626130
3293 12:18:29.626480
3294 12:18:29.626807 TX Vref Scan disable
3295 12:18:29.629343 == TX Byte 0 ==
3296 12:18:29.632835 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3297 12:18:29.635987 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3298 12:18:29.639145 == TX Byte 1 ==
3299 12:18:29.642686 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3300 12:18:29.646272 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3301 12:18:29.649456 ==
3302 12:18:29.650291 Dram Type= 6, Freq= 0, CH_1, rank 0
3303 12:18:29.655785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3304 12:18:29.656411 ==
3305 12:18:29.666892 TX Vref=22, minBit 1, minWin=24, winSum=397
3306 12:18:29.669834 TX Vref=24, minBit 7, minWin=24, winSum=404
3307 12:18:29.673452 TX Vref=26, minBit 10, minWin=23, winSum=407
3308 12:18:29.676927 TX Vref=28, minBit 8, minWin=25, winSum=416
3309 12:18:29.680087 TX Vref=30, minBit 10, minWin=25, winSum=420
3310 12:18:29.686623 TX Vref=32, minBit 9, minWin=25, winSum=416
3311 12:18:29.689612 [TxChooseVref] Worse bit 10, Min win 25, Win sum 420, Final Vref 30
3312 12:18:29.689982
3313 12:18:29.693103 Final TX Range 1 Vref 30
3314 12:18:29.693431
3315 12:18:29.693653 ==
3316 12:18:29.696495 Dram Type= 6, Freq= 0, CH_1, rank 0
3317 12:18:29.700343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3318 12:18:29.700587 ==
3319 12:18:29.703166
3320 12:18:29.703406
3321 12:18:29.703600 TX Vref Scan disable
3322 12:18:29.707034 == TX Byte 0 ==
3323 12:18:29.710252 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3324 12:18:29.713298 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3325 12:18:29.716750 == TX Byte 1 ==
3326 12:18:29.720122 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3327 12:18:29.724017 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3328 12:18:29.724483
3329 12:18:29.726592 [DATLAT]
3330 12:18:29.727056 Freq=1200, CH1 RK0
3331 12:18:29.727430
3332 12:18:29.730137 DATLAT Default: 0xd
3333 12:18:29.730605 0, 0xFFFF, sum = 0
3334 12:18:29.733492 1, 0xFFFF, sum = 0
3335 12:18:29.734008 2, 0xFFFF, sum = 0
3336 12:18:29.737066 3, 0xFFFF, sum = 0
3337 12:18:29.737537 4, 0xFFFF, sum = 0
3338 12:18:29.740110 5, 0xFFFF, sum = 0
3339 12:18:29.740481 6, 0xFFFF, sum = 0
3340 12:18:29.743451 7, 0xFFFF, sum = 0
3341 12:18:29.743696 8, 0xFFFF, sum = 0
3342 12:18:29.746680 9, 0xFFFF, sum = 0
3343 12:18:29.749980 10, 0xFFFF, sum = 0
3344 12:18:29.750178 11, 0xFFFF, sum = 0
3345 12:18:29.753176 12, 0x0, sum = 1
3346 12:18:29.753380 13, 0x0, sum = 2
3347 12:18:29.753509 14, 0x0, sum = 3
3348 12:18:29.756569 15, 0x0, sum = 4
3349 12:18:29.756732 best_step = 13
3350 12:18:29.756860
3351 12:18:29.760330 ==
3352 12:18:29.760488 Dram Type= 6, Freq= 0, CH_1, rank 0
3353 12:18:29.766682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3354 12:18:29.766842 ==
3355 12:18:29.766972 RX Vref Scan: 1
3356 12:18:29.767092
3357 12:18:29.770152 Set Vref Range= 32 -> 127
3358 12:18:29.770312
3359 12:18:29.773347 RX Vref 32 -> 127, step: 1
3360 12:18:29.773504
3361 12:18:29.776841 RX Delay -13 -> 252, step: 4
3362 12:18:29.776998
3363 12:18:29.780153 Set Vref, RX VrefLevel [Byte0]: 32
3364 12:18:29.783204 [Byte1]: 32
3365 12:18:29.783360
3366 12:18:29.786539 Set Vref, RX VrefLevel [Byte0]: 33
3367 12:18:29.789635 [Byte1]: 33
3368 12:18:29.789791
3369 12:18:29.793431 Set Vref, RX VrefLevel [Byte0]: 34
3370 12:18:29.796738 [Byte1]: 34
3371 12:18:29.800810
3372 12:18:29.800965 Set Vref, RX VrefLevel [Byte0]: 35
3373 12:18:29.803904 [Byte1]: 35
3374 12:18:29.808502
3375 12:18:29.808664 Set Vref, RX VrefLevel [Byte0]: 36
3376 12:18:29.812159 [Byte1]: 36
3377 12:18:29.816391
3378 12:18:29.816603 Set Vref, RX VrefLevel [Byte0]: 37
3379 12:18:29.819877 [Byte1]: 37
3380 12:18:29.824831
3381 12:18:29.825131 Set Vref, RX VrefLevel [Byte0]: 38
3382 12:18:29.831149 [Byte1]: 38
3383 12:18:29.831495
3384 12:18:29.834418 Set Vref, RX VrefLevel [Byte0]: 39
3385 12:18:29.838190 [Byte1]: 39
3386 12:18:29.838709
3387 12:18:29.840916 Set Vref, RX VrefLevel [Byte0]: 40
3388 12:18:29.844846 [Byte1]: 40
3389 12:18:29.848476
3390 12:18:29.849029 Set Vref, RX VrefLevel [Byte0]: 41
3391 12:18:29.851969 [Byte1]: 41
3392 12:18:29.856346
3393 12:18:29.856902 Set Vref, RX VrefLevel [Byte0]: 42
3394 12:18:29.859583 [Byte1]: 42
3395 12:18:29.863962
3396 12:18:29.864416 Set Vref, RX VrefLevel [Byte0]: 43
3397 12:18:29.867360 [Byte1]: 43
3398 12:18:29.872040
3399 12:18:29.872606 Set Vref, RX VrefLevel [Byte0]: 44
3400 12:18:29.875108 [Byte1]: 44
3401 12:18:29.880289
3402 12:18:29.880845 Set Vref, RX VrefLevel [Byte0]: 45
3403 12:18:29.882906 [Byte1]: 45
3404 12:18:29.887919
3405 12:18:29.888373 Set Vref, RX VrefLevel [Byte0]: 46
3406 12:18:29.891132 [Byte1]: 46
3407 12:18:29.895993
3408 12:18:29.896605 Set Vref, RX VrefLevel [Byte0]: 47
3409 12:18:29.899014 [Byte1]: 47
3410 12:18:29.903738
3411 12:18:29.904298 Set Vref, RX VrefLevel [Byte0]: 48
3412 12:18:29.906875 [Byte1]: 48
3413 12:18:29.911383
3414 12:18:29.911938 Set Vref, RX VrefLevel [Byte0]: 49
3415 12:18:29.914761 [Byte1]: 49
3416 12:18:29.919626
3417 12:18:29.920375 Set Vref, RX VrefLevel [Byte0]: 50
3418 12:18:29.922639 [Byte1]: 50
3419 12:18:29.927466
3420 12:18:29.928023 Set Vref, RX VrefLevel [Byte0]: 51
3421 12:18:29.930836 [Byte1]: 51
3422 12:18:29.935407
3423 12:18:29.935965 Set Vref, RX VrefLevel [Byte0]: 52
3424 12:18:29.938874 [Byte1]: 52
3425 12:18:29.943136
3426 12:18:29.943602 Set Vref, RX VrefLevel [Byte0]: 53
3427 12:18:29.946588 [Byte1]: 53
3428 12:18:29.951010
3429 12:18:29.951595 Set Vref, RX VrefLevel [Byte0]: 54
3430 12:18:29.954285 [Byte1]: 54
3431 12:18:29.959329
3432 12:18:29.960045 Set Vref, RX VrefLevel [Byte0]: 55
3433 12:18:29.962154 [Byte1]: 55
3434 12:18:29.966930
3435 12:18:29.967506 Set Vref, RX VrefLevel [Byte0]: 56
3436 12:18:29.969780 [Byte1]: 56
3437 12:18:29.974346
3438 12:18:29.974811 Set Vref, RX VrefLevel [Byte0]: 57
3439 12:18:29.977773 [Byte1]: 57
3440 12:18:29.982456
3441 12:18:29.983190 Set Vref, RX VrefLevel [Byte0]: 58
3442 12:18:29.985488 [Byte1]: 58
3443 12:18:29.990312
3444 12:18:29.990778 Set Vref, RX VrefLevel [Byte0]: 59
3445 12:18:29.993544 [Byte1]: 59
3446 12:18:29.998598
3447 12:18:29.999160 Set Vref, RX VrefLevel [Byte0]: 60
3448 12:18:30.001988 [Byte1]: 60
3449 12:18:30.006259
3450 12:18:30.006827 Set Vref, RX VrefLevel [Byte0]: 61
3451 12:18:30.009631 [Byte1]: 61
3452 12:18:30.014098
3453 12:18:30.014659 Set Vref, RX VrefLevel [Byte0]: 62
3454 12:18:30.017902 [Byte1]: 62
3455 12:18:30.022143
3456 12:18:30.022748 Set Vref, RX VrefLevel [Byte0]: 63
3457 12:18:30.025569 [Byte1]: 63
3458 12:18:30.029789
3459 12:18:30.030405 Set Vref, RX VrefLevel [Byte0]: 64
3460 12:18:30.033031 [Byte1]: 64
3461 12:18:30.037831
3462 12:18:30.038456 Set Vref, RX VrefLevel [Byte0]: 65
3463 12:18:30.040959 [Byte1]: 65
3464 12:18:30.045850
3465 12:18:30.046465 Set Vref, RX VrefLevel [Byte0]: 66
3466 12:18:30.048839 [Byte1]: 66
3467 12:18:30.053581
3468 12:18:30.054199 Set Vref, RX VrefLevel [Byte0]: 67
3469 12:18:30.057115 [Byte1]: 67
3470 12:18:30.061301
3471 12:18:30.061876 Final RX Vref Byte 0 = 53 to rank0
3472 12:18:30.065363 Final RX Vref Byte 1 = 53 to rank0
3473 12:18:30.067951 Final RX Vref Byte 0 = 53 to rank1
3474 12:18:30.071402 Final RX Vref Byte 1 = 53 to rank1==
3475 12:18:30.074714 Dram Type= 6, Freq= 0, CH_1, rank 0
3476 12:18:30.078134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3477 12:18:30.081407 ==
3478 12:18:30.081880 DQS Delay:
3479 12:18:30.082287 DQS0 = 0, DQS1 = 0
3480 12:18:30.084982 DQM Delay:
3481 12:18:30.085608 DQM0 = 119, DQM1 = 112
3482 12:18:30.087917 DQ Delay:
3483 12:18:30.091584 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3484 12:18:30.095236 DQ4 =118, DQ5 =126, DQ6 =130, DQ7 =118
3485 12:18:30.098273 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3486 12:18:30.101635 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =118
3487 12:18:30.102251
3488 12:18:30.102633
3489 12:18:30.108513 [DQSOSCAuto] RK0, (LSB)MR18= 0x518, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 408 ps
3490 12:18:30.111429 CH1 RK0: MR19=404, MR18=518
3491 12:18:30.118299 CH1_RK0: MR19=0x404, MR18=0x518, DQSOSC=400, MR23=63, INC=40, DEC=27
3492 12:18:30.118874
3493 12:18:30.121842 ----->DramcWriteLeveling(PI) begin...
3494 12:18:30.122444 ==
3495 12:18:30.124664 Dram Type= 6, Freq= 0, CH_1, rank 1
3496 12:18:30.128292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3497 12:18:30.128866 ==
3498 12:18:30.131653 Write leveling (Byte 0): 26 => 26
3499 12:18:30.135086 Write leveling (Byte 1): 30 => 30
3500 12:18:30.138129 DramcWriteLeveling(PI) end<-----
3501 12:18:30.138695
3502 12:18:30.139071 ==
3503 12:18:30.141819 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 12:18:30.144577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 12:18:30.148489 ==
3506 12:18:30.149058 [Gating] SW mode calibration
3507 12:18:30.158294 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3508 12:18:30.161613 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3509 12:18:30.164724 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 12:18:30.171415 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 12:18:30.174707 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 12:18:30.178293 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3513 12:18:30.184842 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3514 12:18:30.188225 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3515 12:18:30.191360 0 15 24 | B1->B0 | 2b2b 3434 | 0 0 | (0 0) (0 1)
3516 12:18:30.198240 0 15 28 | B1->B0 | 2323 2a2a | 0 1 | (1 0) (1 0)
3517 12:18:30.201731 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 12:18:30.205031 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 12:18:30.211432 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 12:18:30.214796 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3521 12:18:30.218012 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3522 12:18:30.224873 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3523 12:18:30.228070 1 0 24 | B1->B0 | 3e3e 2a2a | 0 0 | (0 0) (1 1)
3524 12:18:30.231615 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3525 12:18:30.234822 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 12:18:30.241472 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 12:18:30.244941 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 12:18:30.248229 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3529 12:18:30.254873 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3530 12:18:30.258274 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 12:18:30.261508 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3532 12:18:30.268417 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3533 12:18:30.271559 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 12:18:30.274673 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 12:18:30.282002 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 12:18:30.284723 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 12:18:30.288275 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 12:18:30.294646 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 12:18:30.298233 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 12:18:30.301473 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 12:18:30.308198 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 12:18:30.311521 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 12:18:30.315178 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 12:18:30.321702 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 12:18:30.325220 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 12:18:30.327865 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 12:18:30.334519 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3548 12:18:30.337964 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3549 12:18:30.340925 Total UI for P1: 0, mck2ui 16
3550 12:18:30.344569 best dqsien dly found for B0: ( 1, 3, 24)
3551 12:18:30.347770 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3552 12:18:30.351290 Total UI for P1: 0, mck2ui 16
3553 12:18:30.354551 best dqsien dly found for B1: ( 1, 3, 26)
3554 12:18:30.358193 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3555 12:18:30.361472 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3556 12:18:30.362088
3557 12:18:30.364439 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3558 12:18:30.371141 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3559 12:18:30.371713 [Gating] SW calibration Done
3560 12:18:30.372087 ==
3561 12:18:30.374332 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 12:18:30.380828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 12:18:30.381377 ==
3564 12:18:30.381758 RX Vref Scan: 0
3565 12:18:30.382168
3566 12:18:30.384497 RX Vref 0 -> 0, step: 1
3567 12:18:30.385078
3568 12:18:30.387342 RX Delay -40 -> 252, step: 8
3569 12:18:30.390606 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3570 12:18:30.394073 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3571 12:18:30.397335 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3572 12:18:30.404272 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3573 12:18:30.407717 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3574 12:18:30.410598 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3575 12:18:30.414109 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3576 12:18:30.417409 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3577 12:18:30.424059 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3578 12:18:30.427231 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3579 12:18:30.430961 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3580 12:18:30.434507 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3581 12:18:30.437853 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3582 12:18:30.444193 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3583 12:18:30.448089 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3584 12:18:30.450708 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3585 12:18:30.451183 ==
3586 12:18:30.454030 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 12:18:30.457657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 12:18:30.458270 ==
3589 12:18:30.460791 DQS Delay:
3590 12:18:30.461353 DQS0 = 0, DQS1 = 0
3591 12:18:30.464063 DQM Delay:
3592 12:18:30.464626 DQM0 = 119, DQM1 = 112
3593 12:18:30.465005 DQ Delay:
3594 12:18:30.467184 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =119
3595 12:18:30.470819 DQ4 =119, DQ5 =131, DQ6 =123, DQ7 =115
3596 12:18:30.477529 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3597 12:18:30.480881 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3598 12:18:30.481445
3599 12:18:30.481822
3600 12:18:30.482226 ==
3601 12:18:30.483987 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 12:18:30.487688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 12:18:30.488263 ==
3604 12:18:30.488647
3605 12:18:30.489013
3606 12:18:30.490868 TX Vref Scan disable
3607 12:18:30.491329 == TX Byte 0 ==
3608 12:18:30.496939 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3609 12:18:30.500693 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3610 12:18:30.501347 == TX Byte 1 ==
3611 12:18:30.507509 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3612 12:18:30.510473 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3613 12:18:30.510953 ==
3614 12:18:30.513494 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 12:18:30.517126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 12:18:30.517691 ==
3617 12:18:30.530324 TX Vref=22, minBit 11, minWin=24, winSum=412
3618 12:18:30.533729 TX Vref=24, minBit 1, minWin=25, winSum=416
3619 12:18:30.536961 TX Vref=26, minBit 1, minWin=26, winSum=424
3620 12:18:30.540251 TX Vref=28, minBit 0, minWin=26, winSum=425
3621 12:18:30.543906 TX Vref=30, minBit 1, minWin=26, winSum=427
3622 12:18:30.550533 TX Vref=32, minBit 9, minWin=26, winSum=426
3623 12:18:30.554205 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 30
3624 12:18:30.554769
3625 12:18:30.557356 Final TX Range 1 Vref 30
3626 12:18:30.557925
3627 12:18:30.558345 ==
3628 12:18:30.560290 Dram Type= 6, Freq= 0, CH_1, rank 1
3629 12:18:30.563666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3630 12:18:30.564239 ==
3631 12:18:30.564612
3632 12:18:30.567121
3633 12:18:30.567584 TX Vref Scan disable
3634 12:18:30.570561 == TX Byte 0 ==
3635 12:18:30.573818 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3636 12:18:30.577337 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3637 12:18:30.580545 == TX Byte 1 ==
3638 12:18:30.583683 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3639 12:18:30.587047 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3640 12:18:30.590085
3641 12:18:30.590549 [DATLAT]
3642 12:18:30.590916 Freq=1200, CH1 RK1
3643 12:18:30.591261
3644 12:18:30.593322 DATLAT Default: 0xd
3645 12:18:30.593825 0, 0xFFFF, sum = 0
3646 12:18:30.596821 1, 0xFFFF, sum = 0
3647 12:18:30.597442 2, 0xFFFF, sum = 0
3648 12:18:30.600179 3, 0xFFFF, sum = 0
3649 12:18:30.603316 4, 0xFFFF, sum = 0
3650 12:18:30.603940 5, 0xFFFF, sum = 0
3651 12:18:30.606738 6, 0xFFFF, sum = 0
3652 12:18:30.607208 7, 0xFFFF, sum = 0
3653 12:18:30.610578 8, 0xFFFF, sum = 0
3654 12:18:30.611160 9, 0xFFFF, sum = 0
3655 12:18:30.613169 10, 0xFFFF, sum = 0
3656 12:18:30.613643 11, 0xFFFF, sum = 0
3657 12:18:30.616940 12, 0x0, sum = 1
3658 12:18:30.617522 13, 0x0, sum = 2
3659 12:18:30.619995 14, 0x0, sum = 3
3660 12:18:30.620604 15, 0x0, sum = 4
3661 12:18:30.623025 best_step = 13
3662 12:18:30.623493
3663 12:18:30.623863 ==
3664 12:18:30.626831 Dram Type= 6, Freq= 0, CH_1, rank 1
3665 12:18:30.629897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3666 12:18:30.630395 ==
3667 12:18:30.630792 RX Vref Scan: 0
3668 12:18:30.631150
3669 12:18:30.633016 RX Vref 0 -> 0, step: 1
3670 12:18:30.633481
3671 12:18:30.636397 RX Delay -13 -> 252, step: 4
3672 12:18:30.639679 iDelay=191, Bit 0, Center 122 (63 ~ 182) 120
3673 12:18:30.646573 iDelay=191, Bit 1, Center 114 (55 ~ 174) 120
3674 12:18:30.649670 iDelay=191, Bit 2, Center 108 (51 ~ 166) 116
3675 12:18:30.652658 iDelay=191, Bit 3, Center 118 (59 ~ 178) 120
3676 12:18:30.655912 iDelay=191, Bit 4, Center 122 (63 ~ 182) 120
3677 12:18:30.659373 iDelay=191, Bit 5, Center 128 (67 ~ 190) 124
3678 12:18:30.666128 iDelay=191, Bit 6, Center 126 (67 ~ 186) 120
3679 12:18:30.669534 iDelay=191, Bit 7, Center 118 (59 ~ 178) 120
3680 12:18:30.672903 iDelay=191, Bit 8, Center 98 (35 ~ 162) 128
3681 12:18:30.676041 iDelay=191, Bit 9, Center 102 (39 ~ 166) 128
3682 12:18:30.679316 iDelay=191, Bit 10, Center 114 (51 ~ 178) 128
3683 12:18:30.686468 iDelay=191, Bit 11, Center 108 (43 ~ 174) 132
3684 12:18:30.689258 iDelay=191, Bit 12, Center 122 (59 ~ 186) 128
3685 12:18:30.692711 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3686 12:18:30.696188 iDelay=191, Bit 14, Center 122 (59 ~ 186) 128
3687 12:18:30.699894 iDelay=191, Bit 15, Center 124 (59 ~ 190) 132
3688 12:18:30.702696 ==
3689 12:18:30.706533 Dram Type= 6, Freq= 0, CH_1, rank 1
3690 12:18:30.709329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3691 12:18:30.709808 ==
3692 12:18:30.710238 DQS Delay:
3693 12:18:30.712869 DQS0 = 0, DQS1 = 0
3694 12:18:30.713431 DQM Delay:
3695 12:18:30.716023 DQM0 = 119, DQM1 = 113
3696 12:18:30.716490 DQ Delay:
3697 12:18:30.719349 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3698 12:18:30.722810 DQ4 =122, DQ5 =128, DQ6 =126, DQ7 =118
3699 12:18:30.726154 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =108
3700 12:18:30.730229 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3701 12:18:30.730794
3702 12:18:30.731169
3703 12:18:30.739189 [DQSOSCAuto] RK1, (LSB)MR18= 0x7eb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 407 ps
3704 12:18:30.739752 CH1 RK1: MR19=403, MR18=7EB
3705 12:18:30.746085 CH1_RK1: MR19=0x403, MR18=0x7EB, DQSOSC=407, MR23=63, INC=39, DEC=26
3706 12:18:30.749461 [RxdqsGatingPostProcess] freq 1200
3707 12:18:30.755871 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3708 12:18:30.759241 best DQS0 dly(2T, 0.5T) = (0, 11)
3709 12:18:30.762649 best DQS1 dly(2T, 0.5T) = (0, 11)
3710 12:18:30.766104 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3711 12:18:30.769132 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3712 12:18:30.772902 best DQS0 dly(2T, 0.5T) = (0, 11)
3713 12:18:30.776445 best DQS1 dly(2T, 0.5T) = (0, 11)
3714 12:18:30.779983 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3715 12:18:30.780546 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3716 12:18:30.782779 Pre-setting of DQS Precalculation
3717 12:18:30.789433 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3718 12:18:30.795633 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3719 12:18:30.802483 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3720 12:18:30.803053
3721 12:18:30.803491
3722 12:18:30.805813 [Calibration Summary] 2400 Mbps
3723 12:18:30.808905 CH 0, Rank 0
3724 12:18:30.809366 SW Impedance : PASS
3725 12:18:30.812258 DUTY Scan : NO K
3726 12:18:30.815709 ZQ Calibration : PASS
3727 12:18:30.816275 Jitter Meter : NO K
3728 12:18:30.819000 CBT Training : PASS
3729 12:18:30.822307 Write leveling : PASS
3730 12:18:30.822874 RX DQS gating : PASS
3731 12:18:30.825615 RX DQ/DQS(RDDQC) : PASS
3732 12:18:30.826108 TX DQ/DQS : PASS
3733 12:18:30.828756 RX DATLAT : PASS
3734 12:18:30.832125 RX DQ/DQS(Engine): PASS
3735 12:18:30.832588 TX OE : NO K
3736 12:18:30.835457 All Pass.
3737 12:18:30.835919
3738 12:18:30.836284 CH 0, Rank 1
3739 12:18:30.839400 SW Impedance : PASS
3740 12:18:30.839994 DUTY Scan : NO K
3741 12:18:30.841914 ZQ Calibration : PASS
3742 12:18:30.845447 Jitter Meter : NO K
3743 12:18:30.846069 CBT Training : PASS
3744 12:18:30.848888 Write leveling : PASS
3745 12:18:30.852756 RX DQS gating : PASS
3746 12:18:30.853331 RX DQ/DQS(RDDQC) : PASS
3747 12:18:30.855123 TX DQ/DQS : PASS
3748 12:18:30.859008 RX DATLAT : PASS
3749 12:18:30.859574 RX DQ/DQS(Engine): PASS
3750 12:18:30.862137 TX OE : NO K
3751 12:18:30.862699 All Pass.
3752 12:18:30.863074
3753 12:18:30.865293 CH 1, Rank 0
3754 12:18:30.865859 SW Impedance : PASS
3755 12:18:30.869040 DUTY Scan : NO K
3756 12:18:30.871968 ZQ Calibration : PASS
3757 12:18:30.872435 Jitter Meter : NO K
3758 12:18:30.875026 CBT Training : PASS
3759 12:18:30.878391 Write leveling : PASS
3760 12:18:30.878854 RX DQS gating : PASS
3761 12:18:30.881637 RX DQ/DQS(RDDQC) : PASS
3762 12:18:30.882139 TX DQ/DQS : PASS
3763 12:18:30.884843 RX DATLAT : PASS
3764 12:18:30.888901 RX DQ/DQS(Engine): PASS
3765 12:18:30.889465 TX OE : NO K
3766 12:18:30.891911 All Pass.
3767 12:18:30.892557
3768 12:18:30.892935 CH 1, Rank 1
3769 12:18:30.895425 SW Impedance : PASS
3770 12:18:30.895887 DUTY Scan : NO K
3771 12:18:30.898492 ZQ Calibration : PASS
3772 12:18:30.901712 Jitter Meter : NO K
3773 12:18:30.902236 CBT Training : PASS
3774 12:18:30.905384 Write leveling : PASS
3775 12:18:30.908650 RX DQS gating : PASS
3776 12:18:30.909232 RX DQ/DQS(RDDQC) : PASS
3777 12:18:30.911850 TX DQ/DQS : PASS
3778 12:18:30.914892 RX DATLAT : PASS
3779 12:18:30.915358 RX DQ/DQS(Engine): PASS
3780 12:18:30.918206 TX OE : NO K
3781 12:18:30.918676 All Pass.
3782 12:18:30.919046
3783 12:18:30.921628 DramC Write-DBI off
3784 12:18:30.925350 PER_BANK_REFRESH: Hybrid Mode
3785 12:18:30.925816 TX_TRACKING: ON
3786 12:18:30.935099 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3787 12:18:30.938527 [FAST_K] Save calibration result to emmc
3788 12:18:30.941715 dramc_set_vcore_voltage set vcore to 650000
3789 12:18:30.945188 Read voltage for 600, 5
3790 12:18:30.945668 Vio18 = 0
3791 12:18:30.946193 Vcore = 650000
3792 12:18:30.948380 Vdram = 0
3793 12:18:30.948861 Vddq = 0
3794 12:18:30.949342 Vmddr = 0
3795 12:18:30.955262 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3796 12:18:30.958685 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3797 12:18:30.961781 MEM_TYPE=3, freq_sel=19
3798 12:18:30.964924 sv_algorithm_assistance_LP4_1600
3799 12:18:30.968189 ============ PULL DRAM RESETB DOWN ============
3800 12:18:30.971546 ========== PULL DRAM RESETB DOWN end =========
3801 12:18:30.978612 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3802 12:18:30.982192 ===================================
3803 12:18:30.982757 LPDDR4 DRAM CONFIGURATION
3804 12:18:30.984832 ===================================
3805 12:18:30.988884 EX_ROW_EN[0] = 0x0
3806 12:18:30.991732 EX_ROW_EN[1] = 0x0
3807 12:18:30.992362 LP4Y_EN = 0x0
3808 12:18:30.995210 WORK_FSP = 0x0
3809 12:18:30.995679 WL = 0x2
3810 12:18:30.998237 RL = 0x2
3811 12:18:30.998805 BL = 0x2
3812 12:18:31.001752 RPST = 0x0
3813 12:18:31.002287 RD_PRE = 0x0
3814 12:18:31.004777 WR_PRE = 0x1
3815 12:18:31.005343 WR_PST = 0x0
3816 12:18:31.008298 DBI_WR = 0x0
3817 12:18:31.008788 DBI_RD = 0x0
3818 12:18:31.011451 OTF = 0x1
3819 12:18:31.015097 ===================================
3820 12:18:31.018007 ===================================
3821 12:18:31.018485 ANA top config
3822 12:18:31.021590 ===================================
3823 12:18:31.025082 DLL_ASYNC_EN = 0
3824 12:18:31.028200 ALL_SLAVE_EN = 1
3825 12:18:31.031362 NEW_RANK_MODE = 1
3826 12:18:31.031935 DLL_IDLE_MODE = 1
3827 12:18:31.034612 LP45_APHY_COMB_EN = 1
3828 12:18:31.038142 TX_ODT_DIS = 1
3829 12:18:31.041388 NEW_8X_MODE = 1
3830 12:18:31.044749 ===================================
3831 12:18:31.047835 ===================================
3832 12:18:31.051638 data_rate = 1200
3833 12:18:31.052204 CKR = 1
3834 12:18:31.054624 DQ_P2S_RATIO = 8
3835 12:18:31.058237 ===================================
3836 12:18:31.061316 CA_P2S_RATIO = 8
3837 12:18:31.064622 DQ_CA_OPEN = 0
3838 12:18:31.067938 DQ_SEMI_OPEN = 0
3839 12:18:31.071139 CA_SEMI_OPEN = 0
3840 12:18:31.071699 CA_FULL_RATE = 0
3841 12:18:31.074483 DQ_CKDIV4_EN = 1
3842 12:18:31.078110 CA_CKDIV4_EN = 1
3843 12:18:31.081107 CA_PREDIV_EN = 0
3844 12:18:31.084525 PH8_DLY = 0
3845 12:18:31.087761 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3846 12:18:31.088229 DQ_AAMCK_DIV = 4
3847 12:18:31.091352 CA_AAMCK_DIV = 4
3848 12:18:31.094233 CA_ADMCK_DIV = 4
3849 12:18:31.097900 DQ_TRACK_CA_EN = 0
3850 12:18:31.101198 CA_PICK = 600
3851 12:18:31.104470 CA_MCKIO = 600
3852 12:18:31.105034 MCKIO_SEMI = 0
3853 12:18:31.107829 PLL_FREQ = 2288
3854 12:18:31.111252 DQ_UI_PI_RATIO = 32
3855 12:18:31.114461 CA_UI_PI_RATIO = 0
3856 12:18:31.117541 ===================================
3857 12:18:31.121145 ===================================
3858 12:18:31.124284 memory_type:LPDDR4
3859 12:18:31.124851 GP_NUM : 10
3860 12:18:31.127547 SRAM_EN : 1
3861 12:18:31.131239 MD32_EN : 0
3862 12:18:31.134355 ===================================
3863 12:18:31.134925 [ANA_INIT] >>>>>>>>>>>>>>
3864 12:18:31.137820 <<<<<< [CONFIGURE PHASE]: ANA_TX
3865 12:18:31.140850 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3866 12:18:31.143973 ===================================
3867 12:18:31.147390 data_rate = 1200,PCW = 0X5800
3868 12:18:31.151061 ===================================
3869 12:18:31.154078 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3870 12:18:31.160863 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3871 12:18:31.164277 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3872 12:18:31.170851 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3873 12:18:31.173988 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3874 12:18:31.177568 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3875 12:18:31.178217 [ANA_INIT] flow start
3876 12:18:31.180635 [ANA_INIT] PLL >>>>>>>>
3877 12:18:31.184040 [ANA_INIT] PLL <<<<<<<<
3878 12:18:31.187380 [ANA_INIT] MIDPI >>>>>>>>
3879 12:18:31.187949 [ANA_INIT] MIDPI <<<<<<<<
3880 12:18:31.190699 [ANA_INIT] DLL >>>>>>>>
3881 12:18:31.191170 [ANA_INIT] flow end
3882 12:18:31.197414 ============ LP4 DIFF to SE enter ============
3883 12:18:31.200705 ============ LP4 DIFF to SE exit ============
3884 12:18:31.204250 [ANA_INIT] <<<<<<<<<<<<<
3885 12:18:31.207186 [Flow] Enable top DCM control >>>>>
3886 12:18:31.210773 [Flow] Enable top DCM control <<<<<
3887 12:18:31.214143 Enable DLL master slave shuffle
3888 12:18:31.217140 ==============================================================
3889 12:18:31.220555 Gating Mode config
3890 12:18:31.223912 ==============================================================
3891 12:18:31.227346 Config description:
3892 12:18:31.237308 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3893 12:18:31.243694 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3894 12:18:31.247130 SELPH_MODE 0: By rank 1: By Phase
3895 12:18:31.253568 ==============================================================
3896 12:18:31.257297 GAT_TRACK_EN = 1
3897 12:18:31.260228 RX_GATING_MODE = 2
3898 12:18:31.263722 RX_GATING_TRACK_MODE = 2
3899 12:18:31.267063 SELPH_MODE = 1
3900 12:18:31.270139 PICG_EARLY_EN = 1
3901 12:18:31.270612 VALID_LAT_VALUE = 1
3902 12:18:31.277166 ==============================================================
3903 12:18:31.280312 Enter into Gating configuration >>>>
3904 12:18:31.283956 Exit from Gating configuration <<<<
3905 12:18:31.286729 Enter into DVFS_PRE_config >>>>>
3906 12:18:31.297217 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3907 12:18:31.300297 Exit from DVFS_PRE_config <<<<<
3908 12:18:31.303540 Enter into PICG configuration >>>>
3909 12:18:31.307231 Exit from PICG configuration <<<<
3910 12:18:31.310509 [RX_INPUT] configuration >>>>>
3911 12:18:31.314077 [RX_INPUT] configuration <<<<<
3912 12:18:31.316952 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3913 12:18:31.323557 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3914 12:18:31.330373 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3915 12:18:31.337189 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3916 12:18:31.343683 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3917 12:18:31.346975 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3918 12:18:31.353762 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3919 12:18:31.357163 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3920 12:18:31.360342 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3921 12:18:31.363824 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3922 12:18:31.370067 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3923 12:18:31.373511 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3924 12:18:31.376791 ===================================
3925 12:18:31.380382 LPDDR4 DRAM CONFIGURATION
3926 12:18:31.383583 ===================================
3927 12:18:31.384154 EX_ROW_EN[0] = 0x0
3928 12:18:31.386731 EX_ROW_EN[1] = 0x0
3929 12:18:31.387301 LP4Y_EN = 0x0
3930 12:18:31.390571 WORK_FSP = 0x0
3931 12:18:31.391138 WL = 0x2
3932 12:18:31.393400 RL = 0x2
3933 12:18:31.394076 BL = 0x2
3934 12:18:31.397060 RPST = 0x0
3935 12:18:31.397622 RD_PRE = 0x0
3936 12:18:31.400390 WR_PRE = 0x1
3937 12:18:31.400976 WR_PST = 0x0
3938 12:18:31.403220 DBI_WR = 0x0
3939 12:18:31.406472 DBI_RD = 0x0
3940 12:18:31.406939 OTF = 0x1
3941 12:18:31.410023 ===================================
3942 12:18:31.413315 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3943 12:18:31.417131 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3944 12:18:31.423456 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3945 12:18:31.426609 ===================================
3946 12:18:31.427082 LPDDR4 DRAM CONFIGURATION
3947 12:18:31.430206 ===================================
3948 12:18:31.433631 EX_ROW_EN[0] = 0x10
3949 12:18:31.436553 EX_ROW_EN[1] = 0x0
3950 12:18:31.437022 LP4Y_EN = 0x0
3951 12:18:31.440067 WORK_FSP = 0x0
3952 12:18:31.440538 WL = 0x2
3953 12:18:31.443106 RL = 0x2
3954 12:18:31.443575 BL = 0x2
3955 12:18:31.446992 RPST = 0x0
3956 12:18:31.447556 RD_PRE = 0x0
3957 12:18:31.449835 WR_PRE = 0x1
3958 12:18:31.450332 WR_PST = 0x0
3959 12:18:31.453378 DBI_WR = 0x0
3960 12:18:31.453967 DBI_RD = 0x0
3961 12:18:31.456808 OTF = 0x1
3962 12:18:31.460404 ===================================
3963 12:18:31.466815 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3964 12:18:31.470322 nWR fixed to 30
3965 12:18:31.473439 [ModeRegInit_LP4] CH0 RK0
3966 12:18:31.474034 [ModeRegInit_LP4] CH0 RK1
3967 12:18:31.476649 [ModeRegInit_LP4] CH1 RK0
3968 12:18:31.480191 [ModeRegInit_LP4] CH1 RK1
3969 12:18:31.480762 match AC timing 17
3970 12:18:31.486624 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3971 12:18:31.490091 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3972 12:18:31.493865 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3973 12:18:31.499876 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3974 12:18:31.503085 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3975 12:18:31.503558 ==
3976 12:18:31.506761 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 12:18:31.510493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 12:18:31.511066 ==
3979 12:18:31.517351 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3980 12:18:31.523385 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3981 12:18:31.526468 [CA 0] Center 36 (5~67) winsize 63
3982 12:18:31.530361 [CA 1] Center 36 (6~67) winsize 62
3983 12:18:31.533504 [CA 2] Center 34 (4~65) winsize 62
3984 12:18:31.536519 [CA 3] Center 34 (4~65) winsize 62
3985 12:18:31.539889 [CA 4] Center 33 (3~64) winsize 62
3986 12:18:31.543090 [CA 5] Center 33 (3~64) winsize 62
3987 12:18:31.543559
3988 12:18:31.546702 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3989 12:18:31.547267
3990 12:18:31.550085 [CATrainingPosCal] consider 1 rank data
3991 12:18:31.553220 u2DelayCellTimex100 = 270/100 ps
3992 12:18:31.556274 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3993 12:18:31.559699 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3994 12:18:31.562951 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3995 12:18:31.566323 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3996 12:18:31.569758 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3997 12:18:31.573061 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3998 12:18:31.573625
3999 12:18:31.579738 CA PerBit enable=1, Macro0, CA PI delay=33
4000 12:18:31.580300
4001 12:18:31.580673 [CBTSetCACLKResult] CA Dly = 33
4002 12:18:31.582918 CS Dly: 5 (0~36)
4003 12:18:31.583382 ==
4004 12:18:31.586389 Dram Type= 6, Freq= 0, CH_0, rank 1
4005 12:18:31.590266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4006 12:18:31.590834 ==
4007 12:18:31.596457 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4008 12:18:31.602603 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4009 12:18:31.605972 [CA 0] Center 36 (6~67) winsize 62
4010 12:18:31.609469 [CA 1] Center 36 (6~67) winsize 62
4011 12:18:31.612949 [CA 2] Center 34 (4~65) winsize 62
4012 12:18:31.616429 [CA 3] Center 34 (4~65) winsize 62
4013 12:18:31.619506 [CA 4] Center 34 (4~65) winsize 62
4014 12:18:31.622695 [CA 5] Center 33 (3~64) winsize 62
4015 12:18:31.623158
4016 12:18:31.626295 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4017 12:18:31.626757
4018 12:18:31.629299 [CATrainingPosCal] consider 2 rank data
4019 12:18:31.632789 u2DelayCellTimex100 = 270/100 ps
4020 12:18:31.636424 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4021 12:18:31.640192 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4022 12:18:31.642765 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4023 12:18:31.646401 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4024 12:18:31.649417 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4025 12:18:31.653277 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4026 12:18:31.653740
4027 12:18:31.659481 CA PerBit enable=1, Macro0, CA PI delay=33
4028 12:18:31.659945
4029 12:18:31.662610 [CBTSetCACLKResult] CA Dly = 33
4030 12:18:31.663071 CS Dly: 5 (0~37)
4031 12:18:31.663443
4032 12:18:31.666271 ----->DramcWriteLeveling(PI) begin...
4033 12:18:31.666924 ==
4034 12:18:31.669805 Dram Type= 6, Freq= 0, CH_0, rank 0
4035 12:18:31.672960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 12:18:31.676386 ==
4037 12:18:31.676950 Write leveling (Byte 0): 34 => 34
4038 12:18:31.679217 Write leveling (Byte 1): 31 => 31
4039 12:18:31.682886 DramcWriteLeveling(PI) end<-----
4040 12:18:31.683456
4041 12:18:31.684044 ==
4042 12:18:31.686054 Dram Type= 6, Freq= 0, CH_0, rank 0
4043 12:18:31.692379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 12:18:31.692845 ==
4045 12:18:31.693337 [Gating] SW mode calibration
4046 12:18:31.702447 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4047 12:18:31.705746 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4048 12:18:31.708938 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4049 12:18:31.715663 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4050 12:18:31.718969 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4051 12:18:31.722506 0 9 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
4052 12:18:31.729276 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
4053 12:18:31.733148 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 12:18:31.736125 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 12:18:31.742542 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 12:18:31.745632 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 12:18:31.749216 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 12:18:31.755625 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4059 12:18:31.758846 0 10 12 | B1->B0 | 2424 3939 | 1 1 | (0 0) (0 0)
4060 12:18:31.762536 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4061 12:18:31.769259 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 12:18:31.772133 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 12:18:31.775543 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 12:18:31.782597 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 12:18:31.785598 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 12:18:31.789062 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4067 12:18:31.795554 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4068 12:18:31.798877 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 12:18:31.802552 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 12:18:31.808692 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 12:18:31.812239 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 12:18:31.815724 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 12:18:31.822383 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 12:18:31.825551 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 12:18:31.828983 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 12:18:31.835377 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 12:18:31.839168 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 12:18:31.842251 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 12:18:31.845796 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 12:18:31.852236 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 12:18:31.855231 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 12:18:31.858614 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 12:18:31.865807 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4084 12:18:31.868790 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4085 12:18:31.871946 Total UI for P1: 0, mck2ui 16
4086 12:18:31.875334 best dqsien dly found for B0: ( 0, 13, 12)
4087 12:18:31.878856 Total UI for P1: 0, mck2ui 16
4088 12:18:31.881818 best dqsien dly found for B1: ( 0, 13, 12)
4089 12:18:31.885475 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4090 12:18:31.888396 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4091 12:18:31.888870
4092 12:18:31.891914 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4093 12:18:31.898389 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4094 12:18:31.898940 [Gating] SW calibration Done
4095 12:18:31.899315 ==
4096 12:18:31.902159 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 12:18:31.908255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 12:18:31.908805 ==
4099 12:18:31.909179 RX Vref Scan: 0
4100 12:18:31.909525
4101 12:18:31.912260 RX Vref 0 -> 0, step: 1
4102 12:18:31.912837
4103 12:18:31.915126 RX Delay -230 -> 252, step: 16
4104 12:18:31.918944 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4105 12:18:31.921722 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4106 12:18:31.925126 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4107 12:18:31.931975 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4108 12:18:31.935419 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4109 12:18:31.938379 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4110 12:18:31.941813 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4111 12:18:31.945354 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4112 12:18:31.952005 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4113 12:18:31.955173 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4114 12:18:31.958704 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4115 12:18:31.961761 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4116 12:18:31.968589 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4117 12:18:31.972196 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4118 12:18:31.975180 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4119 12:18:31.979007 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4120 12:18:31.979573 ==
4121 12:18:31.982085 Dram Type= 6, Freq= 0, CH_0, rank 0
4122 12:18:31.988858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4123 12:18:31.989428 ==
4124 12:18:31.989807 DQS Delay:
4125 12:18:31.992101 DQS0 = 0, DQS1 = 0
4126 12:18:31.992664 DQM Delay:
4127 12:18:31.993038 DQM0 = 51, DQM1 = 41
4128 12:18:31.995252 DQ Delay:
4129 12:18:31.998384 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4130 12:18:32.001731 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4131 12:18:32.005212 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4132 12:18:32.009005 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4133 12:18:32.009570
4134 12:18:32.009973
4135 12:18:32.010330 ==
4136 12:18:32.011746 Dram Type= 6, Freq= 0, CH_0, rank 0
4137 12:18:32.015197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4138 12:18:32.015764 ==
4139 12:18:32.016141
4140 12:18:32.016485
4141 12:18:32.018840 TX Vref Scan disable
4142 12:18:32.019401 == TX Byte 0 ==
4143 12:18:32.025274 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4144 12:18:32.028898 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4145 12:18:32.029597 == TX Byte 1 ==
4146 12:18:32.035476 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4147 12:18:32.038797 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4148 12:18:32.039365 ==
4149 12:18:32.042287 Dram Type= 6, Freq= 0, CH_0, rank 0
4150 12:18:32.045042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 12:18:32.045514 ==
4152 12:18:32.045892
4153 12:18:32.048532
4154 12:18:32.049098 TX Vref Scan disable
4155 12:18:32.052066 == TX Byte 0 ==
4156 12:18:32.055232 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4157 12:18:32.062171 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4158 12:18:32.062810 == TX Byte 1 ==
4159 12:18:32.065267 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4160 12:18:32.071950 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4161 12:18:32.072693
4162 12:18:32.073123 [DATLAT]
4163 12:18:32.073476 Freq=600, CH0 RK0
4164 12:18:32.073814
4165 12:18:32.075165 DATLAT Default: 0x9
4166 12:18:32.075675 0, 0xFFFF, sum = 0
4167 12:18:32.078968 1, 0xFFFF, sum = 0
4168 12:18:32.079542 2, 0xFFFF, sum = 0
4169 12:18:32.082244 3, 0xFFFF, sum = 0
4170 12:18:32.082817 4, 0xFFFF, sum = 0
4171 12:18:32.085201 5, 0xFFFF, sum = 0
4172 12:18:32.088735 6, 0xFFFF, sum = 0
4173 12:18:32.089322 7, 0xFFFF, sum = 0
4174 12:18:32.092171 8, 0x0, sum = 1
4175 12:18:32.092743 9, 0x0, sum = 2
4176 12:18:32.093123 10, 0x0, sum = 3
4177 12:18:32.095331 11, 0x0, sum = 4
4178 12:18:32.095803 best_step = 9
4179 12:18:32.096259
4180 12:18:32.096611 ==
4181 12:18:32.098375 Dram Type= 6, Freq= 0, CH_0, rank 0
4182 12:18:32.105496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 12:18:32.106134 ==
4184 12:18:32.106524 RX Vref Scan: 1
4185 12:18:32.106873
4186 12:18:32.108208 RX Vref 0 -> 0, step: 1
4187 12:18:32.108669
4188 12:18:32.112260 RX Delay -179 -> 252, step: 8
4189 12:18:32.112820
4190 12:18:32.115189 Set Vref, RX VrefLevel [Byte0]: 59
4191 12:18:32.118318 [Byte1]: 49
4192 12:18:32.118879
4193 12:18:32.121876 Final RX Vref Byte 0 = 59 to rank0
4194 12:18:32.124861 Final RX Vref Byte 1 = 49 to rank0
4195 12:18:32.128367 Final RX Vref Byte 0 = 59 to rank1
4196 12:18:32.131971 Final RX Vref Byte 1 = 49 to rank1==
4197 12:18:32.134870 Dram Type= 6, Freq= 0, CH_0, rank 0
4198 12:18:32.138464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4199 12:18:32.139033 ==
4200 12:18:32.141517 DQS Delay:
4201 12:18:32.142009 DQS0 = 0, DQS1 = 0
4202 12:18:32.144616 DQM Delay:
4203 12:18:32.145076 DQM0 = 48, DQM1 = 36
4204 12:18:32.145439 DQ Delay:
4205 12:18:32.148308 DQ0 =44, DQ1 =48, DQ2 =44, DQ3 =44
4206 12:18:32.152068 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4207 12:18:32.154973 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4208 12:18:32.158524 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =44
4209 12:18:32.159104
4210 12:18:32.159484
4211 12:18:32.168090 [DQSOSCAuto] RK0, (LSB)MR18= 0x534e, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
4212 12:18:32.171412 CH0 RK0: MR19=808, MR18=534E
4213 12:18:32.178185 CH0_RK0: MR19=0x808, MR18=0x534E, DQSOSC=394, MR23=63, INC=168, DEC=112
4214 12:18:32.178793
4215 12:18:32.181245 ----->DramcWriteLeveling(PI) begin...
4216 12:18:32.181716 ==
4217 12:18:32.185408 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 12:18:32.187995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 12:18:32.188470 ==
4220 12:18:32.191234 Write leveling (Byte 0): 35 => 35
4221 12:18:32.194482 Write leveling (Byte 1): 31 => 31
4222 12:18:32.198213 DramcWriteLeveling(PI) end<-----
4223 12:18:32.198705
4224 12:18:32.199075 ==
4225 12:18:32.201746 Dram Type= 6, Freq= 0, CH_0, rank 1
4226 12:18:32.204757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4227 12:18:32.205335 ==
4228 12:18:32.207819 [Gating] SW mode calibration
4229 12:18:32.214695 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4230 12:18:32.221039 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4231 12:18:32.224506 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4232 12:18:32.227875 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4233 12:18:32.234804 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4234 12:18:32.238536 0 9 12 | B1->B0 | 3333 3030 | 0 1 | (0 0) (1 0)
4235 12:18:32.241119 0 9 16 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 0)
4236 12:18:32.248261 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 12:18:32.251209 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 12:18:32.254871 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 12:18:32.261150 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 12:18:32.264759 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 12:18:32.267412 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4242 12:18:32.271489 0 10 12 | B1->B0 | 2d2d 3131 | 0 0 | (0 0) (0 0)
4243 12:18:32.278004 0 10 16 | B1->B0 | 4040 4545 | 0 0 | (0 0) (0 0)
4244 12:18:32.281059 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 12:18:32.284266 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 12:18:32.290920 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 12:18:32.294378 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 12:18:32.297635 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 12:18:32.304437 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4250 12:18:32.307940 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 12:18:32.310723 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 12:18:32.317765 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 12:18:32.320859 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 12:18:32.324317 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 12:18:32.331153 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 12:18:32.334445 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 12:18:32.337505 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 12:18:32.344041 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 12:18:32.347879 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 12:18:32.351186 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 12:18:32.357542 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 12:18:32.360996 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 12:18:32.363862 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 12:18:32.370873 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 12:18:32.374242 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 12:18:32.377748 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4267 12:18:32.384379 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4268 12:18:32.384956 Total UI for P1: 0, mck2ui 16
4269 12:18:32.387363 best dqsien dly found for B0: ( 0, 13, 12)
4270 12:18:32.390679 Total UI for P1: 0, mck2ui 16
4271 12:18:32.394312 best dqsien dly found for B1: ( 0, 13, 12)
4272 12:18:32.400624 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4273 12:18:32.403683 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4274 12:18:32.404146
4275 12:18:32.407356 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4276 12:18:32.410580 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4277 12:18:32.413785 [Gating] SW calibration Done
4278 12:18:32.414394 ==
4279 12:18:32.417400 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 12:18:32.420499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 12:18:32.421064 ==
4282 12:18:32.424094 RX Vref Scan: 0
4283 12:18:32.424656
4284 12:18:32.425019 RX Vref 0 -> 0, step: 1
4285 12:18:32.425364
4286 12:18:32.427176 RX Delay -230 -> 252, step: 16
4287 12:18:32.430331 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4288 12:18:32.437234 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4289 12:18:32.440485 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4290 12:18:32.443720 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4291 12:18:32.446938 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4292 12:18:32.453837 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4293 12:18:32.456738 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4294 12:18:32.460362 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4295 12:18:32.463615 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4296 12:18:32.467209 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4297 12:18:32.473605 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4298 12:18:32.477151 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4299 12:18:32.480054 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4300 12:18:32.483566 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4301 12:18:32.490310 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4302 12:18:32.493545 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4303 12:18:32.494147 ==
4304 12:18:32.496621 Dram Type= 6, Freq= 0, CH_0, rank 1
4305 12:18:32.500297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4306 12:18:32.500761 ==
4307 12:18:32.503597 DQS Delay:
4308 12:18:32.504088 DQS0 = 0, DQS1 = 0
4309 12:18:32.504456 DQM Delay:
4310 12:18:32.506591 DQM0 = 49, DQM1 = 42
4311 12:18:32.507053 DQ Delay:
4312 12:18:32.510019 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =49
4313 12:18:32.513373 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4314 12:18:32.517092 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4315 12:18:32.520289 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4316 12:18:32.520851
4317 12:18:32.521218
4318 12:18:32.521585 ==
4319 12:18:32.523490 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 12:18:32.530199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 12:18:32.530737 ==
4322 12:18:32.531110
4323 12:18:32.531449
4324 12:18:32.531774 TX Vref Scan disable
4325 12:18:32.533894 == TX Byte 0 ==
4326 12:18:32.536863 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4327 12:18:32.543704 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4328 12:18:32.544170 == TX Byte 1 ==
4329 12:18:32.546869 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4330 12:18:32.553993 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4331 12:18:32.554563 ==
4332 12:18:32.557013 Dram Type= 6, Freq= 0, CH_0, rank 1
4333 12:18:32.560434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 12:18:32.560901 ==
4335 12:18:32.561277
4336 12:18:32.561620
4337 12:18:32.563711 TX Vref Scan disable
4338 12:18:32.567498 == TX Byte 0 ==
4339 12:18:32.570863 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4340 12:18:32.573504 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4341 12:18:32.577264 == TX Byte 1 ==
4342 12:18:32.580834 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4343 12:18:32.583770 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4344 12:18:32.584346
4345 12:18:32.584721 [DATLAT]
4346 12:18:32.586739 Freq=600, CH0 RK1
4347 12:18:32.587207
4348 12:18:32.590348 DATLAT Default: 0x9
4349 12:18:32.590917 0, 0xFFFF, sum = 0
4350 12:18:32.593619 1, 0xFFFF, sum = 0
4351 12:18:32.594383 2, 0xFFFF, sum = 0
4352 12:18:32.596614 3, 0xFFFF, sum = 0
4353 12:18:32.597090 4, 0xFFFF, sum = 0
4354 12:18:32.600446 5, 0xFFFF, sum = 0
4355 12:18:32.601104 6, 0xFFFF, sum = 0
4356 12:18:32.603430 7, 0xFFFF, sum = 0
4357 12:18:32.603938 8, 0x0, sum = 1
4358 12:18:32.606985 9, 0x0, sum = 2
4359 12:18:32.607459 10, 0x0, sum = 3
4360 12:18:32.607832 11, 0x0, sum = 4
4361 12:18:32.609888 best_step = 9
4362 12:18:32.610380
4363 12:18:32.610740 ==
4364 12:18:32.613737 Dram Type= 6, Freq= 0, CH_0, rank 1
4365 12:18:32.616679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 12:18:32.617135 ==
4367 12:18:32.620121 RX Vref Scan: 0
4368 12:18:32.620588
4369 12:18:32.621001 RX Vref 0 -> 0, step: 1
4370 12:18:32.623374
4371 12:18:32.623826 RX Delay -179 -> 252, step: 8
4372 12:18:32.631127 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4373 12:18:32.634207 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4374 12:18:32.637822 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4375 12:18:32.641023 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4376 12:18:32.643836 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4377 12:18:32.651039 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4378 12:18:32.654267 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4379 12:18:32.657560 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4380 12:18:32.660562 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4381 12:18:32.667883 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4382 12:18:32.670476 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4383 12:18:32.674382 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4384 12:18:32.677713 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4385 12:18:32.681093 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4386 12:18:32.687315 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4387 12:18:32.691574 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4388 12:18:32.692156 ==
4389 12:18:32.693836 Dram Type= 6, Freq= 0, CH_0, rank 1
4390 12:18:32.697596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4391 12:18:32.698204 ==
4392 12:18:32.700563 DQS Delay:
4393 12:18:32.701185 DQS0 = 0, DQS1 = 0
4394 12:18:32.701562 DQM Delay:
4395 12:18:32.704068 DQM0 = 48, DQM1 = 42
4396 12:18:32.704526 DQ Delay:
4397 12:18:32.707482 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4398 12:18:32.710625 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4399 12:18:32.713663 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =36
4400 12:18:32.717251 DQ12 =48, DQ13 =48, DQ14 =52, DQ15 =52
4401 12:18:32.717716
4402 12:18:32.718126
4403 12:18:32.727483 [DQSOSCAuto] RK1, (LSB)MR18= 0x6633, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4404 12:18:32.730396 CH0 RK1: MR19=808, MR18=6633
4405 12:18:32.733615 CH0_RK1: MR19=0x808, MR18=0x6633, DQSOSC=390, MR23=63, INC=172, DEC=114
4406 12:18:32.737068 [RxdqsGatingPostProcess] freq 600
4407 12:18:32.743672 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4408 12:18:32.747053 Pre-setting of DQS Precalculation
4409 12:18:32.750769 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4410 12:18:32.751365 ==
4411 12:18:32.754274 Dram Type= 6, Freq= 0, CH_1, rank 0
4412 12:18:32.760379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 12:18:32.760842 ==
4414 12:18:32.764225 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4415 12:18:32.770600 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4416 12:18:32.773672 [CA 0] Center 35 (5~66) winsize 62
4417 12:18:32.777511 [CA 1] Center 35 (5~66) winsize 62
4418 12:18:32.780607 [CA 2] Center 34 (4~65) winsize 62
4419 12:18:32.783875 [CA 3] Center 33 (3~64) winsize 62
4420 12:18:32.787317 [CA 4] Center 34 (3~65) winsize 63
4421 12:18:32.790367 [CA 5] Center 33 (3~64) winsize 62
4422 12:18:32.790838
4423 12:18:32.794102 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4424 12:18:32.794674
4425 12:18:32.797136 [CATrainingPosCal] consider 1 rank data
4426 12:18:32.800586 u2DelayCellTimex100 = 270/100 ps
4427 12:18:32.804058 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4428 12:18:32.806923 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4429 12:18:32.810523 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4430 12:18:32.816956 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4431 12:18:32.820619 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4432 12:18:32.823843 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4433 12:18:32.824313
4434 12:18:32.827180 CA PerBit enable=1, Macro0, CA PI delay=33
4435 12:18:32.827747
4436 12:18:32.830583 [CBTSetCACLKResult] CA Dly = 33
4437 12:18:32.831149 CS Dly: 4 (0~35)
4438 12:18:32.831522 ==
4439 12:18:32.833862 Dram Type= 6, Freq= 0, CH_1, rank 1
4440 12:18:32.840279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4441 12:18:32.840753 ==
4442 12:18:32.843692 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4443 12:18:32.850818 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4444 12:18:32.854044 [CA 0] Center 35 (5~66) winsize 62
4445 12:18:32.857041 [CA 1] Center 35 (5~66) winsize 62
4446 12:18:32.860081 [CA 2] Center 34 (4~65) winsize 62
4447 12:18:32.863801 [CA 3] Center 34 (4~65) winsize 62
4448 12:18:32.866917 [CA 4] Center 34 (4~65) winsize 62
4449 12:18:32.870056 [CA 5] Center 33 (3~64) winsize 62
4450 12:18:32.870555
4451 12:18:32.873630 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4452 12:18:32.874135
4453 12:18:32.877062 [CATrainingPosCal] consider 2 rank data
4454 12:18:32.880257 u2DelayCellTimex100 = 270/100 ps
4455 12:18:32.883293 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4456 12:18:32.890403 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4457 12:18:32.893523 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4458 12:18:32.896754 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4459 12:18:32.900660 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4460 12:18:32.903362 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4461 12:18:32.903827
4462 12:18:32.906994 CA PerBit enable=1, Macro0, CA PI delay=33
4463 12:18:32.907478
4464 12:18:32.910050 [CBTSetCACLKResult] CA Dly = 33
4465 12:18:32.910511 CS Dly: 5 (0~37)
4466 12:18:32.910874
4467 12:18:32.913252 ----->DramcWriteLeveling(PI) begin...
4468 12:18:32.917062 ==
4469 12:18:32.920256 Dram Type= 6, Freq= 0, CH_1, rank 0
4470 12:18:32.923301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 12:18:32.923768 ==
4472 12:18:32.926636 Write leveling (Byte 0): 27 => 27
4473 12:18:32.929726 Write leveling (Byte 1): 29 => 29
4474 12:18:32.933492 DramcWriteLeveling(PI) end<-----
4475 12:18:32.934100
4476 12:18:32.934472 ==
4477 12:18:32.937023 Dram Type= 6, Freq= 0, CH_1, rank 0
4478 12:18:32.940315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4479 12:18:32.940909 ==
4480 12:18:32.943213 [Gating] SW mode calibration
4481 12:18:32.949804 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4482 12:18:32.956848 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4483 12:18:32.959863 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4484 12:18:32.963690 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4485 12:18:32.970274 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 0) (1 0)
4486 12:18:32.973684 0 9 12 | B1->B0 | 2f2f 2c2c | 1 0 | (1 0) (1 0)
4487 12:18:32.976739 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 12:18:32.980014 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 12:18:32.986755 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 12:18:32.990130 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 12:18:32.993261 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 12:18:32.999696 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 12:18:33.002977 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4494 12:18:33.006108 0 10 12 | B1->B0 | 3c3c 3c3c | 0 0 | (1 1) (0 0)
4495 12:18:33.013308 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 12:18:33.016740 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 12:18:33.019641 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 12:18:33.026294 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 12:18:33.029780 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 12:18:33.033391 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 12:18:33.039710 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 12:18:33.042608 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4503 12:18:33.045867 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 12:18:33.052765 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 12:18:33.056230 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 12:18:33.059754 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 12:18:33.065898 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 12:18:33.069440 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 12:18:33.072792 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 12:18:33.079324 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 12:18:33.082903 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 12:18:33.086498 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 12:18:33.092629 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 12:18:33.096158 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 12:18:33.099267 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 12:18:33.106198 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 12:18:33.109208 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4518 12:18:33.112354 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4519 12:18:33.118872 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4520 12:18:33.119424 Total UI for P1: 0, mck2ui 16
4521 12:18:33.125999 best dqsien dly found for B0: ( 0, 13, 10)
4522 12:18:33.126562 Total UI for P1: 0, mck2ui 16
4523 12:18:33.129253 best dqsien dly found for B1: ( 0, 13, 14)
4524 12:18:33.135953 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4525 12:18:33.139418 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4526 12:18:33.139992
4527 12:18:33.142382 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4528 12:18:33.145541 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4529 12:18:33.149500 [Gating] SW calibration Done
4530 12:18:33.150219 ==
4531 12:18:33.152460 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 12:18:33.155779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 12:18:33.156347 ==
4534 12:18:33.158896 RX Vref Scan: 0
4535 12:18:33.159465
4536 12:18:33.159862 RX Vref 0 -> 0, step: 1
4537 12:18:33.160212
4538 12:18:33.162167 RX Delay -230 -> 252, step: 16
4539 12:18:33.165989 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4540 12:18:33.172683 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4541 12:18:33.175218 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4542 12:18:33.178866 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4543 12:18:33.182436 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4544 12:18:33.189039 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4545 12:18:33.191800 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4546 12:18:33.195524 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4547 12:18:33.199145 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4548 12:18:33.202621 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4549 12:18:33.208859 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4550 12:18:33.212258 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4551 12:18:33.215410 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4552 12:18:33.218745 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4553 12:18:33.225903 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4554 12:18:33.228541 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4555 12:18:33.229117 ==
4556 12:18:33.232240 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 12:18:33.235259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 12:18:33.235838 ==
4559 12:18:33.238259 DQS Delay:
4560 12:18:33.238727 DQS0 = 0, DQS1 = 0
4561 12:18:33.241760 DQM Delay:
4562 12:18:33.242368 DQM0 = 49, DQM1 = 42
4563 12:18:33.242745 DQ Delay:
4564 12:18:33.245223 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4565 12:18:33.248636 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =49
4566 12:18:33.251707 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4567 12:18:33.254814 DQ12 =57, DQ13 =57, DQ14 =41, DQ15 =41
4568 12:18:33.255380
4569 12:18:33.255763
4570 12:18:33.256109 ==
4571 12:18:33.258421 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 12:18:33.265119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 12:18:33.265706 ==
4574 12:18:33.266120
4575 12:18:33.266477
4576 12:18:33.266809 TX Vref Scan disable
4577 12:18:33.268702 == TX Byte 0 ==
4578 12:18:33.272950 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4579 12:18:33.278886 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4580 12:18:33.279462 == TX Byte 1 ==
4581 12:18:33.282459 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4582 12:18:33.288938 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4583 12:18:33.289516 ==
4584 12:18:33.292197 Dram Type= 6, Freq= 0, CH_1, rank 0
4585 12:18:33.295801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 12:18:33.296379 ==
4587 12:18:33.296758
4588 12:18:33.297107
4589 12:18:33.298718 TX Vref Scan disable
4590 12:18:33.302219 == TX Byte 0 ==
4591 12:18:33.305643 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4592 12:18:33.308825 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4593 12:18:33.312334 == TX Byte 1 ==
4594 12:18:33.315742 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4595 12:18:33.318495 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4596 12:18:33.318971
4597 12:18:33.319340 [DATLAT]
4598 12:18:33.321809 Freq=600, CH1 RK0
4599 12:18:33.322309
4600 12:18:33.322685 DATLAT Default: 0x9
4601 12:18:33.325413 0, 0xFFFF, sum = 0
4602 12:18:33.328708 1, 0xFFFF, sum = 0
4603 12:18:33.329292 2, 0xFFFF, sum = 0
4604 12:18:33.331756 3, 0xFFFF, sum = 0
4605 12:18:33.332232 4, 0xFFFF, sum = 0
4606 12:18:33.335155 5, 0xFFFF, sum = 0
4607 12:18:33.335737 6, 0xFFFF, sum = 0
4608 12:18:33.339099 7, 0xFFFF, sum = 0
4609 12:18:33.339682 8, 0x0, sum = 1
4610 12:18:33.342061 9, 0x0, sum = 2
4611 12:18:33.342539 10, 0x0, sum = 3
4612 12:18:33.342922 11, 0x0, sum = 4
4613 12:18:33.345058 best_step = 9
4614 12:18:33.345565
4615 12:18:33.346136 ==
4616 12:18:33.348293 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 12:18:33.352286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 12:18:33.352868 ==
4619 12:18:33.355210 RX Vref Scan: 1
4620 12:18:33.355681
4621 12:18:33.356052 RX Vref 0 -> 0, step: 1
4622 12:18:33.358176
4623 12:18:33.358668 RX Delay -163 -> 252, step: 8
4624 12:18:33.359145
4625 12:18:33.361597 Set Vref, RX VrefLevel [Byte0]: 53
4626 12:18:33.365039 [Byte1]: 53
4627 12:18:33.369575
4628 12:18:33.370181 Final RX Vref Byte 0 = 53 to rank0
4629 12:18:33.373194 Final RX Vref Byte 1 = 53 to rank0
4630 12:18:33.376355 Final RX Vref Byte 0 = 53 to rank1
4631 12:18:33.379631 Final RX Vref Byte 1 = 53 to rank1==
4632 12:18:33.382601 Dram Type= 6, Freq= 0, CH_1, rank 0
4633 12:18:33.389196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4634 12:18:33.389774 ==
4635 12:18:33.390192 DQS Delay:
4636 12:18:33.390542 DQS0 = 0, DQS1 = 0
4637 12:18:33.392639 DQM Delay:
4638 12:18:33.393218 DQM0 = 48, DQM1 = 40
4639 12:18:33.395886 DQ Delay:
4640 12:18:33.399130 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4641 12:18:33.402875 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =44
4642 12:18:33.403450 DQ8 =28, DQ9 =24, DQ10 =44, DQ11 =32
4643 12:18:33.409162 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4644 12:18:33.409736
4645 12:18:33.410175
4646 12:18:33.416435 [DQSOSCAuto] RK0, (LSB)MR18= 0x476f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4647 12:18:33.419263 CH1 RK0: MR19=808, MR18=476F
4648 12:18:33.426038 CH1_RK0: MR19=0x808, MR18=0x476F, DQSOSC=389, MR23=63, INC=173, DEC=115
4649 12:18:33.426625
4650 12:18:33.429388 ----->DramcWriteLeveling(PI) begin...
4651 12:18:33.430019 ==
4652 12:18:33.432383 Dram Type= 6, Freq= 0, CH_1, rank 1
4653 12:18:33.435555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 12:18:33.436127 ==
4655 12:18:33.439577 Write leveling (Byte 0): 30 => 30
4656 12:18:33.442392 Write leveling (Byte 1): 30 => 30
4657 12:18:33.445775 DramcWriteLeveling(PI) end<-----
4658 12:18:33.446323
4659 12:18:33.446709 ==
4660 12:18:33.448844 Dram Type= 6, Freq= 0, CH_1, rank 1
4661 12:18:33.452665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4662 12:18:33.453256 ==
4663 12:18:33.455998 [Gating] SW mode calibration
4664 12:18:33.462169 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4665 12:18:33.468706 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4666 12:18:33.472215 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4667 12:18:33.478837 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4668 12:18:33.482141 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4669 12:18:33.485655 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (0 1)
4670 12:18:33.491907 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 12:18:33.495214 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 12:18:33.498709 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 12:18:33.505242 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 12:18:33.508779 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 12:18:33.512046 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 12:18:33.515437 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 12:18:33.522118 0 10 12 | B1->B0 | 3939 2e2e | 0 0 | (0 0) (0 0)
4678 12:18:33.525024 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 12:18:33.528417 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 12:18:33.534991 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 12:18:33.538277 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 12:18:33.542082 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 12:18:33.548206 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 12:18:33.551477 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4685 12:18:33.555193 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4686 12:18:33.562185 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 12:18:33.565268 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 12:18:33.568618 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 12:18:33.575436 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 12:18:33.578892 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 12:18:33.582062 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 12:18:33.588741 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 12:18:33.591796 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 12:18:33.595080 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 12:18:33.602071 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 12:18:33.605290 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 12:18:33.608736 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 12:18:33.614849 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 12:18:33.618302 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 12:18:33.621406 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 12:18:33.628677 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 12:18:33.631637 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4703 12:18:33.634642 Total UI for P1: 0, mck2ui 16
4704 12:18:33.638499 best dqsien dly found for B0: ( 0, 13, 14)
4705 12:18:33.641623 Total UI for P1: 0, mck2ui 16
4706 12:18:33.645130 best dqsien dly found for B1: ( 0, 13, 14)
4707 12:18:33.648254 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4708 12:18:33.651601 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4709 12:18:33.652072
4710 12:18:33.654697 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4711 12:18:33.658129 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4712 12:18:33.661503 [Gating] SW calibration Done
4713 12:18:33.662110 ==
4714 12:18:33.665123 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 12:18:33.668557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 12:18:33.669130 ==
4717 12:18:33.671428 RX Vref Scan: 0
4718 12:18:33.671901
4719 12:18:33.674976 RX Vref 0 -> 0, step: 1
4720 12:18:33.675637
4721 12:18:33.676023 RX Delay -230 -> 252, step: 16
4722 12:18:33.681884 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4723 12:18:33.684921 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4724 12:18:33.688376 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4725 12:18:33.691210 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4726 12:18:33.698124 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4727 12:18:33.701476 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4728 12:18:33.704740 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4729 12:18:33.708207 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4730 12:18:33.711740 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4731 12:18:33.718302 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4732 12:18:33.721172 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4733 12:18:33.724574 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4734 12:18:33.727867 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4735 12:18:33.734324 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4736 12:18:33.738049 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4737 12:18:33.741033 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4738 12:18:33.741654 ==
4739 12:18:33.744484 Dram Type= 6, Freq= 0, CH_1, rank 1
4740 12:18:33.747561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4741 12:18:33.751250 ==
4742 12:18:33.751720 DQS Delay:
4743 12:18:33.752093 DQS0 = 0, DQS1 = 0
4744 12:18:33.754216 DQM Delay:
4745 12:18:33.754729 DQM0 = 53, DQM1 = 48
4746 12:18:33.757601 DQ Delay:
4747 12:18:33.758278 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4748 12:18:33.761142 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4749 12:18:33.764669 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4750 12:18:33.767713 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =57
4751 12:18:33.768189
4752 12:18:33.771140
4753 12:18:33.771707 ==
4754 12:18:33.774496 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 12:18:33.777754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 12:18:33.778393 ==
4757 12:18:33.778778
4758 12:18:33.779128
4759 12:18:33.780968 TX Vref Scan disable
4760 12:18:33.781439 == TX Byte 0 ==
4761 12:18:33.787869 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4762 12:18:33.790867 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4763 12:18:33.791436 == TX Byte 1 ==
4764 12:18:33.797994 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4765 12:18:33.800982 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4766 12:18:33.801454 ==
4767 12:18:33.804243 Dram Type= 6, Freq= 0, CH_1, rank 1
4768 12:18:33.807472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4769 12:18:33.807947 ==
4770 12:18:33.808326
4771 12:18:33.808674
4772 12:18:33.810973 TX Vref Scan disable
4773 12:18:33.813974 == TX Byte 0 ==
4774 12:18:33.817548 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4775 12:18:33.820789 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4776 12:18:33.824450 == TX Byte 1 ==
4777 12:18:33.827314 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4778 12:18:33.831039 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4779 12:18:33.831608
4780 12:18:33.834171 [DATLAT]
4781 12:18:33.834640 Freq=600, CH1 RK1
4782 12:18:33.835012
4783 12:18:33.837641 DATLAT Default: 0x9
4784 12:18:33.838241 0, 0xFFFF, sum = 0
4785 12:18:33.841112 1, 0xFFFF, sum = 0
4786 12:18:33.841677 2, 0xFFFF, sum = 0
4787 12:18:33.844292 3, 0xFFFF, sum = 0
4788 12:18:33.844863 4, 0xFFFF, sum = 0
4789 12:18:33.847400 5, 0xFFFF, sum = 0
4790 12:18:33.847902 6, 0xFFFF, sum = 0
4791 12:18:33.850491 7, 0xFFFF, sum = 0
4792 12:18:33.850963 8, 0x0, sum = 1
4793 12:18:33.854017 9, 0x0, sum = 2
4794 12:18:33.854586 10, 0x0, sum = 3
4795 12:18:33.857604 11, 0x0, sum = 4
4796 12:18:33.858212 best_step = 9
4797 12:18:33.858590
4798 12:18:33.858934 ==
4799 12:18:33.860478 Dram Type= 6, Freq= 0, CH_1, rank 1
4800 12:18:33.867072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4801 12:18:33.867542 ==
4802 12:18:33.867915 RX Vref Scan: 0
4803 12:18:33.868314
4804 12:18:33.870393 RX Vref 0 -> 0, step: 1
4805 12:18:33.870861
4806 12:18:33.873599 RX Delay -163 -> 252, step: 8
4807 12:18:33.877474 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4808 12:18:33.880596 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4809 12:18:33.887403 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4810 12:18:33.890971 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4811 12:18:33.894152 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4812 12:18:33.897472 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4813 12:18:33.900498 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4814 12:18:33.906933 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4815 12:18:33.910076 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4816 12:18:33.914102 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4817 12:18:33.917145 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4818 12:18:33.923314 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4819 12:18:33.927165 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4820 12:18:33.930067 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4821 12:18:33.933711 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4822 12:18:33.937087 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4823 12:18:33.940379 ==
4824 12:18:33.940942 Dram Type= 6, Freq= 0, CH_1, rank 1
4825 12:18:33.947018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4826 12:18:33.947735 ==
4827 12:18:33.948133 DQS Delay:
4828 12:18:33.949995 DQS0 = 0, DQS1 = 0
4829 12:18:33.950592 DQM Delay:
4830 12:18:33.953866 DQM0 = 49, DQM1 = 43
4831 12:18:33.954467 DQ Delay:
4832 12:18:33.956958 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =48
4833 12:18:33.960102 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4834 12:18:33.963540 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4835 12:18:33.966772 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4836 12:18:33.967405
4837 12:18:33.967789
4838 12:18:33.973406 [DQSOSCAuto] RK1, (LSB)MR18= 0x571d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4839 12:18:33.976835 CH1 RK1: MR19=808, MR18=571D
4840 12:18:33.983627 CH1_RK1: MR19=0x808, MR18=0x571D, DQSOSC=393, MR23=63, INC=169, DEC=113
4841 12:18:33.986898 [RxdqsGatingPostProcess] freq 600
4842 12:18:33.993643 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4843 12:18:33.994277 Pre-setting of DQS Precalculation
4844 12:18:34.000491 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4845 12:18:34.006383 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4846 12:18:34.013581 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4847 12:18:34.014189
4848 12:18:34.014565
4849 12:18:34.016405 [Calibration Summary] 1200 Mbps
4850 12:18:34.019977 CH 0, Rank 0
4851 12:18:34.020594 SW Impedance : PASS
4852 12:18:34.023001 DUTY Scan : NO K
4853 12:18:34.023488 ZQ Calibration : PASS
4854 12:18:34.026557 Jitter Meter : NO K
4855 12:18:34.029726 CBT Training : PASS
4856 12:18:34.030465 Write leveling : PASS
4857 12:18:34.033070 RX DQS gating : PASS
4858 12:18:34.036360 RX DQ/DQS(RDDQC) : PASS
4859 12:18:34.036928 TX DQ/DQS : PASS
4860 12:18:34.039719 RX DATLAT : PASS
4861 12:18:34.042813 RX DQ/DQS(Engine): PASS
4862 12:18:34.043278 TX OE : NO K
4863 12:18:34.046124 All Pass.
4864 12:18:34.046604
4865 12:18:34.046973 CH 0, Rank 1
4866 12:18:34.049344 SW Impedance : PASS
4867 12:18:34.049828 DUTY Scan : NO K
4868 12:18:34.052946 ZQ Calibration : PASS
4869 12:18:34.056169 Jitter Meter : NO K
4870 12:18:34.056733 CBT Training : PASS
4871 12:18:34.059282 Write leveling : PASS
4872 12:18:34.062853 RX DQS gating : PASS
4873 12:18:34.063317 RX DQ/DQS(RDDQC) : PASS
4874 12:18:34.066213 TX DQ/DQS : PASS
4875 12:18:34.070020 RX DATLAT : PASS
4876 12:18:34.070489 RX DQ/DQS(Engine): PASS
4877 12:18:34.072539 TX OE : NO K
4878 12:18:34.073114 All Pass.
4879 12:18:34.073483
4880 12:18:34.076134 CH 1, Rank 0
4881 12:18:34.076594 SW Impedance : PASS
4882 12:18:34.079455 DUTY Scan : NO K
4883 12:18:34.080034 ZQ Calibration : PASS
4884 12:18:34.082744 Jitter Meter : NO K
4885 12:18:34.086297 CBT Training : PASS
4886 12:18:34.086867 Write leveling : PASS
4887 12:18:34.089458 RX DQS gating : PASS
4888 12:18:34.093274 RX DQ/DQS(RDDQC) : PASS
4889 12:18:34.093841 TX DQ/DQS : PASS
4890 12:18:34.096343 RX DATLAT : PASS
4891 12:18:34.099472 RX DQ/DQS(Engine): PASS
4892 12:18:34.099936 TX OE : NO K
4893 12:18:34.102809 All Pass.
4894 12:18:34.103266
4895 12:18:34.103629 CH 1, Rank 1
4896 12:18:34.106444 SW Impedance : PASS
4897 12:18:34.107006 DUTY Scan : NO K
4898 12:18:34.109680 ZQ Calibration : PASS
4899 12:18:34.112755 Jitter Meter : NO K
4900 12:18:34.113335 CBT Training : PASS
4901 12:18:34.116121 Write leveling : PASS
4902 12:18:34.116705 RX DQS gating : PASS
4903 12:18:34.119778 RX DQ/DQS(RDDQC) : PASS
4904 12:18:34.122634 TX DQ/DQS : PASS
4905 12:18:34.123116 RX DATLAT : PASS
4906 12:18:34.126324 RX DQ/DQS(Engine): PASS
4907 12:18:34.129389 TX OE : NO K
4908 12:18:34.129999 All Pass.
4909 12:18:34.130484
4910 12:18:34.132905 DramC Write-DBI off
4911 12:18:34.133506 PER_BANK_REFRESH: Hybrid Mode
4912 12:18:34.136073 TX_TRACKING: ON
4913 12:18:34.145836 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4914 12:18:34.149110 [FAST_K] Save calibration result to emmc
4915 12:18:34.152584 dramc_set_vcore_voltage set vcore to 662500
4916 12:18:34.153153 Read voltage for 933, 3
4917 12:18:34.155809 Vio18 = 0
4918 12:18:34.156275 Vcore = 662500
4919 12:18:34.156641 Vdram = 0
4920 12:18:34.159394 Vddq = 0
4921 12:18:34.160154 Vmddr = 0
4922 12:18:34.162622 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4923 12:18:34.169147 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4924 12:18:34.172629 MEM_TYPE=3, freq_sel=17
4925 12:18:34.175770 sv_algorithm_assistance_LP4_1600
4926 12:18:34.179078 ============ PULL DRAM RESETB DOWN ============
4927 12:18:34.182362 ========== PULL DRAM RESETB DOWN end =========
4928 12:18:34.188953 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4929 12:18:34.192657 ===================================
4930 12:18:34.193123 LPDDR4 DRAM CONFIGURATION
4931 12:18:34.195511 ===================================
4932 12:18:34.199448 EX_ROW_EN[0] = 0x0
4933 12:18:34.200022 EX_ROW_EN[1] = 0x0
4934 12:18:34.202261 LP4Y_EN = 0x0
4935 12:18:34.205260 WORK_FSP = 0x0
4936 12:18:34.205729 WL = 0x3
4937 12:18:34.208749 RL = 0x3
4938 12:18:34.209225 BL = 0x2
4939 12:18:34.212432 RPST = 0x0
4940 12:18:34.213007 RD_PRE = 0x0
4941 12:18:34.215415 WR_PRE = 0x1
4942 12:18:34.215885 WR_PST = 0x0
4943 12:18:34.219144 DBI_WR = 0x0
4944 12:18:34.219718 DBI_RD = 0x0
4945 12:18:34.222225 OTF = 0x1
4946 12:18:34.225626 ===================================
4947 12:18:34.228683 ===================================
4948 12:18:34.229248 ANA top config
4949 12:18:34.232253 ===================================
4950 12:18:34.235711 DLL_ASYNC_EN = 0
4951 12:18:34.238528 ALL_SLAVE_EN = 1
4952 12:18:34.238995 NEW_RANK_MODE = 1
4953 12:18:34.242535 DLL_IDLE_MODE = 1
4954 12:18:34.245567 LP45_APHY_COMB_EN = 1
4955 12:18:34.248510 TX_ODT_DIS = 1
4956 12:18:34.251944 NEW_8X_MODE = 1
4957 12:18:34.255721 ===================================
4958 12:18:34.258994 ===================================
4959 12:18:34.259563 data_rate = 1866
4960 12:18:34.262461 CKR = 1
4961 12:18:34.265424 DQ_P2S_RATIO = 8
4962 12:18:34.268718 ===================================
4963 12:18:34.271933 CA_P2S_RATIO = 8
4964 12:18:34.275678 DQ_CA_OPEN = 0
4965 12:18:34.278945 DQ_SEMI_OPEN = 0
4966 12:18:34.279518 CA_SEMI_OPEN = 0
4967 12:18:34.282539 CA_FULL_RATE = 0
4968 12:18:34.285375 DQ_CKDIV4_EN = 1
4969 12:18:34.288535 CA_CKDIV4_EN = 1
4970 12:18:34.292322 CA_PREDIV_EN = 0
4971 12:18:34.295029 PH8_DLY = 0
4972 12:18:34.295491 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4973 12:18:34.298590 DQ_AAMCK_DIV = 4
4974 12:18:34.302002 CA_AAMCK_DIV = 4
4975 12:18:34.305288 CA_ADMCK_DIV = 4
4976 12:18:34.308478 DQ_TRACK_CA_EN = 0
4977 12:18:34.312137 CA_PICK = 933
4978 12:18:34.312708 CA_MCKIO = 933
4979 12:18:34.315173 MCKIO_SEMI = 0
4980 12:18:34.318701 PLL_FREQ = 3732
4981 12:18:34.322296 DQ_UI_PI_RATIO = 32
4982 12:18:34.325223 CA_UI_PI_RATIO = 0
4983 12:18:34.328640 ===================================
4984 12:18:34.331995 ===================================
4985 12:18:34.335319 memory_type:LPDDR4
4986 12:18:34.335792 GP_NUM : 10
4987 12:18:34.338624 SRAM_EN : 1
4988 12:18:34.339206 MD32_EN : 0
4989 12:18:34.342232 ===================================
4990 12:18:34.345254 [ANA_INIT] >>>>>>>>>>>>>>
4991 12:18:34.348442 <<<<<< [CONFIGURE PHASE]: ANA_TX
4992 12:18:34.352026 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4993 12:18:34.355084 ===================================
4994 12:18:34.358551 data_rate = 1866,PCW = 0X8f00
4995 12:18:34.361815 ===================================
4996 12:18:34.365323 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4997 12:18:34.368771 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4998 12:18:34.375622 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4999 12:18:34.379037 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5000 12:18:34.385155 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5001 12:18:34.388985 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5002 12:18:34.389553 [ANA_INIT] flow start
5003 12:18:34.391745 [ANA_INIT] PLL >>>>>>>>
5004 12:18:34.395085 [ANA_INIT] PLL <<<<<<<<
5005 12:18:34.395553 [ANA_INIT] MIDPI >>>>>>>>
5006 12:18:34.398856 [ANA_INIT] MIDPI <<<<<<<<
5007 12:18:34.401910 [ANA_INIT] DLL >>>>>>>>
5008 12:18:34.402408 [ANA_INIT] flow end
5009 12:18:34.405318 ============ LP4 DIFF to SE enter ============
5010 12:18:34.411448 ============ LP4 DIFF to SE exit ============
5011 12:18:34.411921 [ANA_INIT] <<<<<<<<<<<<<
5012 12:18:34.414896 [Flow] Enable top DCM control >>>>>
5013 12:18:34.418497 [Flow] Enable top DCM control <<<<<
5014 12:18:34.421555 Enable DLL master slave shuffle
5015 12:18:34.428752 ==============================================================
5016 12:18:34.429338 Gating Mode config
5017 12:18:34.434767 ==============================================================
5018 12:18:34.438256 Config description:
5019 12:18:34.448280 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5020 12:18:34.454874 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5021 12:18:34.458391 SELPH_MODE 0: By rank 1: By Phase
5022 12:18:34.465067 ==============================================================
5023 12:18:34.468547 GAT_TRACK_EN = 1
5024 12:18:34.471689 RX_GATING_MODE = 2
5025 12:18:34.472339 RX_GATING_TRACK_MODE = 2
5026 12:18:34.474829 SELPH_MODE = 1
5027 12:18:34.478361 PICG_EARLY_EN = 1
5028 12:18:34.481719 VALID_LAT_VALUE = 1
5029 12:18:34.487863 ==============================================================
5030 12:18:34.491715 Enter into Gating configuration >>>>
5031 12:18:34.494490 Exit from Gating configuration <<<<
5032 12:18:34.498077 Enter into DVFS_PRE_config >>>>>
5033 12:18:34.507920 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5034 12:18:34.511168 Exit from DVFS_PRE_config <<<<<
5035 12:18:34.514506 Enter into PICG configuration >>>>
5036 12:18:34.518182 Exit from PICG configuration <<<<
5037 12:18:34.521721 [RX_INPUT] configuration >>>>>
5038 12:18:34.525048 [RX_INPUT] configuration <<<<<
5039 12:18:34.528227 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5040 12:18:34.534714 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5041 12:18:34.541731 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5042 12:18:34.544757 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5043 12:18:34.551042 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5044 12:18:34.558255 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5045 12:18:34.561749 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5046 12:18:34.568109 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5047 12:18:34.571272 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5048 12:18:34.574877 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5049 12:18:34.577771 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5050 12:18:34.584854 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5051 12:18:34.587615 ===================================
5052 12:18:34.588089 LPDDR4 DRAM CONFIGURATION
5053 12:18:34.591127 ===================================
5054 12:18:34.594961 EX_ROW_EN[0] = 0x0
5055 12:18:34.597901 EX_ROW_EN[1] = 0x0
5056 12:18:34.598511 LP4Y_EN = 0x0
5057 12:18:34.601497 WORK_FSP = 0x0
5058 12:18:34.602288 WL = 0x3
5059 12:18:34.604743 RL = 0x3
5060 12:18:34.605208 BL = 0x2
5061 12:18:34.607709 RPST = 0x0
5062 12:18:34.608174 RD_PRE = 0x0
5063 12:18:34.611419 WR_PRE = 0x1
5064 12:18:34.611888 WR_PST = 0x0
5065 12:18:34.614501 DBI_WR = 0x0
5066 12:18:34.614965 DBI_RD = 0x0
5067 12:18:34.617890 OTF = 0x1
5068 12:18:34.620995 ===================================
5069 12:18:34.624287 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5070 12:18:34.627512 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5071 12:18:34.634513 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5072 12:18:34.637650 ===================================
5073 12:18:34.638181 LPDDR4 DRAM CONFIGURATION
5074 12:18:34.641108 ===================================
5075 12:18:34.644659 EX_ROW_EN[0] = 0x10
5076 12:18:34.647453 EX_ROW_EN[1] = 0x0
5077 12:18:34.647935 LP4Y_EN = 0x0
5078 12:18:34.650996 WORK_FSP = 0x0
5079 12:18:34.651479 WL = 0x3
5080 12:18:34.654034 RL = 0x3
5081 12:18:34.654599 BL = 0x2
5082 12:18:34.657628 RPST = 0x0
5083 12:18:34.658247 RD_PRE = 0x0
5084 12:18:34.661388 WR_PRE = 0x1
5085 12:18:34.662028 WR_PST = 0x0
5086 12:18:34.664456 DBI_WR = 0x0
5087 12:18:34.665023 DBI_RD = 0x0
5088 12:18:34.667302 OTF = 0x1
5089 12:18:34.670791 ===================================
5090 12:18:34.677303 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5091 12:18:34.680735 nWR fixed to 30
5092 12:18:34.681300 [ModeRegInit_LP4] CH0 RK0
5093 12:18:34.684020 [ModeRegInit_LP4] CH0 RK1
5094 12:18:34.687384 [ModeRegInit_LP4] CH1 RK0
5095 12:18:34.690752 [ModeRegInit_LP4] CH1 RK1
5096 12:18:34.691348 match AC timing 9
5097 12:18:34.697180 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5098 12:18:34.700160 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5099 12:18:34.703462 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5100 12:18:34.710737 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5101 12:18:34.713514 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5102 12:18:34.714020 ==
5103 12:18:34.716984 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 12:18:34.720362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 12:18:34.720932 ==
5106 12:18:34.726829 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5107 12:18:34.733599 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5108 12:18:34.736946 [CA 0] Center 37 (7~68) winsize 62
5109 12:18:34.740301 [CA 1] Center 37 (7~68) winsize 62
5110 12:18:34.743779 [CA 2] Center 35 (5~66) winsize 62
5111 12:18:34.746395 [CA 3] Center 34 (4~65) winsize 62
5112 12:18:34.749646 [CA 4] Center 34 (4~64) winsize 61
5113 12:18:34.753787 [CA 5] Center 33 (3~64) winsize 62
5114 12:18:34.754386
5115 12:18:34.756909 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5116 12:18:34.757476
5117 12:18:34.760274 [CATrainingPosCal] consider 1 rank data
5118 12:18:34.763200 u2DelayCellTimex100 = 270/100 ps
5119 12:18:34.766676 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5120 12:18:34.769700 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5121 12:18:34.773234 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5122 12:18:34.776401 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5123 12:18:34.779620 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5124 12:18:34.783531 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5125 12:18:34.784000
5126 12:18:34.789767 CA PerBit enable=1, Macro0, CA PI delay=33
5127 12:18:34.790272
5128 12:18:34.790648 [CBTSetCACLKResult] CA Dly = 33
5129 12:18:34.793454 CS Dly: 7 (0~38)
5130 12:18:34.794078 ==
5131 12:18:34.796530 Dram Type= 6, Freq= 0, CH_0, rank 1
5132 12:18:34.800002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5133 12:18:34.800574 ==
5134 12:18:34.806875 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5135 12:18:34.813137 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5136 12:18:34.816331 [CA 0] Center 38 (8~69) winsize 62
5137 12:18:34.820028 [CA 1] Center 38 (8~69) winsize 62
5138 12:18:34.822921 [CA 2] Center 36 (6~66) winsize 61
5139 12:18:34.826236 [CA 3] Center 35 (5~66) winsize 62
5140 12:18:34.829662 [CA 4] Center 34 (4~65) winsize 62
5141 12:18:34.832932 [CA 5] Center 34 (4~64) winsize 61
5142 12:18:34.833509
5143 12:18:34.836322 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5144 12:18:34.836891
5145 12:18:34.839585 [CATrainingPosCal] consider 2 rank data
5146 12:18:34.843249 u2DelayCellTimex100 = 270/100 ps
5147 12:18:34.846226 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5148 12:18:34.849486 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5149 12:18:34.853390 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5150 12:18:34.856214 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5151 12:18:34.859825 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5152 12:18:34.866168 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5153 12:18:34.866868
5154 12:18:34.869160 CA PerBit enable=1, Macro0, CA PI delay=34
5155 12:18:34.869753
5156 12:18:34.872999 [CBTSetCACLKResult] CA Dly = 34
5157 12:18:34.873464 CS Dly: 7 (0~39)
5158 12:18:34.873833
5159 12:18:34.876294 ----->DramcWriteLeveling(PI) begin...
5160 12:18:34.876763 ==
5161 12:18:34.879583 Dram Type= 6, Freq= 0, CH_0, rank 0
5162 12:18:34.882656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 12:18:34.886377 ==
5164 12:18:34.886945 Write leveling (Byte 0): 32 => 32
5165 12:18:34.889115 Write leveling (Byte 1): 31 => 31
5166 12:18:34.892959 DramcWriteLeveling(PI) end<-----
5167 12:18:34.893570
5168 12:18:34.894149 ==
5169 12:18:34.895854 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 12:18:34.902650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 12:18:34.903271 ==
5172 12:18:34.905846 [Gating] SW mode calibration
5173 12:18:34.912459 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5174 12:18:34.916018 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5175 12:18:34.922540 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5176 12:18:34.925986 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 12:18:34.929619 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 12:18:34.932337 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 12:18:34.939658 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 12:18:34.942942 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 12:18:34.946242 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5182 12:18:34.952268 0 14 28 | B1->B0 | 3030 2424 | 1 0 | (1 0) (1 0)
5183 12:18:34.956175 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
5184 12:18:34.959301 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 12:18:34.965689 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 12:18:34.969270 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 12:18:34.972740 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 12:18:34.979378 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5189 12:18:34.982811 0 15 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (1 1)
5190 12:18:34.985883 0 15 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
5191 12:18:34.992783 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 12:18:34.995397 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 12:18:34.998747 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 12:18:35.005712 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 12:18:35.008736 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 12:18:35.012304 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 12:18:35.019017 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5198 12:18:35.022167 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5199 12:18:35.025411 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5200 12:18:35.031964 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 12:18:35.035347 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 12:18:35.038504 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 12:18:35.045178 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 12:18:35.048412 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 12:18:35.051776 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 12:18:35.058271 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 12:18:35.061839 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 12:18:35.065116 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 12:18:35.071573 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 12:18:35.075027 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 12:18:35.078219 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 12:18:35.081629 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 12:18:35.088107 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5214 12:18:35.091885 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5215 12:18:35.095139 Total UI for P1: 0, mck2ui 16
5216 12:18:35.098239 best dqsien dly found for B0: ( 1, 2, 24)
5217 12:18:35.101791 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5218 12:18:35.107992 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5219 12:18:35.111706 Total UI for P1: 0, mck2ui 16
5220 12:18:35.115308 best dqsien dly found for B1: ( 1, 2, 30)
5221 12:18:35.118163 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5222 12:18:35.121684 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5223 12:18:35.122075
5224 12:18:35.124940 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5225 12:18:35.128367 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5226 12:18:35.132047 [Gating] SW calibration Done
5227 12:18:35.132565 ==
5228 12:18:35.135210 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 12:18:35.138589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 12:18:35.139056 ==
5231 12:18:35.141878 RX Vref Scan: 0
5232 12:18:35.142472
5233 12:18:35.142840 RX Vref 0 -> 0, step: 1
5234 12:18:35.145091
5235 12:18:35.145652 RX Delay -80 -> 252, step: 8
5236 12:18:35.151475 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5237 12:18:35.155083 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5238 12:18:35.158677 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5239 12:18:35.161649 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5240 12:18:35.164962 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5241 12:18:35.168799 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5242 12:18:35.174925 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5243 12:18:35.178129 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5244 12:18:35.181684 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5245 12:18:35.184878 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5246 12:18:35.188539 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5247 12:18:35.191990 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5248 12:18:35.198533 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5249 12:18:35.201749 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5250 12:18:35.204873 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5251 12:18:35.208592 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5252 12:18:35.209078 ==
5253 12:18:35.211922 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 12:18:35.215346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 12:18:35.215910 ==
5256 12:18:35.218334 DQS Delay:
5257 12:18:35.218835 DQS0 = 0, DQS1 = 0
5258 12:18:35.222052 DQM Delay:
5259 12:18:35.222559 DQM0 = 105, DQM1 = 90
5260 12:18:35.222977 DQ Delay:
5261 12:18:35.225167 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5262 12:18:35.228455 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5263 12:18:35.231725 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5264 12:18:35.235280 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5265 12:18:35.238263
5266 12:18:35.238720
5267 12:18:35.239083 ==
5268 12:18:35.241557 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 12:18:35.245147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 12:18:35.245734 ==
5271 12:18:35.246148
5272 12:18:35.246492
5273 12:18:35.248178 TX Vref Scan disable
5274 12:18:35.248640 == TX Byte 0 ==
5275 12:18:35.254955 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5276 12:18:35.258446 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5277 12:18:35.259020 == TX Byte 1 ==
5278 12:18:35.265542 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5279 12:18:35.268188 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5280 12:18:35.268758 ==
5281 12:18:35.271957 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 12:18:35.274909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 12:18:35.275384 ==
5284 12:18:35.275760
5285 12:18:35.276108
5286 12:18:35.278060 TX Vref Scan disable
5287 12:18:35.281542 == TX Byte 0 ==
5288 12:18:35.284866 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5289 12:18:35.288119 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5290 12:18:35.291668 == TX Byte 1 ==
5291 12:18:35.294842 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5292 12:18:35.297823 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5293 12:18:35.298406
5294 12:18:35.301372 [DATLAT]
5295 12:18:35.301930 Freq=933, CH0 RK0
5296 12:18:35.302400
5297 12:18:35.304516 DATLAT Default: 0xd
5298 12:18:35.304986 0, 0xFFFF, sum = 0
5299 12:18:35.307792 1, 0xFFFF, sum = 0
5300 12:18:35.308267 2, 0xFFFF, sum = 0
5301 12:18:35.311310 3, 0xFFFF, sum = 0
5302 12:18:35.311874 4, 0xFFFF, sum = 0
5303 12:18:35.314799 5, 0xFFFF, sum = 0
5304 12:18:35.315275 6, 0xFFFF, sum = 0
5305 12:18:35.318353 7, 0xFFFF, sum = 0
5306 12:18:35.318827 8, 0xFFFF, sum = 0
5307 12:18:35.321212 9, 0xFFFF, sum = 0
5308 12:18:35.321688 10, 0x0, sum = 1
5309 12:18:35.324621 11, 0x0, sum = 2
5310 12:18:35.325097 12, 0x0, sum = 3
5311 12:18:35.327964 13, 0x0, sum = 4
5312 12:18:35.328527 best_step = 11
5313 12:18:35.328902
5314 12:18:35.329247 ==
5315 12:18:35.331245 Dram Type= 6, Freq= 0, CH_0, rank 0
5316 12:18:35.338198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 12:18:35.338765 ==
5318 12:18:35.339145 RX Vref Scan: 1
5319 12:18:35.339496
5320 12:18:35.341290 RX Vref 0 -> 0, step: 1
5321 12:18:35.341758
5322 12:18:35.344779 RX Delay -53 -> 252, step: 4
5323 12:18:35.345336
5324 12:18:35.348200 Set Vref, RX VrefLevel [Byte0]: 59
5325 12:18:35.351112 [Byte1]: 49
5326 12:18:35.351690
5327 12:18:35.354806 Final RX Vref Byte 0 = 59 to rank0
5328 12:18:35.357523 Final RX Vref Byte 1 = 49 to rank0
5329 12:18:35.361197 Final RX Vref Byte 0 = 59 to rank1
5330 12:18:35.364083 Final RX Vref Byte 1 = 49 to rank1==
5331 12:18:35.368156 Dram Type= 6, Freq= 0, CH_0, rank 0
5332 12:18:35.370966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5333 12:18:35.371721 ==
5334 12:18:35.374344 DQS Delay:
5335 12:18:35.374909 DQS0 = 0, DQS1 = 0
5336 12:18:35.375284 DQM Delay:
5337 12:18:35.377545 DQM0 = 108, DQM1 = 92
5338 12:18:35.378054 DQ Delay:
5339 12:18:35.381256 DQ0 =108, DQ1 =108, DQ2 =102, DQ3 =106
5340 12:18:35.384058 DQ4 =108, DQ5 =98, DQ6 =118, DQ7 =116
5341 12:18:35.387843 DQ8 =86, DQ9 =76, DQ10 =92, DQ11 =90
5342 12:18:35.391399 DQ12 =96, DQ13 =94, DQ14 =104, DQ15 =98
5343 12:18:35.394810
5344 12:18:35.395374
5345 12:18:35.401166 [DQSOSCAuto] RK0, (LSB)MR18= 0x2722, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
5346 12:18:35.404168 CH0 RK0: MR19=505, MR18=2722
5347 12:18:35.410744 CH0_RK0: MR19=0x505, MR18=0x2722, DQSOSC=409, MR23=63, INC=64, DEC=43
5348 12:18:35.411311
5349 12:18:35.413975 ----->DramcWriteLeveling(PI) begin...
5350 12:18:35.414794 ==
5351 12:18:35.417304 Dram Type= 6, Freq= 0, CH_0, rank 1
5352 12:18:35.420730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5353 12:18:35.421314 ==
5354 12:18:35.424174 Write leveling (Byte 0): 33 => 33
5355 12:18:35.427252 Write leveling (Byte 1): 28 => 28
5356 12:18:35.431093 DramcWriteLeveling(PI) end<-----
5357 12:18:35.431668
5358 12:18:35.432157 ==
5359 12:18:35.434035 Dram Type= 6, Freq= 0, CH_0, rank 1
5360 12:18:35.437001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5361 12:18:35.437576 ==
5362 12:18:35.440460 [Gating] SW mode calibration
5363 12:18:35.447037 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5364 12:18:35.453662 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5365 12:18:35.457121 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 12:18:35.460181 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 12:18:35.467141 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 12:18:35.470255 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 12:18:35.473358 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 12:18:35.480366 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 12:18:35.483454 0 14 24 | B1->B0 | 3434 3030 | 0 1 | (0 0) (1 1)
5372 12:18:35.486972 0 14 28 | B1->B0 | 2a2a 2b2b | 0 0 | (1 0) (1 0)
5373 12:18:35.493552 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 12:18:35.497225 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 12:18:35.500037 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 12:18:35.506707 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 12:18:35.509952 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 12:18:35.513782 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 12:18:35.520550 0 15 24 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)
5380 12:18:35.523631 0 15 28 | B1->B0 | 3636 4242 | 0 0 | (0 0) (1 1)
5381 12:18:35.526843 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 12:18:35.533720 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 12:18:35.537075 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 12:18:35.539986 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 12:18:35.546707 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 12:18:35.550100 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 12:18:35.553429 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 12:18:35.560111 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5389 12:18:35.563456 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 12:18:35.566625 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 12:18:35.573507 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 12:18:35.577191 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 12:18:35.579788 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 12:18:35.583340 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 12:18:35.590383 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 12:18:35.593126 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 12:18:35.596861 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 12:18:35.603357 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 12:18:35.606527 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 12:18:35.610071 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 12:18:35.616715 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 12:18:35.619675 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 12:18:35.623347 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 12:18:35.629389 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5405 12:18:35.632833 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5406 12:18:35.636492 Total UI for P1: 0, mck2ui 16
5407 12:18:35.639806 best dqsien dly found for B0: ( 1, 2, 28)
5408 12:18:35.643292 Total UI for P1: 0, mck2ui 16
5409 12:18:35.646406 best dqsien dly found for B1: ( 1, 2, 28)
5410 12:18:35.649444 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5411 12:18:35.652724 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5412 12:18:35.653194
5413 12:18:35.656354 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5414 12:18:35.659586 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5415 12:18:35.663320 [Gating] SW calibration Done
5416 12:18:35.663894 ==
5417 12:18:35.666480 Dram Type= 6, Freq= 0, CH_0, rank 1
5418 12:18:35.669582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5419 12:18:35.673186 ==
5420 12:18:35.673759 RX Vref Scan: 0
5421 12:18:35.674177
5422 12:18:35.676096 RX Vref 0 -> 0, step: 1
5423 12:18:35.676666
5424 12:18:35.679483 RX Delay -80 -> 252, step: 8
5425 12:18:35.682629 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5426 12:18:35.686307 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5427 12:18:35.689902 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5428 12:18:35.693253 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5429 12:18:35.699251 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5430 12:18:35.702527 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5431 12:18:35.706129 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5432 12:18:35.709681 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5433 12:18:35.713021 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5434 12:18:35.716114 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5435 12:18:35.722665 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5436 12:18:35.726251 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5437 12:18:35.729481 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5438 12:18:35.732819 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5439 12:18:35.736340 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5440 12:18:35.739057 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5441 12:18:35.739538 ==
5442 12:18:35.742640 Dram Type= 6, Freq= 0, CH_0, rank 1
5443 12:18:35.749454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5444 12:18:35.749961 ==
5445 12:18:35.750447 DQS Delay:
5446 12:18:35.752715 DQS0 = 0, DQS1 = 0
5447 12:18:35.753196 DQM Delay:
5448 12:18:35.756069 DQM0 = 104, DQM1 = 90
5449 12:18:35.756549 DQ Delay:
5450 12:18:35.759324 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5451 12:18:35.762590 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5452 12:18:35.765838 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5453 12:18:35.769295 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5454 12:18:35.769773
5455 12:18:35.770286
5456 12:18:35.770771 ==
5457 12:18:35.772533 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 12:18:35.776164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 12:18:35.776729 ==
5460 12:18:35.777271
5461 12:18:35.777736
5462 12:18:35.778984 TX Vref Scan disable
5463 12:18:35.782575 == TX Byte 0 ==
5464 12:18:35.785790 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5465 12:18:35.789304 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5466 12:18:35.792208 == TX Byte 1 ==
5467 12:18:35.795869 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5468 12:18:35.798864 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5469 12:18:35.799328 ==
5470 12:18:35.802437 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 12:18:35.808994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 12:18:35.809424 ==
5473 12:18:35.809761
5474 12:18:35.810117
5475 12:18:35.810420 TX Vref Scan disable
5476 12:18:35.812832 == TX Byte 0 ==
5477 12:18:35.816185 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5478 12:18:35.819729 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5479 12:18:35.823229 == TX Byte 1 ==
5480 12:18:35.826526 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5481 12:18:35.829828 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5482 12:18:35.833106
5483 12:18:35.833569 [DATLAT]
5484 12:18:35.833973 Freq=933, CH0 RK1
5485 12:18:35.834350
5486 12:18:35.836477 DATLAT Default: 0xb
5487 12:18:35.836897 0, 0xFFFF, sum = 0
5488 12:18:35.839794 1, 0xFFFF, sum = 0
5489 12:18:35.840267 2, 0xFFFF, sum = 0
5490 12:18:35.843125 3, 0xFFFF, sum = 0
5491 12:18:35.843670 4, 0xFFFF, sum = 0
5492 12:18:35.846306 5, 0xFFFF, sum = 0
5493 12:18:35.846735 6, 0xFFFF, sum = 0
5494 12:18:35.849760 7, 0xFFFF, sum = 0
5495 12:18:35.853028 8, 0xFFFF, sum = 0
5496 12:18:35.853496 9, 0xFFFF, sum = 0
5497 12:18:35.856357 10, 0x0, sum = 1
5498 12:18:35.856932 11, 0x0, sum = 2
5499 12:18:35.857308 12, 0x0, sum = 3
5500 12:18:35.859937 13, 0x0, sum = 4
5501 12:18:35.860514 best_step = 11
5502 12:18:35.860886
5503 12:18:35.861229 ==
5504 12:18:35.863104 Dram Type= 6, Freq= 0, CH_0, rank 1
5505 12:18:35.869448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5506 12:18:35.869902 ==
5507 12:18:35.870398 RX Vref Scan: 0
5508 12:18:35.870748
5509 12:18:35.872842 RX Vref 0 -> 0, step: 1
5510 12:18:35.873261
5511 12:18:35.876412 RX Delay -53 -> 252, step: 4
5512 12:18:35.879552 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5513 12:18:35.886510 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5514 12:18:35.890074 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5515 12:18:35.893509 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5516 12:18:35.896650 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5517 12:18:35.899759 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5518 12:18:35.902857 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5519 12:18:35.909861 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5520 12:18:35.913608 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5521 12:18:35.916547 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5522 12:18:35.920013 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5523 12:18:35.923252 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5524 12:18:35.926874 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5525 12:18:35.933119 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5526 12:18:35.936825 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5527 12:18:35.939688 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5528 12:18:35.940184 ==
5529 12:18:35.943404 Dram Type= 6, Freq= 0, CH_0, rank 1
5530 12:18:35.946510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5531 12:18:35.946984 ==
5532 12:18:35.949592 DQS Delay:
5533 12:18:35.950089 DQS0 = 0, DQS1 = 0
5534 12:18:35.953301 DQM Delay:
5535 12:18:35.953765 DQM0 = 103, DQM1 = 93
5536 12:18:35.954239 DQ Delay:
5537 12:18:35.959938 DQ0 =102, DQ1 =106, DQ2 =100, DQ3 =98
5538 12:18:35.963045 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5539 12:18:35.966251 DQ8 =88, DQ9 =80, DQ10 =94, DQ11 =92
5540 12:18:35.970179 DQ12 =98, DQ13 =94, DQ14 =100, DQ15 =98
5541 12:18:35.970740
5542 12:18:35.971114
5543 12:18:35.976659 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5544 12:18:35.979415 CH0 RK1: MR19=505, MR18=2B0C
5545 12:18:35.986343 CH0_RK1: MR19=0x505, MR18=0x2B0C, DQSOSC=408, MR23=63, INC=65, DEC=43
5546 12:18:35.989832 [RxdqsGatingPostProcess] freq 933
5547 12:18:35.993186 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5548 12:18:35.996258 best DQS0 dly(2T, 0.5T) = (0, 10)
5549 12:18:35.999550 best DQS1 dly(2T, 0.5T) = (0, 10)
5550 12:18:36.002638 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5551 12:18:36.006384 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5552 12:18:36.009532 best DQS0 dly(2T, 0.5T) = (0, 10)
5553 12:18:36.013179 best DQS1 dly(2T, 0.5T) = (0, 10)
5554 12:18:36.016660 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5555 12:18:36.019781 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5556 12:18:36.023231 Pre-setting of DQS Precalculation
5557 12:18:36.026369 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5558 12:18:36.026930 ==
5559 12:18:36.029490 Dram Type= 6, Freq= 0, CH_1, rank 0
5560 12:18:36.036000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5561 12:18:36.036571 ==
5562 12:18:36.039167 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5563 12:18:36.046356 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5564 12:18:36.049124 [CA 0] Center 36 (6~67) winsize 62
5565 12:18:36.052901 [CA 1] Center 37 (6~68) winsize 63
5566 12:18:36.055524 [CA 2] Center 35 (5~65) winsize 61
5567 12:18:36.059027 [CA 3] Center 34 (4~64) winsize 61
5568 12:18:36.062776 [CA 4] Center 34 (4~65) winsize 62
5569 12:18:36.065643 [CA 5] Center 33 (3~64) winsize 62
5570 12:18:36.066152
5571 12:18:36.069508 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5572 12:18:36.070109
5573 12:18:36.072444 [CATrainingPosCal] consider 1 rank data
5574 12:18:36.075806 u2DelayCellTimex100 = 270/100 ps
5575 12:18:36.079186 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5576 12:18:36.082687 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5577 12:18:36.089387 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5578 12:18:36.092547 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5579 12:18:36.096234 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5580 12:18:36.099232 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5581 12:18:36.099731
5582 12:18:36.102597 CA PerBit enable=1, Macro0, CA PI delay=33
5583 12:18:36.103180
5584 12:18:36.105820 [CBTSetCACLKResult] CA Dly = 33
5585 12:18:36.106446 CS Dly: 5 (0~36)
5586 12:18:36.106825 ==
5587 12:18:36.109327 Dram Type= 6, Freq= 0, CH_1, rank 1
5588 12:18:36.115663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5589 12:18:36.116230 ==
5590 12:18:36.119030 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5591 12:18:36.125880 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5592 12:18:36.129164 [CA 0] Center 37 (7~68) winsize 62
5593 12:18:36.132495 [CA 1] Center 37 (7~68) winsize 62
5594 12:18:36.136039 [CA 2] Center 35 (5~66) winsize 62
5595 12:18:36.139208 [CA 3] Center 35 (5~65) winsize 61
5596 12:18:36.142595 [CA 4] Center 34 (4~65) winsize 62
5597 12:18:36.145837 [CA 5] Center 34 (4~64) winsize 61
5598 12:18:36.146511
5599 12:18:36.149805 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5600 12:18:36.150521
5601 12:18:36.152233 [CATrainingPosCal] consider 2 rank data
5602 12:18:36.155708 u2DelayCellTimex100 = 270/100 ps
5603 12:18:36.159461 CA0 delay=37 (7~67),Diff = 3 PI (18 cell)
5604 12:18:36.162556 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5605 12:18:36.169007 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5606 12:18:36.172198 CA3 delay=34 (5~64),Diff = 0 PI (0 cell)
5607 12:18:36.175545 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5608 12:18:36.179000 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5609 12:18:36.179568
5610 12:18:36.182219 CA PerBit enable=1, Macro0, CA PI delay=34
5611 12:18:36.182783
5612 12:18:36.185649 [CBTSetCACLKResult] CA Dly = 34
5613 12:18:36.186254 CS Dly: 6 (0~38)
5614 12:18:36.189037
5615 12:18:36.192222 ----->DramcWriteLeveling(PI) begin...
5616 12:18:36.192785 ==
5617 12:18:36.195988 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 12:18:36.198854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 12:18:36.199370 ==
5620 12:18:36.202437 Write leveling (Byte 0): 26 => 26
5621 12:18:36.205471 Write leveling (Byte 1): 28 => 28
5622 12:18:36.208947 DramcWriteLeveling(PI) end<-----
5623 12:18:36.209503
5624 12:18:36.209873 ==
5625 12:18:36.212474 Dram Type= 6, Freq= 0, CH_1, rank 0
5626 12:18:36.215465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 12:18:36.215934 ==
5628 12:18:36.218564 [Gating] SW mode calibration
5629 12:18:36.225981 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5630 12:18:36.232314 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5631 12:18:36.235757 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5632 12:18:36.238765 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 12:18:36.242299 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 12:18:36.249102 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5635 12:18:36.252063 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 12:18:36.255599 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5637 12:18:36.262404 0 14 24 | B1->B0 | 3232 3232 | 1 1 | (1 1) (1 0)
5638 12:18:36.265505 0 14 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
5639 12:18:36.268669 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 12:18:36.275426 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 12:18:36.278597 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 12:18:36.282141 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5643 12:18:36.288985 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 12:18:36.291666 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 12:18:36.295281 0 15 24 | B1->B0 | 2727 2f2f | 0 0 | (0 0) (0 0)
5646 12:18:36.301808 0 15 28 | B1->B0 | 3c3c 3e3e | 1 0 | (0 0) (0 0)
5647 12:18:36.305556 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 12:18:36.308650 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 12:18:36.315539 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 12:18:36.318644 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 12:18:36.321901 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 12:18:36.328642 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 12:18:36.331711 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5654 12:18:36.335213 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 12:18:36.341776 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 12:18:36.345252 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 12:18:36.348678 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 12:18:36.355348 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 12:18:36.358320 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 12:18:36.361836 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 12:18:36.368554 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 12:18:36.371427 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 12:18:36.375018 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 12:18:36.381539 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 12:18:36.384848 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 12:18:36.388231 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 12:18:36.391737 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 12:18:36.398005 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5669 12:18:36.401574 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5670 12:18:36.404681 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5671 12:18:36.408076 Total UI for P1: 0, mck2ui 16
5672 12:18:36.411534 best dqsien dly found for B0: ( 1, 2, 22)
5673 12:18:36.414612 Total UI for P1: 0, mck2ui 16
5674 12:18:36.417995 best dqsien dly found for B1: ( 1, 2, 24)
5675 12:18:36.421231 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5676 12:18:36.424701 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5677 12:18:36.427953
5678 12:18:36.431353 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5679 12:18:36.434590 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5680 12:18:36.437928 [Gating] SW calibration Done
5681 12:18:36.438444 ==
5682 12:18:36.441413 Dram Type= 6, Freq= 0, CH_1, rank 0
5683 12:18:36.444760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5684 12:18:36.445325 ==
5685 12:18:36.445706 RX Vref Scan: 0
5686 12:18:36.448084
5687 12:18:36.448545 RX Vref 0 -> 0, step: 1
5688 12:18:36.448916
5689 12:18:36.451244 RX Delay -80 -> 252, step: 8
5690 12:18:36.454674 iDelay=208, Bit 0, Center 107 (24 ~ 191) 168
5691 12:18:36.457915 iDelay=208, Bit 1, Center 99 (16 ~ 183) 168
5692 12:18:36.464356 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5693 12:18:36.467705 iDelay=208, Bit 3, Center 107 (24 ~ 191) 168
5694 12:18:36.471712 iDelay=208, Bit 4, Center 107 (24 ~ 191) 168
5695 12:18:36.474532 iDelay=208, Bit 5, Center 115 (32 ~ 199) 168
5696 12:18:36.477825 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5697 12:18:36.484158 iDelay=208, Bit 7, Center 107 (24 ~ 191) 168
5698 12:18:36.487668 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5699 12:18:36.490675 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5700 12:18:36.494577 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5701 12:18:36.497622 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5702 12:18:36.500858 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5703 12:18:36.507333 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5704 12:18:36.511021 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5705 12:18:36.513993 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5706 12:18:36.514460 ==
5707 12:18:36.517240 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 12:18:36.520899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 12:18:36.521366 ==
5710 12:18:36.524241 DQS Delay:
5711 12:18:36.524818 DQS0 = 0, DQS1 = 0
5712 12:18:36.527183 DQM Delay:
5713 12:18:36.527648 DQM0 = 107, DQM1 = 98
5714 12:18:36.528018 DQ Delay:
5715 12:18:36.530572 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =107
5716 12:18:36.537360 DQ4 =107, DQ5 =115, DQ6 =119, DQ7 =107
5717 12:18:36.540729 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5718 12:18:36.544323 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =103
5719 12:18:36.544888
5720 12:18:36.545257
5721 12:18:36.545598 ==
5722 12:18:36.547561 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 12:18:36.550878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 12:18:36.551350 ==
5725 12:18:36.551726
5726 12:18:36.552134
5727 12:18:36.553718 TX Vref Scan disable
5728 12:18:36.554227 == TX Byte 0 ==
5729 12:18:36.560782 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5730 12:18:36.564195 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5731 12:18:36.564758 == TX Byte 1 ==
5732 12:18:36.570427 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5733 12:18:36.574003 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5734 12:18:36.574577 ==
5735 12:18:36.577264 Dram Type= 6, Freq= 0, CH_1, rank 0
5736 12:18:36.580388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 12:18:36.580992 ==
5738 12:18:36.581444
5739 12:18:36.583910
5740 12:18:36.584369 TX Vref Scan disable
5741 12:18:36.587276 == TX Byte 0 ==
5742 12:18:36.590875 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5743 12:18:36.593967 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5744 12:18:36.597490 == TX Byte 1 ==
5745 12:18:36.600781 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5746 12:18:36.604014 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5747 12:18:36.604482
5748 12:18:36.607087 [DATLAT]
5749 12:18:36.607549 Freq=933, CH1 RK0
5750 12:18:36.607921
5751 12:18:36.610691 DATLAT Default: 0xd
5752 12:18:36.611155 0, 0xFFFF, sum = 0
5753 12:18:36.613819 1, 0xFFFF, sum = 0
5754 12:18:36.614412 2, 0xFFFF, sum = 0
5755 12:18:36.617398 3, 0xFFFF, sum = 0
5756 12:18:36.618006 4, 0xFFFF, sum = 0
5757 12:18:36.620416 5, 0xFFFF, sum = 0
5758 12:18:36.621131 6, 0xFFFF, sum = 0
5759 12:18:36.623902 7, 0xFFFF, sum = 0
5760 12:18:36.624376 8, 0xFFFF, sum = 0
5761 12:18:36.627013 9, 0xFFFF, sum = 0
5762 12:18:36.627582 10, 0x0, sum = 1
5763 12:18:36.630650 11, 0x0, sum = 2
5764 12:18:36.631215 12, 0x0, sum = 3
5765 12:18:36.633643 13, 0x0, sum = 4
5766 12:18:36.634147 best_step = 11
5767 12:18:36.634525
5768 12:18:36.634876 ==
5769 12:18:36.637431 Dram Type= 6, Freq= 0, CH_1, rank 0
5770 12:18:36.643954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5771 12:18:36.644528 ==
5772 12:18:36.644965 RX Vref Scan: 1
5773 12:18:36.645315
5774 12:18:36.647130 RX Vref 0 -> 0, step: 1
5775 12:18:36.647692
5776 12:18:36.650264 RX Delay -45 -> 252, step: 4
5777 12:18:36.650728
5778 12:18:36.653678 Set Vref, RX VrefLevel [Byte0]: 53
5779 12:18:36.657269 [Byte1]: 53
5780 12:18:36.657731
5781 12:18:36.660525 Final RX Vref Byte 0 = 53 to rank0
5782 12:18:36.664074 Final RX Vref Byte 1 = 53 to rank0
5783 12:18:36.667075 Final RX Vref Byte 0 = 53 to rank1
5784 12:18:36.670498 Final RX Vref Byte 1 = 53 to rank1==
5785 12:18:36.673368 Dram Type= 6, Freq= 0, CH_1, rank 0
5786 12:18:36.677275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5787 12:18:36.677875 ==
5788 12:18:36.680209 DQS Delay:
5789 12:18:36.680670 DQS0 = 0, DQS1 = 0
5790 12:18:36.683920 DQM Delay:
5791 12:18:36.684482 DQM0 = 107, DQM1 = 100
5792 12:18:36.684851 DQ Delay:
5793 12:18:36.686964 DQ0 =110, DQ1 =102, DQ2 =100, DQ3 =106
5794 12:18:36.690252 DQ4 =106, DQ5 =116, DQ6 =116, DQ7 =104
5795 12:18:36.694015 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =92
5796 12:18:36.700723 DQ12 =110, DQ13 =104, DQ14 =110, DQ15 =104
5797 12:18:36.701277
5798 12:18:36.701648
5799 12:18:36.706671 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5800 12:18:36.709861 CH1 RK0: MR19=505, MR18=1A32
5801 12:18:36.717049 CH1_RK0: MR19=0x505, MR18=0x1A32, DQSOSC=406, MR23=63, INC=65, DEC=43
5802 12:18:36.717610
5803 12:18:36.720474 ----->DramcWriteLeveling(PI) begin...
5804 12:18:36.721085 ==
5805 12:18:36.723547 Dram Type= 6, Freq= 0, CH_1, rank 1
5806 12:18:36.727053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5807 12:18:36.727621 ==
5808 12:18:36.730650 Write leveling (Byte 0): 28 => 28
5809 12:18:36.733844 Write leveling (Byte 1): 29 => 29
5810 12:18:36.736721 DramcWriteLeveling(PI) end<-----
5811 12:18:36.737285
5812 12:18:36.737659 ==
5813 12:18:36.740233 Dram Type= 6, Freq= 0, CH_1, rank 1
5814 12:18:36.743842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5815 12:18:36.744424 ==
5816 12:18:36.746567 [Gating] SW mode calibration
5817 12:18:36.753204 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5818 12:18:36.759823 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5819 12:18:36.763593 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5820 12:18:36.770040 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5821 12:18:36.773752 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 12:18:36.776800 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5823 12:18:36.783118 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5824 12:18:36.786428 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 12:18:36.790066 0 14 24 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 0)
5826 12:18:36.793538 0 14 28 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
5827 12:18:36.799842 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5828 12:18:36.803170 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5829 12:18:36.806578 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5830 12:18:36.813569 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 12:18:36.816711 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5832 12:18:36.820003 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 12:18:36.826434 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 12:18:36.829893 0 15 28 | B1->B0 | 4141 3434 | 0 0 | (0 0) (0 0)
5835 12:18:36.833234 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 12:18:36.839756 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 12:18:36.843238 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 12:18:36.846600 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 12:18:36.853089 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 12:18:36.856663 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 12:18:36.859456 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5842 12:18:36.866389 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5843 12:18:36.869501 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 12:18:36.873318 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 12:18:36.879792 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 12:18:36.883596 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 12:18:36.886740 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 12:18:36.892805 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 12:18:36.895928 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 12:18:36.899814 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 12:18:36.906403 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 12:18:36.909392 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 12:18:36.912536 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 12:18:36.919178 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 12:18:36.922569 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 12:18:36.925768 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5857 12:18:36.932597 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 12:18:36.936057 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5859 12:18:36.939128 Total UI for P1: 0, mck2ui 16
5860 12:18:36.942727 best dqsien dly found for B0: ( 1, 2, 26)
5861 12:18:36.945588 Total UI for P1: 0, mck2ui 16
5862 12:18:36.948902 best dqsien dly found for B1: ( 1, 2, 26)
5863 12:18:36.952324 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5864 12:18:36.955731 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5865 12:18:36.956199
5866 12:18:36.959528 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5867 12:18:36.962740 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5868 12:18:36.965851 [Gating] SW calibration Done
5869 12:18:36.966503 ==
5870 12:18:36.968680 Dram Type= 6, Freq= 0, CH_1, rank 1
5871 12:18:36.972166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5872 12:18:36.975786 ==
5873 12:18:36.976350 RX Vref Scan: 0
5874 12:18:36.976720
5875 12:18:36.978878 RX Vref 0 -> 0, step: 1
5876 12:18:36.979341
5877 12:18:36.979707 RX Delay -80 -> 252, step: 8
5878 12:18:36.985823 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
5879 12:18:36.989007 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5880 12:18:36.992360 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5881 12:18:36.995237 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5882 12:18:36.998877 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5883 12:18:37.005563 iDelay=200, Bit 5, Center 115 (32 ~ 199) 168
5884 12:18:37.008841 iDelay=200, Bit 6, Center 111 (32 ~ 191) 160
5885 12:18:37.012287 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5886 12:18:37.015771 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5887 12:18:37.018729 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5888 12:18:37.025129 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5889 12:18:37.028661 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5890 12:18:37.032222 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5891 12:18:37.035395 iDelay=200, Bit 13, Center 103 (16 ~ 191) 176
5892 12:18:37.038787 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5893 12:18:37.045534 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5894 12:18:37.046136 ==
5895 12:18:37.049168 Dram Type= 6, Freq= 0, CH_1, rank 1
5896 12:18:37.051709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5897 12:18:37.052234 ==
5898 12:18:37.052609 DQS Delay:
5899 12:18:37.055239 DQS0 = 0, DQS1 = 0
5900 12:18:37.055701 DQM Delay:
5901 12:18:37.058779 DQM0 = 104, DQM1 = 96
5902 12:18:37.059238 DQ Delay:
5903 12:18:37.062031 DQ0 =111, DQ1 =99, DQ2 =91, DQ3 =103
5904 12:18:37.065694 DQ4 =103, DQ5 =115, DQ6 =111, DQ7 =103
5905 12:18:37.068762 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5906 12:18:37.072087 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5907 12:18:37.072650
5908 12:18:37.073021
5909 12:18:37.073361 ==
5910 12:18:37.075056 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 12:18:37.082239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 12:18:37.082948 ==
5913 12:18:37.083394
5914 12:18:37.083741
5915 12:18:37.084072 TX Vref Scan disable
5916 12:18:37.085395 == TX Byte 0 ==
5917 12:18:37.088896 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5918 12:18:37.092256 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5919 12:18:37.095695 == TX Byte 1 ==
5920 12:18:37.098839 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5921 12:18:37.101773 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5922 12:18:37.105575 ==
5923 12:18:37.108761 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 12:18:37.112091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 12:18:37.112667 ==
5926 12:18:37.113038
5927 12:18:37.113376
5928 12:18:37.115704 TX Vref Scan disable
5929 12:18:37.116273 == TX Byte 0 ==
5930 12:18:37.122088 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5931 12:18:37.125126 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5932 12:18:37.125592 == TX Byte 1 ==
5933 12:18:37.131600 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5934 12:18:37.135452 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5935 12:18:37.136018
5936 12:18:37.136383 [DATLAT]
5937 12:18:37.138436 Freq=933, CH1 RK1
5938 12:18:37.138898
5939 12:18:37.139262 DATLAT Default: 0xb
5940 12:18:37.142085 0, 0xFFFF, sum = 0
5941 12:18:37.142658 1, 0xFFFF, sum = 0
5942 12:18:37.145566 2, 0xFFFF, sum = 0
5943 12:18:37.146181 3, 0xFFFF, sum = 0
5944 12:18:37.149032 4, 0xFFFF, sum = 0
5945 12:18:37.149604 5, 0xFFFF, sum = 0
5946 12:18:37.151843 6, 0xFFFF, sum = 0
5947 12:18:37.152405 7, 0xFFFF, sum = 0
5948 12:18:37.155130 8, 0xFFFF, sum = 0
5949 12:18:37.155598 9, 0xFFFF, sum = 0
5950 12:18:37.159234 10, 0x0, sum = 1
5951 12:18:37.159806 11, 0x0, sum = 2
5952 12:18:37.161793 12, 0x0, sum = 3
5953 12:18:37.162415 13, 0x0, sum = 4
5954 12:18:37.164994 best_step = 11
5955 12:18:37.165553
5956 12:18:37.165918 ==
5957 12:18:37.168579 Dram Type= 6, Freq= 0, CH_1, rank 1
5958 12:18:37.172277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5959 12:18:37.172742 ==
5960 12:18:37.175004 RX Vref Scan: 0
5961 12:18:37.175467
5962 12:18:37.175830 RX Vref 0 -> 0, step: 1
5963 12:18:37.176171
5964 12:18:37.178357 RX Delay -53 -> 252, step: 4
5965 12:18:37.185447 iDelay=199, Bit 0, Center 112 (39 ~ 186) 148
5966 12:18:37.188905 iDelay=199, Bit 1, Center 104 (31 ~ 178) 148
5967 12:18:37.192436 iDelay=199, Bit 2, Center 98 (23 ~ 174) 152
5968 12:18:37.195510 iDelay=199, Bit 3, Center 106 (27 ~ 186) 160
5969 12:18:37.198856 iDelay=199, Bit 4, Center 108 (31 ~ 186) 156
5970 12:18:37.205305 iDelay=199, Bit 5, Center 120 (43 ~ 198) 156
5971 12:18:37.208874 iDelay=199, Bit 6, Center 116 (39 ~ 194) 156
5972 12:18:37.212207 iDelay=199, Bit 7, Center 106 (31 ~ 182) 152
5973 12:18:37.215344 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5974 12:18:37.218542 iDelay=199, Bit 9, Center 90 (11 ~ 170) 160
5975 12:18:37.225083 iDelay=199, Bit 10, Center 100 (19 ~ 182) 164
5976 12:18:37.228617 iDelay=199, Bit 11, Center 94 (11 ~ 178) 168
5977 12:18:37.231942 iDelay=199, Bit 12, Center 108 (27 ~ 190) 164
5978 12:18:37.235665 iDelay=199, Bit 13, Center 106 (23 ~ 190) 168
5979 12:18:37.238279 iDelay=199, Bit 14, Center 108 (27 ~ 190) 164
5980 12:18:37.245258 iDelay=199, Bit 15, Center 110 (27 ~ 194) 168
5981 12:18:37.245816 ==
5982 12:18:37.248746 Dram Type= 6, Freq= 0, CH_1, rank 1
5983 12:18:37.251958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5984 12:18:37.252454 ==
5985 12:18:37.252874 DQS Delay:
5986 12:18:37.255093 DQS0 = 0, DQS1 = 0
5987 12:18:37.255552 DQM Delay:
5988 12:18:37.258578 DQM0 = 108, DQM1 = 100
5989 12:18:37.259142 DQ Delay:
5990 12:18:37.262075 DQ0 =112, DQ1 =104, DQ2 =98, DQ3 =106
5991 12:18:37.265192 DQ4 =108, DQ5 =120, DQ6 =116, DQ7 =106
5992 12:18:37.268572 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =94
5993 12:18:37.271835 DQ12 =108, DQ13 =106, DQ14 =108, DQ15 =110
5994 12:18:37.272298
5995 12:18:37.272662
5996 12:18:37.282476 [DQSOSCAuto] RK1, (LSB)MR18= 0x2400, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 410 ps
5997 12:18:37.285448 CH1 RK1: MR19=505, MR18=2400
5998 12:18:37.289022 CH1_RK1: MR19=0x505, MR18=0x2400, DQSOSC=410, MR23=63, INC=64, DEC=42
5999 12:18:37.292601 [RxdqsGatingPostProcess] freq 933
6000 12:18:37.298866 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6001 12:18:37.302397 best DQS0 dly(2T, 0.5T) = (0, 10)
6002 12:18:37.306072 best DQS1 dly(2T, 0.5T) = (0, 10)
6003 12:18:37.308665 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6004 12:18:37.311693 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6005 12:18:37.315476 best DQS0 dly(2T, 0.5T) = (0, 10)
6006 12:18:37.318762 best DQS1 dly(2T, 0.5T) = (0, 10)
6007 12:18:37.322159 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6008 12:18:37.325210 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6009 12:18:37.325679 Pre-setting of DQS Precalculation
6010 12:18:37.331918 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6011 12:18:37.338651 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6012 12:18:37.345638 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6013 12:18:37.346268
6014 12:18:37.346641
6015 12:18:37.349026 [Calibration Summary] 1866 Mbps
6016 12:18:37.352009 CH 0, Rank 0
6017 12:18:37.352489 SW Impedance : PASS
6018 12:18:37.354930 DUTY Scan : NO K
6019 12:18:37.358591 ZQ Calibration : PASS
6020 12:18:37.359153 Jitter Meter : NO K
6021 12:18:37.362115 CBT Training : PASS
6022 12:18:37.365011 Write leveling : PASS
6023 12:18:37.365579 RX DQS gating : PASS
6024 12:18:37.368566 RX DQ/DQS(RDDQC) : PASS
6025 12:18:37.369135 TX DQ/DQS : PASS
6026 12:18:37.371544 RX DATLAT : PASS
6027 12:18:37.375090 RX DQ/DQS(Engine): PASS
6028 12:18:37.375661 TX OE : NO K
6029 12:18:37.378792 All Pass.
6030 12:18:37.379359
6031 12:18:37.379726 CH 0, Rank 1
6032 12:18:37.381761 SW Impedance : PASS
6033 12:18:37.382376 DUTY Scan : NO K
6034 12:18:37.385629 ZQ Calibration : PASS
6035 12:18:37.388413 Jitter Meter : NO K
6036 12:18:37.388972 CBT Training : PASS
6037 12:18:37.392191 Write leveling : PASS
6038 12:18:37.395113 RX DQS gating : PASS
6039 12:18:37.395675 RX DQ/DQS(RDDQC) : PASS
6040 12:18:37.398616 TX DQ/DQS : PASS
6041 12:18:37.401817 RX DATLAT : PASS
6042 12:18:37.402433 RX DQ/DQS(Engine): PASS
6043 12:18:37.405200 TX OE : NO K
6044 12:18:37.405765 All Pass.
6045 12:18:37.406176
6046 12:18:37.408492 CH 1, Rank 0
6047 12:18:37.409104 SW Impedance : PASS
6048 12:18:37.411506 DUTY Scan : NO K
6049 12:18:37.411969 ZQ Calibration : PASS
6050 12:18:37.415069 Jitter Meter : NO K
6051 12:18:37.418124 CBT Training : PASS
6052 12:18:37.418594 Write leveling : PASS
6053 12:18:37.421706 RX DQS gating : PASS
6054 12:18:37.425059 RX DQ/DQS(RDDQC) : PASS
6055 12:18:37.425683 TX DQ/DQS : PASS
6056 12:18:37.428808 RX DATLAT : PASS
6057 12:18:37.431885 RX DQ/DQS(Engine): PASS
6058 12:18:37.432597 TX OE : NO K
6059 12:18:37.435303 All Pass.
6060 12:18:37.435868
6061 12:18:37.436245 CH 1, Rank 1
6062 12:18:37.438471 SW Impedance : PASS
6063 12:18:37.438936 DUTY Scan : NO K
6064 12:18:37.441838 ZQ Calibration : PASS
6065 12:18:37.445543 Jitter Meter : NO K
6066 12:18:37.446153 CBT Training : PASS
6067 12:18:37.448660 Write leveling : PASS
6068 12:18:37.451731 RX DQS gating : PASS
6069 12:18:37.452362 RX DQ/DQS(RDDQC) : PASS
6070 12:18:37.454764 TX DQ/DQS : PASS
6071 12:18:37.455231 RX DATLAT : PASS
6072 12:18:37.458492 RX DQ/DQS(Engine): PASS
6073 12:18:37.461727 TX OE : NO K
6074 12:18:37.462332 All Pass.
6075 12:18:37.462713
6076 12:18:37.465279 DramC Write-DBI off
6077 12:18:37.465849 PER_BANK_REFRESH: Hybrid Mode
6078 12:18:37.468694 TX_TRACKING: ON
6079 12:18:37.478784 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6080 12:18:37.481631 [FAST_K] Save calibration result to emmc
6081 12:18:37.485681 dramc_set_vcore_voltage set vcore to 650000
6082 12:18:37.486285 Read voltage for 400, 6
6083 12:18:37.488370 Vio18 = 0
6084 12:18:37.488936 Vcore = 650000
6085 12:18:37.489306 Vdram = 0
6086 12:18:37.491483 Vddq = 0
6087 12:18:37.492049 Vmddr = 0
6088 12:18:37.497869 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6089 12:18:37.501553 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6090 12:18:37.504976 MEM_TYPE=3, freq_sel=20
6091 12:18:37.508505 sv_algorithm_assistance_LP4_800
6092 12:18:37.511799 ============ PULL DRAM RESETB DOWN ============
6093 12:18:37.514565 ========== PULL DRAM RESETB DOWN end =========
6094 12:18:37.521213 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6095 12:18:37.524733 ===================================
6096 12:18:37.525328 LPDDR4 DRAM CONFIGURATION
6097 12:18:37.527702 ===================================
6098 12:18:37.531186 EX_ROW_EN[0] = 0x0
6099 12:18:37.531652 EX_ROW_EN[1] = 0x0
6100 12:18:37.534700 LP4Y_EN = 0x0
6101 12:18:37.537828 WORK_FSP = 0x0
6102 12:18:37.538423 WL = 0x2
6103 12:18:37.541980 RL = 0x2
6104 12:18:37.542576 BL = 0x2
6105 12:18:37.544731 RPST = 0x0
6106 12:18:37.545194 RD_PRE = 0x0
6107 12:18:37.547631 WR_PRE = 0x1
6108 12:18:37.548096 WR_PST = 0x0
6109 12:18:37.551930 DBI_WR = 0x0
6110 12:18:37.552568 DBI_RD = 0x0
6111 12:18:37.554604 OTF = 0x1
6112 12:18:37.558031 ===================================
6113 12:18:37.561384 ===================================
6114 12:18:37.562004 ANA top config
6115 12:18:37.564681 ===================================
6116 12:18:37.568028 DLL_ASYNC_EN = 0
6117 12:18:37.571676 ALL_SLAVE_EN = 1
6118 12:18:37.572278 NEW_RANK_MODE = 1
6119 12:18:37.574159 DLL_IDLE_MODE = 1
6120 12:18:37.577783 LP45_APHY_COMB_EN = 1
6121 12:18:37.581311 TX_ODT_DIS = 1
6122 12:18:37.584601 NEW_8X_MODE = 1
6123 12:18:37.588137 ===================================
6124 12:18:37.591352 ===================================
6125 12:18:37.592083 data_rate = 800
6126 12:18:37.594417 CKR = 1
6127 12:18:37.597875 DQ_P2S_RATIO = 4
6128 12:18:37.601061 ===================================
6129 12:18:37.604063 CA_P2S_RATIO = 4
6130 12:18:37.607228 DQ_CA_OPEN = 0
6131 12:18:37.610744 DQ_SEMI_OPEN = 1
6132 12:18:37.611212 CA_SEMI_OPEN = 1
6133 12:18:37.614031 CA_FULL_RATE = 0
6134 12:18:37.617292 DQ_CKDIV4_EN = 0
6135 12:18:37.620503 CA_CKDIV4_EN = 1
6136 12:18:37.624052 CA_PREDIV_EN = 0
6137 12:18:37.627421 PH8_DLY = 0
6138 12:18:37.627893 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6139 12:18:37.630646 DQ_AAMCK_DIV = 0
6140 12:18:37.634108 CA_AAMCK_DIV = 0
6141 12:18:37.637309 CA_ADMCK_DIV = 4
6142 12:18:37.640707 DQ_TRACK_CA_EN = 0
6143 12:18:37.643931 CA_PICK = 800
6144 12:18:37.647370 CA_MCKIO = 400
6145 12:18:37.647957 MCKIO_SEMI = 400
6146 12:18:37.650352 PLL_FREQ = 3016
6147 12:18:37.653849 DQ_UI_PI_RATIO = 32
6148 12:18:37.657011 CA_UI_PI_RATIO = 32
6149 12:18:37.660871 ===================================
6150 12:18:37.664157 ===================================
6151 12:18:37.667577 memory_type:LPDDR4
6152 12:18:37.668108 GP_NUM : 10
6153 12:18:37.670741 SRAM_EN : 1
6154 12:18:37.673860 MD32_EN : 0
6155 12:18:37.677053 ===================================
6156 12:18:37.677590 [ANA_INIT] >>>>>>>>>>>>>>
6157 12:18:37.680548 <<<<<< [CONFIGURE PHASE]: ANA_TX
6158 12:18:37.684285 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6159 12:18:37.687365 ===================================
6160 12:18:37.690677 data_rate = 800,PCW = 0X7400
6161 12:18:37.693516 ===================================
6162 12:18:37.697343 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6163 12:18:37.703755 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6164 12:18:37.713528 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6165 12:18:37.717055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6166 12:18:37.723502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6167 12:18:37.726816 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6168 12:18:37.727499 [ANA_INIT] flow start
6169 12:18:37.730299 [ANA_INIT] PLL >>>>>>>>
6170 12:18:37.733700 [ANA_INIT] PLL <<<<<<<<
6171 12:18:37.734331 [ANA_INIT] MIDPI >>>>>>>>
6172 12:18:37.737196 [ANA_INIT] MIDPI <<<<<<<<
6173 12:18:37.740300 [ANA_INIT] DLL >>>>>>>>
6174 12:18:37.740881 [ANA_INIT] flow end
6175 12:18:37.743503 ============ LP4 DIFF to SE enter ============
6176 12:18:37.750068 ============ LP4 DIFF to SE exit ============
6177 12:18:37.750645 [ANA_INIT] <<<<<<<<<<<<<
6178 12:18:37.753092 [Flow] Enable top DCM control >>>>>
6179 12:18:37.756890 [Flow] Enable top DCM control <<<<<
6180 12:18:37.760158 Enable DLL master slave shuffle
6181 12:18:37.766664 ==============================================================
6182 12:18:37.767243 Gating Mode config
6183 12:18:37.773229 ==============================================================
6184 12:18:37.776720 Config description:
6185 12:18:37.786599 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6186 12:18:37.793484 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6187 12:18:37.796465 SELPH_MODE 0: By rank 1: By Phase
6188 12:18:37.803215 ==============================================================
6189 12:18:37.806454 GAT_TRACK_EN = 0
6190 12:18:37.809474 RX_GATING_MODE = 2
6191 12:18:37.809984 RX_GATING_TRACK_MODE = 2
6192 12:18:37.812987 SELPH_MODE = 1
6193 12:18:37.816393 PICG_EARLY_EN = 1
6194 12:18:37.819906 VALID_LAT_VALUE = 1
6195 12:18:37.826588 ==============================================================
6196 12:18:37.829719 Enter into Gating configuration >>>>
6197 12:18:37.832987 Exit from Gating configuration <<<<
6198 12:18:37.836461 Enter into DVFS_PRE_config >>>>>
6199 12:18:37.846479 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6200 12:18:37.849271 Exit from DVFS_PRE_config <<<<<
6201 12:18:37.852821 Enter into PICG configuration >>>>
6202 12:18:37.856366 Exit from PICG configuration <<<<
6203 12:18:37.859588 [RX_INPUT] configuration >>>>>
6204 12:18:37.862743 [RX_INPUT] configuration <<<<<
6205 12:18:37.866058 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6206 12:18:37.872763 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6207 12:18:37.879648 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6208 12:18:37.886490 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6209 12:18:37.889741 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6210 12:18:37.896696 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6211 12:18:37.899928 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6212 12:18:37.906329 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6213 12:18:37.910159 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6214 12:18:37.913351 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6215 12:18:37.916739 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6216 12:18:37.923254 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6217 12:18:37.926628 ===================================
6218 12:18:37.927196 LPDDR4 DRAM CONFIGURATION
6219 12:18:37.929735 ===================================
6220 12:18:37.933290 EX_ROW_EN[0] = 0x0
6221 12:18:37.936461 EX_ROW_EN[1] = 0x0
6222 12:18:37.937029 LP4Y_EN = 0x0
6223 12:18:37.939427 WORK_FSP = 0x0
6224 12:18:37.939894 WL = 0x2
6225 12:18:37.943189 RL = 0x2
6226 12:18:37.943749 BL = 0x2
6227 12:18:37.946132 RPST = 0x0
6228 12:18:37.946603 RD_PRE = 0x0
6229 12:18:37.949728 WR_PRE = 0x1
6230 12:18:37.950357 WR_PST = 0x0
6231 12:18:37.953256 DBI_WR = 0x0
6232 12:18:37.953821 DBI_RD = 0x0
6233 12:18:37.956158 OTF = 0x1
6234 12:18:37.959977 ===================================
6235 12:18:37.962882 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6236 12:18:37.966297 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6237 12:18:37.973298 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6238 12:18:37.976423 ===================================
6239 12:18:37.977041 LPDDR4 DRAM CONFIGURATION
6240 12:18:37.979771 ===================================
6241 12:18:37.982780 EX_ROW_EN[0] = 0x10
6242 12:18:37.983248 EX_ROW_EN[1] = 0x0
6243 12:18:37.986315 LP4Y_EN = 0x0
6244 12:18:37.986778 WORK_FSP = 0x0
6245 12:18:37.989749 WL = 0x2
6246 12:18:37.993531 RL = 0x2
6247 12:18:37.994137 BL = 0x2
6248 12:18:37.996234 RPST = 0x0
6249 12:18:37.996796 RD_PRE = 0x0
6250 12:18:37.999444 WR_PRE = 0x1
6251 12:18:38.000004 WR_PST = 0x0
6252 12:18:38.002839 DBI_WR = 0x0
6253 12:18:38.003400 DBI_RD = 0x0
6254 12:18:38.006048 OTF = 0x1
6255 12:18:38.009558 ===================================
6256 12:18:38.016008 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6257 12:18:38.019162 nWR fixed to 30
6258 12:18:38.019733 [ModeRegInit_LP4] CH0 RK0
6259 12:18:38.022509 [ModeRegInit_LP4] CH0 RK1
6260 12:18:38.026017 [ModeRegInit_LP4] CH1 RK0
6261 12:18:38.029020 [ModeRegInit_LP4] CH1 RK1
6262 12:18:38.029488 match AC timing 19
6263 12:18:38.032215 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6264 12:18:38.039133 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6265 12:18:38.042672 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6266 12:18:38.045575 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6267 12:18:38.052424 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6268 12:18:38.052986 ==
6269 12:18:38.055407 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 12:18:38.058515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 12:18:38.058986 ==
6272 12:18:38.065309 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6273 12:18:38.071881 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6274 12:18:38.075242 [CA 0] Center 36 (8~64) winsize 57
6275 12:18:38.075720 [CA 1] Center 36 (8~64) winsize 57
6276 12:18:38.078716 [CA 2] Center 36 (8~64) winsize 57
6277 12:18:38.081479 [CA 3] Center 36 (8~64) winsize 57
6278 12:18:38.085509 [CA 4] Center 36 (8~64) winsize 57
6279 12:18:38.088446 [CA 5] Center 36 (8~64) winsize 57
6280 12:18:38.089011
6281 12:18:38.091730 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6282 12:18:38.092202
6283 12:18:38.098338 [CATrainingPosCal] consider 1 rank data
6284 12:18:38.098889 u2DelayCellTimex100 = 270/100 ps
6285 12:18:38.105153 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 12:18:38.108458 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 12:18:38.112290 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 12:18:38.114942 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 12:18:38.118771 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 12:18:38.121759 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 12:18:38.122401
6292 12:18:38.125077 CA PerBit enable=1, Macro0, CA PI delay=36
6293 12:18:38.125640
6294 12:18:38.128404 [CBTSetCACLKResult] CA Dly = 36
6295 12:18:38.131746 CS Dly: 1 (0~32)
6296 12:18:38.132222 ==
6297 12:18:38.135355 Dram Type= 6, Freq= 0, CH_0, rank 1
6298 12:18:38.138641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6299 12:18:38.139212 ==
6300 12:18:38.145214 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6301 12:18:38.148201 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6302 12:18:38.151610 [CA 0] Center 36 (8~64) winsize 57
6303 12:18:38.155294 [CA 1] Center 36 (8~64) winsize 57
6304 12:18:38.158108 [CA 2] Center 36 (8~64) winsize 57
6305 12:18:38.161396 [CA 3] Center 36 (8~64) winsize 57
6306 12:18:38.164791 [CA 4] Center 36 (8~64) winsize 57
6307 12:18:38.168107 [CA 5] Center 36 (8~64) winsize 57
6308 12:18:38.168686
6309 12:18:38.171343 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6310 12:18:38.171813
6311 12:18:38.174632 [CATrainingPosCal] consider 2 rank data
6312 12:18:38.178088 u2DelayCellTimex100 = 270/100 ps
6313 12:18:38.181316 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 12:18:38.184529 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 12:18:38.188190 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 12:18:38.194573 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 12:18:38.197897 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 12:18:38.201313 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 12:18:38.201875
6320 12:18:38.204169 CA PerBit enable=1, Macro0, CA PI delay=36
6321 12:18:38.204639
6322 12:18:38.207853 [CBTSetCACLKResult] CA Dly = 36
6323 12:18:38.208422 CS Dly: 1 (0~32)
6324 12:18:38.208802
6325 12:18:38.211476 ----->DramcWriteLeveling(PI) begin...
6326 12:18:38.211953 ==
6327 12:18:38.214451 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 12:18:38.221045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 12:18:38.221606 ==
6330 12:18:38.224791 Write leveling (Byte 0): 40 => 8
6331 12:18:38.227958 Write leveling (Byte 1): 32 => 0
6332 12:18:38.228522 DramcWriteLeveling(PI) end<-----
6333 12:18:38.228900
6334 12:18:38.231062 ==
6335 12:18:38.231534 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 12:18:38.237903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 12:18:38.238515 ==
6338 12:18:38.241142 [Gating] SW mode calibration
6339 12:18:38.247506 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6340 12:18:38.251162 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6341 12:18:38.258046 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6342 12:18:38.261374 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6343 12:18:38.264296 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6344 12:18:38.270993 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6345 12:18:38.274326 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6346 12:18:38.277359 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6347 12:18:38.284124 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6348 12:18:38.287457 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6349 12:18:38.290889 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6350 12:18:38.294107 Total UI for P1: 0, mck2ui 16
6351 12:18:38.297258 best dqsien dly found for B0: ( 0, 14, 24)
6352 12:18:38.301034 Total UI for P1: 0, mck2ui 16
6353 12:18:38.304070 best dqsien dly found for B1: ( 0, 14, 24)
6354 12:18:38.307647 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6355 12:18:38.310815 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6356 12:18:38.311381
6357 12:18:38.317655 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6358 12:18:38.321176 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6359 12:18:38.321744 [Gating] SW calibration Done
6360 12:18:38.323983 ==
6361 12:18:38.327104 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 12:18:38.330706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 12:18:38.331161 ==
6364 12:18:38.331520 RX Vref Scan: 0
6365 12:18:38.331854
6366 12:18:38.333882 RX Vref 0 -> 0, step: 1
6367 12:18:38.334373
6368 12:18:38.337569 RX Delay -410 -> 252, step: 16
6369 12:18:38.340570 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6370 12:18:38.344041 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6371 12:18:38.350590 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6372 12:18:38.354317 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6373 12:18:38.357588 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6374 12:18:38.360683 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6375 12:18:38.367034 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6376 12:18:38.370277 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6377 12:18:38.373980 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6378 12:18:38.377345 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6379 12:18:38.383954 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6380 12:18:38.387117 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6381 12:18:38.390363 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6382 12:18:38.393799 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6383 12:18:38.400783 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6384 12:18:38.403844 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6385 12:18:38.404396 ==
6386 12:18:38.407223 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 12:18:38.410643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 12:18:38.411151 ==
6389 12:18:38.414303 DQS Delay:
6390 12:18:38.414854 DQS0 = 27, DQS1 = 43
6391 12:18:38.417188 DQM Delay:
6392 12:18:38.417737 DQM0 = 12, DQM1 = 12
6393 12:18:38.418132 DQ Delay:
6394 12:18:38.420820 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6395 12:18:38.423637 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6396 12:18:38.427005 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6397 12:18:38.430554 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6398 12:18:38.431244
6399 12:18:38.431619
6400 12:18:38.431967 ==
6401 12:18:38.433441 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 12:18:38.440549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 12:18:38.441120 ==
6404 12:18:38.441490
6405 12:18:38.441825
6406 12:18:38.442188 TX Vref Scan disable
6407 12:18:38.443775 == TX Byte 0 ==
6408 12:18:38.446863 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6409 12:18:38.450576 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6410 12:18:38.453539 == TX Byte 1 ==
6411 12:18:38.456791 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6412 12:18:38.460366 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6413 12:18:38.463429 ==
6414 12:18:38.463887 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 12:18:38.470196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 12:18:38.470763 ==
6417 12:18:38.471229
6418 12:18:38.471579
6419 12:18:38.473536 TX Vref Scan disable
6420 12:18:38.474187 == TX Byte 0 ==
6421 12:18:38.476545 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6422 12:18:38.483281 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6423 12:18:38.483828 == TX Byte 1 ==
6424 12:18:38.486849 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6425 12:18:38.493654 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6426 12:18:38.494254
6427 12:18:38.494685 [DATLAT]
6428 12:18:38.495033 Freq=400, CH0 RK0
6429 12:18:38.495364
6430 12:18:38.496437 DATLAT Default: 0xf
6431 12:18:38.499563 0, 0xFFFF, sum = 0
6432 12:18:38.500025 1, 0xFFFF, sum = 0
6433 12:18:38.503664 2, 0xFFFF, sum = 0
6434 12:18:38.504232 3, 0xFFFF, sum = 0
6435 12:18:38.506516 4, 0xFFFF, sum = 0
6436 12:18:38.506981 5, 0xFFFF, sum = 0
6437 12:18:38.509878 6, 0xFFFF, sum = 0
6438 12:18:38.510466 7, 0xFFFF, sum = 0
6439 12:18:38.513627 8, 0xFFFF, sum = 0
6440 12:18:38.514251 9, 0xFFFF, sum = 0
6441 12:18:38.516489 10, 0xFFFF, sum = 0
6442 12:18:38.517074 11, 0xFFFF, sum = 0
6443 12:18:38.520095 12, 0xFFFF, sum = 0
6444 12:18:38.520668 13, 0x0, sum = 1
6445 12:18:38.523506 14, 0x0, sum = 2
6446 12:18:38.524070 15, 0x0, sum = 3
6447 12:18:38.526782 16, 0x0, sum = 4
6448 12:18:38.527350 best_step = 14
6449 12:18:38.527715
6450 12:18:38.528048 ==
6451 12:18:38.529593 Dram Type= 6, Freq= 0, CH_0, rank 0
6452 12:18:38.533341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6453 12:18:38.536824 ==
6454 12:18:38.537383 RX Vref Scan: 1
6455 12:18:38.537748
6456 12:18:38.540384 RX Vref 0 -> 0, step: 1
6457 12:18:38.540940
6458 12:18:38.542781 RX Delay -327 -> 252, step: 8
6459 12:18:38.543241
6460 12:18:38.546521 Set Vref, RX VrefLevel [Byte0]: 59
6461 12:18:38.550129 [Byte1]: 49
6462 12:18:38.550678
6463 12:18:38.553325 Final RX Vref Byte 0 = 59 to rank0
6464 12:18:38.556406 Final RX Vref Byte 1 = 49 to rank0
6465 12:18:38.559297 Final RX Vref Byte 0 = 59 to rank1
6466 12:18:38.562845 Final RX Vref Byte 1 = 49 to rank1==
6467 12:18:38.566391 Dram Type= 6, Freq= 0, CH_0, rank 0
6468 12:18:38.569742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 12:18:38.570364 ==
6470 12:18:38.572838 DQS Delay:
6471 12:18:38.573295 DQS0 = 28, DQS1 = 48
6472 12:18:38.576425 DQM Delay:
6473 12:18:38.576981 DQM0 = 12, DQM1 = 15
6474 12:18:38.577343 DQ Delay:
6475 12:18:38.579701 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6476 12:18:38.582705 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =20
6477 12:18:38.586053 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =12
6478 12:18:38.589040 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6479 12:18:38.589511
6480 12:18:38.589879
6481 12:18:38.599498 [DQSOSCAuto] RK0, (LSB)MR18= 0xaba3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6482 12:18:38.602574 CH0 RK0: MR19=C0C, MR18=ABA3
6483 12:18:38.606106 CH0_RK0: MR19=0xC0C, MR18=0xABA3, DQSOSC=388, MR23=63, INC=392, DEC=261
6484 12:18:38.608973 ==
6485 12:18:38.612381 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 12:18:38.616050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 12:18:38.616571 ==
6488 12:18:38.619105 [Gating] SW mode calibration
6489 12:18:38.626099 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6490 12:18:38.629437 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6491 12:18:38.636152 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6492 12:18:38.639347 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6493 12:18:38.642701 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 12:18:38.649212 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6495 12:18:38.652197 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6496 12:18:38.655838 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6497 12:18:38.662643 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6498 12:18:38.666623 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 12:18:38.669288 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6500 12:18:38.672597 Total UI for P1: 0, mck2ui 16
6501 12:18:38.675753 best dqsien dly found for B0: ( 0, 14, 24)
6502 12:18:38.679323 Total UI for P1: 0, mck2ui 16
6503 12:18:38.682839 best dqsien dly found for B1: ( 0, 14, 24)
6504 12:18:38.685697 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6505 12:18:38.689113 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6506 12:18:38.689681
6507 12:18:38.695787 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6508 12:18:38.699356 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6509 12:18:38.699953 [Gating] SW calibration Done
6510 12:18:38.702772 ==
6511 12:18:38.703349 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 12:18:38.709463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 12:18:38.710097 ==
6514 12:18:38.710484 RX Vref Scan: 0
6515 12:18:38.710840
6516 12:18:38.712652 RX Vref 0 -> 0, step: 1
6517 12:18:38.713118
6518 12:18:38.715750 RX Delay -410 -> 252, step: 16
6519 12:18:38.719446 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6520 12:18:38.722435 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6521 12:18:38.729332 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6522 12:18:38.732095 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6523 12:18:38.735665 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6524 12:18:38.739238 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6525 12:18:38.746079 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6526 12:18:38.749312 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6527 12:18:38.752646 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6528 12:18:38.755789 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6529 12:18:38.762480 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6530 12:18:38.766040 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6531 12:18:38.769151 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6532 12:18:38.772677 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6533 12:18:38.779140 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6534 12:18:38.782331 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6535 12:18:38.782910 ==
6536 12:18:38.785627 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 12:18:38.788707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 12:18:38.789180 ==
6539 12:18:38.792410 DQS Delay:
6540 12:18:38.792983 DQS0 = 27, DQS1 = 43
6541 12:18:38.795727 DQM Delay:
6542 12:18:38.796318 DQM0 = 9, DQM1 = 15
6543 12:18:38.796697 DQ Delay:
6544 12:18:38.799027 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6545 12:18:38.802337 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6546 12:18:38.805629 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6547 12:18:38.808628 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6548 12:18:38.809099
6549 12:18:38.809473
6550 12:18:38.809821 ==
6551 12:18:38.812210 Dram Type= 6, Freq= 0, CH_0, rank 1
6552 12:18:38.815530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6553 12:18:38.818836 ==
6554 12:18:38.819306
6555 12:18:38.819680
6556 12:18:38.820023 TX Vref Scan disable
6557 12:18:38.822179 == TX Byte 0 ==
6558 12:18:38.825431 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6559 12:18:38.829111 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6560 12:18:38.832005 == TX Byte 1 ==
6561 12:18:38.835176 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6562 12:18:38.838618 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6563 12:18:38.839091 ==
6564 12:18:38.842045 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 12:18:38.848594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 12:18:38.849196 ==
6567 12:18:38.849575
6568 12:18:38.849921
6569 12:18:38.850307 TX Vref Scan disable
6570 12:18:38.852068 == TX Byte 0 ==
6571 12:18:38.855437 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6572 12:18:38.858731 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6573 12:18:38.862108 == TX Byte 1 ==
6574 12:18:38.865524 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6575 12:18:38.868572 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6576 12:18:38.869045
6577 12:18:38.871752 [DATLAT]
6578 12:18:38.872292 Freq=400, CH0 RK1
6579 12:18:38.872680
6580 12:18:38.875080 DATLAT Default: 0xe
6581 12:18:38.875556 0, 0xFFFF, sum = 0
6582 12:18:38.878751 1, 0xFFFF, sum = 0
6583 12:18:38.879231 2, 0xFFFF, sum = 0
6584 12:18:38.881590 3, 0xFFFF, sum = 0
6585 12:18:38.882105 4, 0xFFFF, sum = 0
6586 12:18:38.885072 5, 0xFFFF, sum = 0
6587 12:18:38.885581 6, 0xFFFF, sum = 0
6588 12:18:38.888622 7, 0xFFFF, sum = 0
6589 12:18:38.889095 8, 0xFFFF, sum = 0
6590 12:18:38.891808 9, 0xFFFF, sum = 0
6591 12:18:38.892240 10, 0xFFFF, sum = 0
6592 12:18:38.895011 11, 0xFFFF, sum = 0
6593 12:18:38.895444 12, 0xFFFF, sum = 0
6594 12:18:38.898534 13, 0x0, sum = 1
6595 12:18:38.898965 14, 0x0, sum = 2
6596 12:18:38.901971 15, 0x0, sum = 3
6597 12:18:38.902411 16, 0x0, sum = 4
6598 12:18:38.905270 best_step = 14
6599 12:18:38.905801
6600 12:18:38.906215 ==
6601 12:18:38.908640 Dram Type= 6, Freq= 0, CH_0, rank 1
6602 12:18:38.911660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6603 12:18:38.912093 ==
6604 12:18:38.915251 RX Vref Scan: 0
6605 12:18:38.915678
6606 12:18:38.916066 RX Vref 0 -> 0, step: 1
6607 12:18:38.916403
6608 12:18:38.918574 RX Delay -327 -> 252, step: 8
6609 12:18:38.927254 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6610 12:18:38.929704 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6611 12:18:38.932869 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6612 12:18:38.936077 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6613 12:18:38.942802 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6614 12:18:38.946313 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6615 12:18:38.949368 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6616 12:18:38.953029 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6617 12:18:38.959459 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6618 12:18:38.963007 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6619 12:18:38.966344 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6620 12:18:38.969623 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6621 12:18:38.976369 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6622 12:18:38.979638 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6623 12:18:38.982990 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6624 12:18:38.989738 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6625 12:18:38.990361 ==
6626 12:18:38.992710 Dram Type= 6, Freq= 0, CH_0, rank 1
6627 12:18:38.996036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6628 12:18:38.996612 ==
6629 12:18:38.996994 DQS Delay:
6630 12:18:38.999419 DQS0 = 28, DQS1 = 40
6631 12:18:38.999991 DQM Delay:
6632 12:18:39.002788 DQM0 = 10, DQM1 = 11
6633 12:18:39.003370 DQ Delay:
6634 12:18:39.006259 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6635 12:18:39.009569 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6636 12:18:39.012922 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6637 12:18:39.016008 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6638 12:18:39.016561
6639 12:18:39.016943
6640 12:18:39.022729 [DQSOSCAuto] RK1, (LSB)MR18= 0xb76a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6641 12:18:39.026104 CH0 RK1: MR19=C0C, MR18=B76A
6642 12:18:39.032559 CH0_RK1: MR19=0xC0C, MR18=0xB76A, DQSOSC=387, MR23=63, INC=394, DEC=262
6643 12:18:39.036242 [RxdqsGatingPostProcess] freq 400
6644 12:18:39.042710 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6645 12:18:39.043287 best DQS0 dly(2T, 0.5T) = (0, 10)
6646 12:18:39.045558 best DQS1 dly(2T, 0.5T) = (0, 10)
6647 12:18:39.049252 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6648 12:18:39.052830 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6649 12:18:39.056054 best DQS0 dly(2T, 0.5T) = (0, 10)
6650 12:18:39.059254 best DQS1 dly(2T, 0.5T) = (0, 10)
6651 12:18:39.062484 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6652 12:18:39.065771 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6653 12:18:39.069242 Pre-setting of DQS Precalculation
6654 12:18:39.075662 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6655 12:18:39.076138 ==
6656 12:18:39.079066 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 12:18:39.082377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 12:18:39.082954 ==
6659 12:18:39.089396 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6660 12:18:39.092286 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6661 12:18:39.095714 [CA 0] Center 36 (8~64) winsize 57
6662 12:18:39.098821 [CA 1] Center 36 (8~64) winsize 57
6663 12:18:39.102335 [CA 2] Center 36 (8~64) winsize 57
6664 12:18:39.105722 [CA 3] Center 36 (8~64) winsize 57
6665 12:18:39.108700 [CA 4] Center 36 (8~64) winsize 57
6666 12:18:39.112194 [CA 5] Center 36 (8~64) winsize 57
6667 12:18:39.112775
6668 12:18:39.115291 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6669 12:18:39.115762
6670 12:18:39.118562 [CATrainingPosCal] consider 1 rank data
6671 12:18:39.122105 u2DelayCellTimex100 = 270/100 ps
6672 12:18:39.125233 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 12:18:39.128689 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 12:18:39.132047 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 12:18:39.138586 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 12:18:39.141623 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 12:18:39.145434 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 12:18:39.146141
6679 12:18:39.148579 CA PerBit enable=1, Macro0, CA PI delay=36
6680 12:18:39.149162
6681 12:18:39.151853 [CBTSetCACLKResult] CA Dly = 36
6682 12:18:39.152440 CS Dly: 1 (0~32)
6683 12:18:39.152857 ==
6684 12:18:39.155050 Dram Type= 6, Freq= 0, CH_1, rank 1
6685 12:18:39.161432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6686 12:18:39.161905 ==
6687 12:18:39.164945 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6688 12:18:39.171529 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6689 12:18:39.174566 [CA 0] Center 36 (8~64) winsize 57
6690 12:18:39.178114 [CA 1] Center 36 (8~64) winsize 57
6691 12:18:39.181569 [CA 2] Center 36 (8~64) winsize 57
6692 12:18:39.184888 [CA 3] Center 36 (8~64) winsize 57
6693 12:18:39.188178 [CA 4] Center 36 (8~64) winsize 57
6694 12:18:39.191065 [CA 5] Center 36 (8~64) winsize 57
6695 12:18:39.191537
6696 12:18:39.194872 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6697 12:18:39.195447
6698 12:18:39.197804 [CATrainingPosCal] consider 2 rank data
6699 12:18:39.200883 u2DelayCellTimex100 = 270/100 ps
6700 12:18:39.204842 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 12:18:39.208262 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 12:18:39.211619 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 12:18:39.214748 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 12:18:39.217898 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 12:18:39.224365 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 12:18:39.224925
6707 12:18:39.228191 CA PerBit enable=1, Macro0, CA PI delay=36
6708 12:18:39.228768
6709 12:18:39.231220 [CBTSetCACLKResult] CA Dly = 36
6710 12:18:39.231810 CS Dly: 1 (0~32)
6711 12:18:39.232191
6712 12:18:39.234306 ----->DramcWriteLeveling(PI) begin...
6713 12:18:39.234838 ==
6714 12:18:39.237508 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 12:18:39.244226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 12:18:39.244800 ==
6717 12:18:39.247664 Write leveling (Byte 0): 40 => 8
6718 12:18:39.248247 Write leveling (Byte 1): 32 => 0
6719 12:18:39.250792 DramcWriteLeveling(PI) end<-----
6720 12:18:39.251263
6721 12:18:39.251637 ==
6722 12:18:39.253839 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 12:18:39.260758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 12:18:39.261494 ==
6725 12:18:39.264142 [Gating] SW mode calibration
6726 12:18:39.271044 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6727 12:18:39.273773 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6728 12:18:39.280691 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6729 12:18:39.283755 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6730 12:18:39.286912 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6731 12:18:39.293977 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6732 12:18:39.297279 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6733 12:18:39.300443 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6734 12:18:39.306911 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6735 12:18:39.310401 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6736 12:18:39.314127 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6737 12:18:39.317249 Total UI for P1: 0, mck2ui 16
6738 12:18:39.320226 best dqsien dly found for B0: ( 0, 14, 24)
6739 12:18:39.323553 Total UI for P1: 0, mck2ui 16
6740 12:18:39.327154 best dqsien dly found for B1: ( 0, 14, 24)
6741 12:18:39.330609 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6742 12:18:39.333662 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6743 12:18:39.334278
6744 12:18:39.336857 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6745 12:18:39.344057 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6746 12:18:39.344634 [Gating] SW calibration Done
6747 12:18:39.346801 ==
6748 12:18:39.347274 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 12:18:39.353674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 12:18:39.354179 ==
6751 12:18:39.354557 RX Vref Scan: 0
6752 12:18:39.354904
6753 12:18:39.356980 RX Vref 0 -> 0, step: 1
6754 12:18:39.357446
6755 12:18:39.360201 RX Delay -410 -> 252, step: 16
6756 12:18:39.363661 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6757 12:18:39.366782 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6758 12:18:39.373759 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6759 12:18:39.377065 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6760 12:18:39.380319 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6761 12:18:39.383882 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6762 12:18:39.390539 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6763 12:18:39.393818 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6764 12:18:39.396792 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6765 12:18:39.400147 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6766 12:18:39.406850 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6767 12:18:39.410128 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6768 12:18:39.413420 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6769 12:18:39.416827 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6770 12:18:39.423779 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6771 12:18:39.427081 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6772 12:18:39.427657 ==
6773 12:18:39.430237 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 12:18:39.434140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 12:18:39.434720 ==
6776 12:18:39.436779 DQS Delay:
6777 12:18:39.437245 DQS0 = 27, DQS1 = 43
6778 12:18:39.439955 DQM Delay:
6779 12:18:39.440425 DQM0 = 9, DQM1 = 17
6780 12:18:39.440800 DQ Delay:
6781 12:18:39.443389 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6782 12:18:39.446795 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6783 12:18:39.450043 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6784 12:18:39.453459 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6785 12:18:39.454076
6786 12:18:39.454459
6787 12:18:39.454807 ==
6788 12:18:39.456975 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 12:18:39.463570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 12:18:39.464151 ==
6791 12:18:39.464534
6792 12:18:39.464882
6793 12:18:39.465216 TX Vref Scan disable
6794 12:18:39.466425 == TX Byte 0 ==
6795 12:18:39.469692 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6796 12:18:39.473404 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6797 12:18:39.476760 == TX Byte 1 ==
6798 12:18:39.480191 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6799 12:18:39.483034 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6800 12:18:39.483508 ==
6801 12:18:39.486529 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 12:18:39.493432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 12:18:39.494037 ==
6804 12:18:39.494423
6805 12:18:39.494771
6806 12:18:39.495102 TX Vref Scan disable
6807 12:18:39.496346 == TX Byte 0 ==
6808 12:18:39.499897 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6809 12:18:39.503372 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6810 12:18:39.506786 == TX Byte 1 ==
6811 12:18:39.510062 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6812 12:18:39.512942 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6813 12:18:39.513416
6814 12:18:39.516559 [DATLAT]
6815 12:18:39.517136 Freq=400, CH1 RK0
6816 12:18:39.517607
6817 12:18:39.520140 DATLAT Default: 0xf
6818 12:18:39.520713 0, 0xFFFF, sum = 0
6819 12:18:39.522759 1, 0xFFFF, sum = 0
6820 12:18:39.523236 2, 0xFFFF, sum = 0
6821 12:18:39.527171 3, 0xFFFF, sum = 0
6822 12:18:39.527750 4, 0xFFFF, sum = 0
6823 12:18:39.529902 5, 0xFFFF, sum = 0
6824 12:18:39.530515 6, 0xFFFF, sum = 0
6825 12:18:39.533306 7, 0xFFFF, sum = 0
6826 12:18:39.533886 8, 0xFFFF, sum = 0
6827 12:18:39.536311 9, 0xFFFF, sum = 0
6828 12:18:39.539737 10, 0xFFFF, sum = 0
6829 12:18:39.540307 11, 0xFFFF, sum = 0
6830 12:18:39.542937 12, 0xFFFF, sum = 0
6831 12:18:39.543506 13, 0x0, sum = 1
6832 12:18:39.546313 14, 0x0, sum = 2
6833 12:18:39.546895 15, 0x0, sum = 3
6834 12:18:39.549606 16, 0x0, sum = 4
6835 12:18:39.550113 best_step = 14
6836 12:18:39.550588
6837 12:18:39.551104 ==
6838 12:18:39.552796 Dram Type= 6, Freq= 0, CH_1, rank 0
6839 12:18:39.556045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6840 12:18:39.556555 ==
6841 12:18:39.559311 RX Vref Scan: 1
6842 12:18:39.559774
6843 12:18:39.562846 RX Vref 0 -> 0, step: 1
6844 12:18:39.563313
6845 12:18:39.563683 RX Delay -327 -> 252, step: 8
6846 12:18:39.564025
6847 12:18:39.566095 Set Vref, RX VrefLevel [Byte0]: 53
6848 12:18:39.569566 [Byte1]: 53
6849 12:18:39.574981
6850 12:18:39.575442 Final RX Vref Byte 0 = 53 to rank0
6851 12:18:39.578149 Final RX Vref Byte 1 = 53 to rank0
6852 12:18:39.581440 Final RX Vref Byte 0 = 53 to rank1
6853 12:18:39.585001 Final RX Vref Byte 1 = 53 to rank1==
6854 12:18:39.588332 Dram Type= 6, Freq= 0, CH_1, rank 0
6855 12:18:39.594806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 12:18:39.595371 ==
6857 12:18:39.595743 DQS Delay:
6858 12:18:39.597932 DQS0 = 32, DQS1 = 40
6859 12:18:39.598444 DQM Delay:
6860 12:18:39.598865 DQM0 = 11, DQM1 = 12
6861 12:18:39.601615 DQ Delay:
6862 12:18:39.605259 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6863 12:18:39.605815 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =8
6864 12:18:39.608047 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6865 12:18:39.611705 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6866 12:18:39.612263
6867 12:18:39.614427
6868 12:18:39.621324 [DQSOSCAuto] RK0, (LSB)MR18= 0x97d3, (MSB)MR19= 0xc0c, tDQSOscB0 = 383 ps tDQSOscB1 = 390 ps
6869 12:18:39.624675 CH1 RK0: MR19=C0C, MR18=97D3
6870 12:18:39.631517 CH1_RK0: MR19=0xC0C, MR18=0x97D3, DQSOSC=383, MR23=63, INC=402, DEC=268
6871 12:18:39.632142 ==
6872 12:18:39.634644 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 12:18:39.638112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 12:18:39.638581 ==
6875 12:18:39.641198 [Gating] SW mode calibration
6876 12:18:39.648085 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6877 12:18:39.654658 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6878 12:18:39.658091 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6879 12:18:39.661314 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6880 12:18:39.664611 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6881 12:18:39.671306 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6882 12:18:39.674422 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6883 12:18:39.677588 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6884 12:18:39.684685 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6885 12:18:39.687604 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6886 12:18:39.691263 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6887 12:18:39.694380 Total UI for P1: 0, mck2ui 16
6888 12:18:39.697876 best dqsien dly found for B0: ( 0, 14, 24)
6889 12:18:39.700976 Total UI for P1: 0, mck2ui 16
6890 12:18:39.704487 best dqsien dly found for B1: ( 0, 14, 24)
6891 12:18:39.707946 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6892 12:18:39.710930 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6893 12:18:39.715010
6894 12:18:39.717849 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6895 12:18:39.721788 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6896 12:18:39.724813 [Gating] SW calibration Done
6897 12:18:39.725278 ==
6898 12:18:39.727575 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 12:18:39.731298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 12:18:39.731870 ==
6901 12:18:39.732247 RX Vref Scan: 0
6902 12:18:39.732590
6903 12:18:39.734302 RX Vref 0 -> 0, step: 1
6904 12:18:39.734769
6905 12:18:39.737425 RX Delay -410 -> 252, step: 16
6906 12:18:39.740780 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6907 12:18:39.747558 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6908 12:18:39.750856 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6909 12:18:39.754449 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6910 12:18:39.757570 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6911 12:18:39.764167 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6912 12:18:39.767253 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6913 12:18:39.770796 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6914 12:18:39.774001 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6915 12:18:39.780986 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6916 12:18:39.784167 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6917 12:18:39.787208 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6918 12:18:39.790465 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6919 12:18:39.797337 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6920 12:18:39.800781 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6921 12:18:39.804089 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6922 12:18:39.804649 ==
6923 12:18:39.806998 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 12:18:39.810628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 12:18:39.814220 ==
6926 12:18:39.814785 DQS Delay:
6927 12:18:39.815159 DQS0 = 35, DQS1 = 43
6928 12:18:39.817194 DQM Delay:
6929 12:18:39.817764 DQM0 = 18, DQM1 = 18
6930 12:18:39.820676 DQ Delay:
6931 12:18:39.824162 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6932 12:18:39.824647 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6933 12:18:39.827668 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6934 12:18:39.830503 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6935 12:18:39.830975
6936 12:18:39.834237
6937 12:18:39.834794 ==
6938 12:18:39.836973 Dram Type= 6, Freq= 0, CH_1, rank 1
6939 12:18:39.840933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6940 12:18:39.841507 ==
6941 12:18:39.841887
6942 12:18:39.842272
6943 12:18:39.843935 TX Vref Scan disable
6944 12:18:39.844503 == TX Byte 0 ==
6945 12:18:39.847520 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6946 12:18:39.853905 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6947 12:18:39.854527 == TX Byte 1 ==
6948 12:18:39.857465 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6949 12:18:39.863722 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6950 12:18:39.864279 ==
6951 12:18:39.867152 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 12:18:39.870307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 12:18:39.870781 ==
6954 12:18:39.871150
6955 12:18:39.871495
6956 12:18:39.873490 TX Vref Scan disable
6957 12:18:39.873983 == TX Byte 0 ==
6958 12:18:39.877686 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6959 12:18:39.883831 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6960 12:18:39.884397 == TX Byte 1 ==
6961 12:18:39.886923 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6962 12:18:39.893725 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6963 12:18:39.894343
6964 12:18:39.894826 [DATLAT]
6965 12:18:39.895277 Freq=400, CH1 RK1
6966 12:18:39.895720
6967 12:18:39.896803 DATLAT Default: 0xe
6968 12:18:39.900241 0, 0xFFFF, sum = 0
6969 12:18:39.900867 1, 0xFFFF, sum = 0
6970 12:18:39.903627 2, 0xFFFF, sum = 0
6971 12:18:39.904106 3, 0xFFFF, sum = 0
6972 12:18:39.906791 4, 0xFFFF, sum = 0
6973 12:18:39.907271 5, 0xFFFF, sum = 0
6974 12:18:39.910220 6, 0xFFFF, sum = 0
6975 12:18:39.910698 7, 0xFFFF, sum = 0
6976 12:18:39.913406 8, 0xFFFF, sum = 0
6977 12:18:39.913882 9, 0xFFFF, sum = 0
6978 12:18:39.916718 10, 0xFFFF, sum = 0
6979 12:18:39.917194 11, 0xFFFF, sum = 0
6980 12:18:39.920052 12, 0xFFFF, sum = 0
6981 12:18:39.920529 13, 0x0, sum = 1
6982 12:18:39.923299 14, 0x0, sum = 2
6983 12:18:39.923775 15, 0x0, sum = 3
6984 12:18:39.926836 16, 0x0, sum = 4
6985 12:18:39.927377 best_step = 14
6986 12:18:39.927754
6987 12:18:39.928100 ==
6988 12:18:39.930335 Dram Type= 6, Freq= 0, CH_1, rank 1
6989 12:18:39.937121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6990 12:18:39.937704 ==
6991 12:18:39.938214 RX Vref Scan: 0
6992 12:18:39.938807
6993 12:18:39.940172 RX Vref 0 -> 0, step: 1
6994 12:18:39.940641
6995 12:18:39.943316 RX Delay -327 -> 252, step: 8
6996 12:18:39.950340 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6997 12:18:39.953527 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6998 12:18:39.956876 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6999 12:18:39.960484 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
7000 12:18:39.964013 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7001 12:18:39.970112 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
7002 12:18:39.973457 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
7003 12:18:39.976633 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
7004 12:18:39.980495 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7005 12:18:39.986578 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
7006 12:18:39.989816 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7007 12:18:39.993709 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
7008 12:18:39.996865 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7009 12:18:40.003642 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7010 12:18:40.006608 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7011 12:18:40.010270 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
7012 12:18:40.010844 ==
7013 12:18:40.013704 Dram Type= 6, Freq= 0, CH_1, rank 1
7014 12:18:40.020364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7015 12:18:40.020963 ==
7016 12:18:40.021343 DQS Delay:
7017 12:18:40.023627 DQS0 = 32, DQS1 = 36
7018 12:18:40.024204 DQM Delay:
7019 12:18:40.024583 DQM0 = 13, DQM1 = 10
7020 12:18:40.026985 DQ Delay:
7021 12:18:40.030581 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =16
7022 12:18:40.033924 DQ4 =16, DQ5 =20, DQ6 =16, DQ7 =8
7023 12:18:40.034537 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7024 12:18:40.036538 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
7025 12:18:40.039679
7026 12:18:40.040145
7027 12:18:40.046910 [DQSOSCAuto] RK1, (LSB)MR18= 0xa44e, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 389 ps
7028 12:18:40.050386 CH1 RK1: MR19=C0C, MR18=A44E
7029 12:18:40.056807 CH1_RK1: MR19=0xC0C, MR18=0xA44E, DQSOSC=389, MR23=63, INC=390, DEC=260
7030 12:18:40.059941 [RxdqsGatingPostProcess] freq 400
7031 12:18:40.062682 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7032 12:18:40.066641 best DQS0 dly(2T, 0.5T) = (0, 10)
7033 12:18:40.070013 best DQS1 dly(2T, 0.5T) = (0, 10)
7034 12:18:40.073044 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7035 12:18:40.076465 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7036 12:18:40.079891 best DQS0 dly(2T, 0.5T) = (0, 10)
7037 12:18:40.082823 best DQS1 dly(2T, 0.5T) = (0, 10)
7038 12:18:40.086781 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7039 12:18:40.089743 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7040 12:18:40.093123 Pre-setting of DQS Precalculation
7041 12:18:40.096009 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7042 12:18:40.106795 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7043 12:18:40.113067 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7044 12:18:40.113643
7045 12:18:40.114057
7046 12:18:40.116139 [Calibration Summary] 800 Mbps
7047 12:18:40.116607 CH 0, Rank 0
7048 12:18:40.119496 SW Impedance : PASS
7049 12:18:40.119967 DUTY Scan : NO K
7050 12:18:40.122796 ZQ Calibration : PASS
7051 12:18:40.126189 Jitter Meter : NO K
7052 12:18:40.126759 CBT Training : PASS
7053 12:18:40.129631 Write leveling : PASS
7054 12:18:40.132762 RX DQS gating : PASS
7055 12:18:40.133338 RX DQ/DQS(RDDQC) : PASS
7056 12:18:40.135871 TX DQ/DQS : PASS
7057 12:18:40.136342 RX DATLAT : PASS
7058 12:18:40.139441 RX DQ/DQS(Engine): PASS
7059 12:18:40.142496 TX OE : NO K
7060 12:18:40.142965 All Pass.
7061 12:18:40.143339
7062 12:18:40.143687 CH 0, Rank 1
7063 12:18:40.145882 SW Impedance : PASS
7064 12:18:40.149404 DUTY Scan : NO K
7065 12:18:40.150020 ZQ Calibration : PASS
7066 12:18:40.152919 Jitter Meter : NO K
7067 12:18:40.156195 CBT Training : PASS
7068 12:18:40.156773 Write leveling : NO K
7069 12:18:40.159534 RX DQS gating : PASS
7070 12:18:40.162702 RX DQ/DQS(RDDQC) : PASS
7071 12:18:40.163277 TX DQ/DQS : PASS
7072 12:18:40.166189 RX DATLAT : PASS
7073 12:18:40.169717 RX DQ/DQS(Engine): PASS
7074 12:18:40.170331 TX OE : NO K
7075 12:18:40.170719 All Pass.
7076 12:18:40.172928
7077 12:18:40.173501 CH 1, Rank 0
7078 12:18:40.176156 SW Impedance : PASS
7079 12:18:40.176735 DUTY Scan : NO K
7080 12:18:40.179827 ZQ Calibration : PASS
7081 12:18:40.182520 Jitter Meter : NO K
7082 12:18:40.182989 CBT Training : PASS
7083 12:18:40.186115 Write leveling : PASS
7084 12:18:40.186686 RX DQS gating : PASS
7085 12:18:40.189321 RX DQ/DQS(RDDQC) : PASS
7086 12:18:40.193007 TX DQ/DQS : PASS
7087 12:18:40.193594 RX DATLAT : PASS
7088 12:18:40.196451 RX DQ/DQS(Engine): PASS
7089 12:18:40.199724 TX OE : NO K
7090 12:18:40.200300 All Pass.
7091 12:18:40.200678
7092 12:18:40.201024 CH 1, Rank 1
7093 12:18:40.202736 SW Impedance : PASS
7094 12:18:40.206565 DUTY Scan : NO K
7095 12:18:40.207148 ZQ Calibration : PASS
7096 12:18:40.209309 Jitter Meter : NO K
7097 12:18:40.212641 CBT Training : PASS
7098 12:18:40.213235 Write leveling : NO K
7099 12:18:40.216150 RX DQS gating : PASS
7100 12:18:40.219125 RX DQ/DQS(RDDQC) : PASS
7101 12:18:40.219601 TX DQ/DQS : PASS
7102 12:18:40.222812 RX DATLAT : PASS
7103 12:18:40.223382 RX DQ/DQS(Engine): PASS
7104 12:18:40.226109 TX OE : NO K
7105 12:18:40.226585 All Pass.
7106 12:18:40.226960
7107 12:18:40.229646 DramC Write-DBI off
7108 12:18:40.232684 PER_BANK_REFRESH: Hybrid Mode
7109 12:18:40.233258 TX_TRACKING: ON
7110 12:18:40.242483 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7111 12:18:40.246166 [FAST_K] Save calibration result to emmc
7112 12:18:40.249352 dramc_set_vcore_voltage set vcore to 725000
7113 12:18:40.252778 Read voltage for 1600, 0
7114 12:18:40.253357 Vio18 = 0
7115 12:18:40.255853 Vcore = 725000
7116 12:18:40.256426 Vdram = 0
7117 12:18:40.256801 Vddq = 0
7118 12:18:40.257151 Vmddr = 0
7119 12:18:40.262804 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7120 12:18:40.269184 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7121 12:18:40.269763 MEM_TYPE=3, freq_sel=13
7122 12:18:40.272497 sv_algorithm_assistance_LP4_3733
7123 12:18:40.275960 ============ PULL DRAM RESETB DOWN ============
7124 12:18:40.282659 ========== PULL DRAM RESETB DOWN end =========
7125 12:18:40.285829 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7126 12:18:40.289086 ===================================
7127 12:18:40.292511 LPDDR4 DRAM CONFIGURATION
7128 12:18:40.295789 ===================================
7129 12:18:40.296366 EX_ROW_EN[0] = 0x0
7130 12:18:40.299038 EX_ROW_EN[1] = 0x0
7131 12:18:40.299510 LP4Y_EN = 0x0
7132 12:18:40.302334 WORK_FSP = 0x1
7133 12:18:40.302802 WL = 0x5
7134 12:18:40.305538 RL = 0x5
7135 12:18:40.306036 BL = 0x2
7136 12:18:40.308996 RPST = 0x0
7137 12:18:40.312208 RD_PRE = 0x0
7138 12:18:40.312676 WR_PRE = 0x1
7139 12:18:40.315455 WR_PST = 0x1
7140 12:18:40.315969 DBI_WR = 0x0
7141 12:18:40.318822 DBI_RD = 0x0
7142 12:18:40.319326 OTF = 0x1
7143 12:18:40.322113 ===================================
7144 12:18:40.325672 ===================================
7145 12:18:40.328775 ANA top config
7146 12:18:40.331889 ===================================
7147 12:18:40.332364 DLL_ASYNC_EN = 0
7148 12:18:40.335595 ALL_SLAVE_EN = 0
7149 12:18:40.338899 NEW_RANK_MODE = 1
7150 12:18:40.341932 DLL_IDLE_MODE = 1
7151 12:18:40.342432 LP45_APHY_COMB_EN = 1
7152 12:18:40.345473 TX_ODT_DIS = 0
7153 12:18:40.348892 NEW_8X_MODE = 1
7154 12:18:40.352229 ===================================
7155 12:18:40.355216 ===================================
7156 12:18:40.359051 data_rate = 3200
7157 12:18:40.361898 CKR = 1
7158 12:18:40.365575 DQ_P2S_RATIO = 8
7159 12:18:40.366180 ===================================
7160 12:18:40.369059 CA_P2S_RATIO = 8
7161 12:18:40.371808 DQ_CA_OPEN = 0
7162 12:18:40.375479 DQ_SEMI_OPEN = 0
7163 12:18:40.378860 CA_SEMI_OPEN = 0
7164 12:18:40.382047 CA_FULL_RATE = 0
7165 12:18:40.382616 DQ_CKDIV4_EN = 0
7166 12:18:40.385422 CA_CKDIV4_EN = 0
7167 12:18:40.388728 CA_PREDIV_EN = 0
7168 12:18:40.391981 PH8_DLY = 12
7169 12:18:40.395309 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7170 12:18:40.398949 DQ_AAMCK_DIV = 4
7171 12:18:40.399520 CA_AAMCK_DIV = 4
7172 12:18:40.402137 CA_ADMCK_DIV = 4
7173 12:18:40.405203 DQ_TRACK_CA_EN = 0
7174 12:18:40.408527 CA_PICK = 1600
7175 12:18:40.411463 CA_MCKIO = 1600
7176 12:18:40.415300 MCKIO_SEMI = 0
7177 12:18:40.418168 PLL_FREQ = 3068
7178 12:18:40.421926 DQ_UI_PI_RATIO = 32
7179 12:18:40.422534 CA_UI_PI_RATIO = 0
7180 12:18:40.425146 ===================================
7181 12:18:40.428189 ===================================
7182 12:18:40.431547 memory_type:LPDDR4
7183 12:18:40.434672 GP_NUM : 10
7184 12:18:40.435141 SRAM_EN : 1
7185 12:18:40.438620 MD32_EN : 0
7186 12:18:40.441471 ===================================
7187 12:18:40.445034 [ANA_INIT] >>>>>>>>>>>>>>
7188 12:18:40.448125 <<<<<< [CONFIGURE PHASE]: ANA_TX
7189 12:18:40.451612 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7190 12:18:40.455494 ===================================
7191 12:18:40.456054 data_rate = 3200,PCW = 0X7600
7192 12:18:40.458222 ===================================
7193 12:18:40.461808 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7194 12:18:40.468016 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7195 12:18:40.474987 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7196 12:18:40.478446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7197 12:18:40.482084 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7198 12:18:40.485128 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7199 12:18:40.488611 [ANA_INIT] flow start
7200 12:18:40.489164 [ANA_INIT] PLL >>>>>>>>
7201 12:18:40.491495 [ANA_INIT] PLL <<<<<<<<
7202 12:18:40.494848 [ANA_INIT] MIDPI >>>>>>>>
7203 12:18:40.498401 [ANA_INIT] MIDPI <<<<<<<<
7204 12:18:40.498965 [ANA_INIT] DLL >>>>>>>>
7205 12:18:40.501756 [ANA_INIT] DLL <<<<<<<<
7206 12:18:40.504817 [ANA_INIT] flow end
7207 12:18:40.508166 ============ LP4 DIFF to SE enter ============
7208 12:18:40.511071 ============ LP4 DIFF to SE exit ============
7209 12:18:40.514900 [ANA_INIT] <<<<<<<<<<<<<
7210 12:18:40.518289 [Flow] Enable top DCM control >>>>>
7211 12:18:40.521374 [Flow] Enable top DCM control <<<<<
7212 12:18:40.524589 Enable DLL master slave shuffle
7213 12:18:40.527817 ==============================================================
7214 12:18:40.531269 Gating Mode config
7215 12:18:40.534501 ==============================================================
7216 12:18:40.538138 Config description:
7217 12:18:40.547996 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7218 12:18:40.554403 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7219 12:18:40.557643 SELPH_MODE 0: By rank 1: By Phase
7220 12:18:40.564877 ==============================================================
7221 12:18:40.567478 GAT_TRACK_EN = 1
7222 12:18:40.571935 RX_GATING_MODE = 2
7223 12:18:40.574534 RX_GATING_TRACK_MODE = 2
7224 12:18:40.577766 SELPH_MODE = 1
7225 12:18:40.581177 PICG_EARLY_EN = 1
7226 12:18:40.581741 VALID_LAT_VALUE = 1
7227 12:18:40.587633 ==============================================================
7228 12:18:40.591288 Enter into Gating configuration >>>>
7229 12:18:40.594598 Exit from Gating configuration <<<<
7230 12:18:40.598047 Enter into DVFS_PRE_config >>>>>
7231 12:18:40.607699 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7232 12:18:40.610962 Exit from DVFS_PRE_config <<<<<
7233 12:18:40.614517 Enter into PICG configuration >>>>
7234 12:18:40.617301 Exit from PICG configuration <<<<
7235 12:18:40.620987 [RX_INPUT] configuration >>>>>
7236 12:18:40.624137 [RX_INPUT] configuration <<<<<
7237 12:18:40.630788 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7238 12:18:40.634112 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7239 12:18:40.641025 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7240 12:18:40.647263 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7241 12:18:40.653654 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7242 12:18:40.660474 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7243 12:18:40.663932 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7244 12:18:40.667114 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7245 12:18:40.670788 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7246 12:18:40.676976 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7247 12:18:40.680443 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7248 12:18:40.683771 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7249 12:18:40.687392 ===================================
7250 12:18:40.689961 LPDDR4 DRAM CONFIGURATION
7251 12:18:40.693853 ===================================
7252 12:18:40.694464 EX_ROW_EN[0] = 0x0
7253 12:18:40.696894 EX_ROW_EN[1] = 0x0
7254 12:18:40.700551 LP4Y_EN = 0x0
7255 12:18:40.701123 WORK_FSP = 0x1
7256 12:18:40.703817 WL = 0x5
7257 12:18:40.704388 RL = 0x5
7258 12:18:40.707177 BL = 0x2
7259 12:18:40.707748 RPST = 0x0
7260 12:18:40.710385 RD_PRE = 0x0
7261 12:18:40.710955 WR_PRE = 0x1
7262 12:18:40.713693 WR_PST = 0x1
7263 12:18:40.714311 DBI_WR = 0x0
7264 12:18:40.716710 DBI_RD = 0x0
7265 12:18:40.717310 OTF = 0x1
7266 12:18:40.720032 ===================================
7267 12:18:40.723446 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7268 12:18:40.729974 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7269 12:18:40.733379 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7270 12:18:40.737129 ===================================
7271 12:18:40.740039 LPDDR4 DRAM CONFIGURATION
7272 12:18:40.743297 ===================================
7273 12:18:40.743767 EX_ROW_EN[0] = 0x10
7274 12:18:40.746500 EX_ROW_EN[1] = 0x0
7275 12:18:40.746969 LP4Y_EN = 0x0
7276 12:18:40.750210 WORK_FSP = 0x1
7277 12:18:40.753369 WL = 0x5
7278 12:18:40.753986 RL = 0x5
7279 12:18:40.756603 BL = 0x2
7280 12:18:40.757070 RPST = 0x0
7281 12:18:40.759948 RD_PRE = 0x0
7282 12:18:40.760487 WR_PRE = 0x1
7283 12:18:40.762936 WR_PST = 0x1
7284 12:18:40.763409 DBI_WR = 0x0
7285 12:18:40.766684 DBI_RD = 0x0
7286 12:18:40.767154 OTF = 0x1
7287 12:18:40.769920 ===================================
7288 12:18:40.776572 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7289 12:18:40.777171 ==
7290 12:18:40.779663 Dram Type= 6, Freq= 0, CH_0, rank 0
7291 12:18:40.783066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7292 12:18:40.783644 ==
7293 12:18:40.786556 [Duty_Offset_Calibration]
7294 12:18:40.789543 B0:2 B1:0 CA:1
7295 12:18:40.790149
7296 12:18:40.793132 [DutyScan_Calibration_Flow] k_type=0
7297 12:18:40.801133
7298 12:18:40.801702 ==CLK 0==
7299 12:18:40.804185 Final CLK duty delay cell = -4
7300 12:18:40.807680 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7301 12:18:40.810793 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7302 12:18:40.814083 [-4] AVG Duty = 4937%(X100)
7303 12:18:40.814654
7304 12:18:40.817367 CH0 CLK Duty spec in!! Max-Min= 187%
7305 12:18:40.820674 [DutyScan_Calibration_Flow] ====Done====
7306 12:18:40.821136
7307 12:18:40.824181 [DutyScan_Calibration_Flow] k_type=1
7308 12:18:40.840743
7309 12:18:40.841302 ==DQS 0 ==
7310 12:18:40.843265 Final DQS duty delay cell = 0
7311 12:18:40.846604 [0] MAX Duty = 5218%(X100), DQS PI = 32
7312 12:18:40.850135 [0] MIN Duty = 4938%(X100), DQS PI = 60
7313 12:18:40.853454 [0] AVG Duty = 5078%(X100)
7314 12:18:40.854227
7315 12:18:40.854613 ==DQS 1 ==
7316 12:18:40.856737 Final DQS duty delay cell = -4
7317 12:18:40.860281 [-4] MAX Duty = 5125%(X100), DQS PI = 46
7318 12:18:40.863534 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7319 12:18:40.867007 [-4] AVG Duty = 5000%(X100)
7320 12:18:40.867477
7321 12:18:40.870153 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7322 12:18:40.870623
7323 12:18:40.873711 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7324 12:18:40.876982 [DutyScan_Calibration_Flow] ====Done====
7325 12:18:40.877558
7326 12:18:40.879851 [DutyScan_Calibration_Flow] k_type=3
7327 12:18:40.898397
7328 12:18:40.898970 ==DQM 0 ==
7329 12:18:40.901435 Final DQM duty delay cell = 0
7330 12:18:40.904671 [0] MAX Duty = 5093%(X100), DQS PI = 26
7331 12:18:40.908041 [0] MIN Duty = 4813%(X100), DQS PI = 50
7332 12:18:40.911098 [0] AVG Duty = 4953%(X100)
7333 12:18:40.911740
7334 12:18:40.912126 ==DQM 1 ==
7335 12:18:40.914351 Final DQM duty delay cell = 0
7336 12:18:40.918133 [0] MAX Duty = 5249%(X100), DQS PI = 30
7337 12:18:40.921055 [0] MIN Duty = 5000%(X100), DQS PI = 20
7338 12:18:40.921525 [0] AVG Duty = 5124%(X100)
7339 12:18:40.924214
7340 12:18:40.927460 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7341 12:18:40.927932
7342 12:18:40.930964 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7343 12:18:40.934056 [DutyScan_Calibration_Flow] ====Done====
7344 12:18:40.934530
7345 12:18:40.937422 [DutyScan_Calibration_Flow] k_type=2
7346 12:18:40.954607
7347 12:18:40.955076 ==DQ 0 ==
7348 12:18:40.958050 Final DQ duty delay cell = 0
7349 12:18:40.961615 [0] MAX Duty = 5124%(X100), DQS PI = 32
7350 12:18:40.964687 [0] MIN Duty = 5000%(X100), DQS PI = 16
7351 12:18:40.965158 [0] AVG Duty = 5062%(X100)
7352 12:18:40.968682
7353 12:18:40.969317 ==DQ 1 ==
7354 12:18:40.971670 Final DQ duty delay cell = 0
7355 12:18:40.974741 [0] MAX Duty = 4969%(X100), DQS PI = 44
7356 12:18:40.978127 [0] MIN Duty = 4875%(X100), DQS PI = 12
7357 12:18:40.978708 [0] AVG Duty = 4922%(X100)
7358 12:18:40.981403
7359 12:18:40.984457 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7360 12:18:40.984916
7361 12:18:40.987918 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7362 12:18:40.991238 [DutyScan_Calibration_Flow] ====Done====
7363 12:18:40.991698 ==
7364 12:18:40.994701 Dram Type= 6, Freq= 0, CH_1, rank 0
7365 12:18:40.997867 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7366 12:18:40.998310 ==
7367 12:18:41.001445 [Duty_Offset_Calibration]
7368 12:18:41.001861 B0:0 B1:-1 CA:2
7369 12:18:41.002222
7370 12:18:41.004199 [DutyScan_Calibration_Flow] k_type=0
7371 12:18:41.014972
7372 12:18:41.015488 ==CLK 0==
7373 12:18:41.018432 Final CLK duty delay cell = 0
7374 12:18:41.021736 [0] MAX Duty = 5156%(X100), DQS PI = 10
7375 12:18:41.025181 [0] MIN Duty = 4938%(X100), DQS PI = 44
7376 12:18:41.025701 [0] AVG Duty = 5047%(X100)
7377 12:18:41.028639
7378 12:18:41.031779 CH1 CLK Duty spec in!! Max-Min= 218%
7379 12:18:41.034903 [DutyScan_Calibration_Flow] ====Done====
7380 12:18:41.035361
7381 12:18:41.038425 [DutyScan_Calibration_Flow] k_type=1
7382 12:18:41.055066
7383 12:18:41.055628 ==DQS 0 ==
7384 12:18:41.058323 Final DQS duty delay cell = 0
7385 12:18:41.061380 [0] MAX Duty = 5124%(X100), DQS PI = 28
7386 12:18:41.065393 [0] MIN Duty = 5000%(X100), DQS PI = 0
7387 12:18:41.067974 [0] AVG Duty = 5062%(X100)
7388 12:18:41.068436
7389 12:18:41.068804 ==DQS 1 ==
7390 12:18:41.071883 Final DQS duty delay cell = 0
7391 12:18:41.074381 [0] MAX Duty = 5187%(X100), DQS PI = 0
7392 12:18:41.077973 [0] MIN Duty = 4844%(X100), DQS PI = 32
7393 12:18:41.081372 [0] AVG Duty = 5015%(X100)
7394 12:18:41.081935
7395 12:18:41.084418 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7396 12:18:41.084875
7397 12:18:41.087845 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7398 12:18:41.091339 [DutyScan_Calibration_Flow] ====Done====
7399 12:18:41.091901
7400 12:18:41.094468 [DutyScan_Calibration_Flow] k_type=3
7401 12:18:41.112534
7402 12:18:41.113095 ==DQM 0 ==
7403 12:18:41.115980 Final DQM duty delay cell = 4
7404 12:18:41.118995 [4] MAX Duty = 5125%(X100), DQS PI = 22
7405 12:18:41.122681 [4] MIN Duty = 5000%(X100), DQS PI = 30
7406 12:18:41.123251 [4] AVG Duty = 5062%(X100)
7407 12:18:41.126063
7408 12:18:41.126620 ==DQM 1 ==
7409 12:18:41.128970 Final DQM duty delay cell = 0
7410 12:18:41.132547 [0] MAX Duty = 5281%(X100), DQS PI = 58
7411 12:18:41.135688 [0] MIN Duty = 4876%(X100), DQS PI = 34
7412 12:18:41.138875 [0] AVG Duty = 5078%(X100)
7413 12:18:41.139441
7414 12:18:41.142188 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7415 12:18:41.142772
7416 12:18:41.145602 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7417 12:18:41.149013 [DutyScan_Calibration_Flow] ====Done====
7418 12:18:41.149565
7419 12:18:41.151926 [DutyScan_Calibration_Flow] k_type=2
7420 12:18:41.169370
7421 12:18:41.170044 ==DQ 0 ==
7422 12:18:41.172540 Final DQ duty delay cell = 0
7423 12:18:41.175850 [0] MAX Duty = 5093%(X100), DQS PI = 18
7424 12:18:41.179481 [0] MIN Duty = 4969%(X100), DQS PI = 46
7425 12:18:41.180055 [0] AVG Duty = 5031%(X100)
7426 12:18:41.180415
7427 12:18:41.182474 ==DQ 1 ==
7428 12:18:41.185873 Final DQ duty delay cell = 0
7429 12:18:41.189581 [0] MAX Duty = 5062%(X100), DQS PI = 2
7430 12:18:41.192811 [0] MIN Duty = 4813%(X100), DQS PI = 34
7431 12:18:41.193271 [0] AVG Duty = 4937%(X100)
7432 12:18:41.193634
7433 12:18:41.196083 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7434 12:18:41.199369
7435 12:18:41.202783 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7436 12:18:41.206044 [DutyScan_Calibration_Flow] ====Done====
7437 12:18:41.209628 nWR fixed to 30
7438 12:18:41.210218 [ModeRegInit_LP4] CH0 RK0
7439 12:18:41.212628 [ModeRegInit_LP4] CH0 RK1
7440 12:18:41.215775 [ModeRegInit_LP4] CH1 RK0
7441 12:18:41.216329 [ModeRegInit_LP4] CH1 RK1
7442 12:18:41.219010 match AC timing 5
7443 12:18:41.222629 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7444 12:18:41.229162 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7445 12:18:41.232580 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7446 12:18:41.239415 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7447 12:18:41.242350 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7448 12:18:41.242822 [MiockJmeterHQA]
7449 12:18:41.243193
7450 12:18:41.245759 [DramcMiockJmeter] u1RxGatingPI = 0
7451 12:18:41.249184 0 : 4257, 4029
7452 12:18:41.249756 4 : 4253, 4026
7453 12:18:41.250186 8 : 4253, 4027
7454 12:18:41.252385 12 : 4253, 4026
7455 12:18:41.252860 16 : 4253, 4027
7456 12:18:41.255734 20 : 4253, 4026
7457 12:18:41.256208 24 : 4252, 4027
7458 12:18:41.259382 28 : 4363, 4137
7459 12:18:41.259953 32 : 4363, 4137
7460 12:18:41.262280 36 : 4363, 4138
7461 12:18:41.262757 40 : 4252, 4027
7462 12:18:41.263133 44 : 4254, 4029
7463 12:18:41.265656 48 : 4255, 4029
7464 12:18:41.266149 52 : 4363, 4137
7465 12:18:41.269205 56 : 4363, 4138
7466 12:18:41.269778 60 : 4363, 4139
7467 12:18:41.273078 64 : 4253, 4029
7468 12:18:41.273648 68 : 4252, 4029
7469 12:18:41.274072 72 : 4253, 4029
7470 12:18:41.275519 76 : 4250, 4027
7471 12:18:41.275991 80 : 4360, 4137
7472 12:18:41.278853 84 : 4252, 4029
7473 12:18:41.279328 88 : 4250, 3804
7474 12:18:41.282361 92 : 4250, 0
7475 12:18:41.282934 96 : 4252, 0
7476 12:18:41.283314 100 : 4363, 0
7477 12:18:41.285780 104 : 4252, 0
7478 12:18:41.286384 108 : 4252, 0
7479 12:18:41.288954 112 : 4250, 0
7480 12:18:41.289425 116 : 4252, 0
7481 12:18:41.289803 120 : 4250, 0
7482 12:18:41.292446 124 : 4250, 0
7483 12:18:41.293027 128 : 4253, 0
7484 12:18:41.295707 132 : 4361, 0
7485 12:18:41.296184 136 : 4365, 0
7486 12:18:41.296561 140 : 4363, 0
7487 12:18:41.298986 144 : 4252, 0
7488 12:18:41.299555 148 : 4362, 0
7489 12:18:41.299932 152 : 4250, 0
7490 12:18:41.302176 156 : 4250, 0
7491 12:18:41.302651 160 : 4250, 0
7492 12:18:41.305225 164 : 4250, 0
7493 12:18:41.305700 168 : 4252, 0
7494 12:18:41.306114 172 : 4250, 0
7495 12:18:41.308654 176 : 4250, 0
7496 12:18:41.309128 180 : 4250, 0
7497 12:18:41.312473 184 : 4363, 0
7498 12:18:41.313071 188 : 4365, 0
7499 12:18:41.313512 192 : 4363, 0
7500 12:18:41.315450 196 : 4250, 0
7501 12:18:41.315925 200 : 4360, 1
7502 12:18:41.318502 204 : 4250, 2245
7503 12:18:41.318977 208 : 4360, 4137
7504 12:18:41.322330 212 : 4360, 4137
7505 12:18:41.322898 216 : 4250, 4027
7506 12:18:41.323279 220 : 4250, 4026
7507 12:18:41.325729 224 : 4252, 4029
7508 12:18:41.326344 228 : 4250, 4026
7509 12:18:41.328751 232 : 4250, 4026
7510 12:18:41.329220 236 : 4363, 4140
7511 12:18:41.332290 240 : 4249, 4027
7512 12:18:41.332859 244 : 4250, 4026
7513 12:18:41.335648 248 : 4250, 4026
7514 12:18:41.336214 252 : 4253, 4029
7515 12:18:41.338676 256 : 4249, 4027
7516 12:18:41.339244 260 : 4363, 4139
7517 12:18:41.342109 264 : 4360, 4137
7518 12:18:41.342674 268 : 4249, 4027
7519 12:18:41.345757 272 : 4250, 4026
7520 12:18:41.346405 276 : 4252, 4029
7521 12:18:41.346793 280 : 4250, 4027
7522 12:18:41.348615 284 : 4250, 4027
7523 12:18:41.349089 288 : 4362, 4140
7524 12:18:41.352108 292 : 4249, 4027
7525 12:18:41.352680 296 : 4250, 4027
7526 12:18:41.355106 300 : 4363, 4140
7527 12:18:41.355582 304 : 4249, 4027
7528 12:18:41.358438 308 : 4250, 4027
7529 12:18:41.358912 312 : 4363, 4119
7530 12:18:41.361716 316 : 4360, 2198
7531 12:18:41.362227 320 : 4250, 10
7532 12:18:41.362609
7533 12:18:41.365100 MIOCK jitter meter ch=0
7534 12:18:41.365565
7535 12:18:41.368792 1T = (320-92) = 228 dly cells
7536 12:18:41.371899 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7537 12:18:41.372467 ==
7538 12:18:41.375238 Dram Type= 6, Freq= 0, CH_0, rank 0
7539 12:18:41.381909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7540 12:18:41.382530 ==
7541 12:18:41.385087 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7542 12:18:41.391465 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7543 12:18:41.395296 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7544 12:18:41.401642 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7545 12:18:41.410107 [CA 0] Center 43 (13~73) winsize 61
7546 12:18:41.412904 [CA 1] Center 43 (13~73) winsize 61
7547 12:18:41.416388 [CA 2] Center 38 (8~68) winsize 61
7548 12:18:41.419682 [CA 3] Center 37 (8~67) winsize 60
7549 12:18:41.422829 [CA 4] Center 36 (6~66) winsize 61
7550 12:18:41.426352 [CA 5] Center 35 (5~65) winsize 61
7551 12:18:41.426917
7552 12:18:41.429453 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7553 12:18:41.430060
7554 12:18:41.433147 [CATrainingPosCal] consider 1 rank data
7555 12:18:41.436244 u2DelayCellTimex100 = 285/100 ps
7556 12:18:41.439537 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7557 12:18:41.446080 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7558 12:18:41.450326 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7559 12:18:41.452432 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7560 12:18:41.456131 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7561 12:18:41.459411 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7562 12:18:41.459975
7563 12:18:41.463027 CA PerBit enable=1, Macro0, CA PI delay=35
7564 12:18:41.463588
7565 12:18:41.466356 [CBTSetCACLKResult] CA Dly = 35
7566 12:18:41.469490 CS Dly: 9 (0~40)
7567 12:18:41.472987 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7568 12:18:41.476112 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7569 12:18:41.476676 ==
7570 12:18:41.479582 Dram Type= 6, Freq= 0, CH_0, rank 1
7571 12:18:41.482631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7572 12:18:41.486059 ==
7573 12:18:41.489281 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7574 12:18:41.492379 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7575 12:18:41.499057 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7576 12:18:41.505486 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7577 12:18:41.512825 [CA 0] Center 43 (13~73) winsize 61
7578 12:18:41.516443 [CA 1] Center 43 (13~73) winsize 61
7579 12:18:41.519612 [CA 2] Center 38 (8~68) winsize 61
7580 12:18:41.523110 [CA 3] Center 38 (8~68) winsize 61
7581 12:18:41.526619 [CA 4] Center 36 (6~66) winsize 61
7582 12:18:41.529672 [CA 5] Center 36 (6~66) winsize 61
7583 12:18:41.530265
7584 12:18:41.532952 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7585 12:18:41.533519
7586 12:18:41.536600 [CATrainingPosCal] consider 2 rank data
7587 12:18:41.539350 u2DelayCellTimex100 = 285/100 ps
7588 12:18:41.542972 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7589 12:18:41.550000 CA1 delay=43 (13~73),Diff = 8 PI (27 cell)
7590 12:18:41.553003 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7591 12:18:41.556450 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7592 12:18:41.560126 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7593 12:18:41.563016 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7594 12:18:41.563487
7595 12:18:41.566256 CA PerBit enable=1, Macro0, CA PI delay=35
7596 12:18:41.566822
7597 12:18:41.569776 [CBTSetCACLKResult] CA Dly = 35
7598 12:18:41.573066 CS Dly: 10 (0~43)
7599 12:18:41.576297 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7600 12:18:41.579557 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7601 12:18:41.580026
7602 12:18:41.582855 ----->DramcWriteLeveling(PI) begin...
7603 12:18:41.583426 ==
7604 12:18:41.586778 Dram Type= 6, Freq= 0, CH_0, rank 0
7605 12:18:41.589790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7606 12:18:41.593071 ==
7607 12:18:41.593631 Write leveling (Byte 0): 35 => 35
7608 12:18:41.596264 Write leveling (Byte 1): 32 => 32
7609 12:18:41.599369 DramcWriteLeveling(PI) end<-----
7610 12:18:41.599930
7611 12:18:41.600300 ==
7612 12:18:41.602850 Dram Type= 6, Freq= 0, CH_0, rank 0
7613 12:18:41.609304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7614 12:18:41.609860 ==
7615 12:18:41.610290 [Gating] SW mode calibration
7616 12:18:41.619070 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7617 12:18:41.622940 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7618 12:18:41.629152 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 12:18:41.633281 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 12:18:41.635901 1 4 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
7621 12:18:41.639273 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7622 12:18:41.645992 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7623 12:18:41.649047 1 4 20 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
7624 12:18:41.655308 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7625 12:18:41.659358 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7626 12:18:41.662004 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7627 12:18:41.665865 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7628 12:18:41.672857 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7629 12:18:41.675859 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7630 12:18:41.678967 1 5 16 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7631 12:18:41.685778 1 5 20 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
7632 12:18:41.689213 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 12:18:41.692489 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7634 12:18:41.699105 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7635 12:18:41.702115 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 12:18:41.705612 1 6 8 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
7637 12:18:41.711974 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7638 12:18:41.715322 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7639 12:18:41.718599 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7640 12:18:41.725672 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 12:18:41.728609 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 12:18:41.732161 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 12:18:41.738486 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 12:18:41.741986 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7645 12:18:41.745606 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7646 12:18:41.751812 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7647 12:18:41.755222 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7648 12:18:41.758478 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7649 12:18:41.765299 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 12:18:41.768437 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 12:18:41.771947 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 12:18:41.778532 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 12:18:41.781788 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 12:18:41.785294 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 12:18:41.792009 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 12:18:41.795472 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 12:18:41.798568 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 12:18:41.802193 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 12:18:41.808402 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 12:18:41.811840 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 12:18:41.814784 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7662 12:18:41.821899 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7663 12:18:41.824913 Total UI for P1: 0, mck2ui 16
7664 12:18:41.828313 best dqsien dly found for B0: ( 1, 9, 12)
7665 12:18:41.831759 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7666 12:18:41.835112 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7667 12:18:41.838484 Total UI for P1: 0, mck2ui 16
7668 12:18:41.841685 best dqsien dly found for B1: ( 1, 9, 20)
7669 12:18:41.844777 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7670 12:18:41.848420 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7671 12:18:41.848901
7672 12:18:41.855417 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7673 12:18:41.858211 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7674 12:18:41.861850 [Gating] SW calibration Done
7675 12:18:41.862555 ==
7676 12:18:41.865025 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 12:18:41.868167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 12:18:41.868676 ==
7679 12:18:41.869156 RX Vref Scan: 0
7680 12:18:41.869621
7681 12:18:41.871764 RX Vref 0 -> 0, step: 1
7682 12:18:41.872256
7683 12:18:41.875227 RX Delay 0 -> 252, step: 8
7684 12:18:41.878341 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7685 12:18:41.882049 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7686 12:18:41.885008 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7687 12:18:41.891716 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7688 12:18:41.894643 iDelay=200, Bit 4, Center 143 (96 ~ 191) 96
7689 12:18:41.898404 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7690 12:18:41.901890 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7691 12:18:41.905284 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7692 12:18:41.911941 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7693 12:18:41.914787 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7694 12:18:41.918261 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
7695 12:18:41.921388 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7696 12:18:41.924629 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7697 12:18:41.931635 iDelay=200, Bit 13, Center 131 (88 ~ 175) 88
7698 12:18:41.934882 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7699 12:18:41.938543 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
7700 12:18:41.939117 ==
7701 12:18:41.941347 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 12:18:41.944708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 12:18:41.945188 ==
7704 12:18:41.948126 DQS Delay:
7705 12:18:41.948797 DQS0 = 0, DQS1 = 0
7706 12:18:41.951021 DQM Delay:
7707 12:18:41.951556 DQM0 = 138, DQM1 = 126
7708 12:18:41.952128 DQ Delay:
7709 12:18:41.955216 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7710 12:18:41.958152 DQ4 =143, DQ5 =123, DQ6 =147, DQ7 =147
7711 12:18:41.964661 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7712 12:18:41.968578 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =131
7713 12:18:41.969056
7714 12:18:41.969526
7715 12:18:41.970002 ==
7716 12:18:41.971101 Dram Type= 6, Freq= 0, CH_0, rank 0
7717 12:18:41.974659 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7718 12:18:41.975140 ==
7719 12:18:41.975642
7720 12:18:41.976087
7721 12:18:41.977987 TX Vref Scan disable
7722 12:18:41.981726 == TX Byte 0 ==
7723 12:18:41.984745 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7724 12:18:41.987806 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7725 12:18:41.991257 == TX Byte 1 ==
7726 12:18:41.994582 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7727 12:18:41.998331 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7728 12:18:41.998860 ==
7729 12:18:42.001421 Dram Type= 6, Freq= 0, CH_0, rank 0
7730 12:18:42.004906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7731 12:18:42.007828 ==
7732 12:18:42.018834
7733 12:18:42.022491 TX Vref early break, caculate TX vref
7734 12:18:42.025557 TX Vref=16, minBit 4, minWin=23, winSum=382
7735 12:18:42.029326 TX Vref=18, minBit 12, minWin=23, winSum=393
7736 12:18:42.032383 TX Vref=20, minBit 12, minWin=23, winSum=397
7737 12:18:42.035761 TX Vref=22, minBit 0, minWin=25, winSum=412
7738 12:18:42.038919 TX Vref=24, minBit 1, minWin=25, winSum=416
7739 12:18:42.045324 TX Vref=26, minBit 2, minWin=25, winSum=421
7740 12:18:42.049128 TX Vref=28, minBit 0, minWin=26, winSum=425
7741 12:18:42.052576 TX Vref=30, minBit 2, minWin=25, winSum=414
7742 12:18:42.055636 TX Vref=32, minBit 0, minWin=25, winSum=408
7743 12:18:42.058613 TX Vref=34, minBit 0, minWin=24, winSum=399
7744 12:18:42.065626 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
7745 12:18:42.066204
7746 12:18:42.068757 Final TX Range 0 Vref 28
7747 12:18:42.069188
7748 12:18:42.069616 ==
7749 12:18:42.072187 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 12:18:42.075202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 12:18:42.075757 ==
7752 12:18:42.076196
7753 12:18:42.076602
7754 12:18:42.078455 TX Vref Scan disable
7755 12:18:42.085663 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7756 12:18:42.086239 == TX Byte 0 ==
7757 12:18:42.089151 u2DelayCellOfst[0]=13 cells (4 PI)
7758 12:18:42.091922 u2DelayCellOfst[1]=17 cells (5 PI)
7759 12:18:42.095119 u2DelayCellOfst[2]=10 cells (3 PI)
7760 12:18:42.099015 u2DelayCellOfst[3]=13 cells (4 PI)
7761 12:18:42.102704 u2DelayCellOfst[4]=10 cells (3 PI)
7762 12:18:42.106002 u2DelayCellOfst[5]=0 cells (0 PI)
7763 12:18:42.108828 u2DelayCellOfst[6]=17 cells (5 PI)
7764 12:18:42.112451 u2DelayCellOfst[7]=17 cells (5 PI)
7765 12:18:42.115070 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7766 12:18:42.118760 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7767 12:18:42.122056 == TX Byte 1 ==
7768 12:18:42.125256 u2DelayCellOfst[8]=0 cells (0 PI)
7769 12:18:42.125784 u2DelayCellOfst[9]=0 cells (0 PI)
7770 12:18:42.128304 u2DelayCellOfst[10]=6 cells (2 PI)
7771 12:18:42.132191 u2DelayCellOfst[11]=3 cells (1 PI)
7772 12:18:42.135458 u2DelayCellOfst[12]=13 cells (4 PI)
7773 12:18:42.138484 u2DelayCellOfst[13]=10 cells (3 PI)
7774 12:18:42.142342 u2DelayCellOfst[14]=17 cells (5 PI)
7775 12:18:42.145011 u2DelayCellOfst[15]=10 cells (3 PI)
7776 12:18:42.148322 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7777 12:18:42.154962 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7778 12:18:42.155555 DramC Write-DBI on
7779 12:18:42.156008 ==
7780 12:18:42.158455 Dram Type= 6, Freq= 0, CH_0, rank 0
7781 12:18:42.162043 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7782 12:18:42.164689 ==
7783 12:18:42.165116
7784 12:18:42.165541
7785 12:18:42.166072 TX Vref Scan disable
7786 12:18:42.168384 == TX Byte 0 ==
7787 12:18:42.171785 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7788 12:18:42.175651 == TX Byte 1 ==
7789 12:18:42.178455 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7790 12:18:42.182137 DramC Write-DBI off
7791 12:18:42.182673
7792 12:18:42.183134 [DATLAT]
7793 12:18:42.183544 Freq=1600, CH0 RK0
7794 12:18:42.183941
7795 12:18:42.184961 DATLAT Default: 0xf
7796 12:18:42.185509 0, 0xFFFF, sum = 0
7797 12:18:42.188866 1, 0xFFFF, sum = 0
7798 12:18:42.191667 2, 0xFFFF, sum = 0
7799 12:18:42.192106 3, 0xFFFF, sum = 0
7800 12:18:42.195256 4, 0xFFFF, sum = 0
7801 12:18:42.195693 5, 0xFFFF, sum = 0
7802 12:18:42.198614 6, 0xFFFF, sum = 0
7803 12:18:42.199163 7, 0xFFFF, sum = 0
7804 12:18:42.201894 8, 0xFFFF, sum = 0
7805 12:18:42.202470 9, 0xFFFF, sum = 0
7806 12:18:42.204793 10, 0xFFFF, sum = 0
7807 12:18:42.205229 11, 0xFFFF, sum = 0
7808 12:18:42.208743 12, 0xFFFF, sum = 0
7809 12:18:42.209280 13, 0xFFFF, sum = 0
7810 12:18:42.212273 14, 0x0, sum = 1
7811 12:18:42.212808 15, 0x0, sum = 2
7812 12:18:42.214938 16, 0x0, sum = 3
7813 12:18:42.215379 17, 0x0, sum = 4
7814 12:18:42.218588 best_step = 15
7815 12:18:42.219116
7816 12:18:42.219554 ==
7817 12:18:42.221315 Dram Type= 6, Freq= 0, CH_0, rank 0
7818 12:18:42.224848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7819 12:18:42.225286 ==
7820 12:18:42.228300 RX Vref Scan: 1
7821 12:18:42.228837
7822 12:18:42.229272 Set Vref Range= 24 -> 127
7823 12:18:42.229677
7824 12:18:42.231649 RX Vref 24 -> 127, step: 1
7825 12:18:42.232080
7826 12:18:42.234781 RX Delay 19 -> 252, step: 4
7827 12:18:42.235308
7828 12:18:42.238484 Set Vref, RX VrefLevel [Byte0]: 24
7829 12:18:42.241516 [Byte1]: 24
7830 12:18:42.241976
7831 12:18:42.244709 Set Vref, RX VrefLevel [Byte0]: 25
7832 12:18:42.248375 [Byte1]: 25
7833 12:18:42.251235
7834 12:18:42.251667 Set Vref, RX VrefLevel [Byte0]: 26
7835 12:18:42.254541 [Byte1]: 26
7836 12:18:42.258715
7837 12:18:42.259238 Set Vref, RX VrefLevel [Byte0]: 27
7838 12:18:42.262042 [Byte1]: 27
7839 12:18:42.266812
7840 12:18:42.267344 Set Vref, RX VrefLevel [Byte0]: 28
7841 12:18:42.269902 [Byte1]: 28
7842 12:18:42.274215
7843 12:18:42.274743 Set Vref, RX VrefLevel [Byte0]: 29
7844 12:18:42.277739 [Byte1]: 29
7845 12:18:42.281466
7846 12:18:42.282029 Set Vref, RX VrefLevel [Byte0]: 30
7847 12:18:42.285196 [Byte1]: 30
7848 12:18:42.289414
7849 12:18:42.290096 Set Vref, RX VrefLevel [Byte0]: 31
7850 12:18:42.292518 [Byte1]: 31
7851 12:18:42.297122
7852 12:18:42.297652 Set Vref, RX VrefLevel [Byte0]: 32
7853 12:18:42.300403 [Byte1]: 32
7854 12:18:42.304539
7855 12:18:42.305085 Set Vref, RX VrefLevel [Byte0]: 33
7856 12:18:42.307961 [Byte1]: 33
7857 12:18:42.312127
7858 12:18:42.312653 Set Vref, RX VrefLevel [Byte0]: 34
7859 12:18:42.314861 [Byte1]: 34
7860 12:18:42.319695
7861 12:18:42.320224 Set Vref, RX VrefLevel [Byte0]: 35
7862 12:18:42.322875 [Byte1]: 35
7863 12:18:42.327354
7864 12:18:42.327881 Set Vref, RX VrefLevel [Byte0]: 36
7865 12:18:42.330273 [Byte1]: 36
7866 12:18:42.334808
7867 12:18:42.335451 Set Vref, RX VrefLevel [Byte0]: 37
7868 12:18:42.340140 [Byte1]: 37
7869 12:18:42.341639
7870 12:18:42.341723 Set Vref, RX VrefLevel [Byte0]: 38
7871 12:18:42.344786 [Byte1]: 38
7872 12:18:42.349470
7873 12:18:42.349929 Set Vref, RX VrefLevel [Byte0]: 39
7874 12:18:42.352817 [Byte1]: 39
7875 12:18:42.357569
7876 12:18:42.358164 Set Vref, RX VrefLevel [Byte0]: 40
7877 12:18:42.361061 [Byte1]: 40
7878 12:18:42.365334
7879 12:18:42.365921 Set Vref, RX VrefLevel [Byte0]: 41
7880 12:18:42.368166 [Byte1]: 41
7881 12:18:42.372786
7882 12:18:42.373345 Set Vref, RX VrefLevel [Byte0]: 42
7883 12:18:42.375913 [Byte1]: 42
7884 12:18:42.380735
7885 12:18:42.381220 Set Vref, RX VrefLevel [Byte0]: 43
7886 12:18:42.383195 [Byte1]: 43
7887 12:18:42.388642
7888 12:18:42.389212 Set Vref, RX VrefLevel [Byte0]: 44
7889 12:18:42.390865 [Byte1]: 44
7890 12:18:42.395476
7891 12:18:42.396043 Set Vref, RX VrefLevel [Byte0]: 45
7892 12:18:42.398692 [Byte1]: 45
7893 12:18:42.402875
7894 12:18:42.403433 Set Vref, RX VrefLevel [Byte0]: 46
7895 12:18:42.406386 [Byte1]: 46
7896 12:18:42.410358
7897 12:18:42.410914 Set Vref, RX VrefLevel [Byte0]: 47
7898 12:18:42.413657 [Byte1]: 47
7899 12:18:42.418071
7900 12:18:42.418626 Set Vref, RX VrefLevel [Byte0]: 48
7901 12:18:42.421791 [Byte1]: 48
7902 12:18:42.425852
7903 12:18:42.426447 Set Vref, RX VrefLevel [Byte0]: 49
7904 12:18:42.429331 [Byte1]: 49
7905 12:18:42.433174
7906 12:18:42.433731 Set Vref, RX VrefLevel [Byte0]: 50
7907 12:18:42.436717 [Byte1]: 50
7908 12:18:42.441076
7909 12:18:42.441644 Set Vref, RX VrefLevel [Byte0]: 51
7910 12:18:42.444145 [Byte1]: 51
7911 12:18:42.448486
7912 12:18:42.449049 Set Vref, RX VrefLevel [Byte0]: 52
7913 12:18:42.451337 [Byte1]: 52
7914 12:18:42.455785
7915 12:18:42.456350 Set Vref, RX VrefLevel [Byte0]: 53
7916 12:18:42.459436 [Byte1]: 53
7917 12:18:42.463690
7918 12:18:42.464384 Set Vref, RX VrefLevel [Byte0]: 54
7919 12:18:42.466460 [Byte1]: 54
7920 12:18:42.471067
7921 12:18:42.471674 Set Vref, RX VrefLevel [Byte0]: 55
7922 12:18:42.474042 [Byte1]: 55
7923 12:18:42.478233
7924 12:18:42.478848 Set Vref, RX VrefLevel [Byte0]: 56
7925 12:18:42.481533 [Byte1]: 56
7926 12:18:42.486001
7927 12:18:42.486458 Set Vref, RX VrefLevel [Byte0]: 57
7928 12:18:42.489042 [Byte1]: 57
7929 12:18:42.493857
7930 12:18:42.494456 Set Vref, RX VrefLevel [Byte0]: 58
7931 12:18:42.497312 [Byte1]: 58
7932 12:18:42.501370
7933 12:18:42.501932 Set Vref, RX VrefLevel [Byte0]: 59
7934 12:18:42.504753 [Byte1]: 59
7935 12:18:42.509051
7936 12:18:42.509616 Set Vref, RX VrefLevel [Byte0]: 60
7937 12:18:42.512497 [Byte1]: 60
7938 12:18:42.516103
7939 12:18:42.516591 Set Vref, RX VrefLevel [Byte0]: 61
7940 12:18:42.519568 [Byte1]: 61
7941 12:18:42.524232
7942 12:18:42.524798 Set Vref, RX VrefLevel [Byte0]: 62
7943 12:18:42.527315 [Byte1]: 62
7944 12:18:42.531664
7945 12:18:42.532240 Set Vref, RX VrefLevel [Byte0]: 63
7946 12:18:42.534777 [Byte1]: 63
7947 12:18:42.539359
7948 12:18:42.539930 Set Vref, RX VrefLevel [Byte0]: 64
7949 12:18:42.542334 [Byte1]: 64
7950 12:18:42.546621
7951 12:18:42.547091 Set Vref, RX VrefLevel [Byte0]: 65
7952 12:18:42.550094 [Byte1]: 65
7953 12:18:42.554018
7954 12:18:42.554485 Set Vref, RX VrefLevel [Byte0]: 66
7955 12:18:42.557895 [Byte1]: 66
7956 12:18:42.562057
7957 12:18:42.562619 Set Vref, RX VrefLevel [Byte0]: 67
7958 12:18:42.564807 [Byte1]: 67
7959 12:18:42.569548
7960 12:18:42.570170 Set Vref, RX VrefLevel [Byte0]: 68
7961 12:18:42.572733 [Byte1]: 68
7962 12:18:42.577124
7963 12:18:42.577699 Set Vref, RX VrefLevel [Byte0]: 69
7964 12:18:42.580523 [Byte1]: 69
7965 12:18:42.584373
7966 12:18:42.584838 Set Vref, RX VrefLevel [Byte0]: 70
7967 12:18:42.587550 [Byte1]: 70
7968 12:18:42.592268
7969 12:18:42.592847 Set Vref, RX VrefLevel [Byte0]: 71
7970 12:18:42.595921 [Byte1]: 71
7971 12:18:42.599960
7972 12:18:42.600537 Set Vref, RX VrefLevel [Byte0]: 72
7973 12:18:42.602692 [Byte1]: 72
7974 12:18:42.607158
7975 12:18:42.607736 Set Vref, RX VrefLevel [Byte0]: 73
7976 12:18:42.610595 [Byte1]: 73
7977 12:18:42.614811
7978 12:18:42.615294 Set Vref, RX VrefLevel [Byte0]: 74
7979 12:18:42.618193 [Byte1]: 74
7980 12:18:42.622339
7981 12:18:42.622824 Set Vref, RX VrefLevel [Byte0]: 75
7982 12:18:42.625519 [Byte1]: 75
7983 12:18:42.630120
7984 12:18:42.630689 Set Vref, RX VrefLevel [Byte0]: 76
7985 12:18:42.633205 [Byte1]: 76
7986 12:18:42.637719
7987 12:18:42.638346 Set Vref, RX VrefLevel [Byte0]: 77
7988 12:18:42.641216 [Byte1]: 77
7989 12:18:42.645149
7990 12:18:42.645726 Set Vref, RX VrefLevel [Byte0]: 78
7991 12:18:42.648662 [Byte1]: 78
7992 12:18:42.652876
7993 12:18:42.653748 Set Vref, RX VrefLevel [Byte0]: 79
7994 12:18:42.656260 [Byte1]: 79
7995 12:18:42.659961
7996 12:18:42.660497 Set Vref, RX VrefLevel [Byte0]: 80
7997 12:18:42.663549 [Byte1]: 80
7998 12:18:42.668074
7999 12:18:42.668635 Set Vref, RX VrefLevel [Byte0]: 81
8000 12:18:42.671033 [Byte1]: 81
8001 12:18:42.675613
8002 12:18:42.676174 Final RX Vref Byte 0 = 59 to rank0
8003 12:18:42.678601 Final RX Vref Byte 1 = 63 to rank0
8004 12:18:42.681901 Final RX Vref Byte 0 = 59 to rank1
8005 12:18:42.685415 Final RX Vref Byte 1 = 63 to rank1==
8006 12:18:42.688617 Dram Type= 6, Freq= 0, CH_0, rank 0
8007 12:18:42.695598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8008 12:18:42.696165 ==
8009 12:18:42.696545 DQS Delay:
8010 12:18:42.696892 DQS0 = 0, DQS1 = 0
8011 12:18:42.698476 DQM Delay:
8012 12:18:42.698947 DQM0 = 136, DQM1 = 125
8013 12:18:42.702013 DQ Delay:
8014 12:18:42.705166 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
8015 12:18:42.708911 DQ4 =140, DQ5 =126, DQ6 =142, DQ7 =144
8016 12:18:42.711990 DQ8 =116, DQ9 =112, DQ10 =128, DQ11 =120
8017 12:18:42.715234 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =132
8018 12:18:42.715799
8019 12:18:42.716167
8020 12:18:42.716511
8021 12:18:42.718392 [DramC_TX_OE_Calibration] TA2
8022 12:18:42.721900 Original DQ_B0 (3 6) =30, OEN = 27
8023 12:18:42.725130 Original DQ_B1 (3 6) =30, OEN = 27
8024 12:18:42.728302 24, 0x0, End_B0=24 End_B1=24
8025 12:18:42.728783 25, 0x0, End_B0=25 End_B1=25
8026 12:18:42.732333 26, 0x0, End_B0=26 End_B1=26
8027 12:18:42.735131 27, 0x0, End_B0=27 End_B1=27
8028 12:18:42.738518 28, 0x0, End_B0=28 End_B1=28
8029 12:18:42.741799 29, 0x0, End_B0=29 End_B1=29
8030 12:18:42.742407 30, 0x0, End_B0=30 End_B1=30
8031 12:18:42.745123 31, 0x4141, End_B0=30 End_B1=30
8032 12:18:42.748434 Byte0 end_step=30 best_step=27
8033 12:18:42.751974 Byte1 end_step=30 best_step=27
8034 12:18:42.755046 Byte0 TX OE(2T, 0.5T) = (3, 3)
8035 12:18:42.758506 Byte1 TX OE(2T, 0.5T) = (3, 3)
8036 12:18:42.759069
8037 12:18:42.759464
8038 12:18:42.765113 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
8039 12:18:42.768395 CH0 RK0: MR19=303, MR18=1E1C
8040 12:18:42.775168 CH0_RK0: MR19=0x303, MR18=0x1E1C, DQSOSC=394, MR23=63, INC=23, DEC=15
8041 12:18:42.775736
8042 12:18:42.777907 ----->DramcWriteLeveling(PI) begin...
8043 12:18:42.778436 ==
8044 12:18:42.781383 Dram Type= 6, Freq= 0, CH_0, rank 1
8045 12:18:42.784975 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8046 12:18:42.785544 ==
8047 12:18:42.788274 Write leveling (Byte 0): 36 => 36
8048 12:18:42.791383 Write leveling (Byte 1): 29 => 29
8049 12:18:42.795005 DramcWriteLeveling(PI) end<-----
8050 12:18:42.795592
8051 12:18:42.795970 ==
8052 12:18:42.798087 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 12:18:42.801624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 12:18:42.802236 ==
8055 12:18:42.805315 [Gating] SW mode calibration
8056 12:18:42.811735 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8057 12:18:42.818402 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8058 12:18:42.821602 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8059 12:18:42.825160 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8060 12:18:42.831772 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8061 12:18:42.834834 1 4 12 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
8062 12:18:42.838099 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 12:18:42.844855 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8064 12:18:42.848172 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 12:18:42.851356 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8066 12:18:42.858211 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8067 12:18:42.861279 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8068 12:18:42.864268 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 12:18:42.870846 1 5 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
8070 12:18:42.874422 1 5 16 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
8071 12:18:42.878026 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 12:18:42.884390 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 12:18:42.887629 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 12:18:42.891140 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 12:18:42.898025 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 12:18:42.901134 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8077 12:18:42.904543 1 6 12 | B1->B0 | 2929 3e3e | 0 0 | (0 0) (0 0)
8078 12:18:42.911219 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 12:18:42.914624 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 12:18:42.917367 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 12:18:42.924436 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 12:18:42.927510 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8083 12:18:42.930981 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8084 12:18:42.937880 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 12:18:42.941195 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8086 12:18:42.944284 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8087 12:18:42.950975 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8088 12:18:42.954177 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 12:18:42.957614 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 12:18:42.963768 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 12:18:42.967417 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 12:18:42.970495 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 12:18:42.977088 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 12:18:42.980817 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 12:18:42.984531 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 12:18:42.987979 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 12:18:42.994011 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 12:18:42.997638 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 12:18:43.000958 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 12:18:43.007376 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8101 12:18:43.010484 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8102 12:18:43.014214 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8103 12:18:43.017514 Total UI for P1: 0, mck2ui 16
8104 12:18:43.020532 best dqsien dly found for B0: ( 1, 9, 10)
8105 12:18:43.028105 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8106 12:18:43.028641 Total UI for P1: 0, mck2ui 16
8107 12:18:43.033894 best dqsien dly found for B1: ( 1, 9, 14)
8108 12:18:43.037542 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8109 12:18:43.040827 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8110 12:18:43.041364
8111 12:18:43.043714 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8112 12:18:43.047483 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8113 12:18:43.050553 [Gating] SW calibration Done
8114 12:18:43.051086 ==
8115 12:18:43.054261 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 12:18:43.058122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 12:18:43.058551 ==
8118 12:18:43.060633 RX Vref Scan: 0
8119 12:18:43.061056
8120 12:18:43.061389 RX Vref 0 -> 0, step: 1
8121 12:18:43.061704
8122 12:18:43.063629 RX Delay 0 -> 252, step: 8
8123 12:18:43.066944 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8124 12:18:43.073555 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8125 12:18:43.076729 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8126 12:18:43.080417 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8127 12:18:43.083458 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8128 12:18:43.086686 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8129 12:18:43.093589 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8130 12:18:43.096699 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8131 12:18:43.100451 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8132 12:18:43.103349 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8133 12:18:43.107265 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8134 12:18:43.113373 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8135 12:18:43.116785 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8136 12:18:43.120060 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8137 12:18:43.123163 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8138 12:18:43.129935 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8139 12:18:43.130488 ==
8140 12:18:43.133454 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 12:18:43.136597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 12:18:43.137115 ==
8143 12:18:43.137461 DQS Delay:
8144 12:18:43.139756 DQS0 = 0, DQS1 = 0
8145 12:18:43.140273 DQM Delay:
8146 12:18:43.143169 DQM0 = 136, DQM1 = 125
8147 12:18:43.143683 DQ Delay:
8148 12:18:43.146512 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8149 12:18:43.149649 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8150 12:18:43.153178 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8151 12:18:43.156539 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
8152 12:18:43.156966
8153 12:18:43.157302
8154 12:18:43.159713 ==
8155 12:18:43.163047 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 12:18:43.166163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 12:18:43.166588 ==
8158 12:18:43.166928
8159 12:18:43.167243
8160 12:18:43.169590 TX Vref Scan disable
8161 12:18:43.170157 == TX Byte 0 ==
8162 12:18:43.176319 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8163 12:18:43.179765 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8164 12:18:43.180282 == TX Byte 1 ==
8165 12:18:43.186017 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8166 12:18:43.189525 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8167 12:18:43.190106 ==
8168 12:18:43.192527 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 12:18:43.196047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 12:18:43.196566 ==
8171 12:18:43.210299
8172 12:18:43.213536 TX Vref early break, caculate TX vref
8173 12:18:43.217257 TX Vref=16, minBit 0, minWin=24, winSum=393
8174 12:18:43.219843 TX Vref=18, minBit 0, minWin=24, winSum=402
8175 12:18:43.223497 TX Vref=20, minBit 8, minWin=24, winSum=411
8176 12:18:43.226838 TX Vref=22, minBit 1, minWin=25, winSum=417
8177 12:18:43.230233 TX Vref=24, minBit 8, minWin=25, winSum=426
8178 12:18:43.236711 TX Vref=26, minBit 0, minWin=26, winSum=426
8179 12:18:43.240034 TX Vref=28, minBit 0, minWin=26, winSum=429
8180 12:18:43.243412 TX Vref=30, minBit 0, minWin=25, winSum=423
8181 12:18:43.246625 TX Vref=32, minBit 0, minWin=25, winSum=409
8182 12:18:43.250072 TX Vref=34, minBit 2, minWin=24, winSum=406
8183 12:18:43.256553 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
8184 12:18:43.257111
8185 12:18:43.259851 Final TX Range 0 Vref 28
8186 12:18:43.260320
8187 12:18:43.260776 ==
8188 12:18:43.263305 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 12:18:43.266598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 12:18:43.267067 ==
8191 12:18:43.267440
8192 12:18:43.267782
8193 12:18:43.269580 TX Vref Scan disable
8194 12:18:43.276989 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8195 12:18:43.277566 == TX Byte 0 ==
8196 12:18:43.280060 u2DelayCellOfst[0]=13 cells (4 PI)
8197 12:18:43.283261 u2DelayCellOfst[1]=17 cells (5 PI)
8198 12:18:43.286573 u2DelayCellOfst[2]=13 cells (4 PI)
8199 12:18:43.289972 u2DelayCellOfst[3]=10 cells (3 PI)
8200 12:18:43.293220 u2DelayCellOfst[4]=6 cells (2 PI)
8201 12:18:43.297214 u2DelayCellOfst[5]=0 cells (0 PI)
8202 12:18:43.300102 u2DelayCellOfst[6]=17 cells (5 PI)
8203 12:18:43.300669 u2DelayCellOfst[7]=17 cells (5 PI)
8204 12:18:43.306793 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8205 12:18:43.310108 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8206 12:18:43.310671 == TX Byte 1 ==
8207 12:18:43.312931 u2DelayCellOfst[8]=0 cells (0 PI)
8208 12:18:43.316761 u2DelayCellOfst[9]=0 cells (0 PI)
8209 12:18:43.319857 u2DelayCellOfst[10]=6 cells (2 PI)
8210 12:18:43.323512 u2DelayCellOfst[11]=3 cells (1 PI)
8211 12:18:43.326611 u2DelayCellOfst[12]=13 cells (4 PI)
8212 12:18:43.330050 u2DelayCellOfst[13]=13 cells (4 PI)
8213 12:18:43.333040 u2DelayCellOfst[14]=13 cells (4 PI)
8214 12:18:43.336348 u2DelayCellOfst[15]=10 cells (3 PI)
8215 12:18:43.339826 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8216 12:18:43.346331 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8217 12:18:43.346883 DramC Write-DBI on
8218 12:18:43.347255 ==
8219 12:18:43.350222 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 12:18:43.353287 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 12:18:43.353852 ==
8222 12:18:43.356328
8223 12:18:43.356820
8224 12:18:43.357192 TX Vref Scan disable
8225 12:18:43.359683 == TX Byte 0 ==
8226 12:18:43.362804 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8227 12:18:43.366101 == TX Byte 1 ==
8228 12:18:43.369749 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8229 12:18:43.373359 DramC Write-DBI off
8230 12:18:43.373916
8231 12:18:43.374336 [DATLAT]
8232 12:18:43.374681 Freq=1600, CH0 RK1
8233 12:18:43.375016
8234 12:18:43.376271 DATLAT Default: 0xf
8235 12:18:43.376739 0, 0xFFFF, sum = 0
8236 12:18:43.379638 1, 0xFFFF, sum = 0
8237 12:18:43.380113 2, 0xFFFF, sum = 0
8238 12:18:43.383161 3, 0xFFFF, sum = 0
8239 12:18:43.386034 4, 0xFFFF, sum = 0
8240 12:18:43.386507 5, 0xFFFF, sum = 0
8241 12:18:43.390007 6, 0xFFFF, sum = 0
8242 12:18:43.390559 7, 0xFFFF, sum = 0
8243 12:18:43.392828 8, 0xFFFF, sum = 0
8244 12:18:43.393360 9, 0xFFFF, sum = 0
8245 12:18:43.396635 10, 0xFFFF, sum = 0
8246 12:18:43.397164 11, 0xFFFF, sum = 0
8247 12:18:43.399898 12, 0xFFFF, sum = 0
8248 12:18:43.400428 13, 0xFFFF, sum = 0
8249 12:18:43.403268 14, 0x0, sum = 1
8250 12:18:43.403792 15, 0x0, sum = 2
8251 12:18:43.406330 16, 0x0, sum = 3
8252 12:18:43.406859 17, 0x0, sum = 4
8253 12:18:43.409817 best_step = 15
8254 12:18:43.410367
8255 12:18:43.410704 ==
8256 12:18:43.413687 Dram Type= 6, Freq= 0, CH_0, rank 1
8257 12:18:43.416654 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8258 12:18:43.417099 ==
8259 12:18:43.417438 RX Vref Scan: 0
8260 12:18:43.419497
8261 12:18:43.419920 RX Vref 0 -> 0, step: 1
8262 12:18:43.420252
8263 12:18:43.423253 RX Delay 11 -> 252, step: 4
8264 12:18:43.425870 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8265 12:18:43.433043 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8266 12:18:43.436446 iDelay=191, Bit 2, Center 128 (79 ~ 178) 100
8267 12:18:43.439440 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8268 12:18:43.442928 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8269 12:18:43.446005 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8270 12:18:43.449532 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8271 12:18:43.456398 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8272 12:18:43.459716 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8273 12:18:43.463683 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8274 12:18:43.465961 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8275 12:18:43.469676 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8276 12:18:43.476563 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8277 12:18:43.479945 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8278 12:18:43.483025 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8279 12:18:43.486513 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8280 12:18:43.487035 ==
8281 12:18:43.489597 Dram Type= 6, Freq= 0, CH_0, rank 1
8282 12:18:43.496260 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8283 12:18:43.496787 ==
8284 12:18:43.497133 DQS Delay:
8285 12:18:43.499578 DQS0 = 0, DQS1 = 0
8286 12:18:43.500099 DQM Delay:
8287 12:18:43.502789 DQM0 = 133, DQM1 = 123
8288 12:18:43.503277 DQ Delay:
8289 12:18:43.506275 DQ0 =132, DQ1 =136, DQ2 =128, DQ3 =130
8290 12:18:43.509682 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8291 12:18:43.512987 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8292 12:18:43.516590 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =128
8293 12:18:43.517115
8294 12:18:43.517449
8295 12:18:43.517758
8296 12:18:43.519792 [DramC_TX_OE_Calibration] TA2
8297 12:18:43.522756 Original DQ_B0 (3 6) =30, OEN = 27
8298 12:18:43.526424 Original DQ_B1 (3 6) =30, OEN = 27
8299 12:18:43.529481 24, 0x0, End_B0=24 End_B1=24
8300 12:18:43.529911 25, 0x0, End_B0=25 End_B1=25
8301 12:18:43.533024 26, 0x0, End_B0=26 End_B1=26
8302 12:18:43.536211 27, 0x0, End_B0=27 End_B1=27
8303 12:18:43.539396 28, 0x0, End_B0=28 End_B1=28
8304 12:18:43.542914 29, 0x0, End_B0=29 End_B1=29
8305 12:18:43.543515 30, 0x0, End_B0=30 End_B1=30
8306 12:18:43.546034 31, 0x5151, End_B0=30 End_B1=30
8307 12:18:43.549687 Byte0 end_step=30 best_step=27
8308 12:18:43.552741 Byte1 end_step=30 best_step=27
8309 12:18:43.556595 Byte0 TX OE(2T, 0.5T) = (3, 3)
8310 12:18:43.559587 Byte1 TX OE(2T, 0.5T) = (3, 3)
8311 12:18:43.560012
8312 12:18:43.560350
8313 12:18:43.566043 [DQSOSCAuto] RK1, (LSB)MR18= 0x210e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8314 12:18:43.569683 CH0 RK1: MR19=303, MR18=210E
8315 12:18:43.576175 CH0_RK1: MR19=0x303, MR18=0x210E, DQSOSC=393, MR23=63, INC=23, DEC=15
8316 12:18:43.579728 [RxdqsGatingPostProcess] freq 1600
8317 12:18:43.582621 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8318 12:18:43.586220 best DQS0 dly(2T, 0.5T) = (1, 1)
8319 12:18:43.589434 best DQS1 dly(2T, 0.5T) = (1, 1)
8320 12:18:43.592725 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8321 12:18:43.596168 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8322 12:18:43.599431 best DQS0 dly(2T, 0.5T) = (1, 1)
8323 12:18:43.602565 best DQS1 dly(2T, 0.5T) = (1, 1)
8324 12:18:43.606225 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8325 12:18:43.609394 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8326 12:18:43.612878 Pre-setting of DQS Precalculation
8327 12:18:43.615852 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8328 12:18:43.616281 ==
8329 12:18:43.619129 Dram Type= 6, Freq= 0, CH_1, rank 0
8330 12:18:43.622418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8331 12:18:43.622847 ==
8332 12:18:43.629210 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8333 12:18:43.633356 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8334 12:18:43.639524 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8335 12:18:43.642570 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8336 12:18:43.652896 [CA 0] Center 42 (12~72) winsize 61
8337 12:18:43.655994 [CA 1] Center 42 (12~72) winsize 61
8338 12:18:43.658913 [CA 2] Center 38 (9~68) winsize 60
8339 12:18:43.662645 [CA 3] Center 37 (8~67) winsize 60
8340 12:18:43.665787 [CA 4] Center 37 (7~67) winsize 61
8341 12:18:43.669107 [CA 5] Center 37 (7~67) winsize 61
8342 12:18:43.669577
8343 12:18:43.672230 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8344 12:18:43.672699
8345 12:18:43.676099 [CATrainingPosCal] consider 1 rank data
8346 12:18:43.679206 u2DelayCellTimex100 = 285/100 ps
8347 12:18:43.682647 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8348 12:18:43.689279 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8349 12:18:43.692476 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8350 12:18:43.695668 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8351 12:18:43.699171 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
8352 12:18:43.702898 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8353 12:18:43.703460
8354 12:18:43.705439 CA PerBit enable=1, Macro0, CA PI delay=37
8355 12:18:43.705910
8356 12:18:43.708812 [CBTSetCACLKResult] CA Dly = 37
8357 12:18:43.712838 CS Dly: 9 (0~40)
8358 12:18:43.715473 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8359 12:18:43.719179 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8360 12:18:43.719632 ==
8361 12:18:43.722747 Dram Type= 6, Freq= 0, CH_1, rank 1
8362 12:18:43.725478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8363 12:18:43.725935 ==
8364 12:18:43.732402 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8365 12:18:43.735659 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8366 12:18:43.742247 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8367 12:18:43.745336 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8368 12:18:43.755657 [CA 0] Center 42 (13~72) winsize 60
8369 12:18:43.758649 [CA 1] Center 42 (12~72) winsize 61
8370 12:18:43.762235 [CA 2] Center 38 (9~68) winsize 60
8371 12:18:43.765790 [CA 3] Center 37 (8~67) winsize 60
8372 12:18:43.769004 [CA 4] Center 38 (9~68) winsize 60
8373 12:18:43.772484 [CA 5] Center 37 (8~67) winsize 60
8374 12:18:43.773048
8375 12:18:43.775680 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8376 12:18:43.776234
8377 12:18:43.778720 [CATrainingPosCal] consider 2 rank data
8378 12:18:43.782218 u2DelayCellTimex100 = 285/100 ps
8379 12:18:43.785378 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8380 12:18:43.792181 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8381 12:18:43.795322 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8382 12:18:43.798849 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8383 12:18:43.802275 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8384 12:18:43.805426 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8385 12:18:43.806022
8386 12:18:43.809025 CA PerBit enable=1, Macro0, CA PI delay=37
8387 12:18:43.809582
8388 12:18:43.812365 [CBTSetCACLKResult] CA Dly = 37
8389 12:18:43.815748 CS Dly: 9 (0~41)
8390 12:18:43.819340 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8391 12:18:43.822585 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8392 12:18:43.823169
8393 12:18:43.825239 ----->DramcWriteLeveling(PI) begin...
8394 12:18:43.825700 ==
8395 12:18:43.829012 Dram Type= 6, Freq= 0, CH_1, rank 0
8396 12:18:43.832188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8397 12:18:43.835680 ==
8398 12:18:43.836239 Write leveling (Byte 0): 25 => 25
8399 12:18:43.838737 Write leveling (Byte 1): 27 => 27
8400 12:18:43.842346 DramcWriteLeveling(PI) end<-----
8401 12:18:43.842905
8402 12:18:43.843264 ==
8403 12:18:43.845425 Dram Type= 6, Freq= 0, CH_1, rank 0
8404 12:18:43.852215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8405 12:18:43.852782 ==
8406 12:18:43.853150 [Gating] SW mode calibration
8407 12:18:43.862173 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8408 12:18:43.865174 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8409 12:18:43.868999 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 12:18:43.875557 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 12:18:43.878639 1 4 8 | B1->B0 | 2a2a 3030 | 0 1 | (1 1) (1 1)
8412 12:18:43.882108 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 12:18:43.888753 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 12:18:43.892088 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8415 12:18:43.895093 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8416 12:18:43.902469 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8417 12:18:43.905296 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8418 12:18:43.908588 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8419 12:18:43.915531 1 5 8 | B1->B0 | 3030 3030 | 0 0 | (0 0) (1 0)
8420 12:18:43.918480 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8421 12:18:43.922176 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 12:18:43.928575 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 12:18:43.932390 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 12:18:43.935345 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 12:18:43.942049 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 12:18:43.945403 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8427 12:18:43.948821 1 6 8 | B1->B0 | 4444 4444 | 0 0 | (0 0) (0 0)
8428 12:18:43.955008 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 12:18:43.958837 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 12:18:43.961810 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 12:18:43.968344 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 12:18:43.971772 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8433 12:18:43.974964 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8434 12:18:43.981824 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8435 12:18:43.985293 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8436 12:18:43.988286 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8437 12:18:43.994886 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8438 12:18:43.998283 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 12:18:44.002088 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 12:18:44.008413 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 12:18:44.011388 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 12:18:44.014564 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 12:18:44.018034 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 12:18:44.024967 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 12:18:44.028078 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 12:18:44.031806 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 12:18:44.038076 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 12:18:44.041033 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 12:18:44.044474 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 12:18:44.051091 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8451 12:18:44.054601 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8452 12:18:44.057692 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8453 12:18:44.061266 Total UI for P1: 0, mck2ui 16
8454 12:18:44.064477 best dqsien dly found for B0: ( 1, 9, 6)
8455 12:18:44.071360 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8456 12:18:44.074255 Total UI for P1: 0, mck2ui 16
8457 12:18:44.077776 best dqsien dly found for B1: ( 1, 9, 10)
8458 12:18:44.081230 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8459 12:18:44.084230 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8460 12:18:44.084865
8461 12:18:44.087494 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8462 12:18:44.090730 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8463 12:18:44.094342 [Gating] SW calibration Done
8464 12:18:44.094908 ==
8465 12:18:44.097298 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 12:18:44.100938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8467 12:18:44.101501 ==
8468 12:18:44.104191 RX Vref Scan: 0
8469 12:18:44.104757
8470 12:18:44.107437 RX Vref 0 -> 0, step: 1
8471 12:18:44.107897
8472 12:18:44.108261 RX Delay 0 -> 252, step: 8
8473 12:18:44.113903 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8474 12:18:44.117207 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8475 12:18:44.120551 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8476 12:18:44.123961 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8477 12:18:44.127217 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8478 12:18:44.130807 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8479 12:18:44.137325 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8480 12:18:44.140933 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8481 12:18:44.143889 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8482 12:18:44.147398 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8483 12:18:44.150684 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8484 12:18:44.157296 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8485 12:18:44.160399 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8486 12:18:44.163799 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8487 12:18:44.167038 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8488 12:18:44.170859 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8489 12:18:44.173809 ==
8490 12:18:44.177640 Dram Type= 6, Freq= 0, CH_1, rank 0
8491 12:18:44.180655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8492 12:18:44.181232 ==
8493 12:18:44.181610 DQS Delay:
8494 12:18:44.183973 DQS0 = 0, DQS1 = 0
8495 12:18:44.184547 DQM Delay:
8496 12:18:44.186983 DQM0 = 136, DQM1 = 130
8497 12:18:44.187517 DQ Delay:
8498 12:18:44.190554 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8499 12:18:44.193853 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8500 12:18:44.196731 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8501 12:18:44.200310 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
8502 12:18:44.200886
8503 12:18:44.201259
8504 12:18:44.204020 ==
8505 12:18:44.204491 Dram Type= 6, Freq= 0, CH_1, rank 0
8506 12:18:44.210569 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8507 12:18:44.211146 ==
8508 12:18:44.211528
8509 12:18:44.211872
8510 12:18:44.212204 TX Vref Scan disable
8511 12:18:44.214158 == TX Byte 0 ==
8512 12:18:44.217423 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8513 12:18:44.223903 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8514 12:18:44.224377 == TX Byte 1 ==
8515 12:18:44.227423 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8516 12:18:44.234237 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8517 12:18:44.234814 ==
8518 12:18:44.237278 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 12:18:44.240745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 12:18:44.241325 ==
8521 12:18:44.253337
8522 12:18:44.255828 TX Vref early break, caculate TX vref
8523 12:18:44.259436 TX Vref=16, minBit 10, minWin=21, winSum=371
8524 12:18:44.262544 TX Vref=18, minBit 10, minWin=22, winSum=384
8525 12:18:44.265477 TX Vref=20, minBit 10, minWin=23, winSum=392
8526 12:18:44.268894 TX Vref=22, minBit 10, minWin=23, winSum=402
8527 12:18:44.275954 TX Vref=24, minBit 6, minWin=25, winSum=412
8528 12:18:44.279125 TX Vref=26, minBit 0, minWin=25, winSum=418
8529 12:18:44.282412 TX Vref=28, minBit 12, minWin=25, winSum=421
8530 12:18:44.285570 TX Vref=30, minBit 12, minWin=24, winSum=412
8531 12:18:44.288559 TX Vref=32, minBit 9, minWin=24, winSum=404
8532 12:18:44.296220 TX Vref=34, minBit 12, minWin=23, winSum=392
8533 12:18:44.299407 [TxChooseVref] Worse bit 12, Min win 25, Win sum 421, Final Vref 28
8534 12:18:44.299988
8535 12:18:44.302039 Final TX Range 0 Vref 28
8536 12:18:44.302509
8537 12:18:44.302877 ==
8538 12:18:44.305648 Dram Type= 6, Freq= 0, CH_1, rank 0
8539 12:18:44.308784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8540 12:18:44.309344 ==
8541 12:18:44.312427
8542 12:18:44.312995
8543 12:18:44.313373 TX Vref Scan disable
8544 12:18:44.318463 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8545 12:18:44.319012 == TX Byte 0 ==
8546 12:18:44.322198 u2DelayCellOfst[0]=17 cells (5 PI)
8547 12:18:44.325384 u2DelayCellOfst[1]=10 cells (3 PI)
8548 12:18:44.328781 u2DelayCellOfst[2]=0 cells (0 PI)
8549 12:18:44.331949 u2DelayCellOfst[3]=6 cells (2 PI)
8550 12:18:44.335048 u2DelayCellOfst[4]=6 cells (2 PI)
8551 12:18:44.338590 u2DelayCellOfst[5]=17 cells (5 PI)
8552 12:18:44.341804 u2DelayCellOfst[6]=17 cells (5 PI)
8553 12:18:44.345500 u2DelayCellOfst[7]=3 cells (1 PI)
8554 12:18:44.349083 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8555 12:18:44.351875 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8556 12:18:44.355209 == TX Byte 1 ==
8557 12:18:44.358303 u2DelayCellOfst[8]=0 cells (0 PI)
8558 12:18:44.361612 u2DelayCellOfst[9]=3 cells (1 PI)
8559 12:18:44.364892 u2DelayCellOfst[10]=10 cells (3 PI)
8560 12:18:44.368259 u2DelayCellOfst[11]=3 cells (1 PI)
8561 12:18:44.372004 u2DelayCellOfst[12]=13 cells (4 PI)
8562 12:18:44.372571 u2DelayCellOfst[13]=17 cells (5 PI)
8563 12:18:44.374738 u2DelayCellOfst[14]=20 cells (6 PI)
8564 12:18:44.378562 u2DelayCellOfst[15]=17 cells (5 PI)
8565 12:18:44.384925 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8566 12:18:44.388101 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8567 12:18:44.388670 DramC Write-DBI on
8568 12:18:44.391542 ==
8569 12:18:44.394855 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 12:18:44.397861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 12:18:44.398367 ==
8572 12:18:44.398741
8573 12:18:44.399084
8574 12:18:44.401413 TX Vref Scan disable
8575 12:18:44.402006 == TX Byte 0 ==
8576 12:18:44.407872 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8577 12:18:44.408445 == TX Byte 1 ==
8578 12:18:44.411017 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8579 12:18:44.414352 DramC Write-DBI off
8580 12:18:44.414930
8581 12:18:44.415303 [DATLAT]
8582 12:18:44.417855 Freq=1600, CH1 RK0
8583 12:18:44.418477
8584 12:18:44.418855 DATLAT Default: 0xf
8585 12:18:44.421044 0, 0xFFFF, sum = 0
8586 12:18:44.421520 1, 0xFFFF, sum = 0
8587 12:18:44.424976 2, 0xFFFF, sum = 0
8588 12:18:44.425543 3, 0xFFFF, sum = 0
8589 12:18:44.427864 4, 0xFFFF, sum = 0
8590 12:18:44.430841 5, 0xFFFF, sum = 0
8591 12:18:44.431318 6, 0xFFFF, sum = 0
8592 12:18:44.434488 7, 0xFFFF, sum = 0
8593 12:18:44.435059 8, 0xFFFF, sum = 0
8594 12:18:44.437511 9, 0xFFFF, sum = 0
8595 12:18:44.438012 10, 0xFFFF, sum = 0
8596 12:18:44.441015 11, 0xFFFF, sum = 0
8597 12:18:44.441585 12, 0xFFFF, sum = 0
8598 12:18:44.444407 13, 0xFFFF, sum = 0
8599 12:18:44.444976 14, 0x0, sum = 1
8600 12:18:44.447631 15, 0x0, sum = 2
8601 12:18:44.448204 16, 0x0, sum = 3
8602 12:18:44.450753 17, 0x0, sum = 4
8603 12:18:44.451228 best_step = 15
8604 12:18:44.451595
8605 12:18:44.451937 ==
8606 12:18:44.454261 Dram Type= 6, Freq= 0, CH_1, rank 0
8607 12:18:44.457686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8608 12:18:44.461175 ==
8609 12:18:44.461737 RX Vref Scan: 1
8610 12:18:44.462367
8611 12:18:44.464152 Set Vref Range= 24 -> 127
8612 12:18:44.464632
8613 12:18:44.465003 RX Vref 24 -> 127, step: 1
8614 12:18:44.467598
8615 12:18:44.468061 RX Delay 19 -> 252, step: 4
8616 12:18:44.468432
8617 12:18:44.470827 Set Vref, RX VrefLevel [Byte0]: 24
8618 12:18:44.474093 [Byte1]: 24
8619 12:18:44.478035
8620 12:18:44.478608 Set Vref, RX VrefLevel [Byte0]: 25
8621 12:18:44.480925 [Byte1]: 25
8622 12:18:44.485532
8623 12:18:44.486143 Set Vref, RX VrefLevel [Byte0]: 26
8624 12:18:44.488612 [Byte1]: 26
8625 12:18:44.492927
8626 12:18:44.493562 Set Vref, RX VrefLevel [Byte0]: 27
8627 12:18:44.495904 [Byte1]: 27
8628 12:18:44.500533
8629 12:18:44.501107 Set Vref, RX VrefLevel [Byte0]: 28
8630 12:18:44.503643 [Byte1]: 28
8631 12:18:44.507859
8632 12:18:44.508424 Set Vref, RX VrefLevel [Byte0]: 29
8633 12:18:44.510934 [Byte1]: 29
8634 12:18:44.515280
8635 12:18:44.515741 Set Vref, RX VrefLevel [Byte0]: 30
8636 12:18:44.519156 [Byte1]: 30
8637 12:18:44.523305
8638 12:18:44.523879 Set Vref, RX VrefLevel [Byte0]: 31
8639 12:18:44.526604 [Byte1]: 31
8640 12:18:44.530491
8641 12:18:44.530958 Set Vref, RX VrefLevel [Byte0]: 32
8642 12:18:44.534202 [Byte1]: 32
8643 12:18:44.538439
8644 12:18:44.539009 Set Vref, RX VrefLevel [Byte0]: 33
8645 12:18:44.541977 [Byte1]: 33
8646 12:18:44.545996
8647 12:18:44.546578 Set Vref, RX VrefLevel [Byte0]: 34
8648 12:18:44.548789 [Byte1]: 34
8649 12:18:44.553482
8650 12:18:44.554076 Set Vref, RX VrefLevel [Byte0]: 35
8651 12:18:44.557266 [Byte1]: 35
8652 12:18:44.561480
8653 12:18:44.562077 Set Vref, RX VrefLevel [Byte0]: 36
8654 12:18:44.564084 [Byte1]: 36
8655 12:18:44.568139
8656 12:18:44.568600 Set Vref, RX VrefLevel [Byte0]: 37
8657 12:18:44.572159 [Byte1]: 37
8658 12:18:44.575829
8659 12:18:44.576294 Set Vref, RX VrefLevel [Byte0]: 38
8660 12:18:44.579409 [Byte1]: 38
8661 12:18:44.583944
8662 12:18:44.584518 Set Vref, RX VrefLevel [Byte0]: 39
8663 12:18:44.587241 [Byte1]: 39
8664 12:18:44.591337
8665 12:18:44.591898 Set Vref, RX VrefLevel [Byte0]: 40
8666 12:18:44.594492 [Byte1]: 40
8667 12:18:44.599269
8668 12:18:44.599827 Set Vref, RX VrefLevel [Byte0]: 41
8669 12:18:44.602225 [Byte1]: 41
8670 12:18:44.606767
8671 12:18:44.607328 Set Vref, RX VrefLevel [Byte0]: 42
8672 12:18:44.610044 [Byte1]: 42
8673 12:18:44.614197
8674 12:18:44.614658 Set Vref, RX VrefLevel [Byte0]: 43
8675 12:18:44.617194 [Byte1]: 43
8676 12:18:44.621718
8677 12:18:44.622331 Set Vref, RX VrefLevel [Byte0]: 44
8678 12:18:44.624726 [Byte1]: 44
8679 12:18:44.628998
8680 12:18:44.629460 Set Vref, RX VrefLevel [Byte0]: 45
8681 12:18:44.632767 [Byte1]: 45
8682 12:18:44.636557
8683 12:18:44.637021 Set Vref, RX VrefLevel [Byte0]: 46
8684 12:18:44.640303 [Byte1]: 46
8685 12:18:44.644611
8686 12:18:44.645166 Set Vref, RX VrefLevel [Byte0]: 47
8687 12:18:44.647333 [Byte1]: 47
8688 12:18:44.652098
8689 12:18:44.652564 Set Vref, RX VrefLevel [Byte0]: 48
8690 12:18:44.655191 [Byte1]: 48
8691 12:18:44.659249
8692 12:18:44.659806 Set Vref, RX VrefLevel [Byte0]: 49
8693 12:18:44.662882 [Byte1]: 49
8694 12:18:44.667126
8695 12:18:44.667595 Set Vref, RX VrefLevel [Byte0]: 50
8696 12:18:44.670060 [Byte1]: 50
8697 12:18:44.674869
8698 12:18:44.675450 Set Vref, RX VrefLevel [Byte0]: 51
8699 12:18:44.678057 [Byte1]: 51
8700 12:18:44.682326
8701 12:18:44.682898 Set Vref, RX VrefLevel [Byte0]: 52
8702 12:18:44.685669 [Byte1]: 52
8703 12:18:44.689734
8704 12:18:44.690324 Set Vref, RX VrefLevel [Byte0]: 53
8705 12:18:44.693474 [Byte1]: 53
8706 12:18:44.697613
8707 12:18:44.698202 Set Vref, RX VrefLevel [Byte0]: 54
8708 12:18:44.700915 [Byte1]: 54
8709 12:18:44.705020
8710 12:18:44.705576 Set Vref, RX VrefLevel [Byte0]: 55
8711 12:18:44.708477 [Byte1]: 55
8712 12:18:44.712746
8713 12:18:44.713309 Set Vref, RX VrefLevel [Byte0]: 56
8714 12:18:44.715629 [Byte1]: 56
8715 12:18:44.720195
8716 12:18:44.720902 Set Vref, RX VrefLevel [Byte0]: 57
8717 12:18:44.723477 [Byte1]: 57
8718 12:18:44.727572
8719 12:18:44.728029 Set Vref, RX VrefLevel [Byte0]: 58
8720 12:18:44.730777 [Byte1]: 58
8721 12:18:44.735005
8722 12:18:44.735567 Set Vref, RX VrefLevel [Byte0]: 59
8723 12:18:44.738676 [Byte1]: 59
8724 12:18:44.742777
8725 12:18:44.743367 Set Vref, RX VrefLevel [Byte0]: 60
8726 12:18:44.745813 [Byte1]: 60
8727 12:18:44.750183
8728 12:18:44.750737 Set Vref, RX VrefLevel [Byte0]: 61
8729 12:18:44.753639 [Byte1]: 61
8730 12:18:44.758053
8731 12:18:44.758610 Set Vref, RX VrefLevel [Byte0]: 62
8732 12:18:44.761157 [Byte1]: 62
8733 12:18:44.765102
8734 12:18:44.765564 Set Vref, RX VrefLevel [Byte0]: 63
8735 12:18:44.768517 [Byte1]: 63
8736 12:18:44.773346
8737 12:18:44.773910 Set Vref, RX VrefLevel [Byte0]: 64
8738 12:18:44.776140 [Byte1]: 64
8739 12:18:44.780435
8740 12:18:44.781019 Set Vref, RX VrefLevel [Byte0]: 65
8741 12:18:44.783809 [Byte1]: 65
8742 12:18:44.788110
8743 12:18:44.788674 Set Vref, RX VrefLevel [Byte0]: 66
8744 12:18:44.791699 [Byte1]: 66
8745 12:18:44.796271
8746 12:18:44.796827 Set Vref, RX VrefLevel [Byte0]: 67
8747 12:18:44.799100 [Byte1]: 67
8748 12:18:44.803921
8749 12:18:44.804479 Set Vref, RX VrefLevel [Byte0]: 68
8750 12:18:44.807096 [Byte1]: 68
8751 12:18:44.811111
8752 12:18:44.811674 Set Vref, RX VrefLevel [Byte0]: 69
8753 12:18:44.814122 [Byte1]: 69
8754 12:18:44.818685
8755 12:18:44.819288 Set Vref, RX VrefLevel [Byte0]: 70
8756 12:18:44.821636 [Byte1]: 70
8757 12:18:44.825923
8758 12:18:44.826530 Set Vref, RX VrefLevel [Byte0]: 71
8759 12:18:44.829669 [Byte1]: 71
8760 12:18:44.833597
8761 12:18:44.834095 Set Vref, RX VrefLevel [Byte0]: 72
8762 12:18:44.837115 [Byte1]: 72
8763 12:18:44.841213
8764 12:18:44.841830 Set Vref, RX VrefLevel [Byte0]: 73
8765 12:18:44.844284 [Byte1]: 73
8766 12:18:44.848834
8767 12:18:44.849390 Set Vref, RX VrefLevel [Byte0]: 74
8768 12:18:44.852005 [Byte1]: 74
8769 12:18:44.856490
8770 12:18:44.856950 Set Vref, RX VrefLevel [Byte0]: 75
8771 12:18:44.859611 [Byte1]: 75
8772 12:18:44.863520
8773 12:18:44.864146 Set Vref, RX VrefLevel [Byte0]: 76
8774 12:18:44.867152 [Byte1]: 76
8775 12:18:44.871087
8776 12:18:44.871553 Final RX Vref Byte 0 = 59 to rank0
8777 12:18:44.874863 Final RX Vref Byte 1 = 62 to rank0
8778 12:18:44.878124 Final RX Vref Byte 0 = 59 to rank1
8779 12:18:44.881682 Final RX Vref Byte 1 = 62 to rank1==
8780 12:18:44.884707 Dram Type= 6, Freq= 0, CH_1, rank 0
8781 12:18:44.891415 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8782 12:18:44.891991 ==
8783 12:18:44.892373 DQS Delay:
8784 12:18:44.892722 DQS0 = 0, DQS1 = 0
8785 12:18:44.894563 DQM Delay:
8786 12:18:44.895047 DQM0 = 134, DQM1 = 130
8787 12:18:44.898243 DQ Delay:
8788 12:18:44.901508 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =132
8789 12:18:44.904396 DQ4 =130, DQ5 =144, DQ6 =146, DQ7 =132
8790 12:18:44.908013 DQ8 =116, DQ9 =120, DQ10 =134, DQ11 =122
8791 12:18:44.911281 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =138
8792 12:18:44.911856
8793 12:18:44.912344
8794 12:18:44.912800
8795 12:18:44.914706 [DramC_TX_OE_Calibration] TA2
8796 12:18:44.918011 Original DQ_B0 (3 6) =30, OEN = 27
8797 12:18:44.921623 Original DQ_B1 (3 6) =30, OEN = 27
8798 12:18:44.924629 24, 0x0, End_B0=24 End_B1=24
8799 12:18:44.925232 25, 0x0, End_B0=25 End_B1=25
8800 12:18:44.928043 26, 0x0, End_B0=26 End_B1=26
8801 12:18:44.930994 27, 0x0, End_B0=27 End_B1=27
8802 12:18:44.934717 28, 0x0, End_B0=28 End_B1=28
8803 12:18:44.935301 29, 0x0, End_B0=29 End_B1=29
8804 12:18:44.938358 30, 0x0, End_B0=30 End_B1=30
8805 12:18:44.941587 31, 0x4141, End_B0=30 End_B1=30
8806 12:18:44.944510 Byte0 end_step=30 best_step=27
8807 12:18:44.947928 Byte1 end_step=30 best_step=27
8808 12:18:44.951350 Byte0 TX OE(2T, 0.5T) = (3, 3)
8809 12:18:44.951935 Byte1 TX OE(2T, 0.5T) = (3, 3)
8810 12:18:44.954619
8811 12:18:44.955192
8812 12:18:44.960928 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8813 12:18:44.964253 CH1 RK0: MR19=303, MR18=1927
8814 12:18:44.971104 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8815 12:18:44.971595
8816 12:18:44.974535 ----->DramcWriteLeveling(PI) begin...
8817 12:18:44.975030 ==
8818 12:18:44.977990 Dram Type= 6, Freq= 0, CH_1, rank 1
8819 12:18:44.981399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8820 12:18:44.982010 ==
8821 12:18:44.984377 Write leveling (Byte 0): 25 => 25
8822 12:18:44.987674 Write leveling (Byte 1): 27 => 27
8823 12:18:44.991216 DramcWriteLeveling(PI) end<-----
8824 12:18:44.991783
8825 12:18:44.992158 ==
8826 12:18:44.994503 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 12:18:44.998119 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 12:18:44.998682 ==
8829 12:18:45.000925 [Gating] SW mode calibration
8830 12:18:45.007914 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8831 12:18:45.014401 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8832 12:18:45.017774 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8833 12:18:45.021360 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8834 12:18:45.028001 1 4 8 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
8835 12:18:45.030865 1 4 12 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 1)
8836 12:18:45.034468 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 12:18:45.041048 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 12:18:45.044727 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8839 12:18:45.047683 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8840 12:18:45.053736 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8841 12:18:45.057459 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8842 12:18:45.060714 1 5 8 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 0)
8843 12:18:45.067244 1 5 12 | B1->B0 | 2323 2f2f | 0 0 | (1 0) (0 1)
8844 12:18:45.070620 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 12:18:45.074487 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 12:18:45.081334 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 12:18:45.084324 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8848 12:18:45.087134 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8849 12:18:45.094047 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8850 12:18:45.097244 1 6 8 | B1->B0 | 4141 2525 | 0 0 | (0 0) (0 0)
8851 12:18:45.100752 1 6 12 | B1->B0 | 4646 3d3d | 0 0 | (0 0) (0 0)
8852 12:18:45.107650 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 12:18:45.110476 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 12:18:45.113740 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 12:18:45.117200 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 12:18:45.123866 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 12:18:45.127550 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8858 12:18:45.130649 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8859 12:18:45.137780 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8860 12:18:45.140673 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 12:18:45.144100 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 12:18:45.150820 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 12:18:45.153990 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 12:18:45.157114 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 12:18:45.163757 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 12:18:45.166829 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 12:18:45.170344 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 12:18:45.177132 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 12:18:45.180294 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 12:18:45.183979 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 12:18:45.190106 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 12:18:45.193764 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 12:18:45.196642 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 12:18:45.203278 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8875 12:18:45.206772 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8876 12:18:45.209905 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8877 12:18:45.213541 Total UI for P1: 0, mck2ui 16
8878 12:18:45.216746 best dqsien dly found for B0: ( 1, 9, 10)
8879 12:18:45.219811 Total UI for P1: 0, mck2ui 16
8880 12:18:45.222951 best dqsien dly found for B1: ( 1, 9, 10)
8881 12:18:45.226594 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8882 12:18:45.230423 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8883 12:18:45.230989
8884 12:18:45.236782 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8885 12:18:45.240326 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8886 12:18:45.243321 [Gating] SW calibration Done
8887 12:18:45.243886 ==
8888 12:18:45.246704 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 12:18:45.250348 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 12:18:45.250925 ==
8891 12:18:45.251300 RX Vref Scan: 0
8892 12:18:45.251640
8893 12:18:45.253467 RX Vref 0 -> 0, step: 1
8894 12:18:45.253927
8895 12:18:45.256847 RX Delay 0 -> 252, step: 8
8896 12:18:45.259955 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8897 12:18:45.263157 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8898 12:18:45.266375 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8899 12:18:45.273216 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8900 12:18:45.276456 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8901 12:18:45.279645 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8902 12:18:45.283254 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8903 12:18:45.286325 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8904 12:18:45.293592 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8905 12:18:45.296658 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8906 12:18:45.300165 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8907 12:18:45.303196 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8908 12:18:45.306752 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8909 12:18:45.313247 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8910 12:18:45.316824 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8911 12:18:45.320115 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8912 12:18:45.320683 ==
8913 12:18:45.323422 Dram Type= 6, Freq= 0, CH_1, rank 1
8914 12:18:45.326491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8915 12:18:45.329745 ==
8916 12:18:45.330354 DQS Delay:
8917 12:18:45.330727 DQS0 = 0, DQS1 = 0
8918 12:18:45.333138 DQM Delay:
8919 12:18:45.333598 DQM0 = 136, DQM1 = 132
8920 12:18:45.336325 DQ Delay:
8921 12:18:45.339623 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8922 12:18:45.343239 DQ4 =139, DQ5 =147, DQ6 =143, DQ7 =135
8923 12:18:45.346464 DQ8 =115, DQ9 =123, DQ10 =131, DQ11 =127
8924 12:18:45.349692 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8925 12:18:45.350213
8926 12:18:45.350587
8927 12:18:45.350951 ==
8928 12:18:45.352848 Dram Type= 6, Freq= 0, CH_1, rank 1
8929 12:18:45.356401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8930 12:18:45.356967 ==
8931 12:18:45.357343
8932 12:18:45.359642
8933 12:18:45.360106 TX Vref Scan disable
8934 12:18:45.363043 == TX Byte 0 ==
8935 12:18:45.366076 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8936 12:18:45.369546 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8937 12:18:45.372587 == TX Byte 1 ==
8938 12:18:45.376345 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8939 12:18:45.379567 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8940 12:18:45.380134 ==
8941 12:18:45.382638 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 12:18:45.389167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 12:18:45.389733 ==
8944 12:18:45.401014
8945 12:18:45.404394 TX Vref early break, caculate TX vref
8946 12:18:45.407454 TX Vref=16, minBit 8, minWin=23, winSum=386
8947 12:18:45.411038 TX Vref=18, minBit 0, minWin=24, winSum=398
8948 12:18:45.414248 TX Vref=20, minBit 8, minWin=24, winSum=404
8949 12:18:45.417455 TX Vref=22, minBit 8, minWin=25, winSum=414
8950 12:18:45.420908 TX Vref=24, minBit 10, minWin=24, winSum=418
8951 12:18:45.427700 TX Vref=26, minBit 10, minWin=25, winSum=421
8952 12:18:45.431140 TX Vref=28, minBit 10, minWin=25, winSum=424
8953 12:18:45.434192 TX Vref=30, minBit 5, minWin=25, winSum=414
8954 12:18:45.437757 TX Vref=32, minBit 10, minWin=24, winSum=406
8955 12:18:45.441132 TX Vref=34, minBit 0, minWin=23, winSum=397
8956 12:18:45.447816 [TxChooseVref] Worse bit 10, Min win 25, Win sum 424, Final Vref 28
8957 12:18:45.448388
8958 12:18:45.451060 Final TX Range 0 Vref 28
8959 12:18:45.451634
8960 12:18:45.452006 ==
8961 12:18:45.454159 Dram Type= 6, Freq= 0, CH_1, rank 1
8962 12:18:45.457899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8963 12:18:45.458503 ==
8964 12:18:45.458880
8965 12:18:45.459225
8966 12:18:45.460709 TX Vref Scan disable
8967 12:18:45.467677 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8968 12:18:45.468249 == TX Byte 0 ==
8969 12:18:45.470970 u2DelayCellOfst[0]=13 cells (4 PI)
8970 12:18:45.474165 u2DelayCellOfst[1]=10 cells (3 PI)
8971 12:18:45.478001 u2DelayCellOfst[2]=0 cells (0 PI)
8972 12:18:45.480843 u2DelayCellOfst[3]=3 cells (1 PI)
8973 12:18:45.484403 u2DelayCellOfst[4]=6 cells (2 PI)
8974 12:18:45.487458 u2DelayCellOfst[5]=17 cells (5 PI)
8975 12:18:45.490457 u2DelayCellOfst[6]=17 cells (5 PI)
8976 12:18:45.493855 u2DelayCellOfst[7]=3 cells (1 PI)
8977 12:18:45.497552 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8978 12:18:45.500537 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8979 12:18:45.504257 == TX Byte 1 ==
8980 12:18:45.504840 u2DelayCellOfst[8]=0 cells (0 PI)
8981 12:18:45.507480 u2DelayCellOfst[9]=3 cells (1 PI)
8982 12:18:45.510814 u2DelayCellOfst[10]=10 cells (3 PI)
8983 12:18:45.514128 u2DelayCellOfst[11]=3 cells (1 PI)
8984 12:18:45.517133 u2DelayCellOfst[12]=13 cells (4 PI)
8985 12:18:45.520615 u2DelayCellOfst[13]=17 cells (5 PI)
8986 12:18:45.523742 u2DelayCellOfst[14]=20 cells (6 PI)
8987 12:18:45.527170 u2DelayCellOfst[15]=17 cells (5 PI)
8988 12:18:45.530665 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8989 12:18:45.537211 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8990 12:18:45.537767 DramC Write-DBI on
8991 12:18:45.538193 ==
8992 12:18:45.540545 Dram Type= 6, Freq= 0, CH_1, rank 1
8993 12:18:45.543955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8994 12:18:45.547413 ==
8995 12:18:45.547975
8996 12:18:45.548347
8997 12:18:45.548690 TX Vref Scan disable
8998 12:18:45.550401 == TX Byte 0 ==
8999 12:18:45.554163 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9000 12:18:45.557189 == TX Byte 1 ==
9001 12:18:45.560188 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9002 12:18:45.563627 DramC Write-DBI off
9003 12:18:45.564188
9004 12:18:45.564603 [DATLAT]
9005 12:18:45.564954 Freq=1600, CH1 RK1
9006 12:18:45.565295
9007 12:18:45.567078 DATLAT Default: 0xf
9008 12:18:45.567537 0, 0xFFFF, sum = 0
9009 12:18:45.570242 1, 0xFFFF, sum = 0
9010 12:18:45.573839 2, 0xFFFF, sum = 0
9011 12:18:45.574339 3, 0xFFFF, sum = 0
9012 12:18:45.576893 4, 0xFFFF, sum = 0
9013 12:18:45.577480 5, 0xFFFF, sum = 0
9014 12:18:45.580663 6, 0xFFFF, sum = 0
9015 12:18:45.581235 7, 0xFFFF, sum = 0
9016 12:18:45.583711 8, 0xFFFF, sum = 0
9017 12:18:45.584287 9, 0xFFFF, sum = 0
9018 12:18:45.586835 10, 0xFFFF, sum = 0
9019 12:18:45.587305 11, 0xFFFF, sum = 0
9020 12:18:45.590065 12, 0xFFFF, sum = 0
9021 12:18:45.590538 13, 0xFFFF, sum = 0
9022 12:18:45.593710 14, 0x0, sum = 1
9023 12:18:45.594325 15, 0x0, sum = 2
9024 12:18:45.596556 16, 0x0, sum = 3
9025 12:18:45.597023 17, 0x0, sum = 4
9026 12:18:45.599793 best_step = 15
9027 12:18:45.600256
9028 12:18:45.600621 ==
9029 12:18:45.603694 Dram Type= 6, Freq= 0, CH_1, rank 1
9030 12:18:45.606538 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9031 12:18:45.607011 ==
9032 12:18:45.610478 RX Vref Scan: 0
9033 12:18:45.611040
9034 12:18:45.611407 RX Vref 0 -> 0, step: 1
9035 12:18:45.611746
9036 12:18:45.613313 RX Delay 19 -> 252, step: 4
9037 12:18:45.620173 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
9038 12:18:45.623225 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9039 12:18:45.626926 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9040 12:18:45.630312 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9041 12:18:45.633516 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9042 12:18:45.636686 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
9043 12:18:45.643454 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9044 12:18:45.646635 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
9045 12:18:45.649838 iDelay=195, Bit 8, Center 114 (67 ~ 162) 96
9046 12:18:45.653433 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9047 12:18:45.656287 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9048 12:18:45.663375 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9049 12:18:45.666391 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9050 12:18:45.670035 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9051 12:18:45.672954 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9052 12:18:45.676152 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9053 12:18:45.679276 ==
9054 12:18:45.679743 Dram Type= 6, Freq= 0, CH_1, rank 1
9055 12:18:45.686442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9056 12:18:45.687024 ==
9057 12:18:45.687404 DQS Delay:
9058 12:18:45.689413 DQS0 = 0, DQS1 = 0
9059 12:18:45.689872 DQM Delay:
9060 12:18:45.693008 DQM0 = 133, DQM1 = 130
9061 12:18:45.693575 DQ Delay:
9062 12:18:45.695850 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
9063 12:18:45.699291 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =130
9064 12:18:45.702438 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =124
9065 12:18:45.706464 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9066 12:18:45.707032
9067 12:18:45.707407
9068 12:18:45.707750
9069 12:18:45.709795 [DramC_TX_OE_Calibration] TA2
9070 12:18:45.713273 Original DQ_B0 (3 6) =30, OEN = 27
9071 12:18:45.716451 Original DQ_B1 (3 6) =30, OEN = 27
9072 12:18:45.719704 24, 0x0, End_B0=24 End_B1=24
9073 12:18:45.722602 25, 0x0, End_B0=25 End_B1=25
9074 12:18:45.723135 26, 0x0, End_B0=26 End_B1=26
9075 12:18:45.726228 27, 0x0, End_B0=27 End_B1=27
9076 12:18:45.729736 28, 0x0, End_B0=28 End_B1=28
9077 12:18:45.732746 29, 0x0, End_B0=29 End_B1=29
9078 12:18:45.733225 30, 0x0, End_B0=30 End_B1=30
9079 12:18:45.736079 31, 0x4141, End_B0=30 End_B1=30
9080 12:18:45.739337 Byte0 end_step=30 best_step=27
9081 12:18:45.742592 Byte1 end_step=30 best_step=27
9082 12:18:45.746037 Byte0 TX OE(2T, 0.5T) = (3, 3)
9083 12:18:45.749620 Byte1 TX OE(2T, 0.5T) = (3, 3)
9084 12:18:45.750225
9085 12:18:45.750605
9086 12:18:45.756175 [DQSOSCAuto] RK1, (LSB)MR18= 0x1904, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
9087 12:18:45.759269 CH1 RK1: MR19=303, MR18=1904
9088 12:18:45.765988 CH1_RK1: MR19=0x303, MR18=0x1904, DQSOSC=397, MR23=63, INC=23, DEC=15
9089 12:18:45.769476 [RxdqsGatingPostProcess] freq 1600
9090 12:18:45.776096 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9091 12:18:45.776672 best DQS0 dly(2T, 0.5T) = (1, 1)
9092 12:18:45.779295 best DQS1 dly(2T, 0.5T) = (1, 1)
9093 12:18:45.782546 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9094 12:18:45.785833 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9095 12:18:45.789276 best DQS0 dly(2T, 0.5T) = (1, 1)
9096 12:18:45.792475 best DQS1 dly(2T, 0.5T) = (1, 1)
9097 12:18:45.795843 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9098 12:18:45.799275 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9099 12:18:45.802514 Pre-setting of DQS Precalculation
9100 12:18:45.805648 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9101 12:18:45.812492 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9102 12:18:45.822551 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9103 12:18:45.823122
9104 12:18:45.823495
9105 12:18:45.825405 [Calibration Summary] 3200 Mbps
9106 12:18:45.825893 CH 0, Rank 0
9107 12:18:45.828972 SW Impedance : PASS
9108 12:18:45.829579 DUTY Scan : NO K
9109 12:18:45.832839 ZQ Calibration : PASS
9110 12:18:45.835604 Jitter Meter : NO K
9111 12:18:45.836176 CBT Training : PASS
9112 12:18:45.839026 Write leveling : PASS
9113 12:18:45.839492 RX DQS gating : PASS
9114 12:18:45.842304 RX DQ/DQS(RDDQC) : PASS
9115 12:18:45.845851 TX DQ/DQS : PASS
9116 12:18:45.846446 RX DATLAT : PASS
9117 12:18:45.849172 RX DQ/DQS(Engine): PASS
9118 12:18:45.852612 TX OE : PASS
9119 12:18:45.853184 All Pass.
9120 12:18:45.853558
9121 12:18:45.853898 CH 0, Rank 1
9122 12:18:45.855746 SW Impedance : PASS
9123 12:18:45.858886 DUTY Scan : NO K
9124 12:18:45.859454 ZQ Calibration : PASS
9125 12:18:45.862540 Jitter Meter : NO K
9126 12:18:45.865521 CBT Training : PASS
9127 12:18:45.865999 Write leveling : PASS
9128 12:18:45.868804 RX DQS gating : PASS
9129 12:18:45.872112 RX DQ/DQS(RDDQC) : PASS
9130 12:18:45.872575 TX DQ/DQS : PASS
9131 12:18:45.875373 RX DATLAT : PASS
9132 12:18:45.878632 RX DQ/DQS(Engine): PASS
9133 12:18:45.879094 TX OE : PASS
9134 12:18:45.879465 All Pass.
9135 12:18:45.882241
9136 12:18:45.882703 CH 1, Rank 0
9137 12:18:45.885474 SW Impedance : PASS
9138 12:18:45.886083 DUTY Scan : NO K
9139 12:18:45.888910 ZQ Calibration : PASS
9140 12:18:45.889479 Jitter Meter : NO K
9141 12:18:45.891875 CBT Training : PASS
9142 12:18:45.895642 Write leveling : PASS
9143 12:18:45.896227 RX DQS gating : PASS
9144 12:18:45.898982 RX DQ/DQS(RDDQC) : PASS
9145 12:18:45.902060 TX DQ/DQS : PASS
9146 12:18:45.902531 RX DATLAT : PASS
9147 12:18:45.905715 RX DQ/DQS(Engine): PASS
9148 12:18:45.908843 TX OE : PASS
9149 12:18:45.909413 All Pass.
9150 12:18:45.909784
9151 12:18:45.910171 CH 1, Rank 1
9152 12:18:45.912100 SW Impedance : PASS
9153 12:18:45.915574 DUTY Scan : NO K
9154 12:18:45.916156 ZQ Calibration : PASS
9155 12:18:45.918860 Jitter Meter : NO K
9156 12:18:45.922144 CBT Training : PASS
9157 12:18:45.922756 Write leveling : PASS
9158 12:18:45.925582 RX DQS gating : PASS
9159 12:18:45.928929 RX DQ/DQS(RDDQC) : PASS
9160 12:18:45.929395 TX DQ/DQS : PASS
9161 12:18:45.932292 RX DATLAT : PASS
9162 12:18:45.935280 RX DQ/DQS(Engine): PASS
9163 12:18:45.935870 TX OE : PASS
9164 12:18:45.936248 All Pass.
9165 12:18:45.938803
9166 12:18:45.939369 DramC Write-DBI on
9167 12:18:45.941921 PER_BANK_REFRESH: Hybrid Mode
9168 12:18:45.942420 TX_TRACKING: ON
9169 12:18:45.952003 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9170 12:18:45.958582 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9171 12:18:45.968649 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9172 12:18:45.971573 [FAST_K] Save calibration result to emmc
9173 12:18:45.972100 sync common calibartion params.
9174 12:18:45.975240 sync cbt_mode0:1, 1:1
9175 12:18:45.978452 dram_init: ddr_geometry: 2
9176 12:18:45.981834 dram_init: ddr_geometry: 2
9177 12:18:45.982436 dram_init: ddr_geometry: 2
9178 12:18:45.985115 0:dram_rank_size:100000000
9179 12:18:45.988702 1:dram_rank_size:100000000
9180 12:18:45.992108 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9181 12:18:45.995343 DFS_SHUFFLE_HW_MODE: ON
9182 12:18:45.998806 dramc_set_vcore_voltage set vcore to 725000
9183 12:18:46.001622 Read voltage for 1600, 0
9184 12:18:46.002129 Vio18 = 0
9185 12:18:46.005238 Vcore = 725000
9186 12:18:46.005815 Vdram = 0
9187 12:18:46.006241 Vddq = 0
9188 12:18:46.006597 Vmddr = 0
9189 12:18:46.008531 switch to 3200 Mbps bootup
9190 12:18:46.012104 [DramcRunTimeConfig]
9191 12:18:46.012681 PHYPLL
9192 12:18:46.015114 DPM_CONTROL_AFTERK: ON
9193 12:18:46.015584 PER_BANK_REFRESH: ON
9194 12:18:46.018253 REFRESH_OVERHEAD_REDUCTION: ON
9195 12:18:46.021931 CMD_PICG_NEW_MODE: OFF
9196 12:18:46.022567 XRTWTW_NEW_MODE: ON
9197 12:18:46.025338 XRTRTR_NEW_MODE: ON
9198 12:18:46.025806 TX_TRACKING: ON
9199 12:18:46.028254 RDSEL_TRACKING: OFF
9200 12:18:46.028745 DQS Precalculation for DVFS: ON
9201 12:18:46.031555 RX_TRACKING: OFF
9202 12:18:46.032171 HW_GATING DBG: ON
9203 12:18:46.035004 ZQCS_ENABLE_LP4: ON
9204 12:18:46.038390 RX_PICG_NEW_MODE: ON
9205 12:18:46.038862 TX_PICG_NEW_MODE: ON
9206 12:18:46.041665 ENABLE_RX_DCM_DPHY: ON
9207 12:18:46.045174 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9208 12:18:46.045751 DUMMY_READ_FOR_TRACKING: OFF
9209 12:18:46.048198 !!! SPM_CONTROL_AFTERK: OFF
9210 12:18:46.051764 !!! SPM could not control APHY
9211 12:18:46.055105 IMPEDANCE_TRACKING: ON
9212 12:18:46.055677 TEMP_SENSOR: ON
9213 12:18:46.058501 HW_SAVE_FOR_SR: OFF
9214 12:18:46.061711 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9215 12:18:46.065175 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9216 12:18:46.065750 Read ODT Tracking: ON
9217 12:18:46.068200 Refresh Rate DeBounce: ON
9218 12:18:46.071740 DFS_NO_QUEUE_FLUSH: ON
9219 12:18:46.072443 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9220 12:18:46.074939 ENABLE_DFS_RUNTIME_MRW: OFF
9221 12:18:46.078257 DDR_RESERVE_NEW_MODE: ON
9222 12:18:46.081452 MR_CBT_SWITCH_FREQ: ON
9223 12:18:46.081932 =========================
9224 12:18:46.101438 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9225 12:18:46.104812 dram_init: ddr_geometry: 2
9226 12:18:46.122897 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9227 12:18:46.126062 dram_init: dram init end (result: 0)
9228 12:18:46.133042 DRAM-K: Full calibration passed in 24521 msecs
9229 12:18:46.136636 MRC: failed to locate region type 0.
9230 12:18:46.137215 DRAM rank0 size:0x100000000,
9231 12:18:46.139822 DRAM rank1 size=0x100000000
9232 12:18:46.149640 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9233 12:18:46.156344 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9234 12:18:46.162905 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9235 12:18:46.169766 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9236 12:18:46.172805 DRAM rank0 size:0x100000000,
9237 12:18:46.176155 DRAM rank1 size=0x100000000
9238 12:18:46.176721 CBMEM:
9239 12:18:46.179696 IMD: root @ 0xfffff000 254 entries.
9240 12:18:46.182601 IMD: root @ 0xffffec00 62 entries.
9241 12:18:46.186391 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9242 12:18:46.189600 WARNING: RO_VPD is uninitialized or empty.
9243 12:18:46.196028 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9244 12:18:46.203431 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9245 12:18:46.215489 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9246 12:18:46.227059 BS: romstage times (exec / console): total (unknown) / 24019 ms
9247 12:18:46.227652
9248 12:18:46.228256
9249 12:18:46.237292 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9250 12:18:46.240353 ARM64: Exception handlers installed.
9251 12:18:46.243930 ARM64: Testing exception
9252 12:18:46.247183 ARM64: Done test exception
9253 12:18:46.247763 Enumerating buses...
9254 12:18:46.250280 Show all devs... Before device enumeration.
9255 12:18:46.253869 Root Device: enabled 1
9256 12:18:46.257415 CPU_CLUSTER: 0: enabled 1
9257 12:18:46.258021 CPU: 00: enabled 1
9258 12:18:46.260789 Compare with tree...
9259 12:18:46.261362 Root Device: enabled 1
9260 12:18:46.263768 CPU_CLUSTER: 0: enabled 1
9261 12:18:46.267181 CPU: 00: enabled 1
9262 12:18:46.267753 Root Device scanning...
9263 12:18:46.270258 scan_static_bus for Root Device
9264 12:18:46.273382 CPU_CLUSTER: 0 enabled
9265 12:18:46.276942 scan_static_bus for Root Device done
9266 12:18:46.280482 scan_bus: bus Root Device finished in 8 msecs
9267 12:18:46.281053 done
9268 12:18:46.287162 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9269 12:18:46.290345 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9270 12:18:46.297266 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9271 12:18:46.300304 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9272 12:18:46.303738 Allocating resources...
9273 12:18:46.304304 Reading resources...
9274 12:18:46.310394 Root Device read_resources bus 0 link: 0
9275 12:18:46.310961 DRAM rank0 size:0x100000000,
9276 12:18:46.313811 DRAM rank1 size=0x100000000
9277 12:18:46.316839 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9278 12:18:46.319967 CPU: 00 missing read_resources
9279 12:18:46.323812 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9280 12:18:46.330102 Root Device read_resources bus 0 link: 0 done
9281 12:18:46.330742 Done reading resources.
9282 12:18:46.336660 Show resources in subtree (Root Device)...After reading.
9283 12:18:46.339897 Root Device child on link 0 CPU_CLUSTER: 0
9284 12:18:46.343154 CPU_CLUSTER: 0 child on link 0 CPU: 00
9285 12:18:46.353302 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9286 12:18:46.353892 CPU: 00
9287 12:18:46.356262 Root Device assign_resources, bus 0 link: 0
9288 12:18:46.360260 CPU_CLUSTER: 0 missing set_resources
9289 12:18:46.363588 Root Device assign_resources, bus 0 link: 0 done
9290 12:18:46.366858 Done setting resources.
9291 12:18:46.373235 Show resources in subtree (Root Device)...After assigning values.
9292 12:18:46.376468 Root Device child on link 0 CPU_CLUSTER: 0
9293 12:18:46.380066 CPU_CLUSTER: 0 child on link 0 CPU: 00
9294 12:18:46.390470 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9295 12:18:46.391078 CPU: 00
9296 12:18:46.393458 Done allocating resources.
9297 12:18:46.397096 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9298 12:18:46.400211 Enabling resources...
9299 12:18:46.400805 done.
9300 12:18:46.406899 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9301 12:18:46.407466 Initializing devices...
9302 12:18:46.410311 Root Device init
9303 12:18:46.410874 init hardware done!
9304 12:18:46.413551 0x00000018: ctrlr->caps
9305 12:18:46.417226 52.000 MHz: ctrlr->f_max
9306 12:18:46.417804 0.400 MHz: ctrlr->f_min
9307 12:18:46.419953 0x40ff8080: ctrlr->voltages
9308 12:18:46.420539 sclk: 390625
9309 12:18:46.423346 Bus Width = 1
9310 12:18:46.423914 sclk: 390625
9311 12:18:46.424289 Bus Width = 1
9312 12:18:46.426843 Early init status = 3
9313 12:18:46.433656 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9314 12:18:46.437098 in-header: 03 fc 00 00 01 00 00 00
9315 12:18:46.437662 in-data: 00
9316 12:18:46.443526 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9317 12:18:46.446667 in-header: 03 fd 00 00 00 00 00 00
9318 12:18:46.450002 in-data:
9319 12:18:46.453163 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9320 12:18:46.456743 in-header: 03 fc 00 00 01 00 00 00
9321 12:18:46.459884 in-data: 00
9322 12:18:46.463195 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9323 12:18:46.468595 in-header: 03 fd 00 00 00 00 00 00
9324 12:18:46.471764 in-data:
9325 12:18:46.474934 [SSUSB] Setting up USB HOST controller...
9326 12:18:46.478897 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9327 12:18:46.482076 [SSUSB] phy power-on done.
9328 12:18:46.485330 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9329 12:18:46.492138 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9330 12:18:46.495150 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9331 12:18:46.501761 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9332 12:18:46.508485 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9333 12:18:46.515173 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9334 12:18:46.521913 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9335 12:18:46.528455 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9336 12:18:46.531424 SPM: binary array size = 0x9dc
9337 12:18:46.535343 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9338 12:18:46.542166 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9339 12:18:46.548344 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9340 12:18:46.554769 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9341 12:18:46.558048 configure_display: Starting display init
9342 12:18:46.592268 anx7625_power_on_init: Init interface.
9343 12:18:46.595295 anx7625_disable_pd_protocol: Disabled PD feature.
9344 12:18:46.598562 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9345 12:18:46.626651 anx7625_start_dp_work: Secure OCM version=00
9346 12:18:46.629790 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9347 12:18:46.644856 sp_tx_get_edid_block: EDID Block = 1
9348 12:18:46.747479 Extracted contents:
9349 12:18:46.750435 header: 00 ff ff ff ff ff ff 00
9350 12:18:46.753687 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9351 12:18:46.757009 version: 01 04
9352 12:18:46.760558 basic params: 95 1f 11 78 0a
9353 12:18:46.763661 chroma info: 76 90 94 55 54 90 27 21 50 54
9354 12:18:46.766960 established: 00 00 00
9355 12:18:46.773717 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9356 12:18:46.776752 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9357 12:18:46.783384 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9358 12:18:46.790095 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9359 12:18:46.796380 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9360 12:18:46.799608 extensions: 00
9361 12:18:46.800058 checksum: fb
9362 12:18:46.800413
9363 12:18:46.802983 Manufacturer: IVO Model 57d Serial Number 0
9364 12:18:46.806397 Made week 0 of 2020
9365 12:18:46.809462 EDID version: 1.4
9366 12:18:46.809911 Digital display
9367 12:18:46.813175 6 bits per primary color channel
9368 12:18:46.813634 DisplayPort interface
9369 12:18:46.816491 Maximum image size: 31 cm x 17 cm
9370 12:18:46.820279 Gamma: 220%
9371 12:18:46.820847 Check DPMS levels
9372 12:18:46.823254 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9373 12:18:46.830108 First detailed timing is preferred timing
9374 12:18:46.830565 Established timings supported:
9375 12:18:46.833764 Standard timings supported:
9376 12:18:46.836564 Detailed timings
9377 12:18:46.839707 Hex of detail: 383680a07038204018303c0035ae10000019
9378 12:18:46.843393 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9379 12:18:46.850111 0780 0798 07c8 0820 hborder 0
9380 12:18:46.853365 0438 043b 0447 0458 vborder 0
9381 12:18:46.856472 -hsync -vsync
9382 12:18:46.856925 Did detailed timing
9383 12:18:46.863707 Hex of detail: 000000000000000000000000000000000000
9384 12:18:46.864256 Manufacturer-specified data, tag 0
9385 12:18:46.869731 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9386 12:18:46.870310 ASCII string: InfoVision
9387 12:18:46.876463 Hex of detail: 000000fe00523134304e574635205248200a
9388 12:18:46.879729 ASCII string: R140NWF5 RH
9389 12:18:46.880178 Checksum
9390 12:18:46.880529 Checksum: 0xfb (valid)
9391 12:18:46.886476 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9392 12:18:46.889702 DSI data_rate: 832800000 bps
9393 12:18:46.893301 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9394 12:18:46.900084 anx7625_parse_edid: pixelclock(138800).
9395 12:18:46.903224 hactive(1920), hsync(48), hfp(24), hbp(88)
9396 12:18:46.906637 vactive(1080), vsync(12), vfp(3), vbp(17)
9397 12:18:46.909813 anx7625_dsi_config: config dsi.
9398 12:18:46.916523 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9399 12:18:46.929316 anx7625_dsi_config: success to config DSI
9400 12:18:46.932337 anx7625_dp_start: MIPI phy setup OK.
9401 12:18:46.935995 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9402 12:18:46.939361 mtk_ddp_mode_set invalid vrefresh 60
9403 12:18:46.942340 main_disp_path_setup
9404 12:18:46.942892 ovl_layer_smi_id_en
9405 12:18:46.945737 ovl_layer_smi_id_en
9406 12:18:46.946335 ccorr_config
9407 12:18:46.946695 aal_config
9408 12:18:46.948816 gamma_config
9409 12:18:46.949264 postmask_config
9410 12:18:46.952517 dither_config
9411 12:18:46.956060 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9412 12:18:46.962565 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9413 12:18:46.966033 Root Device init finished in 553 msecs
9414 12:18:46.966585 CPU_CLUSTER: 0 init
9415 12:18:46.975811 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9416 12:18:46.978989 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9417 12:18:46.981992 APU_MBOX 0x190000b0 = 0x10001
9418 12:18:46.985675 APU_MBOX 0x190001b0 = 0x10001
9419 12:18:46.988690 APU_MBOX 0x190005b0 = 0x10001
9420 12:18:46.991938 APU_MBOX 0x190006b0 = 0x10001
9421 12:18:46.995289 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9422 12:18:47.008605 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9423 12:18:47.020554 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9424 12:18:47.027434 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9425 12:18:47.038792 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9426 12:18:47.047632 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9427 12:18:47.051188 CPU_CLUSTER: 0 init finished in 81 msecs
9428 12:18:47.054823 Devices initialized
9429 12:18:47.057561 Show all devs... After init.
9430 12:18:47.058059 Root Device: enabled 1
9431 12:18:47.061441 CPU_CLUSTER: 0: enabled 1
9432 12:18:47.064781 CPU: 00: enabled 1
9433 12:18:47.068590 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9434 12:18:47.071299 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9435 12:18:47.074189 ELOG: NV offset 0x57f000 size 0x1000
9436 12:18:47.081224 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9437 12:18:47.087534 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9438 12:18:47.090868 ELOG: Event(17) added with size 13 at 2024-01-31 12:18:10 UTC
9439 12:18:47.094370 out: cmd=0x121: 03 db 21 01 00 00 00 00
9440 12:18:47.098387 in-header: 03 1d 00 00 2c 00 00 00
9441 12:18:47.111551 in-data: 42 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9442 12:18:47.118018 ELOG: Event(A1) added with size 10 at 2024-01-31 12:18:10 UTC
9443 12:18:47.124565 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9444 12:18:47.131203 ELOG: Event(A0) added with size 9 at 2024-01-31 12:18:10 UTC
9445 12:18:47.134520 elog_add_boot_reason: Logged dev mode boot
9446 12:18:47.137873 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9447 12:18:47.141301 Finalize devices...
9448 12:18:47.141869 Devices finalized
9449 12:18:47.148001 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9450 12:18:47.151116 Writing coreboot table at 0xffe64000
9451 12:18:47.154587 0. 000000000010a000-0000000000113fff: RAMSTAGE
9452 12:18:47.157704 1. 0000000040000000-00000000400fffff: RAM
9453 12:18:47.164580 2. 0000000040100000-000000004032afff: RAMSTAGE
9454 12:18:47.168303 3. 000000004032b000-00000000545fffff: RAM
9455 12:18:47.171187 4. 0000000054600000-000000005465ffff: BL31
9456 12:18:47.174141 5. 0000000054660000-00000000ffe63fff: RAM
9457 12:18:47.181083 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9458 12:18:47.185279 7. 0000000100000000-000000023fffffff: RAM
9459 12:18:47.185859 Passing 5 GPIOs to payload:
9460 12:18:47.191198 NAME | PORT | POLARITY | VALUE
9461 12:18:47.194067 EC in RW | 0x000000aa | low | undefined
9462 12:18:47.200805 EC interrupt | 0x00000005 | low | undefined
9463 12:18:47.204243 TPM interrupt | 0x000000ab | high | undefined
9464 12:18:47.207442 SD card detect | 0x00000011 | high | undefined
9465 12:18:47.214522 speaker enable | 0x00000093 | high | undefined
9466 12:18:47.217857 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9467 12:18:47.221211 in-header: 03 f9 00 00 02 00 00 00
9468 12:18:47.221787 in-data: 02 00
9469 12:18:47.224248 ADC[4]: Raw value=901032 ID=7
9470 12:18:47.227948 ADC[3]: Raw value=212810 ID=1
9471 12:18:47.228423 RAM Code: 0x71
9472 12:18:47.230608 ADC[6]: Raw value=74502 ID=0
9473 12:18:47.234467 ADC[5]: Raw value=212072 ID=1
9474 12:18:47.234936 SKU Code: 0x1
9475 12:18:47.240748 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3f73
9476 12:18:47.244137 coreboot table: 964 bytes.
9477 12:18:47.248083 IMD ROOT 0. 0xfffff000 0x00001000
9478 12:18:47.250885 IMD SMALL 1. 0xffffe000 0x00001000
9479 12:18:47.254148 RO MCACHE 2. 0xffffc000 0x00001104
9480 12:18:47.257794 CONSOLE 3. 0xfff7c000 0x00080000
9481 12:18:47.260887 FMAP 4. 0xfff7b000 0x00000452
9482 12:18:47.264253 TIME STAMP 5. 0xfff7a000 0x00000910
9483 12:18:47.267487 VBOOT WORK 6. 0xfff66000 0x00014000
9484 12:18:47.270871 RAMOOPS 7. 0xffe66000 0x00100000
9485 12:18:47.274169 COREBOOT 8. 0xffe64000 0x00002000
9486 12:18:47.274637 IMD small region:
9487 12:18:47.277540 IMD ROOT 0. 0xffffec00 0x00000400
9488 12:18:47.280811 VPD 1. 0xffffeb80 0x0000006c
9489 12:18:47.284234 MMC STATUS 2. 0xffffeb60 0x00000004
9490 12:18:47.290633 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9491 12:18:47.294120 Probing TPM: done!
9492 12:18:47.297006 Connected to device vid:did:rid of 1ae0:0028:00
9493 12:18:47.307147 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9494 12:18:47.310915 Initialized TPM device CR50 revision 0
9495 12:18:47.314461 Checking cr50 for pending updates
9496 12:18:47.317799 Reading cr50 TPM mode
9497 12:18:47.326214 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9498 12:18:47.332796 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9499 12:18:47.373249 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9500 12:18:47.376511 Checking segment from ROM address 0x40100000
9501 12:18:47.379494 Checking segment from ROM address 0x4010001c
9502 12:18:47.386250 Loading segment from ROM address 0x40100000
9503 12:18:47.386816 code (compression=0)
9504 12:18:47.396590 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9505 12:18:47.402842 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9506 12:18:47.403391 it's not compressed!
9507 12:18:47.409765 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9508 12:18:47.412979 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9509 12:18:47.433036 Loading segment from ROM address 0x4010001c
9510 12:18:47.433584 Entry Point 0x80000000
9511 12:18:47.436784 Loaded segments
9512 12:18:47.439947 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9513 12:18:47.446940 Jumping to boot code at 0x80000000(0xffe64000)
9514 12:18:47.453364 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9515 12:18:47.460263 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9516 12:18:47.467731 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9517 12:18:47.471239 Checking segment from ROM address 0x40100000
9518 12:18:47.474614 Checking segment from ROM address 0x4010001c
9519 12:18:47.481290 Loading segment from ROM address 0x40100000
9520 12:18:47.481758 code (compression=1)
9521 12:18:47.488346 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9522 12:18:47.498071 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9523 12:18:47.498634 using LZMA
9524 12:18:47.506382 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9525 12:18:47.513202 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9526 12:18:47.516544 Loading segment from ROM address 0x4010001c
9527 12:18:47.517109 Entry Point 0x54601000
9528 12:18:47.520181 Loaded segments
9529 12:18:47.523000 NOTICE: MT8192 bl31_setup
9530 12:18:47.529774 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9531 12:18:47.533147 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9532 12:18:47.536500 WARNING: region 0:
9533 12:18:47.540007 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9534 12:18:47.540573 WARNING: region 1:
9535 12:18:47.546441 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9536 12:18:47.549650 WARNING: region 2:
9537 12:18:47.554008 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9538 12:18:47.556671 WARNING: region 3:
9539 12:18:47.559901 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9540 12:18:47.563117 WARNING: region 4:
9541 12:18:47.570065 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9542 12:18:47.570629 WARNING: region 5:
9543 12:18:47.573027 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9544 12:18:47.576219 WARNING: region 6:
9545 12:18:47.579673 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9546 12:18:47.580135 WARNING: region 7:
9547 12:18:47.586125 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9548 12:18:47.593526 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9549 12:18:47.596364 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9550 12:18:47.599795 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9551 12:18:47.606592 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9552 12:18:47.609597 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9553 12:18:47.612681 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9554 12:18:47.619950 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9555 12:18:47.622922 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9556 12:18:47.629173 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9557 12:18:47.632720 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9558 12:18:47.635943 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9559 12:18:47.642936 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9560 12:18:47.646134 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9561 12:18:47.649397 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9562 12:18:47.656507 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9563 12:18:47.659243 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9564 12:18:47.666063 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9565 12:18:47.669789 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9566 12:18:47.672665 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9567 12:18:47.679157 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9568 12:18:47.682595 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9569 12:18:47.685886 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9570 12:18:47.693125 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9571 12:18:47.696073 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9572 12:18:47.702864 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9573 12:18:47.706159 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9574 12:18:47.709767 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9575 12:18:47.716180 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9576 12:18:47.719657 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9577 12:18:47.726638 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9578 12:18:47.729571 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9579 12:18:47.732893 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9580 12:18:47.739470 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9581 12:18:47.743194 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9582 12:18:47.746322 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9583 12:18:47.749736 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9584 12:18:47.756358 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9585 12:18:47.759662 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9586 12:18:47.763382 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9587 12:18:47.766674 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9588 12:18:47.769860 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9589 12:18:47.776560 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9590 12:18:47.779735 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9591 12:18:47.783092 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9592 12:18:47.786642 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9593 12:18:47.793411 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9594 12:18:47.796660 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9595 12:18:47.799895 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9596 12:18:47.806913 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9597 12:18:47.809980 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9598 12:18:47.816915 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9599 12:18:47.819775 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9600 12:18:47.823342 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9601 12:18:47.830138 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9602 12:18:47.833511 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9603 12:18:47.839893 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9604 12:18:47.843039 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9605 12:18:47.846365 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9606 12:18:47.852980 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9607 12:18:47.856804 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9608 12:18:47.863352 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9609 12:18:47.866406 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9610 12:18:47.873309 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9611 12:18:47.876419 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9612 12:18:47.882955 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9613 12:18:47.886804 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9614 12:18:47.889818 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9615 12:18:47.897172 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9616 12:18:47.900437 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9617 12:18:47.906904 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9618 12:18:47.910250 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9619 12:18:47.917237 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9620 12:18:47.920429 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9621 12:18:47.923378 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9622 12:18:47.930015 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9623 12:18:47.933411 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9624 12:18:47.939744 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9625 12:18:47.943257 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9626 12:18:47.950036 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9627 12:18:47.952982 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9628 12:18:47.960176 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9629 12:18:47.963233 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9630 12:18:47.966681 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9631 12:18:47.973256 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9632 12:18:47.976458 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9633 12:18:47.982914 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9634 12:18:47.986894 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9635 12:18:47.990025 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9636 12:18:47.996568 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9637 12:18:47.999801 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9638 12:18:48.006668 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9639 12:18:48.010891 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9640 12:18:48.016703 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9641 12:18:48.020147 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9642 12:18:48.026749 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9643 12:18:48.030105 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9644 12:18:48.033306 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9645 12:18:48.036954 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9646 12:18:48.043758 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9647 12:18:48.046337 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9648 12:18:48.049563 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9649 12:18:48.057011 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9650 12:18:48.059818 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9651 12:18:48.063492 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9652 12:18:48.069984 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9653 12:18:48.072699 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9654 12:18:48.079631 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9655 12:18:48.082984 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9656 12:18:48.086495 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9657 12:18:48.093230 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9658 12:18:48.097125 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9659 12:18:48.103147 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9660 12:18:48.106380 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9661 12:18:48.109895 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9662 12:18:48.116462 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9663 12:18:48.119787 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9664 12:18:48.123110 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9665 12:18:48.130010 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9666 12:18:48.133504 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9667 12:18:48.136639 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9668 12:18:48.139491 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9669 12:18:48.146454 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9670 12:18:48.149506 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9671 12:18:48.153111 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9672 12:18:48.159721 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9673 12:18:48.162977 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9674 12:18:48.166515 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9675 12:18:48.173356 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9676 12:18:48.176900 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9677 12:18:48.183298 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9678 12:18:48.186612 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9679 12:18:48.190175 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9680 12:18:48.196957 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9681 12:18:48.200268 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9682 12:18:48.203541 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9683 12:18:48.209868 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9684 12:18:48.213471 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9685 12:18:48.220258 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9686 12:18:48.223482 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9687 12:18:48.226537 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9688 12:18:48.233622 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9689 12:18:48.236858 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9690 12:18:48.243228 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9691 12:18:48.246693 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9692 12:18:48.250064 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9693 12:18:48.256607 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9694 12:18:48.259844 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9695 12:18:48.263021 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9696 12:18:48.269857 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9697 12:18:48.273591 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9698 12:18:48.279593 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9699 12:18:48.283205 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9700 12:18:48.286473 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9701 12:18:48.293321 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9702 12:18:48.296279 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9703 12:18:48.303179 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9704 12:18:48.306700 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9705 12:18:48.309646 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9706 12:18:48.316496 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9707 12:18:48.320045 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9708 12:18:48.326876 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9709 12:18:48.329564 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9710 12:18:48.333162 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9711 12:18:48.339723 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9712 12:18:48.342842 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9713 12:18:48.346589 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9714 12:18:48.353075 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9715 12:18:48.356467 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9716 12:18:48.363263 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9717 12:18:48.366193 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9718 12:18:48.369857 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9719 12:18:48.376302 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9720 12:18:48.379284 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9721 12:18:48.386217 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9722 12:18:48.389293 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9723 12:18:48.392807 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9724 12:18:48.399754 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9725 12:18:48.402870 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9726 12:18:48.409681 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9727 12:18:48.412387 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9728 12:18:48.416249 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9729 12:18:48.422385 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9730 12:18:48.426168 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9731 12:18:48.432780 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9732 12:18:48.435825 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9733 12:18:48.439433 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9734 12:18:48.446027 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9735 12:18:48.449319 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9736 12:18:48.455791 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9737 12:18:48.459449 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9738 12:18:48.462644 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9739 12:18:48.468838 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9740 12:18:48.472290 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9741 12:18:48.478745 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9742 12:18:48.482534 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9743 12:18:48.485384 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9744 12:18:48.492638 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9745 12:18:48.495161 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9746 12:18:48.502145 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9747 12:18:48.505677 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9748 12:18:48.511970 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9749 12:18:48.515135 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9750 12:18:48.518551 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9751 12:18:48.525227 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9752 12:18:48.528634 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9753 12:18:48.534967 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9754 12:18:48.538584 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9755 12:18:48.545032 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9756 12:18:48.548142 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9757 12:18:48.551750 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9758 12:18:48.558362 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9759 12:18:48.561467 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9760 12:18:48.568394 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9761 12:18:48.571449 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9762 12:18:48.574992 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9763 12:18:48.581665 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9764 12:18:48.584794 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9765 12:18:48.591419 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9766 12:18:48.594600 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9767 12:18:48.602093 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9768 12:18:48.604602 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9769 12:18:48.608211 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9770 12:18:48.614528 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9771 12:18:48.618053 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9772 12:18:48.624672 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9773 12:18:48.628193 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9774 12:18:48.634750 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9775 12:18:48.638258 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9776 12:18:48.641180 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9777 12:18:48.644964 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9778 12:18:48.651246 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9779 12:18:48.654522 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9780 12:18:48.658125 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9781 12:18:48.661262 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9782 12:18:48.668068 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9783 12:18:48.671172 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9784 12:18:48.678242 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9785 12:18:48.680871 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9786 12:18:48.684156 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9787 12:18:48.690784 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9788 12:18:48.694141 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9789 12:18:48.697555 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9790 12:18:48.703989 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9791 12:18:48.707484 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9792 12:18:48.714237 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9793 12:18:48.718103 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9794 12:18:48.721076 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9795 12:18:48.727556 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9796 12:18:48.730849 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9797 12:18:48.734497 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9798 12:18:48.740820 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9799 12:18:48.744074 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9800 12:18:48.750812 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9801 12:18:48.753992 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9802 12:18:48.757268 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9803 12:18:48.764030 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9804 12:18:48.767179 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9805 12:18:48.770632 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9806 12:18:48.777065 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9807 12:18:48.780260 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9808 12:18:48.783721 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9809 12:18:48.790297 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9810 12:18:48.793931 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9811 12:18:48.796868 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9812 12:18:48.803688 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9813 12:18:48.807092 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9814 12:18:48.813820 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9815 12:18:48.817543 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9816 12:18:48.820542 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9817 12:18:48.824327 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9818 12:18:48.830655 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9819 12:18:48.833894 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9820 12:18:48.837256 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9821 12:18:48.840391 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9822 12:18:48.846894 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9823 12:18:48.850149 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9824 12:18:48.853592 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9825 12:18:48.857107 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9826 12:18:48.863708 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9827 12:18:48.866891 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9828 12:18:48.870520 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9829 12:18:48.873383 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9830 12:18:48.880085 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9831 12:18:48.883529 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9832 12:18:48.890019 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9833 12:18:48.893819 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9834 12:18:48.899981 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9835 12:18:48.903649 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9836 12:18:48.907031 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9837 12:18:48.913660 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9838 12:18:48.916756 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9839 12:18:48.923286 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9840 12:18:48.926795 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9841 12:18:48.930002 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9842 12:18:48.936870 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9843 12:18:48.940046 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9844 12:18:48.946201 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9845 12:18:48.949426 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9846 12:18:48.952980 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9847 12:18:48.959481 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9848 12:18:48.963037 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9849 12:18:48.969573 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9850 12:18:48.972514 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9851 12:18:48.979054 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9852 12:18:48.982360 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9853 12:18:48.985923 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9854 12:18:48.992592 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9855 12:18:48.995906 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9856 12:18:49.002270 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9857 12:18:49.005885 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9858 12:18:49.012390 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9859 12:18:49.015517 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9860 12:18:49.018968 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9861 12:18:49.025607 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9862 12:18:49.029017 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9863 12:18:49.035365 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9864 12:18:49.038698 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9865 12:18:49.042165 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9866 12:18:49.048367 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9867 12:18:49.051934 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9868 12:18:49.058880 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9869 12:18:49.062026 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9870 12:18:49.065514 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9871 12:18:49.071843 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9872 12:18:49.075430 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9873 12:18:49.081877 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9874 12:18:49.085074 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9875 12:18:49.092317 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9876 12:18:49.095292 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9877 12:18:49.098567 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9878 12:18:49.105166 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9879 12:18:49.108315 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9880 12:18:49.115044 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9881 12:18:49.118586 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9882 12:18:49.121771 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9883 12:18:49.128388 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9884 12:18:49.131391 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9885 12:18:49.138415 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9886 12:18:49.141988 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9887 12:18:49.144986 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9888 12:18:49.151672 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9889 12:18:49.155032 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9890 12:18:49.161705 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9891 12:18:49.165392 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9892 12:18:49.171314 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9893 12:18:49.174659 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9894 12:18:49.177934 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9895 12:18:49.184691 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9896 12:18:49.188009 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9897 12:18:49.191356 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9898 12:18:49.198045 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9899 12:18:49.201457 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9900 12:18:49.207843 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9901 12:18:49.211208 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9902 12:18:49.214469 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9903 12:18:49.221339 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9904 12:18:49.224601 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9905 12:18:49.231394 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9906 12:18:49.234921 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9907 12:18:49.241292 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9908 12:18:49.244363 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9909 12:18:49.251266 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9910 12:18:49.254783 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9911 12:18:49.257890 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9912 12:18:49.264806 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9913 12:18:49.268005 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9914 12:18:49.274385 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9915 12:18:49.277863 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9916 12:18:49.284084 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9917 12:18:49.287499 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9918 12:18:49.294041 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9919 12:18:49.297685 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9920 12:18:49.300517 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9921 12:18:49.307286 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9922 12:18:49.310626 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9923 12:18:49.317242 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9924 12:18:49.321002 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9925 12:18:49.327210 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9926 12:18:49.330812 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9927 12:18:49.334023 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9928 12:18:49.340705 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9929 12:18:49.343984 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9930 12:18:49.350624 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9931 12:18:49.354063 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9932 12:18:49.360641 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9933 12:18:49.363592 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9934 12:18:49.367745 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9935 12:18:49.373838 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9936 12:18:49.377260 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9937 12:18:49.383715 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9938 12:18:49.387268 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9939 12:18:49.393619 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9940 12:18:49.397093 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9941 12:18:49.400410 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9942 12:18:49.406773 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9943 12:18:49.410541 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9944 12:18:49.416682 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9945 12:18:49.420621 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9946 12:18:49.426734 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9947 12:18:49.430750 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9948 12:18:49.436670 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9949 12:18:49.440307 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9950 12:18:49.443540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9951 12:18:49.450087 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9952 12:18:49.453639 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9953 12:18:49.460083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9954 12:18:49.463346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9955 12:18:49.470452 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9956 12:18:49.473521 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9957 12:18:49.480002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9958 12:18:49.483444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9959 12:18:49.489614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9960 12:18:49.493601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9961 12:18:49.499596 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9962 12:18:49.503202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9963 12:18:49.506439 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9964 12:18:49.513257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9965 12:18:49.517072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9966 12:18:49.523089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9967 12:18:49.526492 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9968 12:18:49.533001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9969 12:18:49.536041 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9970 12:18:49.542937 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9971 12:18:49.546057 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9972 12:18:49.553113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9973 12:18:49.556406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9974 12:18:49.562842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9975 12:18:49.565919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9976 12:18:49.573093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9977 12:18:49.576467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9978 12:18:49.583140 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9979 12:18:49.586383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9980 12:18:49.592804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9981 12:18:49.596140 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9982 12:18:49.602751 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9983 12:18:49.603225 INFO: [APUAPC] vio 0
9984 12:18:49.609423 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9985 12:18:49.612945 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9986 12:18:49.616363 INFO: [APUAPC] D0_APC_0: 0x400510
9987 12:18:49.619957 INFO: [APUAPC] D0_APC_1: 0x0
9988 12:18:49.622698 INFO: [APUAPC] D0_APC_2: 0x1540
9989 12:18:49.626514 INFO: [APUAPC] D0_APC_3: 0x0
9990 12:18:49.629276 INFO: [APUAPC] D1_APC_0: 0xffffffff
9991 12:18:49.632919 INFO: [APUAPC] D1_APC_1: 0xffffffff
9992 12:18:49.636128 INFO: [APUAPC] D1_APC_2: 0x3fffff
9993 12:18:49.639021 INFO: [APUAPC] D1_APC_3: 0x0
9994 12:18:49.642558 INFO: [APUAPC] D2_APC_0: 0xffffffff
9995 12:18:49.646091 INFO: [APUAPC] D2_APC_1: 0xffffffff
9996 12:18:49.649461 INFO: [APUAPC] D2_APC_2: 0x3fffff
9997 12:18:49.652955 INFO: [APUAPC] D2_APC_3: 0x0
9998 12:18:49.655747 INFO: [APUAPC] D3_APC_0: 0xffffffff
9999 12:18:49.659266 INFO: [APUAPC] D3_APC_1: 0xffffffff
10000 12:18:49.662821 INFO: [APUAPC] D3_APC_2: 0x3fffff
10001 12:18:49.665787 INFO: [APUAPC] D3_APC_3: 0x0
10002 12:18:49.668938 INFO: [APUAPC] D4_APC_0: 0xffffffff
10003 12:18:49.672172 INFO: [APUAPC] D4_APC_1: 0xffffffff
10004 12:18:49.676045 INFO: [APUAPC] D4_APC_2: 0x3fffff
10005 12:18:49.678938 INFO: [APUAPC] D4_APC_3: 0x0
10006 12:18:49.682336 INFO: [APUAPC] D5_APC_0: 0xffffffff
10007 12:18:49.685995 INFO: [APUAPC] D5_APC_1: 0xffffffff
10008 12:18:49.689017 INFO: [APUAPC] D5_APC_2: 0x3fffff
10009 12:18:49.689488 INFO: [APUAPC] D5_APC_3: 0x0
10010 12:18:49.692159 INFO: [APUAPC] D6_APC_0: 0xffffffff
10011 12:18:49.698978 INFO: [APUAPC] D6_APC_1: 0xffffffff
10012 12:18:49.702104 INFO: [APUAPC] D6_APC_2: 0x3fffff
10013 12:18:49.702675 INFO: [APUAPC] D6_APC_3: 0x0
10014 12:18:49.706241 INFO: [APUAPC] D7_APC_0: 0xffffffff
10015 12:18:49.711972 INFO: [APUAPC] D7_APC_1: 0xffffffff
10016 12:18:49.715873 INFO: [APUAPC] D7_APC_2: 0x3fffff
10017 12:18:49.716452 INFO: [APUAPC] D7_APC_3: 0x0
10018 12:18:49.718702 INFO: [APUAPC] D8_APC_0: 0xffffffff
10019 12:18:49.722000 INFO: [APUAPC] D8_APC_1: 0xffffffff
10020 12:18:49.725236 INFO: [APUAPC] D8_APC_2: 0x3fffff
10021 12:18:49.728413 INFO: [APUAPC] D8_APC_3: 0x0
10022 12:18:49.732006 INFO: [APUAPC] D9_APC_0: 0xffffffff
10023 12:18:49.735203 INFO: [APUAPC] D9_APC_1: 0xffffffff
10024 12:18:49.738882 INFO: [APUAPC] D9_APC_2: 0x3fffff
10025 12:18:49.741997 INFO: [APUAPC] D9_APC_3: 0x0
10026 12:18:49.745513 INFO: [APUAPC] D10_APC_0: 0xffffffff
10027 12:18:49.748966 INFO: [APUAPC] D10_APC_1: 0xffffffff
10028 12:18:49.751764 INFO: [APUAPC] D10_APC_2: 0x3fffff
10029 12:18:49.755243 INFO: [APUAPC] D10_APC_3: 0x0
10030 12:18:49.758497 INFO: [APUAPC] D11_APC_0: 0xffffffff
10031 12:18:49.762322 INFO: [APUAPC] D11_APC_1: 0xffffffff
10032 12:18:49.765131 INFO: [APUAPC] D11_APC_2: 0x3fffff
10033 12:18:49.768428 INFO: [APUAPC] D11_APC_3: 0x0
10034 12:18:49.771926 INFO: [APUAPC] D12_APC_0: 0xffffffff
10035 12:18:49.775192 INFO: [APUAPC] D12_APC_1: 0xffffffff
10036 12:18:49.778243 INFO: [APUAPC] D12_APC_2: 0x3fffff
10037 12:18:49.781522 INFO: [APUAPC] D12_APC_3: 0x0
10038 12:18:49.785313 INFO: [APUAPC] D13_APC_0: 0xffffffff
10039 12:18:49.788610 INFO: [APUAPC] D13_APC_1: 0xffffffff
10040 12:18:49.791503 INFO: [APUAPC] D13_APC_2: 0x3fffff
10041 12:18:49.794886 INFO: [APUAPC] D13_APC_3: 0x0
10042 12:18:49.798339 INFO: [APUAPC] D14_APC_0: 0xffffffff
10043 12:18:49.801691 INFO: [APUAPC] D14_APC_1: 0xffffffff
10044 12:18:49.804765 INFO: [APUAPC] D14_APC_2: 0x3fffff
10045 12:18:49.808180 INFO: [APUAPC] D14_APC_3: 0x0
10046 12:18:49.811488 INFO: [APUAPC] D15_APC_0: 0xffffffff
10047 12:18:49.814643 INFO: [APUAPC] D15_APC_1: 0xffffffff
10048 12:18:49.821484 INFO: [APUAPC] D15_APC_2: 0x3fffff
10049 12:18:49.822081 INFO: [APUAPC] D15_APC_3: 0x0
10050 12:18:49.824885 INFO: [APUAPC] APC_CON: 0x4
10051 12:18:49.828460 INFO: [NOCDAPC] D0_APC_0: 0x0
10052 12:18:49.831428 INFO: [NOCDAPC] D0_APC_1: 0x0
10053 12:18:49.834488 INFO: [NOCDAPC] D1_APC_0: 0x0
10054 12:18:49.838084 INFO: [NOCDAPC] D1_APC_1: 0xfff
10055 12:18:49.841411 INFO: [NOCDAPC] D2_APC_0: 0x0
10056 12:18:49.845215 INFO: [NOCDAPC] D2_APC_1: 0xfff
10057 12:18:49.845783 INFO: [NOCDAPC] D3_APC_0: 0x0
10058 12:18:49.848374 INFO: [NOCDAPC] D3_APC_1: 0xfff
10059 12:18:49.851091 INFO: [NOCDAPC] D4_APC_0: 0x0
10060 12:18:49.854600 INFO: [NOCDAPC] D4_APC_1: 0xfff
10061 12:18:49.857840 INFO: [NOCDAPC] D5_APC_0: 0x0
10062 12:18:49.861112 INFO: [NOCDAPC] D5_APC_1: 0xfff
10063 12:18:49.864589 INFO: [NOCDAPC] D6_APC_0: 0x0
10064 12:18:49.868208 INFO: [NOCDAPC] D6_APC_1: 0xfff
10065 12:18:49.871240 INFO: [NOCDAPC] D7_APC_0: 0x0
10066 12:18:49.874847 INFO: [NOCDAPC] D7_APC_1: 0xfff
10067 12:18:49.878119 INFO: [NOCDAPC] D8_APC_0: 0x0
10068 12:18:49.881794 INFO: [NOCDAPC] D8_APC_1: 0xfff
10069 12:18:49.882413 INFO: [NOCDAPC] D9_APC_0: 0x0
10070 12:18:49.884455 INFO: [NOCDAPC] D9_APC_1: 0xfff
10071 12:18:49.887852 INFO: [NOCDAPC] D10_APC_0: 0x0
10072 12:18:49.891456 INFO: [NOCDAPC] D10_APC_1: 0xfff
10073 12:18:49.894459 INFO: [NOCDAPC] D11_APC_0: 0x0
10074 12:18:49.897800 INFO: [NOCDAPC] D11_APC_1: 0xfff
10075 12:18:49.901102 INFO: [NOCDAPC] D12_APC_0: 0x0
10076 12:18:49.904392 INFO: [NOCDAPC] D12_APC_1: 0xfff
10077 12:18:49.908177 INFO: [NOCDAPC] D13_APC_0: 0x0
10078 12:18:49.911002 INFO: [NOCDAPC] D13_APC_1: 0xfff
10079 12:18:49.914489 INFO: [NOCDAPC] D14_APC_0: 0x0
10080 12:18:49.917847 INFO: [NOCDAPC] D14_APC_1: 0xfff
10081 12:18:49.921093 INFO: [NOCDAPC] D15_APC_0: 0x0
10082 12:18:49.924098 INFO: [NOCDAPC] D15_APC_1: 0xfff
10083 12:18:49.924667 INFO: [NOCDAPC] APC_CON: 0x4
10084 12:18:49.927577 INFO: [APUAPC] set_apusys_apc done
10085 12:18:49.930790 INFO: [DEVAPC] devapc_init done
10086 12:18:49.937322 INFO: GICv3 without legacy support detected.
10087 12:18:49.940678 INFO: ARM GICv3 driver initialized in EL3
10088 12:18:49.944307 INFO: Maximum SPI INTID supported: 639
10089 12:18:49.947362 INFO: BL31: Initializing runtime services
10090 12:18:49.954040 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10091 12:18:49.957526 INFO: SPM: enable CPC mode
10092 12:18:49.960899 INFO: mcdi ready for mcusys-off-idle and system suspend
10093 12:18:49.967316 INFO: BL31: Preparing for EL3 exit to normal world
10094 12:18:49.970520 INFO: Entry point address = 0x80000000
10095 12:18:49.971089 INFO: SPSR = 0x8
10096 12:18:49.978067
10097 12:18:49.978653
10098 12:18:49.979026
10099 12:18:49.981206 Starting depthcharge on Spherion...
10100 12:18:49.981772
10101 12:18:49.982208 Wipe memory regions:
10102 12:18:49.982560
10103 12:18:49.984969 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10104 12:18:49.985517 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10105 12:18:49.985996 Setting prompt string to ['asurada:']
10106 12:18:49.986445 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10107 12:18:49.987159 [0x00000040000000, 0x00000054600000)
10108 12:18:50.106480
10109 12:18:50.107037 [0x00000054660000, 0x00000080000000)
10110 12:18:50.367278
10111 12:18:50.367841 [0x000000821a7280, 0x000000ffe64000)
10112 12:18:51.112333
10113 12:18:51.112891 [0x00000100000000, 0x00000240000000)
10114 12:18:53.002398
10115 12:18:53.005647 Initializing XHCI USB controller at 0x11200000.
10116 12:18:54.043501
10117 12:18:54.046717 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10118 12:18:54.047185
10119 12:18:54.047567
10120 12:18:54.047913
10121 12:18:54.048698 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10123 12:18:54.150220 asurada: tftpboot 192.168.201.1 12669536/tftp-deploy-ij7nhhg4/kernel/image.itb 12669536/tftp-deploy-ij7nhhg4/kernel/cmdline
10124 12:18:54.150886 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10125 12:18:54.151366 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10126 12:18:54.155635 tftpboot 192.168.201.1 12669536/tftp-deploy-ij7nhhg4/kernel/image.ittp-deploy-ij7nhhg4/kernel/cmdline
10127 12:18:54.156112
10128 12:18:54.156481 Waiting for link
10129 12:18:54.316405
10130 12:18:54.317187 R8152: Initializing
10131 12:18:54.317593
10132 12:18:54.319807 Version 9 (ocp_data = 6010)
10133 12:18:54.320375
10134 12:18:54.323033 R8152: Done initializing
10135 12:18:54.323600
10136 12:18:54.323978 Adding net device
10137 12:18:56.192190
10138 12:18:56.192820 done.
10139 12:18:56.193215
10140 12:18:56.193566 MAC: 00:e0:4c:72:2d:d6
10141 12:18:56.194149
10142 12:18:56.194918 Sending DHCP discover... done.
10143 12:18:56.195446
10144 12:18:56.197824 Waiting for reply... done.
10145 12:18:56.198363
10146 12:18:56.201207 Sending DHCP request... done.
10147 12:18:56.201673
10148 12:18:56.202075 Waiting for reply... done.
10149 12:18:56.202426
10150 12:18:56.204959 My ip is 192.168.201.21
10151 12:18:56.205444
10152 12:18:56.207849 The DHCP server ip is 192.168.201.1
10153 12:18:56.208315
10154 12:18:56.211628 TFTP server IP predefined by user: 192.168.201.1
10155 12:18:56.212196
10156 12:18:56.218092 Bootfile predefined by user: 12669536/tftp-deploy-ij7nhhg4/kernel/image.itb
10157 12:18:56.218651
10158 12:18:56.221350 Sending tftp read request... done.
10159 12:18:56.221816
10160 12:18:56.228051 Waiting for the transfer...
10161 12:18:56.228626
10162 12:18:56.563549 00000000 ################################################################
10163 12:18:56.563683
10164 12:18:56.861058 00080000 ################################################################
10165 12:18:56.861222
10166 12:18:57.149254 00100000 ################################################################
10167 12:18:57.149389
10168 12:18:57.424544 00180000 ################################################################
10169 12:18:57.424670
10170 12:18:57.677522 00200000 ################################################################
10171 12:18:57.677689
10172 12:18:57.926521 00280000 ################################################################
10173 12:18:57.926647
10174 12:18:58.184374 00300000 ################################################################
10175 12:18:58.184498
10176 12:18:58.474379 00380000 ################################################################
10177 12:18:58.474516
10178 12:18:58.751382 00400000 ################################################################
10179 12:18:58.751526
10180 12:18:59.040644 00480000 ################################################################
10181 12:18:59.040788
10182 12:18:59.326409 00500000 ################################################################
10183 12:18:59.326536
10184 12:18:59.637301 00580000 ################################################################
10185 12:18:59.637797
10186 12:19:00.015396 00600000 ################################################################
10187 12:19:00.016023
10188 12:19:00.388619 00680000 ################################################################
10189 12:19:00.389187
10190 12:19:00.766460 00700000 ################################################################
10191 12:19:00.766606
10192 12:19:01.056731 00780000 ################################################################
10193 12:19:01.056864
10194 12:19:01.313004 00800000 ################################################################
10195 12:19:01.313131
10196 12:19:01.600933 00880000 ################################################################
10197 12:19:01.601063
10198 12:19:01.886398 00900000 ################################################################
10199 12:19:01.886542
10200 12:19:02.134906 00980000 ################################################################
10201 12:19:02.135030
10202 12:19:02.384322 00a00000 ################################################################
10203 12:19:02.384446
10204 12:19:02.674140 00a80000 ################################################################
10205 12:19:02.674271
10206 12:19:02.926900 00b00000 ################################################################
10207 12:19:02.927024
10208 12:19:03.214363 00b80000 ################################################################
10209 12:19:03.214514
10210 12:19:03.476313 00c00000 ################################################################
10211 12:19:03.476443
10212 12:19:03.855758 00c80000 ################################################################
10213 12:19:03.856339
10214 12:19:04.241025 00d00000 ################################################################
10215 12:19:04.241523
10216 12:19:04.635496 00d80000 ################################################################
10217 12:19:04.635626
10218 12:19:04.931632 00e00000 ################################################################
10219 12:19:04.931773
10220 12:19:05.231693 00e80000 ################################################################
10221 12:19:05.231824
10222 12:19:05.532652 00f00000 ################################################################
10223 12:19:05.532781
10224 12:19:05.830132 00f80000 ################################################################
10225 12:19:05.830269
10226 12:19:06.126392 01000000 ################################################################
10227 12:19:06.126533
10228 12:19:06.427080 01080000 ################################################################
10229 12:19:06.427207
10230 12:19:06.719509 01100000 ################################################################
10231 12:19:06.719632
10232 12:19:07.015800 01180000 ################################################################
10233 12:19:07.015934
10234 12:19:07.316878 01200000 ################################################################
10235 12:19:07.317007
10236 12:19:07.617354 01280000 ################################################################
10237 12:19:07.617477
10238 12:19:07.912023 01300000 ################################################################
10239 12:19:07.912156
10240 12:19:08.212273 01380000 ################################################################
10241 12:19:08.212405
10242 12:19:08.506059 01400000 ################################################################
10243 12:19:08.506183
10244 12:19:08.805523 01480000 ################################################################
10245 12:19:08.805664
10246 12:19:09.101533 01500000 ################################################################
10247 12:19:09.101675
10248 12:19:09.402575 01580000 ################################################################
10249 12:19:09.402705
10250 12:19:09.702899 01600000 ################################################################
10251 12:19:09.703050
10252 12:19:09.992078 01680000 ################################################################
10253 12:19:09.992220
10254 12:19:10.283398 01700000 ################################################################
10255 12:19:10.283527
10256 12:19:10.576368 01780000 ################################################################
10257 12:19:10.576492
10258 12:19:10.871626 01800000 ################################################################
10259 12:19:10.871781
10260 12:19:11.153767 01880000 ################################################################
10261 12:19:11.153896
10262 12:19:11.450841 01900000 ################################################################
10263 12:19:11.450979
10264 12:19:11.750343 01980000 ################################################################
10265 12:19:11.750470
10266 12:19:12.039213 01a00000 ################################################################
10267 12:19:12.039348
10268 12:19:12.300956 01a80000 ################################################################
10269 12:19:12.301079
10270 12:19:12.579737 01b00000 ################################################################
10271 12:19:12.579872
10272 12:19:12.876261 01b80000 ################################################################
10273 12:19:12.876401
10274 12:19:13.132768 01c00000 ################################################################
10275 12:19:13.132906
10276 12:19:13.141726 01c80000 ### done.
10277 12:19:13.141833
10278 12:19:13.145081 The bootfile was 29902642 bytes long.
10279 12:19:13.145173
10280 12:19:13.148319 Sending tftp read request... done.
10281 12:19:13.148407
10282 12:19:13.151615 Waiting for the transfer...
10283 12:19:13.151704
10284 12:19:13.151772 00000000 # done.
10285 12:19:13.151834
10286 12:19:13.161200 Command line loaded dynamically from TFTP file: 12669536/tftp-deploy-ij7nhhg4/kernel/cmdline
10287 12:19:13.161313
10288 12:19:13.181217 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12669536/extract-nfsrootfs-heetpg7n,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10289 12:19:13.181338
10290 12:19:13.184567 Loading FIT.
10291 12:19:13.184656
10292 12:19:13.187524 Image ramdisk-1 has 17806045 bytes.
10293 12:19:13.187611
10294 12:19:13.187677 Image fdt-1 has 47278 bytes.
10295 12:19:13.187739
10296 12:19:13.191012 Image kernel-1 has 12047284 bytes.
10297 12:19:13.191094
10298 12:19:13.200860 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10299 12:19:13.200956
10300 12:19:13.217586 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10301 12:19:13.217716
10302 12:19:13.224288 Choosing best match conf-1 for compat google,spherion-rev2.
10303 12:19:13.227773
10304 12:19:13.251086 Connected to device vid:did:rid of 1ae0:0028:00
10305 12:19:13.267751
10306 12:19:13.270891 tpm_get_response: command 0x17b, return code 0x0
10307 12:19:13.270986
10308 12:19:13.277851 ec_init: CrosEC protocol v3 supported (256, 248)
10309 12:19:13.278025
10310 12:19:13.280778 tpm_cleanup: add release locality here.
10311 12:19:13.280871
10312 12:19:13.284104 Shutting down all USB controllers.
10313 12:19:13.284191
10314 12:19:13.287852 Removing current net device
10315 12:19:13.287937
10316 12:19:13.291328 Exiting depthcharge with code 4 at timestamp: 52631189
10317 12:19:13.291413
10318 12:19:13.297574 LZMA decompressing kernel-1 to 0x821a6718
10319 12:19:13.297687
10320 12:19:13.300997 LZMA decompressing kernel-1 to 0x40000000
10321 12:19:14.800585
10322 12:19:14.801144 jumping to kernel
10323 12:19:14.802900 end: 2.2.4 bootloader-commands (duration 00:00:25) [common]
10324 12:19:14.803432 start: 2.2.5 auto-login-action (timeout 00:04:00) [common]
10325 12:19:14.803831 Setting prompt string to ['Linux version [0-9]']
10326 12:19:14.804195 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10327 12:19:14.804560 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10328 12:19:14.882493
10329 12:19:14.885590 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10330 12:19:14.889164 start: 2.2.5.1 login-action (timeout 00:04:00) [common]
10331 12:19:14.889713 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10332 12:19:14.890219 Setting prompt string to []
10333 12:19:14.890670 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10334 12:19:14.891118 Using line separator: #'\n'#
10335 12:19:14.891474 No login prompt set.
10336 12:19:14.891870 Parsing kernel messages
10337 12:19:14.892237 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10338 12:19:14.892855 [login-action] Waiting for messages, (timeout 00:04:00)
10339 12:19:14.908706 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j93261-arm64-gcc-10-defconfig-arm64-chromebook-cwjwh) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024
10340 12:19:14.912301 [ 0.000000] random: crng init done
10341 12:19:14.918597 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10342 12:19:14.922247 [ 0.000000] efi: UEFI not found.
10343 12:19:14.928632 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10344 12:19:14.935210 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10345 12:19:14.945048 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10346 12:19:14.955199 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10347 12:19:14.962032 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10348 12:19:14.968347 [ 0.000000] printk: bootconsole [mtk8250] enabled
10349 12:19:14.975020 [ 0.000000] NUMA: No NUMA configuration found
10350 12:19:14.981314 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10351 12:19:14.984485 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10352 12:19:14.987841 [ 0.000000] Zone ranges:
10353 12:19:14.994479 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10354 12:19:14.998044 [ 0.000000] DMA32 empty
10355 12:19:15.004443 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10356 12:19:15.008153 [ 0.000000] Movable zone start for each node
10357 12:19:15.011438 [ 0.000000] Early memory node ranges
10358 12:19:15.017652 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10359 12:19:15.024162 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10360 12:19:15.030896 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10361 12:19:15.037698 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10362 12:19:15.044356 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10363 12:19:15.050643 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10364 12:19:15.106919 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10365 12:19:15.113855 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10366 12:19:15.119929 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10367 12:19:15.123082 [ 0.000000] psci: probing for conduit method from DT.
10368 12:19:15.130343 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10369 12:19:15.133308 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10370 12:19:15.140636 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10371 12:19:15.143304 [ 0.000000] psci: SMC Calling Convention v1.2
10372 12:19:15.149872 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10373 12:19:15.152902 [ 0.000000] Detected VIPT I-cache on CPU0
10374 12:19:15.159832 [ 0.000000] CPU features: detected: GIC system register CPU interface
10375 12:19:15.166151 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10376 12:19:15.173268 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10377 12:19:15.179394 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10378 12:19:15.186228 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10379 12:19:15.192923 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10380 12:19:15.199780 [ 0.000000] alternatives: applying boot alternatives
10381 12:19:15.203127 [ 0.000000] Fallback order for Node 0: 0
10382 12:19:15.213164 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10383 12:19:15.213735 [ 0.000000] Policy zone: Normal
10384 12:19:15.236188 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12669536/extract-nfsrootfs-heetpg7n,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10385 12:19:15.249671 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10386 12:19:15.259794 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10387 12:19:15.269815 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10388 12:19:15.276569 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10389 12:19:15.279337 <6>[ 0.000000] software IO TLB: area num 8.
10390 12:19:15.336199 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10391 12:19:15.485671 <6>[ 0.000000] Memory: 7949860K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 402908K reserved, 32768K cma-reserved)
10392 12:19:15.491919 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10393 12:19:15.498526 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10394 12:19:15.501915 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10395 12:19:15.508944 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10396 12:19:15.515173 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10397 12:19:15.518142 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10398 12:19:15.528289 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10399 12:19:15.534850 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10400 12:19:15.541494 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10401 12:19:15.548103 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10402 12:19:15.551297 <6>[ 0.000000] GICv3: 608 SPIs implemented
10403 12:19:15.554539 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10404 12:19:15.561110 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10405 12:19:15.564453 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10406 12:19:15.570986 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10407 12:19:15.584820 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10408 12:19:15.594606 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10409 12:19:15.604267 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10410 12:19:15.611578 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10411 12:19:15.625221 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10412 12:19:15.631239 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10413 12:19:15.638295 <6>[ 0.009183] Console: colour dummy device 80x25
10414 12:19:15.647987 <6>[ 0.013910] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10415 12:19:15.654818 <6>[ 0.024352] pid_max: default: 32768 minimum: 301
10416 12:19:15.658179 <6>[ 0.029223] LSM: Security Framework initializing
10417 12:19:15.664714 <6>[ 0.034193] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10418 12:19:15.674760 <6>[ 0.042007] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10419 12:19:15.681283 <6>[ 0.051420] cblist_init_generic: Setting adjustable number of callback queues.
10420 12:19:15.687710 <6>[ 0.058864] cblist_init_generic: Setting shift to 3 and lim to 1.
10421 12:19:15.698143 <6>[ 0.065202] cblist_init_generic: Setting adjustable number of callback queues.
10422 12:19:15.701526 <6>[ 0.072628] cblist_init_generic: Setting shift to 3 and lim to 1.
10423 12:19:15.708365 <6>[ 0.079028] rcu: Hierarchical SRCU implementation.
10424 12:19:15.714610 <6>[ 0.084043] rcu: Max phase no-delay instances is 1000.
10425 12:19:15.720988 <6>[ 0.091068] EFI services will not be available.
10426 12:19:15.724934 <6>[ 0.096023] smp: Bringing up secondary CPUs ...
10427 12:19:15.732704 <6>[ 0.101071] Detected VIPT I-cache on CPU1
10428 12:19:15.739511 <6>[ 0.101140] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10429 12:19:15.745992 <6>[ 0.101173] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10430 12:19:15.748890 <6>[ 0.101506] Detected VIPT I-cache on CPU2
10431 12:19:15.755811 <6>[ 0.101557] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10432 12:19:15.762756 <6>[ 0.101574] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10433 12:19:15.769035 <6>[ 0.101831] Detected VIPT I-cache on CPU3
10434 12:19:15.775737 <6>[ 0.101878] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10435 12:19:15.782515 <6>[ 0.101892] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10436 12:19:15.785419 <6>[ 0.102197] CPU features: detected: Spectre-v4
10437 12:19:15.792168 <6>[ 0.102204] CPU features: detected: Spectre-BHB
10438 12:19:15.795130 <6>[ 0.102209] Detected PIPT I-cache on CPU4
10439 12:19:15.802295 <6>[ 0.102264] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10440 12:19:15.808167 <6>[ 0.102281] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10441 12:19:15.814793 <6>[ 0.102577] Detected PIPT I-cache on CPU5
10442 12:19:15.821556 <6>[ 0.102640] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10443 12:19:15.828881 <6>[ 0.102656] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10444 12:19:15.831455 <6>[ 0.102934] Detected PIPT I-cache on CPU6
10445 12:19:15.838295 <6>[ 0.102998] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10446 12:19:15.845163 <6>[ 0.103014] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10447 12:19:15.851447 <6>[ 0.103308] Detected PIPT I-cache on CPU7
10448 12:19:15.858207 <6>[ 0.103372] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10449 12:19:15.865231 <6>[ 0.103389] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10450 12:19:15.868504 <6>[ 0.103437] smp: Brought up 1 node, 8 CPUs
10451 12:19:15.874930 <6>[ 0.244761] SMP: Total of 8 processors activated.
10452 12:19:15.878141 <6>[ 0.249682] CPU features: detected: 32-bit EL0 Support
10453 12:19:15.888362 <6>[ 0.255044] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10454 12:19:15.894903 <6>[ 0.263844] CPU features: detected: Common not Private translations
10455 12:19:15.897991 <6>[ 0.270319] CPU features: detected: CRC32 instructions
10456 12:19:15.905083 <6>[ 0.275671] CPU features: detected: RCpc load-acquire (LDAPR)
10457 12:19:15.911377 <6>[ 0.281630] CPU features: detected: LSE atomic instructions
10458 12:19:15.918128 <6>[ 0.287412] CPU features: detected: Privileged Access Never
10459 12:19:15.921036 <6>[ 0.293191] CPU features: detected: RAS Extension Support
10460 12:19:15.931404 <6>[ 0.298800] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10461 12:19:15.934495 <6>[ 0.306022] CPU: All CPU(s) started at EL2
10462 12:19:15.940892 <6>[ 0.310366] alternatives: applying system-wide alternatives
10463 12:19:15.949587 <6>[ 0.321080] devtmpfs: initialized
10464 12:19:15.965909 <6>[ 0.330046] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10465 12:19:15.972185 <6>[ 0.340009] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10466 12:19:15.978662 <6>[ 0.348243] pinctrl core: initialized pinctrl subsystem
10467 12:19:15.982011 <6>[ 0.354885] DMI not present or invalid.
10468 12:19:15.989026 <6>[ 0.359297] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10469 12:19:15.998606 <6>[ 0.366191] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10470 12:19:16.005048 <6>[ 0.373781] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10471 12:19:16.015303 <6>[ 0.382006] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10472 12:19:16.018341 <6>[ 0.390249] audit: initializing netlink subsys (disabled)
10473 12:19:16.028228 <5>[ 0.395942] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10474 12:19:16.035234 <6>[ 0.396643] thermal_sys: Registered thermal governor 'step_wise'
10475 12:19:16.041995 <6>[ 0.403910] thermal_sys: Registered thermal governor 'power_allocator'
10476 12:19:16.045191 <6>[ 0.410165] cpuidle: using governor menu
10477 12:19:16.051534 <6>[ 0.421125] NET: Registered PF_QIPCRTR protocol family
10478 12:19:16.058413 <6>[ 0.426612] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10479 12:19:16.064853 <6>[ 0.433712] ASID allocator initialised with 32768 entries
10480 12:19:16.067670 <6>[ 0.440257] Serial: AMBA PL011 UART driver
10481 12:19:16.077715 <4>[ 0.449063] Trying to register duplicate clock ID: 134
10482 12:19:16.133890 <6>[ 0.508301] KASLR enabled
10483 12:19:16.148481 <6>[ 0.516087] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10484 12:19:16.154756 <6>[ 0.523103] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10485 12:19:16.161527 <6>[ 0.529592] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10486 12:19:16.168228 <6>[ 0.536599] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10487 12:19:16.175324 <6>[ 0.543086] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10488 12:19:16.181391 <6>[ 0.550090] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10489 12:19:16.188494 <6>[ 0.556580] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10490 12:19:16.194599 <6>[ 0.563584] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10491 12:19:16.198685 <6>[ 0.571043] ACPI: Interpreter disabled.
10492 12:19:16.206278 <6>[ 0.577459] iommu: Default domain type: Translated
10493 12:19:16.212526 <6>[ 0.582610] iommu: DMA domain TLB invalidation policy: strict mode
10494 12:19:16.215673 <5>[ 0.589272] SCSI subsystem initialized
10495 12:19:16.222429 <6>[ 0.593522] usbcore: registered new interface driver usbfs
10496 12:19:16.229173 <6>[ 0.599253] usbcore: registered new interface driver hub
10497 12:19:16.232526 <6>[ 0.604807] usbcore: registered new device driver usb
10498 12:19:16.239580 <6>[ 0.610929] pps_core: LinuxPPS API ver. 1 registered
10499 12:19:16.249447 <6>[ 0.616123] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10500 12:19:16.252987 <6>[ 0.625466] PTP clock support registered
10501 12:19:16.256086 <6>[ 0.629707] EDAC MC: Ver: 3.0.0
10502 12:19:16.263761 <6>[ 0.634908] FPGA manager framework
10503 12:19:16.270243 <6>[ 0.638585] Advanced Linux Sound Architecture Driver Initialized.
10504 12:19:16.273643 <6>[ 0.645361] vgaarb: loaded
10505 12:19:16.280011 <6>[ 0.648511] clocksource: Switched to clocksource arch_sys_counter
10506 12:19:16.283598 <5>[ 0.654957] VFS: Disk quotas dquot_6.6.0
10507 12:19:16.290102 <6>[ 0.659143] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10508 12:19:16.294049 <6>[ 0.666336] pnp: PnP ACPI: disabled
10509 12:19:16.302114 <6>[ 0.673162] NET: Registered PF_INET protocol family
10510 12:19:16.312409 <6>[ 0.678762] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10511 12:19:16.323082 <6>[ 0.690983] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10512 12:19:16.333170 <6>[ 0.699795] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10513 12:19:16.339442 <6>[ 0.707763] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10514 12:19:16.345899 <6>[ 0.716461] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10515 12:19:16.358459 <6>[ 0.726168] TCP: Hash tables configured (established 65536 bind 65536)
10516 12:19:16.364931 <6>[ 0.733036] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10517 12:19:16.371430 <6>[ 0.740237] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10518 12:19:16.378344 <6>[ 0.747944] NET: Registered PF_UNIX/PF_LOCAL protocol family
10519 12:19:16.384813 <6>[ 0.754037] RPC: Registered named UNIX socket transport module.
10520 12:19:16.388139 <6>[ 0.760186] RPC: Registered udp transport module.
10521 12:19:16.394810 <6>[ 0.765119] RPC: Registered tcp transport module.
10522 12:19:16.401603 <6>[ 0.770049] RPC: Registered tcp NFSv4.1 backchannel transport module.
10523 12:19:16.405209 <6>[ 0.776714] PCI: CLS 0 bytes, default 64
10524 12:19:16.408603 <6>[ 0.781120] Unpacking initramfs...
10525 12:19:16.432915 <6>[ 0.800607] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10526 12:19:16.443128 <6>[ 0.809277] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10527 12:19:16.446173 <6>[ 0.818134] kvm [1]: IPA Size Limit: 40 bits
10528 12:19:16.452619 <6>[ 0.822661] kvm [1]: GICv3: no GICV resource entry
10529 12:19:16.456231 <6>[ 0.827681] kvm [1]: disabling GICv2 emulation
10530 12:19:16.462463 <6>[ 0.832370] kvm [1]: GIC system register CPU interface enabled
10531 12:19:16.465726 <6>[ 0.838540] kvm [1]: vgic interrupt IRQ18
10532 12:19:16.472342 <6>[ 0.842893] kvm [1]: VHE mode initialized successfully
10533 12:19:16.478688 <5>[ 0.849385] Initialise system trusted keyrings
10534 12:19:16.485497 <6>[ 0.854217] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10535 12:19:16.492747 <6>[ 0.864212] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10536 12:19:16.499519 <5>[ 0.870587] NFS: Registering the id_resolver key type
10537 12:19:16.502823 <5>[ 0.875886] Key type id_resolver registered
10538 12:19:16.509676 <5>[ 0.880302] Key type id_legacy registered
10539 12:19:16.516151 <6>[ 0.884581] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10540 12:19:16.522618 <6>[ 0.891502] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10541 12:19:16.529457 <6>[ 0.899198] 9p: Installing v9fs 9p2000 file system support
10542 12:19:16.566166 <5>[ 0.937093] Key type asymmetric registered
10543 12:19:16.569669 <5>[ 0.941425] Asymmetric key parser 'x509' registered
10544 12:19:16.579492 <6>[ 0.946558] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10545 12:19:16.582406 <6>[ 0.954171] io scheduler mq-deadline registered
10546 12:19:16.585742 <6>[ 0.958929] io scheduler kyber registered
10547 12:19:16.604031 <6>[ 0.975961] EINJ: ACPI disabled.
10548 12:19:16.638134 <4>[ 1.002308] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10549 12:19:16.647824 <4>[ 1.012932] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10550 12:19:16.662728 <6>[ 1.033910] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10551 12:19:16.670501 <6>[ 1.041955] printk: console [ttyS0] disabled
10552 12:19:16.698999 <6>[ 1.066617] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10553 12:19:16.705767 <6>[ 1.076087] printk: console [ttyS0] enabled
10554 12:19:16.708958 <6>[ 1.076087] printk: console [ttyS0] enabled
10555 12:19:16.715602 <6>[ 1.084981] printk: bootconsole [mtk8250] disabled
10556 12:19:16.718574 <6>[ 1.084981] printk: bootconsole [mtk8250] disabled
10557 12:19:16.725039 <6>[ 1.096048] SuperH (H)SCI(F) driver initialized
10558 12:19:16.728889 <6>[ 1.101326] msm_serial: driver initialized
10559 12:19:16.742375 <6>[ 1.110312] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10560 12:19:16.752441 <6>[ 1.118858] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10561 12:19:16.759236 <6>[ 1.127405] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10562 12:19:16.769571 <6>[ 1.136035] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10563 12:19:16.775992 <6>[ 1.144743] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10564 12:19:16.785886 <6>[ 1.153456] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10565 12:19:16.795463 <6>[ 1.161996] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10566 12:19:16.802566 <6>[ 1.170789] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10567 12:19:16.812034 <6>[ 1.179335] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10568 12:19:16.823394 <6>[ 1.194735] loop: module loaded
10569 12:19:16.830109 <6>[ 1.200681] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10570 12:19:16.852830 <4>[ 1.223960] mtk-pmic-keys: Failed to locate of_node [id: -1]
10571 12:19:16.859798 <6>[ 1.230708] megasas: 07.719.03.00-rc1
10572 12:19:16.868795 <6>[ 1.240427] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10573 12:19:16.876274 <6>[ 1.247882] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10574 12:19:16.893003 <6>[ 1.264370] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10575 12:19:16.948759 <6>[ 1.313488] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10576 12:19:17.150996 <6>[ 1.522276] Freeing initrd memory: 17388K
10577 12:19:17.161258 <6>[ 1.532394] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10578 12:19:17.172316 <6>[ 1.543507] tun: Universal TUN/TAP device driver, 1.6
10579 12:19:17.175837 <6>[ 1.549582] thunder_xcv, ver 1.0
10580 12:19:17.178803 <6>[ 1.553089] thunder_bgx, ver 1.0
10581 12:19:17.182398 <6>[ 1.556584] nicpf, ver 1.0
10582 12:19:17.193150 <6>[ 1.560614] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10583 12:19:17.196271 <6>[ 1.568090] hns3: Copyright (c) 2017 Huawei Corporation.
10584 12:19:17.199342 <6>[ 1.573676] hclge is initializing
10585 12:19:17.206075 <6>[ 1.577257] e1000: Intel(R) PRO/1000 Network Driver
10586 12:19:17.213145 <6>[ 1.582387] e1000: Copyright (c) 1999-2006 Intel Corporation.
10587 12:19:17.215872 <6>[ 1.588400] e1000e: Intel(R) PRO/1000 Network Driver
10588 12:19:17.223043 <6>[ 1.593616] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10589 12:19:17.229690 <6>[ 1.599805] igb: Intel(R) Gigabit Ethernet Network Driver
10590 12:19:17.236569 <6>[ 1.605455] igb: Copyright (c) 2007-2014 Intel Corporation.
10591 12:19:17.242698 <6>[ 1.611291] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10592 12:19:17.246269 <6>[ 1.617810] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10593 12:19:17.252912 <6>[ 1.624270] sky2: driver version 1.30
10594 12:19:17.259157 <6>[ 1.629267] VFIO - User Level meta-driver version: 0.3
10595 12:19:17.266238 <6>[ 1.637513] usbcore: registered new interface driver usb-storage
10596 12:19:17.272955 <6>[ 1.643958] usbcore: registered new device driver onboard-usb-hub
10597 12:19:17.282196 <6>[ 1.653183] mt6397-rtc mt6359-rtc: registered as rtc0
10598 12:19:17.291865 <6>[ 1.658650] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-31T12:18:40 UTC (1706703520)
10599 12:19:17.295012 <6>[ 1.668256] i2c_dev: i2c /dev entries driver
10600 12:19:17.312524 <6>[ 1.680135] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10601 12:19:17.332055 <6>[ 1.703146] cpu cpu0: EM: created perf domain
10602 12:19:17.335398 <6>[ 1.708073] cpu cpu4: EM: created perf domain
10603 12:19:17.342206 <6>[ 1.713345] sdhci: Secure Digital Host Controller Interface driver
10604 12:19:17.348850 <6>[ 1.719782] sdhci: Copyright(c) Pierre Ossman
10605 12:19:17.355519 <6>[ 1.724734] Synopsys Designware Multimedia Card Interface Driver
10606 12:19:17.362191 <6>[ 1.731365] sdhci-pltfm: SDHCI platform and OF driver helper
10607 12:19:17.365450 <6>[ 1.731391] mmc0: CQHCI version 5.10
10608 12:19:17.372091 <6>[ 1.741346] ledtrig-cpu: registered to indicate activity on CPUs
10609 12:19:17.378563 <6>[ 1.748362] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10610 12:19:17.385139 <6>[ 1.755414] usbcore: registered new interface driver usbhid
10611 12:19:17.388958 <6>[ 1.761236] usbhid: USB HID core driver
10612 12:19:17.395721 <6>[ 1.765431] spi_master spi0: will run message pump with realtime priority
10613 12:19:17.439395 <6>[ 1.803680] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10614 12:19:17.455384 <6>[ 1.819891] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10615 12:19:17.462118 <6>[ 1.833512] mmc0: Command Queue Engine enabled
10616 12:19:17.469203 <6>[ 1.838326] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10617 12:19:17.472116 <6>[ 1.845624] mmcblk0: mmc0:0001 DA4128 116 GiB
10618 12:19:17.479386 <6>[ 1.850569] cros-ec-spi spi0.0: Chrome EC device registered
10619 12:19:17.486008 <6>[ 1.854780] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10620 12:19:17.492707 <6>[ 1.864055] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10621 12:19:17.499180 <6>[ 1.870017] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10622 12:19:17.506387 <6>[ 1.876112] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10623 12:19:17.525371 <6>[ 1.893282] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10624 12:19:17.532775 <6>[ 1.903971] NET: Registered PF_PACKET protocol family
10625 12:19:17.536031 <6>[ 1.909374] 9pnet: Installing 9P2000 support
10626 12:19:17.543006 <5>[ 1.913922] Key type dns_resolver registered
10627 12:19:17.546340 <6>[ 1.918954] registered taskstats version 1
10628 12:19:17.552710 <5>[ 1.923339] Loading compiled-in X.509 certificates
10629 12:19:17.585111 <4>[ 1.949541] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10630 12:19:17.594964 <4>[ 1.960314] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10631 12:19:17.601881 <3>[ 1.970853] debugfs: File 'uA_load' in directory '/' already present!
10632 12:19:17.608594 <3>[ 1.977556] debugfs: File 'min_uV' in directory '/' already present!
10633 12:19:17.614955 <3>[ 1.984167] debugfs: File 'max_uV' in directory '/' already present!
10634 12:19:17.621780 <3>[ 1.990773] debugfs: File 'constraint_flags' in directory '/' already present!
10635 12:19:17.632251 <3>[ 2.000493] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10636 12:19:17.644467 <6>[ 2.015925] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10637 12:19:17.651357 <6>[ 2.022718] xhci-mtk 11200000.usb: xHCI Host Controller
10638 12:19:17.657422 <6>[ 2.028224] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10639 12:19:17.667691 <6>[ 2.036076] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10640 12:19:17.674854 <6>[ 2.045522] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10641 12:19:17.681593 <6>[ 2.051727] xhci-mtk 11200000.usb: xHCI Host Controller
10642 12:19:17.688358 <6>[ 2.057245] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10643 12:19:17.694825 <6>[ 2.064995] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10644 12:19:17.701396 <6>[ 2.072958] hub 1-0:1.0: USB hub found
10645 12:19:17.705137 <6>[ 2.076996] hub 1-0:1.0: 1 port detected
10646 12:19:17.711863 <6>[ 2.081336] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10647 12:19:17.718990 <6>[ 2.090133] hub 2-0:1.0: USB hub found
10648 12:19:17.722378 <6>[ 2.094164] hub 2-0:1.0: 1 port detected
10649 12:19:17.729566 <6>[ 2.100581] mtk-msdc 11f70000.mmc: Got CD GPIO
10650 12:19:17.743114 <6>[ 2.111107] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10651 12:19:17.750512 <6>[ 2.119145] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10652 12:19:17.759772 <4>[ 2.127071] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10653 12:19:17.770204 <6>[ 2.136644] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10654 12:19:17.776560 <6>[ 2.144724] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10655 12:19:17.782785 <6>[ 2.152744] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10656 12:19:17.793191 <6>[ 2.160660] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10657 12:19:17.799878 <6>[ 2.168477] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10658 12:19:17.809379 <6>[ 2.176292] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10659 12:19:17.819381 <6>[ 2.186704] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10660 12:19:17.826357 <6>[ 2.195086] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10661 12:19:17.835879 <6>[ 2.203432] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10662 12:19:17.842331 <6>[ 2.211772] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10663 12:19:17.852400 <6>[ 2.220111] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10664 12:19:17.859411 <6>[ 2.228449] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10665 12:19:17.869521 <6>[ 2.236792] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10666 12:19:17.875896 <6>[ 2.245131] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10667 12:19:17.885834 <6>[ 2.253474] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10668 12:19:17.892703 <6>[ 2.261814] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10669 12:19:17.902469 <6>[ 2.270153] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10670 12:19:17.909342 <6>[ 2.278492] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10671 12:19:17.919187 <6>[ 2.286831] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10672 12:19:17.925804 <6>[ 2.295170] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10673 12:19:17.935776 <6>[ 2.303509] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10674 12:19:17.942336 <6>[ 2.312263] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10675 12:19:17.948812 <6>[ 2.319413] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10676 12:19:17.955466 <6>[ 2.326171] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10677 12:19:17.962403 <6>[ 2.332935] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10678 12:19:17.969471 <6>[ 2.339875] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10679 12:19:17.978780 <6>[ 2.346733] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10680 12:19:17.988664 <6>[ 2.355870] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10681 12:19:17.998984 <6>[ 2.364988] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10682 12:19:18.009054 <6>[ 2.374282] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10683 12:19:18.015484 <6>[ 2.383749] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10684 12:19:18.025313 <6>[ 2.393214] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10685 12:19:18.035192 <6>[ 2.402332] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10686 12:19:18.045366 <6>[ 2.411797] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10687 12:19:18.055131 <6>[ 2.420916] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10688 12:19:18.065071 <6>[ 2.430209] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10689 12:19:18.074907 <6>[ 2.440369] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10690 12:19:18.084825 <6>[ 2.452174] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10691 12:19:18.091416 <6>[ 2.462010] Trying to probe devices needed for running init ...
10692 12:19:18.137306 <6>[ 2.504769] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10693 12:19:18.291386 <6>[ 2.662927] hub 1-1:1.0: USB hub found
10694 12:19:18.294844 <6>[ 2.667447] hub 1-1:1.0: 4 ports detected
10695 12:19:18.304357 <6>[ 2.675762] hub 1-1:1.0: USB hub found
10696 12:19:18.307663 <6>[ 2.680120] hub 1-1:1.0: 4 ports detected
10697 12:19:18.417444 <6>[ 2.785037] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10698 12:19:18.443476 <6>[ 2.814644] hub 2-1:1.0: USB hub found
10699 12:19:18.446463 <6>[ 2.819138] hub 2-1:1.0: 3 ports detected
10700 12:19:18.456288 <6>[ 2.827205] hub 2-1:1.0: USB hub found
10701 12:19:18.459714 <6>[ 2.831656] hub 2-1:1.0: 3 ports detected
10702 12:19:18.632696 <6>[ 3.000827] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10703 12:19:18.765454 <6>[ 3.136700] hub 1-1.4:1.0: USB hub found
10704 12:19:18.768776 <6>[ 3.141374] hub 1-1.4:1.0: 2 ports detected
10705 12:19:18.777381 <6>[ 3.148785] hub 1-1.4:1.0: USB hub found
10706 12:19:18.780798 <6>[ 3.153333] hub 1-1.4:1.0: 2 ports detected
10707 12:19:18.848918 <6>[ 3.216925] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10708 12:19:19.076933 <6>[ 3.444858] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10709 12:19:19.268662 <6>[ 3.636827] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10710 12:19:30.389230 <6>[ 14.765799] ALSA device list:
10711 12:19:30.396080 <6>[ 14.769092] No soundcards found.
10712 12:19:30.403983 <6>[ 14.777068] Freeing unused kernel memory: 8448K
10713 12:19:30.407113 <6>[ 14.782093] Run /init as init process
10714 12:19:30.418688 Loading, please wait...
10715 12:19:30.438843 Starting version 247.3-7+deb11u2
10716 12:19:30.643239 <6>[ 15.012863] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10717 12:19:30.660505 <6>[ 15.030326] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10718 12:19:30.667100 <3>[ 15.034629] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 12:19:30.676907 <6>[ 15.043131] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10720 12:19:30.687117 <6>[ 15.055017] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10721 12:19:30.693666 <3>[ 15.055182] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 12:19:30.700382 <6>[ 15.059817] remoteproc remoteproc0: scp is available
10723 12:19:30.703696 <6>[ 15.059937] remoteproc remoteproc0: powering up scp
10724 12:19:30.713175 <6>[ 15.059941] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10725 12:19:30.716543 <6>[ 15.059964] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10726 12:19:30.726726 <3>[ 15.096472] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 12:19:30.733061 <6>[ 15.097352] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10728 12:19:30.743406 <3>[ 15.107990] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10729 12:19:30.749828 <4>[ 15.114660] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10730 12:19:30.753052 <6>[ 15.118180] mc: Linux media interface: v0.10
10731 12:19:30.763144 <3>[ 15.120687] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 12:19:30.769850 <4>[ 15.136675] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10733 12:19:30.776291 <3>[ 15.140599] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10734 12:19:30.782904 <6>[ 15.153704] videodev: Linux video capture interface: v2.00
10735 12:19:30.793575 <4>[ 15.155756] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10736 12:19:30.796808 <4>[ 15.155756] Fallback method does not support PEC.
10737 12:19:30.803416 <3>[ 15.156168] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10738 12:19:30.810208 <6>[ 15.159465] usbcore: registered new device driver r8152-cfgselector
10739 12:19:30.820787 <3>[ 15.173073] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10740 12:19:30.827530 <3>[ 15.175333] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10741 12:19:30.834119 <6>[ 15.181878] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10742 12:19:30.840916 <6>[ 15.181885] pci_bus 0000:00: root bus resource [bus 00-ff]
10743 12:19:30.847193 <6>[ 15.181894] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10744 12:19:30.857334 <6>[ 15.181900] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10745 12:19:30.863810 <6>[ 15.181937] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10746 12:19:30.870706 <6>[ 15.181963] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10747 12:19:30.877072 <6>[ 15.182043] pci 0000:00:00.0: supports D1 D2
10748 12:19:30.883747 <6>[ 15.182046] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10749 12:19:30.890348 <6>[ 15.183597] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10750 12:19:30.899903 <6>[ 15.185091] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10751 12:19:30.906548 <6>[ 15.185196] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10752 12:19:30.913279 <6>[ 15.185206] remoteproc remoteproc0: remote processor scp is now up
10753 12:19:30.920081 <3>[ 15.189950] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10754 12:19:30.929793 <6>[ 15.191015] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10755 12:19:30.936254 <6>[ 15.192138] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10756 12:19:30.943058 <6>[ 15.198849] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10757 12:19:30.952948 <3>[ 15.203864] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10758 12:19:30.959517 <3>[ 15.206809] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 12:19:30.969387 <6>[ 15.213683] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10760 12:19:30.976048 <3>[ 15.219386] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 12:19:30.986064 <3>[ 15.219390] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10762 12:19:30.992790 <6>[ 15.226528] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10763 12:19:30.999710 <3>[ 15.236442] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 12:19:31.009607 <6>[ 15.242763] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10765 12:19:31.016296 <3>[ 15.250140] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10766 12:19:31.022749 <3>[ 15.250143] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 12:19:31.032837 <3>[ 15.250146] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 12:19:31.039360 <6>[ 15.252783] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10769 12:19:31.045766 <6>[ 15.254774] pci 0000:01:00.0: supports D1 D2
10770 12:19:31.055755 <6>[ 15.255718] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10771 12:19:31.062280 <3>[ 15.261527] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10772 12:19:31.068942 <6>[ 15.269775] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10773 12:19:31.078780 <6>[ 15.273437] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10774 12:19:31.088767 <6>[ 15.273907] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10775 12:19:31.095690 <3>[ 15.276839] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 12:19:31.105288 <4>[ 15.280558] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10777 12:19:31.111930 <4>[ 15.280568] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10778 12:19:31.121761 <6>[ 15.296655] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10779 12:19:31.124982 <6>[ 15.317157] Bluetooth: Core ver 2.22
10780 12:19:31.131771 <6>[ 15.322804] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10781 12:19:31.138446 <6>[ 15.331549] NET: Registered PF_BLUETOOTH protocol family
10782 12:19:31.144958 <6>[ 15.332343] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10783 12:19:31.158475 <6>[ 15.333426] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10784 12:19:31.164692 <6>[ 15.333551] usbcore: registered new interface driver uvcvideo
10785 12:19:31.171311 <6>[ 15.339566] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10786 12:19:31.177808 <6>[ 15.339576] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10787 12:19:31.184656 <6>[ 15.340647] r8152 2-1.3:1.0 eth0: v1.12.13
10788 12:19:31.187993 <6>[ 15.340738] usbcore: registered new interface driver r8152
10789 12:19:31.194787 <6>[ 15.347036] Bluetooth: HCI device and connection manager initialized
10790 12:19:31.204335 <6>[ 15.355126] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10791 12:19:31.207719 <6>[ 15.363217] Bluetooth: HCI socket layer initialized
10792 12:19:31.214148 <6>[ 15.364037] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10793 12:19:31.224414 <6>[ 15.370673] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10794 12:19:31.230824 <6>[ 15.370868] usbcore: registered new interface driver cdc_ether
10795 12:19:31.233891 <6>[ 15.378740] Bluetooth: L2CAP socket layer initialized
10796 12:19:31.240456 <6>[ 15.386216] pci 0000:00:00.0: PCI bridge to [bus 01]
10797 12:19:31.247056 <6>[ 15.386348] usbcore: registered new interface driver r8153_ecm
10798 12:19:31.250414 <6>[ 15.394286] Bluetooth: SCO socket layer initialized
10799 12:19:31.260382 <6>[ 15.402361] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10800 12:19:31.263973 <6>[ 15.402984] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10801 12:19:31.270269 <6>[ 15.484246] usbcore: registered new interface driver btusb
10802 12:19:31.280164 <4>[ 15.485168] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10803 12:19:31.286790 <3>[ 15.485180] Bluetooth: hci0: Failed to load firmware file (-2)
10804 12:19:31.293712 <3>[ 15.485185] Bluetooth: hci0: Failed to set up firmware (-2)
10805 12:19:31.303426 <4>[ 15.485190] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10806 12:19:31.309810 <6>[ 15.491943] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10807 12:19:31.316374 <6>[ 15.689127] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10808 12:19:31.323394 <6>[ 15.695718] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10809 12:19:31.344329 <5>[ 15.714302] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10810 12:19:31.363019 <5>[ 15.733122] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10811 12:19:31.369774 <5>[ 15.740534] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10812 12:19:31.380017 <4>[ 15.749012] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10813 12:19:31.382834 <6>[ 15.757892] cfg80211: failed to load regulatory.db
10814 12:19:31.433027 <6>[ 15.802857] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10815 12:19:31.439508 <6>[ 15.810360] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10816 12:19:31.463771 <6>[ 15.837012] mt7921e 0000:01:00.0: ASIC revision: 79610010
10817 12:19:31.566475 <6>[ 15.936286] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10818 12:19:31.569758 <6>[ 15.936286]
10819 12:19:31.580648 Begin: Loading essential drivers ... done.
10820 12:19:31.584098 Begin: Running /scripts/init-premount ... done.
10821 12:19:31.590860 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10822 12:19:31.600442 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10823 12:19:31.603719 Device /sys/class/net/enx00e04c722dd6 found
10824 12:19:31.603807 done.
10825 12:19:31.650565 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10826 12:19:31.834522 <6>[ 16.204618] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10827 12:19:32.647679 <6>[ 17.021286] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10828 12:19:32.677316 <6>[ 17.050922] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10829 12:19:32.785319 IP-Config: no response after 2 secs - giving up
10830 12:19:32.818339 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10831 12:19:32.847307 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:7b mtu 1500 DHCP
10832 12:19:33.579752 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10833 12:19:33.585954 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10834 12:19:33.592916 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10835 12:19:33.599532 host : mt8192-asurada-spherion-r0-cbg-1
10836 12:19:33.606172 domain : lava-rack
10837 12:19:33.609566 rootserver: 192.168.201.1 rootpath:
10838 12:19:33.612404 filename :
10839 12:19:33.687674 done.
10840 12:19:33.694145 Begin: Running /scripts/nfs-bottom ... done.
10841 12:19:33.712518 Begin: Running /scripts/init-bottom ... done.
10842 12:19:34.923280 <6>[ 19.296624] NET: Registered PF_INET6 protocol family
10843 12:19:34.931056 <6>[ 19.304553] Segment Routing with IPv6
10844 12:19:34.934517 <6>[ 19.308520] In-situ OAM (IOAM) with IPv6
10845 12:19:35.085440 <30>[ 19.438962] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10846 12:19:35.088657 <30>[ 19.463210] systemd[1]: Detected architecture arm64.
10847 12:19:35.110810
10848 12:19:35.113800 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10849 12:19:35.114266
10850 12:19:35.133929 <30>[ 19.507473] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10851 12:19:35.955836 <30>[ 20.326236] systemd[1]: Queued start job for default target Graphical Interface.
10852 12:19:35.989747 <30>[ 20.363185] systemd[1]: Created slice system-getty.slice.
10853 12:19:35.996340 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10854 12:19:36.012508 <30>[ 20.386179] systemd[1]: Created slice system-modprobe.slice.
10855 12:19:36.019228 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10856 12:19:36.036379 <30>[ 20.410007] systemd[1]: Created slice system-serial\x2dgetty.slice.
10857 12:19:36.046358 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10858 12:19:36.060664 <30>[ 20.433863] systemd[1]: Created slice User and Session Slice.
10859 12:19:36.067095 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10860 12:19:36.087407 <30>[ 20.457668] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10861 12:19:36.097159 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10862 12:19:36.115540 <30>[ 20.485567] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10863 12:19:36.122165 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10864 12:19:36.145818 <30>[ 20.512956] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10865 12:19:36.152487 <30>[ 20.525108] systemd[1]: Reached target Local Encrypted Volumes.
10866 12:19:36.159350 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10867 12:19:36.176256 <30>[ 20.549358] systemd[1]: Reached target Paths.
10868 12:19:36.179090 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10869 12:19:36.195099 <30>[ 20.568799] systemd[1]: Reached target Remote File Systems.
10870 12:19:36.201906 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10871 12:19:36.219561 <30>[ 20.593185] systemd[1]: Reached target Slices.
10872 12:19:36.226116 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10873 12:19:36.239613 <30>[ 20.612902] systemd[1]: Reached target Swap.
10874 12:19:36.243151 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10875 12:19:36.262937 <30>[ 20.633278] systemd[1]: Listening on initctl Compatibility Named Pipe.
10876 12:19:36.269425 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10877 12:19:36.276610 <30>[ 20.649333] systemd[1]: Listening on Journal Audit Socket.
10878 12:19:36.282574 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10879 12:19:36.300580 <30>[ 20.674063] systemd[1]: Listening on Journal Socket (/dev/log).
10880 12:19:36.307092 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10881 12:19:36.323632 <30>[ 20.697365] systemd[1]: Listening on Journal Socket.
10882 12:19:36.330560 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10883 12:19:36.345023 <30>[ 20.718303] systemd[1]: Listening on Network Service Netlink Socket.
10884 12:19:36.354823 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10885 12:19:36.370228 <30>[ 20.743603] systemd[1]: Listening on udev Control Socket.
10886 12:19:36.376804 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10887 12:19:36.392002 <30>[ 20.765346] systemd[1]: Listening on udev Kernel Socket.
10888 12:19:36.398332 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10889 12:19:36.455556 <30>[ 20.828949] systemd[1]: Mounting Huge Pages File System...
10890 12:19:36.462009 Mounting [0;1;39mHuge Pages File System[0m...
10891 12:19:36.479387 <30>[ 20.853140] systemd[1]: Mounting POSIX Message Queue File System...
10892 12:19:36.486047 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10893 12:19:36.531438 <30>[ 20.905188] systemd[1]: Mounting Kernel Debug File System...
10894 12:19:36.538383 Mounting [0;1;39mKernel Debug File System[0m...
10895 12:19:36.554874 <30>[ 20.925250] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10896 12:19:36.566946 <30>[ 20.937677] systemd[1]: Starting Create list of static device nodes for the current kernel...
10897 12:19:36.573619 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10898 12:19:36.596176 <30>[ 20.969805] systemd[1]: Starting Load Kernel Module configfs...
10899 12:19:36.603233 Starting [0;1;39mLoad Kernel Module configfs[0m...
10900 12:19:36.623671 <30>[ 20.997163] systemd[1]: Starting Load Kernel Module drm...
10901 12:19:36.629972 Starting [0;1;39mLoad Kernel Module drm[0m...
10902 12:19:36.646652 <30>[ 21.020245] systemd[1]: Starting Load Kernel Module fuse...
10903 12:19:36.653076 Starting [0;1;39mLoad Kernel Module fuse[0m...
10904 12:19:36.687319 <6>[ 21.060933] fuse: init (API version 7.37)
10905 12:19:36.697118 <30>[ 21.060962] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10906 12:19:36.743624 <30>[ 21.117395] systemd[1]: Starting Journal Service...
10907 12:19:36.750167 Starting [0;1;39mJournal Service[0m...
10908 12:19:36.772138 <30>[ 21.145720] systemd[1]: Starting Load Kernel Modules...
10909 12:19:36.778577 Starting [0;1;39mLoad Kernel Modules[0m...
10910 12:19:36.797916 <30>[ 21.168337] systemd[1]: Starting Remount Root and Kernel File Systems...
10911 12:19:36.804505 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10912 12:19:36.825725 <30>[ 21.199486] systemd[1]: Starting Coldplug All udev Devices...
10913 12:19:36.832681 Starting [0;1;39mColdplug All udev Devices[0m...
10914 12:19:36.850504 <30>[ 21.224346] systemd[1]: Mounted Huge Pages File System.
10915 12:19:36.857499 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10916 12:19:36.871482 <30>[ 21.245149] systemd[1]: Mounted POSIX Message Queue File System.
10917 12:19:36.878385 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10918 12:19:36.895761 <30>[ 21.269271] systemd[1]: Mounted Kernel Debug File System.
10919 12:19:36.902214 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10920 12:19:36.924436 <30>[ 21.294787] systemd[1]: Finished Create list of static device nodes for the current kernel.
10921 12:19:36.931558 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10922 12:19:36.942030 <3>[ 21.310984] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 12:19:36.948055 <30>[ 21.321646] systemd[1]: modprobe@configfs.service: Succeeded.
10924 12:19:36.954983 <30>[ 21.328597] systemd[1]: Finished Load Kernel Module configfs.
10925 12:19:36.962054 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10926 12:19:36.975345 <3>[ 21.345729] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 12:19:36.981831 <30>[ 21.355604] systemd[1]: modprobe@drm.service: Succeeded.
10928 12:19:36.988712 <30>[ 21.362166] systemd[1]: Finished Load Kernel Module drm.
10929 12:19:36.995123 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10930 12:19:37.012573 <30>[ 21.385525] systemd[1]: modprobe@fuse.service: Succeeded.
10931 12:19:37.022743 <3>[ 21.391764] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 12:19:37.029233 <30>[ 21.391938] systemd[1]: Finished Load Kernel Module fuse.
10933 12:19:37.032626 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10934 12:19:37.052142 <3>[ 21.421864] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 12:19:37.058701 <30>[ 21.421970] systemd[1]: Finished Load Kernel Modules.
10936 12:19:37.061650 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10937 12:19:37.076578 <30>[ 21.450076] systemd[1]: Finished Remount Root and Kernel File Systems.
10938 12:19:37.086483 <3>[ 21.451443] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 12:19:37.093416 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10940 12:19:37.116843 <3>[ 21.486832] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 12:19:37.146517 <3>[ 21.516671] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 12:19:37.152976 <30>[ 21.523385] systemd[1]: Mounting FUSE Control File System...
10943 12:19:37.159355 Mounting [0;1;39mFUSE Control File System[0m...
10944 12:19:37.176027 <3>[ 21.546446] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 12:19:37.182748 <30>[ 21.547322] systemd[1]: Mounting Kernel Configuration File System...
10946 12:19:37.189141 Mounting [0;1;39mKernel Configuration File System[0m...
10947 12:19:37.204680 <3>[ 21.575420] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 12:19:37.217335 <30>[ 21.588204] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10949 12:19:37.228125 <30>[ 21.597361] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10950 12:19:37.252141 <30>[ 21.625296] systemd[1]: Starting Load/Save Random Seed...
10951 12:19:37.259097 Starting [0;1;39mLoad/Save Random Seed[0m...
10952 12:19:37.269478 <3>[ 21.638739] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10953 12:19:37.278118 <30>[ 21.651823] systemd[1]: Starting Apply Kernel Variables...
10954 12:19:37.284585 Starting [0;1;39mApply Kernel Variables[0m...
10955 12:19:37.305343 <30>[ 21.679233] systemd[1]: Starting Create System Users...
10956 12:19:37.312312 Starting [0;1;39mCreate System Users[0m...
10957 12:19:37.333239 <30>[ 21.706875] systemd[1]: Mounted FUSE Control File System.
10958 12:19:37.339797 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10959 12:19:37.362488 <4>[ 21.725769] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10960 12:19:37.369028 <3>[ 21.741461] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10961 12:19:37.375705 <30>[ 21.742149] systemd[1]: Started Journal Service.
10962 12:19:37.381782 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10963 12:19:37.405405 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10964 12:19:37.422996 See 'systemctl status systemd-udev-trigger.service' for details.
10965 12:19:37.443628 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10966 12:19:37.461140 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10967 12:19:37.477466 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10968 12:19:37.493064 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10969 12:19:37.535646 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10970 12:19:37.558747 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10971 12:19:37.586447 <46>[ 21.957063] systemd-journald[298]: Received client request to flush runtime journal.
10972 12:19:37.643664 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10973 12:19:37.655906 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10974 12:19:37.671618 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10975 12:19:37.719819 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10976 12:19:38.989003 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10977 12:19:39.039874 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10978 12:19:39.073129 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10979 12:19:39.095293 Starting [0;1;39mNetwork Service[0m...
10980 12:19:39.412705 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10981 12:19:39.431088 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10982 12:19:39.480234 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10983 12:19:39.772357 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10984 12:19:39.789865 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10985 12:19:39.827605 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10986 12:19:39.848787 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10987 12:19:39.863802 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10988 12:19:39.897603 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10989 12:19:39.964351 Starting [0;1;39mNetwork Name Resolution[0m...
10990 12:19:39.987889 Starting [0;1;39mNetwork Time Synchronization[0m...
10991 12:19:40.006486 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10992 12:19:40.023284 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10993 12:19:40.062554 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10994 12:19:40.185757 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10995 12:19:40.203448 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10996 12:19:40.222965 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10997 12:19:40.235270 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10998 12:19:40.251229 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10999 12:19:40.276200 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11000 12:19:40.344389 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11001 12:19:40.387410 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11002 12:19:40.433419 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11003 12:19:40.446424 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11004 12:19:40.472051 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11005 12:19:40.486200 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11006 12:19:40.502455 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11007 12:19:40.568166 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11008 12:19:41.334692 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11009 12:19:41.722940 Starting [0;1;39mUser Login Management[0m...
11010 12:19:41.740331 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11011 12:19:41.761192 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11012 12:19:41.781496 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11013 12:19:41.827221 Starting [0;1;39mPermit User Sessions[0m...
11014 12:19:41.933668 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11015 12:19:41.986773 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11016 12:19:42.007588 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11017 12:19:42.026887 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11018 12:19:42.053533 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11019 12:19:42.081340 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11020 12:19:42.103830 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11021 12:19:42.118996 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11022 12:19:42.175312 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11023 12:19:42.220911 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11024 12:19:42.287124
11025 12:19:42.287236
11026 12:19:42.290648 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11027 12:19:42.290759
11028 12:19:42.293922 debian-bullseye-arm64 login: root (automatic login)
11029 12:19:42.294086
11030 12:19:42.294149
11031 12:19:42.599905 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024 aarch64
11032 12:19:42.600038
11033 12:19:42.606117 The programs included with the Debian GNU/Linux system are free software;
11034 12:19:42.612978 the exact distribution terms for each program are described in the
11035 12:19:42.616238 individual files in /usr/share/doc/*/copyright.
11036 12:19:42.616314
11037 12:19:42.622919 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11038 12:19:42.625854 permitted by applicable law.
11039 12:19:43.355061 Matched prompt #10: / #
11041 12:19:43.355398 Setting prompt string to ['/ #']
11042 12:19:43.355502 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11044 12:19:43.355700 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11045 12:19:43.355799 start: 2.2.6 expect-shell-connection (timeout 00:03:32) [common]
11046 12:19:43.355871 Setting prompt string to ['/ #']
11047 12:19:43.355932 Forcing a shell prompt, looking for ['/ #']
11049 12:19:43.406124 / #
11050 12:19:43.406224 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11051 12:19:43.406301 Waiting using forced prompt support (timeout 00:02:30)
11052 12:19:43.411512
11053 12:19:43.411773 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11054 12:19:43.411867 start: 2.2.7 export-device-env (timeout 00:03:32) [common]
11056 12:19:43.512163 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12669536/extract-nfsrootfs-heetpg7n'
11057 12:19:43.517256 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12669536/extract-nfsrootfs-heetpg7n'
11059 12:19:43.617756 / # export NFS_SERVER_IP='192.168.201.1'
11060 12:19:43.622948 export NFS_SERVER_IP='192.168.201.1'
11061 12:19:43.623230 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11062 12:19:43.623347 end: 2.2 depthcharge-retry (duration 00:01:28) [common]
11063 12:19:43.623443 end: 2 depthcharge-action (duration 00:01:28) [common]
11064 12:19:43.623542 start: 3 lava-test-retry (timeout 00:07:51) [common]
11065 12:19:43.623632 start: 3.1 lava-test-shell (timeout 00:07:51) [common]
11066 12:19:43.623707 Using namespace: common
11068 12:19:43.723994 / # #
11069 12:19:43.724125 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11070 12:19:43.729125 #
11071 12:19:43.729385 Using /lava-12669536
11073 12:19:43.829657 / # export SHELL=/bin/bash
11074 12:19:43.834839 export SHELL=/bin/bash
11076 12:19:43.935301 / # . /lava-12669536/environment
11077 12:19:43.940460 . /lava-12669536/environment
11079 12:19:44.045790 / # /lava-12669536/bin/lava-test-runner /lava-12669536/0
11080 12:19:44.045908 Test shell timeout: 10s (minimum of the action and connection timeout)
11081 12:19:44.050820 /lava-12669536/bin/lava-test-runner /lava-12669536/0
11082 12:19:44.272657 + export TESTRUN_ID=0_timesync-off
11083 12:19:44.275587 + TESTRUN_ID=0_timesync-off
11084 12:19:44.279059 + cd /lava-12669536/0/tests/0_timesync-off
11085 12:19:44.282074 ++ cat uuid
11086 12:19:44.285554 + UUID=12669536_1.6.2.3.1
11087 12:19:44.285631 + set +x
11088 12:19:44.292373 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12669536_1.6.2.3.1>
11089 12:19:44.292643 Received signal: <STARTRUN> 0_timesync-off 12669536_1.6.2.3.1
11090 12:19:44.292719 Starting test lava.0_timesync-off (12669536_1.6.2.3.1)
11091 12:19:44.292806 Skipping test definition patterns.
11092 12:19:44.295256 + systemctl stop systemd-timesyncd
11093 12:19:44.346530 + set +x
11094 12:19:44.349924 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12669536_1.6.2.3.1>
11095 12:19:44.350212 Received signal: <ENDRUN> 0_timesync-off 12669536_1.6.2.3.1
11096 12:19:44.350308 Ending use of test pattern.
11097 12:19:44.350383 Ending test lava.0_timesync-off (12669536_1.6.2.3.1), duration 0.06
11099 12:19:44.401242 + export TESTRUN_ID=1_kselftest-rtc
11100 12:19:44.404626 + TESTRUN_ID=1_kselftest-rtc
11101 12:19:44.407974 + cd /lava-12669536/0/tests/1_kselftest-rtc
11102 12:19:44.411356 ++ cat uuid
11103 12:19:44.414512 + UUID=12669536_1.6.2.3.5
11104 12:19:44.414602 + set +x
11105 12:19:44.417853 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 12669536_1.6.2.3.5>
11106 12:19:44.418157 Received signal: <STARTRUN> 1_kselftest-rtc 12669536_1.6.2.3.5
11107 12:19:44.418238 Starting test lava.1_kselftest-rtc (12669536_1.6.2.3.5)
11108 12:19:44.418344 Skipping test definition patterns.
11109 12:19:44.421250 + cd ./automated/linux/kselftest/
11110 12:19:44.450986 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11111 12:19:44.472595 INFO: install_deps skipped
11112 12:19:44.581176 --2024-01-31 12:19:04-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11113 12:19:44.592841 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11114 12:19:44.724328 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11115 12:19:44.855668 HTTP request sent, awaiting response... 200 OK
11116 12:19:44.858610 Length: 2966336 (2.8M) [application/octet-stream]
11117 12:19:44.862136 Saving to: 'kselftest.tar.xz'
11118 12:19:44.862254
11119 12:19:44.862321
11120 12:19:45.118977 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11121 12:19:45.381456 kselftest.tar.xz 1%[ ] 49.22K 188KB/s
11122 12:19:45.692914 kselftest.tar.xz 7%[> ] 217.50K 415KB/s
11123 12:19:45.967183 kselftest.tar.xz 28%[====> ] 819.89K 980KB/s
11124 12:19:46.091534 kselftest.tar.xz 68%[============> ] 1.93M 1.74MB/s
11125 12:19:46.098486 kselftest.tar.xz 100%[===================>] 2.83M 2.29MB/s in 1.2s
11126 12:19:46.098585
11127 12:19:46.356450 2024-01-31 12:19:06 (2.29 MB/s) - 'kselftest.tar.xz' saved [2966336/2966336]
11128 12:19:46.356587
11129 12:19:51.537373 skiplist:
11130 12:19:51.540573 ========================================
11131 12:19:51.543928 ========================================
11132 12:19:51.580871 rtc:rtctest
11133 12:19:51.596990 ============== Tests to run ===============
11134 12:19:51.597088 rtc:rtctest
11135 12:19:51.600453 ===========End Tests to run ===============
11136 12:19:51.603505 shardfile-rtc pass
11137 12:19:51.688985 <12>[ 36.064648] kselftest: Running tests in rtc
11138 12:19:51.697376 TAP version 13
11139 12:19:51.707963 1..1
11140 12:19:51.732641 # selftests: rtc: rtctest
11141 12:19:52.144936 # TAP version 13
11142 12:19:52.145091 # 1..8
11143 12:19:52.148262 # # Starting 8 tests from 2 test cases.
11144 12:19:52.151250 # # RUN rtc.date_read ...
11145 12:19:52.157869 # # rtctest.c:49:date_read:Current RTC date/time is 31/01/2024 12:19:11.
11146 12:19:52.161196 # # OK rtc.date_read
11147 12:19:52.164271 # ok 1 rtc.date_read
11148 12:19:52.167954 # # RUN rtc.date_read_loop ...
11149 12:19:52.177629 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11150 12:20:01.776433 <6>[ 46.156769] vpu: disabling
11151 12:20:01.779869 <6>[ 46.159875] vproc2: disabling
11152 12:20:01.782857 <6>[ 46.163198] vproc1: disabling
11153 12:20:01.786514 <6>[ 46.166510] vaud18: disabling
11154 12:20:01.792925 <6>[ 46.170019] vsram_others: disabling
11155 12:20:01.796482 <6>[ 46.173982] va09: disabling
11156 12:20:01.800115 <6>[ 46.177214] vsram_md: disabling
11157 12:20:01.803050 <6>[ 46.180781] Vgpu: disabling
11158 12:20:21.825794 # # rtctest.c:115:date_read_loop:Performed 2617 RTC time reads.
11159 12:20:21.829281 # # OK rtc.date_read_loop
11160 12:20:21.832359 # ok 2 rtc.date_read_loop
11161 12:20:21.835472 # # RUN rtc.uie_read ...
11162 12:20:24.810445 # # OK rtc.uie_read
11163 12:20:24.813507 # ok 3 rtc.uie_read
11164 12:20:24.816859 # # RUN rtc.uie_select ...
11165 12:20:27.810403 # # OK rtc.uie_select
11166 12:20:27.813423 # ok 4 rtc.uie_select
11167 12:20:27.817117 # # RUN rtc.alarm_alm_set ...
11168 12:20:27.823611 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 12:19:51.
11169 12:20:27.827048 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11170 12:20:27.833749 # # alarm_alm_set: Test terminated by assertion
11171 12:20:27.837159 # # FAIL rtc.alarm_alm_set
11172 12:20:27.837739 # not ok 5 rtc.alarm_alm_set
11173 12:20:27.843854 # # RUN rtc.alarm_wkalm_set ...
11174 12:20:27.849848 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 31/01/2024 12:19:51.
11175 12:20:30.812859 # # OK rtc.alarm_wkalm_set
11176 12:20:30.813437 # ok 6 rtc.alarm_wkalm_set
11177 12:20:30.819510 # # RUN rtc.alarm_alm_set_minute ...
11178 12:20:30.822669 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 12:20:00.
11179 12:20:30.829323 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11180 12:20:30.836065 # # alarm_alm_set_minute: Test terminated by assertion
11181 12:20:30.839548 # # FAIL rtc.alarm_alm_set_minute
11182 12:20:30.842308 # not ok 7 rtc.alarm_alm_set_minute
11183 12:20:30.846344 # # RUN rtc.alarm_wkalm_set_minute ...
11184 12:20:30.852250 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 31/01/2024 12:20:00.
11185 12:20:39.811908 # # OK rtc.alarm_wkalm_set_minute
11186 12:20:39.814923 # ok 8 rtc.alarm_wkalm_set_minute
11187 12:20:39.817924 # # FAILED: 6 / 8 tests passed.
11188 12:20:39.821456 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11189 12:20:39.824688 not ok 1 selftests: rtc: rtctest # exit=1
11190 12:20:40.444305 rtc_rtctest_rtc_date_read pass
11191 12:20:40.447371 rtc_rtctest_rtc_date_read_loop pass
11192 12:20:40.451258 rtc_rtctest_rtc_uie_read pass
11193 12:20:40.454391 rtc_rtctest_rtc_uie_select pass
11194 12:20:40.457431 rtc_rtctest_rtc_alarm_alm_set fail
11195 12:20:40.461011 rtc_rtctest_rtc_alarm_wkalm_set pass
11196 12:20:40.464716 rtc_rtctest_rtc_alarm_alm_set_minute fail
11197 12:20:40.467664 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11198 12:20:40.470719 rtc_rtctest fail
11199 12:20:40.477572 + ../../utils/send-to-lava.sh ./output/result.txt
11200 12:20:40.560335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11201 12:20:40.561208 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11203 12:20:40.617854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11204 12:20:40.618652 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11206 12:20:40.683466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11207 12:20:40.684149 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11209 12:20:40.742028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11210 12:20:40.742848 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11212 12:20:40.800942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11213 12:20:40.801284 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11215 12:20:40.862871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11216 12:20:40.863681 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11218 12:20:40.919753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11219 12:20:40.920476 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11221 12:20:40.984456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11222 12:20:40.985311 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11224 12:20:41.040783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11225 12:20:41.041513 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11227 12:20:41.089366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11228 12:20:41.089543 + set +x
11229 12:20:41.089816 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11231 12:20:41.096518 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 12669536_1.6.2.3.5>
11232 12:20:41.096897 Received signal: <ENDRUN> 1_kselftest-rtc 12669536_1.6.2.3.5
11233 12:20:41.097010 Ending use of test pattern.
11234 12:20:41.097093 Ending test lava.1_kselftest-rtc (12669536_1.6.2.3.5), duration 56.68
11236 12:20:41.097390 ok: lava_test_shell seems to have completed
11237 12:20:41.097559 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11238 12:20:41.097677 end: 3.1 lava-test-shell (duration 00:00:57) [common]
11239 12:20:41.097784 end: 3 lava-test-retry (duration 00:00:57) [common]
11240 12:20:41.097893 start: 4 finalize (timeout 00:06:53) [common]
11241 12:20:41.098010 start: 4.1 power-off (timeout 00:00:30) [common]
11242 12:20:41.098200 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11243 12:20:41.176979 >> Command sent successfully.
11244 12:20:41.182168 Returned 0 in 0 seconds
11245 12:20:41.283172 end: 4.1 power-off (duration 00:00:00) [common]
11247 12:20:41.285254 start: 4.2 read-feedback (timeout 00:06:53) [common]
11249 12:20:41.287498 Listened to connection for namespace 'common' for up to 1s
11250 12:20:42.286235 Finalising connection for namespace 'common'
11251 12:20:42.286953 Disconnecting from shell: Finalise
11252 12:20:42.287520 / #
11253 12:20:42.388616 end: 4.2 read-feedback (duration 00:00:01) [common]
11254 12:20:42.389314 end: 4 finalize (duration 00:00:01) [common]
11255 12:20:42.389917 Cleaning after the job
11256 12:20:42.390498 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669536/tftp-deploy-ij7nhhg4/ramdisk
11257 12:20:42.401359 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669536/tftp-deploy-ij7nhhg4/kernel
11258 12:20:42.432616 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669536/tftp-deploy-ij7nhhg4/dtb
11259 12:20:42.432948 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669536/tftp-deploy-ij7nhhg4/nfsrootfs
11260 12:20:42.505117 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669536/tftp-deploy-ij7nhhg4/modules
11261 12:20:42.510601 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12669536
11262 12:20:43.034314 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12669536
11263 12:20:43.034506 Job finished correctly