Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 17
- Kernel Errors: 37
1 12:11:13.484596 lava-dispatcher, installed at version: 2023.10
2 12:11:13.484835 start: 0 validate
3 12:11:13.484976 Start time: 2024-01-31 12:11:13.484968+00:00 (UTC)
4 12:11:13.485111 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:11:13.485252 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 12:11:13.752118 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:11:13.752312 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:11:14.026633 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:11:14.026843 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:11:14.290719 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:11:14.290948 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:11:14.825189 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:11:14.825380 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:11:14.827764 validate duration: 1.34
16 12:11:14.827993 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:11:14.828095 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:11:14.828190 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:11:14.828321 Not decompressing ramdisk as can be used compressed.
20 12:11:14.828409 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 12:11:14.828476 saving as /var/lib/lava/dispatcher/tmp/12669498/tftp-deploy-anyajq8p/ramdisk/initrd.cpio.gz
22 12:11:14.828543 total size: 4665395 (4 MB)
23 12:11:14.829596 progress 0 % (0 MB)
24 12:11:14.831135 progress 5 % (0 MB)
25 12:11:14.832417 progress 10 % (0 MB)
26 12:11:14.833727 progress 15 % (0 MB)
27 12:11:14.834984 progress 20 % (0 MB)
28 12:11:14.836227 progress 25 % (1 MB)
29 12:11:14.837479 progress 30 % (1 MB)
30 12:11:14.838759 progress 35 % (1 MB)
31 12:11:14.839992 progress 40 % (1 MB)
32 12:11:14.841388 progress 45 % (2 MB)
33 12:11:14.842703 progress 50 % (2 MB)
34 12:11:14.843962 progress 55 % (2 MB)
35 12:11:14.845205 progress 60 % (2 MB)
36 12:11:14.846485 progress 65 % (2 MB)
37 12:11:14.847716 progress 70 % (3 MB)
38 12:11:14.849079 progress 75 % (3 MB)
39 12:11:14.850360 progress 80 % (3 MB)
40 12:11:14.851779 progress 85 % (3 MB)
41 12:11:14.853041 progress 90 % (4 MB)
42 12:11:14.854390 progress 95 % (4 MB)
43 12:11:14.855651 progress 100 % (4 MB)
44 12:11:14.855810 4 MB downloaded in 0.03 s (163.18 MB/s)
45 12:11:14.855965 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:11:14.856212 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:11:14.856299 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:11:14.856383 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:11:14.856519 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:11:14.856592 saving as /var/lib/lava/dispatcher/tmp/12669498/tftp-deploy-anyajq8p/kernel/Image
52 12:11:14.856655 total size: 51532288 (49 MB)
53 12:11:14.856718 No compression specified
54 12:11:14.857854 progress 0 % (0 MB)
55 12:11:14.871466 progress 5 % (2 MB)
56 12:11:14.885189 progress 10 % (4 MB)
57 12:11:14.898538 progress 15 % (7 MB)
58 12:11:14.912523 progress 20 % (9 MB)
59 12:11:14.926277 progress 25 % (12 MB)
60 12:11:14.939603 progress 30 % (14 MB)
61 12:11:14.953138 progress 35 % (17 MB)
62 12:11:14.966855 progress 40 % (19 MB)
63 12:11:14.980382 progress 45 % (22 MB)
64 12:11:14.994034 progress 50 % (24 MB)
65 12:11:15.007399 progress 55 % (27 MB)
66 12:11:15.021106 progress 60 % (29 MB)
67 12:11:15.034850 progress 65 % (31 MB)
68 12:11:15.048141 progress 70 % (34 MB)
69 12:11:15.061700 progress 75 % (36 MB)
70 12:11:15.075310 progress 80 % (39 MB)
71 12:11:15.088809 progress 85 % (41 MB)
72 12:11:15.102326 progress 90 % (44 MB)
73 12:11:15.115851 progress 95 % (46 MB)
74 12:11:15.128984 progress 100 % (49 MB)
75 12:11:15.129247 49 MB downloaded in 0.27 s (180.29 MB/s)
76 12:11:15.129405 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:11:15.129698 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:11:15.129787 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:11:15.129879 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:11:15.130018 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:11:15.130089 saving as /var/lib/lava/dispatcher/tmp/12669498/tftp-deploy-anyajq8p/dtb/mt8192-asurada-spherion-r0.dtb
83 12:11:15.130152 total size: 47278 (0 MB)
84 12:11:15.130216 No compression specified
85 12:11:15.131338 progress 69 % (0 MB)
86 12:11:15.131616 progress 100 % (0 MB)
87 12:11:15.131773 0 MB downloaded in 0.00 s (27.86 MB/s)
88 12:11:15.131899 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:11:15.132127 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:11:15.132216 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:11:15.132299 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:11:15.132417 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 12:11:15.132523 saving as /var/lib/lava/dispatcher/tmp/12669498/tftp-deploy-anyajq8p/nfsrootfs/full.rootfs.tar
95 12:11:15.132589 total size: 200813988 (191 MB)
96 12:11:15.132652 Using unxz to decompress xz
97 12:11:15.136965 progress 0 % (0 MB)
98 12:11:15.670260 progress 5 % (9 MB)
99 12:11:16.186250 progress 10 % (19 MB)
100 12:11:16.776959 progress 15 % (28 MB)
101 12:11:17.155329 progress 20 % (38 MB)
102 12:11:17.496426 progress 25 % (47 MB)
103 12:11:18.110595 progress 30 % (57 MB)
104 12:11:18.673832 progress 35 % (67 MB)
105 12:11:19.276984 progress 40 % (76 MB)
106 12:11:19.847099 progress 45 % (86 MB)
107 12:11:20.443226 progress 50 % (95 MB)
108 12:11:21.082476 progress 55 % (105 MB)
109 12:11:21.751118 progress 60 % (114 MB)
110 12:11:21.870051 progress 65 % (124 MB)
111 12:11:22.009088 progress 70 % (134 MB)
112 12:11:22.111274 progress 75 % (143 MB)
113 12:11:22.187256 progress 80 % (153 MB)
114 12:11:22.262640 progress 85 % (162 MB)
115 12:11:22.371981 progress 90 % (172 MB)
116 12:11:22.661731 progress 95 % (181 MB)
117 12:11:23.235631 progress 100 % (191 MB)
118 12:11:23.240899 191 MB downloaded in 8.11 s (23.62 MB/s)
119 12:11:23.241155 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:11:23.241419 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:11:23.241586 start: 1.5 download-retry (timeout 00:09:52) [common]
123 12:11:23.241678 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 12:11:23.241837 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:11:23.241911 saving as /var/lib/lava/dispatcher/tmp/12669498/tftp-deploy-anyajq8p/modules/modules.tar
126 12:11:23.241976 total size: 8639916 (8 MB)
127 12:11:23.242042 Using unxz to decompress xz
128 12:11:23.511254 progress 0 % (0 MB)
129 12:11:23.571946 progress 5 % (0 MB)
130 12:11:23.597078 progress 10 % (0 MB)
131 12:11:23.620665 progress 15 % (1 MB)
132 12:11:23.644199 progress 20 % (1 MB)
133 12:11:23.668137 progress 25 % (2 MB)
134 12:11:23.695319 progress 30 % (2 MB)
135 12:11:23.719216 progress 35 % (2 MB)
136 12:11:23.742411 progress 40 % (3 MB)
137 12:11:23.766837 progress 45 % (3 MB)
138 12:11:23.792074 progress 50 % (4 MB)
139 12:11:23.818703 progress 55 % (4 MB)
140 12:11:23.843623 progress 60 % (4 MB)
141 12:11:23.869161 progress 65 % (5 MB)
142 12:11:23.894442 progress 70 % (5 MB)
143 12:11:23.917995 progress 75 % (6 MB)
144 12:11:23.945715 progress 80 % (6 MB)
145 12:11:23.973807 progress 85 % (7 MB)
146 12:11:23.999071 progress 90 % (7 MB)
147 12:11:24.030374 progress 95 % (7 MB)
148 12:11:24.059774 progress 100 % (8 MB)
149 12:11:24.065990 8 MB downloaded in 0.82 s (10.00 MB/s)
150 12:11:24.066245 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:11:24.066508 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:11:24.066605 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:11:24.066703 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:11:27.638315 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12669498/extract-nfsrootfs-y_nv2isg
156 12:11:27.638565 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 12:11:27.638713 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 12:11:27.638965 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05
159 12:11:27.639165 makedir: /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin
160 12:11:27.639319 makedir: /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/tests
161 12:11:27.639465 makedir: /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/results
162 12:11:27.639610 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-add-keys
163 12:11:27.639813 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-add-sources
164 12:11:27.639996 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-background-process-start
165 12:11:27.640178 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-background-process-stop
166 12:11:27.640360 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-common-functions
167 12:11:27.640539 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-echo-ipv4
168 12:11:27.640721 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-install-packages
169 12:11:27.640901 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-installed-packages
170 12:11:27.641094 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-os-build
171 12:11:27.641292 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-probe-channel
172 12:11:27.641488 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-probe-ip
173 12:11:27.641675 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-target-ip
174 12:11:27.641859 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-target-mac
175 12:11:27.642044 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-target-storage
176 12:11:27.642233 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-test-case
177 12:11:27.642421 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-test-event
178 12:11:27.642603 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-test-feedback
179 12:11:27.642791 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-test-raise
180 12:11:27.642975 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-test-reference
181 12:11:27.643162 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-test-runner
182 12:11:27.643347 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-test-set
183 12:11:27.643535 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-test-shell
184 12:11:27.643722 Updating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-add-keys (debian)
185 12:11:27.643939 Updating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-add-sources (debian)
186 12:11:27.644148 Updating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-install-packages (debian)
187 12:11:27.644352 Updating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-installed-packages (debian)
188 12:11:27.644557 Updating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/bin/lava-os-build (debian)
189 12:11:27.644738 Creating /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/environment
190 12:11:27.644880 LAVA metadata
191 12:11:27.644989 - LAVA_JOB_ID=12669498
192 12:11:27.645088 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:11:27.645263 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 12:11:27.645376 skipped lava-vland-overlay
195 12:11:27.645512 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:11:27.645642 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 12:11:27.645738 skipped lava-multinode-overlay
198 12:11:27.645850 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:11:27.645967 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 12:11:27.646083 Loading test definitions
201 12:11:27.646217 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 12:11:27.646328 Using /lava-12669498 at stage 0
203 12:11:27.646747 uuid=12669498_1.6.2.3.1 testdef=None
204 12:11:27.646874 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:11:27.646998 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 12:11:27.647655 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:11:27.647998 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 12:11:27.648893 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:11:27.649298 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 12:11:27.650319 runner path: /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/0/tests/0_timesync-off test_uuid 12669498_1.6.2.3.1
213 12:11:27.650543 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:11:27.650902 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 12:11:27.651013 Using /lava-12669498 at stage 0
217 12:11:27.651162 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:11:27.651278 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/0/tests/1_kselftest-tpm2'
219 12:11:35.598704 Running '/usr/bin/git checkout kernelci.org
220 12:11:35.752650 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 12:11:35.753655 uuid=12669498_1.6.2.3.5 testdef=None
222 12:11:35.753839 end: 1.6.2.3.5 git-repo-action (duration 00:00:08) [common]
224 12:11:35.754108 start: 1.6.2.3.6 test-overlay (timeout 00:09:39) [common]
225 12:11:35.754898 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:11:35.755137 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:39) [common]
228 12:11:35.756151 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:11:35.756392 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:39) [common]
231 12:11:35.757360 runner path: /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/0/tests/1_kselftest-tpm2 test_uuid 12669498_1.6.2.3.5
232 12:11:35.757456 BOARD='mt8192-asurada-spherion-r0'
233 12:11:35.757537 BRANCH='cip-gitlab'
234 12:11:35.757600 SKIPFILE='/dev/null'
235 12:11:35.757660 SKIP_INSTALL='True'
236 12:11:35.757718 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:11:35.757781 TST_CASENAME=''
238 12:11:35.757838 TST_CMDFILES='tpm2'
239 12:11:35.757984 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:11:35.758197 Creating lava-test-runner.conf files
242 12:11:35.758262 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12669498/lava-overlay-wc98rq05/lava-12669498/0 for stage 0
243 12:11:35.758360 - 0_timesync-off
244 12:11:35.758430 - 1_kselftest-tpm2
245 12:11:35.758528 end: 1.6.2.3 test-definition (duration 00:00:08) [common]
246 12:11:35.758616 start: 1.6.2.4 compress-overlay (timeout 00:09:39) [common]
247 12:11:43.346148 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 12:11:43.346312 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:31) [common]
249 12:11:43.346404 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:11:43.346510 end: 1.6.2 lava-overlay (duration 00:00:16) [common]
251 12:11:43.346635 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:31) [common]
252 12:11:43.468932 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:11:43.469338 start: 1.6.4 extract-modules (timeout 00:09:31) [common]
254 12:11:43.469461 extracting modules file /var/lib/lava/dispatcher/tmp/12669498/tftp-deploy-anyajq8p/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12669498/extract-nfsrootfs-y_nv2isg
255 12:11:43.697228 extracting modules file /var/lib/lava/dispatcher/tmp/12669498/tftp-deploy-anyajq8p/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12669498/extract-overlay-ramdisk-pl0rhn4g/ramdisk
256 12:11:43.930287 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 12:11:43.930461 start: 1.6.5 apply-overlay-tftp (timeout 00:09:31) [common]
258 12:11:43.930563 [common] Applying overlay to NFS
259 12:11:43.930638 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12669498/compress-overlay-cxbur2ez/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12669498/extract-nfsrootfs-y_nv2isg
260 12:11:44.881918 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:11:44.882097 start: 1.6.6 configure-preseed-file (timeout 00:09:30) [common]
262 12:11:44.882194 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:11:44.882290 start: 1.6.7 compress-ramdisk (timeout 00:09:30) [common]
264 12:11:44.882378 Building ramdisk /var/lib/lava/dispatcher/tmp/12669498/extract-overlay-ramdisk-pl0rhn4g/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12669498/extract-overlay-ramdisk-pl0rhn4g/ramdisk
265 12:11:45.215577 >> 119414 blocks
266 12:11:47.204033 rename /var/lib/lava/dispatcher/tmp/12669498/extract-overlay-ramdisk-pl0rhn4g/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12669498/tftp-deploy-anyajq8p/ramdisk/ramdisk.cpio.gz
267 12:11:47.204494 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:11:47.204619 start: 1.6.8 prepare-kernel (timeout 00:09:28) [common]
269 12:11:47.204728 start: 1.6.8.1 prepare-fit (timeout 00:09:28) [common]
270 12:11:47.204838 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12669498/tftp-deploy-anyajq8p/kernel/Image'
271 12:12:00.135352 Returned 0 in 12 seconds
272 12:12:00.236446 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12669498/tftp-deploy-anyajq8p/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12669498/tftp-deploy-anyajq8p/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12669498/tftp-deploy-anyajq8p/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12669498/tftp-deploy-anyajq8p/kernel/image.itb
273 12:12:01.502758 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:12:01.504450 output: Created: Wed Jan 31 12:12:01 2024
275 12:12:01.504827 output: Image 0 (kernel-1)
276 12:12:01.505185 output: Description:
277 12:12:01.505550 output: Created: Wed Jan 31 12:12:01 2024
278 12:12:01.505875 output: Type: Kernel Image
279 12:12:01.506219 output: Compression: lzma compressed
280 12:12:01.506775 output: Data Size: 12047284 Bytes = 11764.93 KiB = 11.49 MiB
281 12:12:01.507120 output: Architecture: AArch64
282 12:12:01.507444 output: OS: Linux
283 12:12:01.507540 output: Load Address: 0x00000000
284 12:12:01.507599 output: Entry Point: 0x00000000
285 12:12:01.507654 output: Hash algo: crc32
286 12:12:01.507713 output: Hash value: 5a47eb78
287 12:12:01.507773 output: Image 1 (fdt-1)
288 12:12:01.507826 output: Description: mt8192-asurada-spherion-r0
289 12:12:01.507880 output: Created: Wed Jan 31 12:12:01 2024
290 12:12:01.507934 output: Type: Flat Device Tree
291 12:12:01.507988 output: Compression: uncompressed
292 12:12:01.508042 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 12:12:01.508096 output: Architecture: AArch64
294 12:12:01.508150 output: Hash algo: crc32
295 12:12:01.508220 output: Hash value: cc4352de
296 12:12:01.508322 output: Image 2 (ramdisk-1)
297 12:12:01.508389 output: Description: unavailable
298 12:12:01.508443 output: Created: Wed Jan 31 12:12:01 2024
299 12:12:01.508510 output: Type: RAMDisk Image
300 12:12:01.508579 output: Compression: Unknown Compression
301 12:12:01.508662 output: Data Size: 17804195 Bytes = 17386.91 KiB = 16.98 MiB
302 12:12:01.508716 output: Architecture: AArch64
303 12:12:01.508770 output: OS: Linux
304 12:12:01.508824 output: Load Address: unavailable
305 12:12:01.508878 output: Entry Point: unavailable
306 12:12:01.508932 output: Hash algo: crc32
307 12:12:01.508998 output: Hash value: cdb3de74
308 12:12:01.509080 output: Default Configuration: 'conf-1'
309 12:12:01.509133 output: Configuration 0 (conf-1)
310 12:12:01.509186 output: Description: mt8192-asurada-spherion-r0
311 12:12:01.509239 output: Kernel: kernel-1
312 12:12:01.509291 output: Init Ramdisk: ramdisk-1
313 12:12:01.509344 output: FDT: fdt-1
314 12:12:01.509409 output: Loadables: kernel-1
315 12:12:01.509463 output:
316 12:12:01.509712 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 12:12:01.509813 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 12:12:01.509919 end: 1.6 prepare-tftp-overlay (duration 00:00:37) [common]
319 12:12:01.510011 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:13) [common]
320 12:12:01.510093 No LXC device requested
321 12:12:01.510175 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:12:01.510260 start: 1.8 deploy-device-env (timeout 00:09:13) [common]
323 12:12:01.510339 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:12:01.510411 Checking files for TFTP limit of 4294967296 bytes.
325 12:12:01.510928 end: 1 tftp-deploy (duration 00:00:47) [common]
326 12:12:01.511050 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:12:01.511145 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:12:01.511276 substitutions:
329 12:12:01.511347 - {DTB}: 12669498/tftp-deploy-anyajq8p/dtb/mt8192-asurada-spherion-r0.dtb
330 12:12:01.511413 - {INITRD}: 12669498/tftp-deploy-anyajq8p/ramdisk/ramdisk.cpio.gz
331 12:12:01.511474 - {KERNEL}: 12669498/tftp-deploy-anyajq8p/kernel/Image
332 12:12:01.511533 - {LAVA_MAC}: None
333 12:12:01.511591 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12669498/extract-nfsrootfs-y_nv2isg
334 12:12:01.511648 - {NFS_SERVER_IP}: 192.168.201.1
335 12:12:01.511705 - {PRESEED_CONFIG}: None
336 12:12:01.511761 - {PRESEED_LOCAL}: None
337 12:12:01.511819 - {RAMDISK}: 12669498/tftp-deploy-anyajq8p/ramdisk/ramdisk.cpio.gz
338 12:12:01.511875 - {ROOT_PART}: None
339 12:12:01.511931 - {ROOT}: None
340 12:12:01.511988 - {SERVER_IP}: 192.168.201.1
341 12:12:01.512044 - {TEE}: None
342 12:12:01.512100 Parsed boot commands:
343 12:12:01.512155 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:12:01.512375 Parsed boot commands: tftpboot 192.168.201.1 12669498/tftp-deploy-anyajq8p/kernel/image.itb 12669498/tftp-deploy-anyajq8p/kernel/cmdline
345 12:12:01.512466 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:12:01.512553 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:12:01.512648 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:12:01.512736 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:12:01.512811 Not connected, no need to disconnect.
350 12:12:01.512888 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:12:01.512974 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:12:01.513041 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
353 12:12:01.517164 Setting prompt string to ['lava-test: # ']
354 12:12:01.517584 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:12:01.517696 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:12:01.517797 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:12:01.517893 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:12:01.518091 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
359 12:12:06.665884 >> Command sent successfully.
360 12:12:06.676193 Returned 0 in 5 seconds
361 12:12:06.777591 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:12:06.779166 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:12:06.779769 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:12:06.780304 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:12:06.780865 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:12:06.781350 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:12:06.782788 [Enter `^Ec?' for help]
369 12:12:06.941377
370 12:12:06.941949
371 12:12:06.942417 F0: 102B 0000
372 12:12:06.942867
373 12:12:06.943298 F3: 1001 0000 [0200]
374 12:12:06.944888
375 12:12:06.945467 F3: 1001 0000
376 12:12:06.946058
377 12:12:06.946591 F7: 102D 0000
378 12:12:06.947020
379 12:12:06.948304 F1: 0000 0000
380 12:12:06.948761
381 12:12:06.949221 V0: 0000 0000 [0001]
382 12:12:06.949756
383 12:12:06.950187 00: 0007 8000
384 12:12:06.950628
385 12:12:06.952397 01: 0000 0000
386 12:12:06.952857
387 12:12:06.953314 BP: 0C00 0209 [0000]
388 12:12:06.953799
389 12:12:06.955897 G0: 1182 0000
390 12:12:06.956355
391 12:12:06.956817 EC: 0000 0021 [4000]
392 12:12:06.957250
393 12:12:06.959716 S7: 0000 0000 [0000]
394 12:12:06.960168
395 12:12:06.960629 CC: 0000 0000 [0001]
396 12:12:06.961065
397 12:12:06.962656 T0: 0000 0040 [010F]
398 12:12:06.963128
399 12:12:06.963590 Jump to BL
400 12:12:06.964029
401 12:12:06.988341
402 12:12:06.988790
403 12:12:06.989255
404 12:12:06.995349 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:12:06.999156 ARM64: Exception handlers installed.
406 12:12:07.002856 ARM64: Testing exception
407 12:12:07.006478 ARM64: Done test exception
408 12:12:07.013787 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:12:07.021135 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:12:07.028625 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:12:07.038890 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:12:07.045581 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:12:07.055565 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:12:07.066233 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:12:07.072937 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:12:07.091094 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:12:07.094101 WDT: Last reset was cold boot
418 12:12:07.097547 SPI1(PAD0) initialized at 2873684 Hz
419 12:12:07.101116 SPI5(PAD0) initialized at 992727 Hz
420 12:12:07.104370 VBOOT: Loading verstage.
421 12:12:07.110987 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:12:07.114557 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:12:07.117692 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:12:07.120803 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:12:07.128451 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:12:07.134797 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:12:07.145637 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
428 12:12:07.146079
429 12:12:07.146432
430 12:12:07.156008 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:12:07.159003 ARM64: Exception handlers installed.
432 12:12:07.162513 ARM64: Testing exception
433 12:12:07.163009 ARM64: Done test exception
434 12:12:07.169056 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:12:07.173168 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:12:07.186951 Probing TPM: . done!
437 12:12:07.187452 TPM ready after 0 ms
438 12:12:07.193675 Connected to device vid:did:rid of 1ae0:0028:00
439 12:12:07.200404 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 12:12:07.278304 Initialized TPM device CR50 revision 0
441 12:12:07.289968 tlcl_send_startup: Startup return code is 0
442 12:12:07.290430 TPM: setup succeeded
443 12:12:07.302777 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:12:07.312053 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:12:07.323880 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:12:07.334121 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:12:07.337523 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:12:07.340968 in-header: 03 07 00 00 08 00 00 00
449 12:12:07.345313 in-data: aa e4 47 04 13 02 00 00
450 12:12:07.345857 Chrome EC: UHEPI supported
451 12:12:07.351882 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:12:07.355048 in-header: 03 95 00 00 08 00 00 00
453 12:12:07.358540 in-data: 18 20 20 08 00 00 00 00
454 12:12:07.361570 Phase 1
455 12:12:07.364926 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:12:07.371685 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:12:07.375262 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:12:07.378496 Recovery requested (1009000e)
459 12:12:07.387697 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:12:07.393269 tlcl_extend: response is 0
461 12:12:07.402291 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:12:07.408036 tlcl_extend: response is 0
463 12:12:07.414756 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:12:07.435599 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
465 12:12:07.442924 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:12:07.443032
467 12:12:07.443112
468 12:12:07.450427 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:12:07.454127 ARM64: Exception handlers installed.
470 12:12:07.457992 ARM64: Testing exception
471 12:12:07.458094 ARM64: Done test exception
472 12:12:07.480940 pmic_efuse_setting: Set efuses in 11 msecs
473 12:12:07.484798 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:12:07.488009 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:12:07.495015 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:12:07.498144 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:12:07.504674 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:12:07.508400 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:12:07.514728 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:12:07.518384 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:12:07.524862 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:12:07.527998 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:12:07.531470 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:12:07.538024 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:12:07.541861 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:12:07.545086 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:12:07.552374 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:12:07.559521 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:12:07.563112 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:12:07.570258 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:12:07.576646 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:12:07.580307 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:12:07.586956 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:12:07.593454 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:12:07.597014 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:12:07.603974 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:12:07.607907 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:12:07.615143 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:12:07.618950 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:12:07.626270 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:12:07.630116 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:12:07.634063 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:12:07.640907 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:12:07.644441 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:12:07.650857 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:12:07.654413 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:12:07.660891 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:12:07.664144 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:12:07.671047 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:12:07.674100 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:12:07.680733 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:12:07.684086 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:12:07.687428 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:12:07.694146 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:12:07.697408 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:12:07.700868 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:12:07.704055 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:12:07.711059 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:12:07.714305 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:12:07.717512 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:12:07.724129 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:12:07.727676 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:12:07.730672 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:12:07.734345 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:12:07.743900 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:12:07.750630 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:12:07.757292 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:12:07.763829 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:12:07.774027 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:12:07.777504 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:12:07.780902 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:12:07.787581 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:12:07.794053 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x23
534 12:12:07.797522 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:12:07.805174 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 12:12:07.808318 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:12:07.818021 [RTC]rtc_get_frequency_meter,154: input=15, output=793
538 12:12:07.821141 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 12:12:07.824769 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 12:12:07.831729 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 12:12:07.835041 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 12:12:07.838625 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 12:12:07.841856 ADC[4]: Raw value=894821 ID=7
544 12:12:07.845554 ADC[3]: Raw value=212700 ID=1
545 12:12:07.845959 RAM Code: 0x71
546 12:12:07.852891 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 12:12:07.856437 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 12:12:07.863634 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 12:12:07.870788 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 12:12:07.874002 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 12:12:07.877227 in-header: 03 07 00 00 08 00 00 00
552 12:12:07.880844 in-data: aa e4 47 04 13 02 00 00
553 12:12:07.884038 Chrome EC: UHEPI supported
554 12:12:07.891409 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 12:12:07.894945 in-header: 03 d5 00 00 08 00 00 00
556 12:12:07.898217 in-data: 98 20 60 08 00 00 00 00
557 12:12:07.901556 MRC: failed to locate region type 0.
558 12:12:07.908243 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 12:12:07.911704 DRAM-K: Running full calibration
560 12:12:07.918426 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 12:12:07.918865 header.status = 0x0
562 12:12:07.921529 header.version = 0x6 (expected: 0x6)
563 12:12:07.924943 header.size = 0xd00 (expected: 0xd00)
564 12:12:07.928177 header.flags = 0x0
565 12:12:07.934913 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 12:12:07.950943 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
567 12:12:07.957667 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 12:12:07.960847 dram_init: ddr_geometry: 2
569 12:12:07.964202 [EMI] MDL number = 2
570 12:12:07.964637 [EMI] Get MDL freq = 0
571 12:12:07.967863 dram_init: ddr_type: 0
572 12:12:07.968300 is_discrete_lpddr4: 1
573 12:12:07.970973 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 12:12:07.971407
575 12:12:07.971756
576 12:12:07.974533 [Bian_co] ETT version 0.0.0.1
577 12:12:07.981145 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 12:12:07.981619
579 12:12:07.984266 dramc_set_vcore_voltage set vcore to 650000
580 12:12:07.984703 Read voltage for 800, 4
581 12:12:07.987777 Vio18 = 0
582 12:12:07.988213 Vcore = 650000
583 12:12:07.988563 Vdram = 0
584 12:12:07.991130 Vddq = 0
585 12:12:07.991568 Vmddr = 0
586 12:12:07.994478 dram_init: config_dvfs: 1
587 12:12:07.997453 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 12:12:08.004296 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 12:12:08.007751 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 12:12:08.011104 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 12:12:08.014547 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 12:12:08.017763 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 12:12:08.021233 MEM_TYPE=3, freq_sel=18
594 12:12:08.024368 sv_algorithm_assistance_LP4_1600
595 12:12:08.027901 ============ PULL DRAM RESETB DOWN ============
596 12:12:08.030820 ========== PULL DRAM RESETB DOWN end =========
597 12:12:08.037731 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 12:12:08.041232 ===================================
599 12:12:08.041718 LPDDR4 DRAM CONFIGURATION
600 12:12:08.044433 ===================================
601 12:12:08.048024 EX_ROW_EN[0] = 0x0
602 12:12:08.051275 EX_ROW_EN[1] = 0x0
603 12:12:08.051708 LP4Y_EN = 0x0
604 12:12:08.054335 WORK_FSP = 0x0
605 12:12:08.054771 WL = 0x2
606 12:12:08.057851 RL = 0x2
607 12:12:08.058286 BL = 0x2
608 12:12:08.061092 RPST = 0x0
609 12:12:08.061587 RD_PRE = 0x0
610 12:12:08.064307 WR_PRE = 0x1
611 12:12:08.064737 WR_PST = 0x0
612 12:12:08.067660 DBI_WR = 0x0
613 12:12:08.068092 DBI_RD = 0x0
614 12:12:08.071108 OTF = 0x1
615 12:12:08.074466 ===================================
616 12:12:08.077716 ===================================
617 12:12:08.078148 ANA top config
618 12:12:08.081183 ===================================
619 12:12:08.084447 DLL_ASYNC_EN = 0
620 12:12:08.088014 ALL_SLAVE_EN = 1
621 12:12:08.091166 NEW_RANK_MODE = 1
622 12:12:08.091600 DLL_IDLE_MODE = 1
623 12:12:08.094635 LP45_APHY_COMB_EN = 1
624 12:12:08.098179 TX_ODT_DIS = 1
625 12:12:08.101075 NEW_8X_MODE = 1
626 12:12:08.104727 ===================================
627 12:12:08.107815 ===================================
628 12:12:08.108251 data_rate = 1600
629 12:12:08.111367 CKR = 1
630 12:12:08.114567 DQ_P2S_RATIO = 8
631 12:12:08.117861 ===================================
632 12:12:08.121118 CA_P2S_RATIO = 8
633 12:12:08.124473 DQ_CA_OPEN = 0
634 12:12:08.128016 DQ_SEMI_OPEN = 0
635 12:12:08.128452 CA_SEMI_OPEN = 0
636 12:12:08.132057 CA_FULL_RATE = 0
637 12:12:08.135500 DQ_CKDIV4_EN = 1
638 12:12:08.138951 CA_CKDIV4_EN = 1
639 12:12:08.139401 CA_PREDIV_EN = 0
640 12:12:08.142861 PH8_DLY = 0
641 12:12:08.146421 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 12:12:08.150243 DQ_AAMCK_DIV = 4
643 12:12:08.150674 CA_AAMCK_DIV = 4
644 12:12:08.153984 CA_ADMCK_DIV = 4
645 12:12:08.158263 DQ_TRACK_CA_EN = 0
646 12:12:08.158699 CA_PICK = 800
647 12:12:08.161948 CA_MCKIO = 800
648 12:12:08.165707 MCKIO_SEMI = 0
649 12:12:08.169227 PLL_FREQ = 3068
650 12:12:08.173147 DQ_UI_PI_RATIO = 32
651 12:12:08.173637 CA_UI_PI_RATIO = 0
652 12:12:08.176858 ===================================
653 12:12:08.180498 ===================================
654 12:12:08.184051 memory_type:LPDDR4
655 12:12:08.184485 GP_NUM : 10
656 12:12:08.187876 SRAM_EN : 1
657 12:12:08.188396 MD32_EN : 0
658 12:12:08.191758 ===================================
659 12:12:08.194996 [ANA_INIT] >>>>>>>>>>>>>>
660 12:12:08.198663 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 12:12:08.202309 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 12:12:08.206469 ===================================
663 12:12:08.207037 data_rate = 1600,PCW = 0X7600
664 12:12:08.209710 ===================================
665 12:12:08.213441 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 12:12:08.221160 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 12:12:08.224741 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 12:12:08.228234 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 12:12:08.232327 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 12:12:08.235850 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 12:12:08.239325 [ANA_INIT] flow start
672 12:12:08.239961 [ANA_INIT] PLL >>>>>>>>
673 12:12:08.243077 [ANA_INIT] PLL <<<<<<<<
674 12:12:08.246663 [ANA_INIT] MIDPI >>>>>>>>
675 12:12:08.247274 [ANA_INIT] MIDPI <<<<<<<<
676 12:12:08.250365 [ANA_INIT] DLL >>>>>>>>
677 12:12:08.250960 [ANA_INIT] flow end
678 12:12:08.257802 ============ LP4 DIFF to SE enter ============
679 12:12:08.261570 ============ LP4 DIFF to SE exit ============
680 12:12:08.262052 [ANA_INIT] <<<<<<<<<<<<<
681 12:12:08.265224 [Flow] Enable top DCM control >>>>>
682 12:12:08.268253 [Flow] Enable top DCM control <<<<<
683 12:12:08.271800 Enable DLL master slave shuffle
684 12:12:08.278456 ==============================================================
685 12:12:08.278892 Gating Mode config
686 12:12:08.285122 ==============================================================
687 12:12:08.285745 Config description:
688 12:12:08.295019 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 12:12:08.301733 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 12:12:08.308394 SELPH_MODE 0: By rank 1: By Phase
691 12:12:08.311734 ==============================================================
692 12:12:08.314911 GAT_TRACK_EN = 1
693 12:12:08.318264 RX_GATING_MODE = 2
694 12:12:08.321687 RX_GATING_TRACK_MODE = 2
695 12:12:08.325177 SELPH_MODE = 1
696 12:12:08.328339 PICG_EARLY_EN = 1
697 12:12:08.331850 VALID_LAT_VALUE = 1
698 12:12:08.338597 ==============================================================
699 12:12:08.341600 Enter into Gating configuration >>>>
700 12:12:08.345072 Exit from Gating configuration <<<<
701 12:12:08.345647 Enter into DVFS_PRE_config >>>>>
702 12:12:08.358524 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 12:12:08.361762 Exit from DVFS_PRE_config <<<<<
704 12:12:08.365014 Enter into PICG configuration >>>>
705 12:12:08.368607 Exit from PICG configuration <<<<
706 12:12:08.369046 [RX_INPUT] configuration >>>>>
707 12:12:08.371968 [RX_INPUT] configuration <<<<<
708 12:12:08.378393 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 12:12:08.381556 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 12:12:08.388726 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 12:12:08.396181 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 12:12:08.403459 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 12:12:08.406935 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 12:12:08.410616 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 12:12:08.414245 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 12:12:08.421804 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 12:12:08.425456 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 12:12:08.429064 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 12:12:08.432655 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 12:12:08.436584 ===================================
721 12:12:08.439605 LPDDR4 DRAM CONFIGURATION
722 12:12:08.443344 ===================================
723 12:12:08.443847 EX_ROW_EN[0] = 0x0
724 12:12:08.447084 EX_ROW_EN[1] = 0x0
725 12:12:08.447515 LP4Y_EN = 0x0
726 12:12:08.450881 WORK_FSP = 0x0
727 12:12:08.451314 WL = 0x2
728 12:12:08.454560 RL = 0x2
729 12:12:08.455070 BL = 0x2
730 12:12:08.455430 RPST = 0x0
731 12:12:08.458255 RD_PRE = 0x0
732 12:12:08.458683 WR_PRE = 0x1
733 12:12:08.461544 WR_PST = 0x0
734 12:12:08.462151 DBI_WR = 0x0
735 12:12:08.465595 DBI_RD = 0x0
736 12:12:08.466022 OTF = 0x1
737 12:12:08.469169 ===================================
738 12:12:08.472532 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 12:12:08.476261 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 12:12:08.483328 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 12:12:08.486941 ===================================
742 12:12:08.487394 LPDDR4 DRAM CONFIGURATION
743 12:12:08.490534 ===================================
744 12:12:08.494268 EX_ROW_EN[0] = 0x10
745 12:12:08.494746 EX_ROW_EN[1] = 0x0
746 12:12:08.498283 LP4Y_EN = 0x0
747 12:12:08.498803 WORK_FSP = 0x0
748 12:12:08.502119 WL = 0x2
749 12:12:08.502575 RL = 0x2
750 12:12:08.505459 BL = 0x2
751 12:12:08.505987 RPST = 0x0
752 12:12:08.509001 RD_PRE = 0x0
753 12:12:08.509449 WR_PRE = 0x1
754 12:12:08.512557 WR_PST = 0x0
755 12:12:08.513007 DBI_WR = 0x0
756 12:12:08.513402 DBI_RD = 0x0
757 12:12:08.516465 OTF = 0x1
758 12:12:08.519920 ===================================
759 12:12:08.527230 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 12:12:08.531347 nWR fixed to 40
761 12:12:08.531963 [ModeRegInit_LP4] CH0 RK0
762 12:12:08.535082 [ModeRegInit_LP4] CH0 RK1
763 12:12:08.535694 [ModeRegInit_LP4] CH1 RK0
764 12:12:08.538620 [ModeRegInit_LP4] CH1 RK1
765 12:12:08.539087 match AC timing 13
766 12:12:08.545861 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 12:12:08.549561 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 12:12:08.553146 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 12:12:08.556976 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 12:12:08.560668 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 12:12:08.564332 [EMI DOE] emi_dcm 0
772 12:12:08.567777 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 12:12:08.568206 ==
774 12:12:08.571745 Dram Type= 6, Freq= 0, CH_0, rank 0
775 12:12:08.575299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 12:12:08.575829 ==
777 12:12:08.582505 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 12:12:08.589133 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 12:12:08.597056 [CA 0] Center 38 (7~69) winsize 63
780 12:12:08.600600 [CA 1] Center 37 (7~68) winsize 62
781 12:12:08.604431 [CA 2] Center 35 (5~66) winsize 62
782 12:12:08.608225 [CA 3] Center 35 (5~66) winsize 62
783 12:12:08.611746 [CA 4] Center 34 (4~65) winsize 62
784 12:12:08.615187 [CA 5] Center 34 (4~65) winsize 62
785 12:12:08.615645
786 12:12:08.619505 [CmdBusTrainingLP45] Vref(ca) range 1: 34
787 12:12:08.619938
788 12:12:08.623378 [CATrainingPosCal] consider 1 rank data
789 12:12:08.623870 u2DelayCellTimex100 = 270/100 ps
790 12:12:08.626844 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 12:12:08.630770 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
792 12:12:08.634493 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
793 12:12:08.637811 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 12:12:08.641302 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 12:12:08.644965 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
796 12:12:08.645408
797 12:12:08.648888 CA PerBit enable=1, Macro0, CA PI delay=34
798 12:12:08.649321
799 12:12:08.652364 [CBTSetCACLKResult] CA Dly = 34
800 12:12:08.656057 CS Dly: 6 (0~37)
801 12:12:08.656541 ==
802 12:12:08.659459 Dram Type= 6, Freq= 0, CH_0, rank 1
803 12:12:08.663086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 12:12:08.663611 ==
805 12:12:08.666831 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 12:12:08.673871 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 12:12:08.683791 [CA 0] Center 38 (7~69) winsize 63
808 12:12:08.687372 [CA 1] Center 37 (7~68) winsize 62
809 12:12:08.690987 [CA 2] Center 35 (5~66) winsize 62
810 12:12:08.694211 [CA 3] Center 35 (5~66) winsize 62
811 12:12:08.697788 [CA 4] Center 34 (4~65) winsize 62
812 12:12:08.700694 [CA 5] Center 34 (4~65) winsize 62
813 12:12:08.701142
814 12:12:08.703994 [CmdBusTrainingLP45] Vref(ca) range 1: 32
815 12:12:08.704471
816 12:12:08.707582 [CATrainingPosCal] consider 2 rank data
817 12:12:08.710955 u2DelayCellTimex100 = 270/100 ps
818 12:12:08.714134 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 12:12:08.717314 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 12:12:08.720835 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 12:12:08.724040 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 12:12:08.727750 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 12:12:08.730754 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
824 12:12:08.733912
825 12:12:08.737533 CA PerBit enable=1, Macro0, CA PI delay=34
826 12:12:08.738080
827 12:12:08.740752 [CBTSetCACLKResult] CA Dly = 34
828 12:12:08.741185 CS Dly: 6 (0~37)
829 12:12:08.741605
830 12:12:08.744174 ----->DramcWriteLeveling(PI) begin...
831 12:12:08.744613 ==
832 12:12:08.747434 Dram Type= 6, Freq= 0, CH_0, rank 0
833 12:12:08.750562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 12:12:08.754122 ==
835 12:12:08.754611 Write leveling (Byte 0): 34 => 34
836 12:12:08.757275 Write leveling (Byte 1): 30 => 30
837 12:12:08.761016 DramcWriteLeveling(PI) end<-----
838 12:12:08.761446
839 12:12:08.761850 ==
840 12:12:08.763993 Dram Type= 6, Freq= 0, CH_0, rank 0
841 12:12:08.770706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 12:12:08.771137 ==
843 12:12:08.771483 [Gating] SW mode calibration
844 12:12:08.780850 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 12:12:08.784578 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 12:12:08.788149 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 12:12:08.792205 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 12:12:08.799644 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
849 12:12:08.802740 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 12:12:08.806198 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 12:12:08.810025 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 12:12:08.813606 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 12:12:08.820154 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 12:12:08.823479 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 12:12:08.826740 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 12:12:08.833631 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 12:12:08.836886 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:12:08.840307 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:12:08.846942 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:12:08.850182 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:12:08.853578 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:12:08.860356 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:12:08.863316 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:12:08.866897 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
865 12:12:08.873835 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
866 12:12:08.876941 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 12:12:08.880252 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 12:12:08.886906 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 12:12:08.890427 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:12:08.893722 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 12:12:08.900200 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 12:12:08.903412 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
873 12:12:08.907080 0 9 12 | B1->B0 | 2b2b 3232 | 1 0 | (0 0) (0 0)
874 12:12:08.910557 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 12:12:08.917040 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 12:12:08.920599 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 12:12:08.923840 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 12:12:08.930159 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 12:12:08.933670 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 12:12:08.937054 0 10 8 | B1->B0 | 3333 3131 | 1 1 | (1 1) (1 0)
881 12:12:08.943746 0 10 12 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
882 12:12:08.946804 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 12:12:08.950088 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 12:12:08.956996 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 12:12:08.960054 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 12:12:08.963339 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 12:12:08.970077 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 12:12:08.973584 0 11 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
889 12:12:08.977130 0 11 12 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
890 12:12:08.983791 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 12:12:08.987135 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 12:12:08.990620 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 12:12:08.996725 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 12:12:09.000225 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 12:12:09.003493 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 12:12:09.010162 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
897 12:12:09.013338 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
898 12:12:09.016638 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 12:12:09.020230 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 12:12:09.026440 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 12:12:09.030135 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 12:12:09.036489 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 12:12:09.039722 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 12:12:09.043153 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:12:09.046380 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:12:09.053011 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:12:09.056692 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:12:09.060045 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:12:09.066727 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:12:09.069780 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:12:09.073212 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:12:09.079633 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
913 12:12:09.083210 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
914 12:12:09.086490 Total UI for P1: 0, mck2ui 16
915 12:12:09.089694 best dqsien dly found for B0: ( 0, 14, 8)
916 12:12:09.093337 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
917 12:12:09.096433 Total UI for P1: 0, mck2ui 16
918 12:12:09.100079 best dqsien dly found for B1: ( 0, 14, 12)
919 12:12:09.102979 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
920 12:12:09.106353 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
921 12:12:09.106793
922 12:12:09.109820 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
923 12:12:09.116506 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
924 12:12:09.116958 [Gating] SW calibration Done
925 12:12:09.120133 ==
926 12:12:09.120572 Dram Type= 6, Freq= 0, CH_0, rank 0
927 12:12:09.126694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 12:12:09.127137 ==
929 12:12:09.127488 RX Vref Scan: 0
930 12:12:09.127816
931 12:12:09.130112 RX Vref 0 -> 0, step: 1
932 12:12:09.130548
933 12:12:09.133248 RX Delay -130 -> 252, step: 16
934 12:12:09.136871 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
935 12:12:09.140302 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
936 12:12:09.143304 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
937 12:12:09.150142 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
938 12:12:09.153646 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
939 12:12:09.156653 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
940 12:12:09.159914 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
941 12:12:09.163366 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
942 12:12:09.170059 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
943 12:12:09.173343 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
944 12:12:09.176769 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
945 12:12:09.180191 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
946 12:12:09.183192 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
947 12:12:09.190237 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
948 12:12:09.193847 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
949 12:12:09.197389 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
950 12:12:09.197878 ==
951 12:12:09.200741 Dram Type= 6, Freq= 0, CH_0, rank 0
952 12:12:09.204165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
953 12:12:09.204646 ==
954 12:12:09.207492 DQS Delay:
955 12:12:09.207926 DQS0 = 0, DQS1 = 0
956 12:12:09.208271 DQM Delay:
957 12:12:09.210584 DQM0 = 81, DQM1 = 69
958 12:12:09.211019 DQ Delay:
959 12:12:09.213968 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
960 12:12:09.217283 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
961 12:12:09.220565 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
962 12:12:09.224192 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
963 12:12:09.224626
964 12:12:09.224973
965 12:12:09.225294 ==
966 12:12:09.227252 Dram Type= 6, Freq= 0, CH_0, rank 0
967 12:12:09.230785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 12:12:09.233925 ==
969 12:12:09.234359
970 12:12:09.234710
971 12:12:09.235033 TX Vref Scan disable
972 12:12:09.237299 == TX Byte 0 ==
973 12:12:09.240807 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
974 12:12:09.244114 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
975 12:12:09.247313 == TX Byte 1 ==
976 12:12:09.250546 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
977 12:12:09.253993 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
978 12:12:09.257566 ==
979 12:12:09.258002 Dram Type= 6, Freq= 0, CH_0, rank 0
980 12:12:09.264109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 12:12:09.264546 ==
982 12:12:09.276639 TX Vref=22, minBit 14, minWin=26, winSum=433
983 12:12:09.280023 TX Vref=24, minBit 4, minWin=27, winSum=439
984 12:12:09.283533 TX Vref=26, minBit 4, minWin=27, winSum=441
985 12:12:09.286643 TX Vref=28, minBit 5, minWin=27, winSum=444
986 12:12:09.290099 TX Vref=30, minBit 10, minWin=26, winSum=441
987 12:12:09.297032 TX Vref=32, minBit 9, minWin=26, winSum=438
988 12:12:09.300220 [TxChooseVref] Worse bit 5, Min win 27, Win sum 444, Final Vref 28
989 12:12:09.300667
990 12:12:09.303522 Final TX Range 1 Vref 28
991 12:12:09.304103
992 12:12:09.304594 ==
993 12:12:09.306749 Dram Type= 6, Freq= 0, CH_0, rank 0
994 12:12:09.310144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
995 12:12:09.310581 ==
996 12:12:09.310930
997 12:12:09.313248
998 12:12:09.313729 TX Vref Scan disable
999 12:12:09.316801 == TX Byte 0 ==
1000 12:12:09.320204 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1001 12:12:09.323353 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1002 12:12:09.326743 == TX Byte 1 ==
1003 12:12:09.330176 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1004 12:12:09.333792 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1005 12:12:09.336854
1006 12:12:09.337284 [DATLAT]
1007 12:12:09.337672 Freq=800, CH0 RK0
1008 12:12:09.338008
1009 12:12:09.340110 DATLAT Default: 0xa
1010 12:12:09.340542 0, 0xFFFF, sum = 0
1011 12:12:09.343500 1, 0xFFFF, sum = 0
1012 12:12:09.343998 2, 0xFFFF, sum = 0
1013 12:12:09.347033 3, 0xFFFF, sum = 0
1014 12:12:09.347470 4, 0xFFFF, sum = 0
1015 12:12:09.350412 5, 0xFFFF, sum = 0
1016 12:12:09.350851 6, 0xFFFF, sum = 0
1017 12:12:09.353470 7, 0xFFFF, sum = 0
1018 12:12:09.357060 8, 0xFFFF, sum = 0
1019 12:12:09.357541 9, 0x0, sum = 1
1020 12:12:09.357911 10, 0x0, sum = 2
1021 12:12:09.360282 11, 0x0, sum = 3
1022 12:12:09.360720 12, 0x0, sum = 4
1023 12:12:09.363521 best_step = 10
1024 12:12:09.363951
1025 12:12:09.364323 ==
1026 12:12:09.366893 Dram Type= 6, Freq= 0, CH_0, rank 0
1027 12:12:09.370009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1028 12:12:09.370439 ==
1029 12:12:09.373854 RX Vref Scan: 1
1030 12:12:09.374280
1031 12:12:09.374620 Set Vref Range= 32 -> 127
1032 12:12:09.374937
1033 12:12:09.376929 RX Vref 32 -> 127, step: 1
1034 12:12:09.377358
1035 12:12:09.380405 RX Delay -111 -> 252, step: 8
1036 12:12:09.380829
1037 12:12:09.383348 Set Vref, RX VrefLevel [Byte0]: 32
1038 12:12:09.386997 [Byte1]: 32
1039 12:12:09.387422
1040 12:12:09.390054 Set Vref, RX VrefLevel [Byte0]: 33
1041 12:12:09.393465 [Byte1]: 33
1042 12:12:09.396960
1043 12:12:09.397382 Set Vref, RX VrefLevel [Byte0]: 34
1044 12:12:09.400442 [Byte1]: 34
1045 12:12:09.404827
1046 12:12:09.405251 Set Vref, RX VrefLevel [Byte0]: 35
1047 12:12:09.408196 [Byte1]: 35
1048 12:12:09.412814
1049 12:12:09.413238 Set Vref, RX VrefLevel [Byte0]: 36
1050 12:12:09.415903 [Byte1]: 36
1051 12:12:09.420106
1052 12:12:09.420526 Set Vref, RX VrefLevel [Byte0]: 37
1053 12:12:09.423572 [Byte1]: 37
1054 12:12:09.427861
1055 12:12:09.428284 Set Vref, RX VrefLevel [Byte0]: 38
1056 12:12:09.431097 [Byte1]: 38
1057 12:12:09.435482
1058 12:12:09.435903 Set Vref, RX VrefLevel [Byte0]: 39
1059 12:12:09.438688 [Byte1]: 39
1060 12:12:09.443430
1061 12:12:09.443862 Set Vref, RX VrefLevel [Byte0]: 40
1062 12:12:09.446395 [Byte1]: 40
1063 12:12:09.451323
1064 12:12:09.451748 Set Vref, RX VrefLevel [Byte0]: 41
1065 12:12:09.454053 [Byte1]: 41
1066 12:12:09.458710
1067 12:12:09.459133 Set Vref, RX VrefLevel [Byte0]: 42
1068 12:12:09.461900 [Byte1]: 42
1069 12:12:09.466270
1070 12:12:09.466696 Set Vref, RX VrefLevel [Byte0]: 43
1071 12:12:09.469782 [Byte1]: 43
1072 12:12:09.474095
1073 12:12:09.474518 Set Vref, RX VrefLevel [Byte0]: 44
1074 12:12:09.477654 [Byte1]: 44
1075 12:12:09.481540
1076 12:12:09.481967 Set Vref, RX VrefLevel [Byte0]: 45
1077 12:12:09.484659 [Byte1]: 45
1078 12:12:09.488840
1079 12:12:09.489265 Set Vref, RX VrefLevel [Byte0]: 46
1080 12:12:09.492509 [Byte1]: 46
1081 12:12:09.496488
1082 12:12:09.496909 Set Vref, RX VrefLevel [Byte0]: 47
1083 12:12:09.499903 [Byte1]: 47
1084 12:12:09.504118
1085 12:12:09.504542 Set Vref, RX VrefLevel [Byte0]: 48
1086 12:12:09.507666 [Byte1]: 48
1087 12:12:09.512117
1088 12:12:09.512536 Set Vref, RX VrefLevel [Byte0]: 49
1089 12:12:09.515158 [Byte1]: 49
1090 12:12:09.519654
1091 12:12:09.520077 Set Vref, RX VrefLevel [Byte0]: 50
1092 12:12:09.522802 [Byte1]: 50
1093 12:12:09.527147
1094 12:12:09.527571 Set Vref, RX VrefLevel [Byte0]: 51
1095 12:12:09.530730 [Byte1]: 51
1096 12:12:09.534932
1097 12:12:09.535354 Set Vref, RX VrefLevel [Byte0]: 52
1098 12:12:09.538100 [Byte1]: 52
1099 12:12:09.542656
1100 12:12:09.543078 Set Vref, RX VrefLevel [Byte0]: 53
1101 12:12:09.545638 [Byte1]: 53
1102 12:12:09.550110
1103 12:12:09.550535 Set Vref, RX VrefLevel [Byte0]: 54
1104 12:12:09.553503 [Byte1]: 54
1105 12:12:09.557623
1106 12:12:09.558047 Set Vref, RX VrefLevel [Byte0]: 55
1107 12:12:09.561233 [Byte1]: 55
1108 12:12:09.565553
1109 12:12:09.566063 Set Vref, RX VrefLevel [Byte0]: 56
1110 12:12:09.568618 [Byte1]: 56
1111 12:12:09.573187
1112 12:12:09.573684 Set Vref, RX VrefLevel [Byte0]: 57
1113 12:12:09.576392 [Byte1]: 57
1114 12:12:09.580634
1115 12:12:09.581057 Set Vref, RX VrefLevel [Byte0]: 58
1116 12:12:09.584227 [Byte1]: 58
1117 12:12:09.588217
1118 12:12:09.588642 Set Vref, RX VrefLevel [Byte0]: 59
1119 12:12:09.591697 [Byte1]: 59
1120 12:12:09.596158
1121 12:12:09.596590 Set Vref, RX VrefLevel [Byte0]: 60
1122 12:12:09.599227 [Byte1]: 60
1123 12:12:09.603736
1124 12:12:09.604221 Set Vref, RX VrefLevel [Byte0]: 61
1125 12:12:09.607034 [Byte1]: 61
1126 12:12:09.611443
1127 12:12:09.611864 Set Vref, RX VrefLevel [Byte0]: 62
1128 12:12:09.614868 [Byte1]: 62
1129 12:12:09.619175
1130 12:12:09.619596 Set Vref, RX VrefLevel [Byte0]: 63
1131 12:12:09.622510 [Byte1]: 63
1132 12:12:09.626576
1133 12:12:09.626998 Set Vref, RX VrefLevel [Byte0]: 64
1134 12:12:09.629882 [Byte1]: 64
1135 12:12:09.634645
1136 12:12:09.635103 Set Vref, RX VrefLevel [Byte0]: 65
1137 12:12:09.637764 [Byte1]: 65
1138 12:12:09.642165
1139 12:12:09.642590 Set Vref, RX VrefLevel [Byte0]: 66
1140 12:12:09.645190 [Byte1]: 66
1141 12:12:09.649753
1142 12:12:09.650173 Set Vref, RX VrefLevel [Byte0]: 67
1143 12:12:09.652875 [Byte1]: 67
1144 12:12:09.657241
1145 12:12:09.657712 Set Vref, RX VrefLevel [Byte0]: 68
1146 12:12:09.663601 [Byte1]: 68
1147 12:12:09.664042
1148 12:12:09.666993 Set Vref, RX VrefLevel [Byte0]: 69
1149 12:12:09.670462 [Byte1]: 69
1150 12:12:09.670888
1151 12:12:09.673569 Set Vref, RX VrefLevel [Byte0]: 70
1152 12:12:09.676850 [Byte1]: 70
1153 12:12:09.677311
1154 12:12:09.680403 Set Vref, RX VrefLevel [Byte0]: 71
1155 12:12:09.683512 [Byte1]: 71
1156 12:12:09.687847
1157 12:12:09.688272 Set Vref, RX VrefLevel [Byte0]: 72
1158 12:12:09.690971 [Byte1]: 72
1159 12:12:09.695362
1160 12:12:09.695784 Set Vref, RX VrefLevel [Byte0]: 73
1161 12:12:09.698876 [Byte1]: 73
1162 12:12:09.703146
1163 12:12:09.703567 Set Vref, RX VrefLevel [Byte0]: 74
1164 12:12:09.706485 [Byte1]: 74
1165 12:12:09.710732
1166 12:12:09.711305 Set Vref, RX VrefLevel [Byte0]: 75
1167 12:12:09.713815 [Byte1]: 75
1168 12:12:09.718397
1169 12:12:09.718850 Set Vref, RX VrefLevel [Byte0]: 76
1170 12:12:09.721737 [Byte1]: 76
1171 12:12:09.726014
1172 12:12:09.726440 Set Vref, RX VrefLevel [Byte0]: 77
1173 12:12:09.729276 [Byte1]: 77
1174 12:12:09.733776
1175 12:12:09.734198 Set Vref, RX VrefLevel [Byte0]: 78
1176 12:12:09.736897 [Byte1]: 78
1177 12:12:09.741165
1178 12:12:09.741650 Set Vref, RX VrefLevel [Byte0]: 79
1179 12:12:09.744653 [Byte1]: 79
1180 12:12:09.748962
1181 12:12:09.749386 Set Vref, RX VrefLevel [Byte0]: 80
1182 12:12:09.752448 [Byte1]: 80
1183 12:12:09.756696
1184 12:12:09.757116 Final RX Vref Byte 0 = 58 to rank0
1185 12:12:09.759788 Final RX Vref Byte 1 = 60 to rank0
1186 12:12:09.763292 Final RX Vref Byte 0 = 58 to rank1
1187 12:12:09.766698 Final RX Vref Byte 1 = 60 to rank1==
1188 12:12:09.769810 Dram Type= 6, Freq= 0, CH_0, rank 0
1189 12:12:09.776803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1190 12:12:09.777279 ==
1191 12:12:09.777676 DQS Delay:
1192 12:12:09.778006 DQS0 = 0, DQS1 = 0
1193 12:12:09.779846 DQM Delay:
1194 12:12:09.780268 DQM0 = 82, DQM1 = 67
1195 12:12:09.783157 DQ Delay:
1196 12:12:09.786662 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1197 12:12:09.787090 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1198 12:12:09.790041 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1199 12:12:09.796276 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1200 12:12:09.796702
1201 12:12:09.797040
1202 12:12:09.802913 [DQSOSCAuto] RK0, (LSB)MR18= 0x2423, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1203 12:12:09.806310 CH0 RK0: MR19=606, MR18=2423
1204 12:12:09.813529 CH0_RK0: MR19=0x606, MR18=0x2423, DQSOSC=400, MR23=63, INC=92, DEC=61
1205 12:12:09.814013
1206 12:12:09.816430 ----->DramcWriteLeveling(PI) begin...
1207 12:12:09.816860 ==
1208 12:12:09.819850 Dram Type= 6, Freq= 0, CH_0, rank 1
1209 12:12:09.823218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1210 12:12:09.823649 ==
1211 12:12:09.826479 Write leveling (Byte 0): 33 => 33
1212 12:12:09.829648 Write leveling (Byte 1): 29 => 29
1213 12:12:09.833270 DramcWriteLeveling(PI) end<-----
1214 12:12:09.833742
1215 12:12:09.834217 ==
1216 12:12:09.836650 Dram Type= 6, Freq= 0, CH_0, rank 1
1217 12:12:09.839622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1218 12:12:09.840053 ==
1219 12:12:09.842929 [Gating] SW mode calibration
1220 12:12:09.849732 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1221 12:12:09.856401 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1222 12:12:09.859849 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1223 12:12:09.863054 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1224 12:12:09.907052 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1225 12:12:09.907481 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 12:12:09.908146 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 12:12:09.908497 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:12:09.908816 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:12:09.909119 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:12:09.909417 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 12:12:09.909749 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:12:09.910045 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 12:12:09.910334 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 12:12:09.951121 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 12:12:09.951886 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 12:12:09.952253 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 12:12:09.952582 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 12:12:09.952888 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 12:12:09.953192 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1240 12:12:09.953522 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1241 12:12:09.953891 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 12:12:09.954196 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 12:12:09.954486 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 12:12:09.961439 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 12:12:09.964636 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 12:12:09.968094 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 12:12:09.971635 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 12:12:09.974751 0 9 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
1249 12:12:09.978188 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1250 12:12:09.981598 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 12:12:09.988409 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 12:12:09.991397 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 12:12:09.994877 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 12:12:10.001353 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 12:12:10.004847 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
1256 12:12:10.008333 0 10 8 | B1->B0 | 2f2f 2626 | 1 0 | (0 1) (0 0)
1257 12:12:10.014975 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 12:12:10.018037 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 12:12:10.021498 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 12:12:10.025197 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 12:12:10.032741 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 12:12:10.036661 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 12:12:10.039731 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1264 12:12:10.042967 0 11 8 | B1->B0 | 2e2e 3e3e | 1 0 | (0 0) (0 0)
1265 12:12:10.050166 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1266 12:12:10.053652 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 12:12:10.056732 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 12:12:10.063394 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 12:12:10.066878 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 12:12:10.070093 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 12:12:10.073810 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1272 12:12:10.080191 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1273 12:12:10.083485 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 12:12:10.086982 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 12:12:10.093441 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 12:12:10.096657 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 12:12:10.099898 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 12:12:10.106900 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 12:12:10.110030 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 12:12:10.113466 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 12:12:10.119838 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 12:12:10.123389 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 12:12:10.126572 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 12:12:10.133269 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 12:12:10.136358 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 12:12:10.139847 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 12:12:10.145954 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1288 12:12:10.149359 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1289 12:12:10.152776 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1290 12:12:10.155818 Total UI for P1: 0, mck2ui 16
1291 12:12:10.159043 best dqsien dly found for B0: ( 0, 14, 6)
1292 12:12:10.162623 Total UI for P1: 0, mck2ui 16
1293 12:12:10.165901 best dqsien dly found for B1: ( 0, 14, 10)
1294 12:12:10.169267 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1295 12:12:10.172683 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1296 12:12:10.172766
1297 12:12:10.179505 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1298 12:12:10.182459 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1299 12:12:10.182543 [Gating] SW calibration Done
1300 12:12:10.185881 ==
1301 12:12:10.189241 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 12:12:10.192372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 12:12:10.192456 ==
1304 12:12:10.192522 RX Vref Scan: 0
1305 12:12:10.192584
1306 12:12:10.195825 RX Vref 0 -> 0, step: 1
1307 12:12:10.195909
1308 12:12:10.199450 RX Delay -130 -> 252, step: 16
1309 12:12:10.202566 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1310 12:12:10.205642 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1311 12:12:10.212216 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1312 12:12:10.215743 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1313 12:12:10.218952 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1314 12:12:10.222593 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1315 12:12:10.225693 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1316 12:12:10.232464 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1317 12:12:10.235620 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1318 12:12:10.239225 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1319 12:12:10.242462 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1320 12:12:10.245845 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1321 12:12:10.252542 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1322 12:12:10.255724 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1323 12:12:10.258855 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1324 12:12:10.262391 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1325 12:12:10.262474 ==
1326 12:12:10.265592 Dram Type= 6, Freq= 0, CH_0, rank 1
1327 12:12:10.269015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1328 12:12:10.272557 ==
1329 12:12:10.272641 DQS Delay:
1330 12:12:10.272707 DQS0 = 0, DQS1 = 0
1331 12:12:10.275842 DQM Delay:
1332 12:12:10.275925 DQM0 = 80, DQM1 = 71
1333 12:12:10.278999 DQ Delay:
1334 12:12:10.282426 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =69
1335 12:12:10.282509 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
1336 12:12:10.285682 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1337 12:12:10.288793 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
1338 12:12:10.292186
1339 12:12:10.292269
1340 12:12:10.292334 ==
1341 12:12:10.295735 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 12:12:10.298846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 12:12:10.298930 ==
1344 12:12:10.298996
1345 12:12:10.299058
1346 12:12:10.302042 TX Vref Scan disable
1347 12:12:10.302125 == TX Byte 0 ==
1348 12:12:10.308794 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1349 12:12:10.312238 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1350 12:12:10.312321 == TX Byte 1 ==
1351 12:12:10.319116 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1352 12:12:10.322252 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1353 12:12:10.322336 ==
1354 12:12:10.325857 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 12:12:10.328848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 12:12:10.328932 ==
1357 12:12:10.343084 TX Vref=22, minBit 0, minWin=27, winSum=435
1358 12:12:10.346505 TX Vref=24, minBit 1, minWin=27, winSum=442
1359 12:12:10.349437 TX Vref=26, minBit 1, minWin=27, winSum=443
1360 12:12:10.353027 TX Vref=28, minBit 1, minWin=27, winSum=443
1361 12:12:10.356546 TX Vref=30, minBit 1, minWin=27, winSum=443
1362 12:12:10.359731 TX Vref=32, minBit 1, minWin=27, winSum=441
1363 12:12:10.366736 [TxChooseVref] Worse bit 1, Min win 27, Win sum 443, Final Vref 26
1364 12:12:10.366974
1365 12:12:10.370028 Final TX Range 1 Vref 26
1366 12:12:10.370229
1367 12:12:10.370352 ==
1368 12:12:10.373183 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 12:12:10.376874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 12:12:10.377101 ==
1371 12:12:10.377266
1372 12:12:10.377416
1373 12:12:10.379718 TX Vref Scan disable
1374 12:12:10.383315 == TX Byte 0 ==
1375 12:12:10.386572 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1376 12:12:10.389973 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1377 12:12:10.393553 == TX Byte 1 ==
1378 12:12:10.396679 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1379 12:12:10.400120 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1380 12:12:10.400548
1381 12:12:10.403543 [DATLAT]
1382 12:12:10.403971 Freq=800, CH0 RK1
1383 12:12:10.404314
1384 12:12:10.406706 DATLAT Default: 0xa
1385 12:12:10.407182 0, 0xFFFF, sum = 0
1386 12:12:10.409927 1, 0xFFFF, sum = 0
1387 12:12:10.410361 2, 0xFFFF, sum = 0
1388 12:12:10.413390 3, 0xFFFF, sum = 0
1389 12:12:10.413854 4, 0xFFFF, sum = 0
1390 12:12:10.416826 5, 0xFFFF, sum = 0
1391 12:12:10.417261 6, 0xFFFF, sum = 0
1392 12:12:10.419726 7, 0xFFFF, sum = 0
1393 12:12:10.420159 8, 0xFFFF, sum = 0
1394 12:12:10.423384 9, 0x0, sum = 1
1395 12:12:10.423815 10, 0x0, sum = 2
1396 12:12:10.426813 11, 0x0, sum = 3
1397 12:12:10.427245 12, 0x0, sum = 4
1398 12:12:10.429852 best_step = 10
1399 12:12:10.430275
1400 12:12:10.430610 ==
1401 12:12:10.433308 Dram Type= 6, Freq= 0, CH_0, rank 1
1402 12:12:10.436938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1403 12:12:10.437375 ==
1404 12:12:10.440310 RX Vref Scan: 0
1405 12:12:10.440790
1406 12:12:10.441183 RX Vref 0 -> 0, step: 1
1407 12:12:10.441547
1408 12:12:10.443445 RX Delay -111 -> 252, step: 8
1409 12:12:10.450039 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1410 12:12:10.453462 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1411 12:12:10.456555 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1412 12:12:10.459770 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1413 12:12:10.466585 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1414 12:12:10.469986 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1415 12:12:10.473333 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1416 12:12:10.476529 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1417 12:12:10.479741 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1418 12:12:10.483179 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1419 12:12:10.489545 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1420 12:12:10.493057 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1421 12:12:10.496487 iDelay=209, Bit 12, Center 76 (-47 ~ 200) 248
1422 12:12:10.499679 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1423 12:12:10.506330 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1424 12:12:10.509791 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1425 12:12:10.510219 ==
1426 12:12:10.513181 Dram Type= 6, Freq= 0, CH_0, rank 1
1427 12:12:10.516476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1428 12:12:10.516905 ==
1429 12:12:10.519553 DQS Delay:
1430 12:12:10.519974 DQS0 = 0, DQS1 = 0
1431 12:12:10.520312 DQM Delay:
1432 12:12:10.522963 DQM0 = 78, DQM1 = 71
1433 12:12:10.523451 DQ Delay:
1434 12:12:10.526217 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1435 12:12:10.529558 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =92
1436 12:12:10.532705 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1437 12:12:10.536184 DQ12 =76, DQ13 =76, DQ14 =80, DQ15 =80
1438 12:12:10.536612
1439 12:12:10.536948
1440 12:12:10.546150 [DQSOSCAuto] RK1, (LSB)MR18= 0x441f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
1441 12:12:10.546580 CH0 RK1: MR19=606, MR18=441F
1442 12:12:10.553053 CH0_RK1: MR19=0x606, MR18=0x441F, DQSOSC=392, MR23=63, INC=96, DEC=64
1443 12:12:10.556126 [RxdqsGatingPostProcess] freq 800
1444 12:12:10.563218 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1445 12:12:10.566064 Pre-setting of DQS Precalculation
1446 12:12:10.569621 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1447 12:12:10.570051 ==
1448 12:12:10.572690 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 12:12:10.579867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 12:12:10.580431 ==
1451 12:12:10.582842 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1452 12:12:10.589359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1453 12:12:10.598413 [CA 0] Center 36 (6~67) winsize 62
1454 12:12:10.601594 [CA 1] Center 36 (6~67) winsize 62
1455 12:12:10.605212 [CA 2] Center 34 (5~64) winsize 60
1456 12:12:10.608815 [CA 3] Center 34 (4~64) winsize 61
1457 12:12:10.611775 [CA 4] Center 34 (4~65) winsize 62
1458 12:12:10.615171 [CA 5] Center 34 (4~64) winsize 61
1459 12:12:10.615599
1460 12:12:10.618216 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1461 12:12:10.618646
1462 12:12:10.621563 [CATrainingPosCal] consider 1 rank data
1463 12:12:10.625231 u2DelayCellTimex100 = 270/100 ps
1464 12:12:10.628215 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1465 12:12:10.631739 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1466 12:12:10.638322 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1467 12:12:10.641813 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1468 12:12:10.645097 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1469 12:12:10.648231 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1470 12:12:10.648655
1471 12:12:10.651665 CA PerBit enable=1, Macro0, CA PI delay=34
1472 12:12:10.652095
1473 12:12:10.654832 [CBTSetCACLKResult] CA Dly = 34
1474 12:12:10.655261 CS Dly: 5 (0~36)
1475 12:12:10.658006 ==
1476 12:12:10.658435 Dram Type= 6, Freq= 0, CH_1, rank 1
1477 12:12:10.664994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1478 12:12:10.665426 ==
1479 12:12:10.668435 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1480 12:12:10.674844 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1481 12:12:10.684823 [CA 0] Center 36 (6~67) winsize 62
1482 12:12:10.688408 [CA 1] Center 36 (6~67) winsize 62
1483 12:12:10.692063 [CA 2] Center 35 (5~65) winsize 61
1484 12:12:10.696082 [CA 3] Center 34 (4~64) winsize 61
1485 12:12:10.699712 [CA 4] Center 34 (4~65) winsize 62
1486 12:12:10.703096 [CA 5] Center 33 (3~64) winsize 62
1487 12:12:10.703526
1488 12:12:10.707233 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1489 12:12:10.707668
1490 12:12:10.710796 [CATrainingPosCal] consider 2 rank data
1491 12:12:10.711231 u2DelayCellTimex100 = 270/100 ps
1492 12:12:10.714312 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1493 12:12:10.717898 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1494 12:12:10.724209 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1495 12:12:10.727796 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1496 12:12:10.730926 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1497 12:12:10.734461 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1498 12:12:10.734888
1499 12:12:10.737646 CA PerBit enable=1, Macro0, CA PI delay=34
1500 12:12:10.738074
1501 12:12:10.740978 [CBTSetCACLKResult] CA Dly = 34
1502 12:12:10.741405 CS Dly: 5 (0~37)
1503 12:12:10.741773
1504 12:12:10.744562 ----->DramcWriteLeveling(PI) begin...
1505 12:12:10.747508 ==
1506 12:12:10.750992 Dram Type= 6, Freq= 0, CH_1, rank 0
1507 12:12:10.754422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1508 12:12:10.754853 ==
1509 12:12:10.757532 Write leveling (Byte 0): 25 => 25
1510 12:12:10.760844 Write leveling (Byte 1): 29 => 29
1511 12:12:10.764244 DramcWriteLeveling(PI) end<-----
1512 12:12:10.764677
1513 12:12:10.765018 ==
1514 12:12:10.767233 Dram Type= 6, Freq= 0, CH_1, rank 0
1515 12:12:10.770695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1516 12:12:10.771129 ==
1517 12:12:10.774108 [Gating] SW mode calibration
1518 12:12:10.780633 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1519 12:12:10.787161 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1520 12:12:10.790643 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1521 12:12:10.793592 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1522 12:12:10.800429 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1523 12:12:10.803951 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 12:12:10.807533 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 12:12:10.810623 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 12:12:10.817209 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 12:12:10.820647 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 12:12:10.824159 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 12:12:10.830744 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 12:12:10.833890 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 12:12:10.837351 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 12:12:10.844120 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 12:12:10.847295 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 12:12:10.850730 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 12:12:10.857190 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 12:12:10.860689 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 12:12:10.863831 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 12:12:10.870525 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1539 12:12:10.873836 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 12:12:10.877564 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 12:12:10.884070 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 12:12:10.887411 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 12:12:10.890471 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 12:12:10.897170 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 12:12:10.900561 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 12:12:10.903887 0 9 8 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
1547 12:12:10.910486 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 12:12:10.913963 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 12:12:10.917152 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 12:12:10.920708 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 12:12:10.927075 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 12:12:10.930472 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 12:12:10.933953 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1554 12:12:10.940340 0 10 8 | B1->B0 | 2d2d 2727 | 1 0 | (1 0) (1 0)
1555 12:12:10.943812 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 12:12:10.946923 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 12:12:10.953656 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 12:12:10.956934 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 12:12:10.960411 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 12:12:10.966912 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 12:12:10.970353 0 11 4 | B1->B0 | 2525 2727 | 0 0 | (0 0) (0 0)
1562 12:12:10.973875 0 11 8 | B1->B0 | 3b3b 3e3e | 0 0 | (0 0) (0 0)
1563 12:12:10.980157 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 12:12:10.983765 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 12:12:10.986981 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 12:12:10.993581 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 12:12:10.997089 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 12:12:11.000485 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 12:12:11.007062 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 12:12:11.010513 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1571 12:12:11.013888 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1572 12:12:11.020363 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 12:12:11.023510 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 12:12:11.027051 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 12:12:11.030205 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 12:12:11.037210 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 12:12:11.040186 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 12:12:11.043877 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 12:12:11.050353 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 12:12:11.053906 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 12:12:11.057022 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 12:12:11.063731 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 12:12:11.067275 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 12:12:11.070257 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 12:12:11.077137 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 12:12:11.080256 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1587 12:12:11.083838 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1588 12:12:11.087304 Total UI for P1: 0, mck2ui 16
1589 12:12:11.090264 best dqsien dly found for B0: ( 0, 14, 8)
1590 12:12:11.096948 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1591 12:12:11.097381 Total UI for P1: 0, mck2ui 16
1592 12:12:11.100421 best dqsien dly found for B1: ( 0, 14, 10)
1593 12:12:11.103817 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1594 12:12:11.110669 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1595 12:12:11.111100
1596 12:12:11.113911 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1597 12:12:11.117082 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1598 12:12:11.120453 [Gating] SW calibration Done
1599 12:12:11.120883 ==
1600 12:12:11.123965 Dram Type= 6, Freq= 0, CH_1, rank 0
1601 12:12:11.127080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1602 12:12:11.127509 ==
1603 12:12:11.127856 RX Vref Scan: 0
1604 12:12:11.130592
1605 12:12:11.131016 RX Vref 0 -> 0, step: 1
1606 12:12:11.131360
1607 12:12:11.133786 RX Delay -130 -> 252, step: 16
1608 12:12:11.137304 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1609 12:12:11.140318 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1610 12:12:11.147015 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1611 12:12:11.150325 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1612 12:12:11.153570 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1613 12:12:11.157323 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1614 12:12:11.160359 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1615 12:12:11.167102 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1616 12:12:11.170348 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1617 12:12:11.173652 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1618 12:12:11.177200 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1619 12:12:11.180295 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1620 12:12:11.186662 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1621 12:12:11.190195 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1622 12:12:11.193290 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1623 12:12:11.196630 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1624 12:12:11.197056 ==
1625 12:12:11.200310 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 12:12:11.206731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 12:12:11.207326 ==
1628 12:12:11.207700 DQS Delay:
1629 12:12:11.210419 DQS0 = 0, DQS1 = 0
1630 12:12:11.210843 DQM Delay:
1631 12:12:11.211178 DQM0 = 81, DQM1 = 71
1632 12:12:11.213912 DQ Delay:
1633 12:12:11.217069 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1634 12:12:11.220232 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1635 12:12:11.223873 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1636 12:12:11.227214 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1637 12:12:11.227638
1638 12:12:11.227976
1639 12:12:11.228292 ==
1640 12:12:11.230505 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 12:12:11.233808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 12:12:11.234238 ==
1643 12:12:11.234581
1644 12:12:11.234898
1645 12:12:11.237050 TX Vref Scan disable
1646 12:12:11.237503 == TX Byte 0 ==
1647 12:12:11.243565 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1648 12:12:11.247096 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1649 12:12:11.247523 == TX Byte 1 ==
1650 12:12:11.253632 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1651 12:12:11.257187 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1652 12:12:11.257661 ==
1653 12:12:11.260340 Dram Type= 6, Freq= 0, CH_1, rank 0
1654 12:12:11.263740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1655 12:12:11.264304 ==
1656 12:12:11.277991 TX Vref=22, minBit 5, minWin=27, winSum=445
1657 12:12:11.281242 TX Vref=24, minBit 5, minWin=27, winSum=447
1658 12:12:11.284395 TX Vref=26, minBit 5, minWin=27, winSum=446
1659 12:12:11.288049 TX Vref=28, minBit 5, minWin=28, winSum=456
1660 12:12:11.291364 TX Vref=30, minBit 9, minWin=27, winSum=453
1661 12:12:11.294551 TX Vref=32, minBit 9, minWin=27, winSum=451
1662 12:12:11.301298 [TxChooseVref] Worse bit 5, Min win 28, Win sum 456, Final Vref 28
1663 12:12:11.301862
1664 12:12:11.304835 Final TX Range 1 Vref 28
1665 12:12:11.305265
1666 12:12:11.305637 ==
1667 12:12:11.308152 Dram Type= 6, Freq= 0, CH_1, rank 0
1668 12:12:11.311197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1669 12:12:11.311630 ==
1670 12:12:11.311974
1671 12:12:11.314632
1672 12:12:11.315130 TX Vref Scan disable
1673 12:12:11.317830 == TX Byte 0 ==
1674 12:12:11.321250 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1675 12:12:11.324837 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1676 12:12:11.327810 == TX Byte 1 ==
1677 12:12:11.331476 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1678 12:12:11.334578 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1679 12:12:11.337987
1680 12:12:11.338407 [DATLAT]
1681 12:12:11.338743 Freq=800, CH1 RK0
1682 12:12:11.339061
1683 12:12:11.341376 DATLAT Default: 0xa
1684 12:12:11.341833 0, 0xFFFF, sum = 0
1685 12:12:11.344805 1, 0xFFFF, sum = 0
1686 12:12:11.345236 2, 0xFFFF, sum = 0
1687 12:12:11.348078 3, 0xFFFF, sum = 0
1688 12:12:11.348508 4, 0xFFFF, sum = 0
1689 12:12:11.351131 5, 0xFFFF, sum = 0
1690 12:12:11.351561 6, 0xFFFF, sum = 0
1691 12:12:11.354712 7, 0xFFFF, sum = 0
1692 12:12:11.357802 8, 0xFFFF, sum = 0
1693 12:12:11.358235 9, 0x0, sum = 1
1694 12:12:11.358576 10, 0x0, sum = 2
1695 12:12:11.361337 11, 0x0, sum = 3
1696 12:12:11.361823 12, 0x0, sum = 4
1697 12:12:11.364562 best_step = 10
1698 12:12:11.364987
1699 12:12:11.365419 ==
1700 12:12:11.367756 Dram Type= 6, Freq= 0, CH_1, rank 0
1701 12:12:11.370953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1702 12:12:11.371380 ==
1703 12:12:11.374495 RX Vref Scan: 1
1704 12:12:11.374919
1705 12:12:11.375264 Set Vref Range= 32 -> 127
1706 12:12:11.377831
1707 12:12:11.378258 RX Vref 32 -> 127, step: 1
1708 12:12:11.378653
1709 12:12:11.381350 RX Delay -111 -> 252, step: 8
1710 12:12:11.381845
1711 12:12:11.384709 Set Vref, RX VrefLevel [Byte0]: 32
1712 12:12:11.387825 [Byte1]: 32
1713 12:12:11.388257
1714 12:12:11.391241 Set Vref, RX VrefLevel [Byte0]: 33
1715 12:12:11.394585 [Byte1]: 33
1716 12:12:11.398385
1717 12:12:11.398815 Set Vref, RX VrefLevel [Byte0]: 34
1718 12:12:11.401771 [Byte1]: 34
1719 12:12:11.406070
1720 12:12:11.406498 Set Vref, RX VrefLevel [Byte0]: 35
1721 12:12:11.409380 [Byte1]: 35
1722 12:12:11.413636
1723 12:12:11.414061 Set Vref, RX VrefLevel [Byte0]: 36
1724 12:12:11.417076 [Byte1]: 36
1725 12:12:11.421168
1726 12:12:11.421621 Set Vref, RX VrefLevel [Byte0]: 37
1727 12:12:11.424696 [Byte1]: 37
1728 12:12:11.429082
1729 12:12:11.429532 Set Vref, RX VrefLevel [Byte0]: 38
1730 12:12:11.432368 [Byte1]: 38
1731 12:12:11.436791
1732 12:12:11.437212 Set Vref, RX VrefLevel [Byte0]: 39
1733 12:12:11.439872 [Byte1]: 39
1734 12:12:11.444183
1735 12:12:11.444604 Set Vref, RX VrefLevel [Byte0]: 40
1736 12:12:11.447387 [Byte1]: 40
1737 12:12:11.451993
1738 12:12:11.452416 Set Vref, RX VrefLevel [Byte0]: 41
1739 12:12:11.455080 [Byte1]: 41
1740 12:12:11.459431
1741 12:12:11.459854 Set Vref, RX VrefLevel [Byte0]: 42
1742 12:12:11.462686 [Byte1]: 42
1743 12:12:11.467241
1744 12:12:11.467670 Set Vref, RX VrefLevel [Byte0]: 43
1745 12:12:11.470518 [Byte1]: 43
1746 12:12:11.474872
1747 12:12:11.475314 Set Vref, RX VrefLevel [Byte0]: 44
1748 12:12:11.478012 [Byte1]: 44
1749 12:12:11.482534
1750 12:12:11.482962 Set Vref, RX VrefLevel [Byte0]: 45
1751 12:12:11.486021 [Byte1]: 45
1752 12:12:11.490017
1753 12:12:11.490446 Set Vref, RX VrefLevel [Byte0]: 46
1754 12:12:11.493435 [Byte1]: 46
1755 12:12:11.497630
1756 12:12:11.498059 Set Vref, RX VrefLevel [Byte0]: 47
1757 12:12:11.501164 [Byte1]: 47
1758 12:12:11.505366
1759 12:12:11.505839 Set Vref, RX VrefLevel [Byte0]: 48
1760 12:12:11.508716 [Byte1]: 48
1761 12:12:11.513441
1762 12:12:11.513902 Set Vref, RX VrefLevel [Byte0]: 49
1763 12:12:11.516584 [Byte1]: 49
1764 12:12:11.520696
1765 12:12:11.521118 Set Vref, RX VrefLevel [Byte0]: 50
1766 12:12:11.524055 [Byte1]: 50
1767 12:12:11.528795
1768 12:12:11.529217 Set Vref, RX VrefLevel [Byte0]: 51
1769 12:12:11.531698 [Byte1]: 51
1770 12:12:11.536129
1771 12:12:11.536552 Set Vref, RX VrefLevel [Byte0]: 52
1772 12:12:11.539469 [Byte1]: 52
1773 12:12:11.543779
1774 12:12:11.544200 Set Vref, RX VrefLevel [Byte0]: 53
1775 12:12:11.546904 [Byte1]: 53
1776 12:12:11.551251
1777 12:12:11.551673 Set Vref, RX VrefLevel [Byte0]: 54
1778 12:12:11.554639 [Byte1]: 54
1779 12:12:11.558738
1780 12:12:11.559160 Set Vref, RX VrefLevel [Byte0]: 55
1781 12:12:11.562001 [Byte1]: 55
1782 12:12:11.566450
1783 12:12:11.566872 Set Vref, RX VrefLevel [Byte0]: 56
1784 12:12:11.569869 [Byte1]: 56
1785 12:12:11.574214
1786 12:12:11.574642 Set Vref, RX VrefLevel [Byte0]: 57
1787 12:12:11.577311 [Byte1]: 57
1788 12:12:11.582053
1789 12:12:11.582482 Set Vref, RX VrefLevel [Byte0]: 58
1790 12:12:11.585171 [Byte1]: 58
1791 12:12:11.589724
1792 12:12:11.590153 Set Vref, RX VrefLevel [Byte0]: 59
1793 12:12:11.592920 [Byte1]: 59
1794 12:12:11.597416
1795 12:12:11.597874 Set Vref, RX VrefLevel [Byte0]: 60
1796 12:12:11.600622 [Byte1]: 60
1797 12:12:11.604880
1798 12:12:11.605304 Set Vref, RX VrefLevel [Byte0]: 61
1799 12:12:11.608078 [Byte1]: 61
1800 12:12:11.612256
1801 12:12:11.615812 Set Vref, RX VrefLevel [Byte0]: 62
1802 12:12:11.619231 [Byte1]: 62
1803 12:12:11.619721
1804 12:12:11.622169 Set Vref, RX VrefLevel [Byte0]: 63
1805 12:12:11.625584 [Byte1]: 63
1806 12:12:11.626116
1807 12:12:11.628801 Set Vref, RX VrefLevel [Byte0]: 64
1808 12:12:11.632343 [Byte1]: 64
1809 12:12:11.635493
1810 12:12:11.635921 Set Vref, RX VrefLevel [Byte0]: 65
1811 12:12:11.638711 [Byte1]: 65
1812 12:12:11.643241
1813 12:12:11.643675 Set Vref, RX VrefLevel [Byte0]: 66
1814 12:12:11.646138 [Byte1]: 66
1815 12:12:11.650568
1816 12:12:11.650994 Set Vref, RX VrefLevel [Byte0]: 67
1817 12:12:11.654108 [Byte1]: 67
1818 12:12:11.658397
1819 12:12:11.658818 Set Vref, RX VrefLevel [Byte0]: 68
1820 12:12:11.661577 [Byte1]: 68
1821 12:12:11.666044
1822 12:12:11.666467 Set Vref, RX VrefLevel [Byte0]: 69
1823 12:12:11.669392 [Byte1]: 69
1824 12:12:11.673736
1825 12:12:11.674164 Set Vref, RX VrefLevel [Byte0]: 70
1826 12:12:11.676682 [Byte1]: 70
1827 12:12:11.681416
1828 12:12:11.681908 Set Vref, RX VrefLevel [Byte0]: 71
1829 12:12:11.684668 [Byte1]: 71
1830 12:12:11.688937
1831 12:12:11.689360 Set Vref, RX VrefLevel [Byte0]: 72
1832 12:12:11.692441 [Byte1]: 72
1833 12:12:11.696642
1834 12:12:11.697066 Set Vref, RX VrefLevel [Byte0]: 73
1835 12:12:11.699923 [Byte1]: 73
1836 12:12:11.704365
1837 12:12:11.704786 Set Vref, RX VrefLevel [Byte0]: 74
1838 12:12:11.707613 [Byte1]: 74
1839 12:12:11.711863
1840 12:12:11.715003 Set Vref, RX VrefLevel [Byte0]: 75
1841 12:12:11.718179 [Byte1]: 75
1842 12:12:11.718603
1843 12:12:11.721565 Final RX Vref Byte 0 = 61 to rank0
1844 12:12:11.725064 Final RX Vref Byte 1 = 55 to rank0
1845 12:12:11.728394 Final RX Vref Byte 0 = 61 to rank1
1846 12:12:11.731705 Final RX Vref Byte 1 = 55 to rank1==
1847 12:12:11.735030 Dram Type= 6, Freq= 0, CH_1, rank 0
1848 12:12:11.738506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1849 12:12:11.738933 ==
1850 12:12:11.739272 DQS Delay:
1851 12:12:11.741741 DQS0 = 0, DQS1 = 0
1852 12:12:11.742164 DQM Delay:
1853 12:12:11.745087 DQM0 = 81, DQM1 = 71
1854 12:12:11.745539 DQ Delay:
1855 12:12:11.747994 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1856 12:12:11.751417 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =76
1857 12:12:11.754904 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1858 12:12:11.758380 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1859 12:12:11.758958
1860 12:12:11.759317
1861 12:12:11.764901 [DQSOSCAuto] RK0, (LSB)MR18= 0x121c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
1862 12:12:11.768290 CH1 RK0: MR19=606, MR18=121C
1863 12:12:11.774828 CH1_RK0: MR19=0x606, MR18=0x121C, DQSOSC=402, MR23=63, INC=91, DEC=60
1864 12:12:11.775256
1865 12:12:11.778317 ----->DramcWriteLeveling(PI) begin...
1866 12:12:11.778749 ==
1867 12:12:11.781363 Dram Type= 6, Freq= 0, CH_1, rank 1
1868 12:12:11.785006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1869 12:12:11.785432 ==
1870 12:12:11.788109 Write leveling (Byte 0): 25 => 25
1871 12:12:11.791657 Write leveling (Byte 1): 31 => 31
1872 12:12:11.794782 DramcWriteLeveling(PI) end<-----
1873 12:12:11.795212
1874 12:12:11.795606 ==
1875 12:12:11.798366 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 12:12:11.804652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1877 12:12:11.805081 ==
1878 12:12:11.805427 [Gating] SW mode calibration
1879 12:12:11.815037 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1880 12:12:11.818203 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1881 12:12:11.821383 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1882 12:12:11.828022 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1883 12:12:11.831533 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 12:12:11.834863 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 12:12:11.841924 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 12:12:11.844864 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 12:12:11.847995 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 12:12:11.854988 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 12:12:11.858190 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 12:12:11.861458 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 12:12:11.868473 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 12:12:11.871398 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 12:12:11.874848 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 12:12:11.881645 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 12:12:11.884863 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 12:12:11.888104 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 12:12:11.891657 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 12:12:11.898311 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1899 12:12:11.901500 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1900 12:12:11.904813 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 12:12:11.911769 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 12:12:11.914699 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 12:12:11.918100 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 12:12:11.924776 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 12:12:11.928265 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 12:12:11.931447 0 9 4 | B1->B0 | 2323 2f2f | 1 1 | (0 0) (0 0)
1907 12:12:11.938082 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1908 12:12:11.941547 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 12:12:11.945000 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 12:12:11.951472 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 12:12:11.954800 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 12:12:11.958070 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 12:12:11.964968 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 12:12:11.968398 0 10 4 | B1->B0 | 3131 2e2e | 0 1 | (0 0) (1 1)
1915 12:12:11.971585 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1916 12:12:11.978237 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 12:12:11.981428 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 12:12:11.984605 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 12:12:11.991375 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 12:12:11.994492 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 12:12:11.998127 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 12:12:12.001512 0 11 4 | B1->B0 | 2d2d 3a39 | 0 1 | (0 0) (0 0)
1923 12:12:12.008129 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1924 12:12:12.011741 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 12:12:12.014801 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 12:12:12.021698 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 12:12:12.024907 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 12:12:12.028458 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 12:12:12.035204 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 12:12:12.038203 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1931 12:12:12.041867 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1932 12:12:12.048145 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 12:12:12.051735 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 12:12:12.054939 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 12:12:12.061724 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 12:12:12.065185 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 12:12:12.068201 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 12:12:12.075058 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 12:12:12.078057 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 12:12:12.081672 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 12:12:12.085180 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 12:12:12.091629 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 12:12:12.094900 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 12:12:12.098109 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 12:12:12.104899 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 12:12:12.108111 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1947 12:12:12.111695 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1948 12:12:12.114793 Total UI for P1: 0, mck2ui 16
1949 12:12:12.118044 best dqsien dly found for B0: ( 0, 14, 4)
1950 12:12:12.125112 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1951 12:12:12.125566 Total UI for P1: 0, mck2ui 16
1952 12:12:12.131591 best dqsien dly found for B1: ( 0, 14, 8)
1953 12:12:12.135120 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1954 12:12:12.138282 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1955 12:12:12.138711
1956 12:12:12.141936 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1957 12:12:12.144996 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1958 12:12:12.148450 [Gating] SW calibration Done
1959 12:12:12.148876 ==
1960 12:12:12.151839 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 12:12:12.154829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 12:12:12.155257 ==
1963 12:12:12.158568 RX Vref Scan: 0
1964 12:12:12.158993
1965 12:12:12.159331 RX Vref 0 -> 0, step: 1
1966 12:12:12.159649
1967 12:12:12.161756 RX Delay -130 -> 252, step: 16
1968 12:12:12.165118 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1969 12:12:12.171695 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1970 12:12:12.174804 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1971 12:12:12.178366 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1972 12:12:12.181740 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1973 12:12:12.185067 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1974 12:12:12.191494 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1975 12:12:12.194645 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1976 12:12:12.198143 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1977 12:12:12.201766 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1978 12:12:12.204995 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1979 12:12:12.208264 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1980 12:12:12.214863 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1981 12:12:12.218244 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1982 12:12:12.221774 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1983 12:12:12.224814 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1984 12:12:12.225239 ==
1985 12:12:12.228311 Dram Type= 6, Freq= 0, CH_1, rank 1
1986 12:12:12.234936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1987 12:12:12.235364 ==
1988 12:12:12.235709 DQS Delay:
1989 12:12:12.238340 DQS0 = 0, DQS1 = 0
1990 12:12:12.238764 DQM Delay:
1991 12:12:12.239103 DQM0 = 78, DQM1 = 71
1992 12:12:12.241697 DQ Delay:
1993 12:12:12.244815 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1994 12:12:12.248283 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1995 12:12:12.251803 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1996 12:12:12.254814 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1997 12:12:12.255243
1998 12:12:12.255577
1999 12:12:12.255893 ==
2000 12:12:12.258062 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 12:12:12.261699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 12:12:12.262131 ==
2003 12:12:12.262475
2004 12:12:12.262795
2005 12:12:12.265119 TX Vref Scan disable
2006 12:12:12.265585 == TX Byte 0 ==
2007 12:12:12.271665 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2008 12:12:12.274843 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2009 12:12:12.275312 == TX Byte 1 ==
2010 12:12:12.281736 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2011 12:12:12.284805 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2012 12:12:12.285233 ==
2013 12:12:12.288262 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 12:12:12.291736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 12:12:12.292167 ==
2016 12:12:12.306219 TX Vref=22, minBit 11, minWin=27, winSum=455
2017 12:12:12.309781 TX Vref=24, minBit 2, minWin=28, winSum=457
2018 12:12:12.313021 TX Vref=26, minBit 3, minWin=28, winSum=459
2019 12:12:12.316370 TX Vref=28, minBit 3, minWin=28, winSum=461
2020 12:12:12.319609 TX Vref=30, minBit 13, minWin=28, winSum=467
2021 12:12:12.326140 TX Vref=32, minBit 5, minWin=28, winSum=467
2022 12:12:12.329675 [TxChooseVref] Worse bit 13, Min win 28, Win sum 467, Final Vref 30
2023 12:12:12.330106
2024 12:12:12.332777 Final TX Range 1 Vref 30
2025 12:12:12.333205
2026 12:12:12.333583 ==
2027 12:12:12.336147 Dram Type= 6, Freq= 0, CH_1, rank 1
2028 12:12:12.339710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2029 12:12:12.342921 ==
2030 12:12:12.343346
2031 12:12:12.343684
2032 12:12:12.343997 TX Vref Scan disable
2033 12:12:12.346575 == TX Byte 0 ==
2034 12:12:12.349776 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2035 12:12:12.356625 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2036 12:12:12.357062 == TX Byte 1 ==
2037 12:12:12.359564 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2038 12:12:12.366406 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2039 12:12:12.366849
2040 12:12:12.367187 [DATLAT]
2041 12:12:12.367560 Freq=800, CH1 RK1
2042 12:12:12.367889
2043 12:12:12.370034 DATLAT Default: 0xa
2044 12:12:12.370486 0, 0xFFFF, sum = 0
2045 12:12:12.373051 1, 0xFFFF, sum = 0
2046 12:12:12.373531 2, 0xFFFF, sum = 0
2047 12:12:12.376514 3, 0xFFFF, sum = 0
2048 12:12:12.379549 4, 0xFFFF, sum = 0
2049 12:12:12.379987 5, 0xFFFF, sum = 0
2050 12:12:12.383240 6, 0xFFFF, sum = 0
2051 12:12:12.383692 7, 0xFFFF, sum = 0
2052 12:12:12.386572 8, 0xFFFF, sum = 0
2053 12:12:12.387011 9, 0x0, sum = 1
2054 12:12:12.387379 10, 0x0, sum = 2
2055 12:12:12.389775 11, 0x0, sum = 3
2056 12:12:12.390212 12, 0x0, sum = 4
2057 12:12:12.393424 best_step = 10
2058 12:12:12.393886
2059 12:12:12.394228 ==
2060 12:12:12.396538 Dram Type= 6, Freq= 0, CH_1, rank 1
2061 12:12:12.399953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2062 12:12:12.400386 ==
2063 12:12:12.403102 RX Vref Scan: 0
2064 12:12:12.403528
2065 12:12:12.403871 RX Vref 0 -> 0, step: 1
2066 12:12:12.404191
2067 12:12:12.406412 RX Delay -111 -> 252, step: 8
2068 12:12:12.413327 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
2069 12:12:12.416770 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2070 12:12:12.420058 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2071 12:12:12.423227 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2072 12:12:12.426600 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2073 12:12:12.433232 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2074 12:12:12.436744 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2075 12:12:12.439930 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2076 12:12:12.443236 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2077 12:12:12.446624 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2078 12:12:12.453051 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2079 12:12:12.456443 iDelay=209, Bit 11, Center 72 (-47 ~ 192) 240
2080 12:12:12.459806 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
2081 12:12:12.463432 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2082 12:12:12.466793 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2083 12:12:12.473662 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2084 12:12:12.474119 ==
2085 12:12:12.476732 Dram Type= 6, Freq= 0, CH_1, rank 1
2086 12:12:12.480071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2087 12:12:12.480503 ==
2088 12:12:12.480846 DQS Delay:
2089 12:12:12.483699 DQS0 = 0, DQS1 = 0
2090 12:12:12.484128 DQM Delay:
2091 12:12:12.486823 DQM0 = 78, DQM1 = 75
2092 12:12:12.487255 DQ Delay:
2093 12:12:12.489991 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =72
2094 12:12:12.493674 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2095 12:12:12.496779 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =72
2096 12:12:12.500218 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
2097 12:12:12.500650
2098 12:12:12.500993
2099 12:12:12.506500 [DQSOSCAuto] RK1, (LSB)MR18= 0x263d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2100 12:12:12.510125 CH1 RK1: MR19=606, MR18=263D
2101 12:12:12.516505 CH1_RK1: MR19=0x606, MR18=0x263D, DQSOSC=394, MR23=63, INC=95, DEC=63
2102 12:12:12.520005 [RxdqsGatingPostProcess] freq 800
2103 12:12:12.526776 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2104 12:12:12.529874 Pre-setting of DQS Precalculation
2105 12:12:12.533449 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2106 12:12:12.539984 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2107 12:12:12.546383 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2108 12:12:12.549789
2109 12:12:12.550215
2110 12:12:12.550558 [Calibration Summary] 1600 Mbps
2111 12:12:12.553401 CH 0, Rank 0
2112 12:12:12.553896 SW Impedance : PASS
2113 12:12:12.556586 DUTY Scan : NO K
2114 12:12:12.559823 ZQ Calibration : PASS
2115 12:12:12.560254 Jitter Meter : NO K
2116 12:12:12.563183 CBT Training : PASS
2117 12:12:12.566502 Write leveling : PASS
2118 12:12:12.566930 RX DQS gating : PASS
2119 12:12:12.569661 RX DQ/DQS(RDDQC) : PASS
2120 12:12:12.572868 TX DQ/DQS : PASS
2121 12:12:12.573298 RX DATLAT : PASS
2122 12:12:12.576291 RX DQ/DQS(Engine): PASS
2123 12:12:12.579795 TX OE : NO K
2124 12:12:12.580224 All Pass.
2125 12:12:12.580566
2126 12:12:12.580883 CH 0, Rank 1
2127 12:12:12.582596 SW Impedance : PASS
2128 12:12:12.586243 DUTY Scan : NO K
2129 12:12:12.586670 ZQ Calibration : PASS
2130 12:12:12.589421 Jitter Meter : NO K
2131 12:12:12.592761 CBT Training : PASS
2132 12:12:12.593187 Write leveling : PASS
2133 12:12:12.595951 RX DQS gating : PASS
2134 12:12:12.596374 RX DQ/DQS(RDDQC) : PASS
2135 12:12:12.599576 TX DQ/DQS : PASS
2136 12:12:12.602997 RX DATLAT : PASS
2137 12:12:12.603470 RX DQ/DQS(Engine): PASS
2138 12:12:12.606361 TX OE : NO K
2139 12:12:12.606792 All Pass.
2140 12:12:12.607135
2141 12:12:12.609547 CH 1, Rank 0
2142 12:12:12.610003 SW Impedance : PASS
2143 12:12:12.613034 DUTY Scan : NO K
2144 12:12:12.616295 ZQ Calibration : PASS
2145 12:12:12.616721 Jitter Meter : NO K
2146 12:12:12.619655 CBT Training : PASS
2147 12:12:12.622784 Write leveling : PASS
2148 12:12:12.623284 RX DQS gating : PASS
2149 12:12:12.626133 RX DQ/DQS(RDDQC) : PASS
2150 12:12:12.629722 TX DQ/DQS : PASS
2151 12:12:12.630154 RX DATLAT : PASS
2152 12:12:12.632790 RX DQ/DQS(Engine): PASS
2153 12:12:12.636116 TX OE : NO K
2154 12:12:12.636581 All Pass.
2155 12:12:12.636933
2156 12:12:12.637312 CH 1, Rank 1
2157 12:12:12.639558 SW Impedance : PASS
2158 12:12:12.642729 DUTY Scan : NO K
2159 12:12:12.643156 ZQ Calibration : PASS
2160 12:12:12.646213 Jitter Meter : NO K
2161 12:12:12.646646 CBT Training : PASS
2162 12:12:12.649375 Write leveling : PASS
2163 12:12:12.652829 RX DQS gating : PASS
2164 12:12:12.653256 RX DQ/DQS(RDDQC) : PASS
2165 12:12:12.656300 TX DQ/DQS : PASS
2166 12:12:12.659168 RX DATLAT : PASS
2167 12:12:12.659664 RX DQ/DQS(Engine): PASS
2168 12:12:12.662724 TX OE : NO K
2169 12:12:12.663156 All Pass.
2170 12:12:12.663503
2171 12:12:12.666077 DramC Write-DBI off
2172 12:12:12.669313 PER_BANK_REFRESH: Hybrid Mode
2173 12:12:12.669777 TX_TRACKING: ON
2174 12:12:12.672619 [GetDramInforAfterCalByMRR] Vendor 6.
2175 12:12:12.676061 [GetDramInforAfterCalByMRR] Revision 606.
2176 12:12:12.679101 [GetDramInforAfterCalByMRR] Revision 2 0.
2177 12:12:12.682531 MR0 0x3b3b
2178 12:12:12.682976 MR8 0x5151
2179 12:12:12.686091 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2180 12:12:12.686525
2181 12:12:12.689215 MR0 0x3b3b
2182 12:12:12.689684 MR8 0x5151
2183 12:12:12.692826 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2184 12:12:12.693256
2185 12:12:12.702441 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2186 12:12:12.705941 [FAST_K] Save calibration result to emmc
2187 12:12:12.709386 [FAST_K] Save calibration result to emmc
2188 12:12:12.709888 dram_init: config_dvfs: 1
2189 12:12:12.716156 dramc_set_vcore_voltage set vcore to 662500
2190 12:12:12.716860 Read voltage for 1200, 2
2191 12:12:12.719282 Vio18 = 0
2192 12:12:12.719708 Vcore = 662500
2193 12:12:12.720053 Vdram = 0
2194 12:12:12.722492 Vddq = 0
2195 12:12:12.723145 Vmddr = 0
2196 12:12:12.725799 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2197 12:12:12.732883 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2198 12:12:12.736058 MEM_TYPE=3, freq_sel=15
2199 12:12:12.739020 sv_algorithm_assistance_LP4_1600
2200 12:12:12.742506 ============ PULL DRAM RESETB DOWN ============
2201 12:12:12.745561 ========== PULL DRAM RESETB DOWN end =========
2202 12:12:12.749074 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2203 12:12:12.752251 ===================================
2204 12:12:12.755500 LPDDR4 DRAM CONFIGURATION
2205 12:12:12.759157 ===================================
2206 12:12:12.762202 EX_ROW_EN[0] = 0x0
2207 12:12:12.762335 EX_ROW_EN[1] = 0x0
2208 12:12:12.765462 LP4Y_EN = 0x0
2209 12:12:12.765610 WORK_FSP = 0x0
2210 12:12:12.768686 WL = 0x4
2211 12:12:12.768818 RL = 0x4
2212 12:12:12.772580 BL = 0x2
2213 12:12:12.772712 RPST = 0x0
2214 12:12:12.775580 RD_PRE = 0x0
2215 12:12:12.775711 WR_PRE = 0x1
2216 12:12:12.778919 WR_PST = 0x0
2217 12:12:12.779049 DBI_WR = 0x0
2218 12:12:12.782202 DBI_RD = 0x0
2219 12:12:12.782335 OTF = 0x1
2220 12:12:12.785463 ===================================
2221 12:12:12.789044 ===================================
2222 12:12:12.792449 ANA top config
2223 12:12:12.795815 ===================================
2224 12:12:12.798906 DLL_ASYNC_EN = 0
2225 12:12:12.799102 ALL_SLAVE_EN = 0
2226 12:12:12.802525 NEW_RANK_MODE = 1
2227 12:12:12.805525 DLL_IDLE_MODE = 1
2228 12:12:12.809079 LP45_APHY_COMB_EN = 1
2229 12:12:12.809362 TX_ODT_DIS = 1
2230 12:12:12.812703 NEW_8X_MODE = 1
2231 12:12:12.815895 ===================================
2232 12:12:12.819358 ===================================
2233 12:12:12.822704 data_rate = 2400
2234 12:12:12.826063 CKR = 1
2235 12:12:12.829330 DQ_P2S_RATIO = 8
2236 12:12:12.832740 ===================================
2237 12:12:12.836032 CA_P2S_RATIO = 8
2238 12:12:12.836466 DQ_CA_OPEN = 0
2239 12:12:12.839524 DQ_SEMI_OPEN = 0
2240 12:12:12.842538 CA_SEMI_OPEN = 0
2241 12:12:12.846107 CA_FULL_RATE = 0
2242 12:12:12.849287 DQ_CKDIV4_EN = 0
2243 12:12:12.852492 CA_CKDIV4_EN = 0
2244 12:12:12.852919 CA_PREDIV_EN = 0
2245 12:12:12.855703 PH8_DLY = 17
2246 12:12:12.859280 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2247 12:12:12.862363 DQ_AAMCK_DIV = 4
2248 12:12:12.866008 CA_AAMCK_DIV = 4
2249 12:12:12.869130 CA_ADMCK_DIV = 4
2250 12:12:12.869665 DQ_TRACK_CA_EN = 0
2251 12:12:12.872618 CA_PICK = 1200
2252 12:12:12.875984 CA_MCKIO = 1200
2253 12:12:12.879061 MCKIO_SEMI = 0
2254 12:12:12.882329 PLL_FREQ = 2366
2255 12:12:12.885901 DQ_UI_PI_RATIO = 32
2256 12:12:12.889101 CA_UI_PI_RATIO = 0
2257 12:12:12.892537 ===================================
2258 12:12:12.895960 ===================================
2259 12:12:12.896384 memory_type:LPDDR4
2260 12:12:12.899460 GP_NUM : 10
2261 12:12:12.899886 SRAM_EN : 1
2262 12:12:12.902907 MD32_EN : 0
2263 12:12:12.906090 ===================================
2264 12:12:12.909346 [ANA_INIT] >>>>>>>>>>>>>>
2265 12:12:12.912672 <<<<<< [CONFIGURE PHASE]: ANA_TX
2266 12:12:12.916011 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2267 12:12:12.919124 ===================================
2268 12:12:12.919573 data_rate = 2400,PCW = 0X5b00
2269 12:12:12.922726 ===================================
2270 12:12:12.929302 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2271 12:12:12.932528 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2272 12:12:12.939077 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2273 12:12:12.942210 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2274 12:12:12.945739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2275 12:12:12.948877 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2276 12:12:12.952186 [ANA_INIT] flow start
2277 12:12:12.955682 [ANA_INIT] PLL >>>>>>>>
2278 12:12:12.956317 [ANA_INIT] PLL <<<<<<<<
2279 12:12:12.958824 [ANA_INIT] MIDPI >>>>>>>>
2280 12:12:12.961971 [ANA_INIT] MIDPI <<<<<<<<
2281 12:12:12.962562 [ANA_INIT] DLL >>>>>>>>
2282 12:12:12.965404 [ANA_INIT] DLL <<<<<<<<
2283 12:12:12.968585 [ANA_INIT] flow end
2284 12:12:12.972051 ============ LP4 DIFF to SE enter ============
2285 12:12:12.975317 ============ LP4 DIFF to SE exit ============
2286 12:12:12.978808 [ANA_INIT] <<<<<<<<<<<<<
2287 12:12:12.982156 [Flow] Enable top DCM control >>>>>
2288 12:12:12.985394 [Flow] Enable top DCM control <<<<<
2289 12:12:12.988689 Enable DLL master slave shuffle
2290 12:12:12.992087 ==============================================================
2291 12:12:12.995423 Gating Mode config
2292 12:12:13.001956 ==============================================================
2293 12:12:13.002386 Config description:
2294 12:12:13.012262 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2295 12:12:13.018671 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2296 12:12:13.025383 SELPH_MODE 0: By rank 1: By Phase
2297 12:12:13.028618 ==============================================================
2298 12:12:13.031687 GAT_TRACK_EN = 1
2299 12:12:13.035390 RX_GATING_MODE = 2
2300 12:12:13.038290 RX_GATING_TRACK_MODE = 2
2301 12:12:13.041706 SELPH_MODE = 1
2302 12:12:13.045245 PICG_EARLY_EN = 1
2303 12:12:13.048390 VALID_LAT_VALUE = 1
2304 12:12:13.051909 ==============================================================
2305 12:12:13.055446 Enter into Gating configuration >>>>
2306 12:12:13.058599 Exit from Gating configuration <<<<
2307 12:12:13.061874 Enter into DVFS_PRE_config >>>>>
2308 12:12:13.075086 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2309 12:12:13.078192 Exit from DVFS_PRE_config <<<<<
2310 12:12:13.078613 Enter into PICG configuration >>>>
2311 12:12:13.081743 Exit from PICG configuration <<<<
2312 12:12:13.085263 [RX_INPUT] configuration >>>>>
2313 12:12:13.088505 [RX_INPUT] configuration <<<<<
2314 12:12:13.095131 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2315 12:12:13.098314 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2316 12:12:13.105322 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2317 12:12:13.111782 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2318 12:12:13.118398 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2319 12:12:13.125025 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2320 12:12:13.128413 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2321 12:12:13.131496 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2322 12:12:13.134897 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2323 12:12:13.141459 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2324 12:12:13.144957 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2325 12:12:13.148331 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2326 12:12:13.151460 ===================================
2327 12:12:13.154646 LPDDR4 DRAM CONFIGURATION
2328 12:12:13.158178 ===================================
2329 12:12:13.161675 EX_ROW_EN[0] = 0x0
2330 12:12:13.162351 EX_ROW_EN[1] = 0x0
2331 12:12:13.164710 LP4Y_EN = 0x0
2332 12:12:13.165132 WORK_FSP = 0x0
2333 12:12:13.168386 WL = 0x4
2334 12:12:13.168811 RL = 0x4
2335 12:12:13.171549 BL = 0x2
2336 12:12:13.171973 RPST = 0x0
2337 12:12:13.174802 RD_PRE = 0x0
2338 12:12:13.175225 WR_PRE = 0x1
2339 12:12:13.178317 WR_PST = 0x0
2340 12:12:13.178741 DBI_WR = 0x0
2341 12:12:13.181697 DBI_RD = 0x0
2342 12:12:13.182183 OTF = 0x1
2343 12:12:13.184751 ===================================
2344 12:12:13.188327 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2345 12:12:13.195094 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2346 12:12:13.198041 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2347 12:12:13.201775 ===================================
2348 12:12:13.205088 LPDDR4 DRAM CONFIGURATION
2349 12:12:13.208187 ===================================
2350 12:12:13.208632 EX_ROW_EN[0] = 0x10
2351 12:12:13.211396 EX_ROW_EN[1] = 0x0
2352 12:12:13.211814 LP4Y_EN = 0x0
2353 12:12:13.214859 WORK_FSP = 0x0
2354 12:12:13.218432 WL = 0x4
2355 12:12:13.218853 RL = 0x4
2356 12:12:13.221455 BL = 0x2
2357 12:12:13.221899 RPST = 0x0
2358 12:12:13.224668 RD_PRE = 0x0
2359 12:12:13.225089 WR_PRE = 0x1
2360 12:12:13.228100 WR_PST = 0x0
2361 12:12:13.228515 DBI_WR = 0x0
2362 12:12:13.231470 DBI_RD = 0x0
2363 12:12:13.231887 OTF = 0x1
2364 12:12:13.234849 ===================================
2365 12:12:13.241381 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2366 12:12:13.241832 ==
2367 12:12:13.244769 Dram Type= 6, Freq= 0, CH_0, rank 0
2368 12:12:13.248264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2369 12:12:13.248684 ==
2370 12:12:13.251486 [Duty_Offset_Calibration]
2371 12:12:13.254668 B0:2 B1:0 CA:3
2372 12:12:13.255169
2373 12:12:13.257762 [DutyScan_Calibration_Flow] k_type=0
2374 12:12:13.265956
2375 12:12:13.266379 ==CLK 0==
2376 12:12:13.269404 Final CLK duty delay cell = 0
2377 12:12:13.272634 [0] MAX Duty = 5062%(X100), DQS PI = 20
2378 12:12:13.276075 [0] MIN Duty = 4875%(X100), DQS PI = 58
2379 12:12:13.276493 [0] AVG Duty = 4968%(X100)
2380 12:12:13.279385
2381 12:12:13.282502 CH0 CLK Duty spec in!! Max-Min= 187%
2382 12:12:13.286002 [DutyScan_Calibration_Flow] ====Done====
2383 12:12:13.286510
2384 12:12:13.289410 [DutyScan_Calibration_Flow] k_type=1
2385 12:12:13.304671
2386 12:12:13.305098 ==DQS 0 ==
2387 12:12:13.307857 Final DQS duty delay cell = 0
2388 12:12:13.311157 [0] MAX Duty = 5062%(X100), DQS PI = 14
2389 12:12:13.314476 [0] MIN Duty = 4907%(X100), DQS PI = 2
2390 12:12:13.314899 [0] AVG Duty = 4984%(X100)
2391 12:12:13.317758
2392 12:12:13.318210 ==DQS 1 ==
2393 12:12:13.321012 Final DQS duty delay cell = -4
2394 12:12:13.324515 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2395 12:12:13.327716 [-4] MIN Duty = 4875%(X100), DQS PI = 16
2396 12:12:13.331275 [-4] AVG Duty = 4937%(X100)
2397 12:12:13.331692
2398 12:12:13.334289 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2399 12:12:13.334708
2400 12:12:13.337547 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2401 12:12:13.340928 [DutyScan_Calibration_Flow] ====Done====
2402 12:12:13.341383
2403 12:12:13.344488 [DutyScan_Calibration_Flow] k_type=3
2404 12:12:13.361999
2405 12:12:13.362453 ==DQM 0 ==
2406 12:12:13.365555 Final DQM duty delay cell = 0
2407 12:12:13.368698 [0] MAX Duty = 5124%(X100), DQS PI = 26
2408 12:12:13.371956 [0] MIN Duty = 4876%(X100), DQS PI = 48
2409 12:12:13.375522 [0] AVG Duty = 5000%(X100)
2410 12:12:13.375945
2411 12:12:13.376476 ==DQM 1 ==
2412 12:12:13.378869 Final DQM duty delay cell = 4
2413 12:12:13.382054 [4] MAX Duty = 5124%(X100), DQS PI = 50
2414 12:12:13.385291 [4] MIN Duty = 5031%(X100), DQS PI = 12
2415 12:12:13.388912 [4] AVG Duty = 5077%(X100)
2416 12:12:13.389333
2417 12:12:13.392072 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2418 12:12:13.392494
2419 12:12:13.395139 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2420 12:12:13.398557 [DutyScan_Calibration_Flow] ====Done====
2421 12:12:13.399028
2422 12:12:13.401881 [DutyScan_Calibration_Flow] k_type=2
2423 12:12:13.416825
2424 12:12:13.417269 ==DQ 0 ==
2425 12:12:13.420265 Final DQ duty delay cell = -4
2426 12:12:13.423739 [-4] MAX Duty = 5000%(X100), DQS PI = 12
2427 12:12:13.426911 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2428 12:12:13.430126 [-4] AVG Duty = 4953%(X100)
2429 12:12:13.430551
2430 12:12:13.430887 ==DQ 1 ==
2431 12:12:13.433648 Final DQ duty delay cell = -4
2432 12:12:13.436841 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2433 12:12:13.440282 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2434 12:12:13.443534 [-4] AVG Duty = 4938%(X100)
2435 12:12:13.443960
2436 12:12:13.447206 CH0 DQ 0 Duty spec in!! Max-Min= 93%
2437 12:12:13.447631
2438 12:12:13.450279 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2439 12:12:13.453441 [DutyScan_Calibration_Flow] ====Done====
2440 12:12:13.453899 ==
2441 12:12:13.456970 Dram Type= 6, Freq= 0, CH_1, rank 0
2442 12:12:13.460139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2443 12:12:13.460569 ==
2444 12:12:13.463524 [Duty_Offset_Calibration]
2445 12:12:13.463979 B0:1 B1:-2 CA:0
2446 12:12:13.464509
2447 12:12:13.466924 [DutyScan_Calibration_Flow] k_type=0
2448 12:12:13.477380
2449 12:12:13.477817 ==CLK 0==
2450 12:12:13.480793 Final CLK duty delay cell = 0
2451 12:12:13.484017 [0] MAX Duty = 5031%(X100), DQS PI = 16
2452 12:12:13.487540 [0] MIN Duty = 4844%(X100), DQS PI = 58
2453 12:12:13.487972 [0] AVG Duty = 4937%(X100)
2454 12:12:13.490866
2455 12:12:13.493939 CH1 CLK Duty spec in!! Max-Min= 187%
2456 12:12:13.497116 [DutyScan_Calibration_Flow] ====Done====
2457 12:12:13.497571
2458 12:12:13.500644 [DutyScan_Calibration_Flow] k_type=1
2459 12:12:13.515834
2460 12:12:13.516257 ==DQS 0 ==
2461 12:12:13.519111 Final DQS duty delay cell = -4
2462 12:12:13.522698 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2463 12:12:13.525800 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2464 12:12:13.529165 [-4] AVG Duty = 4953%(X100)
2465 12:12:13.529749
2466 12:12:13.530130 ==DQS 1 ==
2467 12:12:13.532741 Final DQS duty delay cell = 0
2468 12:12:13.536037 [0] MAX Duty = 5093%(X100), DQS PI = 0
2469 12:12:13.539052 [0] MIN Duty = 4875%(X100), DQS PI = 42
2470 12:12:13.542556 [0] AVG Duty = 4984%(X100)
2471 12:12:13.543128
2472 12:12:13.545927 CH1 DQS 0 Duty spec in!! Max-Min= 93%
2473 12:12:13.546336
2474 12:12:13.549153 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2475 12:12:13.552698 [DutyScan_Calibration_Flow] ====Done====
2476 12:12:13.553145
2477 12:12:13.555725 [DutyScan_Calibration_Flow] k_type=3
2478 12:12:13.572699
2479 12:12:13.573122 ==DQM 0 ==
2480 12:12:13.575643 Final DQM duty delay cell = 0
2481 12:12:13.579188 [0] MAX Duty = 5000%(X100), DQS PI = 22
2482 12:12:13.582432 [0] MIN Duty = 4844%(X100), DQS PI = 56
2483 12:12:13.582861 [0] AVG Duty = 4922%(X100)
2484 12:12:13.585550
2485 12:12:13.585977 ==DQM 1 ==
2486 12:12:13.589075 Final DQM duty delay cell = 0
2487 12:12:13.592700 [0] MAX Duty = 5031%(X100), DQS PI = 36
2488 12:12:13.595840 [0] MIN Duty = 4907%(X100), DQS PI = 4
2489 12:12:13.596421 [0] AVG Duty = 4969%(X100)
2490 12:12:13.596959
2491 12:12:13.602522 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2492 12:12:13.603070
2493 12:12:13.605865 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2494 12:12:13.609267 [DutyScan_Calibration_Flow] ====Done====
2495 12:12:13.609746
2496 12:12:13.612426 [DutyScan_Calibration_Flow] k_type=2
2497 12:12:13.628686
2498 12:12:13.629090 ==DQ 0 ==
2499 12:12:13.632017 Final DQ duty delay cell = 0
2500 12:12:13.635355 [0] MAX Duty = 5062%(X100), DQS PI = 18
2501 12:12:13.638921 [0] MIN Duty = 4938%(X100), DQS PI = 52
2502 12:12:13.639447 [0] AVG Duty = 5000%(X100)
2503 12:12:13.639932
2504 12:12:13.642291 ==DQ 1 ==
2505 12:12:13.645349 Final DQ duty delay cell = 0
2506 12:12:13.648677 [0] MAX Duty = 5125%(X100), DQS PI = 36
2507 12:12:13.652250 [0] MIN Duty = 4969%(X100), DQS PI = 26
2508 12:12:13.652681 [0] AVG Duty = 5047%(X100)
2509 12:12:13.653017
2510 12:12:13.655340 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2511 12:12:13.658841
2512 12:12:13.662173 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2513 12:12:13.665327 [DutyScan_Calibration_Flow] ====Done====
2514 12:12:13.668898 nWR fixed to 30
2515 12:12:13.669370 [ModeRegInit_LP4] CH0 RK0
2516 12:12:13.671893 [ModeRegInit_LP4] CH0 RK1
2517 12:12:13.675193 [ModeRegInit_LP4] CH1 RK0
2518 12:12:13.675621 [ModeRegInit_LP4] CH1 RK1
2519 12:12:13.678688 match AC timing 7
2520 12:12:13.682425 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2521 12:12:13.685211 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2522 12:12:13.691836 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2523 12:12:13.695178 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2524 12:12:13.701882 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2525 12:12:13.702317 ==
2526 12:12:13.705261 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 12:12:13.708869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 12:12:13.709319 ==
2529 12:12:13.715128 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2530 12:12:13.721773 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2531 12:12:13.728828 [CA 0] Center 40 (10~71) winsize 62
2532 12:12:13.732073 [CA 1] Center 40 (10~70) winsize 61
2533 12:12:13.735446 [CA 2] Center 36 (6~66) winsize 61
2534 12:12:13.738835 [CA 3] Center 35 (5~66) winsize 62
2535 12:12:13.742142 [CA 4] Center 34 (4~65) winsize 62
2536 12:12:13.745617 [CA 5] Center 33 (3~64) winsize 62
2537 12:12:13.746053
2538 12:12:13.748775 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2539 12:12:13.749276
2540 12:12:13.752044 [CATrainingPosCal] consider 1 rank data
2541 12:12:13.755332 u2DelayCellTimex100 = 270/100 ps
2542 12:12:13.758823 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2543 12:12:13.765563 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2544 12:12:13.768867 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2545 12:12:13.772187 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2546 12:12:13.775496 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2547 12:12:13.779166 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2548 12:12:13.779598
2549 12:12:13.782242 CA PerBit enable=1, Macro0, CA PI delay=33
2550 12:12:13.782744
2551 12:12:13.785373 [CBTSetCACLKResult] CA Dly = 33
2552 12:12:13.788777 CS Dly: 7 (0~38)
2553 12:12:13.789207 ==
2554 12:12:13.792294 Dram Type= 6, Freq= 0, CH_0, rank 1
2555 12:12:13.795489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2556 12:12:13.795921 ==
2557 12:12:13.801841 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2558 12:12:13.805098 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2559 12:12:13.815010 [CA 0] Center 40 (10~71) winsize 62
2560 12:12:13.818496 [CA 1] Center 40 (10~70) winsize 61
2561 12:12:13.821634 [CA 2] Center 35 (5~66) winsize 62
2562 12:12:13.825204 [CA 3] Center 35 (5~66) winsize 62
2563 12:12:13.828210 [CA 4] Center 34 (4~65) winsize 62
2564 12:12:13.831797 [CA 5] Center 33 (3~63) winsize 61
2565 12:12:13.832226
2566 12:12:13.834887 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2567 12:12:13.835316
2568 12:12:13.838430 [CATrainingPosCal] consider 2 rank data
2569 12:12:13.841939 u2DelayCellTimex100 = 270/100 ps
2570 12:12:13.845096 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2571 12:12:13.851523 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2572 12:12:13.855077 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2573 12:12:13.858490 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2574 12:12:13.861661 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2575 12:12:13.864785 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2576 12:12:13.865443
2577 12:12:13.868114 CA PerBit enable=1, Macro0, CA PI delay=33
2578 12:12:13.868639
2579 12:12:13.871521 [CBTSetCACLKResult] CA Dly = 33
2580 12:12:13.874642 CS Dly: 7 (0~39)
2581 12:12:13.875071
2582 12:12:13.878129 ----->DramcWriteLeveling(PI) begin...
2583 12:12:13.878697 ==
2584 12:12:13.881603 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 12:12:13.884773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 12:12:13.885217 ==
2587 12:12:13.888299 Write leveling (Byte 0): 32 => 32
2588 12:12:13.891346 Write leveling (Byte 1): 30 => 30
2589 12:12:13.894830 DramcWriteLeveling(PI) end<-----
2590 12:12:13.895255
2591 12:12:13.895597 ==
2592 12:12:13.898127 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 12:12:13.901547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 12:12:13.901977 ==
2595 12:12:13.905022 [Gating] SW mode calibration
2596 12:12:13.911731 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2597 12:12:13.917790 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2598 12:12:13.920899 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 12:12:13.924449 0 15 4 | B1->B0 | 2626 3232 | 1 1 | (1 1) (1 1)
2600 12:12:13.931046 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 12:12:13.934228 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 12:12:13.937398 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 12:12:13.944072 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 12:12:13.947550 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 12:12:13.950663 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2606 12:12:13.957768 1 0 0 | B1->B0 | 3333 2c2c | 0 0 | (0 0) (0 1)
2607 12:12:13.961041 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2608 12:12:13.964381 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 12:12:13.970835 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 12:12:13.974323 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 12:12:13.977638 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 12:12:13.980777 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 12:12:13.987337 1 0 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2614 12:12:13.990776 1 1 0 | B1->B0 | 2828 3232 | 0 0 | (0 0) (0 0)
2615 12:12:13.994059 1 1 4 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
2616 12:12:14.000868 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 12:12:14.003957 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 12:12:14.007362 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 12:12:14.013898 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 12:12:14.017363 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 12:12:14.020853 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 12:12:14.027492 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2623 12:12:14.030748 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 12:12:14.033782 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 12:12:14.040507 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 12:12:14.044100 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 12:12:14.047318 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 12:12:14.053923 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 12:12:14.057214 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 12:12:14.060711 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 12:12:14.067706 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 12:12:14.070663 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 12:12:14.074237 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 12:12:14.080819 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 12:12:14.083939 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 12:12:14.087289 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 12:12:14.090758 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2638 12:12:14.097207 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2639 12:12:14.100933 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2640 12:12:14.103932 Total UI for P1: 0, mck2ui 16
2641 12:12:14.107701 best dqsien dly found for B0: ( 1, 3, 30)
2642 12:12:14.110609 Total UI for P1: 0, mck2ui 16
2643 12:12:14.113922 best dqsien dly found for B1: ( 1, 4, 0)
2644 12:12:14.117427 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2645 12:12:14.120573 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2646 12:12:14.120685
2647 12:12:14.124071 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2648 12:12:14.127261 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2649 12:12:14.130444 [Gating] SW calibration Done
2650 12:12:14.130537 ==
2651 12:12:14.134088 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 12:12:14.137297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2653 12:12:14.140752 ==
2654 12:12:14.140836 RX Vref Scan: 0
2655 12:12:14.140928
2656 12:12:14.144013 RX Vref 0 -> 0, step: 1
2657 12:12:14.144118
2658 12:12:14.147230 RX Delay -40 -> 252, step: 8
2659 12:12:14.150313 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2660 12:12:14.153784 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2661 12:12:14.157056 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2662 12:12:14.160485 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2663 12:12:14.167204 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2664 12:12:14.170572 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2665 12:12:14.173778 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2666 12:12:14.177157 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2667 12:12:14.180678 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2668 12:12:14.184029 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2669 12:12:14.190550 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2670 12:12:14.193996 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2671 12:12:14.197386 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2672 12:12:14.200394 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2673 12:12:14.203752 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2674 12:12:14.210466 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2675 12:12:14.210574 ==
2676 12:12:14.213991 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 12:12:14.216946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 12:12:14.217060 ==
2679 12:12:14.217127 DQS Delay:
2680 12:12:14.220607 DQS0 = 0, DQS1 = 0
2681 12:12:14.220691 DQM Delay:
2682 12:12:14.223964 DQM0 = 113, DQM1 = 104
2683 12:12:14.224083 DQ Delay:
2684 12:12:14.227274 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =111
2685 12:12:14.230515 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2686 12:12:14.233894 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2687 12:12:14.237364 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =111
2688 12:12:14.237465
2689 12:12:14.237556
2690 12:12:14.240662 ==
2691 12:12:14.240781 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 12:12:14.246904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 12:12:14.247019 ==
2694 12:12:14.247114
2695 12:12:14.247204
2696 12:12:14.250388 TX Vref Scan disable
2697 12:12:14.250491 == TX Byte 0 ==
2698 12:12:14.253555 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2699 12:12:14.260297 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2700 12:12:14.260404 == TX Byte 1 ==
2701 12:12:14.263783 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2702 12:12:14.270384 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2703 12:12:14.270468 ==
2704 12:12:14.273538 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 12:12:14.277078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 12:12:14.277161 ==
2707 12:12:14.288833 TX Vref=22, minBit 4, minWin=25, winSum=417
2708 12:12:14.292385 TX Vref=24, minBit 1, minWin=26, winSum=424
2709 12:12:14.295939 TX Vref=26, minBit 5, minWin=26, winSum=431
2710 12:12:14.299330 TX Vref=28, minBit 8, minWin=26, winSum=437
2711 12:12:14.302399 TX Vref=30, minBit 12, minWin=26, winSum=434
2712 12:12:14.309077 TX Vref=32, minBit 10, minWin=25, winSum=429
2713 12:12:14.312470 [TxChooseVref] Worse bit 8, Min win 26, Win sum 437, Final Vref 28
2714 12:12:14.312553
2715 12:12:14.315681 Final TX Range 1 Vref 28
2716 12:12:14.315764
2717 12:12:14.315830 ==
2718 12:12:14.318652 Dram Type= 6, Freq= 0, CH_0, rank 0
2719 12:12:14.322183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2720 12:12:14.325286 ==
2721 12:12:14.325368
2722 12:12:14.325432
2723 12:12:14.325522 TX Vref Scan disable
2724 12:12:14.328936 == TX Byte 0 ==
2725 12:12:14.332326 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2726 12:12:14.338779 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2727 12:12:14.338862 == TX Byte 1 ==
2728 12:12:14.342342 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2729 12:12:14.348717 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2730 12:12:14.348799
2731 12:12:14.348865 [DATLAT]
2732 12:12:14.348926 Freq=1200, CH0 RK0
2733 12:12:14.348985
2734 12:12:14.352362 DATLAT Default: 0xd
2735 12:12:14.352445 0, 0xFFFF, sum = 0
2736 12:12:14.355345 1, 0xFFFF, sum = 0
2737 12:12:14.358796 2, 0xFFFF, sum = 0
2738 12:12:14.358908 3, 0xFFFF, sum = 0
2739 12:12:14.362534 4, 0xFFFF, sum = 0
2740 12:12:14.362618 5, 0xFFFF, sum = 0
2741 12:12:14.365438 6, 0xFFFF, sum = 0
2742 12:12:14.365543 7, 0xFFFF, sum = 0
2743 12:12:14.369014 8, 0xFFFF, sum = 0
2744 12:12:14.369097 9, 0xFFFF, sum = 0
2745 12:12:14.372265 10, 0xFFFF, sum = 0
2746 12:12:14.372349 11, 0xFFFF, sum = 0
2747 12:12:14.375526 12, 0x0, sum = 1
2748 12:12:14.375609 13, 0x0, sum = 2
2749 12:12:14.378815 14, 0x0, sum = 3
2750 12:12:14.378898 15, 0x0, sum = 4
2751 12:12:14.381876 best_step = 13
2752 12:12:14.381957
2753 12:12:14.382023 ==
2754 12:12:14.385353 Dram Type= 6, Freq= 0, CH_0, rank 0
2755 12:12:14.388540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2756 12:12:14.388624 ==
2757 12:12:14.388692 RX Vref Scan: 1
2758 12:12:14.388754
2759 12:12:14.392095 Set Vref Range= 32 -> 127
2760 12:12:14.392191
2761 12:12:14.395542 RX Vref 32 -> 127, step: 1
2762 12:12:14.395624
2763 12:12:14.398858 RX Delay -37 -> 252, step: 4
2764 12:12:14.398940
2765 12:12:14.401767 Set Vref, RX VrefLevel [Byte0]: 32
2766 12:12:14.405390 [Byte1]: 32
2767 12:12:14.405472
2768 12:12:14.408442 Set Vref, RX VrefLevel [Byte0]: 33
2769 12:12:14.411851 [Byte1]: 33
2770 12:12:14.415636
2771 12:12:14.415718 Set Vref, RX VrefLevel [Byte0]: 34
2772 12:12:14.419150 [Byte1]: 34
2773 12:12:14.423398
2774 12:12:14.423480 Set Vref, RX VrefLevel [Byte0]: 35
2775 12:12:14.426777 [Byte1]: 35
2776 12:12:14.431659
2777 12:12:14.431771 Set Vref, RX VrefLevel [Byte0]: 36
2778 12:12:14.434848 [Byte1]: 36
2779 12:12:14.439432
2780 12:12:14.439513 Set Vref, RX VrefLevel [Byte0]: 37
2781 12:12:14.442792 [Byte1]: 37
2782 12:12:14.447791
2783 12:12:14.447873 Set Vref, RX VrefLevel [Byte0]: 38
2784 12:12:14.454209 [Byte1]: 38
2785 12:12:14.454291
2786 12:12:14.457380 Set Vref, RX VrefLevel [Byte0]: 39
2787 12:12:14.460915 [Byte1]: 39
2788 12:12:14.460997
2789 12:12:14.464252 Set Vref, RX VrefLevel [Byte0]: 40
2790 12:12:14.467402 [Byte1]: 40
2791 12:12:14.471393
2792 12:12:14.471475 Set Vref, RX VrefLevel [Byte0]: 41
2793 12:12:14.474935 [Byte1]: 41
2794 12:12:14.479834
2795 12:12:14.479917 Set Vref, RX VrefLevel [Byte0]: 42
2796 12:12:14.482902 [Byte1]: 42
2797 12:12:14.487562
2798 12:12:14.487647 Set Vref, RX VrefLevel [Byte0]: 43
2799 12:12:14.490780 [Byte1]: 43
2800 12:12:14.495814
2801 12:12:14.495897 Set Vref, RX VrefLevel [Byte0]: 44
2802 12:12:14.498955 [Byte1]: 44
2803 12:12:14.503811
2804 12:12:14.503894 Set Vref, RX VrefLevel [Byte0]: 45
2805 12:12:14.507167 [Byte1]: 45
2806 12:12:14.511491
2807 12:12:14.511573 Set Vref, RX VrefLevel [Byte0]: 46
2808 12:12:14.514953 [Byte1]: 46
2809 12:12:14.519508
2810 12:12:14.519590 Set Vref, RX VrefLevel [Byte0]: 47
2811 12:12:14.523200 [Byte1]: 47
2812 12:12:14.527787
2813 12:12:14.527870 Set Vref, RX VrefLevel [Byte0]: 48
2814 12:12:14.531260 [Byte1]: 48
2815 12:12:14.535825
2816 12:12:14.535908 Set Vref, RX VrefLevel [Byte0]: 49
2817 12:12:14.539010 [Byte1]: 49
2818 12:12:14.543726
2819 12:12:14.543808 Set Vref, RX VrefLevel [Byte0]: 50
2820 12:12:14.547141 [Byte1]: 50
2821 12:12:14.551444
2822 12:12:14.551526 Set Vref, RX VrefLevel [Byte0]: 51
2823 12:12:14.554885 [Byte1]: 51
2824 12:12:14.559579
2825 12:12:14.559662 Set Vref, RX VrefLevel [Byte0]: 52
2826 12:12:14.562731 [Byte1]: 52
2827 12:12:14.567380
2828 12:12:14.567463 Set Vref, RX VrefLevel [Byte0]: 53
2829 12:12:14.570822 [Byte1]: 53
2830 12:12:14.575743
2831 12:12:14.575826 Set Vref, RX VrefLevel [Byte0]: 54
2832 12:12:14.578824 [Byte1]: 54
2833 12:12:14.583756
2834 12:12:14.583840 Set Vref, RX VrefLevel [Byte0]: 55
2835 12:12:14.586935 [Byte1]: 55
2836 12:12:14.591573
2837 12:12:14.591656 Set Vref, RX VrefLevel [Byte0]: 56
2838 12:12:14.594749 [Byte1]: 56
2839 12:12:14.599794
2840 12:12:14.599876 Set Vref, RX VrefLevel [Byte0]: 57
2841 12:12:14.603131 [Byte1]: 57
2842 12:12:14.607729
2843 12:12:14.607812 Set Vref, RX VrefLevel [Byte0]: 58
2844 12:12:14.610923 [Byte1]: 58
2845 12:12:14.615545
2846 12:12:14.615649 Set Vref, RX VrefLevel [Byte0]: 59
2847 12:12:14.618803 [Byte1]: 59
2848 12:12:14.623263
2849 12:12:14.626827 Set Vref, RX VrefLevel [Byte0]: 60
2850 12:12:14.630098 [Byte1]: 60
2851 12:12:14.630181
2852 12:12:14.633223 Set Vref, RX VrefLevel [Byte0]: 61
2853 12:12:14.636603 [Byte1]: 61
2854 12:12:14.636685
2855 12:12:14.640029 Set Vref, RX VrefLevel [Byte0]: 62
2856 12:12:14.643855 [Byte1]: 62
2857 12:12:14.647712
2858 12:12:14.647822 Set Vref, RX VrefLevel [Byte0]: 63
2859 12:12:14.650883 [Byte1]: 63
2860 12:12:14.655613
2861 12:12:14.655693 Set Vref, RX VrefLevel [Byte0]: 64
2862 12:12:14.659155 [Byte1]: 64
2863 12:12:14.663792
2864 12:12:14.663873 Set Vref, RX VrefLevel [Byte0]: 65
2865 12:12:14.666662 [Byte1]: 65
2866 12:12:14.671771
2867 12:12:14.671893 Set Vref, RX VrefLevel [Byte0]: 66
2868 12:12:14.674859 [Byte1]: 66
2869 12:12:14.679817
2870 12:12:14.679898 Set Vref, RX VrefLevel [Byte0]: 67
2871 12:12:14.682846 [Byte1]: 67
2872 12:12:14.688038
2873 12:12:14.688120 Set Vref, RX VrefLevel [Byte0]: 68
2874 12:12:14.690832 [Byte1]: 68
2875 12:12:14.695405
2876 12:12:14.695486 Set Vref, RX VrefLevel [Byte0]: 69
2877 12:12:14.699017 [Byte1]: 69
2878 12:12:14.703576
2879 12:12:14.703704 Set Vref, RX VrefLevel [Byte0]: 70
2880 12:12:14.707163 [Byte1]: 70
2881 12:12:14.711500
2882 12:12:14.711584 Set Vref, RX VrefLevel [Byte0]: 71
2883 12:12:14.717821 [Byte1]: 71
2884 12:12:14.717904
2885 12:12:14.721406 Set Vref, RX VrefLevel [Byte0]: 72
2886 12:12:14.724733 [Byte1]: 72
2887 12:12:14.724816
2888 12:12:14.728259 Set Vref, RX VrefLevel [Byte0]: 73
2889 12:12:14.731369 [Byte1]: 73
2890 12:12:14.735636
2891 12:12:14.735718 Set Vref, RX VrefLevel [Byte0]: 74
2892 12:12:14.738836 [Byte1]: 74
2893 12:12:14.743462
2894 12:12:14.743547 Final RX Vref Byte 0 = 61 to rank0
2895 12:12:14.746997 Final RX Vref Byte 1 = 53 to rank0
2896 12:12:14.750328 Final RX Vref Byte 0 = 61 to rank1
2897 12:12:14.753481 Final RX Vref Byte 1 = 53 to rank1==
2898 12:12:14.757024 Dram Type= 6, Freq= 0, CH_0, rank 0
2899 12:12:14.763570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2900 12:12:14.763654 ==
2901 12:12:14.763719 DQS Delay:
2902 12:12:14.763780 DQS0 = 0, DQS1 = 0
2903 12:12:14.766947 DQM Delay:
2904 12:12:14.767064 DQM0 = 111, DQM1 = 102
2905 12:12:14.770487 DQ Delay:
2906 12:12:14.773675 DQ0 =110, DQ1 =112, DQ2 =110, DQ3 =108
2907 12:12:14.776792 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2908 12:12:14.780343 DQ8 =94, DQ9 =84, DQ10 =104, DQ11 =94
2909 12:12:14.783774 DQ12 =108, DQ13 =106, DQ14 =116, DQ15 =110
2910 12:12:14.783857
2911 12:12:14.783922
2912 12:12:14.790251 [DQSOSCAuto] RK0, (LSB)MR18= 0xfafa, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2913 12:12:14.793602 CH0 RK0: MR19=303, MR18=FAFA
2914 12:12:14.800359 CH0_RK0: MR19=0x303, MR18=0xFAFA, DQSOSC=412, MR23=63, INC=38, DEC=25
2915 12:12:14.800442
2916 12:12:14.803618 ----->DramcWriteLeveling(PI) begin...
2917 12:12:14.803702 ==
2918 12:12:14.807199 Dram Type= 6, Freq= 0, CH_0, rank 1
2919 12:12:14.810681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 12:12:14.810764 ==
2921 12:12:14.813703 Write leveling (Byte 0): 32 => 32
2922 12:12:14.817237 Write leveling (Byte 1): 30 => 30
2923 12:12:14.820363 DramcWriteLeveling(PI) end<-----
2924 12:12:14.820445
2925 12:12:14.820510 ==
2926 12:12:14.823594 Dram Type= 6, Freq= 0, CH_0, rank 1
2927 12:12:14.830432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2928 12:12:14.830515 ==
2929 12:12:14.830585 [Gating] SW mode calibration
2930 12:12:14.840235 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2931 12:12:14.843504 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2932 12:12:14.846990 0 15 0 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
2933 12:12:14.853810 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2934 12:12:14.857153 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2935 12:12:14.860532 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2936 12:12:14.866884 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2937 12:12:14.870554 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2938 12:12:14.873624 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2939 12:12:14.880109 0 15 28 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
2940 12:12:14.883674 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
2941 12:12:14.886775 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2942 12:12:14.893644 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2943 12:12:14.896975 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2944 12:12:14.900259 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2945 12:12:14.906703 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2946 12:12:14.910189 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2947 12:12:14.913678 1 0 28 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
2948 12:12:14.920011 1 1 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
2949 12:12:14.923561 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2950 12:12:14.926756 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2951 12:12:14.930490 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2952 12:12:14.936870 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2953 12:12:14.940027 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2954 12:12:14.943390 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2955 12:12:14.950328 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2956 12:12:14.953365 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2957 12:12:14.956773 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 12:12:14.963535 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 12:12:14.966758 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 12:12:14.969914 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 12:12:14.976584 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 12:12:14.980030 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 12:12:14.983251 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 12:12:14.990165 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 12:12:14.993358 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2966 12:12:14.996518 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2967 12:12:15.003388 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2968 12:12:15.006591 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 12:12:15.009901 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 12:12:15.016639 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 12:12:15.019906 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2972 12:12:15.023011 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2973 12:12:15.026655 Total UI for P1: 0, mck2ui 16
2974 12:12:15.030097 best dqsien dly found for B0: ( 1, 3, 28)
2975 12:12:15.036742 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2976 12:12:15.036852 Total UI for P1: 0, mck2ui 16
2977 12:12:15.039675 best dqsien dly found for B1: ( 1, 4, 0)
2978 12:12:15.046486 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2979 12:12:15.050008 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2980 12:12:15.050090
2981 12:12:15.053432 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2982 12:12:15.056456 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2983 12:12:15.059852 [Gating] SW calibration Done
2984 12:12:15.059934 ==
2985 12:12:15.063257 Dram Type= 6, Freq= 0, CH_0, rank 1
2986 12:12:15.066445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2987 12:12:15.066528 ==
2988 12:12:15.069780 RX Vref Scan: 0
2989 12:12:15.069861
2990 12:12:15.069926 RX Vref 0 -> 0, step: 1
2991 12:12:15.069987
2992 12:12:15.073052 RX Delay -40 -> 252, step: 8
2993 12:12:15.076301 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2994 12:12:15.079810 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2995 12:12:15.086593 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2996 12:12:15.089919 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2997 12:12:15.093296 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2998 12:12:15.096484 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2999 12:12:15.100014 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3000 12:12:15.106585 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3001 12:12:15.109984 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3002 12:12:15.113055 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
3003 12:12:15.116410 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3004 12:12:15.119845 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
3005 12:12:15.122988 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
3006 12:12:15.129954 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3007 12:12:15.133306 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3008 12:12:15.136361 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
3009 12:12:15.136442 ==
3010 12:12:15.139702 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 12:12:15.143289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 12:12:15.146589 ==
3013 12:12:15.146670 DQS Delay:
3014 12:12:15.146735 DQS0 = 0, DQS1 = 0
3015 12:12:15.149915 DQM Delay:
3016 12:12:15.149995 DQM0 = 111, DQM1 = 101
3017 12:12:15.153313 DQ Delay:
3018 12:12:15.156651 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
3019 12:12:15.160032 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
3020 12:12:15.163351 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
3021 12:12:15.166393 DQ12 =107, DQ13 =111, DQ14 =111, DQ15 =107
3022 12:12:15.166481
3023 12:12:15.166550
3024 12:12:15.166676 ==
3025 12:12:15.169864 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 12:12:15.172898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 12:12:15.172982 ==
3028 12:12:15.173048
3029 12:12:15.173109
3030 12:12:15.176672 TX Vref Scan disable
3031 12:12:15.179774 == TX Byte 0 ==
3032 12:12:15.183480 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3033 12:12:15.186855 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3034 12:12:15.190010 == TX Byte 1 ==
3035 12:12:15.193719 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3036 12:12:15.196780 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3037 12:12:15.196861 ==
3038 12:12:15.200004 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 12:12:15.203472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 12:12:15.203553 ==
3041 12:12:15.216317 TX Vref=22, minBit 1, minWin=25, winSum=427
3042 12:12:15.219760 TX Vref=24, minBit 1, minWin=26, winSum=433
3043 12:12:15.223006 TX Vref=26, minBit 0, minWin=27, winSum=435
3044 12:12:15.226622 TX Vref=28, minBit 8, minWin=26, winSum=440
3045 12:12:15.229762 TX Vref=30, minBit 1, minWin=27, winSum=441
3046 12:12:15.236442 TX Vref=32, minBit 13, minWin=26, winSum=439
3047 12:12:15.240032 [TxChooseVref] Worse bit 1, Min win 27, Win sum 441, Final Vref 30
3048 12:12:15.240114
3049 12:12:15.242968 Final TX Range 1 Vref 30
3050 12:12:15.243051
3051 12:12:15.243116 ==
3052 12:12:15.246252 Dram Type= 6, Freq= 0, CH_0, rank 1
3053 12:12:15.249558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3054 12:12:15.253077 ==
3055 12:12:15.253600
3056 12:12:15.254078
3057 12:12:15.254405 TX Vref Scan disable
3058 12:12:15.256883 == TX Byte 0 ==
3059 12:12:15.260072 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3060 12:12:15.263477 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3061 12:12:15.266592 == TX Byte 1 ==
3062 12:12:15.270130 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3063 12:12:15.273553 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3064 12:12:15.276896
3065 12:12:15.277431 [DATLAT]
3066 12:12:15.277828 Freq=1200, CH0 RK1
3067 12:12:15.278145
3068 12:12:15.280165 DATLAT Default: 0xd
3069 12:12:15.280629 0, 0xFFFF, sum = 0
3070 12:12:15.283492 1, 0xFFFF, sum = 0
3071 12:12:15.283919 2, 0xFFFF, sum = 0
3072 12:12:15.286756 3, 0xFFFF, sum = 0
3073 12:12:15.287235 4, 0xFFFF, sum = 0
3074 12:12:15.290150 5, 0xFFFF, sum = 0
3075 12:12:15.293366 6, 0xFFFF, sum = 0
3076 12:12:15.293866 7, 0xFFFF, sum = 0
3077 12:12:15.296818 8, 0xFFFF, sum = 0
3078 12:12:15.297242 9, 0xFFFF, sum = 0
3079 12:12:15.299944 10, 0xFFFF, sum = 0
3080 12:12:15.300424 11, 0xFFFF, sum = 0
3081 12:12:15.303431 12, 0x0, sum = 1
3082 12:12:15.303858 13, 0x0, sum = 2
3083 12:12:15.306674 14, 0x0, sum = 3
3084 12:12:15.307105 15, 0x0, sum = 4
3085 12:12:15.307447 best_step = 13
3086 12:12:15.307762
3087 12:12:15.309958 ==
3088 12:12:15.313386 Dram Type= 6, Freq= 0, CH_0, rank 1
3089 12:12:15.316506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3090 12:12:15.316925 ==
3091 12:12:15.317274 RX Vref Scan: 0
3092 12:12:15.317634
3093 12:12:15.320111 RX Vref 0 -> 0, step: 1
3094 12:12:15.320530
3095 12:12:15.323440 RX Delay -37 -> 252, step: 4
3096 12:12:15.326816 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3097 12:12:15.333314 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3098 12:12:15.336553 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3099 12:12:15.340142 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3100 12:12:15.343598 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3101 12:12:15.346714 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3102 12:12:15.353441 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3103 12:12:15.356789 iDelay=195, Bit 7, Center 116 (43 ~ 190) 148
3104 12:12:15.360133 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3105 12:12:15.363234 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3106 12:12:15.366671 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3107 12:12:15.370272 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3108 12:12:15.376857 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3109 12:12:15.379861 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3110 12:12:15.383242 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3111 12:12:15.386716 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3112 12:12:15.387186 ==
3113 12:12:15.389802 Dram Type= 6, Freq= 0, CH_0, rank 1
3114 12:12:15.396930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 12:12:15.397355 ==
3116 12:12:15.397763 DQS Delay:
3117 12:12:15.399835 DQS0 = 0, DQS1 = 0
3118 12:12:15.400251 DQM Delay:
3119 12:12:15.403043 DQM0 = 110, DQM1 = 101
3120 12:12:15.403464 DQ Delay:
3121 12:12:15.406505 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3122 12:12:15.409791 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =116
3123 12:12:15.413201 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3124 12:12:15.416380 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3125 12:12:15.416860
3126 12:12:15.417312
3127 12:12:15.426502 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3128 12:12:15.426979 CH0 RK1: MR19=403, MR18=10F8
3129 12:12:15.432979 CH0_RK1: MR19=0x403, MR18=0x10F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3130 12:12:15.436578 [RxdqsGatingPostProcess] freq 1200
3131 12:12:15.443228 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3132 12:12:15.446412 best DQS0 dly(2T, 0.5T) = (0, 11)
3133 12:12:15.449894 best DQS1 dly(2T, 0.5T) = (0, 12)
3134 12:12:15.453224 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3135 12:12:15.456475 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3136 12:12:15.457093 best DQS0 dly(2T, 0.5T) = (0, 11)
3137 12:12:15.459678 best DQS1 dly(2T, 0.5T) = (0, 12)
3138 12:12:15.463219 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3139 12:12:15.466407 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3140 12:12:15.469628 Pre-setting of DQS Precalculation
3141 12:12:15.476436 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3142 12:12:15.476852 ==
3143 12:12:15.479856 Dram Type= 6, Freq= 0, CH_1, rank 0
3144 12:12:15.483313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3145 12:12:15.483776 ==
3146 12:12:15.489587 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3147 12:12:15.493021 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3148 12:12:15.502929 [CA 0] Center 37 (7~67) winsize 61
3149 12:12:15.506299 [CA 1] Center 38 (8~68) winsize 61
3150 12:12:15.509700 [CA 2] Center 34 (4~64) winsize 61
3151 12:12:15.512983 [CA 3] Center 33 (3~64) winsize 62
3152 12:12:15.516498 [CA 4] Center 34 (4~64) winsize 61
3153 12:12:15.519705 [CA 5] Center 33 (3~63) winsize 61
3154 12:12:15.520117
3155 12:12:15.522884 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3156 12:12:15.523261
3157 12:12:15.526241 [CATrainingPosCal] consider 1 rank data
3158 12:12:15.529666 u2DelayCellTimex100 = 270/100 ps
3159 12:12:15.532853 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3160 12:12:15.536276 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3161 12:12:15.543253 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3162 12:12:15.546148 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3163 12:12:15.549710 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3164 12:12:15.552778 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3165 12:12:15.553210
3166 12:12:15.556219 CA PerBit enable=1, Macro0, CA PI delay=33
3167 12:12:15.556742
3168 12:12:15.559876 [CBTSetCACLKResult] CA Dly = 33
3169 12:12:15.560453 CS Dly: 6 (0~37)
3170 12:12:15.560904 ==
3171 12:12:15.563082 Dram Type= 6, Freq= 0, CH_1, rank 1
3172 12:12:15.569576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 12:12:15.570021 ==
3174 12:12:15.573158 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3175 12:12:15.579471 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3176 12:12:15.588607 [CA 0] Center 37 (7~67) winsize 61
3177 12:12:15.591999 [CA 1] Center 37 (7~68) winsize 62
3178 12:12:15.595030 [CA 2] Center 34 (4~65) winsize 62
3179 12:12:15.598472 [CA 3] Center 33 (3~64) winsize 62
3180 12:12:15.602005 [CA 4] Center 34 (4~64) winsize 61
3181 12:12:15.605076 [CA 5] Center 33 (2~64) winsize 63
3182 12:12:15.605705
3183 12:12:15.608652 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3184 12:12:15.609111
3185 12:12:15.611711 [CATrainingPosCal] consider 2 rank data
3186 12:12:15.615229 u2DelayCellTimex100 = 270/100 ps
3187 12:12:15.618830 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3188 12:12:15.621810 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3189 12:12:15.628699 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3190 12:12:15.631895 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3191 12:12:15.635450 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3192 12:12:15.638446 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3193 12:12:15.638876
3194 12:12:15.641772 CA PerBit enable=1, Macro0, CA PI delay=33
3195 12:12:15.642198
3196 12:12:15.645348 [CBTSetCACLKResult] CA Dly = 33
3197 12:12:15.645807 CS Dly: 7 (0~39)
3198 12:12:15.646186
3199 12:12:15.648392 ----->DramcWriteLeveling(PI) begin...
3200 12:12:15.651839 ==
3201 12:12:15.652264 Dram Type= 6, Freq= 0, CH_1, rank 0
3202 12:12:15.658341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3203 12:12:15.658930 ==
3204 12:12:15.661779 Write leveling (Byte 0): 25 => 25
3205 12:12:15.665171 Write leveling (Byte 1): 27 => 27
3206 12:12:15.665641 DramcWriteLeveling(PI) end<-----
3207 12:12:15.668528
3208 12:12:15.668959 ==
3209 12:12:15.671762 Dram Type= 6, Freq= 0, CH_1, rank 0
3210 12:12:15.675274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3211 12:12:15.675700 ==
3212 12:12:15.678810 [Gating] SW mode calibration
3213 12:12:15.685119 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3214 12:12:15.688610 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3215 12:12:15.695222 0 15 0 | B1->B0 | 2f2f 2c2b | 0 1 | (0 0) (0 0)
3216 12:12:15.698633 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3217 12:12:15.701880 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3218 12:12:15.708353 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3219 12:12:15.711685 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3220 12:12:15.714945 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3221 12:12:15.721705 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3222 12:12:15.725153 0 15 28 | B1->B0 | 2d2d 3030 | 0 0 | (0 0) (0 0)
3223 12:12:15.728373 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3224 12:12:15.734923 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3225 12:12:15.738112 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3226 12:12:15.741891 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3227 12:12:15.748498 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3228 12:12:15.751769 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3229 12:12:15.754665 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3230 12:12:15.761684 1 0 28 | B1->B0 | 3a3a 3838 | 1 0 | (0 0) (1 1)
3231 12:12:15.765047 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3232 12:12:15.768149 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3233 12:12:15.774998 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3234 12:12:15.778154 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3235 12:12:15.781554 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3236 12:12:15.788182 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3237 12:12:15.791607 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3238 12:12:15.794806 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3239 12:12:15.801398 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3240 12:12:15.804776 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 12:12:15.808309 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 12:12:15.811298 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 12:12:15.818275 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 12:12:15.821421 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 12:12:15.824958 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 12:12:15.831490 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 12:12:15.834884 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3248 12:12:15.837948 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3249 12:12:15.844713 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3250 12:12:15.848154 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 12:12:15.851325 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 12:12:15.858164 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 12:12:15.861547 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3254 12:12:15.864773 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3255 12:12:15.871595 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3256 12:12:15.872024 Total UI for P1: 0, mck2ui 16
3257 12:12:15.878356 best dqsien dly found for B0: ( 1, 3, 28)
3258 12:12:15.878782 Total UI for P1: 0, mck2ui 16
3259 12:12:15.881537 best dqsien dly found for B1: ( 1, 3, 28)
3260 12:12:15.888184 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3261 12:12:15.891269 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3262 12:12:15.891694
3263 12:12:15.894879 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3264 12:12:15.898083 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3265 12:12:15.901313 [Gating] SW calibration Done
3266 12:12:15.901786 ==
3267 12:12:15.904453 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 12:12:15.908182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 12:12:15.908611 ==
3270 12:12:15.911193 RX Vref Scan: 0
3271 12:12:15.911618
3272 12:12:15.911957 RX Vref 0 -> 0, step: 1
3273 12:12:15.912273
3274 12:12:15.914432 RX Delay -40 -> 252, step: 8
3275 12:12:15.917835 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3276 12:12:15.924606 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3277 12:12:15.927885 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3278 12:12:15.931158 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3279 12:12:15.934473 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3280 12:12:15.937974 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3281 12:12:15.944568 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3282 12:12:15.947727 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3283 12:12:15.951260 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3284 12:12:15.954624 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3285 12:12:15.958051 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3286 12:12:15.961318 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3287 12:12:15.967890 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3288 12:12:15.971225 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3289 12:12:15.974242 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3290 12:12:15.977962 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3291 12:12:15.978387 ==
3292 12:12:15.980943 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 12:12:15.987712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3294 12:12:15.988142 ==
3295 12:12:15.988481 DQS Delay:
3296 12:12:15.990754 DQS0 = 0, DQS1 = 0
3297 12:12:15.991177 DQM Delay:
3298 12:12:15.994370 DQM0 = 115, DQM1 = 105
3299 12:12:15.994790 DQ Delay:
3300 12:12:15.997427 DQ0 =123, DQ1 =111, DQ2 =99, DQ3 =115
3301 12:12:16.000998 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3302 12:12:16.004177 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3303 12:12:16.007609 DQ12 =115, DQ13 =111, DQ14 =111, DQ15 =111
3304 12:12:16.008032
3305 12:12:16.008367
3306 12:12:16.008677 ==
3307 12:12:16.010584 Dram Type= 6, Freq= 0, CH_1, rank 0
3308 12:12:16.014162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3309 12:12:16.017746 ==
3310 12:12:16.018168
3311 12:12:16.018504
3312 12:12:16.018817 TX Vref Scan disable
3313 12:12:16.020834 == TX Byte 0 ==
3314 12:12:16.024406 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3315 12:12:16.027434 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3316 12:12:16.030701 == TX Byte 1 ==
3317 12:12:16.034132 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3318 12:12:16.037391 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3319 12:12:16.040860 ==
3320 12:12:16.041348 Dram Type= 6, Freq= 0, CH_1, rank 0
3321 12:12:16.047324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3322 12:12:16.047823 ==
3323 12:12:16.058179 TX Vref=22, minBit 8, minWin=24, winSum=407
3324 12:12:16.061756 TX Vref=24, minBit 11, minWin=23, winSum=407
3325 12:12:16.065056 TX Vref=26, minBit 9, minWin=25, winSum=415
3326 12:12:16.068114 TX Vref=28, minBit 9, minWin=25, winSum=417
3327 12:12:16.071571 TX Vref=30, minBit 9, minWin=24, winSum=424
3328 12:12:16.078400 TX Vref=32, minBit 9, minWin=25, winSum=418
3329 12:12:16.081525 [TxChooseVref] Worse bit 9, Min win 25, Win sum 418, Final Vref 32
3330 12:12:16.081954
3331 12:12:16.085274 Final TX Range 1 Vref 32
3332 12:12:16.085899
3333 12:12:16.086266 ==
3334 12:12:16.088598 Dram Type= 6, Freq= 0, CH_1, rank 0
3335 12:12:16.091762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3336 12:12:16.092301 ==
3337 12:12:16.092662
3338 12:12:16.095234
3339 12:12:16.095653 TX Vref Scan disable
3340 12:12:16.098414 == TX Byte 0 ==
3341 12:12:16.101576 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3342 12:12:16.105001 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3343 12:12:16.108264 == TX Byte 1 ==
3344 12:12:16.112215 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3345 12:12:16.115260 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3346 12:12:16.118118
3347 12:12:16.118551 [DATLAT]
3348 12:12:16.118907 Freq=1200, CH1 RK0
3349 12:12:16.119249
3350 12:12:16.121630 DATLAT Default: 0xd
3351 12:12:16.122073 0, 0xFFFF, sum = 0
3352 12:12:16.125120 1, 0xFFFF, sum = 0
3353 12:12:16.125613 2, 0xFFFF, sum = 0
3354 12:12:16.128260 3, 0xFFFF, sum = 0
3355 12:12:16.128697 4, 0xFFFF, sum = 0
3356 12:12:16.131581 5, 0xFFFF, sum = 0
3357 12:12:16.132167 6, 0xFFFF, sum = 0
3358 12:12:16.135082 7, 0xFFFF, sum = 0
3359 12:12:16.138132 8, 0xFFFF, sum = 0
3360 12:12:16.138637 9, 0xFFFF, sum = 0
3361 12:12:16.141905 10, 0xFFFF, sum = 0
3362 12:12:16.142381 11, 0xFFFF, sum = 0
3363 12:12:16.145081 12, 0x0, sum = 1
3364 12:12:16.145547 13, 0x0, sum = 2
3365 12:12:16.148125 14, 0x0, sum = 3
3366 12:12:16.148553 15, 0x0, sum = 4
3367 12:12:16.148891 best_step = 13
3368 12:12:16.149200
3369 12:12:16.151764 ==
3370 12:12:16.154949 Dram Type= 6, Freq= 0, CH_1, rank 0
3371 12:12:16.158202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3372 12:12:16.158625 ==
3373 12:12:16.158959 RX Vref Scan: 1
3374 12:12:16.159270
3375 12:12:16.161866 Set Vref Range= 32 -> 127
3376 12:12:16.162393
3377 12:12:16.164677 RX Vref 32 -> 127, step: 1
3378 12:12:16.165098
3379 12:12:16.168437 RX Delay -21 -> 252, step: 4
3380 12:12:16.168857
3381 12:12:16.171367 Set Vref, RX VrefLevel [Byte0]: 32
3382 12:12:16.174676 [Byte1]: 32
3383 12:12:16.175175
3384 12:12:16.178094 Set Vref, RX VrefLevel [Byte0]: 33
3385 12:12:16.181472 [Byte1]: 33
3386 12:12:16.182010
3387 12:12:16.184668 Set Vref, RX VrefLevel [Byte0]: 34
3388 12:12:16.187889 [Byte1]: 34
3389 12:12:16.192532
3390 12:12:16.193030 Set Vref, RX VrefLevel [Byte0]: 35
3391 12:12:16.195672 [Byte1]: 35
3392 12:12:16.200329
3393 12:12:16.203617 Set Vref, RX VrefLevel [Byte0]: 36
3394 12:12:16.206844 [Byte1]: 36
3395 12:12:16.207352
3396 12:12:16.210307 Set Vref, RX VrefLevel [Byte0]: 37
3397 12:12:16.213706 [Byte1]: 37
3398 12:12:16.214210
3399 12:12:16.216860 Set Vref, RX VrefLevel [Byte0]: 38
3400 12:12:16.220457 [Byte1]: 38
3401 12:12:16.224366
3402 12:12:16.224765 Set Vref, RX VrefLevel [Byte0]: 39
3403 12:12:16.227567 [Byte1]: 39
3404 12:12:16.232194
3405 12:12:16.232581 Set Vref, RX VrefLevel [Byte0]: 40
3406 12:12:16.235438 [Byte1]: 40
3407 12:12:16.240052
3408 12:12:16.240438 Set Vref, RX VrefLevel [Byte0]: 41
3409 12:12:16.243507 [Byte1]: 41
3410 12:12:16.247801
3411 12:12:16.248326 Set Vref, RX VrefLevel [Byte0]: 42
3412 12:12:16.251447 [Byte1]: 42
3413 12:12:16.255777
3414 12:12:16.256304 Set Vref, RX VrefLevel [Byte0]: 43
3415 12:12:16.259220 [Byte1]: 43
3416 12:12:16.263876
3417 12:12:16.264400 Set Vref, RX VrefLevel [Byte0]: 44
3418 12:12:16.266998 [Byte1]: 44
3419 12:12:16.271660
3420 12:12:16.272262 Set Vref, RX VrefLevel [Byte0]: 45
3421 12:12:16.274859 [Byte1]: 45
3422 12:12:16.279759
3423 12:12:16.280473 Set Vref, RX VrefLevel [Byte0]: 46
3424 12:12:16.283040 [Byte1]: 46
3425 12:12:16.287522
3426 12:12:16.287966 Set Vref, RX VrefLevel [Byte0]: 47
3427 12:12:16.290851 [Byte1]: 47
3428 12:12:16.295754
3429 12:12:16.296173 Set Vref, RX VrefLevel [Byte0]: 48
3430 12:12:16.298991 [Byte1]: 48
3431 12:12:16.303279
3432 12:12:16.303695 Set Vref, RX VrefLevel [Byte0]: 49
3433 12:12:16.306691 [Byte1]: 49
3434 12:12:16.311182
3435 12:12:16.311599 Set Vref, RX VrefLevel [Byte0]: 50
3436 12:12:16.314699 [Byte1]: 50
3437 12:12:16.319418
3438 12:12:16.319841 Set Vref, RX VrefLevel [Byte0]: 51
3439 12:12:16.322283 [Byte1]: 51
3440 12:12:16.327167
3441 12:12:16.327590 Set Vref, RX VrefLevel [Byte0]: 52
3442 12:12:16.330682 [Byte1]: 52
3443 12:12:16.335176
3444 12:12:16.335716 Set Vref, RX VrefLevel [Byte0]: 53
3445 12:12:16.338189 [Byte1]: 53
3446 12:12:16.342895
3447 12:12:16.343317 Set Vref, RX VrefLevel [Byte0]: 54
3448 12:12:16.346132 [Byte1]: 54
3449 12:12:16.350901
3450 12:12:16.351324 Set Vref, RX VrefLevel [Byte0]: 55
3451 12:12:16.354336 [Byte1]: 55
3452 12:12:16.359139
3453 12:12:16.359564 Set Vref, RX VrefLevel [Byte0]: 56
3454 12:12:16.362044 [Byte1]: 56
3455 12:12:16.366822
3456 12:12:16.367245 Set Vref, RX VrefLevel [Byte0]: 57
3457 12:12:16.370180 [Byte1]: 57
3458 12:12:16.374936
3459 12:12:16.375426 Set Vref, RX VrefLevel [Byte0]: 58
3460 12:12:16.378003 [Byte1]: 58
3461 12:12:16.382760
3462 12:12:16.383188 Set Vref, RX VrefLevel [Byte0]: 59
3463 12:12:16.385912 [Byte1]: 59
3464 12:12:16.390666
3465 12:12:16.391092 Set Vref, RX VrefLevel [Byte0]: 60
3466 12:12:16.393893 [Byte1]: 60
3467 12:12:16.398665
3468 12:12:16.401522 Set Vref, RX VrefLevel [Byte0]: 61
3469 12:12:16.405089 [Byte1]: 61
3470 12:12:16.405564
3471 12:12:16.408226 Set Vref, RX VrefLevel [Byte0]: 62
3472 12:12:16.411396 [Byte1]: 62
3473 12:12:16.411825
3474 12:12:16.415002 Set Vref, RX VrefLevel [Byte0]: 63
3475 12:12:16.418098 [Byte1]: 63
3476 12:12:16.422152
3477 12:12:16.422624 Set Vref, RX VrefLevel [Byte0]: 64
3478 12:12:16.425535 [Byte1]: 64
3479 12:12:16.430145
3480 12:12:16.430570 Set Vref, RX VrefLevel [Byte0]: 65
3481 12:12:16.433440 [Byte1]: 65
3482 12:12:16.438021
3483 12:12:16.438447 Final RX Vref Byte 0 = 57 to rank0
3484 12:12:16.441382 Final RX Vref Byte 1 = 50 to rank0
3485 12:12:16.444603 Final RX Vref Byte 0 = 57 to rank1
3486 12:12:16.447956 Final RX Vref Byte 1 = 50 to rank1==
3487 12:12:16.451420 Dram Type= 6, Freq= 0, CH_1, rank 0
3488 12:12:16.457964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3489 12:12:16.458395 ==
3490 12:12:16.458736 DQS Delay:
3491 12:12:16.459056 DQS0 = 0, DQS1 = 0
3492 12:12:16.461601 DQM Delay:
3493 12:12:16.462098 DQM0 = 114, DQM1 = 106
3494 12:12:16.464677 DQ Delay:
3495 12:12:16.467990 DQ0 =120, DQ1 =108, DQ2 =108, DQ3 =112
3496 12:12:16.471153 DQ4 =110, DQ5 =124, DQ6 =126, DQ7 =110
3497 12:12:16.474719 DQ8 =92, DQ9 =100, DQ10 =104, DQ11 =100
3498 12:12:16.478152 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =114
3499 12:12:16.478616
3500 12:12:16.478966
3501 12:12:16.484697 [DQSOSCAuto] RK0, (LSB)MR18= 0xeff6, (MSB)MR19= 0x303, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
3502 12:12:16.487865 CH1 RK0: MR19=303, MR18=EFF6
3503 12:12:16.494562 CH1_RK0: MR19=0x303, MR18=0xEFF6, DQSOSC=414, MR23=63, INC=38, DEC=25
3504 12:12:16.495040
3505 12:12:16.497842 ----->DramcWriteLeveling(PI) begin...
3506 12:12:16.498396 ==
3507 12:12:16.501138 Dram Type= 6, Freq= 0, CH_1, rank 1
3508 12:12:16.504746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3509 12:12:16.507935 ==
3510 12:12:16.508346 Write leveling (Byte 0): 25 => 25
3511 12:12:16.511447 Write leveling (Byte 1): 26 => 26
3512 12:12:16.514568 DramcWriteLeveling(PI) end<-----
3513 12:12:16.514971
3514 12:12:16.515310 ==
3515 12:12:16.518131 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 12:12:16.524768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 12:12:16.525261 ==
3518 12:12:16.525688 [Gating] SW mode calibration
3519 12:12:16.534735 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3520 12:12:16.538106 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3521 12:12:16.544554 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3522 12:12:16.547788 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3523 12:12:16.551290 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3524 12:12:16.554727 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3525 12:12:16.561379 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3526 12:12:16.564769 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3527 12:12:16.567846 0 15 24 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
3528 12:12:16.574592 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3529 12:12:16.578116 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 12:12:16.581277 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3531 12:12:16.587683 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3532 12:12:16.591061 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3533 12:12:16.594471 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3534 12:12:16.600906 1 0 20 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
3535 12:12:16.604279 1 0 24 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
3536 12:12:16.607470 1 0 28 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
3537 12:12:16.613972 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 12:12:16.617470 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 12:12:16.620553 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3540 12:12:16.627056 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 12:12:16.630621 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3542 12:12:16.633849 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 12:12:16.640562 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3544 12:12:16.643471 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3545 12:12:16.646862 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 12:12:16.653761 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 12:12:16.656816 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 12:12:16.660291 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 12:12:16.666820 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 12:12:16.670305 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 12:12:16.673532 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 12:12:16.680185 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 12:12:16.683592 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 12:12:16.686801 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 12:12:16.693324 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 12:12:16.696746 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 12:12:16.699958 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 12:12:16.706488 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 12:12:16.709778 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3560 12:12:16.712959 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3561 12:12:16.716147 Total UI for P1: 0, mck2ui 16
3562 12:12:16.719630 best dqsien dly found for B0: ( 1, 3, 24)
3563 12:12:16.723246 Total UI for P1: 0, mck2ui 16
3564 12:12:16.726556 best dqsien dly found for B1: ( 1, 3, 24)
3565 12:12:16.729955 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3566 12:12:16.733244 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3567 12:12:16.733732
3568 12:12:16.739607 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3569 12:12:16.742873 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3570 12:12:16.743336 [Gating] SW calibration Done
3571 12:12:16.746460 ==
3572 12:12:16.750075 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 12:12:16.752943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 12:12:16.753536 ==
3575 12:12:16.754096 RX Vref Scan: 0
3576 12:12:16.754476
3577 12:12:16.755747 RX Vref 0 -> 0, step: 1
3578 12:12:16.755855
3579 12:12:16.759267 RX Delay -40 -> 252, step: 8
3580 12:12:16.762264 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3581 12:12:16.765857 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3582 12:12:16.772369 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3583 12:12:16.775937 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3584 12:12:16.779023 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3585 12:12:16.782302 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3586 12:12:16.785862 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3587 12:12:16.792159 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3588 12:12:16.795411 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3589 12:12:16.799005 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3590 12:12:16.802092 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3591 12:12:16.805450 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3592 12:12:16.808943 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3593 12:12:16.815297 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3594 12:12:16.818913 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3595 12:12:16.822044 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3596 12:12:16.822127 ==
3597 12:12:16.825240 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 12:12:16.828752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 12:12:16.832309 ==
3600 12:12:16.832392 DQS Delay:
3601 12:12:16.832458 DQS0 = 0, DQS1 = 0
3602 12:12:16.835258 DQM Delay:
3603 12:12:16.835340 DQM0 = 110, DQM1 = 107
3604 12:12:16.838654 DQ Delay:
3605 12:12:16.842029 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3606 12:12:16.845377 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3607 12:12:16.848568 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =99
3608 12:12:16.851988 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =115
3609 12:12:16.852071
3610 12:12:16.852136
3611 12:12:16.852196 ==
3612 12:12:16.855601 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 12:12:16.858608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 12:12:16.858692 ==
3615 12:12:16.858758
3616 12:12:16.858818
3617 12:12:16.861860 TX Vref Scan disable
3618 12:12:16.865009 == TX Byte 0 ==
3619 12:12:16.868415 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3620 12:12:16.871908 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3621 12:12:16.875014 == TX Byte 1 ==
3622 12:12:16.878363 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3623 12:12:16.881444 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3624 12:12:16.881564 ==
3625 12:12:16.884865 Dram Type= 6, Freq= 0, CH_1, rank 1
3626 12:12:16.891649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3627 12:12:16.891733 ==
3628 12:12:16.901842 TX Vref=22, minBit 0, minWin=25, winSum=422
3629 12:12:16.905447 TX Vref=24, minBit 1, minWin=26, winSum=427
3630 12:12:16.908593 TX Vref=26, minBit 11, minWin=25, winSum=427
3631 12:12:16.912239 TX Vref=28, minBit 13, minWin=26, winSum=435
3632 12:12:16.915082 TX Vref=30, minBit 8, minWin=26, winSum=432
3633 12:12:16.921953 TX Vref=32, minBit 3, minWin=26, winSum=428
3634 12:12:16.925057 [TxChooseVref] Worse bit 13, Min win 26, Win sum 435, Final Vref 28
3635 12:12:16.925140
3636 12:12:16.928643 Final TX Range 1 Vref 28
3637 12:12:16.928726
3638 12:12:16.928795 ==
3639 12:12:16.931741 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 12:12:16.935277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 12:12:16.938553 ==
3642 12:12:16.938636
3643 12:12:16.938702
3644 12:12:16.938763 TX Vref Scan disable
3645 12:12:16.941835 == TX Byte 0 ==
3646 12:12:16.945206 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3647 12:12:16.951900 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3648 12:12:16.951984 == TX Byte 1 ==
3649 12:12:16.955042 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3650 12:12:16.961775 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3651 12:12:16.961868
3652 12:12:16.962004 [DATLAT]
3653 12:12:16.962130 Freq=1200, CH1 RK1
3654 12:12:16.962260
3655 12:12:16.965068 DATLAT Default: 0xd
3656 12:12:16.965151 0, 0xFFFF, sum = 0
3657 12:12:16.968175 1, 0xFFFF, sum = 0
3658 12:12:16.971467 2, 0xFFFF, sum = 0
3659 12:12:16.971552 3, 0xFFFF, sum = 0
3660 12:12:16.975020 4, 0xFFFF, sum = 0
3661 12:12:16.975104 5, 0xFFFF, sum = 0
3662 12:12:16.978091 6, 0xFFFF, sum = 0
3663 12:12:16.978176 7, 0xFFFF, sum = 0
3664 12:12:16.981714 8, 0xFFFF, sum = 0
3665 12:12:16.981871 9, 0xFFFF, sum = 0
3666 12:12:16.985077 10, 0xFFFF, sum = 0
3667 12:12:16.985187 11, 0xFFFF, sum = 0
3668 12:12:16.988197 12, 0x0, sum = 1
3669 12:12:16.988281 13, 0x0, sum = 2
3670 12:12:16.991855 14, 0x0, sum = 3
3671 12:12:16.991940 15, 0x0, sum = 4
3672 12:12:16.994755 best_step = 13
3673 12:12:16.994838
3674 12:12:16.994905 ==
3675 12:12:16.998339 Dram Type= 6, Freq= 0, CH_1, rank 1
3676 12:12:17.001350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3677 12:12:17.001492 ==
3678 12:12:17.001595 RX Vref Scan: 0
3679 12:12:17.001700
3680 12:12:17.004825 RX Vref 0 -> 0, step: 1
3681 12:12:17.004900
3682 12:12:17.007914 RX Delay -21 -> 252, step: 4
3683 12:12:17.014604 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3684 12:12:17.018194 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3685 12:12:17.021350 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3686 12:12:17.024864 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3687 12:12:17.027990 iDelay=195, Bit 4, Center 106 (35 ~ 178) 144
3688 12:12:17.031338 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3689 12:12:17.037851 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3690 12:12:17.041291 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3691 12:12:17.044381 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3692 12:12:17.047897 iDelay=195, Bit 9, Center 102 (35 ~ 170) 136
3693 12:12:17.051209 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3694 12:12:17.057779 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3695 12:12:17.061220 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3696 12:12:17.064259 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3697 12:12:17.067667 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3698 12:12:17.074214 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3699 12:12:17.074295 ==
3700 12:12:17.077689 Dram Type= 6, Freq= 0, CH_1, rank 1
3701 12:12:17.081033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3702 12:12:17.081135 ==
3703 12:12:17.081228 DQS Delay:
3704 12:12:17.084302 DQS0 = 0, DQS1 = 0
3705 12:12:17.084376 DQM Delay:
3706 12:12:17.087563 DQM0 = 111, DQM1 = 110
3707 12:12:17.087675 DQ Delay:
3708 12:12:17.090847 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3709 12:12:17.093961 DQ4 =106, DQ5 =120, DQ6 =122, DQ7 =110
3710 12:12:17.097029 DQ8 =96, DQ9 =102, DQ10 =112, DQ11 =102
3711 12:12:17.100619 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =118
3712 12:12:17.100697
3713 12:12:17.103922
3714 12:12:17.110565 [DQSOSCAuto] RK1, (LSB)MR18= 0xfd0c, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 411 ps
3715 12:12:17.113591 CH1 RK1: MR19=304, MR18=FD0C
3716 12:12:17.120394 CH1_RK1: MR19=0x304, MR18=0xFD0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3717 12:12:17.123722 [RxdqsGatingPostProcess] freq 1200
3718 12:12:17.127005 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3719 12:12:17.130196 best DQS0 dly(2T, 0.5T) = (0, 11)
3720 12:12:17.133295 best DQS1 dly(2T, 0.5T) = (0, 11)
3721 12:12:17.136970 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3722 12:12:17.140221 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3723 12:12:17.143747 best DQS0 dly(2T, 0.5T) = (0, 11)
3724 12:12:17.147022 best DQS1 dly(2T, 0.5T) = (0, 11)
3725 12:12:17.150253 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3726 12:12:17.153364 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3727 12:12:17.156883 Pre-setting of DQS Precalculation
3728 12:12:17.159881 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3729 12:12:17.170101 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3730 12:12:17.176566 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3731 12:12:17.176651
3732 12:12:17.176716
3733 12:12:17.180024 [Calibration Summary] 2400 Mbps
3734 12:12:17.180108 CH 0, Rank 0
3735 12:12:17.183288 SW Impedance : PASS
3736 12:12:17.183371 DUTY Scan : NO K
3737 12:12:17.186772 ZQ Calibration : PASS
3738 12:12:17.189728 Jitter Meter : NO K
3739 12:12:17.189832 CBT Training : PASS
3740 12:12:17.193242 Write leveling : PASS
3741 12:12:17.196401 RX DQS gating : PASS
3742 12:12:17.196482 RX DQ/DQS(RDDQC) : PASS
3743 12:12:17.199886 TX DQ/DQS : PASS
3744 12:12:17.202937 RX DATLAT : PASS
3745 12:12:17.203045 RX DQ/DQS(Engine): PASS
3746 12:12:17.206354 TX OE : NO K
3747 12:12:17.206500 All Pass.
3748 12:12:17.206631
3749 12:12:17.209622 CH 0, Rank 1
3750 12:12:17.209697 SW Impedance : PASS
3751 12:12:17.212891 DUTY Scan : NO K
3752 12:12:17.215948 ZQ Calibration : PASS
3753 12:12:17.216031 Jitter Meter : NO K
3754 12:12:17.219354 CBT Training : PASS
3755 12:12:17.219452 Write leveling : PASS
3756 12:12:17.222539 RX DQS gating : PASS
3757 12:12:17.226095 RX DQ/DQS(RDDQC) : PASS
3758 12:12:17.226172 TX DQ/DQS : PASS
3759 12:12:17.229223 RX DATLAT : PASS
3760 12:12:17.232773 RX DQ/DQS(Engine): PASS
3761 12:12:17.232856 TX OE : NO K
3762 12:12:17.236100 All Pass.
3763 12:12:17.236183
3764 12:12:17.236249 CH 1, Rank 0
3765 12:12:17.239227 SW Impedance : PASS
3766 12:12:17.239310 DUTY Scan : NO K
3767 12:12:17.242451 ZQ Calibration : PASS
3768 12:12:17.245905 Jitter Meter : NO K
3769 12:12:17.245988 CBT Training : PASS
3770 12:12:17.249246 Write leveling : PASS
3771 12:12:17.252423 RX DQS gating : PASS
3772 12:12:17.252528 RX DQ/DQS(RDDQC) : PASS
3773 12:12:17.255768 TX DQ/DQS : PASS
3774 12:12:17.259024 RX DATLAT : PASS
3775 12:12:17.259099 RX DQ/DQS(Engine): PASS
3776 12:12:17.262326 TX OE : NO K
3777 12:12:17.262409 All Pass.
3778 12:12:17.262475
3779 12:12:17.265767 CH 1, Rank 1
3780 12:12:17.265872 SW Impedance : PASS
3781 12:12:17.268897 DUTY Scan : NO K
3782 12:12:17.272675 ZQ Calibration : PASS
3783 12:12:17.272753 Jitter Meter : NO K
3784 12:12:17.275631 CBT Training : PASS
3785 12:12:17.278957 Write leveling : PASS
3786 12:12:17.279040 RX DQS gating : PASS
3787 12:12:17.282322 RX DQ/DQS(RDDQC) : PASS
3788 12:12:17.282406 TX DQ/DQS : PASS
3789 12:12:17.285663 RX DATLAT : PASS
3790 12:12:17.289088 RX DQ/DQS(Engine): PASS
3791 12:12:17.289171 TX OE : NO K
3792 12:12:17.291978 All Pass.
3793 12:12:17.292060
3794 12:12:17.292127 DramC Write-DBI off
3795 12:12:17.295469 PER_BANK_REFRESH: Hybrid Mode
3796 12:12:17.298991 TX_TRACKING: ON
3797 12:12:17.305432 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3798 12:12:17.308586 [FAST_K] Save calibration result to emmc
3799 12:12:17.312106 dramc_set_vcore_voltage set vcore to 650000
3800 12:12:17.315269 Read voltage for 600, 5
3801 12:12:17.315384 Vio18 = 0
3802 12:12:17.318727 Vcore = 650000
3803 12:12:17.318804 Vdram = 0
3804 12:12:17.318869 Vddq = 0
3805 12:12:17.321625 Vmddr = 0
3806 12:12:17.324855 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3807 12:12:17.331652 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3808 12:12:17.334977 MEM_TYPE=3, freq_sel=19
3809 12:12:17.335059 sv_algorithm_assistance_LP4_1600
3810 12:12:17.341625 ============ PULL DRAM RESETB DOWN ============
3811 12:12:17.344932 ========== PULL DRAM RESETB DOWN end =========
3812 12:12:17.348408 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3813 12:12:17.351517 ===================================
3814 12:12:17.355259 LPDDR4 DRAM CONFIGURATION
3815 12:12:17.357999 ===================================
3816 12:12:17.361465 EX_ROW_EN[0] = 0x0
3817 12:12:17.361600 EX_ROW_EN[1] = 0x0
3818 12:12:17.364548 LP4Y_EN = 0x0
3819 12:12:17.364637 WORK_FSP = 0x0
3820 12:12:17.368239 WL = 0x2
3821 12:12:17.368314 RL = 0x2
3822 12:12:17.371463 BL = 0x2
3823 12:12:17.371539 RPST = 0x0
3824 12:12:17.374746 RD_PRE = 0x0
3825 12:12:17.374863 WR_PRE = 0x1
3826 12:12:17.378054 WR_PST = 0x0
3827 12:12:17.378180 DBI_WR = 0x0
3828 12:12:17.381246 DBI_RD = 0x0
3829 12:12:17.384569 OTF = 0x1
3830 12:12:17.387696 ===================================
3831 12:12:17.391072 ===================================
3832 12:12:17.391156 ANA top config
3833 12:12:17.394303 ===================================
3834 12:12:17.397692 DLL_ASYNC_EN = 0
3835 12:12:17.397776 ALL_SLAVE_EN = 1
3836 12:12:17.401112 NEW_RANK_MODE = 1
3837 12:12:17.404155 DLL_IDLE_MODE = 1
3838 12:12:17.407653 LP45_APHY_COMB_EN = 1
3839 12:12:17.410866 TX_ODT_DIS = 1
3840 12:12:17.410943 NEW_8X_MODE = 1
3841 12:12:17.414321 ===================================
3842 12:12:17.417778 ===================================
3843 12:12:17.420799 data_rate = 1200
3844 12:12:17.424060 CKR = 1
3845 12:12:17.427480 DQ_P2S_RATIO = 8
3846 12:12:17.430590 ===================================
3847 12:12:17.434017 CA_P2S_RATIO = 8
3848 12:12:17.437415 DQ_CA_OPEN = 0
3849 12:12:17.437577 DQ_SEMI_OPEN = 0
3850 12:12:17.440753 CA_SEMI_OPEN = 0
3851 12:12:17.443942 CA_FULL_RATE = 0
3852 12:12:17.447296 DQ_CKDIV4_EN = 1
3853 12:12:17.450569 CA_CKDIV4_EN = 1
3854 12:12:17.453801 CA_PREDIV_EN = 0
3855 12:12:17.453878 PH8_DLY = 0
3856 12:12:17.457286 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3857 12:12:17.460711 DQ_AAMCK_DIV = 4
3858 12:12:17.463801 CA_AAMCK_DIV = 4
3859 12:12:17.467178 CA_ADMCK_DIV = 4
3860 12:12:17.470633 DQ_TRACK_CA_EN = 0
3861 12:12:17.473731 CA_PICK = 600
3862 12:12:17.473808 CA_MCKIO = 600
3863 12:12:17.476952 MCKIO_SEMI = 0
3864 12:12:17.480437 PLL_FREQ = 2288
3865 12:12:17.483725 DQ_UI_PI_RATIO = 32
3866 12:12:17.486772 CA_UI_PI_RATIO = 0
3867 12:12:17.490274 ===================================
3868 12:12:17.493215 ===================================
3869 12:12:17.496581 memory_type:LPDDR4
3870 12:12:17.496659 GP_NUM : 10
3871 12:12:17.499995 SRAM_EN : 1
3872 12:12:17.500105 MD32_EN : 0
3873 12:12:17.503378 ===================================
3874 12:12:17.506902 [ANA_INIT] >>>>>>>>>>>>>>
3875 12:12:17.510063 <<<<<< [CONFIGURE PHASE]: ANA_TX
3876 12:12:17.513191 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3877 12:12:17.516333 ===================================
3878 12:12:17.519515 data_rate = 1200,PCW = 0X5800
3879 12:12:17.523140 ===================================
3880 12:12:17.526212 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3881 12:12:17.532821 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3882 12:12:17.536304 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3883 12:12:17.542716 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3884 12:12:17.546212 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3885 12:12:17.549400 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3886 12:12:17.549485 [ANA_INIT] flow start
3887 12:12:17.552884 [ANA_INIT] PLL >>>>>>>>
3888 12:12:17.556197 [ANA_INIT] PLL <<<<<<<<
3889 12:12:17.556277 [ANA_INIT] MIDPI >>>>>>>>
3890 12:12:17.559312 [ANA_INIT] MIDPI <<<<<<<<
3891 12:12:17.562684 [ANA_INIT] DLL >>>>>>>>
3892 12:12:17.562766 [ANA_INIT] flow end
3893 12:12:17.569712 ============ LP4 DIFF to SE enter ============
3894 12:12:17.572666 ============ LP4 DIFF to SE exit ============
3895 12:12:17.576063 [ANA_INIT] <<<<<<<<<<<<<
3896 12:12:17.579229 [Flow] Enable top DCM control >>>>>
3897 12:12:17.582738 [Flow] Enable top DCM control <<<<<
3898 12:12:17.586064 Enable DLL master slave shuffle
3899 12:12:17.589298 ==============================================================
3900 12:12:17.592474 Gating Mode config
3901 12:12:17.596036 ==============================================================
3902 12:12:17.599406 Config description:
3903 12:12:17.609380 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3904 12:12:17.615981 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3905 12:12:17.619157 SELPH_MODE 0: By rank 1: By Phase
3906 12:12:17.625683 ==============================================================
3907 12:12:17.629043 GAT_TRACK_EN = 1
3908 12:12:17.632287 RX_GATING_MODE = 2
3909 12:12:17.635714 RX_GATING_TRACK_MODE = 2
3910 12:12:17.638956 SELPH_MODE = 1
3911 12:12:17.642333 PICG_EARLY_EN = 1
3912 12:12:17.642415 VALID_LAT_VALUE = 1
3913 12:12:17.649157 ==============================================================
3914 12:12:17.652331 Enter into Gating configuration >>>>
3915 12:12:17.655506 Exit from Gating configuration <<<<
3916 12:12:17.658846 Enter into DVFS_PRE_config >>>>>
3917 12:12:17.668698 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3918 12:12:17.671880 Exit from DVFS_PRE_config <<<<<
3919 12:12:17.675488 Enter into PICG configuration >>>>
3920 12:12:17.678649 Exit from PICG configuration <<<<
3921 12:12:17.681948 [RX_INPUT] configuration >>>>>
3922 12:12:17.685306 [RX_INPUT] configuration <<<<<
3923 12:12:17.691848 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3924 12:12:17.695416 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3925 12:12:17.701785 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3926 12:12:17.708275 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3927 12:12:17.714968 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3928 12:12:17.721816 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3929 12:12:17.724994 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3930 12:12:17.728096 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3931 12:12:17.731538 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3932 12:12:17.738148 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3933 12:12:17.741111 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3934 12:12:17.744822 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3935 12:12:17.747898 ===================================
3936 12:12:17.751133 LPDDR4 DRAM CONFIGURATION
3937 12:12:17.754620 ===================================
3938 12:12:17.757818 EX_ROW_EN[0] = 0x0
3939 12:12:17.758022 EX_ROW_EN[1] = 0x0
3940 12:12:17.761209 LP4Y_EN = 0x0
3941 12:12:17.761411 WORK_FSP = 0x0
3942 12:12:17.764602 WL = 0x2
3943 12:12:17.764898 RL = 0x2
3944 12:12:17.768095 BL = 0x2
3945 12:12:17.768398 RPST = 0x0
3946 12:12:17.771024 RD_PRE = 0x0
3947 12:12:17.771326 WR_PRE = 0x1
3948 12:12:17.774647 WR_PST = 0x0
3949 12:12:17.775035 DBI_WR = 0x0
3950 12:12:17.777734 DBI_RD = 0x0
3951 12:12:17.778162 OTF = 0x1
3952 12:12:17.781581 ===================================
3953 12:12:17.787980 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3954 12:12:17.791385 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3955 12:12:17.794555 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3956 12:12:17.797875 ===================================
3957 12:12:17.801005 LPDDR4 DRAM CONFIGURATION
3958 12:12:17.804110 ===================================
3959 12:12:17.807633 EX_ROW_EN[0] = 0x10
3960 12:12:17.808062 EX_ROW_EN[1] = 0x0
3961 12:12:17.810850 LP4Y_EN = 0x0
3962 12:12:17.811278 WORK_FSP = 0x0
3963 12:12:17.814241 WL = 0x2
3964 12:12:17.814672 RL = 0x2
3965 12:12:17.817328 BL = 0x2
3966 12:12:17.817800 RPST = 0x0
3967 12:12:17.820581 RD_PRE = 0x0
3968 12:12:17.821005 WR_PRE = 0x1
3969 12:12:17.823753 WR_PST = 0x0
3970 12:12:17.824180 DBI_WR = 0x0
3971 12:12:17.827319 DBI_RD = 0x0
3972 12:12:17.827745 OTF = 0x1
3973 12:12:17.830417 ===================================
3974 12:12:17.837075 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3975 12:12:17.842195 nWR fixed to 30
3976 12:12:17.845351 [ModeRegInit_LP4] CH0 RK0
3977 12:12:17.845860 [ModeRegInit_LP4] CH0 RK1
3978 12:12:17.848917 [ModeRegInit_LP4] CH1 RK0
3979 12:12:17.852053 [ModeRegInit_LP4] CH1 RK1
3980 12:12:17.852482 match AC timing 17
3981 12:12:17.858567 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3982 12:12:17.862042 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3983 12:12:17.865110 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3984 12:12:17.871551 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3985 12:12:17.874690 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3986 12:12:17.874775 ==
3987 12:12:17.878025 Dram Type= 6, Freq= 0, CH_0, rank 0
3988 12:12:17.881259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 12:12:17.881344 ==
3990 12:12:17.888220 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3991 12:12:17.894496 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3992 12:12:17.897802 [CA 0] Center 37 (7~67) winsize 61
3993 12:12:17.901220 [CA 1] Center 36 (6~67) winsize 62
3994 12:12:17.904461 [CA 2] Center 35 (5~65) winsize 61
3995 12:12:17.907759 [CA 3] Center 35 (5~65) winsize 61
3996 12:12:17.911399 [CA 4] Center 34 (4~64) winsize 61
3997 12:12:17.914698 [CA 5] Center 34 (4~65) winsize 62
3998 12:12:17.914783
3999 12:12:17.917841 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4000 12:12:17.917924
4001 12:12:17.921227 [CATrainingPosCal] consider 1 rank data
4002 12:12:17.924446 u2DelayCellTimex100 = 270/100 ps
4003 12:12:17.927636 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4004 12:12:17.931124 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4005 12:12:17.934568 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4006 12:12:17.937650 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4007 12:12:17.944379 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4008 12:12:17.947652 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4009 12:12:17.947735
4010 12:12:17.951036 CA PerBit enable=1, Macro0, CA PI delay=34
4011 12:12:17.951119
4012 12:12:17.954109 [CBTSetCACLKResult] CA Dly = 34
4013 12:12:17.954192 CS Dly: 6 (0~37)
4014 12:12:17.954259 ==
4015 12:12:17.957660 Dram Type= 6, Freq= 0, CH_0, rank 1
4016 12:12:17.960732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4017 12:12:17.964366 ==
4018 12:12:17.967447 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4019 12:12:17.974122 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4020 12:12:17.977424 [CA 0] Center 37 (7~67) winsize 61
4021 12:12:17.980794 [CA 1] Center 37 (7~67) winsize 61
4022 12:12:17.984464 [CA 2] Center 35 (5~65) winsize 61
4023 12:12:17.987746 [CA 3] Center 35 (5~65) winsize 61
4024 12:12:17.990593 [CA 4] Center 34 (4~65) winsize 62
4025 12:12:17.993947 [CA 5] Center 33 (3~64) winsize 62
4026 12:12:17.994033
4027 12:12:17.997342 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4028 12:12:17.997426
4029 12:12:18.000609 [CATrainingPosCal] consider 2 rank data
4030 12:12:18.004404 u2DelayCellTimex100 = 270/100 ps
4031 12:12:18.007368 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4032 12:12:18.010881 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4033 12:12:18.014170 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4034 12:12:18.020644 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4035 12:12:18.023920 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4036 12:12:18.027281 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4037 12:12:18.027365
4038 12:12:18.030513 CA PerBit enable=1, Macro0, CA PI delay=34
4039 12:12:18.030597
4040 12:12:18.034195 [CBTSetCACLKResult] CA Dly = 34
4041 12:12:18.034279 CS Dly: 6 (0~38)
4042 12:12:18.034346
4043 12:12:18.037154 ----->DramcWriteLeveling(PI) begin...
4044 12:12:18.040475 ==
4045 12:12:18.040559 Dram Type= 6, Freq= 0, CH_0, rank 0
4046 12:12:18.047464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4047 12:12:18.047548 ==
4048 12:12:18.050514 Write leveling (Byte 0): 33 => 33
4049 12:12:18.053828 Write leveling (Byte 1): 32 => 32
4050 12:12:18.057026 DramcWriteLeveling(PI) end<-----
4051 12:12:18.057107
4052 12:12:18.057173 ==
4053 12:12:18.060598 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 12:12:18.063744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 12:12:18.063828 ==
4056 12:12:18.067101 [Gating] SW mode calibration
4057 12:12:18.073459 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4058 12:12:18.080243 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4059 12:12:18.083374 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4060 12:12:18.086991 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4061 12:12:18.090392 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4062 12:12:18.096669 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
4063 12:12:18.100325 0 9 16 | B1->B0 | 3434 2c2c | 1 1 | (1 0) (1 0)
4064 12:12:18.103433 0 9 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4065 12:12:18.109909 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 12:12:18.113732 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 12:12:18.116857 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 12:12:18.123490 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4069 12:12:18.126672 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4070 12:12:18.130048 0 10 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4071 12:12:18.136550 0 10 16 | B1->B0 | 3030 3d3d | 0 0 | (0 0) (0 0)
4072 12:12:18.140178 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 12:12:18.143240 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 12:12:18.149975 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 12:12:18.153278 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 12:12:18.156663 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 12:12:18.163481 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 12:12:18.166598 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 12:12:18.169983 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4080 12:12:18.176235 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 12:12:18.179821 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 12:12:18.182891 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 12:12:18.189507 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 12:12:18.192973 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 12:12:18.196351 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 12:12:18.202558 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 12:12:18.206212 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 12:12:18.209447 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 12:12:18.216122 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 12:12:18.219118 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 12:12:18.222544 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 12:12:18.229227 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 12:12:18.232525 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 12:12:18.235792 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 12:12:18.242418 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4096 12:12:18.242501 Total UI for P1: 0, mck2ui 16
4097 12:12:18.248977 best dqsien dly found for B0: ( 0, 13, 14)
4098 12:12:18.249059 Total UI for P1: 0, mck2ui 16
4099 12:12:18.255743 best dqsien dly found for B1: ( 0, 13, 14)
4100 12:12:18.258874 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4101 12:12:18.262309 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4102 12:12:18.262392
4103 12:12:18.265605 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4104 12:12:18.268924 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4105 12:12:18.272237 [Gating] SW calibration Done
4106 12:12:18.272320 ==
4107 12:12:18.275721 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 12:12:18.278754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 12:12:18.278838 ==
4110 12:12:18.281901 RX Vref Scan: 0
4111 12:12:18.281982
4112 12:12:18.282048 RX Vref 0 -> 0, step: 1
4113 12:12:18.282110
4114 12:12:18.285410 RX Delay -230 -> 252, step: 16
4115 12:12:18.291838 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4116 12:12:18.295183 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4117 12:12:18.298562 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4118 12:12:18.301942 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4119 12:12:18.305406 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4120 12:12:18.312131 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4121 12:12:18.315213 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4122 12:12:18.318603 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4123 12:12:18.321796 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4124 12:12:18.328397 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4125 12:12:18.331774 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4126 12:12:18.335088 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4127 12:12:18.338030 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4128 12:12:18.345307 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4129 12:12:18.348327 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4130 12:12:18.351844 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4131 12:12:18.352009 ==
4132 12:12:18.355116 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 12:12:18.358169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 12:12:18.361764 ==
4135 12:12:18.361973 DQS Delay:
4136 12:12:18.362113 DQS0 = 0, DQS1 = 0
4137 12:12:18.365022 DQM Delay:
4138 12:12:18.365222 DQM0 = 38, DQM1 = 30
4139 12:12:18.368333 DQ Delay:
4140 12:12:18.368548 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4141 12:12:18.371609 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4142 12:12:18.374962 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4143 12:12:18.377974 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4144 12:12:18.381418
4145 12:12:18.381737
4146 12:12:18.381943 ==
4147 12:12:18.385014 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 12:12:18.388022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 12:12:18.388334 ==
4150 12:12:18.388590
4151 12:12:18.388862
4152 12:12:18.391475 TX Vref Scan disable
4153 12:12:18.391845 == TX Byte 0 ==
4154 12:12:18.398213 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4155 12:12:18.401435 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4156 12:12:18.401970 == TX Byte 1 ==
4157 12:12:18.408035 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4158 12:12:18.411460 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4159 12:12:18.411935 ==
4160 12:12:18.414669 Dram Type= 6, Freq= 0, CH_0, rank 0
4161 12:12:18.418128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 12:12:18.418602 ==
4163 12:12:18.418975
4164 12:12:18.419321
4165 12:12:18.421569 TX Vref Scan disable
4166 12:12:18.424804 == TX Byte 0 ==
4167 12:12:18.427764 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4168 12:12:18.431242 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4169 12:12:18.434758 == TX Byte 1 ==
4170 12:12:18.437993 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4171 12:12:18.441056 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4172 12:12:18.444872
4173 12:12:18.445295 [DATLAT]
4174 12:12:18.445700 Freq=600, CH0 RK0
4175 12:12:18.446037
4176 12:12:18.447907 DATLAT Default: 0x9
4177 12:12:18.448334 0, 0xFFFF, sum = 0
4178 12:12:18.451205 1, 0xFFFF, sum = 0
4179 12:12:18.451634 2, 0xFFFF, sum = 0
4180 12:12:18.454693 3, 0xFFFF, sum = 0
4181 12:12:18.455123 4, 0xFFFF, sum = 0
4182 12:12:18.457977 5, 0xFFFF, sum = 0
4183 12:12:18.458413 6, 0xFFFF, sum = 0
4184 12:12:18.461265 7, 0xFFFF, sum = 0
4185 12:12:18.461722 8, 0x0, sum = 1
4186 12:12:18.464625 9, 0x0, sum = 2
4187 12:12:18.465119 10, 0x0, sum = 3
4188 12:12:18.468049 11, 0x0, sum = 4
4189 12:12:18.468544 best_step = 9
4190 12:12:18.468898
4191 12:12:18.469310 ==
4192 12:12:18.471106 Dram Type= 6, Freq= 0, CH_0, rank 0
4193 12:12:18.477711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 12:12:18.478327 ==
4195 12:12:18.478762 RX Vref Scan: 1
4196 12:12:18.479151
4197 12:12:18.480913 RX Vref 0 -> 0, step: 1
4198 12:12:18.481593
4199 12:12:18.484498 RX Delay -195 -> 252, step: 8
4200 12:12:18.485070
4201 12:12:18.487841 Set Vref, RX VrefLevel [Byte0]: 61
4202 12:12:18.491296 [Byte1]: 53
4203 12:12:18.491744
4204 12:12:18.494082 Final RX Vref Byte 0 = 61 to rank0
4205 12:12:18.497724 Final RX Vref Byte 1 = 53 to rank0
4206 12:12:18.500896 Final RX Vref Byte 0 = 61 to rank1
4207 12:12:18.504376 Final RX Vref Byte 1 = 53 to rank1==
4208 12:12:18.507677 Dram Type= 6, Freq= 0, CH_0, rank 0
4209 12:12:18.510938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 12:12:18.511369 ==
4211 12:12:18.514065 DQS Delay:
4212 12:12:18.514490 DQS0 = 0, DQS1 = 0
4213 12:12:18.517522 DQM Delay:
4214 12:12:18.517953 DQM0 = 35, DQM1 = 29
4215 12:12:18.518295 DQ Delay:
4216 12:12:18.520827 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =32
4217 12:12:18.523952 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =44
4218 12:12:18.527488 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4219 12:12:18.530704 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =36
4220 12:12:18.531131
4221 12:12:18.531467
4222 12:12:18.540599 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f3f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4223 12:12:18.544128 CH0 RK0: MR19=808, MR18=3F3F
4224 12:12:18.547272 CH0_RK0: MR19=0x808, MR18=0x3F3F, DQSOSC=397, MR23=63, INC=166, DEC=110
4225 12:12:18.550754
4226 12:12:18.553971 ----->DramcWriteLeveling(PI) begin...
4227 12:12:18.554409 ==
4228 12:12:18.557449 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 12:12:18.560661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 12:12:18.561253 ==
4231 12:12:18.563995 Write leveling (Byte 0): 34 => 34
4232 12:12:18.567121 Write leveling (Byte 1): 30 => 30
4233 12:12:18.570280 DramcWriteLeveling(PI) end<-----
4234 12:12:18.570711
4235 12:12:18.571052 ==
4236 12:12:18.573769 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 12:12:18.577326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 12:12:18.577824 ==
4239 12:12:18.580568 [Gating] SW mode calibration
4240 12:12:18.587081 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4241 12:12:18.593702 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4242 12:12:18.597100 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4243 12:12:18.600131 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4244 12:12:18.606619 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4245 12:12:18.610147 0 9 12 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 0)
4246 12:12:18.613645 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
4247 12:12:18.620347 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 12:12:18.623431 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 12:12:18.626889 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 12:12:18.633382 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 12:12:18.636498 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 12:12:18.640066 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4253 12:12:18.646441 0 10 12 | B1->B0 | 2626 2e2e | 0 0 | (0 0) (0 0)
4254 12:12:18.649956 0 10 16 | B1->B0 | 3838 4444 | 0 0 | (0 0) (0 0)
4255 12:12:18.653124 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 12:12:18.659671 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 12:12:18.663036 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 12:12:18.666601 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 12:12:18.673145 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 12:12:18.676514 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 12:12:18.679982 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4262 12:12:18.686153 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4263 12:12:18.689850 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 12:12:18.693210 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 12:12:18.696342 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 12:12:18.703027 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 12:12:18.706520 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 12:12:18.709652 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 12:12:18.716083 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 12:12:18.719589 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 12:12:18.722827 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 12:12:18.729319 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 12:12:18.732631 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 12:12:18.735986 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 12:12:18.742456 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 12:12:18.745858 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 12:12:18.749065 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4278 12:12:18.755590 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4279 12:12:18.758986 Total UI for P1: 0, mck2ui 16
4280 12:12:18.762244 best dqsien dly found for B0: ( 0, 13, 12)
4281 12:12:18.762327 Total UI for P1: 0, mck2ui 16
4282 12:12:18.768929 best dqsien dly found for B1: ( 0, 13, 14)
4283 12:12:18.771966 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4284 12:12:18.775608 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4285 12:12:18.775691
4286 12:12:18.778923 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4287 12:12:18.781983 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4288 12:12:18.785407 [Gating] SW calibration Done
4289 12:12:18.785531 ==
4290 12:12:18.788655 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 12:12:18.791833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 12:12:18.791916 ==
4293 12:12:18.795504 RX Vref Scan: 0
4294 12:12:18.795587
4295 12:12:18.795653 RX Vref 0 -> 0, step: 1
4296 12:12:18.798626
4297 12:12:18.798708 RX Delay -230 -> 252, step: 16
4298 12:12:18.805493 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4299 12:12:18.808454 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4300 12:12:18.812059 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4301 12:12:18.815227 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4302 12:12:18.821686 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4303 12:12:18.825124 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4304 12:12:18.828246 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4305 12:12:18.831566 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4306 12:12:18.834940 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4307 12:12:18.841565 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4308 12:12:18.845268 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4309 12:12:18.848453 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4310 12:12:18.851576 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4311 12:12:18.858202 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4312 12:12:18.861359 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4313 12:12:18.865095 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4314 12:12:18.865178 ==
4315 12:12:18.867906 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 12:12:18.871420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 12:12:18.875022 ==
4318 12:12:18.875105 DQS Delay:
4319 12:12:18.875171 DQS0 = 0, DQS1 = 0
4320 12:12:18.878152 DQM Delay:
4321 12:12:18.878235 DQM0 = 36, DQM1 = 30
4322 12:12:18.881230 DQ Delay:
4323 12:12:18.884835 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4324 12:12:18.884918 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4325 12:12:18.887875 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4326 12:12:18.891185 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4327 12:12:18.894449
4328 12:12:18.894530
4329 12:12:18.894596 ==
4330 12:12:18.897979 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 12:12:18.901402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 12:12:18.901494 ==
4333 12:12:18.901562
4334 12:12:18.901624
4335 12:12:18.904750 TX Vref Scan disable
4336 12:12:18.904832 == TX Byte 0 ==
4337 12:12:18.911246 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4338 12:12:18.914380 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4339 12:12:18.914463 == TX Byte 1 ==
4340 12:12:18.920966 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4341 12:12:18.924330 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4342 12:12:18.924413 ==
4343 12:12:18.927798 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 12:12:18.930942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 12:12:18.931025 ==
4346 12:12:18.931092
4347 12:12:18.931152
4348 12:12:18.934570 TX Vref Scan disable
4349 12:12:18.937648 == TX Byte 0 ==
4350 12:12:18.941283 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4351 12:12:18.947612 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4352 12:12:18.947695 == TX Byte 1 ==
4353 12:12:18.951062 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4354 12:12:18.957762 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4355 12:12:18.957845
4356 12:12:18.957910 [DATLAT]
4357 12:12:18.957970 Freq=600, CH0 RK1
4358 12:12:18.958029
4359 12:12:18.960647 DATLAT Default: 0x9
4360 12:12:18.960729 0, 0xFFFF, sum = 0
4361 12:12:18.964214 1, 0xFFFF, sum = 0
4362 12:12:18.964297 2, 0xFFFF, sum = 0
4363 12:12:18.967535 3, 0xFFFF, sum = 0
4364 12:12:18.970793 4, 0xFFFF, sum = 0
4365 12:12:18.970876 5, 0xFFFF, sum = 0
4366 12:12:18.974180 6, 0xFFFF, sum = 0
4367 12:12:18.974263 7, 0xFFFF, sum = 0
4368 12:12:18.977743 8, 0x0, sum = 1
4369 12:12:18.977826 9, 0x0, sum = 2
4370 12:12:18.977892 10, 0x0, sum = 3
4371 12:12:18.980853 11, 0x0, sum = 4
4372 12:12:18.980936 best_step = 9
4373 12:12:18.981001
4374 12:12:18.981061 ==
4375 12:12:18.983921 Dram Type= 6, Freq= 0, CH_0, rank 1
4376 12:12:18.990593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4377 12:12:18.990679 ==
4378 12:12:18.990745 RX Vref Scan: 0
4379 12:12:18.990806
4380 12:12:18.994013 RX Vref 0 -> 0, step: 1
4381 12:12:18.994094
4382 12:12:18.997331 RX Delay -195 -> 252, step: 8
4383 12:12:19.000443 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4384 12:12:19.007254 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4385 12:12:19.010329 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4386 12:12:19.013667 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4387 12:12:19.016945 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4388 12:12:19.023707 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4389 12:12:19.027040 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4390 12:12:19.030451 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4391 12:12:19.033516 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4392 12:12:19.036949 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4393 12:12:19.043793 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4394 12:12:19.046945 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4395 12:12:19.050155 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4396 12:12:19.053514 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4397 12:12:19.060246 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4398 12:12:19.063525 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4399 12:12:19.063665 ==
4400 12:12:19.066639 Dram Type= 6, Freq= 0, CH_0, rank 1
4401 12:12:19.069842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 12:12:19.069925 ==
4403 12:12:19.073465 DQS Delay:
4404 12:12:19.073562 DQS0 = 0, DQS1 = 0
4405 12:12:19.076555 DQM Delay:
4406 12:12:19.076638 DQM0 = 33, DQM1 = 28
4407 12:12:19.076703 DQ Delay:
4408 12:12:19.079967 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4409 12:12:19.083408 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4410 12:12:19.086462 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4411 12:12:19.089861 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4412 12:12:19.089943
4413 12:12:19.093137
4414 12:12:19.099675 [DQSOSCAuto] RK1, (LSB)MR18= 0x6837, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4415 12:12:19.103075 CH0 RK1: MR19=808, MR18=6837
4416 12:12:19.109399 CH0_RK1: MR19=0x808, MR18=0x6837, DQSOSC=390, MR23=63, INC=172, DEC=114
4417 12:12:19.112918 [RxdqsGatingPostProcess] freq 600
4418 12:12:19.116126 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4419 12:12:19.119493 Pre-setting of DQS Precalculation
4420 12:12:19.126037 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4421 12:12:19.126160 ==
4422 12:12:19.129501 Dram Type= 6, Freq= 0, CH_1, rank 0
4423 12:12:19.133028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4424 12:12:19.133182 ==
4425 12:12:19.136372 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4426 12:12:19.142957 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4427 12:12:19.146934 [CA 0] Center 36 (6~66) winsize 61
4428 12:12:19.150434 [CA 1] Center 36 (6~66) winsize 61
4429 12:12:19.153638 [CA 2] Center 34 (4~65) winsize 62
4430 12:12:19.157265 [CA 3] Center 34 (4~65) winsize 62
4431 12:12:19.160514 [CA 4] Center 34 (4~65) winsize 62
4432 12:12:19.163593 [CA 5] Center 33 (3~64) winsize 62
4433 12:12:19.164018
4434 12:12:19.167132 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4435 12:12:19.167557
4436 12:12:19.170520 [CATrainingPosCal] consider 1 rank data
4437 12:12:19.173709 u2DelayCellTimex100 = 270/100 ps
4438 12:12:19.176818 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4439 12:12:19.183415 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4440 12:12:19.186891 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4441 12:12:19.190298 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4442 12:12:19.193622 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4443 12:12:19.196738 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4444 12:12:19.197161
4445 12:12:19.200107 CA PerBit enable=1, Macro0, CA PI delay=33
4446 12:12:19.200534
4447 12:12:19.203551 [CBTSetCACLKResult] CA Dly = 33
4448 12:12:19.203977 CS Dly: 5 (0~36)
4449 12:12:19.206731 ==
4450 12:12:19.210074 Dram Type= 6, Freq= 0, CH_1, rank 1
4451 12:12:19.213255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 12:12:19.213735 ==
4453 12:12:19.216739 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4454 12:12:19.223315 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4455 12:12:19.227263 [CA 0] Center 35 (5~66) winsize 62
4456 12:12:19.230637 [CA 1] Center 36 (6~67) winsize 62
4457 12:12:19.233677 [CA 2] Center 34 (4~65) winsize 62
4458 12:12:19.237258 [CA 3] Center 34 (3~65) winsize 63
4459 12:12:19.240538 [CA 4] Center 34 (4~65) winsize 62
4460 12:12:19.243951 [CA 5] Center 33 (3~64) winsize 62
4461 12:12:19.244367
4462 12:12:19.247203 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4463 12:12:19.247627
4464 12:12:19.250484 [CATrainingPosCal] consider 2 rank data
4465 12:12:19.253602 u2DelayCellTimex100 = 270/100 ps
4466 12:12:19.256874 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4467 12:12:19.263844 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4468 12:12:19.266929 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4469 12:12:19.270438 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4470 12:12:19.273546 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4471 12:12:19.276985 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4472 12:12:19.277405
4473 12:12:19.280384 CA PerBit enable=1, Macro0, CA PI delay=33
4474 12:12:19.281005
4475 12:12:19.283476 [CBTSetCACLKResult] CA Dly = 33
4476 12:12:19.283899 CS Dly: 5 (0~36)
4477 12:12:19.286964
4478 12:12:19.290210 ----->DramcWriteLeveling(PI) begin...
4479 12:12:19.290658 ==
4480 12:12:19.293392 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 12:12:19.296758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 12:12:19.297230 ==
4483 12:12:19.299999 Write leveling (Byte 0): 29 => 29
4484 12:12:19.303270 Write leveling (Byte 1): 30 => 30
4485 12:12:19.306671 DramcWriteLeveling(PI) end<-----
4486 12:12:19.307092
4487 12:12:19.307429 ==
4488 12:12:19.310105 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 12:12:19.313175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 12:12:19.313635 ==
4491 12:12:19.316370 [Gating] SW mode calibration
4492 12:12:19.323353 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4493 12:12:19.329671 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4494 12:12:19.332996 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4495 12:12:19.336430 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4496 12:12:19.342981 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4497 12:12:19.346269 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 0) (1 0)
4498 12:12:19.349773 0 9 16 | B1->B0 | 2b2b 2b2b | 1 1 | (1 0) (1 0)
4499 12:12:19.356410 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 12:12:19.359441 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4501 12:12:19.362744 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 12:12:19.369452 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 12:12:19.372737 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 12:12:19.375935 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4505 12:12:19.382803 0 10 12 | B1->B0 | 2c2c 3232 | 1 1 | (0 0) (0 0)
4506 12:12:19.386002 0 10 16 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
4507 12:12:19.389567 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 12:12:19.395828 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 12:12:19.399217 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 12:12:19.402493 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 12:12:19.406021 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 12:12:19.412673 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 12:12:19.415932 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4514 12:12:19.419417 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4515 12:12:19.425860 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 12:12:19.428921 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 12:12:19.432474 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 12:12:19.439227 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 12:12:19.442740 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 12:12:19.445991 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 12:12:19.452513 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 12:12:19.455621 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 12:12:19.459117 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 12:12:19.465822 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 12:12:19.468976 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 12:12:19.472197 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 12:12:19.478659 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 12:12:19.482221 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 12:12:19.485417 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4530 12:12:19.492242 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4531 12:12:19.495367 Total UI for P1: 0, mck2ui 16
4532 12:12:19.498914 best dqsien dly found for B1: ( 0, 13, 12)
4533 12:12:19.502318 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4534 12:12:19.505520 Total UI for P1: 0, mck2ui 16
4535 12:12:19.508880 best dqsien dly found for B0: ( 0, 13, 16)
4536 12:12:19.511981 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4537 12:12:19.515512 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4538 12:12:19.515931
4539 12:12:19.518510 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4540 12:12:19.522090 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4541 12:12:19.525458 [Gating] SW calibration Done
4542 12:12:19.525978 ==
4543 12:12:19.528920 Dram Type= 6, Freq= 0, CH_1, rank 0
4544 12:12:19.535105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4545 12:12:19.535528 ==
4546 12:12:19.535887 RX Vref Scan: 0
4547 12:12:19.536206
4548 12:12:19.538896 RX Vref 0 -> 0, step: 1
4549 12:12:19.539467
4550 12:12:19.541769 RX Delay -230 -> 252, step: 16
4551 12:12:19.545265 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4552 12:12:19.548504 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4553 12:12:19.551586 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4554 12:12:19.558167 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4555 12:12:19.561652 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4556 12:12:19.564807 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4557 12:12:19.568340 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4558 12:12:19.574985 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4559 12:12:19.578422 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4560 12:12:19.581697 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4561 12:12:19.584778 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4562 12:12:19.588436 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4563 12:12:19.594792 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4564 12:12:19.598287 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4565 12:12:19.601408 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4566 12:12:19.604886 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4567 12:12:19.608005 ==
4568 12:12:19.611483 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 12:12:19.614665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 12:12:19.615089 ==
4571 12:12:19.615428 DQS Delay:
4572 12:12:19.618217 DQS0 = 0, DQS1 = 0
4573 12:12:19.618642 DQM Delay:
4574 12:12:19.621272 DQM0 = 39, DQM1 = 30
4575 12:12:19.621743 DQ Delay:
4576 12:12:19.624727 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4577 12:12:19.627871 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4578 12:12:19.631460 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4579 12:12:19.634608 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4580 12:12:19.635024
4581 12:12:19.635353
4582 12:12:19.635664 ==
4583 12:12:19.637825 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 12:12:19.641231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 12:12:19.641699 ==
4586 12:12:19.642056
4587 12:12:19.642368
4588 12:12:19.644450 TX Vref Scan disable
4589 12:12:19.649322 == TX Byte 0 ==
4590 12:12:19.651640 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4591 12:12:19.654501 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4592 12:12:19.657877 == TX Byte 1 ==
4593 12:12:19.661169 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4594 12:12:19.664583 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4595 12:12:19.665010 ==
4596 12:12:19.667720 Dram Type= 6, Freq= 0, CH_1, rank 0
4597 12:12:19.674388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 12:12:19.674818 ==
4599 12:12:19.675162
4600 12:12:19.675478
4601 12:12:19.675781 TX Vref Scan disable
4602 12:12:19.678672 == TX Byte 0 ==
4603 12:12:19.682030 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4604 12:12:19.688684 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4605 12:12:19.689102 == TX Byte 1 ==
4606 12:12:19.691831 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4607 12:12:19.698340 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4608 12:12:19.698760
4609 12:12:19.699092 [DATLAT]
4610 12:12:19.699403 Freq=600, CH1 RK0
4611 12:12:19.699703
4612 12:12:19.701915 DATLAT Default: 0x9
4613 12:12:19.702336 0, 0xFFFF, sum = 0
4614 12:12:19.705017 1, 0xFFFF, sum = 0
4615 12:12:19.708544 2, 0xFFFF, sum = 0
4616 12:12:19.708978 3, 0xFFFF, sum = 0
4617 12:12:19.711663 4, 0xFFFF, sum = 0
4618 12:12:19.712098 5, 0xFFFF, sum = 0
4619 12:12:19.714868 6, 0xFFFF, sum = 0
4620 12:12:19.715301 7, 0xFFFF, sum = 0
4621 12:12:19.718507 8, 0x0, sum = 1
4622 12:12:19.718941 9, 0x0, sum = 2
4623 12:12:19.719286 10, 0x0, sum = 3
4624 12:12:19.721712 11, 0x0, sum = 4
4625 12:12:19.722145 best_step = 9
4626 12:12:19.722488
4627 12:12:19.722805 ==
4628 12:12:19.725105 Dram Type= 6, Freq= 0, CH_1, rank 0
4629 12:12:19.731846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4630 12:12:19.732445 ==
4631 12:12:19.732797 RX Vref Scan: 1
4632 12:12:19.733118
4633 12:12:19.734889 RX Vref 0 -> 0, step: 1
4634 12:12:19.735317
4635 12:12:19.738149 RX Delay -195 -> 252, step: 8
4636 12:12:19.738576
4637 12:12:19.741636 Set Vref, RX VrefLevel [Byte0]: 57
4638 12:12:19.744987 [Byte1]: 50
4639 12:12:19.745414
4640 12:12:19.748180 Final RX Vref Byte 0 = 57 to rank0
4641 12:12:19.751407 Final RX Vref Byte 1 = 50 to rank0
4642 12:12:19.754805 Final RX Vref Byte 0 = 57 to rank1
4643 12:12:19.758121 Final RX Vref Byte 1 = 50 to rank1==
4644 12:12:19.761356 Dram Type= 6, Freq= 0, CH_1, rank 0
4645 12:12:19.764663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 12:12:19.765217 ==
4647 12:12:19.768468 DQS Delay:
4648 12:12:19.769019 DQS0 = 0, DQS1 = 0
4649 12:12:19.771803 DQM Delay:
4650 12:12:19.772330 DQM0 = 39, DQM1 = 28
4651 12:12:19.772672 DQ Delay:
4652 12:12:19.774516 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4653 12:12:19.777768 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4654 12:12:19.781632 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4655 12:12:19.784466 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4656 12:12:19.784895
4657 12:12:19.785231
4658 12:12:19.794778 [DQSOSCAuto] RK0, (LSB)MR18= 0x2532, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
4659 12:12:19.798170 CH1 RK0: MR19=808, MR18=2532
4660 12:12:19.804692 CH1_RK0: MR19=0x808, MR18=0x2532, DQSOSC=400, MR23=63, INC=163, DEC=109
4661 12:12:19.805122
4662 12:12:19.807864 ----->DramcWriteLeveling(PI) begin...
4663 12:12:19.808305 ==
4664 12:12:19.811023 Dram Type= 6, Freq= 0, CH_1, rank 1
4665 12:12:19.814677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 12:12:19.815204 ==
4667 12:12:19.817873 Write leveling (Byte 0): 29 => 29
4668 12:12:19.821019 Write leveling (Byte 1): 29 => 29
4669 12:12:19.824460 DramcWriteLeveling(PI) end<-----
4670 12:12:19.824990
4671 12:12:19.825334 ==
4672 12:12:19.828119 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 12:12:19.831214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 12:12:19.831747 ==
4675 12:12:19.834407 [Gating] SW mode calibration
4676 12:12:19.841202 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4677 12:12:19.847926 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4678 12:12:19.851088 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4679 12:12:19.854333 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4680 12:12:19.861133 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4681 12:12:19.864401 0 9 12 | B1->B0 | 3131 2e2e | 0 0 | (1 1) (1 1)
4682 12:12:19.867362 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4683 12:12:19.874184 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 12:12:19.877623 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 12:12:19.881143 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4686 12:12:19.887457 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4687 12:12:19.890730 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4688 12:12:19.893963 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4689 12:12:19.901050 0 10 12 | B1->B0 | 3333 3939 | 1 1 | (0 0) (0 0)
4690 12:12:19.904182 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4691 12:12:19.907462 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 12:12:19.913914 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 12:12:19.917404 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 12:12:19.920552 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 12:12:19.924100 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4696 12:12:19.930464 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4697 12:12:19.934034 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4698 12:12:19.936944 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 12:12:19.943833 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 12:12:19.946884 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 12:12:19.950461 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 12:12:19.956844 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 12:12:19.960452 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 12:12:19.963576 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 12:12:19.970229 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 12:12:19.973628 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 12:12:19.976733 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 12:12:19.983367 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 12:12:19.986772 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 12:12:19.989928 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 12:12:19.996687 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 12:12:20.000140 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 12:12:20.003066 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4714 12:12:20.009769 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4715 12:12:20.013063 Total UI for P1: 0, mck2ui 16
4716 12:12:20.016542 best dqsien dly found for B0: ( 0, 13, 12)
4717 12:12:20.019782 Total UI for P1: 0, mck2ui 16
4718 12:12:20.023249 best dqsien dly found for B1: ( 0, 13, 12)
4719 12:12:20.026854 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4720 12:12:20.029713 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4721 12:12:20.030134
4722 12:12:20.032952 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4723 12:12:20.036656 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4724 12:12:20.039583 [Gating] SW calibration Done
4725 12:12:20.040004 ==
4726 12:12:20.043192 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 12:12:20.046315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 12:12:20.046739 ==
4729 12:12:20.049856 RX Vref Scan: 0
4730 12:12:20.050275
4731 12:12:20.053019 RX Vref 0 -> 0, step: 1
4732 12:12:20.053438
4733 12:12:20.053831 RX Delay -230 -> 252, step: 16
4734 12:12:20.059719 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4735 12:12:20.062776 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4736 12:12:20.066349 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4737 12:12:20.069638 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4738 12:12:20.076324 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4739 12:12:20.079238 iDelay=218, Bit 5, Center 41 (-134 ~ 217) 352
4740 12:12:20.082749 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4741 12:12:20.086204 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4742 12:12:20.089507 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4743 12:12:20.096318 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4744 12:12:20.099357 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4745 12:12:20.102759 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4746 12:12:20.106277 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4747 12:12:20.112661 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4748 12:12:20.115994 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4749 12:12:20.119434 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4750 12:12:20.119872 ==
4751 12:12:20.122883 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 12:12:20.126181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 12:12:20.129572 ==
4754 12:12:20.130089 DQS Delay:
4755 12:12:20.130429 DQS0 = 0, DQS1 = 0
4756 12:12:20.132879 DQM Delay:
4757 12:12:20.133299 DQM0 = 33, DQM1 = 28
4758 12:12:20.135879 DQ Delay:
4759 12:12:20.136297 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4760 12:12:20.139258 DQ4 =33, DQ5 =41, DQ6 =41, DQ7 =33
4761 12:12:20.142502 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4762 12:12:20.145775 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4763 12:12:20.146195
4764 12:12:20.149073
4765 12:12:20.149542 ==
4766 12:12:20.152386 Dram Type= 6, Freq= 0, CH_1, rank 1
4767 12:12:20.156275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4768 12:12:20.156871 ==
4769 12:12:20.157426
4770 12:12:20.158033
4771 12:12:20.159066 TX Vref Scan disable
4772 12:12:20.159532 == TX Byte 0 ==
4773 12:12:20.165916 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4774 12:12:20.169035 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4775 12:12:20.169461 == TX Byte 1 ==
4776 12:12:20.175747 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4777 12:12:20.178826 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4778 12:12:20.179253 ==
4779 12:12:20.182317 Dram Type= 6, Freq= 0, CH_1, rank 1
4780 12:12:20.185276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4781 12:12:20.185741 ==
4782 12:12:20.186081
4783 12:12:20.186392
4784 12:12:20.188910 TX Vref Scan disable
4785 12:12:20.192278 == TX Byte 0 ==
4786 12:12:20.195314 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4787 12:12:20.201921 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4788 12:12:20.202346 == TX Byte 1 ==
4789 12:12:20.205043 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4790 12:12:20.211918 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4791 12:12:20.212345
4792 12:12:20.212681 [DATLAT]
4793 12:12:20.212996 Freq=600, CH1 RK1
4794 12:12:20.213304
4795 12:12:20.215187 DATLAT Default: 0x9
4796 12:12:20.215773 0, 0xFFFF, sum = 0
4797 12:12:20.218568 1, 0xFFFF, sum = 0
4798 12:12:20.219008 2, 0xFFFF, sum = 0
4799 12:12:20.221731 3, 0xFFFF, sum = 0
4800 12:12:20.224748 4, 0xFFFF, sum = 0
4801 12:12:20.225175 5, 0xFFFF, sum = 0
4802 12:12:20.228038 6, 0xFFFF, sum = 0
4803 12:12:20.228469 7, 0xFFFF, sum = 0
4804 12:12:20.231766 8, 0x0, sum = 1
4805 12:12:20.232195 9, 0x0, sum = 2
4806 12:12:20.232545 10, 0x0, sum = 3
4807 12:12:20.234736 11, 0x0, sum = 4
4808 12:12:20.235168 best_step = 9
4809 12:12:20.235505
4810 12:12:20.238444 ==
4811 12:12:20.238947 Dram Type= 6, Freq= 0, CH_1, rank 1
4812 12:12:20.244813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4813 12:12:20.245245 ==
4814 12:12:20.245635 RX Vref Scan: 0
4815 12:12:20.245963
4816 12:12:20.248330 RX Vref 0 -> 0, step: 1
4817 12:12:20.248752
4818 12:12:20.251357 RX Delay -195 -> 252, step: 8
4819 12:12:20.257833 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4820 12:12:20.261198 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4821 12:12:20.264377 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4822 12:12:20.267796 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4823 12:12:20.271075 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4824 12:12:20.277811 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4825 12:12:20.281127 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4826 12:12:20.284522 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4827 12:12:20.287743 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4828 12:12:20.294397 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4829 12:12:20.297627 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4830 12:12:20.301100 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4831 12:12:20.304345 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4832 12:12:20.310925 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4833 12:12:20.314196 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4834 12:12:20.317426 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4835 12:12:20.317896 ==
4836 12:12:20.320705 Dram Type= 6, Freq= 0, CH_1, rank 1
4837 12:12:20.323884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4838 12:12:20.327286 ==
4839 12:12:20.327714 DQS Delay:
4840 12:12:20.328055 DQS0 = 0, DQS1 = 0
4841 12:12:20.330835 DQM Delay:
4842 12:12:20.331264 DQM0 = 36, DQM1 = 30
4843 12:12:20.334155 DQ Delay:
4844 12:12:20.334583 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4845 12:12:20.337175 DQ4 =32, DQ5 =48, DQ6 =48, DQ7 =32
4846 12:12:20.340502 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4847 12:12:20.343864 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =36
4848 12:12:20.344288
4849 12:12:20.347047
4850 12:12:20.353810 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a5a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4851 12:12:20.356811 CH1 RK1: MR19=808, MR18=3A5A
4852 12:12:20.363466 CH1_RK1: MR19=0x808, MR18=0x3A5A, DQSOSC=392, MR23=63, INC=170, DEC=113
4853 12:12:20.366975 [RxdqsGatingPostProcess] freq 600
4854 12:12:20.370104 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4855 12:12:20.373601 Pre-setting of DQS Precalculation
4856 12:12:20.380149 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4857 12:12:20.386669 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4858 12:12:20.393187 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4859 12:12:20.393651
4860 12:12:20.393998
4861 12:12:20.396614 [Calibration Summary] 1200 Mbps
4862 12:12:20.397043 CH 0, Rank 0
4863 12:12:20.399628 SW Impedance : PASS
4864 12:12:20.403426 DUTY Scan : NO K
4865 12:12:20.403854 ZQ Calibration : PASS
4866 12:12:20.406455 Jitter Meter : NO K
4867 12:12:20.409710 CBT Training : PASS
4868 12:12:20.410137 Write leveling : PASS
4869 12:12:20.413194 RX DQS gating : PASS
4870 12:12:20.416368 RX DQ/DQS(RDDQC) : PASS
4871 12:12:20.416797 TX DQ/DQS : PASS
4872 12:12:20.419723 RX DATLAT : PASS
4873 12:12:20.420153 RX DQ/DQS(Engine): PASS
4874 12:12:20.423148 TX OE : NO K
4875 12:12:20.423579 All Pass.
4876 12:12:20.423924
4877 12:12:20.426389 CH 0, Rank 1
4878 12:12:20.426816 SW Impedance : PASS
4879 12:12:20.429583 DUTY Scan : NO K
4880 12:12:20.432977 ZQ Calibration : PASS
4881 12:12:20.433404 Jitter Meter : NO K
4882 12:12:20.436159 CBT Training : PASS
4883 12:12:20.439748 Write leveling : PASS
4884 12:12:20.440188 RX DQS gating : PASS
4885 12:12:20.442741 RX DQ/DQS(RDDQC) : PASS
4886 12:12:20.446223 TX DQ/DQS : PASS
4887 12:12:20.446654 RX DATLAT : PASS
4888 12:12:20.449312 RX DQ/DQS(Engine): PASS
4889 12:12:20.452755 TX OE : NO K
4890 12:12:20.453185 All Pass.
4891 12:12:20.453723
4892 12:12:20.454061 CH 1, Rank 0
4893 12:12:20.456102 SW Impedance : PASS
4894 12:12:20.459429 DUTY Scan : NO K
4895 12:12:20.459889 ZQ Calibration : PASS
4896 12:12:20.462755 Jitter Meter : NO K
4897 12:12:20.465860 CBT Training : PASS
4898 12:12:20.466285 Write leveling : PASS
4899 12:12:20.469394 RX DQS gating : PASS
4900 12:12:20.472476 RX DQ/DQS(RDDQC) : PASS
4901 12:12:20.472904 TX DQ/DQS : PASS
4902 12:12:20.475914 RX DATLAT : PASS
4903 12:12:20.479434 RX DQ/DQS(Engine): PASS
4904 12:12:20.479860 TX OE : NO K
4905 12:12:20.480205 All Pass.
4906 12:12:20.482622
4907 12:12:20.483047 CH 1, Rank 1
4908 12:12:20.485965 SW Impedance : PASS
4909 12:12:20.486566 DUTY Scan : NO K
4910 12:12:20.488923 ZQ Calibration : PASS
4911 12:12:20.492454 Jitter Meter : NO K
4912 12:12:20.492877 CBT Training : PASS
4913 12:12:20.495796 Write leveling : PASS
4914 12:12:20.496222 RX DQS gating : PASS
4915 12:12:20.499160 RX DQ/DQS(RDDQC) : PASS
4916 12:12:20.502359 TX DQ/DQS : PASS
4917 12:12:20.502782 RX DATLAT : PASS
4918 12:12:20.505961 RX DQ/DQS(Engine): PASS
4919 12:12:20.508941 TX OE : NO K
4920 12:12:20.509362 All Pass.
4921 12:12:20.509759
4922 12:12:20.512538 DramC Write-DBI off
4923 12:12:20.512957 PER_BANK_REFRESH: Hybrid Mode
4924 12:12:20.515654 TX_TRACKING: ON
4925 12:12:20.522276 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4926 12:12:20.528820 [FAST_K] Save calibration result to emmc
4927 12:12:20.531936 dramc_set_vcore_voltage set vcore to 662500
4928 12:12:20.532362 Read voltage for 933, 3
4929 12:12:20.535451 Vio18 = 0
4930 12:12:20.535874 Vcore = 662500
4931 12:12:20.536207 Vdram = 0
4932 12:12:20.538581 Vddq = 0
4933 12:12:20.539005 Vmddr = 0
4934 12:12:20.542086 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4935 12:12:20.548816 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4936 12:12:20.551899 MEM_TYPE=3, freq_sel=17
4937 12:12:20.555106 sv_algorithm_assistance_LP4_1600
4938 12:12:20.558596 ============ PULL DRAM RESETB DOWN ============
4939 12:12:20.562007 ========== PULL DRAM RESETB DOWN end =========
4940 12:12:20.568602 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4941 12:12:20.571949 ===================================
4942 12:12:20.572643 LPDDR4 DRAM CONFIGURATION
4943 12:12:20.575108 ===================================
4944 12:12:20.578484 EX_ROW_EN[0] = 0x0
4945 12:12:20.578908 EX_ROW_EN[1] = 0x0
4946 12:12:20.581631 LP4Y_EN = 0x0
4947 12:12:20.582058 WORK_FSP = 0x0
4948 12:12:20.585216 WL = 0x3
4949 12:12:20.588414 RL = 0x3
4950 12:12:20.588834 BL = 0x2
4951 12:12:20.591656 RPST = 0x0
4952 12:12:20.592114 RD_PRE = 0x0
4953 12:12:20.594990 WR_PRE = 0x1
4954 12:12:20.595413 WR_PST = 0x0
4955 12:12:20.598122 DBI_WR = 0x0
4956 12:12:20.598595 DBI_RD = 0x0
4957 12:12:20.601432 OTF = 0x1
4958 12:12:20.604681 ===================================
4959 12:12:20.607918 ===================================
4960 12:12:20.608413 ANA top config
4961 12:12:20.611425 ===================================
4962 12:12:20.614698 DLL_ASYNC_EN = 0
4963 12:12:20.618148 ALL_SLAVE_EN = 1
4964 12:12:20.618624 NEW_RANK_MODE = 1
4965 12:12:20.621217 DLL_IDLE_MODE = 1
4966 12:12:20.624712 LP45_APHY_COMB_EN = 1
4967 12:12:20.628043 TX_ODT_DIS = 1
4968 12:12:20.631350 NEW_8X_MODE = 1
4969 12:12:20.634452 ===================================
4970 12:12:20.638002 ===================================
4971 12:12:20.638563 data_rate = 1866
4972 12:12:20.641149 CKR = 1
4973 12:12:20.644441 DQ_P2S_RATIO = 8
4974 12:12:20.648004 ===================================
4975 12:12:20.651191 CA_P2S_RATIO = 8
4976 12:12:20.654683 DQ_CA_OPEN = 0
4977 12:12:20.657701 DQ_SEMI_OPEN = 0
4978 12:12:20.658125 CA_SEMI_OPEN = 0
4979 12:12:20.661203 CA_FULL_RATE = 0
4980 12:12:20.664231 DQ_CKDIV4_EN = 1
4981 12:12:20.667793 CA_CKDIV4_EN = 1
4982 12:12:20.670933 CA_PREDIV_EN = 0
4983 12:12:20.674310 PH8_DLY = 0
4984 12:12:20.674868 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4985 12:12:20.677980 DQ_AAMCK_DIV = 4
4986 12:12:20.681223 CA_AAMCK_DIV = 4
4987 12:12:20.684239 CA_ADMCK_DIV = 4
4988 12:12:20.687795 DQ_TRACK_CA_EN = 0
4989 12:12:20.690837 CA_PICK = 933
4990 12:12:20.694269 CA_MCKIO = 933
4991 12:12:20.694695 MCKIO_SEMI = 0
4992 12:12:20.697407 PLL_FREQ = 3732
4993 12:12:20.700722 DQ_UI_PI_RATIO = 32
4994 12:12:20.704115 CA_UI_PI_RATIO = 0
4995 12:12:20.707404 ===================================
4996 12:12:20.710851 ===================================
4997 12:12:20.714147 memory_type:LPDDR4
4998 12:12:20.714635 GP_NUM : 10
4999 12:12:20.717016 SRAM_EN : 1
5000 12:12:20.720528 MD32_EN : 0
5001 12:12:20.724107 ===================================
5002 12:12:20.724700 [ANA_INIT] >>>>>>>>>>>>>>
5003 12:12:20.727522 <<<<<< [CONFIGURE PHASE]: ANA_TX
5004 12:12:20.730532 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5005 12:12:20.734107 ===================================
5006 12:12:20.737389 data_rate = 1866,PCW = 0X8f00
5007 12:12:20.740807 ===================================
5008 12:12:20.743884 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5009 12:12:20.750595 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5010 12:12:20.753988 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5011 12:12:20.760469 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5012 12:12:20.764289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5013 12:12:20.767237 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5014 12:12:20.767669 [ANA_INIT] flow start
5015 12:12:20.770706 [ANA_INIT] PLL >>>>>>>>
5016 12:12:20.773722 [ANA_INIT] PLL <<<<<<<<
5017 12:12:20.774147 [ANA_INIT] MIDPI >>>>>>>>
5018 12:12:20.777146 [ANA_INIT] MIDPI <<<<<<<<
5019 12:12:20.780458 [ANA_INIT] DLL >>>>>>>>
5020 12:12:20.780882 [ANA_INIT] flow end
5021 12:12:20.787138 ============ LP4 DIFF to SE enter ============
5022 12:12:20.790364 ============ LP4 DIFF to SE exit ============
5023 12:12:20.793711 [ANA_INIT] <<<<<<<<<<<<<
5024 12:12:20.797206 [Flow] Enable top DCM control >>>>>
5025 12:12:20.800291 [Flow] Enable top DCM control <<<<<
5026 12:12:20.800775 Enable DLL master slave shuffle
5027 12:12:20.807204 ==============================================================
5028 12:12:20.810297 Gating Mode config
5029 12:12:20.813957 ==============================================================
5030 12:12:20.816811 Config description:
5031 12:12:20.826911 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5032 12:12:20.833394 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5033 12:12:20.836734 SELPH_MODE 0: By rank 1: By Phase
5034 12:12:20.843328 ==============================================================
5035 12:12:20.846779 GAT_TRACK_EN = 1
5036 12:12:20.850118 RX_GATING_MODE = 2
5037 12:12:20.853340 RX_GATING_TRACK_MODE = 2
5038 12:12:20.856650 SELPH_MODE = 1
5039 12:12:20.860162 PICG_EARLY_EN = 1
5040 12:12:20.860586 VALID_LAT_VALUE = 1
5041 12:12:20.866481 ==============================================================
5042 12:12:20.870023 Enter into Gating configuration >>>>
5043 12:12:20.873086 Exit from Gating configuration <<<<
5044 12:12:20.876587 Enter into DVFS_PRE_config >>>>>
5045 12:12:20.886245 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5046 12:12:20.889417 Exit from DVFS_PRE_config <<<<<
5047 12:12:20.893076 Enter into PICG configuration >>>>
5048 12:12:20.896515 Exit from PICG configuration <<<<
5049 12:12:20.899655 [RX_INPUT] configuration >>>>>
5050 12:12:20.902718 [RX_INPUT] configuration <<<<<
5051 12:12:20.909514 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5052 12:12:20.912621 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5053 12:12:20.919640 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5054 12:12:20.926000 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5055 12:12:20.932621 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5056 12:12:20.939433 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5057 12:12:20.942642 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5058 12:12:20.945956 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5059 12:12:20.949175 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5060 12:12:20.956045 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5061 12:12:20.959315 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5062 12:12:20.962406 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5063 12:12:20.965978 ===================================
5064 12:12:20.969322 LPDDR4 DRAM CONFIGURATION
5065 12:12:20.972322 ===================================
5066 12:12:20.972748 EX_ROW_EN[0] = 0x0
5067 12:12:20.975708 EX_ROW_EN[1] = 0x0
5068 12:12:20.979129 LP4Y_EN = 0x0
5069 12:12:20.979549 WORK_FSP = 0x0
5070 12:12:20.982127 WL = 0x3
5071 12:12:20.982597 RL = 0x3
5072 12:12:20.985566 BL = 0x2
5073 12:12:20.985993 RPST = 0x0
5074 12:12:20.988860 RD_PRE = 0x0
5075 12:12:20.989323 WR_PRE = 0x1
5076 12:12:20.992554 WR_PST = 0x0
5077 12:12:20.992978 DBI_WR = 0x0
5078 12:12:20.995680 DBI_RD = 0x0
5079 12:12:20.996102 OTF = 0x1
5080 12:12:20.998760 ===================================
5081 12:12:21.002246 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5082 12:12:21.008923 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5083 12:12:21.012388 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5084 12:12:21.015666 ===================================
5085 12:12:21.019149 LPDDR4 DRAM CONFIGURATION
5086 12:12:21.022142 ===================================
5087 12:12:21.022567 EX_ROW_EN[0] = 0x10
5088 12:12:21.025688 EX_ROW_EN[1] = 0x0
5089 12:12:21.026113 LP4Y_EN = 0x0
5090 12:12:21.028905 WORK_FSP = 0x0
5091 12:12:21.032437 WL = 0x3
5092 12:12:21.032859 RL = 0x3
5093 12:12:21.035520 BL = 0x2
5094 12:12:21.035944 RPST = 0x0
5095 12:12:21.038666 RD_PRE = 0x0
5096 12:12:21.039088 WR_PRE = 0x1
5097 12:12:21.042091 WR_PST = 0x0
5098 12:12:21.042535 DBI_WR = 0x0
5099 12:12:21.045311 DBI_RD = 0x0
5100 12:12:21.045756 OTF = 0x1
5101 12:12:21.048784 ===================================
5102 12:12:21.055064 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5103 12:12:21.059410 nWR fixed to 30
5104 12:12:21.062693 [ModeRegInit_LP4] CH0 RK0
5105 12:12:21.063113 [ModeRegInit_LP4] CH0 RK1
5106 12:12:21.065933 [ModeRegInit_LP4] CH1 RK0
5107 12:12:21.069307 [ModeRegInit_LP4] CH1 RK1
5108 12:12:21.069770 match AC timing 9
5109 12:12:21.075818 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5110 12:12:21.079512 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5111 12:12:21.082843 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5112 12:12:21.089344 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5113 12:12:21.092502 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5114 12:12:21.092925 ==
5115 12:12:21.095770 Dram Type= 6, Freq= 0, CH_0, rank 0
5116 12:12:21.099094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5117 12:12:21.099521 ==
5118 12:12:21.106012 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5119 12:12:21.112716 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5120 12:12:21.115859 [CA 0] Center 38 (7~69) winsize 63
5121 12:12:21.119370 [CA 1] Center 38 (8~69) winsize 62
5122 12:12:21.122478 [CA 2] Center 35 (5~66) winsize 62
5123 12:12:21.125972 [CA 3] Center 34 (4~65) winsize 62
5124 12:12:21.129257 [CA 4] Center 34 (4~65) winsize 62
5125 12:12:21.132551 [CA 5] Center 33 (3~64) winsize 62
5126 12:12:21.132975
5127 12:12:21.136024 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5128 12:12:21.136450
5129 12:12:21.139201 [CATrainingPosCal] consider 1 rank data
5130 12:12:21.142687 u2DelayCellTimex100 = 270/100 ps
5131 12:12:21.145866 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5132 12:12:21.149040 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5133 12:12:21.152523 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5134 12:12:21.155771 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5135 12:12:21.159225 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5136 12:12:21.162548 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5137 12:12:21.166009
5138 12:12:21.169253 CA PerBit enable=1, Macro0, CA PI delay=33
5139 12:12:21.169717
5140 12:12:21.172486 [CBTSetCACLKResult] CA Dly = 33
5141 12:12:21.172912 CS Dly: 7 (0~38)
5142 12:12:21.173253 ==
5143 12:12:21.175872 Dram Type= 6, Freq= 0, CH_0, rank 1
5144 12:12:21.178916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5145 12:12:21.179343 ==
5146 12:12:21.185726 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5147 12:12:21.192050 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5148 12:12:21.195439 [CA 0] Center 38 (8~69) winsize 62
5149 12:12:21.198717 [CA 1] Center 38 (7~69) winsize 63
5150 12:12:21.202032 [CA 2] Center 35 (5~66) winsize 62
5151 12:12:21.205443 [CA 3] Center 35 (5~66) winsize 62
5152 12:12:21.208659 [CA 4] Center 34 (3~65) winsize 63
5153 12:12:21.212109 [CA 5] Center 33 (3~64) winsize 62
5154 12:12:21.212531
5155 12:12:21.215530 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5156 12:12:21.215955
5157 12:12:21.218647 [CATrainingPosCal] consider 2 rank data
5158 12:12:21.221968 u2DelayCellTimex100 = 270/100 ps
5159 12:12:21.225602 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5160 12:12:21.228879 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5161 12:12:21.231814 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5162 12:12:21.235393 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5163 12:12:21.242187 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5164 12:12:21.245267 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5165 12:12:21.245718
5166 12:12:21.248439 CA PerBit enable=1, Macro0, CA PI delay=33
5167 12:12:21.248861
5168 12:12:21.252070 [CBTSetCACLKResult] CA Dly = 33
5169 12:12:21.252497 CS Dly: 7 (0~38)
5170 12:12:21.252835
5171 12:12:21.255184 ----->DramcWriteLeveling(PI) begin...
5172 12:12:21.255613 ==
5173 12:12:21.258592 Dram Type= 6, Freq= 0, CH_0, rank 0
5174 12:12:21.265254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 12:12:21.265716 ==
5176 12:12:21.268695 Write leveling (Byte 0): 30 => 30
5177 12:12:21.271694 Write leveling (Byte 1): 29 => 29
5178 12:12:21.272118 DramcWriteLeveling(PI) end<-----
5179 12:12:21.272457
5180 12:12:21.275052 ==
5181 12:12:21.278319 Dram Type= 6, Freq= 0, CH_0, rank 0
5182 12:12:21.281778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5183 12:12:21.282236 ==
5184 12:12:21.285249 [Gating] SW mode calibration
5185 12:12:21.291682 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5186 12:12:21.295091 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5187 12:12:21.301812 0 14 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
5188 12:12:21.304915 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
5189 12:12:21.308472 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 12:12:21.315148 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 12:12:21.318251 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5192 12:12:21.321625 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5193 12:12:21.328290 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5194 12:12:21.331499 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5195 12:12:21.334816 0 15 0 | B1->B0 | 3333 2d2d | 0 0 | (0 1) (1 1)
5196 12:12:21.341247 0 15 4 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5197 12:12:21.344738 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 12:12:21.348266 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 12:12:21.354494 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5200 12:12:21.357751 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5201 12:12:21.361210 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5202 12:12:21.367804 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5203 12:12:21.371165 1 0 0 | B1->B0 | 2727 3a3a | 0 0 | (0 0) (0 0)
5204 12:12:21.374748 1 0 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5205 12:12:21.381097 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 12:12:21.384547 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 12:12:21.387826 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 12:12:21.394504 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 12:12:21.397562 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 12:12:21.401102 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5211 12:12:21.407420 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5212 12:12:21.410842 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5213 12:12:21.414194 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 12:12:21.420805 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 12:12:21.424070 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 12:12:21.427382 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 12:12:21.434186 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 12:12:21.437283 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 12:12:21.440803 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 12:12:21.443929 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 12:12:21.450636 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 12:12:21.454071 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 12:12:21.457110 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 12:12:21.463897 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 12:12:21.467414 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 12:12:21.470702 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5227 12:12:21.477826 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5228 12:12:21.480519 Total UI for P1: 0, mck2ui 16
5229 12:12:21.483820 best dqsien dly found for B0: ( 1, 2, 28)
5230 12:12:21.487028 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5231 12:12:21.490343 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5232 12:12:21.493796 Total UI for P1: 0, mck2ui 16
5233 12:12:21.496856 best dqsien dly found for B1: ( 1, 3, 2)
5234 12:12:21.500417 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5235 12:12:21.503698 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5236 12:12:21.504122
5237 12:12:21.510562 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5238 12:12:21.513718 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5239 12:12:21.514142 [Gating] SW calibration Done
5240 12:12:21.516990 ==
5241 12:12:21.520520 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 12:12:21.523424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 12:12:21.523850 ==
5244 12:12:21.524186 RX Vref Scan: 0
5245 12:12:21.524500
5246 12:12:21.527043 RX Vref 0 -> 0, step: 1
5247 12:12:21.527465
5248 12:12:21.530083 RX Delay -80 -> 252, step: 8
5249 12:12:21.533383 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5250 12:12:21.537016 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5251 12:12:21.540147 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5252 12:12:21.546767 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5253 12:12:21.549909 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5254 12:12:21.553296 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5255 12:12:21.556247 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5256 12:12:21.559820 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5257 12:12:21.563385 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5258 12:12:21.569866 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5259 12:12:21.573425 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5260 12:12:21.576498 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5261 12:12:21.579708 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5262 12:12:21.586204 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5263 12:12:21.589864 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5264 12:12:21.592960 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5265 12:12:21.593442 ==
5266 12:12:21.596178 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 12:12:21.599735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 12:12:21.600162 ==
5269 12:12:21.603167 DQS Delay:
5270 12:12:21.603629 DQS0 = 0, DQS1 = 0
5271 12:12:21.606544 DQM Delay:
5272 12:12:21.606963 DQM0 = 96, DQM1 = 82
5273 12:12:21.607299 DQ Delay:
5274 12:12:21.609671 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5275 12:12:21.612961 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =107
5276 12:12:21.616471 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75
5277 12:12:21.619724 DQ12 =83, DQ13 =87, DQ14 =91, DQ15 =91
5278 12:12:21.620141
5279 12:12:21.620474
5280 12:12:21.623232 ==
5281 12:12:21.625981 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 12:12:21.629600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 12:12:21.630052 ==
5284 12:12:21.630501
5285 12:12:21.630920
5286 12:12:21.632833 TX Vref Scan disable
5287 12:12:21.633271 == TX Byte 0 ==
5288 12:12:21.636481 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5289 12:12:21.642651 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5290 12:12:21.643091 == TX Byte 1 ==
5291 12:12:21.646161 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5292 12:12:21.652758 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5293 12:12:21.653202 ==
5294 12:12:21.655981 Dram Type= 6, Freq= 0, CH_0, rank 0
5295 12:12:21.659456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 12:12:21.659899 ==
5297 12:12:21.660344
5298 12:12:21.660761
5299 12:12:21.662508 TX Vref Scan disable
5300 12:12:21.665791 == TX Byte 0 ==
5301 12:12:21.669312 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5302 12:12:21.672531 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5303 12:12:21.675774 == TX Byte 1 ==
5304 12:12:21.679079 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5305 12:12:21.682203 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5306 12:12:21.682768
5307 12:12:21.685775 [DATLAT]
5308 12:12:21.686272 Freq=933, CH0 RK0
5309 12:12:21.686777
5310 12:12:21.689223 DATLAT Default: 0xd
5311 12:12:21.689974 0, 0xFFFF, sum = 0
5312 12:12:21.692517 1, 0xFFFF, sum = 0
5313 12:12:21.692972 2, 0xFFFF, sum = 0
5314 12:12:21.695543 3, 0xFFFF, sum = 0
5315 12:12:21.696165 4, 0xFFFF, sum = 0
5316 12:12:21.699061 5, 0xFFFF, sum = 0
5317 12:12:21.699633 6, 0xFFFF, sum = 0
5318 12:12:21.702279 7, 0xFFFF, sum = 0
5319 12:12:21.702777 8, 0xFFFF, sum = 0
5320 12:12:21.705442 9, 0xFFFF, sum = 0
5321 12:12:21.706200 10, 0x0, sum = 1
5322 12:12:21.708853 11, 0x0, sum = 2
5323 12:12:21.709302 12, 0x0, sum = 3
5324 12:12:21.712004 13, 0x0, sum = 4
5325 12:12:21.712449 best_step = 11
5326 12:12:21.712893
5327 12:12:21.713312 ==
5328 12:12:21.715373 Dram Type= 6, Freq= 0, CH_0, rank 0
5329 12:12:21.722150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 12:12:21.722830 ==
5331 12:12:21.723441 RX Vref Scan: 1
5332 12:12:21.723810
5333 12:12:21.725196 RX Vref 0 -> 0, step: 1
5334 12:12:21.725667
5335 12:12:21.728804 RX Delay -69 -> 252, step: 4
5336 12:12:21.729231
5337 12:12:21.732309 Set Vref, RX VrefLevel [Byte0]: 61
5338 12:12:21.735272 [Byte1]: 53
5339 12:12:21.735697
5340 12:12:21.738692 Final RX Vref Byte 0 = 61 to rank0
5341 12:12:21.741847 Final RX Vref Byte 1 = 53 to rank0
5342 12:12:21.745385 Final RX Vref Byte 0 = 61 to rank1
5343 12:12:21.748663 Final RX Vref Byte 1 = 53 to rank1==
5344 12:12:21.751916 Dram Type= 6, Freq= 0, CH_0, rank 0
5345 12:12:21.755310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 12:12:21.755735 ==
5347 12:12:21.758621 DQS Delay:
5348 12:12:21.759043 DQS0 = 0, DQS1 = 0
5349 12:12:21.759380 DQM Delay:
5350 12:12:21.761891 DQM0 = 95, DQM1 = 83
5351 12:12:21.762369 DQ Delay:
5352 12:12:21.765148 DQ0 =94, DQ1 =94, DQ2 =92, DQ3 =92
5353 12:12:21.768553 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =106
5354 12:12:21.771871 DQ8 =76, DQ9 =70, DQ10 =84, DQ11 =76
5355 12:12:21.775024 DQ12 =88, DQ13 =88, DQ14 =94, DQ15 =90
5356 12:12:21.775448
5357 12:12:21.775786
5358 12:12:21.784986 [DQSOSCAuto] RK0, (LSB)MR18= 0x1716, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 414 ps
5359 12:12:21.788083 CH0 RK0: MR19=505, MR18=1716
5360 12:12:21.791843 CH0_RK0: MR19=0x505, MR18=0x1716, DQSOSC=414, MR23=63, INC=63, DEC=42
5361 12:12:21.794608
5362 12:12:21.798024 ----->DramcWriteLeveling(PI) begin...
5363 12:12:21.798453 ==
5364 12:12:21.801299 Dram Type= 6, Freq= 0, CH_0, rank 1
5365 12:12:21.804880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5366 12:12:21.805304 ==
5367 12:12:21.807914 Write leveling (Byte 0): 34 => 34
5368 12:12:21.811547 Write leveling (Byte 1): 30 => 30
5369 12:12:21.814859 DramcWriteLeveling(PI) end<-----
5370 12:12:21.815277
5371 12:12:21.815602 ==
5372 12:12:21.818103 Dram Type= 6, Freq= 0, CH_0, rank 1
5373 12:12:21.821095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 12:12:21.821563 ==
5375 12:12:21.824624 [Gating] SW mode calibration
5376 12:12:21.831420 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5377 12:12:21.838072 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5378 12:12:21.841091 0 14 0 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
5379 12:12:21.844514 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 12:12:21.851131 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 12:12:21.854460 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5382 12:12:21.857720 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5383 12:12:21.864370 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5384 12:12:21.867849 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5385 12:12:21.870900 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
5386 12:12:21.877585 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5387 12:12:21.881084 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 12:12:21.884129 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 12:12:21.890939 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5390 12:12:21.893893 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5391 12:12:21.897281 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5392 12:12:21.903978 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5393 12:12:21.907417 0 15 28 | B1->B0 | 2828 3939 | 0 0 | (0 0) (0 0)
5394 12:12:21.910735 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5395 12:12:21.917668 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 12:12:21.920844 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 12:12:21.924139 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 12:12:21.930636 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 12:12:21.933914 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 12:12:21.937446 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5401 12:12:21.940654 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 12:12:21.947175 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5403 12:12:21.950777 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 12:12:21.953742 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 12:12:21.960349 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 12:12:21.963652 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 12:12:21.967169 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 12:12:21.973569 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 12:12:21.977037 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 12:12:21.980349 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 12:12:21.986667 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 12:12:21.989900 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 12:12:21.993248 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 12:12:22.000030 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 12:12:22.003110 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 12:12:22.006699 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 12:12:22.013263 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5418 12:12:22.016325 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5419 12:12:22.019840 Total UI for P1: 0, mck2ui 16
5420 12:12:22.023273 best dqsien dly found for B0: ( 1, 2, 28)
5421 12:12:22.026543 Total UI for P1: 0, mck2ui 16
5422 12:12:22.029765 best dqsien dly found for B1: ( 1, 2, 28)
5423 12:12:22.032900 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5424 12:12:22.036304 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5425 12:12:22.036723
5426 12:12:22.039701 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5427 12:12:22.046473 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5428 12:12:22.046891 [Gating] SW calibration Done
5429 12:12:22.047224 ==
5430 12:12:22.049665 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 12:12:22.056271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 12:12:22.056690 ==
5433 12:12:22.057077 RX Vref Scan: 0
5434 12:12:22.057403
5435 12:12:22.059358 RX Vref 0 -> 0, step: 1
5436 12:12:22.059776
5437 12:12:22.062962 RX Delay -80 -> 252, step: 8
5438 12:12:22.066032 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5439 12:12:22.069632 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5440 12:12:22.072816 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5441 12:12:22.079141 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5442 12:12:22.082655 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5443 12:12:22.085974 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5444 12:12:22.089205 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5445 12:12:22.092553 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5446 12:12:22.095835 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5447 12:12:22.102853 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5448 12:12:22.105777 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5449 12:12:22.108957 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5450 12:12:22.112402 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5451 12:12:22.115689 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5452 12:12:22.122381 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5453 12:12:22.125868 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5454 12:12:22.126317 ==
5455 12:12:22.129117 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 12:12:22.132449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 12:12:22.132875 ==
5458 12:12:22.135970 DQS Delay:
5459 12:12:22.136435 DQS0 = 0, DQS1 = 0
5460 12:12:22.136772 DQM Delay:
5461 12:12:22.138748 DQM0 = 91, DQM1 = 83
5462 12:12:22.139167 DQ Delay:
5463 12:12:22.141958 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5464 12:12:22.145326 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =103
5465 12:12:22.148593 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =79
5466 12:12:22.152328 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =87
5467 12:12:22.152756
5468 12:12:22.153089
5469 12:12:22.153402 ==
5470 12:12:22.155256 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 12:12:22.161914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 12:12:22.162336 ==
5473 12:12:22.162672
5474 12:12:22.162984
5475 12:12:22.163283 TX Vref Scan disable
5476 12:12:22.165760 == TX Byte 0 ==
5477 12:12:22.169310 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5478 12:12:22.175668 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5479 12:12:22.176096 == TX Byte 1 ==
5480 12:12:22.178931 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5481 12:12:22.185766 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5482 12:12:22.186235 ==
5483 12:12:22.188694 Dram Type= 6, Freq= 0, CH_0, rank 1
5484 12:12:22.192179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 12:12:22.192653 ==
5486 12:12:22.193097
5487 12:12:22.193541
5488 12:12:22.195511 TX Vref Scan disable
5489 12:12:22.195952 == TX Byte 0 ==
5490 12:12:22.201928 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5491 12:12:22.205421 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5492 12:12:22.205904 == TX Byte 1 ==
5493 12:12:22.212159 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5494 12:12:22.215342 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5495 12:12:22.215782
5496 12:12:22.216226 [DATLAT]
5497 12:12:22.218926 Freq=933, CH0 RK1
5498 12:12:22.219362
5499 12:12:22.219808 DATLAT Default: 0xb
5500 12:12:22.222569 0, 0xFFFF, sum = 0
5501 12:12:22.223012 1, 0xFFFF, sum = 0
5502 12:12:22.225456 2, 0xFFFF, sum = 0
5503 12:12:22.225973 3, 0xFFFF, sum = 0
5504 12:12:22.228660 4, 0xFFFF, sum = 0
5505 12:12:22.231952 5, 0xFFFF, sum = 0
5506 12:12:22.232382 6, 0xFFFF, sum = 0
5507 12:12:22.235268 7, 0xFFFF, sum = 0
5508 12:12:22.235699 8, 0xFFFF, sum = 0
5509 12:12:22.238729 9, 0xFFFF, sum = 0
5510 12:12:22.239159 10, 0x0, sum = 1
5511 12:12:22.242194 11, 0x0, sum = 2
5512 12:12:22.242623 12, 0x0, sum = 3
5513 12:12:22.242974 13, 0x0, sum = 4
5514 12:12:22.245168 best_step = 11
5515 12:12:22.245615
5516 12:12:22.245954 ==
5517 12:12:22.248820 Dram Type= 6, Freq= 0, CH_0, rank 1
5518 12:12:22.251814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5519 12:12:22.252241 ==
5520 12:12:22.255419 RX Vref Scan: 0
5521 12:12:22.255845
5522 12:12:22.258699 RX Vref 0 -> 0, step: 1
5523 12:12:22.259121
5524 12:12:22.259458 RX Delay -77 -> 252, step: 4
5525 12:12:22.266070 iDelay=199, Bit 0, Center 88 (-5 ~ 182) 188
5526 12:12:22.269955 iDelay=199, Bit 1, Center 96 (7 ~ 186) 180
5527 12:12:22.272784 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5528 12:12:22.276329 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5529 12:12:22.279295 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5530 12:12:22.286150 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5531 12:12:22.289197 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5532 12:12:22.292575 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5533 12:12:22.295616 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5534 12:12:22.299203 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5535 12:12:22.305801 iDelay=199, Bit 10, Center 84 (-9 ~ 178) 188
5536 12:12:22.309345 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5537 12:12:22.312352 iDelay=199, Bit 12, Center 90 (-5 ~ 186) 192
5538 12:12:22.315701 iDelay=199, Bit 13, Center 90 (-5 ~ 186) 192
5539 12:12:22.319422 iDelay=199, Bit 14, Center 94 (3 ~ 186) 184
5540 12:12:22.325854 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5541 12:12:22.326346 ==
5542 12:12:22.328949 Dram Type= 6, Freq= 0, CH_0, rank 1
5543 12:12:22.332539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 12:12:22.332965 ==
5545 12:12:22.333370 DQS Delay:
5546 12:12:22.335714 DQS0 = 0, DQS1 = 0
5547 12:12:22.336134 DQM Delay:
5548 12:12:22.339013 DQM0 = 92, DQM1 = 84
5549 12:12:22.339438 DQ Delay:
5550 12:12:22.342201 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
5551 12:12:22.345606 DQ4 =90, DQ5 =80, DQ6 =102, DQ7 =104
5552 12:12:22.349025 DQ8 =78, DQ9 =68, DQ10 =84, DQ11 =78
5553 12:12:22.352153 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =92
5554 12:12:22.352578
5555 12:12:22.352914
5556 12:12:22.358859 [DQSOSCAuto] RK1, (LSB)MR18= 0x3213, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5557 12:12:22.362363 CH0 RK1: MR19=505, MR18=3213
5558 12:12:22.368906 CH0_RK1: MR19=0x505, MR18=0x3213, DQSOSC=406, MR23=63, INC=65, DEC=43
5559 12:12:22.372330 [RxdqsGatingPostProcess] freq 933
5560 12:12:22.378813 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5561 12:12:22.382444 best DQS0 dly(2T, 0.5T) = (0, 10)
5562 12:12:22.383065 best DQS1 dly(2T, 0.5T) = (0, 11)
5563 12:12:22.385343 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5564 12:12:22.388986 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5565 12:12:22.391923 best DQS0 dly(2T, 0.5T) = (0, 10)
5566 12:12:22.395312 best DQS1 dly(2T, 0.5T) = (0, 10)
5567 12:12:22.398672 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5568 12:12:22.402006 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5569 12:12:22.405202 Pre-setting of DQS Precalculation
5570 12:12:22.411873 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5571 12:12:22.412312 ==
5572 12:12:22.415174 Dram Type= 6, Freq= 0, CH_1, rank 0
5573 12:12:22.418481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5574 12:12:22.418922 ==
5575 12:12:22.425124 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5576 12:12:22.428705 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5577 12:12:22.432769 [CA 0] Center 37 (7~68) winsize 62
5578 12:12:22.436072 [CA 1] Center 37 (7~68) winsize 62
5579 12:12:22.439191 [CA 2] Center 35 (5~65) winsize 61
5580 12:12:22.442524 [CA 3] Center 34 (4~65) winsize 62
5581 12:12:22.446008 [CA 4] Center 35 (5~65) winsize 61
5582 12:12:22.449156 [CA 5] Center 34 (4~64) winsize 61
5583 12:12:22.449629
5584 12:12:22.452495 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5585 12:12:22.452932
5586 12:12:22.455668 [CATrainingPosCal] consider 1 rank data
5587 12:12:22.459213 u2DelayCellTimex100 = 270/100 ps
5588 12:12:22.462365 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5589 12:12:22.468913 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5590 12:12:22.472459 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5591 12:12:22.475545 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5592 12:12:22.479043 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5593 12:12:22.482265 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5594 12:12:22.482706
5595 12:12:22.485664 CA PerBit enable=1, Macro0, CA PI delay=34
5596 12:12:22.486102
5597 12:12:22.488776 [CBTSetCACLKResult] CA Dly = 34
5598 12:12:22.492223 CS Dly: 5 (0~36)
5599 12:12:22.492658 ==
5600 12:12:22.495519 Dram Type= 6, Freq= 0, CH_1, rank 1
5601 12:12:22.499292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5602 12:12:22.499733 ==
5603 12:12:22.505541 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5604 12:12:22.508721 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5605 12:12:22.512711 [CA 0] Center 38 (8~68) winsize 61
5606 12:12:22.515929 [CA 1] Center 37 (7~68) winsize 62
5607 12:12:22.519243 [CA 2] Center 35 (5~65) winsize 61
5608 12:12:22.522407 [CA 3] Center 34 (4~64) winsize 61
5609 12:12:22.525810 [CA 4] Center 35 (5~65) winsize 61
5610 12:12:22.529212 [CA 5] Center 34 (4~64) winsize 61
5611 12:12:22.529691
5612 12:12:22.532574 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5613 12:12:22.533017
5614 12:12:22.536052 [CATrainingPosCal] consider 2 rank data
5615 12:12:22.539060 u2DelayCellTimex100 = 270/100 ps
5616 12:12:22.542737 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5617 12:12:22.549017 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5618 12:12:22.552593 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5619 12:12:22.555887 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5620 12:12:22.559009 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5621 12:12:22.562632 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5622 12:12:22.563069
5623 12:12:22.565813 CA PerBit enable=1, Macro0, CA PI delay=34
5624 12:12:22.566255
5625 12:12:22.569061 [CBTSetCACLKResult] CA Dly = 34
5626 12:12:22.569528 CS Dly: 6 (0~38)
5627 12:12:22.572534
5628 12:12:22.575774 ----->DramcWriteLeveling(PI) begin...
5629 12:12:22.576217 ==
5630 12:12:22.578895 Dram Type= 6, Freq= 0, CH_1, rank 0
5631 12:12:22.582417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5632 12:12:22.582856 ==
5633 12:12:22.585572 Write leveling (Byte 0): 29 => 29
5634 12:12:22.589217 Write leveling (Byte 1): 31 => 31
5635 12:12:22.592428 DramcWriteLeveling(PI) end<-----
5636 12:12:22.592867
5637 12:12:22.593306 ==
5638 12:12:22.595668 Dram Type= 6, Freq= 0, CH_1, rank 0
5639 12:12:22.598735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5640 12:12:22.599162 ==
5641 12:12:22.602092 [Gating] SW mode calibration
5642 12:12:22.609040 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5643 12:12:22.615430 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5644 12:12:22.618877 0 14 0 | B1->B0 | 3232 3434 | 0 0 | (0 0) (0 0)
5645 12:12:22.621980 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 12:12:22.628757 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 12:12:22.632090 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5648 12:12:22.635237 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5649 12:12:22.642174 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5650 12:12:22.645256 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5651 12:12:22.648817 0 14 28 | B1->B0 | 2e2e 2e2e | 1 0 | (1 1) (0 0)
5652 12:12:22.655344 0 15 0 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
5653 12:12:22.658467 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 12:12:22.661942 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 12:12:22.665363 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5656 12:12:22.671982 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5657 12:12:22.675098 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5658 12:12:22.678740 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5659 12:12:22.685465 0 15 28 | B1->B0 | 2f2f 3131 | 0 1 | (0 0) (0 0)
5660 12:12:22.688639 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 12:12:22.691849 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 12:12:22.698377 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 12:12:22.701640 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 12:12:22.705143 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 12:12:22.711905 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 12:12:22.715075 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5667 12:12:22.718135 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5668 12:12:22.724863 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 12:12:22.728355 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 12:12:22.731826 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 12:12:22.738063 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 12:12:22.741778 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 12:12:22.745092 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 12:12:22.751633 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 12:12:22.754708 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 12:12:22.758010 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 12:12:22.764887 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 12:12:22.768010 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 12:12:22.771451 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 12:12:22.778209 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 12:12:22.781278 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 12:12:22.784533 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5683 12:12:22.791484 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5684 12:12:22.791911 Total UI for P1: 0, mck2ui 16
5685 12:12:22.798068 best dqsien dly found for B1: ( 1, 2, 24)
5686 12:12:22.801050 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5687 12:12:22.804640 Total UI for P1: 0, mck2ui 16
5688 12:12:22.807794 best dqsien dly found for B0: ( 1, 2, 28)
5689 12:12:22.811349 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5690 12:12:22.814875 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5691 12:12:22.815299
5692 12:12:22.818345 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5693 12:12:22.821438 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5694 12:12:22.824779 [Gating] SW calibration Done
5695 12:12:22.825203 ==
5696 12:12:22.828084 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 12:12:22.831564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 12:12:22.831992 ==
5699 12:12:22.834701 RX Vref Scan: 0
5700 12:12:22.835123
5701 12:12:22.838268 RX Vref 0 -> 0, step: 1
5702 12:12:22.838695
5703 12:12:22.839035 RX Delay -80 -> 252, step: 8
5704 12:12:22.844627 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5705 12:12:22.847946 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5706 12:12:22.851177 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5707 12:12:22.855219 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5708 12:12:22.857823 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5709 12:12:22.861425 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5710 12:12:22.867618 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5711 12:12:22.871375 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5712 12:12:22.874644 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5713 12:12:22.878064 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5714 12:12:22.881454 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5715 12:12:22.887627 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5716 12:12:22.891000 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5717 12:12:22.894490 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5718 12:12:22.897872 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5719 12:12:22.901330 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5720 12:12:22.901798 ==
5721 12:12:22.904377 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 12:12:22.910740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 12:12:22.911168 ==
5724 12:12:22.911511 DQS Delay:
5725 12:12:22.914456 DQS0 = 0, DQS1 = 0
5726 12:12:22.914879 DQM Delay:
5727 12:12:22.917500 DQM0 = 94, DQM1 = 86
5728 12:12:22.917934 DQ Delay:
5729 12:12:22.920847 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5730 12:12:22.924043 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5731 12:12:22.927382 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5732 12:12:22.930638 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5733 12:12:22.931131
5734 12:12:22.931475
5735 12:12:22.931794 ==
5736 12:12:22.934265 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 12:12:22.937361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 12:12:22.937834 ==
5739 12:12:22.938178
5740 12:12:22.938491
5741 12:12:22.940747 TX Vref Scan disable
5742 12:12:22.943922 == TX Byte 0 ==
5743 12:12:22.947665 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5744 12:12:22.950627 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5745 12:12:22.953921 == TX Byte 1 ==
5746 12:12:22.957189 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5747 12:12:22.960689 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5748 12:12:22.961113 ==
5749 12:12:22.963973 Dram Type= 6, Freq= 0, CH_1, rank 0
5750 12:12:22.970424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 12:12:22.970853 ==
5752 12:12:22.971190
5753 12:12:22.971504
5754 12:12:22.971805 TX Vref Scan disable
5755 12:12:22.974275 == TX Byte 0 ==
5756 12:12:22.977622 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5757 12:12:22.984197 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5758 12:12:22.984622 == TX Byte 1 ==
5759 12:12:22.987312 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5760 12:12:22.994074 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5761 12:12:22.994499
5762 12:12:22.994882 [DATLAT]
5763 12:12:22.995200 Freq=933, CH1 RK0
5764 12:12:22.995503
5765 12:12:22.997540 DATLAT Default: 0xd
5766 12:12:22.998017 0, 0xFFFF, sum = 0
5767 12:12:23.000789 1, 0xFFFF, sum = 0
5768 12:12:23.001215 2, 0xFFFF, sum = 0
5769 12:12:23.004287 3, 0xFFFF, sum = 0
5770 12:12:23.007612 4, 0xFFFF, sum = 0
5771 12:12:23.008040 5, 0xFFFF, sum = 0
5772 12:12:23.010530 6, 0xFFFF, sum = 0
5773 12:12:23.011008 7, 0xFFFF, sum = 0
5774 12:12:23.013933 8, 0xFFFF, sum = 0
5775 12:12:23.014360 9, 0xFFFF, sum = 0
5776 12:12:23.017450 10, 0x0, sum = 1
5777 12:12:23.017916 11, 0x0, sum = 2
5778 12:12:23.020688 12, 0x0, sum = 3
5779 12:12:23.021112 13, 0x0, sum = 4
5780 12:12:23.021567 best_step = 11
5781 12:12:23.021900
5782 12:12:23.024277 ==
5783 12:12:23.024696 Dram Type= 6, Freq= 0, CH_1, rank 0
5784 12:12:23.030642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 12:12:23.031111 ==
5786 12:12:23.031464 RX Vref Scan: 1
5787 12:12:23.031776
5788 12:12:23.034166 RX Vref 0 -> 0, step: 1
5789 12:12:23.034656
5790 12:12:23.037654 RX Delay -61 -> 252, step: 4
5791 12:12:23.038074
5792 12:12:23.040884 Set Vref, RX VrefLevel [Byte0]: 57
5793 12:12:23.043928 [Byte1]: 50
5794 12:12:23.044347
5795 12:12:23.047195 Final RX Vref Byte 0 = 57 to rank0
5796 12:12:23.050449 Final RX Vref Byte 1 = 50 to rank0
5797 12:12:23.053619 Final RX Vref Byte 0 = 57 to rank1
5798 12:12:23.057168 Final RX Vref Byte 1 = 50 to rank1==
5799 12:12:23.060621 Dram Type= 6, Freq= 0, CH_1, rank 0
5800 12:12:23.063834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 12:12:23.067176 ==
5802 12:12:23.067595 DQS Delay:
5803 12:12:23.067929 DQS0 = 0, DQS1 = 0
5804 12:12:23.070202 DQM Delay:
5805 12:12:23.070620 DQM0 = 97, DQM1 = 89
5806 12:12:23.073760 DQ Delay:
5807 12:12:23.077131 DQ0 =100, DQ1 =94, DQ2 =86, DQ3 =92
5808 12:12:23.077790 DQ4 =94, DQ5 =108, DQ6 =108, DQ7 =94
5809 12:12:23.080396 DQ8 =78, DQ9 =84, DQ10 =88, DQ11 =80
5810 12:12:23.086843 DQ12 =100, DQ13 =94, DQ14 =94, DQ15 =96
5811 12:12:23.087293
5812 12:12:23.087639
5813 12:12:23.093576 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe06, (MSB)MR19= 0x405, tDQSOscB0 = 420 ps tDQSOscB1 = 422 ps
5814 12:12:23.097126 CH1 RK0: MR19=405, MR18=FE06
5815 12:12:23.103517 CH1_RK0: MR19=0x405, MR18=0xFE06, DQSOSC=420, MR23=63, INC=61, DEC=40
5816 12:12:23.104051
5817 12:12:23.106983 ----->DramcWriteLeveling(PI) begin...
5818 12:12:23.107413 ==
5819 12:12:23.110456 Dram Type= 6, Freq= 0, CH_1, rank 1
5820 12:12:23.113396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 12:12:23.113881 ==
5822 12:12:23.116821 Write leveling (Byte 0): 24 => 24
5823 12:12:23.120127 Write leveling (Byte 1): 29 => 29
5824 12:12:23.123408 DramcWriteLeveling(PI) end<-----
5825 12:12:23.123988
5826 12:12:23.124503 ==
5827 12:12:23.126887 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 12:12:23.130095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 12:12:23.130521 ==
5830 12:12:23.133027 [Gating] SW mode calibration
5831 12:12:23.139869 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5832 12:12:23.146460 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5833 12:12:23.149835 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5834 12:12:23.156492 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 12:12:23.159995 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5836 12:12:23.163215 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5837 12:12:23.166760 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5838 12:12:23.173324 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5839 12:12:23.176364 0 14 24 | B1->B0 | 3131 2f2f | 1 1 | (1 0) (0 0)
5840 12:12:23.179918 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (1 0)
5841 12:12:23.186545 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5842 12:12:23.189808 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 12:12:23.193244 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 12:12:23.199730 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5845 12:12:23.203187 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5846 12:12:23.206294 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5847 12:12:23.213089 0 15 24 | B1->B0 | 2626 3838 | 0 0 | (0 0) (0 0)
5848 12:12:23.216227 0 15 28 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5849 12:12:23.219778 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5850 12:12:23.226460 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 12:12:23.229595 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 12:12:23.233002 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 12:12:23.239549 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 12:12:23.243059 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5855 12:12:23.246170 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5856 12:12:23.253142 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5857 12:12:23.256335 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 12:12:23.259781 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 12:12:23.266348 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 12:12:23.269418 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 12:12:23.272895 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 12:12:23.279377 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 12:12:23.282820 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 12:12:23.286215 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 12:12:23.292715 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 12:12:23.296002 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 12:12:23.299212 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 12:12:23.305730 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 12:12:23.309123 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 12:12:23.312594 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 12:12:23.319074 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5872 12:12:23.322133 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5873 12:12:23.325720 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5874 12:12:23.328859 Total UI for P1: 0, mck2ui 16
5875 12:12:23.332335 best dqsien dly found for B0: ( 1, 2, 26)
5876 12:12:23.335395 Total UI for P1: 0, mck2ui 16
5877 12:12:23.338555 best dqsien dly found for B1: ( 1, 2, 28)
5878 12:12:23.342171 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5879 12:12:23.345409 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5880 12:12:23.345885
5881 12:12:23.348882 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5882 12:12:23.355565 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5883 12:12:23.355992 [Gating] SW calibration Done
5884 12:12:23.356330 ==
5885 12:12:23.358927 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 12:12:23.365216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 12:12:23.365675 ==
5888 12:12:23.366018 RX Vref Scan: 0
5889 12:12:23.366334
5890 12:12:23.368827 RX Vref 0 -> 0, step: 1
5891 12:12:23.369248
5892 12:12:23.372075 RX Delay -80 -> 252, step: 8
5893 12:12:23.375249 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5894 12:12:23.378819 iDelay=208, Bit 1, Center 83 (-16 ~ 183) 200
5895 12:12:23.382197 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5896 12:12:23.388749 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5897 12:12:23.391814 iDelay=208, Bit 4, Center 87 (-16 ~ 191) 208
5898 12:12:23.395140 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5899 12:12:23.398600 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5900 12:12:23.401730 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5901 12:12:23.408676 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5902 12:12:23.411832 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5903 12:12:23.415032 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5904 12:12:23.418459 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5905 12:12:23.421765 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5906 12:12:23.428471 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5907 12:12:23.431551 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5908 12:12:23.435107 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5909 12:12:23.435546 ==
5910 12:12:23.438251 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 12:12:23.441458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 12:12:23.441929 ==
5913 12:12:23.444851 DQS Delay:
5914 12:12:23.445306 DQS0 = 0, DQS1 = 0
5915 12:12:23.445696 DQM Delay:
5916 12:12:23.447963 DQM0 = 91, DQM1 = 87
5917 12:12:23.448390 DQ Delay:
5918 12:12:23.451328 DQ0 =95, DQ1 =83, DQ2 =83, DQ3 =87
5919 12:12:23.454636 DQ4 =87, DQ5 =103, DQ6 =103, DQ7 =91
5920 12:12:23.458102 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5921 12:12:23.461419 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5922 12:12:23.461869
5923 12:12:23.462205
5924 12:12:23.462520 ==
5925 12:12:23.464838 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 12:12:23.471291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 12:12:23.471735 ==
5928 12:12:23.472076
5929 12:12:23.472391
5930 12:12:23.472692 TX Vref Scan disable
5931 12:12:23.475296 == TX Byte 0 ==
5932 12:12:23.478369 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5933 12:12:23.485072 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5934 12:12:23.485538 == TX Byte 1 ==
5935 12:12:23.488506 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5936 12:12:23.494821 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5937 12:12:23.495362 ==
5938 12:12:23.498112 Dram Type= 6, Freq= 0, CH_1, rank 1
5939 12:12:23.501333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5940 12:12:23.501909 ==
5941 12:12:23.502405
5942 12:12:23.502733
5943 12:12:23.504849 TX Vref Scan disable
5944 12:12:23.505273 == TX Byte 0 ==
5945 12:12:23.511528 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5946 12:12:23.514865 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5947 12:12:23.515290 == TX Byte 1 ==
5948 12:12:23.521323 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5949 12:12:23.524773 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5950 12:12:23.525197
5951 12:12:23.525588 [DATLAT]
5952 12:12:23.528156 Freq=933, CH1 RK1
5953 12:12:23.528767
5954 12:12:23.529144 DATLAT Default: 0xb
5955 12:12:23.531383 0, 0xFFFF, sum = 0
5956 12:12:23.531816 1, 0xFFFF, sum = 0
5957 12:12:23.534938 2, 0xFFFF, sum = 0
5958 12:12:23.538124 3, 0xFFFF, sum = 0
5959 12:12:23.538556 4, 0xFFFF, sum = 0
5960 12:12:23.541110 5, 0xFFFF, sum = 0
5961 12:12:23.541564 6, 0xFFFF, sum = 0
5962 12:12:23.544775 7, 0xFFFF, sum = 0
5963 12:12:23.545207 8, 0xFFFF, sum = 0
5964 12:12:23.547939 9, 0xFFFF, sum = 0
5965 12:12:23.548369 10, 0x0, sum = 1
5966 12:12:23.551092 11, 0x0, sum = 2
5967 12:12:23.551523 12, 0x0, sum = 3
5968 12:12:23.554534 13, 0x0, sum = 4
5969 12:12:23.554967 best_step = 11
5970 12:12:23.555307
5971 12:12:23.555623 ==
5972 12:12:23.557747 Dram Type= 6, Freq= 0, CH_1, rank 1
5973 12:12:23.560971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5974 12:12:23.561400 ==
5975 12:12:23.564527 RX Vref Scan: 0
5976 12:12:23.564951
5977 12:12:23.567829 RX Vref 0 -> 0, step: 1
5978 12:12:23.568253
5979 12:12:23.568591 RX Delay -69 -> 252, step: 4
5980 12:12:23.575442 iDelay=203, Bit 0, Center 94 (-5 ~ 194) 200
5981 12:12:23.578901 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5982 12:12:23.582344 iDelay=203, Bit 2, Center 80 (-17 ~ 178) 196
5983 12:12:23.585548 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5984 12:12:23.588665 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5985 12:12:23.595575 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5986 12:12:23.598783 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5987 12:12:23.602120 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5988 12:12:23.605446 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5989 12:12:23.608656 iDelay=203, Bit 9, Center 84 (-9 ~ 178) 188
5990 12:12:23.612221 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5991 12:12:23.618798 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5992 12:12:23.621968 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5993 12:12:23.625418 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5994 12:12:23.628775 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
5995 12:12:23.631755 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5996 12:12:23.632180 ==
5997 12:12:23.635437 Dram Type= 6, Freq= 0, CH_1, rank 1
5998 12:12:23.641829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5999 12:12:23.642257 ==
6000 12:12:23.642600 DQS Delay:
6001 12:12:23.645126 DQS0 = 0, DQS1 = 0
6002 12:12:23.645590 DQM Delay:
6003 12:12:23.645939 DQM0 = 90, DQM1 = 90
6004 12:12:23.648641 DQ Delay:
6005 12:12:23.651774 DQ0 =94, DQ1 =86, DQ2 =80, DQ3 =88
6006 12:12:23.654950 DQ4 =88, DQ5 =100, DQ6 =102, DQ7 =88
6007 12:12:23.658637 DQ8 =78, DQ9 =84, DQ10 =90, DQ11 =84
6008 12:12:23.661761 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
6009 12:12:23.662187
6010 12:12:23.662525
6011 12:12:23.668478 [DQSOSCAuto] RK1, (LSB)MR18= 0x1025, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
6012 12:12:23.671852 CH1 RK1: MR19=505, MR18=1025
6013 12:12:23.678753 CH1_RK1: MR19=0x505, MR18=0x1025, DQSOSC=410, MR23=63, INC=64, DEC=42
6014 12:12:23.681961 [RxdqsGatingPostProcess] freq 933
6015 12:12:23.685403 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6016 12:12:23.688708 best DQS0 dly(2T, 0.5T) = (0, 10)
6017 12:12:23.691841 best DQS1 dly(2T, 0.5T) = (0, 10)
6018 12:12:23.695446 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6019 12:12:23.698626 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6020 12:12:23.701906 best DQS0 dly(2T, 0.5T) = (0, 10)
6021 12:12:23.705276 best DQS1 dly(2T, 0.5T) = (0, 10)
6022 12:12:23.708323 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6023 12:12:23.711624 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6024 12:12:23.715019 Pre-setting of DQS Precalculation
6025 12:12:23.718409 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6026 12:12:23.728332 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6027 12:12:23.735021 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6028 12:12:23.735448
6029 12:12:23.735783
6030 12:12:23.738506 [Calibration Summary] 1866 Mbps
6031 12:12:23.738992 CH 0, Rank 0
6032 12:12:23.741816 SW Impedance : PASS
6033 12:12:23.742242 DUTY Scan : NO K
6034 12:12:23.744914 ZQ Calibration : PASS
6035 12:12:23.748148 Jitter Meter : NO K
6036 12:12:23.748575 CBT Training : PASS
6037 12:12:23.751725 Write leveling : PASS
6038 12:12:23.755206 RX DQS gating : PASS
6039 12:12:23.755675 RX DQ/DQS(RDDQC) : PASS
6040 12:12:23.758262 TX DQ/DQS : PASS
6041 12:12:23.761399 RX DATLAT : PASS
6042 12:12:23.761847 RX DQ/DQS(Engine): PASS
6043 12:12:23.765106 TX OE : NO K
6044 12:12:23.765614 All Pass.
6045 12:12:23.765962
6046 12:12:23.768220 CH 0, Rank 1
6047 12:12:23.768645 SW Impedance : PASS
6048 12:12:23.771405 DUTY Scan : NO K
6049 12:12:23.771830 ZQ Calibration : PASS
6050 12:12:23.774906 Jitter Meter : NO K
6051 12:12:23.778085 CBT Training : PASS
6052 12:12:23.778507 Write leveling : PASS
6053 12:12:23.781585 RX DQS gating : PASS
6054 12:12:23.784653 RX DQ/DQS(RDDQC) : PASS
6055 12:12:23.785074 TX DQ/DQS : PASS
6056 12:12:23.788242 RX DATLAT : PASS
6057 12:12:23.791179 RX DQ/DQS(Engine): PASS
6058 12:12:23.791603 TX OE : NO K
6059 12:12:23.794530 All Pass.
6060 12:12:23.795006
6061 12:12:23.795393 CH 1, Rank 0
6062 12:12:23.797909 SW Impedance : PASS
6063 12:12:23.798337 DUTY Scan : NO K
6064 12:12:23.801225 ZQ Calibration : PASS
6065 12:12:23.804524 Jitter Meter : NO K
6066 12:12:23.804964 CBT Training : PASS
6067 12:12:23.808013 Write leveling : PASS
6068 12:12:23.811228 RX DQS gating : PASS
6069 12:12:23.811663 RX DQ/DQS(RDDQC) : PASS
6070 12:12:23.814296 TX DQ/DQS : PASS
6071 12:12:23.817902 RX DATLAT : PASS
6072 12:12:23.818336 RX DQ/DQS(Engine): PASS
6073 12:12:23.821067 TX OE : NO K
6074 12:12:23.821531 All Pass.
6075 12:12:23.821971
6076 12:12:23.824478 CH 1, Rank 1
6077 12:12:23.824911 SW Impedance : PASS
6078 12:12:23.827815 DUTY Scan : NO K
6079 12:12:23.831098 ZQ Calibration : PASS
6080 12:12:23.831535 Jitter Meter : NO K
6081 12:12:23.834454 CBT Training : PASS
6082 12:12:23.834889 Write leveling : PASS
6083 12:12:23.837513 RX DQS gating : PASS
6084 12:12:23.840959 RX DQ/DQS(RDDQC) : PASS
6085 12:12:23.841392 TX DQ/DQS : PASS
6086 12:12:23.844462 RX DATLAT : PASS
6087 12:12:23.847652 RX DQ/DQS(Engine): PASS
6088 12:12:23.848168 TX OE : NO K
6089 12:12:23.851021 All Pass.
6090 12:12:23.851440
6091 12:12:23.851778 DramC Write-DBI off
6092 12:12:23.854529 PER_BANK_REFRESH: Hybrid Mode
6093 12:12:23.854954 TX_TRACKING: ON
6094 12:12:23.864198 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6095 12:12:23.867508 [FAST_K] Save calibration result to emmc
6096 12:12:23.871000 dramc_set_vcore_voltage set vcore to 650000
6097 12:12:23.874026 Read voltage for 400, 6
6098 12:12:23.874449 Vio18 = 0
6099 12:12:23.877325 Vcore = 650000
6100 12:12:23.877778 Vdram = 0
6101 12:12:23.878119 Vddq = 0
6102 12:12:23.880933 Vmddr = 0
6103 12:12:23.883979 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6104 12:12:23.890578 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6105 12:12:23.891073 MEM_TYPE=3, freq_sel=20
6106 12:12:23.893906 sv_algorithm_assistance_LP4_800
6107 12:12:23.900590 ============ PULL DRAM RESETB DOWN ============
6108 12:12:23.903645 ========== PULL DRAM RESETB DOWN end =========
6109 12:12:23.906966 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6110 12:12:23.910146 ===================================
6111 12:12:23.913710 LPDDR4 DRAM CONFIGURATION
6112 12:12:23.916969 ===================================
6113 12:12:23.920456 EX_ROW_EN[0] = 0x0
6114 12:12:23.920880 EX_ROW_EN[1] = 0x0
6115 12:12:23.923705 LP4Y_EN = 0x0
6116 12:12:23.924132 WORK_FSP = 0x0
6117 12:12:23.927035 WL = 0x2
6118 12:12:23.927463 RL = 0x2
6119 12:12:23.930319 BL = 0x2
6120 12:12:23.930744 RPST = 0x0
6121 12:12:23.933657 RD_PRE = 0x0
6122 12:12:23.934080 WR_PRE = 0x1
6123 12:12:23.936805 WR_PST = 0x0
6124 12:12:23.937228 DBI_WR = 0x0
6125 12:12:23.940178 DBI_RD = 0x0
6126 12:12:23.940602 OTF = 0x1
6127 12:12:23.943711 ===================================
6128 12:12:23.946772 ===================================
6129 12:12:23.949960 ANA top config
6130 12:12:23.953550 ===================================
6131 12:12:23.956841 DLL_ASYNC_EN = 0
6132 12:12:23.957264 ALL_SLAVE_EN = 1
6133 12:12:23.960125 NEW_RANK_MODE = 1
6134 12:12:23.963608 DLL_IDLE_MODE = 1
6135 12:12:23.966471 LP45_APHY_COMB_EN = 1
6136 12:12:23.966895 TX_ODT_DIS = 1
6137 12:12:23.970006 NEW_8X_MODE = 1
6138 12:12:23.973400 ===================================
6139 12:12:23.976291 ===================================
6140 12:12:23.979802 data_rate = 800
6141 12:12:23.983272 CKR = 1
6142 12:12:23.986386 DQ_P2S_RATIO = 4
6143 12:12:23.989693 ===================================
6144 12:12:23.993230 CA_P2S_RATIO = 4
6145 12:12:23.993737 DQ_CA_OPEN = 0
6146 12:12:23.996315 DQ_SEMI_OPEN = 1
6147 12:12:23.999720 CA_SEMI_OPEN = 1
6148 12:12:24.003112 CA_FULL_RATE = 0
6149 12:12:24.006354 DQ_CKDIV4_EN = 0
6150 12:12:24.009825 CA_CKDIV4_EN = 1
6151 12:12:24.010463 CA_PREDIV_EN = 0
6152 12:12:24.012995 PH8_DLY = 0
6153 12:12:24.016125 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6154 12:12:24.019853 DQ_AAMCK_DIV = 0
6155 12:12:24.023380 CA_AAMCK_DIV = 0
6156 12:12:24.026516 CA_ADMCK_DIV = 4
6157 12:12:24.026960 DQ_TRACK_CA_EN = 0
6158 12:12:24.029583 CA_PICK = 800
6159 12:12:24.033242 CA_MCKIO = 400
6160 12:12:24.036245 MCKIO_SEMI = 400
6161 12:12:24.039695 PLL_FREQ = 3016
6162 12:12:24.042756 DQ_UI_PI_RATIO = 32
6163 12:12:24.046057 CA_UI_PI_RATIO = 32
6164 12:12:24.049671 ===================================
6165 12:12:24.053069 ===================================
6166 12:12:24.053536 memory_type:LPDDR4
6167 12:12:24.056382 GP_NUM : 10
6168 12:12:24.059412 SRAM_EN : 1
6169 12:12:24.059973 MD32_EN : 0
6170 12:12:24.062834 ===================================
6171 12:12:24.065955 [ANA_INIT] >>>>>>>>>>>>>>
6172 12:12:24.069612 <<<<<< [CONFIGURE PHASE]: ANA_TX
6173 12:12:24.072700 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6174 12:12:24.076059 ===================================
6175 12:12:24.079402 data_rate = 800,PCW = 0X7400
6176 12:12:24.082691 ===================================
6177 12:12:24.085939 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6178 12:12:24.089471 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6179 12:12:24.102447 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6180 12:12:24.105360 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6181 12:12:24.108820 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6182 12:12:24.112261 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6183 12:12:24.115552 [ANA_INIT] flow start
6184 12:12:24.118579 [ANA_INIT] PLL >>>>>>>>
6185 12:12:24.118661 [ANA_INIT] PLL <<<<<<<<
6186 12:12:24.121917 [ANA_INIT] MIDPI >>>>>>>>
6187 12:12:24.125286 [ANA_INIT] MIDPI <<<<<<<<
6188 12:12:24.125362 [ANA_INIT] DLL >>>>>>>>
6189 12:12:24.128523 [ANA_INIT] flow end
6190 12:12:24.131953 ============ LP4 DIFF to SE enter ============
6191 12:12:24.135062 ============ LP4 DIFF to SE exit ============
6192 12:12:24.138605 [ANA_INIT] <<<<<<<<<<<<<
6193 12:12:24.141647 [Flow] Enable top DCM control >>>>>
6194 12:12:24.145263 [Flow] Enable top DCM control <<<<<
6195 12:12:24.148352 Enable DLL master slave shuffle
6196 12:12:24.154890 ==============================================================
6197 12:12:24.154968 Gating Mode config
6198 12:12:24.161354 ==============================================================
6199 12:12:24.164782 Config description:
6200 12:12:24.171312 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6201 12:12:24.178098 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6202 12:12:24.184353 SELPH_MODE 0: By rank 1: By Phase
6203 12:12:24.191422 ==============================================================
6204 12:12:24.194499 GAT_TRACK_EN = 0
6205 12:12:24.194576 RX_GATING_MODE = 2
6206 12:12:24.197647 RX_GATING_TRACK_MODE = 2
6207 12:12:24.201227 SELPH_MODE = 1
6208 12:12:24.204595 PICG_EARLY_EN = 1
6209 12:12:24.207843 VALID_LAT_VALUE = 1
6210 12:12:24.214469 ==============================================================
6211 12:12:24.217482 Enter into Gating configuration >>>>
6212 12:12:24.220803 Exit from Gating configuration <<<<
6213 12:12:24.224159 Enter into DVFS_PRE_config >>>>>
6214 12:12:24.234166 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6215 12:12:24.237660 Exit from DVFS_PRE_config <<<<<
6216 12:12:24.240737 Enter into PICG configuration >>>>
6217 12:12:24.244261 Exit from PICG configuration <<<<
6218 12:12:24.247371 [RX_INPUT] configuration >>>>>
6219 12:12:24.250658 [RX_INPUT] configuration <<<<<
6220 12:12:24.254161 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6221 12:12:24.260533 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6222 12:12:24.267196 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6223 12:12:24.273694 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6224 12:12:24.277167 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6225 12:12:24.283639 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6226 12:12:24.287087 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6227 12:12:24.293317 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6228 12:12:24.296998 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6229 12:12:24.300364 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6230 12:12:24.303386 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6231 12:12:24.310194 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6232 12:12:24.313363 ===================================
6233 12:12:24.316612 LPDDR4 DRAM CONFIGURATION
6234 12:12:24.320101 ===================================
6235 12:12:24.320207 EX_ROW_EN[0] = 0x0
6236 12:12:24.323460 EX_ROW_EN[1] = 0x0
6237 12:12:24.323548 LP4Y_EN = 0x0
6238 12:12:24.326637 WORK_FSP = 0x0
6239 12:12:24.326719 WL = 0x2
6240 12:12:24.330070 RL = 0x2
6241 12:12:24.330145 BL = 0x2
6242 12:12:24.333313 RPST = 0x0
6243 12:12:24.333388 RD_PRE = 0x0
6244 12:12:24.336614 WR_PRE = 0x1
6245 12:12:24.336692 WR_PST = 0x0
6246 12:12:24.339809 DBI_WR = 0x0
6247 12:12:24.339880 DBI_RD = 0x0
6248 12:12:24.343194 OTF = 0x1
6249 12:12:24.346417 ===================================
6250 12:12:24.349681 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6251 12:12:24.352801 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6252 12:12:24.359366 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6253 12:12:24.362739 ===================================
6254 12:12:24.366117 LPDDR4 DRAM CONFIGURATION
6255 12:12:24.369708 ===================================
6256 12:12:24.369790 EX_ROW_EN[0] = 0x10
6257 12:12:24.372654 EX_ROW_EN[1] = 0x0
6258 12:12:24.372736 LP4Y_EN = 0x0
6259 12:12:24.376185 WORK_FSP = 0x0
6260 12:12:24.376271 WL = 0x2
6261 12:12:24.379709 RL = 0x2
6262 12:12:24.379791 BL = 0x2
6263 12:12:24.382573 RPST = 0x0
6264 12:12:24.382655 RD_PRE = 0x0
6265 12:12:24.385895 WR_PRE = 0x1
6266 12:12:24.385978 WR_PST = 0x0
6267 12:12:24.389159 DBI_WR = 0x0
6268 12:12:24.392314 DBI_RD = 0x0
6269 12:12:24.392414 OTF = 0x1
6270 12:12:24.395739 ===================================
6271 12:12:24.402414 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6272 12:12:24.406094 nWR fixed to 30
6273 12:12:24.409442 [ModeRegInit_LP4] CH0 RK0
6274 12:12:24.409564 [ModeRegInit_LP4] CH0 RK1
6275 12:12:24.412399 [ModeRegInit_LP4] CH1 RK0
6276 12:12:24.415859 [ModeRegInit_LP4] CH1 RK1
6277 12:12:24.415941 match AC timing 19
6278 12:12:24.422387 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6279 12:12:24.425433 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6280 12:12:24.428817 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6281 12:12:24.435840 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6282 12:12:24.438789 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6283 12:12:24.438873 ==
6284 12:12:24.442388 Dram Type= 6, Freq= 0, CH_0, rank 0
6285 12:12:24.445702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6286 12:12:24.445800 ==
6287 12:12:24.452244 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6288 12:12:24.458656 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6289 12:12:24.462125 [CA 0] Center 36 (8~64) winsize 57
6290 12:12:24.465618 [CA 1] Center 36 (8~64) winsize 57
6291 12:12:24.468858 [CA 2] Center 36 (8~64) winsize 57
6292 12:12:24.472106 [CA 3] Center 36 (8~64) winsize 57
6293 12:12:24.475612 [CA 4] Center 36 (8~64) winsize 57
6294 12:12:24.475696 [CA 5] Center 36 (8~64) winsize 57
6295 12:12:24.475762
6296 12:12:24.482041 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6297 12:12:24.482124
6298 12:12:24.485165 [CATrainingPosCal] consider 1 rank data
6299 12:12:24.488673 u2DelayCellTimex100 = 270/100 ps
6300 12:12:24.491901 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 12:12:24.495158 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 12:12:24.498375 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 12:12:24.501672 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 12:12:24.505230 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 12:12:24.508781 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 12:12:24.508864
6307 12:12:24.511795 CA PerBit enable=1, Macro0, CA PI delay=36
6308 12:12:24.511879
6309 12:12:24.515423 [CBTSetCACLKResult] CA Dly = 36
6310 12:12:24.518544 CS Dly: 1 (0~32)
6311 12:12:24.518626 ==
6312 12:12:24.521992 Dram Type= 6, Freq= 0, CH_0, rank 1
6313 12:12:24.525355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 12:12:24.525439 ==
6315 12:12:24.531746 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6316 12:12:24.538241 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6317 12:12:24.541790 [CA 0] Center 36 (8~64) winsize 57
6318 12:12:24.541872 [CA 1] Center 36 (8~64) winsize 57
6319 12:12:24.544829 [CA 2] Center 36 (8~64) winsize 57
6320 12:12:24.548605 [CA 3] Center 36 (8~64) winsize 57
6321 12:12:24.551761 [CA 4] Center 36 (8~64) winsize 57
6322 12:12:24.554909 [CA 5] Center 36 (8~64) winsize 57
6323 12:12:24.554992
6324 12:12:24.558447 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6325 12:12:24.558529
6326 12:12:24.561592 [CATrainingPosCal] consider 2 rank data
6327 12:12:24.565115 u2DelayCellTimex100 = 270/100 ps
6328 12:12:24.568252 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 12:12:24.574842 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 12:12:24.578200 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 12:12:24.581275 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 12:12:24.584866 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 12:12:24.588465 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 12:12:24.588547
6335 12:12:24.591620 CA PerBit enable=1, Macro0, CA PI delay=36
6336 12:12:24.591702
6337 12:12:24.594782 [CBTSetCACLKResult] CA Dly = 36
6338 12:12:24.594865 CS Dly: 1 (0~32)
6339 12:12:24.597944
6340 12:12:24.601342 ----->DramcWriteLeveling(PI) begin...
6341 12:12:24.601426 ==
6342 12:12:24.604517 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 12:12:24.608115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 12:12:24.608201 ==
6345 12:12:24.611441 Write leveling (Byte 0): 40 => 8
6346 12:12:24.614783 Write leveling (Byte 1): 40 => 8
6347 12:12:24.617818 DramcWriteLeveling(PI) end<-----
6348 12:12:24.617900
6349 12:12:24.617985 ==
6350 12:12:24.621017 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 12:12:24.624473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 12:12:24.624556 ==
6353 12:12:24.627836 [Gating] SW mode calibration
6354 12:12:24.634410 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6355 12:12:24.641280 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6356 12:12:24.644219 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6357 12:12:24.647698 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6358 12:12:24.654362 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6359 12:12:24.657576 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6360 12:12:24.661024 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6361 12:12:24.667272 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6362 12:12:24.670784 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6363 12:12:24.674169 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6364 12:12:24.680815 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6365 12:12:24.680924 Total UI for P1: 0, mck2ui 16
6366 12:12:24.687554 best dqsien dly found for B0: ( 0, 14, 24)
6367 12:12:24.687637 Total UI for P1: 0, mck2ui 16
6368 12:12:24.690659 best dqsien dly found for B1: ( 0, 14, 24)
6369 12:12:24.697429 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6370 12:12:24.700822 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6371 12:12:24.700904
6372 12:12:24.703843 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6373 12:12:24.707417 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6374 12:12:24.710748 [Gating] SW calibration Done
6375 12:12:24.710831 ==
6376 12:12:24.714122 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 12:12:24.717209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 12:12:24.717292 ==
6379 12:12:24.720703 RX Vref Scan: 0
6380 12:12:24.720785
6381 12:12:24.720850 RX Vref 0 -> 0, step: 1
6382 12:12:24.720911
6383 12:12:24.723899 RX Delay -410 -> 252, step: 16
6384 12:12:24.730495 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6385 12:12:24.733839 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6386 12:12:24.737291 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6387 12:12:24.740149 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6388 12:12:24.747095 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6389 12:12:24.750320 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6390 12:12:24.753734 iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496
6391 12:12:24.756990 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6392 12:12:24.763747 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6393 12:12:24.767239 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6394 12:12:24.770393 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6395 12:12:24.773358 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6396 12:12:24.780102 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6397 12:12:24.783681 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6398 12:12:24.786904 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6399 12:12:24.790109 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6400 12:12:24.793418 ==
6401 12:12:24.793496 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 12:12:24.800208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 12:12:24.800283 ==
6404 12:12:24.800346 DQS Delay:
6405 12:12:24.803535 DQS0 = 59, DQS1 = 59
6406 12:12:24.803609 DQM Delay:
6407 12:12:24.807016 DQM0 = 17, DQM1 = 10
6408 12:12:24.807087 DQ Delay:
6409 12:12:24.809875 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6410 12:12:24.813245 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6411 12:12:24.816694 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6412 12:12:24.820013 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6413 12:12:24.820089
6414 12:12:24.820151
6415 12:12:24.820212 ==
6416 12:12:24.823412 Dram Type= 6, Freq= 0, CH_0, rank 0
6417 12:12:24.826590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6418 12:12:24.826692 ==
6419 12:12:24.826772
6420 12:12:24.826831
6421 12:12:24.829892 TX Vref Scan disable
6422 12:12:24.829962 == TX Byte 0 ==
6423 12:12:24.836577 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6424 12:12:24.839733 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6425 12:12:24.839809 == TX Byte 1 ==
6426 12:12:24.846417 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6427 12:12:24.849843 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6428 12:12:24.849918 ==
6429 12:12:24.853139 Dram Type= 6, Freq= 0, CH_0, rank 0
6430 12:12:24.856539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 12:12:24.856612 ==
6432 12:12:24.856673
6433 12:12:24.856732
6434 12:12:24.859768 TX Vref Scan disable
6435 12:12:24.859835 == TX Byte 0 ==
6436 12:12:24.866461 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6437 12:12:24.869932 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6438 12:12:24.870003 == TX Byte 1 ==
6439 12:12:24.876738 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6440 12:12:24.879905 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6441 12:12:24.879978
6442 12:12:24.880040 [DATLAT]
6443 12:12:24.883058 Freq=400, CH0 RK0
6444 12:12:24.883127
6445 12:12:24.883186 DATLAT Default: 0xf
6446 12:12:24.886422 0, 0xFFFF, sum = 0
6447 12:12:24.886489 1, 0xFFFF, sum = 0
6448 12:12:24.889918 2, 0xFFFF, sum = 0
6449 12:12:24.889988 3, 0xFFFF, sum = 0
6450 12:12:24.893034 4, 0xFFFF, sum = 0
6451 12:12:24.893102 5, 0xFFFF, sum = 0
6452 12:12:24.896268 6, 0xFFFF, sum = 0
6453 12:12:24.896341 7, 0xFFFF, sum = 0
6454 12:12:24.899634 8, 0xFFFF, sum = 0
6455 12:12:24.899702 9, 0xFFFF, sum = 0
6456 12:12:24.903053 10, 0xFFFF, sum = 0
6457 12:12:24.906333 11, 0xFFFF, sum = 0
6458 12:12:24.906408 12, 0xFFFF, sum = 0
6459 12:12:24.909636 13, 0x0, sum = 1
6460 12:12:24.909708 14, 0x0, sum = 2
6461 12:12:24.909769 15, 0x0, sum = 3
6462 12:12:24.913202 16, 0x0, sum = 4
6463 12:12:24.913273 best_step = 14
6464 12:12:24.913332
6465 12:12:24.916174 ==
6466 12:12:24.916261 Dram Type= 6, Freq= 0, CH_0, rank 0
6467 12:12:24.923049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 12:12:24.923131 ==
6469 12:12:24.923197 RX Vref Scan: 1
6470 12:12:24.923258
6471 12:12:24.926048 RX Vref 0 -> 0, step: 1
6472 12:12:24.926129
6473 12:12:24.929661 RX Delay -359 -> 252, step: 8
6474 12:12:24.929744
6475 12:12:24.932970 Set Vref, RX VrefLevel [Byte0]: 61
6476 12:12:24.936112 [Byte1]: 53
6477 12:12:24.939565
6478 12:12:24.939646 Final RX Vref Byte 0 = 61 to rank0
6479 12:12:24.943497 Final RX Vref Byte 1 = 53 to rank0
6480 12:12:24.946499 Final RX Vref Byte 0 = 61 to rank1
6481 12:12:24.949891 Final RX Vref Byte 1 = 53 to rank1==
6482 12:12:24.952877 Dram Type= 6, Freq= 0, CH_0, rank 0
6483 12:12:24.959702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 12:12:24.959810 ==
6485 12:12:24.959891 DQS Delay:
6486 12:12:24.963011 DQS0 = 60, DQS1 = 68
6487 12:12:24.963093 DQM Delay:
6488 12:12:24.963158 DQM0 = 14, DQM1 = 13
6489 12:12:24.966227 DQ Delay:
6490 12:12:24.969670 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =12
6491 12:12:24.973050 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6492 12:12:24.973132 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6493 12:12:24.976551 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6494 12:12:24.979518
6495 12:12:24.979590
6496 12:12:24.986008 [DQSOSCAuto] RK0, (LSB)MR18= 0x8a88, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
6497 12:12:24.989643 CH0 RK0: MR19=C0C, MR18=8A88
6498 12:12:24.996049 CH0_RK0: MR19=0xC0C, MR18=0x8A88, DQSOSC=392, MR23=63, INC=384, DEC=256
6499 12:12:24.996127 ==
6500 12:12:24.999378 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 12:12:25.002821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 12:12:25.002914 ==
6503 12:12:25.006209 [Gating] SW mode calibration
6504 12:12:25.012811 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6505 12:12:25.019771 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6506 12:12:25.023025 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6507 12:12:25.026149 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6508 12:12:25.029638 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6509 12:12:25.036114 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6510 12:12:25.039724 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6511 12:12:25.042914 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6512 12:12:25.049139 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6513 12:12:25.052580 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6514 12:12:25.056035 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6515 12:12:25.059448 Total UI for P1: 0, mck2ui 16
6516 12:12:25.062746 best dqsien dly found for B0: ( 0, 14, 24)
6517 12:12:25.065832 Total UI for P1: 0, mck2ui 16
6518 12:12:25.069381 best dqsien dly found for B1: ( 0, 14, 24)
6519 12:12:25.072647 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6520 12:12:25.079169 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6521 12:12:25.079240
6522 12:12:25.082700 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6523 12:12:25.085837 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6524 12:12:25.089252 [Gating] SW calibration Done
6525 12:12:25.089327 ==
6526 12:12:25.092435 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 12:12:25.095748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 12:12:25.095819 ==
6529 12:12:25.098976 RX Vref Scan: 0
6530 12:12:25.099049
6531 12:12:25.099111 RX Vref 0 -> 0, step: 1
6532 12:12:25.099171
6533 12:12:25.102235 RX Delay -410 -> 252, step: 16
6534 12:12:25.105699 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6535 12:12:25.112258 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6536 12:12:25.115284 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6537 12:12:25.118938 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6538 12:12:25.125380 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6539 12:12:25.128690 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6540 12:12:25.132126 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6541 12:12:25.135454 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6542 12:12:25.138478 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6543 12:12:25.145348 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6544 12:12:25.148650 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6545 12:12:25.151980 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6546 12:12:25.158321 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6547 12:12:25.161778 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6548 12:12:25.165389 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6549 12:12:25.168562 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6550 12:12:25.171793 ==
6551 12:12:25.171870 Dram Type= 6, Freq= 0, CH_0, rank 1
6552 12:12:25.178441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6553 12:12:25.178518 ==
6554 12:12:25.178582 DQS Delay:
6555 12:12:25.181592 DQS0 = 59, DQS1 = 59
6556 12:12:25.181662 DQM Delay:
6557 12:12:25.184910 DQM0 = 16, DQM1 = 10
6558 12:12:25.184980 DQ Delay:
6559 12:12:25.188507 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6560 12:12:25.191558 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6561 12:12:25.194824 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6562 12:12:25.198177 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6563 12:12:25.198260
6564 12:12:25.198328
6565 12:12:25.198387 ==
6566 12:12:25.201588 Dram Type= 6, Freq= 0, CH_0, rank 1
6567 12:12:25.204910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6568 12:12:25.204991 ==
6569 12:12:25.205057
6570 12:12:25.205117
6571 12:12:25.207929 TX Vref Scan disable
6572 12:12:25.207998 == TX Byte 0 ==
6573 12:12:25.214547 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6574 12:12:25.217884 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6575 12:12:25.217958 == TX Byte 1 ==
6576 12:12:25.224575 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6577 12:12:25.228143 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6578 12:12:25.228212 ==
6579 12:12:25.231320 Dram Type= 6, Freq= 0, CH_0, rank 1
6580 12:12:25.234646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6581 12:12:25.234719 ==
6582 12:12:25.234780
6583 12:12:25.234844
6584 12:12:25.237824 TX Vref Scan disable
6585 12:12:25.237890 == TX Byte 0 ==
6586 12:12:25.244674 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6587 12:12:25.247684 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6588 12:12:25.247771 == TX Byte 1 ==
6589 12:12:25.254558 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6590 12:12:25.257650 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6591 12:12:25.257745
6592 12:12:25.257824 [DATLAT]
6593 12:12:25.261240 Freq=400, CH0 RK1
6594 12:12:25.261333
6595 12:12:25.261413 DATLAT Default: 0xe
6596 12:12:25.264496 0, 0xFFFF, sum = 0
6597 12:12:25.264590 1, 0xFFFF, sum = 0
6598 12:12:25.267666 2, 0xFFFF, sum = 0
6599 12:12:25.267773 3, 0xFFFF, sum = 0
6600 12:12:25.271165 4, 0xFFFF, sum = 0
6601 12:12:25.271271 5, 0xFFFF, sum = 0
6602 12:12:25.274306 6, 0xFFFF, sum = 0
6603 12:12:25.274425 7, 0xFFFF, sum = 0
6604 12:12:25.277788 8, 0xFFFF, sum = 0
6605 12:12:25.281329 9, 0xFFFF, sum = 0
6606 12:12:25.281781 10, 0xFFFF, sum = 0
6607 12:12:25.284521 11, 0xFFFF, sum = 0
6608 12:12:25.284965 12, 0xFFFF, sum = 0
6609 12:12:25.288025 13, 0x0, sum = 1
6610 12:12:25.288457 14, 0x0, sum = 2
6611 12:12:25.291300 15, 0x0, sum = 3
6612 12:12:25.291728 16, 0x0, sum = 4
6613 12:12:25.292074 best_step = 14
6614 12:12:25.294427
6615 12:12:25.294848 ==
6616 12:12:25.298029 Dram Type= 6, Freq= 0, CH_0, rank 1
6617 12:12:25.301241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6618 12:12:25.301711 ==
6619 12:12:25.302056 RX Vref Scan: 0
6620 12:12:25.302376
6621 12:12:25.304495 RX Vref 0 -> 0, step: 1
6622 12:12:25.304920
6623 12:12:25.307756 RX Delay -359 -> 252, step: 8
6624 12:12:25.314805 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6625 12:12:25.318031 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6626 12:12:25.321651 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6627 12:12:25.324782 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6628 12:12:25.331241 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6629 12:12:25.334679 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6630 12:12:25.338302 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6631 12:12:25.341088 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6632 12:12:25.348101 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6633 12:12:25.351322 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6634 12:12:25.354759 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6635 12:12:25.361358 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6636 12:12:25.364360 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6637 12:12:25.368000 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6638 12:12:25.371162 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6639 12:12:25.377682 iDelay=217, Bit 15, Center -52 (-303 ~ 200) 504
6640 12:12:25.378073 ==
6641 12:12:25.381354 Dram Type= 6, Freq= 0, CH_0, rank 1
6642 12:12:25.384500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 12:12:25.384934 ==
6644 12:12:25.385285 DQS Delay:
6645 12:12:25.387821 DQS0 = 60, DQS1 = 72
6646 12:12:25.388215 DQM Delay:
6647 12:12:25.391088 DQM0 = 11, DQM1 = 17
6648 12:12:25.391543 DQ Delay:
6649 12:12:25.394551 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6650 12:12:25.397765 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6651 12:12:25.401030 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =8
6652 12:12:25.404430 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =20
6653 12:12:25.404881
6654 12:12:25.405238
6655 12:12:25.410949 [DQSOSCAuto] RK1, (LSB)MR18= 0xc379, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6656 12:12:25.414351 CH0 RK1: MR19=C0C, MR18=C379
6657 12:12:25.420880 CH0_RK1: MR19=0xC0C, MR18=0xC379, DQSOSC=385, MR23=63, INC=398, DEC=265
6658 12:12:25.424643 [RxdqsGatingPostProcess] freq 400
6659 12:12:25.430939 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6660 12:12:25.434303 best DQS0 dly(2T, 0.5T) = (0, 10)
6661 12:12:25.434921 best DQS1 dly(2T, 0.5T) = (0, 10)
6662 12:12:25.437417 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6663 12:12:25.440792 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6664 12:12:25.444080 best DQS0 dly(2T, 0.5T) = (0, 10)
6665 12:12:25.447366 best DQS1 dly(2T, 0.5T) = (0, 10)
6666 12:12:25.450680 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6667 12:12:25.454017 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6668 12:12:25.457216 Pre-setting of DQS Precalculation
6669 12:12:25.463770 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6670 12:12:25.464215 ==
6671 12:12:25.467126 Dram Type= 6, Freq= 0, CH_1, rank 0
6672 12:12:25.470760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6673 12:12:25.471203 ==
6674 12:12:25.477310 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6675 12:12:25.480470 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6676 12:12:25.483655 [CA 0] Center 36 (8~64) winsize 57
6677 12:12:25.487208 [CA 1] Center 36 (8~64) winsize 57
6678 12:12:25.490345 [CA 2] Center 36 (8~64) winsize 57
6679 12:12:25.493769 [CA 3] Center 36 (8~64) winsize 57
6680 12:12:25.497161 [CA 4] Center 36 (8~64) winsize 57
6681 12:12:25.500420 [CA 5] Center 36 (8~64) winsize 57
6682 12:12:25.500870
6683 12:12:25.503919 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6684 12:12:25.504393
6685 12:12:25.506930 [CATrainingPosCal] consider 1 rank data
6686 12:12:25.510427 u2DelayCellTimex100 = 270/100 ps
6687 12:12:25.513414 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 12:12:25.516982 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 12:12:25.523844 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 12:12:25.526775 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 12:12:25.530269 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 12:12:25.533470 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 12:12:25.533984
6694 12:12:25.536821 CA PerBit enable=1, Macro0, CA PI delay=36
6695 12:12:25.537335
6696 12:12:25.540148 [CBTSetCACLKResult] CA Dly = 36
6697 12:12:25.540584 CS Dly: 1 (0~32)
6698 12:12:25.543821 ==
6699 12:12:25.544401 Dram Type= 6, Freq= 0, CH_1, rank 1
6700 12:12:25.549815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 12:12:25.550272 ==
6702 12:12:25.553330 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6703 12:12:25.559982 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6704 12:12:25.563436 [CA 0] Center 36 (8~64) winsize 57
6705 12:12:25.566711 [CA 1] Center 36 (8~64) winsize 57
6706 12:12:25.569919 [CA 2] Center 36 (8~64) winsize 57
6707 12:12:25.573077 [CA 3] Center 36 (8~64) winsize 57
6708 12:12:25.576321 [CA 4] Center 36 (8~64) winsize 57
6709 12:12:25.579636 [CA 5] Center 36 (8~64) winsize 57
6710 12:12:25.580083
6711 12:12:25.582907 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6712 12:12:25.583384
6713 12:12:25.586485 [CATrainingPosCal] consider 2 rank data
6714 12:12:25.589704 u2DelayCellTimex100 = 270/100 ps
6715 12:12:25.592954 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 12:12:25.596407 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 12:12:25.599458 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 12:12:25.603207 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 12:12:25.609456 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 12:12:25.612799 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 12:12:25.613271
6722 12:12:25.616295 CA PerBit enable=1, Macro0, CA PI delay=36
6723 12:12:25.616703
6724 12:12:25.619822 [CBTSetCACLKResult] CA Dly = 36
6725 12:12:25.620264 CS Dly: 1 (0~32)
6726 12:12:25.620649
6727 12:12:25.622939 ----->DramcWriteLeveling(PI) begin...
6728 12:12:25.623420 ==
6729 12:12:25.626061 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 12:12:25.633030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 12:12:25.633659 ==
6732 12:12:25.636242 Write leveling (Byte 0): 40 => 8
6733 12:12:25.636686 Write leveling (Byte 1): 40 => 8
6734 12:12:25.639471 DramcWriteLeveling(PI) end<-----
6735 12:12:25.639945
6736 12:12:25.643307 ==
6737 12:12:25.643856 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 12:12:25.649395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 12:12:25.650010 ==
6740 12:12:25.652608 [Gating] SW mode calibration
6741 12:12:25.659443 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6742 12:12:25.662898 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6743 12:12:25.669528 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6744 12:12:25.672608 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6745 12:12:25.675981 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6746 12:12:25.682689 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6747 12:12:25.686344 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6748 12:12:25.689319 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6749 12:12:25.695842 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6750 12:12:25.699334 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6751 12:12:25.702450 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6752 12:12:25.705925 Total UI for P1: 0, mck2ui 16
6753 12:12:25.709027 best dqsien dly found for B0: ( 0, 14, 24)
6754 12:12:25.712445 Total UI for P1: 0, mck2ui 16
6755 12:12:25.716067 best dqsien dly found for B1: ( 0, 14, 24)
6756 12:12:25.719219 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6757 12:12:25.722347 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6758 12:12:25.722822
6759 12:12:25.725855 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6760 12:12:25.732673 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6761 12:12:25.733236 [Gating] SW calibration Done
6762 12:12:25.735947 ==
6763 12:12:25.736429 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 12:12:25.742642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 12:12:25.743407 ==
6766 12:12:25.743830 RX Vref Scan: 0
6767 12:12:25.744150
6768 12:12:25.745819 RX Vref 0 -> 0, step: 1
6769 12:12:25.746242
6770 12:12:25.748976 RX Delay -410 -> 252, step: 16
6771 12:12:25.752119 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6772 12:12:25.755759 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6773 12:12:25.762305 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6774 12:12:25.765378 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6775 12:12:25.768963 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6776 12:12:25.772239 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6777 12:12:25.778872 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6778 12:12:25.782194 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6779 12:12:25.785562 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6780 12:12:25.788638 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6781 12:12:25.795786 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6782 12:12:25.798696 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6783 12:12:25.802027 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6784 12:12:25.805407 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6785 12:12:25.812001 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6786 12:12:25.815456 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6787 12:12:25.815930 ==
6788 12:12:25.818775 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 12:12:25.821808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 12:12:25.822289 ==
6791 12:12:25.825278 DQS Delay:
6792 12:12:25.825962 DQS0 = 51, DQS1 = 67
6793 12:12:25.828293 DQM Delay:
6794 12:12:25.828766 DQM0 = 13, DQM1 = 18
6795 12:12:25.831843 DQ Delay:
6796 12:12:25.832317 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6797 12:12:25.835174 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6798 12:12:25.838197 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6799 12:12:25.841566 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6800 12:12:25.842021
6801 12:12:25.842374
6802 12:12:25.842715 ==
6803 12:12:25.844962 Dram Type= 6, Freq= 0, CH_1, rank 0
6804 12:12:25.851582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6805 12:12:25.852160 ==
6806 12:12:25.852507
6807 12:12:25.852872
6808 12:12:25.853177 TX Vref Scan disable
6809 12:12:25.855271 == TX Byte 0 ==
6810 12:12:25.858464 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6811 12:12:25.861871 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6812 12:12:25.864874 == TX Byte 1 ==
6813 12:12:25.868233 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6814 12:12:25.871624 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6815 12:12:25.874923 ==
6816 12:12:25.875375 Dram Type= 6, Freq= 0, CH_1, rank 0
6817 12:12:25.881457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 12:12:25.881979 ==
6819 12:12:25.882489
6820 12:12:25.882978
6821 12:12:25.884776 TX Vref Scan disable
6822 12:12:25.885221 == TX Byte 0 ==
6823 12:12:25.888095 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6824 12:12:25.894707 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6825 12:12:25.895128 == TX Byte 1 ==
6826 12:12:25.898267 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6827 12:12:25.901397 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6828 12:12:25.904908
6829 12:12:25.905552 [DATLAT]
6830 12:12:25.906062 Freq=400, CH1 RK0
6831 12:12:25.906418
6832 12:12:25.908297 DATLAT Default: 0xf
6833 12:12:25.908792 0, 0xFFFF, sum = 0
6834 12:12:25.911529 1, 0xFFFF, sum = 0
6835 12:12:25.911990 2, 0xFFFF, sum = 0
6836 12:12:25.914877 3, 0xFFFF, sum = 0
6837 12:12:25.915325 4, 0xFFFF, sum = 0
6838 12:12:25.918030 5, 0xFFFF, sum = 0
6839 12:12:25.921690 6, 0xFFFF, sum = 0
6840 12:12:25.922262 7, 0xFFFF, sum = 0
6841 12:12:25.924852 8, 0xFFFF, sum = 0
6842 12:12:25.925446 9, 0xFFFF, sum = 0
6843 12:12:25.928199 10, 0xFFFF, sum = 0
6844 12:12:25.928809 11, 0xFFFF, sum = 0
6845 12:12:25.931299 12, 0xFFFF, sum = 0
6846 12:12:25.931747 13, 0x0, sum = 1
6847 12:12:25.934618 14, 0x0, sum = 2
6848 12:12:25.935103 15, 0x0, sum = 3
6849 12:12:25.937795 16, 0x0, sum = 4
6850 12:12:25.938245 best_step = 14
6851 12:12:25.938693
6852 12:12:25.939250 ==
6853 12:12:25.941049 Dram Type= 6, Freq= 0, CH_1, rank 0
6854 12:12:25.944431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 12:12:25.944905 ==
6856 12:12:25.947888 RX Vref Scan: 1
6857 12:12:25.948341
6858 12:12:25.950915 RX Vref 0 -> 0, step: 1
6859 12:12:25.951383
6860 12:12:25.954712 RX Delay -375 -> 252, step: 8
6861 12:12:25.955286
6862 12:12:25.955648 Set Vref, RX VrefLevel [Byte0]: 57
6863 12:12:25.957909 [Byte1]: 50
6864 12:12:25.963764
6865 12:12:25.964204 Final RX Vref Byte 0 = 57 to rank0
6866 12:12:25.966900 Final RX Vref Byte 1 = 50 to rank0
6867 12:12:25.970415 Final RX Vref Byte 0 = 57 to rank1
6868 12:12:25.973620 Final RX Vref Byte 1 = 50 to rank1==
6869 12:12:25.977151 Dram Type= 6, Freq= 0, CH_1, rank 0
6870 12:12:25.983696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 12:12:25.984130 ==
6872 12:12:25.984475 DQS Delay:
6873 12:12:25.986847 DQS0 = 56, DQS1 = 64
6874 12:12:25.987375 DQM Delay:
6875 12:12:25.987718 DQM0 = 13, DQM1 = 10
6876 12:12:25.990059 DQ Delay:
6877 12:12:25.993248 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6878 12:12:25.993742 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6879 12:12:25.996522 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6880 12:12:25.999989 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6881 12:12:26.000415
6882 12:12:26.003696
6883 12:12:26.010003 [DQSOSCAuto] RK0, (LSB)MR18= 0x5c6f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
6884 12:12:26.013602 CH1 RK0: MR19=C0C, MR18=5C6F
6885 12:12:26.019792 CH1_RK0: MR19=0xC0C, MR18=0x5C6F, DQSOSC=395, MR23=63, INC=378, DEC=252
6886 12:12:26.020223 ==
6887 12:12:26.023286 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 12:12:26.026657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 12:12:26.027224 ==
6890 12:12:26.030105 [Gating] SW mode calibration
6891 12:12:26.036289 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6892 12:12:26.043097 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6893 12:12:26.046268 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6894 12:12:26.049366 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6895 12:12:26.056089 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6896 12:12:26.059668 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6897 12:12:26.062605 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6898 12:12:26.069162 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6899 12:12:26.072540 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6900 12:12:26.075964 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6901 12:12:26.082539 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6902 12:12:26.082965 Total UI for P1: 0, mck2ui 16
6903 12:12:26.089022 best dqsien dly found for B0: ( 0, 14, 24)
6904 12:12:26.089631 Total UI for P1: 0, mck2ui 16
6905 12:12:26.095543 best dqsien dly found for B1: ( 0, 14, 24)
6906 12:12:26.099046 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6907 12:12:26.102203 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6908 12:12:26.102625
6909 12:12:26.105506 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6910 12:12:26.108743 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6911 12:12:26.112222 [Gating] SW calibration Done
6912 12:12:26.112830 ==
6913 12:12:26.115379 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 12:12:26.118687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 12:12:26.119205 ==
6916 12:12:26.122283 RX Vref Scan: 0
6917 12:12:26.122718
6918 12:12:26.123054 RX Vref 0 -> 0, step: 1
6919 12:12:26.123369
6920 12:12:26.125334 RX Delay -410 -> 252, step: 16
6921 12:12:26.131973 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6922 12:12:26.135234 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6923 12:12:26.138791 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6924 12:12:26.142000 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6925 12:12:26.148675 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6926 12:12:26.152014 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6927 12:12:26.155490 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6928 12:12:26.158882 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6929 12:12:26.165640 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6930 12:12:26.168565 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6931 12:12:26.171899 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6932 12:12:26.175292 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6933 12:12:26.181961 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6934 12:12:26.185135 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6935 12:12:26.188493 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6936 12:12:26.195033 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6937 12:12:26.195459 ==
6938 12:12:26.198314 Dram Type= 6, Freq= 0, CH_1, rank 1
6939 12:12:26.201626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6940 12:12:26.202055 ==
6941 12:12:26.202394 DQS Delay:
6942 12:12:26.204957 DQS0 = 59, DQS1 = 59
6943 12:12:26.205380 DQM Delay:
6944 12:12:26.208170 DQM0 = 19, DQM1 = 13
6945 12:12:26.208685 DQ Delay:
6946 12:12:26.211398 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6947 12:12:26.215022 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6948 12:12:26.218152 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6949 12:12:26.221638 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6950 12:12:26.222078
6951 12:12:26.222503
6952 12:12:26.222825 ==
6953 12:12:26.224661 Dram Type= 6, Freq= 0, CH_1, rank 1
6954 12:12:26.228244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6955 12:12:26.228679 ==
6956 12:12:26.229015
6957 12:12:26.229327
6958 12:12:26.231450 TX Vref Scan disable
6959 12:12:26.231874 == TX Byte 0 ==
6960 12:12:26.237927 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6961 12:12:26.241330 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6962 12:12:26.241787 == TX Byte 1 ==
6963 12:12:26.248227 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6964 12:12:26.251515 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6965 12:12:26.251942 ==
6966 12:12:26.254623 Dram Type= 6, Freq= 0, CH_1, rank 1
6967 12:12:26.257976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6968 12:12:26.258400 ==
6969 12:12:26.258738
6970 12:12:26.259054
6971 12:12:26.261098 TX Vref Scan disable
6972 12:12:26.264686 == TX Byte 0 ==
6973 12:12:26.267631 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6974 12:12:26.271091 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6975 12:12:26.271515 == TX Byte 1 ==
6976 12:12:26.277751 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6977 12:12:26.281275 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6978 12:12:26.281741
6979 12:12:26.282085 [DATLAT]
6980 12:12:26.284470 Freq=400, CH1 RK1
6981 12:12:26.284897
6982 12:12:26.285237 DATLAT Default: 0xe
6983 12:12:26.287689 0, 0xFFFF, sum = 0
6984 12:12:26.288122 1, 0xFFFF, sum = 0
6985 12:12:26.291098 2, 0xFFFF, sum = 0
6986 12:12:26.291589 3, 0xFFFF, sum = 0
6987 12:12:26.294240 4, 0xFFFF, sum = 0
6988 12:12:26.297605 5, 0xFFFF, sum = 0
6989 12:12:26.298054 6, 0xFFFF, sum = 0
6990 12:12:26.301080 7, 0xFFFF, sum = 0
6991 12:12:26.301547 8, 0xFFFF, sum = 0
6992 12:12:26.304130 9, 0xFFFF, sum = 0
6993 12:12:26.304647 10, 0xFFFF, sum = 0
6994 12:12:26.307502 11, 0xFFFF, sum = 0
6995 12:12:26.307990 12, 0xFFFF, sum = 0
6996 12:12:26.310927 13, 0x0, sum = 1
6997 12:12:26.311417 14, 0x0, sum = 2
6998 12:12:26.314127 15, 0x0, sum = 3
6999 12:12:26.314636 16, 0x0, sum = 4
7000 12:12:26.317430 best_step = 14
7001 12:12:26.317966
7002 12:12:26.318320 ==
7003 12:12:26.320829 Dram Type= 6, Freq= 0, CH_1, rank 1
7004 12:12:26.324043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7005 12:12:26.324483 ==
7006 12:12:26.324908 RX Vref Scan: 0
7007 12:12:26.325236
7008 12:12:26.327622 RX Vref 0 -> 0, step: 1
7009 12:12:26.328088
7010 12:12:26.330814 RX Delay -359 -> 252, step: 8
7011 12:12:26.338162 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7012 12:12:26.341467 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7013 12:12:26.344564 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7014 12:12:26.347921 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7015 12:12:26.354761 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
7016 12:12:26.358162 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7017 12:12:26.361053 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7018 12:12:26.364551 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7019 12:12:26.371156 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7020 12:12:26.374756 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7021 12:12:26.378085 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7022 12:12:26.384338 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7023 12:12:26.387671 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7024 12:12:26.390898 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7025 12:12:26.394343 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7026 12:12:26.401016 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7027 12:12:26.401446 ==
7028 12:12:26.404651 Dram Type= 6, Freq= 0, CH_1, rank 1
7029 12:12:26.407776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7030 12:12:26.408206 ==
7031 12:12:26.408550 DQS Delay:
7032 12:12:26.410819 DQS0 = 60, DQS1 = 64
7033 12:12:26.411349 DQM Delay:
7034 12:12:26.414157 DQM0 = 12, DQM1 = 10
7035 12:12:26.414581 DQ Delay:
7036 12:12:26.417791 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7037 12:12:26.420954 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7038 12:12:26.424190 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7039 12:12:26.427469 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7040 12:12:26.427893
7041 12:12:26.428233
7042 12:12:26.433838 [DQSOSCAuto] RK1, (LSB)MR18= 0x77a7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 394 ps
7043 12:12:26.437405 CH1 RK1: MR19=C0C, MR18=77A7
7044 12:12:26.443970 CH1_RK1: MR19=0xC0C, MR18=0x77A7, DQSOSC=389, MR23=63, INC=390, DEC=260
7045 12:12:26.447058 [RxdqsGatingPostProcess] freq 400
7046 12:12:26.453617 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7047 12:12:26.457233 best DQS0 dly(2T, 0.5T) = (0, 10)
7048 12:12:26.460646 best DQS1 dly(2T, 0.5T) = (0, 10)
7049 12:12:26.463850 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7050 12:12:26.467035 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7051 12:12:26.467460 best DQS0 dly(2T, 0.5T) = (0, 10)
7052 12:12:26.470210 best DQS1 dly(2T, 0.5T) = (0, 10)
7053 12:12:26.473934 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7054 12:12:26.476890 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7055 12:12:26.480128 Pre-setting of DQS Precalculation
7056 12:12:26.486816 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7057 12:12:26.493568 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7058 12:12:26.500038 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7059 12:12:26.500592
7060 12:12:26.500937
7061 12:12:26.503406 [Calibration Summary] 800 Mbps
7062 12:12:26.503831 CH 0, Rank 0
7063 12:12:26.506909 SW Impedance : PASS
7064 12:12:26.510082 DUTY Scan : NO K
7065 12:12:26.510504 ZQ Calibration : PASS
7066 12:12:26.513358 Jitter Meter : NO K
7067 12:12:26.516430 CBT Training : PASS
7068 12:12:26.516853 Write leveling : PASS
7069 12:12:26.519854 RX DQS gating : PASS
7070 12:12:26.523142 RX DQ/DQS(RDDQC) : PASS
7071 12:12:26.523716 TX DQ/DQS : PASS
7072 12:12:26.526734 RX DATLAT : PASS
7073 12:12:26.529948 RX DQ/DQS(Engine): PASS
7074 12:12:26.530380 TX OE : NO K
7075 12:12:26.533251 All Pass.
7076 12:12:26.533755
7077 12:12:26.534105 CH 0, Rank 1
7078 12:12:26.536437 SW Impedance : PASS
7079 12:12:26.536867 DUTY Scan : NO K
7080 12:12:26.539960 ZQ Calibration : PASS
7081 12:12:26.543200 Jitter Meter : NO K
7082 12:12:26.543628 CBT Training : PASS
7083 12:12:26.546404 Write leveling : NO K
7084 12:12:26.549639 RX DQS gating : PASS
7085 12:12:26.550070 RX DQ/DQS(RDDQC) : PASS
7086 12:12:26.553155 TX DQ/DQS : PASS
7087 12:12:26.553628 RX DATLAT : PASS
7088 12:12:26.556269 RX DQ/DQS(Engine): PASS
7089 12:12:26.559422 TX OE : NO K
7090 12:12:26.559850 All Pass.
7091 12:12:26.560191
7092 12:12:26.562914 CH 1, Rank 0
7093 12:12:26.563344 SW Impedance : PASS
7094 12:12:26.566356 DUTY Scan : NO K
7095 12:12:26.566786 ZQ Calibration : PASS
7096 12:12:26.569429 Jitter Meter : NO K
7097 12:12:26.572905 CBT Training : PASS
7098 12:12:26.573389 Write leveling : PASS
7099 12:12:26.576112 RX DQS gating : PASS
7100 12:12:26.579409 RX DQ/DQS(RDDQC) : PASS
7101 12:12:26.579855 TX DQ/DQS : PASS
7102 12:12:26.582699 RX DATLAT : PASS
7103 12:12:26.585783 RX DQ/DQS(Engine): PASS
7104 12:12:26.586212 TX OE : NO K
7105 12:12:26.589367 All Pass.
7106 12:12:26.589843
7107 12:12:26.590188 CH 1, Rank 1
7108 12:12:26.592630 SW Impedance : PASS
7109 12:12:26.593057 DUTY Scan : NO K
7110 12:12:26.595642 ZQ Calibration : PASS
7111 12:12:26.599160 Jitter Meter : NO K
7112 12:12:26.599586 CBT Training : PASS
7113 12:12:26.602272 Write leveling : NO K
7114 12:12:26.605578 RX DQS gating : PASS
7115 12:12:26.606065 RX DQ/DQS(RDDQC) : PASS
7116 12:12:26.609117 TX DQ/DQS : PASS
7117 12:12:26.612662 RX DATLAT : PASS
7118 12:12:26.613211 RX DQ/DQS(Engine): PASS
7119 12:12:26.615665 TX OE : NO K
7120 12:12:26.616097 All Pass.
7121 12:12:26.616442
7122 12:12:26.618854 DramC Write-DBI off
7123 12:12:26.622378 PER_BANK_REFRESH: Hybrid Mode
7124 12:12:26.622801 TX_TRACKING: ON
7125 12:12:26.632246 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7126 12:12:26.635591 [FAST_K] Save calibration result to emmc
7127 12:12:26.638903 dramc_set_vcore_voltage set vcore to 725000
7128 12:12:26.642394 Read voltage for 1600, 0
7129 12:12:26.642820 Vio18 = 0
7130 12:12:26.643160 Vcore = 725000
7131 12:12:26.645951 Vdram = 0
7132 12:12:26.646371 Vddq = 0
7133 12:12:26.646713 Vmddr = 0
7134 12:12:26.652658 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7135 12:12:26.655590 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7136 12:12:26.659011 MEM_TYPE=3, freq_sel=13
7137 12:12:26.662494 sv_algorithm_assistance_LP4_3733
7138 12:12:26.665508 ============ PULL DRAM RESETB DOWN ============
7139 12:12:26.668930 ========== PULL DRAM RESETB DOWN end =========
7140 12:12:26.675401 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7141 12:12:26.678825 ===================================
7142 12:12:26.679250 LPDDR4 DRAM CONFIGURATION
7143 12:12:26.682272 ===================================
7144 12:12:26.685563 EX_ROW_EN[0] = 0x0
7145 12:12:26.688731 EX_ROW_EN[1] = 0x0
7146 12:12:26.689156 LP4Y_EN = 0x0
7147 12:12:26.691979 WORK_FSP = 0x1
7148 12:12:26.692401 WL = 0x5
7149 12:12:26.695430 RL = 0x5
7150 12:12:26.695856 BL = 0x2
7151 12:12:26.698630 RPST = 0x0
7152 12:12:26.699052 RD_PRE = 0x0
7153 12:12:26.702088 WR_PRE = 0x1
7154 12:12:26.702510 WR_PST = 0x1
7155 12:12:26.705313 DBI_WR = 0x0
7156 12:12:26.705772 DBI_RD = 0x0
7157 12:12:26.708759 OTF = 0x1
7158 12:12:26.712429 ===================================
7159 12:12:26.715290 ===================================
7160 12:12:26.715719 ANA top config
7161 12:12:26.718489 ===================================
7162 12:12:26.722063 DLL_ASYNC_EN = 0
7163 12:12:26.725135 ALL_SLAVE_EN = 0
7164 12:12:26.728347 NEW_RANK_MODE = 1
7165 12:12:26.728777 DLL_IDLE_MODE = 1
7166 12:12:26.731829 LP45_APHY_COMB_EN = 1
7167 12:12:26.735157 TX_ODT_DIS = 0
7168 12:12:26.738457 NEW_8X_MODE = 1
7169 12:12:26.741737 ===================================
7170 12:12:26.745292 ===================================
7171 12:12:26.748225 data_rate = 3200
7172 12:12:26.748653 CKR = 1
7173 12:12:26.751880 DQ_P2S_RATIO = 8
7174 12:12:26.755093 ===================================
7175 12:12:26.758679 CA_P2S_RATIO = 8
7176 12:12:26.761859 DQ_CA_OPEN = 0
7177 12:12:26.765073 DQ_SEMI_OPEN = 0
7178 12:12:26.765532 CA_SEMI_OPEN = 0
7179 12:12:26.768593 CA_FULL_RATE = 0
7180 12:12:26.771516 DQ_CKDIV4_EN = 0
7181 12:12:26.775162 CA_CKDIV4_EN = 0
7182 12:12:26.778501 CA_PREDIV_EN = 0
7183 12:12:26.781582 PH8_DLY = 12
7184 12:12:26.785185 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7185 12:12:26.785651 DQ_AAMCK_DIV = 4
7186 12:12:26.788237 CA_AAMCK_DIV = 4
7187 12:12:26.791676 CA_ADMCK_DIV = 4
7188 12:12:26.795116 DQ_TRACK_CA_EN = 0
7189 12:12:26.798093 CA_PICK = 1600
7190 12:12:26.801570 CA_MCKIO = 1600
7191 12:12:26.804871 MCKIO_SEMI = 0
7192 12:12:26.805299 PLL_FREQ = 3068
7193 12:12:26.808389 DQ_UI_PI_RATIO = 32
7194 12:12:26.811363 CA_UI_PI_RATIO = 0
7195 12:12:26.814827 ===================================
7196 12:12:26.818037 ===================================
7197 12:12:26.821273 memory_type:LPDDR4
7198 12:12:26.821784 GP_NUM : 10
7199 12:12:26.824683 SRAM_EN : 1
7200 12:12:26.828068 MD32_EN : 0
7201 12:12:26.831134 ===================================
7202 12:12:26.831558 [ANA_INIT] >>>>>>>>>>>>>>
7203 12:12:26.834482 <<<<<< [CONFIGURE PHASE]: ANA_TX
7204 12:12:26.837786 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7205 12:12:26.841144 ===================================
7206 12:12:26.844622 data_rate = 3200,PCW = 0X7600
7207 12:12:26.847622 ===================================
7208 12:12:26.851061 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7209 12:12:26.857520 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7210 12:12:26.864220 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7211 12:12:26.867656 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7212 12:12:26.870727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7213 12:12:26.874286 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7214 12:12:26.877410 [ANA_INIT] flow start
7215 12:12:26.877856 [ANA_INIT] PLL >>>>>>>>
7216 12:12:26.880890 [ANA_INIT] PLL <<<<<<<<
7217 12:12:26.883922 [ANA_INIT] MIDPI >>>>>>>>
7218 12:12:26.884345 [ANA_INIT] MIDPI <<<<<<<<
7219 12:12:26.887480 [ANA_INIT] DLL >>>>>>>>
7220 12:12:26.890908 [ANA_INIT] DLL <<<<<<<<
7221 12:12:26.891332 [ANA_INIT] flow end
7222 12:12:26.897551 ============ LP4 DIFF to SE enter ============
7223 12:12:26.900839 ============ LP4 DIFF to SE exit ============
7224 12:12:26.901324 [ANA_INIT] <<<<<<<<<<<<<
7225 12:12:26.904252 [Flow] Enable top DCM control >>>>>
7226 12:12:26.907359 [Flow] Enable top DCM control <<<<<
7227 12:12:26.910826 Enable DLL master slave shuffle
7228 12:12:26.917562 ==============================================================
7229 12:12:26.920670 Gating Mode config
7230 12:12:26.924089 ==============================================================
7231 12:12:26.927428 Config description:
7232 12:12:26.937463 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7233 12:12:26.944091 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7234 12:12:26.947094 SELPH_MODE 0: By rank 1: By Phase
7235 12:12:26.954111 ==============================================================
7236 12:12:26.956953 GAT_TRACK_EN = 1
7237 12:12:26.960307 RX_GATING_MODE = 2
7238 12:12:26.963797 RX_GATING_TRACK_MODE = 2
7239 12:12:26.967027 SELPH_MODE = 1
7240 12:12:26.967455 PICG_EARLY_EN = 1
7241 12:12:26.970235 VALID_LAT_VALUE = 1
7242 12:12:26.977055 ==============================================================
7243 12:12:26.980462 Enter into Gating configuration >>>>
7244 12:12:26.983781 Exit from Gating configuration <<<<
7245 12:12:26.987072 Enter into DVFS_PRE_config >>>>>
7246 12:12:26.996659 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7247 12:12:27.000052 Exit from DVFS_PRE_config <<<<<
7248 12:12:27.003741 Enter into PICG configuration >>>>
7249 12:12:27.006927 Exit from PICG configuration <<<<
7250 12:12:27.009841 [RX_INPUT] configuration >>>>>
7251 12:12:27.013360 [RX_INPUT] configuration <<<<<
7252 12:12:27.016555 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7253 12:12:27.023109 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7254 12:12:27.029909 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7255 12:12:27.036646 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7256 12:12:27.043149 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7257 12:12:27.049682 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7258 12:12:27.052747 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7259 12:12:27.056106 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7260 12:12:27.059674 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7261 12:12:27.065982 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7262 12:12:27.069403 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7263 12:12:27.072675 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7264 12:12:27.076090 ===================================
7265 12:12:27.079421 LPDDR4 DRAM CONFIGURATION
7266 12:12:27.082313 ===================================
7267 12:12:27.082741 EX_ROW_EN[0] = 0x0
7268 12:12:27.085865 EX_ROW_EN[1] = 0x0
7269 12:12:27.086292 LP4Y_EN = 0x0
7270 12:12:27.089027 WORK_FSP = 0x1
7271 12:12:27.092432 WL = 0x5
7272 12:12:27.092858 RL = 0x5
7273 12:12:27.095755 BL = 0x2
7274 12:12:27.096183 RPST = 0x0
7275 12:12:27.098938 RD_PRE = 0x0
7276 12:12:27.099366 WR_PRE = 0x1
7277 12:12:27.102192 WR_PST = 0x1
7278 12:12:27.102618 DBI_WR = 0x0
7279 12:12:27.105947 DBI_RD = 0x0
7280 12:12:27.106533 OTF = 0x1
7281 12:12:27.108943 ===================================
7282 12:12:27.112113 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7283 12:12:27.119161 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7284 12:12:27.122135 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7285 12:12:27.125301 ===================================
7286 12:12:27.128453 LPDDR4 DRAM CONFIGURATION
7287 12:12:27.132063 ===================================
7288 12:12:27.132485 EX_ROW_EN[0] = 0x10
7289 12:12:27.135160 EX_ROW_EN[1] = 0x0
7290 12:12:27.138841 LP4Y_EN = 0x0
7291 12:12:27.139262 WORK_FSP = 0x1
7292 12:12:27.141783 WL = 0x5
7293 12:12:27.142201 RL = 0x5
7294 12:12:27.145195 BL = 0x2
7295 12:12:27.145719 RPST = 0x0
7296 12:12:27.148465 RD_PRE = 0x0
7297 12:12:27.148886 WR_PRE = 0x1
7298 12:12:27.151522 WR_PST = 0x1
7299 12:12:27.151984 DBI_WR = 0x0
7300 12:12:27.154992 DBI_RD = 0x0
7301 12:12:27.155463 OTF = 0x1
7302 12:12:27.158411 ===================================
7303 12:12:27.165057 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7304 12:12:27.165512 ==
7305 12:12:27.168499 Dram Type= 6, Freq= 0, CH_0, rank 0
7306 12:12:27.171656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7307 12:12:27.175004 ==
7308 12:12:27.175432 [Duty_Offset_Calibration]
7309 12:12:27.178468 B0:2 B1:0 CA:3
7310 12:12:27.178894
7311 12:12:27.181624 [DutyScan_Calibration_Flow] k_type=0
7312 12:12:27.190292
7313 12:12:27.190807 ==CLK 0==
7314 12:12:27.193575 Final CLK duty delay cell = 0
7315 12:12:27.196864 [0] MAX Duty = 5031%(X100), DQS PI = 12
7316 12:12:27.199984 [0] MIN Duty = 4907%(X100), DQS PI = 6
7317 12:12:27.200543 [0] AVG Duty = 4969%(X100)
7318 12:12:27.203448
7319 12:12:27.206527 CH0 CLK Duty spec in!! Max-Min= 124%
7320 12:12:27.210295 [DutyScan_Calibration_Flow] ====Done====
7321 12:12:27.210720
7322 12:12:27.213322 [DutyScan_Calibration_Flow] k_type=1
7323 12:12:27.229846
7324 12:12:27.230270 ==DQS 0 ==
7325 12:12:27.233337 Final DQS duty delay cell = 0
7326 12:12:27.236450 [0] MAX Duty = 5094%(X100), DQS PI = 30
7327 12:12:27.240195 [0] MIN Duty = 4875%(X100), DQS PI = 48
7328 12:12:27.243279 [0] AVG Duty = 4984%(X100)
7329 12:12:27.243705
7330 12:12:27.244046 ==DQS 1 ==
7331 12:12:27.246800 Final DQS duty delay cell = 0
7332 12:12:27.249996 [0] MAX Duty = 5156%(X100), DQS PI = 32
7333 12:12:27.253419 [0] MIN Duty = 5031%(X100), DQS PI = 14
7334 12:12:27.256746 [0] AVG Duty = 5093%(X100)
7335 12:12:27.257170
7336 12:12:27.259744 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7337 12:12:27.260168
7338 12:12:27.263493 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7339 12:12:27.266502 [DutyScan_Calibration_Flow] ====Done====
7340 12:12:27.266927
7341 12:12:27.269603 [DutyScan_Calibration_Flow] k_type=3
7342 12:12:27.287080
7343 12:12:27.287506 ==DQM 0 ==
7344 12:12:27.290272 Final DQM duty delay cell = 0
7345 12:12:27.293762 [0] MAX Duty = 5156%(X100), DQS PI = 30
7346 12:12:27.297000 [0] MIN Duty = 4875%(X100), DQS PI = 0
7347 12:12:27.297652 [0] AVG Duty = 5015%(X100)
7348 12:12:27.300253
7349 12:12:27.300682 ==DQM 1 ==
7350 12:12:27.303382 Final DQM duty delay cell = 0
7351 12:12:27.306900 [0] MAX Duty = 4938%(X100), DQS PI = 62
7352 12:12:27.310055 [0] MIN Duty = 4813%(X100), DQS PI = 12
7353 12:12:27.313554 [0] AVG Duty = 4875%(X100)
7354 12:12:27.314092
7355 12:12:27.316807 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7356 12:12:27.317273
7357 12:12:27.319968 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7358 12:12:27.323475 [DutyScan_Calibration_Flow] ====Done====
7359 12:12:27.323904
7360 12:12:27.326704 [DutyScan_Calibration_Flow] k_type=2
7361 12:12:27.343144
7362 12:12:27.343584 ==DQ 0 ==
7363 12:12:27.346778 Final DQ duty delay cell = -4
7364 12:12:27.349903 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7365 12:12:27.353130 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7366 12:12:27.356193 [-4] AVG Duty = 4938%(X100)
7367 12:12:27.356618
7368 12:12:27.356956 ==DQ 1 ==
7369 12:12:27.359764 Final DQ duty delay cell = 0
7370 12:12:27.362847 [0] MAX Duty = 5156%(X100), DQS PI = 58
7371 12:12:27.366044 [0] MIN Duty = 5000%(X100), DQS PI = 16
7372 12:12:27.369603 [0] AVG Duty = 5078%(X100)
7373 12:12:27.370056
7374 12:12:27.372926 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7375 12:12:27.373352
7376 12:12:27.376239 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7377 12:12:27.379339 [DutyScan_Calibration_Flow] ====Done====
7378 12:12:27.379763 ==
7379 12:12:27.382660 Dram Type= 6, Freq= 0, CH_1, rank 0
7380 12:12:27.386209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7381 12:12:27.386729 ==
7382 12:12:27.389286 [Duty_Offset_Calibration]
7383 12:12:27.389767 B0:1 B1:-2 CA:0
7384 12:12:27.390113
7385 12:12:27.392805 [DutyScan_Calibration_Flow] k_type=0
7386 12:12:27.403654
7387 12:12:27.404077 ==CLK 0==
7388 12:12:27.407033 Final CLK duty delay cell = 0
7389 12:12:27.410337 [0] MAX Duty = 5062%(X100), DQS PI = 20
7390 12:12:27.413578 [0] MIN Duty = 4844%(X100), DQS PI = 60
7391 12:12:27.414022 [0] AVG Duty = 4953%(X100)
7392 12:12:27.416959
7393 12:12:27.420416 CH1 CLK Duty spec in!! Max-Min= 218%
7394 12:12:27.423642 [DutyScan_Calibration_Flow] ====Done====
7395 12:12:27.424018
7396 12:12:27.426705 [DutyScan_Calibration_Flow] k_type=1
7397 12:12:27.443527
7398 12:12:27.443979 ==DQS 0 ==
7399 12:12:27.446699 Final DQS duty delay cell = 0
7400 12:12:27.450000 [0] MAX Duty = 5187%(X100), DQS PI = 24
7401 12:12:27.453264 [0] MIN Duty = 5062%(X100), DQS PI = 48
7402 12:12:27.453870 [0] AVG Duty = 5124%(X100)
7403 12:12:27.456871
7404 12:12:27.457318 ==DQS 1 ==
7405 12:12:27.460041 Final DQS duty delay cell = 0
7406 12:12:27.463194 [0] MAX Duty = 5062%(X100), DQS PI = 0
7407 12:12:27.466528 [0] MIN Duty = 4844%(X100), DQS PI = 26
7408 12:12:27.469791 [0] AVG Duty = 4953%(X100)
7409 12:12:27.470291
7410 12:12:27.473227 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7411 12:12:27.473797
7412 12:12:27.476777 CH1 DQS 1 Duty spec in!! Max-Min= 218%
7413 12:12:27.480177 [DutyScan_Calibration_Flow] ====Done====
7414 12:12:27.480826
7415 12:12:27.483136 [DutyScan_Calibration_Flow] k_type=3
7416 12:12:27.500008
7417 12:12:27.500703 ==DQM 0 ==
7418 12:12:27.503766 Final DQM duty delay cell = 0
7419 12:12:27.506669 [0] MAX Duty = 5031%(X100), DQS PI = 24
7420 12:12:27.509978 [0] MIN Duty = 4813%(X100), DQS PI = 56
7421 12:12:27.513141 [0] AVG Duty = 4922%(X100)
7422 12:12:27.513772
7423 12:12:27.514323 ==DQM 1 ==
7424 12:12:27.516701 Final DQM duty delay cell = 0
7425 12:12:27.520124 [0] MAX Duty = 5062%(X100), DQS PI = 34
7426 12:12:27.523417 [0] MIN Duty = 4875%(X100), DQS PI = 24
7427 12:12:27.526481 [0] AVG Duty = 4968%(X100)
7428 12:12:27.527002
7429 12:12:27.530082 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7430 12:12:27.530531
7431 12:12:27.533135 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7432 12:12:27.536682 [DutyScan_Calibration_Flow] ====Done====
7433 12:12:27.537168
7434 12:12:27.540153 [DutyScan_Calibration_Flow] k_type=2
7435 12:12:27.556794
7436 12:12:27.557337 ==DQ 0 ==
7437 12:12:27.560290 Final DQ duty delay cell = 0
7438 12:12:27.563741 [0] MAX Duty = 5093%(X100), DQS PI = 22
7439 12:12:27.567085 [0] MIN Duty = 4907%(X100), DQS PI = 48
7440 12:12:27.567513 [0] AVG Duty = 5000%(X100)
7441 12:12:27.570459
7442 12:12:27.570883 ==DQ 1 ==
7443 12:12:27.573426 Final DQ duty delay cell = 0
7444 12:12:27.576884 [0] MAX Duty = 5125%(X100), DQS PI = 34
7445 12:12:27.580029 [0] MIN Duty = 4969%(X100), DQS PI = 24
7446 12:12:27.580466 [0] AVG Duty = 5047%(X100)
7447 12:12:27.580808
7448 12:12:27.583597 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7449 12:12:27.586768
7450 12:12:27.590247 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7451 12:12:27.593372 [DutyScan_Calibration_Flow] ====Done====
7452 12:12:27.596862 nWR fixed to 30
7453 12:12:27.597300 [ModeRegInit_LP4] CH0 RK0
7454 12:12:27.600189 [ModeRegInit_LP4] CH0 RK1
7455 12:12:27.603458 [ModeRegInit_LP4] CH1 RK0
7456 12:12:27.603884 [ModeRegInit_LP4] CH1 RK1
7457 12:12:27.606893 match AC timing 5
7458 12:12:27.610054 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7459 12:12:27.616679 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7460 12:12:27.620180 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7461 12:12:27.626795 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7462 12:12:27.629884 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7463 12:12:27.630311 [MiockJmeterHQA]
7464 12:12:27.630646
7465 12:12:27.633300 [DramcMiockJmeter] u1RxGatingPI = 0
7466 12:12:27.636740 0 : 4257, 4032
7467 12:12:27.637171 4 : 4257, 4032
7468 12:12:27.637547 8 : 4259, 4031
7469 12:12:27.639859 12 : 4255, 4029
7470 12:12:27.640427 16 : 4257, 4030
7471 12:12:27.643397 20 : 4254, 4029
7472 12:12:27.643827 24 : 4259, 4031
7473 12:12:27.646456 28 : 4255, 4029
7474 12:12:27.646890 32 : 4365, 4140
7475 12:12:27.649541 36 : 4254, 4029
7476 12:12:27.649978 40 : 4255, 4029
7477 12:12:27.652917 44 : 4363, 4139
7478 12:12:27.653346 48 : 4254, 4029
7479 12:12:27.653749 52 : 4257, 4029
7480 12:12:27.656054 56 : 4257, 4032
7481 12:12:27.656485 60 : 4366, 4140
7482 12:12:27.659396 64 : 4255, 4029
7483 12:12:27.659831 68 : 4363, 4140
7484 12:12:27.662631 72 : 4252, 4029
7485 12:12:27.663077 76 : 4252, 4029
7486 12:12:27.666159 80 : 4249, 4027
7487 12:12:27.666592 84 : 4363, 4140
7488 12:12:27.666938 88 : 4255, 4029
7489 12:12:27.669354 92 : 4255, 4029
7490 12:12:27.669872 96 : 4253, 4029
7491 12:12:27.672674 100 : 4254, 4030
7492 12:12:27.673225 104 : 4253, 3605
7493 12:12:27.676030 108 : 4363, 4
7494 12:12:27.676539 112 : 4363, 0
7495 12:12:27.676892 116 : 4250, 0
7496 12:12:27.679408 120 : 4253, 0
7497 12:12:27.679843 124 : 4255, 0
7498 12:12:27.682769 128 : 4363, 0
7499 12:12:27.683201 132 : 4255, 0
7500 12:12:27.683546 136 : 4366, 0
7501 12:12:27.686040 140 : 4254, 0
7502 12:12:27.686476 144 : 4252, 0
7503 12:12:27.689220 148 : 4252, 0
7504 12:12:27.689701 152 : 4365, 0
7505 12:12:27.690056 156 : 4252, 0
7506 12:12:27.692570 160 : 4253, 0
7507 12:12:27.693005 164 : 4363, 0
7508 12:12:27.693352 168 : 4254, 0
7509 12:12:27.695434 172 : 4252, 0
7510 12:12:27.696012 176 : 4360, 0
7511 12:12:27.699202 180 : 4363, 0
7512 12:12:27.699638 184 : 4363, 0
7513 12:12:27.699987 188 : 4360, 0
7514 12:12:27.702620 192 : 4252, 0
7515 12:12:27.703057 196 : 4255, 0
7516 12:12:27.705602 200 : 4252, 0
7517 12:12:27.706035 204 : 4255, 0
7518 12:12:27.706383 208 : 4255, 0
7519 12:12:27.708913 212 : 4363, 0
7520 12:12:27.709346 216 : 4255, 0
7521 12:12:27.712462 220 : 4253, 0
7522 12:12:27.712898 224 : 4253, 0
7523 12:12:27.713300 228 : 4253, 0
7524 12:12:27.715542 232 : 4254, 0
7525 12:12:27.716079 236 : 4253, 1126
7526 12:12:27.719018 240 : 4365, 4140
7527 12:12:27.719454 244 : 4250, 4027
7528 12:12:27.722165 248 : 4252, 4029
7529 12:12:27.722604 252 : 4255, 4029
7530 12:12:27.725572 256 : 4253, 4029
7531 12:12:27.726008 260 : 4252, 4029
7532 12:12:27.726360 264 : 4255, 4029
7533 12:12:27.729020 268 : 4363, 4140
7534 12:12:27.729458 272 : 4255, 4029
7535 12:12:27.732146 276 : 4254, 4030
7536 12:12:27.732607 280 : 4255, 4029
7537 12:12:27.735413 284 : 4255, 4029
7538 12:12:27.735851 288 : 4253, 4029
7539 12:12:27.738779 292 : 4257, 4032
7540 12:12:27.739216 296 : 4365, 4140
7541 12:12:27.742229 300 : 4252, 4029
7542 12:12:27.742678 304 : 4250, 4027
7543 12:12:27.745360 308 : 4258, 4032
7544 12:12:27.745820 312 : 4363, 4138
7545 12:12:27.748779 316 : 4255, 4029
7546 12:12:27.749282 320 : 4253, 4029
7547 12:12:27.751924 324 : 4255, 4029
7548 12:12:27.752444 328 : 4254, 4030
7549 12:12:27.752939 332 : 4363, 4139
7550 12:12:27.755392 336 : 4252, 4029
7551 12:12:27.755830 340 : 4255, 4029
7552 12:12:27.758877 344 : 4258, 4032
7553 12:12:27.759314 348 : 4365, 4140
7554 12:12:27.762032 352 : 4365, 4102
7555 12:12:27.762467 356 : 4255, 2704
7556 12:12:27.765455 360 : 4253, 0
7557 12:12:27.765932
7558 12:12:27.766274 MIOCK jitter meter ch=0
7559 12:12:27.766597
7560 12:12:27.768995 1T = (360-108) = 252 dly cells
7561 12:12:27.775275 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7562 12:12:27.775784 ==
7563 12:12:27.778840 Dram Type= 6, Freq= 0, CH_0, rank 0
7564 12:12:27.782016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7565 12:12:27.782451 ==
7566 12:12:27.788497 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7567 12:12:27.791840 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7568 12:12:27.798217 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7569 12:12:27.801590 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7570 12:12:27.811848 [CA 0] Center 44 (14~75) winsize 62
7571 12:12:27.814972 [CA 1] Center 43 (13~74) winsize 62
7572 12:12:27.818339 [CA 2] Center 40 (11~69) winsize 59
7573 12:12:27.821854 [CA 3] Center 39 (10~68) winsize 59
7574 12:12:27.825159 [CA 4] Center 37 (8~67) winsize 60
7575 12:12:27.828529 [CA 5] Center 37 (7~67) winsize 61
7576 12:12:27.828955
7577 12:12:27.831797 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7578 12:12:27.832223
7579 12:12:27.838367 [CATrainingPosCal] consider 1 rank data
7580 12:12:27.838791 u2DelayCellTimex100 = 258/100 ps
7581 12:12:27.844974 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7582 12:12:27.848291 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7583 12:12:27.851742 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7584 12:12:27.854750 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7585 12:12:27.858189 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7586 12:12:27.861568 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7587 12:12:27.861996
7588 12:12:27.864798 CA PerBit enable=1, Macro0, CA PI delay=37
7589 12:12:27.865220
7590 12:12:27.867986 [CBTSetCACLKResult] CA Dly = 37
7591 12:12:27.871125 CS Dly: 11 (0~42)
7592 12:12:27.874379 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7593 12:12:27.877868 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7594 12:12:27.878293 ==
7595 12:12:27.881407 Dram Type= 6, Freq= 0, CH_0, rank 1
7596 12:12:27.887847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7597 12:12:27.888274 ==
7598 12:12:27.891063 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7599 12:12:27.897798 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7600 12:12:27.901207 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7601 12:12:27.907476 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7602 12:12:27.915810 [CA 0] Center 44 (14~74) winsize 61
7603 12:12:27.918775 [CA 1] Center 43 (13~74) winsize 62
7604 12:12:27.922292 [CA 2] Center 39 (10~68) winsize 59
7605 12:12:27.925674 [CA 3] Center 39 (10~68) winsize 59
7606 12:12:27.928843 [CA 4] Center 36 (7~66) winsize 60
7607 12:12:27.932192 [CA 5] Center 36 (7~66) winsize 60
7608 12:12:27.932668
7609 12:12:27.935404 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7610 12:12:27.935833
7611 12:12:27.941910 [CATrainingPosCal] consider 2 rank data
7612 12:12:27.942342 u2DelayCellTimex100 = 258/100 ps
7613 12:12:27.948581 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7614 12:12:27.952040 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7615 12:12:27.955450 CA2 delay=39 (11~68),Diff = 3 PI (11 cell)
7616 12:12:27.958809 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7617 12:12:27.961852 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7618 12:12:27.965146 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7619 12:12:27.965614
7620 12:12:27.968773 CA PerBit enable=1, Macro0, CA PI delay=36
7621 12:12:27.969201
7622 12:12:27.971940 [CBTSetCACLKResult] CA Dly = 36
7623 12:12:27.975080 CS Dly: 11 (0~43)
7624 12:12:27.978542 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7625 12:12:27.981670 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7626 12:12:27.982100
7627 12:12:27.985168 ----->DramcWriteLeveling(PI) begin...
7628 12:12:27.988237 ==
7629 12:12:27.988668 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 12:12:27.994901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 12:12:27.995335 ==
7632 12:12:27.998346 Write leveling (Byte 0): 35 => 35
7633 12:12:28.001937 Write leveling (Byte 1): 30 => 30
7634 12:12:28.004924 DramcWriteLeveling(PI) end<-----
7635 12:12:28.005352
7636 12:12:28.005744 ==
7637 12:12:28.008271 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 12:12:28.011581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 12:12:28.012009 ==
7640 12:12:28.014764 [Gating] SW mode calibration
7641 12:12:28.021450 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7642 12:12:28.028226 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7643 12:12:28.031126 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 12:12:28.034730 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 12:12:28.041076 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7646 12:12:28.044581 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7647 12:12:28.047867 1 4 16 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7648 12:12:28.054362 1 4 20 | B1->B0 | 2726 3434 | 1 1 | (0 0) (1 1)
7649 12:12:28.057836 1 4 24 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
7650 12:12:28.061139 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7651 12:12:28.067714 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7652 12:12:28.071149 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7653 12:12:28.074235 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7654 12:12:28.080838 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7655 12:12:28.084175 1 5 16 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
7656 12:12:28.087355 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7657 12:12:28.090852 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
7658 12:12:28.097472 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7659 12:12:28.100594 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7660 12:12:28.104067 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7661 12:12:28.110703 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7662 12:12:28.114245 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7663 12:12:28.117290 1 6 16 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
7664 12:12:28.123867 1 6 20 | B1->B0 | 3131 4646 | 0 0 | (1 1) (0 0)
7665 12:12:28.127167 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7666 12:12:28.130698 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7667 12:12:28.137447 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7668 12:12:28.140664 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7669 12:12:28.143975 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7670 12:12:28.150938 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7671 12:12:28.153755 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7672 12:12:28.157188 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7673 12:12:28.163881 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7674 12:12:28.167008 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 12:12:28.170380 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 12:12:28.177033 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 12:12:28.180349 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 12:12:28.183507 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 12:12:28.190044 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 12:12:28.193345 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 12:12:28.196771 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 12:12:28.203513 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 12:12:28.206581 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 12:12:28.210155 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 12:12:28.216744 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 12:12:28.220109 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7687 12:12:28.223740 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7688 12:12:28.229968 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7689 12:12:28.230545 Total UI for P1: 0, mck2ui 16
7690 12:12:28.233605 best dqsien dly found for B0: ( 1, 9, 14)
7691 12:12:28.240189 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7692 12:12:28.243434 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7693 12:12:28.246509 Total UI for P1: 0, mck2ui 16
7694 12:12:28.249692 best dqsien dly found for B1: ( 1, 9, 22)
7695 12:12:28.253116 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7696 12:12:28.256649 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7697 12:12:28.257072
7698 12:12:28.259815 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7699 12:12:28.266669 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7700 12:12:28.267143 [Gating] SW calibration Done
7701 12:12:28.269888 ==
7702 12:12:28.270314 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 12:12:28.276425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 12:12:28.276855 ==
7705 12:12:28.277196 RX Vref Scan: 0
7706 12:12:28.277536
7707 12:12:28.279745 RX Vref 0 -> 0, step: 1
7708 12:12:28.280166
7709 12:12:28.283177 RX Delay 0 -> 252, step: 8
7710 12:12:28.286170 iDelay=192, Bit 0, Center 131 (72 ~ 191) 120
7711 12:12:28.289675 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7712 12:12:28.293050 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7713 12:12:28.299490 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7714 12:12:28.302623 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7715 12:12:28.306101 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7716 12:12:28.309363 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7717 12:12:28.312484 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7718 12:12:28.319058 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7719 12:12:28.322583 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7720 12:12:28.325802 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7721 12:12:28.328868 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7722 12:12:28.335539 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7723 12:12:28.338985 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7724 12:12:28.342351 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7725 12:12:28.345614 iDelay=192, Bit 15, Center 131 (72 ~ 191) 120
7726 12:12:28.346050 ==
7727 12:12:28.348956 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 12:12:28.355985 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 12:12:28.356421 ==
7730 12:12:28.356770 DQS Delay:
7731 12:12:28.357088 DQS0 = 0, DQS1 = 0
7732 12:12:28.359053 DQM Delay:
7733 12:12:28.359480 DQM0 = 128, DQM1 = 124
7734 12:12:28.362294 DQ Delay:
7735 12:12:28.365578 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =123
7736 12:12:28.369077 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
7737 12:12:28.372132 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7738 12:12:28.375445 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7739 12:12:28.375874
7740 12:12:28.376212
7741 12:12:28.376525 ==
7742 12:12:28.378729 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 12:12:28.381960 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 12:12:28.385334 ==
7745 12:12:28.385789
7746 12:12:28.386130
7747 12:12:28.386446 TX Vref Scan disable
7748 12:12:28.388572 == TX Byte 0 ==
7749 12:12:28.391661 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7750 12:12:28.394930 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7751 12:12:28.398496 == TX Byte 1 ==
7752 12:12:28.402004 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7753 12:12:28.405214 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7754 12:12:28.408419 ==
7755 12:12:28.411812 Dram Type= 6, Freq= 0, CH_0, rank 0
7756 12:12:28.414803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7757 12:12:28.415237 ==
7758 12:12:28.427673
7759 12:12:28.430808 TX Vref early break, caculate TX vref
7760 12:12:28.434309 TX Vref=16, minBit 8, minWin=22, winSum=364
7761 12:12:28.437789 TX Vref=18, minBit 0, minWin=23, winSum=377
7762 12:12:28.440831 TX Vref=20, minBit 7, minWin=23, winSum=387
7763 12:12:28.444328 TX Vref=22, minBit 0, minWin=24, winSum=396
7764 12:12:28.447399 TX Vref=24, minBit 2, minWin=24, winSum=404
7765 12:12:28.454078 TX Vref=26, minBit 3, minWin=25, winSum=418
7766 12:12:28.457224 TX Vref=28, minBit 0, minWin=25, winSum=411
7767 12:12:28.460305 TX Vref=30, minBit 8, minWin=24, winSum=408
7768 12:12:28.463725 TX Vref=32, minBit 4, minWin=24, winSum=399
7769 12:12:28.466959 TX Vref=34, minBit 8, minWin=23, winSum=387
7770 12:12:28.473675 [TxChooseVref] Worse bit 3, Min win 25, Win sum 418, Final Vref 26
7771 12:12:28.474106
7772 12:12:28.477338 Final TX Range 0 Vref 26
7773 12:12:28.477803
7774 12:12:28.478146 ==
7775 12:12:28.480384 Dram Type= 6, Freq= 0, CH_0, rank 0
7776 12:12:28.483653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7777 12:12:28.484085 ==
7778 12:12:28.484431
7779 12:12:28.484753
7780 12:12:28.487103 TX Vref Scan disable
7781 12:12:28.493864 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7782 12:12:28.494294 == TX Byte 0 ==
7783 12:12:28.497089 u2DelayCellOfst[0]=15 cells (4 PI)
7784 12:12:28.500542 u2DelayCellOfst[1]=18 cells (5 PI)
7785 12:12:28.503806 u2DelayCellOfst[2]=15 cells (4 PI)
7786 12:12:28.507027 u2DelayCellOfst[3]=15 cells (4 PI)
7787 12:12:28.510738 u2DelayCellOfst[4]=7 cells (2 PI)
7788 12:12:28.513812 u2DelayCellOfst[5]=0 cells (0 PI)
7789 12:12:28.517300 u2DelayCellOfst[6]=22 cells (6 PI)
7790 12:12:28.520447 u2DelayCellOfst[7]=18 cells (5 PI)
7791 12:12:28.523553 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7792 12:12:28.527062 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7793 12:12:28.530111 == TX Byte 1 ==
7794 12:12:28.533658 u2DelayCellOfst[8]=0 cells (0 PI)
7795 12:12:28.534171 u2DelayCellOfst[9]=0 cells (0 PI)
7796 12:12:28.536766 u2DelayCellOfst[10]=3 cells (1 PI)
7797 12:12:28.540399 u2DelayCellOfst[11]=3 cells (1 PI)
7798 12:12:28.543796 u2DelayCellOfst[12]=11 cells (3 PI)
7799 12:12:28.546963 u2DelayCellOfst[13]=7 cells (2 PI)
7800 12:12:28.550265 u2DelayCellOfst[14]=15 cells (4 PI)
7801 12:12:28.553442 u2DelayCellOfst[15]=7 cells (2 PI)
7802 12:12:28.556879 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7803 12:12:28.563416 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7804 12:12:28.563851 DramC Write-DBI on
7805 12:12:28.564191 ==
7806 12:12:28.566790 Dram Type= 6, Freq= 0, CH_0, rank 0
7807 12:12:28.570116 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7808 12:12:28.573165 ==
7809 12:12:28.573624
7810 12:12:28.573969
7811 12:12:28.574287 TX Vref Scan disable
7812 12:12:28.577073 == TX Byte 0 ==
7813 12:12:28.580232 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7814 12:12:28.583487 == TX Byte 1 ==
7815 12:12:28.587023 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7816 12:12:28.590268 DramC Write-DBI off
7817 12:12:28.590695
7818 12:12:28.591033 [DATLAT]
7819 12:12:28.591352 Freq=1600, CH0 RK0
7820 12:12:28.591729
7821 12:12:28.593705 DATLAT Default: 0xf
7822 12:12:28.594134 0, 0xFFFF, sum = 0
7823 12:12:28.596731 1, 0xFFFF, sum = 0
7824 12:12:28.599959 2, 0xFFFF, sum = 0
7825 12:12:28.600395 3, 0xFFFF, sum = 0
7826 12:12:28.603519 4, 0xFFFF, sum = 0
7827 12:12:28.604082 5, 0xFFFF, sum = 0
7828 12:12:28.606508 6, 0xFFFF, sum = 0
7829 12:12:28.606945 7, 0xFFFF, sum = 0
7830 12:12:28.609941 8, 0xFFFF, sum = 0
7831 12:12:28.610376 9, 0xFFFF, sum = 0
7832 12:12:28.613084 10, 0xFFFF, sum = 0
7833 12:12:28.613557 11, 0xFFFF, sum = 0
7834 12:12:28.616540 12, 0xFFFF, sum = 0
7835 12:12:28.616975 13, 0xEFFF, sum = 0
7836 12:12:28.619882 14, 0x0, sum = 1
7837 12:12:28.620330 15, 0x0, sum = 2
7838 12:12:28.623314 16, 0x0, sum = 3
7839 12:12:28.623754 17, 0x0, sum = 4
7840 12:12:28.626552 best_step = 15
7841 12:12:28.626980
7842 12:12:28.627320 ==
7843 12:12:28.629597 Dram Type= 6, Freq= 0, CH_0, rank 0
7844 12:12:28.633128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7845 12:12:28.633601 ==
7846 12:12:28.636351 RX Vref Scan: 1
7847 12:12:28.636776
7848 12:12:28.637110 Set Vref Range= 24 -> 127
7849 12:12:28.637427
7850 12:12:28.639863 RX Vref 24 -> 127, step: 1
7851 12:12:28.640290
7852 12:12:28.642974 RX Delay 11 -> 252, step: 4
7853 12:12:28.643406
7854 12:12:28.646409 Set Vref, RX VrefLevel [Byte0]: 24
7855 12:12:28.649849 [Byte1]: 24
7856 12:12:28.650276
7857 12:12:28.653021 Set Vref, RX VrefLevel [Byte0]: 25
7858 12:12:28.656463 [Byte1]: 25
7859 12:12:28.659585
7860 12:12:28.660014 Set Vref, RX VrefLevel [Byte0]: 26
7861 12:12:28.663155 [Byte1]: 26
7862 12:12:28.667374
7863 12:12:28.667803 Set Vref, RX VrefLevel [Byte0]: 27
7864 12:12:28.670743 [Byte1]: 27
7865 12:12:28.674835
7866 12:12:28.675260 Set Vref, RX VrefLevel [Byte0]: 28
7867 12:12:28.678118 [Byte1]: 28
7868 12:12:28.682514
7869 12:12:28.682938 Set Vref, RX VrefLevel [Byte0]: 29
7870 12:12:28.685680 [Byte1]: 29
7871 12:12:28.690336
7872 12:12:28.690763 Set Vref, RX VrefLevel [Byte0]: 30
7873 12:12:28.693534 [Byte1]: 30
7874 12:12:28.697901
7875 12:12:28.698360 Set Vref, RX VrefLevel [Byte0]: 31
7876 12:12:28.700860 [Byte1]: 31
7877 12:12:28.705323
7878 12:12:28.708360 Set Vref, RX VrefLevel [Byte0]: 32
7879 12:12:28.711703 [Byte1]: 32
7880 12:12:28.712131
7881 12:12:28.715028 Set Vref, RX VrefLevel [Byte0]: 33
7882 12:12:28.718146 [Byte1]: 33
7883 12:12:28.718578
7884 12:12:28.721842 Set Vref, RX VrefLevel [Byte0]: 34
7885 12:12:28.724823 [Byte1]: 34
7886 12:12:28.728353
7887 12:12:28.728902 Set Vref, RX VrefLevel [Byte0]: 35
7888 12:12:28.731817 [Byte1]: 35
7889 12:12:28.735758
7890 12:12:28.736186 Set Vref, RX VrefLevel [Byte0]: 36
7891 12:12:28.738950 [Byte1]: 36
7892 12:12:28.743558
7893 12:12:28.743986 Set Vref, RX VrefLevel [Byte0]: 37
7894 12:12:28.746811 [Byte1]: 37
7895 12:12:28.751026
7896 12:12:28.751452 Set Vref, RX VrefLevel [Byte0]: 38
7897 12:12:28.754215 [Byte1]: 38
7898 12:12:28.758495
7899 12:12:28.758920 Set Vref, RX VrefLevel [Byte0]: 39
7900 12:12:28.762062 [Byte1]: 39
7901 12:12:28.766324
7902 12:12:28.766753 Set Vref, RX VrefLevel [Byte0]: 40
7903 12:12:28.769501 [Byte1]: 40
7904 12:12:28.773843
7905 12:12:28.774270 Set Vref, RX VrefLevel [Byte0]: 41
7906 12:12:28.776983 [Byte1]: 41
7907 12:12:28.781549
7908 12:12:28.781979 Set Vref, RX VrefLevel [Byte0]: 42
7909 12:12:28.784795 [Byte1]: 42
7910 12:12:28.789121
7911 12:12:28.789622 Set Vref, RX VrefLevel [Byte0]: 43
7912 12:12:28.792239 [Byte1]: 43
7913 12:12:28.796664
7914 12:12:28.797090 Set Vref, RX VrefLevel [Byte0]: 44
7915 12:12:28.800163 [Byte1]: 44
7916 12:12:28.804463
7917 12:12:28.804907 Set Vref, RX VrefLevel [Byte0]: 45
7918 12:12:28.807509 [Byte1]: 45
7919 12:12:28.812093
7920 12:12:28.812518 Set Vref, RX VrefLevel [Byte0]: 46
7921 12:12:28.815201 [Byte1]: 46
7922 12:12:28.819488
7923 12:12:28.819918 Set Vref, RX VrefLevel [Byte0]: 47
7924 12:12:28.822621 [Byte1]: 47
7925 12:12:28.827124
7926 12:12:28.827549 Set Vref, RX VrefLevel [Byte0]: 48
7927 12:12:28.830556 [Byte1]: 48
7928 12:12:28.834704
7929 12:12:28.835132 Set Vref, RX VrefLevel [Byte0]: 49
7930 12:12:28.838164 [Byte1]: 49
7931 12:12:28.842579
7932 12:12:28.843006 Set Vref, RX VrefLevel [Byte0]: 50
7933 12:12:28.845631 [Byte1]: 50
7934 12:12:28.849949
7935 12:12:28.850377 Set Vref, RX VrefLevel [Byte0]: 51
7936 12:12:28.853458 [Byte1]: 51
7937 12:12:28.857659
7938 12:12:28.858090 Set Vref, RX VrefLevel [Byte0]: 52
7939 12:12:28.860882 [Byte1]: 52
7940 12:12:28.865139
7941 12:12:28.865594 Set Vref, RX VrefLevel [Byte0]: 53
7942 12:12:28.868698 [Byte1]: 53
7943 12:12:28.872959
7944 12:12:28.873385 Set Vref, RX VrefLevel [Byte0]: 54
7945 12:12:28.876103 [Byte1]: 54
7946 12:12:28.880423
7947 12:12:28.880849 Set Vref, RX VrefLevel [Byte0]: 55
7948 12:12:28.883864 [Byte1]: 55
7949 12:12:28.888223
7950 12:12:28.888651 Set Vref, RX VrefLevel [Byte0]: 56
7951 12:12:28.891539 [Byte1]: 56
7952 12:12:28.895623
7953 12:12:28.896080 Set Vref, RX VrefLevel [Byte0]: 57
7954 12:12:28.898887 [Byte1]: 57
7955 12:12:28.903379
7956 12:12:28.903807 Set Vref, RX VrefLevel [Byte0]: 58
7957 12:12:28.906803 [Byte1]: 58
7958 12:12:28.911051
7959 12:12:28.911528 Set Vref, RX VrefLevel [Byte0]: 59
7960 12:12:28.914006 [Byte1]: 59
7961 12:12:28.918382
7962 12:12:28.918808 Set Vref, RX VrefLevel [Byte0]: 60
7963 12:12:28.921771 [Byte1]: 60
7964 12:12:28.926109
7965 12:12:28.926537 Set Vref, RX VrefLevel [Byte0]: 61
7966 12:12:28.929270 [Byte1]: 61
7967 12:12:28.933906
7968 12:12:28.934332 Set Vref, RX VrefLevel [Byte0]: 62
7969 12:12:28.936941 [Byte1]: 62
7970 12:12:28.941523
7971 12:12:28.941956 Set Vref, RX VrefLevel [Byte0]: 63
7972 12:12:28.944588 [Byte1]: 63
7973 12:12:28.948750
7974 12:12:28.949178 Set Vref, RX VrefLevel [Byte0]: 64
7975 12:12:28.952386 [Byte1]: 64
7976 12:12:28.956419
7977 12:12:28.956847 Set Vref, RX VrefLevel [Byte0]: 65
7978 12:12:28.959872 [Byte1]: 65
7979 12:12:28.964143
7980 12:12:28.964565 Set Vref, RX VrefLevel [Byte0]: 66
7981 12:12:28.967355 [Byte1]: 66
7982 12:12:28.971669
7983 12:12:28.972129 Set Vref, RX VrefLevel [Byte0]: 67
7984 12:12:28.975513 [Byte1]: 67
7985 12:12:28.979705
7986 12:12:28.980241 Set Vref, RX VrefLevel [Byte0]: 68
7987 12:12:28.982730 [Byte1]: 68
7988 12:12:28.986973
7989 12:12:28.987413 Set Vref, RX VrefLevel [Byte0]: 69
7990 12:12:28.990514 [Byte1]: 69
7991 12:12:28.994882
7992 12:12:28.995475 Set Vref, RX VrefLevel [Byte0]: 70
7993 12:12:28.997807 [Byte1]: 70
7994 12:12:29.002177
7995 12:12:29.002595 Set Vref, RX VrefLevel [Byte0]: 71
7996 12:12:29.005853 [Byte1]: 71
7997 12:12:29.009810
7998 12:12:29.010234 Set Vref, RX VrefLevel [Byte0]: 72
7999 12:12:29.013173 [Byte1]: 72
8000 12:12:29.017550
8001 12:12:29.018026 Set Vref, RX VrefLevel [Byte0]: 73
8002 12:12:29.020564 [Byte1]: 73
8003 12:12:29.024888
8004 12:12:29.025312 Set Vref, RX VrefLevel [Byte0]: 74
8005 12:12:29.028301 [Byte1]: 74
8006 12:12:29.032540
8007 12:12:29.033006 Set Vref, RX VrefLevel [Byte0]: 75
8008 12:12:29.035903 [Byte1]: 75
8009 12:12:29.040469
8010 12:12:29.040936 Set Vref, RX VrefLevel [Byte0]: 76
8011 12:12:29.043695 [Byte1]: 76
8012 12:12:29.048201
8013 12:12:29.048711 Final RX Vref Byte 0 = 64 to rank0
8014 12:12:29.051342 Final RX Vref Byte 1 = 59 to rank0
8015 12:12:29.054672 Final RX Vref Byte 0 = 64 to rank1
8016 12:12:29.057843 Final RX Vref Byte 1 = 59 to rank1==
8017 12:12:29.061134 Dram Type= 6, Freq= 0, CH_0, rank 0
8018 12:12:29.067883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8019 12:12:29.068332 ==
8020 12:12:29.068734 DQS Delay:
8021 12:12:29.069086 DQS0 = 0, DQS1 = 0
8022 12:12:29.071106 DQM Delay:
8023 12:12:29.071538 DQM0 = 126, DQM1 = 120
8024 12:12:29.074704 DQ Delay:
8025 12:12:29.078013 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8026 12:12:29.081283 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8027 12:12:29.084459 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
8028 12:12:29.087887 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
8029 12:12:29.088316
8030 12:12:29.088652
8031 12:12:29.088967
8032 12:12:29.091044 [DramC_TX_OE_Calibration] TA2
8033 12:12:29.094700 Original DQ_B0 (3 6) =30, OEN = 27
8034 12:12:29.097863 Original DQ_B1 (3 6) =30, OEN = 27
8035 12:12:29.100840 24, 0x0, End_B0=24 End_B1=24
8036 12:12:29.101273 25, 0x0, End_B0=25 End_B1=25
8037 12:12:29.104345 26, 0x0, End_B0=26 End_B1=26
8038 12:12:29.107731 27, 0x0, End_B0=27 End_B1=27
8039 12:12:29.111389 28, 0x0, End_B0=28 End_B1=28
8040 12:12:29.111821 29, 0x0, End_B0=29 End_B1=29
8041 12:12:29.114463 30, 0x0, End_B0=30 End_B1=30
8042 12:12:29.118035 31, 0x5151, End_B0=30 End_B1=30
8043 12:12:29.121157 Byte0 end_step=30 best_step=27
8044 12:12:29.124461 Byte1 end_step=30 best_step=27
8045 12:12:29.127766 Byte0 TX OE(2T, 0.5T) = (3, 3)
8046 12:12:29.131000 Byte1 TX OE(2T, 0.5T) = (3, 3)
8047 12:12:29.131431
8048 12:12:29.131771
8049 12:12:29.137579 [DQSOSCAuto] RK0, (LSB)MR18= 0x1312, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
8050 12:12:29.140663 CH0 RK0: MR19=303, MR18=1312
8051 12:12:29.147443 CH0_RK0: MR19=0x303, MR18=0x1312, DQSOSC=400, MR23=63, INC=23, DEC=15
8052 12:12:29.147873
8053 12:12:29.150975 ----->DramcWriteLeveling(PI) begin...
8054 12:12:29.151412 ==
8055 12:12:29.153950 Dram Type= 6, Freq= 0, CH_0, rank 1
8056 12:12:29.157247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8057 12:12:29.157729 ==
8058 12:12:29.160709 Write leveling (Byte 0): 33 => 33
8059 12:12:29.164217 Write leveling (Byte 1): 29 => 29
8060 12:12:29.167431 DramcWriteLeveling(PI) end<-----
8061 12:12:29.167862
8062 12:12:29.168202 ==
8063 12:12:29.170718 Dram Type= 6, Freq= 0, CH_0, rank 1
8064 12:12:29.173893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8065 12:12:29.174328 ==
8066 12:12:29.177181 [Gating] SW mode calibration
8067 12:12:29.184054 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8068 12:12:29.190354 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8069 12:12:29.193610 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 12:12:29.200185 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 12:12:29.203759 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 12:12:29.206819 1 4 12 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
8073 12:12:29.213641 1 4 16 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8074 12:12:29.216664 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8075 12:12:29.220279 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8076 12:12:29.226831 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8077 12:12:29.230223 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8078 12:12:29.233050 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8079 12:12:29.240022 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
8080 12:12:29.243261 1 5 12 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
8081 12:12:29.246516 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (0 1) (0 0)
8082 12:12:29.253353 1 5 20 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
8083 12:12:29.256678 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8084 12:12:29.259830 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8085 12:12:29.262968 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8086 12:12:29.269774 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8087 12:12:29.272966 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8088 12:12:29.279486 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8089 12:12:29.282983 1 6 16 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
8090 12:12:29.286015 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8091 12:12:29.292655 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8092 12:12:29.296027 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8093 12:12:29.299334 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8094 12:12:29.305815 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8095 12:12:29.308904 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8096 12:12:29.312432 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8097 12:12:29.319044 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8098 12:12:29.322228 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8099 12:12:29.325766 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 12:12:29.329000 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 12:12:29.335475 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 12:12:29.338650 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 12:12:29.345391 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 12:12:29.348730 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 12:12:29.352034 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 12:12:29.355443 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 12:12:29.362036 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 12:12:29.365091 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 12:12:29.371695 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 12:12:29.374858 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 12:12:29.378414 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8112 12:12:29.384982 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8113 12:12:29.385566 Total UI for P1: 0, mck2ui 16
8114 12:12:29.388524 best dqsien dly found for B0: ( 1, 9, 8)
8115 12:12:29.395104 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8116 12:12:29.398146 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8117 12:12:29.401758 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8118 12:12:29.404807 Total UI for P1: 0, mck2ui 16
8119 12:12:29.408313 best dqsien dly found for B1: ( 1, 9, 20)
8120 12:12:29.411626 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8121 12:12:29.414635 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8122 12:12:29.417986
8123 12:12:29.421588 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8124 12:12:29.424774 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8125 12:12:29.428223 [Gating] SW calibration Done
8126 12:12:29.428653 ==
8127 12:12:29.431353 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 12:12:29.434464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 12:12:29.434911 ==
8130 12:12:29.438134 RX Vref Scan: 0
8131 12:12:29.438565
8132 12:12:29.438907 RX Vref 0 -> 0, step: 1
8133 12:12:29.439228
8134 12:12:29.441138 RX Delay 0 -> 252, step: 8
8135 12:12:29.444657 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8136 12:12:29.447787 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8137 12:12:29.454241 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8138 12:12:29.457607 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8139 12:12:29.460879 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8140 12:12:29.464361 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8141 12:12:29.467662 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8142 12:12:29.474036 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8143 12:12:29.477557 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8144 12:12:29.480753 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8145 12:12:29.484347 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8146 12:12:29.490795 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8147 12:12:29.493938 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8148 12:12:29.497415 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8149 12:12:29.500615 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8150 12:12:29.504052 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8151 12:12:29.507100 ==
8152 12:12:29.507529 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 12:12:29.513784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 12:12:29.514216 ==
8155 12:12:29.514559 DQS Delay:
8156 12:12:29.516986 DQS0 = 0, DQS1 = 0
8157 12:12:29.517513 DQM Delay:
8158 12:12:29.520569 DQM0 = 127, DQM1 = 121
8159 12:12:29.521015 DQ Delay:
8160 12:12:29.523804 DQ0 =127, DQ1 =127, DQ2 =123, DQ3 =123
8161 12:12:29.527107 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8162 12:12:29.530133 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8163 12:12:29.533714 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8164 12:12:29.534146
8165 12:12:29.534486
8166 12:12:29.534803 ==
8167 12:12:29.536772 Dram Type= 6, Freq= 0, CH_0, rank 1
8168 12:12:29.543418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8169 12:12:29.543854 ==
8170 12:12:29.544200
8171 12:12:29.544519
8172 12:12:29.544824 TX Vref Scan disable
8173 12:12:29.547402 == TX Byte 0 ==
8174 12:12:29.550358 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8175 12:12:29.557275 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8176 12:12:29.557751 == TX Byte 1 ==
8177 12:12:29.560636 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8178 12:12:29.566980 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8179 12:12:29.567412 ==
8180 12:12:29.570416 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 12:12:29.573671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 12:12:29.574110 ==
8183 12:12:29.586195
8184 12:12:29.589719 TX Vref early break, caculate TX vref
8185 12:12:29.593100 TX Vref=16, minBit 0, minWin=22, winSum=365
8186 12:12:29.596397 TX Vref=18, minBit 0, minWin=23, winSum=377
8187 12:12:29.599643 TX Vref=20, minBit 0, minWin=23, winSum=384
8188 12:12:29.602770 TX Vref=22, minBit 1, minWin=23, winSum=390
8189 12:12:29.606138 TX Vref=24, minBit 0, minWin=24, winSum=403
8190 12:12:29.612525 TX Vref=26, minBit 1, minWin=25, winSum=407
8191 12:12:29.616191 TX Vref=28, minBit 2, minWin=25, winSum=411
8192 12:12:29.619329 TX Vref=30, minBit 11, minWin=24, winSum=407
8193 12:12:29.622721 TX Vref=32, minBit 8, minWin=24, winSum=402
8194 12:12:29.625952 TX Vref=34, minBit 8, minWin=22, winSum=389
8195 12:12:29.632421 [TxChooseVref] Worse bit 2, Min win 25, Win sum 411, Final Vref 28
8196 12:12:29.632854
8197 12:12:29.635885 Final TX Range 0 Vref 28
8198 12:12:29.636381
8199 12:12:29.636736 ==
8200 12:12:29.639403 Dram Type= 6, Freq= 0, CH_0, rank 1
8201 12:12:29.642386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8202 12:12:29.642818 ==
8203 12:12:29.643163
8204 12:12:29.643482
8205 12:12:29.645811 TX Vref Scan disable
8206 12:12:29.652636 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8207 12:12:29.653063 == TX Byte 0 ==
8208 12:12:29.655822 u2DelayCellOfst[0]=15 cells (4 PI)
8209 12:12:29.659030 u2DelayCellOfst[1]=22 cells (6 PI)
8210 12:12:29.662371 u2DelayCellOfst[2]=15 cells (4 PI)
8211 12:12:29.665751 u2DelayCellOfst[3]=15 cells (4 PI)
8212 12:12:29.668943 u2DelayCellOfst[4]=11 cells (3 PI)
8213 12:12:29.672028 u2DelayCellOfst[5]=0 cells (0 PI)
8214 12:12:29.675702 u2DelayCellOfst[6]=22 cells (6 PI)
8215 12:12:29.678621 u2DelayCellOfst[7]=18 cells (5 PI)
8216 12:12:29.682387 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8217 12:12:29.685520 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8218 12:12:29.688767 == TX Byte 1 ==
8219 12:12:29.691937 u2DelayCellOfst[8]=0 cells (0 PI)
8220 12:12:29.695246 u2DelayCellOfst[9]=0 cells (0 PI)
8221 12:12:29.698734 u2DelayCellOfst[10]=3 cells (1 PI)
8222 12:12:29.699160 u2DelayCellOfst[11]=3 cells (1 PI)
8223 12:12:29.701867 u2DelayCellOfst[12]=11 cells (3 PI)
8224 12:12:29.705448 u2DelayCellOfst[13]=11 cells (3 PI)
8225 12:12:29.708782 u2DelayCellOfst[14]=11 cells (3 PI)
8226 12:12:29.711738 u2DelayCellOfst[15]=7 cells (2 PI)
8227 12:12:29.718711 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8228 12:12:29.721836 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8229 12:12:29.722259 DramC Write-DBI on
8230 12:12:29.722594 ==
8231 12:12:29.724911 Dram Type= 6, Freq= 0, CH_0, rank 1
8232 12:12:29.731693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8233 12:12:29.732118 ==
8234 12:12:29.732455
8235 12:12:29.732767
8236 12:12:29.735114 TX Vref Scan disable
8237 12:12:29.735536 == TX Byte 0 ==
8238 12:12:29.741700 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8239 12:12:29.742126 == TX Byte 1 ==
8240 12:12:29.745223 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8241 12:12:29.748432 DramC Write-DBI off
8242 12:12:29.748850
8243 12:12:29.749187 [DATLAT]
8244 12:12:29.751387 Freq=1600, CH0 RK1
8245 12:12:29.751816
8246 12:12:29.752160 DATLAT Default: 0xf
8247 12:12:29.754659 0, 0xFFFF, sum = 0
8248 12:12:29.755102 1, 0xFFFF, sum = 0
8249 12:12:29.758137 2, 0xFFFF, sum = 0
8250 12:12:29.758575 3, 0xFFFF, sum = 0
8251 12:12:29.761086 4, 0xFFFF, sum = 0
8252 12:12:29.761552 5, 0xFFFF, sum = 0
8253 12:12:29.764525 6, 0xFFFF, sum = 0
8254 12:12:29.764961 7, 0xFFFF, sum = 0
8255 12:12:29.767776 8, 0xFFFF, sum = 0
8256 12:12:29.771184 9, 0xFFFF, sum = 0
8257 12:12:29.771621 10, 0xFFFF, sum = 0
8258 12:12:29.774720 11, 0xFFFF, sum = 0
8259 12:12:29.775156 12, 0xFFFF, sum = 0
8260 12:12:29.777783 13, 0xCFFF, sum = 0
8261 12:12:29.778218 14, 0x0, sum = 1
8262 12:12:29.781090 15, 0x0, sum = 2
8263 12:12:29.781545 16, 0x0, sum = 3
8264 12:12:29.784533 17, 0x0, sum = 4
8265 12:12:29.784968 best_step = 15
8266 12:12:29.785309
8267 12:12:29.785662 ==
8268 12:12:29.787601 Dram Type= 6, Freq= 0, CH_0, rank 1
8269 12:12:29.790982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8270 12:12:29.791421 ==
8271 12:12:29.794370 RX Vref Scan: 0
8272 12:12:29.794798
8273 12:12:29.797425 RX Vref 0 -> 0, step: 1
8274 12:12:29.797901
8275 12:12:29.798242 RX Delay 3 -> 252, step: 4
8276 12:12:29.804739 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8277 12:12:29.807997 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8278 12:12:29.811426 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8279 12:12:29.814711 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8280 12:12:29.817870 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8281 12:12:29.824525 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8282 12:12:29.827911 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8283 12:12:29.831401 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8284 12:12:29.834459 iDelay=191, Bit 8, Center 110 (51 ~ 170) 120
8285 12:12:29.837937 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8286 12:12:29.844515 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8287 12:12:29.847615 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8288 12:12:29.851204 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8289 12:12:29.854404 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8290 12:12:29.861152 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8291 12:12:29.864126 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8292 12:12:29.864592 ==
8293 12:12:29.867729 Dram Type= 6, Freq= 0, CH_0, rank 1
8294 12:12:29.871008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8295 12:12:29.871505 ==
8296 12:12:29.874165 DQS Delay:
8297 12:12:29.874588 DQS0 = 0, DQS1 = 0
8298 12:12:29.874928 DQM Delay:
8299 12:12:29.877958 DQM0 = 124, DQM1 = 117
8300 12:12:29.878404 DQ Delay:
8301 12:12:29.881073 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8302 12:12:29.884442 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8303 12:12:29.887582 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8304 12:12:29.894155 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8305 12:12:29.894754
8306 12:12:29.895274
8307 12:12:29.895826
8308 12:12:29.897254 [DramC_TX_OE_Calibration] TA2
8309 12:12:29.897915 Original DQ_B0 (3 6) =30, OEN = 27
8310 12:12:29.900769 Original DQ_B1 (3 6) =30, OEN = 27
8311 12:12:29.904310 24, 0x0, End_B0=24 End_B1=24
8312 12:12:29.907418 25, 0x0, End_B0=25 End_B1=25
8313 12:12:29.910669 26, 0x0, End_B0=26 End_B1=26
8314 12:12:29.914170 27, 0x0, End_B0=27 End_B1=27
8315 12:12:29.914604 28, 0x0, End_B0=28 End_B1=28
8316 12:12:29.917883 29, 0x0, End_B0=29 End_B1=29
8317 12:12:29.920871 30, 0x0, End_B0=30 End_B1=30
8318 12:12:29.923983 31, 0x4141, End_B0=30 End_B1=30
8319 12:12:29.927539 Byte0 end_step=30 best_step=27
8320 12:12:29.928171 Byte1 end_step=30 best_step=27
8321 12:12:29.930703 Byte0 TX OE(2T, 0.5T) = (3, 3)
8322 12:12:29.933800 Byte1 TX OE(2T, 0.5T) = (3, 3)
8323 12:12:29.934472
8324 12:12:29.935074
8325 12:12:29.943843 [DQSOSCAuto] RK1, (LSB)MR18= 0x2513, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8326 12:12:29.944451 CH0 RK1: MR19=303, MR18=2513
8327 12:12:29.950708 CH0_RK1: MR19=0x303, MR18=0x2513, DQSOSC=391, MR23=63, INC=24, DEC=16
8328 12:12:29.954159 [RxdqsGatingPostProcess] freq 1600
8329 12:12:29.960455 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8330 12:12:29.963925 best DQS0 dly(2T, 0.5T) = (1, 1)
8331 12:12:29.967099 best DQS1 dly(2T, 0.5T) = (1, 1)
8332 12:12:29.970494 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8333 12:12:29.973783 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8334 12:12:29.974378 best DQS0 dly(2T, 0.5T) = (1, 1)
8335 12:12:29.977231 best DQS1 dly(2T, 0.5T) = (1, 1)
8336 12:12:29.980449 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8337 12:12:29.983716 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8338 12:12:29.987150 Pre-setting of DQS Precalculation
8339 12:12:29.993577 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8340 12:12:29.994022 ==
8341 12:12:29.997199 Dram Type= 6, Freq= 0, CH_1, rank 0
8342 12:12:30.000320 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 12:12:30.000923 ==
8344 12:12:30.006924 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8345 12:12:30.010440 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8346 12:12:30.013445 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8347 12:12:30.020214 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8348 12:12:30.028976 [CA 0] Center 42 (13~71) winsize 59
8349 12:12:30.032318 [CA 1] Center 42 (12~72) winsize 61
8350 12:12:30.035614 [CA 2] Center 37 (9~66) winsize 58
8351 12:12:30.038933 [CA 3] Center 36 (7~66) winsize 60
8352 12:12:30.042377 [CA 4] Center 37 (8~67) winsize 60
8353 12:12:30.045757 [CA 5] Center 37 (8~66) winsize 59
8354 12:12:30.046188
8355 12:12:30.048959 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8356 12:12:30.049527
8357 12:12:30.052254 [CATrainingPosCal] consider 1 rank data
8358 12:12:30.055515 u2DelayCellTimex100 = 258/100 ps
8359 12:12:30.058727 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8360 12:12:30.065721 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8361 12:12:30.068715 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8362 12:12:30.071767 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8363 12:12:30.075296 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8364 12:12:30.078358 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8365 12:12:30.078682
8366 12:12:30.081910 CA PerBit enable=1, Macro0, CA PI delay=36
8367 12:12:30.082214
8368 12:12:30.084940 [CBTSetCACLKResult] CA Dly = 36
8369 12:12:30.088094 CS Dly: 10 (0~41)
8370 12:12:30.091331 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8371 12:12:30.094780 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8372 12:12:30.095083 ==
8373 12:12:30.097856 Dram Type= 6, Freq= 0, CH_1, rank 1
8374 12:12:30.104670 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8375 12:12:30.104974 ==
8376 12:12:30.107803 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8377 12:12:30.114426 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8378 12:12:30.117947 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8379 12:12:30.124165 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8380 12:12:30.131904 [CA 0] Center 42 (12~72) winsize 61
8381 12:12:30.135444 [CA 1] Center 42 (12~72) winsize 61
8382 12:12:30.138676 [CA 2] Center 38 (9~67) winsize 59
8383 12:12:30.141799 [CA 3] Center 36 (7~66) winsize 60
8384 12:12:30.145197 [CA 4] Center 38 (8~68) winsize 61
8385 12:12:30.148593 [CA 5] Center 36 (6~66) winsize 61
8386 12:12:30.148938
8387 12:12:30.151701 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8388 12:12:30.152095
8389 12:12:30.155094 [CATrainingPosCal] consider 2 rank data
8390 12:12:30.158309 u2DelayCellTimex100 = 258/100 ps
8391 12:12:30.165173 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8392 12:12:30.168479 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8393 12:12:30.171892 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8394 12:12:30.175271 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8395 12:12:30.178317 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8396 12:12:30.181827 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8397 12:12:30.182201
8398 12:12:30.184975 CA PerBit enable=1, Macro0, CA PI delay=36
8399 12:12:30.185311
8400 12:12:30.188745 [CBTSetCACLKResult] CA Dly = 36
8401 12:12:30.191892 CS Dly: 11 (0~44)
8402 12:12:30.194937 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8403 12:12:30.198318 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8404 12:12:30.198664
8405 12:12:30.201678 ----->DramcWriteLeveling(PI) begin...
8406 12:12:30.202036 ==
8407 12:12:30.204951 Dram Type= 6, Freq= 0, CH_1, rank 0
8408 12:12:30.211519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8409 12:12:30.211820 ==
8410 12:12:30.214919 Write leveling (Byte 0): 24 => 24
8411 12:12:30.215220 Write leveling (Byte 1): 28 => 28
8412 12:12:30.218451 DramcWriteLeveling(PI) end<-----
8413 12:12:30.218751
8414 12:12:30.221516 ==
8415 12:12:30.221835 Dram Type= 6, Freq= 0, CH_1, rank 0
8416 12:12:30.228113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8417 12:12:30.228479 ==
8418 12:12:30.231250 [Gating] SW mode calibration
8419 12:12:30.237987 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8420 12:12:30.241209 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8421 12:12:30.247956 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 12:12:30.251313 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 12:12:30.254559 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 12:12:30.261270 1 4 12 | B1->B0 | 2626 2423 | 1 1 | (1 1) (1 1)
8425 12:12:30.264474 1 4 16 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 1)
8426 12:12:30.267787 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8427 12:12:30.274274 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8428 12:12:30.277540 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8429 12:12:30.280836 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8430 12:12:30.287835 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8431 12:12:30.291031 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8432 12:12:30.294278 1 5 12 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
8433 12:12:30.301093 1 5 16 | B1->B0 | 2626 2424 | 0 0 | (0 0) (1 0)
8434 12:12:30.304288 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 12:12:30.307432 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 12:12:30.314306 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 12:12:30.317359 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8438 12:12:30.320876 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8439 12:12:30.327213 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8440 12:12:30.330583 1 6 12 | B1->B0 | 2c2c 2828 | 1 0 | (0 0) (0 0)
8441 12:12:30.333697 1 6 16 | B1->B0 | 4040 3e3e | 1 0 | (0 0) (0 0)
8442 12:12:30.340604 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 12:12:30.343744 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8444 12:12:30.347237 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8445 12:12:30.353751 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8446 12:12:30.356991 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8447 12:12:30.360462 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8448 12:12:30.367024 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8449 12:12:30.370143 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8450 12:12:30.373418 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8451 12:12:30.380080 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 12:12:30.383255 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 12:12:30.386785 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 12:12:30.390044 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 12:12:30.396845 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 12:12:30.399855 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 12:12:30.403297 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 12:12:30.409884 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 12:12:30.413184 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 12:12:30.416451 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 12:12:30.423354 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 12:12:30.426436 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 12:12:30.429777 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 12:12:30.436397 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 12:12:30.439885 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8466 12:12:30.443164 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8467 12:12:30.446443 Total UI for P1: 0, mck2ui 16
8468 12:12:30.449907 best dqsien dly found for B0: ( 1, 9, 16)
8469 12:12:30.456097 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8470 12:12:30.456242 Total UI for P1: 0, mck2ui 16
8471 12:12:30.463366 best dqsien dly found for B1: ( 1, 9, 18)
8472 12:12:30.466495 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8473 12:12:30.470110 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8474 12:12:30.470538
8475 12:12:30.473232 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8476 12:12:30.476294 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8477 12:12:30.479712 [Gating] SW calibration Done
8478 12:12:30.480140 ==
8479 12:12:30.483229 Dram Type= 6, Freq= 0, CH_1, rank 0
8480 12:12:30.486586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8481 12:12:30.487019 ==
8482 12:12:30.489953 RX Vref Scan: 0
8483 12:12:30.490475
8484 12:12:30.493207 RX Vref 0 -> 0, step: 1
8485 12:12:30.493696
8486 12:12:30.494051 RX Delay 0 -> 252, step: 8
8487 12:12:30.499762 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8488 12:12:30.503192 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8489 12:12:30.506385 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8490 12:12:30.509551 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8491 12:12:30.512894 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8492 12:12:30.516425 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8493 12:12:30.522811 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8494 12:12:30.526274 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8495 12:12:30.529713 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8496 12:12:30.533044 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8497 12:12:30.536670 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8498 12:12:30.542794 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8499 12:12:30.546180 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8500 12:12:30.549437 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8501 12:12:30.552922 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8502 12:12:30.559538 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8503 12:12:30.559971 ==
8504 12:12:30.562782 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 12:12:30.565971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 12:12:30.566402 ==
8507 12:12:30.566747 DQS Delay:
8508 12:12:30.569364 DQS0 = 0, DQS1 = 0
8509 12:12:30.569838 DQM Delay:
8510 12:12:30.572663 DQM0 = 131, DQM1 = 125
8511 12:12:30.573092 DQ Delay:
8512 12:12:30.576086 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8513 12:12:30.579214 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8514 12:12:30.582813 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8515 12:12:30.586089 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8516 12:12:30.586613
8517 12:12:30.587110
8518 12:12:30.589090 ==
8519 12:12:30.592609 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 12:12:30.596073 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 12:12:30.596508 ==
8522 12:12:30.596849
8523 12:12:30.597167
8524 12:12:30.599341 TX Vref Scan disable
8525 12:12:30.599768 == TX Byte 0 ==
8526 12:12:30.602417 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8527 12:12:30.609201 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8528 12:12:30.609679 == TX Byte 1 ==
8529 12:12:30.612356 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8530 12:12:30.619131 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8531 12:12:30.619563 ==
8532 12:12:30.622660 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 12:12:30.625933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 12:12:30.626367 ==
8535 12:12:30.639104
8536 12:12:30.642070 TX Vref early break, caculate TX vref
8537 12:12:30.645529 TX Vref=16, minBit 10, minWin=21, winSum=361
8538 12:12:30.648724 TX Vref=18, minBit 9, minWin=22, winSum=370
8539 12:12:30.652440 TX Vref=20, minBit 10, minWin=22, winSum=384
8540 12:12:30.655529 TX Vref=22, minBit 11, minWin=23, winSum=392
8541 12:12:30.658777 TX Vref=24, minBit 11, minWin=23, winSum=403
8542 12:12:30.665791 TX Vref=26, minBit 1, minWin=25, winSum=420
8543 12:12:30.668790 TX Vref=28, minBit 1, minWin=25, winSum=422
8544 12:12:30.672307 TX Vref=30, minBit 1, minWin=25, winSum=416
8545 12:12:30.675439 TX Vref=32, minBit 0, minWin=24, winSum=405
8546 12:12:30.678717 TX Vref=34, minBit 1, minWin=23, winSum=396
8547 12:12:30.685320 [TxChooseVref] Worse bit 1, Min win 25, Win sum 422, Final Vref 28
8548 12:12:30.685793
8549 12:12:30.688878 Final TX Range 0 Vref 28
8550 12:12:30.689349
8551 12:12:30.689747 ==
8552 12:12:30.691807 Dram Type= 6, Freq= 0, CH_1, rank 0
8553 12:12:30.695390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8554 12:12:30.695816 ==
8555 12:12:30.696152
8556 12:12:30.696490
8557 12:12:30.698376 TX Vref Scan disable
8558 12:12:30.705339 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8559 12:12:30.705789 == TX Byte 0 ==
8560 12:12:30.708335 u2DelayCellOfst[0]=18 cells (5 PI)
8561 12:12:30.711802 u2DelayCellOfst[1]=11 cells (3 PI)
8562 12:12:30.714943 u2DelayCellOfst[2]=0 cells (0 PI)
8563 12:12:30.718269 u2DelayCellOfst[3]=3 cells (1 PI)
8564 12:12:30.721727 u2DelayCellOfst[4]=7 cells (2 PI)
8565 12:12:30.724858 u2DelayCellOfst[5]=22 cells (6 PI)
8566 12:12:30.728429 u2DelayCellOfst[6]=22 cells (6 PI)
8567 12:12:30.731500 u2DelayCellOfst[7]=3 cells (1 PI)
8568 12:12:30.735158 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8569 12:12:30.738267 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8570 12:12:30.741812 == TX Byte 1 ==
8571 12:12:30.745245 u2DelayCellOfst[8]=0 cells (0 PI)
8572 12:12:30.745720 u2DelayCellOfst[9]=3 cells (1 PI)
8573 12:12:30.748117 u2DelayCellOfst[10]=11 cells (3 PI)
8574 12:12:30.751647 u2DelayCellOfst[11]=7 cells (2 PI)
8575 12:12:30.755127 u2DelayCellOfst[12]=15 cells (4 PI)
8576 12:12:30.758107 u2DelayCellOfst[13]=18 cells (5 PI)
8577 12:12:30.761554 u2DelayCellOfst[14]=18 cells (5 PI)
8578 12:12:30.764809 u2DelayCellOfst[15]=18 cells (5 PI)
8579 12:12:30.768155 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8580 12:12:30.774809 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8581 12:12:30.775284 DramC Write-DBI on
8582 12:12:30.775624 ==
8583 12:12:30.778222 Dram Type= 6, Freq= 0, CH_1, rank 0
8584 12:12:30.784616 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8585 12:12:30.785170 ==
8586 12:12:30.785669
8587 12:12:30.785997
8588 12:12:30.786303 TX Vref Scan disable
8589 12:12:30.788496 == TX Byte 0 ==
8590 12:12:30.791840 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8591 12:12:30.795326 == TX Byte 1 ==
8592 12:12:30.798465 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8593 12:12:30.801760 DramC Write-DBI off
8594 12:12:30.802182
8595 12:12:30.802514 [DATLAT]
8596 12:12:30.802825 Freq=1600, CH1 RK0
8597 12:12:30.803128
8598 12:12:30.804941 DATLAT Default: 0xf
8599 12:12:30.805359 0, 0xFFFF, sum = 0
8600 12:12:30.808385 1, 0xFFFF, sum = 0
8601 12:12:30.811597 2, 0xFFFF, sum = 0
8602 12:12:30.812045 3, 0xFFFF, sum = 0
8603 12:12:30.814975 4, 0xFFFF, sum = 0
8604 12:12:30.815406 5, 0xFFFF, sum = 0
8605 12:12:30.818205 6, 0xFFFF, sum = 0
8606 12:12:30.818639 7, 0xFFFF, sum = 0
8607 12:12:30.821640 8, 0xFFFF, sum = 0
8608 12:12:30.822071 9, 0xFFFF, sum = 0
8609 12:12:30.824822 10, 0xFFFF, sum = 0
8610 12:12:30.825249 11, 0xFFFF, sum = 0
8611 12:12:30.828161 12, 0xFFFF, sum = 0
8612 12:12:30.828587 13, 0x8FFF, sum = 0
8613 12:12:30.831681 14, 0x0, sum = 1
8614 12:12:30.832113 15, 0x0, sum = 2
8615 12:12:30.834865 16, 0x0, sum = 3
8616 12:12:30.835293 17, 0x0, sum = 4
8617 12:12:30.838390 best_step = 15
8618 12:12:30.838810
8619 12:12:30.839143 ==
8620 12:12:30.841681 Dram Type= 6, Freq= 0, CH_1, rank 0
8621 12:12:30.844805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8622 12:12:30.845226 ==
8623 12:12:30.848380 RX Vref Scan: 1
8624 12:12:30.848862
8625 12:12:30.849199 Set Vref Range= 24 -> 127
8626 12:12:30.849555
8627 12:12:30.851388 RX Vref 24 -> 127, step: 1
8628 12:12:30.851809
8629 12:12:30.854606 RX Delay 11 -> 252, step: 4
8630 12:12:30.855025
8631 12:12:30.858255 Set Vref, RX VrefLevel [Byte0]: 24
8632 12:12:30.861292 [Byte1]: 24
8633 12:12:30.861790
8634 12:12:30.864729 Set Vref, RX VrefLevel [Byte0]: 25
8635 12:12:30.867902 [Byte1]: 25
8636 12:12:30.871328
8637 12:12:30.871748 Set Vref, RX VrefLevel [Byte0]: 26
8638 12:12:30.874489 [Byte1]: 26
8639 12:12:30.878817
8640 12:12:30.879237 Set Vref, RX VrefLevel [Byte0]: 27
8641 12:12:30.882184 [Byte1]: 27
8642 12:12:30.886465
8643 12:12:30.886901 Set Vref, RX VrefLevel [Byte0]: 28
8644 12:12:30.890004 [Byte1]: 28
8645 12:12:30.894109
8646 12:12:30.894531 Set Vref, RX VrefLevel [Byte0]: 29
8647 12:12:30.897333 [Byte1]: 29
8648 12:12:30.901656
8649 12:12:30.902078 Set Vref, RX VrefLevel [Byte0]: 30
8650 12:12:30.904934 [Byte1]: 30
8651 12:12:30.909547
8652 12:12:30.909971 Set Vref, RX VrefLevel [Byte0]: 31
8653 12:12:30.912632 [Byte1]: 31
8654 12:12:30.916634
8655 12:12:30.919975 Set Vref, RX VrefLevel [Byte0]: 32
8656 12:12:30.923507 [Byte1]: 32
8657 12:12:30.924014
8658 12:12:30.926637 Set Vref, RX VrefLevel [Byte0]: 33
8659 12:12:30.929902 [Byte1]: 33
8660 12:12:30.930382
8661 12:12:30.933134 Set Vref, RX VrefLevel [Byte0]: 34
8662 12:12:30.936819 [Byte1]: 34
8663 12:12:30.937244
8664 12:12:30.939966 Set Vref, RX VrefLevel [Byte0]: 35
8665 12:12:30.943320 [Byte1]: 35
8666 12:12:30.947563
8667 12:12:30.948045 Set Vref, RX VrefLevel [Byte0]: 36
8668 12:12:30.950521 [Byte1]: 36
8669 12:12:30.955226
8670 12:12:30.955737 Set Vref, RX VrefLevel [Byte0]: 37
8671 12:12:30.958271 [Byte1]: 37
8672 12:12:30.962616
8673 12:12:30.963040 Set Vref, RX VrefLevel [Byte0]: 38
8674 12:12:30.965887 [Byte1]: 38
8675 12:12:30.970253
8676 12:12:30.970675 Set Vref, RX VrefLevel [Byte0]: 39
8677 12:12:30.973634 [Byte1]: 39
8678 12:12:30.977795
8679 12:12:30.978214 Set Vref, RX VrefLevel [Byte0]: 40
8680 12:12:30.981068 [Byte1]: 40
8681 12:12:30.985662
8682 12:12:30.986082 Set Vref, RX VrefLevel [Byte0]: 41
8683 12:12:30.988943 [Byte1]: 41
8684 12:12:30.992979
8685 12:12:30.993400 Set Vref, RX VrefLevel [Byte0]: 42
8686 12:12:30.996208 [Byte1]: 42
8687 12:12:31.000421
8688 12:12:31.000844 Set Vref, RX VrefLevel [Byte0]: 43
8689 12:12:31.003990 [Byte1]: 43
8690 12:12:31.008278
8691 12:12:31.008701 Set Vref, RX VrefLevel [Byte0]: 44
8692 12:12:31.011639 [Byte1]: 44
8693 12:12:31.015835
8694 12:12:31.016382 Set Vref, RX VrefLevel [Byte0]: 45
8695 12:12:31.019178 [Byte1]: 45
8696 12:12:31.023590
8697 12:12:31.024009 Set Vref, RX VrefLevel [Byte0]: 46
8698 12:12:31.026670 [Byte1]: 46
8699 12:12:31.030915
8700 12:12:31.031366 Set Vref, RX VrefLevel [Byte0]: 47
8701 12:12:31.034411 [Byte1]: 47
8702 12:12:31.038650
8703 12:12:31.039069 Set Vref, RX VrefLevel [Byte0]: 48
8704 12:12:31.041907 [Byte1]: 48
8705 12:12:31.046392
8706 12:12:31.046812 Set Vref, RX VrefLevel [Byte0]: 49
8707 12:12:31.049663 [Byte1]: 49
8708 12:12:31.053793
8709 12:12:31.054227 Set Vref, RX VrefLevel [Byte0]: 50
8710 12:12:31.057325 [Byte1]: 50
8711 12:12:31.061522
8712 12:12:31.061957 Set Vref, RX VrefLevel [Byte0]: 51
8713 12:12:31.065102 [Byte1]: 51
8714 12:12:31.069244
8715 12:12:31.069708 Set Vref, RX VrefLevel [Byte0]: 52
8716 12:12:31.072466 [Byte1]: 52
8717 12:12:31.076615
8718 12:12:31.077050 Set Vref, RX VrefLevel [Byte0]: 53
8719 12:12:31.080195 [Byte1]: 53
8720 12:12:31.084225
8721 12:12:31.084640 Set Vref, RX VrefLevel [Byte0]: 54
8722 12:12:31.087707 [Byte1]: 54
8723 12:12:31.092059
8724 12:12:31.092478 Set Vref, RX VrefLevel [Byte0]: 55
8725 12:12:31.095283 [Byte1]: 55
8726 12:12:31.099553
8727 12:12:31.099971 Set Vref, RX VrefLevel [Byte0]: 56
8728 12:12:31.103010 [Byte1]: 56
8729 12:12:31.107268
8730 12:12:31.107701 Set Vref, RX VrefLevel [Byte0]: 57
8731 12:12:31.110668 [Byte1]: 57
8732 12:12:31.114975
8733 12:12:31.115395 Set Vref, RX VrefLevel [Byte0]: 58
8734 12:12:31.118175 [Byte1]: 58
8735 12:12:31.122587
8736 12:12:31.123025 Set Vref, RX VrefLevel [Byte0]: 59
8737 12:12:31.125715 [Byte1]: 59
8738 12:12:31.130147
8739 12:12:31.130566 Set Vref, RX VrefLevel [Byte0]: 60
8740 12:12:31.133144 [Byte1]: 60
8741 12:12:31.137554
8742 12:12:31.137976 Set Vref, RX VrefLevel [Byte0]: 61
8743 12:12:31.140947 [Byte1]: 61
8744 12:12:31.145267
8745 12:12:31.145748 Set Vref, RX VrefLevel [Byte0]: 62
8746 12:12:31.148537 [Byte1]: 62
8747 12:12:31.152820
8748 12:12:31.153237 Set Vref, RX VrefLevel [Byte0]: 63
8749 12:12:31.156353 [Byte1]: 63
8750 12:12:31.160657
8751 12:12:31.161078 Set Vref, RX VrefLevel [Byte0]: 64
8752 12:12:31.163797 [Byte1]: 64
8753 12:12:31.168095
8754 12:12:31.168512 Set Vref, RX VrefLevel [Byte0]: 65
8755 12:12:31.171509 [Byte1]: 65
8756 12:12:31.175835
8757 12:12:31.176254 Set Vref, RX VrefLevel [Byte0]: 66
8758 12:12:31.179143 [Byte1]: 66
8759 12:12:31.183310
8760 12:12:31.183732 Set Vref, RX VrefLevel [Byte0]: 67
8761 12:12:31.186732 [Byte1]: 67
8762 12:12:31.190681
8763 12:12:31.191062 Set Vref, RX VrefLevel [Byte0]: 68
8764 12:12:31.194399 [Byte1]: 68
8765 12:12:31.198499
8766 12:12:31.198880 Set Vref, RX VrefLevel [Byte0]: 69
8767 12:12:31.201789 [Byte1]: 69
8768 12:12:31.205989
8769 12:12:31.206376 Set Vref, RX VrefLevel [Byte0]: 70
8770 12:12:31.209401 [Byte1]: 70
8771 12:12:31.213642
8772 12:12:31.214047 Final RX Vref Byte 0 = 56 to rank0
8773 12:12:31.217139 Final RX Vref Byte 1 = 55 to rank0
8774 12:12:31.220277 Final RX Vref Byte 0 = 56 to rank1
8775 12:12:31.223517 Final RX Vref Byte 1 = 55 to rank1==
8776 12:12:31.226962 Dram Type= 6, Freq= 0, CH_1, rank 0
8777 12:12:31.233436 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8778 12:12:31.233922 ==
8779 12:12:31.234278 DQS Delay:
8780 12:12:31.237038 DQS0 = 0, DQS1 = 0
8781 12:12:31.237429 DQM Delay:
8782 12:12:31.237814 DQM0 = 130, DQM1 = 123
8783 12:12:31.240192 DQ Delay:
8784 12:12:31.243495 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =126
8785 12:12:31.246671 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =126
8786 12:12:31.250103 DQ8 =110, DQ9 =112, DQ10 =122, DQ11 =116
8787 12:12:31.253411 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =130
8788 12:12:31.253847
8789 12:12:31.254215
8790 12:12:31.254529
8791 12:12:31.256539 [DramC_TX_OE_Calibration] TA2
8792 12:12:31.259829 Original DQ_B0 (3 6) =30, OEN = 27
8793 12:12:31.263545 Original DQ_B1 (3 6) =30, OEN = 27
8794 12:12:31.266618 24, 0x0, End_B0=24 End_B1=24
8795 12:12:31.267110 25, 0x0, End_B0=25 End_B1=25
8796 12:12:31.270083 26, 0x0, End_B0=26 End_B1=26
8797 12:12:31.273135 27, 0x0, End_B0=27 End_B1=27
8798 12:12:31.276730 28, 0x0, End_B0=28 End_B1=28
8799 12:12:31.279941 29, 0x0, End_B0=29 End_B1=29
8800 12:12:31.280369 30, 0x0, End_B0=30 End_B1=30
8801 12:12:31.283127 31, 0x4141, End_B0=30 End_B1=30
8802 12:12:31.286500 Byte0 end_step=30 best_step=27
8803 12:12:31.289864 Byte1 end_step=30 best_step=27
8804 12:12:31.292968 Byte0 TX OE(2T, 0.5T) = (3, 3)
8805 12:12:31.296497 Byte1 TX OE(2T, 0.5T) = (3, 3)
8806 12:12:31.296963
8807 12:12:31.297329
8808 12:12:31.303209 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8809 12:12:31.306350 CH1 RK0: MR19=303, MR18=A0F
8810 12:12:31.312909 CH1_RK0: MR19=0x303, MR18=0xA0F, DQSOSC=402, MR23=63, INC=22, DEC=15
8811 12:12:31.313375
8812 12:12:31.316106 ----->DramcWriteLeveling(PI) begin...
8813 12:12:31.316606 ==
8814 12:12:31.319430 Dram Type= 6, Freq= 0, CH_1, rank 1
8815 12:12:31.322950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8816 12:12:31.323419 ==
8817 12:12:31.326295 Write leveling (Byte 0): 25 => 25
8818 12:12:31.329348 Write leveling (Byte 1): 29 => 29
8819 12:12:31.332681 DramcWriteLeveling(PI) end<-----
8820 12:12:31.333143
8821 12:12:31.333561 ==
8822 12:12:31.336063 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 12:12:31.339841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 12:12:31.340309 ==
8825 12:12:31.342831 [Gating] SW mode calibration
8826 12:12:31.349108 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8827 12:12:31.356137 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8828 12:12:31.359308 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 12:12:31.365882 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 12:12:31.369392 1 4 8 | B1->B0 | 2423 2f2f | 1 1 | (0 0) (1 1)
8831 12:12:31.372560 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8832 12:12:31.379082 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 12:12:31.382419 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 12:12:31.385968 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 12:12:31.392272 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 12:12:31.395807 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8837 12:12:31.399049 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8838 12:12:31.405588 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8839 12:12:31.409067 1 5 12 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8840 12:12:31.412401 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 12:12:31.415649 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 12:12:31.422293 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 12:12:31.425246 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 12:12:31.428758 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 12:12:31.435402 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 12:12:31.438652 1 6 8 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
8847 12:12:31.441956 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 12:12:31.448437 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 12:12:31.452025 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 12:12:31.455179 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 12:12:31.461652 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 12:12:31.465369 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8853 12:12:31.468297 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8854 12:12:31.474804 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8855 12:12:31.478110 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8856 12:12:31.481686 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 12:12:31.488197 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 12:12:31.491271 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 12:12:31.494722 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 12:12:31.501086 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 12:12:31.504881 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 12:12:31.507943 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 12:12:31.514438 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 12:12:31.517659 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 12:12:31.521124 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 12:12:31.527833 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 12:12:31.531283 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 12:12:31.534365 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 12:12:31.541111 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 12:12:31.544330 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8871 12:12:31.547661 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8872 12:12:31.550976 Total UI for P1: 0, mck2ui 16
8873 12:12:31.554375 best dqsien dly found for B0: ( 1, 9, 8)
8874 12:12:31.561119 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8875 12:12:31.561621 Total UI for P1: 0, mck2ui 16
8876 12:12:31.567698 best dqsien dly found for B1: ( 1, 9, 10)
8877 12:12:31.571051 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8878 12:12:31.574479 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8879 12:12:31.574870
8880 12:12:31.577531 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8881 12:12:31.580835 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8882 12:12:31.584271 [Gating] SW calibration Done
8883 12:12:31.584684 ==
8884 12:12:31.587388 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 12:12:31.590850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 12:12:31.591243 ==
8887 12:12:31.593860 RX Vref Scan: 0
8888 12:12:31.594265
8889 12:12:31.594582 RX Vref 0 -> 0, step: 1
8890 12:12:31.594936
8891 12:12:31.597321 RX Delay 0 -> 252, step: 8
8892 12:12:31.600646 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8893 12:12:31.607270 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8894 12:12:31.610619 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8895 12:12:31.614039 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8896 12:12:31.617182 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8897 12:12:31.620708 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8898 12:12:31.627214 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8899 12:12:31.630585 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8900 12:12:31.633611 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8901 12:12:31.636920 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8902 12:12:31.640334 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8903 12:12:31.646940 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8904 12:12:31.650358 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8905 12:12:31.653335 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8906 12:12:31.656927 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8907 12:12:31.663585 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8908 12:12:31.663690 ==
8909 12:12:31.666818 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 12:12:31.670113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 12:12:31.670205 ==
8912 12:12:31.670280 DQS Delay:
8913 12:12:31.673224 DQS0 = 0, DQS1 = 0
8914 12:12:31.673327 DQM Delay:
8915 12:12:31.676660 DQM0 = 132, DQM1 = 128
8916 12:12:31.676731 DQ Delay:
8917 12:12:31.680038 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8918 12:12:31.683460 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8919 12:12:31.686763 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8920 12:12:31.689727 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8921 12:12:31.689799
8922 12:12:31.689868
8923 12:12:31.693264 ==
8924 12:12:31.693333 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 12:12:31.699594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 12:12:31.699673 ==
8927 12:12:31.699737
8928 12:12:31.699796
8929 12:12:31.703041 TX Vref Scan disable
8930 12:12:31.703112 == TX Byte 0 ==
8931 12:12:31.706412 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8932 12:12:31.712940 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8933 12:12:31.713022 == TX Byte 1 ==
8934 12:12:31.716514 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8935 12:12:31.722894 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8936 12:12:31.722984 ==
8937 12:12:31.725965 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 12:12:31.729508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 12:12:31.729595 ==
8940 12:12:31.742582
8941 12:12:31.746181 TX Vref early break, caculate TX vref
8942 12:12:31.749545 TX Vref=16, minBit 8, minWin=22, winSum=379
8943 12:12:31.752916 TX Vref=18, minBit 0, minWin=23, winSum=386
8944 12:12:31.755890 TX Vref=20, minBit 0, minWin=24, winSum=398
8945 12:12:31.759337 TX Vref=22, minBit 0, minWin=24, winSum=404
8946 12:12:31.762681 TX Vref=24, minBit 0, minWin=25, winSum=414
8947 12:12:31.769427 TX Vref=26, minBit 0, minWin=24, winSum=421
8948 12:12:31.772515 TX Vref=28, minBit 1, minWin=25, winSum=422
8949 12:12:31.776142 TX Vref=30, minBit 8, minWin=24, winSum=416
8950 12:12:31.779361 TX Vref=32, minBit 8, minWin=23, winSum=409
8951 12:12:31.782940 TX Vref=34, minBit 5, minWin=23, winSum=398
8952 12:12:31.789398 [TxChooseVref] Worse bit 1, Min win 25, Win sum 422, Final Vref 28
8953 12:12:31.789630
8954 12:12:31.792945 Final TX Range 0 Vref 28
8955 12:12:31.793170
8956 12:12:31.793357 ==
8957 12:12:31.796207 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 12:12:31.799598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 12:12:31.799871 ==
8960 12:12:31.800091
8961 12:12:31.800337
8962 12:12:31.802862 TX Vref Scan disable
8963 12:12:31.809368 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8964 12:12:31.809796 == TX Byte 0 ==
8965 12:12:31.812832 u2DelayCellOfst[0]=18 cells (5 PI)
8966 12:12:31.816153 u2DelayCellOfst[1]=11 cells (3 PI)
8967 12:12:31.819536 u2DelayCellOfst[2]=0 cells (0 PI)
8968 12:12:31.822666 u2DelayCellOfst[3]=7 cells (2 PI)
8969 12:12:31.826101 u2DelayCellOfst[4]=7 cells (2 PI)
8970 12:12:31.829330 u2DelayCellOfst[5]=22 cells (6 PI)
8971 12:12:31.832467 u2DelayCellOfst[6]=18 cells (5 PI)
8972 12:12:31.835643 u2DelayCellOfst[7]=7 cells (2 PI)
8973 12:12:31.839148 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8974 12:12:31.842277 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8975 12:12:31.845914 == TX Byte 1 ==
8976 12:12:31.846317 u2DelayCellOfst[8]=0 cells (0 PI)
8977 12:12:31.849067 u2DelayCellOfst[9]=3 cells (1 PI)
8978 12:12:31.852572 u2DelayCellOfst[10]=11 cells (3 PI)
8979 12:12:31.855631 u2DelayCellOfst[11]=7 cells (2 PI)
8980 12:12:31.859140 u2DelayCellOfst[12]=15 cells (4 PI)
8981 12:12:31.862490 u2DelayCellOfst[13]=15 cells (4 PI)
8982 12:12:31.865472 u2DelayCellOfst[14]=18 cells (5 PI)
8983 12:12:31.868905 u2DelayCellOfst[15]=18 cells (5 PI)
8984 12:12:31.872284 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8985 12:12:31.878935 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8986 12:12:31.879360 DramC Write-DBI on
8987 12:12:31.879709 ==
8988 12:12:31.882168 Dram Type= 6, Freq= 0, CH_1, rank 1
8989 12:12:31.888723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8990 12:12:31.889263 ==
8991 12:12:31.889847
8992 12:12:31.890209
8993 12:12:31.890561 TX Vref Scan disable
8994 12:12:31.892611 == TX Byte 0 ==
8995 12:12:31.895731 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8996 12:12:31.899014 == TX Byte 1 ==
8997 12:12:31.902169 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8998 12:12:31.905458 DramC Write-DBI off
8999 12:12:31.905763
9000 12:12:31.906034 [DATLAT]
9001 12:12:31.906258 Freq=1600, CH1 RK1
9002 12:12:31.906498
9003 12:12:31.908582 DATLAT Default: 0xf
9004 12:12:31.911884 0, 0xFFFF, sum = 0
9005 12:12:31.912069 1, 0xFFFF, sum = 0
9006 12:12:31.915303 2, 0xFFFF, sum = 0
9007 12:12:31.915484 3, 0xFFFF, sum = 0
9008 12:12:31.918620 4, 0xFFFF, sum = 0
9009 12:12:31.918757 5, 0xFFFF, sum = 0
9010 12:12:31.921754 6, 0xFFFF, sum = 0
9011 12:12:31.921874 7, 0xFFFF, sum = 0
9012 12:12:31.925221 8, 0xFFFF, sum = 0
9013 12:12:31.925364 9, 0xFFFF, sum = 0
9014 12:12:31.928219 10, 0xFFFF, sum = 0
9015 12:12:31.928337 11, 0xFFFF, sum = 0
9016 12:12:31.932000 12, 0xFFFF, sum = 0
9017 12:12:31.932098 13, 0x8FFF, sum = 0
9018 12:12:31.935106 14, 0x0, sum = 1
9019 12:12:31.935206 15, 0x0, sum = 2
9020 12:12:31.938606 16, 0x0, sum = 3
9021 12:12:31.938700 17, 0x0, sum = 4
9022 12:12:31.941709 best_step = 15
9023 12:12:31.941783
9024 12:12:31.941846 ==
9025 12:12:31.944959 Dram Type= 6, Freq= 0, CH_1, rank 1
9026 12:12:31.948715 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9027 12:12:31.948790 ==
9028 12:12:31.951479 RX Vref Scan: 0
9029 12:12:31.951556
9030 12:12:31.951618 RX Vref 0 -> 0, step: 1
9031 12:12:31.951677
9032 12:12:31.954916 RX Delay 11 -> 252, step: 4
9033 12:12:31.961832 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9034 12:12:31.964742 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9035 12:12:31.968151 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
9036 12:12:31.971611 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9037 12:12:31.975050 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9038 12:12:31.981378 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
9039 12:12:31.985028 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
9040 12:12:31.988100 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9041 12:12:31.991392 iDelay=195, Bit 8, Center 112 (55 ~ 170) 116
9042 12:12:31.994969 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9043 12:12:32.001592 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9044 12:12:32.004980 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9045 12:12:32.008352 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9046 12:12:32.011245 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9047 12:12:32.014663 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9048 12:12:32.021409 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9049 12:12:32.021786 ==
9050 12:12:32.025041 Dram Type= 6, Freq= 0, CH_1, rank 1
9051 12:12:32.028340 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9052 12:12:32.028800 ==
9053 12:12:32.029152 DQS Delay:
9054 12:12:32.031307 DQS0 = 0, DQS1 = 0
9055 12:12:32.031731 DQM Delay:
9056 12:12:32.034697 DQM0 = 129, DQM1 = 125
9057 12:12:32.035266 DQ Delay:
9058 12:12:32.038165 DQ0 =134, DQ1 =128, DQ2 =116, DQ3 =126
9059 12:12:32.041418 DQ4 =124, DQ5 =140, DQ6 =142, DQ7 =124
9060 12:12:32.044717 DQ8 =112, DQ9 =112, DQ10 =128, DQ11 =120
9061 12:12:32.048013 DQ12 =132, DQ13 =134, DQ14 =132, DQ15 =134
9062 12:12:32.048455
9063 12:12:32.051532
9064 12:12:32.051968
9065 12:12:32.052411 [DramC_TX_OE_Calibration] TA2
9066 12:12:32.054660 Original DQ_B0 (3 6) =30, OEN = 27
9067 12:12:32.058031 Original DQ_B1 (3 6) =30, OEN = 27
9068 12:12:32.061324 24, 0x0, End_B0=24 End_B1=24
9069 12:12:32.064664 25, 0x0, End_B0=25 End_B1=25
9070 12:12:32.068019 26, 0x0, End_B0=26 End_B1=26
9071 12:12:32.068554 27, 0x0, End_B0=27 End_B1=27
9072 12:12:32.071211 28, 0x0, End_B0=28 End_B1=28
9073 12:12:32.074390 29, 0x0, End_B0=29 End_B1=29
9074 12:12:32.077781 30, 0x0, End_B0=30 End_B1=30
9075 12:12:32.081175 31, 0x4141, End_B0=30 End_B1=30
9076 12:12:32.081663 Byte0 end_step=30 best_step=27
9077 12:12:32.084455 Byte1 end_step=30 best_step=27
9078 12:12:32.087902 Byte0 TX OE(2T, 0.5T) = (3, 3)
9079 12:12:32.091158 Byte1 TX OE(2T, 0.5T) = (3, 3)
9080 12:12:32.091716
9081 12:12:32.092151
9082 12:12:32.097788 [DQSOSCAuto] RK1, (LSB)MR18= 0x131f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
9083 12:12:32.101092 CH1 RK1: MR19=303, MR18=131F
9084 12:12:32.107841 CH1_RK1: MR19=0x303, MR18=0x131F, DQSOSC=394, MR23=63, INC=23, DEC=15
9085 12:12:32.111054 [RxdqsGatingPostProcess] freq 1600
9086 12:12:32.117951 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9087 12:12:32.121050 best DQS0 dly(2T, 0.5T) = (1, 1)
9088 12:12:32.124449 best DQS1 dly(2T, 0.5T) = (1, 1)
9089 12:12:32.125029 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9090 12:12:32.127799 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9091 12:12:32.130878 best DQS0 dly(2T, 0.5T) = (1, 1)
9092 12:12:32.134237 best DQS1 dly(2T, 0.5T) = (1, 1)
9093 12:12:32.137334 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9094 12:12:32.140718 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9095 12:12:32.144195 Pre-setting of DQS Precalculation
9096 12:12:32.147582 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9097 12:12:32.157399 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9098 12:12:32.163987 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9099 12:12:32.164414
9100 12:12:32.164755
9101 12:12:32.167520 [Calibration Summary] 3200 Mbps
9102 12:12:32.167946 CH 0, Rank 0
9103 12:12:32.170812 SW Impedance : PASS
9104 12:12:32.173778 DUTY Scan : NO K
9105 12:12:32.174204 ZQ Calibration : PASS
9106 12:12:32.177303 Jitter Meter : NO K
9107 12:12:32.180412 CBT Training : PASS
9108 12:12:32.181011 Write leveling : PASS
9109 12:12:32.183875 RX DQS gating : PASS
9110 12:12:32.184314 RX DQ/DQS(RDDQC) : PASS
9111 12:12:32.186895 TX DQ/DQS : PASS
9112 12:12:32.190372 RX DATLAT : PASS
9113 12:12:32.190812 RX DQ/DQS(Engine): PASS
9114 12:12:32.193715 TX OE : PASS
9115 12:12:32.194227 All Pass.
9116 12:12:32.194673
9117 12:12:32.197187 CH 0, Rank 1
9118 12:12:32.197665 SW Impedance : PASS
9119 12:12:32.200068 DUTY Scan : NO K
9120 12:12:32.203341 ZQ Calibration : PASS
9121 12:12:32.203902 Jitter Meter : NO K
9122 12:12:32.206716 CBT Training : PASS
9123 12:12:32.210242 Write leveling : PASS
9124 12:12:32.210682 RX DQS gating : PASS
9125 12:12:32.213533 RX DQ/DQS(RDDQC) : PASS
9126 12:12:32.216668 TX DQ/DQS : PASS
9127 12:12:32.217110 RX DATLAT : PASS
9128 12:12:32.220376 RX DQ/DQS(Engine): PASS
9129 12:12:32.223340 TX OE : PASS
9130 12:12:32.223778 All Pass.
9131 12:12:32.224216
9132 12:12:32.224635 CH 1, Rank 0
9133 12:12:32.226751 SW Impedance : PASS
9134 12:12:32.230206 DUTY Scan : NO K
9135 12:12:32.230673 ZQ Calibration : PASS
9136 12:12:32.233242 Jitter Meter : NO K
9137 12:12:32.236623 CBT Training : PASS
9138 12:12:32.237063 Write leveling : PASS
9139 12:12:32.239658 RX DQS gating : PASS
9140 12:12:32.243176 RX DQ/DQS(RDDQC) : PASS
9141 12:12:32.243616 TX DQ/DQS : PASS
9142 12:12:32.246524 RX DATLAT : PASS
9143 12:12:32.246963 RX DQ/DQS(Engine): PASS
9144 12:12:32.249615 TX OE : PASS
9145 12:12:32.250057 All Pass.
9146 12:12:32.250500
9147 12:12:32.253177 CH 1, Rank 1
9148 12:12:32.253654 SW Impedance : PASS
9149 12:12:32.256613 DUTY Scan : NO K
9150 12:12:32.259933 ZQ Calibration : PASS
9151 12:12:32.260374 Jitter Meter : NO K
9152 12:12:32.263015 CBT Training : PASS
9153 12:12:32.266318 Write leveling : PASS
9154 12:12:32.266757 RX DQS gating : PASS
9155 12:12:32.269666 RX DQ/DQS(RDDQC) : PASS
9156 12:12:32.273000 TX DQ/DQS : PASS
9157 12:12:32.273442 RX DATLAT : PASS
9158 12:12:32.276211 RX DQ/DQS(Engine): PASS
9159 12:12:32.279613 TX OE : PASS
9160 12:12:32.280073 All Pass.
9161 12:12:32.280513
9162 12:12:32.282703 DramC Write-DBI on
9163 12:12:32.283143 PER_BANK_REFRESH: Hybrid Mode
9164 12:12:32.286111 TX_TRACKING: ON
9165 12:12:32.296071 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9166 12:12:32.302730 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9167 12:12:32.309132 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9168 12:12:32.312434 [FAST_K] Save calibration result to emmc
9169 12:12:32.315884 sync common calibartion params.
9170 12:12:32.319158 sync cbt_mode0:1, 1:1
9171 12:12:32.319580 dram_init: ddr_geometry: 2
9172 12:12:32.322566 dram_init: ddr_geometry: 2
9173 12:12:32.325665 dram_init: ddr_geometry: 2
9174 12:12:32.329358 0:dram_rank_size:100000000
9175 12:12:32.329850 1:dram_rank_size:100000000
9176 12:12:32.335736 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9177 12:12:32.339003 DFS_SHUFFLE_HW_MODE: ON
9178 12:12:32.342672 dramc_set_vcore_voltage set vcore to 725000
9179 12:12:32.345466 Read voltage for 1600, 0
9180 12:12:32.345929 Vio18 = 0
9181 12:12:32.346265 Vcore = 725000
9182 12:12:32.348921 Vdram = 0
9183 12:12:32.349344 Vddq = 0
9184 12:12:32.349770 Vmddr = 0
9185 12:12:32.352323 switch to 3200 Mbps bootup
9186 12:12:32.352762 [DramcRunTimeConfig]
9187 12:12:32.355314 PHYPLL
9188 12:12:32.355749 DPM_CONTROL_AFTERK: ON
9189 12:12:32.358892 PER_BANK_REFRESH: ON
9190 12:12:32.362316 REFRESH_OVERHEAD_REDUCTION: ON
9191 12:12:32.362755 CMD_PICG_NEW_MODE: OFF
9192 12:12:32.365421 XRTWTW_NEW_MODE: ON
9193 12:12:32.365917 XRTRTR_NEW_MODE: ON
9194 12:12:32.368819 TX_TRACKING: ON
9195 12:12:32.369257 RDSEL_TRACKING: OFF
9196 12:12:32.372019 DQS Precalculation for DVFS: ON
9197 12:12:32.375425 RX_TRACKING: OFF
9198 12:12:32.375861 HW_GATING DBG: ON
9199 12:12:32.378519 ZQCS_ENABLE_LP4: ON
9200 12:12:32.378956 RX_PICG_NEW_MODE: ON
9201 12:12:32.381930 TX_PICG_NEW_MODE: ON
9202 12:12:32.382367 ENABLE_RX_DCM_DPHY: ON
9203 12:12:32.385322 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9204 12:12:32.388457 DUMMY_READ_FOR_TRACKING: OFF
9205 12:12:32.391964 !!! SPM_CONTROL_AFTERK: OFF
9206 12:12:32.395193 !!! SPM could not control APHY
9207 12:12:32.395639 IMPEDANCE_TRACKING: ON
9208 12:12:32.398369 TEMP_SENSOR: ON
9209 12:12:32.398808 HW_SAVE_FOR_SR: OFF
9210 12:12:32.401774 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9211 12:12:32.404891 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9212 12:12:32.408304 Read ODT Tracking: ON
9213 12:12:32.411590 Refresh Rate DeBounce: ON
9214 12:12:32.412030 DFS_NO_QUEUE_FLUSH: ON
9215 12:12:32.414707 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9216 12:12:32.418273 ENABLE_DFS_RUNTIME_MRW: OFF
9217 12:12:32.421463 DDR_RESERVE_NEW_MODE: ON
9218 12:12:32.421943 MR_CBT_SWITCH_FREQ: ON
9219 12:12:32.424827 =========================
9220 12:12:32.444049 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9221 12:12:32.447486 dram_init: ddr_geometry: 2
9222 12:12:32.465540 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9223 12:12:32.468883 dram_init: dram init end (result: 0)
9224 12:12:32.475786 DRAM-K: Full calibration passed in 24553 msecs
9225 12:12:32.478856 MRC: failed to locate region type 0.
9226 12:12:32.479298 DRAM rank0 size:0x100000000,
9227 12:12:32.482406 DRAM rank1 size=0x100000000
9228 12:12:32.491993 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9229 12:12:32.498677 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9230 12:12:32.505419 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9231 12:12:32.512101 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9232 12:12:32.515042 DRAM rank0 size:0x100000000,
9233 12:12:32.518413 DRAM rank1 size=0x100000000
9234 12:12:32.518852 CBMEM:
9235 12:12:32.521719 IMD: root @ 0xfffff000 254 entries.
9236 12:12:32.525045 IMD: root @ 0xffffec00 62 entries.
9237 12:12:32.528519 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9238 12:12:32.535024 WARNING: RO_VPD is uninitialized or empty.
9239 12:12:32.538256 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9240 12:12:32.546117 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9241 12:12:32.558473 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9242 12:12:32.570144 BS: romstage times (exec / console): total (unknown) / 24022 ms
9243 12:12:32.570664
9244 12:12:32.571066
9245 12:12:32.579635 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9246 12:12:32.583013 ARM64: Exception handlers installed.
9247 12:12:32.586290 ARM64: Testing exception
9248 12:12:32.589956 ARM64: Done test exception
9249 12:12:32.590386 Enumerating buses...
9250 12:12:32.592762 Show all devs... Before device enumeration.
9251 12:12:32.596285 Root Device: enabled 1
9252 12:12:32.599576 CPU_CLUSTER: 0: enabled 1
9253 12:12:32.600123 CPU: 00: enabled 1
9254 12:12:32.602685 Compare with tree...
9255 12:12:32.603092 Root Device: enabled 1
9256 12:12:32.606489 CPU_CLUSTER: 0: enabled 1
9257 12:12:32.609555 CPU: 00: enabled 1
9258 12:12:32.610137 Root Device scanning...
9259 12:12:32.612820 scan_static_bus for Root Device
9260 12:12:32.616453 CPU_CLUSTER: 0 enabled
9261 12:12:32.619953 scan_static_bus for Root Device done
9262 12:12:32.623003 scan_bus: bus Root Device finished in 8 msecs
9263 12:12:32.623449 done
9264 12:12:32.629574 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9265 12:12:32.632575 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9266 12:12:32.639442 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9267 12:12:32.642556 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9268 12:12:32.646142 Allocating resources...
9269 12:12:32.649145 Reading resources...
9270 12:12:32.652615 Root Device read_resources bus 0 link: 0
9271 12:12:32.653049 DRAM rank0 size:0x100000000,
9272 12:12:32.655973 DRAM rank1 size=0x100000000
9273 12:12:32.659268 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9274 12:12:32.662735 CPU: 00 missing read_resources
9275 12:12:32.669292 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9276 12:12:32.672375 Root Device read_resources bus 0 link: 0 done
9277 12:12:32.672805 Done reading resources.
9278 12:12:32.679236 Show resources in subtree (Root Device)...After reading.
9279 12:12:32.682195 Root Device child on link 0 CPU_CLUSTER: 0
9280 12:12:32.685738 CPU_CLUSTER: 0 child on link 0 CPU: 00
9281 12:12:32.695564 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9282 12:12:32.696000 CPU: 00
9283 12:12:32.699003 Root Device assign_resources, bus 0 link: 0
9284 12:12:32.701999 CPU_CLUSTER: 0 missing set_resources
9285 12:12:32.708694 Root Device assign_resources, bus 0 link: 0 done
9286 12:12:32.709179 Done setting resources.
9287 12:12:32.715472 Show resources in subtree (Root Device)...After assigning values.
9288 12:12:32.718805 Root Device child on link 0 CPU_CLUSTER: 0
9289 12:12:32.721958 CPU_CLUSTER: 0 child on link 0 CPU: 00
9290 12:12:32.731781 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9291 12:12:32.732216 CPU: 00
9292 12:12:32.735243 Done allocating resources.
9293 12:12:32.741645 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9294 12:12:32.742096 Enabling resources...
9295 12:12:32.742558 done.
9296 12:12:32.748270 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9297 12:12:32.751356 Initializing devices...
9298 12:12:32.751956 Root Device init
9299 12:12:32.754863 init hardware done!
9300 12:12:32.755346 0x00000018: ctrlr->caps
9301 12:12:32.758194 52.000 MHz: ctrlr->f_max
9302 12:12:32.761582 0.400 MHz: ctrlr->f_min
9303 12:12:32.762032 0x40ff8080: ctrlr->voltages
9304 12:12:32.764623 sclk: 390625
9305 12:12:32.765059 Bus Width = 1
9306 12:12:32.765615 sclk: 390625
9307 12:12:32.768021 Bus Width = 1
9308 12:12:32.768460 Early init status = 3
9309 12:12:32.774836 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9310 12:12:32.777967 in-header: 03 fc 00 00 01 00 00 00
9311 12:12:32.781354 in-data: 00
9312 12:12:32.784425 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9313 12:12:32.788670 in-header: 03 fd 00 00 00 00 00 00
9314 12:12:32.792195 in-data:
9315 12:12:32.795212 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9316 12:12:32.799412 in-header: 03 fc 00 00 01 00 00 00
9317 12:12:32.802686 in-data: 00
9318 12:12:32.805932 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9319 12:12:32.811399 in-header: 03 fd 00 00 00 00 00 00
9320 12:12:32.814795 in-data:
9321 12:12:32.817976 [SSUSB] Setting up USB HOST controller...
9322 12:12:32.821298 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9323 12:12:32.824559 [SSUSB] phy power-on done.
9324 12:12:32.828102 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9325 12:12:32.834508 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9326 12:12:32.837784 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9327 12:12:32.844389 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9328 12:12:32.850935 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9329 12:12:32.857903 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9330 12:12:32.864149 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9331 12:12:32.870854 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9332 12:12:32.874151 SPM: binary array size = 0x9dc
9333 12:12:32.877578 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9334 12:12:32.884631 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9335 12:12:32.891104 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9336 12:12:32.894123 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9337 12:12:32.900569 configure_display: Starting display init
9338 12:12:32.934571 anx7625_power_on_init: Init interface.
9339 12:12:32.938088 anx7625_disable_pd_protocol: Disabled PD feature.
9340 12:12:32.941049 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9341 12:12:32.969069 anx7625_start_dp_work: Secure OCM version=00
9342 12:12:32.972128 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9343 12:12:32.987108 sp_tx_get_edid_block: EDID Block = 1
9344 12:12:33.089762 Extracted contents:
9345 12:12:33.092908 header: 00 ff ff ff ff ff ff 00
9346 12:12:33.096259 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9347 12:12:33.099578 version: 01 04
9348 12:12:33.102979 basic params: 95 1f 11 78 0a
9349 12:12:33.106575 chroma info: 76 90 94 55 54 90 27 21 50 54
9350 12:12:33.109448 established: 00 00 00
9351 12:12:33.116264 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9352 12:12:33.119399 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9353 12:12:33.126253 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9354 12:12:33.132570 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9355 12:12:33.139237 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9356 12:12:33.142692 extensions: 00
9357 12:12:33.143131 checksum: fb
9358 12:12:33.143607
9359 12:12:33.145919 Manufacturer: IVO Model 57d Serial Number 0
9360 12:12:33.149322 Made week 0 of 2020
9361 12:12:33.149927 EDID version: 1.4
9362 12:12:33.152752 Digital display
9363 12:12:33.156767 6 bits per primary color channel
9364 12:12:33.157303 DisplayPort interface
9365 12:12:33.159033 Maximum image size: 31 cm x 17 cm
9366 12:12:33.162292 Gamma: 220%
9367 12:12:33.162799 Check DPMS levels
9368 12:12:33.165715 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9369 12:12:33.172066 First detailed timing is preferred timing
9370 12:12:33.172297 Established timings supported:
9371 12:12:33.175600 Standard timings supported:
9372 12:12:33.178792 Detailed timings
9373 12:12:33.182268 Hex of detail: 383680a07038204018303c0035ae10000019
9374 12:12:33.185418 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9375 12:12:33.191816 0780 0798 07c8 0820 hborder 0
9376 12:12:33.195309 0438 043b 0447 0458 vborder 0
9377 12:12:33.198523 -hsync -vsync
9378 12:12:33.198748 Did detailed timing
9379 12:12:33.205383 Hex of detail: 000000000000000000000000000000000000
9380 12:12:33.208569 Manufacturer-specified data, tag 0
9381 12:12:33.211940 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9382 12:12:33.215200 ASCII string: InfoVision
9383 12:12:33.218828 Hex of detail: 000000fe00523134304e574635205248200a
9384 12:12:33.222470 ASCII string: R140NWF5 RH
9385 12:12:33.222939 Checksum
9386 12:12:33.225466 Checksum: 0xfb (valid)
9387 12:12:33.228803 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9388 12:12:33.231922 DSI data_rate: 832800000 bps
9389 12:12:33.238678 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9390 12:12:33.241850 anx7625_parse_edid: pixelclock(138800).
9391 12:12:33.245066 hactive(1920), hsync(48), hfp(24), hbp(88)
9392 12:12:33.248460 vactive(1080), vsync(12), vfp(3), vbp(17)
9393 12:12:33.251925 anx7625_dsi_config: config dsi.
9394 12:12:33.258717 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9395 12:12:33.271766 anx7625_dsi_config: success to config DSI
9396 12:12:33.275010 anx7625_dp_start: MIPI phy setup OK.
9397 12:12:33.278352 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9398 12:12:33.281444 mtk_ddp_mode_set invalid vrefresh 60
9399 12:12:33.284721 main_disp_path_setup
9400 12:12:33.285144 ovl_layer_smi_id_en
9401 12:12:33.288186 ovl_layer_smi_id_en
9402 12:12:33.288745 ccorr_config
9403 12:12:33.289088 aal_config
9404 12:12:33.291651 gamma_config
9405 12:12:33.292118 postmask_config
9406 12:12:33.294911 dither_config
9407 12:12:33.298009 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9408 12:12:33.304803 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9409 12:12:33.308178 Root Device init finished in 553 msecs
9410 12:12:33.311210 CPU_CLUSTER: 0 init
9411 12:12:33.318069 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9412 12:12:33.324657 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9413 12:12:33.325097 APU_MBOX 0x190000b0 = 0x10001
9414 12:12:33.328145 APU_MBOX 0x190001b0 = 0x10001
9415 12:12:33.331099 APU_MBOX 0x190005b0 = 0x10001
9416 12:12:33.334413 APU_MBOX 0x190006b0 = 0x10001
9417 12:12:33.340749 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9418 12:12:33.350743 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9419 12:12:33.363145 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9420 12:12:33.369649 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9421 12:12:33.381321 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9422 12:12:33.390521 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9423 12:12:33.393909 CPU_CLUSTER: 0 init finished in 81 msecs
9424 12:12:33.397006 Devices initialized
9425 12:12:33.400496 Show all devs... After init.
9426 12:12:33.400922 Root Device: enabled 1
9427 12:12:33.404030 CPU_CLUSTER: 0: enabled 1
9428 12:12:33.407085 CPU: 00: enabled 1
9429 12:12:33.410371 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9430 12:12:33.413867 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9431 12:12:33.417010 ELOG: NV offset 0x57f000 size 0x1000
9432 12:12:33.423637 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9433 12:12:33.430363 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9434 12:12:33.433515 ELOG: Event(17) added with size 13 at 2024-01-31 12:12:33 UTC
9435 12:12:33.439978 out: cmd=0x121: 03 db 21 01 00 00 00 00
9436 12:12:33.443215 in-header: 03 49 00 00 2c 00 00 00
9437 12:12:33.453146 in-data: 15 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9438 12:12:33.459838 ELOG: Event(A1) added with size 10 at 2024-01-31 12:12:33 UTC
9439 12:12:33.466386 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9440 12:12:33.473088 ELOG: Event(A0) added with size 9 at 2024-01-31 12:12:33 UTC
9441 12:12:33.476460 elog_add_boot_reason: Logged dev mode boot
9442 12:12:33.483134 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9443 12:12:33.483567 Finalize devices...
9444 12:12:33.486462 Devices finalized
9445 12:12:33.489792 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9446 12:12:33.493364 Writing coreboot table at 0xffe64000
9447 12:12:33.496395 0. 000000000010a000-0000000000113fff: RAMSTAGE
9448 12:12:33.499821 1. 0000000040000000-00000000400fffff: RAM
9449 12:12:33.506411 2. 0000000040100000-000000004032afff: RAMSTAGE
9450 12:12:33.509803 3. 000000004032b000-00000000545fffff: RAM
9451 12:12:33.513140 4. 0000000054600000-000000005465ffff: BL31
9452 12:12:33.516474 5. 0000000054660000-00000000ffe63fff: RAM
9453 12:12:33.522917 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9454 12:12:33.526250 7. 0000000100000000-000000023fffffff: RAM
9455 12:12:33.529584 Passing 5 GPIOs to payload:
9456 12:12:33.532970 NAME | PORT | POLARITY | VALUE
9457 12:12:33.536173 EC in RW | 0x000000aa | low | undefined
9458 12:12:33.543028 EC interrupt | 0x00000005 | low | undefined
9459 12:12:33.546537 TPM interrupt | 0x000000ab | high | undefined
9460 12:12:33.553098 SD card detect | 0x00000011 | high | undefined
9461 12:12:33.555933 speaker enable | 0x00000093 | high | undefined
9462 12:12:33.559351 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9463 12:12:33.562575 in-header: 03 f9 00 00 02 00 00 00
9464 12:12:33.565799 in-data: 02 00
9465 12:12:33.566229 ADC[4]: Raw value=897040 ID=7
9466 12:12:33.569175 ADC[3]: Raw value=213070 ID=1
9467 12:12:33.572457 RAM Code: 0x71
9468 12:12:33.575939 ADC[6]: Raw value=75092 ID=0
9469 12:12:33.576368 ADC[5]: Raw value=211960 ID=1
9470 12:12:33.579378 SKU Code: 0x1
9471 12:12:33.582595 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum e0ef
9472 12:12:33.585845 coreboot table: 964 bytes.
9473 12:12:33.588892 IMD ROOT 0. 0xfffff000 0x00001000
9474 12:12:33.592149 IMD SMALL 1. 0xffffe000 0x00001000
9475 12:12:33.595651 RO MCACHE 2. 0xffffc000 0x00001104
9476 12:12:33.598967 CONSOLE 3. 0xfff7c000 0x00080000
9477 12:12:33.602380 FMAP 4. 0xfff7b000 0x00000452
9478 12:12:33.605611 TIME STAMP 5. 0xfff7a000 0x00000910
9479 12:12:33.609028 VBOOT WORK 6. 0xfff66000 0x00014000
9480 12:12:33.612395 RAMOOPS 7. 0xffe66000 0x00100000
9481 12:12:33.615829 COREBOOT 8. 0xffe64000 0x00002000
9482 12:12:33.618883 IMD small region:
9483 12:12:33.621888 IMD ROOT 0. 0xffffec00 0x00000400
9484 12:12:33.625427 VPD 1. 0xffffeb80 0x0000006c
9485 12:12:33.628651 MMC STATUS 2. 0xffffeb60 0x00000004
9486 12:12:33.632118 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9487 12:12:33.635069 Probing TPM: done!
9488 12:12:33.638569 Connected to device vid:did:rid of 1ae0:0028:00
9489 12:12:33.649338 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9490 12:12:33.652826 Initialized TPM device CR50 revision 0
9491 12:12:33.656338 Checking cr50 for pending updates
9492 12:12:33.659985 Reading cr50 TPM mode
9493 12:12:33.668964 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9494 12:12:33.675670 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9495 12:12:33.715332 read SPI 0x3990ec 0x4f1b0: 34858 us, 9295 KB/s, 74.360 Mbps
9496 12:12:33.719046 Checking segment from ROM address 0x40100000
9497 12:12:33.722360 Checking segment from ROM address 0x4010001c
9498 12:12:33.729186 Loading segment from ROM address 0x40100000
9499 12:12:33.729661 code (compression=0)
9500 12:12:33.735573 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9501 12:12:33.745456 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9502 12:12:33.745969 it's not compressed!
9503 12:12:33.752487 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9504 12:12:33.755607 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9505 12:12:33.775888 Loading segment from ROM address 0x4010001c
9506 12:12:33.776311 Entry Point 0x80000000
9507 12:12:33.779155 Loaded segments
9508 12:12:33.782620 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9509 12:12:33.789378 Jumping to boot code at 0x80000000(0xffe64000)
9510 12:12:33.795718 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9511 12:12:33.802655 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9512 12:12:33.810368 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9513 12:12:33.813612 Checking segment from ROM address 0x40100000
9514 12:12:33.816998 Checking segment from ROM address 0x4010001c
9515 12:12:33.823387 Loading segment from ROM address 0x40100000
9516 12:12:33.823810 code (compression=1)
9517 12:12:33.830335 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9518 12:12:33.840252 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9519 12:12:33.840676 using LZMA
9520 12:12:33.848748 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9521 12:12:33.855534 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9522 12:12:33.858897 Loading segment from ROM address 0x4010001c
9523 12:12:33.859373 Entry Point 0x54601000
9524 12:12:33.862075 Loaded segments
9525 12:12:33.865556 NOTICE: MT8192 bl31_setup
9526 12:12:33.872464 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9527 12:12:33.875828 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9528 12:12:33.878967 WARNING: region 0:
9529 12:12:33.882441 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9530 12:12:33.882871 WARNING: region 1:
9531 12:12:33.888860 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9532 12:12:33.892312 WARNING: region 2:
9533 12:12:33.895646 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9534 12:12:33.898793 WARNING: region 3:
9535 12:12:33.902361 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9536 12:12:33.905958 WARNING: region 4:
9537 12:12:33.912077 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9538 12:12:33.912509 WARNING: region 5:
9539 12:12:33.915597 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9540 12:12:33.919022 WARNING: region 6:
9541 12:12:33.922035 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9542 12:12:33.922465 WARNING: region 7:
9543 12:12:33.928501 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9544 12:12:33.935235 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9545 12:12:33.938676 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9546 12:12:33.941911 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9547 12:12:33.948543 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9548 12:12:33.951745 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9549 12:12:33.955208 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9550 12:12:33.961830 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9551 12:12:33.965138 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9552 12:12:33.971663 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9553 12:12:33.975235 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9554 12:12:33.978332 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9555 12:12:33.985039 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9556 12:12:33.987967 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9557 12:12:33.991280 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9558 12:12:33.998197 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9559 12:12:34.001358 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9560 12:12:34.008131 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9561 12:12:34.011487 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9562 12:12:34.014733 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9563 12:12:34.021173 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9564 12:12:34.024473 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9565 12:12:34.031346 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9566 12:12:34.034675 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9567 12:12:34.037995 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9568 12:12:34.044719 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9569 12:12:34.047845 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9570 12:12:34.054689 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9571 12:12:34.058193 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9572 12:12:34.061387 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9573 12:12:34.068160 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9574 12:12:34.071363 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9575 12:12:34.074681 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9576 12:12:34.081394 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9577 12:12:34.084526 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9578 12:12:34.087943 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9579 12:12:34.091443 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9580 12:12:34.098285 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9581 12:12:34.101620 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9582 12:12:34.104663 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9583 12:12:34.108090 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9584 12:12:34.114639 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9585 12:12:34.118111 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9586 12:12:34.121268 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9587 12:12:34.124611 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9588 12:12:34.131296 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9589 12:12:34.134947 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9590 12:12:34.138246 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9591 12:12:34.141261 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9592 12:12:34.148030 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9593 12:12:34.151603 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9594 12:12:34.158256 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9595 12:12:34.161588 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9596 12:12:34.168068 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9597 12:12:34.171475 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9598 12:12:34.174748 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9599 12:12:34.181281 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9600 12:12:34.184532 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9601 12:12:34.191396 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9602 12:12:34.194727 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9603 12:12:34.201323 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9604 12:12:34.204715 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9605 12:12:34.208263 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9606 12:12:34.214683 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9607 12:12:34.218135 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9608 12:12:34.224582 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9609 12:12:34.228061 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9610 12:12:34.234710 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9611 12:12:34.238113 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9612 12:12:34.241172 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9613 12:12:34.247881 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9614 12:12:34.251320 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9615 12:12:34.257703 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9616 12:12:34.261107 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9617 12:12:34.267813 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9618 12:12:34.271115 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9619 12:12:34.274481 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9620 12:12:34.281368 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9621 12:12:34.284501 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9622 12:12:34.291212 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9623 12:12:34.294406 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9624 12:12:34.301144 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9625 12:12:34.304322 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9626 12:12:34.311303 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9627 12:12:34.314557 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9628 12:12:34.317674 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9629 12:12:34.324758 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9630 12:12:34.327811 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9631 12:12:34.334481 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9632 12:12:34.337943 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9633 12:12:34.344380 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9634 12:12:34.347892 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9635 12:12:34.351014 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9636 12:12:34.357687 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9637 12:12:34.361082 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9638 12:12:34.367885 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9639 12:12:34.371101 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9640 12:12:34.374572 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9641 12:12:34.380954 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9642 12:12:34.384298 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9643 12:12:34.387797 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9644 12:12:34.391281 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9645 12:12:34.397685 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9646 12:12:34.401017 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9647 12:12:34.407528 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9648 12:12:34.411047 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9649 12:12:34.417448 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9650 12:12:34.421028 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9651 12:12:34.424253 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9652 12:12:34.430684 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9653 12:12:34.434121 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9654 12:12:34.437268 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9655 12:12:34.444308 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9656 12:12:34.447138 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9657 12:12:34.454016 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9658 12:12:34.457308 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9659 12:12:34.460769 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9660 12:12:34.467114 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9661 12:12:34.470837 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9662 12:12:34.473911 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9663 12:12:34.480725 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9664 12:12:34.483772 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9665 12:12:34.487127 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9666 12:12:34.490558 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9667 12:12:34.497377 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9668 12:12:34.500443 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9669 12:12:34.503761 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9670 12:12:34.510363 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9671 12:12:34.513775 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9672 12:12:34.520611 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9673 12:12:34.523688 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9674 12:12:34.527260 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9675 12:12:34.533754 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9676 12:12:34.537155 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9677 12:12:34.543885 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9678 12:12:34.547195 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9679 12:12:34.550265 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9680 12:12:34.557026 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9681 12:12:34.560360 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9682 12:12:34.563578 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9683 12:12:34.570450 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9684 12:12:34.573685 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9685 12:12:34.580596 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9686 12:12:34.583935 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9687 12:12:34.587540 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9688 12:12:34.593722 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9689 12:12:34.597436 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9690 12:12:34.603816 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9691 12:12:34.607078 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9692 12:12:34.610763 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9693 12:12:34.617185 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9694 12:12:34.620340 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9695 12:12:34.623710 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9696 12:12:34.630532 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9697 12:12:34.634155 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9698 12:12:34.640648 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9699 12:12:34.643772 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9700 12:12:34.647149 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9701 12:12:34.653782 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9702 12:12:34.656981 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9703 12:12:34.663896 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9704 12:12:34.667220 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9705 12:12:34.670341 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9706 12:12:34.677000 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9707 12:12:34.680268 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9708 12:12:34.687138 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9709 12:12:34.690360 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9710 12:12:34.693337 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9711 12:12:34.700193 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9712 12:12:34.703511 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9713 12:12:34.710006 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9714 12:12:34.713326 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9715 12:12:34.716890 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9716 12:12:34.723113 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9717 12:12:34.726542 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9718 12:12:34.730008 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9719 12:12:34.736668 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9720 12:12:34.740039 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9721 12:12:34.746393 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9722 12:12:34.749919 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9723 12:12:34.753315 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9724 12:12:34.759733 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9725 12:12:34.762765 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9726 12:12:34.769613 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9727 12:12:34.772999 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9728 12:12:34.776207 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9729 12:12:34.782939 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9730 12:12:34.786309 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9731 12:12:34.792748 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9732 12:12:34.795813 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9733 12:12:34.802698 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9734 12:12:34.805844 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9735 12:12:34.809159 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9736 12:12:34.815985 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9737 12:12:34.819089 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9738 12:12:34.825963 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9739 12:12:34.829226 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9740 12:12:34.832690 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9741 12:12:34.839217 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9742 12:12:34.842193 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9743 12:12:34.848788 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9744 12:12:34.852420 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9745 12:12:34.858691 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9746 12:12:34.862073 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9747 12:12:34.865543 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9748 12:12:34.871975 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9749 12:12:34.875512 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9750 12:12:34.881868 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9751 12:12:34.885284 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9752 12:12:34.892026 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9753 12:12:34.895363 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9754 12:12:34.898426 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9755 12:12:34.904974 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9756 12:12:34.908239 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9757 12:12:34.914743 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9758 12:12:34.918253 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9759 12:12:34.921636 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9760 12:12:34.928085 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9761 12:12:34.931265 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9762 12:12:34.938195 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9763 12:12:34.941335 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9764 12:12:34.947890 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9765 12:12:34.951445 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9766 12:12:34.954619 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9767 12:12:34.961417 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9768 12:12:34.964577 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9769 12:12:34.971059 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9770 12:12:34.974692 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9771 12:12:34.981263 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9772 12:12:34.984645 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9773 12:12:34.987583 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9774 12:12:34.991252 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9775 12:12:34.997681 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9776 12:12:35.001129 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9777 12:12:35.004099 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9778 12:12:35.007756 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9779 12:12:35.014438 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9780 12:12:35.017726 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9781 12:12:35.024260 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9782 12:12:35.027483 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9783 12:12:35.030912 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9784 12:12:35.037457 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9785 12:12:35.040813 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9786 12:12:35.047405 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9787 12:12:35.050877 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9788 12:12:35.053817 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9789 12:12:35.060491 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9790 12:12:35.064069 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9791 12:12:35.067328 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9792 12:12:35.073797 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9793 12:12:35.077164 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9794 12:12:35.080462 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9795 12:12:35.087187 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9796 12:12:35.090487 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9797 12:12:35.093598 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9798 12:12:35.100383 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9799 12:12:35.103702 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9800 12:12:35.110632 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9801 12:12:35.114032 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9802 12:12:35.117270 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9803 12:12:35.123855 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9804 12:12:35.127144 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9805 12:12:35.133956 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9806 12:12:35.137099 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9807 12:12:35.140459 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9808 12:12:35.147194 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9809 12:12:35.150204 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9810 12:12:35.153433 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9811 12:12:35.159955 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9812 12:12:35.163841 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9813 12:12:35.166905 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9814 12:12:35.170113 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9815 12:12:35.177108 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9816 12:12:35.180174 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9817 12:12:35.183643 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9818 12:12:35.186729 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9819 12:12:35.193543 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9820 12:12:35.196817 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9821 12:12:35.200036 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9822 12:12:35.203522 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9823 12:12:35.210011 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9824 12:12:35.213332 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9825 12:12:35.216768 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9826 12:12:35.223324 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9827 12:12:35.226727 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9828 12:12:35.230063 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9829 12:12:35.236669 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9830 12:12:35.240028 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9831 12:12:35.246852 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9832 12:12:35.249778 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9833 12:12:35.253279 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9834 12:12:35.259722 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9835 12:12:35.263357 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9836 12:12:35.269788 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9837 12:12:35.272978 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9838 12:12:35.279761 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9839 12:12:35.283110 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9840 12:12:35.289541 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9841 12:12:35.292826 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9842 12:12:35.296459 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9843 12:12:35.302924 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9844 12:12:35.306268 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9845 12:12:35.309620 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9846 12:12:35.315913 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9847 12:12:35.319474 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9848 12:12:35.326045 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9849 12:12:35.329549 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9850 12:12:35.332685 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9851 12:12:35.339485 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9852 12:12:35.342788 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9853 12:12:35.349588 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9854 12:12:35.352601 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9855 12:12:35.359068 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9856 12:12:35.362588 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9857 12:12:35.366014 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9858 12:12:35.372481 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9859 12:12:35.376021 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9860 12:12:35.382646 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9861 12:12:35.385945 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9862 12:12:35.389220 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9863 12:12:35.395699 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9864 12:12:35.399061 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9865 12:12:35.405644 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9866 12:12:35.409032 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9867 12:12:35.415461 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9868 12:12:35.418633 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9869 12:12:35.422095 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9870 12:12:35.428687 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9871 12:12:35.431799 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9872 12:12:35.438724 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9873 12:12:35.441999 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9874 12:12:35.445142 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9875 12:12:35.451708 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9876 12:12:35.455252 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9877 12:12:35.461683 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9878 12:12:35.465078 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9879 12:12:35.471579 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9880 12:12:35.475072 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9881 12:12:35.478259 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9882 12:12:35.485050 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9883 12:12:35.488225 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9884 12:12:35.494910 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9885 12:12:35.498317 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9886 12:12:35.501424 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9887 12:12:35.508356 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9888 12:12:35.511326 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9889 12:12:35.517981 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9890 12:12:35.521314 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9891 12:12:35.524699 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9892 12:12:35.530961 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9893 12:12:35.534518 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9894 12:12:35.541181 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9895 12:12:35.544555 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9896 12:12:35.551305 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9897 12:12:35.554510 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9898 12:12:35.557957 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9899 12:12:35.564654 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9900 12:12:35.567865 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9901 12:12:35.574672 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9902 12:12:35.577722 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9903 12:12:35.584639 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9904 12:12:35.587645 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9905 12:12:35.591194 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9906 12:12:35.597860 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9907 12:12:35.600980 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9908 12:12:35.607525 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9909 12:12:35.610773 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9910 12:12:35.617529 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9911 12:12:35.620862 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9912 12:12:35.627482 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9913 12:12:35.630670 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9914 12:12:35.634270 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9915 12:12:35.640583 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9916 12:12:35.644103 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9917 12:12:35.650643 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9918 12:12:35.653921 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9919 12:12:35.660372 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9920 12:12:35.663789 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9921 12:12:35.667099 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9922 12:12:35.673670 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9923 12:12:35.677283 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9924 12:12:35.683740 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9925 12:12:35.686970 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9926 12:12:35.693595 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9927 12:12:35.696842 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9928 12:12:35.703524 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9929 12:12:35.706977 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9930 12:12:35.710129 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9931 12:12:35.716950 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9932 12:12:35.720375 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9933 12:12:35.726612 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9934 12:12:35.729946 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9935 12:12:35.736584 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9936 12:12:35.739971 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9937 12:12:35.743549 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9938 12:12:35.750065 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9939 12:12:35.753177 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9940 12:12:35.760045 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9941 12:12:35.763452 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9942 12:12:35.770122 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9943 12:12:35.773222 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9944 12:12:35.779836 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9945 12:12:35.783281 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9946 12:12:35.786396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9947 12:12:35.793095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9948 12:12:35.796079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9949 12:12:35.803007 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9950 12:12:35.806303 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9951 12:12:35.812867 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9952 12:12:35.815964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9953 12:12:35.822560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9954 12:12:35.826188 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9955 12:12:35.832655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9956 12:12:35.835740 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9957 12:12:35.842252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9958 12:12:35.845538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9959 12:12:35.849061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9960 12:12:35.855790 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9961 12:12:35.858885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9962 12:12:35.865778 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9963 12:12:35.868825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9964 12:12:35.875651 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9965 12:12:35.878939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9966 12:12:35.885663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9967 12:12:35.888912 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9968 12:12:35.895411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9969 12:12:35.899049 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9970 12:12:35.905292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9971 12:12:35.908990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9972 12:12:35.915336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9973 12:12:35.918899 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9974 12:12:35.925537 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9975 12:12:35.929062 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9976 12:12:35.935586 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9977 12:12:35.938853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9978 12:12:35.945432 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9979 12:12:35.945895 INFO: [APUAPC] vio 0
9980 12:12:35.952279 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9981 12:12:35.955470 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9982 12:12:35.958918 INFO: [APUAPC] D0_APC_0: 0x400510
9983 12:12:35.962208 INFO: [APUAPC] D0_APC_1: 0x0
9984 12:12:35.965681 INFO: [APUAPC] D0_APC_2: 0x1540
9985 12:12:35.969169 INFO: [APUAPC] D0_APC_3: 0x0
9986 12:12:35.972240 INFO: [APUAPC] D1_APC_0: 0xffffffff
9987 12:12:35.975590 INFO: [APUAPC] D1_APC_1: 0xffffffff
9988 12:12:35.979079 INFO: [APUAPC] D1_APC_2: 0x3fffff
9989 12:12:35.982240 INFO: [APUAPC] D1_APC_3: 0x0
9990 12:12:35.985719 INFO: [APUAPC] D2_APC_0: 0xffffffff
9991 12:12:35.988750 INFO: [APUAPC] D2_APC_1: 0xffffffff
9992 12:12:35.992039 INFO: [APUAPC] D2_APC_2: 0x3fffff
9993 12:12:35.995344 INFO: [APUAPC] D2_APC_3: 0x0
9994 12:12:35.998645 INFO: [APUAPC] D3_APC_0: 0xffffffff
9995 12:12:36.002111 INFO: [APUAPC] D3_APC_1: 0xffffffff
9996 12:12:36.005164 INFO: [APUAPC] D3_APC_2: 0x3fffff
9997 12:12:36.008417 INFO: [APUAPC] D3_APC_3: 0x0
9998 12:12:36.011863 INFO: [APUAPC] D4_APC_0: 0xffffffff
9999 12:12:36.015243 INFO: [APUAPC] D4_APC_1: 0xffffffff
10000 12:12:36.018398 INFO: [APUAPC] D4_APC_2: 0x3fffff
10001 12:12:36.022154 INFO: [APUAPC] D4_APC_3: 0x0
10002 12:12:36.025433 INFO: [APUAPC] D5_APC_0: 0xffffffff
10003 12:12:36.028167 INFO: [APUAPC] D5_APC_1: 0xffffffff
10004 12:12:36.031631 INFO: [APUAPC] D5_APC_2: 0x3fffff
10005 12:12:36.032060 INFO: [APUAPC] D5_APC_3: 0x0
10006 12:12:36.035115 INFO: [APUAPC] D6_APC_0: 0xffffffff
10007 12:12:36.041569 INFO: [APUAPC] D6_APC_1: 0xffffffff
10008 12:12:36.041997 INFO: [APUAPC] D6_APC_2: 0x3fffff
10009 12:12:36.045000 INFO: [APUAPC] D6_APC_3: 0x0
10010 12:12:36.048413 INFO: [APUAPC] D7_APC_0: 0xffffffff
10011 12:12:36.051556 INFO: [APUAPC] D7_APC_1: 0xffffffff
10012 12:12:36.054801 INFO: [APUAPC] D7_APC_2: 0x3fffff
10013 12:12:36.058295 INFO: [APUAPC] D7_APC_3: 0x0
10014 12:12:36.061404 INFO: [APUAPC] D8_APC_0: 0xffffffff
10015 12:12:36.064687 INFO: [APUAPC] D8_APC_1: 0xffffffff
10016 12:12:36.067981 INFO: [APUAPC] D8_APC_2: 0x3fffff
10017 12:12:36.071428 INFO: [APUAPC] D8_APC_3: 0x0
10018 12:12:36.074814 INFO: [APUAPC] D9_APC_0: 0xffffffff
10019 12:12:36.078214 INFO: [APUAPC] D9_APC_1: 0xffffffff
10020 12:12:36.081701 INFO: [APUAPC] D9_APC_2: 0x3fffff
10021 12:12:36.084720 INFO: [APUAPC] D9_APC_3: 0x0
10022 12:12:36.088161 INFO: [APUAPC] D10_APC_0: 0xffffffff
10023 12:12:36.091175 INFO: [APUAPC] D10_APC_1: 0xffffffff
10024 12:12:36.094778 INFO: [APUAPC] D10_APC_2: 0x3fffff
10025 12:12:36.097861 INFO: [APUAPC] D10_APC_3: 0x0
10026 12:12:36.101036 INFO: [APUAPC] D11_APC_0: 0xffffffff
10027 12:12:36.104237 INFO: [APUAPC] D11_APC_1: 0xffffffff
10028 12:12:36.107747 INFO: [APUAPC] D11_APC_2: 0x3fffff
10029 12:12:36.111207 INFO: [APUAPC] D11_APC_3: 0x0
10030 12:12:36.114274 INFO: [APUAPC] D12_APC_0: 0xffffffff
10031 12:12:36.117660 INFO: [APUAPC] D12_APC_1: 0xffffffff
10032 12:12:36.121114 INFO: [APUAPC] D12_APC_2: 0x3fffff
10033 12:12:36.124550 INFO: [APUAPC] D12_APC_3: 0x0
10034 12:12:36.127464 INFO: [APUAPC] D13_APC_0: 0xffffffff
10035 12:12:36.131041 INFO: [APUAPC] D13_APC_1: 0xffffffff
10036 12:12:36.134431 INFO: [APUAPC] D13_APC_2: 0x3fffff
10037 12:12:36.137588 INFO: [APUAPC] D13_APC_3: 0x0
10038 12:12:36.140895 INFO: [APUAPC] D14_APC_0: 0xffffffff
10039 12:12:36.143936 INFO: [APUAPC] D14_APC_1: 0xffffffff
10040 12:12:36.150552 INFO: [APUAPC] D14_APC_2: 0x3fffff
10041 12:12:36.150995 INFO: [APUAPC] D14_APC_3: 0x0
10042 12:12:36.153896 INFO: [APUAPC] D15_APC_0: 0xffffffff
10043 12:12:36.160478 INFO: [APUAPC] D15_APC_1: 0xffffffff
10044 12:12:36.164066 INFO: [APUAPC] D15_APC_2: 0x3fffff
10045 12:12:36.164491 INFO: [APUAPC] D15_APC_3: 0x0
10046 12:12:36.167717 INFO: [APUAPC] APC_CON: 0x4
10047 12:12:36.170584 INFO: [NOCDAPC] D0_APC_0: 0x0
10048 12:12:36.173809 INFO: [NOCDAPC] D0_APC_1: 0x0
10049 12:12:36.177542 INFO: [NOCDAPC] D1_APC_0: 0x0
10050 12:12:36.180541 INFO: [NOCDAPC] D1_APC_1: 0xfff
10051 12:12:36.183837 INFO: [NOCDAPC] D2_APC_0: 0x0
10052 12:12:36.187044 INFO: [NOCDAPC] D2_APC_1: 0xfff
10053 12:12:36.190378 INFO: [NOCDAPC] D3_APC_0: 0x0
10054 12:12:36.190832 INFO: [NOCDAPC] D3_APC_1: 0xfff
10055 12:12:36.194027 INFO: [NOCDAPC] D4_APC_0: 0x0
10056 12:12:36.196938 INFO: [NOCDAPC] D4_APC_1: 0xfff
10057 12:12:36.200261 INFO: [NOCDAPC] D5_APC_0: 0x0
10058 12:12:36.203880 INFO: [NOCDAPC] D5_APC_1: 0xfff
10059 12:12:36.206963 INFO: [NOCDAPC] D6_APC_0: 0x0
10060 12:12:36.210293 INFO: [NOCDAPC] D6_APC_1: 0xfff
10061 12:12:36.213773 INFO: [NOCDAPC] D7_APC_0: 0x0
10062 12:12:36.216971 INFO: [NOCDAPC] D7_APC_1: 0xfff
10063 12:12:36.220215 INFO: [NOCDAPC] D8_APC_0: 0x0
10064 12:12:36.223591 INFO: [NOCDAPC] D8_APC_1: 0xfff
10065 12:12:36.224023 INFO: [NOCDAPC] D9_APC_0: 0x0
10066 12:12:36.226737 INFO: [NOCDAPC] D9_APC_1: 0xfff
10067 12:12:36.230115 INFO: [NOCDAPC] D10_APC_0: 0x0
10068 12:12:36.233580 INFO: [NOCDAPC] D10_APC_1: 0xfff
10069 12:12:36.236606 INFO: [NOCDAPC] D11_APC_0: 0x0
10070 12:12:36.240152 INFO: [NOCDAPC] D11_APC_1: 0xfff
10071 12:12:36.243315 INFO: [NOCDAPC] D12_APC_0: 0x0
10072 12:12:36.246817 INFO: [NOCDAPC] D12_APC_1: 0xfff
10073 12:12:36.250019 INFO: [NOCDAPC] D13_APC_0: 0x0
10074 12:12:36.253436 INFO: [NOCDAPC] D13_APC_1: 0xfff
10075 12:12:36.256882 INFO: [NOCDAPC] D14_APC_0: 0x0
10076 12:12:36.260231 INFO: [NOCDAPC] D14_APC_1: 0xfff
10077 12:12:36.263357 INFO: [NOCDAPC] D15_APC_0: 0x0
10078 12:12:36.266664 INFO: [NOCDAPC] D15_APC_1: 0xfff
10079 12:12:36.267094 INFO: [NOCDAPC] APC_CON: 0x4
10080 12:12:36.273422 INFO: [APUAPC] set_apusys_apc done
10081 12:12:36.273886 INFO: [DEVAPC] devapc_init done
10082 12:12:36.279942 INFO: GICv3 without legacy support detected.
10083 12:12:36.283371 INFO: ARM GICv3 driver initialized in EL3
10084 12:12:36.286597 INFO: Maximum SPI INTID supported: 639
10085 12:12:36.289878 INFO: BL31: Initializing runtime services
10086 12:12:36.296476 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10087 12:12:36.300001 INFO: SPM: enable CPC mode
10088 12:12:36.303102 INFO: mcdi ready for mcusys-off-idle and system suspend
10089 12:12:36.309860 INFO: BL31: Preparing for EL3 exit to normal world
10090 12:12:36.313180 INFO: Entry point address = 0x80000000
10091 12:12:36.313649 INFO: SPSR = 0x8
10092 12:12:36.320211
10093 12:12:36.320781
10094 12:12:36.321137
10095 12:12:36.323631 Starting depthcharge on Spherion...
10096 12:12:36.324059
10097 12:12:36.324398 Wipe memory regions:
10098 12:12:36.324714
10099 12:12:36.327233 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10100 12:12:36.327747 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10101 12:12:36.328169 Setting prompt string to ['asurada:']
10102 12:12:36.328623 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10103 12:12:36.329326 [0x00000040000000, 0x00000054600000)
10104 12:12:36.449280
10105 12:12:36.449772 [0x00000054660000, 0x00000080000000)
10106 12:12:36.709560
10107 12:12:36.710115 [0x000000821a7280, 0x000000ffe64000)
10108 12:12:37.453655
10109 12:12:37.454145 [0x00000100000000, 0x00000240000000)
10110 12:12:39.341427
10111 12:12:39.344554 Initializing XHCI USB controller at 0x11200000.
10112 12:12:40.382479
10113 12:12:40.385573 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10114 12:12:40.386053
10115 12:12:40.386434
10116 12:12:40.386790
10117 12:12:40.387610 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10119 12:12:40.488821 asurada: tftpboot 192.168.201.1 12669498/tftp-deploy-anyajq8p/kernel/image.itb 12669498/tftp-deploy-anyajq8p/kernel/cmdline
10120 12:12:40.489335 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10121 12:12:40.489782 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10122 12:12:40.494095 tftpboot 192.168.201.1 12669498/tftp-deploy-anyajq8p/kernel/image.itp-deploy-anyajq8p/kernel/cmdline
10123 12:12:40.494547
10124 12:12:40.494894 Waiting for link
10125 12:12:40.654529
10126 12:12:40.654991 R8152: Initializing
10127 12:12:40.655339
10128 12:12:40.657917 Version 6 (ocp_data = 5c30)
10129 12:12:40.658351
10130 12:12:40.661326 R8152: Done initializing
10131 12:12:40.661784
10132 12:12:40.662128 Adding net device
10133 12:12:42.561920
10134 12:12:42.562430 done.
10135 12:12:42.562779
10136 12:12:42.563103 MAC: 00:24:32:30:78:ff
10137 12:12:42.563415
10138 12:12:42.565162 Sending DHCP discover... done.
10139 12:12:42.565632
10140 12:12:46.247528 Waiting for reply... done.
10141 12:12:46.248136
10142 12:12:46.248524 Sending DHCP request... done.
10143 12:12:46.250735
10144 12:12:46.255668 Waiting for reply... done.
10145 12:12:46.256304
10146 12:12:46.256762 My ip is 192.168.201.21
10147 12:12:46.257139
10148 12:12:46.259017 The DHCP server ip is 192.168.201.1
10149 12:12:46.259533
10150 12:12:46.265682 TFTP server IP predefined by user: 192.168.201.1
10151 12:12:46.266249
10152 12:12:46.272302 Bootfile predefined by user: 12669498/tftp-deploy-anyajq8p/kernel/image.itb
10153 12:12:46.272869
10154 12:12:46.273244 Sending tftp read request... done.
10155 12:12:46.275522
10156 12:12:46.282498 Waiting for the transfer...
10157 12:12:46.283085
10158 12:12:46.983110 00000000 ################################################################
10159 12:12:46.983681
10160 12:12:47.683813 00080000 ################################################################
10161 12:12:47.684312
10162 12:12:48.362829 00100000 ################################################################
10163 12:12:48.363346
10164 12:12:49.038895 00180000 ################################################################
10165 12:12:49.039397
10166 12:12:49.745504 00200000 ################################################################
10167 12:12:49.746006
10168 12:12:50.449594 00280000 ################################################################
10169 12:12:50.450085
10170 12:12:51.094872 00300000 ################################################################
10171 12:12:51.095015
10172 12:12:51.762664 00380000 ################################################################
10173 12:12:51.763185
10174 12:12:52.464463 00400000 ################################################################
10175 12:12:52.465035
10176 12:12:53.179450 00480000 ################################################################
10177 12:12:53.179966
10178 12:12:53.821256 00500000 ################################################################
10179 12:12:53.821410
10180 12:12:54.518154 00580000 ################################################################
10181 12:12:54.518699
10182 12:12:55.121065 00600000 ################################################################
10183 12:12:55.121200
10184 12:12:55.675599 00680000 ################################################################
10185 12:12:55.675742
10186 12:12:56.223037 00700000 ################################################################
10187 12:12:56.223190
10188 12:12:56.796409 00780000 ################################################################
10189 12:12:56.796586
10190 12:12:57.364563 00800000 ################################################################
10191 12:12:57.364710
10192 12:12:57.919017 00880000 ################################################################
10193 12:12:57.919164
10194 12:12:58.481099 00900000 ################################################################
10195 12:12:58.481251
10196 12:12:59.040781 00980000 ################################################################
10197 12:12:59.040942
10198 12:12:59.598740 00a00000 ################################################################
10199 12:12:59.598891
10200 12:13:00.150632 00a80000 ################################################################
10201 12:13:00.150786
10202 12:13:00.707097 00b00000 ################################################################
10203 12:13:00.707244
10204 12:13:01.278299 00b80000 ################################################################
10205 12:13:01.278451
10206 12:13:01.832639 00c00000 ################################################################
10207 12:13:01.832793
10208 12:13:02.377685 00c80000 ################################################################
10209 12:13:02.377835
10210 12:13:02.926601 00d00000 ################################################################
10211 12:13:02.926757
10212 12:13:03.490385 00d80000 ################################################################
10213 12:13:03.490556
10214 12:13:04.023520 00e00000 ################################################################
10215 12:13:04.023664
10216 12:13:04.579501 00e80000 ################################################################
10217 12:13:04.579651
10218 12:13:05.154331 00f00000 ################################################################
10219 12:13:05.154484
10220 12:13:05.703070 00f80000 ################################################################
10221 12:13:05.703228
10222 12:13:06.258008 01000000 ################################################################
10223 12:13:06.258163
10224 12:13:06.828635 01080000 ################################################################
10225 12:13:06.828790
10226 12:13:07.385284 01100000 ################################################################
10227 12:13:07.385441
10228 12:13:07.931691 01180000 ################################################################
10229 12:13:07.931852
10230 12:13:08.476120 01200000 ################################################################
10231 12:13:08.476286
10232 12:13:09.030776 01280000 ################################################################
10233 12:13:09.030939
10234 12:13:09.577695 01300000 ################################################################
10235 12:13:09.577854
10236 12:13:10.120153 01380000 ################################################################
10237 12:13:10.120297
10238 12:13:10.674400 01400000 ################################################################
10239 12:13:10.674538
10240 12:13:11.232560 01480000 ################################################################
10241 12:13:11.232709
10242 12:13:11.793452 01500000 ################################################################
10243 12:13:11.793650
10244 12:13:12.312401 01580000 ################################################################
10245 12:13:12.312574
10246 12:13:12.835072 01600000 ################################################################
10247 12:13:12.835227
10248 12:13:13.368279 01680000 ################################################################
10249 12:13:13.368446
10250 12:13:13.903075 01700000 ################################################################
10251 12:13:13.903229
10252 12:13:14.442037 01780000 ################################################################
10253 12:13:14.442189
10254 12:13:14.989912 01800000 ################################################################
10255 12:13:14.990046
10256 12:13:15.525131 01880000 ################################################################
10257 12:13:15.525287
10258 12:13:16.048362 01900000 ################################################################
10259 12:13:16.048515
10260 12:13:16.564460 01980000 ################################################################
10261 12:13:16.564615
10262 12:13:17.099617 01a00000 ################################################################
10263 12:13:17.099752
10264 12:13:17.665211 01a80000 ################################################################
10265 12:13:17.665362
10266 12:13:18.281425 01b00000 ################################################################
10267 12:13:18.281620
10268 12:13:18.881046 01b80000 ################################################################
10269 12:13:18.881275
10270 12:13:19.527608 01c00000 ################################################################
10271 12:13:19.528112
10272 12:13:19.548145 01c80000 ## done.
10273 12:13:19.548752
10274 12:13:19.551599 The bootfile was 29900790 bytes long.
10275 12:13:19.552032
10276 12:13:19.554612 Sending tftp read request... done.
10277 12:13:19.555043
10278 12:13:19.558338 Waiting for the transfer...
10279 12:13:19.558771
10280 12:13:19.559114 00000000 # done.
10281 12:13:19.559445
10282 12:13:19.565170 Command line loaded dynamically from TFTP file: 12669498/tftp-deploy-anyajq8p/kernel/cmdline
10283 12:13:19.565769
10284 12:13:19.588570 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12669498/extract-nfsrootfs-y_nv2isg,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10285 12:13:19.589096
10286 12:13:19.589440 Loading FIT.
10287 12:13:19.589817
10288 12:13:19.591747 Image ramdisk-1 has 17804195 bytes.
10289 12:13:19.592178
10290 12:13:19.594828 Image fdt-1 has 47278 bytes.
10291 12:13:19.595257
10292 12:13:19.598513 Image kernel-1 has 12047284 bytes.
10293 12:13:19.598943
10294 12:13:19.608324 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10295 12:13:19.608836
10296 12:13:19.625135 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10297 12:13:19.625721
10298 12:13:19.631291 Choosing best match conf-1 for compat google,spherion-rev2.
10299 12:13:19.631803
10300 12:13:19.639828 Connected to device vid:did:rid of 1ae0:0028:00
10301 12:13:19.647783
10302 12:13:19.650643 tpm_get_response: command 0x17b, return code 0x0
10303 12:13:19.651076
10304 12:13:19.654236 ec_init: CrosEC protocol v3 supported (256, 248)
10305 12:13:19.658772
10306 12:13:19.662228 tpm_cleanup: add release locality here.
10307 12:13:19.662754
10308 12:13:19.663097 Shutting down all USB controllers.
10309 12:13:19.663418
10310 12:13:19.665344 Removing current net device
10311 12:13:19.665818
10312 12:13:19.672437 Exiting depthcharge with code 4 at timestamp: 72680206
10313 12:13:19.672986
10314 12:13:19.675681 LZMA decompressing kernel-1 to 0x821a6718
10315 12:13:19.676238
10316 12:13:19.678894 LZMA decompressing kernel-1 to 0x40000000
10317 12:13:21.177194
10318 12:13:21.177347 jumping to kernel
10319 12:13:21.177815 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10320 12:13:21.177928 start: 2.2.5 auto-login-action (timeout 00:03:40) [common]
10321 12:13:21.178008 Setting prompt string to ['Linux version [0-9]']
10322 12:13:21.178082 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10323 12:13:21.178167 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10324 12:13:21.259267
10325 12:13:21.262398 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10326 12:13:21.266022 start: 2.2.5.1 login-action (timeout 00:03:40) [common]
10327 12:13:21.266145 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10328 12:13:21.266243 Setting prompt string to []
10329 12:13:21.266341 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10330 12:13:21.266434 Using line separator: #'\n'#
10331 12:13:21.266505 No login prompt set.
10332 12:13:21.266587 Parsing kernel messages
10333 12:13:21.266654 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10334 12:13:21.266771 [login-action] Waiting for messages, (timeout 00:03:40)
10335 12:13:21.285839 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j93261-arm64-gcc-10-defconfig-arm64-chromebook-cwjwh) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024
10336 12:13:21.289129 [ 0.000000] random: crng init done
10337 12:13:21.295859 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10338 12:13:21.298861 [ 0.000000] efi: UEFI not found.
10339 12:13:21.305500 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10340 12:13:21.312195 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10341 12:13:21.322374 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10342 12:13:21.332000 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10343 12:13:21.338707 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10344 12:13:21.345259 [ 0.000000] printk: bootconsole [mtk8250] enabled
10345 12:13:21.352236 [ 0.000000] NUMA: No NUMA configuration found
10346 12:13:21.358432 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10347 12:13:21.361872 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10348 12:13:21.365259 [ 0.000000] Zone ranges:
10349 12:13:21.372190 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10350 12:13:21.374854 [ 0.000000] DMA32 empty
10351 12:13:21.381722 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10352 12:13:21.385050 [ 0.000000] Movable zone start for each node
10353 12:13:21.388468 [ 0.000000] Early memory node ranges
10354 12:13:21.394735 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10355 12:13:21.401435 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10356 12:13:21.408200 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10357 12:13:21.414844 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10358 12:13:21.421393 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10359 12:13:21.427839 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10360 12:13:21.483695 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10361 12:13:21.490407 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10362 12:13:21.496964 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10363 12:13:21.500135 [ 0.000000] psci: probing for conduit method from DT.
10364 12:13:21.506950 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10365 12:13:21.510072 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10366 12:13:21.517108 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10367 12:13:21.520089 [ 0.000000] psci: SMC Calling Convention v1.2
10368 12:13:21.526684 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10369 12:13:21.530054 [ 0.000000] Detected VIPT I-cache on CPU0
10370 12:13:21.536753 [ 0.000000] CPU features: detected: GIC system register CPU interface
10371 12:13:21.543216 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10372 12:13:21.549717 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10373 12:13:21.556341 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10374 12:13:21.562991 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10375 12:13:21.573109 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10376 12:13:21.576416 [ 0.000000] alternatives: applying boot alternatives
10377 12:13:21.583002 [ 0.000000] Fallback order for Node 0: 0
10378 12:13:21.589658 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10379 12:13:21.592801 [ 0.000000] Policy zone: Normal
10380 12:13:21.616379 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12669498/extract-nfsrootfs-y_nv2isg,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10381 12:13:21.626337 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10382 12:13:21.636599 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10383 12:13:21.646801 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10384 12:13:21.653199 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10385 12:13:21.656217 <6>[ 0.000000] software IO TLB: area num 8.
10386 12:13:21.711783 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10387 12:13:21.861876 <6>[ 0.000000] Memory: 7949868K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 402900K reserved, 32768K cma-reserved)
10388 12:13:21.868320 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10389 12:13:21.874729 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10390 12:13:21.878462 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10391 12:13:21.884842 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10392 12:13:21.891252 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10393 12:13:21.894391 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10394 12:13:21.904680 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10395 12:13:21.911588 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10396 12:13:21.914516 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10397 12:13:21.922163 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10398 12:13:21.925683 <6>[ 0.000000] GICv3: 608 SPIs implemented
10399 12:13:21.932378 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10400 12:13:21.935397 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10401 12:13:21.938927 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10402 12:13:21.948745 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10403 12:13:21.958878 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10404 12:13:21.971477 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10405 12:13:21.978241 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10406 12:13:21.987712 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10407 12:13:22.000734 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10408 12:13:22.007344 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10409 12:13:22.014129 <6>[ 0.009235] Console: colour dummy device 80x25
10410 12:13:22.024048 <6>[ 0.013962] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10411 12:13:22.030701 <6>[ 0.024403] pid_max: default: 32768 minimum: 301
10412 12:13:22.034201 <6>[ 0.029275] LSM: Security Framework initializing
10413 12:13:22.040954 <6>[ 0.034215] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10414 12:13:22.050485 <6>[ 0.042030] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10415 12:13:22.057130 <6>[ 0.051438] cblist_init_generic: Setting adjustable number of callback queues.
10416 12:13:22.063695 <6>[ 0.058881] cblist_init_generic: Setting shift to 3 and lim to 1.
10417 12:13:22.073614 <6>[ 0.065222] cblist_init_generic: Setting adjustable number of callback queues.
10418 12:13:22.080414 <6>[ 0.072649] cblist_init_generic: Setting shift to 3 and lim to 1.
10419 12:13:22.083624 <6>[ 0.079053] rcu: Hierarchical SRCU implementation.
10420 12:13:22.090349 <6>[ 0.084069] rcu: Max phase no-delay instances is 1000.
10421 12:13:22.097168 <6>[ 0.091128] EFI services will not be available.
10422 12:13:22.100275 <6>[ 0.096108] smp: Bringing up secondary CPUs ...
10423 12:13:22.108539 <6>[ 0.101189] Detected VIPT I-cache on CPU1
10424 12:13:22.115300 <6>[ 0.101259] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10425 12:13:22.121950 <6>[ 0.101290] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10426 12:13:22.125170 <6>[ 0.101629] Detected VIPT I-cache on CPU2
10427 12:13:22.135270 <6>[ 0.101680] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10428 12:13:22.141818 <6>[ 0.101697] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10429 12:13:22.145388 <6>[ 0.101955] Detected VIPT I-cache on CPU3
10430 12:13:22.151516 <6>[ 0.102002] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10431 12:13:22.157884 <6>[ 0.102016] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10432 12:13:22.161316 <6>[ 0.102322] CPU features: detected: Spectre-v4
10433 12:13:22.168044 <6>[ 0.102329] CPU features: detected: Spectre-BHB
10434 12:13:22.171199 <6>[ 0.102334] Detected PIPT I-cache on CPU4
10435 12:13:22.177976 <6>[ 0.102391] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10436 12:13:22.184474 <6>[ 0.102407] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10437 12:13:22.191171 <6>[ 0.102700] Detected PIPT I-cache on CPU5
10438 12:13:22.197624 <6>[ 0.102762] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10439 12:13:22.204222 <6>[ 0.102780] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10440 12:13:22.207750 <6>[ 0.103061] Detected PIPT I-cache on CPU6
10441 12:13:22.214566 <6>[ 0.103130] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10442 12:13:22.220781 <6>[ 0.103146] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10443 12:13:22.227466 <6>[ 0.103445] Detected PIPT I-cache on CPU7
10444 12:13:22.234371 <6>[ 0.103511] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10445 12:13:22.240795 <6>[ 0.103527] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10446 12:13:22.244071 <6>[ 0.103575] smp: Brought up 1 node, 8 CPUs
10447 12:13:22.250976 <6>[ 0.245029] SMP: Total of 8 processors activated.
10448 12:13:22.253972 <6>[ 0.249950] CPU features: detected: 32-bit EL0 Support
10449 12:13:22.264008 <6>[ 0.255346] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10450 12:13:22.270680 <6>[ 0.264200] CPU features: detected: Common not Private translations
10451 12:13:22.277116 <6>[ 0.270716] CPU features: detected: CRC32 instructions
10452 12:13:22.280411 <6>[ 0.276100] CPU features: detected: RCpc load-acquire (LDAPR)
10453 12:13:22.287123 <6>[ 0.282060] CPU features: detected: LSE atomic instructions
10454 12:13:22.293684 <6>[ 0.287877] CPU features: detected: Privileged Access Never
10455 12:13:22.300394 <6>[ 0.293657] CPU features: detected: RAS Extension Support
10456 12:13:22.306778 <6>[ 0.299265] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10457 12:13:22.310172 <6>[ 0.306530] CPU: All CPU(s) started at EL2
10458 12:13:22.316681 <6>[ 0.310847] alternatives: applying system-wide alternatives
10459 12:13:22.326244 <6>[ 0.321562] devtmpfs: initialized
10460 12:13:22.341784 <6>[ 0.330497] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10461 12:13:22.348652 <6>[ 0.340458] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10462 12:13:22.355416 <6>[ 0.348688] pinctrl core: initialized pinctrl subsystem
10463 12:13:22.358706 <6>[ 0.355330] DMI not present or invalid.
10464 12:13:22.365005 <6>[ 0.359748] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10465 12:13:22.375295 <6>[ 0.366630] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10466 12:13:22.381726 <6>[ 0.374214] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10467 12:13:22.391720 <6>[ 0.382442] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10468 12:13:22.394907 <6>[ 0.390688] audit: initializing netlink subsys (disabled)
10469 12:13:22.404856 <5>[ 0.396382] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10470 12:13:22.411225 <6>[ 0.397052] thermal_sys: Registered thermal governor 'step_wise'
10471 12:13:22.418146 <6>[ 0.404353] thermal_sys: Registered thermal governor 'power_allocator'
10472 12:13:22.421709 <6>[ 0.410610] cpuidle: using governor menu
10473 12:13:22.428015 <6>[ 0.421573] NET: Registered PF_QIPCRTR protocol family
10474 12:13:22.434721 <6>[ 0.427060] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10475 12:13:22.441220 <6>[ 0.434169] ASID allocator initialised with 32768 entries
10476 12:13:22.444509 <6>[ 0.440733] Serial: AMBA PL011 UART driver
10477 12:13:22.454482 <4>[ 0.449476] Trying to register duplicate clock ID: 134
10478 12:13:22.508911 <6>[ 0.506834] KASLR enabled
10479 12:13:22.523368 <6>[ 0.514589] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10480 12:13:22.529756 <6>[ 0.521601] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10481 12:13:22.536215 <6>[ 0.528089] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10482 12:13:22.542887 <6>[ 0.535093] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10483 12:13:22.549996 <6>[ 0.541583] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10484 12:13:22.556161 <6>[ 0.548586] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10485 12:13:22.562595 <6>[ 0.555074] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10486 12:13:22.569531 <6>[ 0.562080] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10487 12:13:22.572582 <6>[ 0.569591] ACPI: Interpreter disabled.
10488 12:13:22.581071 <6>[ 0.576011] iommu: Default domain type: Translated
10489 12:13:22.587530 <6>[ 0.581123] iommu: DMA domain TLB invalidation policy: strict mode
10490 12:13:22.590938 <5>[ 0.587782] SCSI subsystem initialized
10491 12:13:22.597407 <6>[ 0.591949] usbcore: registered new interface driver usbfs
10492 12:13:22.603936 <6>[ 0.597681] usbcore: registered new interface driver hub
10493 12:13:22.607418 <6>[ 0.603231] usbcore: registered new device driver usb
10494 12:13:22.614574 <6>[ 0.609334] pps_core: LinuxPPS API ver. 1 registered
10495 12:13:22.624280 <6>[ 0.614528] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10496 12:13:22.627518 <6>[ 0.623875] PTP clock support registered
10497 12:13:22.630988 <6>[ 0.628117] EDAC MC: Ver: 3.0.0
10498 12:13:22.638797 <6>[ 0.633251] FPGA manager framework
10499 12:13:22.641635 <6>[ 0.636931] Advanced Linux Sound Architecture Driver Initialized.
10500 12:13:22.645899 <6>[ 0.643708] vgaarb: loaded
10501 12:13:22.652022 <6>[ 0.646863] clocksource: Switched to clocksource arch_sys_counter
10502 12:13:22.658689 <5>[ 0.653306] VFS: Disk quotas dquot_6.6.0
10503 12:13:22.665216 <6>[ 0.657490] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10504 12:13:22.668400 <6>[ 0.664680] pnp: PnP ACPI: disabled
10505 12:13:22.676958 <6>[ 0.671412] NET: Registered PF_INET protocol family
10506 12:13:22.686109 <6>[ 0.677009] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10507 12:13:22.697585 <6>[ 0.689352] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10508 12:13:22.707426 <6>[ 0.698165] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10509 12:13:22.713967 <6>[ 0.706137] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10510 12:13:22.720738 <6>[ 0.714835] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10511 12:13:22.732966 <6>[ 0.724591] TCP: Hash tables configured (established 65536 bind 65536)
10512 12:13:22.739416 <6>[ 0.731458] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10513 12:13:22.746362 <6>[ 0.738660] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10514 12:13:22.752690 <6>[ 0.746362] NET: Registered PF_UNIX/PF_LOCAL protocol family
10515 12:13:22.759280 <6>[ 0.752506] RPC: Registered named UNIX socket transport module.
10516 12:13:22.762518 <6>[ 0.758660] RPC: Registered udp transport module.
10517 12:13:22.768973 <6>[ 0.763594] RPC: Registered tcp transport module.
10518 12:13:22.775667 <6>[ 0.768526] RPC: Registered tcp NFSv4.1 backchannel transport module.
10519 12:13:22.778814 <6>[ 0.775192] PCI: CLS 0 bytes, default 64
10520 12:13:22.781911 <6>[ 0.779506] Unpacking initramfs...
10521 12:13:22.799481 <6>[ 0.791443] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10522 12:13:22.809564 <6>[ 0.800120] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10523 12:13:22.812756 <6>[ 0.808973] kvm [1]: IPA Size Limit: 40 bits
10524 12:13:22.819068 <6>[ 0.813502] kvm [1]: GICv3: no GICV resource entry
10525 12:13:22.822412 <6>[ 0.818523] kvm [1]: disabling GICv2 emulation
10526 12:13:22.828770 <6>[ 0.823211] kvm [1]: GIC system register CPU interface enabled
10527 12:13:22.832367 <6>[ 0.829384] kvm [1]: vgic interrupt IRQ18
10528 12:13:22.839134 <6>[ 0.833743] kvm [1]: VHE mode initialized successfully
10529 12:13:22.845584 <5>[ 0.840271] Initialise system trusted keyrings
10530 12:13:22.852200 <6>[ 0.845068] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10531 12:13:22.859938 <6>[ 0.855127] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10532 12:13:22.866372 <5>[ 0.861544] NFS: Registering the id_resolver key type
10533 12:13:22.869491 <5>[ 0.866844] Key type id_resolver registered
10534 12:13:22.876454 <5>[ 0.871260] Key type id_legacy registered
10535 12:13:22.883178 <6>[ 0.875539] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10536 12:13:22.889719 <6>[ 0.882460] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10537 12:13:22.896033 <6>[ 0.890212] 9p: Installing v9fs 9p2000 file system support
10538 12:13:22.932013 <5>[ 0.927461] Key type asymmetric registered
10539 12:13:22.934999 <5>[ 0.931797] Asymmetric key parser 'x509' registered
10540 12:13:22.945113 <6>[ 0.936955] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10541 12:13:22.948468 <6>[ 0.944570] io scheduler mq-deadline registered
10542 12:13:22.951668 <6>[ 0.949347] io scheduler kyber registered
10543 12:13:22.970791 <6>[ 0.966356] EINJ: ACPI disabled.
10544 12:13:23.003029 <4>[ 0.991922] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10545 12:13:23.012672 <4>[ 1.002563] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10546 12:13:23.027944 <6>[ 1.023278] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10547 12:13:23.035533 <6>[ 1.031271] printk: console [ttyS0] disabled
10548 12:13:23.064191 <6>[ 1.055916] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10549 12:13:23.070834 <6>[ 1.065393] printk: console [ttyS0] enabled
10550 12:13:23.073819 <6>[ 1.065393] printk: console [ttyS0] enabled
10551 12:13:23.080397 <6>[ 1.074291] printk: bootconsole [mtk8250] disabled
10552 12:13:23.083640 <6>[ 1.074291] printk: bootconsole [mtk8250] disabled
10553 12:13:23.090475 <6>[ 1.085548] SuperH (H)SCI(F) driver initialized
10554 12:13:23.093744 <6>[ 1.090813] msm_serial: driver initialized
10555 12:13:23.107872 <6>[ 1.099794] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10556 12:13:23.117842 <6>[ 1.108340] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10557 12:13:23.124838 <6>[ 1.116882] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10558 12:13:23.134549 <6>[ 1.125511] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10559 12:13:23.144602 <6>[ 1.134222] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10560 12:13:23.150906 <6>[ 1.142945] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10561 12:13:23.161298 <6>[ 1.151488] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10562 12:13:23.167564 <6>[ 1.160298] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10563 12:13:23.177348 <6>[ 1.168843] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10564 12:13:23.189135 <6>[ 1.184474] loop: module loaded
10565 12:13:23.195621 <6>[ 1.190524] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10566 12:13:23.218767 <4>[ 1.214021] mtk-pmic-keys: Failed to locate of_node [id: -1]
10567 12:13:23.225852 <6>[ 1.220983] megasas: 07.719.03.00-rc1
10568 12:13:23.235504 <6>[ 1.230728] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10569 12:13:23.247225 <6>[ 1.242232] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10570 12:13:23.264104 <6>[ 1.258791] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10571 12:13:23.320137 <6>[ 1.308246] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10572 12:13:23.526474 <6>[ 1.522283] Freeing initrd memory: 17384K
10573 12:13:23.537125 <6>[ 1.532529] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10574 12:13:23.548199 <6>[ 1.543675] tun: Universal TUN/TAP device driver, 1.6
10575 12:13:23.551282 <6>[ 1.549746] thunder_xcv, ver 1.0
10576 12:13:23.554681 <6>[ 1.553252] thunder_bgx, ver 1.0
10577 12:13:23.558243 <6>[ 1.556747] nicpf, ver 1.0
10578 12:13:23.568460 <6>[ 1.560768] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10579 12:13:23.571948 <6>[ 1.568246] hns3: Copyright (c) 2017 Huawei Corporation.
10580 12:13:23.578626 <6>[ 1.573837] hclge is initializing
10581 12:13:23.581835 <6>[ 1.577420] e1000: Intel(R) PRO/1000 Network Driver
10582 12:13:23.588500 <6>[ 1.582549] e1000: Copyright (c) 1999-2006 Intel Corporation.
10583 12:13:23.591588 <6>[ 1.588562] e1000e: Intel(R) PRO/1000 Network Driver
10584 12:13:23.598570 <6>[ 1.593779] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10585 12:13:23.605346 <6>[ 1.599965] igb: Intel(R) Gigabit Ethernet Network Driver
10586 12:13:23.612120 <6>[ 1.605615] igb: Copyright (c) 2007-2014 Intel Corporation.
10587 12:13:23.618583 <6>[ 1.611451] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10588 12:13:23.625060 <6>[ 1.617970] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10589 12:13:23.628567 <6>[ 1.624451] sky2: driver version 1.30
10590 12:13:23.634931 <6>[ 1.629448] VFIO - User Level meta-driver version: 0.3
10591 12:13:23.642417 <6>[ 1.637666] usbcore: registered new interface driver usb-storage
10592 12:13:23.649171 <6>[ 1.644116] usbcore: registered new device driver onboard-usb-hub
10593 12:13:23.658053 <6>[ 1.653350] mt6397-rtc mt6359-rtc: registered as rtc0
10594 12:13:23.668292 <6>[ 1.658810] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-31T12:13:23 UTC (1706703203)
10595 12:13:23.671398 <6>[ 1.668416] i2c_dev: i2c /dev entries driver
10596 12:13:23.688116 <6>[ 1.680162] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10597 12:13:23.707986 <6>[ 1.703152] cpu cpu0: EM: created perf domain
10598 12:13:23.711645 <6>[ 1.708060] cpu cpu4: EM: created perf domain
10599 12:13:23.718579 <6>[ 1.713657] sdhci: Secure Digital Host Controller Interface driver
10600 12:13:23.725470 <6>[ 1.720090] sdhci: Copyright(c) Pierre Ossman
10601 12:13:23.731616 <6>[ 1.725043] Synopsys Designware Multimedia Card Interface Driver
10602 12:13:23.738352 <6>[ 1.731671] sdhci-pltfm: SDHCI platform and OF driver helper
10603 12:13:23.741754 <6>[ 1.731708] mmc0: CQHCI version 5.10
10604 12:13:23.748468 <6>[ 1.741865] ledtrig-cpu: registered to indicate activity on CPUs
10605 12:13:23.755293 <6>[ 1.748887] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10606 12:13:23.761554 <6>[ 1.755947] usbcore: registered new interface driver usbhid
10607 12:13:23.764986 <6>[ 1.761768] usbhid: USB HID core driver
10608 12:13:23.771456 <6>[ 1.765967] spi_master spi0: will run message pump with realtime priority
10609 12:13:23.815449 <6>[ 1.804026] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10610 12:13:23.831151 <6>[ 1.820018] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10611 12:13:23.838870 <6>[ 1.833622] mmc0: Command Queue Engine enabled
10612 12:13:23.845575 <6>[ 1.838397] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10613 12:13:23.852470 <6>[ 1.845319] cros-ec-spi spi0.0: Chrome EC device registered
10614 12:13:23.855494 <6>[ 1.845625] mmcblk0: mmc0:0001 DA4128 116 GiB
10615 12:13:23.867029 <6>[ 1.862091] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10616 12:13:23.874385 <6>[ 1.869447] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10617 12:13:23.884162 <6>[ 1.874114] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10618 12:13:23.887982 <6>[ 1.875408] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10619 12:13:23.894298 <6>[ 1.885226] NET: Registered PF_PACKET protocol family
10620 12:13:23.900593 <6>[ 1.889897] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10621 12:13:23.904191 <6>[ 1.894609] 9pnet: Installing 9P2000 support
10622 12:13:23.910992 <5>[ 1.905584] Key type dns_resolver registered
10623 12:13:23.914526 <6>[ 1.910531] registered taskstats version 1
10624 12:13:23.920834 <5>[ 1.914921] Loading compiled-in X.509 certificates
10625 12:13:23.948496 <4>[ 1.936928] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10626 12:13:23.958595 <4>[ 1.947672] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10627 12:13:23.965137 <3>[ 1.958205] debugfs: File 'uA_load' in directory '/' already present!
10628 12:13:23.971568 <3>[ 1.964954] debugfs: File 'min_uV' in directory '/' already present!
10629 12:13:23.978380 <3>[ 1.971568] debugfs: File 'max_uV' in directory '/' already present!
10630 12:13:23.984929 <3>[ 1.978180] debugfs: File 'constraint_flags' in directory '/' already present!
10631 12:13:23.996251 <3>[ 1.987986] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10632 12:13:24.005090 <6>[ 2.000448] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10633 12:13:24.012266 <6>[ 2.007447] xhci-mtk 11200000.usb: xHCI Host Controller
10634 12:13:24.018906 <6>[ 2.012954] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10635 12:13:24.029106 <6>[ 2.020796] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10636 12:13:24.035694 <6>[ 2.030215] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10637 12:13:24.042322 <6>[ 2.036289] xhci-mtk 11200000.usb: xHCI Host Controller
10638 12:13:24.048688 <6>[ 2.041766] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10639 12:13:24.055424 <6>[ 2.049414] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10640 12:13:24.061946 <6>[ 2.057061] hub 1-0:1.0: USB hub found
10641 12:13:24.065387 <6>[ 2.061071] hub 1-0:1.0: 1 port detected
10642 12:13:24.072227 <6>[ 2.065342] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10643 12:13:24.078753 <6>[ 2.073866] hub 2-0:1.0: USB hub found
10644 12:13:24.081826 <6>[ 2.077871] hub 2-0:1.0: 1 port detected
10645 12:13:24.089389 <6>[ 2.084420] mtk-msdc 11f70000.mmc: Got CD GPIO
10646 12:13:24.103393 <6>[ 2.095288] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10647 12:13:24.110205 <6>[ 2.103311] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10648 12:13:24.120193 <4>[ 2.111206] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10649 12:13:24.129997 <6>[ 2.120740] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10650 12:13:24.136620 <6>[ 2.128818] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10651 12:13:24.143218 <6>[ 2.136846] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10652 12:13:24.153451 <6>[ 2.144761] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10653 12:13:24.159926 <6>[ 2.152583] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10654 12:13:24.170046 <6>[ 2.160399] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10655 12:13:24.179888 <6>[ 2.170825] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10656 12:13:24.186164 <6>[ 2.179184] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10657 12:13:24.196357 <6>[ 2.187530] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10658 12:13:24.203176 <6>[ 2.195870] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10659 12:13:24.212730 <6>[ 2.204208] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10660 12:13:24.219479 <6>[ 2.212546] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10661 12:13:24.229690 <6>[ 2.220885] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10662 12:13:24.236304 <6>[ 2.229224] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10663 12:13:24.245975 <6>[ 2.237564] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10664 12:13:24.252778 <6>[ 2.245903] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10665 12:13:24.262485 <6>[ 2.254250] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10666 12:13:24.268914 <6>[ 2.262590] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10667 12:13:24.278782 <6>[ 2.270944] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10668 12:13:24.285376 <6>[ 2.279284] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10669 12:13:24.295475 <6>[ 2.287622] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10670 12:13:24.301995 <6>[ 2.296382] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10671 12:13:24.309051 <6>[ 2.303513] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10672 12:13:24.315441 <6>[ 2.310265] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10673 12:13:24.321814 <6>[ 2.317025] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10674 12:13:24.328514 <6>[ 2.323953] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10675 12:13:24.338713 <6>[ 2.330793] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10676 12:13:24.348741 <6>[ 2.339943] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10677 12:13:24.358738 <6>[ 2.349067] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10678 12:13:24.368654 <6>[ 2.358360] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10679 12:13:24.378293 <6>[ 2.367826] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10680 12:13:24.385126 <6>[ 2.377293] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10681 12:13:24.394863 <6>[ 2.386413] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10682 12:13:24.404815 <6>[ 2.395877] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10683 12:13:24.414929 <6>[ 2.404995] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10684 12:13:24.424761 <6>[ 2.414290] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10685 12:13:24.434906 <6>[ 2.424450] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10686 12:13:24.444410 <6>[ 2.435923] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10687 12:13:24.451126 <6>[ 2.445670] Trying to probe devices needed for running init ...
10688 12:13:24.471593 <6>[ 2.463474] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10689 12:13:24.500804 <6>[ 2.495921] hub 2-1:1.0: USB hub found
10690 12:13:24.503899 <6>[ 2.500505] hub 2-1:1.0: 3 ports detected
10691 12:13:24.514172 <6>[ 2.509411] hub 2-1:1.0: USB hub found
10692 12:13:24.517632 <6>[ 2.513824] hub 2-1:1.0: 3 ports detected
10693 12:13:24.622914 <6>[ 2.615051] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10694 12:13:24.777452 <6>[ 2.772857] hub 1-1:1.0: USB hub found
10695 12:13:24.780771 <6>[ 2.777278] hub 1-1:1.0: 4 ports detected
10696 12:13:24.789769 <6>[ 2.784987] hub 1-1:1.0: USB hub found
10697 12:13:24.793047 <6>[ 2.789513] hub 1-1:1.0: 4 ports detected
10698 12:13:24.859479 <6>[ 2.851190] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10699 12:13:25.115094 <6>[ 3.107178] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10700 12:13:25.247910 <6>[ 3.243126] hub 1-1.4:1.0: USB hub found
10701 12:13:25.251073 <6>[ 3.247802] hub 1-1.4:1.0: 2 ports detected
10702 12:13:25.260491 <6>[ 3.255696] hub 1-1.4:1.0: USB hub found
10703 12:13:25.263580 <6>[ 3.260267] hub 1-1.4:1.0: 2 ports detected
10704 12:13:25.559227 <6>[ 3.551161] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10705 12:13:25.750736 <6>[ 3.743158] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10706 12:13:36.735955 <6>[ 14.736147] ALSA device list:
10707 12:13:36.742291 <6>[ 14.739443] No soundcards found.
10708 12:13:36.750592 <6>[ 14.747415] Freeing unused kernel memory: 8448K
10709 12:13:36.753795 <6>[ 14.752431] Run /init as init process
10710 12:13:36.764455 Loading, please wait...
10711 12:13:36.785087 Starting version 247.3-7+deb11u2
10712 12:13:36.998323 <6>[ 14.991885] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10713 12:13:37.015519 <6>[ 15.012576] remoteproc remoteproc0: scp is available
10714 12:13:37.023338 <6>[ 15.020531] remoteproc remoteproc0: powering up scp
10715 12:13:37.033382 <6>[ 15.025731] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10716 12:13:37.036953 <6>[ 15.034217] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10717 12:13:37.046700 <3>[ 15.035066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 12:13:37.053276 <6>[ 15.037772] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10719 12:13:37.063167 <6>[ 15.037810] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10720 12:13:37.069938 <6>[ 15.037821] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10721 12:13:37.079680 <4>[ 15.038517] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10722 12:13:37.086443 <4>[ 15.068727] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10723 12:13:37.089444 <6>[ 15.082849] mc: Linux media interface: v0.10
10724 12:13:37.099547 <6>[ 15.086487] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10725 12:13:37.106192 <3>[ 15.088121] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 12:13:37.116048 <3>[ 15.108722] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10727 12:13:37.122882 <4>[ 15.109211] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10728 12:13:37.129179 <4>[ 15.109211] Fallback method does not support PEC.
10729 12:13:37.135990 <6>[ 15.109654] usbcore: registered new device driver r8152-cfgselector
10730 12:13:37.138922 <6>[ 15.109667] videodev: Linux video capture interface: v2.00
10731 12:13:37.149521 <3>[ 15.117011] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 12:13:37.156266 <3>[ 15.148214] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10733 12:13:37.166219 <3>[ 15.150865] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10734 12:13:37.172963 <3>[ 15.150869] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10735 12:13:37.182725 <3>[ 15.150875] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10736 12:13:37.190547 <6>[ 15.152160] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10737 12:13:37.193744 <6>[ 15.152165] pci_bus 0000:00: root bus resource [bus 00-ff]
10738 12:13:37.200131 <6>[ 15.152169] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10739 12:13:37.210127 <6>[ 15.152172] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10740 12:13:37.216727 <6>[ 15.152199] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10741 12:13:37.226732 <6>[ 15.152212] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10742 12:13:37.230087 <6>[ 15.152278] pci 0000:00:00.0: supports D1 D2
10743 12:13:37.236642 <6>[ 15.152280] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10744 12:13:37.246517 <6>[ 15.153270] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10745 12:13:37.249737 <6>[ 15.153341] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10746 12:13:37.259931 <6>[ 15.153365] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10747 12:13:37.266536 <6>[ 15.153380] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10748 12:13:37.272898 <6>[ 15.153395] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10749 12:13:37.279522 <6>[ 15.153497] pci 0000:01:00.0: supports D1 D2
10750 12:13:37.286269 <6>[ 15.153498] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10751 12:13:37.292856 <6>[ 15.165441] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10752 12:13:37.299430 <6>[ 15.165481] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10753 12:13:37.306010 <6>[ 15.165488] remoteproc remoteproc0: remote processor scp is now up
10754 12:13:37.312701 <6>[ 15.167022] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10755 12:13:37.322478 <6>[ 15.167041] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10756 12:13:37.329402 <6>[ 15.167044] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10757 12:13:37.339087 <6>[ 15.167053] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10758 12:13:37.345800 <6>[ 15.167065] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10759 12:13:37.355684 <6>[ 15.167078] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10760 12:13:37.358948 <6>[ 15.167090] pci 0000:00:00.0: PCI bridge to [bus 01]
10761 12:13:37.369090 <6>[ 15.167095] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10762 12:13:37.372235 <6>[ 15.167204] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10763 12:13:37.378916 <6>[ 15.167676] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10764 12:13:37.388700 <3>[ 15.167726] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10765 12:13:37.395227 <3>[ 15.167763] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10766 12:13:37.402062 <6>[ 15.168068] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10767 12:13:37.408498 <6>[ 15.185298] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10768 12:13:37.418530 <3>[ 15.190799] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10769 12:13:37.428456 <3>[ 15.191937] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10770 12:13:37.435291 <6>[ 15.198488] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10771 12:13:37.445003 <6>[ 15.199242] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10772 12:13:37.455010 <6>[ 15.199287] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10773 12:13:37.461697 <6>[ 15.199579] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10774 12:13:37.471320 <6>[ 15.203029] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10775 12:13:37.481307 <3>[ 15.203637] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 12:13:37.488021 <3>[ 15.203640] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10777 12:13:37.497917 <3>[ 15.203678] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 12:13:37.504527 <5>[ 15.222102] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10779 12:13:37.514421 <4>[ 15.223333] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10780 12:13:37.520919 <4>[ 15.223343] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10781 12:13:37.530891 <3>[ 15.227290] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10782 12:13:37.537414 <3>[ 15.227293] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10783 12:13:37.544097 <3>[ 15.227297] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10784 12:13:37.553984 <5>[ 15.246555] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10785 12:13:37.560555 <3>[ 15.247109] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10786 12:13:37.564121 <6>[ 15.247667] Bluetooth: Core ver 2.22
10787 12:13:37.570612 <6>[ 15.247736] NET: Registered PF_BLUETOOTH protocol family
10788 12:13:37.576968 <6>[ 15.247739] Bluetooth: HCI device and connection manager initialized
10789 12:13:37.580268 <6>[ 15.247773] Bluetooth: HCI socket layer initialized
10790 12:13:37.586853 <6>[ 15.247780] Bluetooth: L2CAP socket layer initialized
10791 12:13:37.593505 <6>[ 15.247790] Bluetooth: SCO socket layer initialized
10792 12:13:37.600074 <5>[ 15.253979] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10793 12:13:37.606955 <6>[ 15.254822] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10794 12:13:37.619910 <6>[ 15.256347] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10795 12:13:37.626716 <6>[ 15.256492] usbcore: registered new interface driver uvcvideo
10796 12:13:37.633258 <3>[ 15.260816] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10797 12:13:37.640064 <6>[ 15.277017] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10798 12:13:37.643386 <6>[ 15.278968] r8152 2-1.3:1.0 eth0: v1.12.13
10799 12:13:37.649713 <6>[ 15.279039] usbcore: registered new interface driver r8152
10800 12:13:37.659856 <4>[ 15.280732] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10801 12:13:37.666467 <6>[ 15.289068] usbcore: registered new interface driver btusb
10802 12:13:37.676336 <4>[ 15.289641] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10803 12:13:37.682731 <3>[ 15.289651] Bluetooth: hci0: Failed to load firmware file (-2)
10804 12:13:37.686142 <3>[ 15.289655] Bluetooth: hci0: Failed to set up firmware (-2)
10805 12:13:37.699280 <4>[ 15.289659] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10806 12:13:37.702709 <6>[ 15.294333] cfg80211: failed to load regulatory.db
10807 12:13:37.709053 <6>[ 15.294915] usbcore: registered new interface driver cdc_ether
10808 12:13:37.715744 <6>[ 15.359923] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10809 12:13:37.722148 <6>[ 15.376102] usbcore: registered new interface driver r8153_ecm
10810 12:13:37.728914 <6>[ 15.382182] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10811 12:13:37.735772 <6>[ 15.422285] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10812 12:13:37.738893 <6>[ 15.449678] mt7921e 0000:01:00.0: ASIC revision: 79610010
10813 12:13:37.841094 <6>[ 15.835106] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10814 12:13:37.844192 <6>[ 15.835106]
10815 12:13:37.860250 Begin: Loading essential drivers ... done.
10816 12:13:37.863902 Begin: Running /scripts/init-premount ... done.
10817 12:13:37.870510 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10818 12:13:37.880399 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10819 12:13:37.883458 Device /sys/class/net/enx0024323078ff found
10820 12:13:37.883540 done.
10821 12:13:37.940947 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10822 12:13:38.109451 <6>[ 16.103238] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10823 12:13:38.862885 <6>[ 16.860041] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10824 12:13:38.958939 <6>[ 16.956481] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10825 12:13:39.161389 IP-Config: no response after 2 secs - giving up
10826 12:13:39.193934 IP-Config: wlp1s0 hardware address d8:f3:bc:78:28:07 mtu 1500 DHCP
10827 12:13:39.913862 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10828 12:13:39.920857 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10829 12:13:39.927524 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10830 12:13:39.934193 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10831 12:13:39.940522 host : mt8192-asurada-spherion-r0-cbg-8
10832 12:13:39.947300 domain : lava-rack
10833 12:13:39.950700 rootserver: 192.168.201.1 rootpath:
10834 12:13:39.953766 filename :
10835 12:13:40.075525 done.
10836 12:13:40.083077 Begin: Running /scripts/nfs-bottom ... done.
10837 12:13:40.101244 Begin: Running /scripts/init-bottom ... done.
10838 12:13:41.315451 <6>[ 19.313012] NET: Registered PF_INET6 protocol family
10839 12:13:41.323128 <6>[ 19.320687] Segment Routing with IPv6
10840 12:13:41.326515 <6>[ 19.324653] In-situ OAM (IOAM) with IPv6
10841 12:13:41.459493 <30>[ 19.440362] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10842 12:13:41.467232 <30>[ 19.464720] systemd[1]: Detected architecture arm64.
10843 12:13:41.487318
10844 12:13:41.490647 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10845 12:13:41.490731
10846 12:13:41.507901 <30>[ 19.505482] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10847 12:13:42.402573 <30>[ 20.396874] systemd[1]: Queued start job for default target Graphical Interface.
10848 12:13:42.443572 <30>[ 20.441501] systemd[1]: Created slice system-getty.slice.
10849 12:13:42.450306 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10850 12:13:42.466857 <30>[ 20.464541] systemd[1]: Created slice system-modprobe.slice.
10851 12:13:42.473456 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10852 12:13:42.490563 <30>[ 20.488374] systemd[1]: Created slice system-serial\x2dgetty.slice.
10853 12:13:42.500530 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10854 12:13:42.514814 <30>[ 20.512263] systemd[1]: Created slice User and Session Slice.
10855 12:13:42.521276 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10856 12:13:42.541041 <30>[ 20.535443] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10857 12:13:42.550813 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10858 12:13:42.569074 <30>[ 20.563352] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10859 12:13:42.575539 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10860 12:13:42.596072 <30>[ 20.587242] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10861 12:13:42.602807 <30>[ 20.599405] systemd[1]: Reached target Local Encrypted Volumes.
10862 12:13:42.609035 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10863 12:13:42.626136 <30>[ 20.623739] systemd[1]: Reached target Paths.
10864 12:13:42.632469 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10865 12:13:42.645410 <30>[ 20.643158] systemd[1]: Reached target Remote File Systems.
10866 12:13:42.651888 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10867 12:13:42.669795 <30>[ 20.667543] systemd[1]: Reached target Slices.
10868 12:13:42.676527 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10869 12:13:42.689355 <30>[ 20.687182] systemd[1]: Reached target Swap.
10870 12:13:42.692967 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10871 12:13:42.713361 <30>[ 20.707660] systemd[1]: Listening on initctl Compatibility Named Pipe.
10872 12:13:42.720053 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10873 12:13:42.726341 <30>[ 20.723855] systemd[1]: Listening on Journal Audit Socket.
10874 12:13:42.732873 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10875 12:13:42.750686 <30>[ 20.748475] systemd[1]: Listening on Journal Socket (/dev/log).
10876 12:13:42.757179 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10877 12:13:42.774148 <30>[ 20.771725] systemd[1]: Listening on Journal Socket.
10878 12:13:42.780570 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10879 12:13:42.798154 <30>[ 20.792642] systemd[1]: Listening on Network Service Netlink Socket.
10880 12:13:42.804543 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10881 12:13:42.820177 <30>[ 20.818057] systemd[1]: Listening on udev Control Socket.
10882 12:13:42.826578 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10883 12:13:42.841655 <30>[ 20.839589] systemd[1]: Listening on udev Kernel Socket.
10884 12:13:42.848368 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10885 12:13:42.905437 <30>[ 20.903293] systemd[1]: Mounting Huge Pages File System...
10886 12:13:42.911901 Mounting [0;1;39mHuge Pages File System[0m...
10887 12:13:42.929422 <30>[ 20.927412] systemd[1]: Mounting POSIX Message Queue File System...
10888 12:13:42.936390 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10889 12:13:42.958079 <30>[ 20.955755] systemd[1]: Mounting Kernel Debug File System...
10890 12:13:42.964287 Mounting [0;1;39mKernel Debug File System[0m...
10891 12:13:42.981073 <30>[ 20.975814] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10892 12:13:42.994112 <30>[ 20.988643] systemd[1]: Starting Create list of static device nodes for the current kernel...
10893 12:13:43.000809 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10894 12:13:43.021793 <30>[ 21.019638] systemd[1]: Starting Load Kernel Module configfs...
10895 12:13:43.028238 Starting [0;1;39mLoad Kernel Module configfs[0m...
10896 12:13:43.044415 <30>[ 21.042149] systemd[1]: Starting Load Kernel Module drm...
10897 12:13:43.050837 Starting [0;1;39mLoad Kernel Module drm[0m...
10898 12:13:43.069957 <30>[ 21.067661] systemd[1]: Starting Load Kernel Module fuse...
10899 12:13:43.076532 Starting [0;1;39mLoad Kernel Module fuse[0m...
10900 12:13:43.112584 <30>[ 21.107216] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10901 12:13:43.119634 <6>[ 21.117726] fuse: init (API version 7.37)
10902 12:13:43.153788 <30>[ 21.151898] systemd[1]: Starting Journal Service...
10903 12:13:43.160489 Starting [0;1;39mJournal Service[0m...
10904 12:13:43.183962 <30>[ 21.182002] systemd[1]: Starting Load Kernel Modules...
10905 12:13:43.190771 Starting [0;1;39mLoad Kernel Modules[0m...
10906 12:13:43.217761 <30>[ 21.212174] systemd[1]: Starting Remount Root and Kernel File Systems...
10907 12:13:43.224205 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10908 12:13:43.242568 <30>[ 21.240418] systemd[1]: Starting Coldplug All udev Devices...
10909 12:13:43.249011 Starting [0;1;39mColdplug All udev Devices[0m...
10910 12:13:43.274518 <30>[ 21.272401] systemd[1]: Mounted Huge Pages File System.
10911 12:13:43.281596 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10912 12:13:43.292829 <3>[ 21.287345] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 12:13:43.301718 <30>[ 21.299551] systemd[1]: Mounted POSIX Message Queue File System.
10914 12:13:43.308232 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10915 12:13:43.333175 <3>[ 21.327633] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 12:13:43.340045 <30>[ 21.327641] systemd[1]: Mounted Kernel Debug File System.
10917 12:13:43.346428 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10918 12:13:43.373276 <3>[ 21.367625] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 12:13:43.383006 <30>[ 21.370898] systemd[1]: Finished Create list of static device nodes for the current kernel.
10920 12:13:43.389590 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10921 12:13:43.414248 <3>[ 21.408990] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 12:13:43.421048 <30>[ 21.409183] systemd[1]: modprobe@configfs.service: Succeeded.
10923 12:13:43.427547 <30>[ 21.425391] systemd[1]: Finished Load Kernel Module configfs.
10924 12:13:43.434205 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10925 12:13:43.451227 <30>[ 21.448573] systemd[1]: modprobe@drm.service: Succeeded.
10926 12:13:43.461173 <3>[ 21.450906] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 12:13:43.464393 <30>[ 21.455149] systemd[1]: Finished Load Kernel Module drm.
10928 12:13:43.471082 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10929 12:13:43.490629 <3>[ 21.485333] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 12:13:43.498316 <30>[ 21.496206] systemd[1]: modprobe@fuse.service: Succeeded.
10931 12:13:43.505609 <30>[ 21.503187] systemd[1]: Finished Load Kernel Module fuse.
10932 12:13:43.512709 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10933 12:13:43.522795 <3>[ 21.516246] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 12:13:43.529421 <30>[ 21.526832] systemd[1]: Finished Load Kernel Modules.
10935 12:13:43.535861 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10936 12:13:43.553208 <30>[ 21.547683] systemd[1]: Finished Remount Root and Kernel File Systems.
10937 12:13:43.559649 <3>[ 21.547936] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 12:13:43.566391 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10939 12:13:43.591045 <3>[ 21.585610] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10940 12:13:43.609817 <30>[ 21.607179] systemd[1]: Mounting FUSE Control File System...
10941 12:13:43.623114 Mounting [0;1;39mFUSE <3>[ 21.615949] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 12:13:43.623232 Control File System[0m...
10943 12:13:43.640729 <30>[ 21.638480] systemd[1]: Mounting Kernel Configuration File System...
10944 12:13:43.647886 Mounting [0;1;39mKernel Configuration File System[0m...
10945 12:13:43.674209 <30>[ 21.668258] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10946 12:13:43.683938 <30>[ 21.677353] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10947 12:13:43.714382 <30>[ 21.712262] systemd[1]: Starting Load/Save Random Seed...
10948 12:13:43.720724 Starting [0;1;39mLoad/Save Random Seed[0m...
10949 12:13:43.738253 <30>[ 21.736110] systemd[1]: Starting Apply Kernel Variables...
10950 12:13:43.744833 Starting [0;1;39mApply Kernel Variables[0m...
10951 12:13:43.764807 <4>[ 21.752958] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10952 12:13:43.774760 <3>[ 21.768642] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10953 12:13:43.778346 <30>[ 21.772132] systemd[1]: Starting Create System Users...
10954 12:13:43.784514 Starting [0;1;39mCreate System Users[0m...
10955 12:13:43.803644 <30>[ 21.801519] systemd[1]: Started Journal Service.
10956 12:13:43.810169 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10957 12:13:43.832537 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10958 12:13:43.845391 See 'systemctl status systemd-udev-trigger.service' for details.
10959 12:13:43.865694 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10960 12:13:43.881390 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10961 12:13:43.899023 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10962 12:13:43.915152 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10963 12:13:43.931263 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10964 12:13:43.974102 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10965 12:13:43.991845 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10966 12:13:44.029896 <46>[ 22.024466] systemd-journald[301]: Received client request to flush runtime journal.
10967 12:13:44.262895 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10968 12:13:44.277789 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10969 12:13:44.293232 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10970 12:13:44.353637 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10971 12:13:45.434931 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10972 12:13:45.473733 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10973 12:13:45.537416 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10974 12:13:45.602322 Starting [0;1;39mNetwork Service[0m...
10975 12:13:45.859040 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10976 12:13:45.881482 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10977 12:13:45.938747 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10978 12:13:46.174533 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10979 12:13:46.217832 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10980 12:13:46.266453 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10981 12:13:46.315519 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10982 12:13:46.350149 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10983 12:13:46.371350 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10984 12:13:46.385251 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10985 12:13:46.433971 Starting [0;1;39mNetwork Name Resolution[0m...
10986 12:13:46.461821 Starting [0;1;39mNetwork Time Synchronization[0m...
10987 12:13:46.480826 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10988 12:13:46.537759 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10989 12:13:46.691001 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10990 12:13:46.709968 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10991 12:13:46.728701 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10992 12:13:46.749586 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10993 12:13:46.765285 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10994 12:13:46.867289 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10995 12:13:46.911674 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10996 12:13:46.939399 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10997 12:13:46.963335 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10998 12:13:46.976822 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10999 12:13:46.998332 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11000 12:13:47.013039 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11001 12:13:47.028890 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11002 12:13:47.077961 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11003 12:13:47.189002 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11004 12:13:47.244227 Starting [0;1;39mUser Login Management[0m...
11005 12:13:47.260922 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11006 12:13:47.269939 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11007 12:13:47.286066 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11008 12:13:47.338817 Starting [0;1;39mPermit User Sessions[0m...
11009 12:13:47.433295 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11010 12:13:47.468540 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11011 12:13:47.491045 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11012 12:13:47.498221 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11013 12:13:47.531230 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11014 12:13:47.553126 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11015 12:13:47.576017 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11016 12:13:47.594293 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11017 12:13:47.641732 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11018 12:13:47.691637 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11019 12:13:47.821571
11020 12:13:47.822178
11021 12:13:47.824720 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11022 12:13:47.825318
11023 12:13:47.827843 debian-bullseye-arm64 login: root (automatic login)
11024 12:13:47.828379
11025 12:13:47.828991
11026 12:13:48.231874 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024 aarch64
11027 12:13:48.232477
11028 12:13:48.238497 The programs included with the Debian GNU/Linux system are free software;
11029 12:13:48.245121 the exact distribution terms for each program are described in the
11030 12:13:48.248038 individual files in /usr/share/doc/*/copyright.
11031 12:13:48.248675
11032 12:13:48.254925 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11033 12:13:48.258229 permitted by applicable law.
11034 12:13:49.112725 Matched prompt #10: / #
11036 12:13:49.113114 Setting prompt string to ['/ #']
11037 12:13:49.113238 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11039 12:13:49.113566 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11040 12:13:49.113660 start: 2.2.6 expect-shell-connection (timeout 00:03:12) [common]
11041 12:13:49.113730 Setting prompt string to ['/ #']
11042 12:13:49.113793 Forcing a shell prompt, looking for ['/ #']
11044 12:13:49.163995 / #
11045 12:13:49.164126 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11046 12:13:49.164244 Waiting using forced prompt support (timeout 00:02:30)
11047 12:13:49.168693
11048 12:13:49.168993 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11049 12:13:49.169111 start: 2.2.7 export-device-env (timeout 00:03:12) [common]
11051 12:13:49.269463 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12669498/extract-nfsrootfs-y_nv2isg'
11052 12:13:49.274939 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12669498/extract-nfsrootfs-y_nv2isg'
11054 12:13:49.375439 / # export NFS_SERVER_IP='192.168.201.1'
11055 12:13:49.380456 export NFS_SERVER_IP='192.168.201.1'
11056 12:13:49.380743 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11057 12:13:49.380848 end: 2.2 depthcharge-retry (duration 00:01:48) [common]
11058 12:13:49.380941 end: 2 depthcharge-action (duration 00:01:48) [common]
11059 12:13:49.381031 start: 3 lava-test-retry (timeout 00:07:25) [common]
11060 12:13:49.381114 start: 3.1 lava-test-shell (timeout 00:07:25) [common]
11061 12:13:49.381189 Using namespace: common
11063 12:13:49.481539 / # #
11064 12:13:49.481678 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11065 12:13:49.486492 #
11066 12:13:49.486763 Using /lava-12669498
11068 12:13:49.587097 / # export SHELL=/bin/bash
11069 12:13:49.592037 export SHELL=/bin/bash
11071 12:13:49.692618 / # . /lava-12669498/environment
11072 12:13:49.697710 . /lava-12669498/environment
11074 12:13:49.803720 / # /lava-12669498/bin/lava-test-runner /lava-12669498/0
11075 12:13:49.803840 Test shell timeout: 10s (minimum of the action and connection timeout)
11076 12:13:49.808883 /lava-12669498/bin/lava-test-runner /lava-12669498/0
11077 12:13:50.097190 + export TESTRUN_ID=0_timesync-off
11078 12:13:50.100476 + TESTRUN_ID=0_timesync-off
11079 12:13:50.103799 + cd /lava-12669498/0/tests/0_timesync-off
11080 12:13:50.106830 ++ cat uuid
11081 12:13:50.110758 + UUID=12669498_1.6.2.3.1
11082 12:13:50.110846 + set +x
11083 12:13:50.117255 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12669498_1.6.2.3.1>
11084 12:13:50.117531 Received signal: <STARTRUN> 0_timesync-off 12669498_1.6.2.3.1
11085 12:13:50.117611 Starting test lava.0_timesync-off (12669498_1.6.2.3.1)
11086 12:13:50.117698 Skipping test definition patterns.
11087 12:13:50.120630 + systemctl stop systemd-timesyncd
11088 12:13:50.184632 + set +x
11089 12:13:50.187627 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12669498_1.6.2.3.1>
11090 12:13:50.187887 Received signal: <ENDRUN> 0_timesync-off 12669498_1.6.2.3.1
11091 12:13:50.187972 Ending use of test pattern.
11092 12:13:50.188036 Ending test lava.0_timesync-off (12669498_1.6.2.3.1), duration 0.07
11094 12:13:50.265687 + export TESTRUN_ID=1_kselftest-tpm2
11095 12:13:50.269068 + TESTRUN_ID=1_kselftest-tpm2
11096 12:13:50.272411 + cd /lava-12669498/0/tests/1_kselftest-tpm2
11097 12:13:50.275430 ++ cat uuid
11098 12:13:50.279330 + UUID=12669498_1.6.2.3.5
11099 12:13:50.279413 + set +x
11100 12:13:50.285754 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 12669498_1.6.2.3.5>
11101 12:13:50.286035 Received signal: <STARTRUN> 1_kselftest-tpm2 12669498_1.6.2.3.5
11102 12:13:50.286111 Starting test lava.1_kselftest-tpm2 (12669498_1.6.2.3.5)
11103 12:13:50.286192 Skipping test definition patterns.
11104 12:13:50.289001 + cd ./automated/linux/kselftest/
11105 12:13:50.315625 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11106 12:13:50.352558 INFO: install_deps skipped
11107 12:13:50.474130 --2024-01-31 12:13:50-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11108 12:13:50.486428 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11109 12:13:50.618826 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11110 12:13:50.753086 HTTP request sent, awaiting response... 200 OK
11111 12:13:50.756374 Length: 2966336 (2.8M) [application/octet-stream]
11112 12:13:50.759420 Saving to: 'kselftest.tar.xz'
11113 12:13:50.759547
11114 12:13:50.759616
11115 12:13:51.016800 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11116 12:13:51.283017 kselftest.tar.xz 1%[ ] 47.81K 180KB/s
11117 12:13:51.571782 kselftest.tar.xz 7%[> ] 217.50K 407KB/s
11118 12:13:51.769510 kselftest.tar.xz 20%[===> ] 593.15K 718KB/s
11119 12:13:51.968502 kselftest.tar.xz 46%[========> ] 1.30M 1.27MB/s
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11122 12:13:52.117721
11123 12:13:52.374833 2024-01-31 12:13:52 (2.06 MB/s) - 'kselftest.tar.xz' saved [2966336/2966336]
11124 12:13:52.374972
11125 12:13:58.512602 skiplist:
11126 12:13:58.515925 ========================================
11127 12:13:58.519013 ========================================
11128 12:13:58.565536 tpm2:test_smoke.sh
11129 12:13:58.568433 tpm2:test_space.sh
11130 12:13:58.583811 ============== Tests to run ===============
11131 12:13:58.583897 tpm2:test_smoke.sh
11132 12:13:58.587232 tpm2:test_space.sh
11133 12:13:58.590528 ===========End Tests to run ===============
11134 12:13:58.593831 shardfile-tpm2 pass
11135 12:13:58.707067 <12>[ 36.706618] kselftest: Running tests in tpm2
11136 12:13:58.718160 TAP version 13
11137 12:13:58.731089 1..2
11138 12:13:58.764936 # selftests: tpm2: test_smoke.sh
11139 12:14:00.239283 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
11140 12:14:00.242374 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
11141 12:14:00.248930 # Exception ignored in: <function Client.__del__ at 0xffff99ef7d30>
11142 12:14:00.252631 # Traceback (most recent call last):
11143 12:14:00.262193 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11144 12:14:00.265526 # if self.tpm:
11145 12:14:00.269056 # AttributeError: 'Client' object has no attribute 'tpm'
11146 12:14:00.275457 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
11147 12:14:00.278911 # Exception ignored in: <function Client.__del__ at 0xffff99ef7d30>
11148 12:14:00.282285 # Traceback (most recent call last):
11149 12:14:00.292218 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11150 12:14:00.295576 # if self.tpm:
11151 12:14:00.298663 # AttributeError: 'Client' object has no attribute 'tpm'
11152 12:14:00.305425 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
11153 12:14:00.312126 # Exception ignored in: <function Client.__del__ at 0xffff99ef7d30>
11154 12:14:00.315582 # Traceback (most recent call last):
11155 12:14:00.325184 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11156 12:14:00.325293 # if self.tpm:
11157 12:14:00.331965 # AttributeError: 'Client' object has no attribute 'tpm'
11158 12:14:00.335451 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
11159 12:14:00.341957 # Exception ignored in: <function Client.__del__ at 0xffff99ef7d30>
11160 12:14:00.345379 # Traceback (most recent call last):
11161 12:14:00.355253 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11162 12:14:00.358808 # if self.tpm:
11163 12:14:00.362237 # AttributeError: 'Client' object has no attribute 'tpm'
11164 12:14:00.368791 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
11165 12:14:00.371741 # Exception ignored in: <function Client.__del__ at 0xffff99ef7d30>
11166 12:14:00.375120 # Traceback (most recent call last):
11167 12:14:00.385134 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11168 12:14:00.388509 # if self.tpm:
11169 12:14:00.391813 # AttributeError: 'Client' object has no attribute 'tpm'
11170 12:14:00.398767 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
11171 12:14:00.405019 # Exception ignored in: <function Client.__del__ at 0xffff99ef7d30>
11172 12:14:00.408293 # Traceback (most recent call last):
11173 12:14:00.418300 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11174 12:14:00.418392 # if self.tpm:
11175 12:14:00.424848 # AttributeError: 'Client' object has no attribute 'tpm'
11176 12:14:00.428090 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
11177 12:14:00.434773 # Exception ignored in: <function Client.__del__ at 0xffff99ef7d30>
11178 12:14:00.437722 # Traceback (most recent call last):
11179 12:14:00.447787 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11180 12:14:00.451256 # if self.tpm:
11181 12:14:00.454260 # AttributeError: 'Client' object has no attribute 'tpm'
11182 12:14:00.461114 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
11183 12:14:00.467409 # Exception ignored in: <function Client.__del__ at 0xffff99ef7d30>
11184 12:14:00.470787 # Traceback (most recent call last):
11185 12:14:00.480687 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11186 12:14:00.480770 # if self.tpm:
11187 12:14:00.487685 # AttributeError: 'Client' object has no attribute 'tpm'
11188 12:14:00.487767 #
11189 12:14:00.494232 # ======================================================================
11190 12:14:00.497657 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
11191 12:14:00.504200 # ----------------------------------------------------------------------
11192 12:14:00.507534 # Traceback (most recent call last):
11193 12:14:00.517531 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11194 12:14:00.522057 # self.root_key = self.client.create_root_key()
11195 12:14:00.532920 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11196 12:14:00.540012 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11197 12:14:00.549940 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11198 12:14:00.553128 # raise ProtocolError(cc, rc)
11199 12:14:00.556666 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11200 12:14:00.559749 #
11201 12:14:00.566310 # ======================================================================
11202 12:14:00.569670 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
11203 12:14:00.576464 # ----------------------------------------------------------------------
11204 12:14:00.579510 # Traceback (most recent call last):
11205 12:14:00.589550 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11206 12:14:00.592847 # self.client = tpm2.Client()
11207 12:14:00.603087 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11208 12:14:00.606120 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11209 12:14:00.612918 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11210 12:14:00.613000 #
11211 12:14:00.619581 # ======================================================================
11212 12:14:00.622719 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
11213 12:14:00.629246 # ----------------------------------------------------------------------
11214 12:14:00.632430 # Traceback (most recent call last):
11215 12:14:00.642418 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11216 12:14:00.645668 # self.client = tpm2.Client()
11217 12:14:00.655695 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11218 12:14:00.662163 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11219 12:14:00.665472 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11220 12:14:00.665593 #
11221 12:14:00.672020 # ======================================================================
11222 12:14:00.678807 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
11223 12:14:00.685435 # ----------------------------------------------------------------------
11224 12:14:00.688879 # Traceback (most recent call last):
11225 12:14:00.698589 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11226 12:14:00.702063 # self.client = tpm2.Client()
11227 12:14:00.711860 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11228 12:14:00.715358 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11229 12:14:00.721998 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11230 12:14:00.722112 #
11231 12:14:00.728644 # ======================================================================
11232 12:14:00.732121 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
11233 12:14:00.738468 # ----------------------------------------------------------------------
11234 12:14:00.741958 # Traceback (most recent call last):
11235 12:14:00.751652 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11236 12:14:00.755316 # self.client = tpm2.Client()
11237 12:14:00.765153 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11238 12:14:00.771703 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11239 12:14:00.774900 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11240 12:14:00.775004 #
11241 12:14:00.781496 # ======================================================================
11242 12:14:00.788318 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
11243 12:14:00.794773 # ----------------------------------------------------------------------
11244 12:14:00.798240 # Traceback (most recent call last):
11245 12:14:00.808042 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11246 12:14:00.811427 # self.client = tpm2.Client()
11247 12:14:00.821646 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11248 12:14:00.824693 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11249 12:14:00.828639 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11250 12:14:00.828741 #
11251 12:14:00.838884 # ======================================================================
11252 12:14:00.842685 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
11253 12:14:00.846842 # ----------------------------------------------------------------------
11254 12:14:00.850247 # Traceback (most recent call last):
11255 12:14:00.863716 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11256 12:14:00.863825 # self.client = tpm2.Client()
11257 12:14:00.876982 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11258 12:14:00.880930 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11259 12:14:00.884175 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11260 12:14:00.884283 #
11261 12:14:00.890718 # ======================================================================
11262 12:14:00.897729 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
11263 12:14:00.904153 # ----------------------------------------------------------------------
11264 12:14:00.907373 # Traceback (most recent call last):
11265 12:14:00.917273 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11266 12:14:00.920751 # self.client = tpm2.Client()
11267 12:14:00.930431 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11268 12:14:00.933935 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11269 12:14:00.940569 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11270 12:14:00.940659 #
11271 12:14:00.947324 # ======================================================================
11272 12:14:00.950316 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11273 12:14:00.957238 # ----------------------------------------------------------------------
11274 12:14:00.960246 # Traceback (most recent call last):
11275 12:14:00.970673 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11276 12:14:00.973543 # self.client = tpm2.Client()
11277 12:14:00.983520 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11278 12:14:00.990278 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11279 12:14:00.993575 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11280 12:14:00.993676 #
11281 12:14:01.000087 # ----------------------------------------------------------------------
11282 12:14:01.003444 # Ran 9 tests in 0.045s
11283 12:14:01.003542 #
11284 12:14:01.003633 # FAILED (errors=9)
11285 12:14:01.010775 # test_async (tpm2_tests.AsyncTest) ... ok
11286 12:14:01.013702 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11287 12:14:01.013771 #
11288 12:14:01.020268 # ----------------------------------------------------------------------
11289 12:14:01.023531 # Ran 2 tests in 0.037s
11290 12:14:01.023600 #
11291 12:14:01.023664 # OK
11292 12:14:01.026872 ok 1 selftests: tpm2: test_smoke.sh
11293 12:14:01.030112 # selftests: tpm2: test_space.sh
11294 12:14:01.033762 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11295 12:14:01.040152 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11296 12:14:01.043596 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11297 12:14:01.050312 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11298 12:14:01.050385 #
11299 12:14:01.057059 # ======================================================================
11300 12:14:01.060353 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11301 12:14:01.067038 # ----------------------------------------------------------------------
11302 12:14:01.070303 # Traceback (most recent call last):
11303 12:14:01.080155 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11304 12:14:01.083460 # root1 = space1.create_root_key()
11305 12:14:01.096922 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11306 12:14:01.100166 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11307 12:14:01.110112 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11308 12:14:01.113425 # raise ProtocolError(cc, rc)
11309 12:14:01.119994 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11310 12:14:01.120094 #
11311 12:14:01.126642 # ======================================================================
11312 12:14:01.130004 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11313 12:14:01.136629 # ----------------------------------------------------------------------
11314 12:14:01.140013 # Traceback (most recent call last):
11315 12:14:01.153191 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11316 12:14:01.153287 # space1.create_root_key()
11317 12:14:01.166625 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11318 12:14:01.169721 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11319 12:14:01.179815 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11320 12:14:01.182987 # raise ProtocolError(cc, rc)
11321 12:14:01.189560 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11322 12:14:01.189633 #
11323 12:14:01.196224 # ======================================================================
11324 12:14:01.199625 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11325 12:14:01.206272 # ----------------------------------------------------------------------
11326 12:14:01.209790 # Traceback (most recent call last):
11327 12:14:01.219896 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11328 12:14:01.223255 # root1 = space1.create_root_key()
11329 12:14:01.236186 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11330 12:14:01.239491 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11331 12:14:01.249577 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11332 12:14:01.252753 # raise ProtocolError(cc, rc)
11333 12:14:01.259668 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11334 12:14:01.259748 #
11335 12:14:01.266032 # ======================================================================
11336 12:14:01.269490 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11337 12:14:01.276258 # ----------------------------------------------------------------------
11338 12:14:01.279384 # Traceback (most recent call last):
11339 12:14:01.292607 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11340 12:14:01.296058 # root1 = space1.create_root_key()
11341 12:14:01.306062 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11342 12:14:01.312635 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11343 12:14:01.322430 # File "/lava-12669498/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11344 12:14:01.325823 # raise ProtocolError(cc, rc)
11345 12:14:01.329104 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11346 12:14:01.332644 #
11347 12:14:01.335897 # ----------------------------------------------------------------------
11348 12:14:01.339418 # Ran 4 tests in 0.058s
11349 12:14:01.339526 #
11350 12:14:01.342329 # FAILED (errors=4)
11351 12:14:01.345790 not ok 2 selftests: tpm2: test_space.sh # exit=1
11352 12:14:01.372530 tpm2_test_smoke_sh pass
11353 12:14:01.375839 tpm2_test_space_sh fail
11354 12:14:01.389851 + ../../utils/send-to-lava.sh ./output/result.txt
11355 12:14:01.467946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11356 12:14:01.468239 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11358 12:14:01.525829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11359 12:14:01.526096 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11361 12:14:01.588434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11362 12:14:01.588778 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11364 12:14:01.591885 + set +x
11365 12:14:01.594998 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 12669498_1.6.2.3.5>
11366 12:14:01.595282 Received signal: <ENDRUN> 1_kselftest-tpm2 12669498_1.6.2.3.5
11367 12:14:01.595394 Ending use of test pattern.
11368 12:14:01.595485 Ending test lava.1_kselftest-tpm2 (12669498_1.6.2.3.5), duration 11.31
11370 12:14:01.598205 <LAVA_TEST_RUNNER EXIT>
11371 12:14:01.598453 ok: lava_test_shell seems to have completed
11372 12:14:01.598562 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11373 12:14:01.598652 end: 3.1 lava-test-shell (duration 00:00:12) [common]
11374 12:14:01.598737 end: 3 lava-test-retry (duration 00:00:12) [common]
11375 12:14:01.598825 start: 4 finalize (timeout 00:07:13) [common]
11376 12:14:01.598917 start: 4.1 power-off (timeout 00:00:30) [common]
11377 12:14:01.599087 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11378 12:14:01.674576 >> Command sent successfully.
11379 12:14:01.677188 Returned 0 in 0 seconds
11380 12:14:01.777636 end: 4.1 power-off (duration 00:00:00) [common]
11382 12:14:01.777987 start: 4.2 read-feedback (timeout 00:07:13) [common]
11383 12:14:01.778262 Listened to connection for namespace 'common' for up to 1s
11384 12:14:02.779411 Finalising connection for namespace 'common'
11385 12:14:02.780102 Disconnecting from shell: Finalise
11386 12:14:02.780567 / #
11387 12:14:02.881777 end: 4.2 read-feedback (duration 00:00:01) [common]
11388 12:14:02.882505 end: 4 finalize (duration 00:00:01) [common]
11389 12:14:02.883146 Cleaning after the job
11390 12:14:02.883672 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669498/tftp-deploy-anyajq8p/ramdisk
11391 12:14:02.888371 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669498/tftp-deploy-anyajq8p/kernel
11392 12:14:02.900975 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669498/tftp-deploy-anyajq8p/dtb
11393 12:14:02.901141 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669498/tftp-deploy-anyajq8p/nfsrootfs
11394 12:14:02.991152 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669498/tftp-deploy-anyajq8p/modules
11395 12:14:02.998721 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12669498
11396 12:14:03.625820 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12669498
11397 12:14:03.626003 Job finished correctly