Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 38
- Kernel Errors: 33
1 12:12:12.712845 lava-dispatcher, installed at version: 2023.10
2 12:12:12.713033 start: 0 validate
3 12:12:12.713158 Start time: 2024-01-31 12:12:12.713150+00:00 (UTC)
4 12:12:12.713277 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:12:12.713404 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:12:12.984559 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:12:12.985341 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:12:13.256131 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:12:13.257013 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:12:32.631140 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:12:32.631867 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:12:33.170127 validate duration: 20.46
14 12:12:33.170405 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:12:33.170502 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:12:33.170588 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:12:33.170708 Not decompressing ramdisk as can be used compressed.
18 12:12:33.170793 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/rootfs.cpio.gz
19 12:12:33.170859 saving as /var/lib/lava/dispatcher/tmp/12669505/tftp-deploy-kbhi3sxt/ramdisk/rootfs.cpio.gz
20 12:12:33.170924 total size: 84918747 (80 MB)
21 12:12:35.816888 progress 0 % (0 MB)
22 12:12:35.840605 progress 5 % (4 MB)
23 12:12:35.861894 progress 10 % (8 MB)
24 12:12:35.882614 progress 15 % (12 MB)
25 12:12:35.903786 progress 20 % (16 MB)
26 12:12:35.924764 progress 25 % (20 MB)
27 12:12:35.945773 progress 30 % (24 MB)
28 12:12:35.967060 progress 35 % (28 MB)
29 12:12:35.987856 progress 40 % (32 MB)
30 12:12:36.008925 progress 45 % (36 MB)
31 12:12:36.029676 progress 50 % (40 MB)
32 12:12:36.050561 progress 55 % (44 MB)
33 12:12:36.071583 progress 60 % (48 MB)
34 12:12:36.092614 progress 65 % (52 MB)
35 12:12:36.113772 progress 70 % (56 MB)
36 12:12:36.134627 progress 75 % (60 MB)
37 12:12:36.155632 progress 80 % (64 MB)
38 12:12:36.176659 progress 85 % (68 MB)
39 12:12:36.197834 progress 90 % (72 MB)
40 12:12:36.218655 progress 95 % (76 MB)
41 12:12:36.239173 progress 100 % (80 MB)
42 12:12:36.239368 80 MB downloaded in 3.07 s (26.39 MB/s)
43 12:12:36.239530 end: 1.1.1 http-download (duration 00:00:03) [common]
45 12:12:36.239774 end: 1.1 download-retry (duration 00:00:03) [common]
46 12:12:36.239923 start: 1.2 download-retry (timeout 00:09:57) [common]
47 12:12:36.240051 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 12:12:36.240186 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:12:36.240260 saving as /var/lib/lava/dispatcher/tmp/12669505/tftp-deploy-kbhi3sxt/kernel/Image
50 12:12:36.240324 total size: 51532288 (49 MB)
51 12:12:36.240387 No compression specified
52 12:12:36.506249 progress 0 % (0 MB)
53 12:12:36.555841 progress 5 % (2 MB)
54 12:12:36.573708 progress 10 % (4 MB)
55 12:12:36.587220 progress 15 % (7 MB)
56 12:12:36.600266 progress 20 % (9 MB)
57 12:12:36.613816 progress 25 % (12 MB)
58 12:12:36.628037 progress 30 % (14 MB)
59 12:12:36.641349 progress 35 % (17 MB)
60 12:12:36.654359 progress 40 % (19 MB)
61 12:12:36.667131 progress 45 % (22 MB)
62 12:12:36.680147 progress 50 % (24 MB)
63 12:12:36.692951 progress 55 % (27 MB)
64 12:12:36.706045 progress 60 % (29 MB)
65 12:12:36.719020 progress 65 % (31 MB)
66 12:12:36.731707 progress 70 % (34 MB)
67 12:12:36.744356 progress 75 % (36 MB)
68 12:12:36.756917 progress 80 % (39 MB)
69 12:12:36.769379 progress 85 % (41 MB)
70 12:12:36.782142 progress 90 % (44 MB)
71 12:12:36.794863 progress 95 % (46 MB)
72 12:12:36.807428 progress 100 % (49 MB)
73 12:12:36.807631 49 MB downloaded in 0.57 s (86.63 MB/s)
74 12:12:36.807783 end: 1.2.1 http-download (duration 00:00:01) [common]
76 12:12:36.808016 end: 1.2 download-retry (duration 00:00:01) [common]
77 12:12:36.808107 start: 1.3 download-retry (timeout 00:09:56) [common]
78 12:12:36.808194 start: 1.3.1 http-download (timeout 00:09:56) [common]
79 12:12:36.808328 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:12:36.808398 saving as /var/lib/lava/dispatcher/tmp/12669505/tftp-deploy-kbhi3sxt/dtb/mt8192-asurada-spherion-r0.dtb
81 12:12:36.808461 total size: 47278 (0 MB)
82 12:12:36.808523 No compression specified
83 12:12:36.809644 progress 69 % (0 MB)
84 12:12:36.809912 progress 100 % (0 MB)
85 12:12:36.810127 0 MB downloaded in 0.00 s (27.10 MB/s)
86 12:12:36.810250 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:12:36.810473 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:12:36.810558 start: 1.4 download-retry (timeout 00:09:56) [common]
90 12:12:36.810641 start: 1.4.1 http-download (timeout 00:09:56) [common]
91 12:12:36.810753 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:12:36.810825 saving as /var/lib/lava/dispatcher/tmp/12669505/tftp-deploy-kbhi3sxt/modules/modules.tar
93 12:12:36.810886 total size: 8639916 (8 MB)
94 12:12:36.810948 Using unxz to decompress xz
95 12:12:36.814507 progress 0 % (0 MB)
96 12:12:36.835450 progress 5 % (0 MB)
97 12:12:36.857869 progress 10 % (0 MB)
98 12:12:36.880683 progress 15 % (1 MB)
99 12:12:36.903871 progress 20 % (1 MB)
100 12:12:36.927444 progress 25 % (2 MB)
101 12:12:36.953918 progress 30 % (2 MB)
102 12:12:36.977104 progress 35 % (2 MB)
103 12:12:36.999681 progress 40 % (3 MB)
104 12:12:37.023438 progress 45 % (3 MB)
105 12:12:37.047967 progress 50 % (4 MB)
106 12:12:37.072980 progress 55 % (4 MB)
107 12:12:37.096937 progress 60 % (4 MB)
108 12:12:37.121917 progress 65 % (5 MB)
109 12:12:37.146060 progress 70 % (5 MB)
110 12:12:37.168615 progress 75 % (6 MB)
111 12:12:37.194596 progress 80 % (6 MB)
112 12:12:37.221503 progress 85 % (7 MB)
113 12:12:37.245675 progress 90 % (7 MB)
114 12:12:37.274096 progress 95 % (7 MB)
115 12:12:37.300802 progress 100 % (8 MB)
116 12:12:37.306764 8 MB downloaded in 0.50 s (16.62 MB/s)
117 12:12:37.307034 end: 1.4.1 http-download (duration 00:00:00) [common]
119 12:12:37.307301 end: 1.4 download-retry (duration 00:00:00) [common]
120 12:12:37.307394 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 12:12:37.307490 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 12:12:37.307572 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:12:37.307658 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 12:12:37.307873 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy
125 12:12:37.308001 makedir: /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin
126 12:12:37.308103 makedir: /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/tests
127 12:12:37.308199 makedir: /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/results
128 12:12:37.308313 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-add-keys
129 12:12:37.308456 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-add-sources
130 12:12:37.308584 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-background-process-start
131 12:12:37.308711 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-background-process-stop
132 12:12:37.308834 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-common-functions
133 12:12:37.308955 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-echo-ipv4
134 12:12:37.309093 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-install-packages
135 12:12:37.309217 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-installed-packages
136 12:12:37.309338 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-os-build
137 12:12:37.309459 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-probe-channel
138 12:12:37.309583 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-probe-ip
139 12:12:37.309704 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-target-ip
140 12:12:37.309823 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-target-mac
141 12:12:37.309949 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-target-storage
142 12:12:37.310127 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-test-case
143 12:12:37.310250 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-test-event
144 12:12:37.310371 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-test-feedback
145 12:12:37.310492 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-test-raise
146 12:12:37.310613 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-test-reference
147 12:12:37.310733 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-test-runner
148 12:12:37.310853 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-test-set
149 12:12:37.310975 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-test-shell
150 12:12:37.311146 Updating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-install-packages (oe)
151 12:12:37.311338 Updating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/bin/lava-installed-packages (oe)
152 12:12:37.311472 Creating /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/environment
153 12:12:37.311574 LAVA metadata
154 12:12:37.311657 - LAVA_JOB_ID=12669505
155 12:12:37.311723 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:12:37.311825 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 12:12:37.311893 skipped lava-vland-overlay
158 12:12:37.311967 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:12:37.312049 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 12:12:37.312115 skipped lava-multinode-overlay
161 12:12:37.312191 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:12:37.312274 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 12:12:37.312348 Loading test definitions
164 12:12:37.312438 start: 1.5.2.3.1 git-repo-action (timeout 00:09:56) [common]
165 12:12:37.312511 Using /lava-12669505 at stage 0
166 12:12:37.312616 Fetching tests from https://github.com/kernelci/kernelci-core
167 12:12:37.312702 Running '/usr/bin/git clone -b kernelci.org --depth=1 https://github.com/kernelci/kernelci-core /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/0/tests/0_sleep'
168 12:12:37.960604 Removing '.git' directory in /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/0/tests/0_sleep
169 12:12:37.962627 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/0/tests/0_sleep/config/lava/sleep/sleep.yaml
170 12:12:37.963313 uuid=12669505_1.5.2.3.1 testdef=None
171 12:12:37.963565 end: 1.5.2.3.1 git-repo-action (duration 00:00:01) [common]
173 12:12:37.964018 start: 1.5.2.3.2 test-overlay (timeout 00:09:55) [common]
174 12:12:37.965027 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
176 12:12:37.965461 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:55) [common]
177 12:12:37.966736 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
179 12:12:37.967186 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:55) [common]
180 12:12:37.968405 runner path: /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/0/tests/0_sleep test_uuid 12669505_1.5.2.3.1
181 12:12:37.968564 sleep_params='mem'
182 12:12:37.968823 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
184 12:12:37.969220 Creating lava-test-runner.conf files
185 12:12:37.969343 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12669505/lava-overlay-6nseijvy/lava-12669505/0 for stage 0
186 12:12:37.969509 - 0_sleep
187 12:12:37.969698 end: 1.5.2.3 test-definition (duration 00:00:01) [common]
188 12:12:37.969857 start: 1.5.2.4 compress-overlay (timeout 00:09:55) [common]
189 12:12:38.114588 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
190 12:12:38.114740 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:55) [common]
191 12:12:38.114833 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
192 12:12:38.114929 end: 1.5.2 lava-overlay (duration 00:00:01) [common]
193 12:12:38.115017 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:55) [common]
194 12:12:40.353648 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
195 12:12:40.354072 start: 1.5.4 extract-modules (timeout 00:09:53) [common]
196 12:12:40.354187 extracting modules file /var/lib/lava/dispatcher/tmp/12669505/tftp-deploy-kbhi3sxt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12669505/extract-overlay-ramdisk-_15_kv6c/ramdisk
197 12:12:40.565357 end: 1.5.4 extract-modules (duration 00:00:00) [common]
198 12:12:40.565523 start: 1.5.5 apply-overlay-tftp (timeout 00:09:53) [common]
199 12:12:40.565623 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12669505/compress-overlay-sfkf8vdn/overlay-1.5.2.4.tar.gz to ramdisk
200 12:12:40.565698 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12669505/compress-overlay-sfkf8vdn/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12669505/extract-overlay-ramdisk-_15_kv6c/ramdisk
201 12:12:40.663086 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
202 12:12:40.663240 start: 1.5.6 configure-preseed-file (timeout 00:09:53) [common]
203 12:12:40.663337 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
204 12:12:40.663436 start: 1.5.7 compress-ramdisk (timeout 00:09:53) [common]
205 12:12:40.663522 Building ramdisk /var/lib/lava/dispatcher/tmp/12669505/extract-overlay-ramdisk-_15_kv6c/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12669505/extract-overlay-ramdisk-_15_kv6c/ramdisk
206 12:12:42.294277 >> 563683 blocks
207 12:12:51.909888 rename /var/lib/lava/dispatcher/tmp/12669505/extract-overlay-ramdisk-_15_kv6c/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12669505/tftp-deploy-kbhi3sxt/ramdisk/ramdisk.cpio.gz
208 12:12:51.910316 end: 1.5.7 compress-ramdisk (duration 00:00:11) [common]
209 12:12:51.910453 start: 1.5.8 prepare-kernel (timeout 00:09:41) [common]
210 12:12:51.910556 start: 1.5.8.1 prepare-fit (timeout 00:09:41) [common]
211 12:12:51.910681 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12669505/tftp-deploy-kbhi3sxt/kernel/Image'
212 12:13:04.205644 Returned 0 in 12 seconds
213 12:13:04.306640 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12669505/tftp-deploy-kbhi3sxt/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12669505/tftp-deploy-kbhi3sxt/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12669505/tftp-deploy-kbhi3sxt/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12669505/tftp-deploy-kbhi3sxt/kernel/image.itb
214 12:13:05.483228 output: FIT description: Kernel Image image with one or more FDT blobs
215 12:13:05.483576 output: Created: Wed Jan 31 12:13:05 2024
216 12:13:05.483655 output: Image 0 (kernel-1)
217 12:13:05.483724 output: Description:
218 12:13:05.483790 output: Created: Wed Jan 31 12:13:05 2024
219 12:13:05.483856 output: Type: Kernel Image
220 12:13:05.483917 output: Compression: lzma compressed
221 12:13:05.483977 output: Data Size: 12047284 Bytes = 11764.93 KiB = 11.49 MiB
222 12:13:05.484036 output: Architecture: AArch64
223 12:13:05.484095 output: OS: Linux
224 12:13:05.484153 output: Load Address: 0x00000000
225 12:13:05.484211 output: Entry Point: 0x00000000
226 12:13:05.484267 output: Hash algo: crc32
227 12:13:05.484323 output: Hash value: 5a47eb78
228 12:13:05.484380 output: Image 1 (fdt-1)
229 12:13:05.484436 output: Description: mt8192-asurada-spherion-r0
230 12:13:05.484490 output: Created: Wed Jan 31 12:13:05 2024
231 12:13:05.484544 output: Type: Flat Device Tree
232 12:13:05.484598 output: Compression: uncompressed
233 12:13:05.484652 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
234 12:13:05.484706 output: Architecture: AArch64
235 12:13:05.484760 output: Hash algo: crc32
236 12:13:05.484813 output: Hash value: cc4352de
237 12:13:05.484866 output: Image 2 (ramdisk-1)
238 12:13:05.484919 output: Description: unavailable
239 12:13:05.484972 output: Created: Wed Jan 31 12:13:05 2024
240 12:13:05.485026 output: Type: RAMDisk Image
241 12:13:05.485079 output: Compression: Unknown Compression
242 12:13:05.485133 output: Data Size: 98370703 Bytes = 96065.14 KiB = 93.81 MiB
243 12:13:05.485188 output: Architecture: AArch64
244 12:13:05.485241 output: OS: Linux
245 12:13:05.485294 output: Load Address: unavailable
246 12:13:05.485347 output: Entry Point: unavailable
247 12:13:05.485400 output: Hash algo: crc32
248 12:13:05.485454 output: Hash value: 407abfc9
249 12:13:05.485507 output: Default Configuration: 'conf-1'
250 12:13:05.485560 output: Configuration 0 (conf-1)
251 12:13:05.485613 output: Description: mt8192-asurada-spherion-r0
252 12:13:05.485667 output: Kernel: kernel-1
253 12:13:05.485720 output: Init Ramdisk: ramdisk-1
254 12:13:05.485773 output: FDT: fdt-1
255 12:13:05.485826 output: Loadables: kernel-1
256 12:13:05.485879 output:
257 12:13:05.486110 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
258 12:13:05.486205 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
259 12:13:05.486307 end: 1.5 prepare-tftp-overlay (duration 00:00:28) [common]
260 12:13:05.486398 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:28) [common]
261 12:13:05.486477 No LXC device requested
262 12:13:05.486556 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
263 12:13:05.486639 start: 1.7 deploy-device-env (timeout 00:09:28) [common]
264 12:13:05.486716 end: 1.7 deploy-device-env (duration 00:00:00) [common]
265 12:13:05.486787 Checking files for TFTP limit of 4294967296 bytes.
266 12:13:05.487255 end: 1 tftp-deploy (duration 00:00:32) [common]
267 12:13:05.487362 start: 2 depthcharge-action (timeout 00:05:00) [common]
268 12:13:05.487454 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
269 12:13:05.487581 substitutions:
270 12:13:05.487650 - {DTB}: 12669505/tftp-deploy-kbhi3sxt/dtb/mt8192-asurada-spherion-r0.dtb
271 12:13:05.487716 - {INITRD}: 12669505/tftp-deploy-kbhi3sxt/ramdisk/ramdisk.cpio.gz
272 12:13:05.487777 - {KERNEL}: 12669505/tftp-deploy-kbhi3sxt/kernel/Image
273 12:13:05.487836 - {LAVA_MAC}: None
274 12:13:05.487893 - {PRESEED_CONFIG}: None
275 12:13:05.487950 - {PRESEED_LOCAL}: None
276 12:13:05.488005 - {RAMDISK}: 12669505/tftp-deploy-kbhi3sxt/ramdisk/ramdisk.cpio.gz
277 12:13:05.488061 - {ROOT_PART}: None
278 12:13:05.488116 - {ROOT}: None
279 12:13:05.488172 - {SERVER_IP}: 192.168.201.1
280 12:13:05.488227 - {TEE}: None
281 12:13:05.488282 Parsed boot commands:
282 12:13:05.488336 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
283 12:13:05.488510 Parsed boot commands: tftpboot 192.168.201.1 12669505/tftp-deploy-kbhi3sxt/kernel/image.itb 12669505/tftp-deploy-kbhi3sxt/kernel/cmdline
284 12:13:05.488601 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
285 12:13:05.488686 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
286 12:13:05.488780 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
287 12:13:05.488866 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
288 12:13:05.488939 Not connected, no need to disconnect.
289 12:13:05.489015 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
290 12:13:05.489098 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
291 12:13:05.489167 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
292 12:13:05.492482 Setting prompt string to ['lava-test: # ']
293 12:13:05.492805 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
294 12:13:05.492913 end: 2.2.1 reset-connection (duration 00:00:00) [common]
295 12:13:05.493052 start: 2.2.2 reset-device (timeout 00:05:00) [common]
296 12:13:05.493198 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
297 12:13:05.493390 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
298 12:13:10.637895 >> Command sent successfully.
299 12:13:10.649090 Returned 0 in 5 seconds
300 12:13:10.750495 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
302 12:13:10.752049 end: 2.2.2 reset-device (duration 00:00:05) [common]
303 12:13:10.752628 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
304 12:13:10.753337 Setting prompt string to 'Starting depthcharge on Spherion...'
305 12:13:10.753746 Changing prompt to 'Starting depthcharge on Spherion...'
306 12:13:10.754245 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
307 12:13:10.755553 [Enter `^Ec?' for help]
308 12:13:10.915059
309 12:13:10.915670
310 12:13:10.916073 F0: 102B 0000
311 12:13:10.916468
312 12:13:10.916822 F3: 1001 0000 [0200]
313 12:13:10.918591
314 12:13:10.919072 F3: 1001 0000
315 12:13:10.919456
316 12:13:10.919806 F7: 102D 0000
317 12:13:10.920143
318 12:13:10.922097 F1: 0000 0000
319 12:13:10.922680
320 12:13:10.923068 V0: 0000 0000 [0001]
321 12:13:10.923426
322 12:13:10.925233 00: 0007 8000
323 12:13:10.925722
324 12:13:10.926175 01: 0000 0000
325 12:13:10.926550
326 12:13:10.928370 BP: 0C00 0209 [0000]
327 12:13:10.928852
328 12:13:10.929231 G0: 1182 0000
329 12:13:10.929588
330 12:13:10.932274 EC: 0000 0021 [4000]
331 12:13:10.932851
332 12:13:10.933237 S7: 0000 0000 [0000]
333 12:13:10.933600
334 12:13:10.935722 CC: 0000 0000 [0001]
335 12:13:10.936205
336 12:13:10.936585 T0: 0000 0040 [010F]
337 12:13:10.936945
338 12:13:10.937290 Jump to BL
339 12:13:10.937628
340 12:13:10.961909
341 12:13:10.962528
342 12:13:10.962911
343 12:13:10.969102 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
344 12:13:10.972707 ARM64: Exception handlers installed.
345 12:13:10.976685 ARM64: Testing exception
346 12:13:10.979801 ARM64: Done test exception
347 12:13:10.986374 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
348 12:13:10.997063 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
349 12:13:11.003856 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
350 12:13:11.013722 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
351 12:13:11.020418 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
352 12:13:11.026892 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
353 12:13:11.039701 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
354 12:13:11.045925 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
355 12:13:11.064839 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
356 12:13:11.068234 WDT: Last reset was cold boot
357 12:13:11.071822 SPI1(PAD0) initialized at 2873684 Hz
358 12:13:11.075157 SPI5(PAD0) initialized at 992727 Hz
359 12:13:11.078062 VBOOT: Loading verstage.
360 12:13:11.085026 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
361 12:13:11.088469 FMAP: Found "FLASH" version 1.1 at 0x20000.
362 12:13:11.091962 FMAP: base = 0x0 size = 0x800000 #areas = 25
363 12:13:11.094945 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
364 12:13:11.102572 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
365 12:13:11.109067 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
366 12:13:11.120172 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
367 12:13:11.120757
368 12:13:11.121133
369 12:13:11.130028 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
370 12:13:11.133510 ARM64: Exception handlers installed.
371 12:13:11.137024 ARM64: Testing exception
372 12:13:11.137624 ARM64: Done test exception
373 12:13:11.143617 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
374 12:13:11.146455 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
375 12:13:11.160824 Probing TPM: . done!
376 12:13:11.161455 TPM ready after 0 ms
377 12:13:11.168113 Connected to device vid:did:rid of 1ae0:0028:00
378 12:13:11.175253 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
379 12:13:11.231698 Initialized TPM device CR50 revision 0
380 12:13:11.243873 tlcl_send_startup: Startup return code is 0
381 12:13:11.244476 TPM: setup succeeded
382 12:13:11.255530 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
383 12:13:11.264141 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
384 12:13:11.274549 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
385 12:13:11.283637 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
386 12:13:11.287022 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
387 12:13:11.293611 in-header: 03 07 00 00 08 00 00 00
388 12:13:11.297184 in-data: aa e4 47 04 13 02 00 00
389 12:13:11.300798 Chrome EC: UHEPI supported
390 12:13:11.308008 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
391 12:13:11.311508 in-header: 03 ad 00 00 08 00 00 00
392 12:13:11.315353 in-data: 00 20 20 08 00 00 00 00
393 12:13:11.316053 Phase 1
394 12:13:11.319174 FMAP: area GBB found @ 3f5000 (12032 bytes)
395 12:13:11.326900 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
396 12:13:11.330482 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
397 12:13:11.334099 Recovery requested (1009000e)
398 12:13:11.342623 TPM: Extending digest for VBOOT: boot mode into PCR 0
399 12:13:11.348466 tlcl_extend: response is 0
400 12:13:11.357916 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
401 12:13:11.363620 tlcl_extend: response is 0
402 12:13:11.370522 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
403 12:13:11.390664 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
404 12:13:11.397490 BS: bootblock times (exec / console): total (unknown) / 148 ms
405 12:13:11.398013
406 12:13:11.398398
407 12:13:11.407766 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
408 12:13:11.411268 ARM64: Exception handlers installed.
409 12:13:11.411853 ARM64: Testing exception
410 12:13:11.414451 ARM64: Done test exception
411 12:13:11.435978 pmic_efuse_setting: Set efuses in 11 msecs
412 12:13:11.439613 pmwrap_interface_init: Select PMIF_VLD_RDY
413 12:13:11.446494 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
414 12:13:11.450336 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
415 12:13:11.453287 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
416 12:13:11.460042 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
417 12:13:11.463435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
418 12:13:11.470895 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
419 12:13:11.474583 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
420 12:13:11.478268 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
421 12:13:11.481822 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
422 12:13:11.489461 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
423 12:13:11.493009 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
424 12:13:11.497182 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
425 12:13:11.500298 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
426 12:13:11.507656 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
427 12:13:11.514879 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
428 12:13:11.521604 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
429 12:13:11.525380 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
430 12:13:11.532453 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
431 12:13:11.536223 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
432 12:13:11.542822 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
433 12:13:11.546102 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
434 12:13:11.553363 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
435 12:13:11.560349 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
436 12:13:11.563937 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
437 12:13:11.570163 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
438 12:13:11.576642 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
439 12:13:11.580190 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
440 12:13:11.583533 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
441 12:13:11.590283 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
442 12:13:11.593716 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
443 12:13:11.600224 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
444 12:13:11.603665 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
445 12:13:11.610599 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
446 12:13:11.613844 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
447 12:13:11.620318 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
448 12:13:11.623547 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
449 12:13:11.630329 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
450 12:13:11.633750 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
451 12:13:11.640629 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
452 12:13:11.644351 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
453 12:13:11.648214 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
454 12:13:11.651837 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
455 12:13:11.658639 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
456 12:13:11.661923 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
457 12:13:11.665300 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
458 12:13:11.668523 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
459 12:13:11.675073 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
460 12:13:11.678029 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
461 12:13:11.681347 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
462 12:13:11.688205 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
463 12:13:11.691747 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
464 12:13:11.698567 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
465 12:13:11.708535 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
466 12:13:11.711636 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
467 12:13:11.718061 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
468 12:13:11.728315 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
469 12:13:11.731700 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
470 12:13:11.738272 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
471 12:13:11.741688 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
472 12:13:11.748222 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
473 12:13:11.755136 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
474 12:13:11.758974 [RTC]rtc_osc_init,62: osc32con val = 0xde70
475 12:13:11.761418 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
476 12:13:11.772743 [RTC]rtc_get_frequency_meter,154: input=15, output=771
477 12:13:11.782978 [RTC]rtc_get_frequency_meter,154: input=23, output=956
478 12:13:11.792087 [RTC]rtc_get_frequency_meter,154: input=19, output=865
479 12:13:11.801719 [RTC]rtc_get_frequency_meter,154: input=17, output=819
480 12:13:11.810940 [RTC]rtc_get_frequency_meter,154: input=16, output=796
481 12:13:11.814677 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
482 12:13:11.820706 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
483 12:13:11.824402 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
484 12:13:11.827600 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
485 12:13:11.830645 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
486 12:13:11.834578 ADC[4]: Raw value=902876 ID=7
487 12:13:11.837936 ADC[3]: Raw value=213179 ID=1
488 12:13:11.838517 RAM Code: 0x71
489 12:13:11.844259 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
490 12:13:11.847613 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
491 12:13:11.857529 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
492 12:13:11.864314 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
493 12:13:11.867563 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
494 12:13:11.870795 in-header: 03 07 00 00 08 00 00 00
495 12:13:11.874487 in-data: aa e4 47 04 13 02 00 00
496 12:13:11.878321 Chrome EC: UHEPI supported
497 12:13:11.881590 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
498 12:13:11.892547 in-header: 03 ed 00 00 08 00 00 00
499 12:13:11.895770 in-data: 80 20 60 08 00 00 00 00
500 12:13:11.899409 MRC: failed to locate region type 0.
501 12:13:11.907103 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
502 12:13:11.910862 DRAM-K: Running full calibration
503 12:13:11.915039 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
504 12:13:11.918737 header.status = 0x0
505 12:13:11.922350 header.version = 0x6 (expected: 0x6)
506 12:13:11.926373 header.size = 0xd00 (expected: 0xd00)
507 12:13:11.926956 header.flags = 0x0
508 12:13:11.933042 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
509 12:13:11.950084 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
510 12:13:11.955992 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
511 12:13:11.959366 dram_init: ddr_geometry: 2
512 12:13:11.962826 [EMI] MDL number = 2
513 12:13:11.963422 [EMI] Get MDL freq = 0
514 12:13:11.966321 dram_init: ddr_type: 0
515 12:13:11.966911 is_discrete_lpddr4: 1
516 12:13:11.969357 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
517 12:13:11.969967
518 12:13:11.970359
519 12:13:11.972742 [Bian_co] ETT version 0.0.0.1
520 12:13:11.979580 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
521 12:13:11.980353
522 12:13:11.983090 dramc_set_vcore_voltage set vcore to 650000
523 12:13:11.983579 Read voltage for 800, 4
524 12:13:11.985995 Vio18 = 0
525 12:13:11.986563 Vcore = 650000
526 12:13:11.986952 Vdram = 0
527 12:13:11.989564 Vddq = 0
528 12:13:11.990087 Vmddr = 0
529 12:13:11.993645 dram_init: config_dvfs: 1
530 12:13:11.996917 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
531 12:13:12.001020 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
532 12:13:12.004350 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
533 12:13:12.011975 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
534 12:13:12.015525 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
535 12:13:12.019101 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
536 12:13:12.019543 MEM_TYPE=3, freq_sel=18
537 12:13:12.022659 sv_algorithm_assistance_LP4_1600
538 12:13:12.026038 ============ PULL DRAM RESETB DOWN ============
539 12:13:12.032632 ========== PULL DRAM RESETB DOWN end =========
540 12:13:12.036457 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
541 12:13:12.039770 ===================================
542 12:13:12.042911 LPDDR4 DRAM CONFIGURATION
543 12:13:12.046312 ===================================
544 12:13:12.046851 EX_ROW_EN[0] = 0x0
545 12:13:12.049345 EX_ROW_EN[1] = 0x0
546 12:13:12.049782 LP4Y_EN = 0x0
547 12:13:12.053000 WORK_FSP = 0x0
548 12:13:12.053438 WL = 0x2
549 12:13:12.056068 RL = 0x2
550 12:13:12.056508 BL = 0x2
551 12:13:12.059417 RPST = 0x0
552 12:13:12.059959 RD_PRE = 0x0
553 12:13:12.062842 WR_PRE = 0x1
554 12:13:12.063280 WR_PST = 0x0
555 12:13:12.066083 DBI_WR = 0x0
556 12:13:12.066622 DBI_RD = 0x0
557 12:13:12.069493 OTF = 0x1
558 12:13:12.073164 ===================================
559 12:13:12.076282 ===================================
560 12:13:12.076826 ANA top config
561 12:13:12.079856 ===================================
562 12:13:12.082563 DLL_ASYNC_EN = 0
563 12:13:12.086121 ALL_SLAVE_EN = 1
564 12:13:12.089711 NEW_RANK_MODE = 1
565 12:13:12.090309 DLL_IDLE_MODE = 1
566 12:13:12.092981 LP45_APHY_COMB_EN = 1
567 12:13:12.096132 TX_ODT_DIS = 1
568 12:13:12.099563 NEW_8X_MODE = 1
569 12:13:12.103060 ===================================
570 12:13:12.106177 ===================================
571 12:13:12.109688 data_rate = 1600
572 12:13:12.110272 CKR = 1
573 12:13:12.113019 DQ_P2S_RATIO = 8
574 12:13:12.116912 ===================================
575 12:13:12.119621 CA_P2S_RATIO = 8
576 12:13:12.123134 DQ_CA_OPEN = 0
577 12:13:12.126415 DQ_SEMI_OPEN = 0
578 12:13:12.126950 CA_SEMI_OPEN = 0
579 12:13:12.130032 CA_FULL_RATE = 0
580 12:13:12.133725 DQ_CKDIV4_EN = 1
581 12:13:12.136390 CA_CKDIV4_EN = 1
582 12:13:12.139865 CA_PREDIV_EN = 0
583 12:13:12.143193 PH8_DLY = 0
584 12:13:12.143734 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
585 12:13:12.146574 DQ_AAMCK_DIV = 4
586 12:13:12.149826 CA_AAMCK_DIV = 4
587 12:13:12.153148 CA_ADMCK_DIV = 4
588 12:13:12.156244 DQ_TRACK_CA_EN = 0
589 12:13:12.159503 CA_PICK = 800
590 12:13:12.163147 CA_MCKIO = 800
591 12:13:12.163599 MCKIO_SEMI = 0
592 12:13:12.166506 PLL_FREQ = 3068
593 12:13:12.169605 DQ_UI_PI_RATIO = 32
594 12:13:12.172787 CA_UI_PI_RATIO = 0
595 12:13:12.176357 ===================================
596 12:13:12.179658 ===================================
597 12:13:12.182467 memory_type:LPDDR4
598 12:13:12.182908 GP_NUM : 10
599 12:13:12.186559 SRAM_EN : 1
600 12:13:12.187037 MD32_EN : 0
601 12:13:12.190303 ===================================
602 12:13:12.193829 [ANA_INIT] >>>>>>>>>>>>>>
603 12:13:12.197259 <<<<<< [CONFIGURE PHASE]: ANA_TX
604 12:13:12.201242 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
605 12:13:12.205152 ===================================
606 12:13:12.205717 data_rate = 1600,PCW = 0X7600
607 12:13:12.208715 ===================================
608 12:13:12.212643 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
609 12:13:12.219333 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
610 12:13:12.223907 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
611 12:13:12.227170 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
612 12:13:12.230868 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
613 12:13:12.234368 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
614 12:13:12.238394 [ANA_INIT] flow start
615 12:13:12.238987 [ANA_INIT] PLL >>>>>>>>
616 12:13:12.242237 [ANA_INIT] PLL <<<<<<<<
617 12:13:12.245419 [ANA_INIT] MIDPI >>>>>>>>
618 12:13:12.245899 [ANA_INIT] MIDPI <<<<<<<<
619 12:13:12.249213 [ANA_INIT] DLL >>>>>>>>
620 12:13:12.249819 [ANA_INIT] flow end
621 12:13:12.256593 ============ LP4 DIFF to SE enter ============
622 12:13:12.260783 ============ LP4 DIFF to SE exit ============
623 12:13:12.261372 [ANA_INIT] <<<<<<<<<<<<<
624 12:13:12.264099 [Flow] Enable top DCM control >>>>>
625 12:13:12.268157 [Flow] Enable top DCM control <<<<<
626 12:13:12.271865 Enable DLL master slave shuffle
627 12:13:12.275566 ==============================================================
628 12:13:12.279178 Gating Mode config
629 12:13:12.283061 ==============================================================
630 12:13:12.286597 Config description:
631 12:13:12.293793 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
632 12:13:12.301507 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
633 12:13:12.305422 SELPH_MODE 0: By rank 1: By Phase
634 12:13:12.312497 ==============================================================
635 12:13:12.315884 GAT_TRACK_EN = 1
636 12:13:12.319665 RX_GATING_MODE = 2
637 12:13:12.320156 RX_GATING_TRACK_MODE = 2
638 12:13:12.322710 SELPH_MODE = 1
639 12:13:12.326895 PICG_EARLY_EN = 1
640 12:13:12.330299 VALID_LAT_VALUE = 1
641 12:13:12.334223 ==============================================================
642 12:13:12.337770 Enter into Gating configuration >>>>
643 12:13:12.341452 Exit from Gating configuration <<<<
644 12:13:12.345243 Enter into DVFS_PRE_config >>>>>
645 12:13:12.356444 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
646 12:13:12.360378 Exit from DVFS_PRE_config <<<<<
647 12:13:12.363688 Enter into PICG configuration >>>>
648 12:13:12.367415 Exit from PICG configuration <<<<
649 12:13:12.368207 [RX_INPUT] configuration >>>>>
650 12:13:12.370838 [RX_INPUT] configuration <<<<<
651 12:13:12.378273 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
652 12:13:12.382073 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
653 12:13:12.389415 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
654 12:13:12.393271 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
655 12:13:12.401035 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
656 12:13:12.408015 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
657 12:13:12.411866 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
658 12:13:12.415274 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
659 12:13:12.418799 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
660 12:13:12.422673 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
661 12:13:12.427029 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
662 12:13:12.430832 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
663 12:13:12.433914 ===================================
664 12:13:12.437320 LPDDR4 DRAM CONFIGURATION
665 12:13:12.440888 ===================================
666 12:13:12.441426 EX_ROW_EN[0] = 0x0
667 12:13:12.444544 EX_ROW_EN[1] = 0x0
668 12:13:12.444974 LP4Y_EN = 0x0
669 12:13:12.448328 WORK_FSP = 0x0
670 12:13:12.448758 WL = 0x2
671 12:13:12.451974 RL = 0x2
672 12:13:12.452617 BL = 0x2
673 12:13:12.455615 RPST = 0x0
674 12:13:12.456044 RD_PRE = 0x0
675 12:13:12.459024 WR_PRE = 0x1
676 12:13:12.459571 WR_PST = 0x0
677 12:13:12.463294 DBI_WR = 0x0
678 12:13:12.463721 DBI_RD = 0x0
679 12:13:12.466605 OTF = 0x1
680 12:13:12.470456 ===================================
681 12:13:12.473990 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
682 12:13:12.477765 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
683 12:13:12.481525 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
684 12:13:12.485016 ===================================
685 12:13:12.485471 LPDDR4 DRAM CONFIGURATION
686 12:13:12.488877 ===================================
687 12:13:12.492944 EX_ROW_EN[0] = 0x10
688 12:13:12.493520 EX_ROW_EN[1] = 0x0
689 12:13:12.496306 LP4Y_EN = 0x0
690 12:13:12.496783 WORK_FSP = 0x0
691 12:13:12.500223 WL = 0x2
692 12:13:12.500706 RL = 0x2
693 12:13:12.503987 BL = 0x2
694 12:13:12.504588 RPST = 0x0
695 12:13:12.508101 RD_PRE = 0x0
696 12:13:12.508682 WR_PRE = 0x1
697 12:13:12.509140 WR_PST = 0x0
698 12:13:12.511434 DBI_WR = 0x0
699 12:13:12.511912 DBI_RD = 0x0
700 12:13:12.515394 OTF = 0x1
701 12:13:12.518751 ===================================
702 12:13:12.526295 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
703 12:13:12.526887 nWR fixed to 40
704 12:13:12.529763 [ModeRegInit_LP4] CH0 RK0
705 12:13:12.533016 [ModeRegInit_LP4] CH0 RK1
706 12:13:12.533603 [ModeRegInit_LP4] CH1 RK0
707 12:13:12.536622 [ModeRegInit_LP4] CH1 RK1
708 12:13:12.539904 match AC timing 13
709 12:13:12.542900 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
710 12:13:12.546248 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
711 12:13:12.552874 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
712 12:13:12.556292 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
713 12:13:12.560040 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
714 12:13:12.562757 [EMI DOE] emi_dcm 0
715 12:13:12.566331 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
716 12:13:12.566925 ==
717 12:13:12.570327 Dram Type= 6, Freq= 0, CH_0, rank 0
718 12:13:12.576720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
719 12:13:12.577339 ==
720 12:13:12.579710 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
721 12:13:12.586478 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
722 12:13:12.595586 [CA 0] Center 37 (7~68) winsize 62
723 12:13:12.598693 [CA 1] Center 38 (7~69) winsize 63
724 12:13:12.602212 [CA 2] Center 35 (5~66) winsize 62
725 12:13:12.605765 [CA 3] Center 35 (5~66) winsize 62
726 12:13:12.609307 [CA 4] Center 35 (4~66) winsize 63
727 12:13:12.612419 [CA 5] Center 33 (3~64) winsize 62
728 12:13:12.612996
729 12:13:12.615278 [CmdBusTrainingLP45] Vref(ca) range 1: 32
730 12:13:12.615759
731 12:13:12.618842 [CATrainingPosCal] consider 1 rank data
732 12:13:12.622275 u2DelayCellTimex100 = 270/100 ps
733 12:13:12.626116 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
734 12:13:12.628703 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
735 12:13:12.635850 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
736 12:13:12.639156 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
737 12:13:12.642485 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
738 12:13:12.645384 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
739 12:13:12.645984
740 12:13:12.648871 CA PerBit enable=1, Macro0, CA PI delay=33
741 12:13:12.649451
742 12:13:12.652441 [CBTSetCACLKResult] CA Dly = 33
743 12:13:12.653087 CS Dly: 5 (0~36)
744 12:13:12.655290 ==
745 12:13:12.655766 Dram Type= 6, Freq= 0, CH_0, rank 1
746 12:13:12.662104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
747 12:13:12.662679 ==
748 12:13:12.665713 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
749 12:13:12.672535 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
750 12:13:12.682324 [CA 0] Center 38 (7~69) winsize 63
751 12:13:12.685187 [CA 1] Center 38 (8~69) winsize 62
752 12:13:12.688744 [CA 2] Center 36 (6~67) winsize 62
753 12:13:12.691957 [CA 3] Center 36 (5~67) winsize 63
754 12:13:12.695499 [CA 4] Center 35 (4~66) winsize 63
755 12:13:12.698875 [CA 5] Center 34 (4~65) winsize 62
756 12:13:12.699459
757 12:13:12.702635 [CmdBusTrainingLP45] Vref(ca) range 1: 34
758 12:13:12.703222
759 12:13:12.706169 [CATrainingPosCal] consider 2 rank data
760 12:13:12.709206 u2DelayCellTimex100 = 270/100 ps
761 12:13:12.712745 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
762 12:13:12.715863 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
763 12:13:12.718923 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
764 12:13:12.725821 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
765 12:13:12.729256 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
766 12:13:12.732434 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
767 12:13:12.733033
768 12:13:12.735907 CA PerBit enable=1, Macro0, CA PI delay=34
769 12:13:12.736488
770 12:13:12.738892 [CBTSetCACLKResult] CA Dly = 34
771 12:13:12.739365 CS Dly: 6 (0~38)
772 12:13:12.739747
773 12:13:12.742501 ----->DramcWriteLeveling(PI) begin...
774 12:13:12.743085 ==
775 12:13:12.746190 Dram Type= 6, Freq= 0, CH_0, rank 0
776 12:13:12.752389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
777 12:13:12.752971 ==
778 12:13:12.755803 Write leveling (Byte 0): 31 => 31
779 12:13:12.759085 Write leveling (Byte 1): 27 => 27
780 12:13:12.759746 DramcWriteLeveling(PI) end<-----
781 12:13:12.760133
782 12:13:12.762595 ==
783 12:13:12.765726 Dram Type= 6, Freq= 0, CH_0, rank 0
784 12:13:12.769798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
785 12:13:12.770439 ==
786 12:13:12.773142 [Gating] SW mode calibration
787 12:13:12.780707 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
788 12:13:12.784279 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
789 12:13:12.787372 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
790 12:13:12.790754 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
791 12:13:12.798163 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:13:12.801818 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:13:12.805084 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:13:12.811684 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:13:12.815056 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:13:12.818549 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:13:12.821627 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:13:12.828435 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:13:12.831836 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:13:12.835158 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:13:12.841350 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:13:12.845329 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:13:12.848237 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 12:13:12.855325 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:13:12.858303 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
806 12:13:12.861687 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
807 12:13:12.868360 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
808 12:13:12.871749 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:13:12.875098 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:13:12.882073 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:13:12.885056 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:13:12.888724 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 12:13:12.892235 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 12:13:12.898674 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 12:13:12.901960 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
816 12:13:12.904946 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
817 12:13:12.912143 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 12:13:12.915415 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 12:13:12.918848 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 12:13:12.925404 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
821 12:13:12.928799 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
822 12:13:12.931795 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
823 12:13:12.938353 0 10 8 | B1->B0 | 3333 2424 | 1 0 | (1 0) (0 0)
824 12:13:12.942177 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
825 12:13:12.945234 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:13:12.952544 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:13:12.955436 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:13:12.958410 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 12:13:12.964919 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 12:13:12.968468 0 11 4 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
831 12:13:12.971735 0 11 8 | B1->B0 | 2928 4646 | 1 0 | (0 0) (0 0)
832 12:13:12.978309 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 12:13:12.981715 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:13:12.985235 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:13:12.988405 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 12:13:12.995430 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
837 12:13:12.998535 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
838 12:13:13.001847 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
839 12:13:13.008862 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
840 12:13:13.011943 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:13:13.015237 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:13:13.021702 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:13:13.025454 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:13:13.028804 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:13:13.035195 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:13:13.038751 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:13:13.042162 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:13:13.048798 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:13:13.051957 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:13:13.055250 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:13:13.062180 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 12:13:13.065482 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 12:13:13.068758 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
854 12:13:13.072159 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
855 12:13:13.078844 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
856 12:13:13.082016 Total UI for P1: 0, mck2ui 16
857 12:13:13.085168 best dqsien dly found for B0: ( 0, 14, 2)
858 12:13:13.088886 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
859 12:13:13.092185 Total UI for P1: 0, mck2ui 16
860 12:13:13.095404 best dqsien dly found for B1: ( 0, 14, 6)
861 12:13:13.098454 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
862 12:13:13.101931 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
863 12:13:13.102550
864 12:13:13.105575 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
865 12:13:13.108963 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
866 12:13:13.112312 [Gating] SW calibration Done
867 12:13:13.112898 ==
868 12:13:13.115726 Dram Type= 6, Freq= 0, CH_0, rank 0
869 12:13:13.118938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
870 12:13:13.122032 ==
871 12:13:13.122508 RX Vref Scan: 0
872 12:13:13.122886
873 12:13:13.125503 RX Vref 0 -> 0, step: 1
874 12:13:13.126124
875 12:13:13.128756 RX Delay -130 -> 252, step: 16
876 12:13:13.132066 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
877 12:13:13.135270 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
878 12:13:13.138813 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
879 12:13:13.142401 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
880 12:13:13.148785 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
881 12:13:13.151867 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
882 12:13:13.155244 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
883 12:13:13.159060 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
884 12:13:13.161918 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
885 12:13:13.168721 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
886 12:13:13.171859 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
887 12:13:13.175214 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
888 12:13:13.178857 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
889 12:13:13.182556 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
890 12:13:13.188541 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
891 12:13:13.192305 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
892 12:13:13.192896 ==
893 12:13:13.195332 Dram Type= 6, Freq= 0, CH_0, rank 0
894 12:13:13.198741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
895 12:13:13.199228 ==
896 12:13:13.202409 DQS Delay:
897 12:13:13.203001 DQS0 = 0, DQS1 = 0
898 12:13:13.203388 DQM Delay:
899 12:13:13.205560 DQM0 = 91, DQM1 = 80
900 12:13:13.206193 DQ Delay:
901 12:13:13.208792 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
902 12:13:13.212181 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
903 12:13:13.216062 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
904 12:13:13.218929 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
905 12:13:13.219522
906 12:13:13.219905
907 12:13:13.220261 ==
908 12:13:13.222171 Dram Type= 6, Freq= 0, CH_0, rank 0
909 12:13:13.229199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
910 12:13:13.229790 ==
911 12:13:13.230239
912 12:13:13.230604
913 12:13:13.230946 TX Vref Scan disable
914 12:13:13.231912 == TX Byte 0 ==
915 12:13:13.235438 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
916 12:13:13.238912 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
917 12:13:13.242382 == TX Byte 1 ==
918 12:13:13.245259 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
919 12:13:13.248819 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
920 12:13:13.252325 ==
921 12:13:13.255094 Dram Type= 6, Freq= 0, CH_0, rank 0
922 12:13:13.258474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 12:13:13.258961 ==
924 12:13:13.271563 TX Vref=22, minBit 8, minWin=26, winSum=442
925 12:13:13.274834 TX Vref=24, minBit 6, minWin=27, winSum=448
926 12:13:13.278248 TX Vref=26, minBit 11, minWin=27, winSum=450
927 12:13:13.281580 TX Vref=28, minBit 9, minWin=27, winSum=453
928 12:13:13.284833 TX Vref=30, minBit 5, minWin=28, winSum=457
929 12:13:13.291409 TX Vref=32, minBit 8, minWin=28, winSum=458
930 12:13:13.294683 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 32
931 12:13:13.295167
932 12:13:13.298092 Final TX Range 1 Vref 32
933 12:13:13.298580
934 12:13:13.298969 ==
935 12:13:13.301882 Dram Type= 6, Freq= 0, CH_0, rank 0
936 12:13:13.304923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
937 12:13:13.305518 ==
938 12:13:13.305905
939 12:13:13.308227
940 12:13:13.308814 TX Vref Scan disable
941 12:13:13.312047 == TX Byte 0 ==
942 12:13:13.314883 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
943 12:13:13.318157 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
944 12:13:13.321598 == TX Byte 1 ==
945 12:13:13.325249 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
946 12:13:13.331633 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
947 12:13:13.332220
948 12:13:13.332606 [DATLAT]
949 12:13:13.332960 Freq=800, CH0 RK0
950 12:13:13.333303
951 12:13:13.334581 DATLAT Default: 0xa
952 12:13:13.335059 0, 0xFFFF, sum = 0
953 12:13:13.338088 1, 0xFFFF, sum = 0
954 12:13:13.338682 2, 0xFFFF, sum = 0
955 12:13:13.341892 3, 0xFFFF, sum = 0
956 12:13:13.342529 4, 0xFFFF, sum = 0
957 12:13:13.345044 5, 0xFFFF, sum = 0
958 12:13:13.345644 6, 0xFFFF, sum = 0
959 12:13:13.348415 7, 0xFFFF, sum = 0
960 12:13:13.351300 8, 0xFFFF, sum = 0
961 12:13:13.351790 9, 0x0, sum = 1
962 12:13:13.352228 10, 0x0, sum = 2
963 12:13:13.354929 11, 0x0, sum = 3
964 12:13:13.355415 12, 0x0, sum = 4
965 12:13:13.358452 best_step = 10
966 12:13:13.358932
967 12:13:13.359313 ==
968 12:13:13.361900 Dram Type= 6, Freq= 0, CH_0, rank 0
969 12:13:13.365127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
970 12:13:13.365612 ==
971 12:13:13.368562 RX Vref Scan: 1
972 12:13:13.369149
973 12:13:13.369531 Set Vref Range= 32 -> 127
974 12:13:13.369891
975 12:13:13.371823 RX Vref 32 -> 127, step: 1
976 12:13:13.372408
977 12:13:13.374959 RX Delay -95 -> 252, step: 8
978 12:13:13.375453
979 12:13:13.378092 Set Vref, RX VrefLevel [Byte0]: 32
980 12:13:13.382040 [Byte1]: 32
981 12:13:13.382624
982 12:13:13.385737 Set Vref, RX VrefLevel [Byte0]: 33
983 12:13:13.388194 [Byte1]: 33
984 12:13:13.391707
985 12:13:13.392184 Set Vref, RX VrefLevel [Byte0]: 34
986 12:13:13.395588 [Byte1]: 34
987 12:13:13.399716
988 12:13:13.400300 Set Vref, RX VrefLevel [Byte0]: 35
989 12:13:13.402749 [Byte1]: 35
990 12:13:13.407004
991 12:13:13.407648 Set Vref, RX VrefLevel [Byte0]: 36
992 12:13:13.410442 [Byte1]: 36
993 12:13:13.414786
994 12:13:13.415367 Set Vref, RX VrefLevel [Byte0]: 37
995 12:13:13.418012 [Byte1]: 37
996 12:13:13.421996
997 12:13:13.422676 Set Vref, RX VrefLevel [Byte0]: 38
998 12:13:13.425241 [Byte1]: 38
999 12:13:13.429767
1000 12:13:13.430373 Set Vref, RX VrefLevel [Byte0]: 39
1001 12:13:13.433599 [Byte1]: 39
1002 12:13:13.437525
1003 12:13:13.438219 Set Vref, RX VrefLevel [Byte0]: 40
1004 12:13:13.440591 [Byte1]: 40
1005 12:13:13.445397
1006 12:13:13.445876 Set Vref, RX VrefLevel [Byte0]: 41
1007 12:13:13.448864 [Byte1]: 41
1008 12:13:13.453400
1009 12:13:13.453836 Set Vref, RX VrefLevel [Byte0]: 42
1010 12:13:13.456551 [Byte1]: 42
1011 12:13:13.460701
1012 12:13:13.461137 Set Vref, RX VrefLevel [Byte0]: 43
1013 12:13:13.463576 [Byte1]: 43
1014 12:13:13.468107
1015 12:13:13.468633 Set Vref, RX VrefLevel [Byte0]: 44
1016 12:13:13.471857 [Byte1]: 44
1017 12:13:13.475338
1018 12:13:13.475775 Set Vref, RX VrefLevel [Byte0]: 45
1019 12:13:13.478879 [Byte1]: 45
1020 12:13:13.482895
1021 12:13:13.483360 Set Vref, RX VrefLevel [Byte0]: 46
1022 12:13:13.486154 [Byte1]: 46
1023 12:13:13.490451
1024 12:13:13.490890 Set Vref, RX VrefLevel [Byte0]: 47
1025 12:13:13.493900 [Byte1]: 47
1026 12:13:13.498096
1027 12:13:13.498526 Set Vref, RX VrefLevel [Byte0]: 48
1028 12:13:13.501456 [Byte1]: 48
1029 12:13:13.505540
1030 12:13:13.505988 Set Vref, RX VrefLevel [Byte0]: 49
1031 12:13:13.509130 [Byte1]: 49
1032 12:13:13.513475
1033 12:13:13.513788 Set Vref, RX VrefLevel [Byte0]: 50
1034 12:13:13.516889 [Byte1]: 50
1035 12:13:13.521024
1036 12:13:13.521256 Set Vref, RX VrefLevel [Byte0]: 51
1037 12:13:13.523898 [Byte1]: 51
1038 12:13:13.528447
1039 12:13:13.528604 Set Vref, RX VrefLevel [Byte0]: 52
1040 12:13:13.531621 [Byte1]: 52
1041 12:13:13.535685
1042 12:13:13.535826 Set Vref, RX VrefLevel [Byte0]: 53
1043 12:13:13.539491 [Byte1]: 53
1044 12:13:13.543392
1045 12:13:13.543498 Set Vref, RX VrefLevel [Byte0]: 54
1046 12:13:13.546721 [Byte1]: 54
1047 12:13:13.550964
1048 12:13:13.551069 Set Vref, RX VrefLevel [Byte0]: 55
1049 12:13:13.554251 [Byte1]: 55
1050 12:13:13.558906
1051 12:13:13.559012 Set Vref, RX VrefLevel [Byte0]: 56
1052 12:13:13.561906 [Byte1]: 56
1053 12:13:13.566092
1054 12:13:13.566196 Set Vref, RX VrefLevel [Byte0]: 57
1055 12:13:13.569574 [Byte1]: 57
1056 12:13:13.573880
1057 12:13:13.574040 Set Vref, RX VrefLevel [Byte0]: 58
1058 12:13:13.577292 [Byte1]: 58
1059 12:13:13.581356
1060 12:13:13.581460 Set Vref, RX VrefLevel [Byte0]: 59
1061 12:13:13.584614 [Byte1]: 59
1062 12:13:13.588798
1063 12:13:13.588883 Set Vref, RX VrefLevel [Byte0]: 60
1064 12:13:13.592271 [Byte1]: 60
1065 12:13:13.596736
1066 12:13:13.597163 Set Vref, RX VrefLevel [Byte0]: 61
1067 12:13:13.600283 [Byte1]: 61
1068 12:13:13.604690
1069 12:13:13.605114 Set Vref, RX VrefLevel [Byte0]: 62
1070 12:13:13.607740 [Byte1]: 62
1071 12:13:13.612139
1072 12:13:13.612562 Set Vref, RX VrefLevel [Byte0]: 63
1073 12:13:13.615352 [Byte1]: 63
1074 12:13:13.619335
1075 12:13:13.619635 Set Vref, RX VrefLevel [Byte0]: 64
1076 12:13:13.622949 [Byte1]: 64
1077 12:13:13.627184
1078 12:13:13.627414 Set Vref, RX VrefLevel [Byte0]: 65
1079 12:13:13.630297 [Byte1]: 65
1080 12:13:13.634642
1081 12:13:13.634794 Set Vref, RX VrefLevel [Byte0]: 66
1082 12:13:13.637759 [Byte1]: 66
1083 12:13:13.642471
1084 12:13:13.642706 Set Vref, RX VrefLevel [Byte0]: 67
1085 12:13:13.645855 [Byte1]: 67
1086 12:13:13.649828
1087 12:13:13.650005 Set Vref, RX VrefLevel [Byte0]: 68
1088 12:13:13.653105 [Byte1]: 68
1089 12:13:13.657517
1090 12:13:13.657684 Set Vref, RX VrefLevel [Byte0]: 69
1091 12:13:13.660743 [Byte1]: 69
1092 12:13:13.665648
1093 12:13:13.665947 Set Vref, RX VrefLevel [Byte0]: 70
1094 12:13:13.668566 [Byte1]: 70
1095 12:13:13.672864
1096 12:13:13.673225 Set Vref, RX VrefLevel [Byte0]: 71
1097 12:13:13.676286 [Byte1]: 71
1098 12:13:13.680598
1099 12:13:13.680899 Set Vref, RX VrefLevel [Byte0]: 72
1100 12:13:13.683807 [Byte1]: 72
1101 12:13:13.687855
1102 12:13:13.688157 Set Vref, RX VrefLevel [Byte0]: 73
1103 12:13:13.691494 [Byte1]: 73
1104 12:13:13.695253
1105 12:13:13.695553 Set Vref, RX VrefLevel [Byte0]: 74
1106 12:13:13.698865 [Byte1]: 74
1107 12:13:13.703084
1108 12:13:13.703449 Set Vref, RX VrefLevel [Byte0]: 75
1109 12:13:13.706274 [Byte1]: 75
1110 12:13:13.710752
1111 12:13:13.710944 Set Vref, RX VrefLevel [Byte0]: 76
1112 12:13:13.713890 [Byte1]: 76
1113 12:13:13.718410
1114 12:13:13.718540 Set Vref, RX VrefLevel [Byte0]: 77
1115 12:13:13.721510 [Byte1]: 77
1116 12:13:13.725782
1117 12:13:13.725912 Final RX Vref Byte 0 = 63 to rank0
1118 12:13:13.729097 Final RX Vref Byte 1 = 51 to rank0
1119 12:13:13.732620 Final RX Vref Byte 0 = 63 to rank1
1120 12:13:13.735848 Final RX Vref Byte 1 = 51 to rank1==
1121 12:13:13.739084 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 12:13:13.745813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 12:13:13.746045 ==
1124 12:13:13.746171 DQS Delay:
1125 12:13:13.746280 DQS0 = 0, DQS1 = 0
1126 12:13:13.749001 DQM Delay:
1127 12:13:13.749152 DQM0 = 93, DQM1 = 81
1128 12:13:13.752657 DQ Delay:
1129 12:13:13.755790 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1130 12:13:13.759039 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1131 12:13:13.762536 DQ8 =76, DQ9 =64, DQ10 =80, DQ11 =76
1132 12:13:13.765872 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1133 12:13:13.766137
1134 12:13:13.766318
1135 12:13:13.772442 [DQSOSCAuto] RK0, (LSB)MR18= 0x3733, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1136 12:13:13.776061 CH0 RK0: MR19=606, MR18=3733
1137 12:13:13.782810 CH0_RK0: MR19=0x606, MR18=0x3733, DQSOSC=395, MR23=63, INC=94, DEC=63
1138 12:13:13.783280
1139 12:13:13.786083 ----->DramcWriteLeveling(PI) begin...
1140 12:13:13.786571 ==
1141 12:13:13.789327 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 12:13:13.792749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 12:13:13.793259 ==
1144 12:13:13.795920 Write leveling (Byte 0): 34 => 34
1145 12:13:13.799426 Write leveling (Byte 1): 28 => 28
1146 12:13:13.803162 DramcWriteLeveling(PI) end<-----
1147 12:13:13.803708
1148 12:13:13.804085 ==
1149 12:13:13.806397 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 12:13:13.809610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 12:13:13.810114 ==
1152 12:13:13.812768 [Gating] SW mode calibration
1153 12:13:13.819522 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 12:13:13.826111 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 12:13:13.829367 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1156 12:13:13.832807 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1157 12:13:13.839192 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:13:13.883560 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:13:13.883958 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:13:13.884105 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:13:13.884217 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:13:13.884305 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:13:13.884591 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:13:13.884878 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:13:13.884962 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:13:13.885070 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:13:13.885485 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:13:13.888178 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:13:13.891603 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 12:13:13.895002 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:13:13.898337 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:13:13.905122 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1173 12:13:13.908492 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1174 12:13:13.911883 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:13:13.918289 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:13:13.921876 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:13:13.925244 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:13:13.931962 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:13:13.935260 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:13:13.938533 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:13:13.945594 0 9 8 | B1->B0 | 2929 3333 | 1 1 | (1 1) (1 1)
1182 12:13:13.949169 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 12:13:13.952282 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 12:13:13.955554 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 12:13:13.962619 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 12:13:13.965935 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 12:13:13.968970 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 12:13:13.975484 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 1)
1189 12:13:13.978966 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1190 12:13:13.982640 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:13:13.989073 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:13:13.992538 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:13:13.995500 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:13:14.002863 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 12:13:14.006099 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 12:13:14.009024 0 11 4 | B1->B0 | 2727 3030 | 1 1 | (0 0) (0 0)
1197 12:13:14.016183 0 11 8 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
1198 12:13:14.019952 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 12:13:14.023625 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 12:13:14.027665 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 12:13:14.031662 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 12:13:14.038129 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 12:13:14.040919 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 12:13:14.045276 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 12:13:14.048825 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:13:14.055714 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:13:14.058723 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:13:14.062788 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:13:14.065545 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:13:14.072341 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:13:14.075604 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:13:14.078855 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:13:14.085445 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:13:14.089253 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:13:14.092423 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:13:14.099116 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:13:14.102322 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:13:14.106145 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 12:13:14.112370 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 12:13:14.115361 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1221 12:13:14.118561 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1222 12:13:14.122402 Total UI for P1: 0, mck2ui 16
1223 12:13:14.125601 best dqsien dly found for B0: ( 0, 14, 4)
1224 12:13:14.128687 Total UI for P1: 0, mck2ui 16
1225 12:13:14.132450 best dqsien dly found for B1: ( 0, 14, 4)
1226 12:13:14.135331 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1227 12:13:14.138882 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1228 12:13:14.139449
1229 12:13:14.142388 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1230 12:13:14.148865 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1231 12:13:14.149431 [Gating] SW calibration Done
1232 12:13:14.149810 ==
1233 12:13:14.152344 Dram Type= 6, Freq= 0, CH_0, rank 1
1234 12:13:14.158972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1235 12:13:14.159532 ==
1236 12:13:14.159909 RX Vref Scan: 0
1237 12:13:14.160255
1238 12:13:14.161878 RX Vref 0 -> 0, step: 1
1239 12:13:14.162394
1240 12:13:14.165798 RX Delay -130 -> 252, step: 16
1241 12:13:14.169037 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1242 12:13:14.172764 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1243 12:13:14.176022 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1244 12:13:14.182159 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1245 12:13:14.185503 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1246 12:13:14.189042 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1247 12:13:14.192023 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1248 12:13:14.195683 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1249 12:13:14.198583 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1250 12:13:14.205637 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1251 12:13:14.209112 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1252 12:13:14.212237 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1253 12:13:14.215623 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1254 12:13:14.218862 iDelay=206, Bit 13, Center 85 (-18 ~ 189) 208
1255 12:13:14.225620 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1256 12:13:14.229189 iDelay=206, Bit 15, Center 85 (-18 ~ 189) 208
1257 12:13:14.229774 ==
1258 12:13:14.232047 Dram Type= 6, Freq= 0, CH_0, rank 1
1259 12:13:14.235599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1260 12:13:14.236086 ==
1261 12:13:14.238877 DQS Delay:
1262 12:13:14.239461 DQS0 = 0, DQS1 = 0
1263 12:13:14.239947 DQM Delay:
1264 12:13:14.242064 DQM0 = 87, DQM1 = 81
1265 12:13:14.242546 DQ Delay:
1266 12:13:14.246050 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1267 12:13:14.248939 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1268 12:13:14.252241 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1269 12:13:14.255816 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1270 12:13:14.256395
1271 12:13:14.256879
1272 12:13:14.257332 ==
1273 12:13:14.258710 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 12:13:14.265563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1275 12:13:14.266195 ==
1276 12:13:14.266687
1277 12:13:14.267131
1278 12:13:14.267567 TX Vref Scan disable
1279 12:13:14.269303 == TX Byte 0 ==
1280 12:13:14.272435 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1281 12:13:14.275848 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1282 12:13:14.279516 == TX Byte 1 ==
1283 12:13:14.282649 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1284 12:13:14.286123 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1285 12:13:14.289679 ==
1286 12:13:14.290380 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 12:13:14.295938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 12:13:14.296413 ==
1289 12:13:14.308960 TX Vref=22, minBit 8, minWin=27, winSum=446
1290 12:13:14.312485 TX Vref=24, minBit 8, minWin=27, winSum=451
1291 12:13:14.315825 TX Vref=26, minBit 8, minWin=27, winSum=451
1292 12:13:14.318769 TX Vref=28, minBit 8, minWin=28, winSum=457
1293 12:13:14.322448 TX Vref=30, minBit 8, minWin=28, winSum=459
1294 12:13:14.325727 TX Vref=32, minBit 8, minWin=27, winSum=458
1295 12:13:14.332423 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
1296 12:13:14.332990
1297 12:13:14.335792 Final TX Range 1 Vref 30
1298 12:13:14.336361
1299 12:13:14.336727 ==
1300 12:13:14.339166 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 12:13:14.342454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 12:13:14.342917 ==
1303 12:13:14.343283
1304 12:13:14.343615
1305 12:13:14.345625 TX Vref Scan disable
1306 12:13:14.348865 == TX Byte 0 ==
1307 12:13:14.352287 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1308 12:13:14.355477 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1309 12:13:14.359089 == TX Byte 1 ==
1310 12:13:14.362305 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1311 12:13:14.366008 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1312 12:13:14.369306
1313 12:13:14.369722 [DATLAT]
1314 12:13:14.370005 Freq=800, CH0 RK1
1315 12:13:14.370248
1316 12:13:14.372332 DATLAT Default: 0xa
1317 12:13:14.372693 0, 0xFFFF, sum = 0
1318 12:13:14.375618 1, 0xFFFF, sum = 0
1319 12:13:14.376048 2, 0xFFFF, sum = 0
1320 12:13:14.379074 3, 0xFFFF, sum = 0
1321 12:13:14.379498 4, 0xFFFF, sum = 0
1322 12:13:14.382451 5, 0xFFFF, sum = 0
1323 12:13:14.382874 6, 0xFFFF, sum = 0
1324 12:13:14.385630 7, 0xFFFF, sum = 0
1325 12:13:14.388678 8, 0xFFFF, sum = 0
1326 12:13:14.389152 9, 0x0, sum = 1
1327 12:13:14.389517 10, 0x0, sum = 2
1328 12:13:14.392337 11, 0x0, sum = 3
1329 12:13:14.392823 12, 0x0, sum = 4
1330 12:13:14.395354 best_step = 10
1331 12:13:14.395810
1332 12:13:14.396171 ==
1333 12:13:14.398978 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 12:13:14.402191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 12:13:14.402652 ==
1336 12:13:14.405547 RX Vref Scan: 0
1337 12:13:14.406144
1338 12:13:14.406516 RX Vref 0 -> 0, step: 1
1339 12:13:14.406859
1340 12:13:14.409261 RX Delay -95 -> 252, step: 8
1341 12:13:14.415799 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1342 12:13:14.419149 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1343 12:13:14.422429 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1344 12:13:14.425785 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1345 12:13:14.429362 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1346 12:13:14.436015 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1347 12:13:14.439439 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1348 12:13:14.442381 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1349 12:13:14.446104 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1350 12:13:14.448994 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1351 12:13:14.455847 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1352 12:13:14.459518 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1353 12:13:14.462343 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1354 12:13:14.465738 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1355 12:13:14.469339 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1356 12:13:14.475898 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1357 12:13:14.476455 ==
1358 12:13:14.479134 Dram Type= 6, Freq= 0, CH_0, rank 1
1359 12:13:14.482231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1360 12:13:14.482691 ==
1361 12:13:14.483052 DQS Delay:
1362 12:13:14.485987 DQS0 = 0, DQS1 = 0
1363 12:13:14.486447 DQM Delay:
1364 12:13:14.489442 DQM0 = 90, DQM1 = 82
1365 12:13:14.490037 DQ Delay:
1366 12:13:14.492182 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1367 12:13:14.496032 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1368 12:13:14.499184 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76
1369 12:13:14.502561 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1370 12:13:14.503125
1371 12:13:14.503573
1372 12:13:14.509358 [DQSOSCAuto] RK1, (LSB)MR18= 0x401a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1373 12:13:14.512722 CH0 RK1: MR19=606, MR18=401A
1374 12:13:14.519220 CH0_RK1: MR19=0x606, MR18=0x401A, DQSOSC=393, MR23=63, INC=95, DEC=63
1375 12:13:14.522629 [RxdqsGatingPostProcess] freq 800
1376 12:13:14.529062 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1377 12:13:14.532786 Pre-setting of DQS Precalculation
1378 12:13:14.535665 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1379 12:13:14.536127 ==
1380 12:13:14.539156 Dram Type= 6, Freq= 0, CH_1, rank 0
1381 12:13:14.542538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 12:13:14.543114 ==
1383 12:13:14.549266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1384 12:13:14.555792 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1385 12:13:14.564271 [CA 0] Center 36 (6~67) winsize 62
1386 12:13:14.567607 [CA 1] Center 36 (6~67) winsize 62
1387 12:13:14.570835 [CA 2] Center 34 (4~65) winsize 62
1388 12:13:14.574014 [CA 3] Center 34 (3~65) winsize 63
1389 12:13:14.577537 [CA 4] Center 34 (4~65) winsize 62
1390 12:13:14.580561 [CA 5] Center 34 (3~65) winsize 63
1391 12:13:14.581030
1392 12:13:14.584598 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1393 12:13:14.585218
1394 12:13:14.587230 [CATrainingPosCal] consider 1 rank data
1395 12:13:14.590714 u2DelayCellTimex100 = 270/100 ps
1396 12:13:14.594168 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1397 12:13:14.597751 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 12:13:14.604395 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1399 12:13:14.607462 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1400 12:13:14.610529 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 12:13:14.613861 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1402 12:13:14.614376
1403 12:13:14.617523 CA PerBit enable=1, Macro0, CA PI delay=34
1404 12:13:14.618140
1405 12:13:14.621052 [CBTSetCACLKResult] CA Dly = 34
1406 12:13:14.621624 CS Dly: 5 (0~36)
1407 12:13:14.622047 ==
1408 12:13:14.624175 Dram Type= 6, Freq= 0, CH_1, rank 1
1409 12:13:14.630741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1410 12:13:14.631317 ==
1411 12:13:14.634204 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1412 12:13:14.640883 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1413 12:13:14.650318 [CA 0] Center 37 (6~68) winsize 63
1414 12:13:14.653476 [CA 1] Center 37 (6~68) winsize 63
1415 12:13:14.657155 [CA 2] Center 35 (5~66) winsize 62
1416 12:13:14.660297 [CA 3] Center 34 (4~65) winsize 62
1417 12:13:14.663699 [CA 4] Center 34 (4~65) winsize 62
1418 12:13:14.667180 [CA 5] Center 33 (3~64) winsize 62
1419 12:13:14.667753
1420 12:13:14.670548 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1421 12:13:14.671115
1422 12:13:14.673591 [CATrainingPosCal] consider 2 rank data
1423 12:13:14.676745 u2DelayCellTimex100 = 270/100 ps
1424 12:13:14.680851 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1425 12:13:14.684134 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1426 12:13:14.688022 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1427 12:13:14.692218 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1428 12:13:14.695073 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1429 12:13:14.699414 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1430 12:13:14.699891
1431 12:13:14.702887 CA PerBit enable=1, Macro0, CA PI delay=33
1432 12:13:14.703387
1433 12:13:14.706360 [CBTSetCACLKResult] CA Dly = 33
1434 12:13:14.706888 CS Dly: 6 (0~38)
1435 12:13:14.710533
1436 12:13:14.710999 ----->DramcWriteLeveling(PI) begin...
1437 12:13:14.711377 ==
1438 12:13:14.714004 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 12:13:14.720764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 12:13:14.721267 ==
1441 12:13:14.724396 Write leveling (Byte 0): 30 => 30
1442 12:13:14.724982 Write leveling (Byte 1): 31 => 31
1443 12:13:14.727613 DramcWriteLeveling(PI) end<-----
1444 12:13:14.728098
1445 12:13:14.731129 ==
1446 12:13:14.731713 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 12:13:14.737466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 12:13:14.738078 ==
1449 12:13:14.741224 [Gating] SW mode calibration
1450 12:13:14.747603 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1451 12:13:14.750897 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1452 12:13:14.757610 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1453 12:13:14.760741 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1454 12:13:14.764251 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 12:13:14.770787 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:13:14.774364 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:13:14.777809 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:13:14.781153 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:13:14.787787 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:13:14.790883 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:13:14.794328 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:13:14.800960 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:13:14.804512 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:13:14.807709 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:13:14.814275 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:13:14.817590 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 12:13:14.820704 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 12:13:14.827424 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1469 12:13:14.831404 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1470 12:13:14.834295 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1471 12:13:14.841356 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:13:14.844621 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:13:14.847980 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:13:14.854219 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:13:14.857658 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:13:14.860888 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:13:14.864328 0 9 4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
1478 12:13:14.870853 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1479 12:13:14.874658 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 12:13:14.877718 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 12:13:14.884287 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 12:13:14.887693 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 12:13:14.890783 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 12:13:14.897870 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1485 12:13:14.900858 0 10 4 | B1->B0 | 2e2e 2a2a | 0 0 | (0 1) (1 1)
1486 12:13:14.904618 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:13:14.911161 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:13:14.914712 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:13:14.917517 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:13:14.924321 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:13:14.927731 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 12:13:14.931101 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1493 12:13:14.937620 0 11 4 | B1->B0 | 3131 3333 | 0 0 | (0 0) (0 0)
1494 12:13:14.940878 0 11 8 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1495 12:13:14.944663 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 12:13:14.951358 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 12:13:14.954662 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 12:13:14.958011 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 12:13:14.961213 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 12:13:14.967860 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 12:13:14.971185 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1502 12:13:14.974523 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:13:14.981198 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:13:14.984717 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:13:14.988123 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:13:14.994572 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:13:14.997625 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:13:15.001073 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:13:15.007917 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:13:15.011074 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:13:15.014935 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:13:15.021523 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:13:15.024595 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:13:15.028107 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:13:15.034646 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 12:13:15.038120 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 12:13:15.041535 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1518 12:13:15.044544 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 12:13:15.047976 Total UI for P1: 0, mck2ui 16
1520 12:13:15.051197 best dqsien dly found for B0: ( 0, 14, 4)
1521 12:13:15.054689 Total UI for P1: 0, mck2ui 16
1522 12:13:15.057641 best dqsien dly found for B1: ( 0, 14, 4)
1523 12:13:15.061401 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1524 12:13:15.064770 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1525 12:13:15.065343
1526 12:13:15.071607 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1527 12:13:15.074816 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1528 12:13:15.075393 [Gating] SW calibration Done
1529 12:13:15.077700 ==
1530 12:13:15.081729 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 12:13:15.084771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1532 12:13:15.085346 ==
1533 12:13:15.085721 RX Vref Scan: 0
1534 12:13:15.086104
1535 12:13:15.088057 RX Vref 0 -> 0, step: 1
1536 12:13:15.088629
1537 12:13:15.091122 RX Delay -130 -> 252, step: 16
1538 12:13:15.094667 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1539 12:13:15.098060 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1540 12:13:15.101345 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1541 12:13:15.108279 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1542 12:13:15.111750 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1543 12:13:15.114870 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1544 12:13:15.117843 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1545 12:13:15.121531 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1546 12:13:15.128375 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1547 12:13:15.131302 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1548 12:13:15.134838 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1549 12:13:15.137932 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1550 12:13:15.141922 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1551 12:13:15.148145 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1552 12:13:15.151749 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1553 12:13:15.154747 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1554 12:13:15.155222 ==
1555 12:13:15.158385 Dram Type= 6, Freq= 0, CH_1, rank 0
1556 12:13:15.161583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1557 12:13:15.162087 ==
1558 12:13:15.165129 DQS Delay:
1559 12:13:15.165711 DQS0 = 0, DQS1 = 0
1560 12:13:15.168312 DQM Delay:
1561 12:13:15.168786 DQM0 = 90, DQM1 = 80
1562 12:13:15.169165 DQ Delay:
1563 12:13:15.171295 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1564 12:13:15.175058 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =85
1565 12:13:15.178603 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1566 12:13:15.182065 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1567 12:13:15.182644
1568 12:13:15.183130
1569 12:13:15.185506 ==
1570 12:13:15.186128 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 12:13:15.192048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 12:13:15.192634 ==
1573 12:13:15.193124
1574 12:13:15.193576
1575 12:13:15.195028 TX Vref Scan disable
1576 12:13:15.195652 == TX Byte 0 ==
1577 12:13:15.198222 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1578 12:13:15.204833 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1579 12:13:15.205407 == TX Byte 1 ==
1580 12:13:15.208428 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1581 12:13:15.215239 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1582 12:13:15.215815 ==
1583 12:13:15.218238 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 12:13:15.221531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 12:13:15.222101 ==
1586 12:13:15.234663 TX Vref=22, minBit 15, minWin=27, winSum=452
1587 12:13:15.237872 TX Vref=24, minBit 13, minWin=27, winSum=453
1588 12:13:15.241426 TX Vref=26, minBit 15, minWin=27, winSum=456
1589 12:13:15.244558 TX Vref=28, minBit 15, minWin=27, winSum=457
1590 12:13:15.247772 TX Vref=30, minBit 15, minWin=27, winSum=457
1591 12:13:15.254798 TX Vref=32, minBit 15, minWin=27, winSum=457
1592 12:13:15.258051 [TxChooseVref] Worse bit 15, Min win 27, Win sum 457, Final Vref 28
1593 12:13:15.258619
1594 12:13:15.261024 Final TX Range 1 Vref 28
1595 12:13:15.261496
1596 12:13:15.261936 ==
1597 12:13:15.264854 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 12:13:15.268480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 12:13:15.269058 ==
1600 12:13:15.269431
1601 12:13:15.269772
1602 12:13:15.271812 TX Vref Scan disable
1603 12:13:15.275044 == TX Byte 0 ==
1604 12:13:15.278669 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1605 12:13:15.281784 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1606 12:13:15.285772 == TX Byte 1 ==
1607 12:13:15.288942 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1608 12:13:15.292135 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1609 12:13:15.292706
1610 12:13:15.295134 [DATLAT]
1611 12:13:15.295601 Freq=800, CH1 RK0
1612 12:13:15.295970
1613 12:13:15.298713 DATLAT Default: 0xa
1614 12:13:15.299180 0, 0xFFFF, sum = 0
1615 12:13:15.301834 1, 0xFFFF, sum = 0
1616 12:13:15.302351 2, 0xFFFF, sum = 0
1617 12:13:15.305487 3, 0xFFFF, sum = 0
1618 12:13:15.306002 4, 0xFFFF, sum = 0
1619 12:13:15.309156 5, 0xFFFF, sum = 0
1620 12:13:15.309745 6, 0xFFFF, sum = 0
1621 12:13:15.312547 7, 0xFFFF, sum = 0
1622 12:13:15.313146 8, 0xFFFF, sum = 0
1623 12:13:15.315483 9, 0x0, sum = 1
1624 12:13:15.316060 10, 0x0, sum = 2
1625 12:13:15.319084 11, 0x0, sum = 3
1626 12:13:15.319665 12, 0x0, sum = 4
1627 12:13:15.322510 best_step = 10
1628 12:13:15.323084
1629 12:13:15.323455 ==
1630 12:13:15.325348 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 12:13:15.328725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 12:13:15.329196 ==
1633 12:13:15.332263 RX Vref Scan: 1
1634 12:13:15.332734
1635 12:13:15.333103 Set Vref Range= 32 -> 127
1636 12:13:15.333453
1637 12:13:15.335373 RX Vref 32 -> 127, step: 1
1638 12:13:15.335847
1639 12:13:15.338872 RX Delay -95 -> 252, step: 8
1640 12:13:15.339450
1641 12:13:15.342131 Set Vref, RX VrefLevel [Byte0]: 32
1642 12:13:15.345463 [Byte1]: 32
1643 12:13:15.346084
1644 12:13:15.348481 Set Vref, RX VrefLevel [Byte0]: 33
1645 12:13:15.351566 [Byte1]: 33
1646 12:13:15.355529
1647 12:13:15.356109 Set Vref, RX VrefLevel [Byte0]: 34
1648 12:13:15.358611 [Byte1]: 34
1649 12:13:15.363168
1650 12:13:15.363741 Set Vref, RX VrefLevel [Byte0]: 35
1651 12:13:15.366117 [Byte1]: 35
1652 12:13:15.370355
1653 12:13:15.370998 Set Vref, RX VrefLevel [Byte0]: 36
1654 12:13:15.374305 [Byte1]: 36
1655 12:13:15.377978
1656 12:13:15.378484 Set Vref, RX VrefLevel [Byte0]: 37
1657 12:13:15.381421 [Byte1]: 37
1658 12:13:15.385803
1659 12:13:15.386418 Set Vref, RX VrefLevel [Byte0]: 38
1660 12:13:15.389308 [Byte1]: 38
1661 12:13:15.393406
1662 12:13:15.394008 Set Vref, RX VrefLevel [Byte0]: 39
1663 12:13:15.396377 [Byte1]: 39
1664 12:13:15.400684
1665 12:13:15.401151 Set Vref, RX VrefLevel [Byte0]: 40
1666 12:13:15.404674 [Byte1]: 40
1667 12:13:15.408630
1668 12:13:15.409359 Set Vref, RX VrefLevel [Byte0]: 41
1669 12:13:15.411824 [Byte1]: 41
1670 12:13:15.416433
1671 12:13:15.417009 Set Vref, RX VrefLevel [Byte0]: 42
1672 12:13:15.419322 [Byte1]: 42
1673 12:13:15.423653
1674 12:13:15.424229 Set Vref, RX VrefLevel [Byte0]: 43
1675 12:13:15.427102 [Byte1]: 43
1676 12:13:15.431627
1677 12:13:15.432200 Set Vref, RX VrefLevel [Byte0]: 44
1678 12:13:15.434757 [Byte1]: 44
1679 12:13:15.438840
1680 12:13:15.439419 Set Vref, RX VrefLevel [Byte0]: 45
1681 12:13:15.442349 [Byte1]: 45
1682 12:13:15.446592
1683 12:13:15.447191 Set Vref, RX VrefLevel [Byte0]: 46
1684 12:13:15.450138 [Byte1]: 46
1685 12:13:15.453908
1686 12:13:15.454438 Set Vref, RX VrefLevel [Byte0]: 47
1687 12:13:15.457565 [Byte1]: 47
1688 12:13:15.461550
1689 12:13:15.462285 Set Vref, RX VrefLevel [Byte0]: 48
1690 12:13:15.465171 [Byte1]: 48
1691 12:13:15.469182
1692 12:13:15.469751 Set Vref, RX VrefLevel [Byte0]: 49
1693 12:13:15.472752 [Byte1]: 49
1694 12:13:15.477300
1695 12:13:15.477871 Set Vref, RX VrefLevel [Byte0]: 50
1696 12:13:15.480179 [Byte1]: 50
1697 12:13:15.484659
1698 12:13:15.485266 Set Vref, RX VrefLevel [Byte0]: 51
1699 12:13:15.487606 [Byte1]: 51
1700 12:13:15.492024
1701 12:13:15.492493 Set Vref, RX VrefLevel [Byte0]: 52
1702 12:13:15.495139 [Byte1]: 52
1703 12:13:15.499567
1704 12:13:15.500035 Set Vref, RX VrefLevel [Byte0]: 53
1705 12:13:15.506211 [Byte1]: 53
1706 12:13:15.506866
1707 12:13:15.509131 Set Vref, RX VrefLevel [Byte0]: 54
1708 12:13:15.512855 [Byte1]: 54
1709 12:13:15.513485
1710 12:13:15.516095 Set Vref, RX VrefLevel [Byte0]: 55
1711 12:13:15.519242 [Byte1]: 55
1712 12:13:15.519712
1713 12:13:15.522753 Set Vref, RX VrefLevel [Byte0]: 56
1714 12:13:15.526116 [Byte1]: 56
1715 12:13:15.530028
1716 12:13:15.530595 Set Vref, RX VrefLevel [Byte0]: 57
1717 12:13:15.533328 [Byte1]: 57
1718 12:13:15.537637
1719 12:13:15.538248 Set Vref, RX VrefLevel [Byte0]: 58
1720 12:13:15.541252 [Byte1]: 58
1721 12:13:15.545219
1722 12:13:15.545766 Set Vref, RX VrefLevel [Byte0]: 59
1723 12:13:15.548661 [Byte1]: 59
1724 12:13:15.552983
1725 12:13:15.553451 Set Vref, RX VrefLevel [Byte0]: 60
1726 12:13:15.556192 [Byte1]: 60
1727 12:13:15.560707
1728 12:13:15.561286 Set Vref, RX VrefLevel [Byte0]: 61
1729 12:13:15.563473 [Byte1]: 61
1730 12:13:15.568096
1731 12:13:15.568683 Set Vref, RX VrefLevel [Byte0]: 62
1732 12:13:15.571255 [Byte1]: 62
1733 12:13:15.575433
1734 12:13:15.576065 Set Vref, RX VrefLevel [Byte0]: 63
1735 12:13:15.579021 [Byte1]: 63
1736 12:13:15.583327
1737 12:13:15.584046 Set Vref, RX VrefLevel [Byte0]: 64
1738 12:13:15.586074 [Byte1]: 64
1739 12:13:15.590688
1740 12:13:15.591158 Set Vref, RX VrefLevel [Byte0]: 65
1741 12:13:15.594325 [Byte1]: 65
1742 12:13:15.598471
1743 12:13:15.599068 Set Vref, RX VrefLevel [Byte0]: 66
1744 12:13:15.604753 [Byte1]: 66
1745 12:13:15.605332
1746 12:13:15.608350 Set Vref, RX VrefLevel [Byte0]: 67
1747 12:13:15.611367 [Byte1]: 67
1748 12:13:15.611837
1749 12:13:15.614676 Set Vref, RX VrefLevel [Byte0]: 68
1750 12:13:15.618214 [Byte1]: 68
1751 12:13:15.618759
1752 12:13:15.621192 Set Vref, RX VrefLevel [Byte0]: 69
1753 12:13:15.624692 [Byte1]: 69
1754 12:13:15.628423
1755 12:13:15.628972 Set Vref, RX VrefLevel [Byte0]: 70
1756 12:13:15.632148 [Byte1]: 70
1757 12:13:15.636122
1758 12:13:15.636594 Set Vref, RX VrefLevel [Byte0]: 71
1759 12:13:15.640038 [Byte1]: 71
1760 12:13:15.644073
1761 12:13:15.644637 Set Vref, RX VrefLevel [Byte0]: 72
1762 12:13:15.647230 [Byte1]: 72
1763 12:13:15.651972
1764 12:13:15.652540 Set Vref, RX VrefLevel [Byte0]: 73
1765 12:13:15.654544 [Byte1]: 73
1766 12:13:15.659031
1767 12:13:15.659511 Set Vref, RX VrefLevel [Byte0]: 74
1768 12:13:15.662151 [Byte1]: 74
1769 12:13:15.666628
1770 12:13:15.667094 Set Vref, RX VrefLevel [Byte0]: 75
1771 12:13:15.670177 [Byte1]: 75
1772 12:13:15.674394
1773 12:13:15.674869 Set Vref, RX VrefLevel [Byte0]: 76
1774 12:13:15.677557 [Byte1]: 76
1775 12:13:15.681974
1776 12:13:15.682548 Set Vref, RX VrefLevel [Byte0]: 77
1777 12:13:15.685543 [Byte1]: 77
1778 12:13:15.689529
1779 12:13:15.690170 Final RX Vref Byte 0 = 50 to rank0
1780 12:13:15.692915 Final RX Vref Byte 1 = 62 to rank0
1781 12:13:15.696289 Final RX Vref Byte 0 = 50 to rank1
1782 12:13:15.699524 Final RX Vref Byte 1 = 62 to rank1==
1783 12:13:15.703230 Dram Type= 6, Freq= 0, CH_1, rank 0
1784 12:13:15.710119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1785 12:13:15.710682 ==
1786 12:13:15.711060 DQS Delay:
1787 12:13:15.711409 DQS0 = 0, DQS1 = 0
1788 12:13:15.713318 DQM Delay:
1789 12:13:15.713886 DQM0 = 92, DQM1 = 82
1790 12:13:15.716564 DQ Delay:
1791 12:13:15.720033 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =88
1792 12:13:15.722722 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1793 12:13:15.723200 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =80
1794 12:13:15.729807 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =88
1795 12:13:15.730431
1796 12:13:15.730812
1797 12:13:15.736898 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1798 12:13:15.740104 CH1 RK0: MR19=606, MR18=2E4B
1799 12:13:15.746859 CH1_RK0: MR19=0x606, MR18=0x2E4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1800 12:13:15.747427
1801 12:13:15.749901 ----->DramcWriteLeveling(PI) begin...
1802 12:13:15.750518 ==
1803 12:13:15.753177 Dram Type= 6, Freq= 0, CH_1, rank 1
1804 12:13:15.756958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1805 12:13:15.757535 ==
1806 12:13:15.759813 Write leveling (Byte 0): 26 => 26
1807 12:13:15.763118 Write leveling (Byte 1): 31 => 31
1808 12:13:15.766511 DramcWriteLeveling(PI) end<-----
1809 12:13:15.767078
1810 12:13:15.767453 ==
1811 12:13:15.769830 Dram Type= 6, Freq= 0, CH_1, rank 1
1812 12:13:15.773044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1813 12:13:15.773611 ==
1814 12:13:15.776391 [Gating] SW mode calibration
1815 12:13:15.783286 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1816 12:13:15.790037 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1817 12:13:15.793933 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1818 12:13:15.796743 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1819 12:13:15.803230 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:13:15.806676 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:13:15.809716 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:13:15.816474 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 12:13:15.820254 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 12:13:15.822888 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 12:13:15.830231 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 12:13:15.833211 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 12:13:15.836599 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 12:13:15.839828 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 12:13:15.846605 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:13:15.850310 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:13:15.853581 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:13:15.860063 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:13:15.862942 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:13:15.866721 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1835 12:13:15.873206 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1836 12:13:15.876398 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 12:13:15.879807 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 12:13:15.886853 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 12:13:15.889736 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 12:13:15.893492 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 12:13:15.899848 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:13:15.902850 0 9 4 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
1843 12:13:15.906406 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 12:13:15.913202 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 12:13:15.916570 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 12:13:15.919743 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 12:13:15.926435 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1848 12:13:15.929844 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 12:13:15.933181 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 12:13:15.936540 0 10 4 | B1->B0 | 2b2b 2e2e | 0 0 | (1 0) (0 0)
1851 12:13:15.942884 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
1852 12:13:15.946469 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 12:13:15.949792 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 12:13:15.956735 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 12:13:15.960082 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 12:13:15.962948 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 12:13:15.969733 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 12:13:15.972908 0 11 4 | B1->B0 | 3131 3030 | 0 1 | (0 0) (0 0)
1859 12:13:15.976330 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 12:13:15.982811 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 12:13:15.986507 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 12:13:15.989584 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 12:13:15.996351 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 12:13:15.999446 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 12:13:16.002947 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 12:13:16.009412 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1867 12:13:16.012935 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 12:13:16.016769 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 12:13:16.023277 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 12:13:16.026470 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 12:13:16.029612 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 12:13:16.036594 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 12:13:16.039665 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 12:13:16.042853 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 12:13:16.046070 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 12:13:16.052961 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 12:13:16.056428 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 12:13:16.059911 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 12:13:16.066677 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 12:13:16.069850 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 12:13:16.073438 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 12:13:16.079890 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 12:13:16.082971 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 12:13:16.086810 Total UI for P1: 0, mck2ui 16
1885 12:13:16.089778 best dqsien dly found for B0: ( 0, 14, 6)
1886 12:13:16.092958 Total UI for P1: 0, mck2ui 16
1887 12:13:16.096563 best dqsien dly found for B1: ( 0, 14, 6)
1888 12:13:16.099964 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1889 12:13:16.103177 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1890 12:13:16.103653
1891 12:13:16.106406 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1892 12:13:16.110047 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1893 12:13:16.113622 [Gating] SW calibration Done
1894 12:13:16.114247 ==
1895 12:13:16.116592 Dram Type= 6, Freq= 0, CH_1, rank 1
1896 12:13:16.119972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1897 12:13:16.120544 ==
1898 12:13:16.123355 RX Vref Scan: 0
1899 12:13:16.123920
1900 12:13:16.126347 RX Vref 0 -> 0, step: 1
1901 12:13:16.126816
1902 12:13:16.127186 RX Delay -130 -> 252, step: 16
1903 12:13:16.133252 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1904 12:13:16.136564 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1905 12:13:16.139700 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1906 12:13:16.142999 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1907 12:13:16.146811 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1908 12:13:16.153325 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1909 12:13:16.156239 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1910 12:13:16.160220 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1911 12:13:16.162711 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1912 12:13:16.166239 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1913 12:13:16.173202 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1914 12:13:16.176105 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1915 12:13:16.179741 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1916 12:13:16.183034 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1917 12:13:16.186189 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1918 12:13:16.192924 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1919 12:13:16.193491 ==
1920 12:13:16.196589 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 12:13:16.199823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 12:13:16.200405 ==
1923 12:13:16.200918 DQS Delay:
1924 12:13:16.202992 DQS0 = 0, DQS1 = 0
1925 12:13:16.203483 DQM Delay:
1926 12:13:16.206405 DQM0 = 88, DQM1 = 81
1927 12:13:16.206879 DQ Delay:
1928 12:13:16.209682 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1929 12:13:16.213007 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1930 12:13:16.216408 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1931 12:13:16.219810 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1932 12:13:16.220461
1933 12:13:16.220845
1934 12:13:16.221198 ==
1935 12:13:16.223185 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 12:13:16.226424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 12:13:16.226900 ==
1938 12:13:16.229548
1939 12:13:16.230150
1940 12:13:16.230529 TX Vref Scan disable
1941 12:13:16.233075 == TX Byte 0 ==
1942 12:13:16.236372 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1943 12:13:16.239275 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1944 12:13:16.243216 == TX Byte 1 ==
1945 12:13:16.246120 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1946 12:13:16.249327 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1947 12:13:16.249804 ==
1948 12:13:16.253021 Dram Type= 6, Freq= 0, CH_1, rank 1
1949 12:13:16.259196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1950 12:13:16.259676 ==
1951 12:13:16.272147 TX Vref=22, minBit 8, minWin=27, winSum=450
1952 12:13:16.275394 TX Vref=24, minBit 13, minWin=27, winSum=454
1953 12:13:16.278642 TX Vref=26, minBit 13, minWin=27, winSum=455
1954 12:13:16.282068 TX Vref=28, minBit 8, minWin=28, winSum=459
1955 12:13:16.285449 TX Vref=30, minBit 8, minWin=28, winSum=459
1956 12:13:16.291698 TX Vref=32, minBit 8, minWin=28, winSum=459
1957 12:13:16.295470 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 28
1958 12:13:16.296175
1959 12:13:16.298880 Final TX Range 1 Vref 28
1960 12:13:16.299463
1961 12:13:16.299838 ==
1962 12:13:16.301538 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 12:13:16.305425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 12:13:16.308430 ==
1965 12:13:16.308903
1966 12:13:16.309275
1967 12:13:16.309621 TX Vref Scan disable
1968 12:13:16.312245 == TX Byte 0 ==
1969 12:13:16.315618 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1970 12:13:16.318553 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1971 12:13:16.322273 == TX Byte 1 ==
1972 12:13:16.325466 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1973 12:13:16.331775 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1974 12:13:16.332339
1975 12:13:16.332716 [DATLAT]
1976 12:13:16.333071 Freq=800, CH1 RK1
1977 12:13:16.333415
1978 12:13:16.335322 DATLAT Default: 0xa
1979 12:13:16.335906 0, 0xFFFF, sum = 0
1980 12:13:16.338641 1, 0xFFFF, sum = 0
1981 12:13:16.339231 2, 0xFFFF, sum = 0
1982 12:13:16.342064 3, 0xFFFF, sum = 0
1983 12:13:16.345269 4, 0xFFFF, sum = 0
1984 12:13:16.345860 5, 0xFFFF, sum = 0
1985 12:13:16.348933 6, 0xFFFF, sum = 0
1986 12:13:16.349517 7, 0xFFFF, sum = 0
1987 12:13:16.351874 8, 0xFFFF, sum = 0
1988 12:13:16.352359 9, 0x0, sum = 1
1989 12:13:16.352741 10, 0x0, sum = 2
1990 12:13:16.355053 11, 0x0, sum = 3
1991 12:13:16.355537 12, 0x0, sum = 4
1992 12:13:16.358749 best_step = 10
1993 12:13:16.359324
1994 12:13:16.359704 ==
1995 12:13:16.362118 Dram Type= 6, Freq= 0, CH_1, rank 1
1996 12:13:16.365296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1997 12:13:16.365865 ==
1998 12:13:16.368783 RX Vref Scan: 0
1999 12:13:16.369358
2000 12:13:16.369735 RX Vref 0 -> 0, step: 1
2001 12:13:16.370137
2002 12:13:16.372219 RX Delay -79 -> 252, step: 8
2003 12:13:16.378582 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2004 12:13:16.382229 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2005 12:13:16.385655 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2006 12:13:16.388497 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2007 12:13:16.391935 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2008 12:13:16.398873 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
2009 12:13:16.402335 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2010 12:13:16.405571 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2011 12:13:16.408611 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2012 12:13:16.411923 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2013 12:13:16.415681 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2014 12:13:16.422072 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2015 12:13:16.425911 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2016 12:13:16.428811 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2017 12:13:16.431981 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2018 12:13:16.438997 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2019 12:13:16.439580 ==
2020 12:13:16.442169 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 12:13:16.445711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 12:13:16.446334 ==
2023 12:13:16.446721 DQS Delay:
2024 12:13:16.449164 DQS0 = 0, DQS1 = 0
2025 12:13:16.449748 DQM Delay:
2026 12:13:16.452483 DQM0 = 90, DQM1 = 83
2027 12:13:16.453062 DQ Delay:
2028 12:13:16.455694 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
2029 12:13:16.458981 DQ4 =92, DQ5 =100, DQ6 =96, DQ7 =88
2030 12:13:16.462339 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2031 12:13:16.465652 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2032 12:13:16.466199
2033 12:13:16.466580
2034 12:13:16.472676 [DQSOSCAuto] RK1, (LSB)MR18= 0x3309, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
2035 12:13:16.475901 CH1 RK1: MR19=606, MR18=3309
2036 12:13:16.482158 CH1_RK1: MR19=0x606, MR18=0x3309, DQSOSC=396, MR23=63, INC=94, DEC=62
2037 12:13:16.486210 [RxdqsGatingPostProcess] freq 800
2038 12:13:16.492663 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2039 12:13:16.493263 Pre-setting of DQS Precalculation
2040 12:13:16.499197 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2041 12:13:16.505673 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2042 12:13:16.512512 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2043 12:13:16.513099
2044 12:13:16.513474
2045 12:13:16.515923 [Calibration Summary] 1600 Mbps
2046 12:13:16.518976 CH 0, Rank 0
2047 12:13:16.519451 SW Impedance : PASS
2048 12:13:16.522282 DUTY Scan : NO K
2049 12:13:16.522864 ZQ Calibration : PASS
2050 12:13:16.526011 Jitter Meter : NO K
2051 12:13:16.529092 CBT Training : PASS
2052 12:13:16.529670 Write leveling : PASS
2053 12:13:16.532434 RX DQS gating : PASS
2054 12:13:16.535853 RX DQ/DQS(RDDQC) : PASS
2055 12:13:16.536440 TX DQ/DQS : PASS
2056 12:13:16.539117 RX DATLAT : PASS
2057 12:13:16.542217 RX DQ/DQS(Engine): PASS
2058 12:13:16.542692 TX OE : NO K
2059 12:13:16.546103 All Pass.
2060 12:13:16.546677
2061 12:13:16.547057 CH 0, Rank 1
2062 12:13:16.549439 SW Impedance : PASS
2063 12:13:16.550055 DUTY Scan : NO K
2064 12:13:16.552668 ZQ Calibration : PASS
2065 12:13:16.555626 Jitter Meter : NO K
2066 12:13:16.556107 CBT Training : PASS
2067 12:13:16.559348 Write leveling : PASS
2068 12:13:16.559933 RX DQS gating : PASS
2069 12:13:16.562480 RX DQ/DQS(RDDQC) : PASS
2070 12:13:16.565789 TX DQ/DQS : PASS
2071 12:13:16.566291 RX DATLAT : PASS
2072 12:13:16.569361 RX DQ/DQS(Engine): PASS
2073 12:13:16.572222 TX OE : NO K
2074 12:13:16.572789 All Pass.
2075 12:13:16.573166
2076 12:13:16.573515 CH 1, Rank 0
2077 12:13:16.575446 SW Impedance : PASS
2078 12:13:16.579066 DUTY Scan : NO K
2079 12:13:16.579644 ZQ Calibration : PASS
2080 12:13:16.582123 Jitter Meter : NO K
2081 12:13:16.585631 CBT Training : PASS
2082 12:13:16.586202 Write leveling : PASS
2083 12:13:16.588794 RX DQS gating : PASS
2084 12:13:16.592436 RX DQ/DQS(RDDQC) : PASS
2085 12:13:16.592912 TX DQ/DQS : PASS
2086 12:13:16.595670 RX DATLAT : PASS
2087 12:13:16.599003 RX DQ/DQS(Engine): PASS
2088 12:13:16.599476 TX OE : NO K
2089 12:13:16.599861 All Pass.
2090 12:13:16.602785
2091 12:13:16.603463 CH 1, Rank 1
2092 12:13:16.605708 SW Impedance : PASS
2093 12:13:16.606220 DUTY Scan : NO K
2094 12:13:16.608915 ZQ Calibration : PASS
2095 12:13:16.609386 Jitter Meter : NO K
2096 12:13:16.612264 CBT Training : PASS
2097 12:13:16.615772 Write leveling : PASS
2098 12:13:16.616353 RX DQS gating : PASS
2099 12:13:16.618862 RX DQ/DQS(RDDQC) : PASS
2100 12:13:16.622896 TX DQ/DQS : PASS
2101 12:13:16.623470 RX DATLAT : PASS
2102 12:13:16.625870 RX DQ/DQS(Engine): PASS
2103 12:13:16.629039 TX OE : NO K
2104 12:13:16.629604 All Pass.
2105 12:13:16.630034
2106 12:13:16.632445 DramC Write-DBI off
2107 12:13:16.632921 PER_BANK_REFRESH: Hybrid Mode
2108 12:13:16.635850 TX_TRACKING: ON
2109 12:13:16.639458 [GetDramInforAfterCalByMRR] Vendor 6.
2110 12:13:16.642537 [GetDramInforAfterCalByMRR] Revision 606.
2111 12:13:16.645428 [GetDramInforAfterCalByMRR] Revision 2 0.
2112 12:13:16.645905 MR0 0x3b3b
2113 12:13:16.649208 MR8 0x5151
2114 12:13:16.652254 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 12:13:16.652829
2116 12:13:16.653207 MR0 0x3b3b
2117 12:13:16.653557 MR8 0x5151
2118 12:13:16.659041 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 12:13:16.659616
2120 12:13:16.665727 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2121 12:13:16.668934 [FAST_K] Save calibration result to emmc
2122 12:13:16.672387 [FAST_K] Save calibration result to emmc
2123 12:13:16.675585 dram_init: config_dvfs: 1
2124 12:13:16.678723 dramc_set_vcore_voltage set vcore to 662500
2125 12:13:16.682473 Read voltage for 1200, 2
2126 12:13:16.683042 Vio18 = 0
2127 12:13:16.685821 Vcore = 662500
2128 12:13:16.686452 Vdram = 0
2129 12:13:16.686835 Vddq = 0
2130 12:13:16.687321 Vmddr = 0
2131 12:13:16.692313 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2132 12:13:16.699173 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2133 12:13:16.699749 MEM_TYPE=3, freq_sel=15
2134 12:13:16.702863 sv_algorithm_assistance_LP4_1600
2135 12:13:16.705861 ============ PULL DRAM RESETB DOWN ============
2136 12:13:16.712192 ========== PULL DRAM RESETB DOWN end =========
2137 12:13:16.715979 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2138 12:13:16.719196 ===================================
2139 12:13:16.722315 LPDDR4 DRAM CONFIGURATION
2140 12:13:16.725706 ===================================
2141 12:13:16.726329 EX_ROW_EN[0] = 0x0
2142 12:13:16.728958 EX_ROW_EN[1] = 0x0
2143 12:13:16.729607 LP4Y_EN = 0x0
2144 12:13:16.732584 WORK_FSP = 0x0
2145 12:13:16.733075 WL = 0x4
2146 12:13:16.735820 RL = 0x4
2147 12:13:16.736286 BL = 0x2
2148 12:13:16.739159 RPST = 0x0
2149 12:13:16.739625 RD_PRE = 0x0
2150 12:13:16.742223 WR_PRE = 0x1
2151 12:13:16.742717 WR_PST = 0x0
2152 12:13:16.745896 DBI_WR = 0x0
2153 12:13:16.749220 DBI_RD = 0x0
2154 12:13:16.749683 OTF = 0x1
2155 12:13:16.752775 ===================================
2156 12:13:16.756310 ===================================
2157 12:13:16.756934 ANA top config
2158 12:13:16.759567 ===================================
2159 12:13:16.762792 DLL_ASYNC_EN = 0
2160 12:13:16.765703 ALL_SLAVE_EN = 0
2161 12:13:16.769552 NEW_RANK_MODE = 1
2162 12:13:16.770299 DLL_IDLE_MODE = 1
2163 12:13:16.772711 LP45_APHY_COMB_EN = 1
2164 12:13:16.775645 TX_ODT_DIS = 1
2165 12:13:16.779241 NEW_8X_MODE = 1
2166 12:13:16.782544 ===================================
2167 12:13:16.785871 ===================================
2168 12:13:16.789182 data_rate = 2400
2169 12:13:16.792619 CKR = 1
2170 12:13:16.793216 DQ_P2S_RATIO = 8
2171 12:13:16.795977 ===================================
2172 12:13:16.799308 CA_P2S_RATIO = 8
2173 12:13:16.802467 DQ_CA_OPEN = 0
2174 12:13:16.805680 DQ_SEMI_OPEN = 0
2175 12:13:16.809235 CA_SEMI_OPEN = 0
2176 12:13:16.809730 CA_FULL_RATE = 0
2177 12:13:16.812662 DQ_CKDIV4_EN = 0
2178 12:13:16.815906 CA_CKDIV4_EN = 0
2179 12:13:16.819080 CA_PREDIV_EN = 0
2180 12:13:16.822578 PH8_DLY = 17
2181 12:13:16.826132 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2182 12:13:16.826605 DQ_AAMCK_DIV = 4
2183 12:13:16.829410 CA_AAMCK_DIV = 4
2184 12:13:16.832560 CA_ADMCK_DIV = 4
2185 12:13:16.835834 DQ_TRACK_CA_EN = 0
2186 12:13:16.839505 CA_PICK = 1200
2187 12:13:16.842567 CA_MCKIO = 1200
2188 12:13:16.845928 MCKIO_SEMI = 0
2189 12:13:16.846437 PLL_FREQ = 2366
2190 12:13:16.849494 DQ_UI_PI_RATIO = 32
2191 12:13:16.853154 CA_UI_PI_RATIO = 0
2192 12:13:16.855934 ===================================
2193 12:13:16.859703 ===================================
2194 12:13:16.862875 memory_type:LPDDR4
2195 12:13:16.863346 GP_NUM : 10
2196 12:13:16.866056 SRAM_EN : 1
2197 12:13:16.869727 MD32_EN : 0
2198 12:13:16.872920 ===================================
2199 12:13:16.873494 [ANA_INIT] >>>>>>>>>>>>>>
2200 12:13:16.876227 <<<<<< [CONFIGURE PHASE]: ANA_TX
2201 12:13:16.879084 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2202 12:13:16.882599 ===================================
2203 12:13:16.886203 data_rate = 2400,PCW = 0X5b00
2204 12:13:16.889415 ===================================
2205 12:13:16.892885 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2206 12:13:16.899405 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2207 12:13:16.902682 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2208 12:13:16.909489 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2209 12:13:16.912560 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2210 12:13:16.916182 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2211 12:13:16.916756 [ANA_INIT] flow start
2212 12:13:16.919126 [ANA_INIT] PLL >>>>>>>>
2213 12:13:16.922863 [ANA_INIT] PLL <<<<<<<<
2214 12:13:16.923431 [ANA_INIT] MIDPI >>>>>>>>
2215 12:13:16.926177 [ANA_INIT] MIDPI <<<<<<<<
2216 12:13:16.929472 [ANA_INIT] DLL >>>>>>>>
2217 12:13:16.932670 [ANA_INIT] DLL <<<<<<<<
2218 12:13:16.933245 [ANA_INIT] flow end
2219 12:13:16.936408 ============ LP4 DIFF to SE enter ============
2220 12:13:16.942653 ============ LP4 DIFF to SE exit ============
2221 12:13:16.943199 [ANA_INIT] <<<<<<<<<<<<<
2222 12:13:16.945783 [Flow] Enable top DCM control >>>>>
2223 12:13:16.949689 [Flow] Enable top DCM control <<<<<
2224 12:13:16.952904 Enable DLL master slave shuffle
2225 12:13:16.959721 ==============================================================
2226 12:13:16.960351 Gating Mode config
2227 12:13:16.966042 ==============================================================
2228 12:13:16.969605 Config description:
2229 12:13:16.976372 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2230 12:13:16.982765 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2231 12:13:16.989595 SELPH_MODE 0: By rank 1: By Phase
2232 12:13:16.996330 ==============================================================
2233 12:13:16.996901 GAT_TRACK_EN = 1
2234 12:13:16.999741 RX_GATING_MODE = 2
2235 12:13:17.003172 RX_GATING_TRACK_MODE = 2
2236 12:13:17.006172 SELPH_MODE = 1
2237 12:13:17.009710 PICG_EARLY_EN = 1
2238 12:13:17.013024 VALID_LAT_VALUE = 1
2239 12:13:17.019490 ==============================================================
2240 12:13:17.022809 Enter into Gating configuration >>>>
2241 12:13:17.025905 Exit from Gating configuration <<<<
2242 12:13:17.029737 Enter into DVFS_PRE_config >>>>>
2243 12:13:17.040074 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2244 12:13:17.042879 Exit from DVFS_PRE_config <<<<<
2245 12:13:17.046145 Enter into PICG configuration >>>>
2246 12:13:17.049414 Exit from PICG configuration <<<<
2247 12:13:17.050029 [RX_INPUT] configuration >>>>>
2248 12:13:17.053168 [RX_INPUT] configuration <<<<<
2249 12:13:17.059386 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2250 12:13:17.063025 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2251 12:13:17.069736 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2252 12:13:17.076645 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2253 12:13:17.083094 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2254 12:13:17.089703 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2255 12:13:17.093201 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2256 12:13:17.096577 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2257 12:13:17.099657 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2258 12:13:17.106344 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2259 12:13:17.109805 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2260 12:13:17.113446 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2261 12:13:17.116668 ===================================
2262 12:13:17.119928 LPDDR4 DRAM CONFIGURATION
2263 12:13:17.123475 ===================================
2264 12:13:17.126574 EX_ROW_EN[0] = 0x0
2265 12:13:17.127052 EX_ROW_EN[1] = 0x0
2266 12:13:17.130160 LP4Y_EN = 0x0
2267 12:13:17.130732 WORK_FSP = 0x0
2268 12:13:17.133388 WL = 0x4
2269 12:13:17.133988 RL = 0x4
2270 12:13:17.136762 BL = 0x2
2271 12:13:17.137329 RPST = 0x0
2272 12:13:17.140285 RD_PRE = 0x0
2273 12:13:17.140871 WR_PRE = 0x1
2274 12:13:17.143148 WR_PST = 0x0
2275 12:13:17.143620 DBI_WR = 0x0
2276 12:13:17.146800 DBI_RD = 0x0
2277 12:13:17.147384 OTF = 0x1
2278 12:13:17.150324 ===================================
2279 12:13:17.153285 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2280 12:13:17.159841 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2281 12:13:17.163169 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2282 12:13:17.166473 ===================================
2283 12:13:17.170018 LPDDR4 DRAM CONFIGURATION
2284 12:13:17.173456 ===================================
2285 12:13:17.174058 EX_ROW_EN[0] = 0x10
2286 12:13:17.176767 EX_ROW_EN[1] = 0x0
2287 12:13:17.179987 LP4Y_EN = 0x0
2288 12:13:17.180564 WORK_FSP = 0x0
2289 12:13:17.183166 WL = 0x4
2290 12:13:17.183639 RL = 0x4
2291 12:13:17.186764 BL = 0x2
2292 12:13:17.187334 RPST = 0x0
2293 12:13:17.190055 RD_PRE = 0x0
2294 12:13:17.190647 WR_PRE = 0x1
2295 12:13:17.193195 WR_PST = 0x0
2296 12:13:17.193846 DBI_WR = 0x0
2297 12:13:17.196830 DBI_RD = 0x0
2298 12:13:17.197399 OTF = 0x1
2299 12:13:17.199861 ===================================
2300 12:13:17.206159 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2301 12:13:17.206647 ==
2302 12:13:17.209875 Dram Type= 6, Freq= 0, CH_0, rank 0
2303 12:13:17.213293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2304 12:13:17.213756 ==
2305 12:13:17.216478 [Duty_Offset_Calibration]
2306 12:13:17.219743 B0:2 B1:0 CA:1
2307 12:13:17.220200
2308 12:13:17.223040 [DutyScan_Calibration_Flow] k_type=0
2309 12:13:17.230682
2310 12:13:17.231100 ==CLK 0==
2311 12:13:17.233889 Final CLK duty delay cell = -4
2312 12:13:17.237124 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2313 12:13:17.240288 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2314 12:13:17.244072 [-4] AVG Duty = 4953%(X100)
2315 12:13:17.244495
2316 12:13:17.247076 CH0 CLK Duty spec in!! Max-Min= 156%
2317 12:13:17.250022 [DutyScan_Calibration_Flow] ====Done====
2318 12:13:17.250346
2319 12:13:17.253907 [DutyScan_Calibration_Flow] k_type=1
2320 12:13:17.269560
2321 12:13:17.270133 ==DQS 0 ==
2322 12:13:17.272703 Final DQS duty delay cell = 0
2323 12:13:17.275752 [0] MAX Duty = 5187%(X100), DQS PI = 30
2324 12:13:17.278965 [0] MIN Duty = 4938%(X100), DQS PI = 0
2325 12:13:17.279426 [0] AVG Duty = 5062%(X100)
2326 12:13:17.282634
2327 12:13:17.283133 ==DQS 1 ==
2328 12:13:17.285992 Final DQS duty delay cell = -4
2329 12:13:17.289263 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2330 12:13:17.292997 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2331 12:13:17.295993 [-4] AVG Duty = 5015%(X100)
2332 12:13:17.296550
2333 12:13:17.299345 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2334 12:13:17.299806
2335 12:13:17.303114 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2336 12:13:17.305746 [DutyScan_Calibration_Flow] ====Done====
2337 12:13:17.306240
2338 12:13:17.309134 [DutyScan_Calibration_Flow] k_type=3
2339 12:13:17.326135
2340 12:13:17.326691 ==DQM 0 ==
2341 12:13:17.329262 Final DQM duty delay cell = 0
2342 12:13:17.333217 [0] MAX Duty = 5062%(X100), DQS PI = 24
2343 12:13:17.336043 [0] MIN Duty = 4813%(X100), DQS PI = 0
2344 12:13:17.336504 [0] AVG Duty = 4937%(X100)
2345 12:13:17.339654
2346 12:13:17.340105 ==DQM 1 ==
2347 12:13:17.342848 Final DQM duty delay cell = 0
2348 12:13:17.346051 [0] MAX Duty = 5187%(X100), DQS PI = 48
2349 12:13:17.349410 [0] MIN Duty = 5000%(X100), DQS PI = 10
2350 12:13:17.350098 [0] AVG Duty = 5093%(X100)
2351 12:13:17.352912
2352 12:13:17.356048 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2353 12:13:17.356503
2354 12:13:17.359412 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2355 12:13:17.362642 [DutyScan_Calibration_Flow] ====Done====
2356 12:13:17.363115
2357 12:13:17.366065 [DutyScan_Calibration_Flow] k_type=2
2358 12:13:17.382029
2359 12:13:17.382614 ==DQ 0 ==
2360 12:13:17.385017 Final DQ duty delay cell = -4
2361 12:13:17.388684 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2362 12:13:17.391578 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2363 12:13:17.395289 [-4] AVG Duty = 4984%(X100)
2364 12:13:17.395865
2365 12:13:17.396238 ==DQ 1 ==
2366 12:13:17.398432 Final DQ duty delay cell = 0
2367 12:13:17.402043 [0] MAX Duty = 4938%(X100), DQS PI = 4
2368 12:13:17.405073 [0] MIN Duty = 4907%(X100), DQS PI = 0
2369 12:13:17.405652 [0] AVG Duty = 4922%(X100)
2370 12:13:17.406069
2371 12:13:17.408270 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2372 12:13:17.411639
2373 12:13:17.414938 CH0 DQ 1 Duty spec in!! Max-Min= 31%
2374 12:13:17.418543 [DutyScan_Calibration_Flow] ====Done====
2375 12:13:17.419125 ==
2376 12:13:17.421641 Dram Type= 6, Freq= 0, CH_1, rank 0
2377 12:13:17.425350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2378 12:13:17.425929 ==
2379 12:13:17.428144 [Duty_Offset_Calibration]
2380 12:13:17.428615 B0:0 B1:-1 CA:2
2381 12:13:17.428988
2382 12:13:17.432066 [DutyScan_Calibration_Flow] k_type=0
2383 12:13:17.442108
2384 12:13:17.442671 ==CLK 0==
2385 12:13:17.445630 Final CLK duty delay cell = 0
2386 12:13:17.448911 [0] MAX Duty = 5156%(X100), DQS PI = 16
2387 12:13:17.451939 [0] MIN Duty = 4938%(X100), DQS PI = 44
2388 12:13:17.452519 [0] AVG Duty = 5047%(X100)
2389 12:13:17.455221
2390 12:13:17.455798 CH1 CLK Duty spec in!! Max-Min= 218%
2391 12:13:17.461920 [DutyScan_Calibration_Flow] ====Done====
2392 12:13:17.462542
2393 12:13:17.465152 [DutyScan_Calibration_Flow] k_type=1
2394 12:13:17.481641
2395 12:13:17.482266 ==DQS 0 ==
2396 12:13:17.484767 Final DQS duty delay cell = 0
2397 12:13:17.488324 [0] MAX Duty = 5093%(X100), DQS PI = 24
2398 12:13:17.491140 [0] MIN Duty = 4969%(X100), DQS PI = 0
2399 12:13:17.491616 [0] AVG Duty = 5031%(X100)
2400 12:13:17.494549
2401 12:13:17.495130 ==DQS 1 ==
2402 12:13:17.497910 Final DQS duty delay cell = 0
2403 12:13:17.501355 [0] MAX Duty = 5156%(X100), DQS PI = 0
2404 12:13:17.505064 [0] MIN Duty = 4844%(X100), DQS PI = 34
2405 12:13:17.505645 [0] AVG Duty = 5000%(X100)
2406 12:13:17.507631
2407 12:13:17.511485 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2408 12:13:17.511999
2409 12:13:17.514773 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2410 12:13:17.518026 [DutyScan_Calibration_Flow] ====Done====
2411 12:13:17.518509
2412 12:13:17.521458 [DutyScan_Calibration_Flow] k_type=3
2413 12:13:17.538584
2414 12:13:17.539177 ==DQM 0 ==
2415 12:13:17.541532 Final DQM duty delay cell = 4
2416 12:13:17.545098 [4] MAX Duty = 5093%(X100), DQS PI = 6
2417 12:13:17.548310 [4] MIN Duty = 4938%(X100), DQS PI = 30
2418 12:13:17.548790 [4] AVG Duty = 5015%(X100)
2419 12:13:17.552000
2420 12:13:17.552580 ==DQM 1 ==
2421 12:13:17.554928 Final DQM duty delay cell = 0
2422 12:13:17.558289 [0] MAX Duty = 5249%(X100), DQS PI = 0
2423 12:13:17.561492 [0] MIN Duty = 4875%(X100), DQS PI = 36
2424 12:13:17.562005 [0] AVG Duty = 5062%(X100)
2425 12:13:17.565115
2426 12:13:17.568401 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2427 12:13:17.568876
2428 12:13:17.571878 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2429 12:13:17.575016 [DutyScan_Calibration_Flow] ====Done====
2430 12:13:17.575491
2431 12:13:17.578298 [DutyScan_Calibration_Flow] k_type=2
2432 12:13:17.595240
2433 12:13:17.595817 ==DQ 0 ==
2434 12:13:17.598886 Final DQ duty delay cell = 0
2435 12:13:17.601722 [0] MAX Duty = 5062%(X100), DQS PI = 20
2436 12:13:17.605136 [0] MIN Duty = 4938%(X100), DQS PI = 44
2437 12:13:17.605710 [0] AVG Duty = 5000%(X100)
2438 12:13:17.608113
2439 12:13:17.608664 ==DQ 1 ==
2440 12:13:17.611345 Final DQ duty delay cell = 0
2441 12:13:17.615204 [0] MAX Duty = 5031%(X100), DQS PI = 2
2442 12:13:17.618318 [0] MIN Duty = 4813%(X100), DQS PI = 34
2443 12:13:17.618795 [0] AVG Duty = 4922%(X100)
2444 12:13:17.619172
2445 12:13:17.622052 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2446 12:13:17.622611
2447 12:13:17.625195 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2448 12:13:17.631747 [DutyScan_Calibration_Flow] ====Done====
2449 12:13:17.634900 nWR fixed to 30
2450 12:13:17.635378 [ModeRegInit_LP4] CH0 RK0
2451 12:13:17.638444 [ModeRegInit_LP4] CH0 RK1
2452 12:13:17.641370 [ModeRegInit_LP4] CH1 RK0
2453 12:13:17.641842 [ModeRegInit_LP4] CH1 RK1
2454 12:13:17.644807 match AC timing 7
2455 12:13:17.648139 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2456 12:13:17.651607 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2457 12:13:17.658463 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2458 12:13:17.661466 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2459 12:13:17.668199 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2460 12:13:17.668770 ==
2461 12:13:17.671761 Dram Type= 6, Freq= 0, CH_0, rank 0
2462 12:13:17.674796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2463 12:13:17.675273 ==
2464 12:13:17.681488 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2465 12:13:17.684814 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2466 12:13:17.695045 [CA 0] Center 38 (7~69) winsize 63
2467 12:13:17.697989 [CA 1] Center 38 (8~69) winsize 62
2468 12:13:17.701664 [CA 2] Center 35 (5~66) winsize 62
2469 12:13:17.704689 [CA 3] Center 35 (4~66) winsize 63
2470 12:13:17.708219 [CA 4] Center 34 (4~65) winsize 62
2471 12:13:17.711222 [CA 5] Center 33 (3~64) winsize 62
2472 12:13:17.711697
2473 12:13:17.714678 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2474 12:13:17.715293
2475 12:13:17.718118 [CATrainingPosCal] consider 1 rank data
2476 12:13:17.721410 u2DelayCellTimex100 = 270/100 ps
2477 12:13:17.724891 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2478 12:13:17.728050 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2479 12:13:17.734810 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2480 12:13:17.738305 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2481 12:13:17.741373 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2482 12:13:17.744812 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2483 12:13:17.745380
2484 12:13:17.748186 CA PerBit enable=1, Macro0, CA PI delay=33
2485 12:13:17.748755
2486 12:13:17.751748 [CBTSetCACLKResult] CA Dly = 33
2487 12:13:17.752319 CS Dly: 6 (0~37)
2488 12:13:17.752698 ==
2489 12:13:17.754790 Dram Type= 6, Freq= 0, CH_0, rank 1
2490 12:13:17.761661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2491 12:13:17.762327 ==
2492 12:13:17.764878 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2493 12:13:17.771362 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2494 12:13:17.780362 [CA 0] Center 39 (8~70) winsize 63
2495 12:13:17.783854 [CA 1] Center 38 (8~69) winsize 62
2496 12:13:17.787337 [CA 2] Center 35 (5~66) winsize 62
2497 12:13:17.790252 [CA 3] Center 35 (5~66) winsize 62
2498 12:13:17.793493 [CA 4] Center 34 (4~65) winsize 62
2499 12:13:17.796847 [CA 5] Center 34 (4~64) winsize 61
2500 12:13:17.797352
2501 12:13:17.800634 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2502 12:13:17.801210
2503 12:13:17.803538 [CATrainingPosCal] consider 2 rank data
2504 12:13:17.807191 u2DelayCellTimex100 = 270/100 ps
2505 12:13:17.810256 CA0 delay=38 (8~69),Diff = 4 PI (19 cell)
2506 12:13:17.817058 CA1 delay=38 (8~69),Diff = 4 PI (19 cell)
2507 12:13:17.820247 CA2 delay=35 (5~66),Diff = 1 PI (4 cell)
2508 12:13:17.823361 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2509 12:13:17.826599 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2510 12:13:17.829902 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2511 12:13:17.830464
2512 12:13:17.833470 CA PerBit enable=1, Macro0, CA PI delay=34
2513 12:13:17.834074
2514 12:13:17.837147 [CBTSetCACLKResult] CA Dly = 34
2515 12:13:17.837616 CS Dly: 7 (0~39)
2516 12:13:17.839907
2517 12:13:17.843673 ----->DramcWriteLeveling(PI) begin...
2518 12:13:17.844150 ==
2519 12:13:17.847041 Dram Type= 6, Freq= 0, CH_0, rank 0
2520 12:13:17.850646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 12:13:17.851226 ==
2522 12:13:17.853787 Write leveling (Byte 0): 33 => 33
2523 12:13:17.856967 Write leveling (Byte 1): 33 => 33
2524 12:13:17.860405 DramcWriteLeveling(PI) end<-----
2525 12:13:17.860988
2526 12:13:17.861364 ==
2527 12:13:17.863718 Dram Type= 6, Freq= 0, CH_0, rank 0
2528 12:13:17.866659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2529 12:13:17.867156 ==
2530 12:13:17.870542 [Gating] SW mode calibration
2531 12:13:17.876935 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2532 12:13:17.883683 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2533 12:13:17.886899 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2534 12:13:17.890463 0 15 4 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
2535 12:13:17.893761 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 12:13:17.900481 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2537 12:13:17.903910 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 12:13:17.906930 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 12:13:17.913373 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2540 12:13:17.917275 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
2541 12:13:17.920308 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
2542 12:13:17.926648 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 12:13:17.930473 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 12:13:17.933449 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2545 12:13:17.940380 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 12:13:17.943715 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 12:13:17.946959 1 0 24 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2548 12:13:17.954054 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2549 12:13:17.957273 1 1 0 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)
2550 12:13:17.960349 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 12:13:17.963962 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 12:13:17.970496 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 12:13:17.974089 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 12:13:17.977024 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 12:13:17.983503 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 12:13:17.987255 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2557 12:13:17.990633 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2558 12:13:17.997515 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 12:13:18.000327 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 12:13:18.003927 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 12:13:18.010363 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 12:13:18.013639 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 12:13:18.017047 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 12:13:18.024149 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 12:13:18.027307 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 12:13:18.030835 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 12:13:18.037094 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 12:13:18.040339 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 12:13:18.043958 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 12:13:18.050533 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 12:13:18.054096 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 12:13:18.057247 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2573 12:13:18.060466 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2574 12:13:18.064151 Total UI for P1: 0, mck2ui 16
2575 12:13:18.067141 best dqsien dly found for B0: ( 1, 3, 28)
2576 12:13:18.074092 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2577 12:13:18.074679 Total UI for P1: 0, mck2ui 16
2578 12:13:18.081051 best dqsien dly found for B1: ( 1, 4, 0)
2579 12:13:18.083902 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2580 12:13:18.087419 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2581 12:13:18.087997
2582 12:13:18.090856 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2583 12:13:18.093793 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2584 12:13:18.097679 [Gating] SW calibration Done
2585 12:13:18.098302 ==
2586 12:13:18.100673 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 12:13:18.104120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 12:13:18.104603 ==
2589 12:13:18.107487 RX Vref Scan: 0
2590 12:13:18.108056
2591 12:13:18.108429 RX Vref 0 -> 0, step: 1
2592 12:13:18.108775
2593 12:13:18.110506 RX Delay -40 -> 252, step: 8
2594 12:13:18.113881 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
2595 12:13:18.121025 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2596 12:13:18.124161 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2597 12:13:18.127579 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2598 12:13:18.131103 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2599 12:13:18.134230 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2600 12:13:18.140489 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2601 12:13:18.143942 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2602 12:13:18.147111 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2603 12:13:18.151053 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2604 12:13:18.154053 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2605 12:13:18.157522 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2606 12:13:18.164402 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2607 12:13:18.167252 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2608 12:13:18.170902 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2609 12:13:18.174101 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2610 12:13:18.174668 ==
2611 12:13:18.177634 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 12:13:18.184195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 12:13:18.184773 ==
2614 12:13:18.185150 DQS Delay:
2615 12:13:18.187551 DQS0 = 0, DQS1 = 0
2616 12:13:18.188133 DQM Delay:
2617 12:13:18.188510 DQM0 = 122, DQM1 = 110
2618 12:13:18.190821 DQ Delay:
2619 12:13:18.194210 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2620 12:13:18.197535 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2621 12:13:18.200995 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2622 12:13:18.204178 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2623 12:13:18.204748
2624 12:13:18.205119
2625 12:13:18.205467 ==
2626 12:13:18.207668 Dram Type= 6, Freq= 0, CH_0, rank 0
2627 12:13:18.210684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2628 12:13:18.213720 ==
2629 12:13:18.214245
2630 12:13:18.214619
2631 12:13:18.214968 TX Vref Scan disable
2632 12:13:18.217458 == TX Byte 0 ==
2633 12:13:18.220741 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2634 12:13:18.223994 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2635 12:13:18.227751 == TX Byte 1 ==
2636 12:13:18.230854 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2637 12:13:18.234242 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2638 12:13:18.234818 ==
2639 12:13:18.237617 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 12:13:18.243926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 12:13:18.244504 ==
2642 12:13:18.254850 TX Vref=22, minBit 3, minWin=24, winSum=401
2643 12:13:18.257856 TX Vref=24, minBit 1, minWin=24, winSum=409
2644 12:13:18.261406 TX Vref=26, minBit 0, minWin=25, winSum=414
2645 12:13:18.264460 TX Vref=28, minBit 3, minWin=25, winSum=416
2646 12:13:18.267819 TX Vref=30, minBit 3, minWin=25, winSum=416
2647 12:13:18.271132 TX Vref=32, minBit 5, minWin=25, winSum=416
2648 12:13:18.278132 [TxChooseVref] Worse bit 3, Min win 25, Win sum 416, Final Vref 28
2649 12:13:18.278704
2650 12:13:18.281211 Final TX Range 1 Vref 28
2651 12:13:18.281782
2652 12:13:18.282222 ==
2653 12:13:18.284822 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 12:13:18.288140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 12:13:18.288720 ==
2656 12:13:18.289099
2657 12:13:18.291253
2658 12:13:18.291821 TX Vref Scan disable
2659 12:13:18.294192 == TX Byte 0 ==
2660 12:13:18.298107 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2661 12:13:18.301141 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2662 12:13:18.304309 == TX Byte 1 ==
2663 12:13:18.307884 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2664 12:13:18.311197 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2665 12:13:18.311696
2666 12:13:18.314331 [DATLAT]
2667 12:13:18.314802 Freq=1200, CH0 RK0
2668 12:13:18.315176
2669 12:13:18.317700 DATLAT Default: 0xd
2670 12:13:18.318309 0, 0xFFFF, sum = 0
2671 12:13:18.321416 1, 0xFFFF, sum = 0
2672 12:13:18.322045 2, 0xFFFF, sum = 0
2673 12:13:18.324672 3, 0xFFFF, sum = 0
2674 12:13:18.325254 4, 0xFFFF, sum = 0
2675 12:13:18.327768 5, 0xFFFF, sum = 0
2676 12:13:18.328346 6, 0xFFFF, sum = 0
2677 12:13:18.331141 7, 0xFFFF, sum = 0
2678 12:13:18.331619 8, 0xFFFF, sum = 0
2679 12:13:18.334243 9, 0xFFFF, sum = 0
2680 12:13:18.337749 10, 0xFFFF, sum = 0
2681 12:13:18.338355 11, 0xFFFF, sum = 0
2682 12:13:18.341316 12, 0x0, sum = 1
2683 12:13:18.341891 13, 0x0, sum = 2
2684 12:13:18.342313 14, 0x0, sum = 3
2685 12:13:18.344476 15, 0x0, sum = 4
2686 12:13:18.345075 best_step = 13
2687 12:13:18.345454
2688 12:13:18.345799 ==
2689 12:13:18.347694 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 12:13:18.354124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 12:13:18.354681 ==
2692 12:13:18.355055 RX Vref Scan: 1
2693 12:13:18.355398
2694 12:13:18.357649 Set Vref Range= 32 -> 127
2695 12:13:18.358153
2696 12:13:18.361339 RX Vref 32 -> 127, step: 1
2697 12:13:18.361909
2698 12:13:18.364300 RX Delay -13 -> 252, step: 4
2699 12:13:18.364771
2700 12:13:18.367558 Set Vref, RX VrefLevel [Byte0]: 32
2701 12:13:18.371024 [Byte1]: 32
2702 12:13:18.371593
2703 12:13:18.374798 Set Vref, RX VrefLevel [Byte0]: 33
2704 12:13:18.377577 [Byte1]: 33
2705 12:13:18.378097
2706 12:13:18.381502 Set Vref, RX VrefLevel [Byte0]: 34
2707 12:13:18.384858 [Byte1]: 34
2708 12:13:18.388282
2709 12:13:18.388843 Set Vref, RX VrefLevel [Byte0]: 35
2710 12:13:18.391970 [Byte1]: 35
2711 12:13:18.396347
2712 12:13:18.396963 Set Vref, RX VrefLevel [Byte0]: 36
2713 12:13:18.400177 [Byte1]: 36
2714 12:13:18.404295
2715 12:13:18.404859 Set Vref, RX VrefLevel [Byte0]: 37
2716 12:13:18.407519 [Byte1]: 37
2717 12:13:18.412106
2718 12:13:18.412578 Set Vref, RX VrefLevel [Byte0]: 38
2719 12:13:18.415440 [Byte1]: 38
2720 12:13:18.420124
2721 12:13:18.420689 Set Vref, RX VrefLevel [Byte0]: 39
2722 12:13:18.422921 [Byte1]: 39
2723 12:13:18.428100
2724 12:13:18.428664 Set Vref, RX VrefLevel [Byte0]: 40
2725 12:13:18.430797 [Byte1]: 40
2726 12:13:18.435636
2727 12:13:18.436202 Set Vref, RX VrefLevel [Byte0]: 41
2728 12:13:18.439284 [Byte1]: 41
2729 12:13:18.443822
2730 12:13:18.444388 Set Vref, RX VrefLevel [Byte0]: 42
2731 12:13:18.446833 [Byte1]: 42
2732 12:13:18.451755
2733 12:13:18.452371 Set Vref, RX VrefLevel [Byte0]: 43
2734 12:13:18.454952 [Byte1]: 43
2735 12:13:18.459381
2736 12:13:18.459951 Set Vref, RX VrefLevel [Byte0]: 44
2737 12:13:18.462563 [Byte1]: 44
2738 12:13:18.467152
2739 12:13:18.467757 Set Vref, RX VrefLevel [Byte0]: 45
2740 12:13:18.470792 [Byte1]: 45
2741 12:13:18.475478
2742 12:13:18.476048 Set Vref, RX VrefLevel [Byte0]: 46
2743 12:13:18.478763 [Byte1]: 46
2744 12:13:18.482997
2745 12:13:18.483570 Set Vref, RX VrefLevel [Byte0]: 47
2746 12:13:18.486262 [Byte1]: 47
2747 12:13:18.490881
2748 12:13:18.491449 Set Vref, RX VrefLevel [Byte0]: 48
2749 12:13:18.494414 [Byte1]: 48
2750 12:13:18.498864
2751 12:13:18.499426 Set Vref, RX VrefLevel [Byte0]: 49
2752 12:13:18.501997 [Byte1]: 49
2753 12:13:18.506798
2754 12:13:18.509886 Set Vref, RX VrefLevel [Byte0]: 50
2755 12:13:18.510435 [Byte1]: 50
2756 12:13:18.514341
2757 12:13:18.514828 Set Vref, RX VrefLevel [Byte0]: 51
2758 12:13:18.517928 [Byte1]: 51
2759 12:13:18.522712
2760 12:13:18.523181 Set Vref, RX VrefLevel [Byte0]: 52
2761 12:13:18.525904 [Byte1]: 52
2762 12:13:18.530418
2763 12:13:18.531021 Set Vref, RX VrefLevel [Byte0]: 53
2764 12:13:18.533626 [Byte1]: 53
2765 12:13:18.538365
2766 12:13:18.538832 Set Vref, RX VrefLevel [Byte0]: 54
2767 12:13:18.541444 [Byte1]: 54
2768 12:13:18.545788
2769 12:13:18.546052 Set Vref, RX VrefLevel [Byte0]: 55
2770 12:13:18.549378 [Byte1]: 55
2771 12:13:18.553989
2772 12:13:18.554244 Set Vref, RX VrefLevel [Byte0]: 56
2773 12:13:18.557184 [Byte1]: 56
2774 12:13:18.561753
2775 12:13:18.561894 Set Vref, RX VrefLevel [Byte0]: 57
2776 12:13:18.564947 [Byte1]: 57
2777 12:13:18.569340
2778 12:13:18.569463 Set Vref, RX VrefLevel [Byte0]: 58
2779 12:13:18.572579 [Byte1]: 58
2780 12:13:18.577356
2781 12:13:18.577459 Set Vref, RX VrefLevel [Byte0]: 59
2782 12:13:18.580526 [Byte1]: 59
2783 12:13:18.585376
2784 12:13:18.585533 Set Vref, RX VrefLevel [Byte0]: 60
2785 12:13:18.588487 [Byte1]: 60
2786 12:13:18.592918
2787 12:13:18.593019 Set Vref, RX VrefLevel [Byte0]: 61
2788 12:13:18.596165 [Byte1]: 61
2789 12:13:18.600852
2790 12:13:18.600945 Set Vref, RX VrefLevel [Byte0]: 62
2791 12:13:18.604173 [Byte1]: 62
2792 12:13:18.608807
2793 12:13:18.608921 Set Vref, RX VrefLevel [Byte0]: 63
2794 12:13:18.612364 [Byte1]: 63
2795 12:13:18.616636
2796 12:13:18.616721 Set Vref, RX VrefLevel [Byte0]: 64
2797 12:13:18.620032 [Byte1]: 64
2798 12:13:18.624878
2799 12:13:18.625041 Set Vref, RX VrefLevel [Byte0]: 65
2800 12:13:18.628190 [Byte1]: 65
2801 12:13:18.632781
2802 12:13:18.632963 Set Vref, RX VrefLevel [Byte0]: 66
2803 12:13:18.635728 [Byte1]: 66
2804 12:13:18.640829
2805 12:13:18.641021 Set Vref, RX VrefLevel [Byte0]: 67
2806 12:13:18.643803 [Byte1]: 67
2807 12:13:18.648313
2808 12:13:18.648514 Set Vref, RX VrefLevel [Byte0]: 68
2809 12:13:18.652041 [Byte1]: 68
2810 12:13:18.656502
2811 12:13:18.656742 Set Vref, RX VrefLevel [Byte0]: 69
2812 12:13:18.659849 [Byte1]: 69
2813 12:13:18.664046
2814 12:13:18.664287 Set Vref, RX VrefLevel [Byte0]: 70
2815 12:13:18.667386 [Byte1]: 70
2816 12:13:18.672003
2817 12:13:18.672335 Set Vref, RX VrefLevel [Byte0]: 71
2818 12:13:18.675445 [Byte1]: 71
2819 12:13:18.680352
2820 12:13:18.680862 Final RX Vref Byte 0 = 57 to rank0
2821 12:13:18.683516 Final RX Vref Byte 1 = 51 to rank0
2822 12:13:18.686809 Final RX Vref Byte 0 = 57 to rank1
2823 12:13:18.690643 Final RX Vref Byte 1 = 51 to rank1==
2824 12:13:18.693739 Dram Type= 6, Freq= 0, CH_0, rank 0
2825 12:13:18.700494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 12:13:18.701085 ==
2827 12:13:18.701462 DQS Delay:
2828 12:13:18.701814 DQS0 = 0, DQS1 = 0
2829 12:13:18.703917 DQM Delay:
2830 12:13:18.704518 DQM0 = 122, DQM1 = 109
2831 12:13:18.707116 DQ Delay:
2832 12:13:18.710325 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =118
2833 12:13:18.714056 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2834 12:13:18.717137 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =108
2835 12:13:18.720362 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2836 12:13:18.720839
2837 12:13:18.721212
2838 12:13:18.727245 [DQSOSCAuto] RK0, (LSB)MR18= 0x804, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
2839 12:13:18.730397 CH0 RK0: MR19=404, MR18=804
2840 12:13:18.737087 CH0_RK0: MR19=0x404, MR18=0x804, DQSOSC=406, MR23=63, INC=39, DEC=26
2841 12:13:18.737686
2842 12:13:18.740280 ----->DramcWriteLeveling(PI) begin...
2843 12:13:18.740758 ==
2844 12:13:18.744095 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 12:13:18.747255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 12:13:18.747739 ==
2847 12:13:18.750518 Write leveling (Byte 0): 34 => 34
2848 12:13:18.753933 Write leveling (Byte 1): 28 => 28
2849 12:13:18.757259 DramcWriteLeveling(PI) end<-----
2850 12:13:18.757835
2851 12:13:18.758254 ==
2852 12:13:18.760460 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 12:13:18.763660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 12:13:18.766776 ==
2855 12:13:18.767248 [Gating] SW mode calibration
2856 12:13:18.773792 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2857 12:13:18.780761 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2858 12:13:18.783664 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2859 12:13:18.790734 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 12:13:18.794319 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 12:13:18.797411 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 12:13:18.803659 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 12:13:18.807178 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 12:13:18.810651 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 12:13:18.816953 0 15 28 | B1->B0 | 3232 2d2d | 0 0 | (1 0) (1 0)
2866 12:13:18.820538 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 12:13:18.823906 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 12:13:18.830323 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 12:13:18.833732 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 12:13:18.837573 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 12:13:18.840327 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 12:13:18.847247 1 0 24 | B1->B0 | 2525 2a2a | 0 0 | (0 0) (0 0)
2873 12:13:18.850645 1 0 28 | B1->B0 | 3838 4342 | 0 1 | (0 0) (0 0)
2874 12:13:18.854214 1 1 0 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
2875 12:13:18.860926 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 12:13:18.864252 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 12:13:18.867152 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 12:13:18.874088 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 12:13:18.877271 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 12:13:18.881107 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 12:13:18.887637 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 12:13:18.890833 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 12:13:18.894204 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 12:13:18.901049 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 12:13:18.904125 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 12:13:18.907270 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 12:13:18.914270 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 12:13:18.917054 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 12:13:18.920876 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 12:13:18.923911 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 12:13:18.930812 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 12:13:18.934418 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 12:13:18.937282 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 12:13:18.944327 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 12:13:18.947151 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 12:13:18.950650 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 12:13:18.957170 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2898 12:13:18.961108 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2899 12:13:18.964196 Total UI for P1: 0, mck2ui 16
2900 12:13:18.967443 best dqsien dly found for B0: ( 1, 3, 28)
2901 12:13:18.971153 Total UI for P1: 0, mck2ui 16
2902 12:13:18.973896 best dqsien dly found for B1: ( 1, 3, 30)
2903 12:13:18.977154 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2904 12:13:18.981041 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2905 12:13:18.981655
2906 12:13:18.984085 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2907 12:13:18.987138 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2908 12:13:18.990847 [Gating] SW calibration Done
2909 12:13:18.991419 ==
2910 12:13:18.994203 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 12:13:18.997373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 12:13:18.997968 ==
2913 12:13:19.000905 RX Vref Scan: 0
2914 12:13:19.001475
2915 12:13:19.004269 RX Vref 0 -> 0, step: 1
2916 12:13:19.004842
2917 12:13:19.005217 RX Delay -40 -> 252, step: 8
2918 12:13:19.011121 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2919 12:13:19.014195 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2920 12:13:19.017201 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2921 12:13:19.020820 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2922 12:13:19.024198 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2923 12:13:19.030927 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2924 12:13:19.034248 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2925 12:13:19.037646 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2926 12:13:19.040977 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2927 12:13:19.044262 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2928 12:13:19.050911 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2929 12:13:19.054262 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2930 12:13:19.057306 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2931 12:13:19.060835 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2932 12:13:19.064400 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2933 12:13:19.071059 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2934 12:13:19.071630 ==
2935 12:13:19.074691 Dram Type= 6, Freq= 0, CH_0, rank 1
2936 12:13:19.077888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2937 12:13:19.078402 ==
2938 12:13:19.078777 DQS Delay:
2939 12:13:19.081146 DQS0 = 0, DQS1 = 0
2940 12:13:19.081705 DQM Delay:
2941 12:13:19.084734 DQM0 = 120, DQM1 = 109
2942 12:13:19.085333 DQ Delay:
2943 12:13:19.087962 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2944 12:13:19.091142 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2945 12:13:19.094526 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2946 12:13:19.097904 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2947 12:13:19.098521
2948 12:13:19.098889
2949 12:13:19.099230 ==
2950 12:13:19.101075 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 12:13:19.107848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 12:13:19.108423 ==
2953 12:13:19.108865
2954 12:13:19.109379
2955 12:13:19.109731 TX Vref Scan disable
2956 12:13:19.111529 == TX Byte 0 ==
2957 12:13:19.114887 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2958 12:13:19.117824 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2959 12:13:19.121431 == TX Byte 1 ==
2960 12:13:19.124577 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2961 12:13:19.128337 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2962 12:13:19.131053 ==
2963 12:13:19.134723 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 12:13:19.137887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 12:13:19.138402 ==
2966 12:13:19.149597 TX Vref=22, minBit 1, minWin=24, winSum=404
2967 12:13:19.152854 TX Vref=24, minBit 4, minWin=24, winSum=409
2968 12:13:19.156577 TX Vref=26, minBit 1, minWin=24, winSum=412
2969 12:13:19.159490 TX Vref=28, minBit 1, minWin=24, winSum=416
2970 12:13:19.163040 TX Vref=30, minBit 5, minWin=25, winSum=420
2971 12:13:19.166427 TX Vref=32, minBit 0, minWin=25, winSum=418
2972 12:13:19.173344 [TxChooseVref] Worse bit 5, Min win 25, Win sum 420, Final Vref 30
2973 12:13:19.173910
2974 12:13:19.176738 Final TX Range 1 Vref 30
2975 12:13:19.177375
2976 12:13:19.177755 ==
2977 12:13:19.179457 Dram Type= 6, Freq= 0, CH_0, rank 1
2978 12:13:19.183164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2979 12:13:19.183769 ==
2980 12:13:19.184149
2981 12:13:19.186707
2982 12:13:19.187173 TX Vref Scan disable
2983 12:13:19.189609 == TX Byte 0 ==
2984 12:13:19.192946 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2985 12:13:19.196283 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2986 12:13:19.199824 == TX Byte 1 ==
2987 12:13:19.203173 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2988 12:13:19.206604 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2989 12:13:19.207165
2990 12:13:19.209744 [DATLAT]
2991 12:13:19.210359 Freq=1200, CH0 RK1
2992 12:13:19.210744
2993 12:13:19.213750 DATLAT Default: 0xd
2994 12:13:19.214366 0, 0xFFFF, sum = 0
2995 12:13:19.216363 1, 0xFFFF, sum = 0
2996 12:13:19.216839 2, 0xFFFF, sum = 0
2997 12:13:19.219828 3, 0xFFFF, sum = 0
2998 12:13:19.220306 4, 0xFFFF, sum = 0
2999 12:13:19.222901 5, 0xFFFF, sum = 0
3000 12:13:19.223375 6, 0xFFFF, sum = 0
3001 12:13:19.226401 7, 0xFFFF, sum = 0
3002 12:13:19.226875 8, 0xFFFF, sum = 0
3003 12:13:19.230016 9, 0xFFFF, sum = 0
3004 12:13:19.233490 10, 0xFFFF, sum = 0
3005 12:13:19.234120 11, 0xFFFF, sum = 0
3006 12:13:19.236108 12, 0x0, sum = 1
3007 12:13:19.236586 13, 0x0, sum = 2
3008 12:13:19.236961 14, 0x0, sum = 3
3009 12:13:19.239966 15, 0x0, sum = 4
3010 12:13:19.240553 best_step = 13
3011 12:13:19.240933
3012 12:13:19.241280 ==
3013 12:13:19.243263 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 12:13:19.249825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 12:13:19.250445 ==
3016 12:13:19.250822 RX Vref Scan: 0
3017 12:13:19.251168
3018 12:13:19.253364 RX Vref 0 -> 0, step: 1
3019 12:13:19.253831
3020 12:13:19.256714 RX Delay -21 -> 252, step: 4
3021 12:13:19.259934 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3022 12:13:19.263006 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3023 12:13:19.269753 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3024 12:13:19.273206 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3025 12:13:19.276008 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3026 12:13:19.280165 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3027 12:13:19.283176 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3028 12:13:19.289383 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3029 12:13:19.293060 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3030 12:13:19.296410 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3031 12:13:19.299880 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3032 12:13:19.302746 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3033 12:13:19.309858 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3034 12:13:19.313400 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3035 12:13:19.316389 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3036 12:13:19.319687 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3037 12:13:19.320166 ==
3038 12:13:19.323168 Dram Type= 6, Freq= 0, CH_0, rank 1
3039 12:13:19.326542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3040 12:13:19.330106 ==
3041 12:13:19.330673 DQS Delay:
3042 12:13:19.331047 DQS0 = 0, DQS1 = 0
3043 12:13:19.333309 DQM Delay:
3044 12:13:19.333883 DQM0 = 119, DQM1 = 107
3045 12:13:19.336423 DQ Delay:
3046 12:13:19.339658 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =112
3047 12:13:19.343391 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =124
3048 12:13:19.346136 DQ8 =98, DQ9 =96, DQ10 =108, DQ11 =106
3049 12:13:19.349751 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3050 12:13:19.350389
3051 12:13:19.350766
3052 12:13:19.356787 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3053 12:13:19.359770 CH0 RK1: MR19=403, MR18=10F7
3054 12:13:19.366308 CH0_RK1: MR19=0x403, MR18=0x10F7, DQSOSC=403, MR23=63, INC=40, DEC=26
3055 12:13:19.369559 [RxdqsGatingPostProcess] freq 1200
3056 12:13:19.376680 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3057 12:13:19.379906 best DQS0 dly(2T, 0.5T) = (0, 11)
3058 12:13:19.380479 best DQS1 dly(2T, 0.5T) = (0, 12)
3059 12:13:19.383445 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3060 12:13:19.386507 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3061 12:13:19.389986 best DQS0 dly(2T, 0.5T) = (0, 11)
3062 12:13:19.393444 best DQS1 dly(2T, 0.5T) = (0, 11)
3063 12:13:19.396632 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3064 12:13:19.399766 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3065 12:13:19.403548 Pre-setting of DQS Precalculation
3066 12:13:19.406835 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3067 12:13:19.409999 ==
3068 12:13:19.413049 Dram Type= 6, Freq= 0, CH_1, rank 0
3069 12:13:19.416762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3070 12:13:19.417358 ==
3071 12:13:19.419861 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3072 12:13:19.426525 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3073 12:13:19.435827 [CA 0] Center 37 (7~68) winsize 62
3074 12:13:19.439274 [CA 1] Center 37 (7~68) winsize 62
3075 12:13:19.442557 [CA 2] Center 35 (5~65) winsize 61
3076 12:13:19.445846 [CA 3] Center 34 (4~65) winsize 62
3077 12:13:19.449004 [CA 4] Center 34 (4~65) winsize 62
3078 12:13:19.452694 [CA 5] Center 33 (3~64) winsize 62
3079 12:13:19.453276
3080 12:13:19.456453 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3081 12:13:19.457077
3082 12:13:19.459319 [CATrainingPosCal] consider 1 rank data
3083 12:13:19.462892 u2DelayCellTimex100 = 270/100 ps
3084 12:13:19.466252 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3085 12:13:19.469406 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3086 12:13:19.472429 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3087 12:13:19.479248 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3088 12:13:19.482784 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3089 12:13:19.485766 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3090 12:13:19.486374
3091 12:13:19.489891 CA PerBit enable=1, Macro0, CA PI delay=33
3092 12:13:19.490493
3093 12:13:19.492622 [CBTSetCACLKResult] CA Dly = 33
3094 12:13:19.493197 CS Dly: 5 (0~36)
3095 12:13:19.493649 ==
3096 12:13:19.496345 Dram Type= 6, Freq= 0, CH_1, rank 1
3097 12:13:19.502594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 12:13:19.503165 ==
3099 12:13:19.505922 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3100 12:13:19.512860 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3101 12:13:19.521556 [CA 0] Center 38 (8~68) winsize 61
3102 12:13:19.524769 [CA 1] Center 38 (8~68) winsize 61
3103 12:13:19.528062 [CA 2] Center 35 (5~66) winsize 62
3104 12:13:19.531801 [CA 3] Center 34 (4~65) winsize 62
3105 12:13:19.534826 [CA 4] Center 35 (5~65) winsize 61
3106 12:13:19.538218 [CA 5] Center 34 (4~65) winsize 62
3107 12:13:19.538776
3108 12:13:19.541450 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3109 12:13:19.542073
3110 12:13:19.544862 [CATrainingPosCal] consider 2 rank data
3111 12:13:19.548317 u2DelayCellTimex100 = 270/100 ps
3112 12:13:19.551807 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3113 12:13:19.554488 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3114 12:13:19.561577 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3115 12:13:19.564762 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3116 12:13:19.568232 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3117 12:13:19.571650 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3118 12:13:19.572276
3119 12:13:19.574492 CA PerBit enable=1, Macro0, CA PI delay=34
3120 12:13:19.574962
3121 12:13:19.577907 [CBTSetCACLKResult] CA Dly = 34
3122 12:13:19.578411 CS Dly: 6 (0~39)
3123 12:13:19.578782
3124 12:13:19.581302 ----->DramcWriteLeveling(PI) begin...
3125 12:13:19.584448 ==
3126 12:13:19.588528 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 12:13:19.591517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 12:13:19.592109 ==
3129 12:13:19.594966 Write leveling (Byte 0): 24 => 24
3130 12:13:19.598385 Write leveling (Byte 1): 30 => 30
3131 12:13:19.601813 DramcWriteLeveling(PI) end<-----
3132 12:13:19.602430
3133 12:13:19.603007 ==
3134 12:13:19.604777 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 12:13:19.608313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 12:13:19.608912 ==
3137 12:13:19.611320 [Gating] SW mode calibration
3138 12:13:19.617691 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3139 12:13:19.621517 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3140 12:13:19.627837 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 12:13:19.631317 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 12:13:19.634576 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 12:13:19.641427 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 12:13:19.644949 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 12:13:19.648429 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 12:13:19.655001 0 15 24 | B1->B0 | 2c2c 2929 | 0 0 | (0 0) (0 1)
3147 12:13:19.658003 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 12:13:19.661910 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 12:13:19.668021 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 12:13:19.671511 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 12:13:19.674885 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 12:13:19.682144 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 12:13:19.684770 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 12:13:19.688267 1 0 24 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
3155 12:13:19.692038 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 12:13:19.698260 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 12:13:19.701749 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 12:13:19.705539 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 12:13:19.711887 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 12:13:19.715247 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 12:13:19.718890 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 12:13:19.725542 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3163 12:13:19.728677 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3164 12:13:19.731910 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 12:13:19.738529 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 12:13:19.741819 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 12:13:19.745271 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 12:13:19.751977 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 12:13:19.755086 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 12:13:19.758315 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 12:13:19.765209 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 12:13:19.768197 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 12:13:19.772100 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 12:13:19.774972 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 12:13:19.782049 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 12:13:19.785194 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 12:13:19.788120 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 12:13:19.795148 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3179 12:13:19.798329 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3180 12:13:19.801689 Total UI for P1: 0, mck2ui 16
3181 12:13:19.805584 best dqsien dly found for B0: ( 1, 3, 24)
3182 12:13:19.808159 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 12:13:19.812121 Total UI for P1: 0, mck2ui 16
3184 12:13:19.815349 best dqsien dly found for B1: ( 1, 3, 26)
3185 12:13:19.818442 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3186 12:13:19.821624 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3187 12:13:19.822147
3188 12:13:19.828164 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3189 12:13:19.831533 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3190 12:13:19.834852 [Gating] SW calibration Done
3191 12:13:19.835379 ==
3192 12:13:19.838061 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 12:13:19.841852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 12:13:19.842374 ==
3195 12:13:19.842748 RX Vref Scan: 0
3196 12:13:19.843100
3197 12:13:19.845272 RX Vref 0 -> 0, step: 1
3198 12:13:19.845840
3199 12:13:19.848656 RX Delay -40 -> 252, step: 8
3200 12:13:19.851817 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3201 12:13:19.854928 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3202 12:13:19.861793 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3203 12:13:19.864618 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3204 12:13:19.868743 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3205 12:13:19.871338 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3206 12:13:19.875468 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3207 12:13:19.881671 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3208 12:13:19.884901 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3209 12:13:19.888129 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3210 12:13:19.891517 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3211 12:13:19.894998 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3212 12:13:19.898402 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3213 12:13:19.904983 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3214 12:13:19.907799 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3215 12:13:19.911325 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3216 12:13:19.911572 ==
3217 12:13:19.914619 Dram Type= 6, Freq= 0, CH_1, rank 0
3218 12:13:19.917743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3219 12:13:19.921307 ==
3220 12:13:19.921472 DQS Delay:
3221 12:13:19.921602 DQS0 = 0, DQS1 = 0
3222 12:13:19.924624 DQM Delay:
3223 12:13:19.924786 DQM0 = 119, DQM1 = 112
3224 12:13:19.927616 DQ Delay:
3225 12:13:19.930954 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3226 12:13:19.934427 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3227 12:13:19.937700 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3228 12:13:19.941387 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3229 12:13:19.941485
3230 12:13:19.941562
3231 12:13:19.941633 ==
3232 12:13:19.944384 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 12:13:19.947825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 12:13:19.947916 ==
3235 12:13:19.947986
3236 12:13:19.948050
3237 12:13:19.951358 TX Vref Scan disable
3238 12:13:19.954363 == TX Byte 0 ==
3239 12:13:19.957776 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3240 12:13:19.961249 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3241 12:13:19.964633 == TX Byte 1 ==
3242 12:13:19.967874 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3243 12:13:19.971595 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3244 12:13:19.971684 ==
3245 12:13:19.974522 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 12:13:19.977806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 12:13:19.981273 ==
3248 12:13:19.991640 TX Vref=22, minBit 1, minWin=24, winSum=404
3249 12:13:19.994727 TX Vref=24, minBit 3, minWin=25, winSum=413
3250 12:13:19.997912 TX Vref=26, minBit 10, minWin=25, winSum=419
3251 12:13:20.001369 TX Vref=28, minBit 14, minWin=25, winSum=423
3252 12:13:20.004900 TX Vref=30, minBit 1, minWin=26, winSum=425
3253 12:13:20.011178 TX Vref=32, minBit 11, minWin=25, winSum=421
3254 12:13:20.015003 [TxChooseVref] Worse bit 1, Min win 26, Win sum 425, Final Vref 30
3255 12:13:20.015092
3256 12:13:20.018146 Final TX Range 1 Vref 30
3257 12:13:20.018231
3258 12:13:20.018299 ==
3259 12:13:20.021546 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 12:13:20.024717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 12:13:20.024804 ==
3262 12:13:20.024871
3263 12:13:20.028456
3264 12:13:20.028539 TX Vref Scan disable
3265 12:13:20.031498 == TX Byte 0 ==
3266 12:13:20.034642 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3267 12:13:20.038583 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3268 12:13:20.041710 == TX Byte 1 ==
3269 12:13:20.044953 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3270 12:13:20.048537 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3271 12:13:20.048697
3272 12:13:20.051800 [DATLAT]
3273 12:13:20.051963 Freq=1200, CH1 RK0
3274 12:13:20.052036
3275 12:13:20.054707 DATLAT Default: 0xd
3276 12:13:20.054872 0, 0xFFFF, sum = 0
3277 12:13:20.058366 1, 0xFFFF, sum = 0
3278 12:13:20.058532 2, 0xFFFF, sum = 0
3279 12:13:20.061133 3, 0xFFFF, sum = 0
3280 12:13:20.061262 4, 0xFFFF, sum = 0
3281 12:13:20.064624 5, 0xFFFF, sum = 0
3282 12:13:20.068243 6, 0xFFFF, sum = 0
3283 12:13:20.068408 7, 0xFFFF, sum = 0
3284 12:13:20.071437 8, 0xFFFF, sum = 0
3285 12:13:20.071572 9, 0xFFFF, sum = 0
3286 12:13:20.074491 10, 0xFFFF, sum = 0
3287 12:13:20.074658 11, 0xFFFF, sum = 0
3288 12:13:20.078486 12, 0x0, sum = 1
3289 12:13:20.078652 13, 0x0, sum = 2
3290 12:13:20.081464 14, 0x0, sum = 3
3291 12:13:20.081633 15, 0x0, sum = 4
3292 12:13:20.081714 best_step = 13
3293 12:13:20.081785
3294 12:13:20.084717 ==
3295 12:13:20.088430 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 12:13:20.091421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 12:13:20.091606 ==
3298 12:13:20.091696 RX Vref Scan: 1
3299 12:13:20.091781
3300 12:13:20.094633 Set Vref Range= 32 -> 127
3301 12:13:20.094747
3302 12:13:20.098277 RX Vref 32 -> 127, step: 1
3303 12:13:20.098388
3304 12:13:20.101312 RX Delay -13 -> 252, step: 4
3305 12:13:20.101512
3306 12:13:20.104720 Set Vref, RX VrefLevel [Byte0]: 32
3307 12:13:20.108456 [Byte1]: 32
3308 12:13:20.108681
3309 12:13:20.111400 Set Vref, RX VrefLevel [Byte0]: 33
3310 12:13:20.114526 [Byte1]: 33
3311 12:13:20.114762
3312 12:13:20.118024 Set Vref, RX VrefLevel [Byte0]: 34
3313 12:13:20.121206 [Byte1]: 34
3314 12:13:20.125897
3315 12:13:20.126250 Set Vref, RX VrefLevel [Byte0]: 35
3316 12:13:20.129114 [Byte1]: 35
3317 12:13:20.133644
3318 12:13:20.134049 Set Vref, RX VrefLevel [Byte0]: 36
3319 12:13:20.137195 [Byte1]: 36
3320 12:13:20.142010
3321 12:13:20.142704 Set Vref, RX VrefLevel [Byte0]: 37
3322 12:13:20.145396 [Byte1]: 37
3323 12:13:20.149461
3324 12:13:20.150053 Set Vref, RX VrefLevel [Byte0]: 38
3325 12:13:20.152936 [Byte1]: 38
3326 12:13:20.157339
3327 12:13:20.160688 Set Vref, RX VrefLevel [Byte0]: 39
3328 12:13:20.161267 [Byte1]: 39
3329 12:13:20.165378
3330 12:13:20.165830 Set Vref, RX VrefLevel [Byte0]: 40
3331 12:13:20.168925 [Byte1]: 40
3332 12:13:20.173208
3333 12:13:20.173668 Set Vref, RX VrefLevel [Byte0]: 41
3334 12:13:20.176791 [Byte1]: 41
3335 12:13:20.181262
3336 12:13:20.181730 Set Vref, RX VrefLevel [Byte0]: 42
3337 12:13:20.184488 [Byte1]: 42
3338 12:13:20.189171
3339 12:13:20.189628 Set Vref, RX VrefLevel [Byte0]: 43
3340 12:13:20.192611 [Byte1]: 43
3341 12:13:20.196975
3342 12:13:20.197238 Set Vref, RX VrefLevel [Byte0]: 44
3343 12:13:20.199862 [Byte1]: 44
3344 12:13:20.204668
3345 12:13:20.204869 Set Vref, RX VrefLevel [Byte0]: 45
3346 12:13:20.207876 [Byte1]: 45
3347 12:13:20.212499
3348 12:13:20.212668 Set Vref, RX VrefLevel [Byte0]: 46
3349 12:13:20.215571 [Byte1]: 46
3350 12:13:20.220211
3351 12:13:20.220340 Set Vref, RX VrefLevel [Byte0]: 47
3352 12:13:20.223560 [Byte1]: 47
3353 12:13:20.228269
3354 12:13:20.228442 Set Vref, RX VrefLevel [Byte0]: 48
3355 12:13:20.231388 [Byte1]: 48
3356 12:13:20.236130
3357 12:13:20.236293 Set Vref, RX VrefLevel [Byte0]: 49
3358 12:13:20.239295 [Byte1]: 49
3359 12:13:20.244640
3360 12:13:20.244807 Set Vref, RX VrefLevel [Byte0]: 50
3361 12:13:20.247561 [Byte1]: 50
3362 12:13:20.251856
3363 12:13:20.252017 Set Vref, RX VrefLevel [Byte0]: 51
3364 12:13:20.255531 [Byte1]: 51
3365 12:13:20.259822
3366 12:13:20.259990 Set Vref, RX VrefLevel [Byte0]: 52
3367 12:13:20.262945 [Byte1]: 52
3368 12:13:20.267601
3369 12:13:20.267793 Set Vref, RX VrefLevel [Byte0]: 53
3370 12:13:20.270990 [Byte1]: 53
3371 12:13:20.276193
3372 12:13:20.276753 Set Vref, RX VrefLevel [Byte0]: 54
3373 12:13:20.279401 [Byte1]: 54
3374 12:13:20.283978
3375 12:13:20.284556 Set Vref, RX VrefLevel [Byte0]: 55
3376 12:13:20.287306 [Byte1]: 55
3377 12:13:20.291984
3378 12:13:20.292553 Set Vref, RX VrefLevel [Byte0]: 56
3379 12:13:20.295596 [Byte1]: 56
3380 12:13:20.299479
3381 12:13:20.300045 Set Vref, RX VrefLevel [Byte0]: 57
3382 12:13:20.302840 [Byte1]: 57
3383 12:13:20.307443
3384 12:13:20.308031 Set Vref, RX VrefLevel [Byte0]: 58
3385 12:13:20.311008 [Byte1]: 58
3386 12:13:20.315590
3387 12:13:20.316162 Set Vref, RX VrefLevel [Byte0]: 59
3388 12:13:20.318549 [Byte1]: 59
3389 12:13:20.323115
3390 12:13:20.323676 Set Vref, RX VrefLevel [Byte0]: 60
3391 12:13:20.326171 [Byte1]: 60
3392 12:13:20.331361
3393 12:13:20.331928 Set Vref, RX VrefLevel [Byte0]: 61
3394 12:13:20.334172 [Byte1]: 61
3395 12:13:20.339055
3396 12:13:20.339622 Set Vref, RX VrefLevel [Byte0]: 62
3397 12:13:20.342690 [Byte1]: 62
3398 12:13:20.347223
3399 12:13:20.347784 Set Vref, RX VrefLevel [Byte0]: 63
3400 12:13:20.350071 [Byte1]: 63
3401 12:13:20.355006
3402 12:13:20.355570 Set Vref, RX VrefLevel [Byte0]: 64
3403 12:13:20.358149 [Byte1]: 64
3404 12:13:20.362882
3405 12:13:20.363451 Set Vref, RX VrefLevel [Byte0]: 65
3406 12:13:20.366046 [Byte1]: 65
3407 12:13:20.370357
3408 12:13:20.370831 Set Vref, RX VrefLevel [Byte0]: 66
3409 12:13:20.374200 [Byte1]: 66
3410 12:13:20.378370
3411 12:13:20.378937 Set Vref, RX VrefLevel [Byte0]: 67
3412 12:13:20.381680 [Byte1]: 67
3413 12:13:20.386342
3414 12:13:20.386920 Final RX Vref Byte 0 = 53 to rank0
3415 12:13:20.390067 Final RX Vref Byte 1 = 53 to rank0
3416 12:13:20.393215 Final RX Vref Byte 0 = 53 to rank1
3417 12:13:20.396792 Final RX Vref Byte 1 = 53 to rank1==
3418 12:13:20.399670 Dram Type= 6, Freq= 0, CH_1, rank 0
3419 12:13:20.403090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3420 12:13:20.406651 ==
3421 12:13:20.407225 DQS Delay:
3422 12:13:20.407595 DQS0 = 0, DQS1 = 0
3423 12:13:20.410292 DQM Delay:
3424 12:13:20.410877 DQM0 = 119, DQM1 = 112
3425 12:13:20.413536 DQ Delay:
3426 12:13:20.417250 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =120
3427 12:13:20.419898 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =118
3428 12:13:20.423232 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3429 12:13:20.426629 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =118
3430 12:13:20.427209
3431 12:13:20.427578
3432 12:13:20.433529 [DQSOSCAuto] RK0, (LSB)MR18= 0x115, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3433 12:13:20.437395 CH1 RK0: MR19=404, MR18=115
3434 12:13:20.443267 CH1_RK0: MR19=0x404, MR18=0x115, DQSOSC=401, MR23=63, INC=40, DEC=27
3435 12:13:20.443829
3436 12:13:20.446619 ----->DramcWriteLeveling(PI) begin...
3437 12:13:20.447162 ==
3438 12:13:20.449913 Dram Type= 6, Freq= 0, CH_1, rank 1
3439 12:13:20.453589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3440 12:13:20.454226 ==
3441 12:13:20.456674 Write leveling (Byte 0): 25 => 25
3442 12:13:20.460309 Write leveling (Byte 1): 30 => 30
3443 12:13:20.463423 DramcWriteLeveling(PI) end<-----
3444 12:13:20.463894
3445 12:13:20.464264 ==
3446 12:13:20.466469 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 12:13:20.470308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3448 12:13:20.473839 ==
3449 12:13:20.474453 [Gating] SW mode calibration
3450 12:13:20.483151 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3451 12:13:20.486499 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3452 12:13:20.489908 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 12:13:20.496589 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 12:13:20.500303 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 12:13:20.503054 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 12:13:20.510278 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 12:13:20.513134 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3458 12:13:20.516736 0 15 24 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 1)
3459 12:13:20.523481 0 15 28 | B1->B0 | 2323 2c2c | 0 0 | (1 0) (0 0)
3460 12:13:20.526523 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 12:13:20.530890 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 12:13:20.533329 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 12:13:20.539831 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 12:13:20.543404 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 12:13:20.546669 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3466 12:13:20.553406 1 0 24 | B1->B0 | 3535 2929 | 0 0 | (0 0) (0 0)
3467 12:13:20.556954 1 0 28 | B1->B0 | 4646 3b3b | 0 0 | (0 0) (1 1)
3468 12:13:20.560986 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 12:13:20.566992 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 12:13:20.569806 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 12:13:20.573341 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 12:13:20.580038 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 12:13:20.583020 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 12:13:20.586723 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3475 12:13:20.593312 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3476 12:13:20.596741 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 12:13:20.599949 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 12:13:20.606572 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 12:13:20.610068 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 12:13:20.613271 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 12:13:20.619773 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 12:13:20.623542 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 12:13:20.626258 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 12:13:20.632870 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 12:13:20.636579 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 12:13:20.639868 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 12:13:20.645871 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 12:13:20.649660 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 12:13:20.652637 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 12:13:20.659193 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3491 12:13:20.662682 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 12:13:20.665875 Total UI for P1: 0, mck2ui 16
3493 12:13:20.669146 best dqsien dly found for B0: ( 1, 3, 24)
3494 12:13:20.672523 Total UI for P1: 0, mck2ui 16
3495 12:13:20.676985 best dqsien dly found for B1: ( 1, 3, 24)
3496 12:13:20.679238 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3497 12:13:20.682752 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3498 12:13:20.683230
3499 12:13:20.685978 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3500 12:13:20.688865 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3501 12:13:20.692446 [Gating] SW calibration Done
3502 12:13:20.692919 ==
3503 12:13:20.695868 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 12:13:20.699674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 12:13:20.700253 ==
3506 12:13:20.702265 RX Vref Scan: 0
3507 12:13:20.702748
3508 12:13:20.705500 RX Vref 0 -> 0, step: 1
3509 12:13:20.706027
3510 12:13:20.706404 RX Delay -40 -> 252, step: 8
3511 12:13:20.712512 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3512 12:13:20.715978 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3513 12:13:20.719581 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3514 12:13:20.722474 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3515 12:13:20.726021 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3516 12:13:20.732508 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3517 12:13:20.736504 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3518 12:13:20.739424 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3519 12:13:20.742595 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3520 12:13:20.745699 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3521 12:13:20.752273 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3522 12:13:20.755991 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3523 12:13:20.759192 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3524 12:13:20.762368 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3525 12:13:20.766073 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3526 12:13:20.772035 iDelay=200, Bit 15, Center 123 (48 ~ 199) 152
3527 12:13:20.772623 ==
3528 12:13:20.775781 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 12:13:20.778762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 12:13:20.779240 ==
3531 12:13:20.779616 DQS Delay:
3532 12:13:20.782261 DQS0 = 0, DQS1 = 0
3533 12:13:20.782736 DQM Delay:
3534 12:13:20.785872 DQM0 = 118, DQM1 = 112
3535 12:13:20.786484 DQ Delay:
3536 12:13:20.789147 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =119
3537 12:13:20.792592 DQ4 =115, DQ5 =131, DQ6 =123, DQ7 =115
3538 12:13:20.795528 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3539 12:13:20.798843 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3540 12:13:20.799413
3541 12:13:20.799787
3542 12:13:20.802125 ==
3543 12:13:20.805723 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 12:13:20.808854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 12:13:20.809429 ==
3546 12:13:20.809802
3547 12:13:20.810205
3548 12:13:20.812116 TX Vref Scan disable
3549 12:13:20.812684 == TX Byte 0 ==
3550 12:13:20.818930 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3551 12:13:20.821911 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3552 12:13:20.822510 == TX Byte 1 ==
3553 12:13:20.829007 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3554 12:13:20.831798 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3555 12:13:20.832282 ==
3556 12:13:20.835040 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 12:13:20.838808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 12:13:20.839287 ==
3559 12:13:20.850868 TX Vref=22, minBit 1, minWin=25, winSum=420
3560 12:13:20.854373 TX Vref=24, minBit 1, minWin=25, winSum=422
3561 12:13:20.857864 TX Vref=26, minBit 9, minWin=25, winSum=425
3562 12:13:20.860875 TX Vref=28, minBit 8, minWin=26, winSum=431
3563 12:13:20.864294 TX Vref=30, minBit 1, minWin=26, winSum=431
3564 12:13:20.870737 TX Vref=32, minBit 1, minWin=26, winSum=427
3565 12:13:20.874273 [TxChooseVref] Worse bit 8, Min win 26, Win sum 431, Final Vref 28
3566 12:13:20.874849
3567 12:13:20.877692 Final TX Range 1 Vref 28
3568 12:13:20.878300
3569 12:13:20.878680 ==
3570 12:13:20.880813 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 12:13:20.884074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 12:13:20.884663 ==
3573 12:13:20.887546
3574 12:13:20.888020
3575 12:13:20.888393 TX Vref Scan disable
3576 12:13:20.890727 == TX Byte 0 ==
3577 12:13:20.894258 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3578 12:13:20.901213 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3579 12:13:20.901784 == TX Byte 1 ==
3580 12:13:20.903813 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3581 12:13:20.910595 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3582 12:13:20.911215
3583 12:13:20.911774 [DATLAT]
3584 12:13:20.912151 Freq=1200, CH1 RK1
3585 12:13:20.912498
3586 12:13:20.913665 DATLAT Default: 0xd
3587 12:13:20.914177 0, 0xFFFF, sum = 0
3588 12:13:20.917509 1, 0xFFFF, sum = 0
3589 12:13:20.918129 2, 0xFFFF, sum = 0
3590 12:13:20.920759 3, 0xFFFF, sum = 0
3591 12:13:20.923656 4, 0xFFFF, sum = 0
3592 12:13:20.924141 5, 0xFFFF, sum = 0
3593 12:13:20.926998 6, 0xFFFF, sum = 0
3594 12:13:20.927476 7, 0xFFFF, sum = 0
3595 12:13:20.930391 8, 0xFFFF, sum = 0
3596 12:13:20.930872 9, 0xFFFF, sum = 0
3597 12:13:20.933899 10, 0xFFFF, sum = 0
3598 12:13:20.934413 11, 0xFFFF, sum = 0
3599 12:13:20.937040 12, 0x0, sum = 1
3600 12:13:20.937522 13, 0x0, sum = 2
3601 12:13:20.940517 14, 0x0, sum = 3
3602 12:13:20.941101 15, 0x0, sum = 4
3603 12:13:20.943977 best_step = 13
3604 12:13:20.944548
3605 12:13:20.944924 ==
3606 12:13:20.946952 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 12:13:20.950688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 12:13:20.951262 ==
3609 12:13:20.951642 RX Vref Scan: 0
3610 12:13:20.951995
3611 12:13:20.953721 RX Vref 0 -> 0, step: 1
3612 12:13:20.954237
3613 12:13:20.957031 RX Delay -13 -> 252, step: 4
3614 12:13:20.960615 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3615 12:13:20.966958 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3616 12:13:20.970482 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3617 12:13:20.973705 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3618 12:13:20.977029 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3619 12:13:20.980771 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3620 12:13:20.987011 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3621 12:13:20.990566 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3622 12:13:20.993743 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3623 12:13:20.997118 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3624 12:13:21.000298 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3625 12:13:21.006876 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3626 12:13:21.010730 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3627 12:13:21.013642 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3628 12:13:21.016710 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3629 12:13:21.020391 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3630 12:13:21.023514 ==
3631 12:13:21.026744 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 12:13:21.030020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 12:13:21.030662 ==
3634 12:13:21.031188 DQS Delay:
3635 12:13:21.033492 DQS0 = 0, DQS1 = 0
3636 12:13:21.034018 DQM Delay:
3637 12:13:21.036859 DQM0 = 119, DQM1 = 113
3638 12:13:21.037424 DQ Delay:
3639 12:13:21.040109 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3640 12:13:21.043268 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3641 12:13:21.046632 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =108
3642 12:13:21.049958 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3643 12:13:21.050540
3644 12:13:21.050920
3645 12:13:21.059878 [DQSOSCAuto] RK1, (LSB)MR18= 0x5ea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 408 ps
3646 12:13:21.063058 CH1 RK1: MR19=403, MR18=5EA
3647 12:13:21.066647 CH1_RK1: MR19=0x403, MR18=0x5EA, DQSOSC=408, MR23=63, INC=39, DEC=26
3648 12:13:21.069919 [RxdqsGatingPostProcess] freq 1200
3649 12:13:21.076499 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3650 12:13:21.079901 best DQS0 dly(2T, 0.5T) = (0, 11)
3651 12:13:21.082851 best DQS1 dly(2T, 0.5T) = (0, 11)
3652 12:13:21.086878 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3653 12:13:21.089600 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3654 12:13:21.093089 best DQS0 dly(2T, 0.5T) = (0, 11)
3655 12:13:21.096520 best DQS1 dly(2T, 0.5T) = (0, 11)
3656 12:13:21.099712 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3657 12:13:21.102988 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3658 12:13:21.103559 Pre-setting of DQS Precalculation
3659 12:13:21.110453 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3660 12:13:21.116222 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3661 12:13:21.122652 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3662 12:13:21.123207
3663 12:13:21.123580
3664 12:13:21.126414 [Calibration Summary] 2400 Mbps
3665 12:13:21.129392 CH 0, Rank 0
3666 12:13:21.129868 SW Impedance : PASS
3667 12:13:21.132907 DUTY Scan : NO K
3668 12:13:21.136391 ZQ Calibration : PASS
3669 12:13:21.136901 Jitter Meter : NO K
3670 12:13:21.139681 CBT Training : PASS
3671 12:13:21.142769 Write leveling : PASS
3672 12:13:21.143410 RX DQS gating : PASS
3673 12:13:21.146053 RX DQ/DQS(RDDQC) : PASS
3674 12:13:21.146617 TX DQ/DQS : PASS
3675 12:13:21.149895 RX DATLAT : PASS
3676 12:13:21.153064 RX DQ/DQS(Engine): PASS
3677 12:13:21.153538 TX OE : NO K
3678 12:13:21.156399 All Pass.
3679 12:13:21.156970
3680 12:13:21.157348 CH 0, Rank 1
3681 12:13:21.159315 SW Impedance : PASS
3682 12:13:21.159887 DUTY Scan : NO K
3683 12:13:21.163034 ZQ Calibration : PASS
3684 12:13:21.165885 Jitter Meter : NO K
3685 12:13:21.166400 CBT Training : PASS
3686 12:13:21.169363 Write leveling : PASS
3687 12:13:21.172607 RX DQS gating : PASS
3688 12:13:21.173233 RX DQ/DQS(RDDQC) : PASS
3689 12:13:21.175904 TX DQ/DQS : PASS
3690 12:13:21.179414 RX DATLAT : PASS
3691 12:13:21.179989 RX DQ/DQS(Engine): PASS
3692 12:13:21.182417 TX OE : NO K
3693 12:13:21.182897 All Pass.
3694 12:13:21.183269
3695 12:13:21.186136 CH 1, Rank 0
3696 12:13:21.186694 SW Impedance : PASS
3697 12:13:21.189360 DUTY Scan : NO K
3698 12:13:21.192544 ZQ Calibration : PASS
3699 12:13:21.193113 Jitter Meter : NO K
3700 12:13:21.195973 CBT Training : PASS
3701 12:13:21.199196 Write leveling : PASS
3702 12:13:21.199674 RX DQS gating : PASS
3703 12:13:21.202387 RX DQ/DQS(RDDQC) : PASS
3704 12:13:21.202864 TX DQ/DQS : PASS
3705 12:13:21.205928 RX DATLAT : PASS
3706 12:13:21.209267 RX DQ/DQS(Engine): PASS
3707 12:13:21.209839 TX OE : NO K
3708 12:13:21.212600 All Pass.
3709 12:13:21.213166
3710 12:13:21.213540 CH 1, Rank 1
3711 12:13:21.216090 SW Impedance : PASS
3712 12:13:21.216566 DUTY Scan : NO K
3713 12:13:21.219140 ZQ Calibration : PASS
3714 12:13:21.222313 Jitter Meter : NO K
3715 12:13:21.222813 CBT Training : PASS
3716 12:13:21.225793 Write leveling : PASS
3717 12:13:21.229209 RX DQS gating : PASS
3718 12:13:21.229685 RX DQ/DQS(RDDQC) : PASS
3719 12:13:21.232548 TX DQ/DQS : PASS
3720 12:13:21.235981 RX DATLAT : PASS
3721 12:13:21.236558 RX DQ/DQS(Engine): PASS
3722 12:13:21.239317 TX OE : NO K
3723 12:13:21.239899 All Pass.
3724 12:13:21.240285
3725 12:13:21.242321 DramC Write-DBI off
3726 12:13:21.245936 PER_BANK_REFRESH: Hybrid Mode
3727 12:13:21.246557 TX_TRACKING: ON
3728 12:13:21.256168 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3729 12:13:21.259420 [FAST_K] Save calibration result to emmc
3730 12:13:21.262280 dramc_set_vcore_voltage set vcore to 650000
3731 12:13:21.266034 Read voltage for 600, 5
3732 12:13:21.266602 Vio18 = 0
3733 12:13:21.266979 Vcore = 650000
3734 12:13:21.269049 Vdram = 0
3735 12:13:21.269525 Vddq = 0
3736 12:13:21.269898 Vmddr = 0
3737 12:13:21.275703 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3738 12:13:21.279116 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3739 12:13:21.282548 MEM_TYPE=3, freq_sel=19
3740 12:13:21.285692 sv_algorithm_assistance_LP4_1600
3741 12:13:21.289186 ============ PULL DRAM RESETB DOWN ============
3742 12:13:21.292704 ========== PULL DRAM RESETB DOWN end =========
3743 12:13:21.299199 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3744 12:13:21.302553 ===================================
3745 12:13:21.303128 LPDDR4 DRAM CONFIGURATION
3746 12:13:21.306099 ===================================
3747 12:13:21.309157 EX_ROW_EN[0] = 0x0
3748 12:13:21.312442 EX_ROW_EN[1] = 0x0
3749 12:13:21.313014 LP4Y_EN = 0x0
3750 12:13:21.315958 WORK_FSP = 0x0
3751 12:13:21.316433 WL = 0x2
3752 12:13:21.319057 RL = 0x2
3753 12:13:21.319626 BL = 0x2
3754 12:13:21.322601 RPST = 0x0
3755 12:13:21.323171 RD_PRE = 0x0
3756 12:13:21.325599 WR_PRE = 0x1
3757 12:13:21.326236 WR_PST = 0x0
3758 12:13:21.329000 DBI_WR = 0x0
3759 12:13:21.329473 DBI_RD = 0x0
3760 12:13:21.332165 OTF = 0x1
3761 12:13:21.335452 ===================================
3762 12:13:21.338890 ===================================
3763 12:13:21.339366 ANA top config
3764 12:13:21.342223 ===================================
3765 12:13:21.345603 DLL_ASYNC_EN = 0
3766 12:13:21.348968 ALL_SLAVE_EN = 1
3767 12:13:21.349542 NEW_RANK_MODE = 1
3768 12:13:21.352318 DLL_IDLE_MODE = 1
3769 12:13:21.356067 LP45_APHY_COMB_EN = 1
3770 12:13:21.359168 TX_ODT_DIS = 1
3771 12:13:21.362470 NEW_8X_MODE = 1
3772 12:13:21.365428 ===================================
3773 12:13:21.368919 ===================================
3774 12:13:21.369488 data_rate = 1200
3775 12:13:21.372442 CKR = 1
3776 12:13:21.375978 DQ_P2S_RATIO = 8
3777 12:13:21.378993 ===================================
3778 12:13:21.382737 CA_P2S_RATIO = 8
3779 12:13:21.385548 DQ_CA_OPEN = 0
3780 12:13:21.388927 DQ_SEMI_OPEN = 0
3781 12:13:21.389507 CA_SEMI_OPEN = 0
3782 12:13:21.392442 CA_FULL_RATE = 0
3783 12:13:21.395571 DQ_CKDIV4_EN = 1
3784 12:13:21.398720 CA_CKDIV4_EN = 1
3785 12:13:21.402442 CA_PREDIV_EN = 0
3786 12:13:21.405520 PH8_DLY = 0
3787 12:13:21.406108 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3788 12:13:21.408498 DQ_AAMCK_DIV = 4
3789 12:13:21.412074 CA_AAMCK_DIV = 4
3790 12:13:21.414992 CA_ADMCK_DIV = 4
3791 12:13:21.418388 DQ_TRACK_CA_EN = 0
3792 12:13:21.422049 CA_PICK = 600
3793 12:13:21.425257 CA_MCKIO = 600
3794 12:13:21.425821 MCKIO_SEMI = 0
3795 12:13:21.428414 PLL_FREQ = 2288
3796 12:13:21.432063 DQ_UI_PI_RATIO = 32
3797 12:13:21.435081 CA_UI_PI_RATIO = 0
3798 12:13:21.438472 ===================================
3799 12:13:21.442008 ===================================
3800 12:13:21.445307 memory_type:LPDDR4
3801 12:13:21.445882 GP_NUM : 10
3802 12:13:21.448533 SRAM_EN : 1
3803 12:13:21.451780 MD32_EN : 0
3804 12:13:21.455024 ===================================
3805 12:13:21.455596 [ANA_INIT] >>>>>>>>>>>>>>
3806 12:13:21.458093 <<<<<< [CONFIGURE PHASE]: ANA_TX
3807 12:13:21.461439 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3808 12:13:21.464810 ===================================
3809 12:13:21.468588 data_rate = 1200,PCW = 0X5800
3810 12:13:21.471329 ===================================
3811 12:13:21.474595 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3812 12:13:21.481968 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3813 12:13:21.484802 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3814 12:13:21.491663 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3815 12:13:21.494783 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3816 12:13:21.498348 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3817 12:13:21.498828 [ANA_INIT] flow start
3818 12:13:21.501446 [ANA_INIT] PLL >>>>>>>>
3819 12:13:21.505096 [ANA_INIT] PLL <<<<<<<<
3820 12:13:21.505666 [ANA_INIT] MIDPI >>>>>>>>
3821 12:13:21.508174 [ANA_INIT] MIDPI <<<<<<<<
3822 12:13:21.511636 [ANA_INIT] DLL >>>>>>>>
3823 12:13:21.512203 [ANA_INIT] flow end
3824 12:13:21.518501 ============ LP4 DIFF to SE enter ============
3825 12:13:21.521455 ============ LP4 DIFF to SE exit ============
3826 12:13:21.524638 [ANA_INIT] <<<<<<<<<<<<<
3827 12:13:21.527819 [Flow] Enable top DCM control >>>>>
3828 12:13:21.531387 [Flow] Enable top DCM control <<<<<
3829 12:13:21.531864 Enable DLL master slave shuffle
3830 12:13:21.537926 ==============================================================
3831 12:13:21.541647 Gating Mode config
3832 12:13:21.544867 ==============================================================
3833 12:13:21.548116 Config description:
3834 12:13:21.557930 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3835 12:13:21.564801 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3836 12:13:21.567790 SELPH_MODE 0: By rank 1: By Phase
3837 12:13:21.574765 ==============================================================
3838 12:13:21.577737 GAT_TRACK_EN = 1
3839 12:13:21.581460 RX_GATING_MODE = 2
3840 12:13:21.584397 RX_GATING_TRACK_MODE = 2
3841 12:13:21.587800 SELPH_MODE = 1
3842 12:13:21.588267 PICG_EARLY_EN = 1
3843 12:13:21.590969 VALID_LAT_VALUE = 1
3844 12:13:21.598000 ==============================================================
3845 12:13:21.601179 Enter into Gating configuration >>>>
3846 12:13:21.604389 Exit from Gating configuration <<<<
3847 12:13:21.607974 Enter into DVFS_PRE_config >>>>>
3848 12:13:21.617828 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3849 12:13:21.621156 Exit from DVFS_PRE_config <<<<<
3850 12:13:21.624376 Enter into PICG configuration >>>>
3851 12:13:21.627416 Exit from PICG configuration <<<<
3852 12:13:21.630891 [RX_INPUT] configuration >>>>>
3853 12:13:21.634287 [RX_INPUT] configuration <<<<<
3854 12:13:21.637360 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3855 12:13:21.644384 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3856 12:13:21.651233 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3857 12:13:21.657679 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3858 12:13:21.664442 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3859 12:13:21.667462 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3860 12:13:21.674043 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3861 12:13:21.677718 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3862 12:13:21.680909 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3863 12:13:21.684296 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3864 12:13:21.690580 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3865 12:13:21.693877 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3866 12:13:21.697436 ===================================
3867 12:13:21.700535 LPDDR4 DRAM CONFIGURATION
3868 12:13:21.703752 ===================================
3869 12:13:21.704221 EX_ROW_EN[0] = 0x0
3870 12:13:21.707114 EX_ROW_EN[1] = 0x0
3871 12:13:21.707594 LP4Y_EN = 0x0
3872 12:13:21.710654 WORK_FSP = 0x0
3873 12:13:21.711118 WL = 0x2
3874 12:13:21.713602 RL = 0x2
3875 12:13:21.716911 BL = 0x2
3876 12:13:21.717378 RPST = 0x0
3877 12:13:21.720526 RD_PRE = 0x0
3878 12:13:21.721109 WR_PRE = 0x1
3879 12:13:21.723706 WR_PST = 0x0
3880 12:13:21.724284 DBI_WR = 0x0
3881 12:13:21.726837 DBI_RD = 0x0
3882 12:13:21.727414 OTF = 0x1
3883 12:13:21.729917 ===================================
3884 12:13:21.733860 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3885 12:13:21.740120 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3886 12:13:21.743776 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3887 12:13:21.747015 ===================================
3888 12:13:21.750528 LPDDR4 DRAM CONFIGURATION
3889 12:13:21.754126 ===================================
3890 12:13:21.754699 EX_ROW_EN[0] = 0x10
3891 12:13:21.756959 EX_ROW_EN[1] = 0x0
3892 12:13:21.757537 LP4Y_EN = 0x0
3893 12:13:21.760464 WORK_FSP = 0x0
3894 12:13:21.761044 WL = 0x2
3895 12:13:21.763887 RL = 0x2
3896 12:13:21.764463 BL = 0x2
3897 12:13:21.766669 RPST = 0x0
3898 12:13:21.767141 RD_PRE = 0x0
3899 12:13:21.770382 WR_PRE = 0x1
3900 12:13:21.770965 WR_PST = 0x0
3901 12:13:21.773427 DBI_WR = 0x0
3902 12:13:21.777025 DBI_RD = 0x0
3903 12:13:21.777608 OTF = 0x1
3904 12:13:21.779871 ===================================
3905 12:13:21.786630 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3906 12:13:21.790619 nWR fixed to 30
3907 12:13:21.793685 [ModeRegInit_LP4] CH0 RK0
3908 12:13:21.794302 [ModeRegInit_LP4] CH0 RK1
3909 12:13:21.797112 [ModeRegInit_LP4] CH1 RK0
3910 12:13:21.800297 [ModeRegInit_LP4] CH1 RK1
3911 12:13:21.800776 match AC timing 17
3912 12:13:21.807399 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3913 12:13:21.810191 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3914 12:13:21.813631 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3915 12:13:21.820367 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3916 12:13:21.823941 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3917 12:13:21.824511 ==
3918 12:13:21.826634 Dram Type= 6, Freq= 0, CH_0, rank 0
3919 12:13:21.830029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3920 12:13:21.830579 ==
3921 12:13:21.836585 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3922 12:13:21.843358 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3923 12:13:21.846993 [CA 0] Center 36 (6~67) winsize 62
3924 12:13:21.850139 [CA 1] Center 36 (6~67) winsize 62
3925 12:13:21.853746 [CA 2] Center 34 (4~65) winsize 62
3926 12:13:21.856924 [CA 3] Center 34 (3~65) winsize 63
3927 12:13:21.860537 [CA 4] Center 33 (3~64) winsize 62
3928 12:13:21.863397 [CA 5] Center 33 (2~64) winsize 63
3929 12:13:21.863870
3930 12:13:21.866750 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3931 12:13:21.867218
3932 12:13:21.870358 [CATrainingPosCal] consider 1 rank data
3933 12:13:21.873384 u2DelayCellTimex100 = 270/100 ps
3934 12:13:21.876734 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3935 12:13:21.879847 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3936 12:13:21.883726 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3937 12:13:21.886652 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3938 12:13:21.890193 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3939 12:13:21.893240 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3940 12:13:21.897002
3941 12:13:21.899886 CA PerBit enable=1, Macro0, CA PI delay=33
3942 12:13:21.900356
3943 12:13:21.903081 [CBTSetCACLKResult] CA Dly = 33
3944 12:13:21.903548 CS Dly: 5 (0~36)
3945 12:13:21.903920 ==
3946 12:13:21.906457 Dram Type= 6, Freq= 0, CH_0, rank 1
3947 12:13:21.909806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3948 12:13:21.910449 ==
3949 12:13:21.917093 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3950 12:13:21.923261 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3951 12:13:21.926389 [CA 0] Center 36 (6~67) winsize 62
3952 12:13:21.929904 [CA 1] Center 36 (6~67) winsize 62
3953 12:13:21.933674 [CA 2] Center 35 (5~66) winsize 62
3954 12:13:21.936828 [CA 3] Center 35 (4~66) winsize 63
3955 12:13:21.939827 [CA 4] Center 34 (3~65) winsize 63
3956 12:13:21.943011 [CA 5] Center 34 (3~65) winsize 63
3957 12:13:21.943480
3958 12:13:21.946606 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3959 12:13:21.947175
3960 12:13:21.950031 [CATrainingPosCal] consider 2 rank data
3961 12:13:21.953720 u2DelayCellTimex100 = 270/100 ps
3962 12:13:21.956588 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3963 12:13:21.960403 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3964 12:13:21.963522 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3965 12:13:21.966312 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3966 12:13:21.973601 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3967 12:13:21.976525 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3968 12:13:21.977093
3969 12:13:21.979658 CA PerBit enable=1, Macro0, CA PI delay=33
3970 12:13:21.980225
3971 12:13:21.982876 [CBTSetCACLKResult] CA Dly = 33
3972 12:13:21.983505 CS Dly: 5 (0~37)
3973 12:13:21.983887
3974 12:13:21.986268 ----->DramcWriteLeveling(PI) begin...
3975 12:13:21.986747 ==
3976 12:13:21.989794 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 12:13:21.996648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 12:13:21.997276 ==
3979 12:13:21.999505 Write leveling (Byte 0): 33 => 33
3980 12:13:22.003218 Write leveling (Byte 1): 31 => 31
3981 12:13:22.003795 DramcWriteLeveling(PI) end<-----
3982 12:13:22.004167
3983 12:13:22.006667 ==
3984 12:13:22.007240 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 12:13:22.012995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 12:13:22.013577 ==
3987 12:13:22.016112 [Gating] SW mode calibration
3988 12:13:22.023131 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3989 12:13:22.026350 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3990 12:13:22.032679 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 12:13:22.036123 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3992 12:13:22.039558 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3993 12:13:22.046169 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (0 0) (0 0)
3994 12:13:22.049756 0 9 16 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
3995 12:13:22.052797 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 12:13:22.059313 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 12:13:22.062963 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 12:13:22.065741 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 12:13:22.072727 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 12:13:22.075804 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4001 12:13:22.079282 0 10 12 | B1->B0 | 2828 3939 | 1 1 | (0 0) (0 0)
4002 12:13:22.086033 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4003 12:13:22.089404 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 12:13:22.092404 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 12:13:22.099300 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 12:13:22.102735 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 12:13:22.106029 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 12:13:22.109233 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4009 12:13:22.115878 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4010 12:13:22.119288 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4011 12:13:22.122497 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 12:13:22.129175 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 12:13:22.132406 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 12:13:22.135442 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 12:13:22.142490 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 12:13:22.145895 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 12:13:22.149192 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 12:13:22.155655 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 12:13:22.158870 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 12:13:22.162129 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 12:13:22.168752 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 12:13:22.172641 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 12:13:22.175296 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 12:13:22.182352 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 12:13:22.185407 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4026 12:13:22.188533 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4027 12:13:22.191897 Total UI for P1: 0, mck2ui 16
4028 12:13:22.195638 best dqsien dly found for B0: ( 0, 13, 12)
4029 12:13:22.201816 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4030 12:13:22.202459 Total UI for P1: 0, mck2ui 16
4031 12:13:22.208847 best dqsien dly found for B1: ( 0, 13, 18)
4032 12:13:22.211880 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4033 12:13:22.215163 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4034 12:13:22.215758
4035 12:13:22.218398 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4036 12:13:22.221972 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4037 12:13:22.225227 [Gating] SW calibration Done
4038 12:13:22.225704 ==
4039 12:13:22.228423 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 12:13:22.231616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 12:13:22.232360 ==
4042 12:13:22.234869 RX Vref Scan: 0
4043 12:13:22.235345
4044 12:13:22.235720 RX Vref 0 -> 0, step: 1
4045 12:13:22.236068
4046 12:13:22.238700 RX Delay -230 -> 252, step: 16
4047 12:13:22.245044 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4048 12:13:22.248667 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4049 12:13:22.251658 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4050 12:13:22.254943 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4051 12:13:22.258806 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4052 12:13:22.264906 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4053 12:13:22.268090 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4054 12:13:22.271696 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4055 12:13:22.274793 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4056 12:13:22.281636 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4057 12:13:22.285265 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4058 12:13:22.288040 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4059 12:13:22.291886 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4060 12:13:22.298672 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4061 12:13:22.301428 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4062 12:13:22.304768 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4063 12:13:22.305341 ==
4064 12:13:22.308279 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 12:13:22.311539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 12:13:22.312121 ==
4067 12:13:22.314704 DQS Delay:
4068 12:13:22.315285 DQS0 = 0, DQS1 = 0
4069 12:13:22.318374 DQM Delay:
4070 12:13:22.318995 DQM0 = 49, DQM1 = 41
4071 12:13:22.319381 DQ Delay:
4072 12:13:22.321486 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4073 12:13:22.325010 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4074 12:13:22.328294 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4075 12:13:22.331581 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4076 12:13:22.332175
4077 12:13:22.332639
4078 12:13:22.334763 ==
4079 12:13:22.335238 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 12:13:22.341458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 12:13:22.342090 ==
4082 12:13:22.342481
4083 12:13:22.342828
4084 12:13:22.344466 TX Vref Scan disable
4085 12:13:22.344939 == TX Byte 0 ==
4086 12:13:22.348078 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4087 12:13:22.354870 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4088 12:13:22.355454 == TX Byte 1 ==
4089 12:13:22.358302 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4090 12:13:22.364701 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4091 12:13:22.365284 ==
4092 12:13:22.368158 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 12:13:22.371550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 12:13:22.372139 ==
4095 12:13:22.372516
4096 12:13:22.372907
4097 12:13:22.374556 TX Vref Scan disable
4098 12:13:22.378093 == TX Byte 0 ==
4099 12:13:22.381268 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4100 12:13:22.384625 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4101 12:13:22.388062 == TX Byte 1 ==
4102 12:13:22.391286 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4103 12:13:22.394673 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4104 12:13:22.395252
4105 12:13:22.398053 [DATLAT]
4106 12:13:22.398656 Freq=600, CH0 RK0
4107 12:13:22.399042
4108 12:13:22.401087 DATLAT Default: 0x9
4109 12:13:22.401558 0, 0xFFFF, sum = 0
4110 12:13:22.404518 1, 0xFFFF, sum = 0
4111 12:13:22.405110 2, 0xFFFF, sum = 0
4112 12:13:22.407599 3, 0xFFFF, sum = 0
4113 12:13:22.408081 4, 0xFFFF, sum = 0
4114 12:13:22.411407 5, 0xFFFF, sum = 0
4115 12:13:22.411888 6, 0xFFFF, sum = 0
4116 12:13:22.414996 7, 0xFFFF, sum = 0
4117 12:13:22.415586 8, 0x0, sum = 1
4118 12:13:22.417821 9, 0x0, sum = 2
4119 12:13:22.418346 10, 0x0, sum = 3
4120 12:13:22.420873 11, 0x0, sum = 4
4121 12:13:22.421368 best_step = 9
4122 12:13:22.421741
4123 12:13:22.422124 ==
4124 12:13:22.424728 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 12:13:22.427448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 12:13:22.431399 ==
4127 12:13:22.432020 RX Vref Scan: 1
4128 12:13:22.432407
4129 12:13:22.434269 RX Vref 0 -> 0, step: 1
4130 12:13:22.434742
4131 12:13:22.437424 RX Delay -179 -> 252, step: 8
4132 12:13:22.437899
4133 12:13:22.438321 Set Vref, RX VrefLevel [Byte0]: 57
4134 12:13:22.441084 [Byte1]: 51
4135 12:13:22.445831
4136 12:13:22.446458 Final RX Vref Byte 0 = 57 to rank0
4137 12:13:22.449497 Final RX Vref Byte 1 = 51 to rank0
4138 12:13:22.452752 Final RX Vref Byte 0 = 57 to rank1
4139 12:13:22.456224 Final RX Vref Byte 1 = 51 to rank1==
4140 12:13:22.459296 Dram Type= 6, Freq= 0, CH_0, rank 0
4141 12:13:22.465878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 12:13:22.466490 ==
4143 12:13:22.466869 DQS Delay:
4144 12:13:22.467215 DQS0 = 0, DQS1 = 0
4145 12:13:22.469246 DQM Delay:
4146 12:13:22.469810 DQM0 = 50, DQM1 = 39
4147 12:13:22.472633 DQ Delay:
4148 12:13:22.475872 DQ0 =48, DQ1 =52, DQ2 =48, DQ3 =44
4149 12:13:22.479074 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4150 12:13:22.482503 DQ8 =32, DQ9 =28, DQ10 =36, DQ11 =32
4151 12:13:22.485745 DQ12 =48, DQ13 =40, DQ14 =52, DQ15 =48
4152 12:13:22.486262
4153 12:13:22.486632
4154 12:13:22.492304 [DQSOSCAuto] RK0, (LSB)MR18= 0x5e59, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4155 12:13:22.495678 CH0 RK0: MR19=808, MR18=5E59
4156 12:13:22.502377 CH0_RK0: MR19=0x808, MR18=0x5E59, DQSOSC=392, MR23=63, INC=170, DEC=113
4157 12:13:22.502940
4158 12:13:22.505680 ----->DramcWriteLeveling(PI) begin...
4159 12:13:22.506350 ==
4160 12:13:22.508667 Dram Type= 6, Freq= 0, CH_0, rank 1
4161 12:13:22.512041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 12:13:22.512515 ==
4163 12:13:22.515582 Write leveling (Byte 0): 35 => 35
4164 12:13:22.519518 Write leveling (Byte 1): 32 => 32
4165 12:13:22.522498 DramcWriteLeveling(PI) end<-----
4166 12:13:22.522971
4167 12:13:22.523337 ==
4168 12:13:22.525559 Dram Type= 6, Freq= 0, CH_0, rank 1
4169 12:13:22.528856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 12:13:22.529424 ==
4171 12:13:22.532022 [Gating] SW mode calibration
4172 12:13:22.538790 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4173 12:13:22.545571 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4174 12:13:22.548945 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 12:13:22.555536 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 12:13:22.558859 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4177 12:13:22.562200 0 9 12 | B1->B0 | 3232 3434 | 1 0 | (1 1) (0 1)
4178 12:13:22.568481 0 9 16 | B1->B0 | 2b2b 2a2a | 0 0 | (0 0) (1 0)
4179 12:13:22.572308 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 12:13:22.575422 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 12:13:22.579125 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 12:13:22.585019 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 12:13:22.588830 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 12:13:22.591536 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 12:13:22.598550 0 10 12 | B1->B0 | 3030 2f2f | 0 1 | (1 1) (0 0)
4186 12:13:22.601392 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 12:13:22.605146 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 12:13:22.611684 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 12:13:22.615172 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 12:13:22.617928 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 12:13:22.625276 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 12:13:22.627985 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 12:13:22.631346 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4194 12:13:22.638086 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4195 12:13:22.641460 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 12:13:22.645329 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 12:13:22.651361 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 12:13:22.655033 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 12:13:22.658063 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 12:13:22.664783 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 12:13:22.667929 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 12:13:22.671606 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 12:13:22.677988 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 12:13:22.681477 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 12:13:22.684726 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 12:13:22.690937 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 12:13:22.694360 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 12:13:22.697859 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 12:13:22.704520 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 12:13:22.707939 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4211 12:13:22.711061 Total UI for P1: 0, mck2ui 16
4212 12:13:22.714129 best dqsien dly found for B0: ( 0, 13, 14)
4213 12:13:22.717508 Total UI for P1: 0, mck2ui 16
4214 12:13:22.720758 best dqsien dly found for B1: ( 0, 13, 14)
4215 12:13:22.724507 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4216 12:13:22.727650 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4217 12:13:22.728161
4218 12:13:22.730884 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4219 12:13:22.734181 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4220 12:13:22.737177 [Gating] SW calibration Done
4221 12:13:22.737650 ==
4222 12:13:22.740896 Dram Type= 6, Freq= 0, CH_0, rank 1
4223 12:13:22.744290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4224 12:13:22.747924 ==
4225 12:13:22.748397 RX Vref Scan: 0
4226 12:13:22.748777
4227 12:13:22.751084 RX Vref 0 -> 0, step: 1
4228 12:13:22.751555
4229 12:13:22.754361 RX Delay -230 -> 252, step: 16
4230 12:13:22.757332 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4231 12:13:22.760911 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4232 12:13:22.764224 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4233 12:13:22.771647 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4234 12:13:22.774103 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4235 12:13:22.777212 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4236 12:13:22.780720 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4237 12:13:22.784303 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4238 12:13:22.790860 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4239 12:13:22.794367 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4240 12:13:22.797637 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4241 12:13:22.800805 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4242 12:13:22.807439 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4243 12:13:22.810597 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4244 12:13:22.813634 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4245 12:13:22.817435 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4246 12:13:22.818082 ==
4247 12:13:22.820950 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 12:13:22.827103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 12:13:22.827581 ==
4250 12:13:22.827960 DQS Delay:
4251 12:13:22.830511 DQS0 = 0, DQS1 = 0
4252 12:13:22.830986 DQM Delay:
4253 12:13:22.831358 DQM0 = 48, DQM1 = 41
4254 12:13:22.834045 DQ Delay:
4255 12:13:22.836885 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =41
4256 12:13:22.840727 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4257 12:13:22.844147 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4258 12:13:22.847338 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4259 12:13:22.847920
4260 12:13:22.848294
4261 12:13:22.848638 ==
4262 12:13:22.850351 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 12:13:22.854008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 12:13:22.854598 ==
4265 12:13:22.855112
4266 12:13:22.855592
4267 12:13:22.856996 TX Vref Scan disable
4268 12:13:22.857508 == TX Byte 0 ==
4269 12:13:22.864388 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4270 12:13:22.867061 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4271 12:13:22.867641 == TX Byte 1 ==
4272 12:13:22.873918 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4273 12:13:22.876736 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4274 12:13:22.877214 ==
4275 12:13:22.880460 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 12:13:22.883818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 12:13:22.884396 ==
4278 12:13:22.886842
4279 12:13:22.887411
4280 12:13:22.887785 TX Vref Scan disable
4281 12:13:22.890814 == TX Byte 0 ==
4282 12:13:22.894138 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4283 12:13:22.897666 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4284 12:13:22.901091 == TX Byte 1 ==
4285 12:13:22.904639 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4286 12:13:22.907258 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4287 12:13:22.910622
4288 12:13:22.911093 [DATLAT]
4289 12:13:22.911468 Freq=600, CH0 RK1
4290 12:13:22.911822
4291 12:13:22.914058 DATLAT Default: 0x9
4292 12:13:22.914645 0, 0xFFFF, sum = 0
4293 12:13:22.917408 1, 0xFFFF, sum = 0
4294 12:13:22.917888 2, 0xFFFF, sum = 0
4295 12:13:22.920696 3, 0xFFFF, sum = 0
4296 12:13:22.921182 4, 0xFFFF, sum = 0
4297 12:13:22.923718 5, 0xFFFF, sum = 0
4298 12:13:22.927511 6, 0xFFFF, sum = 0
4299 12:13:22.927985 7, 0xFFFF, sum = 0
4300 12:13:22.928361 8, 0x0, sum = 1
4301 12:13:22.930691 9, 0x0, sum = 2
4302 12:13:22.931301 10, 0x0, sum = 3
4303 12:13:22.934067 11, 0x0, sum = 4
4304 12:13:22.934538 best_step = 9
4305 12:13:22.934903
4306 12:13:22.935242 ==
4307 12:13:22.937128 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 12:13:22.943963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 12:13:22.944430 ==
4310 12:13:22.944794 RX Vref Scan: 0
4311 12:13:22.945128
4312 12:13:22.947570 RX Vref 0 -> 0, step: 1
4313 12:13:22.948053
4314 12:13:22.950528 RX Delay -179 -> 252, step: 8
4315 12:13:22.954063 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4316 12:13:22.960409 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4317 12:13:22.963591 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4318 12:13:22.966903 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4319 12:13:22.970415 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4320 12:13:22.974105 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4321 12:13:22.980568 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4322 12:13:22.983693 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4323 12:13:22.986919 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4324 12:13:22.990535 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4325 12:13:22.993909 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4326 12:13:23.000726 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4327 12:13:23.003333 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4328 12:13:23.006935 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4329 12:13:23.010535 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4330 12:13:23.016746 iDelay=205, Bit 15, Center 48 (-99 ~ 196) 296
4331 12:13:23.017320 ==
4332 12:13:23.020024 Dram Type= 6, Freq= 0, CH_0, rank 1
4333 12:13:23.023022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4334 12:13:23.023487 ==
4335 12:13:23.023851 DQS Delay:
4336 12:13:23.026614 DQS0 = 0, DQS1 = 0
4337 12:13:23.027075 DQM Delay:
4338 12:13:23.029700 DQM0 = 47, DQM1 = 41
4339 12:13:23.030187 DQ Delay:
4340 12:13:23.032823 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4341 12:13:23.036183 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =52
4342 12:13:23.039763 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4343 12:13:23.042872 DQ12 =44, DQ13 =48, DQ14 =52, DQ15 =48
4344 12:13:23.043335
4345 12:13:23.043698
4346 12:13:23.053223 [DQSOSCAuto] RK1, (LSB)MR18= 0x5c2a, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
4347 12:13:23.053798 CH0 RK1: MR19=808, MR18=5C2A
4348 12:13:23.059517 CH0_RK1: MR19=0x808, MR18=0x5C2A, DQSOSC=392, MR23=63, INC=170, DEC=113
4349 12:13:23.062573 [RxdqsGatingPostProcess] freq 600
4350 12:13:23.069178 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4351 12:13:23.072836 Pre-setting of DQS Precalculation
4352 12:13:23.075732 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4353 12:13:23.076199 ==
4354 12:13:23.079369 Dram Type= 6, Freq= 0, CH_1, rank 0
4355 12:13:23.082671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4356 12:13:23.085880 ==
4357 12:13:23.089099 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4358 12:13:23.096631 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4359 12:13:23.099286 [CA 0] Center 35 (5~66) winsize 62
4360 12:13:23.103328 [CA 1] Center 35 (5~66) winsize 62
4361 12:13:23.105869 [CA 2] Center 34 (4~65) winsize 62
4362 12:13:23.109482 [CA 3] Center 33 (3~64) winsize 62
4363 12:13:23.112603 [CA 4] Center 34 (3~65) winsize 63
4364 12:13:23.115789 [CA 5] Center 33 (3~64) winsize 62
4365 12:13:23.116361
4366 12:13:23.119038 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4367 12:13:23.119604
4368 12:13:23.122517 [CATrainingPosCal] consider 1 rank data
4369 12:13:23.125827 u2DelayCellTimex100 = 270/100 ps
4370 12:13:23.128892 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4371 12:13:23.132386 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4372 12:13:23.135455 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4373 12:13:23.142603 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4374 12:13:23.145898 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4375 12:13:23.148951 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4376 12:13:23.149518
4377 12:13:23.152028 CA PerBit enable=1, Macro0, CA PI delay=33
4378 12:13:23.152500
4379 12:13:23.155571 [CBTSetCACLKResult] CA Dly = 33
4380 12:13:23.156138 CS Dly: 5 (0~36)
4381 12:13:23.156505 ==
4382 12:13:23.159197 Dram Type= 6, Freq= 0, CH_1, rank 1
4383 12:13:23.165369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4384 12:13:23.165925 ==
4385 12:13:23.168839 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4386 12:13:23.175413 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4387 12:13:23.178814 [CA 0] Center 35 (5~66) winsize 62
4388 12:13:23.182469 [CA 1] Center 35 (5~66) winsize 62
4389 12:13:23.185621 [CA 2] Center 34 (4~65) winsize 62
4390 12:13:23.188765 [CA 3] Center 34 (4~65) winsize 62
4391 12:13:23.192139 [CA 4] Center 34 (4~65) winsize 62
4392 12:13:23.196110 [CA 5] Center 34 (3~65) winsize 63
4393 12:13:23.196687
4394 12:13:23.199297 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4395 12:13:23.199871
4396 12:13:23.202326 [CATrainingPosCal] consider 2 rank data
4397 12:13:23.205477 u2DelayCellTimex100 = 270/100 ps
4398 12:13:23.208977 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4399 12:13:23.212215 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4400 12:13:23.218849 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4401 12:13:23.222263 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4402 12:13:23.225222 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4403 12:13:23.228878 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4404 12:13:23.229457
4405 12:13:23.231941 CA PerBit enable=1, Macro0, CA PI delay=33
4406 12:13:23.232517
4407 12:13:23.235294 [CBTSetCACLKResult] CA Dly = 33
4408 12:13:23.235772 CS Dly: 5 (0~37)
4409 12:13:23.238554
4410 12:13:23.241729 ----->DramcWriteLeveling(PI) begin...
4411 12:13:23.242355 ==
4412 12:13:23.245040 Dram Type= 6, Freq= 0, CH_1, rank 0
4413 12:13:23.249105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4414 12:13:23.249681 ==
4415 12:13:23.251809 Write leveling (Byte 0): 31 => 31
4416 12:13:23.255038 Write leveling (Byte 1): 31 => 31
4417 12:13:23.258577 DramcWriteLeveling(PI) end<-----
4418 12:13:23.259050
4419 12:13:23.259425 ==
4420 12:13:23.261574 Dram Type= 6, Freq= 0, CH_1, rank 0
4421 12:13:23.265400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 12:13:23.266034 ==
4423 12:13:23.268647 [Gating] SW mode calibration
4424 12:13:23.274891 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4425 12:13:23.282016 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4426 12:13:23.284905 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4427 12:13:23.288377 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4428 12:13:23.295135 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4429 12:13:23.298741 0 9 12 | B1->B0 | 2d2d 2d2d | 0 1 | (0 0) (1 0)
4430 12:13:23.301965 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 12:13:23.305245 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 12:13:23.311694 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 12:13:23.314745 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 12:13:23.318521 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 12:13:23.325488 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4436 12:13:23.328144 0 10 8 | B1->B0 | 2525 2626 | 0 0 | (0 0) (0 0)
4437 12:13:23.331885 0 10 12 | B1->B0 | 3d3d 4040 | 0 0 | (0 0) (0 0)
4438 12:13:23.338165 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 12:13:23.341174 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 12:13:23.344500 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 12:13:23.351445 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 12:13:23.354420 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 12:13:23.358015 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 12:13:23.364777 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4445 12:13:23.368143 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4446 12:13:23.371211 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 12:13:23.378446 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 12:13:23.381073 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 12:13:23.384412 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 12:13:23.391114 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 12:13:23.394383 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 12:13:23.398111 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 12:13:23.404479 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 12:13:23.407760 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 12:13:23.411129 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 12:13:23.418106 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 12:13:23.421172 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 12:13:23.424324 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 12:13:23.431005 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 12:13:23.434512 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4461 12:13:23.437370 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4462 12:13:23.444354 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 12:13:23.444949 Total UI for P1: 0, mck2ui 16
4464 12:13:23.447648 best dqsien dly found for B0: ( 0, 13, 10)
4465 12:13:23.451439 Total UI for P1: 0, mck2ui 16
4466 12:13:23.454661 best dqsien dly found for B1: ( 0, 13, 12)
4467 12:13:23.460743 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4468 12:13:23.464625 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4469 12:13:23.465206
4470 12:13:23.467831 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4471 12:13:23.470642 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4472 12:13:23.474246 [Gating] SW calibration Done
4473 12:13:23.474867 ==
4474 12:13:23.477507 Dram Type= 6, Freq= 0, CH_1, rank 0
4475 12:13:23.481039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4476 12:13:23.481624 ==
4477 12:13:23.484277 RX Vref Scan: 0
4478 12:13:23.484752
4479 12:13:23.485127 RX Vref 0 -> 0, step: 1
4480 12:13:23.485481
4481 12:13:23.487514 RX Delay -230 -> 252, step: 16
4482 12:13:23.490942 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4483 12:13:23.497905 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4484 12:13:23.501264 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4485 12:13:23.504650 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4486 12:13:23.507401 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4487 12:13:23.510858 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4488 12:13:23.517087 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4489 12:13:23.521006 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4490 12:13:23.524455 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4491 12:13:23.527488 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4492 12:13:23.534054 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4493 12:13:23.537277 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4494 12:13:23.540621 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4495 12:13:23.544227 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4496 12:13:23.550280 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4497 12:13:23.553832 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4498 12:13:23.554335 ==
4499 12:13:23.557533 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 12:13:23.560579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 12:13:23.561180 ==
4502 12:13:23.564256 DQS Delay:
4503 12:13:23.564909 DQS0 = 0, DQS1 = 0
4504 12:13:23.565295 DQM Delay:
4505 12:13:23.567121 DQM0 = 52, DQM1 = 42
4506 12:13:23.567589 DQ Delay:
4507 12:13:23.570359 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4508 12:13:23.573714 DQ4 =49, DQ5 =57, DQ6 =65, DQ7 =49
4509 12:13:23.576912 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4510 12:13:23.580379 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =49
4511 12:13:23.580998
4512 12:13:23.581435
4513 12:13:23.581837 ==
4514 12:13:23.583854 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 12:13:23.590094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 12:13:23.590562 ==
4517 12:13:23.590928
4518 12:13:23.591268
4519 12:13:23.591593 TX Vref Scan disable
4520 12:13:23.593711 == TX Byte 0 ==
4521 12:13:23.597254 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4522 12:13:23.603842 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4523 12:13:23.604312 == TX Byte 1 ==
4524 12:13:23.607523 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4525 12:13:23.613889 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4526 12:13:23.614506 ==
4527 12:13:23.617596 Dram Type= 6, Freq= 0, CH_1, rank 0
4528 12:13:23.620550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4529 12:13:23.621031 ==
4530 12:13:23.621447
4531 12:13:23.621808
4532 12:13:23.623453 TX Vref Scan disable
4533 12:13:23.627042 == TX Byte 0 ==
4534 12:13:23.630338 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4535 12:13:23.633268 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4536 12:13:23.636660 == TX Byte 1 ==
4537 12:13:23.639820 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4538 12:13:23.643164 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4539 12:13:23.643801
4540 12:13:23.644366 [DATLAT]
4541 12:13:23.646872 Freq=600, CH1 RK0
4542 12:13:23.647416
4543 12:13:23.647949 DATLAT Default: 0x9
4544 12:13:23.650085 0, 0xFFFF, sum = 0
4545 12:13:23.650496 1, 0xFFFF, sum = 0
4546 12:13:23.653580 2, 0xFFFF, sum = 0
4547 12:13:23.656755 3, 0xFFFF, sum = 0
4548 12:13:23.657389 4, 0xFFFF, sum = 0
4549 12:13:23.660266 5, 0xFFFF, sum = 0
4550 12:13:23.660739 6, 0xFFFF, sum = 0
4551 12:13:23.663222 7, 0xFFFF, sum = 0
4552 12:13:23.663695 8, 0x0, sum = 1
4553 12:13:23.664072 9, 0x0, sum = 2
4554 12:13:23.666457 10, 0x0, sum = 3
4555 12:13:23.666986 11, 0x0, sum = 4
4556 12:13:23.670004 best_step = 9
4557 12:13:23.670627
4558 12:13:23.671117 ==
4559 12:13:23.673391 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 12:13:23.676494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 12:13:23.677024 ==
4562 12:13:23.679838 RX Vref Scan: 1
4563 12:13:23.680301
4564 12:13:23.680666 RX Vref 0 -> 0, step: 1
4565 12:13:23.681008
4566 12:13:23.683180 RX Delay -179 -> 252, step: 8
4567 12:13:23.683649
4568 12:13:23.686488 Set Vref, RX VrefLevel [Byte0]: 53
4569 12:13:23.689740 [Byte1]: 53
4570 12:13:23.694306
4571 12:13:23.694873 Final RX Vref Byte 0 = 53 to rank0
4572 12:13:23.697504 Final RX Vref Byte 1 = 53 to rank0
4573 12:13:23.701045 Final RX Vref Byte 0 = 53 to rank1
4574 12:13:23.704069 Final RX Vref Byte 1 = 53 to rank1==
4575 12:13:23.707938 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 12:13:23.714392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 12:13:23.714961 ==
4578 12:13:23.715332 DQS Delay:
4579 12:13:23.715673 DQS0 = 0, DQS1 = 0
4580 12:13:23.717442 DQM Delay:
4581 12:13:23.717908 DQM0 = 48, DQM1 = 41
4582 12:13:23.720546 DQ Delay:
4583 12:13:23.724308 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4584 12:13:23.724881 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =44
4585 12:13:23.727527 DQ8 =28, DQ9 =24, DQ10 =44, DQ11 =36
4586 12:13:23.730685 DQ12 =52, DQ13 =48, DQ14 =48, DQ15 =48
4587 12:13:23.733894
4588 12:13:23.734559
4589 12:13:23.740491 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d74, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4590 12:13:23.743775 CH1 RK0: MR19=808, MR18=4D74
4591 12:13:23.750533 CH1_RK0: MR19=0x808, MR18=0x4D74, DQSOSC=388, MR23=63, INC=174, DEC=116
4592 12:13:23.751006
4593 12:13:23.754007 ----->DramcWriteLeveling(PI) begin...
4594 12:13:23.754536 ==
4595 12:13:23.757179 Dram Type= 6, Freq= 0, CH_1, rank 1
4596 12:13:23.760784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4597 12:13:23.761293 ==
4598 12:13:23.763976 Write leveling (Byte 0): 30 => 30
4599 12:13:23.767228 Write leveling (Byte 1): 30 => 30
4600 12:13:23.770600 DramcWriteLeveling(PI) end<-----
4601 12:13:23.771067
4602 12:13:23.771434 ==
4603 12:13:23.773655 Dram Type= 6, Freq= 0, CH_1, rank 1
4604 12:13:23.776895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 12:13:23.777417 ==
4606 12:13:23.780164 [Gating] SW mode calibration
4607 12:13:23.786925 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4608 12:13:23.793669 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4609 12:13:23.796805 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4610 12:13:23.804070 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4611 12:13:23.807047 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4612 12:13:23.810498 0 9 12 | B1->B0 | 2929 3131 | 1 1 | (1 0) (1 0)
4613 12:13:23.813416 0 9 16 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4614 12:13:23.820602 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 12:13:23.824289 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 12:13:23.827051 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 12:13:23.833768 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 12:13:23.836939 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4619 12:13:23.840196 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4620 12:13:23.846817 0 10 12 | B1->B0 | 3e3e 2e2e | 0 0 | (0 0) (0 0)
4621 12:13:23.850063 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 12:13:23.853741 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 12:13:23.860010 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 12:13:23.863643 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 12:13:23.867134 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 12:13:23.873278 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 12:13:23.876872 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4628 12:13:23.880057 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4629 12:13:23.886887 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 12:13:23.890052 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 12:13:23.893441 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 12:13:23.900172 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 12:13:23.903379 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 12:13:23.906412 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 12:13:23.913487 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 12:13:23.916634 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 12:13:23.919936 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 12:13:23.926837 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 12:13:23.930254 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 12:13:23.933490 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 12:13:23.939966 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 12:13:23.943531 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 12:13:23.946727 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4644 12:13:23.950097 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4645 12:13:23.957107 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4646 12:13:23.960383 Total UI for P1: 0, mck2ui 16
4647 12:13:23.963839 best dqsien dly found for B0: ( 0, 13, 10)
4648 12:13:23.966729 Total UI for P1: 0, mck2ui 16
4649 12:13:23.970252 best dqsien dly found for B1: ( 0, 13, 14)
4650 12:13:23.973647 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4651 12:13:23.976308 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4652 12:13:23.976787
4653 12:13:23.979621 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4654 12:13:23.983386 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4655 12:13:23.986178 [Gating] SW calibration Done
4656 12:13:23.986657 ==
4657 12:13:23.989893 Dram Type= 6, Freq= 0, CH_1, rank 1
4658 12:13:23.992842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4659 12:13:23.993425 ==
4660 12:13:23.996095 RX Vref Scan: 0
4661 12:13:23.996572
4662 12:13:24.000099 RX Vref 0 -> 0, step: 1
4663 12:13:24.000680
4664 12:13:24.001068 RX Delay -230 -> 252, step: 16
4665 12:13:24.006050 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4666 12:13:24.009701 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4667 12:13:24.012667 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4668 12:13:24.016689 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4669 12:13:24.022671 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4670 12:13:24.026435 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4671 12:13:24.029691 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4672 12:13:24.032913 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4673 12:13:24.036129 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4674 12:13:24.042702 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4675 12:13:24.046137 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4676 12:13:24.049662 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4677 12:13:24.053270 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4678 12:13:24.059291 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4679 12:13:24.062840 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4680 12:13:24.065814 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4681 12:13:24.066438 ==
4682 12:13:24.069566 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 12:13:24.072975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 12:13:24.075888 ==
4685 12:13:24.076464 DQS Delay:
4686 12:13:24.076840 DQS0 = 0, DQS1 = 0
4687 12:13:24.079534 DQM Delay:
4688 12:13:24.080048 DQM0 = 51, DQM1 = 45
4689 12:13:24.082694 DQ Delay:
4690 12:13:24.083166 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4691 12:13:24.085832 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4692 12:13:24.089271 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4693 12:13:24.092577 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4694 12:13:24.093158
4695 12:13:24.093533
4696 12:13:24.095654 ==
4697 12:13:24.099289 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 12:13:24.102646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 12:13:24.103231 ==
4700 12:13:24.103613
4701 12:13:24.103963
4702 12:13:24.105618 TX Vref Scan disable
4703 12:13:24.106200 == TX Byte 0 ==
4704 12:13:24.112334 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4705 12:13:24.116039 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4706 12:13:24.116520 == TX Byte 1 ==
4707 12:13:24.122595 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4708 12:13:24.126106 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4709 12:13:24.126685 ==
4710 12:13:24.129063 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 12:13:24.133056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 12:13:24.133646 ==
4713 12:13:24.134079
4714 12:13:24.134439
4715 12:13:24.135579 TX Vref Scan disable
4716 12:13:24.139485 == TX Byte 0 ==
4717 12:13:24.142450 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4718 12:13:24.145892 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4719 12:13:24.149069 == TX Byte 1 ==
4720 12:13:24.152441 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4721 12:13:24.155811 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4722 12:13:24.156397
4723 12:13:24.158948 [DATLAT]
4724 12:13:24.159529 Freq=600, CH1 RK1
4725 12:13:24.159911
4726 12:13:24.162606 DATLAT Default: 0x9
4727 12:13:24.163187 0, 0xFFFF, sum = 0
4728 12:13:24.166044 1, 0xFFFF, sum = 0
4729 12:13:24.166635 2, 0xFFFF, sum = 0
4730 12:13:24.168819 3, 0xFFFF, sum = 0
4731 12:13:24.169300 4, 0xFFFF, sum = 0
4732 12:13:24.172294 5, 0xFFFF, sum = 0
4733 12:13:24.172782 6, 0xFFFF, sum = 0
4734 12:13:24.175481 7, 0xFFFF, sum = 0
4735 12:13:24.175966 8, 0x0, sum = 1
4736 12:13:24.178971 9, 0x0, sum = 2
4737 12:13:24.179546 10, 0x0, sum = 3
4738 12:13:24.182056 11, 0x0, sum = 4
4739 12:13:24.182541 best_step = 9
4740 12:13:24.182916
4741 12:13:24.183267 ==
4742 12:13:24.185718 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 12:13:24.188883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 12:13:24.192095 ==
4745 12:13:24.192662 RX Vref Scan: 0
4746 12:13:24.193040
4747 12:13:24.195161 RX Vref 0 -> 0, step: 1
4748 12:13:24.195636
4749 12:13:24.198798 RX Delay -179 -> 252, step: 8
4750 12:13:24.202180 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4751 12:13:24.205420 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4752 12:13:24.212216 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4753 12:13:24.215286 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4754 12:13:24.218531 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4755 12:13:24.222043 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4756 12:13:24.225808 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4757 12:13:24.231993 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4758 12:13:24.235458 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4759 12:13:24.238619 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4760 12:13:24.241982 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4761 12:13:24.248452 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4762 12:13:24.251661 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4763 12:13:24.255356 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4764 12:13:24.258683 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4765 12:13:24.261435 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4766 12:13:24.265125 ==
4767 12:13:24.265697 Dram Type= 6, Freq= 0, CH_1, rank 1
4768 12:13:24.271352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4769 12:13:24.271867 ==
4770 12:13:24.272253 DQS Delay:
4771 12:13:24.275220 DQS0 = 0, DQS1 = 0
4772 12:13:24.275796 DQM Delay:
4773 12:13:24.278057 DQM0 = 49, DQM1 = 43
4774 12:13:24.278534 DQ Delay:
4775 12:13:24.281488 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =48
4776 12:13:24.284889 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4777 12:13:24.288202 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4778 12:13:24.291561 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =56
4779 12:13:24.292038
4780 12:13:24.292411
4781 12:13:24.298012 [DQSOSCAuto] RK1, (LSB)MR18= 0x5218, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
4782 12:13:24.301718 CH1 RK1: MR19=808, MR18=5218
4783 12:13:24.308007 CH1_RK1: MR19=0x808, MR18=0x5218, DQSOSC=394, MR23=63, INC=168, DEC=112
4784 12:13:24.311377 [RxdqsGatingPostProcess] freq 600
4785 12:13:24.317866 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4786 12:13:24.318476 Pre-setting of DQS Precalculation
4787 12:13:24.325165 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4788 12:13:24.331246 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4789 12:13:24.338089 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4790 12:13:24.338813
4791 12:13:24.339204
4792 12:13:24.341116 [Calibration Summary] 1200 Mbps
4793 12:13:24.344577 CH 0, Rank 0
4794 12:13:24.345061 SW Impedance : PASS
4795 12:13:24.348115 DUTY Scan : NO K
4796 12:13:24.350915 ZQ Calibration : PASS
4797 12:13:24.351412 Jitter Meter : NO K
4798 12:13:24.354288 CBT Training : PASS
4799 12:13:24.354859 Write leveling : PASS
4800 12:13:24.357846 RX DQS gating : PASS
4801 12:13:24.360983 RX DQ/DQS(RDDQC) : PASS
4802 12:13:24.361460 TX DQ/DQS : PASS
4803 12:13:24.364396 RX DATLAT : PASS
4804 12:13:24.367487 RX DQ/DQS(Engine): PASS
4805 12:13:24.368054 TX OE : NO K
4806 12:13:24.370799 All Pass.
4807 12:13:24.371389
4808 12:13:24.371768 CH 0, Rank 1
4809 12:13:24.374112 SW Impedance : PASS
4810 12:13:24.374677 DUTY Scan : NO K
4811 12:13:24.377560 ZQ Calibration : PASS
4812 12:13:24.380680 Jitter Meter : NO K
4813 12:13:24.381157 CBT Training : PASS
4814 12:13:24.384298 Write leveling : PASS
4815 12:13:24.387728 RX DQS gating : PASS
4816 12:13:24.388301 RX DQ/DQS(RDDQC) : PASS
4817 12:13:24.390523 TX DQ/DQS : PASS
4818 12:13:24.394113 RX DATLAT : PASS
4819 12:13:24.394710 RX DQ/DQS(Engine): PASS
4820 12:13:24.397513 TX OE : NO K
4821 12:13:24.398063 All Pass.
4822 12:13:24.398451
4823 12:13:24.400552 CH 1, Rank 0
4824 12:13:24.401265 SW Impedance : PASS
4825 12:13:24.403820 DUTY Scan : NO K
4826 12:13:24.407607 ZQ Calibration : PASS
4827 12:13:24.408178 Jitter Meter : NO K
4828 12:13:24.410707 CBT Training : PASS
4829 12:13:24.413783 Write leveling : PASS
4830 12:13:24.414387 RX DQS gating : PASS
4831 12:13:24.417316 RX DQ/DQS(RDDQC) : PASS
4832 12:13:24.417887 TX DQ/DQS : PASS
4833 12:13:24.420361 RX DATLAT : PASS
4834 12:13:24.423762 RX DQ/DQS(Engine): PASS
4835 12:13:24.424238 TX OE : NO K
4836 12:13:24.427231 All Pass.
4837 12:13:24.427802
4838 12:13:24.428176 CH 1, Rank 1
4839 12:13:24.430809 SW Impedance : PASS
4840 12:13:24.431286 DUTY Scan : NO K
4841 12:13:24.433619 ZQ Calibration : PASS
4842 12:13:24.437513 Jitter Meter : NO K
4843 12:13:24.438115 CBT Training : PASS
4844 12:13:24.440454 Write leveling : PASS
4845 12:13:24.443533 RX DQS gating : PASS
4846 12:13:24.444014 RX DQ/DQS(RDDQC) : PASS
4847 12:13:24.446974 TX DQ/DQS : PASS
4848 12:13:24.450683 RX DATLAT : PASS
4849 12:13:24.451254 RX DQ/DQS(Engine): PASS
4850 12:13:24.453859 TX OE : NO K
4851 12:13:24.454474 All Pass.
4852 12:13:24.454858
4853 12:13:24.457231 DramC Write-DBI off
4854 12:13:24.460649 PER_BANK_REFRESH: Hybrid Mode
4855 12:13:24.461222 TX_TRACKING: ON
4856 12:13:24.470641 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4857 12:13:24.473690 [FAST_K] Save calibration result to emmc
4858 12:13:24.477047 dramc_set_vcore_voltage set vcore to 662500
4859 12:13:24.480604 Read voltage for 933, 3
4860 12:13:24.481080 Vio18 = 0
4861 12:13:24.481457 Vcore = 662500
4862 12:13:24.483507 Vdram = 0
4863 12:13:24.483981 Vddq = 0
4864 12:13:24.484357 Vmddr = 0
4865 12:13:24.490394 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4866 12:13:24.493890 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4867 12:13:24.497049 MEM_TYPE=3, freq_sel=17
4868 12:13:24.500599 sv_algorithm_assistance_LP4_1600
4869 12:13:24.504812 ============ PULL DRAM RESETB DOWN ============
4870 12:13:24.506833 ========== PULL DRAM RESETB DOWN end =========
4871 12:13:24.513549 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4872 12:13:24.516895 ===================================
4873 12:13:24.517388 LPDDR4 DRAM CONFIGURATION
4874 12:13:24.520160 ===================================
4875 12:13:24.523296 EX_ROW_EN[0] = 0x0
4876 12:13:24.526454 EX_ROW_EN[1] = 0x0
4877 12:13:24.526966 LP4Y_EN = 0x0
4878 12:13:24.530173 WORK_FSP = 0x0
4879 12:13:24.530729 WL = 0x3
4880 12:13:24.533469 RL = 0x3
4881 12:13:24.534074 BL = 0x2
4882 12:13:24.536400 RPST = 0x0
4883 12:13:24.536863 RD_PRE = 0x0
4884 12:13:24.540319 WR_PRE = 0x1
4885 12:13:24.540888 WR_PST = 0x0
4886 12:13:24.543260 DBI_WR = 0x0
4887 12:13:24.543891 DBI_RD = 0x0
4888 12:13:24.546552 OTF = 0x1
4889 12:13:24.550184 ===================================
4890 12:13:24.553177 ===================================
4891 12:13:24.553739 ANA top config
4892 12:13:24.556686 ===================================
4893 12:13:24.559787 DLL_ASYNC_EN = 0
4894 12:13:24.563444 ALL_SLAVE_EN = 1
4895 12:13:24.566501 NEW_RANK_MODE = 1
4896 12:13:24.567065 DLL_IDLE_MODE = 1
4897 12:13:24.569679 LP45_APHY_COMB_EN = 1
4898 12:13:24.573383 TX_ODT_DIS = 1
4899 12:13:24.576762 NEW_8X_MODE = 1
4900 12:13:24.579439 ===================================
4901 12:13:24.583480 ===================================
4902 12:13:24.586875 data_rate = 1866
4903 12:13:24.587436 CKR = 1
4904 12:13:24.589619 DQ_P2S_RATIO = 8
4905 12:13:24.593551 ===================================
4906 12:13:24.596457 CA_P2S_RATIO = 8
4907 12:13:24.599694 DQ_CA_OPEN = 0
4908 12:13:24.603051 DQ_SEMI_OPEN = 0
4909 12:13:24.606541 CA_SEMI_OPEN = 0
4910 12:13:24.607149 CA_FULL_RATE = 0
4911 12:13:24.610233 DQ_CKDIV4_EN = 1
4912 12:13:24.613367 CA_CKDIV4_EN = 1
4913 12:13:24.616225 CA_PREDIV_EN = 0
4914 12:13:24.619803 PH8_DLY = 0
4915 12:13:24.620394 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4916 12:13:24.622780 DQ_AAMCK_DIV = 4
4917 12:13:24.626211 CA_AAMCK_DIV = 4
4918 12:13:24.630038 CA_ADMCK_DIV = 4
4919 12:13:24.632958 DQ_TRACK_CA_EN = 0
4920 12:13:24.636570 CA_PICK = 933
4921 12:13:24.639659 CA_MCKIO = 933
4922 12:13:24.640147 MCKIO_SEMI = 0
4923 12:13:24.642865 PLL_FREQ = 3732
4924 12:13:24.646247 DQ_UI_PI_RATIO = 32
4925 12:13:24.649873 CA_UI_PI_RATIO = 0
4926 12:13:24.652808 ===================================
4927 12:13:24.656839 ===================================
4928 12:13:24.659738 memory_type:LPDDR4
4929 12:13:24.660206 GP_NUM : 10
4930 12:13:24.663150 SRAM_EN : 1
4931 12:13:24.666573 MD32_EN : 0
4932 12:13:24.669631 ===================================
4933 12:13:24.670248 [ANA_INIT] >>>>>>>>>>>>>>
4934 12:13:24.673162 <<<<<< [CONFIGURE PHASE]: ANA_TX
4935 12:13:24.676431 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4936 12:13:24.679907 ===================================
4937 12:13:24.683072 data_rate = 1866,PCW = 0X8f00
4938 12:13:24.686494 ===================================
4939 12:13:24.689744 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4940 12:13:24.696086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4941 12:13:24.699756 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4942 12:13:24.706639 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4943 12:13:24.709839 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4944 12:13:24.713198 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4945 12:13:24.713775 [ANA_INIT] flow start
4946 12:13:24.716500 [ANA_INIT] PLL >>>>>>>>
4947 12:13:24.719569 [ANA_INIT] PLL <<<<<<<<
4948 12:13:24.720145 [ANA_INIT] MIDPI >>>>>>>>
4949 12:13:24.722750 [ANA_INIT] MIDPI <<<<<<<<
4950 12:13:24.726356 [ANA_INIT] DLL >>>>>>>>
4951 12:13:24.726926 [ANA_INIT] flow end
4952 12:13:24.733141 ============ LP4 DIFF to SE enter ============
4953 12:13:24.736224 ============ LP4 DIFF to SE exit ============
4954 12:13:24.739467 [ANA_INIT] <<<<<<<<<<<<<
4955 12:13:24.742979 [Flow] Enable top DCM control >>>>>
4956 12:13:24.746016 [Flow] Enable top DCM control <<<<<
4957 12:13:24.746496 Enable DLL master slave shuffle
4958 12:13:24.752957 ==============================================================
4959 12:13:24.755977 Gating Mode config
4960 12:13:24.759346 ==============================================================
4961 12:13:24.762793 Config description:
4962 12:13:24.772756 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4963 12:13:24.779217 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4964 12:13:24.782804 SELPH_MODE 0: By rank 1: By Phase
4965 12:13:24.789103 ==============================================================
4966 12:13:24.792427 GAT_TRACK_EN = 1
4967 12:13:24.795670 RX_GATING_MODE = 2
4968 12:13:24.799124 RX_GATING_TRACK_MODE = 2
4969 12:13:24.802070 SELPH_MODE = 1
4970 12:13:24.802564 PICG_EARLY_EN = 1
4971 12:13:24.805679 VALID_LAT_VALUE = 1
4972 12:13:24.812504 ==============================================================
4973 12:13:24.815603 Enter into Gating configuration >>>>
4974 12:13:24.818866 Exit from Gating configuration <<<<
4975 12:13:24.822119 Enter into DVFS_PRE_config >>>>>
4976 12:13:24.832051 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4977 12:13:24.835565 Exit from DVFS_PRE_config <<<<<
4978 12:13:24.838559 Enter into PICG configuration >>>>
4979 12:13:24.842308 Exit from PICG configuration <<<<
4980 12:13:24.845178 [RX_INPUT] configuration >>>>>
4981 12:13:24.848892 [RX_INPUT] configuration <<<<<
4982 12:13:24.851746 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4983 12:13:24.858762 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4984 12:13:24.865375 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4985 12:13:24.871824 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4986 12:13:24.878396 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4987 12:13:24.885238 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4988 12:13:24.888249 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4989 12:13:24.891589 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4990 12:13:24.895057 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4991 12:13:24.901995 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4992 12:13:24.905256 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4993 12:13:24.908262 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4994 12:13:24.911660 ===================================
4995 12:13:24.914950 LPDDR4 DRAM CONFIGURATION
4996 12:13:24.918204 ===================================
4997 12:13:24.918780 EX_ROW_EN[0] = 0x0
4998 12:13:24.921575 EX_ROW_EN[1] = 0x0
4999 12:13:24.922190 LP4Y_EN = 0x0
5000 12:13:24.924895 WORK_FSP = 0x0
5001 12:13:24.928498 WL = 0x3
5002 12:13:24.929084 RL = 0x3
5003 12:13:24.931648 BL = 0x2
5004 12:13:24.932230 RPST = 0x0
5005 12:13:24.935105 RD_PRE = 0x0
5006 12:13:24.935704 WR_PRE = 0x1
5007 12:13:24.938091 WR_PST = 0x0
5008 12:13:24.938665 DBI_WR = 0x0
5009 12:13:24.941221 DBI_RD = 0x0
5010 12:13:24.941721 OTF = 0x1
5011 12:13:24.944958 ===================================
5012 12:13:24.948172 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5013 12:13:24.954532 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5014 12:13:24.958078 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5015 12:13:24.961208 ===================================
5016 12:13:24.964881 LPDDR4 DRAM CONFIGURATION
5017 12:13:24.967823 ===================================
5018 12:13:24.968299 EX_ROW_EN[0] = 0x10
5019 12:13:24.971018 EX_ROW_EN[1] = 0x0
5020 12:13:24.971491 LP4Y_EN = 0x0
5021 12:13:24.974378 WORK_FSP = 0x0
5022 12:13:24.974965 WL = 0x3
5023 12:13:24.978157 RL = 0x3
5024 12:13:24.978734 BL = 0x2
5025 12:13:24.981321 RPST = 0x0
5026 12:13:24.984456 RD_PRE = 0x0
5027 12:13:24.985038 WR_PRE = 0x1
5028 12:13:24.988165 WR_PST = 0x0
5029 12:13:24.988745 DBI_WR = 0x0
5030 12:13:24.991464 DBI_RD = 0x0
5031 12:13:24.992046 OTF = 0x1
5032 12:13:24.994608 ===================================
5033 12:13:25.000916 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5034 12:13:25.005219 nWR fixed to 30
5035 12:13:25.008095 [ModeRegInit_LP4] CH0 RK0
5036 12:13:25.008575 [ModeRegInit_LP4] CH0 RK1
5037 12:13:25.011415 [ModeRegInit_LP4] CH1 RK0
5038 12:13:25.014610 [ModeRegInit_LP4] CH1 RK1
5039 12:13:25.015084 match AC timing 9
5040 12:13:25.021726 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5041 12:13:25.024829 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5042 12:13:25.028116 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5043 12:13:25.034819 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5044 12:13:25.038307 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5045 12:13:25.038892 ==
5046 12:13:25.041149 Dram Type= 6, Freq= 0, CH_0, rank 0
5047 12:13:25.044630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5048 12:13:25.045269 ==
5049 12:13:25.051544 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5050 12:13:25.057915 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5051 12:13:25.061096 [CA 0] Center 38 (7~69) winsize 63
5052 12:13:25.065025 [CA 1] Center 38 (8~69) winsize 62
5053 12:13:25.067671 [CA 2] Center 35 (5~66) winsize 62
5054 12:13:25.071036 [CA 3] Center 35 (4~66) winsize 63
5055 12:13:25.074543 [CA 4] Center 35 (5~65) winsize 61
5056 12:13:25.078149 [CA 5] Center 33 (3~64) winsize 62
5057 12:13:25.078729
5058 12:13:25.081009 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5059 12:13:25.081485
5060 12:13:25.084732 [CATrainingPosCal] consider 1 rank data
5061 12:13:25.087951 u2DelayCellTimex100 = 270/100 ps
5062 12:13:25.091534 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5063 12:13:25.094534 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5064 12:13:25.097992 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5065 12:13:25.101453 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5066 12:13:25.104667 CA4 delay=35 (5~65),Diff = 2 PI (12 cell)
5067 12:13:25.111485 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5068 12:13:25.112063
5069 12:13:25.114404 CA PerBit enable=1, Macro0, CA PI delay=33
5070 12:13:25.114885
5071 12:13:25.117626 [CBTSetCACLKResult] CA Dly = 33
5072 12:13:25.118312 CS Dly: 7 (0~38)
5073 12:13:25.118704 ==
5074 12:13:25.121265 Dram Type= 6, Freq= 0, CH_0, rank 1
5075 12:13:25.124379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5076 12:13:25.127618 ==
5077 12:13:25.131012 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5078 12:13:25.137427 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5079 12:13:25.140798 [CA 0] Center 38 (8~69) winsize 62
5080 12:13:25.144442 [CA 1] Center 38 (8~69) winsize 62
5081 12:13:25.147498 [CA 2] Center 36 (6~67) winsize 62
5082 12:13:25.150945 [CA 3] Center 36 (5~67) winsize 63
5083 12:13:25.154489 [CA 4] Center 34 (4~65) winsize 62
5084 12:13:25.157654 [CA 5] Center 34 (4~64) winsize 61
5085 12:13:25.158281
5086 12:13:25.160858 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5087 12:13:25.161433
5088 12:13:25.164261 [CATrainingPosCal] consider 2 rank data
5089 12:13:25.167239 u2DelayCellTimex100 = 270/100 ps
5090 12:13:25.170401 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5091 12:13:25.174043 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5092 12:13:25.177996 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5093 12:13:25.180690 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5094 12:13:25.187516 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5095 12:13:25.190835 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5096 12:13:25.191404
5097 12:13:25.194085 CA PerBit enable=1, Macro0, CA PI delay=34
5098 12:13:25.194654
5099 12:13:25.197566 [CBTSetCACLKResult] CA Dly = 34
5100 12:13:25.198170 CS Dly: 7 (0~39)
5101 12:13:25.198551
5102 12:13:25.200712 ----->DramcWriteLeveling(PI) begin...
5103 12:13:25.201240 ==
5104 12:13:25.203869 Dram Type= 6, Freq= 0, CH_0, rank 0
5105 12:13:25.210809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5106 12:13:25.211379 ==
5107 12:13:25.214025 Write leveling (Byte 0): 31 => 31
5108 12:13:25.217681 Write leveling (Byte 1): 28 => 28
5109 12:13:25.218305 DramcWriteLeveling(PI) end<-----
5110 12:13:25.218685
5111 12:13:25.220569 ==
5112 12:13:25.224052 Dram Type= 6, Freq= 0, CH_0, rank 0
5113 12:13:25.227161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 12:13:25.227740 ==
5115 12:13:25.230598 [Gating] SW mode calibration
5116 12:13:25.237613 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5117 12:13:25.240769 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5118 12:13:25.247128 0 14 0 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
5119 12:13:25.250495 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 12:13:25.254009 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 12:13:25.260483 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 12:13:25.264434 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5123 12:13:25.267034 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5124 12:13:25.274080 0 14 24 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5125 12:13:25.276963 0 14 28 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (1 0)
5126 12:13:25.280615 0 15 0 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
5127 12:13:25.287335 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 12:13:25.290766 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 12:13:25.294083 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 12:13:25.300709 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5131 12:13:25.303956 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5132 12:13:25.307236 0 15 24 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
5133 12:13:25.313848 0 15 28 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
5134 12:13:25.316997 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5135 12:13:25.320223 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 12:13:25.324360 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 12:13:25.330689 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 12:13:25.333494 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 12:13:25.337105 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5140 12:13:25.343381 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5141 12:13:25.346764 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5142 12:13:25.350140 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5143 12:13:25.356780 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 12:13:25.360330 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 12:13:25.363096 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 12:13:25.370150 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 12:13:25.373070 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 12:13:25.376457 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 12:13:25.382874 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 12:13:25.386291 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 12:13:25.389643 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 12:13:25.396454 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 12:13:25.399960 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 12:13:25.403077 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 12:13:25.409760 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 12:13:25.413169 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 12:13:25.416891 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5158 12:13:25.423118 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5159 12:13:25.423694 Total UI for P1: 0, mck2ui 16
5160 12:13:25.429650 best dqsien dly found for B0: ( 1, 2, 28)
5161 12:13:25.433017 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5162 12:13:25.436356 Total UI for P1: 0, mck2ui 16
5163 12:13:25.439531 best dqsien dly found for B1: ( 1, 2, 30)
5164 12:13:25.443001 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5165 12:13:25.446902 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5166 12:13:25.447552
5167 12:13:25.449269 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5168 12:13:25.452903 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5169 12:13:25.456174 [Gating] SW calibration Done
5170 12:13:25.456746 ==
5171 12:13:25.459395 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 12:13:25.463011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 12:13:25.465735 ==
5174 12:13:25.466252 RX Vref Scan: 0
5175 12:13:25.466625
5176 12:13:25.469370 RX Vref 0 -> 0, step: 1
5177 12:13:25.469973
5178 12:13:25.472324 RX Delay -80 -> 252, step: 8
5179 12:13:25.475791 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5180 12:13:25.479145 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5181 12:13:25.482536 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5182 12:13:25.485673 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5183 12:13:25.489169 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5184 12:13:25.496202 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5185 12:13:25.499117 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5186 12:13:25.502330 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5187 12:13:25.505513 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5188 12:13:25.509002 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5189 12:13:25.515656 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5190 12:13:25.519189 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5191 12:13:25.522468 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5192 12:13:25.526321 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5193 12:13:25.529137 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5194 12:13:25.532421 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5195 12:13:25.535502 ==
5196 12:13:25.535978 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 12:13:25.542369 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 12:13:25.542943 ==
5199 12:13:25.543317 DQS Delay:
5200 12:13:25.545798 DQS0 = 0, DQS1 = 0
5201 12:13:25.546397 DQM Delay:
5202 12:13:25.549070 DQM0 = 105, DQM1 = 91
5203 12:13:25.549633 DQ Delay:
5204 12:13:25.552384 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5205 12:13:25.555819 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5206 12:13:25.558897 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =91
5207 12:13:25.562312 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =99
5208 12:13:25.562882
5209 12:13:25.563257
5210 12:13:25.563598 ==
5211 12:13:25.565563 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 12:13:25.568898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 12:13:25.569470 ==
5214 12:13:25.569844
5215 12:13:25.570243
5216 12:13:25.571965 TX Vref Scan disable
5217 12:13:25.575583 == TX Byte 0 ==
5218 12:13:25.578655 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5219 12:13:25.581709 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5220 12:13:25.585216 == TX Byte 1 ==
5221 12:13:25.588783 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5222 12:13:25.592354 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5223 12:13:25.592948 ==
5224 12:13:25.595299 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 12:13:25.602085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 12:13:25.602677 ==
5227 12:13:25.603056
5228 12:13:25.603402
5229 12:13:25.603734 TX Vref Scan disable
5230 12:13:25.606318 == TX Byte 0 ==
5231 12:13:25.609571 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5232 12:13:25.615777 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5233 12:13:25.616336 == TX Byte 1 ==
5234 12:13:25.619318 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5235 12:13:25.626140 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5236 12:13:25.626727
5237 12:13:25.627102 [DATLAT]
5238 12:13:25.627448 Freq=933, CH0 RK0
5239 12:13:25.627784
5240 12:13:25.629260 DATLAT Default: 0xd
5241 12:13:25.629728 0, 0xFFFF, sum = 0
5242 12:13:25.632435 1, 0xFFFF, sum = 0
5243 12:13:25.633004 2, 0xFFFF, sum = 0
5244 12:13:25.635820 3, 0xFFFF, sum = 0
5245 12:13:25.639254 4, 0xFFFF, sum = 0
5246 12:13:25.639824 5, 0xFFFF, sum = 0
5247 12:13:25.642514 6, 0xFFFF, sum = 0
5248 12:13:25.642993 7, 0xFFFF, sum = 0
5249 12:13:25.645826 8, 0xFFFF, sum = 0
5250 12:13:25.646491 9, 0xFFFF, sum = 0
5251 12:13:25.649063 10, 0x0, sum = 1
5252 12:13:25.649641 11, 0x0, sum = 2
5253 12:13:25.652573 12, 0x0, sum = 3
5254 12:13:25.653049 13, 0x0, sum = 4
5255 12:13:25.653423 best_step = 11
5256 12:13:25.653761
5257 12:13:25.655644 ==
5258 12:13:25.659237 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 12:13:25.662307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 12:13:25.662950 ==
5261 12:13:25.663342 RX Vref Scan: 1
5262 12:13:25.663688
5263 12:13:25.665563 RX Vref 0 -> 0, step: 1
5264 12:13:25.666066
5265 12:13:25.669166 RX Delay -53 -> 252, step: 4
5266 12:13:25.669736
5267 12:13:25.672521 Set Vref, RX VrefLevel [Byte0]: 57
5268 12:13:25.675650 [Byte1]: 51
5269 12:13:25.676221
5270 12:13:25.679038 Final RX Vref Byte 0 = 57 to rank0
5271 12:13:25.681977 Final RX Vref Byte 1 = 51 to rank0
5272 12:13:25.685523 Final RX Vref Byte 0 = 57 to rank1
5273 12:13:25.689386 Final RX Vref Byte 1 = 51 to rank1==
5274 12:13:25.692354 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 12:13:25.695574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 12:13:25.696062 ==
5277 12:13:25.698664 DQS Delay:
5278 12:13:25.699129 DQS0 = 0, DQS1 = 0
5279 12:13:25.702118 DQM Delay:
5280 12:13:25.702583 DQM0 = 107, DQM1 = 92
5281 12:13:25.706083 DQ Delay:
5282 12:13:25.708900 DQ0 =108, DQ1 =106, DQ2 =104, DQ3 =106
5283 12:13:25.712388 DQ4 =108, DQ5 =98, DQ6 =116, DQ7 =114
5284 12:13:25.715724 DQ8 =86, DQ9 =78, DQ10 =92, DQ11 =90
5285 12:13:25.718720 DQ12 =96, DQ13 =92, DQ14 =102, DQ15 =100
5286 12:13:25.719286
5287 12:13:25.719654
5288 12:13:25.726068 [DQSOSCAuto] RK0, (LSB)MR18= 0x2723, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
5289 12:13:25.728904 CH0 RK0: MR19=505, MR18=2723
5290 12:13:25.735788 CH0_RK0: MR19=0x505, MR18=0x2723, DQSOSC=409, MR23=63, INC=64, DEC=43
5291 12:13:25.736357
5292 12:13:25.738823 ----->DramcWriteLeveling(PI) begin...
5293 12:13:25.739392 ==
5294 12:13:25.741987 Dram Type= 6, Freq= 0, CH_0, rank 1
5295 12:13:25.745843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 12:13:25.746459 ==
5297 12:13:25.748872 Write leveling (Byte 0): 30 => 30
5298 12:13:25.751770 Write leveling (Byte 1): 30 => 30
5299 12:13:25.755071 DramcWriteLeveling(PI) end<-----
5300 12:13:25.755531
5301 12:13:25.755890 ==
5302 12:13:25.759350 Dram Type= 6, Freq= 0, CH_0, rank 1
5303 12:13:25.761788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 12:13:25.762292 ==
5305 12:13:25.765398 [Gating] SW mode calibration
5306 12:13:25.771875 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5307 12:13:25.778689 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5308 12:13:25.782206 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 12:13:25.788129 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 12:13:25.791443 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 12:13:25.795084 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 12:13:25.801592 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5313 12:13:25.804936 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5314 12:13:25.808264 0 14 24 | B1->B0 | 3333 3232 | 1 1 | (1 1) (1 1)
5315 12:13:25.814684 0 14 28 | B1->B0 | 2d2d 2525 | 1 0 | (1 0) (0 0)
5316 12:13:25.818511 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 12:13:25.821621 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 12:13:25.828293 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 12:13:25.831549 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 12:13:25.835141 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 12:13:25.838401 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5322 12:13:25.844669 0 15 24 | B1->B0 | 2828 2828 | 0 0 | (0 0) (0 0)
5323 12:13:25.847976 0 15 28 | B1->B0 | 3938 4242 | 1 0 | (0 0) (0 0)
5324 12:13:25.851479 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 12:13:25.858284 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 12:13:25.861338 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 12:13:25.864955 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 12:13:25.871867 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 12:13:25.874501 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 12:13:25.878373 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 12:13:25.885337 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5332 12:13:25.888173 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 12:13:25.891260 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 12:13:25.898232 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 12:13:25.901807 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 12:13:25.904263 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 12:13:25.911074 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 12:13:25.914633 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 12:13:25.918176 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 12:13:25.924547 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 12:13:25.927880 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 12:13:25.930860 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 12:13:25.937420 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 12:13:25.941036 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 12:13:25.944280 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 12:13:25.950928 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5347 12:13:25.954167 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5348 12:13:25.957683 Total UI for P1: 0, mck2ui 16
5349 12:13:25.960917 best dqsien dly found for B0: ( 1, 2, 24)
5350 12:13:25.964239 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 12:13:25.967470 Total UI for P1: 0, mck2ui 16
5352 12:13:25.970578 best dqsien dly found for B1: ( 1, 2, 26)
5353 12:13:25.974168 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5354 12:13:25.977306 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5355 12:13:25.977878
5356 12:13:25.983823 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5357 12:13:25.987247 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5358 12:13:25.987823 [Gating] SW calibration Done
5359 12:13:25.990708 ==
5360 12:13:25.994088 Dram Type= 6, Freq= 0, CH_0, rank 1
5361 12:13:25.997415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5362 12:13:25.998033 ==
5363 12:13:25.998411 RX Vref Scan: 0
5364 12:13:25.998758
5365 12:13:26.000399 RX Vref 0 -> 0, step: 1
5366 12:13:26.000870
5367 12:13:26.003921 RX Delay -80 -> 252, step: 8
5368 12:13:26.007346 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5369 12:13:26.011008 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5370 12:13:26.013851 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5371 12:13:26.020479 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5372 12:13:26.023662 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5373 12:13:26.027368 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5374 12:13:26.030543 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5375 12:13:26.033739 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5376 12:13:26.040520 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5377 12:13:26.043583 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5378 12:13:26.047381 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5379 12:13:26.050940 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5380 12:13:26.053887 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5381 12:13:26.057083 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5382 12:13:26.063559 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5383 12:13:26.066941 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5384 12:13:26.067526 ==
5385 12:13:26.070137 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 12:13:26.073612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 12:13:26.074249 ==
5388 12:13:26.076772 DQS Delay:
5389 12:13:26.077491 DQS0 = 0, DQS1 = 0
5390 12:13:26.077933 DQM Delay:
5391 12:13:26.079757 DQM0 = 106, DQM1 = 92
5392 12:13:26.080229 DQ Delay:
5393 12:13:26.083132 DQ0 =103, DQ1 =111, DQ2 =99, DQ3 =103
5394 12:13:26.086826 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5395 12:13:26.090181 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5396 12:13:26.093473 DQ12 =95, DQ13 =91, DQ14 =103, DQ15 =103
5397 12:13:26.094078
5398 12:13:26.094457
5399 12:13:26.096689 ==
5400 12:13:26.099902 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 12:13:26.103852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 12:13:26.104455 ==
5403 12:13:26.104837
5404 12:13:26.105185
5405 12:13:26.106437 TX Vref Scan disable
5406 12:13:26.106911 == TX Byte 0 ==
5407 12:13:26.113124 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5408 12:13:26.116499 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5409 12:13:26.117071 == TX Byte 1 ==
5410 12:13:26.123396 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5411 12:13:26.126477 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5412 12:13:26.127061 ==
5413 12:13:26.130007 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 12:13:26.132828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 12:13:26.133306 ==
5416 12:13:26.133681
5417 12:13:26.134060
5418 12:13:26.136238 TX Vref Scan disable
5419 12:13:26.139570 == TX Byte 0 ==
5420 12:13:26.142901 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5421 12:13:26.146380 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5422 12:13:26.149787 == TX Byte 1 ==
5423 12:13:26.153114 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5424 12:13:26.156240 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5425 12:13:26.156711
5426 12:13:26.159693 [DATLAT]
5427 12:13:26.160261 Freq=933, CH0 RK1
5428 12:13:26.160638
5429 12:13:26.162731 DATLAT Default: 0xb
5430 12:13:26.163200 0, 0xFFFF, sum = 0
5431 12:13:26.166279 1, 0xFFFF, sum = 0
5432 12:13:26.166853 2, 0xFFFF, sum = 0
5433 12:13:26.169554 3, 0xFFFF, sum = 0
5434 12:13:26.170166 4, 0xFFFF, sum = 0
5435 12:13:26.172775 5, 0xFFFF, sum = 0
5436 12:13:26.173350 6, 0xFFFF, sum = 0
5437 12:13:26.176052 7, 0xFFFF, sum = 0
5438 12:13:26.176534 8, 0xFFFF, sum = 0
5439 12:13:26.179320 9, 0xFFFF, sum = 0
5440 12:13:26.179904 10, 0x0, sum = 1
5441 12:13:26.182603 11, 0x0, sum = 2
5442 12:13:26.183192 12, 0x0, sum = 3
5443 12:13:26.186589 13, 0x0, sum = 4
5444 12:13:26.187163 best_step = 11
5445 12:13:26.187535
5446 12:13:26.187882 ==
5447 12:13:26.189240 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 12:13:26.196229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 12:13:26.196787 ==
5450 12:13:26.197164 RX Vref Scan: 0
5451 12:13:26.197512
5452 12:13:26.199047 RX Vref 0 -> 0, step: 1
5453 12:13:26.199521
5454 12:13:26.202528 RX Delay -53 -> 252, step: 4
5455 12:13:26.206145 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5456 12:13:26.209343 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5457 12:13:26.215944 iDelay=199, Bit 2, Center 100 (15 ~ 186) 172
5458 12:13:26.219329 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5459 12:13:26.222578 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5460 12:13:26.225802 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5461 12:13:26.229109 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5462 12:13:26.235816 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5463 12:13:26.238997 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5464 12:13:26.242627 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5465 12:13:26.245751 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5466 12:13:26.249610 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5467 12:13:26.252224 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5468 12:13:26.259513 iDelay=199, Bit 13, Center 96 (15 ~ 178) 164
5469 12:13:26.262403 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5470 12:13:26.265715 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5471 12:13:26.266405 ==
5472 12:13:26.269256 Dram Type= 6, Freq= 0, CH_0, rank 1
5473 12:13:26.272708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5474 12:13:26.273281 ==
5475 12:13:26.275474 DQS Delay:
5476 12:13:26.275945 DQS0 = 0, DQS1 = 0
5477 12:13:26.279182 DQM Delay:
5478 12:13:26.279753 DQM0 = 104, DQM1 = 93
5479 12:13:26.280131 DQ Delay:
5480 12:13:26.282821 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =98
5481 12:13:26.285565 DQ4 =104, DQ5 =98, DQ6 =112, DQ7 =112
5482 12:13:26.289236 DQ8 =86, DQ9 =80, DQ10 =94, DQ11 =92
5483 12:13:26.295353 DQ12 =98, DQ13 =96, DQ14 =100, DQ15 =98
5484 12:13:26.295908
5485 12:13:26.296278
5486 12:13:26.302605 [DQSOSCAuto] RK1, (LSB)MR18= 0x290a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5487 12:13:26.305980 CH0 RK1: MR19=505, MR18=290A
5488 12:13:26.312571 CH0_RK1: MR19=0x505, MR18=0x290A, DQSOSC=408, MR23=63, INC=65, DEC=43
5489 12:13:26.315766 [RxdqsGatingPostProcess] freq 933
5490 12:13:26.318913 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5491 12:13:26.322616 best DQS0 dly(2T, 0.5T) = (0, 10)
5492 12:13:26.325231 best DQS1 dly(2T, 0.5T) = (0, 10)
5493 12:13:26.328394 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5494 12:13:26.332235 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5495 12:13:26.335536 best DQS0 dly(2T, 0.5T) = (0, 10)
5496 12:13:26.338721 best DQS1 dly(2T, 0.5T) = (0, 10)
5497 12:13:26.341883 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5498 12:13:26.345191 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5499 12:13:26.348774 Pre-setting of DQS Precalculation
5500 12:13:26.351718 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5501 12:13:26.352194 ==
5502 12:13:26.355334 Dram Type= 6, Freq= 0, CH_1, rank 0
5503 12:13:26.361809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 12:13:26.362404 ==
5505 12:13:26.365197 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5506 12:13:26.371619 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5507 12:13:26.374773 [CA 0] Center 37 (7~68) winsize 62
5508 12:13:26.378470 [CA 1] Center 37 (7~68) winsize 62
5509 12:13:26.382133 [CA 2] Center 35 (5~66) winsize 62
5510 12:13:26.385149 [CA 3] Center 35 (5~65) winsize 61
5511 12:13:26.388705 [CA 4] Center 35 (5~66) winsize 62
5512 12:13:26.391679 [CA 5] Center 34 (4~65) winsize 62
5513 12:13:26.392257
5514 12:13:26.394724 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5515 12:13:26.395195
5516 12:13:26.398525 [CATrainingPosCal] consider 1 rank data
5517 12:13:26.401740 u2DelayCellTimex100 = 270/100 ps
5518 12:13:26.405094 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5519 12:13:26.408219 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5520 12:13:26.414686 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5521 12:13:26.418543 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5522 12:13:26.421503 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5523 12:13:26.424920 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5524 12:13:26.425486
5525 12:13:26.428328 CA PerBit enable=1, Macro0, CA PI delay=34
5526 12:13:26.428914
5527 12:13:26.431343 [CBTSetCACLKResult] CA Dly = 34
5528 12:13:26.431818 CS Dly: 6 (0~37)
5529 12:13:26.434935 ==
5530 12:13:26.435511 Dram Type= 6, Freq= 0, CH_1, rank 1
5531 12:13:26.441424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 12:13:26.442047 ==
5533 12:13:26.444781 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5534 12:13:26.451363 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5535 12:13:26.454771 [CA 0] Center 37 (7~68) winsize 62
5536 12:13:26.458376 [CA 1] Center 38 (7~69) winsize 63
5537 12:13:26.461199 [CA 2] Center 36 (6~67) winsize 62
5538 12:13:26.465306 [CA 3] Center 35 (5~66) winsize 62
5539 12:13:26.468346 [CA 4] Center 35 (5~66) winsize 62
5540 12:13:26.471419 [CA 5] Center 34 (4~65) winsize 62
5541 12:13:26.471892
5542 12:13:26.474986 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5543 12:13:26.475460
5544 12:13:26.477730 [CATrainingPosCal] consider 2 rank data
5545 12:13:26.481569 u2DelayCellTimex100 = 270/100 ps
5546 12:13:26.485070 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5547 12:13:26.491278 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5548 12:13:26.494799 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5549 12:13:26.498125 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5550 12:13:26.501495 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5551 12:13:26.505266 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5552 12:13:26.505834
5553 12:13:26.508008 CA PerBit enable=1, Macro0, CA PI delay=34
5554 12:13:26.508580
5555 12:13:26.511262 [CBTSetCACLKResult] CA Dly = 34
5556 12:13:26.511734 CS Dly: 7 (0~39)
5557 12:13:26.514808
5558 12:13:26.518060 ----->DramcWriteLeveling(PI) begin...
5559 12:13:26.518540 ==
5560 12:13:26.521738 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 12:13:26.524396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 12:13:26.524873 ==
5563 12:13:26.528108 Write leveling (Byte 0): 27 => 27
5564 12:13:26.531191 Write leveling (Byte 1): 27 => 27
5565 12:13:26.534415 DramcWriteLeveling(PI) end<-----
5566 12:13:26.534890
5567 12:13:26.535262 ==
5568 12:13:26.537837 Dram Type= 6, Freq= 0, CH_1, rank 0
5569 12:13:26.541177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5570 12:13:26.541747 ==
5571 12:13:26.544600 [Gating] SW mode calibration
5572 12:13:26.551304 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5573 12:13:26.558117 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5574 12:13:26.561265 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 12:13:26.564963 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 12:13:26.571284 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 12:13:26.574450 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 12:13:26.577599 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5579 12:13:26.584105 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5580 12:13:26.587502 0 14 24 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 1)
5581 12:13:26.591179 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5582 12:13:26.597681 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 12:13:26.601284 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 12:13:26.604436 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 12:13:26.608108 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 12:13:26.614578 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5587 12:13:26.617524 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5588 12:13:26.621177 0 15 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5589 12:13:26.627816 0 15 28 | B1->B0 | 3b3b 4242 | 1 0 | (0 0) (0 0)
5590 12:13:26.630681 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 12:13:26.634148 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 12:13:26.640889 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 12:13:26.644894 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 12:13:26.647925 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 12:13:26.654373 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5596 12:13:26.657578 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5597 12:13:26.661295 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5598 12:13:26.667734 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 12:13:26.671338 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 12:13:26.674019 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 12:13:26.680785 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 12:13:26.684124 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 12:13:26.687484 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 12:13:26.694330 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 12:13:26.697621 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 12:13:26.700768 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 12:13:26.707488 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 12:13:26.710851 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 12:13:26.714038 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 12:13:26.720823 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 12:13:26.724172 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 12:13:26.727343 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5613 12:13:26.734109 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 12:13:26.734825 Total UI for P1: 0, mck2ui 16
5615 12:13:26.737419 best dqsien dly found for B0: ( 1, 2, 24)
5616 12:13:26.740783 Total UI for P1: 0, mck2ui 16
5617 12:13:26.744272 best dqsien dly found for B1: ( 1, 2, 26)
5618 12:13:26.747226 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5619 12:13:26.753657 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5620 12:13:26.754265
5621 12:13:26.757689 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5622 12:13:26.760859 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5623 12:13:26.763528 [Gating] SW calibration Done
5624 12:13:26.764006 ==
5625 12:13:26.766884 Dram Type= 6, Freq= 0, CH_1, rank 0
5626 12:13:26.770284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5627 12:13:26.770877 ==
5628 12:13:26.771259 RX Vref Scan: 0
5629 12:13:26.774036
5630 12:13:26.774625 RX Vref 0 -> 0, step: 1
5631 12:13:26.775103
5632 12:13:26.776955 RX Delay -80 -> 252, step: 8
5633 12:13:26.780721 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5634 12:13:26.783611 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5635 12:13:26.790483 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5636 12:13:26.794060 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5637 12:13:26.798376 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5638 12:13:26.800783 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5639 12:13:26.803795 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5640 12:13:26.807047 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5641 12:13:26.813803 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5642 12:13:26.817266 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5643 12:13:26.820430 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5644 12:13:26.823526 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5645 12:13:26.827051 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5646 12:13:26.833649 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5647 12:13:26.837241 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5648 12:13:26.840116 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5649 12:13:26.840726 ==
5650 12:13:26.843798 Dram Type= 6, Freq= 0, CH_1, rank 0
5651 12:13:26.846544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5652 12:13:26.847022 ==
5653 12:13:26.850589 DQS Delay:
5654 12:13:26.851169 DQS0 = 0, DQS1 = 0
5655 12:13:26.851547 DQM Delay:
5656 12:13:26.853351 DQM0 = 102, DQM1 = 95
5657 12:13:26.853824 DQ Delay:
5658 12:13:26.856694 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =103
5659 12:13:26.859907 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =99
5660 12:13:26.863126 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5661 12:13:26.866832 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =99
5662 12:13:26.867310
5663 12:13:26.870164
5664 12:13:26.870824 ==
5665 12:13:26.873050 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 12:13:26.876692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 12:13:26.877169 ==
5668 12:13:26.877540
5669 12:13:26.877890
5670 12:13:26.879815 TX Vref Scan disable
5671 12:13:26.880288 == TX Byte 0 ==
5672 12:13:26.886218 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5673 12:13:26.889866 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5674 12:13:26.890388 == TX Byte 1 ==
5675 12:13:26.896567 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5676 12:13:26.900238 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5677 12:13:26.900780 ==
5678 12:13:26.903223 Dram Type= 6, Freq= 0, CH_1, rank 0
5679 12:13:26.906703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5680 12:13:26.907245 ==
5681 12:13:26.907590
5682 12:13:26.907904
5683 12:13:26.910227 TX Vref Scan disable
5684 12:13:26.913471 == TX Byte 0 ==
5685 12:13:26.916548 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5686 12:13:26.920005 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5687 12:13:26.923209 == TX Byte 1 ==
5688 12:13:26.926430 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5689 12:13:26.930089 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5690 12:13:26.930643
5691 12:13:26.933631 [DATLAT]
5692 12:13:26.934198 Freq=933, CH1 RK0
5693 12:13:26.934550
5694 12:13:26.936476 DATLAT Default: 0xd
5695 12:13:26.937013 0, 0xFFFF, sum = 0
5696 12:13:26.939584 1, 0xFFFF, sum = 0
5697 12:13:26.940139 2, 0xFFFF, sum = 0
5698 12:13:26.942895 3, 0xFFFF, sum = 0
5699 12:13:26.943440 4, 0xFFFF, sum = 0
5700 12:13:26.946201 5, 0xFFFF, sum = 0
5701 12:13:26.946751 6, 0xFFFF, sum = 0
5702 12:13:26.949656 7, 0xFFFF, sum = 0
5703 12:13:26.950128 8, 0xFFFF, sum = 0
5704 12:13:26.952682 9, 0xFFFF, sum = 0
5705 12:13:26.953118 10, 0x0, sum = 1
5706 12:13:26.956462 11, 0x0, sum = 2
5707 12:13:26.956968 12, 0x0, sum = 3
5708 12:13:26.959573 13, 0x0, sum = 4
5709 12:13:26.960113 best_step = 11
5710 12:13:26.960461
5711 12:13:26.960779 ==
5712 12:13:26.963078 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 12:13:26.965925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 12:13:26.969303 ==
5715 12:13:26.969732 RX Vref Scan: 1
5716 12:13:26.970112
5717 12:13:26.972969 RX Vref 0 -> 0, step: 1
5718 12:13:26.973520
5719 12:13:26.976034 RX Delay -53 -> 252, step: 4
5720 12:13:26.976463
5721 12:13:26.979428 Set Vref, RX VrefLevel [Byte0]: 53
5722 12:13:26.982758 [Byte1]: 53
5723 12:13:26.983189
5724 12:13:26.986042 Final RX Vref Byte 0 = 53 to rank0
5725 12:13:26.989222 Final RX Vref Byte 1 = 53 to rank0
5726 12:13:26.992669 Final RX Vref Byte 0 = 53 to rank1
5727 12:13:26.996477 Final RX Vref Byte 1 = 53 to rank1==
5728 12:13:26.999210 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 12:13:27.002999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 12:13:27.003540 ==
5731 12:13:27.006098 DQS Delay:
5732 12:13:27.006635 DQS0 = 0, DQS1 = 0
5733 12:13:27.006981 DQM Delay:
5734 12:13:27.009599 DQM0 = 104, DQM1 = 97
5735 12:13:27.010167 DQ Delay:
5736 12:13:27.012733 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =102
5737 12:13:27.016120 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =102
5738 12:13:27.019322 DQ8 =86, DQ9 =84, DQ10 =98, DQ11 =94
5739 12:13:27.022954 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =104
5740 12:13:27.023491
5741 12:13:27.023832
5742 12:13:27.033143 [DQSOSCAuto] RK0, (LSB)MR18= 0x162e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5743 12:13:27.035666 CH1 RK0: MR19=505, MR18=162E
5744 12:13:27.042590 CH1_RK0: MR19=0x505, MR18=0x162E, DQSOSC=407, MR23=63, INC=65, DEC=43
5745 12:13:27.043132
5746 12:13:27.045810 ----->DramcWriteLeveling(PI) begin...
5747 12:13:27.046403 ==
5748 12:13:27.048987 Dram Type= 6, Freq= 0, CH_1, rank 1
5749 12:13:27.052419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 12:13:27.052961 ==
5751 12:13:27.055629 Write leveling (Byte 0): 28 => 28
5752 12:13:27.059076 Write leveling (Byte 1): 27 => 27
5753 12:13:27.062504 DramcWriteLeveling(PI) end<-----
5754 12:13:27.063038
5755 12:13:27.063374 ==
5756 12:13:27.066024 Dram Type= 6, Freq= 0, CH_1, rank 1
5757 12:13:27.068844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5758 12:13:27.069280 ==
5759 12:13:27.072294 [Gating] SW mode calibration
5760 12:13:27.079128 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5761 12:13:27.085443 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5762 12:13:27.089078 0 14 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5763 12:13:27.092312 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 12:13:27.099176 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 12:13:27.102314 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 12:13:27.106060 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 12:13:27.112054 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5768 12:13:27.115760 0 14 24 | B1->B0 | 3131 3333 | 0 0 | (0 1) (0 1)
5769 12:13:27.118873 0 14 28 | B1->B0 | 2626 2e2e | 0 1 | (1 0) (1 0)
5770 12:13:27.125875 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 12:13:27.128668 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 12:13:27.132366 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 12:13:27.138665 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 12:13:27.141902 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 12:13:27.146483 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5776 12:13:27.152522 0 15 24 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
5777 12:13:27.155292 0 15 28 | B1->B0 | 4646 3939 | 0 0 | (0 0) (0 0)
5778 12:13:27.158885 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 12:13:27.165305 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 12:13:27.168819 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 12:13:27.171930 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 12:13:27.178423 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 12:13:27.181832 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 12:13:27.184984 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5785 12:13:27.189083 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5786 12:13:27.195419 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 12:13:27.198919 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 12:13:27.202107 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 12:13:27.208426 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 12:13:27.211701 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 12:13:27.215662 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 12:13:27.222124 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 12:13:27.225614 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 12:13:27.229217 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 12:13:27.235154 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 12:13:27.238759 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 12:13:27.241757 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 12:13:27.248581 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 12:13:27.251995 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 12:13:27.255292 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5801 12:13:27.261479 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5802 12:13:27.265131 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 12:13:27.268940 Total UI for P1: 0, mck2ui 16
5804 12:13:27.271468 best dqsien dly found for B0: ( 1, 2, 26)
5805 12:13:27.275172 Total UI for P1: 0, mck2ui 16
5806 12:13:27.278672 best dqsien dly found for B1: ( 1, 2, 28)
5807 12:13:27.281873 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5808 12:13:27.284778 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5809 12:13:27.285251
5810 12:13:27.288409 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5811 12:13:27.291474 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5812 12:13:27.294633 [Gating] SW calibration Done
5813 12:13:27.295104 ==
5814 12:13:27.298165 Dram Type= 6, Freq= 0, CH_1, rank 1
5815 12:13:27.301512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5816 12:13:27.304785 ==
5817 12:13:27.305254 RX Vref Scan: 0
5818 12:13:27.305626
5819 12:13:27.307963 RX Vref 0 -> 0, step: 1
5820 12:13:27.308430
5821 12:13:27.311247 RX Delay -80 -> 252, step: 8
5822 12:13:27.314878 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5823 12:13:27.318178 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5824 12:13:27.321058 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5825 12:13:27.324362 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5826 12:13:27.331375 iDelay=208, Bit 4, Center 103 (16 ~ 191) 176
5827 12:13:27.334632 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5828 12:13:27.338153 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5829 12:13:27.341309 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5830 12:13:27.344469 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5831 12:13:27.347818 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5832 12:13:27.351507 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5833 12:13:27.357893 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5834 12:13:27.360760 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5835 12:13:27.364315 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5836 12:13:27.367541 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5837 12:13:27.370793 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5838 12:13:27.374271 ==
5839 12:13:27.374847 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 12:13:27.381055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 12:13:27.381652 ==
5842 12:13:27.382079 DQS Delay:
5843 12:13:27.384346 DQS0 = 0, DQS1 = 0
5844 12:13:27.384865 DQM Delay:
5845 12:13:27.387219 DQM0 = 101, DQM1 = 96
5846 12:13:27.387687 DQ Delay:
5847 12:13:27.390822 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5848 12:13:27.394187 DQ4 =103, DQ5 =115, DQ6 =107, DQ7 =99
5849 12:13:27.397563 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5850 12:13:27.400941 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5851 12:13:27.401518
5852 12:13:27.401889
5853 12:13:27.402349 ==
5854 12:13:27.404255 Dram Type= 6, Freq= 0, CH_1, rank 1
5855 12:13:27.407170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5856 12:13:27.407694 ==
5857 12:13:27.410858
5858 12:13:27.411441
5859 12:13:27.411814 TX Vref Scan disable
5860 12:13:27.414105 == TX Byte 0 ==
5861 12:13:27.417361 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5862 12:13:27.420816 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5863 12:13:27.424059 == TX Byte 1 ==
5864 12:13:27.427474 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5865 12:13:27.430584 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5866 12:13:27.431157 ==
5867 12:13:27.434023 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 12:13:27.440519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 12:13:27.441095 ==
5870 12:13:27.441471
5871 12:13:27.441816
5872 12:13:27.442199 TX Vref Scan disable
5873 12:13:27.444974 == TX Byte 0 ==
5874 12:13:27.448546 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5875 12:13:27.454813 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5876 12:13:27.455389 == TX Byte 1 ==
5877 12:13:27.457897 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5878 12:13:27.465219 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5879 12:13:27.465787
5880 12:13:27.466237 [DATLAT]
5881 12:13:27.466597 Freq=933, CH1 RK1
5882 12:13:27.466939
5883 12:13:27.468102 DATLAT Default: 0xb
5884 12:13:27.468576 0, 0xFFFF, sum = 0
5885 12:13:27.471804 1, 0xFFFF, sum = 0
5886 12:13:27.475013 2, 0xFFFF, sum = 0
5887 12:13:27.475493 3, 0xFFFF, sum = 0
5888 12:13:27.477731 4, 0xFFFF, sum = 0
5889 12:13:27.478350 5, 0xFFFF, sum = 0
5890 12:13:27.480999 6, 0xFFFF, sum = 0
5891 12:13:27.481480 7, 0xFFFF, sum = 0
5892 12:13:27.484523 8, 0xFFFF, sum = 0
5893 12:13:27.485024 9, 0xFFFF, sum = 0
5894 12:13:27.487759 10, 0x0, sum = 1
5895 12:13:27.488242 11, 0x0, sum = 2
5896 12:13:27.491227 12, 0x0, sum = 3
5897 12:13:27.491803 13, 0x0, sum = 4
5898 12:13:27.492184 best_step = 11
5899 12:13:27.492533
5900 12:13:27.494723 ==
5901 12:13:27.498043 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 12:13:27.501288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 12:13:27.501764 ==
5904 12:13:27.502178 RX Vref Scan: 0
5905 12:13:27.502529
5906 12:13:27.504488 RX Vref 0 -> 0, step: 1
5907 12:13:27.504964
5908 12:13:27.507965 RX Delay -53 -> 252, step: 4
5909 12:13:27.511455 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5910 12:13:27.518045 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5911 12:13:27.521292 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5912 12:13:27.524461 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5913 12:13:27.527697 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5914 12:13:27.531268 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5915 12:13:27.538295 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5916 12:13:27.541347 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5917 12:13:27.544626 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5918 12:13:27.547647 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5919 12:13:27.551062 iDelay=199, Bit 10, Center 96 (11 ~ 182) 172
5920 12:13:27.554615 iDelay=199, Bit 11, Center 90 (3 ~ 178) 176
5921 12:13:27.560848 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5922 12:13:27.564662 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5923 12:13:27.567898 iDelay=199, Bit 14, Center 104 (15 ~ 194) 180
5924 12:13:27.570837 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5925 12:13:27.571314 ==
5926 12:13:27.574525 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 12:13:27.581170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 12:13:27.581650 ==
5929 12:13:27.582092 DQS Delay:
5930 12:13:27.584286 DQS0 = 0, DQS1 = 0
5931 12:13:27.584762 DQM Delay:
5932 12:13:27.585137 DQM0 = 104, DQM1 = 97
5933 12:13:27.587608 DQ Delay:
5934 12:13:27.591382 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5935 12:13:27.594221 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
5936 12:13:27.597925 DQ8 =84, DQ9 =88, DQ10 =96, DQ11 =90
5937 12:13:27.600954 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =106
5938 12:13:27.601523
5939 12:13:27.601898
5940 12:13:27.608263 [DQSOSCAuto] RK1, (LSB)MR18= 0x1ffb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 412 ps
5941 12:13:27.611013 CH1 RK1: MR19=504, MR18=1FFB
5942 12:13:27.617839 CH1_RK1: MR19=0x504, MR18=0x1FFB, DQSOSC=412, MR23=63, INC=63, DEC=42
5943 12:13:27.620710 [RxdqsGatingPostProcess] freq 933
5944 12:13:27.627560 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5945 12:13:27.630586 best DQS0 dly(2T, 0.5T) = (0, 10)
5946 12:13:27.631065 best DQS1 dly(2T, 0.5T) = (0, 10)
5947 12:13:27.633996 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5948 12:13:27.638093 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5949 12:13:27.640974 best DQS0 dly(2T, 0.5T) = (0, 10)
5950 12:13:27.643964 best DQS1 dly(2T, 0.5T) = (0, 10)
5951 12:13:27.647401 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5952 12:13:27.650960 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5953 12:13:27.654230 Pre-setting of DQS Precalculation
5954 12:13:27.660541 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5955 12:13:27.667374 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5956 12:13:27.673830 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5957 12:13:27.674348
5958 12:13:27.674717
5959 12:13:27.677550 [Calibration Summary] 1866 Mbps
5960 12:13:27.678083 CH 0, Rank 0
5961 12:13:27.680509 SW Impedance : PASS
5962 12:13:27.684111 DUTY Scan : NO K
5963 12:13:27.684690 ZQ Calibration : PASS
5964 12:13:27.687771 Jitter Meter : NO K
5965 12:13:27.690615 CBT Training : PASS
5966 12:13:27.691184 Write leveling : PASS
5967 12:13:27.694135 RX DQS gating : PASS
5968 12:13:27.694605 RX DQ/DQS(RDDQC) : PASS
5969 12:13:27.697501 TX DQ/DQS : PASS
5970 12:13:27.700428 RX DATLAT : PASS
5971 12:13:27.700916 RX DQ/DQS(Engine): PASS
5972 12:13:27.703912 TX OE : NO K
5973 12:13:27.704384 All Pass.
5974 12:13:27.704797
5975 12:13:27.707180 CH 0, Rank 1
5976 12:13:27.707648 SW Impedance : PASS
5977 12:13:27.711017 DUTY Scan : NO K
5978 12:13:27.713990 ZQ Calibration : PASS
5979 12:13:27.714560 Jitter Meter : NO K
5980 12:13:27.716941 CBT Training : PASS
5981 12:13:27.720283 Write leveling : PASS
5982 12:13:27.720757 RX DQS gating : PASS
5983 12:13:27.723807 RX DQ/DQS(RDDQC) : PASS
5984 12:13:27.727188 TX DQ/DQS : PASS
5985 12:13:27.727766 RX DATLAT : PASS
5986 12:13:27.730234 RX DQ/DQS(Engine): PASS
5987 12:13:27.734153 TX OE : NO K
5988 12:13:27.734726 All Pass.
5989 12:13:27.735102
5990 12:13:27.735447 CH 1, Rank 0
5991 12:13:27.737197 SW Impedance : PASS
5992 12:13:27.740531 DUTY Scan : NO K
5993 12:13:27.741010 ZQ Calibration : PASS
5994 12:13:27.744195 Jitter Meter : NO K
5995 12:13:27.746907 CBT Training : PASS
5996 12:13:27.747410 Write leveling : PASS
5997 12:13:27.750478 RX DQS gating : PASS
5998 12:13:27.751051 RX DQ/DQS(RDDQC) : PASS
5999 12:13:27.753586 TX DQ/DQS : PASS
6000 12:13:27.756851 RX DATLAT : PASS
6001 12:13:27.757423 RX DQ/DQS(Engine): PASS
6002 12:13:27.759950 TX OE : NO K
6003 12:13:27.760428 All Pass.
6004 12:13:27.760822
6005 12:13:27.763368 CH 1, Rank 1
6006 12:13:27.763941 SW Impedance : PASS
6007 12:13:27.767020 DUTY Scan : NO K
6008 12:13:27.769924 ZQ Calibration : PASS
6009 12:13:27.770429 Jitter Meter : NO K
6010 12:13:27.773642 CBT Training : PASS
6011 12:13:27.776919 Write leveling : PASS
6012 12:13:27.777488 RX DQS gating : PASS
6013 12:13:27.780305 RX DQ/DQS(RDDQC) : PASS
6014 12:13:27.783303 TX DQ/DQS : PASS
6015 12:13:27.783877 RX DATLAT : PASS
6016 12:13:27.786476 RX DQ/DQS(Engine): PASS
6017 12:13:27.789841 TX OE : NO K
6018 12:13:27.790443 All Pass.
6019 12:13:27.790820
6020 12:13:27.791166 DramC Write-DBI off
6021 12:13:27.793256 PER_BANK_REFRESH: Hybrid Mode
6022 12:13:27.797069 TX_TRACKING: ON
6023 12:13:27.803719 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6024 12:13:27.806361 [FAST_K] Save calibration result to emmc
6025 12:13:27.813398 dramc_set_vcore_voltage set vcore to 650000
6026 12:13:27.813968 Read voltage for 400, 6
6027 12:13:27.816514 Vio18 = 0
6028 12:13:27.817112 Vcore = 650000
6029 12:13:27.817554 Vdram = 0
6030 12:13:27.819736 Vddq = 0
6031 12:13:27.820299 Vmddr = 0
6032 12:13:27.823051 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6033 12:13:27.829936 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6034 12:13:27.833354 MEM_TYPE=3, freq_sel=20
6035 12:13:27.833825 sv_algorithm_assistance_LP4_800
6036 12:13:27.840122 ============ PULL DRAM RESETB DOWN ============
6037 12:13:27.843400 ========== PULL DRAM RESETB DOWN end =========
6038 12:13:27.846852 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6039 12:13:27.849796 ===================================
6040 12:13:27.853604 LPDDR4 DRAM CONFIGURATION
6041 12:13:27.856568 ===================================
6042 12:13:27.859609 EX_ROW_EN[0] = 0x0
6043 12:13:27.860110 EX_ROW_EN[1] = 0x0
6044 12:13:27.862968 LP4Y_EN = 0x0
6045 12:13:27.863444 WORK_FSP = 0x0
6046 12:13:27.867089 WL = 0x2
6047 12:13:27.867558 RL = 0x2
6048 12:13:27.869473 BL = 0x2
6049 12:13:27.869977 RPST = 0x0
6050 12:13:27.873233 RD_PRE = 0x0
6051 12:13:27.873805 WR_PRE = 0x1
6052 12:13:27.876313 WR_PST = 0x0
6053 12:13:27.876849 DBI_WR = 0x0
6054 12:13:27.879926 DBI_RD = 0x0
6055 12:13:27.880500 OTF = 0x1
6056 12:13:27.883231 ===================================
6057 12:13:27.886418 ===================================
6058 12:13:27.889850 ANA top config
6059 12:13:27.892972 ===================================
6060 12:13:27.896385 DLL_ASYNC_EN = 0
6061 12:13:27.896969 ALL_SLAVE_EN = 1
6062 12:13:27.899613 NEW_RANK_MODE = 1
6063 12:13:27.903569 DLL_IDLE_MODE = 1
6064 12:13:27.906022 LP45_APHY_COMB_EN = 1
6065 12:13:27.909463 TX_ODT_DIS = 1
6066 12:13:27.909936 NEW_8X_MODE = 1
6067 12:13:27.912534 ===================================
6068 12:13:27.916060 ===================================
6069 12:13:27.919550 data_rate = 800
6070 12:13:27.922514 CKR = 1
6071 12:13:27.925920 DQ_P2S_RATIO = 4
6072 12:13:27.929373 ===================================
6073 12:13:27.932546 CA_P2S_RATIO = 4
6074 12:13:27.935886 DQ_CA_OPEN = 0
6075 12:13:27.936359 DQ_SEMI_OPEN = 1
6076 12:13:27.939586 CA_SEMI_OPEN = 1
6077 12:13:27.942624 CA_FULL_RATE = 0
6078 12:13:27.946042 DQ_CKDIV4_EN = 0
6079 12:13:27.949695 CA_CKDIV4_EN = 1
6080 12:13:27.953186 CA_PREDIV_EN = 0
6081 12:13:27.953753 PH8_DLY = 0
6082 12:13:27.955985 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6083 12:13:27.959166 DQ_AAMCK_DIV = 0
6084 12:13:27.962497 CA_AAMCK_DIV = 0
6085 12:13:27.966504 CA_ADMCK_DIV = 4
6086 12:13:27.969231 DQ_TRACK_CA_EN = 0
6087 12:13:27.969801 CA_PICK = 800
6088 12:13:27.972839 CA_MCKIO = 400
6089 12:13:27.975852 MCKIO_SEMI = 400
6090 12:13:27.979049 PLL_FREQ = 3016
6091 12:13:27.982610 DQ_UI_PI_RATIO = 32
6092 12:13:27.985772 CA_UI_PI_RATIO = 32
6093 12:13:27.989074 ===================================
6094 12:13:27.992698 ===================================
6095 12:13:27.995755 memory_type:LPDDR4
6096 12:13:27.996328 GP_NUM : 10
6097 12:13:27.999127 SRAM_EN : 1
6098 12:13:27.999694 MD32_EN : 0
6099 12:13:28.002383 ===================================
6100 12:13:28.005498 [ANA_INIT] >>>>>>>>>>>>>>
6101 12:13:28.009285 <<<<<< [CONFIGURE PHASE]: ANA_TX
6102 12:13:28.012536 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6103 12:13:28.015423 ===================================
6104 12:13:28.019137 data_rate = 800,PCW = 0X7400
6105 12:13:28.022174 ===================================
6106 12:13:28.025701 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6107 12:13:28.028907 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6108 12:13:28.042054 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6109 12:13:28.045632 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6110 12:13:28.048769 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6111 12:13:28.052365 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6112 12:13:28.055929 [ANA_INIT] flow start
6113 12:13:28.058914 [ANA_INIT] PLL >>>>>>>>
6114 12:13:28.059485 [ANA_INIT] PLL <<<<<<<<
6115 12:13:28.062406 [ANA_INIT] MIDPI >>>>>>>>
6116 12:13:28.065746 [ANA_INIT] MIDPI <<<<<<<<
6117 12:13:28.066308 [ANA_INIT] DLL >>>>>>>>
6118 12:13:28.069209 [ANA_INIT] flow end
6119 12:13:28.072319 ============ LP4 DIFF to SE enter ============
6120 12:13:28.075492 ============ LP4 DIFF to SE exit ============
6121 12:13:28.078619 [ANA_INIT] <<<<<<<<<<<<<
6122 12:13:28.082126 [Flow] Enable top DCM control >>>>>
6123 12:13:28.085557 [Flow] Enable top DCM control <<<<<
6124 12:13:28.089011 Enable DLL master slave shuffle
6125 12:13:28.095364 ==============================================================
6126 12:13:28.095945 Gating Mode config
6127 12:13:28.102152 ==============================================================
6128 12:13:28.102728 Config description:
6129 12:13:28.111869 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6130 12:13:28.118634 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6131 12:13:28.125319 SELPH_MODE 0: By rank 1: By Phase
6132 12:13:28.128644 ==============================================================
6133 12:13:28.131626 GAT_TRACK_EN = 0
6134 12:13:28.135584 RX_GATING_MODE = 2
6135 12:13:28.138527 RX_GATING_TRACK_MODE = 2
6136 12:13:28.141910 SELPH_MODE = 1
6137 12:13:28.145255 PICG_EARLY_EN = 1
6138 12:13:28.149037 VALID_LAT_VALUE = 1
6139 12:13:28.154926 ==============================================================
6140 12:13:28.158303 Enter into Gating configuration >>>>
6141 12:13:28.161704 Exit from Gating configuration <<<<
6142 12:13:28.165000 Enter into DVFS_PRE_config >>>>>
6143 12:13:28.175507 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6144 12:13:28.178523 Exit from DVFS_PRE_config <<<<<
6145 12:13:28.181792 Enter into PICG configuration >>>>
6146 12:13:28.185367 Exit from PICG configuration <<<<
6147 12:13:28.188305 [RX_INPUT] configuration >>>>>
6148 12:13:28.188778 [RX_INPUT] configuration <<<<<
6149 12:13:28.195345 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6150 12:13:28.201853 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6151 12:13:28.205089 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6152 12:13:28.211844 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6153 12:13:28.218378 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6154 12:13:28.225062 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6155 12:13:28.228565 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6156 12:13:28.231546 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6157 12:13:28.238281 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6158 12:13:28.241501 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6159 12:13:28.244981 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6160 12:13:28.248094 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6161 12:13:28.251432 ===================================
6162 12:13:28.254924 LPDDR4 DRAM CONFIGURATION
6163 12:13:28.258280 ===================================
6164 12:13:28.261600 EX_ROW_EN[0] = 0x0
6165 12:13:28.262099 EX_ROW_EN[1] = 0x0
6166 12:13:28.265039 LP4Y_EN = 0x0
6167 12:13:28.265511 WORK_FSP = 0x0
6168 12:13:28.268317 WL = 0x2
6169 12:13:28.268888 RL = 0x2
6170 12:13:28.271400 BL = 0x2
6171 12:13:28.271866 RPST = 0x0
6172 12:13:28.274606 RD_PRE = 0x0
6173 12:13:28.278423 WR_PRE = 0x1
6174 12:13:28.278887 WR_PST = 0x0
6175 12:13:28.281390 DBI_WR = 0x0
6176 12:13:28.281898 DBI_RD = 0x0
6177 12:13:28.284747 OTF = 0x1
6178 12:13:28.288019 ===================================
6179 12:13:28.291375 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6180 12:13:28.294658 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6181 12:13:28.298230 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6182 12:13:28.301260 ===================================
6183 12:13:28.304578 LPDDR4 DRAM CONFIGURATION
6184 12:13:28.307546 ===================================
6185 12:13:28.311250 EX_ROW_EN[0] = 0x10
6186 12:13:28.311819 EX_ROW_EN[1] = 0x0
6187 12:13:28.314439 LP4Y_EN = 0x0
6188 12:13:28.314906 WORK_FSP = 0x0
6189 12:13:28.317759 WL = 0x2
6190 12:13:28.318375 RL = 0x2
6191 12:13:28.320765 BL = 0x2
6192 12:13:28.321230 RPST = 0x0
6193 12:13:28.324732 RD_PRE = 0x0
6194 12:13:28.325304 WR_PRE = 0x1
6195 12:13:28.327714 WR_PST = 0x0
6196 12:13:28.331314 DBI_WR = 0x0
6197 12:13:28.331897 DBI_RD = 0x0
6198 12:13:28.334244 OTF = 0x1
6199 12:13:28.337731 ===================================
6200 12:13:28.340685 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6201 12:13:28.346108 nWR fixed to 30
6202 12:13:28.349608 [ModeRegInit_LP4] CH0 RK0
6203 12:13:28.350247 [ModeRegInit_LP4] CH0 RK1
6204 12:13:28.352896 [ModeRegInit_LP4] CH1 RK0
6205 12:13:28.356220 [ModeRegInit_LP4] CH1 RK1
6206 12:13:28.356796 match AC timing 19
6207 12:13:28.362958 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6208 12:13:28.365863 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6209 12:13:28.369609 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6210 12:13:28.376204 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6211 12:13:28.379670 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6212 12:13:28.380140 ==
6213 12:13:28.382521 Dram Type= 6, Freq= 0, CH_0, rank 0
6214 12:13:28.386714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6215 12:13:28.387193 ==
6216 12:13:28.393046 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6217 12:13:28.399359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6218 12:13:28.402468 [CA 0] Center 36 (8~64) winsize 57
6219 12:13:28.405879 [CA 1] Center 36 (8~64) winsize 57
6220 12:13:28.409569 [CA 2] Center 36 (8~64) winsize 57
6221 12:13:28.412960 [CA 3] Center 36 (8~64) winsize 57
6222 12:13:28.413542 [CA 4] Center 36 (8~64) winsize 57
6223 12:13:28.416088 [CA 5] Center 36 (8~64) winsize 57
6224 12:13:28.416659
6225 12:13:28.422544 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6226 12:13:28.423115
6227 12:13:28.426160 [CATrainingPosCal] consider 1 rank data
6228 12:13:28.429506 u2DelayCellTimex100 = 270/100 ps
6229 12:13:28.433016 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 12:13:28.436299 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 12:13:28.439563 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 12:13:28.442299 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 12:13:28.446443 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 12:13:28.448976 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 12:13:28.449555
6236 12:13:28.452298 CA PerBit enable=1, Macro0, CA PI delay=36
6237 12:13:28.452766
6238 12:13:28.455851 [CBTSetCACLKResult] CA Dly = 36
6239 12:13:28.459140 CS Dly: 1 (0~32)
6240 12:13:28.459706 ==
6241 12:13:28.462245 Dram Type= 6, Freq= 0, CH_0, rank 1
6242 12:13:28.465569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6243 12:13:28.466089 ==
6244 12:13:28.472645 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6245 12:13:28.475799 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6246 12:13:28.478840 [CA 0] Center 36 (8~64) winsize 57
6247 12:13:28.482299 [CA 1] Center 36 (8~64) winsize 57
6248 12:13:28.485826 [CA 2] Center 36 (8~64) winsize 57
6249 12:13:28.488826 [CA 3] Center 36 (8~64) winsize 57
6250 12:13:28.492480 [CA 4] Center 36 (8~64) winsize 57
6251 12:13:28.495260 [CA 5] Center 36 (8~64) winsize 57
6252 12:13:28.495730
6253 12:13:28.498979 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6254 12:13:28.499557
6255 12:13:28.501932 [CATrainingPosCal] consider 2 rank data
6256 12:13:28.505747 u2DelayCellTimex100 = 270/100 ps
6257 12:13:28.509131 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 12:13:28.512218 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 12:13:28.518882 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 12:13:28.522330 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 12:13:28.525465 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 12:13:28.529237 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 12:13:28.529923
6264 12:13:28.532721 CA PerBit enable=1, Macro0, CA PI delay=36
6265 12:13:28.533291
6266 12:13:28.535575 [CBTSetCACLKResult] CA Dly = 36
6267 12:13:28.536147 CS Dly: 1 (0~32)
6268 12:13:28.536520
6269 12:13:28.538946 ----->DramcWriteLeveling(PI) begin...
6270 12:13:28.542188 ==
6271 12:13:28.542780 Dram Type= 6, Freq= 0, CH_0, rank 0
6272 12:13:28.548945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6273 12:13:28.549522 ==
6274 12:13:28.552312 Write leveling (Byte 0): 40 => 8
6275 12:13:28.555522 Write leveling (Byte 1): 32 => 0
6276 12:13:28.556095 DramcWriteLeveling(PI) end<-----
6277 12:13:28.558501
6278 12:13:28.558995 ==
6279 12:13:28.561986 Dram Type= 6, Freq= 0, CH_0, rank 0
6280 12:13:28.565308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6281 12:13:28.565825 ==
6282 12:13:28.568718 [Gating] SW mode calibration
6283 12:13:28.574801 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6284 12:13:28.578388 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6285 12:13:28.585355 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6286 12:13:28.588355 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6287 12:13:28.592116 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6288 12:13:28.598193 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 12:13:28.601863 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 12:13:28.605102 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 12:13:28.611347 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 12:13:28.614819 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 12:13:28.618564 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6294 12:13:28.622043 Total UI for P1: 0, mck2ui 16
6295 12:13:28.624993 best dqsien dly found for B0: ( 0, 14, 24)
6296 12:13:28.628170 Total UI for P1: 0, mck2ui 16
6297 12:13:28.631929 best dqsien dly found for B1: ( 0, 14, 24)
6298 12:13:28.634803 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6299 12:13:28.638204 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6300 12:13:28.638774
6301 12:13:28.644767 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6302 12:13:28.648069 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6303 12:13:28.651816 [Gating] SW calibration Done
6304 12:13:28.652376 ==
6305 12:13:28.654866 Dram Type= 6, Freq= 0, CH_0, rank 0
6306 12:13:28.658115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 12:13:28.658553 ==
6308 12:13:28.658961 RX Vref Scan: 0
6309 12:13:28.659358
6310 12:13:28.661295 RX Vref 0 -> 0, step: 1
6311 12:13:28.661561
6312 12:13:28.664697 RX Delay -410 -> 252, step: 16
6313 12:13:28.668139 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6314 12:13:28.674397 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6315 12:13:28.677821 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6316 12:13:28.681100 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6317 12:13:28.684637 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6318 12:13:28.691501 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6319 12:13:28.694644 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6320 12:13:28.697577 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6321 12:13:28.701274 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6322 12:13:28.704387 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6323 12:13:28.711660 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6324 12:13:28.714813 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6325 12:13:28.718633 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6326 12:13:28.724938 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6327 12:13:28.728110 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6328 12:13:28.731495 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6329 12:13:28.732063 ==
6330 12:13:28.734746 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 12:13:28.738279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 12:13:28.738859 ==
6333 12:13:28.741893 DQS Delay:
6334 12:13:28.742497 DQS0 = 27, DQS1 = 43
6335 12:13:28.744815 DQM Delay:
6336 12:13:28.745379 DQM0 = 12, DQM1 = 12
6337 12:13:28.745745 DQ Delay:
6338 12:13:28.748399 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6339 12:13:28.751648 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6340 12:13:28.754788 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6341 12:13:28.758179 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6342 12:13:28.758753
6343 12:13:28.759118
6344 12:13:28.759456 ==
6345 12:13:28.761834 Dram Type= 6, Freq= 0, CH_0, rank 0
6346 12:13:28.768128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6347 12:13:28.768678 ==
6348 12:13:28.769047
6349 12:13:28.769385
6350 12:13:28.769711 TX Vref Scan disable
6351 12:13:28.771597 == TX Byte 0 ==
6352 12:13:28.774618 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6353 12:13:28.777804 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6354 12:13:28.781271 == TX Byte 1 ==
6355 12:13:28.784667 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6356 12:13:28.788154 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6357 12:13:28.791325 ==
6358 12:13:28.794964 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 12:13:28.797796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 12:13:28.798309 ==
6361 12:13:28.798678
6362 12:13:28.799013
6363 12:13:28.801229 TX Vref Scan disable
6364 12:13:28.801785 == TX Byte 0 ==
6365 12:13:28.804609 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6366 12:13:28.811691 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6367 12:13:28.812247 == TX Byte 1 ==
6368 12:13:28.814424 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6369 12:13:28.820921 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6370 12:13:28.821468
6371 12:13:28.821826 [DATLAT]
6372 12:13:28.822196 Freq=400, CH0 RK0
6373 12:13:28.822544
6374 12:13:28.824255 DATLAT Default: 0xf
6375 12:13:28.827529 0, 0xFFFF, sum = 0
6376 12:13:28.828001 1, 0xFFFF, sum = 0
6377 12:13:28.831063 2, 0xFFFF, sum = 0
6378 12:13:28.831625 3, 0xFFFF, sum = 0
6379 12:13:28.834971 4, 0xFFFF, sum = 0
6380 12:13:28.835539 5, 0xFFFF, sum = 0
6381 12:13:28.837898 6, 0xFFFF, sum = 0
6382 12:13:28.838509 7, 0xFFFF, sum = 0
6383 12:13:28.841427 8, 0xFFFF, sum = 0
6384 12:13:28.842047 9, 0xFFFF, sum = 0
6385 12:13:28.844351 10, 0xFFFF, sum = 0
6386 12:13:28.845109 11, 0xFFFF, sum = 0
6387 12:13:28.847483 12, 0xFFFF, sum = 0
6388 12:13:28.847949 13, 0x0, sum = 1
6389 12:13:28.851100 14, 0x0, sum = 2
6390 12:13:28.851669 15, 0x0, sum = 3
6391 12:13:28.854232 16, 0x0, sum = 4
6392 12:13:28.854793 best_step = 14
6393 12:13:28.855154
6394 12:13:28.855489 ==
6395 12:13:28.857588 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 12:13:28.860995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 12:13:28.864413 ==
6398 12:13:28.864980 RX Vref Scan: 1
6399 12:13:28.865347
6400 12:13:28.867460 RX Vref 0 -> 0, step: 1
6401 12:13:28.867955
6402 12:13:28.870978 RX Delay -327 -> 252, step: 8
6403 12:13:28.871534
6404 12:13:28.874235 Set Vref, RX VrefLevel [Byte0]: 57
6405 12:13:28.877544 [Byte1]: 51
6406 12:13:28.878259
6407 12:13:28.880434 Final RX Vref Byte 0 = 57 to rank0
6408 12:13:28.884229 Final RX Vref Byte 1 = 51 to rank0
6409 12:13:28.887361 Final RX Vref Byte 0 = 57 to rank1
6410 12:13:28.890841 Final RX Vref Byte 1 = 51 to rank1==
6411 12:13:28.894444 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 12:13:28.897481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 12:13:28.898075 ==
6414 12:13:28.900696 DQS Delay:
6415 12:13:28.901252 DQS0 = 24, DQS1 = 48
6416 12:13:28.903937 DQM Delay:
6417 12:13:28.904392 DQM0 = 8, DQM1 = 16
6418 12:13:28.904748 DQ Delay:
6419 12:13:28.907409 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6420 12:13:28.910969 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6421 12:13:28.914194 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6422 12:13:28.917284 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6423 12:13:28.917838
6424 12:13:28.918265
6425 12:13:28.927310 [DQSOSCAuto] RK0, (LSB)MR18= 0xada5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6426 12:13:28.927874 CH0 RK0: MR19=C0C, MR18=ADA5
6427 12:13:28.934154 CH0_RK0: MR19=0xC0C, MR18=0xADA5, DQSOSC=388, MR23=63, INC=392, DEC=261
6428 12:13:28.934719 ==
6429 12:13:28.937018 Dram Type= 6, Freq= 0, CH_0, rank 1
6430 12:13:28.944255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6431 12:13:28.944891 ==
6432 12:13:28.947214 [Gating] SW mode calibration
6433 12:13:28.953508 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6434 12:13:28.957150 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6435 12:13:28.963362 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6436 12:13:28.966750 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6437 12:13:28.970111 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6438 12:13:28.977003 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 12:13:28.980599 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 12:13:28.983673 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 12:13:28.990098 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 12:13:28.993463 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6443 12:13:28.997074 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6444 12:13:29.000152 Total UI for P1: 0, mck2ui 16
6445 12:13:29.003373 best dqsien dly found for B0: ( 0, 14, 24)
6446 12:13:29.007013 Total UI for P1: 0, mck2ui 16
6447 12:13:29.010256 best dqsien dly found for B1: ( 0, 14, 24)
6448 12:13:29.013424 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6449 12:13:29.016708 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6450 12:13:29.017285
6451 12:13:29.020813 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6452 12:13:29.026874 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6453 12:13:29.027453 [Gating] SW calibration Done
6454 12:13:29.027829 ==
6455 12:13:29.030529 Dram Type= 6, Freq= 0, CH_0, rank 1
6456 12:13:29.036878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6457 12:13:29.037451 ==
6458 12:13:29.037822 RX Vref Scan: 0
6459 12:13:29.038206
6460 12:13:29.040617 RX Vref 0 -> 0, step: 1
6461 12:13:29.041188
6462 12:13:29.043743 RX Delay -410 -> 252, step: 16
6463 12:13:29.046905 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6464 12:13:29.050535 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6465 12:13:29.056895 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6466 12:13:29.060725 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6467 12:13:29.063556 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6468 12:13:29.066804 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6469 12:13:29.073380 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6470 12:13:29.076804 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6471 12:13:29.080027 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6472 12:13:29.083551 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6473 12:13:29.090134 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6474 12:13:29.093445 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6475 12:13:29.096638 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6476 12:13:29.099871 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6477 12:13:29.106599 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6478 12:13:29.110069 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6479 12:13:29.110637 ==
6480 12:13:29.113253 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 12:13:29.116890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 12:13:29.117466 ==
6483 12:13:29.119818 DQS Delay:
6484 12:13:29.120390 DQS0 = 27, DQS1 = 35
6485 12:13:29.123099 DQM Delay:
6486 12:13:29.123706 DQM0 = 9, DQM1 = 8
6487 12:13:29.124078 DQ Delay:
6488 12:13:29.126991 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6489 12:13:29.130170 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6490 12:13:29.133588 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6491 12:13:29.136161 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =16
6492 12:13:29.136668
6493 12:13:29.137036
6494 12:13:29.137376 ==
6495 12:13:29.139735 Dram Type= 6, Freq= 0, CH_0, rank 1
6496 12:13:29.142973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6497 12:13:29.143548 ==
6498 12:13:29.146557
6499 12:13:29.147127
6500 12:13:29.147497 TX Vref Scan disable
6501 12:13:29.149587 == TX Byte 0 ==
6502 12:13:29.153197 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6503 12:13:29.156343 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6504 12:13:29.159485 == TX Byte 1 ==
6505 12:13:29.163036 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6506 12:13:29.166400 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6507 12:13:29.166970 ==
6508 12:13:29.169161 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 12:13:29.172806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 12:13:29.176041 ==
6511 12:13:29.176604
6512 12:13:29.176976
6513 12:13:29.177318 TX Vref Scan disable
6514 12:13:29.179793 == TX Byte 0 ==
6515 12:13:29.182565 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6516 12:13:29.186031 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6517 12:13:29.189181 == TX Byte 1 ==
6518 12:13:29.192882 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6519 12:13:29.195633 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6520 12:13:29.196099
6521 12:13:29.199626 [DATLAT]
6522 12:13:29.200183 Freq=400, CH0 RK1
6523 12:13:29.200556
6524 12:13:29.202730 DATLAT Default: 0xe
6525 12:13:29.203354 0, 0xFFFF, sum = 0
6526 12:13:29.206000 1, 0xFFFF, sum = 0
6527 12:13:29.206594 2, 0xFFFF, sum = 0
6528 12:13:29.208883 3, 0xFFFF, sum = 0
6529 12:13:29.209355 4, 0xFFFF, sum = 0
6530 12:13:29.212594 5, 0xFFFF, sum = 0
6531 12:13:29.213065 6, 0xFFFF, sum = 0
6532 12:13:29.215453 7, 0xFFFF, sum = 0
6533 12:13:29.215948 8, 0xFFFF, sum = 0
6534 12:13:29.219456 9, 0xFFFF, sum = 0
6535 12:13:29.220021 10, 0xFFFF, sum = 0
6536 12:13:29.222514 11, 0xFFFF, sum = 0
6537 12:13:29.223088 12, 0xFFFF, sum = 0
6538 12:13:29.226195 13, 0x0, sum = 1
6539 12:13:29.226768 14, 0x0, sum = 2
6540 12:13:29.229117 15, 0x0, sum = 3
6541 12:13:29.229687 16, 0x0, sum = 4
6542 12:13:29.232564 best_step = 14
6543 12:13:29.233125
6544 12:13:29.233494 ==
6545 12:13:29.235529 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 12:13:29.238959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 12:13:29.239541 ==
6548 12:13:29.242507 RX Vref Scan: 0
6549 12:13:29.243070
6550 12:13:29.243439 RX Vref 0 -> 0, step: 1
6551 12:13:29.243787
6552 12:13:29.245637 RX Delay -311 -> 252, step: 8
6553 12:13:29.254055 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6554 12:13:29.257181 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6555 12:13:29.260145 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6556 12:13:29.263322 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6557 12:13:29.270105 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6558 12:13:29.273308 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6559 12:13:29.276760 iDelay=217, Bit 6, Center -12 (-239 ~ 216) 456
6560 12:13:29.280340 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6561 12:13:29.286729 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6562 12:13:29.290243 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6563 12:13:29.293356 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6564 12:13:29.297061 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6565 12:13:29.303659 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6566 12:13:29.306684 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6567 12:13:29.309785 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6568 12:13:29.316878 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6569 12:13:29.317451 ==
6570 12:13:29.320037 Dram Type= 6, Freq= 0, CH_0, rank 1
6571 12:13:29.323279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6572 12:13:29.323867 ==
6573 12:13:29.324241 DQS Delay:
6574 12:13:29.327202 DQS0 = 28, DQS1 = 44
6575 12:13:29.327772 DQM Delay:
6576 12:13:29.330042 DQM0 = 9, DQM1 = 15
6577 12:13:29.330608 DQ Delay:
6578 12:13:29.333638 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6579 12:13:29.336796 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6580 12:13:29.339965 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6581 12:13:29.343463 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =20
6582 12:13:29.344036
6583 12:13:29.344402
6584 12:13:29.349769 [DQSOSCAuto] RK1, (LSB)MR18= 0xb469, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6585 12:13:29.353594 CH0 RK1: MR19=C0C, MR18=B469
6586 12:13:29.359930 CH0_RK1: MR19=0xC0C, MR18=0xB469, DQSOSC=387, MR23=63, INC=394, DEC=262
6587 12:13:29.363123 [RxdqsGatingPostProcess] freq 400
6588 12:13:29.369814 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6589 12:13:29.370556 best DQS0 dly(2T, 0.5T) = (0, 10)
6590 12:13:29.373366 best DQS1 dly(2T, 0.5T) = (0, 10)
6591 12:13:29.376592 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6592 12:13:29.379707 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6593 12:13:29.383103 best DQS0 dly(2T, 0.5T) = (0, 10)
6594 12:13:29.386370 best DQS1 dly(2T, 0.5T) = (0, 10)
6595 12:13:29.389719 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6596 12:13:29.392887 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6597 12:13:29.396115 Pre-setting of DQS Precalculation
6598 12:13:29.403140 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6599 12:13:29.403751 ==
6600 12:13:29.406313 Dram Type= 6, Freq= 0, CH_1, rank 0
6601 12:13:29.409358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 12:13:29.409828 ==
6603 12:13:29.416182 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6604 12:13:29.419150 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6605 12:13:29.423215 [CA 0] Center 36 (8~64) winsize 57
6606 12:13:29.425748 [CA 1] Center 36 (8~64) winsize 57
6607 12:13:29.429433 [CA 2] Center 36 (8~64) winsize 57
6608 12:13:29.433367 [CA 3] Center 36 (8~64) winsize 57
6609 12:13:29.436019 [CA 4] Center 36 (8~64) winsize 57
6610 12:13:29.439317 [CA 5] Center 36 (8~64) winsize 57
6611 12:13:29.439888
6612 12:13:29.442667 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6613 12:13:29.443154
6614 12:13:29.445989 [CATrainingPosCal] consider 1 rank data
6615 12:13:29.449214 u2DelayCellTimex100 = 270/100 ps
6616 12:13:29.452221 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 12:13:29.456063 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 12:13:29.459286 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 12:13:29.462838 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 12:13:29.469365 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 12:13:29.472579 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 12:13:29.473147
6623 12:13:29.475883 CA PerBit enable=1, Macro0, CA PI delay=36
6624 12:13:29.476357
6625 12:13:29.479140 [CBTSetCACLKResult] CA Dly = 36
6626 12:13:29.479606 CS Dly: 1 (0~32)
6627 12:13:29.479976 ==
6628 12:13:29.482237 Dram Type= 6, Freq= 0, CH_1, rank 1
6629 12:13:29.489310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6630 12:13:29.489891 ==
6631 12:13:29.492299 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6632 12:13:29.498835 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6633 12:13:29.502428 [CA 0] Center 36 (8~64) winsize 57
6634 12:13:29.506124 [CA 1] Center 36 (8~64) winsize 57
6635 12:13:29.509070 [CA 2] Center 36 (8~64) winsize 57
6636 12:13:29.512326 [CA 3] Center 36 (8~64) winsize 57
6637 12:13:29.515424 [CA 4] Center 36 (8~64) winsize 57
6638 12:13:29.518664 [CA 5] Center 36 (8~64) winsize 57
6639 12:13:29.519133
6640 12:13:29.522238 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6641 12:13:29.522703
6642 12:13:29.525577 [CATrainingPosCal] consider 2 rank data
6643 12:13:29.529160 u2DelayCellTimex100 = 270/100 ps
6644 12:13:29.532095 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 12:13:29.535859 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 12:13:29.538971 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 12:13:29.542272 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 12:13:29.545617 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 12:13:29.548589 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 12:13:29.549158
6651 12:13:29.555362 CA PerBit enable=1, Macro0, CA PI delay=36
6652 12:13:29.555935
6653 12:13:29.558819 [CBTSetCACLKResult] CA Dly = 36
6654 12:13:29.559388 CS Dly: 1 (0~32)
6655 12:13:29.559759
6656 12:13:29.562363 ----->DramcWriteLeveling(PI) begin...
6657 12:13:29.562944 ==
6658 12:13:29.566056 Dram Type= 6, Freq= 0, CH_1, rank 0
6659 12:13:29.568677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6660 12:13:29.569250 ==
6661 12:13:29.572113 Write leveling (Byte 0): 40 => 8
6662 12:13:29.575078 Write leveling (Byte 1): 32 => 0
6663 12:13:29.578796 DramcWriteLeveling(PI) end<-----
6664 12:13:29.579372
6665 12:13:29.579892 ==
6666 12:13:29.581680 Dram Type= 6, Freq= 0, CH_1, rank 0
6667 12:13:29.585520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6668 12:13:29.588618 ==
6669 12:13:29.589236 [Gating] SW mode calibration
6670 12:13:29.598540 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6671 12:13:29.602319 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6672 12:13:29.605333 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6673 12:13:29.611983 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6674 12:13:29.615670 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6675 12:13:29.618638 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6676 12:13:29.625142 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 12:13:29.628538 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 12:13:29.631872 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 12:13:29.638436 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 12:13:29.641562 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6681 12:13:29.644788 Total UI for P1: 0, mck2ui 16
6682 12:13:29.648439 best dqsien dly found for B0: ( 0, 14, 24)
6683 12:13:29.651787 Total UI for P1: 0, mck2ui 16
6684 12:13:29.655321 best dqsien dly found for B1: ( 0, 14, 24)
6685 12:13:29.658371 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6686 12:13:29.662218 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6687 12:13:29.662794
6688 12:13:29.664698 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6689 12:13:29.668685 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6690 12:13:29.671610 [Gating] SW calibration Done
6691 12:13:29.672076 ==
6692 12:13:29.674868 Dram Type= 6, Freq= 0, CH_1, rank 0
6693 12:13:29.678490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 12:13:29.681858 ==
6695 12:13:29.682523 RX Vref Scan: 0
6696 12:13:29.682902
6697 12:13:29.684985 RX Vref 0 -> 0, step: 1
6698 12:13:29.685589
6699 12:13:29.688578 RX Delay -410 -> 252, step: 16
6700 12:13:29.691635 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6701 12:13:29.695245 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6702 12:13:29.698368 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6703 12:13:29.705187 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6704 12:13:29.708503 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6705 12:13:29.711997 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6706 12:13:29.715064 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6707 12:13:29.721565 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6708 12:13:29.725072 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6709 12:13:29.728514 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6710 12:13:29.731709 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6711 12:13:29.738454 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6712 12:13:29.741443 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6713 12:13:29.745081 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6714 12:13:29.748298 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6715 12:13:29.754780 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6716 12:13:29.755404 ==
6717 12:13:29.758026 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 12:13:29.761739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 12:13:29.762349 ==
6720 12:13:29.762727 DQS Delay:
6721 12:13:29.764714 DQS0 = 27, DQS1 = 43
6722 12:13:29.765177 DQM Delay:
6723 12:13:29.768263 DQM0 = 6, DQM1 = 17
6724 12:13:29.768819 DQ Delay:
6725 12:13:29.771405 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6726 12:13:29.774307 DQ4 =0, DQ5 =24, DQ6 =16, DQ7 =0
6727 12:13:29.777701 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6728 12:13:29.781580 DQ12 =24, DQ13 =32, DQ14 =16, DQ15 =24
6729 12:13:29.782198
6730 12:13:29.782575
6731 12:13:29.782916 ==
6732 12:13:29.784904 Dram Type= 6, Freq= 0, CH_1, rank 0
6733 12:13:29.787711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6734 12:13:29.788281 ==
6735 12:13:29.788655
6736 12:13:29.788993
6737 12:13:29.791066 TX Vref Scan disable
6738 12:13:29.794849 == TX Byte 0 ==
6739 12:13:29.798544 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6740 12:13:29.801555 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6741 12:13:29.802155 == TX Byte 1 ==
6742 12:13:29.808024 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6743 12:13:29.811746 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6744 12:13:29.812317 ==
6745 12:13:29.814585 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 12:13:29.818142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 12:13:29.818708 ==
6748 12:13:29.821255
6749 12:13:29.821823
6750 12:13:29.822229 TX Vref Scan disable
6751 12:13:29.824605 == TX Byte 0 ==
6752 12:13:29.827752 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6753 12:13:29.831364 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6754 12:13:29.834423 == TX Byte 1 ==
6755 12:13:29.837642 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6756 12:13:29.841142 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6757 12:13:29.841706
6758 12:13:29.842107 [DATLAT]
6759 12:13:29.844971 Freq=400, CH1 RK0
6760 12:13:29.845540
6761 12:13:29.847886 DATLAT Default: 0xf
6762 12:13:29.848475 0, 0xFFFF, sum = 0
6763 12:13:29.850887 1, 0xFFFF, sum = 0
6764 12:13:29.851361 2, 0xFFFF, sum = 0
6765 12:13:29.854369 3, 0xFFFF, sum = 0
6766 12:13:29.854944 4, 0xFFFF, sum = 0
6767 12:13:29.858147 5, 0xFFFF, sum = 0
6768 12:13:29.858723 6, 0xFFFF, sum = 0
6769 12:13:29.861023 7, 0xFFFF, sum = 0
6770 12:13:29.861599 8, 0xFFFF, sum = 0
6771 12:13:29.864499 9, 0xFFFF, sum = 0
6772 12:13:29.865085 10, 0xFFFF, sum = 0
6773 12:13:29.867992 11, 0xFFFF, sum = 0
6774 12:13:29.868564 12, 0xFFFF, sum = 0
6775 12:13:29.870723 13, 0x0, sum = 1
6776 12:13:29.871196 14, 0x0, sum = 2
6777 12:13:29.874244 15, 0x0, sum = 3
6778 12:13:29.874717 16, 0x0, sum = 4
6779 12:13:29.877585 best_step = 14
6780 12:13:29.878206
6781 12:13:29.878604 ==
6782 12:13:29.881031 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 12:13:29.884381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 12:13:29.884957 ==
6785 12:13:29.887911 RX Vref Scan: 1
6786 12:13:29.888477
6787 12:13:29.888844 RX Vref 0 -> 0, step: 1
6788 12:13:29.889187
6789 12:13:29.891134 RX Delay -327 -> 252, step: 8
6790 12:13:29.891600
6791 12:13:29.894201 Set Vref, RX VrefLevel [Byte0]: 53
6792 12:13:29.897536 [Byte1]: 53
6793 12:13:29.902078
6794 12:13:29.902635 Final RX Vref Byte 0 = 53 to rank0
6795 12:13:29.905117 Final RX Vref Byte 1 = 53 to rank0
6796 12:13:29.908446 Final RX Vref Byte 0 = 53 to rank1
6797 12:13:29.912280 Final RX Vref Byte 1 = 53 to rank1==
6798 12:13:29.915456 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 12:13:29.922099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 12:13:29.922670 ==
6801 12:13:29.923047 DQS Delay:
6802 12:13:29.925371 DQS0 = 28, DQS1 = 40
6803 12:13:29.925836 DQM Delay:
6804 12:13:29.926245 DQM0 = 7, DQM1 = 13
6805 12:13:29.928735 DQ Delay:
6806 12:13:29.931613 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6807 12:13:29.932106 DQ4 =4, DQ5 =12, DQ6 =16, DQ7 =4
6808 12:13:29.934978 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6809 12:13:29.938650 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =20
6810 12:13:29.939326
6811 12:13:29.939704
6812 12:13:29.948394 [DQSOSCAuto] RK0, (LSB)MR18= 0x91cb, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6813 12:13:29.951809 CH1 RK0: MR19=C0C, MR18=91CB
6814 12:13:29.958529 CH1_RK0: MR19=0xC0C, MR18=0x91CB, DQSOSC=384, MR23=63, INC=400, DEC=267
6815 12:13:29.959104 ==
6816 12:13:29.961831 Dram Type= 6, Freq= 0, CH_1, rank 1
6817 12:13:29.965140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6818 12:13:29.965609 ==
6819 12:13:29.968416 [Gating] SW mode calibration
6820 12:13:29.974988 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6821 12:13:29.978262 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6822 12:13:29.984903 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6823 12:13:29.988074 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6824 12:13:29.991708 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6825 12:13:29.997806 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6826 12:13:30.001339 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 12:13:30.004711 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 12:13:30.011684 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 12:13:30.014625 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6830 12:13:30.018226 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6831 12:13:30.021058 Total UI for P1: 0, mck2ui 16
6832 12:13:30.024698 best dqsien dly found for B0: ( 0, 14, 24)
6833 12:13:30.027911 Total UI for P1: 0, mck2ui 16
6834 12:13:30.031412 best dqsien dly found for B1: ( 0, 14, 24)
6835 12:13:30.034645 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6836 12:13:30.038154 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6837 12:13:30.041054
6838 12:13:30.045411 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6839 12:13:30.048078 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6840 12:13:30.051422 [Gating] SW calibration Done
6841 12:13:30.052046 ==
6842 12:13:30.054503 Dram Type= 6, Freq= 0, CH_1, rank 1
6843 12:13:30.058064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6844 12:13:30.058635 ==
6845 12:13:30.059012 RX Vref Scan: 0
6846 12:13:30.061138
6847 12:13:30.061605 RX Vref 0 -> 0, step: 1
6848 12:13:30.062017
6849 12:13:30.064530 RX Delay -410 -> 252, step: 16
6850 12:13:30.067744 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6851 12:13:30.074274 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6852 12:13:30.077470 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6853 12:13:30.080874 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6854 12:13:30.084552 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6855 12:13:30.091141 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6856 12:13:30.094694 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6857 12:13:30.097867 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6858 12:13:30.101513 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6859 12:13:30.107526 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6860 12:13:30.110971 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6861 12:13:30.114654 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6862 12:13:30.117599 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6863 12:13:30.124134 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6864 12:13:30.127611 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6865 12:13:30.131109 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6866 12:13:30.131686 ==
6867 12:13:30.134533 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 12:13:30.137510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 12:13:30.141240 ==
6870 12:13:30.141814 DQS Delay:
6871 12:13:30.142237 DQS0 = 35, DQS1 = 43
6872 12:13:30.144294 DQM Delay:
6873 12:13:30.144868 DQM0 = 18, DQM1 = 18
6874 12:13:30.147229 DQ Delay:
6875 12:13:30.150864 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6876 12:13:30.151442 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6877 12:13:30.154384 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6878 12:13:30.157464 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6879 12:13:30.158096
6880 12:13:30.161004
6881 12:13:30.161580 ==
6882 12:13:30.164304 Dram Type= 6, Freq= 0, CH_1, rank 1
6883 12:13:30.167953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6884 12:13:30.168531 ==
6885 12:13:30.168902
6886 12:13:30.169245
6887 12:13:30.170843 TX Vref Scan disable
6888 12:13:30.171311 == TX Byte 0 ==
6889 12:13:30.174017 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6890 12:13:30.180723 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6891 12:13:30.181307 == TX Byte 1 ==
6892 12:13:30.183771 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6893 12:13:30.190549 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6894 12:13:30.191131 ==
6895 12:13:30.194180 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 12:13:30.197413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 12:13:30.198046 ==
6898 12:13:30.198437
6899 12:13:30.198804
6900 12:13:30.200611 TX Vref Scan disable
6901 12:13:30.201196 == TX Byte 0 ==
6902 12:13:30.204307 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6903 12:13:30.210586 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6904 12:13:30.211167 == TX Byte 1 ==
6905 12:13:30.213913 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6906 12:13:30.220188 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6907 12:13:30.220839
6908 12:13:30.221223 [DATLAT]
6909 12:13:30.221575 Freq=400, CH1 RK1
6910 12:13:30.223817
6911 12:13:30.224413 DATLAT Default: 0xe
6912 12:13:30.226983 0, 0xFFFF, sum = 0
6913 12:13:30.227577 1, 0xFFFF, sum = 0
6914 12:13:30.230321 2, 0xFFFF, sum = 0
6915 12:13:30.230979 3, 0xFFFF, sum = 0
6916 12:13:30.233630 4, 0xFFFF, sum = 0
6917 12:13:30.234259 5, 0xFFFF, sum = 0
6918 12:13:30.237423 6, 0xFFFF, sum = 0
6919 12:13:30.238045 7, 0xFFFF, sum = 0
6920 12:13:30.240414 8, 0xFFFF, sum = 0
6921 12:13:30.241010 9, 0xFFFF, sum = 0
6922 12:13:30.243792 10, 0xFFFF, sum = 0
6923 12:13:30.244386 11, 0xFFFF, sum = 0
6924 12:13:30.247060 12, 0xFFFF, sum = 0
6925 12:13:30.247543 13, 0x0, sum = 1
6926 12:13:30.250195 14, 0x0, sum = 2
6927 12:13:30.250788 15, 0x0, sum = 3
6928 12:13:30.253235 16, 0x0, sum = 4
6929 12:13:30.253716 best_step = 14
6930 12:13:30.254129
6931 12:13:30.254478 ==
6932 12:13:30.257063 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 12:13:30.263829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 12:13:30.264417 ==
6935 12:13:30.264800 RX Vref Scan: 0
6936 12:13:30.265156
6937 12:13:30.266930 RX Vref 0 -> 0, step: 1
6938 12:13:30.267516
6939 12:13:30.270072 RX Delay -327 -> 252, step: 8
6940 12:13:30.276593 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6941 12:13:30.280098 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6942 12:13:30.283323 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6943 12:13:30.287037 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6944 12:13:30.293647 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6945 12:13:30.297086 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6946 12:13:30.300368 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6947 12:13:30.303712 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6948 12:13:30.306842 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6949 12:13:30.313846 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6950 12:13:30.316909 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6951 12:13:30.320542 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6952 12:13:30.323774 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6953 12:13:30.330157 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6954 12:13:30.334041 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6955 12:13:30.337140 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6956 12:13:30.337738 ==
6957 12:13:30.340412 Dram Type= 6, Freq= 0, CH_1, rank 1
6958 12:13:30.346906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6959 12:13:30.347498 ==
6960 12:13:30.347881 DQS Delay:
6961 12:13:30.350040 DQS0 = 32, DQS1 = 36
6962 12:13:30.350618 DQM Delay:
6963 12:13:30.350997 DQM0 = 13, DQM1 = 11
6964 12:13:30.353702 DQ Delay:
6965 12:13:30.356992 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =12
6966 12:13:30.360336 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =8
6967 12:13:30.360919 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6968 12:13:30.363247 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6969 12:13:30.366617
6970 12:13:30.367091
6971 12:13:30.373669 [DQSOSCAuto] RK1, (LSB)MR18= 0xa952, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6972 12:13:30.376701 CH1 RK1: MR19=C0C, MR18=A952
6973 12:13:30.383474 CH1_RK1: MR19=0xC0C, MR18=0xA952, DQSOSC=388, MR23=63, INC=392, DEC=261
6974 12:13:30.386443 [RxdqsGatingPostProcess] freq 400
6975 12:13:30.389845 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6976 12:13:30.393281 best DQS0 dly(2T, 0.5T) = (0, 10)
6977 12:13:30.396994 best DQS1 dly(2T, 0.5T) = (0, 10)
6978 12:13:30.400235 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6979 12:13:30.403894 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6980 12:13:30.406680 best DQS0 dly(2T, 0.5T) = (0, 10)
6981 12:13:30.410426 best DQS1 dly(2T, 0.5T) = (0, 10)
6982 12:13:30.413566 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6983 12:13:30.416995 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6984 12:13:30.419987 Pre-setting of DQS Precalculation
6985 12:13:30.423379 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6986 12:13:30.433495 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6987 12:13:30.439814 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6988 12:13:30.440386
6989 12:13:30.440762
6990 12:13:30.442882 [Calibration Summary] 800 Mbps
6991 12:13:30.443387 CH 0, Rank 0
6992 12:13:30.446427 SW Impedance : PASS
6993 12:13:30.446904 DUTY Scan : NO K
6994 12:13:30.449657 ZQ Calibration : PASS
6995 12:13:30.452954 Jitter Meter : NO K
6996 12:13:30.453520 CBT Training : PASS
6997 12:13:30.456096 Write leveling : PASS
6998 12:13:30.459974 RX DQS gating : PASS
6999 12:13:30.460549 RX DQ/DQS(RDDQC) : PASS
7000 12:13:30.462995 TX DQ/DQS : PASS
7001 12:13:30.463469 RX DATLAT : PASS
7002 12:13:30.466224 RX DQ/DQS(Engine): PASS
7003 12:13:30.469831 TX OE : NO K
7004 12:13:30.470437 All Pass.
7005 12:13:30.470817
7006 12:13:30.471195 CH 0, Rank 1
7007 12:13:30.472568 SW Impedance : PASS
7008 12:13:30.476022 DUTY Scan : NO K
7009 12:13:30.476511 ZQ Calibration : PASS
7010 12:13:30.479677 Jitter Meter : NO K
7011 12:13:30.482581 CBT Training : PASS
7012 12:13:30.483058 Write leveling : NO K
7013 12:13:30.485776 RX DQS gating : PASS
7014 12:13:30.489111 RX DQ/DQS(RDDQC) : PASS
7015 12:13:30.489587 TX DQ/DQS : PASS
7016 12:13:30.492849 RX DATLAT : PASS
7017 12:13:30.496742 RX DQ/DQS(Engine): PASS
7018 12:13:30.497372 TX OE : NO K
7019 12:13:30.499254 All Pass.
7020 12:13:30.499728
7021 12:13:30.500099 CH 1, Rank 0
7022 12:13:30.502689 SW Impedance : PASS
7023 12:13:30.503165 DUTY Scan : NO K
7024 12:13:30.505572 ZQ Calibration : PASS
7025 12:13:30.509298 Jitter Meter : NO K
7026 12:13:30.509869 CBT Training : PASS
7027 12:13:30.512387 Write leveling : PASS
7028 12:13:30.515905 RX DQS gating : PASS
7029 12:13:30.516476 RX DQ/DQS(RDDQC) : PASS
7030 12:13:30.519096 TX DQ/DQS : PASS
7031 12:13:30.519572 RX DATLAT : PASS
7032 12:13:30.522777 RX DQ/DQS(Engine): PASS
7033 12:13:30.525712 TX OE : NO K
7034 12:13:30.526347 All Pass.
7035 12:13:30.526730
7036 12:13:30.529384 CH 1, Rank 1
7037 12:13:30.529983 SW Impedance : PASS
7038 12:13:30.532229 DUTY Scan : NO K
7039 12:13:30.532710 ZQ Calibration : PASS
7040 12:13:30.535878 Jitter Meter : NO K
7041 12:13:30.538953 CBT Training : PASS
7042 12:13:30.539529 Write leveling : NO K
7043 12:13:30.542604 RX DQS gating : PASS
7044 12:13:30.545832 RX DQ/DQS(RDDQC) : PASS
7045 12:13:30.546453 TX DQ/DQS : PASS
7046 12:13:30.549025 RX DATLAT : PASS
7047 12:13:30.552339 RX DQ/DQS(Engine): PASS
7048 12:13:30.552906 TX OE : NO K
7049 12:13:30.555339 All Pass.
7050 12:13:30.555812
7051 12:13:30.556184 DramC Write-DBI off
7052 12:13:30.558776 PER_BANK_REFRESH: Hybrid Mode
7053 12:13:30.559345 TX_TRACKING: ON
7054 12:13:30.569004 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7055 12:13:30.572375 [FAST_K] Save calibration result to emmc
7056 12:13:30.575554 dramc_set_vcore_voltage set vcore to 725000
7057 12:13:30.578961 Read voltage for 1600, 0
7058 12:13:30.579433 Vio18 = 0
7059 12:13:30.582058 Vcore = 725000
7060 12:13:30.582529 Vdram = 0
7061 12:13:30.582898 Vddq = 0
7062 12:13:30.585349 Vmddr = 0
7063 12:13:30.588905 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7064 12:13:30.595407 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7065 12:13:30.595987 MEM_TYPE=3, freq_sel=13
7066 12:13:30.598540 sv_algorithm_assistance_LP4_3733
7067 12:13:30.605392 ============ PULL DRAM RESETB DOWN ============
7068 12:13:30.608410 ========== PULL DRAM RESETB DOWN end =========
7069 12:13:30.612025 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7070 12:13:30.615554 ===================================
7071 12:13:30.618704 LPDDR4 DRAM CONFIGURATION
7072 12:13:30.622035 ===================================
7073 12:13:30.622607 EX_ROW_EN[0] = 0x0
7074 12:13:30.625499 EX_ROW_EN[1] = 0x0
7075 12:13:30.628547 LP4Y_EN = 0x0
7076 12:13:30.629014 WORK_FSP = 0x1
7077 12:13:30.631533 WL = 0x5
7078 12:13:30.632002 RL = 0x5
7079 12:13:30.634888 BL = 0x2
7080 12:13:30.635357 RPST = 0x0
7081 12:13:30.638275 RD_PRE = 0x0
7082 12:13:30.638860 WR_PRE = 0x1
7083 12:13:30.641343 WR_PST = 0x1
7084 12:13:30.641810 DBI_WR = 0x0
7085 12:13:30.645087 DBI_RD = 0x0
7086 12:13:30.645668 OTF = 0x1
7087 12:13:30.648136 ===================================
7088 12:13:30.651937 ===================================
7089 12:13:30.654743 ANA top config
7090 12:13:30.658408 ===================================
7091 12:13:30.659012 DLL_ASYNC_EN = 0
7092 12:13:30.661815 ALL_SLAVE_EN = 0
7093 12:13:30.665314 NEW_RANK_MODE = 1
7094 12:13:30.668778 DLL_IDLE_MODE = 1
7095 12:13:30.671689 LP45_APHY_COMB_EN = 1
7096 12:13:30.672287 TX_ODT_DIS = 0
7097 12:13:30.674875 NEW_8X_MODE = 1
7098 12:13:30.678309 ===================================
7099 12:13:30.681621 ===================================
7100 12:13:30.684675 data_rate = 3200
7101 12:13:30.688227 CKR = 1
7102 12:13:30.691331 DQ_P2S_RATIO = 8
7103 12:13:30.694705 ===================================
7104 12:13:30.698388 CA_P2S_RATIO = 8
7105 12:13:30.698969 DQ_CA_OPEN = 0
7106 12:13:30.701650 DQ_SEMI_OPEN = 0
7107 12:13:30.705089 CA_SEMI_OPEN = 0
7108 12:13:30.708383 CA_FULL_RATE = 0
7109 12:13:30.711321 DQ_CKDIV4_EN = 0
7110 12:13:30.714545 CA_CKDIV4_EN = 0
7111 12:13:30.715127 CA_PREDIV_EN = 0
7112 12:13:30.718109 PH8_DLY = 12
7113 12:13:30.721329 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7114 12:13:30.724885 DQ_AAMCK_DIV = 4
7115 12:13:30.728009 CA_AAMCK_DIV = 4
7116 12:13:30.731533 CA_ADMCK_DIV = 4
7117 12:13:30.732143 DQ_TRACK_CA_EN = 0
7118 12:13:30.734825 CA_PICK = 1600
7119 12:13:30.738535 CA_MCKIO = 1600
7120 12:13:30.741878 MCKIO_SEMI = 0
7121 12:13:30.744670 PLL_FREQ = 3068
7122 12:13:30.748059 DQ_UI_PI_RATIO = 32
7123 12:13:30.751258 CA_UI_PI_RATIO = 0
7124 12:13:30.755091 ===================================
7125 12:13:30.757579 ===================================
7126 12:13:30.758054 memory_type:LPDDR4
7127 12:13:30.761114 GP_NUM : 10
7128 12:13:30.761518 SRAM_EN : 1
7129 12:13:30.765078 MD32_EN : 0
7130 12:13:30.767845 ===================================
7131 12:13:30.771326 [ANA_INIT] >>>>>>>>>>>>>>
7132 12:13:30.774555 <<<<<< [CONFIGURE PHASE]: ANA_TX
7133 12:13:30.777545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7134 12:13:30.781050 ===================================
7135 12:13:30.784410 data_rate = 3200,PCW = 0X7600
7136 12:13:30.787574 ===================================
7137 12:13:30.791022 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7138 12:13:30.794180 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7139 12:13:30.801565 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7140 12:13:30.804308 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7141 12:13:30.807701 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7142 12:13:30.810942 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7143 12:13:30.814512 [ANA_INIT] flow start
7144 12:13:30.817828 [ANA_INIT] PLL >>>>>>>>
7145 12:13:30.818450 [ANA_INIT] PLL <<<<<<<<
7146 12:13:30.821606 [ANA_INIT] MIDPI >>>>>>>>
7147 12:13:30.824147 [ANA_INIT] MIDPI <<<<<<<<
7148 12:13:30.824724 [ANA_INIT] DLL >>>>>>>>
7149 12:13:30.827386 [ANA_INIT] DLL <<<<<<<<
7150 12:13:30.831160 [ANA_INIT] flow end
7151 12:13:30.834062 ============ LP4 DIFF to SE enter ============
7152 12:13:30.837619 ============ LP4 DIFF to SE exit ============
7153 12:13:30.840742 [ANA_INIT] <<<<<<<<<<<<<
7154 12:13:30.844206 [Flow] Enable top DCM control >>>>>
7155 12:13:30.847262 [Flow] Enable top DCM control <<<<<
7156 12:13:30.851009 Enable DLL master slave shuffle
7157 12:13:30.854173 ==============================================================
7158 12:13:30.857262 Gating Mode config
7159 12:13:30.863971 ==============================================================
7160 12:13:30.864551 Config description:
7161 12:13:30.874052 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7162 12:13:30.880458 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7163 12:13:30.887378 SELPH_MODE 0: By rank 1: By Phase
7164 12:13:30.890318 ==============================================================
7165 12:13:30.893640 GAT_TRACK_EN = 1
7166 12:13:30.897588 RX_GATING_MODE = 2
7167 12:13:30.900509 RX_GATING_TRACK_MODE = 2
7168 12:13:30.903841 SELPH_MODE = 1
7169 12:13:30.907007 PICG_EARLY_EN = 1
7170 12:13:30.910575 VALID_LAT_VALUE = 1
7171 12:13:30.913498 ==============================================================
7172 12:13:30.916810 Enter into Gating configuration >>>>
7173 12:13:30.920624 Exit from Gating configuration <<<<
7174 12:13:30.923558 Enter into DVFS_PRE_config >>>>>
7175 12:13:30.937160 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7176 12:13:30.940101 Exit from DVFS_PRE_config <<<<<
7177 12:13:30.943561 Enter into PICG configuration >>>>
7178 12:13:30.944145 Exit from PICG configuration <<<<
7179 12:13:30.946826 [RX_INPUT] configuration >>>>>
7180 12:13:30.950238 [RX_INPUT] configuration <<<<<
7181 12:13:30.956982 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7182 12:13:30.960428 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7183 12:13:30.966551 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7184 12:13:30.973592 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7185 12:13:30.979856 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7186 12:13:30.986752 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7187 12:13:30.989719 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7188 12:13:30.993579 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7189 12:13:31.000087 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7190 12:13:31.003690 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7191 12:13:31.006595 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7192 12:13:31.010094 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7193 12:13:31.013013 ===================================
7194 12:13:31.016467 LPDDR4 DRAM CONFIGURATION
7195 12:13:31.019892 ===================================
7196 12:13:31.022747 EX_ROW_EN[0] = 0x0
7197 12:13:31.023222 EX_ROW_EN[1] = 0x0
7198 12:13:31.026238 LP4Y_EN = 0x0
7199 12:13:31.026705 WORK_FSP = 0x1
7200 12:13:31.030120 WL = 0x5
7201 12:13:31.030591 RL = 0x5
7202 12:13:31.032783 BL = 0x2
7203 12:13:31.033253 RPST = 0x0
7204 12:13:31.036351 RD_PRE = 0x0
7205 12:13:31.036819 WR_PRE = 0x1
7206 12:13:31.039850 WR_PST = 0x1
7207 12:13:31.040322 DBI_WR = 0x0
7208 12:13:31.042993 DBI_RD = 0x0
7209 12:13:31.043465 OTF = 0x1
7210 12:13:31.046356 ===================================
7211 12:13:31.052923 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7212 12:13:31.056080 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7213 12:13:31.059367 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7214 12:13:31.062483 ===================================
7215 12:13:31.066410 LPDDR4 DRAM CONFIGURATION
7216 12:13:31.069753 ===================================
7217 12:13:31.072758 EX_ROW_EN[0] = 0x10
7218 12:13:31.073184 EX_ROW_EN[1] = 0x0
7219 12:13:31.076006 LP4Y_EN = 0x0
7220 12:13:31.076433 WORK_FSP = 0x1
7221 12:13:31.079262 WL = 0x5
7222 12:13:31.079695 RL = 0x5
7223 12:13:31.082620 BL = 0x2
7224 12:13:31.083045 RPST = 0x0
7225 12:13:31.085726 RD_PRE = 0x0
7226 12:13:31.086188 WR_PRE = 0x1
7227 12:13:31.089032 WR_PST = 0x1
7228 12:13:31.089456 DBI_WR = 0x0
7229 12:13:31.092544 DBI_RD = 0x0
7230 12:13:31.092966 OTF = 0x1
7231 12:13:31.096517 ===================================
7232 12:13:31.102735 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7233 12:13:31.103273 ==
7234 12:13:31.106148 Dram Type= 6, Freq= 0, CH_0, rank 0
7235 12:13:31.112696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7236 12:13:31.113236 ==
7237 12:13:31.113577 [Duty_Offset_Calibration]
7238 12:13:31.116385 B0:2 B1:0 CA:1
7239 12:13:31.116933
7240 12:13:31.118642 [DutyScan_Calibration_Flow] k_type=0
7241 12:13:31.127699
7242 12:13:31.128226 ==CLK 0==
7243 12:13:31.131334 Final CLK duty delay cell = -4
7244 12:13:31.134595 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7245 12:13:31.137634 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7246 12:13:31.140731 [-4] AVG Duty = 4906%(X100)
7247 12:13:31.141203
7248 12:13:31.144425 CH0 CLK Duty spec in!! Max-Min= 187%
7249 12:13:31.147629 [DutyScan_Calibration_Flow] ====Done====
7250 12:13:31.148103
7251 12:13:31.150478 [DutyScan_Calibration_Flow] k_type=1
7252 12:13:31.166906
7253 12:13:31.167477 ==DQS 0 ==
7254 12:13:31.170428 Final DQS duty delay cell = 0
7255 12:13:31.173565 [0] MAX Duty = 5218%(X100), DQS PI = 32
7256 12:13:31.177228 [0] MIN Duty = 4969%(X100), DQS PI = 0
7257 12:13:31.180226 [0] AVG Duty = 5093%(X100)
7258 12:13:31.180725
7259 12:13:31.181104 ==DQS 1 ==
7260 12:13:31.183552 Final DQS duty delay cell = -4
7261 12:13:31.187087 [-4] MAX Duty = 5125%(X100), DQS PI = 30
7262 12:13:31.190312 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7263 12:13:31.193384 [-4] AVG Duty = 5000%(X100)
7264 12:13:31.193857
7265 12:13:31.197175 CH0 DQS 0 Duty spec in!! Max-Min= 249%
7266 12:13:31.197810
7267 12:13:31.200326 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7268 12:13:31.204224 [DutyScan_Calibration_Flow] ====Done====
7269 12:13:31.204701
7270 12:13:31.206728 [DutyScan_Calibration_Flow] k_type=3
7271 12:13:31.224333
7272 12:13:31.224900 ==DQM 0 ==
7273 12:13:31.228027 Final DQM duty delay cell = 0
7274 12:13:31.231407 [0] MAX Duty = 5093%(X100), DQS PI = 26
7275 12:13:31.234656 [0] MIN Duty = 4813%(X100), DQS PI = 50
7276 12:13:31.238069 [0] AVG Duty = 4953%(X100)
7277 12:13:31.238636
7278 12:13:31.239013 ==DQM 1 ==
7279 12:13:31.241165 Final DQM duty delay cell = 0
7280 12:13:31.244555 [0] MAX Duty = 5249%(X100), DQS PI = 30
7281 12:13:31.247559 [0] MIN Duty = 5000%(X100), DQS PI = 20
7282 12:13:31.250790 [0] AVG Duty = 5124%(X100)
7283 12:13:31.251360
7284 12:13:31.254511 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7285 12:13:31.255082
7286 12:13:31.257260 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7287 12:13:31.260717 [DutyScan_Calibration_Flow] ====Done====
7288 12:13:31.261286
7289 12:13:31.263854 [DutyScan_Calibration_Flow] k_type=2
7290 12:13:31.281572
7291 12:13:31.282180 ==DQ 0 ==
7292 12:13:31.285212 Final DQ duty delay cell = 0
7293 12:13:31.288563 [0] MAX Duty = 5156%(X100), DQS PI = 38
7294 12:13:31.292000 [0] MIN Duty = 5000%(X100), DQS PI = 0
7295 12:13:31.292582 [0] AVG Duty = 5078%(X100)
7296 12:13:31.293066
7297 12:13:31.294856 ==DQ 1 ==
7298 12:13:31.298432 Final DQ duty delay cell = 0
7299 12:13:31.301915 [0] MAX Duty = 4969%(X100), DQS PI = 44
7300 12:13:31.305214 [0] MIN Duty = 4875%(X100), DQS PI = 10
7301 12:13:31.305769 [0] AVG Duty = 4922%(X100)
7302 12:13:31.306302
7303 12:13:31.308422 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7304 12:13:31.308965
7305 12:13:31.311543 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7306 12:13:31.318287 [DutyScan_Calibration_Flow] ====Done====
7307 12:13:31.318785 ==
7308 12:13:31.321601 Dram Type= 6, Freq= 0, CH_1, rank 0
7309 12:13:31.324845 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7310 12:13:31.325239 ==
7311 12:13:31.328270 [Duty_Offset_Calibration]
7312 12:13:31.328582 B0:0 B1:-1 CA:2
7313 12:13:31.328766
7314 12:13:31.331473 [DutyScan_Calibration_Flow] k_type=0
7315 12:13:31.341802
7316 12:13:31.342128 ==CLK 0==
7317 12:13:31.345020 Final CLK duty delay cell = 0
7318 12:13:31.348391 [0] MAX Duty = 5156%(X100), DQS PI = 10
7319 12:13:31.351772 [0] MIN Duty = 4906%(X100), DQS PI = 46
7320 12:13:31.352085 [0] AVG Duty = 5031%(X100)
7321 12:13:31.354974
7322 12:13:31.358329 CH1 CLK Duty spec in!! Max-Min= 250%
7323 12:13:31.361524 [DutyScan_Calibration_Flow] ====Done====
7324 12:13:31.361890
7325 12:13:31.364988 [DutyScan_Calibration_Flow] k_type=1
7326 12:13:31.381387
7327 12:13:31.382301 ==DQS 0 ==
7328 12:13:31.384986 Final DQS duty delay cell = 0
7329 12:13:31.388167 [0] MAX Duty = 5093%(X100), DQS PI = 26
7330 12:13:31.391416 [0] MIN Duty = 4969%(X100), DQS PI = 0
7331 12:13:31.394528 [0] AVG Duty = 5031%(X100)
7332 12:13:31.394983
7333 12:13:31.395341 ==DQS 1 ==
7334 12:13:31.398591 Final DQS duty delay cell = 0
7335 12:13:31.401356 [0] MAX Duty = 5187%(X100), DQS PI = 0
7336 12:13:31.404907 [0] MIN Duty = 4844%(X100), DQS PI = 34
7337 12:13:31.407944 [0] AVG Duty = 5015%(X100)
7338 12:13:31.408401
7339 12:13:31.411401 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7340 12:13:31.411957
7341 12:13:31.414612 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7342 12:13:31.418302 [DutyScan_Calibration_Flow] ====Done====
7343 12:13:31.418860
7344 12:13:31.421150 [DutyScan_Calibration_Flow] k_type=3
7345 12:13:31.439946
7346 12:13:31.440496 ==DQM 0 ==
7347 12:13:31.442388 Final DQM duty delay cell = 4
7348 12:13:31.445721 [4] MAX Duty = 5125%(X100), DQS PI = 6
7349 12:13:31.449354 [4] MIN Duty = 4969%(X100), DQS PI = 48
7350 12:13:31.452491 [4] AVG Duty = 5047%(X100)
7351 12:13:31.453047
7352 12:13:31.453403 ==DQM 1 ==
7353 12:13:31.455677 Final DQM duty delay cell = 0
7354 12:13:31.459054 [0] MAX Duty = 5281%(X100), DQS PI = 58
7355 12:13:31.462406 [0] MIN Duty = 4844%(X100), DQS PI = 34
7356 12:13:31.465631 [0] AVG Duty = 5062%(X100)
7357 12:13:31.466251
7358 12:13:31.468807 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7359 12:13:31.469259
7360 12:13:31.472020 CH1 DQM 1 Duty spec in!! Max-Min= 437%
7361 12:13:31.475641 [DutyScan_Calibration_Flow] ====Done====
7362 12:13:31.476093
7363 12:13:31.478589 [DutyScan_Calibration_Flow] k_type=2
7364 12:13:31.496269
7365 12:13:31.496824 ==DQ 0 ==
7366 12:13:31.499335 Final DQ duty delay cell = 0
7367 12:13:31.502725 [0] MAX Duty = 5062%(X100), DQS PI = 16
7368 12:13:31.506117 [0] MIN Duty = 4969%(X100), DQS PI = 46
7369 12:13:31.506666 [0] AVG Duty = 5015%(X100)
7370 12:13:31.509206
7371 12:13:31.509766 ==DQ 1 ==
7372 12:13:31.512870 Final DQ duty delay cell = 0
7373 12:13:31.515981 [0] MAX Duty = 5062%(X100), DQS PI = 2
7374 12:13:31.519122 [0] MIN Duty = 4813%(X100), DQS PI = 34
7375 12:13:31.519578 [0] AVG Duty = 4937%(X100)
7376 12:13:31.519936
7377 12:13:31.522420 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7378 12:13:31.526305
7379 12:13:31.529003 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7380 12:13:31.532354 [DutyScan_Calibration_Flow] ====Done====
7381 12:13:31.535536 nWR fixed to 30
7382 12:13:31.535997 [ModeRegInit_LP4] CH0 RK0
7383 12:13:31.539022 [ModeRegInit_LP4] CH0 RK1
7384 12:13:31.542271 [ModeRegInit_LP4] CH1 RK0
7385 12:13:31.542734 [ModeRegInit_LP4] CH1 RK1
7386 12:13:31.546006 match AC timing 5
7387 12:13:31.549015 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7388 12:13:31.552615 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7389 12:13:31.559423 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7390 12:13:31.562746 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7391 12:13:31.569250 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7392 12:13:31.569810 [MiockJmeterHQA]
7393 12:13:31.570229
7394 12:13:31.572221 [DramcMiockJmeter] u1RxGatingPI = 0
7395 12:13:31.575727 0 : 4258, 4031
7396 12:13:31.576245 4 : 4368, 4140
7397 12:13:31.576620 8 : 4253, 4027
7398 12:13:31.578870 12 : 4252, 4027
7399 12:13:31.579332 16 : 4253, 4027
7400 12:13:31.581887 20 : 4363, 4137
7401 12:13:31.582391 24 : 4363, 4138
7402 12:13:31.585643 28 : 4363, 4138
7403 12:13:31.586256 32 : 4255, 4029
7404 12:13:31.588745 36 : 4254, 4029
7405 12:13:31.589223 40 : 4363, 4137
7406 12:13:31.589600 44 : 4252, 4027
7407 12:13:31.591794 48 : 4365, 4140
7408 12:13:31.592271 52 : 4257, 4029
7409 12:13:31.595256 56 : 4253, 4026
7410 12:13:31.595734 60 : 4252, 4027
7411 12:13:31.598638 64 : 4252, 4030
7412 12:13:31.599070 68 : 4361, 4137
7413 12:13:31.602093 72 : 4250, 4027
7414 12:13:31.602526 76 : 4360, 4137
7415 12:13:31.602868 80 : 4363, 4140
7416 12:13:31.605575 84 : 4252, 4029
7417 12:13:31.606157 88 : 4252, 3643
7418 12:13:31.608669 92 : 4363, 0
7419 12:13:31.609212 96 : 4363, 0
7420 12:13:31.609577 100 : 4361, 0
7421 12:13:31.611900 104 : 4250, 0
7422 12:13:31.612379 108 : 4366, 0
7423 12:13:31.615399 112 : 4361, 0
7424 12:13:31.615985 116 : 4250, 0
7425 12:13:31.616369 120 : 4253, 0
7426 12:13:31.618306 124 : 4363, 0
7427 12:13:31.618785 128 : 4252, 0
7428 12:13:31.621540 132 : 4253, 0
7429 12:13:31.622046 136 : 4250, 0
7430 12:13:31.622479 140 : 4361, 0
7431 12:13:31.624992 144 : 4250, 0
7432 12:13:31.625429 148 : 4250, 0
7433 12:13:31.628399 152 : 4250, 0
7434 12:13:31.628942 156 : 4255, 0
7435 12:13:31.629294 160 : 4360, 0
7436 12:13:31.631927 164 : 4250, 0
7437 12:13:31.632366 168 : 4250, 0
7438 12:13:31.632718 172 : 4250, 0
7439 12:13:31.635055 176 : 4361, 0
7440 12:13:31.635494 180 : 4250, 0
7441 12:13:31.638383 184 : 4253, 0
7442 12:13:31.638818 188 : 4250, 0
7443 12:13:31.639162 192 : 4361, 0
7444 12:13:31.641617 196 : 4250, 0
7445 12:13:31.642120 200 : 4253, 9
7446 12:13:31.644980 204 : 4250, 2472
7447 12:13:31.645518 208 : 4250, 4027
7448 12:13:31.648523 212 : 4250, 4027
7449 12:13:31.648959 216 : 4255, 4031
7450 12:13:31.651871 220 : 4250, 4027
7451 12:13:31.652406 224 : 4361, 4137
7452 12:13:31.652757 228 : 4250, 4027
7453 12:13:31.655242 232 : 4250, 4027
7454 12:13:31.655773 236 : 4250, 4026
7455 12:13:31.658358 240 : 4363, 4140
7456 12:13:31.658798 244 : 4361, 4137
7457 12:13:31.662045 248 : 4250, 4027
7458 12:13:31.662582 252 : 4250, 4027
7459 12:13:31.665385 256 : 4250, 4026
7460 12:13:31.666006 260 : 4250, 4026
7461 12:13:31.668491 264 : 4250, 4026
7462 12:13:31.669074 268 : 4252, 4030
7463 12:13:31.671423 272 : 4250, 4026
7464 12:13:31.671903 276 : 4363, 4140
7465 12:13:31.675172 280 : 4250, 4027
7466 12:13:31.675768 284 : 4250, 4027
7467 12:13:31.676157 288 : 4250, 4026
7468 12:13:31.678540 292 : 4363, 4140
7469 12:13:31.679021 296 : 4361, 4137
7470 12:13:31.681455 300 : 4250, 4027
7471 12:13:31.681935 304 : 4363, 4140
7472 12:13:31.684893 308 : 4252, 4029
7473 12:13:31.685374 312 : 4250, 3895
7474 12:13:31.688512 316 : 4250, 2283
7475 12:13:31.689088 320 : 4252, 5
7476 12:13:31.689504
7477 12:13:31.691713 MIOCK jitter meter ch=0
7478 12:13:31.692291
7479 12:13:31.694929 1T = (320-92) = 228 dly cells
7480 12:13:31.698128 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7481 12:13:31.698607 ==
7482 12:13:31.701510 Dram Type= 6, Freq= 0, CH_0, rank 0
7483 12:13:31.708286 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7484 12:13:31.708860 ==
7485 12:13:31.711554 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7486 12:13:31.717992 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7487 12:13:31.721645 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7488 12:13:31.728210 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7489 12:13:31.736267 [CA 0] Center 42 (12~72) winsize 61
7490 12:13:31.739336 [CA 1] Center 42 (12~72) winsize 61
7491 12:13:31.742337 [CA 2] Center 37 (7~67) winsize 61
7492 12:13:31.745835 [CA 3] Center 37 (7~67) winsize 61
7493 12:13:31.749154 [CA 4] Center 36 (6~66) winsize 61
7494 12:13:31.752444 [CA 5] Center 35 (5~65) winsize 61
7495 12:13:31.753018
7496 12:13:31.755872 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7497 12:13:31.756439
7498 12:13:31.759068 [CATrainingPosCal] consider 1 rank data
7499 12:13:31.762441 u2DelayCellTimex100 = 285/100 ps
7500 12:13:31.768957 CA0 delay=42 (12~72),Diff = 7 PI (23 cell)
7501 12:13:31.772454 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7502 12:13:31.775441 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7503 12:13:31.779368 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7504 12:13:31.782547 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7505 12:13:31.785428 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7506 12:13:31.785902
7507 12:13:31.788484 CA PerBit enable=1, Macro0, CA PI delay=35
7508 12:13:31.788954
7509 12:13:31.792385 [CBTSetCACLKResult] CA Dly = 35
7510 12:13:31.795587 CS Dly: 9 (0~40)
7511 12:13:31.799084 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7512 12:13:31.802019 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7513 12:13:31.802497 ==
7514 12:13:31.805924 Dram Type= 6, Freq= 0, CH_0, rank 1
7515 12:13:31.808453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7516 12:13:31.812282 ==
7517 12:13:31.815181 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7518 12:13:31.818864 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7519 12:13:31.825286 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7520 12:13:31.832008 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7521 12:13:31.839165 [CA 0] Center 43 (13~74) winsize 62
7522 12:13:31.842523 [CA 1] Center 43 (13~73) winsize 61
7523 12:13:31.845724 [CA 2] Center 38 (9~68) winsize 60
7524 12:13:31.849595 [CA 3] Center 38 (9~68) winsize 60
7525 12:13:31.852831 [CA 4] Center 37 (7~67) winsize 61
7526 12:13:31.855757 [CA 5] Center 36 (6~66) winsize 61
7527 12:13:31.856224
7528 12:13:31.858972 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7529 12:13:31.859546
7530 12:13:31.862559 [CATrainingPosCal] consider 2 rank data
7531 12:13:31.866337 u2DelayCellTimex100 = 285/100 ps
7532 12:13:31.869059 CA0 delay=42 (13~72),Diff = 7 PI (23 cell)
7533 12:13:31.875786 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7534 12:13:31.879469 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7535 12:13:31.882690 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7536 12:13:31.885567 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7537 12:13:31.889162 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7538 12:13:31.889628
7539 12:13:31.892485 CA PerBit enable=1, Macro0, CA PI delay=35
7540 12:13:31.892952
7541 12:13:31.895771 [CBTSetCACLKResult] CA Dly = 35
7542 12:13:31.898792 CS Dly: 10 (0~43)
7543 12:13:31.902322 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7544 12:13:31.906089 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7545 12:13:31.906657
7546 12:13:31.909127 ----->DramcWriteLeveling(PI) begin...
7547 12:13:31.909601 ==
7548 12:13:31.912330 Dram Type= 6, Freq= 0, CH_0, rank 0
7549 12:13:31.915995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7550 12:13:31.919101 ==
7551 12:13:31.919570 Write leveling (Byte 0): 34 => 34
7552 12:13:31.922856 Write leveling (Byte 1): 33 => 33
7553 12:13:31.926088 DramcWriteLeveling(PI) end<-----
7554 12:13:31.926663
7555 12:13:31.927035 ==
7556 12:13:31.928795 Dram Type= 6, Freq= 0, CH_0, rank 0
7557 12:13:31.935550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7558 12:13:31.936123 ==
7559 12:13:31.938987 [Gating] SW mode calibration
7560 12:13:31.945558 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7561 12:13:31.948665 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7562 12:13:31.955794 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7563 12:13:31.958808 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7564 12:13:31.962571 1 4 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7565 12:13:31.968520 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7566 12:13:31.972091 1 4 16 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
7567 12:13:31.975563 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
7568 12:13:31.982088 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7569 12:13:31.985408 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7570 12:13:31.988997 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7571 12:13:31.995253 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7572 12:13:31.998352 1 5 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
7573 12:13:32.002103 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7574 12:13:32.005429 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7575 12:13:32.012424 1 5 20 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
7576 12:13:32.015411 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7577 12:13:32.018545 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7578 12:13:32.025583 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 12:13:32.028428 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7580 12:13:32.031757 1 6 8 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
7581 12:13:32.038624 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7582 12:13:32.041681 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7583 12:13:32.044930 1 6 20 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7584 12:13:32.051692 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 12:13:32.055089 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 12:13:32.058408 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 12:13:32.064978 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 12:13:32.068107 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7589 12:13:32.071560 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7590 12:13:32.078530 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7591 12:13:32.081771 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7592 12:13:32.085155 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7593 12:13:32.091839 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 12:13:32.095091 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 12:13:32.098156 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 12:13:32.104963 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 12:13:32.108601 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 12:13:32.111936 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 12:13:32.118320 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 12:13:32.121313 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 12:13:32.125284 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 12:13:32.128519 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 12:13:32.134877 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 12:13:32.138066 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7605 12:13:32.141474 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7606 12:13:32.148118 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7607 12:13:32.151617 Total UI for P1: 0, mck2ui 16
7608 12:13:32.155019 best dqsien dly found for B0: ( 1, 9, 10)
7609 12:13:32.158031 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7610 12:13:32.161530 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 12:13:32.164515 Total UI for P1: 0, mck2ui 16
7612 12:13:32.168234 best dqsien dly found for B1: ( 1, 9, 18)
7613 12:13:32.171275 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7614 12:13:32.174683 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7615 12:13:32.177992
7616 12:13:32.181537 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7617 12:13:32.184808 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7618 12:13:32.187773 [Gating] SW calibration Done
7619 12:13:32.188253 ==
7620 12:13:32.191523 Dram Type= 6, Freq= 0, CH_0, rank 0
7621 12:13:32.194418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7622 12:13:32.194898 ==
7623 12:13:32.197881 RX Vref Scan: 0
7624 12:13:32.198497
7625 12:13:32.198873 RX Vref 0 -> 0, step: 1
7626 12:13:32.199227
7627 12:13:32.201083 RX Delay 0 -> 252, step: 8
7628 12:13:32.204389 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7629 12:13:32.207913 iDelay=200, Bit 1, Center 143 (96 ~ 191) 96
7630 12:13:32.214755 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7631 12:13:32.218077 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7632 12:13:32.221530 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7633 12:13:32.224568 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7634 12:13:32.228379 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7635 12:13:32.231127 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7636 12:13:32.238136 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7637 12:13:32.240855 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7638 12:13:32.244536 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7639 12:13:32.247560 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7640 12:13:32.254095 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7641 12:13:32.257766 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7642 12:13:32.261148 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7643 12:13:32.264032 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7644 12:13:32.264505 ==
7645 12:13:32.267511 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 12:13:32.274071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 12:13:32.274648 ==
7648 12:13:32.275025 DQS Delay:
7649 12:13:32.275369 DQS0 = 0, DQS1 = 0
7650 12:13:32.277587 DQM Delay:
7651 12:13:32.278192 DQM0 = 139, DQM1 = 126
7652 12:13:32.280866 DQ Delay:
7653 12:13:32.283975 DQ0 =139, DQ1 =143, DQ2 =135, DQ3 =135
7654 12:13:32.287213 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7655 12:13:32.290535 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7656 12:13:32.293889 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =135
7657 12:13:32.294495
7658 12:13:32.294870
7659 12:13:32.295219 ==
7660 12:13:32.297316 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 12:13:32.300671 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 12:13:32.301246 ==
7663 12:13:32.304218
7664 12:13:32.304693
7665 12:13:32.305064 TX Vref Scan disable
7666 12:13:32.307666 == TX Byte 0 ==
7667 12:13:32.310190 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7668 12:13:32.314196 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7669 12:13:32.317298 == TX Byte 1 ==
7670 12:13:32.320444 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7671 12:13:32.323686 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7672 12:13:32.324160 ==
7673 12:13:32.327400 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 12:13:32.333830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 12:13:32.334449 ==
7676 12:13:32.345326
7677 12:13:32.348744 TX Vref early break, caculate TX vref
7678 12:13:32.351916 TX Vref=16, minBit 4, minWin=23, winSum=381
7679 12:13:32.355537 TX Vref=18, minBit 6, minWin=23, winSum=392
7680 12:13:32.358607 TX Vref=20, minBit 2, minWin=24, winSum=397
7681 12:13:32.361998 TX Vref=22, minBit 12, minWin=24, winSum=407
7682 12:13:32.365337 TX Vref=24, minBit 0, minWin=25, winSum=415
7683 12:13:32.371692 TX Vref=26, minBit 5, minWin=25, winSum=426
7684 12:13:32.375544 TX Vref=28, minBit 0, minWin=26, winSum=430
7685 12:13:32.378550 TX Vref=30, minBit 0, minWin=26, winSum=421
7686 12:13:32.382258 TX Vref=32, minBit 1, minWin=25, winSum=416
7687 12:13:32.385093 TX Vref=34, minBit 1, minWin=24, winSum=403
7688 12:13:32.391676 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
7689 12:13:32.392242
7690 12:13:32.394856 Final TX Range 0 Vref 28
7691 12:13:32.395329
7692 12:13:32.395699 ==
7693 12:13:32.398054 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 12:13:32.401757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 12:13:32.402401 ==
7696 12:13:32.402784
7697 12:13:32.403131
7698 12:13:32.404723 TX Vref Scan disable
7699 12:13:32.411643 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7700 12:13:32.412115 == TX Byte 0 ==
7701 12:13:32.414588 u2DelayCellOfst[0]=13 cells (4 PI)
7702 12:13:32.418045 u2DelayCellOfst[1]=17 cells (5 PI)
7703 12:13:32.421384 u2DelayCellOfst[2]=13 cells (4 PI)
7704 12:13:32.424625 u2DelayCellOfst[3]=13 cells (4 PI)
7705 12:13:32.428674 u2DelayCellOfst[4]=10 cells (3 PI)
7706 12:13:32.431686 u2DelayCellOfst[5]=0 cells (0 PI)
7707 12:13:32.434629 u2DelayCellOfst[6]=17 cells (5 PI)
7708 12:13:32.438100 u2DelayCellOfst[7]=17 cells (5 PI)
7709 12:13:32.441318 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7710 12:13:32.445278 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7711 12:13:32.447910 == TX Byte 1 ==
7712 12:13:32.451623 u2DelayCellOfst[8]=0 cells (0 PI)
7713 12:13:32.452194 u2DelayCellOfst[9]=0 cells (0 PI)
7714 12:13:32.455445 u2DelayCellOfst[10]=6 cells (2 PI)
7715 12:13:32.458138 u2DelayCellOfst[11]=3 cells (1 PI)
7716 12:13:32.461486 u2DelayCellOfst[12]=13 cells (4 PI)
7717 12:13:32.464766 u2DelayCellOfst[13]=13 cells (4 PI)
7718 12:13:32.467806 u2DelayCellOfst[14]=17 cells (5 PI)
7719 12:13:32.471122 u2DelayCellOfst[15]=10 cells (3 PI)
7720 12:13:32.474428 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7721 12:13:32.481096 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7722 12:13:32.481668 DramC Write-DBI on
7723 12:13:32.482092 ==
7724 12:13:32.484205 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 12:13:32.491176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 12:13:32.491751 ==
7727 12:13:32.492128
7728 12:13:32.492476
7729 12:13:32.492807 TX Vref Scan disable
7730 12:13:32.494639 == TX Byte 0 ==
7731 12:13:32.498065 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7732 12:13:32.501486 == TX Byte 1 ==
7733 12:13:32.505036 Update DQM dly =730 (2 ,6, 26) DQM OEN =(3 ,3)
7734 12:13:32.508019 DramC Write-DBI off
7735 12:13:32.508595
7736 12:13:32.508973 [DATLAT]
7737 12:13:32.509318 Freq=1600, CH0 RK0
7738 12:13:32.509652
7739 12:13:32.511240 DATLAT Default: 0xf
7740 12:13:32.511713 0, 0xFFFF, sum = 0
7741 12:13:32.514746 1, 0xFFFF, sum = 0
7742 12:13:32.518044 2, 0xFFFF, sum = 0
7743 12:13:32.518519 3, 0xFFFF, sum = 0
7744 12:13:32.521419 4, 0xFFFF, sum = 0
7745 12:13:32.521898 5, 0xFFFF, sum = 0
7746 12:13:32.524767 6, 0xFFFF, sum = 0
7747 12:13:32.525346 7, 0xFFFF, sum = 0
7748 12:13:32.527895 8, 0xFFFF, sum = 0
7749 12:13:32.528473 9, 0xFFFF, sum = 0
7750 12:13:32.531085 10, 0xFFFF, sum = 0
7751 12:13:32.531566 11, 0xFFFF, sum = 0
7752 12:13:32.534625 12, 0xFFFF, sum = 0
7753 12:13:32.535205 13, 0xFFFF, sum = 0
7754 12:13:32.538077 14, 0x0, sum = 1
7755 12:13:32.538653 15, 0x0, sum = 2
7756 12:13:32.541296 16, 0x0, sum = 3
7757 12:13:32.542016 17, 0x0, sum = 4
7758 12:13:32.544336 best_step = 15
7759 12:13:32.544804
7760 12:13:32.545173 ==
7761 12:13:32.547633 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 12:13:32.551272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 12:13:32.551848 ==
7764 12:13:32.554332 RX Vref Scan: 1
7765 12:13:32.554802
7766 12:13:32.555171 Set Vref Range= 24 -> 127
7767 12:13:32.555517
7768 12:13:32.557501 RX Vref 24 -> 127, step: 1
7769 12:13:32.557997
7770 12:13:32.560975 RX Delay 19 -> 252, step: 4
7771 12:13:32.561463
7772 12:13:32.564959 Set Vref, RX VrefLevel [Byte0]: 24
7773 12:13:32.567907 [Byte1]: 24
7774 12:13:32.568469
7775 12:13:32.571188 Set Vref, RX VrefLevel [Byte0]: 25
7776 12:13:32.574184 [Byte1]: 25
7777 12:13:32.574656
7778 12:13:32.578127 Set Vref, RX VrefLevel [Byte0]: 26
7779 12:13:32.581109 [Byte1]: 26
7780 12:13:32.585194
7781 12:13:32.585755 Set Vref, RX VrefLevel [Byte0]: 27
7782 12:13:32.588664 [Byte1]: 27
7783 12:13:32.593056
7784 12:13:32.593627 Set Vref, RX VrefLevel [Byte0]: 28
7785 12:13:32.595924 [Byte1]: 28
7786 12:13:32.600358
7787 12:13:32.600933 Set Vref, RX VrefLevel [Byte0]: 29
7788 12:13:32.603982 [Byte1]: 29
7789 12:13:32.607911
7790 12:13:32.608482 Set Vref, RX VrefLevel [Byte0]: 30
7791 12:13:32.611108 [Byte1]: 30
7792 12:13:32.615417
7793 12:13:32.615979 Set Vref, RX VrefLevel [Byte0]: 31
7794 12:13:32.618718 [Byte1]: 31
7795 12:13:32.622724
7796 12:13:32.623196 Set Vref, RX VrefLevel [Byte0]: 32
7797 12:13:32.626233 [Byte1]: 32
7798 12:13:32.630871
7799 12:13:32.631436 Set Vref, RX VrefLevel [Byte0]: 33
7800 12:13:32.633795 [Byte1]: 33
7801 12:13:32.638063
7802 12:13:32.638628 Set Vref, RX VrefLevel [Byte0]: 34
7803 12:13:32.641427 [Byte1]: 34
7804 12:13:32.645536
7805 12:13:32.646229 Set Vref, RX VrefLevel [Byte0]: 35
7806 12:13:32.649097 [Byte1]: 35
7807 12:13:32.653725
7808 12:13:32.654330 Set Vref, RX VrefLevel [Byte0]: 36
7809 12:13:32.656437 [Byte1]: 36
7810 12:13:32.660840
7811 12:13:32.661310 Set Vref, RX VrefLevel [Byte0]: 37
7812 12:13:32.664085 [Byte1]: 37
7813 12:13:32.668893
7814 12:13:32.669460 Set Vref, RX VrefLevel [Byte0]: 38
7815 12:13:32.671471 [Byte1]: 38
7816 12:13:32.676016
7817 12:13:32.676587 Set Vref, RX VrefLevel [Byte0]: 39
7818 12:13:32.679047 [Byte1]: 39
7819 12:13:32.683854
7820 12:13:32.684419 Set Vref, RX VrefLevel [Byte0]: 40
7821 12:13:32.686495 [Byte1]: 40
7822 12:13:32.691339
7823 12:13:32.691925 Set Vref, RX VrefLevel [Byte0]: 41
7824 12:13:32.694220 [Byte1]: 41
7825 12:13:32.698565
7826 12:13:32.699035 Set Vref, RX VrefLevel [Byte0]: 42
7827 12:13:32.701794 [Byte1]: 42
7828 12:13:32.706500
7829 12:13:32.707066 Set Vref, RX VrefLevel [Byte0]: 43
7830 12:13:32.709463 [Byte1]: 43
7831 12:13:32.713872
7832 12:13:32.714495 Set Vref, RX VrefLevel [Byte0]: 44
7833 12:13:32.717850 [Byte1]: 44
7834 12:13:32.721150
7835 12:13:32.721621 Set Vref, RX VrefLevel [Byte0]: 45
7836 12:13:32.724855 [Byte1]: 45
7837 12:13:32.729181
7838 12:13:32.729748 Set Vref, RX VrefLevel [Byte0]: 46
7839 12:13:32.732282 [Byte1]: 46
7840 12:13:32.736510
7841 12:13:32.737113 Set Vref, RX VrefLevel [Byte0]: 47
7842 12:13:32.739969 [Byte1]: 47
7843 12:13:32.744311
7844 12:13:32.744906 Set Vref, RX VrefLevel [Byte0]: 48
7845 12:13:32.747462 [Byte1]: 48
7846 12:13:32.751769
7847 12:13:32.752337 Set Vref, RX VrefLevel [Byte0]: 49
7848 12:13:32.755249 [Byte1]: 49
7849 12:13:32.759721
7850 12:13:32.760292 Set Vref, RX VrefLevel [Byte0]: 50
7851 12:13:32.762866 [Byte1]: 50
7852 12:13:32.766854
7853 12:13:32.767434 Set Vref, RX VrefLevel [Byte0]: 51
7854 12:13:32.770447 [Byte1]: 51
7855 12:13:32.774503
7856 12:13:32.775079 Set Vref, RX VrefLevel [Byte0]: 52
7857 12:13:32.777681 [Byte1]: 52
7858 12:13:32.782298
7859 12:13:32.782870 Set Vref, RX VrefLevel [Byte0]: 53
7860 12:13:32.785281 [Byte1]: 53
7861 12:13:32.789605
7862 12:13:32.790114 Set Vref, RX VrefLevel [Byte0]: 54
7863 12:13:32.792980 [Byte1]: 54
7864 12:13:32.797122
7865 12:13:32.797696 Set Vref, RX VrefLevel [Byte0]: 55
7866 12:13:32.800887 [Byte1]: 55
7867 12:13:32.804714
7868 12:13:32.805289 Set Vref, RX VrefLevel [Byte0]: 56
7869 12:13:32.807849 [Byte1]: 56
7870 12:13:32.812356
7871 12:13:32.812945 Set Vref, RX VrefLevel [Byte0]: 57
7872 12:13:32.815465 [Byte1]: 57
7873 12:13:32.820402
7874 12:13:32.820974 Set Vref, RX VrefLevel [Byte0]: 58
7875 12:13:32.823292 [Byte1]: 58
7876 12:13:32.827511
7877 12:13:32.828086 Set Vref, RX VrefLevel [Byte0]: 59
7878 12:13:32.830782 [Byte1]: 59
7879 12:13:32.835281
7880 12:13:32.835857 Set Vref, RX VrefLevel [Byte0]: 60
7881 12:13:32.838141 [Byte1]: 60
7882 12:13:32.842725
7883 12:13:32.843299 Set Vref, RX VrefLevel [Byte0]: 61
7884 12:13:32.845797 [Byte1]: 61
7885 12:13:32.850069
7886 12:13:32.850636 Set Vref, RX VrefLevel [Byte0]: 62
7887 12:13:32.853306 [Byte1]: 62
7888 12:13:32.858062
7889 12:13:32.858626 Set Vref, RX VrefLevel [Byte0]: 63
7890 12:13:32.860985 [Byte1]: 63
7891 12:13:32.865214
7892 12:13:32.865783 Set Vref, RX VrefLevel [Byte0]: 64
7893 12:13:32.868460 [Byte1]: 64
7894 12:13:32.873096
7895 12:13:32.873672 Set Vref, RX VrefLevel [Byte0]: 65
7896 12:13:32.876309 [Byte1]: 65
7897 12:13:32.880657
7898 12:13:32.881234 Set Vref, RX VrefLevel [Byte0]: 66
7899 12:13:32.883805 [Byte1]: 66
7900 12:13:32.888299
7901 12:13:32.888930 Set Vref, RX VrefLevel [Byte0]: 67
7902 12:13:32.891004 [Byte1]: 67
7903 12:13:32.895366
7904 12:13:32.895835 Set Vref, RX VrefLevel [Byte0]: 68
7905 12:13:32.899256 [Byte1]: 68
7906 12:13:32.903305
7907 12:13:32.903878 Set Vref, RX VrefLevel [Byte0]: 69
7908 12:13:32.906500 [Byte1]: 69
7909 12:13:32.910866
7910 12:13:32.911492 Set Vref, RX VrefLevel [Byte0]: 70
7911 12:13:32.913802 [Byte1]: 70
7912 12:13:32.918326
7913 12:13:32.918929 Set Vref, RX VrefLevel [Byte0]: 71
7914 12:13:32.921528 [Byte1]: 71
7915 12:13:32.926117
7916 12:13:32.926702 Set Vref, RX VrefLevel [Byte0]: 72
7917 12:13:32.929507 [Byte1]: 72
7918 12:13:32.933549
7919 12:13:32.934190 Set Vref, RX VrefLevel [Byte0]: 73
7920 12:13:32.936836 [Byte1]: 73
7921 12:13:32.941082
7922 12:13:32.941668 Set Vref, RX VrefLevel [Byte0]: 74
7923 12:13:32.944142 [Byte1]: 74
7924 12:13:32.949505
7925 12:13:32.950098 Set Vref, RX VrefLevel [Byte0]: 75
7926 12:13:32.951719 [Byte1]: 75
7927 12:13:32.956355
7928 12:13:32.956921 Set Vref, RX VrefLevel [Byte0]: 76
7929 12:13:32.959478 [Byte1]: 76
7930 12:13:32.964416
7931 12:13:32.965005 Set Vref, RX VrefLevel [Byte0]: 77
7932 12:13:32.967042 [Byte1]: 77
7933 12:13:32.971225
7934 12:13:32.971788 Set Vref, RX VrefLevel [Byte0]: 78
7935 12:13:32.974623 [Byte1]: 78
7936 12:13:32.979186
7937 12:13:32.979746 Set Vref, RX VrefLevel [Byte0]: 79
7938 12:13:32.982118 [Byte1]: 79
7939 12:13:32.986386
7940 12:13:32.986947 Final RX Vref Byte 0 = 62 to rank0
7941 12:13:32.989662 Final RX Vref Byte 1 = 61 to rank0
7942 12:13:32.992857 Final RX Vref Byte 0 = 62 to rank1
7943 12:13:32.996074 Final RX Vref Byte 1 = 61 to rank1==
7944 12:13:32.999519 Dram Type= 6, Freq= 0, CH_0, rank 0
7945 12:13:33.006042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7946 12:13:33.006525 ==
7947 12:13:33.006904 DQS Delay:
7948 12:13:33.009498 DQS0 = 0, DQS1 = 0
7949 12:13:33.010006 DQM Delay:
7950 12:13:33.010389 DQM0 = 136, DQM1 = 124
7951 12:13:33.012907 DQ Delay:
7952 12:13:33.016207 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =134
7953 12:13:33.019462 DQ4 =138, DQ5 =126, DQ6 =144, DQ7 =142
7954 12:13:33.022890 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
7955 12:13:33.026248 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =132
7956 12:13:33.026818
7957 12:13:33.027195
7958 12:13:33.027539
7959 12:13:33.029404 [DramC_TX_OE_Calibration] TA2
7960 12:13:33.032388 Original DQ_B0 (3 6) =30, OEN = 27
7961 12:13:33.035967 Original DQ_B1 (3 6) =30, OEN = 27
7962 12:13:33.039299 24, 0x0, End_B0=24 End_B1=24
7963 12:13:33.039875 25, 0x0, End_B0=25 End_B1=25
7964 12:13:33.043147 26, 0x0, End_B0=26 End_B1=26
7965 12:13:33.045780 27, 0x0, End_B0=27 End_B1=27
7966 12:13:33.049273 28, 0x0, End_B0=28 End_B1=28
7967 12:13:33.052342 29, 0x0, End_B0=29 End_B1=29
7968 12:13:33.052918 30, 0x0, End_B0=30 End_B1=30
7969 12:13:33.056044 31, 0x4141, End_B0=30 End_B1=30
7970 12:13:33.059036 Byte0 end_step=30 best_step=27
7971 12:13:33.062499 Byte1 end_step=30 best_step=27
7972 12:13:33.065520 Byte0 TX OE(2T, 0.5T) = (3, 3)
7973 12:13:33.069541 Byte1 TX OE(2T, 0.5T) = (3, 3)
7974 12:13:33.070189
7975 12:13:33.070573
7976 12:13:33.075333 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
7977 12:13:33.078622 CH0 RK0: MR19=303, MR18=1D1C
7978 12:13:33.085176 CH0_RK0: MR19=0x303, MR18=0x1D1C, DQSOSC=395, MR23=63, INC=23, DEC=15
7979 12:13:33.085646
7980 12:13:33.088777 ----->DramcWriteLeveling(PI) begin...
7981 12:13:33.089338 ==
7982 12:13:33.092160 Dram Type= 6, Freq= 0, CH_0, rank 1
7983 12:13:33.095330 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7984 12:13:33.095967 ==
7985 12:13:33.098682 Write leveling (Byte 0): 39 => 39
7986 12:13:33.102022 Write leveling (Byte 1): 31 => 31
7987 12:13:33.105681 DramcWriteLeveling(PI) end<-----
7988 12:13:33.106313
7989 12:13:33.106693 ==
7990 12:13:33.108954 Dram Type= 6, Freq= 0, CH_0, rank 1
7991 12:13:33.112105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7992 12:13:33.112579 ==
7993 12:13:33.115230 [Gating] SW mode calibration
7994 12:13:33.121934 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7995 12:13:33.129158 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7996 12:13:33.132564 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 12:13:33.138743 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7998 12:13:33.142095 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7999 12:13:33.145594 1 4 12 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
8000 12:13:33.151947 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8001 12:13:33.155406 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8002 12:13:33.158548 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8003 12:13:33.165356 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8004 12:13:33.168977 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8005 12:13:33.172254 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8006 12:13:33.178578 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8007 12:13:33.181912 1 5 12 | B1->B0 | 3434 2727 | 0 0 | (0 1) (1 0)
8008 12:13:33.184926 1 5 16 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
8009 12:13:33.191552 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 12:13:33.195038 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 12:13:33.198623 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 12:13:33.201784 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 12:13:33.208500 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 12:13:33.211845 1 6 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8015 12:13:33.215129 1 6 12 | B1->B0 | 2e2e 4343 | 0 0 | (0 0) (0 0)
8016 12:13:33.221529 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 12:13:33.224957 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 12:13:33.228277 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 12:13:33.234991 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 12:13:33.238461 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 12:13:33.241535 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8022 12:13:33.248037 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8023 12:13:33.251983 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8024 12:13:33.254604 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8025 12:13:33.261438 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 12:13:33.264479 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 12:13:33.268070 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 12:13:33.274357 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 12:13:33.277906 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 12:13:33.281419 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 12:13:33.287804 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 12:13:33.291200 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 12:13:33.294364 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 12:13:33.301433 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 12:13:33.304656 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 12:13:33.307954 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 12:13:33.314621 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 12:13:33.317833 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 12:13:33.321039 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8040 12:13:33.327673 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 12:13:33.328247 Total UI for P1: 0, mck2ui 16
8042 12:13:33.330942 best dqsien dly found for B0: ( 1, 9, 12)
8043 12:13:33.334532 Total UI for P1: 0, mck2ui 16
8044 12:13:33.337724 best dqsien dly found for B1: ( 1, 9, 12)
8045 12:13:33.344159 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8046 12:13:33.347712 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8047 12:13:33.348284
8048 12:13:33.350770 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8049 12:13:33.353901 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8050 12:13:33.357616 [Gating] SW calibration Done
8051 12:13:33.358222 ==
8052 12:13:33.361037 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 12:13:33.364141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 12:13:33.364618 ==
8055 12:13:33.367273 RX Vref Scan: 0
8056 12:13:33.367742
8057 12:13:33.368112 RX Vref 0 -> 0, step: 1
8058 12:13:33.368459
8059 12:13:33.370876 RX Delay 0 -> 252, step: 8
8060 12:13:33.374083 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8061 12:13:33.380567 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8062 12:13:33.384120 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8063 12:13:33.387279 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8064 12:13:33.390695 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8065 12:13:33.394149 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8066 12:13:33.397613 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8067 12:13:33.404203 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8068 12:13:33.407663 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8069 12:13:33.410516 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8070 12:13:33.414245 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8071 12:13:33.420447 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8072 12:13:33.423907 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8073 12:13:33.427236 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8074 12:13:33.430586 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8075 12:13:33.434699 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8076 12:13:33.437512 ==
8077 12:13:33.438112 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 12:13:33.443815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 12:13:33.444386 ==
8080 12:13:33.444759 DQS Delay:
8081 12:13:33.447531 DQS0 = 0, DQS1 = 0
8082 12:13:33.448097 DQM Delay:
8083 12:13:33.450669 DQM0 = 136, DQM1 = 125
8084 12:13:33.451240 DQ Delay:
8085 12:13:33.454168 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8086 12:13:33.456950 DQ4 =135, DQ5 =127, DQ6 =143, DQ7 =143
8087 12:13:33.460642 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8088 12:13:33.463969 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8089 12:13:33.464553
8090 12:13:33.464932
8091 12:13:33.465275 ==
8092 12:13:33.467107 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 12:13:33.473472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 12:13:33.474059 ==
8095 12:13:33.474437
8096 12:13:33.474784
8097 12:13:33.475115 TX Vref Scan disable
8098 12:13:33.477329 == TX Byte 0 ==
8099 12:13:33.480311 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8100 12:13:33.486908 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8101 12:13:33.487473 == TX Byte 1 ==
8102 12:13:33.490187 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8103 12:13:33.496807 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8104 12:13:33.497281 ==
8105 12:13:33.500402 Dram Type= 6, Freq= 0, CH_0, rank 1
8106 12:13:33.503475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8107 12:13:33.504049 ==
8108 12:13:33.518357
8109 12:13:33.521408 TX Vref early break, caculate TX vref
8110 12:13:33.524325 TX Vref=16, minBit 3, minWin=23, winSum=388
8111 12:13:33.527900 TX Vref=18, minBit 0, minWin=24, winSum=400
8112 12:13:33.531148 TX Vref=20, minBit 8, minWin=24, winSum=405
8113 12:13:33.534417 TX Vref=22, minBit 0, minWin=25, winSum=415
8114 12:13:33.538116 TX Vref=24, minBit 0, minWin=25, winSum=420
8115 12:13:33.545026 TX Vref=26, minBit 0, minWin=25, winSum=426
8116 12:13:33.548033 TX Vref=28, minBit 0, minWin=26, winSum=430
8117 12:13:33.551166 TX Vref=30, minBit 0, minWin=26, winSum=427
8118 12:13:33.554443 TX Vref=32, minBit 13, minWin=25, winSum=419
8119 12:13:33.557535 TX Vref=34, minBit 0, minWin=25, winSum=410
8120 12:13:33.564300 TX Vref=36, minBit 4, minWin=24, winSum=406
8121 12:13:33.567438 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8122 12:13:33.568007
8123 12:13:33.570561 Final TX Range 0 Vref 28
8124 12:13:33.571171
8125 12:13:33.571554 ==
8126 12:13:33.573997 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 12:13:33.577606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 12:13:33.580579 ==
8129 12:13:33.581050
8130 12:13:33.581420
8131 12:13:33.581764 TX Vref Scan disable
8132 12:13:33.587175 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8133 12:13:33.587725 == TX Byte 0 ==
8134 12:13:33.590664 u2DelayCellOfst[0]=13 cells (4 PI)
8135 12:13:33.594233 u2DelayCellOfst[1]=20 cells (6 PI)
8136 12:13:33.597254 u2DelayCellOfst[2]=13 cells (4 PI)
8137 12:13:33.600550 u2DelayCellOfst[3]=13 cells (4 PI)
8138 12:13:33.604128 u2DelayCellOfst[4]=10 cells (3 PI)
8139 12:13:33.607561 u2DelayCellOfst[5]=0 cells (0 PI)
8140 12:13:33.610520 u2DelayCellOfst[6]=20 cells (6 PI)
8141 12:13:33.613863 u2DelayCellOfst[7]=20 cells (6 PI)
8142 12:13:33.617308 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8143 12:13:33.620795 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8144 12:13:33.623794 == TX Byte 1 ==
8145 12:13:33.626876 u2DelayCellOfst[8]=0 cells (0 PI)
8146 12:13:33.630607 u2DelayCellOfst[9]=0 cells (0 PI)
8147 12:13:33.633685 u2DelayCellOfst[10]=10 cells (3 PI)
8148 12:13:33.637141 u2DelayCellOfst[11]=3 cells (1 PI)
8149 12:13:33.640440 u2DelayCellOfst[12]=13 cells (4 PI)
8150 12:13:33.643726 u2DelayCellOfst[13]=13 cells (4 PI)
8151 12:13:33.647022 u2DelayCellOfst[14]=17 cells (5 PI)
8152 12:13:33.647493 u2DelayCellOfst[15]=13 cells (4 PI)
8153 12:13:33.653854 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8154 12:13:33.657588 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8155 12:13:33.660618 DramC Write-DBI on
8156 12:13:33.661182 ==
8157 12:13:33.663580 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 12:13:33.666922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 12:13:33.667489 ==
8160 12:13:33.667861
8161 12:13:33.668203
8162 12:13:33.670005 TX Vref Scan disable
8163 12:13:33.670573 == TX Byte 0 ==
8164 12:13:33.676967 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8165 12:13:33.677537 == TX Byte 1 ==
8166 12:13:33.680061 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
8167 12:13:33.683878 DramC Write-DBI off
8168 12:13:33.684443
8169 12:13:33.684821 [DATLAT]
8170 12:13:33.686793 Freq=1600, CH0 RK1
8171 12:13:33.687267
8172 12:13:33.687633 DATLAT Default: 0xf
8173 12:13:33.689710 0, 0xFFFF, sum = 0
8174 12:13:33.690238 1, 0xFFFF, sum = 0
8175 12:13:33.693544 2, 0xFFFF, sum = 0
8176 12:13:33.696591 3, 0xFFFF, sum = 0
8177 12:13:33.697082 4, 0xFFFF, sum = 0
8178 12:13:33.700139 5, 0xFFFF, sum = 0
8179 12:13:33.700714 6, 0xFFFF, sum = 0
8180 12:13:33.703644 7, 0xFFFF, sum = 0
8181 12:13:33.704220 8, 0xFFFF, sum = 0
8182 12:13:33.706772 9, 0xFFFF, sum = 0
8183 12:13:33.707246 10, 0xFFFF, sum = 0
8184 12:13:33.709643 11, 0xFFFF, sum = 0
8185 12:13:33.710140 12, 0xFFFF, sum = 0
8186 12:13:33.713114 13, 0xFFFF, sum = 0
8187 12:13:33.713585 14, 0x0, sum = 1
8188 12:13:33.716654 15, 0x0, sum = 2
8189 12:13:33.717178 16, 0x0, sum = 3
8190 12:13:33.720504 17, 0x0, sum = 4
8191 12:13:33.721075 best_step = 15
8192 12:13:33.721466
8193 12:13:33.721810 ==
8194 12:13:33.722824 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 12:13:33.729835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 12:13:33.730450 ==
8197 12:13:33.730823 RX Vref Scan: 0
8198 12:13:33.731163
8199 12:13:33.732908 RX Vref 0 -> 0, step: 1
8200 12:13:33.733468
8201 12:13:33.735965 RX Delay 11 -> 252, step: 4
8202 12:13:33.739905 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8203 12:13:33.743052 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8204 12:13:33.746140 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8205 12:13:33.753308 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8206 12:13:33.756437 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8207 12:13:33.759670 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8208 12:13:33.762844 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8209 12:13:33.766075 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8210 12:13:33.772814 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8211 12:13:33.776205 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8212 12:13:33.779370 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8213 12:13:33.782688 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8214 12:13:33.786204 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8215 12:13:33.793369 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8216 12:13:33.796044 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8217 12:13:33.799532 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8218 12:13:33.800002 ==
8219 12:13:33.802908 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 12:13:33.806487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 12:13:33.807059 ==
8222 12:13:33.809834 DQS Delay:
8223 12:13:33.810440 DQS0 = 0, DQS1 = 0
8224 12:13:33.813216 DQM Delay:
8225 12:13:33.813783 DQM0 = 133, DQM1 = 123
8226 12:13:33.814230 DQ Delay:
8227 12:13:33.816076 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8228 12:13:33.822727 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8229 12:13:33.826506 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8230 12:13:33.829442 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =130
8231 12:13:33.830049
8232 12:13:33.830425
8233 12:13:33.830775
8234 12:13:33.832819 [DramC_TX_OE_Calibration] TA2
8235 12:13:33.836221 Original DQ_B0 (3 6) =30, OEN = 27
8236 12:13:33.839257 Original DQ_B1 (3 6) =30, OEN = 27
8237 12:13:33.839736 24, 0x0, End_B0=24 End_B1=24
8238 12:13:33.842725 25, 0x0, End_B0=25 End_B1=25
8239 12:13:33.846256 26, 0x0, End_B0=26 End_B1=26
8240 12:13:33.849345 27, 0x0, End_B0=27 End_B1=27
8241 12:13:33.849976 28, 0x0, End_B0=28 End_B1=28
8242 12:13:33.853178 29, 0x0, End_B0=29 End_B1=29
8243 12:13:33.856342 30, 0x0, End_B0=30 End_B1=30
8244 12:13:33.859280 31, 0x4545, End_B0=30 End_B1=30
8245 12:13:33.862665 Byte0 end_step=30 best_step=27
8246 12:13:33.866320 Byte1 end_step=30 best_step=27
8247 12:13:33.866894 Byte0 TX OE(2T, 0.5T) = (3, 3)
8248 12:13:33.869550 Byte1 TX OE(2T, 0.5T) = (3, 3)
8249 12:13:33.870067
8250 12:13:33.870446
8251 12:13:33.879346 [DQSOSCAuto] RK1, (LSB)MR18= 0x200c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8252 12:13:33.882787 CH0 RK1: MR19=303, MR18=200C
8253 12:13:33.886199 CH0_RK1: MR19=0x303, MR18=0x200C, DQSOSC=393, MR23=63, INC=23, DEC=15
8254 12:13:33.889092 [RxdqsGatingPostProcess] freq 1600
8255 12:13:33.895880 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8256 12:13:33.899115 best DQS0 dly(2T, 0.5T) = (1, 1)
8257 12:13:33.902508 best DQS1 dly(2T, 0.5T) = (1, 1)
8258 12:13:33.906175 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8259 12:13:33.909279 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8260 12:13:33.912470 best DQS0 dly(2T, 0.5T) = (1, 1)
8261 12:13:33.913052 best DQS1 dly(2T, 0.5T) = (1, 1)
8262 12:13:33.915596 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8263 12:13:33.919328 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8264 12:13:33.922582 Pre-setting of DQS Precalculation
8265 12:13:33.929317 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8266 12:13:33.929891 ==
8267 12:13:33.932689 Dram Type= 6, Freq= 0, CH_1, rank 0
8268 12:13:33.936126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8269 12:13:33.936699 ==
8270 12:13:33.942442 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8271 12:13:33.945693 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8272 12:13:33.948847 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8273 12:13:33.955414 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8274 12:13:33.964920 [CA 0] Center 40 (11~70) winsize 60
8275 12:13:33.968333 [CA 1] Center 40 (10~71) winsize 62
8276 12:13:33.971671 [CA 2] Center 36 (7~66) winsize 60
8277 12:13:33.974630 [CA 3] Center 36 (6~66) winsize 61
8278 12:13:33.978260 [CA 4] Center 36 (6~67) winsize 62
8279 12:13:33.981545 [CA 5] Center 36 (6~66) winsize 61
8280 12:13:33.982154
8281 12:13:33.984653 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8282 12:13:33.985214
8283 12:13:33.988350 [CATrainingPosCal] consider 1 rank data
8284 12:13:33.991104 u2DelayCellTimex100 = 285/100 ps
8285 12:13:33.994832 CA0 delay=40 (11~70),Diff = 4 PI (13 cell)
8286 12:13:34.001256 CA1 delay=40 (10~71),Diff = 4 PI (13 cell)
8287 12:13:34.004973 CA2 delay=36 (7~66),Diff = 0 PI (0 cell)
8288 12:13:34.007939 CA3 delay=36 (6~66),Diff = 0 PI (0 cell)
8289 12:13:34.011597 CA4 delay=36 (6~67),Diff = 0 PI (0 cell)
8290 12:13:34.014610 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
8291 12:13:34.015105
8292 12:13:34.018380 CA PerBit enable=1, Macro0, CA PI delay=36
8293 12:13:34.018978
8294 12:13:34.021145 [CBTSetCACLKResult] CA Dly = 36
8295 12:13:34.024593 CS Dly: 8 (0~39)
8296 12:13:34.028207 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8297 12:13:34.031194 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8298 12:13:34.031794 ==
8299 12:13:34.034381 Dram Type= 6, Freq= 0, CH_1, rank 1
8300 12:13:34.037979 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 12:13:34.041042 ==
8302 12:13:34.044167 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8303 12:13:34.047547 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8304 12:13:34.054659 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8305 12:13:34.057421 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8306 12:13:34.067705 [CA 0] Center 43 (14~72) winsize 59
8307 12:13:34.071049 [CA 1] Center 42 (12~72) winsize 61
8308 12:13:34.074365 [CA 2] Center 38 (9~68) winsize 60
8309 12:13:34.077570 [CA 3] Center 37 (8~67) winsize 60
8310 12:13:34.081051 [CA 4] Center 38 (9~68) winsize 60
8311 12:13:34.084591 [CA 5] Center 37 (8~67) winsize 60
8312 12:13:34.084918
8313 12:13:34.087746 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8314 12:13:34.088076
8315 12:13:34.090959 [CATrainingPosCal] consider 2 rank data
8316 12:13:34.094329 u2DelayCellTimex100 = 285/100 ps
8317 12:13:34.097789 CA0 delay=42 (14~70),Diff = 5 PI (17 cell)
8318 12:13:34.104357 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8319 12:13:34.108034 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8320 12:13:34.111011 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8321 12:13:34.114275 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8322 12:13:34.117573 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8323 12:13:34.118082
8324 12:13:34.121021 CA PerBit enable=1, Macro0, CA PI delay=37
8325 12:13:34.121489
8326 12:13:34.124202 [CBTSetCACLKResult] CA Dly = 37
8327 12:13:34.127564 CS Dly: 10 (0~43)
8328 12:13:34.131085 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8329 12:13:34.134294 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8330 12:13:34.134857
8331 12:13:34.137607 ----->DramcWriteLeveling(PI) begin...
8332 12:13:34.138142 ==
8333 12:13:34.141127 Dram Type= 6, Freq= 0, CH_1, rank 0
8334 12:13:34.147318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 12:13:34.147874 ==
8336 12:13:34.150766 Write leveling (Byte 0): 22 => 22
8337 12:13:34.151230 Write leveling (Byte 1): 28 => 28
8338 12:13:34.154157 DramcWriteLeveling(PI) end<-----
8339 12:13:34.154621
8340 12:13:34.154983 ==
8341 12:13:34.157577 Dram Type= 6, Freq= 0, CH_1, rank 0
8342 12:13:34.164534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 12:13:34.165097 ==
8344 12:13:34.167652 [Gating] SW mode calibration
8345 12:13:34.173849 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8346 12:13:34.177281 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8347 12:13:34.183883 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 12:13:34.187313 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 12:13:34.190874 1 4 8 | B1->B0 | 2626 2e2e | 0 1 | (0 0) (1 1)
8350 12:13:34.197109 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 12:13:34.200773 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 12:13:34.204012 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 12:13:34.210731 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 12:13:34.213624 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8355 12:13:34.217327 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8356 12:13:34.224014 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8357 12:13:34.227268 1 5 8 | B1->B0 | 2e2e 2b2b | 0 1 | (0 1) (1 0)
8358 12:13:34.230552 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8359 12:13:34.233808 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 12:13:34.240208 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 12:13:34.243794 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 12:13:34.247101 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 12:13:34.253532 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 12:13:34.256970 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 12:13:34.260412 1 6 8 | B1->B0 | 3939 4444 | 0 0 | (0 0) (0 0)
8366 12:13:34.267142 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 12:13:34.270226 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 12:13:34.273517 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 12:13:34.280229 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 12:13:34.283831 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 12:13:34.286908 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 12:13:34.294143 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 12:13:34.296746 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8374 12:13:34.300462 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8375 12:13:34.306970 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8376 12:13:34.310284 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 12:13:34.314126 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 12:13:34.319855 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 12:13:34.323658 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 12:13:34.326857 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 12:13:34.333612 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 12:13:34.337196 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 12:13:34.340063 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 12:13:34.346658 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 12:13:34.349981 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 12:13:34.353049 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 12:13:34.360167 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 12:13:34.363351 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 12:13:34.366988 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8390 12:13:34.369932 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8391 12:13:34.376548 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 12:13:34.379947 Total UI for P1: 0, mck2ui 16
8393 12:13:34.383506 best dqsien dly found for B0: ( 1, 9, 10)
8394 12:13:34.386646 Total UI for P1: 0, mck2ui 16
8395 12:13:34.390192 best dqsien dly found for B1: ( 1, 9, 10)
8396 12:13:34.393105 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8397 12:13:34.396833 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8398 12:13:34.397427
8399 12:13:34.399552 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8400 12:13:34.403284 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8401 12:13:34.406890 [Gating] SW calibration Done
8402 12:13:34.407458 ==
8403 12:13:34.409764 Dram Type= 6, Freq= 0, CH_1, rank 0
8404 12:13:34.413188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8405 12:13:34.413756 ==
8406 12:13:34.416533 RX Vref Scan: 0
8407 12:13:34.417100
8408 12:13:34.419955 RX Vref 0 -> 0, step: 1
8409 12:13:34.420581
8410 12:13:34.420963 RX Delay 0 -> 252, step: 8
8411 12:13:34.426267 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8412 12:13:34.430599 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8413 12:13:34.432989 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8414 12:13:34.436573 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8415 12:13:34.439729 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8416 12:13:34.443229 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8417 12:13:34.449814 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8418 12:13:34.453542 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8419 12:13:34.456782 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8420 12:13:34.459979 iDelay=200, Bit 9, Center 123 (80 ~ 167) 88
8421 12:13:34.463568 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8422 12:13:34.469904 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8423 12:13:34.473478 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8424 12:13:34.476037 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8425 12:13:34.480056 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8426 12:13:34.483024 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8427 12:13:34.486767 ==
8428 12:13:34.489545 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 12:13:34.493244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 12:13:34.493815 ==
8431 12:13:34.494248 DQS Delay:
8432 12:13:34.496575 DQS0 = 0, DQS1 = 0
8433 12:13:34.497203 DQM Delay:
8434 12:13:34.499398 DQM0 = 136, DQM1 = 132
8435 12:13:34.500041 DQ Delay:
8436 12:13:34.503049 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =139
8437 12:13:34.506508 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8438 12:13:34.510093 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8439 12:13:34.512961 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8440 12:13:34.513525
8441 12:13:34.513901
8442 12:13:34.514300 ==
8443 12:13:34.515797 Dram Type= 6, Freq= 0, CH_1, rank 0
8444 12:13:34.522601 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8445 12:13:34.523164 ==
8446 12:13:34.523547
8447 12:13:34.523897
8448 12:13:34.526191 TX Vref Scan disable
8449 12:13:34.526669 == TX Byte 0 ==
8450 12:13:34.529282 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8451 12:13:34.535847 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8452 12:13:34.536413 == TX Byte 1 ==
8453 12:13:34.539619 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8454 12:13:34.546057 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8455 12:13:34.546628 ==
8456 12:13:34.549659 Dram Type= 6, Freq= 0, CH_1, rank 0
8457 12:13:34.552430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8458 12:13:34.553012 ==
8459 12:13:34.566124
8460 12:13:34.569190 TX Vref early break, caculate TX vref
8461 12:13:34.571915 TX Vref=16, minBit 10, minWin=21, winSum=365
8462 12:13:34.575683 TX Vref=18, minBit 15, minWin=22, winSum=380
8463 12:13:34.579115 TX Vref=20, minBit 10, minWin=22, winSum=381
8464 12:13:34.582095 TX Vref=22, minBit 10, minWin=23, winSum=393
8465 12:13:34.588580 TX Vref=24, minBit 10, minWin=24, winSum=405
8466 12:13:34.591964 TX Vref=26, minBit 15, minWin=24, winSum=414
8467 12:13:34.595803 TX Vref=28, minBit 10, minWin=25, winSum=422
8468 12:13:34.598503 TX Vref=30, minBit 8, minWin=23, winSum=409
8469 12:13:34.601844 TX Vref=32, minBit 9, minWin=23, winSum=403
8470 12:13:34.605703 TX Vref=34, minBit 9, minWin=23, winSum=391
8471 12:13:34.612409 [TxChooseVref] Worse bit 10, Min win 25, Win sum 422, Final Vref 28
8472 12:13:34.612984
8473 12:13:34.615463 Final TX Range 0 Vref 28
8474 12:13:34.615939
8475 12:13:34.616317 ==
8476 12:13:34.618451 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 12:13:34.621767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 12:13:34.622378 ==
8479 12:13:34.622769
8480 12:13:34.625390
8481 12:13:34.626017 TX Vref Scan disable
8482 12:13:34.631714 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8483 12:13:34.632190 == TX Byte 0 ==
8484 12:13:34.634972 u2DelayCellOfst[0]=17 cells (5 PI)
8485 12:13:34.638215 u2DelayCellOfst[1]=10 cells (3 PI)
8486 12:13:34.641795 u2DelayCellOfst[2]=0 cells (0 PI)
8487 12:13:34.645353 u2DelayCellOfst[3]=3 cells (1 PI)
8488 12:13:34.648530 u2DelayCellOfst[4]=6 cells (2 PI)
8489 12:13:34.651563 u2DelayCellOfst[5]=17 cells (5 PI)
8490 12:13:34.655627 u2DelayCellOfst[6]=17 cells (5 PI)
8491 12:13:34.658328 u2DelayCellOfst[7]=3 cells (1 PI)
8492 12:13:34.662048 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8493 12:13:34.665285 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8494 12:13:34.668001 == TX Byte 1 ==
8495 12:13:34.671320 u2DelayCellOfst[8]=0 cells (0 PI)
8496 12:13:34.675134 u2DelayCellOfst[9]=3 cells (1 PI)
8497 12:13:34.678551 u2DelayCellOfst[10]=10 cells (3 PI)
8498 12:13:34.679132 u2DelayCellOfst[11]=3 cells (1 PI)
8499 12:13:34.681660 u2DelayCellOfst[12]=17 cells (5 PI)
8500 12:13:34.684955 u2DelayCellOfst[13]=17 cells (5 PI)
8501 12:13:34.687916 u2DelayCellOfst[14]=20 cells (6 PI)
8502 12:13:34.691325 u2DelayCellOfst[15]=20 cells (6 PI)
8503 12:13:34.698503 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8504 12:13:34.701089 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8505 12:13:34.701570 DramC Write-DBI on
8506 12:13:34.701981 ==
8507 12:13:34.704849 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 12:13:34.711441 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 12:13:34.712008 ==
8510 12:13:34.712386
8511 12:13:34.712735
8512 12:13:34.713069 TX Vref Scan disable
8513 12:13:34.715285 == TX Byte 0 ==
8514 12:13:34.718625 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8515 12:13:34.722245 == TX Byte 1 ==
8516 12:13:34.725726 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8517 12:13:34.728740 DramC Write-DBI off
8518 12:13:34.729301
8519 12:13:34.729680 [DATLAT]
8520 12:13:34.730081 Freq=1600, CH1 RK0
8521 12:13:34.730434
8522 12:13:34.731886 DATLAT Default: 0xf
8523 12:13:34.732388 0, 0xFFFF, sum = 0
8524 12:13:34.735548 1, 0xFFFF, sum = 0
8525 12:13:34.738700 2, 0xFFFF, sum = 0
8526 12:13:34.739269 3, 0xFFFF, sum = 0
8527 12:13:34.742254 4, 0xFFFF, sum = 0
8528 12:13:34.742836 5, 0xFFFF, sum = 0
8529 12:13:34.745690 6, 0xFFFF, sum = 0
8530 12:13:34.746295 7, 0xFFFF, sum = 0
8531 12:13:34.748640 8, 0xFFFF, sum = 0
8532 12:13:34.749119 9, 0xFFFF, sum = 0
8533 12:13:34.752257 10, 0xFFFF, sum = 0
8534 12:13:34.752737 11, 0xFFFF, sum = 0
8535 12:13:34.755670 12, 0xFFFF, sum = 0
8536 12:13:34.756249 13, 0xFFFF, sum = 0
8537 12:13:34.759051 14, 0x0, sum = 1
8538 12:13:34.759630 15, 0x0, sum = 2
8539 12:13:34.762364 16, 0x0, sum = 3
8540 12:13:34.762938 17, 0x0, sum = 4
8541 12:13:34.765632 best_step = 15
8542 12:13:34.766124
8543 12:13:34.766499 ==
8544 12:13:34.768901 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 12:13:34.772062 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 12:13:34.772639 ==
8547 12:13:34.773016 RX Vref Scan: 1
8548 12:13:34.775599
8549 12:13:34.776069 Set Vref Range= 24 -> 127
8550 12:13:34.776446
8551 12:13:34.778823 RX Vref 24 -> 127, step: 1
8552 12:13:34.779297
8553 12:13:34.782060 RX Delay 19 -> 252, step: 4
8554 12:13:34.782529
8555 12:13:34.785263 Set Vref, RX VrefLevel [Byte0]: 24
8556 12:13:34.788783 [Byte1]: 24
8557 12:13:34.789351
8558 12:13:34.791794 Set Vref, RX VrefLevel [Byte0]: 25
8559 12:13:34.795150 [Byte1]: 25
8560 12:13:34.795729
8561 12:13:34.798421 Set Vref, RX VrefLevel [Byte0]: 26
8562 12:13:34.801462 [Byte1]: 26
8563 12:13:34.806124
8564 12:13:34.806688 Set Vref, RX VrefLevel [Byte0]: 27
8565 12:13:34.809444 [Byte1]: 27
8566 12:13:34.813511
8567 12:13:34.814119 Set Vref, RX VrefLevel [Byte0]: 28
8568 12:13:34.817041 [Byte1]: 28
8569 12:13:34.820836
8570 12:13:34.821401 Set Vref, RX VrefLevel [Byte0]: 29
8571 12:13:34.824441 [Byte1]: 29
8572 12:13:34.829084
8573 12:13:34.829648 Set Vref, RX VrefLevel [Byte0]: 30
8574 12:13:34.832208 [Byte1]: 30
8575 12:13:34.836047
8576 12:13:34.836618 Set Vref, RX VrefLevel [Byte0]: 31
8577 12:13:34.839477 [Byte1]: 31
8578 12:13:34.843583
8579 12:13:34.844052 Set Vref, RX VrefLevel [Byte0]: 32
8580 12:13:34.846783 [Byte1]: 32
8581 12:13:34.851664
8582 12:13:34.852229 Set Vref, RX VrefLevel [Byte0]: 33
8583 12:13:34.854320 [Byte1]: 33
8584 12:13:34.858865
8585 12:13:34.859426 Set Vref, RX VrefLevel [Byte0]: 34
8586 12:13:34.862369 [Byte1]: 34
8587 12:13:34.866605
8588 12:13:34.867174 Set Vref, RX VrefLevel [Byte0]: 35
8589 12:13:34.870126 [Byte1]: 35
8590 12:13:34.874110
8591 12:13:34.874582 Set Vref, RX VrefLevel [Byte0]: 36
8592 12:13:34.877223 [Byte1]: 36
8593 12:13:34.881368
8594 12:13:34.881841 Set Vref, RX VrefLevel [Byte0]: 37
8595 12:13:34.885007 [Byte1]: 37
8596 12:13:34.889482
8597 12:13:34.890085 Set Vref, RX VrefLevel [Byte0]: 38
8598 12:13:34.892276 [Byte1]: 38
8599 12:13:34.896675
8600 12:13:34.897144 Set Vref, RX VrefLevel [Byte0]: 39
8601 12:13:34.899816 [Byte1]: 39
8602 12:13:34.904586
8603 12:13:34.905148 Set Vref, RX VrefLevel [Byte0]: 40
8604 12:13:34.908211 [Byte1]: 40
8605 12:13:34.911842
8606 12:13:34.912410 Set Vref, RX VrefLevel [Byte0]: 41
8607 12:13:34.915146 [Byte1]: 41
8608 12:13:34.919532
8609 12:13:34.920094 Set Vref, RX VrefLevel [Byte0]: 42
8610 12:13:34.922757 [Byte1]: 42
8611 12:13:34.927230
8612 12:13:34.927813 Set Vref, RX VrefLevel [Byte0]: 43
8613 12:13:34.930538 [Byte1]: 43
8614 12:13:34.934697
8615 12:13:34.935264 Set Vref, RX VrefLevel [Byte0]: 44
8616 12:13:34.937851 [Byte1]: 44
8617 12:13:34.942031
8618 12:13:34.942610 Set Vref, RX VrefLevel [Byte0]: 45
8619 12:13:34.945928 [Byte1]: 45
8620 12:13:34.949646
8621 12:13:34.950146 Set Vref, RX VrefLevel [Byte0]: 46
8622 12:13:34.952991 [Byte1]: 46
8623 12:13:34.957069
8624 12:13:34.957539 Set Vref, RX VrefLevel [Byte0]: 47
8625 12:13:34.960672 [Byte1]: 47
8626 12:13:34.965186
8627 12:13:34.965751 Set Vref, RX VrefLevel [Byte0]: 48
8628 12:13:34.968105 [Byte1]: 48
8629 12:13:34.972306
8630 12:13:34.972782 Set Vref, RX VrefLevel [Byte0]: 49
8631 12:13:34.975630 [Byte1]: 49
8632 12:13:34.979971
8633 12:13:34.980539 Set Vref, RX VrefLevel [Byte0]: 50
8634 12:13:34.983159 [Byte1]: 50
8635 12:13:34.987741
8636 12:13:34.988307 Set Vref, RX VrefLevel [Byte0]: 51
8637 12:13:34.990773 [Byte1]: 51
8638 12:13:34.995045
8639 12:13:34.995615 Set Vref, RX VrefLevel [Byte0]: 52
8640 12:13:34.998502 [Byte1]: 52
8641 12:13:35.002499
8642 12:13:35.002971 Set Vref, RX VrefLevel [Byte0]: 53
8643 12:13:35.005911 [Byte1]: 53
8644 12:13:35.010735
8645 12:13:35.011206 Set Vref, RX VrefLevel [Byte0]: 54
8646 12:13:35.013874 [Byte1]: 54
8647 12:13:35.017718
8648 12:13:35.018235 Set Vref, RX VrefLevel [Byte0]: 55
8649 12:13:35.021038 [Byte1]: 55
8650 12:13:35.025633
8651 12:13:35.026247 Set Vref, RX VrefLevel [Byte0]: 56
8652 12:13:35.028743 [Byte1]: 56
8653 12:13:35.033226
8654 12:13:35.033795 Set Vref, RX VrefLevel [Byte0]: 57
8655 12:13:35.036375 [Byte1]: 57
8656 12:13:35.040821
8657 12:13:35.041392 Set Vref, RX VrefLevel [Byte0]: 58
8658 12:13:35.044025 [Byte1]: 58
8659 12:13:35.048058
8660 12:13:35.048635 Set Vref, RX VrefLevel [Byte0]: 59
8661 12:13:35.051408 [Byte1]: 59
8662 12:13:35.055687
8663 12:13:35.056248 Set Vref, RX VrefLevel [Byte0]: 60
8664 12:13:35.058879 [Byte1]: 60
8665 12:13:35.063307
8666 12:13:35.063877 Set Vref, RX VrefLevel [Byte0]: 61
8667 12:13:35.066833 [Byte1]: 61
8668 12:13:35.070925
8669 12:13:35.071497 Set Vref, RX VrefLevel [Byte0]: 62
8670 12:13:35.074494 [Byte1]: 62
8671 12:13:35.078300
8672 12:13:35.078775 Set Vref, RX VrefLevel [Byte0]: 63
8673 12:13:35.081726 [Byte1]: 63
8674 12:13:35.085993
8675 12:13:35.086578 Set Vref, RX VrefLevel [Byte0]: 64
8676 12:13:35.089272 [Byte1]: 64
8677 12:13:35.093626
8678 12:13:35.094220 Set Vref, RX VrefLevel [Byte0]: 65
8679 12:13:35.097046 [Byte1]: 65
8680 12:13:35.101138
8681 12:13:35.101609 Set Vref, RX VrefLevel [Byte0]: 66
8682 12:13:35.104419 [Byte1]: 66
8683 12:13:35.108730
8684 12:13:35.109202 Set Vref, RX VrefLevel [Byte0]: 67
8685 12:13:35.112383 [Byte1]: 67
8686 12:13:35.116393
8687 12:13:35.116952 Set Vref, RX VrefLevel [Byte0]: 68
8688 12:13:35.119619 [Byte1]: 68
8689 12:13:35.123723
8690 12:13:35.124196 Set Vref, RX VrefLevel [Byte0]: 69
8691 12:13:35.127094 [Byte1]: 69
8692 12:13:35.131533
8693 12:13:35.132097 Set Vref, RX VrefLevel [Byte0]: 70
8694 12:13:35.134651 [Byte1]: 70
8695 12:13:35.139009
8696 12:13:35.139516 Set Vref, RX VrefLevel [Byte0]: 71
8697 12:13:35.142505 [Byte1]: 71
8698 12:13:35.146363
8699 12:13:35.146833 Set Vref, RX VrefLevel [Byte0]: 72
8700 12:13:35.149990 [Byte1]: 72
8701 12:13:35.154328
8702 12:13:35.154919 Set Vref, RX VrefLevel [Byte0]: 73
8703 12:13:35.157415 [Byte1]: 73
8704 12:13:35.161770
8705 12:13:35.162278 Set Vref, RX VrefLevel [Byte0]: 74
8706 12:13:35.164798 [Byte1]: 74
8707 12:13:35.169317
8708 12:13:35.169838 Final RX Vref Byte 0 = 59 to rank0
8709 12:13:35.172744 Final RX Vref Byte 1 = 62 to rank0
8710 12:13:35.176090 Final RX Vref Byte 0 = 59 to rank1
8711 12:13:35.179049 Final RX Vref Byte 1 = 62 to rank1==
8712 12:13:35.182234 Dram Type= 6, Freq= 0, CH_1, rank 0
8713 12:13:35.189035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8714 12:13:35.189562 ==
8715 12:13:35.189907 DQS Delay:
8716 12:13:35.190265 DQS0 = 0, DQS1 = 0
8717 12:13:35.192158 DQM Delay:
8718 12:13:35.192585 DQM0 = 134, DQM1 = 129
8719 12:13:35.195732 DQ Delay:
8720 12:13:35.199373 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =132
8721 12:13:35.202205 DQ4 =130, DQ5 =144, DQ6 =146, DQ7 =132
8722 12:13:35.205589 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8723 12:13:35.208977 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =136
8724 12:13:35.209488
8725 12:13:35.209829
8726 12:13:35.210206
8727 12:13:35.212174 [DramC_TX_OE_Calibration] TA2
8728 12:13:35.215926 Original DQ_B0 (3 6) =30, OEN = 27
8729 12:13:35.218983 Original DQ_B1 (3 6) =30, OEN = 27
8730 12:13:35.222201 24, 0x0, End_B0=24 End_B1=24
8731 12:13:35.222631 25, 0x0, End_B0=25 End_B1=25
8732 12:13:35.225573 26, 0x0, End_B0=26 End_B1=26
8733 12:13:35.228773 27, 0x0, End_B0=27 End_B1=27
8734 12:13:35.232610 28, 0x0, End_B0=28 End_B1=28
8735 12:13:35.235789 29, 0x0, End_B0=29 End_B1=29
8736 12:13:35.236319 30, 0x0, End_B0=30 End_B1=30
8737 12:13:35.238758 31, 0x4141, End_B0=30 End_B1=30
8738 12:13:35.241998 Byte0 end_step=30 best_step=27
8739 12:13:35.245624 Byte1 end_step=30 best_step=27
8740 12:13:35.248710 Byte0 TX OE(2T, 0.5T) = (3, 3)
8741 12:13:35.252568 Byte1 TX OE(2T, 0.5T) = (3, 3)
8742 12:13:35.253092
8743 12:13:35.253431
8744 12:13:35.258596 [DQSOSCAuto] RK0, (LSB)MR18= 0x1725, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8745 12:13:35.262483 CH1 RK0: MR19=303, MR18=1725
8746 12:13:35.268648 CH1_RK0: MR19=0x303, MR18=0x1725, DQSOSC=391, MR23=63, INC=24, DEC=16
8747 12:13:35.269179
8748 12:13:35.271933 ----->DramcWriteLeveling(PI) begin...
8749 12:13:35.272458 ==
8750 12:13:35.275701 Dram Type= 6, Freq= 0, CH_1, rank 1
8751 12:13:35.278430 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8752 12:13:35.278863 ==
8753 12:13:35.282273 Write leveling (Byte 0): 24 => 24
8754 12:13:35.285452 Write leveling (Byte 1): 29 => 29
8755 12:13:35.288993 DramcWriteLeveling(PI) end<-----
8756 12:13:35.289540
8757 12:13:35.289889 ==
8758 12:13:35.292031 Dram Type= 6, Freq= 0, CH_1, rank 1
8759 12:13:35.295099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8760 12:13:35.295529 ==
8761 12:13:35.298817 [Gating] SW mode calibration
8762 12:13:35.305006 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8763 12:13:35.311444 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8764 12:13:35.315353 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 12:13:35.321643 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 12:13:35.325080 1 4 8 | B1->B0 | 3232 2323 | 1 0 | (0 0) (0 0)
8767 12:13:35.328436 1 4 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
8768 12:13:35.335127 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 12:13:35.338509 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 12:13:35.341581 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8771 12:13:35.348313 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8772 12:13:35.351509 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8773 12:13:35.354816 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 12:13:35.358163 1 5 8 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 0)
8775 12:13:35.364602 1 5 12 | B1->B0 | 2323 3232 | 0 1 | (1 0) (1 0)
8776 12:13:35.368048 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 12:13:35.371925 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 12:13:35.378126 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 12:13:35.381533 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 12:13:35.384898 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8781 12:13:35.391196 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 12:13:35.394551 1 6 8 | B1->B0 | 3f3f 2323 | 1 0 | (0 0) (0 0)
8783 12:13:35.397761 1 6 12 | B1->B0 | 4646 3939 | 0 0 | (0 0) (0 0)
8784 12:13:35.404411 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 12:13:35.408292 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 12:13:35.411033 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8787 12:13:35.418031 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8788 12:13:35.421283 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 12:13:35.424145 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 12:13:35.431456 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8791 12:13:35.434803 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8792 12:13:35.438020 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 12:13:35.444658 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 12:13:35.448118 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 12:13:35.451001 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 12:13:35.458053 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 12:13:35.461379 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 12:13:35.464508 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 12:13:35.471116 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 12:13:35.474627 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 12:13:35.477700 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 12:13:35.481482 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 12:13:35.487880 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 12:13:35.491244 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 12:13:35.494311 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 12:13:35.501123 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8807 12:13:35.504108 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8808 12:13:35.507880 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 12:13:35.510883 Total UI for P1: 0, mck2ui 16
8810 12:13:35.514374 best dqsien dly found for B0: ( 1, 9, 10)
8811 12:13:35.517676 Total UI for P1: 0, mck2ui 16
8812 12:13:35.521104 best dqsien dly found for B1: ( 1, 9, 10)
8813 12:13:35.524280 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8814 12:13:35.527577 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8815 12:13:35.531265
8816 12:13:35.534360 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8817 12:13:35.537766 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8818 12:13:35.541086 [Gating] SW calibration Done
8819 12:13:35.541651 ==
8820 12:13:35.544197 Dram Type= 6, Freq= 0, CH_1, rank 1
8821 12:13:35.547546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8822 12:13:35.548120 ==
8823 12:13:35.550478 RX Vref Scan: 0
8824 12:13:35.550948
8825 12:13:35.551315 RX Vref 0 -> 0, step: 1
8826 12:13:35.551662
8827 12:13:35.554236 RX Delay 0 -> 252, step: 8
8828 12:13:35.557690 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8829 12:13:35.560682 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8830 12:13:35.567241 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8831 12:13:35.570926 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8832 12:13:35.574569 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8833 12:13:35.577125 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8834 12:13:35.580523 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8835 12:13:35.587414 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8836 12:13:35.590890 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8837 12:13:35.594304 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8838 12:13:35.597400 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8839 12:13:35.600604 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8840 12:13:35.607709 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8841 12:13:35.611278 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8842 12:13:35.613756 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8843 12:13:35.617345 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8844 12:13:35.617922 ==
8845 12:13:35.620480 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 12:13:35.627168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 12:13:35.627739 ==
8848 12:13:35.628115 DQS Delay:
8849 12:13:35.628461 DQS0 = 0, DQS1 = 0
8850 12:13:35.630307 DQM Delay:
8851 12:13:35.630778 DQM0 = 137, DQM1 = 132
8852 12:13:35.633609 DQ Delay:
8853 12:13:35.637199 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8854 12:13:35.640884 DQ4 =139, DQ5 =147, DQ6 =147, DQ7 =135
8855 12:13:35.644019 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8856 12:13:35.647022 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8857 12:13:35.647498
8858 12:13:35.647869
8859 12:13:35.648216 ==
8860 12:13:35.650529 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 12:13:35.653819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 12:13:35.657243 ==
8863 12:13:35.657814
8864 12:13:35.658248
8865 12:13:35.658602 TX Vref Scan disable
8866 12:13:35.660518 == TX Byte 0 ==
8867 12:13:35.664008 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8868 12:13:35.667057 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8869 12:13:35.670575 == TX Byte 1 ==
8870 12:13:35.673630 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8871 12:13:35.677412 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8872 12:13:35.677887 ==
8873 12:13:35.680186 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 12:13:35.687008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 12:13:35.687586 ==
8876 12:13:35.700452
8877 12:13:35.703437 TX Vref early break, caculate TX vref
8878 12:13:35.706536 TX Vref=16, minBit 9, minWin=21, winSum=378
8879 12:13:35.709880 TX Vref=18, minBit 11, minWin=22, winSum=386
8880 12:13:35.713557 TX Vref=20, minBit 8, minWin=23, winSum=394
8881 12:13:35.716680 TX Vref=22, minBit 9, minWin=22, winSum=401
8882 12:13:35.720102 TX Vref=24, minBit 9, minWin=24, winSum=412
8883 12:13:35.726800 TX Vref=26, minBit 9, minWin=24, winSum=416
8884 12:13:35.730000 TX Vref=28, minBit 0, minWin=25, winSum=419
8885 12:13:35.733444 TX Vref=30, minBit 8, minWin=24, winSum=413
8886 12:13:35.736709 TX Vref=32, minBit 9, minWin=24, winSum=401
8887 12:13:35.739864 TX Vref=34, minBit 10, minWin=23, winSum=398
8888 12:13:35.743274 TX Vref=36, minBit 11, minWin=22, winSum=387
8889 12:13:35.749817 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
8890 12:13:35.750421
8891 12:13:35.753088 Final TX Range 0 Vref 28
8892 12:13:35.753562
8893 12:13:35.753931 ==
8894 12:13:35.756446 Dram Type= 6, Freq= 0, CH_1, rank 1
8895 12:13:35.759691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8896 12:13:35.760166 ==
8897 12:13:35.763631
8898 12:13:35.764198
8899 12:13:35.764576 TX Vref Scan disable
8900 12:13:35.770109 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8901 12:13:35.770682 == TX Byte 0 ==
8902 12:13:35.773682 u2DelayCellOfst[0]=17 cells (5 PI)
8903 12:13:35.776471 u2DelayCellOfst[1]=10 cells (3 PI)
8904 12:13:35.779648 u2DelayCellOfst[2]=0 cells (0 PI)
8905 12:13:35.782957 u2DelayCellOfst[3]=3 cells (1 PI)
8906 12:13:35.786555 u2DelayCellOfst[4]=6 cells (2 PI)
8907 12:13:35.789896 u2DelayCellOfst[5]=17 cells (5 PI)
8908 12:13:35.793049 u2DelayCellOfst[6]=17 cells (5 PI)
8909 12:13:35.796150 u2DelayCellOfst[7]=3 cells (1 PI)
8910 12:13:35.799609 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8911 12:13:35.802795 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8912 12:13:35.806052 == TX Byte 1 ==
8913 12:13:35.810099 u2DelayCellOfst[8]=0 cells (0 PI)
8914 12:13:35.813318 u2DelayCellOfst[9]=3 cells (1 PI)
8915 12:13:35.816492 u2DelayCellOfst[10]=6 cells (2 PI)
8916 12:13:35.817062 u2DelayCellOfst[11]=3 cells (1 PI)
8917 12:13:35.819324 u2DelayCellOfst[12]=10 cells (3 PI)
8918 12:13:35.822909 u2DelayCellOfst[13]=17 cells (5 PI)
8919 12:13:35.826146 u2DelayCellOfst[14]=17 cells (5 PI)
8920 12:13:35.829384 u2DelayCellOfst[15]=20 cells (6 PI)
8921 12:13:35.836115 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8922 12:13:35.839757 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8923 12:13:35.840255 DramC Write-DBI on
8924 12:13:35.840634 ==
8925 12:13:35.843072 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 12:13:35.849454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 12:13:35.850079 ==
8928 12:13:35.850468
8929 12:13:35.850820
8930 12:13:35.851154 TX Vref Scan disable
8931 12:13:35.853518 == TX Byte 0 ==
8932 12:13:35.856458 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8933 12:13:35.859839 == TX Byte 1 ==
8934 12:13:35.863120 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8935 12:13:35.866857 DramC Write-DBI off
8936 12:13:35.867333
8937 12:13:35.867709 [DATLAT]
8938 12:13:35.868057 Freq=1600, CH1 RK1
8939 12:13:35.868399
8940 12:13:35.870352 DATLAT Default: 0xf
8941 12:13:35.870823 0, 0xFFFF, sum = 0
8942 12:13:35.873532 1, 0xFFFF, sum = 0
8943 12:13:35.874056 2, 0xFFFF, sum = 0
8944 12:13:35.876777 3, 0xFFFF, sum = 0
8945 12:13:35.879969 4, 0xFFFF, sum = 0
8946 12:13:35.880451 5, 0xFFFF, sum = 0
8947 12:13:35.883470 6, 0xFFFF, sum = 0
8948 12:13:35.883950 7, 0xFFFF, sum = 0
8949 12:13:35.886575 8, 0xFFFF, sum = 0
8950 12:13:35.887056 9, 0xFFFF, sum = 0
8951 12:13:35.889984 10, 0xFFFF, sum = 0
8952 12:13:35.890564 11, 0xFFFF, sum = 0
8953 12:13:35.893792 12, 0xFFFF, sum = 0
8954 12:13:35.894340 13, 0xFFFF, sum = 0
8955 12:13:35.896779 14, 0x0, sum = 1
8956 12:13:35.897264 15, 0x0, sum = 2
8957 12:13:35.899841 16, 0x0, sum = 3
8958 12:13:35.900278 17, 0x0, sum = 4
8959 12:13:35.903306 best_step = 15
8960 12:13:35.903793
8961 12:13:35.904158 ==
8962 12:13:35.906935 Dram Type= 6, Freq= 0, CH_1, rank 1
8963 12:13:35.909968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8964 12:13:35.910422 ==
8965 12:13:35.910764 RX Vref Scan: 0
8966 12:13:35.911089
8967 12:13:35.913377 RX Vref 0 -> 0, step: 1
8968 12:13:35.914026
8969 12:13:35.916432 RX Delay 19 -> 252, step: 4
8970 12:13:35.920578 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8971 12:13:35.923098 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8972 12:13:35.929888 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8973 12:13:35.933191 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8974 12:13:35.936336 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8975 12:13:35.939565 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8976 12:13:35.942966 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8977 12:13:35.949477 iDelay=195, Bit 7, Center 130 (83 ~ 178) 96
8978 12:13:35.952943 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8979 12:13:35.956697 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
8980 12:13:35.959530 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8981 12:13:35.963266 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8982 12:13:35.969626 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8983 12:13:35.973061 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8984 12:13:35.976282 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8985 12:13:35.978982 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8986 12:13:35.979081 ==
8987 12:13:35.982262 Dram Type= 6, Freq= 0, CH_1, rank 1
8988 12:13:35.989124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8989 12:13:35.989675 ==
8990 12:13:35.990197 DQS Delay:
8991 12:13:35.992749 DQS0 = 0, DQS1 = 0
8992 12:13:35.993321 DQM Delay:
8993 12:13:35.995874 DQM0 = 133, DQM1 = 130
8994 12:13:35.996314 DQ Delay:
8995 12:13:35.999034 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
8996 12:13:36.002687 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =130
8997 12:13:36.005759 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =124
8998 12:13:36.009191 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
8999 12:13:36.009645
9000 12:13:36.010049
9001 12:13:36.010377
9002 12:13:36.012384 [DramC_TX_OE_Calibration] TA2
9003 12:13:36.015942 Original DQ_B0 (3 6) =30, OEN = 27
9004 12:13:36.019175 Original DQ_B1 (3 6) =30, OEN = 27
9005 12:13:36.022651 24, 0x0, End_B0=24 End_B1=24
9006 12:13:36.023124 25, 0x0, End_B0=25 End_B1=25
9007 12:13:36.025861 26, 0x0, End_B0=26 End_B1=26
9008 12:13:36.029091 27, 0x0, End_B0=27 End_B1=27
9009 12:13:36.032561 28, 0x0, End_B0=28 End_B1=28
9010 12:13:36.035582 29, 0x0, End_B0=29 End_B1=29
9011 12:13:36.036013 30, 0x0, End_B0=30 End_B1=30
9012 12:13:36.039304 31, 0x4141, End_B0=30 End_B1=30
9013 12:13:36.042208 Byte0 end_step=30 best_step=27
9014 12:13:36.046154 Byte1 end_step=30 best_step=27
9015 12:13:36.049124 Byte0 TX OE(2T, 0.5T) = (3, 3)
9016 12:13:36.052376 Byte1 TX OE(2T, 0.5T) = (3, 3)
9017 12:13:36.052796
9018 12:13:36.053142
9019 12:13:36.059271 [DQSOSCAuto] RK1, (LSB)MR18= 0x1904, (MSB)MR19= 0x303, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
9020 12:13:36.062398 CH1 RK1: MR19=303, MR18=1904
9021 12:13:36.069015 CH1_RK1: MR19=0x303, MR18=0x1904, DQSOSC=397, MR23=63, INC=23, DEC=15
9022 12:13:36.072310 [RxdqsGatingPostProcess] freq 1600
9023 12:13:36.075418 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9024 12:13:36.078776 best DQS0 dly(2T, 0.5T) = (1, 1)
9025 12:13:36.082185 best DQS1 dly(2T, 0.5T) = (1, 1)
9026 12:13:36.086059 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9027 12:13:36.088825 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9028 12:13:36.092243 best DQS0 dly(2T, 0.5T) = (1, 1)
9029 12:13:36.095509 best DQS1 dly(2T, 0.5T) = (1, 1)
9030 12:13:36.098982 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9031 12:13:36.102048 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9032 12:13:36.105486 Pre-setting of DQS Precalculation
9033 12:13:36.108768 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9034 12:13:36.115664 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9035 12:13:36.125829 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9036 12:13:36.126353
9037 12:13:36.126841
9038 12:13:36.127187 [Calibration Summary] 3200 Mbps
9039 12:13:36.128724 CH 0, Rank 0
9040 12:13:36.129148 SW Impedance : PASS
9041 12:13:36.132266 DUTY Scan : NO K
9042 12:13:36.135798 ZQ Calibration : PASS
9043 12:13:36.136220 Jitter Meter : NO K
9044 12:13:36.138763 CBT Training : PASS
9045 12:13:36.142118 Write leveling : PASS
9046 12:13:36.142549 RX DQS gating : PASS
9047 12:13:36.145571 RX DQ/DQS(RDDQC) : PASS
9048 12:13:36.148376 TX DQ/DQS : PASS
9049 12:13:36.148460 RX DATLAT : PASS
9050 12:13:36.151609 RX DQ/DQS(Engine): PASS
9051 12:13:36.155107 TX OE : PASS
9052 12:13:36.155192 All Pass.
9053 12:13:36.155258
9054 12:13:36.155319 CH 0, Rank 1
9055 12:13:36.158237 SW Impedance : PASS
9056 12:13:36.161431 DUTY Scan : NO K
9057 12:13:36.161520 ZQ Calibration : PASS
9058 12:13:36.164849 Jitter Meter : NO K
9059 12:13:36.168199 CBT Training : PASS
9060 12:13:36.168295 Write leveling : PASS
9061 12:13:36.171460 RX DQS gating : PASS
9062 12:13:36.174779 RX DQ/DQS(RDDQC) : PASS
9063 12:13:36.174884 TX DQ/DQS : PASS
9064 12:13:36.178238 RX DATLAT : PASS
9065 12:13:36.178351 RX DQ/DQS(Engine): PASS
9066 12:13:36.181688 TX OE : PASS
9067 12:13:36.181814 All Pass.
9068 12:13:36.181912
9069 12:13:36.184836 CH 1, Rank 0
9070 12:13:36.184960 SW Impedance : PASS
9071 12:13:36.188235 DUTY Scan : NO K
9072 12:13:36.191878 ZQ Calibration : PASS
9073 12:13:36.192311 Jitter Meter : NO K
9074 12:13:36.194901 CBT Training : PASS
9075 12:13:36.198469 Write leveling : PASS
9076 12:13:36.198911 RX DQS gating : PASS
9077 12:13:36.201848 RX DQ/DQS(RDDQC) : PASS
9078 12:13:36.205041 TX DQ/DQS : PASS
9079 12:13:36.205475 RX DATLAT : PASS
9080 12:13:36.208622 RX DQ/DQS(Engine): PASS
9081 12:13:36.211986 TX OE : PASS
9082 12:13:36.212417 All Pass.
9083 12:13:36.212757
9084 12:13:36.213073 CH 1, Rank 1
9085 12:13:36.215451 SW Impedance : PASS
9086 12:13:36.218309 DUTY Scan : NO K
9087 12:13:36.218739 ZQ Calibration : PASS
9088 12:13:36.221800 Jitter Meter : NO K
9089 12:13:36.225433 CBT Training : PASS
9090 12:13:36.225857 Write leveling : PASS
9091 12:13:36.228958 RX DQS gating : PASS
9092 12:13:36.229393 RX DQ/DQS(RDDQC) : PASS
9093 12:13:36.232022 TX DQ/DQS : PASS
9094 12:13:36.235191 RX DATLAT : PASS
9095 12:13:36.235797 RX DQ/DQS(Engine): PASS
9096 12:13:36.238461 TX OE : PASS
9097 12:13:36.238892 All Pass.
9098 12:13:36.239252
9099 12:13:36.241999 DramC Write-DBI on
9100 12:13:36.245052 PER_BANK_REFRESH: Hybrid Mode
9101 12:13:36.245608 TX_TRACKING: ON
9102 12:13:36.255288 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9103 12:13:36.261925 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9104 12:13:36.268276 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9105 12:13:36.274940 [FAST_K] Save calibration result to emmc
9106 12:13:36.275615 sync common calibartion params.
9107 12:13:36.278481 sync cbt_mode0:1, 1:1
9108 12:13:36.281866 dram_init: ddr_geometry: 2
9109 12:13:36.282335 dram_init: ddr_geometry: 2
9110 12:13:36.284995 dram_init: ddr_geometry: 2
9111 12:13:36.288137 0:dram_rank_size:100000000
9112 12:13:36.291642 1:dram_rank_size:100000000
9113 12:13:36.295143 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9114 12:13:36.298504 DFS_SHUFFLE_HW_MODE: ON
9115 12:13:36.301518 dramc_set_vcore_voltage set vcore to 725000
9116 12:13:36.304736 Read voltage for 1600, 0
9117 12:13:36.305170 Vio18 = 0
9118 12:13:36.305682 Vcore = 725000
9119 12:13:36.308253 Vdram = 0
9120 12:13:36.308771 Vddq = 0
9121 12:13:36.309334 Vmddr = 0
9122 12:13:36.311598 switch to 3200 Mbps bootup
9123 12:13:36.314904 [DramcRunTimeConfig]
9124 12:13:36.315561 PHYPLL
9125 12:13:36.315973 DPM_CONTROL_AFTERK: ON
9126 12:13:36.318086 PER_BANK_REFRESH: ON
9127 12:13:36.321658 REFRESH_OVERHEAD_REDUCTION: ON
9128 12:13:36.322133 CMD_PICG_NEW_MODE: OFF
9129 12:13:36.324793 XRTWTW_NEW_MODE: ON
9130 12:13:36.328164 XRTRTR_NEW_MODE: ON
9131 12:13:36.328818 TX_TRACKING: ON
9132 12:13:36.331428 RDSEL_TRACKING: OFF
9133 12:13:36.331858 DQS Precalculation for DVFS: ON
9134 12:13:36.334742 RX_TRACKING: OFF
9135 12:13:36.335224 HW_GATING DBG: ON
9136 12:13:36.337991 ZQCS_ENABLE_LP4: ON
9137 12:13:36.338567 RX_PICG_NEW_MODE: ON
9138 12:13:36.341681 TX_PICG_NEW_MODE: ON
9139 12:13:36.344720 ENABLE_RX_DCM_DPHY: ON
9140 12:13:36.348049 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9141 12:13:36.348666 DUMMY_READ_FOR_TRACKING: OFF
9142 12:13:36.351242 !!! SPM_CONTROL_AFTERK: OFF
9143 12:13:36.354831 !!! SPM could not control APHY
9144 12:13:36.358008 IMPEDANCE_TRACKING: ON
9145 12:13:36.358485 TEMP_SENSOR: ON
9146 12:13:36.361732 HW_SAVE_FOR_SR: OFF
9147 12:13:36.362305 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9148 12:13:36.368277 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9149 12:13:36.368814 Read ODT Tracking: ON
9150 12:13:36.371451 Refresh Rate DeBounce: ON
9151 12:13:36.372001 DFS_NO_QUEUE_FLUSH: ON
9152 12:13:36.374887 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9153 12:13:36.378114 ENABLE_DFS_RUNTIME_MRW: OFF
9154 12:13:36.381473 DDR_RESERVE_NEW_MODE: ON
9155 12:13:36.382102 MR_CBT_SWITCH_FREQ: ON
9156 12:13:36.384588 =========================
9157 12:13:36.404261 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9158 12:13:36.407467 dram_init: ddr_geometry: 2
9159 12:13:36.425618 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9160 12:13:36.429334 dram_init: dram init end (result: 0)
9161 12:13:36.435649 DRAM-K: Full calibration passed in 24514 msecs
9162 12:13:36.439199 MRC: failed to locate region type 0.
9163 12:13:36.439630 DRAM rank0 size:0x100000000,
9164 12:13:36.442110 DRAM rank1 size=0x100000000
9165 12:13:36.452449 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9166 12:13:36.458895 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9167 12:13:36.465630 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9168 12:13:36.471992 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9169 12:13:36.475129 DRAM rank0 size:0x100000000,
9170 12:13:36.478495 DRAM rank1 size=0x100000000
9171 12:13:36.478612 CBMEM:
9172 12:13:36.482557 IMD: root @ 0xfffff000 254 entries.
9173 12:13:36.485270 IMD: root @ 0xffffec00 62 entries.
9174 12:13:36.488676 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9175 12:13:36.492492 WARNING: RO_VPD is uninitialized or empty.
9176 12:13:36.498526 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9177 12:13:36.505773 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9178 12:13:36.518673 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9179 12:13:36.529974 BS: romstage times (exec / console): total (unknown) / 24009 ms
9180 12:13:36.530424
9181 12:13:36.530764
9182 12:13:36.539980 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9183 12:13:36.543344 ARM64: Exception handlers installed.
9184 12:13:36.546299 ARM64: Testing exception
9185 12:13:36.550025 ARM64: Done test exception
9186 12:13:36.550454 Enumerating buses...
9187 12:13:36.553338 Show all devs... Before device enumeration.
9188 12:13:36.556772 Root Device: enabled 1
9189 12:13:36.559725 CPU_CLUSTER: 0: enabled 1
9190 12:13:36.560155 CPU: 00: enabled 1
9191 12:13:36.563122 Compare with tree...
9192 12:13:36.563551 Root Device: enabled 1
9193 12:13:36.566189 CPU_CLUSTER: 0: enabled 1
9194 12:13:36.569694 CPU: 00: enabled 1
9195 12:13:36.570142 Root Device scanning...
9196 12:13:36.572976 scan_static_bus for Root Device
9197 12:13:36.576681 CPU_CLUSTER: 0 enabled
9198 12:13:36.579749 scan_static_bus for Root Device done
9199 12:13:36.583119 scan_bus: bus Root Device finished in 8 msecs
9200 12:13:36.583558 done
9201 12:13:36.589891 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9202 12:13:36.592894 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9203 12:13:36.599720 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9204 12:13:36.603126 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9205 12:13:36.606278 Allocating resources...
9206 12:13:36.609753 Reading resources...
9207 12:13:36.612891 Root Device read_resources bus 0 link: 0
9208 12:13:36.613317 DRAM rank0 size:0x100000000,
9209 12:13:36.616099 DRAM rank1 size=0x100000000
9210 12:13:36.619540 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9211 12:13:36.623266 CPU: 00 missing read_resources
9212 12:13:36.626050 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9213 12:13:36.633025 Root Device read_resources bus 0 link: 0 done
9214 12:13:36.633452 Done reading resources.
9215 12:13:36.639554 Show resources in subtree (Root Device)...After reading.
9216 12:13:36.642777 Root Device child on link 0 CPU_CLUSTER: 0
9217 12:13:36.646184 CPU_CLUSTER: 0 child on link 0 CPU: 00
9218 12:13:36.656192 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9219 12:13:36.656630 CPU: 00
9220 12:13:36.659697 Root Device assign_resources, bus 0 link: 0
9221 12:13:36.662792 CPU_CLUSTER: 0 missing set_resources
9222 12:13:36.665846 Root Device assign_resources, bus 0 link: 0 done
9223 12:13:36.669701 Done setting resources.
9224 12:13:36.676136 Show resources in subtree (Root Device)...After assigning values.
9225 12:13:36.679461 Root Device child on link 0 CPU_CLUSTER: 0
9226 12:13:36.682619 CPU_CLUSTER: 0 child on link 0 CPU: 00
9227 12:13:36.692892 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9228 12:13:36.693329 CPU: 00
9229 12:13:36.696235 Done allocating resources.
9230 12:13:36.699665 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9231 12:13:36.702563 Enabling resources...
9232 12:13:36.702994 done.
9233 12:13:36.709210 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9234 12:13:36.709644 Initializing devices...
9235 12:13:36.712705 Root Device init
9236 12:13:36.713135 init hardware done!
9237 12:13:36.716025 0x00000018: ctrlr->caps
9238 12:13:36.719220 52.000 MHz: ctrlr->f_max
9239 12:13:36.719688 0.400 MHz: ctrlr->f_min
9240 12:13:36.722685 0x40ff8080: ctrlr->voltages
9241 12:13:36.723124 sclk: 390625
9242 12:13:36.725890 Bus Width = 1
9243 12:13:36.726476 sclk: 390625
9244 12:13:36.726852 Bus Width = 1
9245 12:13:36.729498 Early init status = 3
9246 12:13:36.732932 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9247 12:13:36.737313 in-header: 03 fc 00 00 01 00 00 00
9248 12:13:36.740561 in-data: 00
9249 12:13:36.744288 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9250 12:13:36.748787 in-header: 03 fd 00 00 00 00 00 00
9251 12:13:36.751939 in-data:
9252 12:13:36.755209 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9253 12:13:36.759542 in-header: 03 fc 00 00 01 00 00 00
9254 12:13:36.762797 in-data: 00
9255 12:13:36.765519 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9256 12:13:36.771127 in-header: 03 fd 00 00 00 00 00 00
9257 12:13:36.774753 in-data:
9258 12:13:36.777513 [SSUSB] Setting up USB HOST controller...
9259 12:13:36.781042 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9260 12:13:36.784309 [SSUSB] phy power-on done.
9261 12:13:36.787678 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9262 12:13:36.794471 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9263 12:13:36.797787 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9264 12:13:36.804166 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9265 12:13:36.811000 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9266 12:13:36.817839 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9267 12:13:36.824051 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9268 12:13:36.830846 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9269 12:13:36.834306 SPM: binary array size = 0x9dc
9270 12:13:36.837490 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9271 12:13:36.844188 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9272 12:13:36.850705 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9273 12:13:36.853838 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9274 12:13:36.860173 configure_display: Starting display init
9275 12:13:36.894177 anx7625_power_on_init: Init interface.
9276 12:13:36.897408 anx7625_disable_pd_protocol: Disabled PD feature.
9277 12:13:36.900869 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9278 12:13:36.928522 anx7625_start_dp_work: Secure OCM version=00
9279 12:13:36.931749 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9280 12:13:36.947034 sp_tx_get_edid_block: EDID Block = 1
9281 12:13:37.049180 Extracted contents:
9282 12:13:37.052351 header: 00 ff ff ff ff ff ff 00
9283 12:13:37.055957 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9284 12:13:37.059107 version: 01 04
9285 12:13:37.062411 basic params: 95 1f 11 78 0a
9286 12:13:37.065493 chroma info: 76 90 94 55 54 90 27 21 50 54
9287 12:13:37.069224 established: 00 00 00
9288 12:13:37.076047 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9289 12:13:37.079094 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9290 12:13:37.085968 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9291 12:13:37.092440 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9292 12:13:37.099080 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9293 12:13:37.102237 extensions: 00
9294 12:13:37.102659 checksum: fb
9295 12:13:37.102993
9296 12:13:37.105684 Manufacturer: IVO Model 57d Serial Number 0
9297 12:13:37.108799 Made week 0 of 2020
9298 12:13:37.109362 EDID version: 1.4
9299 12:13:37.112170 Digital display
9300 12:13:37.115669 6 bits per primary color channel
9301 12:13:37.116233 DisplayPort interface
9302 12:13:37.118902 Maximum image size: 31 cm x 17 cm
9303 12:13:37.122323 Gamma: 220%
9304 12:13:37.122882 Check DPMS levels
9305 12:13:37.125199 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9306 12:13:37.132122 First detailed timing is preferred timing
9307 12:13:37.132574 Established timings supported:
9308 12:13:37.135397 Standard timings supported:
9309 12:13:37.138465 Detailed timings
9310 12:13:37.142160 Hex of detail: 383680a07038204018303c0035ae10000019
9311 12:13:37.145209 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9312 12:13:37.151558 0780 0798 07c8 0820 hborder 0
9313 12:13:37.154733 0438 043b 0447 0458 vborder 0
9314 12:13:37.158123 -hsync -vsync
9315 12:13:37.158204 Did detailed timing
9316 12:13:37.164952 Hex of detail: 000000000000000000000000000000000000
9317 12:13:37.168437 Manufacturer-specified data, tag 0
9318 12:13:37.171451 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9319 12:13:37.174759 ASCII string: InfoVision
9320 12:13:37.178453 Hex of detail: 000000fe00523134304e574635205248200a
9321 12:13:37.181579 ASCII string: R140NWF5 RH
9322 12:13:37.181677 Checksum
9323 12:13:37.185090 Checksum: 0xfb (valid)
9324 12:13:37.188259 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9325 12:13:37.191538 DSI data_rate: 832800000 bps
9326 12:13:37.198228 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9327 12:13:37.201593 anx7625_parse_edid: pixelclock(138800).
9328 12:13:37.204572 hactive(1920), hsync(48), hfp(24), hbp(88)
9329 12:13:37.208085 vactive(1080), vsync(12), vfp(3), vbp(17)
9330 12:13:37.211659 anx7625_dsi_config: config dsi.
9331 12:13:37.217676 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9332 12:13:37.231932 anx7625_dsi_config: success to config DSI
9333 12:13:37.234826 anx7625_dp_start: MIPI phy setup OK.
9334 12:13:37.237874 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9335 12:13:37.241471 mtk_ddp_mode_set invalid vrefresh 60
9336 12:13:37.244538 main_disp_path_setup
9337 12:13:37.244957 ovl_layer_smi_id_en
9338 12:13:37.248105 ovl_layer_smi_id_en
9339 12:13:37.248522 ccorr_config
9340 12:13:37.248849 aal_config
9341 12:13:37.251362 gamma_config
9342 12:13:37.251777 postmask_config
9343 12:13:37.254879 dither_config
9344 12:13:37.258438 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9345 12:13:37.264656 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9346 12:13:37.268127 Root Device init finished in 552 msecs
9347 12:13:37.268695 CPU_CLUSTER: 0 init
9348 12:13:37.278248 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9349 12:13:37.281029 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9350 12:13:37.284656 APU_MBOX 0x190000b0 = 0x10001
9351 12:13:37.287909 APU_MBOX 0x190001b0 = 0x10001
9352 12:13:37.291241 APU_MBOX 0x190005b0 = 0x10001
9353 12:13:37.294552 APU_MBOX 0x190006b0 = 0x10001
9354 12:13:37.297767 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9355 12:13:37.310505 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9356 12:13:37.322699 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9357 12:13:37.329151 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9358 12:13:37.340990 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9359 12:13:37.350054 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9360 12:13:37.353443 CPU_CLUSTER: 0 init finished in 81 msecs
9361 12:13:37.356958 Devices initialized
9362 12:13:37.360044 Show all devs... After init.
9363 12:13:37.360481 Root Device: enabled 1
9364 12:13:37.363662 CPU_CLUSTER: 0: enabled 1
9365 12:13:37.367247 CPU: 00: enabled 1
9366 12:13:37.370114 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9367 12:13:37.373331 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9368 12:13:37.376784 ELOG: NV offset 0x57f000 size 0x1000
9369 12:13:37.383501 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9370 12:13:37.390108 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9371 12:13:37.393312 ELOG: Event(17) added with size 13 at 2024-01-31 12:13:00 UTC
9372 12:13:37.396295 out: cmd=0x121: 03 db 21 01 00 00 00 00
9373 12:13:37.400252 in-header: 03 1e 00 00 2c 00 00 00
9374 12:13:37.413921 in-data: 41 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9375 12:13:37.420356 ELOG: Event(A1) added with size 10 at 2024-01-31 12:13:00 UTC
9376 12:13:37.426871 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9377 12:13:37.433635 ELOG: Event(A0) added with size 9 at 2024-01-31 12:13:00 UTC
9378 12:13:37.437094 elog_add_boot_reason: Logged dev mode boot
9379 12:13:37.440768 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9380 12:13:37.443356 Finalize devices...
9381 12:13:37.443812 Devices finalized
9382 12:13:37.450312 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9383 12:13:37.453664 Writing coreboot table at 0xffe64000
9384 12:13:37.457097 0. 000000000010a000-0000000000113fff: RAMSTAGE
9385 12:13:37.460546 1. 0000000040000000-00000000400fffff: RAM
9386 12:13:37.463864 2. 0000000040100000-000000004032afff: RAMSTAGE
9387 12:13:37.470870 3. 000000004032b000-00000000545fffff: RAM
9388 12:13:37.473805 4. 0000000054600000-000000005465ffff: BL31
9389 12:13:37.477580 5. 0000000054660000-00000000ffe63fff: RAM
9390 12:13:37.480914 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9391 12:13:37.487164 7. 0000000100000000-000000023fffffff: RAM
9392 12:13:37.487621 Passing 5 GPIOs to payload:
9393 12:13:37.493860 NAME | PORT | POLARITY | VALUE
9394 12:13:37.496957 EC in RW | 0x000000aa | low | undefined
9395 12:13:37.500611 EC interrupt | 0x00000005 | low | undefined
9396 12:13:37.507196 TPM interrupt | 0x000000ab | high | undefined
9397 12:13:37.510424 SD card detect | 0x00000011 | high | undefined
9398 12:13:37.517049 speaker enable | 0x00000093 | high | undefined
9399 12:13:37.520339 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9400 12:13:37.523635 in-header: 03 f9 00 00 02 00 00 00
9401 12:13:37.524071 in-data: 02 00
9402 12:13:37.526936 ADC[4]: Raw value=900295 ID=7
9403 12:13:37.530207 ADC[3]: Raw value=213179 ID=1
9404 12:13:37.530642 RAM Code: 0x71
9405 12:13:37.533782 ADC[6]: Raw value=74502 ID=0
9406 12:13:37.536784 ADC[5]: Raw value=212441 ID=1
9407 12:13:37.537223 SKU Code: 0x1
9408 12:13:37.543502 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3f73
9409 12:13:37.546828 coreboot table: 964 bytes.
9410 12:13:37.550223 IMD ROOT 0. 0xfffff000 0x00001000
9411 12:13:37.553737 IMD SMALL 1. 0xffffe000 0x00001000
9412 12:13:37.556510 RO MCACHE 2. 0xffffc000 0x00001104
9413 12:13:37.560157 CONSOLE 3. 0xfff7c000 0x00080000
9414 12:13:37.563504 FMAP 4. 0xfff7b000 0x00000452
9415 12:13:37.566850 TIME STAMP 5. 0xfff7a000 0x00000910
9416 12:13:37.569804 VBOOT WORK 6. 0xfff66000 0x00014000
9417 12:13:37.573337 RAMOOPS 7. 0xffe66000 0x00100000
9418 12:13:37.577005 COREBOOT 8. 0xffe64000 0x00002000
9419 12:13:37.577442 IMD small region:
9420 12:13:37.580114 IMD ROOT 0. 0xffffec00 0x00000400
9421 12:13:37.583054 VPD 1. 0xffffeb80 0x0000006c
9422 12:13:37.586817 MMC STATUS 2. 0xffffeb60 0x00000004
9423 12:13:37.593747 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9424 12:13:37.594233 Probing TPM: done!
9425 12:13:37.600125 Connected to device vid:did:rid of 1ae0:0028:00
9426 12:13:37.607118 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9427 12:13:37.610321 Initialized TPM device CR50 revision 0
9428 12:13:37.614481 Checking cr50 for pending updates
9429 12:13:37.620004 Reading cr50 TPM mode
9430 12:13:37.628562 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9431 12:13:37.635330 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9432 12:13:37.675437 read SPI 0x3990ec 0x4f1b0: 34852 us, 9296 KB/s, 74.368 Mbps
9433 12:13:37.678469 Checking segment from ROM address 0x40100000
9434 12:13:37.682003 Checking segment from ROM address 0x4010001c
9435 12:13:37.688362 Loading segment from ROM address 0x40100000
9436 12:13:37.688788 code (compression=0)
9437 12:13:37.698379 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9438 12:13:37.705528 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9439 12:13:37.705988 it's not compressed!
9440 12:13:37.711922 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9441 12:13:37.715119 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9442 12:13:37.735701 Loading segment from ROM address 0x4010001c
9443 12:13:37.736127 Entry Point 0x80000000
9444 12:13:37.739299 Loaded segments
9445 12:13:37.742531 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9446 12:13:37.748921 Jumping to boot code at 0x80000000(0xffe64000)
9447 12:13:37.755618 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9448 12:13:37.762339 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9449 12:13:37.770044 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9450 12:13:37.773634 Checking segment from ROM address 0x40100000
9451 12:13:37.776664 Checking segment from ROM address 0x4010001c
9452 12:13:37.783718 Loading segment from ROM address 0x40100000
9453 12:13:37.784149 code (compression=1)
9454 12:13:37.789993 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9455 12:13:37.800398 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9456 12:13:37.801082 using LZMA
9457 12:13:37.808498 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9458 12:13:37.815161 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9459 12:13:37.818272 Loading segment from ROM address 0x4010001c
9460 12:13:37.818967 Entry Point 0x54601000
9461 12:13:37.821576 Loaded segments
9462 12:13:37.824944 NOTICE: MT8192 bl31_setup
9463 12:13:37.832123 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9464 12:13:37.835775 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9465 12:13:37.838934 WARNING: region 0:
9466 12:13:37.842124 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9467 12:13:37.842544 WARNING: region 1:
9468 12:13:37.848671 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9469 12:13:37.852116 WARNING: region 2:
9470 12:13:37.854967 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9471 12:13:37.858307 WARNING: region 3:
9472 12:13:37.861910 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9473 12:13:37.865345 WARNING: region 4:
9474 12:13:37.872165 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9475 12:13:37.872592 WARNING: region 5:
9476 12:13:37.875925 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 12:13:37.878734 WARNING: region 6:
9478 12:13:37.882277 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 12:13:37.882702 WARNING: region 7:
9480 12:13:37.888863 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 12:13:37.895405 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9482 12:13:37.899005 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9483 12:13:37.902345 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9484 12:13:37.908955 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9485 12:13:37.912195 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9486 12:13:37.915884 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9487 12:13:37.922268 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9488 12:13:37.925856 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9489 12:13:37.929257 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9490 12:13:37.936009 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9491 12:13:37.939355 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9492 12:13:37.942503 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9493 12:13:37.949278 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9494 12:13:37.952523 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9495 12:13:37.959095 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9496 12:13:37.962703 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9497 12:13:37.965789 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9498 12:13:37.972630 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9499 12:13:37.975929 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9500 12:13:37.979385 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9501 12:13:37.985764 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9502 12:13:37.988905 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9503 12:13:37.995778 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9504 12:13:37.998980 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9505 12:13:38.002371 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9506 12:13:38.008965 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9507 12:13:38.012692 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9508 12:13:38.016267 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9509 12:13:38.022929 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9510 12:13:38.026052 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9511 12:13:38.032714 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9512 12:13:38.036320 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9513 12:13:38.039348 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9514 12:13:38.046489 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9515 12:13:38.049564 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9516 12:13:38.052985 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9517 12:13:38.056226 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9518 12:13:38.062801 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9519 12:13:38.066228 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9520 12:13:38.069415 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9521 12:13:38.072886 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9522 12:13:38.076715 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9523 12:13:38.082668 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9524 12:13:38.086055 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9525 12:13:38.089638 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9526 12:13:38.096244 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9527 12:13:38.099752 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9528 12:13:38.102880 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9529 12:13:38.106300 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9530 12:13:38.112898 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9531 12:13:38.116455 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9532 12:13:38.122856 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9533 12:13:38.126522 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9534 12:13:38.132938 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9535 12:13:38.136400 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9536 12:13:38.139563 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9537 12:13:38.146338 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9538 12:13:38.149785 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9539 12:13:38.156312 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9540 12:13:38.159754 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9541 12:13:38.165913 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9542 12:13:38.169516 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9543 12:13:38.175997 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9544 12:13:38.179386 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9545 12:13:38.182771 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9546 12:13:38.189215 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9547 12:13:38.192677 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9548 12:13:38.199307 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9549 12:13:38.202667 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9550 12:13:38.205985 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9551 12:13:38.212616 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9552 12:13:38.216033 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9553 12:13:38.222745 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9554 12:13:38.226427 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9555 12:13:38.233004 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9556 12:13:38.236324 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9557 12:13:38.239914 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9558 12:13:38.246446 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9559 12:13:38.249782 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9560 12:13:38.256277 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9561 12:13:38.259536 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9562 12:13:38.266440 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9563 12:13:38.269930 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9564 12:13:38.273173 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9565 12:13:38.279898 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9566 12:13:38.283449 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9567 12:13:38.289931 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9568 12:13:38.293129 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9569 12:13:38.299850 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9570 12:13:38.303505 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9571 12:13:38.306509 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9572 12:13:38.313342 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9573 12:13:38.316581 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9574 12:13:38.323358 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9575 12:13:38.326572 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9576 12:13:38.333568 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9577 12:13:38.336578 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9578 12:13:38.340157 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9579 12:13:38.343016 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9580 12:13:38.350035 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9581 12:13:38.353327 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9582 12:13:38.356752 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9583 12:13:38.363081 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9584 12:13:38.366483 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9585 12:13:38.373473 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9586 12:13:38.376635 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9587 12:13:38.380293 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9588 12:13:38.386473 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9589 12:13:38.390541 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9590 12:13:38.393687 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9591 12:13:38.400142 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9592 12:13:38.403215 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9593 12:13:38.410044 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9594 12:13:38.413537 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9595 12:13:38.416729 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9596 12:13:38.423788 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9597 12:13:38.426974 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9598 12:13:38.429902 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9599 12:13:38.436905 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9600 12:13:38.440084 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9601 12:13:38.443756 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9602 12:13:38.447086 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9603 12:13:38.450367 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9604 12:13:38.456847 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9605 12:13:38.460417 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9606 12:13:38.466966 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9607 12:13:38.470477 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9608 12:13:38.473612 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9609 12:13:38.480573 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9610 12:13:38.484102 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9611 12:13:38.486845 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9612 12:13:38.493850 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9613 12:13:38.497206 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9614 12:13:38.503908 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9615 12:13:38.507324 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9616 12:13:38.510391 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9617 12:13:38.517129 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9618 12:13:38.520748 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9619 12:13:38.527452 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9620 12:13:38.530325 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9621 12:13:38.533526 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9622 12:13:38.540559 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9623 12:13:38.543850 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9624 12:13:38.550889 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9625 12:13:38.553529 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9626 12:13:38.557054 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9627 12:13:38.563450 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9628 12:13:38.566838 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9629 12:13:38.570035 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9630 12:13:38.576791 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9631 12:13:38.580458 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9632 12:13:38.586812 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9633 12:13:38.590306 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9634 12:13:38.593525 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9635 12:13:38.599871 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9636 12:13:38.603437 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9637 12:13:38.610278 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9638 12:13:38.613228 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9639 12:13:38.617107 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9640 12:13:38.623870 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9641 12:13:38.626369 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9642 12:13:38.633600 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9643 12:13:38.636814 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9644 12:13:38.639972 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9645 12:13:38.646526 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9646 12:13:38.649851 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9647 12:13:38.653207 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9648 12:13:38.660265 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9649 12:13:38.663578 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9650 12:13:38.669898 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9651 12:13:38.673402 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9652 12:13:38.676630 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9653 12:13:38.683203 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9654 12:13:38.686393 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9655 12:13:38.693148 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9656 12:13:38.696421 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9657 12:13:38.699591 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9658 12:13:38.706672 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9659 12:13:38.709730 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9660 12:13:38.716132 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9661 12:13:38.719449 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9662 12:13:38.722574 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9663 12:13:38.729829 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9664 12:13:38.732554 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9665 12:13:38.739326 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9666 12:13:38.742486 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9667 12:13:38.745989 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9668 12:13:38.752584 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9669 12:13:38.755889 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9670 12:13:38.762476 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9671 12:13:38.765600 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9672 12:13:38.769086 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9673 12:13:38.775984 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9674 12:13:38.779226 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9675 12:13:38.785801 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9676 12:13:38.789293 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9677 12:13:38.795782 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9678 12:13:38.799215 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9679 12:13:38.802509 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9680 12:13:38.808894 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9681 12:13:38.812286 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9682 12:13:38.818870 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9683 12:13:38.822623 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9684 12:13:38.825794 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9685 12:13:38.832202 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9686 12:13:38.835482 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9687 12:13:38.842343 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9688 12:13:38.845738 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9689 12:13:38.851932 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9690 12:13:38.855506 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9691 12:13:38.858464 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9692 12:13:38.865483 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9693 12:13:38.868783 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9694 12:13:38.875986 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9695 12:13:38.878683 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9696 12:13:38.882055 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9697 12:13:38.888610 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9698 12:13:38.892072 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9699 12:13:38.898435 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9700 12:13:38.902111 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9701 12:13:38.908552 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9702 12:13:38.912262 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9703 12:13:38.915278 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9704 12:13:38.921747 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9705 12:13:38.925228 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9706 12:13:38.931881 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9707 12:13:38.935144 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9708 12:13:38.938779 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9709 12:13:38.945236 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9710 12:13:38.948367 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9711 12:13:38.952063 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9712 12:13:38.955251 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9713 12:13:38.961772 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9714 12:13:38.964926 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9715 12:13:38.968142 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9716 12:13:38.974975 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9717 12:13:38.978324 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9718 12:13:38.984616 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9719 12:13:38.988155 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9720 12:13:38.991659 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9721 12:13:38.997920 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9722 12:13:39.001485 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9723 12:13:39.004679 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9724 12:13:39.011432 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9725 12:13:39.014557 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9726 12:13:39.017813 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9727 12:13:39.024280 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9728 12:13:39.027834 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9729 12:13:39.031318 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9730 12:13:39.037662 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9731 12:13:39.040943 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9732 12:13:39.047694 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9733 12:13:39.051241 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9734 12:13:39.054660 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9735 12:13:39.061206 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9736 12:13:39.064564 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9737 12:13:39.071053 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9738 12:13:39.074688 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9739 12:13:39.077663 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9740 12:13:39.084397 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9741 12:13:39.087633 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9742 12:13:39.090816 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9743 12:13:39.097494 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9744 12:13:39.100534 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9745 12:13:39.104145 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9746 12:13:39.110634 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9747 12:13:39.114054 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9748 12:13:39.120950 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9749 12:13:39.123992 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9750 12:13:39.127379 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9751 12:13:39.130555 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9752 12:13:39.133855 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9753 12:13:39.140823 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9754 12:13:39.143837 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9755 12:13:39.147418 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9756 12:13:39.150589 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9757 12:13:39.157496 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9758 12:13:39.160157 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9759 12:13:39.163697 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9760 12:13:39.167528 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9761 12:13:39.173536 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9762 12:13:39.176895 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9763 12:13:39.183826 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9764 12:13:39.187253 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9765 12:13:39.190362 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9766 12:13:39.196945 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9767 12:13:39.200461 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9768 12:13:39.206951 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9769 12:13:39.210249 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9770 12:13:39.213718 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9771 12:13:39.220027 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9772 12:13:39.223732 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9773 12:13:39.230046 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9774 12:13:39.233410 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9775 12:13:39.236889 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9776 12:13:39.244244 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9777 12:13:39.246820 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9778 12:13:39.253537 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9779 12:13:39.257118 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9780 12:13:39.260058 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9781 12:13:39.266796 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9782 12:13:39.270011 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9783 12:13:39.276629 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9784 12:13:39.280251 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9785 12:13:39.286865 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9786 12:13:39.290030 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9787 12:13:39.293585 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9788 12:13:39.299943 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9789 12:13:39.303295 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9790 12:13:39.309798 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9791 12:13:39.313420 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9792 12:13:39.316713 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9793 12:13:39.323178 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9794 12:13:39.326362 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9795 12:13:39.333328 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9796 12:13:39.336373 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9797 12:13:39.339523 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9798 12:13:39.346461 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9799 12:13:39.349609 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9800 12:13:39.356330 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9801 12:13:39.359553 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9802 12:13:39.362943 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9803 12:13:39.369658 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9804 12:13:39.372685 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9805 12:13:39.380007 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9806 12:13:39.382725 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9807 12:13:39.389342 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9808 12:13:39.392662 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9809 12:13:39.395801 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9810 12:13:39.402431 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9811 12:13:39.405480 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9812 12:13:39.412045 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9813 12:13:39.415666 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9814 12:13:39.419116 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9815 12:13:39.425391 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9816 12:13:39.428767 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9817 12:13:39.435408 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9818 12:13:39.439112 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9819 12:13:39.442550 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9820 12:13:39.449095 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9821 12:13:39.451985 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9822 12:13:39.458899 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9823 12:13:39.462035 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9824 12:13:39.468851 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9825 12:13:39.472238 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9826 12:13:39.475005 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9827 12:13:39.482061 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9828 12:13:39.484964 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9829 12:13:39.491685 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9830 12:13:39.495181 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9831 12:13:39.501443 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9832 12:13:39.504891 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9833 12:13:39.508398 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9834 12:13:39.515185 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9835 12:13:39.518368 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9836 12:13:39.525105 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9837 12:13:39.528264 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9838 12:13:39.531529 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9839 12:13:39.538459 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9840 12:13:39.541626 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9841 12:13:39.548122 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9842 12:13:39.551682 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9843 12:13:39.558062 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9844 12:13:39.561660 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9845 12:13:39.564611 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9846 12:13:39.571242 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9847 12:13:39.574883 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9848 12:13:39.581239 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9849 12:13:39.584667 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9850 12:13:39.591350 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9851 12:13:39.594631 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9852 12:13:39.597691 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9853 12:13:39.604620 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9854 12:13:39.607833 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9855 12:13:39.614784 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9856 12:13:39.617886 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9857 12:13:39.624533 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9858 12:13:39.627750 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9859 12:13:39.634683 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9860 12:13:39.637914 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9861 12:13:39.641612 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9862 12:13:39.647833 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9863 12:13:39.651169 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9864 12:13:39.657771 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9865 12:13:39.660927 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9866 12:13:39.667586 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9867 12:13:39.671108 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9868 12:13:39.674432 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9869 12:13:39.681174 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9870 12:13:39.684207 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9871 12:13:39.691012 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9872 12:13:39.694209 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9873 12:13:39.700874 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9874 12:13:39.704115 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9875 12:13:39.707702 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9876 12:13:39.714677 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9877 12:13:39.718189 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9878 12:13:39.724289 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9879 12:13:39.727496 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9880 12:13:39.734249 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9881 12:13:39.737779 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9882 12:13:39.740721 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9883 12:13:39.747384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9884 12:13:39.750600 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9885 12:13:39.757438 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9886 12:13:39.760795 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9887 12:13:39.767243 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9888 12:13:39.770518 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9889 12:13:39.777218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9890 12:13:39.780566 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9891 12:13:39.787300 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9892 12:13:39.790816 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9893 12:13:39.797356 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9894 12:13:39.800878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9895 12:13:39.804083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9896 12:13:39.810806 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9897 12:13:39.813875 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9898 12:13:39.820357 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9899 12:13:39.823842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9900 12:13:39.830254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9901 12:13:39.833837 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9902 12:13:39.840415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9903 12:13:39.843741 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9904 12:13:39.850509 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9905 12:13:39.853680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9906 12:13:39.860726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9907 12:13:39.863775 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9908 12:13:39.870410 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9909 12:13:39.873782 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9910 12:13:39.880447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9911 12:13:39.883869 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9912 12:13:39.890672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9913 12:13:39.893705 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9914 12:13:39.900426 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9915 12:13:39.903892 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9916 12:13:39.907008 INFO: [APUAPC] vio 0
9917 12:13:39.910349 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9918 12:13:39.917034 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9919 12:13:39.920460 INFO: [APUAPC] D0_APC_0: 0x400510
9920 12:13:39.920961 INFO: [APUAPC] D0_APC_1: 0x0
9921 12:13:39.923602 INFO: [APUAPC] D0_APC_2: 0x1540
9922 12:13:39.927022 INFO: [APUAPC] D0_APC_3: 0x0
9923 12:13:39.930038 INFO: [APUAPC] D1_APC_0: 0xffffffff
9924 12:13:39.933303 INFO: [APUAPC] D1_APC_1: 0xffffffff
9925 12:13:39.937044 INFO: [APUAPC] D1_APC_2: 0x3fffff
9926 12:13:39.940264 INFO: [APUAPC] D1_APC_3: 0x0
9927 12:13:39.943519 INFO: [APUAPC] D2_APC_0: 0xffffffff
9928 12:13:39.946817 INFO: [APUAPC] D2_APC_1: 0xffffffff
9929 12:13:39.950012 INFO: [APUAPC] D2_APC_2: 0x3fffff
9930 12:13:39.953488 INFO: [APUAPC] D2_APC_3: 0x0
9931 12:13:39.956574 INFO: [APUAPC] D3_APC_0: 0xffffffff
9932 12:13:39.959827 INFO: [APUAPC] D3_APC_1: 0xffffffff
9933 12:13:39.963530 INFO: [APUAPC] D3_APC_2: 0x3fffff
9934 12:13:39.966674 INFO: [APUAPC] D3_APC_3: 0x0
9935 12:13:39.970082 INFO: [APUAPC] D4_APC_0: 0xffffffff
9936 12:13:39.973110 INFO: [APUAPC] D4_APC_1: 0xffffffff
9937 12:13:39.976632 INFO: [APUAPC] D4_APC_2: 0x3fffff
9938 12:13:39.979634 INFO: [APUAPC] D4_APC_3: 0x0
9939 12:13:39.983025 INFO: [APUAPC] D5_APC_0: 0xffffffff
9940 12:13:39.986473 INFO: [APUAPC] D5_APC_1: 0xffffffff
9941 12:13:39.989900 INFO: [APUAPC] D5_APC_2: 0x3fffff
9942 12:13:39.993024 INFO: [APUAPC] D5_APC_3: 0x0
9943 12:13:39.996355 INFO: [APUAPC] D6_APC_0: 0xffffffff
9944 12:13:39.999795 INFO: [APUAPC] D6_APC_1: 0xffffffff
9945 12:13:40.002846 INFO: [APUAPC] D6_APC_2: 0x3fffff
9946 12:13:40.006168 INFO: [APUAPC] D6_APC_3: 0x0
9947 12:13:40.009901 INFO: [APUAPC] D7_APC_0: 0xffffffff
9948 12:13:40.012862 INFO: [APUAPC] D7_APC_1: 0xffffffff
9949 12:13:40.016223 INFO: [APUAPC] D7_APC_2: 0x3fffff
9950 12:13:40.019716 INFO: [APUAPC] D7_APC_3: 0x0
9951 12:13:40.022797 INFO: [APUAPC] D8_APC_0: 0xffffffff
9952 12:13:40.025905 INFO: [APUAPC] D8_APC_1: 0xffffffff
9953 12:13:40.029104 INFO: [APUAPC] D8_APC_2: 0x3fffff
9954 12:13:40.032697 INFO: [APUAPC] D8_APC_3: 0x0
9955 12:13:40.035766 INFO: [APUAPC] D9_APC_0: 0xffffffff
9956 12:13:40.039292 INFO: [APUAPC] D9_APC_1: 0xffffffff
9957 12:13:40.042603 INFO: [APUAPC] D9_APC_2: 0x3fffff
9958 12:13:40.045859 INFO: [APUAPC] D9_APC_3: 0x0
9959 12:13:40.049211 INFO: [APUAPC] D10_APC_0: 0xffffffff
9960 12:13:40.052365 INFO: [APUAPC] D10_APC_1: 0xffffffff
9961 12:13:40.056270 INFO: [APUAPC] D10_APC_2: 0x3fffff
9962 12:13:40.058998 INFO: [APUAPC] D10_APC_3: 0x0
9963 12:13:40.062420 INFO: [APUAPC] D11_APC_0: 0xffffffff
9964 12:13:40.065374 INFO: [APUAPC] D11_APC_1: 0xffffffff
9965 12:13:40.068773 INFO: [APUAPC] D11_APC_2: 0x3fffff
9966 12:13:40.072561 INFO: [APUAPC] D11_APC_3: 0x0
9967 12:13:40.076027 INFO: [APUAPC] D12_APC_0: 0xffffffff
9968 12:13:40.079867 INFO: [APUAPC] D12_APC_1: 0xffffffff
9969 12:13:40.082504 INFO: [APUAPC] D12_APC_2: 0x3fffff
9970 12:13:40.085997 INFO: [APUAPC] D12_APC_3: 0x0
9971 12:13:40.088798 INFO: [APUAPC] D13_APC_0: 0xffffffff
9972 12:13:40.091939 INFO: [APUAPC] D13_APC_1: 0xffffffff
9973 12:13:40.095672 INFO: [APUAPC] D13_APC_2: 0x3fffff
9974 12:13:40.098809 INFO: [APUAPC] D13_APC_3: 0x0
9975 12:13:40.102091 INFO: [APUAPC] D14_APC_0: 0xffffffff
9976 12:13:40.105195 INFO: [APUAPC] D14_APC_1: 0xffffffff
9977 12:13:40.108687 INFO: [APUAPC] D14_APC_2: 0x3fffff
9978 12:13:40.111930 INFO: [APUAPC] D14_APC_3: 0x0
9979 12:13:40.115523 INFO: [APUAPC] D15_APC_0: 0xffffffff
9980 12:13:40.118631 INFO: [APUAPC] D15_APC_1: 0xffffffff
9981 12:13:40.121848 INFO: [APUAPC] D15_APC_2: 0x3fffff
9982 12:13:40.125089 INFO: [APUAPC] D15_APC_3: 0x0
9983 12:13:40.128538 INFO: [APUAPC] APC_CON: 0x4
9984 12:13:40.131580 INFO: [NOCDAPC] D0_APC_0: 0x0
9985 12:13:40.134991 INFO: [NOCDAPC] D0_APC_1: 0x0
9986 12:13:40.135412 INFO: [NOCDAPC] D1_APC_0: 0x0
9987 12:13:40.138488 INFO: [NOCDAPC] D1_APC_1: 0xfff
9988 12:13:40.142090 INFO: [NOCDAPC] D2_APC_0: 0x0
9989 12:13:40.145166 INFO: [NOCDAPC] D2_APC_1: 0xfff
9990 12:13:40.148368 INFO: [NOCDAPC] D3_APC_0: 0x0
9991 12:13:40.152172 INFO: [NOCDAPC] D3_APC_1: 0xfff
9992 12:13:40.155064 INFO: [NOCDAPC] D4_APC_0: 0x0
9993 12:13:40.158576 INFO: [NOCDAPC] D4_APC_1: 0xfff
9994 12:13:40.161888 INFO: [NOCDAPC] D5_APC_0: 0x0
9995 12:13:40.164940 INFO: [NOCDAPC] D5_APC_1: 0xfff
9996 12:13:40.165345 INFO: [NOCDAPC] D6_APC_0: 0x0
9997 12:13:40.168460 INFO: [NOCDAPC] D6_APC_1: 0xfff
9998 12:13:40.171904 INFO: [NOCDAPC] D7_APC_0: 0x0
9999 12:13:40.175254 INFO: [NOCDAPC] D7_APC_1: 0xfff
10000 12:13:40.178443 INFO: [NOCDAPC] D8_APC_0: 0x0
10001 12:13:40.181610 INFO: [NOCDAPC] D8_APC_1: 0xfff
10002 12:13:40.185196 INFO: [NOCDAPC] D9_APC_0: 0x0
10003 12:13:40.188520 INFO: [NOCDAPC] D9_APC_1: 0xfff
10004 12:13:40.191629 INFO: [NOCDAPC] D10_APC_0: 0x0
10005 12:13:40.194970 INFO: [NOCDAPC] D10_APC_1: 0xfff
10006 12:13:40.198533 INFO: [NOCDAPC] D11_APC_0: 0x0
10007 12:13:40.201398 INFO: [NOCDAPC] D11_APC_1: 0xfff
10008 12:13:40.204757 INFO: [NOCDAPC] D12_APC_0: 0x0
10009 12:13:40.205251 INFO: [NOCDAPC] D12_APC_1: 0xfff
10010 12:13:40.207979 INFO: [NOCDAPC] D13_APC_0: 0x0
10011 12:13:40.211434 INFO: [NOCDAPC] D13_APC_1: 0xfff
10012 12:13:40.215175 INFO: [NOCDAPC] D14_APC_0: 0x0
10013 12:13:40.218254 INFO: [NOCDAPC] D14_APC_1: 0xfff
10014 12:13:40.221645 INFO: [NOCDAPC] D15_APC_0: 0x0
10015 12:13:40.224521 INFO: [NOCDAPC] D15_APC_1: 0xfff
10016 12:13:40.228154 INFO: [NOCDAPC] APC_CON: 0x4
10017 12:13:40.231723 INFO: [APUAPC] set_apusys_apc done
10018 12:13:40.235342 INFO: [DEVAPC] devapc_init done
10019 12:13:40.238149 INFO: GICv3 without legacy support detected.
10020 12:13:40.241140 INFO: ARM GICv3 driver initialized in EL3
10021 12:13:40.244613 INFO: Maximum SPI INTID supported: 639
10022 12:13:40.251472 INFO: BL31: Initializing runtime services
10023 12:13:40.254511 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10024 12:13:40.257766 INFO: SPM: enable CPC mode
10025 12:13:40.264764 INFO: mcdi ready for mcusys-off-idle and system suspend
10026 12:13:40.267948 INFO: BL31: Preparing for EL3 exit to normal world
10027 12:13:40.271326 INFO: Entry point address = 0x80000000
10028 12:13:40.274817 INFO: SPSR = 0x8
10029 12:13:40.280264
10030 12:13:40.280821
10031 12:13:40.281300
10032 12:13:40.283407 Starting depthcharge on Spherion...
10033 12:13:40.284003
10034 12:13:40.284519 Wipe memory regions:
10035 12:13:40.285001
10036 12:13:40.287342 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10037 12:13:40.287877 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10038 12:13:40.288304 Setting prompt string to ['asurada:']
10039 12:13:40.288708 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10040 12:13:40.289361 [0x00000040000000, 0x00000054600000)
10041 12:13:40.408864
10042 12:13:40.409495 [0x00000054660000, 0x00000080000000)
10043 12:13:40.669880
10044 12:13:40.670423 [0x000000821a7280, 0x000000ffe64000)
10045 12:13:41.414683
10046 12:13:41.415276 [0x00000100000000, 0x00000240000000)
10047 12:13:43.305081
10048 12:13:43.308276 Initializing XHCI USB controller at 0x11200000.
10049 12:13:44.346158
10050 12:13:44.349786 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10051 12:13:44.350300
10052 12:13:44.350686
10053 12:13:44.351057
10054 12:13:44.351911 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10056 12:13:44.453089 asurada: tftpboot 192.168.201.1 12669505/tftp-deploy-kbhi3sxt/kernel/image.itb 12669505/tftp-deploy-kbhi3sxt/kernel/cmdline
10057 12:13:44.453805 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10058 12:13:44.454564 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10059 12:13:44.458934 tftpboot 192.168.201.1 12669505/tftp-deploy-kbhi3sxt/kernel/image.itp-deploy-kbhi3sxt/kernel/cmdline
10060 12:13:44.459421
10061 12:13:44.459899 Waiting for link
10062 12:13:44.619511
10063 12:13:44.619990 R8152: Initializing
10064 12:13:44.620332
10065 12:13:44.622563 Version 9 (ocp_data = 6010)
10066 12:13:44.623165
10067 12:13:44.625742 R8152: Done initializing
10068 12:13:44.626296
10069 12:13:44.626768 Adding net device
10070 12:13:46.567665
10071 12:13:46.568375 done.
10072 12:13:46.568828
10073 12:13:46.569266 MAC: 00:e0:4c:72:2d:d6
10074 12:13:46.569684
10075 12:13:46.571332 Sending DHCP discover... done.
10076 12:13:46.571859
10077 12:13:57.041393 Waiting for reply... R8152: Bulk read error 0xffffffbf
10078 12:13:57.042203
10079 12:13:57.044806 Receive failed.
10080 12:13:57.045434
10081 12:13:57.046044 done.
10082 12:13:57.046417
10083 12:13:57.047813 Sending DHCP request... done.
10084 12:13:57.048276
10085 12:13:57.054721 Waiting for reply... done.
10086 12:13:57.055284
10087 12:13:57.055650 My ip is 192.168.201.21
10088 12:13:57.055989
10089 12:13:57.058094 The DHCP server ip is 192.168.201.1
10090 12:13:57.058564
10091 12:13:57.065244 TFTP server IP predefined by user: 192.168.201.1
10092 12:13:57.065811
10093 12:13:57.071195 Bootfile predefined by user: 12669505/tftp-deploy-kbhi3sxt/kernel/image.itb
10094 12:13:57.071758
10095 12:13:57.072123 Sending tftp read request... done.
10096 12:13:57.074590
10097 12:13:57.078933 Waiting for the transfer...
10098 12:13:57.079439
10099 12:13:57.371626 00000000 ################################################################
10100 12:13:57.371761
10101 12:13:57.620694 00080000 ################################################################
10102 12:13:57.620818
10103 12:13:57.879121 00100000 ################################################################
10104 12:13:57.879254
10105 12:13:58.132620 00180000 ################################################################
10106 12:13:58.132760
10107 12:13:58.383534 00200000 ################################################################
10108 12:13:58.383664
10109 12:13:58.673902 00280000 ################################################################
10110 12:13:58.674039
10111 12:13:58.945192 00300000 ################################################################
10112 12:13:58.945323
10113 12:13:59.194661 00380000 ################################################################
10114 12:13:59.194804
10115 12:13:59.456708 00400000 ################################################################
10116 12:13:59.456853
10117 12:13:59.706181 00480000 ################################################################
10118 12:13:59.706377
10119 12:13:59.953947 00500000 ################################################################
10120 12:13:59.954132
10121 12:14:00.205181 00580000 ################################################################
10122 12:14:00.205313
10123 12:14:00.454984 00600000 ################################################################
10124 12:14:00.455112
10125 12:14:00.705851 00680000 ################################################################
10126 12:14:00.706032
10127 12:14:00.960792 00700000 ################################################################
10128 12:14:00.960926
10129 12:14:01.209009 00780000 ################################################################
10130 12:14:01.209142
10131 12:14:01.458151 00800000 ################################################################
10132 12:14:01.458276
10133 12:14:01.706914 00880000 ################################################################
10134 12:14:01.707045
10135 12:14:01.955702 00900000 ################################################################
10136 12:14:01.955827
10137 12:14:02.203877 00980000 ################################################################
10138 12:14:02.204008
10139 12:14:02.452564 00a00000 ################################################################
10140 12:14:02.452698
10141 12:14:02.701427 00a80000 ################################################################
10142 12:14:02.701550
10143 12:14:02.950185 00b00000 ################################################################
10144 12:14:02.950312
10145 12:14:03.198226 00b80000 ################################################################
10146 12:14:03.198349
10147 12:14:03.447160 00c00000 ################################################################
10148 12:14:03.447290
10149 12:14:03.696523 00c80000 ################################################################
10150 12:14:03.696649
10151 12:14:03.945960 00d00000 ################################################################
10152 12:14:03.946082
10153 12:14:04.196231 00d80000 ################################################################
10154 12:14:04.196362
10155 12:14:04.444937 00e00000 ################################################################
10156 12:14:04.445057
10157 12:14:04.693568 00e80000 ################################################################
10158 12:14:04.693691
10159 12:14:04.943074 00f00000 ################################################################
10160 12:14:04.943202
10161 12:14:05.192218 00f80000 ################################################################
10162 12:14:05.192357
10163 12:14:05.441221 01000000 ################################################################
10164 12:14:05.441350
10165 12:14:05.690047 01080000 ################################################################
10166 12:14:05.690171
10167 12:14:05.939135 01100000 ################################################################
10168 12:14:05.939261
10169 12:14:06.187774 01180000 ################################################################
10170 12:14:06.187908
10171 12:14:06.472737 01200000 ################################################################
10172 12:14:06.472860
10173 12:14:06.769844 01280000 ################################################################
10174 12:14:06.770006
10175 12:14:07.026757 01300000 ################################################################
10176 12:14:07.026885
10177 12:14:07.275974 01380000 ################################################################
10178 12:14:07.276099
10179 12:14:07.524855 01400000 ################################################################
10180 12:14:07.524987
10181 12:14:07.774680 01480000 ################################################################
10182 12:14:07.774809
10183 12:14:08.023548 01500000 ################################################################
10184 12:14:08.023676
10185 12:14:08.278279 01580000 ################################################################
10186 12:14:08.278408
10187 12:14:08.531871 01600000 ################################################################
10188 12:14:08.532022
10189 12:14:08.781081 01680000 ################################################################
10190 12:14:08.781234
10191 12:14:09.029461 01700000 ################################################################
10192 12:14:09.029613
10193 12:14:09.277518 01780000 ################################################################
10194 12:14:09.277675
10195 12:14:09.528658 01800000 ################################################################
10196 12:14:09.528810
10197 12:14:09.778901 01880000 ################################################################
10198 12:14:09.779052
10199 12:14:10.027831 01900000 ################################################################
10200 12:14:10.027956
10201 12:14:10.277077 01980000 ################################################################
10202 12:14:10.277207
10203 12:14:10.533177 01a00000 ################################################################
10204 12:14:10.533352
10205 12:14:10.782763 01a80000 ################################################################
10206 12:14:10.782913
10207 12:14:11.032842 01b00000 ################################################################
10208 12:14:11.032979
10209 12:14:11.281356 01b80000 ################################################################
10210 12:14:11.281507
10211 12:14:11.530991 01c00000 ################################################################
10212 12:14:11.531129
10213 12:14:11.779409 01c80000 ################################################################
10214 12:14:11.779535
10215 12:14:12.027045 01d00000 ################################################################
10216 12:14:12.027172
10217 12:14:12.275808 01d80000 ################################################################
10218 12:14:12.275956
10219 12:14:12.524546 01e00000 ################################################################
10220 12:14:12.524709
10221 12:14:12.774422 01e80000 ################################################################
10222 12:14:12.774558
10223 12:14:13.023749 01f00000 ################################################################
10224 12:14:13.023904
10225 12:14:13.273475 01f80000 ################################################################
10226 12:14:13.273629
10227 12:14:13.526387 02000000 ################################################################
10228 12:14:13.526535
10229 12:14:13.775521 02080000 ################################################################
10230 12:14:13.775678
10231 12:14:14.024815 02100000 ################################################################
10232 12:14:14.024969
10233 12:14:14.275483 02180000 ################################################################
10234 12:14:14.275658
10235 12:14:14.523146 02200000 ################################################################
10236 12:14:14.523318
10237 12:14:14.772344 02280000 ################################################################
10238 12:14:14.772486
10239 12:14:15.021458 02300000 ################################################################
10240 12:14:15.021597
10241 12:14:15.270859 02380000 ################################################################
10242 12:14:15.270998
10243 12:14:15.519541 02400000 ################################################################
10244 12:14:15.519707
10245 12:14:15.778428 02480000 ################################################################
10246 12:14:15.778594
10247 12:14:16.028241 02500000 ################################################################
10248 12:14:16.028406
10249 12:14:16.277909 02580000 ################################################################
10250 12:14:16.278061
10251 12:14:16.531448 02600000 ################################################################
10252 12:14:16.531617
10253 12:14:16.786089 02680000 ################################################################
10254 12:14:16.786233
10255 12:14:17.040369 02700000 ################################################################
10256 12:14:17.040510
10257 12:14:17.288779 02780000 ################################################################
10258 12:14:17.288929
10259 12:14:17.544321 02800000 ################################################################
10260 12:14:17.544462
10261 12:14:18.783871 02880000 ################################################################
10262 12:14:18.784111
10263 12:14:18.784249 02900000 ################################################################
10264 12:14:18.784431
10265 12:14:18.784541 02980000 ################################################################
10266 12:14:18.784663
10267 12:14:18.784771 02a00000 ################################################################
10268 12:14:18.784893
10269 12:14:18.788567 02a80000 ################################################################
10270 12:14:18.788682
10271 12:14:19.052626 02b00000 ################################################################
10272 12:14:19.052792
10273 12:14:19.311442 02b80000 ################################################################
10274 12:14:19.311582
10275 12:14:19.574170 02c00000 ################################################################
10276 12:14:19.574306
10277 12:14:19.826458 02c80000 ################################################################
10278 12:14:19.826622
10279 12:14:20.083316 02d00000 ################################################################
10280 12:14:20.083455
10281 12:14:20.336761 02d80000 ################################################################
10282 12:14:20.336922
10283 12:14:20.590507 02e00000 ################################################################
10284 12:14:20.590684
10285 12:14:20.870758 02e80000 ################################################################
10286 12:14:20.870905
10287 12:14:21.152994 02f00000 ################################################################
10288 12:14:21.153144
10289 12:14:21.411802 02f80000 ################################################################
10290 12:14:21.411963
10291 12:14:21.671241 03000000 ################################################################
10292 12:14:21.671416
10293 12:14:21.928549 03080000 ################################################################
10294 12:14:21.928685
10295 12:14:22.191514 03100000 ################################################################
10296 12:14:22.191662
10297 12:14:22.479245 03180000 ################################################################
10298 12:14:22.479398
10299 12:14:22.778611 03200000 ################################################################
10300 12:14:22.778769
10301 12:14:23.076200 03280000 ################################################################
10302 12:14:23.076358
10303 12:14:23.356110 03300000 ################################################################
10304 12:14:23.356271
10305 12:14:23.635703 03380000 ################################################################
10306 12:14:23.635858
10307 12:14:23.933329 03400000 ################################################################
10308 12:14:23.933480
10309 12:14:24.232681 03480000 ################################################################
10310 12:14:24.232839
10311 12:14:24.529959 03500000 ################################################################
10312 12:14:24.530115
10313 12:14:24.827713 03580000 ################################################################
10314 12:14:24.827869
10315 12:14:25.125684 03600000 ################################################################
10316 12:14:25.125847
10317 12:14:25.417892 03680000 ################################################################
10318 12:14:25.418055
10319 12:14:25.713769 03700000 ################################################################
10320 12:14:25.713949
10321 12:14:26.014093 03780000 ################################################################
10322 12:14:26.014253
10323 12:14:26.315826 03800000 ################################################################
10324 12:14:26.315986
10325 12:14:26.610352 03880000 ################################################################
10326 12:14:26.610510
10327 12:14:26.911567 03900000 ################################################################
10328 12:14:26.911721
10329 12:14:27.210829 03980000 ################################################################
10330 12:14:27.210983
10331 12:14:27.492475 03a00000 ################################################################
10332 12:14:27.492635
10333 12:14:27.791015 03a80000 ################################################################
10334 12:14:27.791174
10335 12:14:28.087171 03b00000 ################################################################
10336 12:14:28.087325
10337 12:14:28.389718 03b80000 ################################################################
10338 12:14:28.389870
10339 12:14:28.691477 03c00000 ################################################################
10340 12:14:28.691629
10341 12:14:28.981343 03c80000 ################################################################
10342 12:14:28.981495
10343 12:14:29.278680 03d00000 ################################################################
10344 12:14:29.278833
10345 12:14:29.559573 03d80000 ################################################################
10346 12:14:29.559722
10347 12:14:29.822523 03e00000 ################################################################
10348 12:14:29.822689
10349 12:14:30.110953 03e80000 ################################################################
10350 12:14:30.111105
10351 12:14:30.395973 03f00000 ################################################################
10352 12:14:30.396153
10353 12:14:30.693929 03f80000 ################################################################
10354 12:14:30.694086
10355 12:14:30.990255 04000000 ################################################################
10356 12:14:30.990405
10357 12:14:31.289260 04080000 ################################################################
10358 12:14:31.289437
10359 12:14:31.588042 04100000 ################################################################
10360 12:14:31.588203
10361 12:14:31.883683 04180000 ################################################################
10362 12:14:31.883834
10363 12:14:32.174924 04200000 ################################################################
10364 12:14:32.175082
10365 12:14:32.477575 04280000 ################################################################
10366 12:14:32.477721
10367 12:14:32.760562 04300000 ################################################################
10368 12:14:32.760736
10369 12:14:33.049782 04380000 ################################################################
10370 12:14:33.049933
10371 12:14:33.348780 04400000 ################################################################
10372 12:14:33.348950
10373 12:14:33.650360 04480000 ################################################################
10374 12:14:33.650512
10375 12:14:33.942543 04500000 ################################################################
10376 12:14:33.942695
10377 12:14:34.225458 04580000 ################################################################
10378 12:14:34.225610
10379 12:14:34.508987 04600000 ################################################################
10380 12:14:34.509138
10381 12:14:34.790838 04680000 ################################################################
10382 12:14:34.790975
10383 12:14:35.049201 04700000 ################################################################
10384 12:14:35.049352
10385 12:14:35.308644 04780000 ################################################################
10386 12:14:35.308795
10387 12:14:35.562223 04800000 ################################################################
10388 12:14:35.562367
10389 12:14:35.843755 04880000 ################################################################
10390 12:14:35.843891
10391 12:14:36.132278 04900000 ################################################################
10392 12:14:36.132411
10393 12:14:36.427312 04980000 ################################################################
10394 12:14:36.427435
10395 12:14:36.685408 04a00000 ################################################################
10396 12:14:36.685531
10397 12:14:36.955995 04a80000 ################################################################
10398 12:14:36.956128
10399 12:14:37.204895 04b00000 ################################################################
10400 12:14:37.205026
10401 12:14:37.453067 04b80000 ################################################################
10402 12:14:37.453187
10403 12:14:37.731119 04c00000 ################################################################
10404 12:14:37.731265
10405 12:14:38.013917 04c80000 ################################################################
10406 12:14:38.014067
10407 12:14:38.297395 04d00000 ################################################################
10408 12:14:38.297538
10409 12:14:38.581255 04d80000 ################################################################
10410 12:14:38.581385
10411 12:14:38.867827 04e00000 ################################################################
10412 12:14:38.867955
10413 12:14:39.149821 04e80000 ################################################################
10414 12:14:39.150021
10415 12:14:39.415670 04f00000 ################################################################
10416 12:14:39.415806
10417 12:14:39.664460 04f80000 ################################################################
10418 12:14:39.664585
10419 12:14:39.912714 05000000 ################################################################
10420 12:14:39.912835
10421 12:14:40.161802 05080000 ################################################################
10422 12:14:40.161934
10423 12:14:40.418201 05100000 ################################################################
10424 12:14:40.418334
10425 12:14:40.667934 05180000 ################################################################
10426 12:14:40.668069
10427 12:14:40.916978 05200000 ################################################################
10428 12:14:40.917118
10429 12:14:41.166109 05280000 ################################################################
10430 12:14:41.166244
10431 12:14:41.415935 05300000 ################################################################
10432 12:14:41.416065
10433 12:14:41.664675 05380000 ################################################################
10434 12:14:41.664802
10435 12:14:41.915095 05400000 ################################################################
10436 12:14:41.915253
10437 12:14:42.178075 05480000 ################################################################
10438 12:14:42.178235
10439 12:14:42.433209 05500000 ################################################################
10440 12:14:42.433360
10441 12:14:42.698140 05580000 ################################################################
10442 12:14:42.698299
10443 12:14:42.946945 05600000 ################################################################
10444 12:14:42.947097
10445 12:14:43.196075 05680000 ################################################################
10446 12:14:43.196233
10447 12:14:43.461706 05700000 ################################################################
10448 12:14:43.461857
10449 12:14:43.720637 05780000 ################################################################
10450 12:14:43.720760
10451 12:14:43.974042 05800000 ################################################################
10452 12:14:43.974169
10453 12:14:44.222916 05880000 ################################################################
10454 12:14:44.223043
10455 12:14:44.472247 05900000 ################################################################
10456 12:14:44.472407
10457 12:14:44.721355 05980000 ################################################################
10458 12:14:44.721504
10459 12:14:44.970679 05a00000 ################################################################
10460 12:14:44.970840
10461 12:14:45.229326 05a80000 ################################################################
10462 12:14:45.229455
10463 12:14:45.481562 05b00000 ################################################################
10464 12:14:45.481699
10465 12:14:45.739551 05b80000 ################################################################
10466 12:14:45.739676
10467 12:14:45.988633 05c00000 ################################################################
10468 12:14:45.988763
10469 12:14:46.237038 05c80000 ################################################################
10470 12:14:46.237161
10471 12:14:46.485599 05d00000 ################################################################
10472 12:14:46.485725
10473 12:14:46.734640 05d80000 ################################################################
10474 12:14:46.734766
10475 12:14:46.983919 05e00000 ################################################################
10476 12:14:46.984042
10477 12:14:47.233004 05e80000 ################################################################
10478 12:14:47.233127
10479 12:14:47.482191 05f00000 ################################################################
10480 12:14:47.482329
10481 12:14:47.730931 05f80000 ################################################################
10482 12:14:47.731059
10483 12:14:47.977421 06000000 ################################################################
10484 12:14:47.977569
10485 12:14:48.217574 06080000 ################################################################
10486 12:14:48.217722
10487 12:14:48.466848 06100000 ################################################################
10488 12:14:48.467000
10489 12:14:48.750449 06180000 ################################################################
10490 12:14:48.750584
10491 12:14:49.040944 06200000 ################################################################
10492 12:14:49.041071
10493 12:14:49.322053 06280000 ################################################################
10494 12:14:49.322216
10495 12:14:49.600625 06300000 ################################################################
10496 12:14:49.600756
10497 12:14:49.879885 06380000 ################################################################
10498 12:14:49.880035
10499 12:14:50.176428 06400000 ################################################################
10500 12:14:50.176580
10501 12:14:50.457866 06480000 ################################################################
10502 12:14:50.458032
10503 12:14:50.737010 06500000 ################################################################
10504 12:14:50.737162
10505 12:14:51.016194 06580000 ################################################################
10506 12:14:51.016343
10507 12:14:51.296532 06600000 ################################################################
10508 12:14:51.296698
10509 12:14:51.552017 06680000 ################################################################
10510 12:14:51.552182
10511 12:14:51.801387 06700000 ################################################################
10512 12:14:51.801551
10513 12:14:52.086663 06780000 ################################################################
10514 12:14:52.086818
10515 12:14:52.335580 06800000 ################################################################
10516 12:14:52.335710
10517 12:14:52.585680 06880000 ################################################################
10518 12:14:52.585845
10519 12:14:52.760001 06900000 ############################################# done.
10520 12:14:52.760128
10521 12:14:52.763033 The bootfile was 110467298 bytes long.
10522 12:14:52.763124
10523 12:14:52.766080 Sending tftp read request... done.
10524 12:14:52.766176
10525 12:14:52.766252 Waiting for the transfer...
10526 12:14:52.766322
10527 12:14:52.769242 00000000 # done.
10528 12:14:52.769340
10529 12:14:52.776606 Command line loaded dynamically from TFTP file: 12669505/tftp-deploy-kbhi3sxt/kernel/cmdline
10530 12:14:52.776804
10531 12:14:52.789437 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10532 12:14:52.789663
10533 12:14:52.793048 Loading FIT.
10534 12:14:52.793289
10535 12:14:52.796239 Image ramdisk-1 has 98370703 bytes.
10536 12:14:52.796519
10537 12:14:52.796677 Image fdt-1 has 47278 bytes.
10538 12:14:52.796819
10539 12:14:52.799313 Image kernel-1 has 12047284 bytes.
10540 12:14:52.799492
10541 12:14:52.809486 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10542 12:14:52.809831
10543 12:14:52.826261 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10544 12:14:52.826853
10545 12:14:52.832743 Choosing best match conf-1 for compat google,spherion-rev2.
10546 12:14:52.836625
10547 12:14:52.841522 Connected to device vid:did:rid of 1ae0:0028:00
10548 12:14:52.849559
10549 12:14:52.852981 tpm_get_response: command 0x17b, return code 0x0
10550 12:14:52.853580
10551 12:14:52.855853 ec_init: CrosEC protocol v3 supported (256, 248)
10552 12:14:52.860280
10553 12:14:52.863299 tpm_cleanup: add release locality here.
10554 12:14:52.863777
10555 12:14:52.864156 Shutting down all USB controllers.
10556 12:14:52.866533
10557 12:14:52.867056 Removing current net device
10558 12:14:52.867440
10559 12:14:52.873552 Exiting depthcharge with code 4 at timestamp: 101907868
10560 12:14:52.874178
10561 12:14:52.876456 LZMA decompressing kernel-1 to 0x821a6718
10562 12:14:52.876933
10563 12:14:52.880037 LZMA decompressing kernel-1 to 0x40000000
10564 12:14:54.379447
10565 12:14:54.379593 jumping to kernel
10566 12:14:54.380147 end: 2.2.4 bootloader-commands (duration 00:01:14) [common]
10567 12:14:54.380248 start: 2.2.5 auto-login-action (timeout 00:03:11) [common]
10568 12:14:54.380329 Setting prompt string to ['Linux version [0-9]']
10569 12:14:54.380399 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10570 12:14:54.380471 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10571 12:14:54.461212
10572 12:14:54.464947 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10573 12:14:54.467910 start: 2.2.5.1 login-action (timeout 00:03:11) [common]
10574 12:14:54.468008 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10575 12:14:54.468102 Setting prompt string to []
10576 12:14:54.468214 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10577 12:14:54.468312 Using line separator: #'\n'#
10578 12:14:54.468376 No login prompt set.
10579 12:14:54.468442 Parsing kernel messages
10580 12:14:54.468500 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10581 12:14:54.468607 [login-action] Waiting for messages, (timeout 00:03:11)
10582 12:14:54.487634 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j93261-arm64-gcc-10-defconfig-arm64-chromebook-cwjwh) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024
10583 12:14:54.490927 [ 0.000000] random: crng init done
10584 12:14:54.497322 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10585 12:14:54.500668 [ 0.000000] efi: UEFI not found.
10586 12:14:54.507542 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10587 12:14:54.514119 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10588 12:14:54.523650 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10589 12:14:54.533801 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10590 12:14:54.540542 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10591 12:14:54.547176 [ 0.000000] printk: bootconsole [mtk8250] enabled
10592 12:14:54.553787 [ 0.000000] NUMA: No NUMA configuration found
10593 12:14:54.560244 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10594 12:14:54.563466 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10595 12:14:54.566989 [ 0.000000] Zone ranges:
10596 12:14:54.573464 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10597 12:14:54.576608 [ 0.000000] DMA32 empty
10598 12:14:54.583512 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10599 12:14:54.586677 [ 0.000000] Movable zone start for each node
10600 12:14:54.590467 [ 0.000000] Early memory node ranges
10601 12:14:54.596654 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10602 12:14:54.603232 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10603 12:14:54.609908 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10604 12:14:54.616413 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10605 12:14:54.619654 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10606 12:14:54.629671 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10607 12:14:54.685405 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10608 12:14:54.691918 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10609 12:14:54.698907 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10610 12:14:54.702219 [ 0.000000] psci: probing for conduit method from DT.
10611 12:14:54.708938 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10612 12:14:54.712099 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10613 12:14:54.718792 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10614 12:14:54.721888 [ 0.000000] psci: SMC Calling Convention v1.2
10615 12:14:54.728952 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10616 12:14:54.732037 [ 0.000000] Detected VIPT I-cache on CPU0
10617 12:14:54.738742 [ 0.000000] CPU features: detected: GIC system register CPU interface
10618 12:14:54.745472 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10619 12:14:54.752181 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10620 12:14:54.758693 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10621 12:14:54.765178 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10622 12:14:54.772002 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10623 12:14:54.778536 [ 0.000000] alternatives: applying boot alternatives
10624 12:14:54.784948 [ 0.000000] Fallback order for Node 0: 0
10625 12:14:54.791859 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10626 12:14:54.791944 [ 0.000000] Policy zone: Normal
10627 12:14:54.808207 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10628 12:14:54.818298 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10629 12:14:54.829870 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10630 12:14:54.839754 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10631 12:14:54.846583 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10632 12:14:54.849679 <6>[ 0.000000] software IO TLB: area num 8.
10633 12:14:54.906260 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10634 12:14:55.055705 <6>[ 0.000000] Memory: 7871188K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 481580K reserved, 32768K cma-reserved)
10635 12:14:55.062241 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10636 12:14:55.068804 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10637 12:14:55.072035 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10638 12:14:55.078837 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10639 12:14:55.085678 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10640 12:14:55.088700 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10641 12:14:55.098939 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10642 12:14:55.105601 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10643 12:14:55.109024 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10644 12:14:55.116546 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10645 12:14:55.119775 <6>[ 0.000000] GICv3: 608 SPIs implemented
10646 12:14:55.126343 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10647 12:14:55.129554 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10648 12:14:55.133002 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10649 12:14:55.143078 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10650 12:14:55.152975 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10651 12:14:55.166423 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10652 12:14:55.172813 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10653 12:14:55.181844 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10654 12:14:55.195339 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10655 12:14:55.201667 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10656 12:14:55.208353 <6>[ 0.009188] Console: colour dummy device 80x25
10657 12:14:55.218497 <6>[ 0.013945] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10658 12:14:55.224749 <6>[ 0.024386] pid_max: default: 32768 minimum: 301
10659 12:14:55.228280 <6>[ 0.029257] LSM: Security Framework initializing
10660 12:14:55.234738 <6>[ 0.034195] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10661 12:14:55.244724 <6>[ 0.042010] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10662 12:14:55.251579 <6>[ 0.051278] cblist_init_generic: Setting adjustable number of callback queues.
10663 12:14:55.258071 <6>[ 0.058766] cblist_init_generic: Setting shift to 3 and lim to 1.
10664 12:14:55.268187 <6>[ 0.065105] cblist_init_generic: Setting adjustable number of callback queues.
10665 12:14:55.271611 <6>[ 0.072578] cblist_init_generic: Setting shift to 3 and lim to 1.
10666 12:14:55.278258 <6>[ 0.078978] rcu: Hierarchical SRCU implementation.
10667 12:14:55.284505 <6>[ 0.083993] rcu: Max phase no-delay instances is 1000.
10668 12:14:55.291286 <6>[ 0.091022] EFI services will not be available.
10669 12:14:55.294712 <6>[ 0.095975] smp: Bringing up secondary CPUs ...
10670 12:14:55.302320 <6>[ 0.100988] Detected VIPT I-cache on CPU1
10671 12:14:55.309039 <6>[ 0.101044] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10672 12:14:55.315692 <6>[ 0.101073] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10673 12:14:55.318918 <6>[ 0.101409] Detected VIPT I-cache on CPU2
10674 12:14:55.325448 <6>[ 0.101459] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10675 12:14:55.332187 <6>[ 0.101475] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10676 12:14:55.338967 <6>[ 0.101732] Detected VIPT I-cache on CPU3
10677 12:14:55.345349 <6>[ 0.101778] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10678 12:14:55.352068 <6>[ 0.101792] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10679 12:14:55.355684 <6>[ 0.102098] CPU features: detected: Spectre-v4
10680 12:14:55.362200 <6>[ 0.102104] CPU features: detected: Spectre-BHB
10681 12:14:55.365584 <6>[ 0.102109] Detected PIPT I-cache on CPU4
10682 12:14:55.372720 <6>[ 0.102164] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10683 12:14:55.379210 <6>[ 0.102180] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10684 12:14:55.385630 <6>[ 0.102473] Detected PIPT I-cache on CPU5
10685 12:14:55.392135 <6>[ 0.102535] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10686 12:14:55.398665 <6>[ 0.102553] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10687 12:14:55.401850 <6>[ 0.102832] Detected PIPT I-cache on CPU6
10688 12:14:55.408366 <6>[ 0.102896] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10689 12:14:55.415110 <6>[ 0.102913] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10690 12:14:55.421756 <6>[ 0.103209] Detected PIPT I-cache on CPU7
10691 12:14:55.428248 <6>[ 0.103273] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10692 12:14:55.435187 <6>[ 0.103290] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10693 12:14:55.438422 <6>[ 0.103336] smp: Brought up 1 node, 8 CPUs
10694 12:14:55.445063 <6>[ 0.244563] SMP: Total of 8 processors activated.
10695 12:14:55.448331 <6>[ 0.249484] CPU features: detected: 32-bit EL0 Support
10696 12:14:55.458260 <6>[ 0.254880] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10697 12:14:55.464883 <6>[ 0.263681] CPU features: detected: Common not Private translations
10698 12:14:55.468255 <6>[ 0.270156] CPU features: detected: CRC32 instructions
10699 12:14:55.475191 <6>[ 0.275541] CPU features: detected: RCpc load-acquire (LDAPR)
10700 12:14:55.481459 <6>[ 0.281501] CPU features: detected: LSE atomic instructions
10701 12:14:55.488260 <6>[ 0.287282] CPU features: detected: Privileged Access Never
10702 12:14:55.491358 <6>[ 0.293062] CPU features: detected: RAS Extension Support
10703 12:14:55.501620 <6>[ 0.298671] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10704 12:14:55.504910 <6>[ 0.305891] CPU: All CPU(s) started at EL2
10705 12:14:55.510972 <6>[ 0.310235] alternatives: applying system-wide alternatives
10706 12:14:55.520126 <6>[ 0.320899] devtmpfs: initialized
10707 12:14:55.532054 <6>[ 0.329784] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10708 12:14:55.542016 <6>[ 0.339744] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10709 12:14:55.548866 <6>[ 0.347981] pinctrl core: initialized pinctrl subsystem
10710 12:14:55.551961 <6>[ 0.354661] DMI not present or invalid.
10711 12:14:55.558610 <6>[ 0.359075] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10712 12:14:55.568608 <6>[ 0.365943] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10713 12:14:55.575473 <6>[ 0.373525] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10714 12:14:55.585435 <6>[ 0.381758] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10715 12:14:55.588453 <6>[ 0.390001] audit: initializing netlink subsys (disabled)
10716 12:14:55.598126 <5>[ 0.395694] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10717 12:14:55.604800 <6>[ 0.396401] thermal_sys: Registered thermal governor 'step_wise'
10718 12:14:55.611649 <6>[ 0.403663] thermal_sys: Registered thermal governor 'power_allocator'
10719 12:14:55.615221 <6>[ 0.409918] cpuidle: using governor menu
10720 12:14:55.621366 <6>[ 0.420877] NET: Registered PF_QIPCRTR protocol family
10721 12:14:55.628363 <6>[ 0.426352] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10722 12:14:55.634790 <6>[ 0.433456] ASID allocator initialised with 32768 entries
10723 12:14:55.638063 <6>[ 0.440029] Serial: AMBA PL011 UART driver
10724 12:14:55.647838 <4>[ 0.448852] Trying to register duplicate clock ID: 134
10725 12:14:55.701784 <6>[ 0.506069] KASLR enabled
10726 12:14:55.716192 <6>[ 0.513774] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10727 12:14:55.722764 <6>[ 0.520787] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10728 12:14:55.729651 <6>[ 0.527276] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10729 12:14:55.736032 <6>[ 0.534281] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10730 12:14:55.742702 <6>[ 0.540771] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10731 12:14:55.749450 <6>[ 0.547775] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10732 12:14:55.755834 <6>[ 0.554263] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10733 12:14:55.762323 <6>[ 0.561268] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10734 12:14:55.765846 <6>[ 0.568712] ACPI: Interpreter disabled.
10735 12:14:55.774323 <6>[ 0.575143] iommu: Default domain type: Translated
10736 12:14:55.781369 <6>[ 0.580258] iommu: DMA domain TLB invalidation policy: strict mode
10737 12:14:55.784218 <5>[ 0.586891] SCSI subsystem initialized
10738 12:14:55.790976 <6>[ 0.591138] usbcore: registered new interface driver usbfs
10739 12:14:55.797572 <6>[ 0.596867] usbcore: registered new interface driver hub
10740 12:14:55.800952 <6>[ 0.602420] usbcore: registered new device driver usb
10741 12:14:55.807519 <6>[ 0.608534] pps_core: LinuxPPS API ver. 1 registered
10742 12:14:55.817328 <6>[ 0.613729] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10743 12:14:55.821003 <6>[ 0.623074] PTP clock support registered
10744 12:14:55.823933 <6>[ 0.627316] EDAC MC: Ver: 3.0.0
10745 12:14:55.831604 <6>[ 0.632520] FPGA manager framework
10746 12:14:55.838116 <6>[ 0.636195] Advanced Linux Sound Architecture Driver Initialized.
10747 12:14:55.841523 <6>[ 0.642956] vgaarb: loaded
10748 12:14:55.844830 <6>[ 0.646107] clocksource: Switched to clocksource arch_sys_counter
10749 12:14:55.851612 <5>[ 0.652549] VFS: Disk quotas dquot_6.6.0
10750 12:14:55.858123 <6>[ 0.656737] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10751 12:14:55.861607 <6>[ 0.663927] pnp: PnP ACPI: disabled
10752 12:14:55.869551 <6>[ 0.670623] NET: Registered PF_INET protocol family
10753 12:14:55.879411 <6>[ 0.676209] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10754 12:14:55.890695 <6>[ 0.688512] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10755 12:14:55.900834 <6>[ 0.697328] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10756 12:14:55.907526 <6>[ 0.705301] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10757 12:14:55.914073 <6>[ 0.714001] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10758 12:14:55.925915 <6>[ 0.723742] TCP: Hash tables configured (established 65536 bind 65536)
10759 12:14:55.933002 <6>[ 0.730605] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10760 12:14:55.939880 <6>[ 0.737804] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10761 12:14:55.946106 <6>[ 0.745509] NET: Registered PF_UNIX/PF_LOCAL protocol family
10762 12:14:55.952719 <6>[ 0.751674] RPC: Registered named UNIX socket transport module.
10763 12:14:55.956010 <6>[ 0.757825] RPC: Registered udp transport module.
10764 12:14:55.962624 <6>[ 0.762756] RPC: Registered tcp transport module.
10765 12:14:55.969444 <6>[ 0.767689] RPC: Registered tcp NFSv4.1 backchannel transport module.
10766 12:14:55.972607 <6>[ 0.774354] PCI: CLS 0 bytes, default 64
10767 12:14:55.975935 <6>[ 0.778754] Unpacking initramfs...
10768 12:14:56.000813 <6>[ 0.798212] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10769 12:14:56.010619 <6>[ 0.806875] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10770 12:14:56.013755 <6>[ 0.815733] kvm [1]: IPA Size Limit: 40 bits
10771 12:14:56.020373 <6>[ 0.820262] kvm [1]: GICv3: no GICV resource entry
10772 12:14:56.023961 <6>[ 0.825282] kvm [1]: disabling GICv2 emulation
10773 12:14:56.030538 <6>[ 0.829970] kvm [1]: GIC system register CPU interface enabled
10774 12:14:56.034153 <6>[ 0.836138] kvm [1]: vgic interrupt IRQ18
10775 12:14:56.040344 <6>[ 0.840503] kvm [1]: VHE mode initialized successfully
10776 12:14:56.046908 <5>[ 0.847018] Initialise system trusted keyrings
10777 12:14:56.053496 <6>[ 0.851853] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10778 12:14:56.060909 <6>[ 0.861821] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10779 12:14:56.067489 <5>[ 0.868196] NFS: Registering the id_resolver key type
10780 12:14:56.070678 <5>[ 0.873501] Key type id_resolver registered
10781 12:14:56.077350 <5>[ 0.877919] Key type id_legacy registered
10782 12:14:56.083835 <6>[ 0.882204] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10783 12:14:56.090495 <6>[ 0.889129] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10784 12:14:56.096979 <6>[ 0.896839] 9p: Installing v9fs 9p2000 file system support
10785 12:14:56.132877 <5>[ 0.934138] Key type asymmetric registered
10786 12:14:56.136276 <5>[ 0.938468] Asymmetric key parser 'x509' registered
10787 12:14:56.146231 <6>[ 0.943655] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10788 12:14:56.149368 <6>[ 0.951272] io scheduler mq-deadline registered
10789 12:14:56.153166 <6>[ 0.956041] io scheduler kyber registered
10790 12:14:56.171997 <6>[ 0.973153] EINJ: ACPI disabled.
10791 12:14:56.204207 <4>[ 0.998648] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10792 12:14:56.214291 <4>[ 1.009282] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10793 12:14:56.228868 <6>[ 1.029821] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10794 12:14:56.236555 <6>[ 1.037724] printk: console [ttyS0] disabled
10795 12:14:56.264558 <6>[ 1.062372] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10796 12:14:56.271423 <6>[ 1.071846] printk: console [ttyS0] enabled
10797 12:14:56.274814 <6>[ 1.071846] printk: console [ttyS0] enabled
10798 12:14:56.281399 <6>[ 1.080739] printk: bootconsole [mtk8250] disabled
10799 12:14:56.284464 <6>[ 1.080739] printk: bootconsole [mtk8250] disabled
10800 12:14:56.291306 <6>[ 1.091753] SuperH (H)SCI(F) driver initialized
10801 12:14:56.294571 <6>[ 1.097025] msm_serial: driver initialized
10802 12:14:56.308618 <6>[ 1.105916] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10803 12:14:56.318240 <6>[ 1.114463] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10804 12:14:56.324864 <6>[ 1.123007] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10805 12:14:56.334877 <6>[ 1.131635] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10806 12:14:56.341486 <6>[ 1.140342] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10807 12:14:56.351418 <6>[ 1.149056] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10808 12:14:56.361453 <6>[ 1.157595] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10809 12:14:56.368210 <6>[ 1.166418] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10810 12:14:56.377888 <6>[ 1.174962] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10811 12:14:56.389264 <6>[ 1.190422] loop: module loaded
10812 12:14:56.395804 <6>[ 1.196162] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10813 12:14:56.418182 <4>[ 1.219115] mtk-pmic-keys: Failed to locate of_node [id: -1]
10814 12:14:56.424768 <6>[ 1.225871] megasas: 07.719.03.00-rc1
10815 12:14:56.434411 <6>[ 1.235457] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10816 12:14:56.444547 <6>[ 1.245482] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10817 12:14:56.461007 <6>[ 1.262052] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10818 12:14:56.517721 <6>[ 1.312097] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10819 12:14:59.999479 <6>[ 4.800747] Freeing initrd memory: 96064K
10820 12:15:00.009750 <6>[ 4.811061] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10821 12:15:00.020640 <6>[ 4.822037] tun: Universal TUN/TAP device driver, 1.6
10822 12:15:00.023825 <6>[ 4.828102] thunder_xcv, ver 1.0
10823 12:15:00.027475 <6>[ 4.831613] thunder_bgx, ver 1.0
10824 12:15:00.030675 <6>[ 4.835109] nicpf, ver 1.0
10825 12:15:00.041363 <6>[ 4.839128] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10826 12:15:00.044196 <6>[ 4.846603] hns3: Copyright (c) 2017 Huawei Corporation.
10827 12:15:00.047931 <6>[ 4.852190] hclge is initializing
10828 12:15:00.054339 <6>[ 4.855764] e1000: Intel(R) PRO/1000 Network Driver
10829 12:15:00.060718 <6>[ 4.860892] e1000: Copyright (c) 1999-2006 Intel Corporation.
10830 12:15:00.064227 <6>[ 4.866906] e1000e: Intel(R) PRO/1000 Network Driver
10831 12:15:00.071082 <6>[ 4.872121] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10832 12:15:00.077394 <6>[ 4.878305] igb: Intel(R) Gigabit Ethernet Network Driver
10833 12:15:00.083924 <6>[ 4.883955] igb: Copyright (c) 2007-2014 Intel Corporation.
10834 12:15:00.091013 <6>[ 4.889797] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10835 12:15:00.097510 <6>[ 4.896315] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10836 12:15:00.100664 <6>[ 4.902776] sky2: driver version 1.30
10837 12:15:00.107599 <6>[ 4.907772] VFIO - User Level meta-driver version: 0.3
10838 12:15:00.114616 <6>[ 4.916000] usbcore: registered new interface driver usb-storage
10839 12:15:00.121048 <6>[ 4.922463] usbcore: registered new device driver onboard-usb-hub
10840 12:15:00.130135 <6>[ 4.931637] mt6397-rtc mt6359-rtc: registered as rtc0
10841 12:15:00.139915 <6>[ 4.937131] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-31T12:14:23 UTC (1706703263)
10842 12:15:00.143568 <6>[ 4.946746] i2c_dev: i2c /dev entries driver
10843 12:15:00.160138 <6>[ 4.958438] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10844 12:15:00.179972 <6>[ 4.981425] cpu cpu0: EM: created perf domain
10845 12:15:00.183338 <6>[ 4.986324] cpu cpu4: EM: created perf domain
10846 12:15:00.190263 <6>[ 4.991987] sdhci: Secure Digital Host Controller Interface driver
10847 12:15:00.196843 <6>[ 4.998421] sdhci: Copyright(c) Pierre Ossman
10848 12:15:00.203703 <6>[ 5.003379] Synopsys Designware Multimedia Card Interface Driver
10849 12:15:00.210094 <6>[ 5.010035] sdhci-pltfm: SDHCI platform and OF driver helper
10850 12:15:00.213890 <6>[ 5.010139] mmc0: CQHCI version 5.10
10851 12:15:00.220196 <6>[ 5.020029] ledtrig-cpu: registered to indicate activity on CPUs
10852 12:15:00.226897 <6>[ 5.026961] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10853 12:15:00.233382 <6>[ 5.034008] usbcore: registered new interface driver usbhid
10854 12:15:00.236934 <6>[ 5.039830] usbhid: USB HID core driver
10855 12:15:00.243359 <6>[ 5.044034] spi_master spi0: will run message pump with realtime priority
10856 12:15:00.286247 <6>[ 5.081257] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10857 12:15:00.305780 <6>[ 5.097067] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10858 12:15:00.312675 <6>[ 5.113158] cros-ec-spi spi0.0: Chrome EC device registered
10859 12:15:00.315891 <6>[ 5.113272] mmc0: Command Queue Engine enabled
10860 12:15:00.322634 <6>[ 5.123744] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10861 12:15:00.329625 <6>[ 5.131129] mmcblk0: mmc0:0001 DA4128 116 GiB
10862 12:15:00.339473 <6>[ 5.141162] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10863 12:15:00.347788 <6>[ 5.148905] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10864 12:15:00.357280 <6>[ 5.152270] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10865 12:15:00.360928 <6>[ 5.154838] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10866 12:15:00.367464 <6>[ 5.164679] NET: Registered PF_PACKET protocol family
10867 12:15:00.374251 <6>[ 5.169367] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10868 12:15:00.377395 <6>[ 5.174041] 9pnet: Installing 9P2000 support
10869 12:15:00.383996 <5>[ 5.185058] Key type dns_resolver registered
10870 12:15:00.387575 <6>[ 5.189987] registered taskstats version 1
10871 12:15:00.393813 <5>[ 5.194366] Loading compiled-in X.509 certificates
10872 12:15:00.423160 <4>[ 5.217939] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10873 12:15:00.432967 <4>[ 5.228706] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10874 12:15:00.439764 <3>[ 5.239240] debugfs: File 'uA_load' in directory '/' already present!
10875 12:15:00.446072 <3>[ 5.245991] debugfs: File 'min_uV' in directory '/' already present!
10876 12:15:00.452886 <3>[ 5.252609] debugfs: File 'max_uV' in directory '/' already present!
10877 12:15:00.459461 <3>[ 5.259221] debugfs: File 'constraint_flags' in directory '/' already present!
10878 12:15:00.471546 <3>[ 5.269615] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10879 12:15:00.481298 <6>[ 5.283016] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10880 12:15:00.488457 <6>[ 5.289965] xhci-mtk 11200000.usb: xHCI Host Controller
10881 12:15:00.495560 <6>[ 5.295530] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10882 12:15:00.505429 <6>[ 5.303403] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10883 12:15:00.512099 <6>[ 5.312831] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10884 12:15:00.518456 <6>[ 5.318920] xhci-mtk 11200000.usb: xHCI Host Controller
10885 12:15:00.525316 <6>[ 5.324401] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10886 12:15:00.531662 <6>[ 5.332049] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10887 12:15:00.538257 <6>[ 5.339813] hub 1-0:1.0: USB hub found
10888 12:15:00.541622 <6>[ 5.343825] hub 1-0:1.0: 1 port detected
10889 12:15:00.551872 <6>[ 5.348113] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10890 12:15:00.555126 <6>[ 5.356687] hub 2-0:1.0: USB hub found
10891 12:15:00.558452 <6>[ 5.360697] hub 2-0:1.0: 1 port detected
10892 12:15:00.566948 <6>[ 5.368429] mtk-msdc 11f70000.mmc: Got CD GPIO
10893 12:15:00.580809 <6>[ 5.378766] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10894 12:15:00.587107 <6>[ 5.386811] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10895 12:15:00.597075 <4>[ 5.394727] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10896 12:15:00.606812 <6>[ 5.404289] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10897 12:15:00.613807 <6>[ 5.412366] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10898 12:15:00.620239 <6>[ 5.420387] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10899 12:15:00.630213 <6>[ 5.428303] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10900 12:15:00.636697 <6>[ 5.436120] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10901 12:15:00.646685 <6>[ 5.443937] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10902 12:15:00.656610 <6>[ 5.454331] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10903 12:15:00.663281 <6>[ 5.462691] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10904 12:15:00.672829 <6>[ 5.471036] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10905 12:15:00.679577 <6>[ 5.479376] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10906 12:15:00.689438 <6>[ 5.487714] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10907 12:15:00.696190 <6>[ 5.496052] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10908 12:15:00.706259 <6>[ 5.504392] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10909 12:15:00.716028 <6>[ 5.512730] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10910 12:15:00.722841 <6>[ 5.521068] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10911 12:15:00.732416 <6>[ 5.529407] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10912 12:15:00.739117 <6>[ 5.537758] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10913 12:15:00.748826 <6>[ 5.546097] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10914 12:15:00.755633 <6>[ 5.554435] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10915 12:15:00.765593 <6>[ 5.562773] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10916 12:15:00.772616 <6>[ 5.571112] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10917 12:15:00.778958 <6>[ 5.579855] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10918 12:15:00.785475 <6>[ 5.587025] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10919 12:15:00.792303 <6>[ 5.593780] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10920 12:15:00.802272 <6>[ 5.600536] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10921 12:15:00.808835 <6>[ 5.607473] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10922 12:15:00.815530 <6>[ 5.614249] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10923 12:15:00.825194 <6>[ 5.623375] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10924 12:15:00.835257 <6>[ 5.632493] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10925 12:15:00.845105 <6>[ 5.641787] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10926 12:15:00.854966 <6>[ 5.651254] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10927 12:15:00.861872 <6>[ 5.660720] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10928 12:15:00.871606 <6>[ 5.669839] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10929 12:15:00.881611 <6>[ 5.679307] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10930 12:15:00.891616 <6>[ 5.688425] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10931 12:15:00.901245 <6>[ 5.697718] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10932 12:15:00.911334 <6>[ 5.707878] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10933 12:15:00.921611 <6>[ 5.719749] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10934 12:15:00.968078 <6>[ 5.766383] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10935 12:15:01.122700 <6>[ 5.924381] hub 1-1:1.0: USB hub found
10936 12:15:01.126218 <6>[ 5.928895] hub 1-1:1.0: 4 ports detected
10937 12:15:01.136069 <6>[ 5.937437] hub 1-1:1.0: USB hub found
10938 12:15:01.139200 <6>[ 5.941806] hub 1-1:1.0: 4 ports detected
10939 12:15:01.248357 <6>[ 6.046520] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10940 12:15:01.274511 <6>[ 6.075768] hub 2-1:1.0: USB hub found
10941 12:15:01.277439 <6>[ 6.080260] hub 2-1:1.0: 3 ports detected
10942 12:15:01.286863 <6>[ 6.088411] hub 2-1:1.0: USB hub found
10943 12:15:01.289945 <6>[ 6.092851] hub 2-1:1.0: 3 ports detected
10944 12:15:01.464218 <6>[ 6.262422] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10945 12:15:01.596299 <6>[ 6.397912] hub 1-1.4:1.0: USB hub found
10946 12:15:01.599695 <6>[ 6.402523] hub 1-1.4:1.0: 2 ports detected
10947 12:15:01.609226 <6>[ 6.410847] hub 1-1.4:1.0: USB hub found
10948 12:15:01.612318 <6>[ 6.415435] hub 1-1.4:1.0: 2 ports detected
10949 12:15:01.680067 <6>[ 6.478515] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10950 12:15:01.907927 <6>[ 6.706423] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10951 12:15:02.099853 <6>[ 6.898420] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10952 12:15:13.193123 <6>[ 17.999418] ALSA device list:
10953 12:15:13.199816 <6>[ 18.002713] No soundcards found.
10954 12:15:13.208110 <6>[ 18.010728] Freeing unused kernel memory: 8448K
10955 12:15:13.211218 <6>[ 18.015743] Run /init as init process
10956 12:15:13.258953 <6>[ 18.061872] NET: Registered PF_INET6 protocol family
10957 12:15:13.265492 <6>[ 18.068292] Segment Routing with IPv6
10958 12:15:13.268737 <6>[ 18.072240] In-situ OAM (IOAM) with IPv6
10959 12:15:13.302345 <30>[ 18.085754] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10960 12:15:13.305830 <30>[ 18.109518] systemd[1]: Detected architecture arm64.
10961 12:15:13.305916
10962 12:15:13.312420 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10963 12:15:13.312506
10964 12:15:13.327380 <30>[ 18.130401] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10965 12:15:13.460034 <30>[ 18.259678] systemd[1]: Queued start job for default target Graphical Interface.
10966 12:15:13.488480 <30>[ 18.291322] systemd[1]: Created slice system-getty.slice.
10967 12:15:13.494700 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10968 12:15:13.511661 <30>[ 18.314720] systemd[1]: Created slice system-modprobe.slice.
10969 12:15:13.518402 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10970 12:15:13.536154 <30>[ 18.338971] systemd[1]: Created slice system-serial\x2dgetty.slice.
10971 12:15:13.546037 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10972 12:15:13.559988 <30>[ 18.362912] systemd[1]: Created slice User and Session Slice.
10973 12:15:13.566414 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10974 12:15:13.587317 <30>[ 18.386961] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10975 12:15:13.597207 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10976 12:15:13.615528 <30>[ 18.415002] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10977 12:15:13.621913 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10978 12:15:13.646562 <30>[ 18.442780] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10979 12:15:13.652840 <30>[ 18.454959] systemd[1]: Reached target Local Encrypted Volumes.
10980 12:15:13.659431 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10981 12:15:13.675738 <30>[ 18.478796] systemd[1]: Reached target Paths.
10982 12:15:13.678984 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10983 12:15:13.695487 <30>[ 18.498367] systemd[1]: Reached target Remote File Systems.
10984 12:15:13.701874 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10985 12:15:13.715434 <30>[ 18.518339] systemd[1]: Reached target Slices.
10986 12:15:13.718652 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10987 12:15:13.735516 <30>[ 18.538364] systemd[1]: Reached target Swap.
10988 12:15:13.738452 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10989 12:15:13.759374 <30>[ 18.559239] systemd[1]: Listening on initctl Compatibility Named Pipe.
10990 12:15:13.765884 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10991 12:15:13.780154 <30>[ 18.583174] systemd[1]: Listening on Journal Audit Socket.
10992 12:15:13.786620 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10993 12:15:13.804357 <30>[ 18.607503] systemd[1]: Listening on Journal Socket (/dev/log).
10994 12:15:13.811183 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10995 12:15:13.828569 <30>[ 18.631505] systemd[1]: Listening on Journal Socket.
10996 12:15:13.834779 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10997 12:15:13.847629 <30>[ 18.650862] systemd[1]: Listening on udev Control Socket.
10998 12:15:13.854537 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10999 12:15:13.872192 <30>[ 18.675378] systemd[1]: Listening on udev Kernel Socket.
11000 12:15:13.878924 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
11001 12:15:13.919825 <30>[ 18.722496] systemd[1]: Mounting Huge Pages File System...
11002 12:15:13.926259 Mounting [0;1;39mHuge Pages File System[0m...
11003 12:15:13.942654 <30>[ 18.745612] systemd[1]: Mounting POSIX Message Queue File System...
11004 12:15:13.949614 Mounting [0;1;39mPOSIX Message Queue File System[0m...
11005 12:15:13.966373 <30>[ 18.769667] systemd[1]: Mounting Kernel Debug File System...
11006 12:15:13.973475 Mounting [0;1;39mKernel Debug File System[0m...
11007 12:15:13.990878 <30>[ 18.790561] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
11008 12:15:14.003582 <30>[ 18.803259] systemd[1]: Starting Create list of static device nodes for the current kernel...
11009 12:15:14.009989 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
11010 12:15:14.047553 <30>[ 18.850641] systemd[1]: Starting Load Kernel Module configfs...
11011 12:15:14.053906 Starting [0;1;39mLoad Kernel Module configfs[0m...
11012 12:15:14.071269 <30>[ 18.874293] systemd[1]: Starting Load Kernel Module drm...
11013 12:15:14.077585 Starting [0;1;39mLoad Kernel Module drm[0m...
11014 12:15:14.094571 <30>[ 18.894618] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
11015 12:15:14.108385 <30>[ 18.911559] systemd[1]: Starting Journal Service...
11016 12:15:14.111558 Starting [0;1;39mJournal Service[0m...
11017 12:15:14.130155 <30>[ 18.933156] systemd[1]: Starting Load Kernel Modules...
11018 12:15:14.136486 Starting [0;1;39mLoad Kernel Modules[0m...
11019 12:15:14.159497 <30>[ 18.959270] systemd[1]: Starting Remount Root and Kernel File Systems...
11020 12:15:14.165769 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
11021 12:15:14.182523 <30>[ 18.985770] systemd[1]: Starting Coldplug All udev Devices...
11022 12:15:14.189227 Starting [0;1;39mColdplug All udev Devices[0m...
11023 12:15:14.206427 <30>[ 19.009679] systemd[1]: Started Journal Service.
11024 12:15:14.213292 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11025 12:15:14.231802 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
11026 12:15:14.248613 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11027 12:15:14.266211 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11028 12:15:14.284782 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
11029 12:15:14.301092 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11030 12:15:14.316873 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11031 12:15:14.333489 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11032 12:15:14.353575 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
11033 12:15:14.367379 See 'systemctl status systemd-remount-fs.service' for details.
11034 12:15:14.411299 Mounting [0;1;39mKernel Configuration File System[0m...
11035 12:15:14.431846 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11036 12:15:14.444767 <46>[ 19.244422] systemd-journald[181]: Received client request to flush runtime journal.
11037 12:15:14.456896 Starting [0;1;39mLoad/Save Random Seed[0m...
11038 12:15:14.504310 Starting [0;1;39mApply Kernel Variables[0m...
11039 12:15:14.527889 Starting [0;1;39mCreate System Users[0m...
11040 12:15:14.552189 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
11041 12:15:14.568243 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11042 12:15:14.592302 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11043 12:15:14.605218 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11044 12:15:14.621347 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11045 12:15:14.641193 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11046 12:15:14.700476 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11047 12:15:14.720079 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11048 12:15:14.731802 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11049 12:15:14.751346 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11050 12:15:14.775467 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11051 12:15:14.806707 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11052 12:15:14.824395 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11053 12:15:14.847856 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11054 12:15:14.933267 Starting [0;1;39mNetwork Time Synchronization[0m...
11055 12:15:14.950309 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11056 12:15:14.992949 <6>[ 19.792993] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
11057 12:15:14.999833 <6>[ 19.800733] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
11058 12:15:15.009728 <6>[ 19.809726] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
11059 12:15:15.016566 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11060 12:15:15.044065 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11061 12:15:15.062916 <3>[ 19.862643] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11062 12:15:15.072763 [[0;32m OK [<3>[ 19.871143] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11063 12:15:15.082380 0m] Found device<3>[ 19.880604] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11064 12:15:15.089437 <4>[ 19.887321] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
11065 12:15:15.092604 [0;1;39m/dev/ttyS0[0m.
11066 12:15:15.104474 <3>[ 19.904137] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11067 12:15:15.110786 <4>[ 19.904180] elants_i2c 4-0010: supply vccio not found, using dummy regulator
11068 12:15:15.120986 <3>[ 19.912279] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11069 12:15:15.127506 <3>[ 19.912285] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11070 12:15:15.137367 <3>[ 19.912294] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11071 12:15:15.143719 <3>[ 19.912301] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11072 12:15:15.147519 <6>[ 19.916356] mc: Linux media interface: v0.10
11073 12:15:15.157237 <3>[ 19.931119] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
11074 12:15:15.163684 <6>[ 19.956182] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
11075 12:15:15.170127 <3>[ 19.959832] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11076 12:15:15.176788 <6>[ 19.965032] pci_bus 0000:00: root bus resource [bus 00-ff]
11077 12:15:15.186894 <6>[ 19.969728] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
11078 12:15:15.196945 <6>[ 19.969962] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
11079 12:15:15.203881 <3>[ 19.971695] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11080 12:15:15.211220 <6>[ 19.973747] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
11081 12:15:15.217916 <6>[ 19.977589] usbcore: registered new device driver r8152-cfgselector
11082 12:15:15.224186 <6>[ 19.979898] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
11083 12:15:15.234140 <3>[ 19.985498] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11084 12:15:15.244791 <6>[ 19.995571] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
11085 12:15:15.251799 <4>[ 20.000287] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11086 12:15:15.258228 <4>[ 20.000287] Fallback method does not support PEC.
11087 12:15:15.264737 <3>[ 20.005605] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11088 12:15:15.271845 <6>[ 20.010431] videodev: Linux video capture interface: v2.00
11089 12:15:15.278211 <6>[ 20.013000] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11090 12:15:15.284986 <3>[ 20.017386] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11091 12:15:15.294665 <3>[ 20.020459] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11092 12:15:15.301181 <6>[ 20.026934] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11093 12:15:15.311433 <3>[ 20.034045] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11094 12:15:15.314642 <6>[ 20.042245] pci 0000:00:00.0: supports D1 D2
11095 12:15:15.324906 <6>[ 20.048454] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11096 12:15:15.331407 <3>[ 20.052031] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11097 12:15:15.341039 <3>[ 20.055238] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11098 12:15:15.347743 <6>[ 20.065662] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11099 12:15:15.358055 <3>[ 20.065758] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11100 12:15:15.364734 <3>[ 20.074364] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11101 12:15:15.374593 <6>[ 20.104242] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
11102 12:15:15.380976 <6>[ 20.105135] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11103 12:15:15.391124 <3>[ 20.119671] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11104 12:15:15.397775 <6>[ 20.122050] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11105 12:15:15.404842 <6>[ 20.122082] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11106 12:15:15.411253 <6>[ 20.122122] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11107 12:15:15.418582 <6>[ 20.122137] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11108 12:15:15.422166 <6>[ 20.122263] pci 0000:01:00.0: supports D1 D2
11109 12:15:15.428694 <6>[ 20.122265] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11110 12:15:15.436155 <6>[ 20.122508] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
11111 12:15:15.442683 <6>[ 20.133471] remoteproc remoteproc0: scp is available
11112 12:15:15.449409 <6>[ 20.141294] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11113 12:15:15.452875 <6>[ 20.142348] Bluetooth: Core ver 2.22
11114 12:15:15.459266 <6>[ 20.142617] NET: Registered PF_BLUETOOTH protocol family
11115 12:15:15.466489 <6>[ 20.142633] Bluetooth: HCI device and connection manager initialized
11116 12:15:15.469875 <6>[ 20.142724] Bluetooth: HCI socket layer initialized
11117 12:15:15.476524 <6>[ 20.142756] Bluetooth: L2CAP socket layer initialized
11118 12:15:15.479608 <6>[ 20.142926] Bluetooth: SCO socket layer initialized
11119 12:15:15.486601 <6>[ 20.150040] remoteproc remoteproc0: powering up scp
11120 12:15:15.493618 <6>[ 20.157310] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11121 12:15:15.503791 <6>[ 20.165607] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
11122 12:15:15.510931 <6>[ 20.173706] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11123 12:15:15.517390 <6>[ 20.174339] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11124 12:15:15.527046 <6>[ 20.174359] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11125 12:15:15.534071 <6>[ 20.174372] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11126 12:15:15.540568 <6>[ 20.174387] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11127 12:15:15.547167 <6>[ 20.174404] pci 0000:00:00.0: PCI bridge to [bus 01]
11128 12:15:15.553734 <6>[ 20.174411] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11129 12:15:15.560539 <6>[ 20.174653] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11130 12:15:15.566853 <6>[ 20.176089] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11131 12:15:15.573778 <6>[ 20.176291] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11132 12:15:15.580921 <6>[ 20.182049] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
11133 12:15:15.584152 <6>[ 20.183361] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11134 12:15:15.594420 <5>[ 20.192075] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11135 12:15:15.607660 <6>[ 20.200715] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11136 12:15:15.614953 <4>[ 20.202061] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11137 12:15:15.624572 <4>[ 20.202070] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11138 12:15:15.627833 <6>[ 20.206388] usbcore: registered new interface driver btusb
11139 12:15:15.641161 <4>[ 20.207371] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11140 12:15:15.644332 <3>[ 20.207381] Bluetooth: hci0: Failed to load firmware file (-2)
11141 12:15:15.650860 <3>[ 20.207384] Bluetooth: hci0: Failed to set up firmware (-2)
11142 12:15:15.661234 <4>[ 20.207388] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11143 12:15:15.667598 <6>[ 20.212597] usbcore: registered new interface driver uvcvideo
11144 12:15:15.674219 <5>[ 20.218028] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11145 12:15:15.684609 <5>[ 20.218285] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11146 12:15:15.691128 <4>[ 20.218347] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11147 12:15:15.698067 <6>[ 20.218354] cfg80211: failed to load regulatory.db
11148 12:15:15.704836 <3>[ 20.230757] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11149 12:15:15.714997 <3>[ 20.231426] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
11150 12:15:15.722232 <3>[ 20.246183] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11151 12:15:15.728153 <6>[ 20.258336] r8152 2-1.3:1.0 eth0: v1.12.13
11152 12:15:15.735413 <3>[ 20.270947] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11153 12:15:15.741909 <6>[ 20.274216] usbcore: registered new interface driver r8152
11154 12:15:15.748861 <6>[ 20.307077] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11155 12:15:15.758883 <3>[ 20.313685] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11156 12:15:15.765676 <6>[ 20.318436] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11157 12:15:15.772275 <6>[ 20.326482] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11158 12:15:15.779314 <6>[ 20.330826] usbcore: registered new interface driver cdc_ether
11159 12:15:15.782868 <6>[ 20.334619] usbcore: registered new interface driver r8153_ecm
11160 12:15:15.792087 <6>[ 20.342552] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11161 12:15:15.798781 <6>[ 20.354377] mt7921e 0000:01:00.0: ASIC revision: 79610010
11162 12:15:15.805328 <6>[ 20.355576] remoteproc remoteproc0: remote processor scp is now up
11163 12:15:15.808512 <6>[ 20.369575] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
11164 12:15:15.818877 <6>[ 20.371415] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11165 12:15:15.828633 <3>[ 20.389656] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11166 12:15:15.834852 <6>[ 20.396658] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11167 12:15:15.844931 <3>[ 20.425073] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11168 12:15:15.851407 <6>[ 20.460052] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
11169 12:15:15.854740 <6>[ 20.460052]
11170 12:15:15.861425 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11171 12:15:15.879665 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11172 12:15:15.899414 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11173 12:15:15.934896 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11174 12:15:15.961556 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11175 12:15:16.122258 [[0;32m OK [<6>[ 20.920148] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
11176 12:15:16.125311 0m] Reached target [0;1;39mBluetooth[0m.
11177 12:15:16.139437 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11178 12:15:16.163740 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11179 12:15:16.182518 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11180 12:15:16.195027 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11181 12:15:16.214933 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11182 12:15:16.227117 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11183 12:15:16.242997 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11184 12:15:16.262815 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11185 12:15:16.295544 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11186 12:15:16.327113 Starting [0;1;39mUser Login Management[0m...
11187 12:15:16.347382 Starting [0;1;39mPermit User Sessions[0m...
11188 12:15:16.367415 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11189 12:15:16.393210 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11190 12:15:16.410262 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11191 12:15:16.427584 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11192 12:15:16.464418 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11193 12:15:16.482367 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11194 12:15:16.500366 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11195 12:15:16.518161 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11196 12:15:16.535952 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11197 12:15:16.589135 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11198 12:15:16.625322 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11199 12:15:16.667296
11200 12:15:16.667387
11201 12:15:16.670639 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11202 12:15:16.670724
11203 12:15:16.674109 debian-bullseye-arm64 login: root (automatic login)
11204 12:15:16.674194
11205 12:15:16.674260
11206 12:15:16.689535 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024 aarch64
11207 12:15:16.689620
11208 12:15:16.696181 The programs included with the Debian GNU/Linux system are free software;
11209 12:15:16.702777 the exact distribution terms for each program are described in the
11210 12:15:16.706035 individual files in /usr/share/doc/*/copyright.
11211 12:15:16.706120
11212 12:15:16.712575 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11213 12:15:16.715966 permitted by applicable law.
11214 12:15:16.716344 Matched prompt #10: / #
11216 12:15:16.716554 Setting prompt string to ['/ #']
11217 12:15:16.716646 end: 2.2.5.1 login-action (duration 00:00:22) [common]
11219 12:15:16.716841 end: 2.2.5 auto-login-action (duration 00:00:22) [common]
11220 12:15:16.716928 start: 2.2.6 expect-shell-connection (timeout 00:02:49) [common]
11221 12:15:16.716998 Setting prompt string to ['/ #']
11222 12:15:16.717060 Forcing a shell prompt, looking for ['/ #']
11224 12:15:16.767276 / #
11225 12:15:16.767388 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11226 12:15:16.767466 Waiting using forced prompt support (timeout 00:02:30)
11227 12:15:16.772176
11228 12:15:16.772449 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11229 12:15:16.772546 start: 2.2.7 export-device-env (timeout 00:02:49) [common]
11230 12:15:16.772641 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11231 12:15:16.772733 end: 2.2 depthcharge-retry (duration 00:02:11) [common]
11232 12:15:16.772822 end: 2 depthcharge-action (duration 00:02:11) [common]
11233 12:15:16.772912 start: 3 lava-test-retry (timeout 00:05:00) [common]
11234 12:15:16.772998 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11235 12:15:16.773072 Using namespace: common
11237 12:15:16.873397 / # #
11238 12:15:16.873513 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11239 12:15:16.878325 #
11240 12:15:16.878620 Using /lava-12669505
11242 12:15:16.978947 / # export SHELL=/bin/sh
11243 12:15:16.979086 export SHELL=/bin/sh<6>[ 21.774908] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11244 12:15:16.983619
11246 12:15:17.084124 / # . /lava-12669505/environment
11247 12:15:17.089197 . /lava-12669505/environment
11249 12:15:17.189772 / # /lava-12669505/bin/lava-test-runner /lava-12669505/0
11250 12:15:17.189891 Test shell timeout: 10s (minimum of the action and connection timeout)
11251 12:15:17.194929 /lava-12669505/bin/lava-test-runner /lava-12669505/0
11252 12:15:17.214632 + export TESTRUN_ID=0_sleep
11253 12:15:17.217885 + cd /lava-12669505/0/tests/0_sleep
11254 12:15:17.221063 + cat uuid
11255 12:15:17.221149 + UUID=12669505_1.5.2.3.1
11256 12:15:17.224282 + set +x
11257 12:15:17.227747 <LAVA_SIGNAL_STARTRUN 0_sleep 12669505_1.5.2.3.1>
11258 12:15:17.228004 Received signal: <STARTRUN> 0_sleep 12669505_1.5.2.3.1
11259 12:15:17.228082 Starting test lava.0_sleep (12669505_1.5.2.3.1)
11260 12:15:17.228165 Skipping test definition patterns.
11261 12:15:17.230932 + ./config/lava/sleep/sleep.sh mem
11262 12:15:17.234118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-exist RESULT=pass>
11263 12:15:17.234370 Received signal: <TESTCASE> TEST_CASE_ID=rtc-exist RESULT=pass
11265 12:15:17.240606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass>
11266 12:15:17.240862 Received signal: <TESTCASE> TEST_CASE_ID=rtc-wakeup-enabled RESULT=pass
11268 12:15:17.243996 rtcwake: assuming RTC uses UTC ...
11269 12:15:17.254082 rtcwake: wakeup from "mem" using rtc0 at Wed Jan 31<6>[ 22.056987] PM: suspend entry (deep)
11270 12:15:17.254194 12:14:46 2024
11271 12:15:17.257328 <6>[ 22.061247] Filesystems sync: 0.000 seconds
11272 12:15:17.266799 <6>[ 22.070091] Freezing user space processes
11273 12:15:17.276708 <6>[ 22.076696] Freezing user space processes completed (elapsed 0.002 seconds)
11274 12:15:17.280043 <6>[ 22.083966] OOM killer disabled.
11275 12:15:17.283209 <6>[ 22.087482] Freezing remaining freezable tasks
11276 12:15:17.293489 <6>[ 22.093595] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11277 12:15:17.300181 <6>[ 22.101271] printk: Suspending console(s) (use no_console_suspend to debug)
11278 12:15:23.291706 <6>[ 22.249906] Disabling non-boot CPUs ...
11279 12:15:23.295472 <4>[ 22.250874] IRQ282: set affinity failed(-22).
11280 12:15:23.298608 <4>[ 22.250889] IRQ284: set affinity failed(-22).
11281 12:15:23.305412 <6>[ 22.250969] psci: CPU1 killed (polled 0 ms)
11282 12:15:23.308552 <4>[ 22.252452] IRQ282: set affinity failed(-22).
11283 12:15:23.315346 <4>[ 22.252464] IRQ284: set affinity failed(-22).
11284 12:15:23.318959 <6>[ 22.252531] psci: CPU2 killed (polled 0 ms)
11285 12:15:23.322013 <4>[ 22.253695] IRQ282: set affinity failed(-22).
11286 12:15:23.328677 <4>[ 22.253707] IRQ284: set affinity failed(-22).
11287 12:15:23.332083 <6>[ 22.254132] psci: CPU3 killed (polled 4 ms)
11288 12:15:23.335478 <4>[ 22.254846] IRQ282: set affinity failed(-22).
11289 12:15:23.341901 <4>[ 22.254853] IRQ284: set affinity failed(-22).
11290 12:15:23.345501 <6>[ 22.254889] psci: CPU4 killed (polled 0 ms)
11291 12:15:23.351854 <4>[ 22.255908] IRQ282: set affinity failed(-22).
11292 12:15:23.355309 <4>[ 22.255918] IRQ284: set affinity failed(-22).
11293 12:15:23.358597 <6>[ 22.255958] psci: CPU5 killed (polled 0 ms)
11294 12:15:23.365392 <6>[ 22.256897] psci: CPU6 killed (polled 0 ms)
11295 12:15:23.368598 <6>[ 22.257829] psci: CPU7 killed (polled 0 ms)
11296 12:15:23.371994 <6>[ 22.258449] Enabling non-boot CPUs ...
11297 12:15:23.374937 <6>[ 22.258688] Detected VIPT I-cache on CPU1
11298 12:15:23.385148 <6>[ 22.258778] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11299 12:15:23.391590 <6>[ 22.258842] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11300 12:15:23.391675 <6>[ 22.259418] CPU1 is up
11301 12:15:23.398643 <6>[ 22.259566] Detected VIPT I-cache on CPU2
11302 12:15:23.405058 <6>[ 22.259625] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11303 12:15:23.412024 <6>[ 22.259665] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11304 12:15:23.415337 <6>[ 22.260131] CPU2 is up
11305 12:15:23.418453 <6>[ 22.260273] Detected VIPT I-cache on CPU3
11306 12:15:23.424907 <6>[ 22.260330] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11307 12:15:23.431520 <6>[ 22.260370] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11308 12:15:23.434824 <6>[ 22.260853] CPU3 is up
11309 12:15:23.441462 <6>[ 22.260977] CPU features: detected: Hardware dirty bit management
11310 12:15:23.444932 <6>[ 22.261001] Detected PIPT I-cache on CPU4
11311 12:15:23.451390 <6>[ 22.261032] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11312 12:15:23.458306 <6>[ 22.261056] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11313 12:15:23.461479 <6>[ 22.261415] CPU4 is up
11314 12:15:23.468339 <6>[ 22.261556] Detected PIPT I-cache on CPU5
11315 12:15:23.474847 <6>[ 22.261591] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11316 12:15:23.481560 <6>[ 22.261615] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11317 12:15:23.484794 <6>[ 22.261938] CPU5 is up
11318 12:15:23.488032 <6>[ 22.262088] Detected PIPT I-cache on CPU6
11319 12:15:23.494841 <6>[ 22.262122] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11320 12:15:23.501645 <6>[ 22.262146] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11321 12:15:23.504448 <6>[ 22.262495] CPU6 is up
11322 12:15:23.508138 <6>[ 22.262638] Detected PIPT I-cache on CPU7
11323 12:15:23.514542 <6>[ 22.262681] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11324 12:15:23.521534 <6>[ 22.262704] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11325 12:15:23.524580 <6>[ 22.263054] CPU7 is up
11326 12:15:23.531161 <4>[ 22.402431] typec port0-partner: PM: parent port0 should not be sleeping
11327 12:15:23.534752 <6>[ 22.857835] OOM killer enabled.
11328 12:15:23.541280 <6>[ 22.861227] Restarting tasks ... done.
11329 12:15:23.544319 <5>[ 22.865575] random: crng reseeded on system resumption
11330 12:15:23.548193 <6>[ 22.871862] PM: suspend exit
11331 12:15:23.558795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-1 RESULT=pass>
11332 12:15:23.559199 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-1 RESULT=pass
11334 12:15:23.561928 rtcwake: assuming RTC uses UTC ...
11335 12:15:23.569051 rtcwake: wakeup from "mem" using rtc0 at Wed Jan 31 12:14:52 2024
11336 12:15:23.582002 <6>[ 22.901890] PM: suspend entry (deep)
11337 12:15:23.585425 <6>[ 22.905778] Filesystems sync: 0.000 seconds
11338 12:15:23.588474 <6>[ 22.910511] Freezing user space processes
11339 12:15:23.599319 <6>[ 22.916125] Freezing user space processes completed (elapsed 0.001 seconds)
11340 12:15:23.602829 <6>[ 22.923345] OOM killer disabled.
11341 12:15:23.606325 <6>[ 22.926825] Freezing remaining freezable tasks
11342 12:15:23.615948 <6>[ 22.932633] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11343 12:15:23.622831 <6>[ 22.940286] printk: Suspending console(s) (use no_console_suspend to debug)
11344 12:15:29.296866 <6>[ 23.014321] Disabling non-boot CPUs ...
11345 12:15:29.300126 <6>[ 23.015184] psci: CPU1 killed (polled 0 ms)
11346 12:15:29.303444 <6>[ 23.017133] psci: CPU2 killed (polled 0 ms)
11347 12:15:29.310441 <6>[ 23.018076] psci: CPU3 killed (polled 4 ms)
11348 12:15:29.313640 <6>[ 23.018556] psci: CPU4 killed (polled 0 ms)
11349 12:15:29.316662 <6>[ 23.019141] psci: CPU5 killed (polled 0 ms)
11350 12:15:29.323543 <6>[ 23.019666] psci: CPU6 killed (polled 0 ms)
11351 12:15:29.326549 <6>[ 23.020256] psci: CPU7 killed (polled 0 ms)
11352 12:15:29.330093 <6>[ 23.020609] Enabling non-boot CPUs ...
11353 12:15:29.337102 <6>[ 23.020816] Detected VIPT I-cache on CPU1
11354 12:15:29.343363 <6>[ 23.020894] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11355 12:15:29.350444 <6>[ 23.020948] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11356 12:15:29.353686 <6>[ 23.021507] CPU1 is up
11357 12:15:29.356934 <6>[ 23.021629] Detected VIPT I-cache on CPU2
11358 12:15:29.363022 <6>[ 23.021675] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11359 12:15:29.370184 <6>[ 23.021706] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11360 12:15:29.373140 <6>[ 23.022153] CPU2 is up
11361 12:15:29.376708 <6>[ 23.022271] Detected VIPT I-cache on CPU3
11362 12:15:29.383154 <6>[ 23.022316] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11363 12:15:29.390166 <6>[ 23.022348] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11364 12:15:29.393073 <6>[ 23.022782] CPU3 is up
11365 12:15:29.399999 <6>[ 23.022899] Detected PIPT I-cache on CPU4
11366 12:15:29.406421 <6>[ 23.022921] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11367 12:15:29.413288 <6>[ 23.022936] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11368 12:15:29.416337 <6>[ 23.023206] CPU4 is up
11369 12:15:29.419488 <6>[ 23.023328] Detected PIPT I-cache on CPU5
11370 12:15:29.426254 <6>[ 23.023351] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11371 12:15:29.432944 <6>[ 23.023366] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11372 12:15:29.436349 <6>[ 23.023601] CPU5 is up
11373 12:15:29.439399 <6>[ 23.023712] Detected PIPT I-cache on CPU6
11374 12:15:29.446266 <6>[ 23.023735] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11375 12:15:29.453018 <6>[ 23.023750] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11376 12:15:29.456330 <6>[ 23.023986] CPU6 is up
11377 12:15:29.459252 <6>[ 23.024100] Detected PIPT I-cache on CPU7
11378 12:15:29.469652 <6>[ 23.024129] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11379 12:15:29.476432 <6>[ 23.024143] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11380 12:15:29.476972 <6>[ 23.024398] CPU7 is up
11381 12:15:29.479741 <6>[ 23.566017] OOM killer enabled.
11382 12:15:29.486628 <6>[ 23.569407] Restarting tasks ... done.
11383 12:15:29.489842 <5>[ 23.573803] random: crng reseeded on system resumption
11384 12:15:29.493567 <6>[ 23.580089] PM: suspend exit
11385 12:15:29.503850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-2 RESULT=pass>
11386 12:15:29.504725 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-2 RESULT=pass
11388 12:15:29.507538 rtcwake: assuming RTC uses UTC ...
11389 12:15:29.513863 rtcwake: wakeup from "mem" using rtc0 at Wed Jan 31 12:14:58 2024
11390 12:15:29.526530 <6>[ 23.610002] PM: suspend entry (deep)
11391 12:15:29.530657 <6>[ 23.613867] Filesystems sync: 0.000 seconds
11392 12:15:29.533531 <6>[ 23.618616] Freezing user space processes
11393 12:15:29.544299 <6>[ 23.624255] Freezing user space processes completed (elapsed 0.001 seconds)
11394 12:15:29.547587 <6>[ 23.631481] OOM killer disabled.
11395 12:15:29.551018 <6>[ 23.634961] Freezing remaining freezable tasks
11396 12:15:29.561353 <6>[ 23.640874] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11397 12:15:29.568128 <6>[ 23.648541] printk: Suspending console(s) (use no_console_suspend to debug)
11398 12:15:35.290642 <6>[ 23.723087] Disabling non-boot CPUs ...
11399 12:15:35.293782 <6>[ 23.723870] psci: CPU1 killed (polled 0 ms)
11400 12:15:35.297657 <6>[ 23.725823] psci: CPU2 killed (polled 0 ms)
11401 12:15:35.304188 <6>[ 23.727553] psci: CPU3 killed (polled 0 ms)
11402 12:15:35.307540 <6>[ 23.727979] psci: CPU4 killed (polled 0 ms)
11403 12:15:35.310525 <6>[ 23.728490] psci: CPU5 killed (polled 0 ms)
11404 12:15:35.317547 <6>[ 23.729063] psci: CPU6 killed (polled 0 ms)
11405 12:15:35.320756 <6>[ 23.729568] psci: CPU7 killed (polled 0 ms)
11406 12:15:35.323863 <6>[ 23.729858] Enabling non-boot CPUs ...
11407 12:15:35.330604 <6>[ 23.730056] Detected VIPT I-cache on CPU1
11408 12:15:35.337347 <6>[ 23.730126] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11409 12:15:35.343792 <6>[ 23.730176] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11410 12:15:35.347198 <6>[ 23.730696] CPU1 is up
11411 12:15:35.350466 <6>[ 23.730809] Detected VIPT I-cache on CPU2
11412 12:15:35.356875 <6>[ 23.730852] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11413 12:15:35.364000 <6>[ 23.730881] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11414 12:15:35.367078 <6>[ 23.731269] CPU2 is up
11415 12:15:35.370516 <6>[ 23.731380] Detected VIPT I-cache on CPU3
11416 12:15:35.377444 <6>[ 23.731422] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11417 12:15:35.384018 <6>[ 23.731450] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11418 12:15:35.387256 <6>[ 23.731844] CPU3 is up
11419 12:15:35.394091 <6>[ 23.731953] Detected PIPT I-cache on CPU4
11420 12:15:35.400125 <6>[ 23.731974] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11421 12:15:35.407044 <6>[ 23.731988] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11422 12:15:35.410551 <6>[ 23.732243] CPU4 is up
11423 12:15:35.413527 <6>[ 23.732359] Detected PIPT I-cache on CPU5
11424 12:15:35.420521 <6>[ 23.732381] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11425 12:15:35.427389 <6>[ 23.732395] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11426 12:15:35.430370 <6>[ 23.732617] CPU5 is up
11427 12:15:35.433828 <6>[ 23.732723] Detected PIPT I-cache on CPU6
11428 12:15:35.440493 <6>[ 23.732743] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11429 12:15:35.446862 <6>[ 23.732757] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11430 12:15:35.450346 <6>[ 23.732981] CPU6 is up
11431 12:15:35.453628 <6>[ 23.733087] Detected PIPT I-cache on CPU7
11432 12:15:35.463852 <6>[ 23.733114] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11433 12:15:35.470504 <6>[ 23.733128] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11434 12:15:35.471072 <6>[ 23.733376] CPU7 is up
11435 12:15:35.473760 <6>[ 24.270148] OOM killer enabled.
11436 12:15:35.480287 <6>[ 24.273538] Restarting tasks ... done.
11437 12:15:35.484012 <5>[ 24.277937] random: crng reseeded on system resumption
11438 12:15:35.487742 <6>[ 24.284318] PM: suspend exit
11439 12:15:35.498432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-3 RESULT=pass>
11440 12:15:35.499325 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-3 RESULT=pass
11442 12:15:35.501473 rtcwake: assuming RTC uses UTC ...
11443 12:15:35.508286 rtcwake: wakeup from "mem" using rtc0 at Wed Jan 31 12:15:04 2024
11444 12:15:35.520573 <6>[ 24.314110] PM: suspend entry (deep)
11445 12:15:35.524017 <6>[ 24.317978] Filesystems sync: 0.000 seconds
11446 12:15:35.527360 <6>[ 24.322692] Freezing user space processes
11447 12:15:35.538304 <6>[ 24.328367] Freezing user space processes completed (elapsed 0.001 seconds)
11448 12:15:35.541925 <6>[ 24.335600] OOM killer disabled.
11449 12:15:35.544672 <6>[ 24.339081] Freezing remaining freezable tasks
11450 12:15:35.555106 <6>[ 24.344985] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11451 12:15:35.561628 <6>[ 24.352650] printk: Suspending console(s) (use no_console_suspend to debug)
11452 12:15:41.300119 <6>[ 24.425319] Disabling non-boot CPUs ...
11453 12:15:41.303298 <6>[ 24.426308] psci: CPU1 killed (polled 0 ms)
11454 12:15:41.306841 <6>[ 24.427367] psci: CPU2 killed (polled 0 ms)
11455 12:15:41.313260 <6>[ 24.429450] psci: CPU3 killed (polled 0 ms)
11456 12:15:41.316535 <6>[ 24.429951] psci: CPU4 killed (polled 0 ms)
11457 12:15:41.319957 <6>[ 24.430584] psci: CPU5 killed (polled 0 ms)
11458 12:15:41.326595 <6>[ 24.431143] psci: CPU6 killed (polled 0 ms)
11459 12:15:41.329809 <6>[ 24.431724] psci: CPU7 killed (polled 0 ms)
11460 12:15:41.333506 <6>[ 24.432130] Enabling non-boot CPUs ...
11461 12:15:41.339731 <6>[ 24.432363] Detected VIPT I-cache on CPU1
11462 12:15:41.346656 <6>[ 24.432448] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11463 12:15:41.353042 <6>[ 24.432507] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11464 12:15:41.356892 <6>[ 24.433159] CPU1 is up
11465 12:15:41.359881 <6>[ 24.433297] Detected VIPT I-cache on CPU2
11466 12:15:41.366748 <6>[ 24.433353] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11467 12:15:41.373272 <6>[ 24.433391] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11468 12:15:41.376556 <6>[ 24.433918] CPU2 is up
11469 12:15:41.379929 <6>[ 24.434105] Detected VIPT I-cache on CPU3
11470 12:15:41.386509 <6>[ 24.434160] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11471 12:15:41.392954 <6>[ 24.434197] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11472 12:15:41.396513 <6>[ 24.434728] CPU3 is up
11473 12:15:41.400034 <6>[ 24.434852] Detected PIPT I-cache on CPU4
11474 12:15:41.410125 <6>[ 24.434874] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11475 12:15:41.416976 <6>[ 24.434888] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11476 12:15:41.417557 <6>[ 24.435162] CPU4 is up
11477 12:15:41.423477 <6>[ 24.435295] Detected PIPT I-cache on CPU5
11478 12:15:41.430082 <6>[ 24.435316] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11479 12:15:41.436499 <6>[ 24.435330] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11480 12:15:41.440069 <6>[ 24.435558] CPU5 is up
11481 12:15:41.443137 <6>[ 24.435680] Detected PIPT I-cache on CPU6
11482 12:15:41.449874 <6>[ 24.435701] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11483 12:15:41.456287 <6>[ 24.435714] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11484 12:15:41.459865 <6>[ 24.435948] CPU6 is up
11485 12:15:41.463157 <6>[ 24.436069] Detected PIPT I-cache on CPU7
11486 12:15:41.469968 <6>[ 24.436096] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11487 12:15:41.476387 <6>[ 24.436110] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11488 12:15:41.479639 <6>[ 24.436358] CPU7 is up
11489 12:15:41.483097 <6>[ 24.982255] OOM killer enabled.
11490 12:15:41.490036 <6>[ 24.985645] Restarting tasks ... done.
11491 12:15:41.493052 <5>[ 24.990044] random: crng reseeded on system resumption
11492 12:15:41.496480 <6>[ 24.996353] PM: suspend exit
11493 12:15:41.507003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-4 RESULT=pass>
11494 12:15:41.507908 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-4 RESULT=pass
11496 12:15:41.510730 rtcwake: assuming RTC uses UTC ...
11497 12:15:41.516670 rtcwake: wakeup from "mem" using rtc0 at Wed Jan 31 12:15:10 2024
11498 12:15:41.529400 <6>[ 25.026096] PM: suspend entry (deep)
11499 12:15:41.533048 <6>[ 25.029955] Filesystems sync: 0.000 seconds
11500 12:15:41.536186 <6>[ 25.034694] Freezing user space processes
11501 12:15:41.547263 <6>[ 25.040390] Freezing user space processes completed (elapsed 0.001 seconds)
11502 12:15:41.550429 <6>[ 25.047621] OOM killer disabled.
11503 12:15:41.553703 <6>[ 25.051107] Freezing remaining freezable tasks
11504 12:15:41.564014 <6>[ 25.057027] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11505 12:15:41.570778 <6>[ 25.064691] printk: Suspending console(s) (use no_console_suspend to debug)
11506 12:15:47.297990 <6>[ 25.149525] Disabling non-boot CPUs ...
11507 12:15:47.301582 <6>[ 25.150363] psci: CPU1 killed (polled 0 ms)
11508 12:15:47.304887 <6>[ 25.152401] psci: CPU2 killed (polled 0 ms)
11509 12:15:47.311577 <6>[ 25.153952] psci: CPU3 killed (polled 4 ms)
11510 12:15:47.314961 <6>[ 25.154395] psci: CPU4 killed (polled 0 ms)
11511 12:15:47.318271 <6>[ 25.154955] psci: CPU5 killed (polled 0 ms)
11512 12:15:47.324574 <6>[ 25.155463] psci: CPU6 killed (polled 0 ms)
11513 12:15:47.328474 <6>[ 25.155997] psci: CPU7 killed (polled 0 ms)
11514 12:15:47.331620 <6>[ 25.156353] Enabling non-boot CPUs ...
11515 12:15:47.338403 <6>[ 25.156559] Detected VIPT I-cache on CPU1
11516 12:15:47.344848 <6>[ 25.156636] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11517 12:15:47.351504 <6>[ 25.156689] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11518 12:15:47.354588 <6>[ 25.157240] CPU1 is up
11519 12:15:47.358025 <6>[ 25.157360] Detected VIPT I-cache on CPU2
11520 12:15:47.364262 <6>[ 25.157406] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11521 12:15:47.371111 <6>[ 25.157437] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11522 12:15:47.374185 <6>[ 25.157854] CPU2 is up
11523 12:15:47.377735 <6>[ 25.158013] Detected VIPT I-cache on CPU3
11524 12:15:47.384512 <6>[ 25.158059] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11525 12:15:47.390963 <6>[ 25.158089] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11526 12:15:47.394746 <6>[ 25.158520] CPU3 is up
11527 12:15:47.401515 <6>[ 25.158636] Detected PIPT I-cache on CPU4
11528 12:15:47.407718 <6>[ 25.158657] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11529 12:15:47.414734 <6>[ 25.158671] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11530 12:15:47.417683 <6>[ 25.158934] CPU4 is up
11531 12:15:47.421207 <6>[ 25.159047] Detected PIPT I-cache on CPU5
11532 12:15:47.427976 <6>[ 25.159069] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11533 12:15:47.434589 <6>[ 25.159084] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11534 12:15:47.438207 <6>[ 25.159308] CPU5 is up
11535 12:15:47.441029 <6>[ 25.159416] Detected PIPT I-cache on CPU6
11536 12:15:47.447996 <6>[ 25.159438] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11537 12:15:47.454510 <6>[ 25.159452] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11538 12:15:47.457456 <6>[ 25.159693] CPU6 is up
11539 12:15:47.464313 <6>[ 25.159812] Detected PIPT I-cache on CPU7
11540 12:15:47.470672 <6>[ 25.159840] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11541 12:15:47.477743 <6>[ 25.159854] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11542 12:15:47.480734 <6>[ 25.160089] CPU7 is up
11543 12:15:47.483885 <6>[ 25.706003] OOM killer enabled.
11544 12:15:47.487272 <6>[ 25.709393] Restarting tasks ... done.
11545 12:15:47.494032 <5>[ 25.713768] random: crng reseeded on system resumption
11546 12:15:47.497044 <6>[ 25.720062] PM: suspend exit
11547 12:15:47.505892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-5 RESULT=pass>
11548 12:15:47.506819 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-5 RESULT=pass
11550 12:15:47.509501 rtcwake: assuming RTC uses UTC ...
11551 12:15:47.515998 rtcwake: wakeup from "mem" using rtc0 at Wed Jan 31 12:15:16 2024
11552 12:15:47.528778 <6>[ 25.750028] PM: suspend entry (deep)
11553 12:15:47.531908 <6>[ 25.753879] Filesystems sync: 0.000 seconds
11554 12:15:47.535100 <6>[ 25.758624] Freezing user space processes
11555 12:15:47.546168 <6>[ 25.764287] Freezing user space processes completed (elapsed 0.001 seconds)
11556 12:15:47.549442 <6>[ 25.771520] OOM killer disabled.
11557 12:15:47.552735 <6>[ 25.775004] Freezing remaining freezable tasks
11558 12:15:47.562460 <6>[ 25.780931] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11559 12:15:47.569182 <6>[ 25.788594] printk: Suspending console(s) (use no_console_suspend to debug)
11560 12:15:53.290360 <6>[ 25.861031] Disabling non-boot CPUs ...
11561 12:15:53.293151 <6>[ 25.861830] psci: CPU1 killed (polled 0 ms)
11562 12:15:53.296773 <6>[ 25.863848] psci: CPU2 killed (polled 0 ms)
11563 12:15:53.303203 <6>[ 25.865670] psci: CPU3 killed (polled 0 ms)
11564 12:15:53.306134 <6>[ 25.866111] psci: CPU4 killed (polled 0 ms)
11565 12:15:53.309684 <6>[ 25.866670] psci: CPU5 killed (polled 0 ms)
11566 12:15:53.316611 <6>[ 25.867207] psci: CPU6 killed (polled 0 ms)
11567 12:15:53.320168 <6>[ 25.867691] psci: CPU7 killed (polled 0 ms)
11568 12:15:53.323280 <6>[ 25.868024] Enabling non-boot CPUs ...
11569 12:15:53.330075 <6>[ 25.868232] Detected VIPT I-cache on CPU1
11570 12:15:53.336884 <6>[ 25.868307] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11571 12:15:53.343399 <6>[ 25.868360] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11572 12:15:53.346540 <6>[ 25.868911] CPU1 is up
11573 12:15:53.350086 <6>[ 25.869032] Detected VIPT I-cache on CPU2
11574 12:15:53.356766 <6>[ 25.869078] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11575 12:15:53.363132 <6>[ 25.869109] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11576 12:15:53.366575 <6>[ 25.869529] CPU2 is up
11577 12:15:53.369854 <6>[ 25.869647] Detected VIPT I-cache on CPU3
11578 12:15:53.376972 <6>[ 25.869693] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11579 12:15:53.383165 <6>[ 25.869723] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11580 12:15:53.386758 <6>[ 25.870170] CPU3 is up
11581 12:15:53.390212 <6>[ 25.870285] Detected PIPT I-cache on CPU4
11582 12:15:53.399803 <6>[ 25.870307] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11583 12:15:53.406750 <6>[ 25.870321] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11584 12:15:53.407459 <6>[ 25.870591] CPU4 is up
11585 12:15:53.413206 <6>[ 25.870712] Detected PIPT I-cache on CPU5
11586 12:15:53.419735 <6>[ 25.870733] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11587 12:15:53.426465 <6>[ 25.870747] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11588 12:15:53.429521 <6>[ 25.870969] CPU5 is up
11589 12:15:53.433133 <6>[ 25.871079] Detected PIPT I-cache on CPU6
11590 12:15:53.439592 <6>[ 25.871100] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11591 12:15:53.446583 <6>[ 25.871114] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11592 12:15:53.449634 <6>[ 25.871347] CPU6 is up
11593 12:15:53.452690 <6>[ 25.871457] Detected PIPT I-cache on CPU7
11594 12:15:53.463169 <6>[ 25.871485] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11595 12:15:53.469835 <6>[ 25.871498] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11596 12:15:53.470441 <6>[ 25.871735] CPU7 is up
11597 12:15:53.473043 <6>[ 26.409947] OOM killer enabled.
11598 12:15:53.479615 <6>[ 26.413337] Restarting tasks ... done.
11599 12:15:53.482984 <5>[ 26.417713] random: crng reseeded on system resumption
11600 12:15:53.486852 <6>[ 26.423924] PM: suspend exit
11601 12:15:53.495933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-6 RESULT=pass>
11602 12:15:53.496803 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-6 RESULT=pass
11604 12:15:53.499277 rtcwake: assuming RTC uses UTC ...
11605 12:15:53.505862 rtcwake: wakeup from "mem" using rtc0 at Wed Jan 31 12:15:22 2024
11606 12:15:53.518334 <6>[ 26.452403] PM: suspend entry (deep)
11607 12:15:53.521496 <6>[ 26.456272] Filesystems sync: 0.000 seconds
11608 12:15:53.524593 <6>[ 26.460998] Freezing user space processes
11609 12:15:53.535953 <6>[ 26.466589] Freezing user space processes completed (elapsed 0.001 seconds)
11610 12:15:53.538948 <6>[ 26.473811] OOM killer disabled.
11611 12:15:53.543157 <6>[ 26.477291] Freezing remaining freezable tasks
11612 12:15:53.552388 <6>[ 26.483198] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11613 12:15:53.559230 <6>[ 26.490861] printk: Suspending console(s) (use no_console_suspend to debug)
11614 12:15:59.288575 <6>[ 26.565393] Disabling non-boot CPUs ...
11615 12:15:59.291618 <6>[ 26.566260] psci: CPU1 killed (polled 0 ms)
11616 12:15:59.295084 <6>[ 26.568184] psci: CPU2 killed (polled 0 ms)
11617 12:15:59.301523 <6>[ 26.569871] psci: CPU3 killed (polled 4 ms)
11618 12:15:59.305061 <6>[ 26.570338] psci: CPU4 killed (polled 0 ms)
11619 12:15:59.308430 <6>[ 26.570905] psci: CPU5 killed (polled 0 ms)
11620 12:15:59.315337 <6>[ 26.571448] psci: CPU6 killed (polled 0 ms)
11621 12:15:59.318250 <6>[ 26.571990] psci: CPU7 killed (polled 0 ms)
11622 12:15:59.321862 <6>[ 26.572392] Enabling non-boot CPUs ...
11623 12:15:59.328433 <6>[ 26.572601] Detected VIPT I-cache on CPU1
11624 12:15:59.335285 <6>[ 26.572677] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11625 12:15:59.342140 <6>[ 26.572731] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11626 12:15:59.342716 <6>[ 26.573289] CPU1 is up
11627 12:15:59.348729 <6>[ 26.573410] Detected VIPT I-cache on CPU2
11628 12:15:59.355585 <6>[ 26.573456] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11629 12:15:59.362203 <6>[ 26.573487] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11630 12:15:59.365791 <6>[ 26.573943] CPU2 is up
11631 12:15:59.368670 <6>[ 26.574063] Detected VIPT I-cache on CPU3
11632 12:15:59.375573 <6>[ 26.574109] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11633 12:15:59.381980 <6>[ 26.574140] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11634 12:15:59.385585 <6>[ 26.574593] CPU3 is up
11635 12:15:59.388650 <6>[ 26.574709] Detected PIPT I-cache on CPU4
11636 12:15:59.398504 <6>[ 26.574732] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11637 12:15:59.404958 <6>[ 26.574747] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11638 12:15:59.405451 <6>[ 26.575024] CPU4 is up
11639 12:15:59.411950 <6>[ 26.575147] Detected PIPT I-cache on CPU5
11640 12:15:59.418529 <6>[ 26.575170] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11641 12:15:59.425260 <6>[ 26.575184] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11642 12:15:59.428296 <6>[ 26.575414] CPU5 is up
11643 12:15:59.431603 <6>[ 26.575527] Detected PIPT I-cache on CPU6
11644 12:15:59.438633 <6>[ 26.575549] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11645 12:15:59.445248 <6>[ 26.575563] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11646 12:15:59.448536 <6>[ 26.575800] CPU6 is up
11647 12:15:59.451636 <6>[ 26.575912] Detected PIPT I-cache on CPU7
11648 12:15:59.458118 <6>[ 26.575941] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11649 12:15:59.468343 <6>[ 26.575955] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11650 12:15:59.468933 <6>[ 26.576204] CPU7 is up
11651 12:15:59.471720 <6>[ 27.113810] OOM killer enabled.
11652 12:15:59.478629 <6>[ 27.117200] Restarting tasks ... done.
11653 12:15:59.481681 <5>[ 27.121587] random: crng reseeded on system resumption
11654 12:15:59.485852 <6>[ 27.128432] PM: suspend exit
11655 12:15:59.496086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-7 RESULT=pass>
11656 12:15:59.496983 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-7 RESULT=pass
11658 12:15:59.499756 rtcwake: assuming RTC uses UTC ...
11659 12:15:59.506228 rtcwake: wakeup from "mem" using rtc0 at Wed Jan 31 12:15:28 2024
11660 12:15:59.518812 <6>[ 27.158119] PM: suspend entry (deep)
11661 12:15:59.522032 <6>[ 27.161987] Filesystems sync: 0.000 seconds
11662 12:15:59.525500 <6>[ 27.166756] Freezing user space processes
11663 12:15:59.536513 <6>[ 27.172458] Freezing user space processes completed (elapsed 0.001 seconds)
11664 12:15:59.539594 <6>[ 27.179694] OOM killer disabled.
11665 12:15:59.543038 <6>[ 27.183181] Freezing remaining freezable tasks
11666 12:15:59.553242 <6>[ 27.189093] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11667 12:15:59.559984 <6>[ 27.196763] printk: Suspending console(s) (use no_console_suspend to debug)
11668 12:16:05.291973 <6>[ 27.281360] Disabling non-boot CPUs ...
11669 12:16:05.295207 <4>[ 27.282161] migrate_one_irq: 88 callbacks suppressed
11670 12:16:05.301786 <4>[ 27.282171] IRQ282: set affinity failed(-22).
11671 12:16:05.304842 <4>[ 27.282179] IRQ284: set affinity failed(-22).
11672 12:16:05.308345 <6>[ 27.283248] psci: CPU1 killed (polled 0 ms)
11673 12:16:05.314939 <4>[ 27.284220] IRQ282: set affinity failed(-22).
11674 12:16:05.318314 <4>[ 27.284229] IRQ284: set affinity failed(-22).
11675 12:16:05.321885 <6>[ 27.284280] psci: CPU2 killed (polled 0 ms)
11676 12:16:05.328709 <4>[ 27.285013] IRQ282: set affinity failed(-22).
11677 12:16:05.332004 <4>[ 27.285022] IRQ284: set affinity failed(-22).
11678 12:16:05.338377 <6>[ 27.285831] psci: CPU3 killed (polled 4 ms)
11679 12:16:05.341741 <4>[ 27.286328] IRQ282: set affinity failed(-22).
11680 12:16:05.345247 <4>[ 27.286333] IRQ284: set affinity failed(-22).
11681 12:16:05.351794 <6>[ 27.286360] psci: CPU4 killed (polled 0 ms)
11682 12:16:05.355019 <4>[ 27.286905] IRQ282: set affinity failed(-22).
11683 12:16:05.358657 <4>[ 27.286911] IRQ284: set affinity failed(-22).
11684 12:16:05.365404 <6>[ 27.286940] psci: CPU5 killed (polled 0 ms)
11685 12:16:05.368941 <6>[ 27.287456] psci: CPU6 killed (polled 0 ms)
11686 12:16:05.371610 <6>[ 27.287996] psci: CPU7 killed (polled 0 ms)
11687 12:16:05.378401 <6>[ 27.288387] Enabling non-boot CPUs ...
11688 12:16:05.381749 <6>[ 27.288599] Detected VIPT I-cache on CPU1
11689 12:16:05.388624 <6>[ 27.288674] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11690 12:16:05.395237 <6>[ 27.288727] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11691 12:16:05.398262 <6>[ 27.289273] CPU1 is up
11692 12:16:05.401914 <6>[ 27.289393] Detected VIPT I-cache on CPU2
11693 12:16:05.408597 <6>[ 27.289439] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11694 12:16:05.415114 <6>[ 27.289471] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11695 12:16:05.418601 <6>[ 27.289925] CPU2 is up
11696 12:16:05.425390 <6>[ 27.290045] Detected VIPT I-cache on CPU3
11697 12:16:05.431714 <6>[ 27.290091] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11698 12:16:05.439115 <6>[ 27.290122] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11699 12:16:05.439688 <6>[ 27.290551] CPU3 is up
11700 12:16:05.444910 <6>[ 27.290666] Detected PIPT I-cache on CPU4
11701 12:16:05.452171 <6>[ 27.290689] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11702 12:16:05.458631 <6>[ 27.290704] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11703 12:16:05.461813 <6>[ 27.290974] CPU4 is up
11704 12:16:05.465232 <6>[ 27.291087] Detected PIPT I-cache on CPU5
11705 12:16:05.471860 <6>[ 27.291110] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11706 12:16:05.478660 <6>[ 27.291125] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11707 12:16:05.481563 <6>[ 27.291362] CPU5 is up
11708 12:16:05.485312 <6>[ 27.291481] Detected PIPT I-cache on CPU6
11709 12:16:05.495369 <6>[ 27.291503] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11710 12:16:05.501715 <6>[ 27.291518] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11711 12:16:05.502345 <6>[ 27.291763] CPU6 is up
11712 12:16:05.508257 <6>[ 27.291873] Detected PIPT I-cache on CPU7
11713 12:16:05.515275 <6>[ 27.291902] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11714 12:16:05.521424 <6>[ 27.291917] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11715 12:16:05.524865 <6>[ 27.292168] CPU7 is up
11716 12:16:05.528244 <6>[ 27.885170] OOM killer enabled.
11717 12:16:05.531345 <6>[ 27.888562] Restarting tasks ... done.
11718 12:16:05.538438 <5>[ 27.892950] random: crng reseeded on system resumption
11719 12:16:05.541436 <6>[ 27.899201] PM: suspend exit
11720 12:16:05.549913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-8 RESULT=pass>
11721 12:16:05.550849 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-8 RESULT=pass
11723 12:16:05.553230 rtcwake: assuming RTC uses UTC ...
11724 12:16:05.559870 rtcwake: wakeup from "mem" using rtc0 at Wed Jan 31 12:15:34 2024
11725 12:16:05.572607 <6>[ 27.928853] PM: suspend entry (deep)
11726 12:16:05.575871 <6>[ 27.932712] Filesystems sync: 0.000 seconds
11727 12:16:05.579046 <6>[ 27.937476] Freezing user space processes
11728 12:16:05.590320 <6>[ 27.943203] Freezing user space processes completed (elapsed 0.001 seconds)
11729 12:16:05.593892 <6>[ 27.950445] OOM killer disabled.
11730 12:16:05.597244 <6>[ 27.953932] Freezing remaining freezable tasks
11731 12:16:05.607068 <6>[ 27.959847] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11732 12:16:05.613606 <6>[ 27.967515] printk: Suspending console(s) (use no_console_suspend to debug)
11733 12:16:11.294934 <6>[ 28.042351] Disabling non-boot CPUs ...
11734 12:16:11.298343 <6>[ 28.043190] psci: CPU1 killed (polled 0 ms)
11735 12:16:11.301896 <6>[ 28.044083] psci: CPU2 killed (polled 0 ms)
11736 12:16:11.307903 <6>[ 28.045796] psci: CPU3 killed (polled 4 ms)
11737 12:16:11.311499 <6>[ 28.046271] psci: CPU4 killed (polled 0 ms)
11738 12:16:11.315013 <6>[ 28.046832] psci: CPU5 killed (polled 0 ms)
11739 12:16:11.321546 <6>[ 28.047356] psci: CPU6 killed (polled 0 ms)
11740 12:16:11.324981 <6>[ 28.047879] psci: CPU7 killed (polled 0 ms)
11741 12:16:11.327922 <6>[ 28.048238] Enabling non-boot CPUs ...
11742 12:16:11.334649 <6>[ 28.048446] Detected VIPT I-cache on CPU1
11743 12:16:11.341818 <6>[ 28.048524] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11744 12:16:11.348115 <6>[ 28.048577] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11745 12:16:11.351602 <6>[ 28.049133] CPU1 is up
11746 12:16:11.354680 <6>[ 28.049252] Detected VIPT I-cache on CPU2
11747 12:16:11.361756 <6>[ 28.049298] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11748 12:16:11.368274 <6>[ 28.049330] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11749 12:16:11.371217 <6>[ 28.049786] CPU2 is up
11750 12:16:11.374898 <6>[ 28.049909] Detected VIPT I-cache on CPU3
11751 12:16:11.381319 <6>[ 28.049954] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11752 12:16:11.388184 <6>[ 28.049985] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11753 12:16:11.391468 <6>[ 28.050407] CPU3 is up
11754 12:16:11.394688 <6>[ 28.050522] Detected PIPT I-cache on CPU4
11755 12:16:11.404780 <6>[ 28.050544] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11756 12:16:11.411022 <6>[ 28.050560] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11757 12:16:11.414675 <6>[ 28.050842] CPU4 is up
11758 12:16:11.417697 <6>[ 28.050965] Detected PIPT I-cache on CPU5
11759 12:16:11.425073 <6>[ 28.050988] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11760 12:16:11.431266 <6>[ 28.051003] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11761 12:16:11.434899 <6>[ 28.051235] CPU5 is up
11762 12:16:11.438364 <6>[ 28.051348] Detected PIPT I-cache on CPU6
11763 12:16:11.444655 <6>[ 28.051370] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11764 12:16:11.451370 <6>[ 28.051385] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11765 12:16:11.454817 <6>[ 28.051626] CPU6 is up
11766 12:16:11.458316 <6>[ 28.051738] Detected PIPT I-cache on CPU7
11767 12:16:11.467956 <6>[ 28.051767] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11768 12:16:11.475148 <6>[ 28.051781] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11769 12:16:11.475737 <6>[ 28.052027] CPU7 is up
11770 12:16:11.478079 <6>[ 28.597786] OOM killer enabled.
11771 12:16:11.484893 <6>[ 28.601176] Restarting tasks ... done.
11772 12:16:11.487717 <5>[ 28.605575] random: crng reseeded on system resumption
11773 12:16:11.491498 <6>[ 28.611896] PM: suspend exit
11774 12:16:11.502123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-9 RESULT=pass>
11775 12:16:11.502987 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-9 RESULT=pass
11777 12:16:11.505586 rtcwake: assuming RTC uses UTC ...
11778 12:16:11.511779 rtcwake: wakeup from "mem" using rtc0 at Wed Jan 31 12:15:40 2024
11779 12:16:11.524383 <6>[ 28.641771] PM: suspend entry (deep)
11780 12:16:11.527942 <6>[ 28.645625] Filesystems sync: 0.000 seconds
11781 12:16:11.531223 <6>[ 28.650371] Freezing user space processes
11782 12:16:11.542267 <6>[ 28.656073] Freezing user space processes completed (elapsed 0.001 seconds)
11783 12:16:11.545580 <6>[ 28.663307] OOM killer disabled.
11784 12:16:11.548662 <6>[ 28.666790] Freezing remaining freezable tasks
11785 12:16:11.559119 <6>[ 28.672720] Freezing remaining freezable tasks completed (elapsed 0.001 seconds)
11786 12:16:11.565546 <6>[ 28.680387] printk: Suspending console(s) (use no_console_suspend to debug)
11787 12:16:17.288496 <6>[ 28.755291] Disabling non-boot CPUs ...
11788 12:16:17.291643 <6>[ 28.756238] psci: CPU1 killed (polled 0 ms)
11789 12:16:17.295094 <6>[ 28.757319] psci: CPU2 killed (polled 0 ms)
11790 12:16:17.301603 <6>[ 28.759253] psci: CPU3 killed (polled 0 ms)
11791 12:16:17.304911 <6>[ 28.759896] psci: CPU4 killed (polled 0 ms)
11792 12:16:17.308234 <6>[ 28.760541] psci: CPU5 killed (polled 0 ms)
11793 12:16:17.314856 <6>[ 28.761094] psci: CPU6 killed (polled 0 ms)
11794 12:16:17.318462 <6>[ 28.761622] psci: CPU7 killed (polled 0 ms)
11795 12:16:17.321419 <6>[ 28.762008] Enabling non-boot CPUs ...
11796 12:16:17.328198 <6>[ 28.762236] Detected VIPT I-cache on CPU1
11797 12:16:17.334865 <6>[ 28.762322] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
11798 12:16:17.341461 <6>[ 28.762381] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
11799 12:16:17.345064 <6>[ 28.763030] CPU1 is up
11800 12:16:17.348399 <6>[ 28.763169] Detected VIPT I-cache on CPU2
11801 12:16:17.354418 <6>[ 28.763225] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
11802 12:16:17.362038 <6>[ 28.763262] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
11803 12:16:17.364728 <6>[ 28.763792] CPU2 is up
11804 12:16:17.368286 <6>[ 28.763925] Detected VIPT I-cache on CPU3
11805 12:16:17.374937 <6>[ 28.763980] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
11806 12:16:17.381549 <6>[ 28.764016] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
11807 12:16:17.384991 <6>[ 28.764538] CPU3 is up
11808 12:16:17.391492 <6>[ 28.764662] Detected PIPT I-cache on CPU4
11809 12:16:17.397854 <6>[ 28.764684] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
11810 12:16:17.404343 <6>[ 28.764699] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
11811 12:16:17.407529 <6>[ 28.764979] CPU4 is up
11812 12:16:17.410863 <6>[ 28.765112] Detected PIPT I-cache on CPU5
11813 12:16:17.417675 <6>[ 28.765134] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
11814 12:16:17.424366 <6>[ 28.765148] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
11815 12:16:17.427744 <6>[ 28.765375] CPU5 is up
11816 12:16:17.431239 <6>[ 28.765497] Detected PIPT I-cache on CPU6
11817 12:16:17.437709 <6>[ 28.765518] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
11818 12:16:17.444591 <6>[ 28.765532] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
11819 12:16:17.447364 <6>[ 28.765794] CPU6 is up
11820 12:16:17.451067 <6>[ 28.765917] Detected PIPT I-cache on CPU7
11821 12:16:17.461216 <6>[ 28.765945] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
11822 12:16:17.468020 <6>[ 28.765959] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
11823 12:16:17.470795 <6>[ 28.766204] CPU7 is up
11824 12:16:17.471344 <6>[ 29.305862] OOM killer enabled.
11825 12:16:17.478348 <6>[ 29.309252] Restarting tasks ... done.
11826 12:16:17.481304 <5>[ 29.313630] random: crng reseeded on system resumption
11827 12:16:17.485360 <6>[ 29.319994] PM: suspend exit
11828 12:16:17.495941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtcwake-mem-10 RESULT=pass>
11829 12:16:17.496523 + set +x
11830 12:16:17.497208 Received signal: <TESTCASE> TEST_CASE_ID=rtcwake-mem-10 RESULT=pass
11832 12:16:17.502169 <LAVA_SIGNAL_ENDRUN 0_sleep 12669505_1.5.2.3.1>
11833 12:16:17.502757 <LAVA_TEST_RUNNER EXIT>
11834 12:16:17.503410 Received signal: <ENDRUN> 0_sleep 12669505_1.5.2.3.1
11835 12:16:17.503837 Ending use of test pattern.
11836 12:16:17.504189 Ending test lava.0_sleep (12669505_1.5.2.3.1), duration 60.28
11838 12:16:17.505421 ok: lava_test_shell seems to have completed
11839 12:16:17.506241 rtc-exist: pass
rtc-wakeup-enabled: pass
rtcwake-mem-1: pass
rtcwake-mem-10: pass
rtcwake-mem-2: pass
rtcwake-mem-3: pass
rtcwake-mem-4: pass
rtcwake-mem-5: pass
rtcwake-mem-6: pass
rtcwake-mem-7: pass
rtcwake-mem-8: pass
rtcwake-mem-9: pass
11840 12:16:17.506728 end: 3.1 lava-test-shell (duration 00:01:01) [common]
11841 12:16:17.507187 end: 3 lava-test-retry (duration 00:01:01) [common]
11842 12:16:17.507672 start: 4 finalize (timeout 00:06:16) [common]
11843 12:16:17.508155 start: 4.1 power-off (timeout 00:00:30) [common]
11844 12:16:17.509023 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11845 12:16:17.633101 >> Command sent successfully.
11846 12:16:17.643348 Returned 0 in 0 seconds
11847 12:16:17.744693 end: 4.1 power-off (duration 00:00:00) [common]
11849 12:16:17.746333 start: 4.2 read-feedback (timeout 00:06:15) [common]
11850 12:16:17.747735 Listened to connection for namespace 'common' for up to 1s
11851 12:16:18.748285 Finalising connection for namespace 'common'
11852 12:16:18.749034 Disconnecting from shell: Finalise
11853 12:16:18.749472 / #
11854 12:16:18.850541 end: 4.2 read-feedback (duration 00:00:01) [common]
11855 12:16:18.851244 end: 4 finalize (duration 00:00:01) [common]
11856 12:16:18.851849 Cleaning after the job
11857 12:16:18.852404 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669505/tftp-deploy-kbhi3sxt/ramdisk
11858 12:16:18.891852 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669505/tftp-deploy-kbhi3sxt/kernel
11859 12:16:18.917455 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669505/tftp-deploy-kbhi3sxt/dtb
11860 12:16:18.917697 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669505/tftp-deploy-kbhi3sxt/modules
11861 12:16:18.923409 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12669505
11862 12:16:19.061750 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12669505
11863 12:16:19.062191 Job finished correctly