Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 1
- Kernel Warnings: 13
- Kernel Errors: 34
1 12:16:54.499777 lava-dispatcher, installed at version: 2023.10
2 12:16:54.500015 start: 0 validate
3 12:16:54.500150 Start time: 2024-01-31 12:16:54.500142+00:00 (UTC)
4 12:16:54.500279 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:16:54.500462 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:16:54.767029 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:16:54.767261 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:16:55.031710 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:16:55.031930 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:16:55.304849 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:16:55.305440 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:16:55.585308 validate duration: 1.09
14 12:16:55.585669 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:16:55.585805 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:16:55.585923 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:16:55.586085 Not decompressing ramdisk as can be used compressed.
18 12:16:55.586207 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 12:16:55.586314 saving as /var/lib/lava/dispatcher/tmp/12669521/tftp-deploy-8bw6ikvl/ramdisk/rootfs.cpio.gz
20 12:16:55.586407 total size: 34390042 (32 MB)
21 12:16:55.588012 progress 0 % (0 MB)
22 12:16:55.597907 progress 5 % (1 MB)
23 12:16:55.606881 progress 10 % (3 MB)
24 12:16:55.616722 progress 15 % (4 MB)
25 12:16:55.626864 progress 20 % (6 MB)
26 12:16:55.636107 progress 25 % (8 MB)
27 12:16:55.646917 progress 30 % (9 MB)
28 12:16:55.656610 progress 35 % (11 MB)
29 12:16:55.665997 progress 40 % (13 MB)
30 12:16:55.675552 progress 45 % (14 MB)
31 12:16:55.686190 progress 50 % (16 MB)
32 12:16:55.697581 progress 55 % (18 MB)
33 12:16:55.709023 progress 60 % (19 MB)
34 12:16:55.718618 progress 65 % (21 MB)
35 12:16:55.728016 progress 70 % (22 MB)
36 12:16:55.739673 progress 75 % (24 MB)
37 12:16:55.751020 progress 80 % (26 MB)
38 12:16:55.760241 progress 85 % (27 MB)
39 12:16:55.770115 progress 90 % (29 MB)
40 12:16:55.779312 progress 95 % (31 MB)
41 12:16:55.788672 progress 100 % (32 MB)
42 12:16:55.788863 32 MB downloaded in 0.20 s (162.00 MB/s)
43 12:16:55.789022 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:16:55.789277 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:16:55.789364 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:16:55.789447 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:16:55.789588 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:16:55.789660 saving as /var/lib/lava/dispatcher/tmp/12669521/tftp-deploy-8bw6ikvl/kernel/Image
50 12:16:55.789722 total size: 51532288 (49 MB)
51 12:16:55.789783 No compression specified
52 12:16:55.790936 progress 0 % (0 MB)
53 12:16:55.806837 progress 5 % (2 MB)
54 12:16:55.821865 progress 10 % (4 MB)
55 12:16:55.836712 progress 15 % (7 MB)
56 12:16:55.851821 progress 20 % (9 MB)
57 12:16:55.867166 progress 25 % (12 MB)
58 12:16:55.882127 progress 30 % (14 MB)
59 12:16:55.897106 progress 35 % (17 MB)
60 12:16:55.912269 progress 40 % (19 MB)
61 12:16:55.927236 progress 45 % (22 MB)
62 12:16:55.942563 progress 50 % (24 MB)
63 12:16:55.957429 progress 55 % (27 MB)
64 12:16:55.972638 progress 60 % (29 MB)
65 12:16:55.987324 progress 65 % (31 MB)
66 12:16:56.001531 progress 70 % (34 MB)
67 12:16:56.016224 progress 75 % (36 MB)
68 12:16:56.031500 progress 80 % (39 MB)
69 12:16:56.046342 progress 85 % (41 MB)
70 12:16:56.061564 progress 90 % (44 MB)
71 12:16:56.076589 progress 95 % (46 MB)
72 12:16:56.092142 progress 100 % (49 MB)
73 12:16:56.092440 49 MB downloaded in 0.30 s (162.35 MB/s)
74 12:16:56.092596 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:16:56.092824 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:16:56.092914 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:16:56.093002 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:16:56.093140 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:16:56.093209 saving as /var/lib/lava/dispatcher/tmp/12669521/tftp-deploy-8bw6ikvl/dtb/mt8192-asurada-spherion-r0.dtb
81 12:16:56.093282 total size: 47278 (0 MB)
82 12:16:56.093353 No compression specified
83 12:16:56.094984 progress 69 % (0 MB)
84 12:16:56.095288 progress 100 % (0 MB)
85 12:16:56.095470 0 MB downloaded in 0.00 s (20.62 MB/s)
86 12:16:56.095637 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:16:56.095987 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:16:56.096100 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:16:56.096211 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:16:56.096419 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:16:56.096491 saving as /var/lib/lava/dispatcher/tmp/12669521/tftp-deploy-8bw6ikvl/modules/modules.tar
93 12:16:56.096551 total size: 8639916 (8 MB)
94 12:16:56.096611 Using unxz to decompress xz
95 12:16:56.101695 progress 0 % (0 MB)
96 12:16:56.123031 progress 5 % (0 MB)
97 12:16:56.147910 progress 10 % (0 MB)
98 12:16:56.172653 progress 15 % (1 MB)
99 12:16:56.196469 progress 20 % (1 MB)
100 12:16:56.220898 progress 25 % (2 MB)
101 12:16:56.248951 progress 30 % (2 MB)
102 12:16:56.273730 progress 35 % (2 MB)
103 12:16:56.297333 progress 40 % (3 MB)
104 12:16:56.322191 progress 45 % (3 MB)
105 12:16:56.347916 progress 50 % (4 MB)
106 12:16:56.374511 progress 55 % (4 MB)
107 12:16:56.399784 progress 60 % (4 MB)
108 12:16:56.425997 progress 65 % (5 MB)
109 12:16:56.451375 progress 70 % (5 MB)
110 12:16:56.475192 progress 75 % (6 MB)
111 12:16:56.502769 progress 80 % (6 MB)
112 12:16:56.530975 progress 85 % (7 MB)
113 12:16:56.556237 progress 90 % (7 MB)
114 12:16:56.586434 progress 95 % (7 MB)
115 12:16:56.614770 progress 100 % (8 MB)
116 12:16:56.620804 8 MB downloaded in 0.52 s (15.72 MB/s)
117 12:16:56.621062 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:16:56.621370 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:16:56.621476 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:16:56.621589 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:16:56.621673 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:16:56.621785 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:16:56.622042 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4
125 12:16:56.622241 makedir: /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin
126 12:16:56.622388 makedir: /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/tests
127 12:16:56.622538 makedir: /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/results
128 12:16:56.622691 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-add-keys
129 12:16:56.622891 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-add-sources
130 12:16:56.623074 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-background-process-start
131 12:16:56.623254 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-background-process-stop
132 12:16:56.623430 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-common-functions
133 12:16:56.623600 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-echo-ipv4
134 12:16:56.623774 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-install-packages
135 12:16:56.623945 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-installed-packages
136 12:16:56.624106 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-os-build
137 12:16:56.624281 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-probe-channel
138 12:16:56.624464 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-probe-ip
139 12:16:56.624633 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-target-ip
140 12:16:56.624807 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-target-mac
141 12:16:56.624979 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-target-storage
142 12:16:56.625146 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-test-case
143 12:16:56.625325 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-test-event
144 12:16:56.625506 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-test-feedback
145 12:16:56.625714 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-test-raise
146 12:16:56.625880 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-test-reference
147 12:16:56.626082 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-test-runner
148 12:16:56.626252 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-test-set
149 12:16:56.626417 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-test-shell
150 12:16:56.626594 Updating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-install-packages (oe)
151 12:16:56.626776 Updating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/bin/lava-installed-packages (oe)
152 12:16:56.626946 Creating /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/environment
153 12:16:56.627093 LAVA metadata
154 12:16:56.627173 - LAVA_JOB_ID=12669521
155 12:16:56.627281 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:16:56.627417 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:16:56.627486 skipped lava-vland-overlay
158 12:16:56.627562 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:16:56.627645 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:16:56.627732 skipped lava-multinode-overlay
161 12:16:56.627809 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:16:56.627946 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:16:56.628029 Loading test definitions
164 12:16:56.628172 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:16:56.628281 Using /lava-12669521 at stage 0
166 12:16:56.628617 uuid=12669521_1.5.2.3.1 testdef=None
167 12:16:56.628722 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:16:56.628812 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:16:56.629466 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:16:56.629806 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:16:56.630629 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:16:56.631038 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:16:56.631932 runner path: /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/0/tests/0_cros-ec test_uuid 12669521_1.5.2.3.1
176 12:16:56.632113 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:16:56.632435 Creating lava-test-runner.conf files
179 12:16:56.632540 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12669521/lava-overlay-uvkd3fy4/lava-12669521/0 for stage 0
180 12:16:56.632640 - 0_cros-ec
181 12:16:56.632744 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:16:56.632831 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:16:56.640845 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:16:56.640988 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:16:56.641077 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:16:56.641171 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:16:56.641264 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:16:57.676027 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:16:57.676456 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:16:57.676579 extracting modules file /var/lib/lava/dispatcher/tmp/12669521/tftp-deploy-8bw6ikvl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12669521/extract-overlay-ramdisk-lbt8ausp/ramdisk
191 12:16:57.933456 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:16:57.933607 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 12:16:57.933698 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12669521/compress-overlay-227uirfa/overlay-1.5.2.4.tar.gz to ramdisk
194 12:16:57.933768 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12669521/compress-overlay-227uirfa/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12669521/extract-overlay-ramdisk-lbt8ausp/ramdisk
195 12:16:57.940590 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:16:57.940705 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 12:16:57.940797 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:16:57.940890 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 12:16:57.940968 Building ramdisk /var/lib/lava/dispatcher/tmp/12669521/extract-overlay-ramdisk-lbt8ausp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12669521/extract-overlay-ramdisk-lbt8ausp/ramdisk
200 12:16:58.660751 >> 271082 blocks
201 12:17:03.391724 rename /var/lib/lava/dispatcher/tmp/12669521/extract-overlay-ramdisk-lbt8ausp/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12669521/tftp-deploy-8bw6ikvl/ramdisk/ramdisk.cpio.gz
202 12:17:03.392170 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 12:17:03.392303 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 12:17:03.392409 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 12:17:03.392509 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12669521/tftp-deploy-8bw6ikvl/kernel/Image'
206 12:17:16.141539 Returned 0 in 12 seconds
207 12:17:16.242207 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12669521/tftp-deploy-8bw6ikvl/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12669521/tftp-deploy-8bw6ikvl/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12669521/tftp-deploy-8bw6ikvl/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12669521/tftp-deploy-8bw6ikvl/kernel/image.itb
208 12:17:16.982885 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:17:16.983267 output: Created: Wed Jan 31 12:17:16 2024
210 12:17:16.983340 output: Image 0 (kernel-1)
211 12:17:16.983407 output: Description:
212 12:17:16.983470 output: Created: Wed Jan 31 12:17:16 2024
213 12:17:16.983556 output: Type: Kernel Image
214 12:17:16.983618 output: Compression: lzma compressed
215 12:17:16.983680 output: Data Size: 12047284 Bytes = 11764.93 KiB = 11.49 MiB
216 12:17:16.983738 output: Architecture: AArch64
217 12:17:16.983798 output: OS: Linux
218 12:17:16.983855 output: Load Address: 0x00000000
219 12:17:16.983911 output: Entry Point: 0x00000000
220 12:17:16.983966 output: Hash algo: crc32
221 12:17:16.984022 output: Hash value: 5a47eb78
222 12:17:16.984074 output: Image 1 (fdt-1)
223 12:17:16.984128 output: Description: mt8192-asurada-spherion-r0
224 12:17:16.984181 output: Created: Wed Jan 31 12:17:16 2024
225 12:17:16.984233 output: Type: Flat Device Tree
226 12:17:16.984295 output: Compression: uncompressed
227 12:17:16.984386 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 12:17:16.984439 output: Architecture: AArch64
229 12:17:16.984494 output: Hash algo: crc32
230 12:17:16.984547 output: Hash value: cc4352de
231 12:17:16.984600 output: Image 2 (ramdisk-1)
232 12:17:16.984652 output: Description: unavailable
233 12:17:16.984704 output: Created: Wed Jan 31 12:17:16 2024
234 12:17:16.984756 output: Type: RAMDisk Image
235 12:17:16.984808 output: Compression: Unknown Compression
236 12:17:16.984860 output: Data Size: 47543377 Bytes = 46429.08 KiB = 45.34 MiB
237 12:17:16.984913 output: Architecture: AArch64
238 12:17:16.984965 output: OS: Linux
239 12:17:16.985017 output: Load Address: unavailable
240 12:17:16.985069 output: Entry Point: unavailable
241 12:17:16.985121 output: Hash algo: crc32
242 12:17:16.985173 output: Hash value: 08cbaab0
243 12:17:16.985225 output: Default Configuration: 'conf-1'
244 12:17:16.985277 output: Configuration 0 (conf-1)
245 12:17:16.985329 output: Description: mt8192-asurada-spherion-r0
246 12:17:16.985381 output: Kernel: kernel-1
247 12:17:16.985432 output: Init Ramdisk: ramdisk-1
248 12:17:16.985484 output: FDT: fdt-1
249 12:17:16.985536 output: Loadables: kernel-1
250 12:17:16.985588 output:
251 12:17:16.985782 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 12:17:16.985882 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 12:17:16.985989 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 12:17:16.986083 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 12:17:16.986166 No LXC device requested
256 12:17:16.986247 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:17:16.986332 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 12:17:16.986407 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:17:16.986478 Checking files for TFTP limit of 4294967296 bytes.
260 12:17:16.986996 end: 1 tftp-deploy (duration 00:00:21) [common]
261 12:17:16.987099 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:17:16.987188 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:17:16.987313 substitutions:
264 12:17:16.987379 - {DTB}: 12669521/tftp-deploy-8bw6ikvl/dtb/mt8192-asurada-spherion-r0.dtb
265 12:17:16.987443 - {INITRD}: 12669521/tftp-deploy-8bw6ikvl/ramdisk/ramdisk.cpio.gz
266 12:17:16.987502 - {KERNEL}: 12669521/tftp-deploy-8bw6ikvl/kernel/Image
267 12:17:16.987559 - {LAVA_MAC}: None
268 12:17:16.987615 - {PRESEED_CONFIG}: None
269 12:17:16.987669 - {PRESEED_LOCAL}: None
270 12:17:16.987723 - {RAMDISK}: 12669521/tftp-deploy-8bw6ikvl/ramdisk/ramdisk.cpio.gz
271 12:17:16.987777 - {ROOT_PART}: None
272 12:17:16.987831 - {ROOT}: None
273 12:17:16.987884 - {SERVER_IP}: 192.168.201.1
274 12:17:16.987938 - {TEE}: None
275 12:17:16.987991 Parsed boot commands:
276 12:17:16.988044 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:17:16.988227 Parsed boot commands: tftpboot 192.168.201.1 12669521/tftp-deploy-8bw6ikvl/kernel/image.itb 12669521/tftp-deploy-8bw6ikvl/kernel/cmdline
278 12:17:16.988359 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:17:16.988476 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:17:16.988613 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:17:16.988700 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:17:16.988772 Not connected, no need to disconnect.
283 12:17:16.988846 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:17:16.988927 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:17:16.988992 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 12:17:16.993071 Setting prompt string to ['lava-test: # ']
287 12:17:16.993481 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:17:16.993632 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:17:16.993751 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:17:16.993842 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:17:16.994047 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 12:17:22.134510 >> Command sent successfully.
293 12:17:22.137721 Returned 0 in 5 seconds
294 12:17:22.238128 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:17:22.238438 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:17:22.238535 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:17:22.238621 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:17:22.238688 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:17:22.238755 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:17:22.239019 [Enter `^Ec?' for help]
302 12:17:22.410410
303 12:17:22.410549
304 12:17:22.410622 F0: 102B 0000
305 12:17:22.410688
306 12:17:22.410749 F3: 1001 0000 [0200]
307 12:17:22.413605
308 12:17:22.413690 F3: 1001 0000
309 12:17:22.413756
310 12:17:22.413817 F7: 102D 0000
311 12:17:22.413876
312 12:17:22.416571 F1: 0000 0000
313 12:17:22.416680
314 12:17:22.416774 V0: 0000 0000 [0001]
315 12:17:22.416866
316 12:17:22.419984 00: 0007 8000
317 12:17:22.420097
318 12:17:22.420194 01: 0000 0000
319 12:17:22.420292
320 12:17:22.423264 BP: 0C00 0209 [0000]
321 12:17:22.423346
322 12:17:22.423411 G0: 1182 0000
323 12:17:22.423472
324 12:17:22.427190 EC: 0000 0021 [4000]
325 12:17:22.427273
326 12:17:22.427338 S7: 0000 0000 [0000]
327 12:17:22.427399
328 12:17:22.430250 CC: 0000 0000 [0001]
329 12:17:22.430333
330 12:17:22.430399 T0: 0000 0040 [010F]
331 12:17:22.430459
332 12:17:22.430518 Jump to BL
333 12:17:22.433626
334 12:17:22.457789
335 12:17:22.457934
336 12:17:22.458001
337 12:17:22.464657 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:17:22.467806 ARM64: Exception handlers installed.
339 12:17:22.472020 ARM64: Testing exception
340 12:17:22.475443 ARM64: Done test exception
341 12:17:22.482652 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:17:22.492177 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:17:22.498885 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:17:22.509502 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:17:22.516169 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:17:22.522369 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:17:22.534445 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:17:22.540730 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:17:22.560411 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:17:22.563211 WDT: Last reset was cold boot
351 12:17:22.567093 SPI1(PAD0) initialized at 2873684 Hz
352 12:17:22.570237 SPI5(PAD0) initialized at 992727 Hz
353 12:17:22.573615 VBOOT: Loading verstage.
354 12:17:22.580243 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:17:22.584337 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:17:22.586977 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:17:22.590655 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:17:22.597787 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:17:22.604450 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:17:22.615925 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 12:17:22.616602
362 12:17:22.616949
363 12:17:22.626421 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:17:22.629609 ARM64: Exception handlers installed.
365 12:17:22.632809 ARM64: Testing exception
366 12:17:22.633339 ARM64: Done test exception
367 12:17:22.636340 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:17:22.643074 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:17:22.656643 Probing TPM: . done!
370 12:17:22.657165 TPM ready after 0 ms
371 12:17:22.663244 Connected to device vid:did:rid of 1ae0:0028:00
372 12:17:22.670105 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 12:17:22.730538 Initialized TPM device CR50 revision 0
374 12:17:22.741201 tlcl_send_startup: Startup return code is 0
375 12:17:22.741635 TPM: setup succeeded
376 12:17:22.752445 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:17:22.761358 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:17:22.773791 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:17:22.783593 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:17:22.786410 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:17:22.790412 in-header: 03 07 00 00 08 00 00 00
382 12:17:22.794666 in-data: aa e4 47 04 13 02 00 00
383 12:17:22.798482 Chrome EC: UHEPI supported
384 12:17:22.801877 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:17:22.806579 in-header: 03 95 00 00 08 00 00 00
386 12:17:22.809766 in-data: 18 20 20 08 00 00 00 00
387 12:17:22.810293 Phase 1
388 12:17:22.813536 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:17:22.821439 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:17:22.829031 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:17:22.829537 Recovery requested (1009000e)
392 12:17:22.840779 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:17:22.844057 tlcl_extend: response is 0
394 12:17:22.855644 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:17:22.859891 tlcl_extend: response is 0
396 12:17:22.866330 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:17:22.886248 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 12:17:22.892504 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:17:22.892935
400 12:17:22.893273
401 12:17:22.903166 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:17:22.906556 ARM64: Exception handlers installed.
403 12:17:22.909891 ARM64: Testing exception
404 12:17:22.910414 ARM64: Done test exception
405 12:17:22.931635 pmic_efuse_setting: Set efuses in 11 msecs
406 12:17:22.935379 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:17:22.941642 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:17:22.945552 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:17:22.952449 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:17:22.955858 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:17:22.959925 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:17:22.967172 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:17:22.970677 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:17:22.974272 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:17:22.977923 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:17:22.985672 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:17:22.989664 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:17:22.993232 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:17:22.996275 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:17:23.004382 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:17:23.007847 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:17:23.015665 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:17:23.022774 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:17:23.026788 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:17:23.034413 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:17:23.037608 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:17:23.045771 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:17:23.049365 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:17:23.053114 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:17:23.060421 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:17:23.063830 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:17:23.071641 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:17:23.075875 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:17:23.082831 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:17:23.086483 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:17:23.089758 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:17:23.097580 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:17:23.101353 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:17:23.104894 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:17:23.113089 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:17:23.116104 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:17:23.119832 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:17:23.127642 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:17:23.131458 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:17:23.135217 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:17:23.139141 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:17:23.142587 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:17:23.149836 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:17:23.153652 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:17:23.157445 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:17:23.161488 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:17:23.165223 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:17:23.169097 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:17:23.172597 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:17:23.180222 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:17:23.183586 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:17:23.187250 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:17:23.194641 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:17:23.202914 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:17:23.206239 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:17:23.217398 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:17:23.224595 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:17:23.227669 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:17:23.231820 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:17:23.238981 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:17:23.246725 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 12:17:23.249993 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:17:23.253382 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 12:17:23.260638 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:17:23.269144 [RTC]rtc_get_frequency_meter,154: input=15, output=759
471 12:17:23.279315 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 12:17:23.288259 [RTC]rtc_get_frequency_meter,154: input=19, output=850
473 12:17:23.297383 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 12:17:23.307954 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 12:17:23.316839 [RTC]rtc_get_frequency_meter,154: input=16, output=782
476 12:17:23.327048 [RTC]rtc_get_frequency_meter,154: input=17, output=804
477 12:17:23.330347 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 12:17:23.334127 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 12:17:23.340642 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 12:17:23.345207 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 12:17:23.348672 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 12:17:23.351958 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 12:17:23.356440 ADC[4]: Raw value=906573 ID=7
484 12:17:23.360340 ADC[3]: Raw value=213441 ID=1
485 12:17:23.360781 RAM Code: 0x71
486 12:17:23.363721 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 12:17:23.367412 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 12:17:23.378602 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 12:17:23.385642 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 12:17:23.386093 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 12:17:23.389900 in-header: 03 07 00 00 08 00 00 00
492 12:17:23.393284 in-data: aa e4 47 04 13 02 00 00
493 12:17:23.397584 Chrome EC: UHEPI supported
494 12:17:23.404457 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 12:17:23.407989 in-header: 03 95 00 00 08 00 00 00
496 12:17:23.408545 in-data: 18 20 20 08 00 00 00 00
497 12:17:23.411941 MRC: failed to locate region type 0.
498 12:17:23.418977 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 12:17:23.422850 DRAM-K: Running full calibration
500 12:17:23.430438 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 12:17:23.430860 header.status = 0x0
502 12:17:23.434005 header.version = 0x6 (expected: 0x6)
503 12:17:23.437664 header.size = 0xd00 (expected: 0xd00)
504 12:17:23.438104 header.flags = 0x0
505 12:17:23.444441 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 12:17:23.463619 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
507 12:17:23.471519 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 12:17:23.472078 dram_init: ddr_geometry: 2
509 12:17:23.474562 [EMI] MDL number = 2
510 12:17:23.478732 [EMI] Get MDL freq = 0
511 12:17:23.479278 dram_init: ddr_type: 0
512 12:17:23.482651 is_discrete_lpddr4: 1
513 12:17:23.483204 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 12:17:23.486303
515 12:17:23.486830
516 12:17:23.487304 [Bian_co] ETT version 0.0.0.1
517 12:17:23.493310 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 12:17:23.493735
519 12:17:23.497506 dramc_set_vcore_voltage set vcore to 650000
520 12:17:23.498037 Read voltage for 800, 4
521 12:17:23.498385 Vio18 = 0
522 12:17:23.501221 Vcore = 650000
523 12:17:23.501643 Vdram = 0
524 12:17:23.501979 Vddq = 0
525 12:17:23.505138 Vmddr = 0
526 12:17:23.505560 dram_init: config_dvfs: 1
527 12:17:23.508738 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 12:17:23.515612 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 12:17:23.519524 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 12:17:23.523220 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 12:17:23.527223 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 12:17:23.530739 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 12:17:23.534829 MEM_TYPE=3, freq_sel=18
534 12:17:23.535344 sv_algorithm_assistance_LP4_1600
535 12:17:23.541809 ============ PULL DRAM RESETB DOWN ============
536 12:17:23.544775 ========== PULL DRAM RESETB DOWN end =========
537 12:17:23.548723 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 12:17:23.552161 ===================================
539 12:17:23.555480 LPDDR4 DRAM CONFIGURATION
540 12:17:23.558461 ===================================
541 12:17:23.558886 EX_ROW_EN[0] = 0x0
542 12:17:23.562452 EX_ROW_EN[1] = 0x0
543 12:17:23.562874 LP4Y_EN = 0x0
544 12:17:23.566314 WORK_FSP = 0x0
545 12:17:23.566738 WL = 0x2
546 12:17:23.569905 RL = 0x2
547 12:17:23.570330 BL = 0x2
548 12:17:23.573381 RPST = 0x0
549 12:17:23.573800 RD_PRE = 0x0
550 12:17:23.577270 WR_PRE = 0x1
551 12:17:23.577691 WR_PST = 0x0
552 12:17:23.581085 DBI_WR = 0x0
553 12:17:23.581582 DBI_RD = 0x0
554 12:17:23.584229 OTF = 0x1
555 12:17:23.587137 ===================================
556 12:17:23.590478 ===================================
557 12:17:23.590904 ANA top config
558 12:17:23.594331 ===================================
559 12:17:23.597650 DLL_ASYNC_EN = 0
560 12:17:23.598072 ALL_SLAVE_EN = 1
561 12:17:23.600630 NEW_RANK_MODE = 1
562 12:17:23.603914 DLL_IDLE_MODE = 1
563 12:17:23.607784 LP45_APHY_COMB_EN = 1
564 12:17:23.611057 TX_ODT_DIS = 1
565 12:17:23.611495 NEW_8X_MODE = 1
566 12:17:23.614177 ===================================
567 12:17:23.617894 ===================================
568 12:17:23.621789 data_rate = 1600
569 12:17:23.624759 CKR = 1
570 12:17:23.628497 DQ_P2S_RATIO = 8
571 12:17:23.631002 ===================================
572 12:17:23.631315 CA_P2S_RATIO = 8
573 12:17:23.634919 DQ_CA_OPEN = 0
574 12:17:23.638518 DQ_SEMI_OPEN = 0
575 12:17:23.641559 CA_SEMI_OPEN = 0
576 12:17:23.644594 CA_FULL_RATE = 0
577 12:17:23.647742 DQ_CKDIV4_EN = 1
578 12:17:23.647900 CA_CKDIV4_EN = 1
579 12:17:23.651014 CA_PREDIV_EN = 0
580 12:17:23.654373 PH8_DLY = 0
581 12:17:23.658084 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 12:17:23.661138 DQ_AAMCK_DIV = 4
583 12:17:23.664195 CA_AAMCK_DIV = 4
584 12:17:23.664338 CA_ADMCK_DIV = 4
585 12:17:23.667931 DQ_TRACK_CA_EN = 0
586 12:17:23.671132 CA_PICK = 800
587 12:17:23.674522 CA_MCKIO = 800
588 12:17:23.678143 MCKIO_SEMI = 0
589 12:17:23.681848 PLL_FREQ = 3068
590 12:17:23.681936 DQ_UI_PI_RATIO = 32
591 12:17:23.685282 CA_UI_PI_RATIO = 0
592 12:17:23.689800 ===================================
593 12:17:23.693164 ===================================
594 12:17:23.693322 memory_type:LPDDR4
595 12:17:23.697127 GP_NUM : 10
596 12:17:23.697212 SRAM_EN : 1
597 12:17:23.700807 MD32_EN : 0
598 12:17:23.704689 ===================================
599 12:17:23.708422 [ANA_INIT] >>>>>>>>>>>>>>
600 12:17:23.708507 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 12:17:23.711722 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 12:17:23.714969 ===================================
603 12:17:23.718809 data_rate = 1600,PCW = 0X7600
604 12:17:23.722048 ===================================
605 12:17:23.725176 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 12:17:23.731475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 12:17:23.735226 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 12:17:23.741722 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 12:17:23.745088 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 12:17:23.748297 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 12:17:23.748417 [ANA_INIT] flow start
612 12:17:23.751980 [ANA_INIT] PLL >>>>>>>>
613 12:17:23.755064 [ANA_INIT] PLL <<<<<<<<
614 12:17:23.758295 [ANA_INIT] MIDPI >>>>>>>>
615 12:17:23.758380 [ANA_INIT] MIDPI <<<<<<<<
616 12:17:23.761954 [ANA_INIT] DLL >>>>>>>>
617 12:17:23.762040 [ANA_INIT] flow end
618 12:17:23.768179 ============ LP4 DIFF to SE enter ============
619 12:17:23.772048 ============ LP4 DIFF to SE exit ============
620 12:17:23.774956 [ANA_INIT] <<<<<<<<<<<<<
621 12:17:23.778270 [Flow] Enable top DCM control >>>>>
622 12:17:23.781598 [Flow] Enable top DCM control <<<<<
623 12:17:23.785575 Enable DLL master slave shuffle
624 12:17:23.788718 ==============================================================
625 12:17:23.792118 Gating Mode config
626 12:17:23.795312 ==============================================================
627 12:17:23.798513 Config description:
628 12:17:23.808668 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 12:17:23.815403 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 12:17:23.818403 SELPH_MODE 0: By rank 1: By Phase
631 12:17:23.825293 ==============================================================
632 12:17:23.829017 GAT_TRACK_EN = 1
633 12:17:23.832100 RX_GATING_MODE = 2
634 12:17:23.835366 RX_GATING_TRACK_MODE = 2
635 12:17:23.838698 SELPH_MODE = 1
636 12:17:23.838870 PICG_EARLY_EN = 1
637 12:17:23.842523 VALID_LAT_VALUE = 1
638 12:17:23.848661 ==============================================================
639 12:17:23.852331 Enter into Gating configuration >>>>
640 12:17:23.855924 Exit from Gating configuration <<<<
641 12:17:23.858964 Enter into DVFS_PRE_config >>>>>
642 12:17:23.868767 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 12:17:23.872652 Exit from DVFS_PRE_config <<<<<
644 12:17:23.876014 Enter into PICG configuration >>>>
645 12:17:23.879381 Exit from PICG configuration <<<<
646 12:17:23.882664 [RX_INPUT] configuration >>>>>
647 12:17:23.886466 [RX_INPUT] configuration <<<<<
648 12:17:23.889125 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 12:17:23.895231 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 12:17:23.902109 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 12:17:23.909415 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 12:17:23.911984 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 12:17:23.918909 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 12:17:23.922070 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 12:17:23.928645 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 12:17:23.932736 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 12:17:23.935739 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 12:17:23.938843 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 12:17:23.945920 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 12:17:23.949095 ===================================
661 12:17:23.949260 LPDDR4 DRAM CONFIGURATION
662 12:17:23.952314 ===================================
663 12:17:23.955702 EX_ROW_EN[0] = 0x0
664 12:17:23.958694 EX_ROW_EN[1] = 0x0
665 12:17:23.958835 LP4Y_EN = 0x0
666 12:17:23.962230 WORK_FSP = 0x0
667 12:17:23.962394 WL = 0x2
668 12:17:23.965400 RL = 0x2
669 12:17:23.965571 BL = 0x2
670 12:17:23.969094 RPST = 0x0
671 12:17:23.969210 RD_PRE = 0x0
672 12:17:23.972050 WR_PRE = 0x1
673 12:17:23.972214 WR_PST = 0x0
674 12:17:23.975548 DBI_WR = 0x0
675 12:17:23.975688 DBI_RD = 0x0
676 12:17:23.979133 OTF = 0x1
677 12:17:23.982717 ===================================
678 12:17:23.985544 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 12:17:23.988761 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 12:17:23.996081 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 12:17:23.999365 ===================================
682 12:17:23.999739 LPDDR4 DRAM CONFIGURATION
683 12:17:24.002455 ===================================
684 12:17:24.006636 EX_ROW_EN[0] = 0x10
685 12:17:24.007136 EX_ROW_EN[1] = 0x0
686 12:17:24.009564 LP4Y_EN = 0x0
687 12:17:24.010016 WORK_FSP = 0x0
688 12:17:24.012670 WL = 0x2
689 12:17:24.013102 RL = 0x2
690 12:17:24.016128 BL = 0x2
691 12:17:24.016720 RPST = 0x0
692 12:17:24.019752 RD_PRE = 0x0
693 12:17:24.022429 WR_PRE = 0x1
694 12:17:24.022866 WR_PST = 0x0
695 12:17:24.026627 DBI_WR = 0x0
696 12:17:24.027155 DBI_RD = 0x0
697 12:17:24.029612 OTF = 0x1
698 12:17:24.032569 ===================================
699 12:17:24.035969 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 12:17:24.041160 nWR fixed to 40
701 12:17:24.044979 [ModeRegInit_LP4] CH0 RK0
702 12:17:24.045514 [ModeRegInit_LP4] CH0 RK1
703 12:17:24.048005 [ModeRegInit_LP4] CH1 RK0
704 12:17:24.051272 [ModeRegInit_LP4] CH1 RK1
705 12:17:24.051803 match AC timing 13
706 12:17:24.057707 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 12:17:24.061256 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 12:17:24.064499 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 12:17:24.071430 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 12:17:24.074709 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 12:17:24.075143 [EMI DOE] emi_dcm 0
712 12:17:24.081336 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 12:17:24.081853 ==
714 12:17:24.084424 Dram Type= 6, Freq= 0, CH_0, rank 0
715 12:17:24.087746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 12:17:24.088172 ==
717 12:17:24.094445 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 12:17:24.101357 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 12:17:24.108876 [CA 0] Center 36 (6~67) winsize 62
720 12:17:24.111757 [CA 1] Center 36 (6~67) winsize 62
721 12:17:24.115297 [CA 2] Center 34 (4~65) winsize 62
722 12:17:24.118651 [CA 3] Center 34 (4~64) winsize 61
723 12:17:24.122209 [CA 4] Center 33 (2~64) winsize 63
724 12:17:24.125420 [CA 5] Center 32 (3~62) winsize 60
725 12:17:24.125845
726 12:17:24.128920 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 12:17:24.129438
728 12:17:24.132508 [CATrainingPosCal] consider 1 rank data
729 12:17:24.135801 u2DelayCellTimex100 = 270/100 ps
730 12:17:24.138850 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 12:17:24.142316 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 12:17:24.148589 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 12:17:24.152781 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
734 12:17:24.155619 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
735 12:17:24.158814 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
736 12:17:24.159239
737 12:17:24.162185 CA PerBit enable=1, Macro0, CA PI delay=32
738 12:17:24.162705
739 12:17:24.165501 [CBTSetCACLKResult] CA Dly = 32
740 12:17:24.166018 CS Dly: 5 (0~36)
741 12:17:24.166362 ==
742 12:17:24.169241 Dram Type= 6, Freq= 0, CH_0, rank 1
743 12:17:24.175426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 12:17:24.175866 ==
745 12:17:24.179426 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 12:17:24.186079 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 12:17:24.194772 [CA 0] Center 36 (6~67) winsize 62
748 12:17:24.198521 [CA 1] Center 36 (6~67) winsize 62
749 12:17:24.201648 [CA 2] Center 34 (4~65) winsize 62
750 12:17:24.205018 [CA 3] Center 33 (3~64) winsize 62
751 12:17:24.208270 [CA 4] Center 32 (2~63) winsize 62
752 12:17:24.211515 [CA 5] Center 32 (2~63) winsize 62
753 12:17:24.211954
754 12:17:24.215191 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 12:17:24.215725
756 12:17:24.218264 [CATrainingPosCal] consider 2 rank data
757 12:17:24.221379 u2DelayCellTimex100 = 270/100 ps
758 12:17:24.224906 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 12:17:24.228325 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 12:17:24.235041 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 12:17:24.237957 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
762 12:17:24.241998 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
763 12:17:24.244929 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
764 12:17:24.245366
765 12:17:24.248832 CA PerBit enable=1, Macro0, CA PI delay=32
766 12:17:24.249364
767 12:17:24.252195 [CBTSetCACLKResult] CA Dly = 32
768 12:17:24.252803 CS Dly: 5 (0~37)
769 12:17:24.253253
770 12:17:24.254984 ----->DramcWriteLeveling(PI) begin...
771 12:17:24.258612 ==
772 12:17:24.259050 Dram Type= 6, Freq= 0, CH_0, rank 0
773 12:17:24.266590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 12:17:24.267045 ==
775 12:17:24.267484 Write leveling (Byte 0): 36 => 36
776 12:17:24.270423 Write leveling (Byte 1): 29 => 29
777 12:17:24.274165 DramcWriteLeveling(PI) end<-----
778 12:17:24.274600
779 12:17:24.275045 ==
780 12:17:24.277354 Dram Type= 6, Freq= 0, CH_0, rank 0
781 12:17:24.280627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 12:17:24.281175 ==
783 12:17:24.284035 [Gating] SW mode calibration
784 12:17:24.291513 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 12:17:24.294817 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 12:17:24.301594 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 12:17:24.304666 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 12:17:24.308874 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 12:17:24.315262 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:17:24.318540 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:17:24.321503 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:17:24.328141 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:17:24.331560 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:17:24.335438 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:17:24.341401 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:17:24.344988 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:17:24.348233 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:17:24.354808 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:17:24.358398 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:17:24.361265 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:17:24.368491 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:17:24.371290 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:17:24.374837 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 12:17:24.382193 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 12:17:24.384634 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:17:24.388173 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:17:24.391606 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:17:24.398423 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:17:24.401546 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:17:24.405200 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:17:24.411940 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:17:24.414929 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (1 1) (1 1)
813 12:17:24.419084 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
814 12:17:24.425251 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:17:24.428712 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 12:17:24.431917 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 12:17:24.438884 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 12:17:24.441855 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 12:17:24.448870 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 12:17:24.451961 0 10 8 | B1->B0 | 3232 2a2a | 0 0 | (0 0) (1 1)
821 12:17:24.455028 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 12:17:24.458388 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:17:24.461604 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:17:24.469064 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:17:24.473554 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:17:24.475279 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:17:24.482313 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 12:17:24.485911 0 11 8 | B1->B0 | 2a2a 4040 | 1 0 | (0 0) (0 0)
829 12:17:24.488660 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
830 12:17:24.495363 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:17:24.498908 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 12:17:24.502213 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 12:17:24.508954 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:17:24.512341 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:17:24.515787 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 12:17:24.521956 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 12:17:24.525604 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 12:17:24.528595 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:17:24.535387 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:17:24.538845 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:17:24.542176 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:17:24.545164 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:17:24.552667 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:17:24.555795 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:17:24.559068 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:17:24.565497 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:17:24.568859 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:17:24.572217 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:17:24.578937 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:17:24.582748 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:17:24.585701 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 12:17:24.592088 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
853 12:17:24.595834 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 12:17:24.599430 Total UI for P1: 0, mck2ui 16
855 12:17:24.602738 best dqsien dly found for B0: ( 0, 14, 6)
856 12:17:24.605712 Total UI for P1: 0, mck2ui 16
857 12:17:24.609150 best dqsien dly found for B1: ( 0, 14, 10)
858 12:17:24.612920 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 12:17:24.616096 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 12:17:24.616660
861 12:17:24.620018 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 12:17:24.622930 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 12:17:24.626537 [Gating] SW calibration Done
864 12:17:24.626958 ==
865 12:17:24.629351 Dram Type= 6, Freq= 0, CH_0, rank 0
866 12:17:24.632773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 12:17:24.633298 ==
868 12:17:24.636162 RX Vref Scan: 0
869 12:17:24.636648
870 12:17:24.636980 RX Vref 0 -> 0, step: 1
871 12:17:24.637290
872 12:17:24.639523 RX Delay -130 -> 252, step: 16
873 12:17:24.642962 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
874 12:17:24.650117 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 12:17:24.652937 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 12:17:24.656267 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 12:17:24.659658 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 12:17:24.663065 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 12:17:24.669874 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
880 12:17:24.672950 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
881 12:17:24.676350 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 12:17:24.680482 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 12:17:24.683323 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 12:17:24.689900 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 12:17:24.693379 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
886 12:17:24.696839 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
887 12:17:24.699839 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
888 12:17:24.702977 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
889 12:17:24.706189 ==
890 12:17:24.706609 Dram Type= 6, Freq= 0, CH_0, rank 0
891 12:17:24.713028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 12:17:24.713539 ==
893 12:17:24.713877 DQS Delay:
894 12:17:24.716681 DQS0 = 0, DQS1 = 0
895 12:17:24.717195 DQM Delay:
896 12:17:24.717534 DQM0 = 90, DQM1 = 82
897 12:17:24.720255 DQ Delay:
898 12:17:24.723769 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
899 12:17:24.726694 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
900 12:17:24.730228 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
901 12:17:24.733096 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
902 12:17:24.733610
903 12:17:24.733944
904 12:17:24.734252 ==
905 12:17:24.737123 Dram Type= 6, Freq= 0, CH_0, rank 0
906 12:17:24.739982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 12:17:24.740534 ==
908 12:17:24.740877
909 12:17:24.741327
910 12:17:24.743114 TX Vref Scan disable
911 12:17:24.746805 == TX Byte 0 ==
912 12:17:24.750147 Update DQ dly =587 (2 ,2, 11) DQ OEN =(1 ,7)
913 12:17:24.753206 Update DQM dly =587 (2 ,2, 11) DQM OEN =(1 ,7)
914 12:17:24.756964 == TX Byte 1 ==
915 12:17:24.760056 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
916 12:17:24.763357 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
917 12:17:24.763781 ==
918 12:17:24.767159 Dram Type= 6, Freq= 0, CH_0, rank 0
919 12:17:24.769862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 12:17:24.770285 ==
921 12:17:24.785189 TX Vref=22, minBit 8, minWin=27, winSum=445
922 12:17:24.788248 TX Vref=24, minBit 10, minWin=27, winSum=451
923 12:17:24.791506 TX Vref=26, minBit 8, minWin=28, winSum=456
924 12:17:24.795420 TX Vref=28, minBit 8, minWin=28, winSum=458
925 12:17:24.798285 TX Vref=30, minBit 8, minWin=28, winSum=459
926 12:17:24.801799 TX Vref=32, minBit 5, minWin=28, winSum=455
927 12:17:24.808222 [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30
928 12:17:24.808842
929 12:17:24.811441 Final TX Range 1 Vref 30
930 12:17:24.811861
931 12:17:24.812196 ==
932 12:17:24.814876 Dram Type= 6, Freq= 0, CH_0, rank 0
933 12:17:24.818604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 12:17:24.819027 ==
935 12:17:24.819360
936 12:17:24.821832
937 12:17:24.822252 TX Vref Scan disable
938 12:17:24.825521 == TX Byte 0 ==
939 12:17:24.828991 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
940 12:17:24.832067 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
941 12:17:24.835379 == TX Byte 1 ==
942 12:17:24.838463 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 12:17:24.841611 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 12:17:24.845642
945 12:17:24.846173 [DATLAT]
946 12:17:24.846628 Freq=800, CH0 RK0
947 12:17:24.847055
948 12:17:24.848443 DATLAT Default: 0xa
949 12:17:24.848884 0, 0xFFFF, sum = 0
950 12:17:24.852637 1, 0xFFFF, sum = 0
951 12:17:24.853190 2, 0xFFFF, sum = 0
952 12:17:24.855074 3, 0xFFFF, sum = 0
953 12:17:24.855628 4, 0xFFFF, sum = 0
954 12:17:24.858918 5, 0xFFFF, sum = 0
955 12:17:24.862214 6, 0xFFFF, sum = 0
956 12:17:24.862768 7, 0xFFFF, sum = 0
957 12:17:24.863232 8, 0x0, sum = 1
958 12:17:24.864946 9, 0x0, sum = 2
959 12:17:24.865390 10, 0x0, sum = 3
960 12:17:24.868075 11, 0x0, sum = 4
961 12:17:24.868609 best_step = 9
962 12:17:24.869054
963 12:17:24.869475 ==
964 12:17:24.871748 Dram Type= 6, Freq= 0, CH_0, rank 0
965 12:17:24.878438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 12:17:24.878958 ==
967 12:17:24.879297 RX Vref Scan: 1
968 12:17:24.879607
969 12:17:24.881151 Set Vref Range= 32 -> 127
970 12:17:24.881566
971 12:17:24.884839 RX Vref 32 -> 127, step: 1
972 12:17:24.885363
973 12:17:24.888538 RX Delay -95 -> 252, step: 8
974 12:17:24.889094
975 12:17:24.891673 Set Vref, RX VrefLevel [Byte0]: 32
976 12:17:24.892094 [Byte1]: 32
977 12:17:24.895959
978 12:17:24.896517 Set Vref, RX VrefLevel [Byte0]: 33
979 12:17:24.898935 [Byte1]: 33
980 12:17:24.902933
981 12:17:24.903463 Set Vref, RX VrefLevel [Byte0]: 34
982 12:17:24.906570 [Byte1]: 34
983 12:17:24.910913
984 12:17:24.911372 Set Vref, RX VrefLevel [Byte0]: 35
985 12:17:24.914303 [Byte1]: 35
986 12:17:24.918429
987 12:17:24.918849 Set Vref, RX VrefLevel [Byte0]: 36
988 12:17:24.922074 [Byte1]: 36
989 12:17:24.926240
990 12:17:24.926672 Set Vref, RX VrefLevel [Byte0]: 37
991 12:17:24.929726 [Byte1]: 37
992 12:17:24.934429
993 12:17:24.934845 Set Vref, RX VrefLevel [Byte0]: 38
994 12:17:24.937586 [Byte1]: 38
995 12:17:24.941682
996 12:17:24.942247 Set Vref, RX VrefLevel [Byte0]: 39
997 12:17:24.944862 [Byte1]: 39
998 12:17:24.948799
999 12:17:24.949215 Set Vref, RX VrefLevel [Byte0]: 40
1000 12:17:24.952567 [Byte1]: 40
1001 12:17:24.957322
1002 12:17:24.957738 Set Vref, RX VrefLevel [Byte0]: 41
1003 12:17:24.960677 [Byte1]: 41
1004 12:17:24.963906
1005 12:17:24.964467 Set Vref, RX VrefLevel [Byte0]: 42
1006 12:17:24.967869 [Byte1]: 42
1007 12:17:24.972527
1008 12:17:24.973104 Set Vref, RX VrefLevel [Byte0]: 43
1009 12:17:24.975374 [Byte1]: 43
1010 12:17:24.979778
1011 12:17:24.980324 Set Vref, RX VrefLevel [Byte0]: 44
1012 12:17:24.983166 [Byte1]: 44
1013 12:17:24.987326
1014 12:17:24.987766 Set Vref, RX VrefLevel [Byte0]: 45
1015 12:17:24.990380 [Byte1]: 45
1016 12:17:24.995115
1017 12:17:24.995536 Set Vref, RX VrefLevel [Byte0]: 46
1018 12:17:24.998136 [Byte1]: 46
1019 12:17:25.001972
1020 12:17:25.002636 Set Vref, RX VrefLevel [Byte0]: 47
1021 12:17:25.005702 [Byte1]: 47
1022 12:17:25.009442
1023 12:17:25.010082 Set Vref, RX VrefLevel [Byte0]: 48
1024 12:17:25.012859 [Byte1]: 48
1025 12:17:25.016969
1026 12:17:25.017418 Set Vref, RX VrefLevel [Byte0]: 49
1027 12:17:25.020278 [Byte1]: 49
1028 12:17:25.024569
1029 12:17:25.024856 Set Vref, RX VrefLevel [Byte0]: 50
1030 12:17:25.027842 [Byte1]: 50
1031 12:17:25.032324
1032 12:17:25.032532 Set Vref, RX VrefLevel [Byte0]: 51
1033 12:17:25.035446 [Byte1]: 51
1034 12:17:25.039773
1035 12:17:25.039917 Set Vref, RX VrefLevel [Byte0]: 52
1036 12:17:25.043192 [Byte1]: 52
1037 12:17:25.047529
1038 12:17:25.047659 Set Vref, RX VrefLevel [Byte0]: 53
1039 12:17:25.050674 [Byte1]: 53
1040 12:17:25.054867
1041 12:17:25.054960 Set Vref, RX VrefLevel [Byte0]: 54
1042 12:17:25.058173 [Byte1]: 54
1043 12:17:25.062476
1044 12:17:25.062567 Set Vref, RX VrefLevel [Byte0]: 55
1045 12:17:25.065774 [Byte1]: 55
1046 12:17:25.070256
1047 12:17:25.070421 Set Vref, RX VrefLevel [Byte0]: 56
1048 12:17:25.073175 [Byte1]: 56
1049 12:17:25.077678
1050 12:17:25.077788 Set Vref, RX VrefLevel [Byte0]: 57
1051 12:17:25.081171 [Byte1]: 57
1052 12:17:25.085542
1053 12:17:25.085634 Set Vref, RX VrefLevel [Byte0]: 58
1054 12:17:25.088749 [Byte1]: 58
1055 12:17:25.093458
1056 12:17:25.093576 Set Vref, RX VrefLevel [Byte0]: 59
1057 12:17:25.096484 [Byte1]: 59
1058 12:17:25.100348
1059 12:17:25.100436 Set Vref, RX VrefLevel [Byte0]: 60
1060 12:17:25.104036 [Byte1]: 60
1061 12:17:25.107888
1062 12:17:25.108008 Set Vref, RX VrefLevel [Byte0]: 61
1063 12:17:25.111858 [Byte1]: 61
1064 12:17:25.116185
1065 12:17:25.116325 Set Vref, RX VrefLevel [Byte0]: 62
1066 12:17:25.118788 [Byte1]: 62
1067 12:17:25.123328
1068 12:17:25.123413 Set Vref, RX VrefLevel [Byte0]: 63
1069 12:17:25.126493 [Byte1]: 63
1070 12:17:25.130998
1071 12:17:25.131079 Set Vref, RX VrefLevel [Byte0]: 64
1072 12:17:25.134020 [Byte1]: 64
1073 12:17:25.138816
1074 12:17:25.138896 Set Vref, RX VrefLevel [Byte0]: 65
1075 12:17:25.142136 [Byte1]: 65
1076 12:17:25.146002
1077 12:17:25.146082 Set Vref, RX VrefLevel [Byte0]: 66
1078 12:17:25.149864 [Byte1]: 66
1079 12:17:25.153834
1080 12:17:25.153914 Set Vref, RX VrefLevel [Byte0]: 67
1081 12:17:25.157473 [Byte1]: 67
1082 12:17:25.161143
1083 12:17:25.161223 Set Vref, RX VrefLevel [Byte0]: 68
1084 12:17:25.164761 [Byte1]: 68
1085 12:17:25.169011
1086 12:17:25.169091 Set Vref, RX VrefLevel [Byte0]: 69
1087 12:17:25.171988 [Byte1]: 69
1088 12:17:25.176544
1089 12:17:25.176625 Set Vref, RX VrefLevel [Byte0]: 70
1090 12:17:25.180180 [Byte1]: 70
1091 12:17:25.184182
1092 12:17:25.184278 Set Vref, RX VrefLevel [Byte0]: 71
1093 12:17:25.187578 [Byte1]: 71
1094 12:17:25.191800
1095 12:17:25.191887 Set Vref, RX VrefLevel [Byte0]: 72
1096 12:17:25.195313 [Byte1]: 72
1097 12:17:25.199356
1098 12:17:25.199439 Set Vref, RX VrefLevel [Byte0]: 73
1099 12:17:25.202448 [Byte1]: 73
1100 12:17:25.206752
1101 12:17:25.206852 Set Vref, RX VrefLevel [Byte0]: 74
1102 12:17:25.210251 [Byte1]: 74
1103 12:17:25.214592
1104 12:17:25.214672 Set Vref, RX VrefLevel [Byte0]: 75
1105 12:17:25.218001 [Byte1]: 75
1106 12:17:25.222518
1107 12:17:25.222598 Set Vref, RX VrefLevel [Byte0]: 76
1108 12:17:25.225485 [Byte1]: 76
1109 12:17:25.229873
1110 12:17:25.229953 Set Vref, RX VrefLevel [Byte0]: 77
1111 12:17:25.233015 [Byte1]: 77
1112 12:17:25.237913
1113 12:17:25.238323 Final RX Vref Byte 0 = 57 to rank0
1114 12:17:25.241180 Final RX Vref Byte 1 = 60 to rank0
1115 12:17:25.244858 Final RX Vref Byte 0 = 57 to rank1
1116 12:17:25.248031 Final RX Vref Byte 1 = 60 to rank1==
1117 12:17:25.251448 Dram Type= 6, Freq= 0, CH_0, rank 0
1118 12:17:25.254561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1119 12:17:25.257784 ==
1120 12:17:25.258195 DQS Delay:
1121 12:17:25.258519 DQS0 = 0, DQS1 = 0
1122 12:17:25.261457 DQM Delay:
1123 12:17:25.261747 DQM0 = 91, DQM1 = 86
1124 12:17:25.264615 DQ Delay:
1125 12:17:25.264835 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1126 12:17:25.267774 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1127 12:17:25.270874 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =80
1128 12:17:25.277483 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1129 12:17:25.277636
1130 12:17:25.277753
1131 12:17:25.284118 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c42, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1132 12:17:25.287676 CH0 RK0: MR19=606, MR18=4C42
1133 12:17:25.294099 CH0_RK0: MR19=0x606, MR18=0x4C42, DQSOSC=390, MR23=63, INC=97, DEC=64
1134 12:17:25.294202
1135 12:17:25.297165 ----->DramcWriteLeveling(PI) begin...
1136 12:17:25.297258 ==
1137 12:17:25.301108 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 12:17:25.304399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 12:17:25.304490 ==
1140 12:17:25.307557 Write leveling (Byte 0): 34 => 34
1141 12:17:25.310837 Write leveling (Byte 1): 29 => 29
1142 12:17:25.314386 DramcWriteLeveling(PI) end<-----
1143 12:17:25.314488
1144 12:17:25.314578 ==
1145 12:17:25.317529 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 12:17:25.320662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 12:17:25.320745 ==
1148 12:17:25.324283 [Gating] SW mode calibration
1149 12:17:25.330837 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1150 12:17:25.374936 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1151 12:17:25.375485 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1152 12:17:25.375689 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 12:17:25.375860 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1154 12:17:25.376021 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 12:17:25.376211 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 12:17:25.376405 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 12:17:25.376563 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 12:17:25.376716 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 12:17:25.376866 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 12:17:25.386624 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 12:17:25.386988 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 12:17:25.390080 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 12:17:25.392959 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 12:17:25.396492 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 12:17:25.403455 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 12:17:25.406469 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 12:17:25.409667 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 12:17:25.416230 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 12:17:25.419770 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1170 12:17:25.423102 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 12:17:25.429424 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 12:17:25.432677 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 12:17:25.436446 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 12:17:25.442761 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:17:25.446437 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:17:25.449687 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:17:25.456548 0 9 8 | B1->B0 | 2c2c 2828 | 0 0 | (0 0) (0 0)
1178 12:17:25.459993 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 12:17:25.463746 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 12:17:25.469972 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 12:17:25.473166 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 12:17:25.476602 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 12:17:25.483784 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 12:17:25.487037 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 12:17:25.490103 0 10 8 | B1->B0 | 2a2a 2828 | 0 0 | (0 0) (0 0)
1186 12:17:25.493405 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 12:17:25.499916 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 12:17:25.503747 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 12:17:25.508109 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 12:17:25.511433 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:17:25.518323 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:17:25.521767 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:17:25.525126 0 11 8 | B1->B0 | 3c3c 3737 | 0 0 | (1 1) (0 0)
1194 12:17:25.528897 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 12:17:25.535744 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 12:17:25.538884 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 12:17:25.542533 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 12:17:25.548961 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 12:17:25.552593 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 12:17:25.555798 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 12:17:25.559096 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1202 12:17:25.565796 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 12:17:25.569220 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 12:17:25.572372 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 12:17:25.579382 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 12:17:25.582454 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 12:17:25.585836 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 12:17:25.592633 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 12:17:25.595657 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 12:17:25.598865 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 12:17:25.605762 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 12:17:25.609545 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 12:17:25.613247 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 12:17:25.619251 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 12:17:25.622610 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 12:17:25.626467 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 12:17:25.629818 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 12:17:25.636565 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1219 12:17:25.639253 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 12:17:25.642810 Total UI for P1: 0, mck2ui 16
1221 12:17:25.646312 best dqsien dly found for B0: ( 0, 14, 12)
1222 12:17:25.649714 Total UI for P1: 0, mck2ui 16
1223 12:17:25.653334 best dqsien dly found for B1: ( 0, 14, 12)
1224 12:17:25.656518 best DQS0 dly(MCK, UI, PI) = (0, 14, 12)
1225 12:17:25.659821 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
1226 12:17:25.660398
1227 12:17:25.663233 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 12)
1228 12:17:25.666667 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
1229 12:17:25.669726 [Gating] SW calibration Done
1230 12:17:25.670143 ==
1231 12:17:25.673645 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 12:17:25.680229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 12:17:25.680808 ==
1234 12:17:25.681148 RX Vref Scan: 0
1235 12:17:25.681456
1236 12:17:25.683471 RX Vref 0 -> 0, step: 1
1237 12:17:25.683987
1238 12:17:25.686800 RX Delay -130 -> 252, step: 16
1239 12:17:25.689997 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1240 12:17:25.692970 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1241 12:17:25.696462 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1242 12:17:25.699870 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1243 12:17:25.706510 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1244 12:17:25.709594 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1245 12:17:25.712869 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1246 12:17:25.716867 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1247 12:17:25.719743 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1248 12:17:25.726717 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1249 12:17:25.729728 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1250 12:17:25.732887 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1251 12:17:25.736613 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1252 12:17:25.740087 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1253 12:17:25.746334 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1254 12:17:25.749869 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1255 12:17:25.750287 ==
1256 12:17:25.753793 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 12:17:25.756747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 12:17:25.757165 ==
1259 12:17:25.759898 DQS Delay:
1260 12:17:25.760342 DQS0 = 0, DQS1 = 0
1261 12:17:25.760684 DQM Delay:
1262 12:17:25.764115 DQM0 = 93, DQM1 = 83
1263 12:17:25.764698 DQ Delay:
1264 12:17:25.766955 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1265 12:17:25.770248 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1266 12:17:25.773595 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1267 12:17:25.776981 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1268 12:17:25.777393
1269 12:17:25.777715
1270 12:17:25.778015 ==
1271 12:17:25.780330 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 12:17:25.787007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 12:17:25.787539 ==
1274 12:17:25.787874
1275 12:17:25.788176
1276 12:17:25.788538 TX Vref Scan disable
1277 12:17:25.790516 == TX Byte 0 ==
1278 12:17:25.793543 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1279 12:17:25.796656 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1280 12:17:25.799975 == TX Byte 1 ==
1281 12:17:25.803835 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1282 12:17:25.806965 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1283 12:17:25.810031 ==
1284 12:17:25.814046 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 12:17:25.817204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 12:17:25.817725 ==
1287 12:17:25.829992 TX Vref=22, minBit 8, minWin=27, winSum=448
1288 12:17:25.833301 TX Vref=24, minBit 8, minWin=27, winSum=449
1289 12:17:25.836399 TX Vref=26, minBit 4, minWin=28, winSum=458
1290 12:17:25.839860 TX Vref=28, minBit 3, minWin=28, winSum=459
1291 12:17:25.843052 TX Vref=30, minBit 4, minWin=28, winSum=457
1292 12:17:25.846082 TX Vref=32, minBit 0, minWin=28, winSum=451
1293 12:17:25.852872 [TxChooseVref] Worse bit 3, Min win 28, Win sum 459, Final Vref 28
1294 12:17:25.853421
1295 12:17:25.856789 Final TX Range 1 Vref 28
1296 12:17:25.857333
1297 12:17:25.857798 ==
1298 12:17:25.859630 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 12:17:25.862901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 12:17:25.863317 ==
1301 12:17:25.863642
1302 12:17:25.863944
1303 12:17:25.866323 TX Vref Scan disable
1304 12:17:25.869300 == TX Byte 0 ==
1305 12:17:25.872974 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1306 12:17:25.876145 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1307 12:17:25.879437 == TX Byte 1 ==
1308 12:17:25.883022 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1309 12:17:25.886472 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1310 12:17:25.886776
1311 12:17:25.890046 [DATLAT]
1312 12:17:25.890347 Freq=800, CH0 RK1
1313 12:17:25.890528
1314 12:17:25.892969 DATLAT Default: 0x9
1315 12:17:25.893189 0, 0xFFFF, sum = 0
1316 12:17:25.896456 1, 0xFFFF, sum = 0
1317 12:17:25.896679 2, 0xFFFF, sum = 0
1318 12:17:25.900009 3, 0xFFFF, sum = 0
1319 12:17:25.900351 4, 0xFFFF, sum = 0
1320 12:17:25.903136 5, 0xFFFF, sum = 0
1321 12:17:25.903446 6, 0xFFFF, sum = 0
1322 12:17:25.906355 7, 0xFFFF, sum = 0
1323 12:17:25.906632 8, 0xFFFF, sum = 0
1324 12:17:25.910355 9, 0x0, sum = 1
1325 12:17:25.910804 10, 0x0, sum = 2
1326 12:17:25.913184 11, 0x0, sum = 3
1327 12:17:25.913584 12, 0x0, sum = 4
1328 12:17:25.916774 best_step = 10
1329 12:17:25.917276
1330 12:17:25.917596 ==
1331 12:17:25.919769 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 12:17:25.923096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 12:17:25.923830 ==
1334 12:17:25.926703 RX Vref Scan: 0
1335 12:17:25.927176
1336 12:17:25.927507 RX Vref 0 -> 0, step: 1
1337 12:17:25.927814
1338 12:17:25.929853 RX Delay -95 -> 252, step: 8
1339 12:17:25.936650 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1340 12:17:25.939812 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1341 12:17:25.943031 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1342 12:17:25.946223 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1343 12:17:25.950052 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1344 12:17:25.956848 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1345 12:17:25.960046 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1346 12:17:25.963372 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1347 12:17:25.966609 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1348 12:17:25.970150 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1349 12:17:25.973131 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1350 12:17:25.979910 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1351 12:17:25.983070 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1352 12:17:25.987061 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1353 12:17:25.990409 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1354 12:17:25.996489 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1355 12:17:25.996900 ==
1356 12:17:25.999722 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 12:17:26.003561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 12:17:26.004068 ==
1359 12:17:26.004451 DQS Delay:
1360 12:17:26.006538 DQS0 = 0, DQS1 = 0
1361 12:17:26.006945 DQM Delay:
1362 12:17:26.010211 DQM0 = 92, DQM1 = 83
1363 12:17:26.010721 DQ Delay:
1364 12:17:26.013090 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1365 12:17:26.017046 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1366 12:17:26.020330 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1367 12:17:26.023405 DQ12 =92, DQ13 =84, DQ14 =92, DQ15 =92
1368 12:17:26.023931
1369 12:17:26.024263
1370 12:17:26.030134 [DQSOSCAuto] RK1, (LSB)MR18= 0x4112, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1371 12:17:26.033275 CH0 RK1: MR19=606, MR18=4112
1372 12:17:26.040448 CH0_RK1: MR19=0x606, MR18=0x4112, DQSOSC=393, MR23=63, INC=95, DEC=63
1373 12:17:26.043541 [RxdqsGatingPostProcess] freq 800
1374 12:17:26.050120 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 12:17:26.050651 Pre-setting of DQS Precalculation
1376 12:17:26.056852 [DualRankRxdatlatCal] RK0: 9, RK1: 10, Final_Datlat 10
1377 12:17:26.057363 ==
1378 12:17:26.060704 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 12:17:26.064087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 12:17:26.064663 ==
1381 12:17:26.070476 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 12:17:26.076736 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 12:17:26.085057 [CA 0] Center 36 (6~67) winsize 62
1384 12:17:26.088683 [CA 1] Center 36 (6~67) winsize 62
1385 12:17:26.091681 [CA 2] Center 35 (5~65) winsize 61
1386 12:17:26.094879 [CA 3] Center 34 (4~65) winsize 62
1387 12:17:26.098163 [CA 4] Center 35 (5~65) winsize 61
1388 12:17:26.101612 [CA 5] Center 34 (4~65) winsize 62
1389 12:17:26.102046
1390 12:17:26.104657 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1391 12:17:26.105071
1392 12:17:26.108230 [CATrainingPosCal] consider 1 rank data
1393 12:17:26.111313 u2DelayCellTimex100 = 270/100 ps
1394 12:17:26.114973 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1395 12:17:26.118312 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 12:17:26.124862 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1397 12:17:26.127699 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1398 12:17:26.132020 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1399 12:17:26.134846 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1400 12:17:26.135354
1401 12:17:26.138093 CA PerBit enable=1, Macro0, CA PI delay=34
1402 12:17:26.138599
1403 12:17:26.141196 [CBTSetCACLKResult] CA Dly = 34
1404 12:17:26.141703 CS Dly: 6 (0~37)
1405 12:17:26.142033 ==
1406 12:17:26.144868 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 12:17:26.151127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 12:17:26.151540 ==
1409 12:17:26.154777 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 12:17:26.160976 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 12:17:26.171553 [CA 0] Center 36 (6~67) winsize 62
1412 12:17:26.174727 [CA 1] Center 37 (6~68) winsize 63
1413 12:17:26.178650 [CA 2] Center 35 (4~66) winsize 63
1414 12:17:26.182478 [CA 3] Center 34 (4~65) winsize 62
1415 12:17:26.186312 [CA 4] Center 35 (4~66) winsize 63
1416 12:17:26.186729 [CA 5] Center 34 (4~65) winsize 62
1417 12:17:26.187056
1418 12:17:26.190095 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1419 12:17:26.194120
1420 12:17:26.194618 [CATrainingPosCal] consider 2 rank data
1421 12:17:26.196869 u2DelayCellTimex100 = 270/100 ps
1422 12:17:26.200602 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 12:17:26.207026 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 12:17:26.210985 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1425 12:17:26.214143 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 12:17:26.217859 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1427 12:17:26.220768 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1428 12:17:26.221271
1429 12:17:26.223813 CA PerBit enable=1, Macro0, CA PI delay=34
1430 12:17:26.224357
1431 12:17:26.227572 [CBTSetCACLKResult] CA Dly = 34
1432 12:17:26.228011 CS Dly: 6 (0~38)
1433 12:17:26.228381
1434 12:17:26.230521 ----->DramcWriteLeveling(PI) begin...
1435 12:17:26.234109 ==
1436 12:17:26.237423 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 12:17:26.240637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 12:17:26.241149 ==
1439 12:17:26.244264 Write leveling (Byte 0): 27 => 27
1440 12:17:26.247603 Write leveling (Byte 1): 26 => 26
1441 12:17:26.250594 DramcWriteLeveling(PI) end<-----
1442 12:17:26.251011
1443 12:17:26.251335 ==
1444 12:17:26.254018 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 12:17:26.257479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 12:17:26.257898 ==
1447 12:17:26.260974 [Gating] SW mode calibration
1448 12:17:26.267216 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 12:17:26.270343 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 12:17:26.277216 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 12:17:26.280282 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1452 12:17:26.283582 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 12:17:26.290476 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 12:17:26.293722 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 12:17:26.296944 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 12:17:26.303469 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 12:17:26.307322 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 12:17:26.310395 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 12:17:26.317486 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 12:17:26.320636 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 12:17:26.324323 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 12:17:26.330631 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 12:17:26.333663 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 12:17:26.337467 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 12:17:26.344243 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 12:17:26.347402 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1467 12:17:26.350961 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1468 12:17:26.357342 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 12:17:26.360663 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 12:17:26.364103 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 12:17:26.366924 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 12:17:26.374415 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:17:26.377360 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:17:26.380536 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:17:26.387505 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1476 12:17:26.391007 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1477 12:17:26.394195 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 12:17:26.400806 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 12:17:26.403837 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 12:17:26.407531 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 12:17:26.414214 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 12:17:26.417765 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
1483 12:17:26.420839 0 10 4 | B1->B0 | 3131 2f2f | 0 0 | (1 1) (1 1)
1484 12:17:26.424514 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1485 12:17:26.431158 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:17:26.434093 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 12:17:26.437777 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 12:17:26.444744 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:17:26.447965 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:17:26.451025 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:17:26.457667 0 11 4 | B1->B0 | 2a2a 3636 | 0 0 | (0 0) (1 1)
1492 12:17:26.460850 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1493 12:17:26.465053 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 12:17:26.471308 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 12:17:26.474611 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 12:17:26.477802 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 12:17:26.484773 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 12:17:26.488049 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1499 12:17:26.491281 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1500 12:17:26.498209 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 12:17:26.501090 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 12:17:26.504782 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 12:17:26.511042 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 12:17:26.514947 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 12:17:26.517836 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 12:17:26.521156 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 12:17:26.528171 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 12:17:26.530860 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 12:17:26.534417 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 12:17:26.541236 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 12:17:26.544457 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 12:17:26.547906 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 12:17:26.554299 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 12:17:26.557692 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 12:17:26.561676 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1516 12:17:26.568004 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 12:17:26.568574 Total UI for P1: 0, mck2ui 16
1518 12:17:26.574844 best dqsien dly found for B0: ( 0, 14, 4)
1519 12:17:26.575352 Total UI for P1: 0, mck2ui 16
1520 12:17:26.577931 best dqsien dly found for B1: ( 0, 14, 4)
1521 12:17:26.581097 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1522 12:17:26.588464 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1523 12:17:26.588968
1524 12:17:26.591627 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1525 12:17:26.594540 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1526 12:17:26.598619 [Gating] SW calibration Done
1527 12:17:26.599146 ==
1528 12:17:26.601393 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 12:17:26.604978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 12:17:26.605392 ==
1531 12:17:26.605721 RX Vref Scan: 0
1532 12:17:26.607722
1533 12:17:26.608132 RX Vref 0 -> 0, step: 1
1534 12:17:26.608513
1535 12:17:26.611546 RX Delay -130 -> 252, step: 16
1536 12:17:26.614729 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1537 12:17:26.618001 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1538 12:17:26.625170 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1539 12:17:26.628620 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1540 12:17:26.631363 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1541 12:17:26.634867 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1542 12:17:26.638472 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1543 12:17:26.645128 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1544 12:17:26.648143 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1545 12:17:26.651812 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1546 12:17:26.655309 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1547 12:17:26.658212 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1548 12:17:26.665033 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1549 12:17:26.668871 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1550 12:17:26.672280 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1551 12:17:26.675280 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1552 12:17:26.675789 ==
1553 12:17:26.678384 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 12:17:26.681458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 12:17:26.685239 ==
1556 12:17:26.685743 DQS Delay:
1557 12:17:26.686068 DQS0 = 0, DQS1 = 0
1558 12:17:26.688477 DQM Delay:
1559 12:17:26.688889 DQM0 = 92, DQM1 = 87
1560 12:17:26.692024 DQ Delay:
1561 12:17:26.692660 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1562 12:17:26.694914 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1563 12:17:26.698740 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1564 12:17:26.701946 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1565 12:17:26.702365
1566 12:17:26.704861
1567 12:17:26.705271 ==
1568 12:17:26.708199 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 12:17:26.712009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 12:17:26.712566 ==
1571 12:17:26.712901
1572 12:17:26.713205
1573 12:17:26.714930 TX Vref Scan disable
1574 12:17:26.715339 == TX Byte 0 ==
1575 12:17:26.722097 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1576 12:17:26.725102 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1577 12:17:26.725523 == TX Byte 1 ==
1578 12:17:26.731792 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1579 12:17:26.734841 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1580 12:17:26.735256 ==
1581 12:17:26.738702 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 12:17:26.741980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 12:17:26.742506 ==
1584 12:17:26.755500 TX Vref=22, minBit 0, minWin=26, winSum=433
1585 12:17:26.758890 TX Vref=24, minBit 3, minWin=26, winSum=442
1586 12:17:26.761880 TX Vref=26, minBit 3, minWin=26, winSum=440
1587 12:17:26.765072 TX Vref=28, minBit 1, minWin=27, winSum=446
1588 12:17:26.769082 TX Vref=30, minBit 2, minWin=26, winSum=444
1589 12:17:26.775323 TX Vref=32, minBit 2, minWin=26, winSum=442
1590 12:17:26.778165 [TxChooseVref] Worse bit 1, Min win 27, Win sum 446, Final Vref 28
1591 12:17:26.778583
1592 12:17:26.781771 Final TX Range 1 Vref 28
1593 12:17:26.782280
1594 12:17:26.782605 ==
1595 12:17:26.784921 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 12:17:26.789006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 12:17:26.789511 ==
1598 12:17:26.789841
1599 12:17:26.791840
1600 12:17:26.792249 TX Vref Scan disable
1601 12:17:26.794991 == TX Byte 0 ==
1602 12:17:26.798388 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1603 12:17:26.801570 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1604 12:17:26.805218 == TX Byte 1 ==
1605 12:17:26.808330 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1606 12:17:26.811826 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1607 12:17:26.815596
1608 12:17:26.816099 [DATLAT]
1609 12:17:26.816482 Freq=800, CH1 RK0
1610 12:17:26.816795
1611 12:17:26.818608 DATLAT Default: 0xa
1612 12:17:26.819037 0, 0xFFFF, sum = 0
1613 12:17:26.821691 1, 0xFFFF, sum = 0
1614 12:17:26.822109 2, 0xFFFF, sum = 0
1615 12:17:26.824923 3, 0xFFFF, sum = 0
1616 12:17:26.825371 4, 0xFFFF, sum = 0
1617 12:17:26.827937 5, 0xFFFF, sum = 0
1618 12:17:26.831725 6, 0xFFFF, sum = 0
1619 12:17:26.832236 7, 0xFFFF, sum = 0
1620 12:17:26.834817 8, 0xFFFF, sum = 0
1621 12:17:26.835235 9, 0x0, sum = 1
1622 12:17:26.835566 10, 0x0, sum = 2
1623 12:17:26.838204 11, 0x0, sum = 3
1624 12:17:26.838623 12, 0x0, sum = 4
1625 12:17:26.841774 best_step = 10
1626 12:17:26.842284
1627 12:17:26.842610 ==
1628 12:17:26.845011 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 12:17:26.848433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 12:17:26.848956 ==
1631 12:17:26.851583 RX Vref Scan: 1
1632 12:17:26.852106
1633 12:17:26.852495 Set Vref Range= 32 -> 127
1634 12:17:26.852811
1635 12:17:26.854647 RX Vref 32 -> 127, step: 1
1636 12:17:26.855062
1637 12:17:26.858010 RX Delay -79 -> 252, step: 8
1638 12:17:26.858426
1639 12:17:26.861719 Set Vref, RX VrefLevel [Byte0]: 32
1640 12:17:26.864823 [Byte1]: 32
1641 12:17:26.865241
1642 12:17:26.868165 Set Vref, RX VrefLevel [Byte0]: 33
1643 12:17:26.871994 [Byte1]: 33
1644 12:17:26.875542
1645 12:17:26.876198 Set Vref, RX VrefLevel [Byte0]: 34
1646 12:17:26.878801 [Byte1]: 34
1647 12:17:26.882662
1648 12:17:26.883073 Set Vref, RX VrefLevel [Byte0]: 35
1649 12:17:26.885804 [Byte1]: 35
1650 12:17:26.890533
1651 12:17:26.891042 Set Vref, RX VrefLevel [Byte0]: 36
1652 12:17:26.893463 [Byte1]: 36
1653 12:17:26.897732
1654 12:17:26.898141 Set Vref, RX VrefLevel [Byte0]: 37
1655 12:17:26.900816 [Byte1]: 37
1656 12:17:26.905513
1657 12:17:26.906022 Set Vref, RX VrefLevel [Byte0]: 38
1658 12:17:26.908710 [Byte1]: 38
1659 12:17:26.913150
1660 12:17:26.913655 Set Vref, RX VrefLevel [Byte0]: 39
1661 12:17:26.916422 [Byte1]: 39
1662 12:17:26.920855
1663 12:17:26.921263 Set Vref, RX VrefLevel [Byte0]: 40
1664 12:17:26.924226 [Byte1]: 40
1665 12:17:26.928381
1666 12:17:26.928888 Set Vref, RX VrefLevel [Byte0]: 41
1667 12:17:26.931410 [Byte1]: 41
1668 12:17:26.935576
1669 12:17:26.936062 Set Vref, RX VrefLevel [Byte0]: 42
1670 12:17:26.938971 [Byte1]: 42
1671 12:17:26.943508
1672 12:17:26.944020 Set Vref, RX VrefLevel [Byte0]: 43
1673 12:17:26.946408 [Byte1]: 43
1674 12:17:26.950904
1675 12:17:26.951590 Set Vref, RX VrefLevel [Byte0]: 44
1676 12:17:26.954150 [Byte1]: 44
1677 12:17:26.958078
1678 12:17:26.958590 Set Vref, RX VrefLevel [Byte0]: 45
1679 12:17:26.961790 [Byte1]: 45
1680 12:17:26.965510
1681 12:17:26.966185 Set Vref, RX VrefLevel [Byte0]: 46
1682 12:17:26.968900 [Byte1]: 46
1683 12:17:26.973693
1684 12:17:26.974105 Set Vref, RX VrefLevel [Byte0]: 47
1685 12:17:26.976490 [Byte1]: 47
1686 12:17:26.980935
1687 12:17:26.981358 Set Vref, RX VrefLevel [Byte0]: 48
1688 12:17:26.983930 [Byte1]: 48
1689 12:17:26.988257
1690 12:17:26.988712 Set Vref, RX VrefLevel [Byte0]: 49
1691 12:17:26.991725 [Byte1]: 49
1692 12:17:26.995824
1693 12:17:26.996252 Set Vref, RX VrefLevel [Byte0]: 50
1694 12:17:26.999169 [Byte1]: 50
1695 12:17:27.003415
1696 12:17:27.004054 Set Vref, RX VrefLevel [Byte0]: 51
1697 12:17:27.007035 [Byte1]: 51
1698 12:17:27.011051
1699 12:17:27.011464 Set Vref, RX VrefLevel [Byte0]: 52
1700 12:17:27.014361 [Byte1]: 52
1701 12:17:27.019209
1702 12:17:27.019717 Set Vref, RX VrefLevel [Byte0]: 53
1703 12:17:27.022423 [Byte1]: 53
1704 12:17:27.026144
1705 12:17:27.026687 Set Vref, RX VrefLevel [Byte0]: 54
1706 12:17:27.029274 [Byte1]: 54
1707 12:17:27.033977
1708 12:17:27.034482 Set Vref, RX VrefLevel [Byte0]: 55
1709 12:17:27.036810 [Byte1]: 55
1710 12:17:27.041545
1711 12:17:27.042049 Set Vref, RX VrefLevel [Byte0]: 56
1712 12:17:27.044475 [Byte1]: 56
1713 12:17:27.049337
1714 12:17:27.049842 Set Vref, RX VrefLevel [Byte0]: 57
1715 12:17:27.052527 [Byte1]: 57
1716 12:17:27.056372
1717 12:17:27.056881 Set Vref, RX VrefLevel [Byte0]: 58
1718 12:17:27.059499 [Byte1]: 58
1719 12:17:27.064042
1720 12:17:27.064596 Set Vref, RX VrefLevel [Byte0]: 59
1721 12:17:27.069992 [Byte1]: 59
1722 12:17:27.070494
1723 12:17:27.074051 Set Vref, RX VrefLevel [Byte0]: 60
1724 12:17:27.077329 [Byte1]: 60
1725 12:17:27.077834
1726 12:17:27.080704 Set Vref, RX VrefLevel [Byte0]: 61
1727 12:17:27.083566 [Byte1]: 61
1728 12:17:27.083977
1729 12:17:27.086924 Set Vref, RX VrefLevel [Byte0]: 62
1730 12:17:27.090505 [Byte1]: 62
1731 12:17:27.094547
1732 12:17:27.095134 Set Vref, RX VrefLevel [Byte0]: 63
1733 12:17:27.097542 [Byte1]: 63
1734 12:17:27.101984
1735 12:17:27.102397 Set Vref, RX VrefLevel [Byte0]: 64
1736 12:17:27.104832 [Byte1]: 64
1737 12:17:27.108862
1738 12:17:27.109271 Set Vref, RX VrefLevel [Byte0]: 65
1739 12:17:27.112187 [Byte1]: 65
1740 12:17:27.116901
1741 12:17:27.117408 Set Vref, RX VrefLevel [Byte0]: 66
1742 12:17:27.120003 [Byte1]: 66
1743 12:17:27.123986
1744 12:17:27.124541 Set Vref, RX VrefLevel [Byte0]: 67
1745 12:17:27.127473 [Byte1]: 67
1746 12:17:27.131519
1747 12:17:27.131930 Set Vref, RX VrefLevel [Byte0]: 68
1748 12:17:27.135433 [Byte1]: 68
1749 12:17:27.139416
1750 12:17:27.139923 Set Vref, RX VrefLevel [Byte0]: 69
1751 12:17:27.142445 [Byte1]: 69
1752 12:17:27.146815
1753 12:17:27.147225 Set Vref, RX VrefLevel [Byte0]: 70
1754 12:17:27.150477 [Byte1]: 70
1755 12:17:27.155044
1756 12:17:27.155624 Set Vref, RX VrefLevel [Byte0]: 71
1757 12:17:27.157937 [Byte1]: 71
1758 12:17:27.162332
1759 12:17:27.162742 Final RX Vref Byte 0 = 61 to rank0
1760 12:17:27.165553 Final RX Vref Byte 1 = 55 to rank0
1761 12:17:27.168600 Final RX Vref Byte 0 = 61 to rank1
1762 12:17:27.172722 Final RX Vref Byte 1 = 55 to rank1==
1763 12:17:27.175769 Dram Type= 6, Freq= 0, CH_1, rank 0
1764 12:17:27.178872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1765 12:17:27.182288 ==
1766 12:17:27.183011 DQS Delay:
1767 12:17:27.183367 DQS0 = 0, DQS1 = 0
1768 12:17:27.185415 DQM Delay:
1769 12:17:27.185827 DQM0 = 95, DQM1 = 90
1770 12:17:27.188817 DQ Delay:
1771 12:17:27.192445 DQ0 =100, DQ1 =88, DQ2 =88, DQ3 =88
1772 12:17:27.195649 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
1773 12:17:27.196062 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1774 12:17:27.201762 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1775 12:17:27.202173
1776 12:17:27.202495
1777 12:17:27.209078 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d49, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1778 12:17:27.212052 CH1 RK0: MR19=606, MR18=2D49
1779 12:17:27.219005 CH1_RK0: MR19=0x606, MR18=0x2D49, DQSOSC=391, MR23=63, INC=96, DEC=64
1780 12:17:27.219538
1781 12:17:27.222206 ----->DramcWriteLeveling(PI) begin...
1782 12:17:27.222715 ==
1783 12:17:27.225598 Dram Type= 6, Freq= 0, CH_1, rank 1
1784 12:17:27.228858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1785 12:17:27.229273 ==
1786 12:17:27.232240 Write leveling (Byte 0): 26 => 26
1787 12:17:27.235410 Write leveling (Byte 1): 27 => 27
1788 12:17:27.239330 DramcWriteLeveling(PI) end<-----
1789 12:17:27.239837
1790 12:17:27.240161 ==
1791 12:17:27.241905 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 12:17:27.245823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 12:17:27.246237 ==
1794 12:17:27.248924 [Gating] SW mode calibration
1795 12:17:27.255452 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1796 12:17:27.261783 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1797 12:17:27.265361 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1798 12:17:27.268530 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1799 12:17:27.274901 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1800 12:17:27.278510 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1801 12:17:27.281946 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1802 12:17:27.288895 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 12:17:27.291849 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 12:17:27.295067 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 12:17:27.301934 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 12:17:27.305217 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 12:17:27.308477 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 12:17:27.315669 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 12:17:27.319109 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 12:17:27.322129 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 12:17:27.328494 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 12:17:27.331803 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 12:17:27.335059 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1814 12:17:27.338915 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1815 12:17:27.345546 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 12:17:27.348920 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 12:17:27.352058 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 12:17:27.358847 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 12:17:27.362104 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 12:17:27.365071 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 12:17:27.372021 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 12:17:27.375129 0 9 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1823 12:17:27.378881 0 9 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
1824 12:17:27.385357 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1825 12:17:27.388753 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1826 12:17:27.392683 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 12:17:27.398383 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 12:17:27.401971 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 12:17:27.406086 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1830 12:17:27.412112 0 10 4 | B1->B0 | 2e2e 3030 | 0 0 | (1 0) (0 1)
1831 12:17:27.415690 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
1832 12:17:27.418820 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:17:27.425270 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:17:27.428667 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:17:27.432073 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 12:17:27.435302 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 12:17:27.442033 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1838 12:17:27.445226 0 11 4 | B1->B0 | 3a3a 2a2a | 0 0 | (0 0) (0 0)
1839 12:17:27.448844 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1840 12:17:27.455596 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1841 12:17:27.458809 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 12:17:27.462712 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 12:17:27.468650 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 12:17:27.472207 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 12:17:27.475818 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 12:17:27.481862 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1847 12:17:27.485206 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1848 12:17:27.488550 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1849 12:17:27.495268 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1850 12:17:27.499064 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 12:17:27.502094 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 12:17:27.508521 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 12:17:27.512048 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 12:17:27.515576 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 12:17:27.518987 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 12:17:27.525467 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 12:17:27.528991 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 12:17:27.532254 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 12:17:27.538863 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 12:17:27.542134 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 12:17:27.545173 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 12:17:27.551944 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1863 12:17:27.554979 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 12:17:27.558632 Total UI for P1: 0, mck2ui 16
1865 12:17:27.562010 best dqsien dly found for B0: ( 0, 14, 4)
1866 12:17:27.565913 Total UI for P1: 0, mck2ui 16
1867 12:17:27.568856 best dqsien dly found for B1: ( 0, 14, 4)
1868 12:17:27.571816 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1869 12:17:27.575461 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1870 12:17:27.575943
1871 12:17:27.579196 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1872 12:17:27.582020 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1873 12:17:27.585609 [Gating] SW calibration Done
1874 12:17:27.586146 ==
1875 12:17:27.588612 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 12:17:27.591805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1877 12:17:27.592381 ==
1878 12:17:27.595548 RX Vref Scan: 0
1879 12:17:27.595996
1880 12:17:27.598753 RX Vref 0 -> 0, step: 1
1881 12:17:27.599297
1882 12:17:27.599805 RX Delay -130 -> 252, step: 16
1883 12:17:27.605981 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1884 12:17:27.609167 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1885 12:17:27.612405 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1886 12:17:27.615435 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1887 12:17:27.618727 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1888 12:17:27.625805 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1889 12:17:27.629009 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1890 12:17:27.632189 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1891 12:17:27.635989 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1892 12:17:27.639348 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1893 12:17:27.645315 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1894 12:17:27.648922 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1895 12:17:27.652305 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1896 12:17:27.655715 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1897 12:17:27.658955 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1898 12:17:27.665800 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1899 12:17:27.666229 ==
1900 12:17:27.669139 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 12:17:27.672270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1902 12:17:27.672750 ==
1903 12:17:27.673188 DQS Delay:
1904 12:17:27.675829 DQS0 = 0, DQS1 = 0
1905 12:17:27.676256 DQM Delay:
1906 12:17:27.679702 DQM0 = 92, DQM1 = 88
1907 12:17:27.680238 DQ Delay:
1908 12:17:27.682418 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1909 12:17:27.685788 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1910 12:17:27.688901 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1911 12:17:27.692466 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1912 12:17:27.693003
1913 12:17:27.693465
1914 12:17:27.693875 ==
1915 12:17:27.695573 Dram Type= 6, Freq= 0, CH_1, rank 1
1916 12:17:27.698948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1917 12:17:27.699425 ==
1918 12:17:27.702773
1919 12:17:27.703200
1920 12:17:27.703638 TX Vref Scan disable
1921 12:17:27.706099 == TX Byte 0 ==
1922 12:17:27.709256 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1923 12:17:27.712708 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1924 12:17:27.715950 == TX Byte 1 ==
1925 12:17:27.719016 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1926 12:17:27.722041 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1927 12:17:27.722497 ==
1928 12:17:27.725828 Dram Type= 6, Freq= 0, CH_1, rank 1
1929 12:17:27.732079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1930 12:17:27.732566 ==
1931 12:17:27.744227 TX Vref=22, minBit 1, minWin=26, winSum=442
1932 12:17:27.747679 TX Vref=24, minBit 0, minWin=27, winSum=442
1933 12:17:27.751324 TX Vref=26, minBit 0, minWin=27, winSum=447
1934 12:17:27.754516 TX Vref=28, minBit 1, minWin=27, winSum=447
1935 12:17:27.757516 TX Vref=30, minBit 0, minWin=27, winSum=448
1936 12:17:27.760712 TX Vref=32, minBit 1, minWin=27, winSum=445
1937 12:17:27.767487 [TxChooseVref] Worse bit 0, Min win 27, Win sum 448, Final Vref 30
1938 12:17:27.767918
1939 12:17:27.770620 Final TX Range 1 Vref 30
1940 12:17:27.771103
1941 12:17:27.771537 ==
1942 12:17:27.774235 Dram Type= 6, Freq= 0, CH_1, rank 1
1943 12:17:27.777912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1944 12:17:27.778450 ==
1945 12:17:27.778897
1946 12:17:27.780996
1947 12:17:27.781426 TX Vref Scan disable
1948 12:17:27.784107 == TX Byte 0 ==
1949 12:17:27.787913 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1950 12:17:27.791294 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1951 12:17:27.794031 == TX Byte 1 ==
1952 12:17:27.797426 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1953 12:17:27.800866 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1954 12:17:27.804144
1955 12:17:27.804631 [DATLAT]
1956 12:17:27.805064 Freq=800, CH1 RK1
1957 12:17:27.805474
1958 12:17:27.807460 DATLAT Default: 0xa
1959 12:17:27.807887 0, 0xFFFF, sum = 0
1960 12:17:27.810953 1, 0xFFFF, sum = 0
1961 12:17:27.811490 2, 0xFFFF, sum = 0
1962 12:17:27.814258 3, 0xFFFF, sum = 0
1963 12:17:27.814795 4, 0xFFFF, sum = 0
1964 12:17:27.817616 5, 0xFFFF, sum = 0
1965 12:17:27.818159 6, 0xFFFF, sum = 0
1966 12:17:27.820917 7, 0xFFFF, sum = 0
1967 12:17:27.824067 8, 0xFFFF, sum = 0
1968 12:17:27.824586 9, 0x0, sum = 1
1969 12:17:27.825037 10, 0x0, sum = 2
1970 12:17:27.827634 11, 0x0, sum = 3
1971 12:17:27.828117 12, 0x0, sum = 4
1972 12:17:27.830794 best_step = 10
1973 12:17:27.831224
1974 12:17:27.831661 ==
1975 12:17:27.834440 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 12:17:27.837279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 12:17:27.837714 ==
1978 12:17:27.841092 RX Vref Scan: 0
1979 12:17:27.841524
1980 12:17:27.841870 RX Vref 0 -> 0, step: 1
1981 12:17:27.842205
1982 12:17:27.844143 RX Delay -79 -> 252, step: 8
1983 12:17:27.850971 iDelay=209, Bit 0, Center 100 (1 ~ 200) 200
1984 12:17:27.854363 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1985 12:17:27.857884 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1986 12:17:27.860968 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1987 12:17:27.864876 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1988 12:17:27.867444 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
1989 12:17:27.874492 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1990 12:17:27.877764 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1991 12:17:27.881452 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1992 12:17:27.886471 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1993 12:17:27.887584 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
1994 12:17:27.891017 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
1995 12:17:27.897963 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1996 12:17:27.900889 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
1997 12:17:27.905974 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
1998 12:17:27.907615 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
1999 12:17:27.908027 ==
2000 12:17:27.911102 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 12:17:27.917414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 12:17:27.917829 ==
2003 12:17:27.918155 DQS Delay:
2004 12:17:27.921473 DQS0 = 0, DQS1 = 0
2005 12:17:27.921990 DQM Delay:
2006 12:17:27.922321 DQM0 = 96, DQM1 = 90
2007 12:17:27.924556 DQ Delay:
2008 12:17:27.927854 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =92
2009 12:17:27.931360 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2010 12:17:27.934145 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2011 12:17:27.937450 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2012 12:17:27.937860
2013 12:17:27.938179
2014 12:17:27.944008 [DQSOSCAuto] RK1, (LSB)MR18= 0x4710, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2015 12:17:27.947502 CH1 RK1: MR19=606, MR18=4710
2016 12:17:27.954358 CH1_RK1: MR19=0x606, MR18=0x4710, DQSOSC=392, MR23=63, INC=96, DEC=64
2017 12:17:27.957847 [RxdqsGatingPostProcess] freq 800
2018 12:17:27.961038 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2019 12:17:27.964495 Pre-setting of DQS Precalculation
2020 12:17:27.971007 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2021 12:17:27.977436 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2022 12:17:27.984430 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2023 12:17:27.985002
2024 12:17:27.985336
2025 12:17:27.987538 [Calibration Summary] 1600 Mbps
2026 12:17:27.988059 CH 0, Rank 0
2027 12:17:27.990923 SW Impedance : PASS
2028 12:17:27.994179 DUTY Scan : NO K
2029 12:17:27.994595 ZQ Calibration : PASS
2030 12:17:27.997388 Jitter Meter : NO K
2031 12:17:28.000970 CBT Training : PASS
2032 12:17:28.001388 Write leveling : PASS
2033 12:17:28.004384 RX DQS gating : PASS
2034 12:17:28.007488 RX DQ/DQS(RDDQC) : PASS
2035 12:17:28.007902 TX DQ/DQS : PASS
2036 12:17:28.011102 RX DATLAT : PASS
2037 12:17:28.014721 RX DQ/DQS(Engine): PASS
2038 12:17:28.015269 TX OE : NO K
2039 12:17:28.015667 All Pass.
2040 12:17:28.017602
2041 12:17:28.018010 CH 0, Rank 1
2042 12:17:28.021689 SW Impedance : PASS
2043 12:17:28.022099 DUTY Scan : NO K
2044 12:17:28.024652 ZQ Calibration : PASS
2045 12:17:28.025058 Jitter Meter : NO K
2046 12:17:28.027812 CBT Training : PASS
2047 12:17:28.031063 Write leveling : PASS
2048 12:17:28.031469 RX DQS gating : PASS
2049 12:17:28.034334 RX DQ/DQS(RDDQC) : PASS
2050 12:17:28.037492 TX DQ/DQS : PASS
2051 12:17:28.037902 RX DATLAT : PASS
2052 12:17:28.041598 RX DQ/DQS(Engine): PASS
2053 12:17:28.044766 TX OE : NO K
2054 12:17:28.045212 All Pass.
2055 12:17:28.045541
2056 12:17:28.045843 CH 1, Rank 0
2057 12:17:28.047743 SW Impedance : PASS
2058 12:17:28.051369 DUTY Scan : NO K
2059 12:17:28.051902 ZQ Calibration : PASS
2060 12:17:28.054442 Jitter Meter : NO K
2061 12:17:28.057421 CBT Training : PASS
2062 12:17:28.057986 Write leveling : PASS
2063 12:17:28.060711 RX DQS gating : PASS
2064 12:17:28.061141 RX DQ/DQS(RDDQC) : PASS
2065 12:17:28.064589 TX DQ/DQS : PASS
2066 12:17:28.067615 RX DATLAT : PASS
2067 12:17:28.068170 RX DQ/DQS(Engine): PASS
2068 12:17:28.070978 TX OE : NO K
2069 12:17:28.071407 All Pass.
2070 12:17:28.071770
2071 12:17:28.074065 CH 1, Rank 1
2072 12:17:28.074481 SW Impedance : PASS
2073 12:17:28.077642 DUTY Scan : NO K
2074 12:17:28.080876 ZQ Calibration : PASS
2075 12:17:28.081313 Jitter Meter : NO K
2076 12:17:28.084186 CBT Training : PASS
2077 12:17:28.087554 Write leveling : PASS
2078 12:17:28.087970 RX DQS gating : PASS
2079 12:17:28.091411 RX DQ/DQS(RDDQC) : PASS
2080 12:17:28.094262 TX DQ/DQS : PASS
2081 12:17:28.094848 RX DATLAT : PASS
2082 12:17:28.097612 RX DQ/DQS(Engine): PASS
2083 12:17:28.098202 TX OE : NO K
2084 12:17:28.101107 All Pass.
2085 12:17:28.101707
2086 12:17:28.102255 DramC Write-DBI off
2087 12:17:28.104694 PER_BANK_REFRESH: Hybrid Mode
2088 12:17:28.107679 TX_TRACKING: ON
2089 12:17:28.111350 [GetDramInforAfterCalByMRR] Vendor 6.
2090 12:17:28.114311 [GetDramInforAfterCalByMRR] Revision 606.
2091 12:17:28.117893 [GetDramInforAfterCalByMRR] Revision 2 0.
2092 12:17:28.118313 MR0 0x3b3b
2093 12:17:28.118805 MR8 0x5151
2094 12:17:28.124814 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2095 12:17:28.125236
2096 12:17:28.125563 MR0 0x3b3b
2097 12:17:28.125869 MR8 0x5151
2098 12:17:28.128356 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2099 12:17:28.128776
2100 12:17:28.137581 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2101 12:17:28.141646 [FAST_K] Save calibration result to emmc
2102 12:17:28.144628 [FAST_K] Save calibration result to emmc
2103 12:17:28.147668 dram_init: config_dvfs: 1
2104 12:17:28.151535 dramc_set_vcore_voltage set vcore to 662500
2105 12:17:28.154727 Read voltage for 1200, 2
2106 12:17:28.155164 Vio18 = 0
2107 12:17:28.155512 Vcore = 662500
2108 12:17:28.157862 Vdram = 0
2109 12:17:28.158281 Vddq = 0
2110 12:17:28.158667 Vmddr = 0
2111 12:17:28.164777 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2112 12:17:28.167927 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2113 12:17:28.171086 MEM_TYPE=3, freq_sel=15
2114 12:17:28.175009 sv_algorithm_assistance_LP4_1600
2115 12:17:28.177886 ============ PULL DRAM RESETB DOWN ============
2116 12:17:28.181399 ========== PULL DRAM RESETB DOWN end =========
2117 12:17:28.188363 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2118 12:17:28.191543 ===================================
2119 12:17:28.191960 LPDDR4 DRAM CONFIGURATION
2120 12:17:28.195430 ===================================
2121 12:17:28.198623 EX_ROW_EN[0] = 0x0
2122 12:17:28.201664 EX_ROW_EN[1] = 0x0
2123 12:17:28.202127 LP4Y_EN = 0x0
2124 12:17:28.204801 WORK_FSP = 0x0
2125 12:17:28.205396 WL = 0x4
2126 12:17:28.208067 RL = 0x4
2127 12:17:28.208686 BL = 0x2
2128 12:17:28.211300 RPST = 0x0
2129 12:17:28.211887 RD_PRE = 0x0
2130 12:17:28.215054 WR_PRE = 0x1
2131 12:17:28.215666 WR_PST = 0x0
2132 12:17:28.218261 DBI_WR = 0x0
2133 12:17:28.218645 DBI_RD = 0x0
2134 12:17:28.221581 OTF = 0x1
2135 12:17:28.224761 ===================================
2136 12:17:28.227886 ===================================
2137 12:17:28.228343 ANA top config
2138 12:17:28.231814 ===================================
2139 12:17:28.235236 DLL_ASYNC_EN = 0
2140 12:17:28.238410 ALL_SLAVE_EN = 0
2141 12:17:28.238825 NEW_RANK_MODE = 1
2142 12:17:28.242147 DLL_IDLE_MODE = 1
2143 12:17:28.244941 LP45_APHY_COMB_EN = 1
2144 12:17:28.248390 TX_ODT_DIS = 1
2145 12:17:28.251472 NEW_8X_MODE = 1
2146 12:17:28.254810 ===================================
2147 12:17:28.258217 ===================================
2148 12:17:28.258627 data_rate = 2400
2149 12:17:28.261895 CKR = 1
2150 12:17:28.265178 DQ_P2S_RATIO = 8
2151 12:17:28.268451 ===================================
2152 12:17:28.272134 CA_P2S_RATIO = 8
2153 12:17:28.275252 DQ_CA_OPEN = 0
2154 12:17:28.278443 DQ_SEMI_OPEN = 0
2155 12:17:28.278855 CA_SEMI_OPEN = 0
2156 12:17:28.281873 CA_FULL_RATE = 0
2157 12:17:28.285160 DQ_CKDIV4_EN = 0
2158 12:17:28.288175 CA_CKDIV4_EN = 0
2159 12:17:28.292020 CA_PREDIV_EN = 0
2160 12:17:28.295210 PH8_DLY = 17
2161 12:17:28.295748 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2162 12:17:28.298101 DQ_AAMCK_DIV = 4
2163 12:17:28.301579 CA_AAMCK_DIV = 4
2164 12:17:28.304849 CA_ADMCK_DIV = 4
2165 12:17:28.308062 DQ_TRACK_CA_EN = 0
2166 12:17:28.311875 CA_PICK = 1200
2167 12:17:28.312283 CA_MCKIO = 1200
2168 12:17:28.315129 MCKIO_SEMI = 0
2169 12:17:28.318571 PLL_FREQ = 2366
2170 12:17:28.322199 DQ_UI_PI_RATIO = 32
2171 12:17:28.325326 CA_UI_PI_RATIO = 0
2172 12:17:28.328539 ===================================
2173 12:17:28.332233 ===================================
2174 12:17:28.335183 memory_type:LPDDR4
2175 12:17:28.335594 GP_NUM : 10
2176 12:17:28.338566 SRAM_EN : 1
2177 12:17:28.339067 MD32_EN : 0
2178 12:17:28.342512 ===================================
2179 12:17:28.345679 [ANA_INIT] >>>>>>>>>>>>>>
2180 12:17:28.349036 <<<<<< [CONFIGURE PHASE]: ANA_TX
2181 12:17:28.352495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2182 12:17:28.355409 ===================================
2183 12:17:28.358576 data_rate = 2400,PCW = 0X5b00
2184 12:17:28.362473 ===================================
2185 12:17:28.365459 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2186 12:17:28.368618 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2187 12:17:28.375703 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2188 12:17:28.378525 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2189 12:17:28.381931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2190 12:17:28.385416 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2191 12:17:28.388738 [ANA_INIT] flow start
2192 12:17:28.392138 [ANA_INIT] PLL >>>>>>>>
2193 12:17:28.392648 [ANA_INIT] PLL <<<<<<<<
2194 12:17:28.394949 [ANA_INIT] MIDPI >>>>>>>>
2195 12:17:28.398457 [ANA_INIT] MIDPI <<<<<<<<
2196 12:17:28.401665 [ANA_INIT] DLL >>>>>>>>
2197 12:17:28.402153 [ANA_INIT] DLL <<<<<<<<
2198 12:17:28.405470 [ANA_INIT] flow end
2199 12:17:28.408450 ============ LP4 DIFF to SE enter ============
2200 12:17:28.411608 ============ LP4 DIFF to SE exit ============
2201 12:17:28.415245 [ANA_INIT] <<<<<<<<<<<<<
2202 12:17:28.418485 [Flow] Enable top DCM control >>>>>
2203 12:17:28.422232 [Flow] Enable top DCM control <<<<<
2204 12:17:28.425543 Enable DLL master slave shuffle
2205 12:17:28.428728 ==============================================================
2206 12:17:28.432084 Gating Mode config
2207 12:17:28.439106 ==============================================================
2208 12:17:28.439516 Config description:
2209 12:17:28.448866 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2210 12:17:28.455761 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2211 12:17:28.458682 SELPH_MODE 0: By rank 1: By Phase
2212 12:17:28.465975 ==============================================================
2213 12:17:28.468856 GAT_TRACK_EN = 1
2214 12:17:28.472166 RX_GATING_MODE = 2
2215 12:17:28.475434 RX_GATING_TRACK_MODE = 2
2216 12:17:28.479133 SELPH_MODE = 1
2217 12:17:28.482381 PICG_EARLY_EN = 1
2218 12:17:28.485415 VALID_LAT_VALUE = 1
2219 12:17:28.489207 ==============================================================
2220 12:17:28.492423 Enter into Gating configuration >>>>
2221 12:17:28.495836 Exit from Gating configuration <<<<
2222 12:17:28.498726 Enter into DVFS_PRE_config >>>>>
2223 12:17:28.509222 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2224 12:17:28.512402 Exit from DVFS_PRE_config <<<<<
2225 12:17:28.515774 Enter into PICG configuration >>>>
2226 12:17:28.519239 Exit from PICG configuration <<<<
2227 12:17:28.522913 [RX_INPUT] configuration >>>>>
2228 12:17:28.526911 [RX_INPUT] configuration <<<<<
2229 12:17:28.529103 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2230 12:17:28.535898 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2231 12:17:28.543262 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2232 12:17:28.549304 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2233 12:17:28.555941 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2234 12:17:28.559708 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2235 12:17:28.566325 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2236 12:17:28.569301 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2237 12:17:28.572703 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2238 12:17:28.576528 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2239 12:17:28.582950 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2240 12:17:28.586503 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2241 12:17:28.589438 ===================================
2242 12:17:28.592629 LPDDR4 DRAM CONFIGURATION
2243 12:17:28.596051 ===================================
2244 12:17:28.596565 EX_ROW_EN[0] = 0x0
2245 12:17:28.599377 EX_ROW_EN[1] = 0x0
2246 12:17:28.599903 LP4Y_EN = 0x0
2247 12:17:28.602616 WORK_FSP = 0x0
2248 12:17:28.603022 WL = 0x4
2249 12:17:28.606121 RL = 0x4
2250 12:17:28.606630 BL = 0x2
2251 12:17:28.609102 RPST = 0x0
2252 12:17:28.609548 RD_PRE = 0x0
2253 12:17:28.612419 WR_PRE = 0x1
2254 12:17:28.612825 WR_PST = 0x0
2255 12:17:28.616049 DBI_WR = 0x0
2256 12:17:28.619332 DBI_RD = 0x0
2257 12:17:28.619738 OTF = 0x1
2258 12:17:28.622713 ===================================
2259 12:17:28.626038 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2260 12:17:28.629378 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2261 12:17:28.636264 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2262 12:17:28.639877 ===================================
2263 12:17:28.640442 LPDDR4 DRAM CONFIGURATION
2264 12:17:28.642700 ===================================
2265 12:17:28.645868 EX_ROW_EN[0] = 0x10
2266 12:17:28.649532 EX_ROW_EN[1] = 0x0
2267 12:17:28.650080 LP4Y_EN = 0x0
2268 12:17:28.652561 WORK_FSP = 0x0
2269 12:17:28.653054 WL = 0x4
2270 12:17:28.655836 RL = 0x4
2271 12:17:28.656414 BL = 0x2
2272 12:17:28.659248 RPST = 0x0
2273 12:17:28.659652 RD_PRE = 0x0
2274 12:17:28.662506 WR_PRE = 0x1
2275 12:17:28.662994 WR_PST = 0x0
2276 12:17:28.666504 DBI_WR = 0x0
2277 12:17:28.667065 DBI_RD = 0x0
2278 12:17:28.669585 OTF = 0x1
2279 12:17:28.672380 ===================================
2280 12:17:28.679301 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2281 12:17:28.680009 ==
2282 12:17:28.682353 Dram Type= 6, Freq= 0, CH_0, rank 0
2283 12:17:28.686089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2284 12:17:28.686777 ==
2285 12:17:28.689384 [Duty_Offset_Calibration]
2286 12:17:28.689953 B0:2 B1:1 CA:1
2287 12:17:28.690459
2288 12:17:28.692539 [DutyScan_Calibration_Flow] k_type=0
2289 12:17:28.702619
2290 12:17:28.703047 ==CLK 0==
2291 12:17:28.706214 Final CLK duty delay cell = 0
2292 12:17:28.709487 [0] MAX Duty = 5187%(X100), DQS PI = 24
2293 12:17:28.712713 [0] MIN Duty = 4875%(X100), DQS PI = 0
2294 12:17:28.713209 [0] AVG Duty = 5031%(X100)
2295 12:17:28.713659
2296 12:17:28.715998 CH0 CLK Duty spec in!! Max-Min= 312%
2297 12:17:28.722500 [DutyScan_Calibration_Flow] ====Done====
2298 12:17:28.722908
2299 12:17:28.726327 [DutyScan_Calibration_Flow] k_type=1
2300 12:17:28.741270
2301 12:17:28.741455 ==DQS 0 ==
2302 12:17:28.744358 Final DQS duty delay cell = -4
2303 12:17:28.747574 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2304 12:17:28.751414 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2305 12:17:28.754589 [-4] AVG Duty = 4953%(X100)
2306 12:17:28.754766
2307 12:17:28.754903 ==DQS 1 ==
2308 12:17:28.757708 Final DQS duty delay cell = 0
2309 12:17:28.761123 [0] MAX Duty = 5187%(X100), DQS PI = 62
2310 12:17:28.764745 [0] MIN Duty = 5000%(X100), DQS PI = 34
2311 12:17:28.767712 [0] AVG Duty = 5093%(X100)
2312 12:17:28.767791
2313 12:17:28.770885 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2314 12:17:28.770964
2315 12:17:28.774138 CH0 DQS 1 Duty spec in!! Max-Min= 187%
2316 12:17:28.777810 [DutyScan_Calibration_Flow] ====Done====
2317 12:17:28.777889
2318 12:17:28.780632 [DutyScan_Calibration_Flow] k_type=3
2319 12:17:28.798152
2320 12:17:28.798238 ==DQM 0 ==
2321 12:17:28.801205 Final DQM duty delay cell = 0
2322 12:17:28.804192 [0] MAX Duty = 5156%(X100), DQS PI = 30
2323 12:17:28.807391 [0] MIN Duty = 4906%(X100), DQS PI = 50
2324 12:17:28.811130 [0] AVG Duty = 5031%(X100)
2325 12:17:28.811229
2326 12:17:28.811306 ==DQM 1 ==
2327 12:17:28.814671 Final DQM duty delay cell = 0
2328 12:17:28.817871 [0] MAX Duty = 5093%(X100), DQS PI = 0
2329 12:17:28.821547 [0] MIN Duty = 5031%(X100), DQS PI = 20
2330 12:17:28.821739 [0] AVG Duty = 5062%(X100)
2331 12:17:28.824586
2332 12:17:28.827979 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2333 12:17:28.828225
2334 12:17:28.831319 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2335 12:17:28.834758 [DutyScan_Calibration_Flow] ====Done====
2336 12:17:28.834837
2337 12:17:28.837908 [DutyScan_Calibration_Flow] k_type=2
2338 12:17:28.853920
2339 12:17:28.854000 ==DQ 0 ==
2340 12:17:28.857723 Final DQ duty delay cell = 0
2341 12:17:28.860782 [0] MAX Duty = 5062%(X100), DQS PI = 32
2342 12:17:28.863792 [0] MIN Duty = 4906%(X100), DQS PI = 0
2343 12:17:28.863872 [0] AVG Duty = 4984%(X100)
2344 12:17:28.863934
2345 12:17:28.867697 ==DQ 1 ==
2346 12:17:28.870925 Final DQ duty delay cell = 0
2347 12:17:28.874416 [0] MAX Duty = 5093%(X100), DQS PI = 24
2348 12:17:28.877482 [0] MIN Duty = 4907%(X100), DQS PI = 36
2349 12:17:28.877562 [0] AVG Duty = 5000%(X100)
2350 12:17:28.877624
2351 12:17:28.880912 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2352 12:17:28.880991
2353 12:17:28.884282 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2354 12:17:28.890784 [DutyScan_Calibration_Flow] ====Done====
2355 12:17:28.890864 ==
2356 12:17:28.894582 Dram Type= 6, Freq= 0, CH_1, rank 0
2357 12:17:28.897698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2358 12:17:28.897788 ==
2359 12:17:28.901132 [Duty_Offset_Calibration]
2360 12:17:28.901212 B0:1 B1:0 CA:0
2361 12:17:28.901273
2362 12:17:28.904140 [DutyScan_Calibration_Flow] k_type=0
2363 12:17:28.913432
2364 12:17:28.913511 ==CLK 0==
2365 12:17:28.916828 Final CLK duty delay cell = -4
2366 12:17:28.919950 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2367 12:17:28.923533 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2368 12:17:28.927124 [-4] AVG Duty = 4953%(X100)
2369 12:17:28.927203
2370 12:17:28.930656 CH1 CLK Duty spec in!! Max-Min= 156%
2371 12:17:28.933623 [DutyScan_Calibration_Flow] ====Done====
2372 12:17:28.933704
2373 12:17:28.936596 [DutyScan_Calibration_Flow] k_type=1
2374 12:17:28.953018
2375 12:17:28.953101 ==DQS 0 ==
2376 12:17:28.956242 Final DQS duty delay cell = 0
2377 12:17:28.959937 [0] MAX Duty = 5062%(X100), DQS PI = 22
2378 12:17:28.963146 [0] MIN Duty = 4844%(X100), DQS PI = 0
2379 12:17:28.963232 [0] AVG Duty = 4953%(X100)
2380 12:17:28.966525
2381 12:17:28.966610 ==DQS 1 ==
2382 12:17:28.969727 Final DQS duty delay cell = 0
2383 12:17:28.972919 [0] MAX Duty = 5187%(X100), DQS PI = 20
2384 12:17:28.976347 [0] MIN Duty = 4969%(X100), DQS PI = 10
2385 12:17:28.976448 [0] AVG Duty = 5078%(X100)
2386 12:17:28.979548
2387 12:17:28.983636 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2388 12:17:28.983756
2389 12:17:28.986676 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2390 12:17:28.989857 [DutyScan_Calibration_Flow] ====Done====
2391 12:17:28.989989
2392 12:17:28.993097 [DutyScan_Calibration_Flow] k_type=3
2393 12:17:29.009822
2394 12:17:29.010056 ==DQM 0 ==
2395 12:17:29.013092 Final DQM duty delay cell = 0
2396 12:17:29.016317 [0] MAX Duty = 5156%(X100), DQS PI = 8
2397 12:17:29.020233 [0] MIN Duty = 5031%(X100), DQS PI = 0
2398 12:17:29.020681 [0] AVG Duty = 5093%(X100)
2399 12:17:29.021006
2400 12:17:29.023392 ==DQM 1 ==
2401 12:17:29.026639 Final DQM duty delay cell = 0
2402 12:17:29.030466 [0] MAX Duty = 5031%(X100), DQS PI = 24
2403 12:17:29.033692 [0] MIN Duty = 4875%(X100), DQS PI = 52
2404 12:17:29.034072 [0] AVG Duty = 4953%(X100)
2405 12:17:29.034372
2406 12:17:29.036980 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2407 12:17:29.040169
2408 12:17:29.043819 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2409 12:17:29.047798 [DutyScan_Calibration_Flow] ====Done====
2410 12:17:29.048271
2411 12:17:29.050016 [DutyScan_Calibration_Flow] k_type=2
2412 12:17:29.066183
2413 12:17:29.066683 ==DQ 0 ==
2414 12:17:29.069004 Final DQ duty delay cell = -4
2415 12:17:29.072733 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2416 12:17:29.075671 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2417 12:17:29.079254 [-4] AVG Duty = 4984%(X100)
2418 12:17:29.079663
2419 12:17:29.079983 ==DQ 1 ==
2420 12:17:29.082763 Final DQ duty delay cell = 0
2421 12:17:29.085946 [0] MAX Duty = 5125%(X100), DQS PI = 20
2422 12:17:29.089287 [0] MIN Duty = 4969%(X100), DQS PI = 12
2423 12:17:29.089793 [0] AVG Duty = 5047%(X100)
2424 12:17:29.090116
2425 12:17:29.095630 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2426 12:17:29.096044
2427 12:17:29.099488 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2428 12:17:29.102304 [DutyScan_Calibration_Flow] ====Done====
2429 12:17:29.106086 nWR fixed to 30
2430 12:17:29.106618 [ModeRegInit_LP4] CH0 RK0
2431 12:17:29.109980 [ModeRegInit_LP4] CH0 RK1
2432 12:17:29.112438 [ModeRegInit_LP4] CH1 RK0
2433 12:17:29.112856 [ModeRegInit_LP4] CH1 RK1
2434 12:17:29.115948 match AC timing 7
2435 12:17:29.119289 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2436 12:17:29.123268 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2437 12:17:29.129420 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2438 12:17:29.133370 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2439 12:17:29.139481 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2440 12:17:29.140019 ==
2441 12:17:29.142801 Dram Type= 6, Freq= 0, CH_0, rank 0
2442 12:17:29.146192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2443 12:17:29.146748 ==
2444 12:17:29.152934 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2445 12:17:29.159330 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2446 12:17:29.166071 [CA 0] Center 39 (8~70) winsize 63
2447 12:17:29.169753 [CA 1] Center 39 (8~70) winsize 63
2448 12:17:29.173031 [CA 2] Center 35 (5~66) winsize 62
2449 12:17:29.176050 [CA 3] Center 34 (4~65) winsize 62
2450 12:17:29.179533 [CA 4] Center 33 (3~64) winsize 62
2451 12:17:29.183097 [CA 5] Center 32 (3~62) winsize 60
2452 12:17:29.183652
2453 12:17:29.186032 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2454 12:17:29.186492
2455 12:17:29.189545 [CATrainingPosCal] consider 1 rank data
2456 12:17:29.192950 u2DelayCellTimex100 = 270/100 ps
2457 12:17:29.196027 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2458 12:17:29.199544 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2459 12:17:29.206538 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2460 12:17:29.209333 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2461 12:17:29.212907 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2462 12:17:29.216433 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2463 12:17:29.217002
2464 12:17:29.219370 CA PerBit enable=1, Macro0, CA PI delay=32
2465 12:17:29.219827
2466 12:17:29.223246 [CBTSetCACLKResult] CA Dly = 32
2467 12:17:29.223793 CS Dly: 6 (0~37)
2468 12:17:29.224152 ==
2469 12:17:29.226402 Dram Type= 6, Freq= 0, CH_0, rank 1
2470 12:17:29.232818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2471 12:17:29.233283 ==
2472 12:17:29.235980 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2473 12:17:29.242945 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2474 12:17:29.252011 [CA 0] Center 38 (8~69) winsize 62
2475 12:17:29.254963 [CA 1] Center 38 (8~69) winsize 62
2476 12:17:29.258806 [CA 2] Center 35 (4~66) winsize 63
2477 12:17:29.262281 [CA 3] Center 34 (4~65) winsize 62
2478 12:17:29.265273 [CA 4] Center 33 (3~64) winsize 62
2479 12:17:29.268715 [CA 5] Center 32 (3~62) winsize 60
2480 12:17:29.269263
2481 12:17:29.271656 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2482 12:17:29.272117
2483 12:17:29.274996 [CATrainingPosCal] consider 2 rank data
2484 12:17:29.278403 u2DelayCellTimex100 = 270/100 ps
2485 12:17:29.281853 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2486 12:17:29.285156 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2487 12:17:29.291896 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2488 12:17:29.295158 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2489 12:17:29.298431 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2490 12:17:29.301667 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2491 12:17:29.302122
2492 12:17:29.304845 CA PerBit enable=1, Macro0, CA PI delay=32
2493 12:17:29.305305
2494 12:17:29.308743 [CBTSetCACLKResult] CA Dly = 32
2495 12:17:29.309248 CS Dly: 6 (0~38)
2496 12:17:29.309596
2497 12:17:29.312237 ----->DramcWriteLeveling(PI) begin...
2498 12:17:29.315792 ==
2499 12:17:29.318280 Dram Type= 6, Freq= 0, CH_0, rank 0
2500 12:17:29.322478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2501 12:17:29.322990 ==
2502 12:17:29.325502 Write leveling (Byte 0): 31 => 31
2503 12:17:29.328851 Write leveling (Byte 1): 29 => 29
2504 12:17:29.331764 DramcWriteLeveling(PI) end<-----
2505 12:17:29.332178
2506 12:17:29.332544 ==
2507 12:17:29.335693 Dram Type= 6, Freq= 0, CH_0, rank 0
2508 12:17:29.338770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 12:17:29.339279 ==
2510 12:17:29.342213 [Gating] SW mode calibration
2511 12:17:29.348848 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2512 12:17:29.352495 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2513 12:17:29.358817 0 15 0 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
2514 12:17:29.362301 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2515 12:17:29.365347 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2516 12:17:29.372161 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2517 12:17:29.375050 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2518 12:17:29.378838 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 12:17:29.385163 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2520 12:17:29.388879 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
2521 12:17:29.391876 1 0 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
2522 12:17:29.398545 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2523 12:17:29.402366 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2524 12:17:29.405875 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2525 12:17:29.408774 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 12:17:29.415277 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 12:17:29.418910 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2528 12:17:29.421909 1 0 28 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2529 12:17:29.428692 1 1 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
2530 12:17:29.431756 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2531 12:17:29.435680 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2532 12:17:29.441982 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2533 12:17:29.445609 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 12:17:29.448933 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 12:17:29.455394 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 12:17:29.459140 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2537 12:17:29.462337 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2538 12:17:29.468978 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2539 12:17:29.472069 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2540 12:17:29.475328 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 12:17:29.482239 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 12:17:29.485487 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 12:17:29.488651 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 12:17:29.492015 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 12:17:29.498448 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 12:17:29.502007 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 12:17:29.505331 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 12:17:29.512025 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 12:17:29.515430 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 12:17:29.518709 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 12:17:29.525667 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 12:17:29.528880 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2553 12:17:29.532022 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2554 12:17:29.535868 Total UI for P1: 0, mck2ui 16
2555 12:17:29.539097 best dqsien dly found for B0: ( 1, 3, 28)
2556 12:17:29.545630 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 12:17:29.545931 Total UI for P1: 0, mck2ui 16
2558 12:17:29.552059 best dqsien dly found for B1: ( 1, 4, 0)
2559 12:17:29.555782 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2560 12:17:29.559097 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2561 12:17:29.559394
2562 12:17:29.561725 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2563 12:17:29.565343 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2564 12:17:29.569205 [Gating] SW calibration Done
2565 12:17:29.569286 ==
2566 12:17:29.572457 Dram Type= 6, Freq= 0, CH_0, rank 0
2567 12:17:29.575553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2568 12:17:29.575634 ==
2569 12:17:29.578620 RX Vref Scan: 0
2570 12:17:29.578700
2571 12:17:29.578763 RX Vref 0 -> 0, step: 1
2572 12:17:29.578823
2573 12:17:29.581886 RX Delay -40 -> 252, step: 8
2574 12:17:29.585280 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2575 12:17:29.588533 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2576 12:17:29.595428 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2577 12:17:29.598908 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2578 12:17:29.602109 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2579 12:17:29.605666 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2580 12:17:29.609035 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2581 12:17:29.616031 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2582 12:17:29.618999 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2583 12:17:29.622418 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2584 12:17:29.625526 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2585 12:17:29.628668 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2586 12:17:29.635434 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2587 12:17:29.638952 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2588 12:17:29.641960 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2589 12:17:29.645877 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2590 12:17:29.645963 ==
2591 12:17:29.648615 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 12:17:29.655506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 12:17:29.655587 ==
2594 12:17:29.655649 DQS Delay:
2595 12:17:29.655708 DQS0 = 0, DQS1 = 0
2596 12:17:29.659100 DQM Delay:
2597 12:17:29.659181 DQM0 = 121, DQM1 = 113
2598 12:17:29.661921 DQ Delay:
2599 12:17:29.665910 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2600 12:17:29.668835 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2601 12:17:29.672478 DQ8 =99, DQ9 =107, DQ10 =115, DQ11 =107
2602 12:17:29.675405 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2603 12:17:29.675510
2604 12:17:29.675600
2605 12:17:29.675686 ==
2606 12:17:29.678568 Dram Type= 6, Freq= 0, CH_0, rank 0
2607 12:17:29.681993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2608 12:17:29.682074 ==
2609 12:17:29.682136
2610 12:17:29.685830
2611 12:17:29.685910 TX Vref Scan disable
2612 12:17:29.689009 == TX Byte 0 ==
2613 12:17:29.692460 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2614 12:17:29.695597 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2615 12:17:29.698832 == TX Byte 1 ==
2616 12:17:29.702330 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2617 12:17:29.705519 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2618 12:17:29.705599 ==
2619 12:17:29.708603 Dram Type= 6, Freq= 0, CH_0, rank 0
2620 12:17:29.715595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2621 12:17:29.715676 ==
2622 12:17:29.726320 TX Vref=22, minBit 0, minWin=24, winSum=408
2623 12:17:29.729425 TX Vref=24, minBit 0, minWin=25, winSum=417
2624 12:17:29.732816 TX Vref=26, minBit 0, minWin=26, winSum=421
2625 12:17:29.735843 TX Vref=28, minBit 8, minWin=26, winSum=428
2626 12:17:29.739672 TX Vref=30, minBit 0, minWin=26, winSum=429
2627 12:17:29.742890 TX Vref=32, minBit 3, minWin=26, winSum=427
2628 12:17:29.749759 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 30
2629 12:17:29.749973
2630 12:17:29.753135 Final TX Range 1 Vref 30
2631 12:17:29.753372
2632 12:17:29.753531 ==
2633 12:17:29.756420 Dram Type= 6, Freq= 0, CH_0, rank 0
2634 12:17:29.760000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2635 12:17:29.760171 ==
2636 12:17:29.760325
2637 12:17:29.762556
2638 12:17:29.762758 TX Vref Scan disable
2639 12:17:29.765889 == TX Byte 0 ==
2640 12:17:29.769711 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2641 12:17:29.772554 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2642 12:17:29.776131 == TX Byte 1 ==
2643 12:17:29.779342 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2644 12:17:29.782687 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2645 12:17:29.783132
2646 12:17:29.786209 [DATLAT]
2647 12:17:29.786658 Freq=1200, CH0 RK0
2648 12:17:29.786988
2649 12:17:29.789722 DATLAT Default: 0xd
2650 12:17:29.790135 0, 0xFFFF, sum = 0
2651 12:17:29.793024 1, 0xFFFF, sum = 0
2652 12:17:29.793446 2, 0xFFFF, sum = 0
2653 12:17:29.796761 3, 0xFFFF, sum = 0
2654 12:17:29.797194 4, 0xFFFF, sum = 0
2655 12:17:29.799767 5, 0xFFFF, sum = 0
2656 12:17:29.800185 6, 0xFFFF, sum = 0
2657 12:17:29.803361 7, 0xFFFF, sum = 0
2658 12:17:29.803779 8, 0xFFFF, sum = 0
2659 12:17:29.806496 9, 0xFFFF, sum = 0
2660 12:17:29.806914 10, 0xFFFF, sum = 0
2661 12:17:29.809641 11, 0xFFFF, sum = 0
2662 12:17:29.810061 12, 0x0, sum = 1
2663 12:17:29.813643 13, 0x0, sum = 2
2664 12:17:29.814139 14, 0x0, sum = 3
2665 12:17:29.816442 15, 0x0, sum = 4
2666 12:17:29.816875 best_step = 13
2667 12:17:29.817264
2668 12:17:29.817630 ==
2669 12:17:29.820007 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 12:17:29.827001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 12:17:29.827417 ==
2672 12:17:29.827747 RX Vref Scan: 1
2673 12:17:29.828054
2674 12:17:29.830142 Set Vref Range= 32 -> 127
2675 12:17:29.830556
2676 12:17:29.833293 RX Vref 32 -> 127, step: 1
2677 12:17:29.833704
2678 12:17:29.834032 RX Delay -13 -> 252, step: 4
2679 12:17:29.836556
2680 12:17:29.836965 Set Vref, RX VrefLevel [Byte0]: 32
2681 12:17:29.839684 [Byte1]: 32
2682 12:17:29.844066
2683 12:17:29.844644 Set Vref, RX VrefLevel [Byte0]: 33
2684 12:17:29.847839 [Byte1]: 33
2685 12:17:29.852178
2686 12:17:29.852644 Set Vref, RX VrefLevel [Byte0]: 34
2687 12:17:29.855757 [Byte1]: 34
2688 12:17:29.860183
2689 12:17:29.860673 Set Vref, RX VrefLevel [Byte0]: 35
2690 12:17:29.864156 [Byte1]: 35
2691 12:17:29.867893
2692 12:17:29.871627 Set Vref, RX VrefLevel [Byte0]: 36
2693 12:17:29.874930 [Byte1]: 36
2694 12:17:29.875343
2695 12:17:29.877898 Set Vref, RX VrefLevel [Byte0]: 37
2696 12:17:29.881301 [Byte1]: 37
2697 12:17:29.881715
2698 12:17:29.884406 Set Vref, RX VrefLevel [Byte0]: 38
2699 12:17:29.888023 [Byte1]: 38
2700 12:17:29.891542
2701 12:17:29.892089 Set Vref, RX VrefLevel [Byte0]: 39
2702 12:17:29.895080 [Byte1]: 39
2703 12:17:29.899433
2704 12:17:29.899842 Set Vref, RX VrefLevel [Byte0]: 40
2705 12:17:29.902861 [Byte1]: 40
2706 12:17:29.907757
2707 12:17:29.908181 Set Vref, RX VrefLevel [Byte0]: 41
2708 12:17:29.910790 [Byte1]: 41
2709 12:17:29.915293
2710 12:17:29.915785 Set Vref, RX VrefLevel [Byte0]: 42
2711 12:17:29.918792 [Byte1]: 42
2712 12:17:29.923219
2713 12:17:29.923643 Set Vref, RX VrefLevel [Byte0]: 43
2714 12:17:29.926736 [Byte1]: 43
2715 12:17:29.931222
2716 12:17:29.931651 Set Vref, RX VrefLevel [Byte0]: 44
2717 12:17:29.934619 [Byte1]: 44
2718 12:17:29.939064
2719 12:17:29.939489 Set Vref, RX VrefLevel [Byte0]: 45
2720 12:17:29.942369 [Byte1]: 45
2721 12:17:29.947475
2722 12:17:29.947999 Set Vref, RX VrefLevel [Byte0]: 46
2723 12:17:29.950359 [Byte1]: 46
2724 12:17:29.955066
2725 12:17:29.955600 Set Vref, RX VrefLevel [Byte0]: 47
2726 12:17:29.958787 [Byte1]: 47
2727 12:17:29.963273
2728 12:17:29.963801 Set Vref, RX VrefLevel [Byte0]: 48
2729 12:17:29.966442 [Byte1]: 48
2730 12:17:29.970795
2731 12:17:29.971224 Set Vref, RX VrefLevel [Byte0]: 49
2732 12:17:29.974218 [Byte1]: 49
2733 12:17:29.979045
2734 12:17:29.979465 Set Vref, RX VrefLevel [Byte0]: 50
2735 12:17:29.982028 [Byte1]: 50
2736 12:17:29.986354
2737 12:17:29.986780 Set Vref, RX VrefLevel [Byte0]: 51
2738 12:17:29.990029 [Byte1]: 51
2739 12:17:29.994769
2740 12:17:29.995299 Set Vref, RX VrefLevel [Byte0]: 52
2741 12:17:29.997536 [Byte1]: 52
2742 12:17:30.002140
2743 12:17:30.002601 Set Vref, RX VrefLevel [Byte0]: 53
2744 12:17:30.005434 [Byte1]: 53
2745 12:17:30.010349
2746 12:17:30.010759 Set Vref, RX VrefLevel [Byte0]: 54
2747 12:17:30.013751 [Byte1]: 54
2748 12:17:30.017863
2749 12:17:30.018288 Set Vref, RX VrefLevel [Byte0]: 55
2750 12:17:30.021084 [Byte1]: 55
2751 12:17:30.025836
2752 12:17:30.026259 Set Vref, RX VrefLevel [Byte0]: 56
2753 12:17:30.029242 [Byte1]: 56
2754 12:17:30.033979
2755 12:17:30.034509 Set Vref, RX VrefLevel [Byte0]: 57
2756 12:17:30.037157 [Byte1]: 57
2757 12:17:30.041540
2758 12:17:30.041952 Set Vref, RX VrefLevel [Byte0]: 58
2759 12:17:30.045272 [Byte1]: 58
2760 12:17:30.049560
2761 12:17:30.049979 Set Vref, RX VrefLevel [Byte0]: 59
2762 12:17:30.052715 [Byte1]: 59
2763 12:17:30.057161
2764 12:17:30.057574 Set Vref, RX VrefLevel [Byte0]: 60
2765 12:17:30.060745 [Byte1]: 60
2766 12:17:30.065295
2767 12:17:30.065713 Set Vref, RX VrefLevel [Byte0]: 61
2768 12:17:30.068640 [Byte1]: 61
2769 12:17:30.073492
2770 12:17:30.073908 Set Vref, RX VrefLevel [Byte0]: 62
2771 12:17:30.076420 [Byte1]: 62
2772 12:17:30.080974
2773 12:17:30.081403 Set Vref, RX VrefLevel [Byte0]: 63
2774 12:17:30.084357 [Byte1]: 63
2775 12:17:30.089566
2776 12:17:30.090071 Set Vref, RX VrefLevel [Byte0]: 64
2777 12:17:30.092752 [Byte1]: 64
2778 12:17:30.096996
2779 12:17:30.097405 Set Vref, RX VrefLevel [Byte0]: 65
2780 12:17:30.100132 [Byte1]: 65
2781 12:17:30.104953
2782 12:17:30.105382 Set Vref, RX VrefLevel [Byte0]: 66
2783 12:17:30.107975 [Byte1]: 66
2784 12:17:30.112579
2785 12:17:30.113027 Set Vref, RX VrefLevel [Byte0]: 67
2786 12:17:30.115753 [Byte1]: 67
2787 12:17:30.120626
2788 12:17:30.121157 Set Vref, RX VrefLevel [Byte0]: 68
2789 12:17:30.124365 [Byte1]: 68
2790 12:17:30.128704
2791 12:17:30.129279 Set Vref, RX VrefLevel [Byte0]: 69
2792 12:17:30.131735 [Byte1]: 69
2793 12:17:30.136559
2794 12:17:30.137129 Final RX Vref Byte 0 = 56 to rank0
2795 12:17:30.140646 Final RX Vref Byte 1 = 47 to rank0
2796 12:17:30.143193 Final RX Vref Byte 0 = 56 to rank1
2797 12:17:30.146441 Final RX Vref Byte 1 = 47 to rank1==
2798 12:17:30.150016 Dram Type= 6, Freq= 0, CH_0, rank 0
2799 12:17:30.156547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2800 12:17:30.157119 ==
2801 12:17:30.157618 DQS Delay:
2802 12:17:30.158080 DQS0 = 0, DQS1 = 0
2803 12:17:30.159568 DQM Delay:
2804 12:17:30.160042 DQM0 = 120, DQM1 = 110
2805 12:17:30.163718 DQ Delay:
2806 12:17:30.166639 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2807 12:17:30.170278 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2808 12:17:30.173474 DQ8 =96, DQ9 =100, DQ10 =112, DQ11 =104
2809 12:17:30.176402 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2810 12:17:30.176847
2811 12:17:30.177283
2812 12:17:30.183682 [DQSOSCAuto] RK0, (LSB)MR18= 0x1009, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 403 ps
2813 12:17:30.186827 CH0 RK0: MR19=404, MR18=1009
2814 12:17:30.193203 CH0_RK0: MR19=0x404, MR18=0x1009, DQSOSC=403, MR23=63, INC=40, DEC=26
2815 12:17:30.193754
2816 12:17:30.196642 ----->DramcWriteLeveling(PI) begin...
2817 12:17:30.197136 ==
2818 12:17:30.200159 Dram Type= 6, Freq= 0, CH_0, rank 1
2819 12:17:30.203319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2820 12:17:30.203911 ==
2821 12:17:30.206250 Write leveling (Byte 0): 33 => 33
2822 12:17:30.210164 Write leveling (Byte 1): 27 => 27
2823 12:17:30.213314 DramcWriteLeveling(PI) end<-----
2824 12:17:30.213771
2825 12:17:30.214134 ==
2826 12:17:30.216465 Dram Type= 6, Freq= 0, CH_0, rank 1
2827 12:17:30.223501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2828 12:17:30.224196 ==
2829 12:17:30.224708 [Gating] SW mode calibration
2830 12:17:30.233731 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2831 12:17:30.237202 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2832 12:17:30.240104 0 15 0 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
2833 12:17:30.246549 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 12:17:30.250138 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 12:17:30.253378 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 12:17:30.259985 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 12:17:30.263210 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 12:17:30.266452 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 12:17:30.273191 0 15 28 | B1->B0 | 3131 2f2f | 0 0 | (1 0) (0 1)
2840 12:17:30.277432 1 0 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2841 12:17:30.280326 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 12:17:30.286997 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 12:17:30.290452 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 12:17:30.293379 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 12:17:30.299971 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 12:17:30.303667 1 0 24 | B1->B0 | 2525 2323 | 1 0 | (0 0) (0 0)
2847 12:17:30.306873 1 0 28 | B1->B0 | 3a3a 3c3c | 0 1 | (0 0) (0 0)
2848 12:17:30.309715 1 1 0 | B1->B0 | 4646 4545 | 0 1 | (0 0) (1 1)
2849 12:17:30.316719 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 12:17:30.320097 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 12:17:30.323832 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 12:17:30.329985 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 12:17:30.333754 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 12:17:30.336749 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 12:17:30.343570 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2856 12:17:30.347217 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2857 12:17:30.350628 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 12:17:30.357272 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 12:17:30.360402 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 12:17:30.363972 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 12:17:30.370596 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 12:17:30.373976 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 12:17:30.376899 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 12:17:30.383849 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 12:17:30.387440 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 12:17:30.390540 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 12:17:30.393357 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 12:17:30.400547 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 12:17:30.403675 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 12:17:30.406973 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2871 12:17:30.413968 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2872 12:17:30.417134 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2873 12:17:30.420466 Total UI for P1: 0, mck2ui 16
2874 12:17:30.423627 best dqsien dly found for B1: ( 1, 3, 26)
2875 12:17:30.427537 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 12:17:30.430671 Total UI for P1: 0, mck2ui 16
2877 12:17:30.433872 best dqsien dly found for B0: ( 1, 3, 28)
2878 12:17:30.437197 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2879 12:17:30.440797 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
2880 12:17:30.441348
2881 12:17:30.447482 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2882 12:17:30.450642 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
2883 12:17:30.451188 [Gating] SW calibration Done
2884 12:17:30.453732 ==
2885 12:17:30.454190 Dram Type= 6, Freq= 0, CH_0, rank 1
2886 12:17:30.460501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 12:17:30.461056 ==
2888 12:17:30.461421 RX Vref Scan: 0
2889 12:17:30.461754
2890 12:17:30.464102 RX Vref 0 -> 0, step: 1
2891 12:17:30.464587
2892 12:17:30.467292 RX Delay -40 -> 252, step: 8
2893 12:17:30.471390 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2894 12:17:30.474295 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2895 12:17:30.477579 iDelay=200, Bit 2, Center 123 (56 ~ 191) 136
2896 12:17:30.484263 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2897 12:17:30.487966 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2898 12:17:30.490743 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2899 12:17:30.494164 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2900 12:17:30.497407 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2901 12:17:30.501101 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2902 12:17:30.507504 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2903 12:17:30.510704 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2904 12:17:30.514292 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2905 12:17:30.517479 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2906 12:17:30.520922 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2907 12:17:30.528167 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2908 12:17:30.531422 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2909 12:17:30.531968 ==
2910 12:17:30.534354 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 12:17:30.537942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 12:17:30.538491 ==
2913 12:17:30.540934 DQS Delay:
2914 12:17:30.541389 DQS0 = 0, DQS1 = 0
2915 12:17:30.541749 DQM Delay:
2916 12:17:30.544474 DQM0 = 123, DQM1 = 112
2917 12:17:30.545019 DQ Delay:
2918 12:17:30.547692 DQ0 =119, DQ1 =123, DQ2 =123, DQ3 =119
2919 12:17:30.550949 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2920 12:17:30.554289 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2921 12:17:30.561196 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2922 12:17:30.561754
2923 12:17:30.562118
2924 12:17:30.562450 ==
2925 12:17:30.564604 Dram Type= 6, Freq= 0, CH_0, rank 1
2926 12:17:30.567453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2927 12:17:30.567913 ==
2928 12:17:30.568272
2929 12:17:30.568630
2930 12:17:30.570983 TX Vref Scan disable
2931 12:17:30.571539 == TX Byte 0 ==
2932 12:17:30.577595 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2933 12:17:30.581144 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2934 12:17:30.581620 == TX Byte 1 ==
2935 12:17:30.587591 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2936 12:17:30.591125 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2937 12:17:30.591586 ==
2938 12:17:30.594104 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 12:17:30.597377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 12:17:30.597985 ==
2941 12:17:30.610509 TX Vref=22, minBit 1, minWin=25, winSum=413
2942 12:17:30.614421 TX Vref=24, minBit 1, minWin=25, winSum=415
2943 12:17:30.617712 TX Vref=26, minBit 3, minWin=25, winSum=418
2944 12:17:30.620977 TX Vref=28, minBit 13, minWin=25, winSum=424
2945 12:17:30.623838 TX Vref=30, minBit 1, minWin=26, winSum=427
2946 12:17:30.630466 TX Vref=32, minBit 12, minWin=25, winSum=424
2947 12:17:30.634243 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 30
2948 12:17:30.634662
2949 12:17:30.637847 Final TX Range 1 Vref 30
2950 12:17:30.638266
2951 12:17:30.638597 ==
2952 12:17:30.640553 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 12:17:30.644205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 12:17:30.644685 ==
2955 12:17:30.645022
2956 12:17:30.647492
2957 12:17:30.647835 TX Vref Scan disable
2958 12:17:30.650628 == TX Byte 0 ==
2959 12:17:30.653758 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2960 12:17:30.657213 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2961 12:17:30.660327 == TX Byte 1 ==
2962 12:17:30.663603 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2963 12:17:30.667423 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2964 12:17:30.667574
2965 12:17:30.670427 [DATLAT]
2966 12:17:30.670556 Freq=1200, CH0 RK1
2967 12:17:30.670657
2968 12:17:30.673441 DATLAT Default: 0xd
2969 12:17:30.673555 0, 0xFFFF, sum = 0
2970 12:17:30.677506 1, 0xFFFF, sum = 0
2971 12:17:30.677621 2, 0xFFFF, sum = 0
2972 12:17:30.680374 3, 0xFFFF, sum = 0
2973 12:17:30.680508 4, 0xFFFF, sum = 0
2974 12:17:30.683677 5, 0xFFFF, sum = 0
2975 12:17:30.683780 6, 0xFFFF, sum = 0
2976 12:17:30.686913 7, 0xFFFF, sum = 0
2977 12:17:30.691100 8, 0xFFFF, sum = 0
2978 12:17:30.691523 9, 0xFFFF, sum = 0
2979 12:17:30.693773 10, 0xFFFF, sum = 0
2980 12:17:30.694196 11, 0xFFFF, sum = 0
2981 12:17:30.697212 12, 0x0, sum = 1
2982 12:17:30.697635 13, 0x0, sum = 2
2983 12:17:30.700694 14, 0x0, sum = 3
2984 12:17:30.701116 15, 0x0, sum = 4
2985 12:17:30.701454 best_step = 13
2986 12:17:30.701763
2987 12:17:30.703872 ==
2988 12:17:30.707465 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 12:17:30.710457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 12:17:30.710879 ==
2991 12:17:30.711213 RX Vref Scan: 0
2992 12:17:30.711517
2993 12:17:30.714095 RX Vref 0 -> 0, step: 1
2994 12:17:30.714511
2995 12:17:30.717302 RX Delay -13 -> 252, step: 4
2996 12:17:30.721048 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
2997 12:17:30.724447 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
2998 12:17:30.730585 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
2999 12:17:30.734245 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3000 12:17:30.737051 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3001 12:17:30.740385 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3002 12:17:30.743509 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3003 12:17:30.750369 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3004 12:17:30.753431 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3005 12:17:30.756986 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3006 12:17:30.760998 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3007 12:17:30.763849 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3008 12:17:30.770887 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3009 12:17:30.774025 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3010 12:17:30.777058 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3011 12:17:30.780232 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3012 12:17:30.780371 ==
3013 12:17:30.784097 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 12:17:30.787419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 12:17:30.790697 ==
3016 12:17:30.790794 DQS Delay:
3017 12:17:30.790881 DQS0 = 0, DQS1 = 0
3018 12:17:30.793691 DQM Delay:
3019 12:17:30.793787 DQM0 = 121, DQM1 = 109
3020 12:17:30.797024 DQ Delay:
3021 12:17:30.800735 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3022 12:17:30.803935 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3023 12:17:30.807192 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3024 12:17:30.810500 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =118
3025 12:17:30.810606
3026 12:17:30.810701
3027 12:17:30.817177 [DQSOSCAuto] RK1, (LSB)MR18= 0xfef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 404 ps
3028 12:17:30.820727 CH0 RK1: MR19=403, MR18=FEF
3029 12:17:30.827229 CH0_RK1: MR19=0x403, MR18=0xFEF, DQSOSC=404, MR23=63, INC=40, DEC=26
3030 12:17:30.830669 [RxdqsGatingPostProcess] freq 1200
3031 12:17:30.837591 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3032 12:17:30.837743 best DQS0 dly(2T, 0.5T) = (0, 11)
3033 12:17:30.840717 best DQS1 dly(2T, 0.5T) = (0, 12)
3034 12:17:30.843797 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3035 12:17:30.847561 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3036 12:17:30.850655 best DQS0 dly(2T, 0.5T) = (0, 11)
3037 12:17:30.854290 best DQS1 dly(2T, 0.5T) = (0, 11)
3038 12:17:30.857693 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3039 12:17:30.860652 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3040 12:17:30.864498 Pre-setting of DQS Precalculation
3041 12:17:30.867557 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3042 12:17:30.871147 ==
3043 12:17:30.871228 Dram Type= 6, Freq= 0, CH_1, rank 0
3044 12:17:30.877458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 12:17:30.877540 ==
3046 12:17:30.880827 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3047 12:17:30.887335 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3048 12:17:30.896729 [CA 0] Center 37 (7~68) winsize 62
3049 12:17:30.899833 [CA 1] Center 37 (7~68) winsize 62
3050 12:17:30.903108 [CA 2] Center 35 (5~65) winsize 61
3051 12:17:30.906795 [CA 3] Center 34 (4~64) winsize 61
3052 12:17:30.910105 [CA 4] Center 34 (4~64) winsize 61
3053 12:17:30.913312 [CA 5] Center 33 (3~63) winsize 61
3054 12:17:30.913463
3055 12:17:30.916488 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3056 12:17:30.916640
3057 12:17:30.919697 [CATrainingPosCal] consider 1 rank data
3058 12:17:30.923474 u2DelayCellTimex100 = 270/100 ps
3059 12:17:30.927009 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3060 12:17:30.930379 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3061 12:17:30.936441 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3062 12:17:30.940040 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3063 12:17:30.943460 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3064 12:17:30.946983 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3065 12:17:30.947370
3066 12:17:30.950178 CA PerBit enable=1, Macro0, CA PI delay=33
3067 12:17:30.950577
3068 12:17:30.953388 [CBTSetCACLKResult] CA Dly = 33
3069 12:17:30.953804 CS Dly: 7 (0~38)
3070 12:17:30.954131 ==
3071 12:17:30.957271 Dram Type= 6, Freq= 0, CH_1, rank 1
3072 12:17:30.963621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 12:17:30.964132 ==
3074 12:17:30.967020 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3075 12:17:30.973781 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3076 12:17:30.982591 [CA 0] Center 37 (7~68) winsize 62
3077 12:17:30.985679 [CA 1] Center 37 (7~68) winsize 62
3078 12:17:30.989103 [CA 2] Center 35 (5~65) winsize 61
3079 12:17:30.992800 [CA 3] Center 34 (4~65) winsize 62
3080 12:17:30.996255 [CA 4] Center 34 (4~65) winsize 62
3081 12:17:30.999062 [CA 5] Center 34 (4~64) winsize 61
3082 12:17:30.999533
3083 12:17:31.002591 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3084 12:17:31.003047
3085 12:17:31.005705 [CATrainingPosCal] consider 2 rank data
3086 12:17:31.009332 u2DelayCellTimex100 = 270/100 ps
3087 12:17:31.012346 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3088 12:17:31.015867 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3089 12:17:31.023179 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3090 12:17:31.026428 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3091 12:17:31.029342 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3092 12:17:31.033230 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3093 12:17:31.033643
3094 12:17:31.035881 CA PerBit enable=1, Macro0, CA PI delay=33
3095 12:17:31.036326
3096 12:17:31.039626 [CBTSetCACLKResult] CA Dly = 33
3097 12:17:31.040037 CS Dly: 8 (0~40)
3098 12:17:31.040405
3099 12:17:31.042913 ----->DramcWriteLeveling(PI) begin...
3100 12:17:31.043329 ==
3101 12:17:31.046050 Dram Type= 6, Freq= 0, CH_1, rank 0
3102 12:17:31.052670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3103 12:17:31.053167 ==
3104 12:17:31.056501 Write leveling (Byte 0): 24 => 24
3105 12:17:31.059482 Write leveling (Byte 1): 28 => 28
3106 12:17:31.060028 DramcWriteLeveling(PI) end<-----
3107 12:17:31.062754
3108 12:17:31.063467 ==
3109 12:17:31.066296 Dram Type= 6, Freq= 0, CH_1, rank 0
3110 12:17:31.069871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 12:17:31.070404 ==
3112 12:17:31.072714 [Gating] SW mode calibration
3113 12:17:31.079687 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3114 12:17:31.082739 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3115 12:17:31.089078 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 12:17:31.092361 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 12:17:31.096215 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 12:17:31.102651 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 12:17:31.106223 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 12:17:31.109615 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 12:17:31.116517 0 15 24 | B1->B0 | 3434 2d2d | 0 0 | (0 1) (0 1)
3122 12:17:31.119625 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3123 12:17:31.122751 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 12:17:31.126482 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 12:17:31.133183 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 12:17:31.136774 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 12:17:31.139729 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 12:17:31.147118 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 12:17:31.150189 1 0 24 | B1->B0 | 2e2e 3e3e | 0 1 | (0 0) (0 0)
3130 12:17:31.153338 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 12:17:31.160061 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 12:17:31.163210 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 12:17:31.166548 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 12:17:31.173197 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 12:17:31.176594 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 12:17:31.179916 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 12:17:31.186442 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3138 12:17:31.189761 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3139 12:17:31.193700 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 12:17:31.199858 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 12:17:31.203134 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 12:17:31.206437 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 12:17:31.209901 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 12:17:31.216631 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 12:17:31.220105 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 12:17:31.223534 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 12:17:31.230157 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 12:17:31.233186 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 12:17:31.236813 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 12:17:31.243571 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 12:17:31.246952 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 12:17:31.250089 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 12:17:31.257012 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3154 12:17:31.260418 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3155 12:17:31.263765 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 12:17:31.266935 Total UI for P1: 0, mck2ui 16
3157 12:17:31.270043 best dqsien dly found for B0: ( 1, 3, 26)
3158 12:17:31.273339 Total UI for P1: 0, mck2ui 16
3159 12:17:31.277255 best dqsien dly found for B1: ( 1, 3, 26)
3160 12:17:31.280628 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3161 12:17:31.283721 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3162 12:17:31.284271
3163 12:17:31.286865 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3164 12:17:31.293871 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3165 12:17:31.294425 [Gating] SW calibration Done
3166 12:17:31.294782 ==
3167 12:17:31.296935 Dram Type= 6, Freq= 0, CH_1, rank 0
3168 12:17:31.303836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3169 12:17:31.304421 ==
3170 12:17:31.304795 RX Vref Scan: 0
3171 12:17:31.305132
3172 12:17:31.306725 RX Vref 0 -> 0, step: 1
3173 12:17:31.307177
3174 12:17:31.310124 RX Delay -40 -> 252, step: 8
3175 12:17:31.313502 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3176 12:17:31.316957 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3177 12:17:31.320220 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3178 12:17:31.323552 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3179 12:17:31.330125 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3180 12:17:31.333318 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3181 12:17:31.336950 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3182 12:17:31.339945 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3183 12:17:31.343459 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3184 12:17:31.350377 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3185 12:17:31.353512 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3186 12:17:31.356829 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3187 12:17:31.360208 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3188 12:17:31.364130 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3189 12:17:31.370362 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3190 12:17:31.374198 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3191 12:17:31.374708 ==
3192 12:17:31.377264 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 12:17:31.380373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 12:17:31.380888 ==
3195 12:17:31.383693 DQS Delay:
3196 12:17:31.384200 DQS0 = 0, DQS1 = 0
3197 12:17:31.384576 DQM Delay:
3198 12:17:31.387003 DQM0 = 119, DQM1 = 116
3199 12:17:31.387507 DQ Delay:
3200 12:17:31.389930 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3201 12:17:31.393265 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3202 12:17:31.400248 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3203 12:17:31.403240 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3204 12:17:31.403653
3205 12:17:31.403981
3206 12:17:31.404282 ==
3207 12:17:31.406534 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 12:17:31.410102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 12:17:31.410519 ==
3210 12:17:31.410846
3211 12:17:31.411151
3212 12:17:31.413432 TX Vref Scan disable
3213 12:17:31.413842 == TX Byte 0 ==
3214 12:17:31.420212 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3215 12:17:31.423412 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3216 12:17:31.423829 == TX Byte 1 ==
3217 12:17:31.430376 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3218 12:17:31.433170 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3219 12:17:31.433587 ==
3220 12:17:31.437053 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 12:17:31.440185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 12:17:31.440749 ==
3223 12:17:31.452989 TX Vref=22, minBit 9, minWin=24, winSum=409
3224 12:17:31.456308 TX Vref=24, minBit 9, minWin=25, winSum=418
3225 12:17:31.459872 TX Vref=26, minBit 9, minWin=25, winSum=424
3226 12:17:31.463258 TX Vref=28, minBit 11, minWin=25, winSum=426
3227 12:17:31.466314 TX Vref=30, minBit 9, minWin=25, winSum=432
3228 12:17:31.473184 TX Vref=32, minBit 9, minWin=26, winSum=432
3229 12:17:31.476696 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 32
3230 12:17:31.477159
3231 12:17:31.479626 Final TX Range 1 Vref 32
3232 12:17:31.480169
3233 12:17:31.480578 ==
3234 12:17:31.482958 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 12:17:31.486308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 12:17:31.486859 ==
3237 12:17:31.489903
3238 12:17:31.490355
3239 12:17:31.490713 TX Vref Scan disable
3240 12:17:31.493141 == TX Byte 0 ==
3241 12:17:31.496474 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3242 12:17:31.499751 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3243 12:17:31.503291 == TX Byte 1 ==
3244 12:17:31.506336 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3245 12:17:31.509890 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3246 12:17:31.510472
3247 12:17:31.512796 [DATLAT]
3248 12:17:31.513264 Freq=1200, CH1 RK0
3249 12:17:31.513739
3250 12:17:31.515995 DATLAT Default: 0xd
3251 12:17:31.516500 0, 0xFFFF, sum = 0
3252 12:17:31.519708 1, 0xFFFF, sum = 0
3253 12:17:31.520342 2, 0xFFFF, sum = 0
3254 12:17:31.523124 3, 0xFFFF, sum = 0
3255 12:17:31.523603 4, 0xFFFF, sum = 0
3256 12:17:31.526595 5, 0xFFFF, sum = 0
3257 12:17:31.527175 6, 0xFFFF, sum = 0
3258 12:17:31.529801 7, 0xFFFF, sum = 0
3259 12:17:31.533799 8, 0xFFFF, sum = 0
3260 12:17:31.534281 9, 0xFFFF, sum = 0
3261 12:17:31.536179 10, 0xFFFF, sum = 0
3262 12:17:31.536709 11, 0xFFFF, sum = 0
3263 12:17:31.539598 12, 0x0, sum = 1
3264 12:17:31.540107 13, 0x0, sum = 2
3265 12:17:31.540641 14, 0x0, sum = 3
3266 12:17:31.543280 15, 0x0, sum = 4
3267 12:17:31.543755 best_step = 13
3268 12:17:31.544226
3269 12:17:31.546480 ==
3270 12:17:31.546950 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 12:17:31.553277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 12:17:31.553749 ==
3273 12:17:31.554184 RX Vref Scan: 1
3274 12:17:31.554597
3275 12:17:31.556575 Set Vref Range= 32 -> 127
3276 12:17:31.557001
3277 12:17:31.559683 RX Vref 32 -> 127, step: 1
3278 12:17:31.560107
3279 12:17:31.563183 RX Delay -5 -> 252, step: 4
3280 12:17:31.563708
3281 12:17:31.566706 Set Vref, RX VrefLevel [Byte0]: 32
3282 12:17:31.569895 [Byte1]: 32
3283 12:17:31.570321
3284 12:17:31.572848 Set Vref, RX VrefLevel [Byte0]: 33
3285 12:17:31.576552 [Byte1]: 33
3286 12:17:31.577084
3287 12:17:31.579652 Set Vref, RX VrefLevel [Byte0]: 34
3288 12:17:31.583102 [Byte1]: 34
3289 12:17:31.587155
3290 12:17:31.587765 Set Vref, RX VrefLevel [Byte0]: 35
3291 12:17:31.590054 [Byte1]: 35
3292 12:17:31.594935
3293 12:17:31.595341 Set Vref, RX VrefLevel [Byte0]: 36
3294 12:17:31.597773 [Byte1]: 36
3295 12:17:31.602416
3296 12:17:31.602938 Set Vref, RX VrefLevel [Byte0]: 37
3297 12:17:31.606139 [Byte1]: 37
3298 12:17:31.610400
3299 12:17:31.610761 Set Vref, RX VrefLevel [Byte0]: 38
3300 12:17:31.614047 [Byte1]: 38
3301 12:17:31.618341
3302 12:17:31.618602 Set Vref, RX VrefLevel [Byte0]: 39
3303 12:17:31.621568 [Byte1]: 39
3304 12:17:31.625917
3305 12:17:31.626177 Set Vref, RX VrefLevel [Byte0]: 40
3306 12:17:31.629204 [Byte1]: 40
3307 12:17:31.633820
3308 12:17:31.634084 Set Vref, RX VrefLevel [Byte0]: 41
3309 12:17:31.636929 [Byte1]: 41
3310 12:17:31.641914
3311 12:17:31.642135 Set Vref, RX VrefLevel [Byte0]: 42
3312 12:17:31.645074 [Byte1]: 42
3313 12:17:31.649239
3314 12:17:31.649414 Set Vref, RX VrefLevel [Byte0]: 43
3315 12:17:31.653164 [Byte1]: 43
3316 12:17:31.657156
3317 12:17:31.657342 Set Vref, RX VrefLevel [Byte0]: 44
3318 12:17:31.660997 [Byte1]: 44
3319 12:17:31.665795
3320 12:17:31.666085 Set Vref, RX VrefLevel [Byte0]: 45
3321 12:17:31.668349 [Byte1]: 45
3322 12:17:31.673551
3323 12:17:31.674057 Set Vref, RX VrefLevel [Byte0]: 46
3324 12:17:31.676729 [Byte1]: 46
3325 12:17:31.681319
3326 12:17:31.681829 Set Vref, RX VrefLevel [Byte0]: 47
3327 12:17:31.685021 [Byte1]: 47
3328 12:17:31.688943
3329 12:17:31.689400 Set Vref, RX VrefLevel [Byte0]: 48
3330 12:17:31.692625 [Byte1]: 48
3331 12:17:31.697208
3332 12:17:31.697758 Set Vref, RX VrefLevel [Byte0]: 49
3333 12:17:31.700184 [Byte1]: 49
3334 12:17:31.704856
3335 12:17:31.705409 Set Vref, RX VrefLevel [Byte0]: 50
3336 12:17:31.707979 [Byte1]: 50
3337 12:17:31.712897
3338 12:17:31.713439 Set Vref, RX VrefLevel [Byte0]: 51
3339 12:17:31.715986 [Byte1]: 51
3340 12:17:31.720367
3341 12:17:31.720823 Set Vref, RX VrefLevel [Byte0]: 52
3342 12:17:31.723282 [Byte1]: 52
3343 12:17:31.728172
3344 12:17:31.728660 Set Vref, RX VrefLevel [Byte0]: 53
3345 12:17:31.732892 [Byte1]: 53
3346 12:17:31.736003
3347 12:17:31.736460 Set Vref, RX VrefLevel [Byte0]: 54
3348 12:17:31.739497 [Byte1]: 54
3349 12:17:31.743838
3350 12:17:31.744420 Set Vref, RX VrefLevel [Byte0]: 55
3351 12:17:31.747140 [Byte1]: 55
3352 12:17:31.751469
3353 12:17:31.751907 Set Vref, RX VrefLevel [Byte0]: 56
3354 12:17:31.754786 [Byte1]: 56
3355 12:17:31.759761
3356 12:17:31.760220 Set Vref, RX VrefLevel [Byte0]: 57
3357 12:17:31.763159 [Byte1]: 57
3358 12:17:31.767715
3359 12:17:31.768269 Set Vref, RX VrefLevel [Byte0]: 58
3360 12:17:31.770840 [Byte1]: 58
3361 12:17:31.775617
3362 12:17:31.776043 Set Vref, RX VrefLevel [Byte0]: 59
3363 12:17:31.778630 [Byte1]: 59
3364 12:17:31.782999
3365 12:17:31.783430 Set Vref, RX VrefLevel [Byte0]: 60
3366 12:17:31.786631 [Byte1]: 60
3367 12:17:31.791137
3368 12:17:31.791571 Set Vref, RX VrefLevel [Byte0]: 61
3369 12:17:31.794335 [Byte1]: 61
3370 12:17:31.799076
3371 12:17:31.799517 Set Vref, RX VrefLevel [Byte0]: 62
3372 12:17:31.802291 [Byte1]: 62
3373 12:17:31.806322
3374 12:17:31.806922 Set Vref, RX VrefLevel [Byte0]: 63
3375 12:17:31.809954 [Byte1]: 63
3376 12:17:31.814697
3377 12:17:31.815266 Set Vref, RX VrefLevel [Byte0]: 64
3378 12:17:31.817860 [Byte1]: 64
3379 12:17:31.822486
3380 12:17:31.822925 Set Vref, RX VrefLevel [Byte0]: 65
3381 12:17:31.825504 [Byte1]: 65
3382 12:17:31.830158
3383 12:17:31.830586 Set Vref, RX VrefLevel [Byte0]: 66
3384 12:17:31.833439 [Byte1]: 66
3385 12:17:31.838136
3386 12:17:31.838571 Set Vref, RX VrefLevel [Byte0]: 67
3387 12:17:31.841573 [Byte1]: 67
3388 12:17:31.845583
3389 12:17:31.846019 Set Vref, RX VrefLevel [Byte0]: 68
3390 12:17:31.849437 [Byte1]: 68
3391 12:17:31.853588
3392 12:17:31.854020 Set Vref, RX VrefLevel [Byte0]: 69
3393 12:17:31.856699 [Byte1]: 69
3394 12:17:31.861248
3395 12:17:31.861675 Final RX Vref Byte 0 = 53 to rank0
3396 12:17:31.865014 Final RX Vref Byte 1 = 51 to rank0
3397 12:17:31.868353 Final RX Vref Byte 0 = 53 to rank1
3398 12:17:31.871647 Final RX Vref Byte 1 = 51 to rank1==
3399 12:17:31.874707 Dram Type= 6, Freq= 0, CH_1, rank 0
3400 12:17:31.881738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3401 12:17:31.882179 ==
3402 12:17:31.882526 DQS Delay:
3403 12:17:31.882858 DQS0 = 0, DQS1 = 0
3404 12:17:31.885063 DQM Delay:
3405 12:17:31.885509 DQM0 = 120, DQM1 = 117
3406 12:17:31.888102 DQ Delay:
3407 12:17:31.891227 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3408 12:17:31.895159 DQ4 =120, DQ5 =128, DQ6 =130, DQ7 =120
3409 12:17:31.897993 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =110
3410 12:17:31.901853 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3411 12:17:31.902286
3412 12:17:31.902643
3413 12:17:31.908569 [DQSOSCAuto] RK0, (LSB)MR18= 0xfc0f, (MSB)MR19= 0x304, tDQSOscB0 = 404 ps tDQSOscB1 = 411 ps
3414 12:17:31.911344 CH1 RK0: MR19=304, MR18=FC0F
3415 12:17:31.918535 CH1_RK0: MR19=0x304, MR18=0xFC0F, DQSOSC=404, MR23=63, INC=40, DEC=26
3416 12:17:31.918978
3417 12:17:31.922055 ----->DramcWriteLeveling(PI) begin...
3418 12:17:31.922507 ==
3419 12:17:31.924921 Dram Type= 6, Freq= 0, CH_1, rank 1
3420 12:17:31.928697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3421 12:17:31.931617 ==
3422 12:17:31.932073 Write leveling (Byte 0): 26 => 26
3423 12:17:31.934974 Write leveling (Byte 1): 28 => 28
3424 12:17:31.938282 DramcWriteLeveling(PI) end<-----
3425 12:17:31.938716
3426 12:17:31.939072 ==
3427 12:17:31.941642 Dram Type= 6, Freq= 0, CH_1, rank 1
3428 12:17:31.948771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3429 12:17:31.949218 ==
3430 12:17:31.949635 [Gating] SW mode calibration
3431 12:17:31.958561 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3432 12:17:31.961518 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3433 12:17:31.965046 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3434 12:17:31.971901 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 12:17:31.974973 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 12:17:31.978781 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 12:17:31.985066 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 12:17:31.988117 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 12:17:31.992379 0 15 24 | B1->B0 | 2a2a 3434 | 0 0 | (0 0) (0 0)
3440 12:17:31.998480 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3441 12:17:32.001699 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3442 12:17:32.005384 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 12:17:32.011724 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 12:17:32.015369 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 12:17:32.018656 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 12:17:32.024913 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3447 12:17:32.028863 1 0 24 | B1->B0 | 3f3f 2f2f | 0 0 | (0 0) (0 0)
3448 12:17:32.031944 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3449 12:17:32.038398 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 12:17:32.041618 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 12:17:32.045029 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 12:17:32.048458 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 12:17:32.055275 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 12:17:32.058503 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 12:17:32.062056 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3456 12:17:32.068444 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3457 12:17:32.071824 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 12:17:32.075109 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 12:17:32.081819 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 12:17:32.085395 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 12:17:32.088501 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 12:17:32.095090 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 12:17:32.098318 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 12:17:32.101539 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 12:17:32.108622 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 12:17:32.111436 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 12:17:32.114514 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 12:17:32.121751 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 12:17:32.124991 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 12:17:32.128153 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3471 12:17:32.134978 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3472 12:17:32.138093 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 12:17:32.141091 Total UI for P1: 0, mck2ui 16
3474 12:17:32.144784 best dqsien dly found for B0: ( 1, 3, 26)
3475 12:17:32.147726 Total UI for P1: 0, mck2ui 16
3476 12:17:32.151087 best dqsien dly found for B1: ( 1, 3, 22)
3477 12:17:32.154619 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3478 12:17:32.158061 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3479 12:17:32.158576
3480 12:17:32.161457 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3481 12:17:32.164781 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3482 12:17:32.167955 [Gating] SW calibration Done
3483 12:17:32.168419 ==
3484 12:17:32.171014 Dram Type= 6, Freq= 0, CH_1, rank 1
3485 12:17:32.174741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3486 12:17:32.177875 ==
3487 12:17:32.178325 RX Vref Scan: 0
3488 12:17:32.178762
3489 12:17:32.181370 RX Vref 0 -> 0, step: 1
3490 12:17:32.181793
3491 12:17:32.184530 RX Delay -40 -> 252, step: 8
3492 12:17:32.187962 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3493 12:17:32.191188 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
3494 12:17:32.194731 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3495 12:17:32.197847 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3496 12:17:32.204386 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3497 12:17:32.208041 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3498 12:17:32.211083 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3499 12:17:32.214107 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3500 12:17:32.217746 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3501 12:17:32.221074 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3502 12:17:32.227476 iDelay=200, Bit 10, Center 123 (56 ~ 191) 136
3503 12:17:32.230815 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3504 12:17:32.234772 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3505 12:17:32.237728 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3506 12:17:32.244269 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3507 12:17:32.247553 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3508 12:17:32.247979 ==
3509 12:17:32.250730 Dram Type= 6, Freq= 0, CH_1, rank 1
3510 12:17:32.254056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3511 12:17:32.254486 ==
3512 12:17:32.257807 DQS Delay:
3513 12:17:32.258235 DQS0 = 0, DQS1 = 0
3514 12:17:32.258668 DQM Delay:
3515 12:17:32.260740 DQM0 = 122, DQM1 = 119
3516 12:17:32.261152 DQ Delay:
3517 12:17:32.264269 DQ0 =123, DQ1 =123, DQ2 =107, DQ3 =119
3518 12:17:32.267412 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3519 12:17:32.270614 DQ8 =107, DQ9 =107, DQ10 =123, DQ11 =115
3520 12:17:32.277573 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3521 12:17:32.277987
3522 12:17:32.278312
3523 12:17:32.278613 ==
3524 12:17:32.280902 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 12:17:32.284392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 12:17:32.284792 ==
3527 12:17:32.285205
3528 12:17:32.285612
3529 12:17:32.287093 TX Vref Scan disable
3530 12:17:32.287596 == TX Byte 0 ==
3531 12:17:32.294050 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3532 12:17:32.297089 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3533 12:17:32.297633 == TX Byte 1 ==
3534 12:17:32.304005 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3535 12:17:32.307607 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3536 12:17:32.308047 ==
3537 12:17:32.310727 Dram Type= 6, Freq= 0, CH_1, rank 1
3538 12:17:32.314170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3539 12:17:32.314619 ==
3540 12:17:32.326450 TX Vref=22, minBit 10, minWin=25, winSum=419
3541 12:17:32.329977 TX Vref=24, minBit 10, minWin=25, winSum=425
3542 12:17:32.333283 TX Vref=26, minBit 2, minWin=26, winSum=429
3543 12:17:32.336578 TX Vref=28, minBit 9, minWin=26, winSum=434
3544 12:17:32.339969 TX Vref=30, minBit 1, minWin=27, winSum=439
3545 12:17:32.346308 TX Vref=32, minBit 9, minWin=26, winSum=433
3546 12:17:32.349957 [TxChooseVref] Worse bit 1, Min win 27, Win sum 439, Final Vref 30
3547 12:17:32.350407
3548 12:17:32.353169 Final TX Range 1 Vref 30
3549 12:17:32.353611
3550 12:17:32.353967 ==
3551 12:17:32.356580 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 12:17:32.359659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 12:17:32.363351 ==
3554 12:17:32.363899
3555 12:17:32.364256
3556 12:17:32.364635 TX Vref Scan disable
3557 12:17:32.366344 == TX Byte 0 ==
3558 12:17:32.369624 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3559 12:17:32.376435 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3560 12:17:32.376994 == TX Byte 1 ==
3561 12:17:32.380149 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3562 12:17:32.385972 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3563 12:17:32.386414
3564 12:17:32.386762 [DATLAT]
3565 12:17:32.387090 Freq=1200, CH1 RK1
3566 12:17:32.387391
3567 12:17:32.389662 DATLAT Default: 0xd
3568 12:17:32.390243 0, 0xFFFF, sum = 0
3569 12:17:32.392788 1, 0xFFFF, sum = 0
3570 12:17:32.396134 2, 0xFFFF, sum = 0
3571 12:17:32.396720 3, 0xFFFF, sum = 0
3572 12:17:32.399572 4, 0xFFFF, sum = 0
3573 12:17:32.400035 5, 0xFFFF, sum = 0
3574 12:17:32.402686 6, 0xFFFF, sum = 0
3575 12:17:32.403142 7, 0xFFFF, sum = 0
3576 12:17:32.405885 8, 0xFFFF, sum = 0
3577 12:17:32.406478 9, 0xFFFF, sum = 0
3578 12:17:32.409542 10, 0xFFFF, sum = 0
3579 12:17:32.410105 11, 0xFFFF, sum = 0
3580 12:17:32.412690 12, 0x0, sum = 1
3581 12:17:32.413273 13, 0x0, sum = 2
3582 12:17:32.416454 14, 0x0, sum = 3
3583 12:17:32.416909 15, 0x0, sum = 4
3584 12:17:32.419087 best_step = 13
3585 12:17:32.419523
3586 12:17:32.419890 ==
3587 12:17:32.422861 Dram Type= 6, Freq= 0, CH_1, rank 1
3588 12:17:32.425815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3589 12:17:32.426257 ==
3590 12:17:32.426605 RX Vref Scan: 0
3591 12:17:32.429186
3592 12:17:32.429631 RX Vref 0 -> 0, step: 1
3593 12:17:32.429983
3594 12:17:32.432420 RX Delay -5 -> 252, step: 4
3595 12:17:32.435955 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3596 12:17:32.442168 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3597 12:17:32.445866 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3598 12:17:32.449207 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3599 12:17:32.452148 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3600 12:17:32.458978 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3601 12:17:32.461833 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3602 12:17:32.464964 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3603 12:17:32.468645 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3604 12:17:32.471834 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3605 12:17:32.478670 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3606 12:17:32.481594 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3607 12:17:32.484924 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3608 12:17:32.488608 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3609 12:17:32.491701 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3610 12:17:32.498017 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3611 12:17:32.498117 ==
3612 12:17:32.501521 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 12:17:32.505022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 12:17:32.505118 ==
3615 12:17:32.505205 DQS Delay:
3616 12:17:32.508540 DQS0 = 0, DQS1 = 0
3617 12:17:32.508634 DQM Delay:
3618 12:17:32.511645 DQM0 = 120, DQM1 = 117
3619 12:17:32.511714 DQ Delay:
3620 12:17:32.514998 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3621 12:17:32.518551 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3622 12:17:32.521621 DQ8 =104, DQ9 =108, DQ10 =116, DQ11 =112
3623 12:17:32.524718 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =128
3624 12:17:32.524815
3625 12:17:32.527930
3626 12:17:32.535048 [DQSOSCAuto] RK1, (LSB)MR18= 0xfec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3627 12:17:32.538157 CH1 RK1: MR19=403, MR18=FEC
3628 12:17:32.544719 CH1_RK1: MR19=0x403, MR18=0xFEC, DQSOSC=404, MR23=63, INC=40, DEC=26
3629 12:17:32.544835 [RxdqsGatingPostProcess] freq 1200
3630 12:17:32.551123 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3631 12:17:32.554795 best DQS0 dly(2T, 0.5T) = (0, 11)
3632 12:17:32.558344 best DQS1 dly(2T, 0.5T) = (0, 11)
3633 12:17:32.561480 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3634 12:17:32.564516 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3635 12:17:32.568148 best DQS0 dly(2T, 0.5T) = (0, 11)
3636 12:17:32.571456 best DQS1 dly(2T, 0.5T) = (0, 11)
3637 12:17:32.574540 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3638 12:17:32.577668 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3639 12:17:32.580914 Pre-setting of DQS Precalculation
3640 12:17:32.584779 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3641 12:17:32.591066 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3642 12:17:32.601091 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3643 12:17:32.601167
3644 12:17:32.601255
3645 12:17:32.601340 [Calibration Summary] 2400 Mbps
3646 12:17:32.604308 CH 0, Rank 0
3647 12:17:32.604394 SW Impedance : PASS
3648 12:17:32.607894 DUTY Scan : NO K
3649 12:17:32.610970 ZQ Calibration : PASS
3650 12:17:32.611071 Jitter Meter : NO K
3651 12:17:32.614457 CBT Training : PASS
3652 12:17:32.617675 Write leveling : PASS
3653 12:17:32.617770 RX DQS gating : PASS
3654 12:17:32.620928 RX DQ/DQS(RDDQC) : PASS
3655 12:17:32.624399 TX DQ/DQS : PASS
3656 12:17:32.624472 RX DATLAT : PASS
3657 12:17:32.627870 RX DQ/DQS(Engine): PASS
3658 12:17:32.630955 TX OE : NO K
3659 12:17:32.631048 All Pass.
3660 12:17:32.631133
3661 12:17:32.631219 CH 0, Rank 1
3662 12:17:32.634638 SW Impedance : PASS
3663 12:17:32.637897 DUTY Scan : NO K
3664 12:17:32.637968 ZQ Calibration : PASS
3665 12:17:32.641178 Jitter Meter : NO K
3666 12:17:32.644536 CBT Training : PASS
3667 12:17:32.644632 Write leveling : PASS
3668 12:17:32.647648 RX DQS gating : PASS
3669 12:17:32.647715 RX DQ/DQS(RDDQC) : PASS
3670 12:17:32.651166 TX DQ/DQS : PASS
3671 12:17:32.654417 RX DATLAT : PASS
3672 12:17:32.654487 RX DQ/DQS(Engine): PASS
3673 12:17:32.657492 TX OE : NO K
3674 12:17:32.657569 All Pass.
3675 12:17:32.657629
3676 12:17:32.661250 CH 1, Rank 0
3677 12:17:32.661347 SW Impedance : PASS
3678 12:17:32.664190 DUTY Scan : NO K
3679 12:17:32.667457 ZQ Calibration : PASS
3680 12:17:32.667552 Jitter Meter : NO K
3681 12:17:32.671407 CBT Training : PASS
3682 12:17:32.674091 Write leveling : PASS
3683 12:17:32.674162 RX DQS gating : PASS
3684 12:17:32.677510 RX DQ/DQS(RDDQC) : PASS
3685 12:17:32.680964 TX DQ/DQS : PASS
3686 12:17:32.681040 RX DATLAT : PASS
3687 12:17:32.684159 RX DQ/DQS(Engine): PASS
3688 12:17:32.687498 TX OE : NO K
3689 12:17:32.687595 All Pass.
3690 12:17:32.687682
3691 12:17:32.687766 CH 1, Rank 1
3692 12:17:32.691243 SW Impedance : PASS
3693 12:17:32.694555 DUTY Scan : NO K
3694 12:17:32.694649 ZQ Calibration : PASS
3695 12:17:32.697505 Jitter Meter : NO K
3696 12:17:32.697599 CBT Training : PASS
3697 12:17:32.700898 Write leveling : PASS
3698 12:17:32.704685 RX DQS gating : PASS
3699 12:17:32.704781 RX DQ/DQS(RDDQC) : PASS
3700 12:17:32.707884 TX DQ/DQS : PASS
3701 12:17:32.711102 RX DATLAT : PASS
3702 12:17:32.711173 RX DQ/DQS(Engine): PASS
3703 12:17:32.714465 TX OE : NO K
3704 12:17:32.714560 All Pass.
3705 12:17:32.714646
3706 12:17:32.717427 DramC Write-DBI off
3707 12:17:32.720829 PER_BANK_REFRESH: Hybrid Mode
3708 12:17:32.720902 TX_TRACKING: ON
3709 12:17:32.730765 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3710 12:17:32.734326 [FAST_K] Save calibration result to emmc
3711 12:17:32.737333 dramc_set_vcore_voltage set vcore to 650000
3712 12:17:32.740835 Read voltage for 600, 5
3713 12:17:32.740911 Vio18 = 0
3714 12:17:32.740973 Vcore = 650000
3715 12:17:32.744071 Vdram = 0
3716 12:17:32.744140 Vddq = 0
3717 12:17:32.744200 Vmddr = 0
3718 12:17:32.750831 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3719 12:17:32.754019 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3720 12:17:32.757575 MEM_TYPE=3, freq_sel=19
3721 12:17:32.760955 sv_algorithm_assistance_LP4_1600
3722 12:17:32.764034 ============ PULL DRAM RESETB DOWN ============
3723 12:17:32.767975 ========== PULL DRAM RESETB DOWN end =========
3724 12:17:32.774214 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3725 12:17:32.777482 ===================================
3726 12:17:32.777556 LPDDR4 DRAM CONFIGURATION
3727 12:17:32.780924 ===================================
3728 12:17:32.784479 EX_ROW_EN[0] = 0x0
3729 12:17:32.787188 EX_ROW_EN[1] = 0x0
3730 12:17:32.787291 LP4Y_EN = 0x0
3731 12:17:32.790797 WORK_FSP = 0x0
3732 12:17:32.790871 WL = 0x2
3733 12:17:32.793909 RL = 0x2
3734 12:17:32.793978 BL = 0x2
3735 12:17:32.797824 RPST = 0x0
3736 12:17:32.797892 RD_PRE = 0x0
3737 12:17:32.800978 WR_PRE = 0x1
3738 12:17:32.801071 WR_PST = 0x0
3739 12:17:32.803853 DBI_WR = 0x0
3740 12:17:32.803947 DBI_RD = 0x0
3741 12:17:32.807417 OTF = 0x1
3742 12:17:32.810802 ===================================
3743 12:17:32.813830 ===================================
3744 12:17:32.813927 ANA top config
3745 12:17:32.817220 ===================================
3746 12:17:32.820461 DLL_ASYNC_EN = 0
3747 12:17:32.824149 ALL_SLAVE_EN = 1
3748 12:17:32.827171 NEW_RANK_MODE = 1
3749 12:17:32.827243 DLL_IDLE_MODE = 1
3750 12:17:32.830319 LP45_APHY_COMB_EN = 1
3751 12:17:32.833996 TX_ODT_DIS = 1
3752 12:17:32.837046 NEW_8X_MODE = 1
3753 12:17:32.840364 ===================================
3754 12:17:32.843976 ===================================
3755 12:17:32.847459 data_rate = 1200
3756 12:17:32.847530 CKR = 1
3757 12:17:32.850725 DQ_P2S_RATIO = 8
3758 12:17:32.853987 ===================================
3759 12:17:32.857761 CA_P2S_RATIO = 8
3760 12:17:32.860713 DQ_CA_OPEN = 0
3761 12:17:32.864220 DQ_SEMI_OPEN = 0
3762 12:17:32.867053 CA_SEMI_OPEN = 0
3763 12:17:32.867132 CA_FULL_RATE = 0
3764 12:17:32.870537 DQ_CKDIV4_EN = 1
3765 12:17:32.873657 CA_CKDIV4_EN = 1
3766 12:17:32.877110 CA_PREDIV_EN = 0
3767 12:17:32.880872 PH8_DLY = 0
3768 12:17:32.880970 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3769 12:17:32.883879 DQ_AAMCK_DIV = 4
3770 12:17:32.887087 CA_AAMCK_DIV = 4
3771 12:17:32.890428 CA_ADMCK_DIV = 4
3772 12:17:32.894083 DQ_TRACK_CA_EN = 0
3773 12:17:32.897502 CA_PICK = 600
3774 12:17:32.900622 CA_MCKIO = 600
3775 12:17:32.900719 MCKIO_SEMI = 0
3776 12:17:32.903603 PLL_FREQ = 2288
3777 12:17:32.907441 DQ_UI_PI_RATIO = 32
3778 12:17:32.910623 CA_UI_PI_RATIO = 0
3779 12:17:32.913880 ===================================
3780 12:17:32.917048 ===================================
3781 12:17:32.920147 memory_type:LPDDR4
3782 12:17:32.920241 GP_NUM : 10
3783 12:17:32.923484 SRAM_EN : 1
3784 12:17:32.927069 MD32_EN : 0
3785 12:17:32.930157 ===================================
3786 12:17:32.930229 [ANA_INIT] >>>>>>>>>>>>>>
3787 12:17:32.933359 <<<<<< [CONFIGURE PHASE]: ANA_TX
3788 12:17:32.937207 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3789 12:17:32.940375 ===================================
3790 12:17:32.943404 data_rate = 1200,PCW = 0X5800
3791 12:17:32.947150 ===================================
3792 12:17:32.950123 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3793 12:17:32.956906 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3794 12:17:32.960438 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3795 12:17:32.966622 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3796 12:17:32.970223 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3797 12:17:32.973387 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3798 12:17:32.973457 [ANA_INIT] flow start
3799 12:17:32.976618 [ANA_INIT] PLL >>>>>>>>
3800 12:17:32.980097 [ANA_INIT] PLL <<<<<<<<
3801 12:17:32.980194 [ANA_INIT] MIDPI >>>>>>>>
3802 12:17:32.983274 [ANA_INIT] MIDPI <<<<<<<<
3803 12:17:32.987042 [ANA_INIT] DLL >>>>>>>>
3804 12:17:32.987115 [ANA_INIT] flow end
3805 12:17:32.993432 ============ LP4 DIFF to SE enter ============
3806 12:17:32.996891 ============ LP4 DIFF to SE exit ============
3807 12:17:32.999992 [ANA_INIT] <<<<<<<<<<<<<
3808 12:17:33.003107 [Flow] Enable top DCM control >>>>>
3809 12:17:33.006801 [Flow] Enable top DCM control <<<<<
3810 12:17:33.009995 Enable DLL master slave shuffle
3811 12:17:33.013225 ==============================================================
3812 12:17:33.016376 Gating Mode config
3813 12:17:33.019999 ==============================================================
3814 12:17:33.023135 Config description:
3815 12:17:33.033775 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3816 12:17:33.039912 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3817 12:17:33.043134 SELPH_MODE 0: By rank 1: By Phase
3818 12:17:33.049740 ==============================================================
3819 12:17:33.053221 GAT_TRACK_EN = 1
3820 12:17:33.056249 RX_GATING_MODE = 2
3821 12:17:33.060178 RX_GATING_TRACK_MODE = 2
3822 12:17:33.063282 SELPH_MODE = 1
3823 12:17:33.063361 PICG_EARLY_EN = 1
3824 12:17:33.066802 VALID_LAT_VALUE = 1
3825 12:17:33.073103 ==============================================================
3826 12:17:33.076690 Enter into Gating configuration >>>>
3827 12:17:33.079897 Exit from Gating configuration <<<<
3828 12:17:33.083228 Enter into DVFS_PRE_config >>>>>
3829 12:17:33.093240 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3830 12:17:33.096405 Exit from DVFS_PRE_config <<<<<
3831 12:17:33.099673 Enter into PICG configuration >>>>
3832 12:17:33.103068 Exit from PICG configuration <<<<
3833 12:17:33.106165 [RX_INPUT] configuration >>>>>
3834 12:17:33.109183 [RX_INPUT] configuration <<<<<
3835 12:17:33.113134 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3836 12:17:33.119262 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3837 12:17:33.125953 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3838 12:17:33.133040 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3839 12:17:33.139607 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3840 12:17:33.142791 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3841 12:17:33.149692 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3842 12:17:33.152902 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3843 12:17:33.155833 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3844 12:17:33.159254 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3845 12:17:33.165652 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3846 12:17:33.169367 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3847 12:17:33.172375 ===================================
3848 12:17:33.175752 LPDDR4 DRAM CONFIGURATION
3849 12:17:33.178925 ===================================
3850 12:17:33.179024 EX_ROW_EN[0] = 0x0
3851 12:17:33.182528 EX_ROW_EN[1] = 0x0
3852 12:17:33.182608 LP4Y_EN = 0x0
3853 12:17:33.185741 WORK_FSP = 0x0
3854 12:17:33.189275 WL = 0x2
3855 12:17:33.189353 RL = 0x2
3856 12:17:33.192388 BL = 0x2
3857 12:17:33.192464 RPST = 0x0
3858 12:17:33.195680 RD_PRE = 0x0
3859 12:17:33.195749 WR_PRE = 0x1
3860 12:17:33.198680 WR_PST = 0x0
3861 12:17:33.198749 DBI_WR = 0x0
3862 12:17:33.201961 DBI_RD = 0x0
3863 12:17:33.202056 OTF = 0x1
3864 12:17:33.205638 ===================================
3865 12:17:33.208464 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3866 12:17:33.215134 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3867 12:17:33.218706 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3868 12:17:33.221743 ===================================
3869 12:17:33.225618 LPDDR4 DRAM CONFIGURATION
3870 12:17:33.228426 ===================================
3871 12:17:33.228530 EX_ROW_EN[0] = 0x10
3872 12:17:33.231889 EX_ROW_EN[1] = 0x0
3873 12:17:33.231986 LP4Y_EN = 0x0
3874 12:17:33.235233 WORK_FSP = 0x0
3875 12:17:33.238382 WL = 0x2
3876 12:17:33.238482 RL = 0x2
3877 12:17:33.242094 BL = 0x2
3878 12:17:33.242191 RPST = 0x0
3879 12:17:33.244872 RD_PRE = 0x0
3880 12:17:33.244948 WR_PRE = 0x1
3881 12:17:33.248538 WR_PST = 0x0
3882 12:17:33.248612 DBI_WR = 0x0
3883 12:17:33.251666 DBI_RD = 0x0
3884 12:17:33.251732 OTF = 0x1
3885 12:17:33.255579 ===================================
3886 12:17:33.261718 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3887 12:17:33.265760 nWR fixed to 30
3888 12:17:33.268802 [ModeRegInit_LP4] CH0 RK0
3889 12:17:33.268896 [ModeRegInit_LP4] CH0 RK1
3890 12:17:33.272631 [ModeRegInit_LP4] CH1 RK0
3891 12:17:33.275694 [ModeRegInit_LP4] CH1 RK1
3892 12:17:33.275766 match AC timing 17
3893 12:17:33.282307 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3894 12:17:33.285712 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3895 12:17:33.288687 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3896 12:17:33.295480 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3897 12:17:33.298705 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3898 12:17:33.298802 ==
3899 12:17:33.302039 Dram Type= 6, Freq= 0, CH_0, rank 0
3900 12:17:33.305218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3901 12:17:33.305320 ==
3902 12:17:33.312341 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3903 12:17:33.318684 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3904 12:17:33.321845 [CA 0] Center 35 (5~66) winsize 62
3905 12:17:33.325649 [CA 1] Center 35 (5~66) winsize 62
3906 12:17:33.328903 [CA 2] Center 33 (3~64) winsize 62
3907 12:17:33.331781 [CA 3] Center 33 (2~64) winsize 63
3908 12:17:33.334853 [CA 4] Center 33 (2~64) winsize 63
3909 12:17:33.338341 [CA 5] Center 32 (2~63) winsize 62
3910 12:17:33.338434
3911 12:17:33.341699 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3912 12:17:33.341776
3913 12:17:33.344956 [CATrainingPosCal] consider 1 rank data
3914 12:17:33.348431 u2DelayCellTimex100 = 270/100 ps
3915 12:17:33.351626 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3916 12:17:33.354737 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3917 12:17:33.358394 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3918 12:17:33.361594 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3919 12:17:33.368544 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3920 12:17:33.371397 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3921 12:17:33.371468
3922 12:17:33.374988 CA PerBit enable=1, Macro0, CA PI delay=32
3923 12:17:33.375082
3924 12:17:33.378457 [CBTSetCACLKResult] CA Dly = 32
3925 12:17:33.378531 CS Dly: 5 (0~36)
3926 12:17:33.378592 ==
3927 12:17:33.381627 Dram Type= 6, Freq= 0, CH_0, rank 1
3928 12:17:33.384690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3929 12:17:33.388346 ==
3930 12:17:33.391473 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3931 12:17:33.398029 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3932 12:17:33.401584 [CA 0] Center 35 (5~66) winsize 62
3933 12:17:33.404848 [CA 1] Center 35 (5~66) winsize 62
3934 12:17:33.408051 [CA 2] Center 34 (3~65) winsize 63
3935 12:17:33.411348 [CA 3] Center 33 (3~64) winsize 62
3936 12:17:33.414459 [CA 4] Center 33 (2~64) winsize 63
3937 12:17:33.417584 [CA 5] Center 32 (2~63) winsize 62
3938 12:17:33.417657
3939 12:17:33.421332 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3940 12:17:33.421399
3941 12:17:33.424550 [CATrainingPosCal] consider 2 rank data
3942 12:17:33.427765 u2DelayCellTimex100 = 270/100 ps
3943 12:17:33.430987 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3944 12:17:33.434576 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3945 12:17:33.441308 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3946 12:17:33.444521 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3947 12:17:33.448035 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3948 12:17:33.451114 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3949 12:17:33.451209
3950 12:17:33.454490 CA PerBit enable=1, Macro0, CA PI delay=32
3951 12:17:33.454586
3952 12:17:33.457444 [CBTSetCACLKResult] CA Dly = 32
3953 12:17:33.457538 CS Dly: 4 (0~35)
3954 12:17:33.457626
3955 12:17:33.461222 ----->DramcWriteLeveling(PI) begin...
3956 12:17:33.464368 ==
3957 12:17:33.464439 Dram Type= 6, Freq= 0, CH_0, rank 0
3958 12:17:33.470854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3959 12:17:33.470952 ==
3960 12:17:33.474601 Write leveling (Byte 0): 34 => 34
3961 12:17:33.477525 Write leveling (Byte 1): 30 => 30
3962 12:17:33.481139 DramcWriteLeveling(PI) end<-----
3963 12:17:33.481233
3964 12:17:33.481322 ==
3965 12:17:33.484054 Dram Type= 6, Freq= 0, CH_0, rank 0
3966 12:17:33.487398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3967 12:17:33.487499 ==
3968 12:17:33.490988 [Gating] SW mode calibration
3969 12:17:33.497313 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3970 12:17:33.501062 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3971 12:17:33.507488 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3972 12:17:33.510803 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3973 12:17:33.514066 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3974 12:17:33.520948 0 9 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
3975 12:17:33.524228 0 9 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
3976 12:17:33.527546 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3977 12:17:33.533894 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 12:17:33.537710 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 12:17:33.540751 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 12:17:33.547493 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 12:17:33.551107 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3982 12:17:33.554155 0 10 12 | B1->B0 | 2323 3636 | 0 1 | (0 0) (0 0)
3983 12:17:33.560932 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
3984 12:17:33.563899 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 12:17:33.567150 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 12:17:33.574003 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 12:17:33.577736 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 12:17:33.580481 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 12:17:33.587284 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 12:17:33.590764 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 12:17:33.593838 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 12:17:33.600676 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 12:17:33.604047 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 12:17:33.607192 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 12:17:33.610555 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 12:17:33.617220 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 12:17:33.620905 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 12:17:33.623943 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 12:17:33.630341 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 12:17:33.634119 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 12:17:33.637420 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 12:17:33.643741 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 12:17:33.646968 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 12:17:33.650490 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 12:17:33.657321 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 12:17:33.660450 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 12:17:33.663980 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 12:17:33.667114 Total UI for P1: 0, mck2ui 16
4009 12:17:33.670883 best dqsien dly found for B0: ( 0, 13, 14)
4010 12:17:33.673945 Total UI for P1: 0, mck2ui 16
4011 12:17:33.677371 best dqsien dly found for B1: ( 0, 13, 14)
4012 12:17:33.680549 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4013 12:17:33.684493 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4014 12:17:33.684566
4015 12:17:33.690623 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4016 12:17:33.694271 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4017 12:17:33.694365 [Gating] SW calibration Done
4018 12:17:33.697375 ==
4019 12:17:33.700560 Dram Type= 6, Freq= 0, CH_0, rank 0
4020 12:17:33.704178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 12:17:33.704248 ==
4022 12:17:33.704351 RX Vref Scan: 0
4023 12:17:33.704411
4024 12:17:33.707414 RX Vref 0 -> 0, step: 1
4025 12:17:33.707480
4026 12:17:33.710840 RX Delay -230 -> 252, step: 16
4027 12:17:33.713929 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4028 12:17:33.717416 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4029 12:17:33.723628 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4030 12:17:33.727044 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4031 12:17:33.730545 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4032 12:17:33.733604 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4033 12:17:33.736958 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4034 12:17:33.744100 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4035 12:17:33.747213 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4036 12:17:33.750851 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4037 12:17:33.754019 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4038 12:17:33.760236 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4039 12:17:33.764127 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4040 12:17:33.767328 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4041 12:17:33.770446 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4042 12:17:33.776783 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4043 12:17:33.776858 ==
4044 12:17:33.780379 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 12:17:33.783751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 12:17:33.783818 ==
4047 12:17:33.783878 DQS Delay:
4048 12:17:33.787207 DQS0 = 0, DQS1 = 0
4049 12:17:33.787273 DQM Delay:
4050 12:17:33.790219 DQM0 = 50, DQM1 = 45
4051 12:17:33.790286 DQ Delay:
4052 12:17:33.793401 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4053 12:17:33.797066 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4054 12:17:33.800478 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4055 12:17:33.803534 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4056 12:17:33.803632
4057 12:17:33.803720
4058 12:17:33.803815 ==
4059 12:17:33.807180 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 12:17:33.810395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 12:17:33.810498 ==
4062 12:17:33.810596
4063 12:17:33.813537
4064 12:17:33.813612 TX Vref Scan disable
4065 12:17:33.816625 == TX Byte 0 ==
4066 12:17:33.820243 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4067 12:17:33.823654 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4068 12:17:33.826849 == TX Byte 1 ==
4069 12:17:33.830667 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4070 12:17:33.833654 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4071 12:17:33.833754 ==
4072 12:17:33.837218 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 12:17:33.843487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 12:17:33.843577 ==
4075 12:17:33.843662
4076 12:17:33.843739
4077 12:17:33.843833 TX Vref Scan disable
4078 12:17:33.848011 == TX Byte 0 ==
4079 12:17:33.851473 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4080 12:17:33.857923 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4081 12:17:33.858029 == TX Byte 1 ==
4082 12:17:33.860900 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4083 12:17:33.867916 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4084 12:17:33.867992
4085 12:17:33.868053 [DATLAT]
4086 12:17:33.868118 Freq=600, CH0 RK0
4087 12:17:33.868174
4088 12:17:33.871009 DATLAT Default: 0x9
4089 12:17:33.871085 0, 0xFFFF, sum = 0
4090 12:17:33.874250 1, 0xFFFF, sum = 0
4091 12:17:33.874351 2, 0xFFFF, sum = 0
4092 12:17:33.877979 3, 0xFFFF, sum = 0
4093 12:17:33.881355 4, 0xFFFF, sum = 0
4094 12:17:33.881454 5, 0xFFFF, sum = 0
4095 12:17:33.884345 6, 0xFFFF, sum = 0
4096 12:17:33.884441 7, 0xFFFF, sum = 0
4097 12:17:33.887552 8, 0x0, sum = 1
4098 12:17:33.887647 9, 0x0, sum = 2
4099 12:17:33.887739 10, 0x0, sum = 3
4100 12:17:33.891394 11, 0x0, sum = 4
4101 12:17:33.891465 best_step = 9
4102 12:17:33.891525
4103 12:17:33.891584 ==
4104 12:17:33.894651 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 12:17:33.900991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 12:17:33.901071 ==
4107 12:17:33.901134 RX Vref Scan: 1
4108 12:17:33.901196
4109 12:17:33.904217 RX Vref 0 -> 0, step: 1
4110 12:17:33.904350
4111 12:17:33.907814 RX Delay -163 -> 252, step: 8
4112 12:17:33.907909
4113 12:17:33.910690 Set Vref, RX VrefLevel [Byte0]: 56
4114 12:17:33.914349 [Byte1]: 47
4115 12:17:33.914447
4116 12:17:33.917535 Final RX Vref Byte 0 = 56 to rank0
4117 12:17:33.920662 Final RX Vref Byte 1 = 47 to rank0
4118 12:17:33.924158 Final RX Vref Byte 0 = 56 to rank1
4119 12:17:33.927311 Final RX Vref Byte 1 = 47 to rank1==
4120 12:17:33.930844 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 12:17:33.934291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 12:17:33.934388 ==
4123 12:17:33.937756 DQS Delay:
4124 12:17:33.937850 DQS0 = 0, DQS1 = 0
4125 12:17:33.940773 DQM Delay:
4126 12:17:33.940866 DQM0 = 53, DQM1 = 46
4127 12:17:33.940954 DQ Delay:
4128 12:17:33.944013 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4129 12:17:33.947331 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4130 12:17:33.950698 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4131 12:17:33.954061 DQ12 =56, DQ13 =48, DQ14 =56, DQ15 =52
4132 12:17:33.954156
4133 12:17:33.954242
4134 12:17:33.963922 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f62, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4135 12:17:33.967422 CH0 RK0: MR19=808, MR18=6F62
4136 12:17:33.970609 CH0_RK0: MR19=0x808, MR18=0x6F62, DQSOSC=389, MR23=63, INC=173, DEC=115
4137 12:17:33.973927
4138 12:17:33.977065 ----->DramcWriteLeveling(PI) begin...
4139 12:17:33.977155 ==
4140 12:17:33.980864 Dram Type= 6, Freq= 0, CH_0, rank 1
4141 12:17:33.984156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 12:17:33.984271 ==
4143 12:17:33.987370 Write leveling (Byte 0): 34 => 34
4144 12:17:33.990779 Write leveling (Byte 1): 30 => 30
4145 12:17:33.993827 DramcWriteLeveling(PI) end<-----
4146 12:17:33.993897
4147 12:17:33.993957 ==
4148 12:17:33.997005 Dram Type= 6, Freq= 0, CH_0, rank 1
4149 12:17:34.000847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 12:17:34.000930 ==
4151 12:17:34.004034 [Gating] SW mode calibration
4152 12:17:34.010729 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4153 12:17:34.016925 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4154 12:17:34.020416 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4155 12:17:34.023994 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4156 12:17:34.030386 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4157 12:17:34.034111 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
4158 12:17:34.037024 0 9 16 | B1->B0 | 2d2d 2d2d | 1 1 | (1 0) (1 0)
4159 12:17:34.043911 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 12:17:34.047010 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 12:17:34.050110 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 12:17:34.057024 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 12:17:34.060273 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 12:17:34.063499 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 12:17:34.067084 0 10 12 | B1->B0 | 2828 2c2c | 0 0 | (0 0) (1 1)
4166 12:17:34.073316 0 10 16 | B1->B0 | 3d3d 3f3f | 0 0 | (0 0) (1 1)
4167 12:17:34.076780 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 12:17:34.080154 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 12:17:34.087017 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 12:17:34.090288 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 12:17:34.093425 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 12:17:34.100429 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 12:17:34.103658 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4174 12:17:34.106911 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 12:17:34.113366 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 12:17:34.116436 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 12:17:34.119748 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 12:17:34.126790 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 12:17:34.130356 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 12:17:34.133268 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 12:17:34.140123 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 12:17:34.143510 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 12:17:34.146440 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 12:17:34.153219 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 12:17:34.156634 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 12:17:34.159758 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 12:17:34.167009 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 12:17:34.169892 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 12:17:34.172993 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 12:17:34.179654 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 12:17:34.179758 Total UI for P1: 0, mck2ui 16
4192 12:17:34.186465 best dqsien dly found for B0: ( 0, 13, 14)
4193 12:17:34.186568 Total UI for P1: 0, mck2ui 16
4194 12:17:34.189572 best dqsien dly found for B1: ( 0, 13, 14)
4195 12:17:34.196256 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4196 12:17:34.199529 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4197 12:17:34.199613
4198 12:17:34.202880 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4199 12:17:34.206199 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4200 12:17:34.209710 [Gating] SW calibration Done
4201 12:17:34.209789 ==
4202 12:17:34.212866 Dram Type= 6, Freq= 0, CH_0, rank 1
4203 12:17:34.216607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4204 12:17:34.216682 ==
4205 12:17:34.219746 RX Vref Scan: 0
4206 12:17:34.219844
4207 12:17:34.219923 RX Vref 0 -> 0, step: 1
4208 12:17:34.219998
4209 12:17:34.222911 RX Delay -230 -> 252, step: 16
4210 12:17:34.229368 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4211 12:17:34.232507 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4212 12:17:34.235909 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4213 12:17:34.239117 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4214 12:17:34.242642 iDelay=218, Bit 4, Center 65 (-86 ~ 217) 304
4215 12:17:34.249091 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4216 12:17:34.253008 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4217 12:17:34.256436 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4218 12:17:34.259323 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4219 12:17:34.262745 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4220 12:17:34.269441 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4221 12:17:34.272744 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4222 12:17:34.275990 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4223 12:17:34.279722 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4224 12:17:34.285838 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4225 12:17:34.289902 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4226 12:17:34.289982 ==
4227 12:17:34.292856 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 12:17:34.296402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 12:17:34.296475 ==
4230 12:17:34.299150 DQS Delay:
4231 12:17:34.299227 DQS0 = 0, DQS1 = 0
4232 12:17:34.299324 DQM Delay:
4233 12:17:34.302461 DQM0 = 55, DQM1 = 44
4234 12:17:34.302541 DQ Delay:
4235 12:17:34.305762 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4236 12:17:34.309058 DQ4 =65, DQ5 =49, DQ6 =65, DQ7 =65
4237 12:17:34.312480 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4238 12:17:34.315964 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4239 12:17:34.316064
4240 12:17:34.316161
4241 12:17:34.316259 ==
4242 12:17:34.319010 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 12:17:34.325702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 12:17:34.325806 ==
4245 12:17:34.325904
4246 12:17:34.326001
4247 12:17:34.326097 TX Vref Scan disable
4248 12:17:34.329509 == TX Byte 0 ==
4249 12:17:34.333034 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4250 12:17:34.339288 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4251 12:17:34.339370 == TX Byte 1 ==
4252 12:17:34.343045 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4253 12:17:34.349793 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4254 12:17:34.349874 ==
4255 12:17:34.352365 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 12:17:34.356145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 12:17:34.356229 ==
4258 12:17:34.356349
4259 12:17:34.356408
4260 12:17:34.359432 TX Vref Scan disable
4261 12:17:34.362573 == TX Byte 0 ==
4262 12:17:34.366041 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4263 12:17:34.369159 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4264 12:17:34.372876 == TX Byte 1 ==
4265 12:17:34.375956 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4266 12:17:34.379460 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4267 12:17:34.379574
4268 12:17:34.379663 [DATLAT]
4269 12:17:34.382901 Freq=600, CH0 RK1
4270 12:17:34.382998
4271 12:17:34.383097 DATLAT Default: 0x9
4272 12:17:34.386108 0, 0xFFFF, sum = 0
4273 12:17:34.389183 1, 0xFFFF, sum = 0
4274 12:17:34.389256 2, 0xFFFF, sum = 0
4275 12:17:34.392495 3, 0xFFFF, sum = 0
4276 12:17:34.392593 4, 0xFFFF, sum = 0
4277 12:17:34.395513 5, 0xFFFF, sum = 0
4278 12:17:34.395594 6, 0xFFFF, sum = 0
4279 12:17:34.399244 7, 0xFFFF, sum = 0
4280 12:17:34.399324 8, 0x0, sum = 1
4281 12:17:34.402435 9, 0x0, sum = 2
4282 12:17:34.402517 10, 0x0, sum = 3
4283 12:17:34.402579 11, 0x0, sum = 4
4284 12:17:34.405895 best_step = 9
4285 12:17:34.405965
4286 12:17:34.406024 ==
4287 12:17:34.409338 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 12:17:34.412554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 12:17:34.412632 ==
4290 12:17:34.415703 RX Vref Scan: 0
4291 12:17:34.415799
4292 12:17:34.415894 RX Vref 0 -> 0, step: 1
4293 12:17:34.415980
4294 12:17:34.419395 RX Delay -163 -> 252, step: 8
4295 12:17:34.426369 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4296 12:17:34.429965 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4297 12:17:34.432907 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4298 12:17:34.436609 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4299 12:17:34.440119 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4300 12:17:34.446432 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4301 12:17:34.449773 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4302 12:17:34.453265 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4303 12:17:34.456595 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4304 12:17:34.459824 iDelay=205, Bit 9, Center 32 (-107 ~ 172) 280
4305 12:17:34.466259 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4306 12:17:34.469975 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4307 12:17:34.472918 iDelay=205, Bit 12, Center 48 (-91 ~ 188) 280
4308 12:17:34.476606 iDelay=205, Bit 13, Center 52 (-83 ~ 188) 272
4309 12:17:34.483385 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4310 12:17:34.486590 iDelay=205, Bit 15, Center 56 (-83 ~ 196) 280
4311 12:17:34.486662 ==
4312 12:17:34.489839 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 12:17:34.492969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 12:17:34.493037 ==
4315 12:17:34.496841 DQS Delay:
4316 12:17:34.496907 DQS0 = 0, DQS1 = 0
4317 12:17:34.496970 DQM Delay:
4318 12:17:34.500130 DQM0 = 53, DQM1 = 46
4319 12:17:34.500228 DQ Delay:
4320 12:17:34.503116 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4321 12:17:34.506474 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60
4322 12:17:34.509685 DQ8 =36, DQ9 =32, DQ10 =48, DQ11 =40
4323 12:17:34.513434 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =56
4324 12:17:34.513517
4325 12:17:34.513582
4326 12:17:34.522839 [DQSOSCAuto] RK1, (LSB)MR18= 0x5c1e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
4327 12:17:34.522940 CH0 RK1: MR19=808, MR18=5C1E
4328 12:17:34.529597 CH0_RK1: MR19=0x808, MR18=0x5C1E, DQSOSC=392, MR23=63, INC=170, DEC=113
4329 12:17:34.533068 [RxdqsGatingPostProcess] freq 600
4330 12:17:34.539399 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4331 12:17:34.543359 Pre-setting of DQS Precalculation
4332 12:17:34.546465 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4333 12:17:34.546537 ==
4334 12:17:34.549634 Dram Type= 6, Freq= 0, CH_1, rank 0
4335 12:17:34.552951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 12:17:34.556044 ==
4337 12:17:34.559869 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4338 12:17:34.566243 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4339 12:17:34.569689 [CA 0] Center 35 (5~66) winsize 62
4340 12:17:34.573140 [CA 1] Center 35 (5~66) winsize 62
4341 12:17:34.576106 [CA 2] Center 34 (4~65) winsize 62
4342 12:17:34.579415 [CA 3] Center 34 (4~65) winsize 62
4343 12:17:34.582627 [CA 4] Center 34 (4~65) winsize 62
4344 12:17:34.586152 [CA 5] Center 34 (4~64) winsize 61
4345 12:17:34.586223
4346 12:17:34.589427 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4347 12:17:34.589522
4348 12:17:34.592774 [CATrainingPosCal] consider 1 rank data
4349 12:17:34.595994 u2DelayCellTimex100 = 270/100 ps
4350 12:17:34.599350 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4351 12:17:34.602556 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4352 12:17:34.605881 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4353 12:17:34.609106 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4354 12:17:34.615938 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4355 12:17:34.619364 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4356 12:17:34.619443
4357 12:17:34.622478 CA PerBit enable=1, Macro0, CA PI delay=34
4358 12:17:34.622573
4359 12:17:34.625986 [CBTSetCACLKResult] CA Dly = 34
4360 12:17:34.626081 CS Dly: 6 (0~37)
4361 12:17:34.626170 ==
4362 12:17:34.629502 Dram Type= 6, Freq= 0, CH_1, rank 1
4363 12:17:34.636120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 12:17:34.636221 ==
4365 12:17:34.639409 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4366 12:17:34.646260 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4367 12:17:34.648979 [CA 0] Center 36 (5~67) winsize 63
4368 12:17:34.652787 [CA 1] Center 36 (5~67) winsize 63
4369 12:17:34.655904 [CA 2] Center 34 (4~65) winsize 62
4370 12:17:34.659039 [CA 3] Center 34 (4~65) winsize 62
4371 12:17:34.662443 [CA 4] Center 35 (4~66) winsize 63
4372 12:17:34.666031 [CA 5] Center 34 (3~65) winsize 63
4373 12:17:34.666124
4374 12:17:34.669169 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4375 12:17:34.669243
4376 12:17:34.672413 [CATrainingPosCal] consider 2 rank data
4377 12:17:34.675497 u2DelayCellTimex100 = 270/100 ps
4378 12:17:34.679303 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4379 12:17:34.682777 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4380 12:17:34.685820 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4381 12:17:34.692032 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4382 12:17:34.695704 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4383 12:17:34.699323 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4384 12:17:34.699398
4385 12:17:34.702095 CA PerBit enable=1, Macro0, CA PI delay=34
4386 12:17:34.702192
4387 12:17:34.705861 [CBTSetCACLKResult] CA Dly = 34
4388 12:17:34.705958 CS Dly: 6 (0~38)
4389 12:17:34.706053
4390 12:17:34.708866 ----->DramcWriteLeveling(PI) begin...
4391 12:17:34.708976 ==
4392 12:17:34.711934 Dram Type= 6, Freq= 0, CH_1, rank 0
4393 12:17:34.718544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 12:17:34.718690 ==
4395 12:17:34.721996 Write leveling (Byte 0): 30 => 30
4396 12:17:34.725329 Write leveling (Byte 1): 30 => 30
4397 12:17:34.725403 DramcWriteLeveling(PI) end<-----
4398 12:17:34.728713
4399 12:17:34.728786 ==
4400 12:17:34.732092 Dram Type= 6, Freq= 0, CH_1, rank 0
4401 12:17:34.735314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 12:17:34.735387 ==
4403 12:17:34.738682 [Gating] SW mode calibration
4404 12:17:34.745137 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4405 12:17:34.748572 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4406 12:17:34.755171 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4407 12:17:34.758798 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4408 12:17:34.762046 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4409 12:17:34.768416 0 9 12 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (0 1)
4410 12:17:34.771960 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 12:17:34.775031 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 12:17:34.782014 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 12:17:34.785150 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 12:17:34.788355 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 12:17:34.795406 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 12:17:34.798428 0 10 8 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
4417 12:17:34.801495 0 10 12 | B1->B0 | 3535 3a3a | 1 0 | (0 0) (0 0)
4418 12:17:34.808553 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 12:17:34.811374 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 12:17:34.814711 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 12:17:34.821431 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 12:17:34.825182 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 12:17:34.828534 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 12:17:34.834801 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 12:17:34.838047 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4426 12:17:34.841525 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 12:17:34.848506 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 12:17:34.851494 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 12:17:34.854605 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 12:17:34.861631 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 12:17:34.864872 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 12:17:34.868018 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 12:17:34.874974 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 12:17:34.877925 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 12:17:34.881096 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 12:17:34.884806 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 12:17:34.891138 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 12:17:34.894911 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 12:17:34.897738 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 12:17:34.904888 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 12:17:34.907934 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4442 12:17:34.911178 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4443 12:17:34.914414 Total UI for P1: 0, mck2ui 16
4444 12:17:34.917995 best dqsien dly found for B0: ( 0, 13, 12)
4445 12:17:34.924534 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 12:17:34.927589 Total UI for P1: 0, mck2ui 16
4447 12:17:34.930883 best dqsien dly found for B1: ( 0, 13, 14)
4448 12:17:34.934231 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4449 12:17:34.937905 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4450 12:17:34.938008
4451 12:17:34.941184 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4452 12:17:34.944490 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4453 12:17:34.947608 [Gating] SW calibration Done
4454 12:17:34.947704 ==
4455 12:17:34.950664 Dram Type= 6, Freq= 0, CH_1, rank 0
4456 12:17:34.954450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4457 12:17:34.954555 ==
4458 12:17:34.957506 RX Vref Scan: 0
4459 12:17:34.957576
4460 12:17:34.961281 RX Vref 0 -> 0, step: 1
4461 12:17:34.961355
4462 12:17:34.961434 RX Delay -230 -> 252, step: 16
4463 12:17:34.967655 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4464 12:17:34.971085 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4465 12:17:34.974530 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4466 12:17:34.977729 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4467 12:17:34.984170 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4468 12:17:34.987262 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4469 12:17:34.990908 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4470 12:17:34.994245 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4471 12:17:34.997270 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4472 12:17:35.004585 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4473 12:17:35.008479 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4474 12:17:35.010829 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4475 12:17:35.014362 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4476 12:17:35.020634 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4477 12:17:35.024041 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4478 12:17:35.027331 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4479 12:17:35.027429 ==
4480 12:17:35.030894 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 12:17:35.034172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 12:17:35.037684 ==
4483 12:17:35.037757 DQS Delay:
4484 12:17:35.037818 DQS0 = 0, DQS1 = 0
4485 12:17:35.040959 DQM Delay:
4486 12:17:35.041029 DQM0 = 50, DQM1 = 45
4487 12:17:35.043982 DQ Delay:
4488 12:17:35.044056 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4489 12:17:35.046972 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4490 12:17:35.050996 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4491 12:17:35.054032 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4492 12:17:35.054103
4493 12:17:35.057631
4494 12:17:35.057732 ==
4495 12:17:35.060681 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 12:17:35.063922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 12:17:35.064005 ==
4498 12:17:35.064092
4499 12:17:35.064174
4500 12:17:35.067569 TX Vref Scan disable
4501 12:17:35.067642 == TX Byte 0 ==
4502 12:17:35.073994 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4503 12:17:35.077296 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4504 12:17:35.077376 == TX Byte 1 ==
4505 12:17:35.083758 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4506 12:17:35.087296 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4507 12:17:35.087387 ==
4508 12:17:35.090311 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 12:17:35.093868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 12:17:35.093945 ==
4511 12:17:35.094007
4512 12:17:35.094082
4513 12:17:35.097353 TX Vref Scan disable
4514 12:17:35.100599 == TX Byte 0 ==
4515 12:17:35.103781 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4516 12:17:35.107069 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4517 12:17:35.110316 == TX Byte 1 ==
4518 12:17:35.114159 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4519 12:17:35.117384 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4520 12:17:35.117459
4521 12:17:35.120639 [DATLAT]
4522 12:17:35.120714 Freq=600, CH1 RK0
4523 12:17:35.120775
4524 12:17:35.123535 DATLAT Default: 0x9
4525 12:17:35.123610 0, 0xFFFF, sum = 0
4526 12:17:35.126904 1, 0xFFFF, sum = 0
4527 12:17:35.127006 2, 0xFFFF, sum = 0
4528 12:17:35.130743 3, 0xFFFF, sum = 0
4529 12:17:35.130845 4, 0xFFFF, sum = 0
4530 12:17:35.133843 5, 0xFFFF, sum = 0
4531 12:17:35.133921 6, 0xFFFF, sum = 0
4532 12:17:35.136898 7, 0xFFFF, sum = 0
4533 12:17:35.136994 8, 0x0, sum = 1
4534 12:17:35.140709 9, 0x0, sum = 2
4535 12:17:35.140783 10, 0x0, sum = 3
4536 12:17:35.143402 11, 0x0, sum = 4
4537 12:17:35.143475 best_step = 9
4538 12:17:35.143535
4539 12:17:35.143595 ==
4540 12:17:35.147149 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 12:17:35.150183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 12:17:35.153903 ==
4543 12:17:35.153974 RX Vref Scan: 1
4544 12:17:35.154033
4545 12:17:35.156705 RX Vref 0 -> 0, step: 1
4546 12:17:35.156804
4547 12:17:35.160000 RX Delay -163 -> 252, step: 8
4548 12:17:35.160097
4549 12:17:35.163991 Set Vref, RX VrefLevel [Byte0]: 53
4550 12:17:35.167440 [Byte1]: 51
4551 12:17:35.167518
4552 12:17:35.170446 Final RX Vref Byte 0 = 53 to rank0
4553 12:17:35.173864 Final RX Vref Byte 1 = 51 to rank0
4554 12:17:35.176772 Final RX Vref Byte 0 = 53 to rank1
4555 12:17:35.180469 Final RX Vref Byte 1 = 51 to rank1==
4556 12:17:35.183661 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 12:17:35.186911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 12:17:35.186985 ==
4559 12:17:35.187050 DQS Delay:
4560 12:17:35.189992 DQS0 = 0, DQS1 = 0
4561 12:17:35.190064 DQM Delay:
4562 12:17:35.193396 DQM0 = 48, DQM1 = 45
4563 12:17:35.193493 DQ Delay:
4564 12:17:35.197158 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4565 12:17:35.200082 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4566 12:17:35.203498 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4567 12:17:35.206641 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4568 12:17:35.206716
4569 12:17:35.206777
4570 12:17:35.216861 [DQSOSCAuto] RK0, (LSB)MR18= 0x4166, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
4571 12:17:35.216940 CH1 RK0: MR19=808, MR18=4166
4572 12:17:35.223243 CH1_RK0: MR19=0x808, MR18=0x4166, DQSOSC=390, MR23=63, INC=172, DEC=114
4573 12:17:35.223343
4574 12:17:35.226943 ----->DramcWriteLeveling(PI) begin...
4575 12:17:35.227047 ==
4576 12:17:35.229934 Dram Type= 6, Freq= 0, CH_1, rank 1
4577 12:17:35.236817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 12:17:35.236894 ==
4579 12:17:35.240029 Write leveling (Byte 0): 30 => 30
4580 12:17:35.243160 Write leveling (Byte 1): 33 => 33
4581 12:17:35.243260 DramcWriteLeveling(PI) end<-----
4582 12:17:35.243348
4583 12:17:35.246428 ==
4584 12:17:35.249663 Dram Type= 6, Freq= 0, CH_1, rank 1
4585 12:17:35.253499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 12:17:35.253573 ==
4587 12:17:35.256315 [Gating] SW mode calibration
4588 12:17:35.262867 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4589 12:17:35.266141 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4590 12:17:35.272963 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4591 12:17:35.276776 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4592 12:17:35.279754 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4593 12:17:35.286385 0 9 12 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
4594 12:17:35.289860 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4595 12:17:35.292938 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 12:17:35.299844 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 12:17:35.303271 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 12:17:35.306664 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 12:17:35.313168 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 12:17:35.316630 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 12:17:35.320055 0 10 12 | B1->B0 | 4141 3534 | 0 1 | (0 0) (0 0)
4602 12:17:35.326372 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 12:17:35.329483 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 12:17:35.333295 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 12:17:35.339568 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 12:17:35.343773 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 12:17:35.346746 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 12:17:35.349914 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4609 12:17:35.356377 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4610 12:17:35.359533 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 12:17:35.362834 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 12:17:35.369618 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 12:17:35.372634 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 12:17:35.376467 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 12:17:35.382911 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 12:17:35.386187 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 12:17:35.389710 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 12:17:35.396181 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 12:17:35.399834 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 12:17:35.403036 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 12:17:35.409607 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 12:17:35.412884 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 12:17:35.416232 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 12:17:35.423043 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 12:17:35.425949 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4626 12:17:35.429221 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4627 12:17:35.432804 Total UI for P1: 0, mck2ui 16
4628 12:17:35.436001 best dqsien dly found for B1: ( 0, 13, 12)
4629 12:17:35.442774 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4630 12:17:35.442878 Total UI for P1: 0, mck2ui 16
4631 12:17:35.445882 best dqsien dly found for B0: ( 0, 13, 14)
4632 12:17:35.453181 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4633 12:17:35.455984 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4634 12:17:35.456084
4635 12:17:35.459227 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4636 12:17:35.462969 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4637 12:17:35.466121 [Gating] SW calibration Done
4638 12:17:35.466224 ==
4639 12:17:35.469350 Dram Type= 6, Freq= 0, CH_1, rank 1
4640 12:17:35.473016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 12:17:35.473089 ==
4642 12:17:35.475961 RX Vref Scan: 0
4643 12:17:35.476055
4644 12:17:35.476151 RX Vref 0 -> 0, step: 1
4645 12:17:35.476237
4646 12:17:35.479624 RX Delay -230 -> 252, step: 16
4647 12:17:35.482856 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4648 12:17:35.489401 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4649 12:17:35.492460 iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288
4650 12:17:35.496358 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4651 12:17:35.499451 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4652 12:17:35.502648 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4653 12:17:35.509565 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4654 12:17:35.512590 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4655 12:17:35.515824 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4656 12:17:35.518959 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4657 12:17:35.525952 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4658 12:17:35.529022 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4659 12:17:35.532667 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4660 12:17:35.535978 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4661 12:17:35.542676 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4662 12:17:35.546053 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4663 12:17:35.546129 ==
4664 12:17:35.549123 Dram Type= 6, Freq= 0, CH_1, rank 1
4665 12:17:35.552151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4666 12:17:35.552248 ==
4667 12:17:35.555895 DQS Delay:
4668 12:17:35.556006 DQS0 = 0, DQS1 = 0
4669 12:17:35.556101 DQM Delay:
4670 12:17:35.559011 DQM0 = 51, DQM1 = 48
4671 12:17:35.559090 DQ Delay:
4672 12:17:35.562660 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4673 12:17:35.565838 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4674 12:17:35.569008 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =49
4675 12:17:35.572548 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4676 12:17:35.572627
4677 12:17:35.572689
4678 12:17:35.572747 ==
4679 12:17:35.575680 Dram Type= 6, Freq= 0, CH_1, rank 1
4680 12:17:35.582466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4681 12:17:35.582546 ==
4682 12:17:35.582610
4683 12:17:35.582667
4684 12:17:35.582722 TX Vref Scan disable
4685 12:17:35.586055 == TX Byte 0 ==
4686 12:17:35.589262 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4687 12:17:35.596310 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4688 12:17:35.596403 == TX Byte 1 ==
4689 12:17:35.599426 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4690 12:17:35.606175 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4691 12:17:35.606255 ==
4692 12:17:35.609468 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 12:17:35.612949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 12:17:35.613029 ==
4695 12:17:35.613093
4696 12:17:35.613150
4697 12:17:35.615645 TX Vref Scan disable
4698 12:17:35.618949 == TX Byte 0 ==
4699 12:17:35.622677 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4700 12:17:35.625962 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4701 12:17:35.629026 == TX Byte 1 ==
4702 12:17:35.632166 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4703 12:17:35.635705 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4704 12:17:35.635785
4705 12:17:35.635848 [DATLAT]
4706 12:17:35.639372 Freq=600, CH1 RK1
4707 12:17:35.639452
4708 12:17:35.639522 DATLAT Default: 0x9
4709 12:17:35.642246 0, 0xFFFF, sum = 0
4710 12:17:35.646108 1, 0xFFFF, sum = 0
4711 12:17:35.646215 2, 0xFFFF, sum = 0
4712 12:17:35.649216 3, 0xFFFF, sum = 0
4713 12:17:35.649297 4, 0xFFFF, sum = 0
4714 12:17:35.652512 5, 0xFFFF, sum = 0
4715 12:17:35.652593 6, 0xFFFF, sum = 0
4716 12:17:35.655565 7, 0xFFFF, sum = 0
4717 12:17:35.655649 8, 0x0, sum = 1
4718 12:17:35.658742 9, 0x0, sum = 2
4719 12:17:35.658823 10, 0x0, sum = 3
4720 12:17:35.658888 11, 0x0, sum = 4
4721 12:17:35.662016 best_step = 9
4722 12:17:35.662103
4723 12:17:35.662179 ==
4724 12:17:35.665744 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 12:17:35.668759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 12:17:35.668839 ==
4727 12:17:35.672424 RX Vref Scan: 0
4728 12:17:35.672503
4729 12:17:35.672566 RX Vref 0 -> 0, step: 1
4730 12:17:35.675260
4731 12:17:35.675366 RX Delay -163 -> 252, step: 8
4732 12:17:35.683701 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4733 12:17:35.686423 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4734 12:17:35.689680 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4735 12:17:35.692965 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4736 12:17:35.699538 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4737 12:17:35.702894 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4738 12:17:35.706333 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4739 12:17:35.709582 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4740 12:17:35.712687 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4741 12:17:35.719231 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4742 12:17:35.722308 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4743 12:17:35.725982 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4744 12:17:35.729167 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4745 12:17:35.732294 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4746 12:17:35.739104 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4747 12:17:35.742327 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4748 12:17:35.742407 ==
4749 12:17:35.745898 Dram Type= 6, Freq= 0, CH_1, rank 1
4750 12:17:35.748886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4751 12:17:35.748981 ==
4752 12:17:35.752774 DQS Delay:
4753 12:17:35.752873 DQS0 = 0, DQS1 = 0
4754 12:17:35.752965 DQM Delay:
4755 12:17:35.755725 DQM0 = 48, DQM1 = 45
4756 12:17:35.755804 DQ Delay:
4757 12:17:35.758768 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4758 12:17:35.762683 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4759 12:17:35.765775 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4760 12:17:35.768858 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4761 12:17:35.768938
4762 12:17:35.769001
4763 12:17:35.779216 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4764 12:17:35.782528 CH1 RK1: MR19=808, MR18=6B23
4765 12:17:35.785572 CH1_RK1: MR19=0x808, MR18=0x6B23, DQSOSC=389, MR23=63, INC=173, DEC=115
4766 12:17:35.788900 [RxdqsGatingPostProcess] freq 600
4767 12:17:35.795355 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4768 12:17:35.798969 Pre-setting of DQS Precalculation
4769 12:17:35.802212 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4770 12:17:35.811944 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4771 12:17:35.818613 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4772 12:17:35.818693
4773 12:17:35.818756
4774 12:17:35.821754 [Calibration Summary] 1200 Mbps
4775 12:17:35.821834 CH 0, Rank 0
4776 12:17:35.824916 SW Impedance : PASS
4777 12:17:35.824996 DUTY Scan : NO K
4778 12:17:35.828390 ZQ Calibration : PASS
4779 12:17:35.831934 Jitter Meter : NO K
4780 12:17:35.832044 CBT Training : PASS
4781 12:17:35.835148 Write leveling : PASS
4782 12:17:35.838603 RX DQS gating : PASS
4783 12:17:35.838683 RX DQ/DQS(RDDQC) : PASS
4784 12:17:35.841801 TX DQ/DQS : PASS
4785 12:17:35.844575 RX DATLAT : PASS
4786 12:17:35.844696 RX DQ/DQS(Engine): PASS
4787 12:17:35.848242 TX OE : NO K
4788 12:17:35.848384 All Pass.
4789 12:17:35.848475
4790 12:17:35.851242 CH 0, Rank 1
4791 12:17:35.851322 SW Impedance : PASS
4792 12:17:35.854734 DUTY Scan : NO K
4793 12:17:35.858008 ZQ Calibration : PASS
4794 12:17:35.858087 Jitter Meter : NO K
4795 12:17:35.861372 CBT Training : PASS
4796 12:17:35.864396 Write leveling : PASS
4797 12:17:35.864475 RX DQS gating : PASS
4798 12:17:35.868206 RX DQ/DQS(RDDQC) : PASS
4799 12:17:35.871467 TX DQ/DQS : PASS
4800 12:17:35.871561 RX DATLAT : PASS
4801 12:17:35.874443 RX DQ/DQS(Engine): PASS
4802 12:17:35.874522 TX OE : NO K
4803 12:17:35.878230 All Pass.
4804 12:17:35.878309
4805 12:17:35.878371 CH 1, Rank 0
4806 12:17:35.881360 SW Impedance : PASS
4807 12:17:35.881438 DUTY Scan : NO K
4808 12:17:35.884502 ZQ Calibration : PASS
4809 12:17:35.887523 Jitter Meter : NO K
4810 12:17:35.887602 CBT Training : PASS
4811 12:17:35.891325 Write leveling : PASS
4812 12:17:35.894676 RX DQS gating : PASS
4813 12:17:35.894756 RX DQ/DQS(RDDQC) : PASS
4814 12:17:35.897621 TX DQ/DQS : PASS
4815 12:17:35.900927 RX DATLAT : PASS
4816 12:17:35.901008 RX DQ/DQS(Engine): PASS
4817 12:17:35.904436 TX OE : NO K
4818 12:17:35.904517 All Pass.
4819 12:17:35.904582
4820 12:17:35.907672 CH 1, Rank 1
4821 12:17:35.907753 SW Impedance : PASS
4822 12:17:35.911025 DUTY Scan : NO K
4823 12:17:35.914198 ZQ Calibration : PASS
4824 12:17:35.914278 Jitter Meter : NO K
4825 12:17:35.917642 CBT Training : PASS
4826 12:17:35.921170 Write leveling : PASS
4827 12:17:35.921251 RX DQS gating : PASS
4828 12:17:35.924327 RX DQ/DQS(RDDQC) : PASS
4829 12:17:35.927954 TX DQ/DQS : PASS
4830 12:17:35.928035 RX DATLAT : PASS
4831 12:17:35.931008 RX DQ/DQS(Engine): PASS
4832 12:17:35.931089 TX OE : NO K
4833 12:17:35.934268 All Pass.
4834 12:17:35.934351
4835 12:17:35.934416 DramC Write-DBI off
4836 12:17:35.937457 PER_BANK_REFRESH: Hybrid Mode
4837 12:17:35.940647 TX_TRACKING: ON
4838 12:17:35.947206 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4839 12:17:35.950879 [FAST_K] Save calibration result to emmc
4840 12:17:35.957229 dramc_set_vcore_voltage set vcore to 662500
4841 12:17:35.957310 Read voltage for 933, 3
4842 12:17:35.957375 Vio18 = 0
4843 12:17:35.960595 Vcore = 662500
4844 12:17:35.960676 Vdram = 0
4845 12:17:35.960741 Vddq = 0
4846 12:17:35.963966 Vmddr = 0
4847 12:17:35.967681 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4848 12:17:35.974415 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4849 12:17:35.974496 MEM_TYPE=3, freq_sel=17
4850 12:17:35.977461 sv_algorithm_assistance_LP4_1600
4851 12:17:35.984145 ============ PULL DRAM RESETB DOWN ============
4852 12:17:35.987225 ========== PULL DRAM RESETB DOWN end =========
4853 12:17:35.990517 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4854 12:17:35.994005 ===================================
4855 12:17:35.997032 LPDDR4 DRAM CONFIGURATION
4856 12:17:36.000440 ===================================
4857 12:17:36.004207 EX_ROW_EN[0] = 0x0
4858 12:17:36.004312 EX_ROW_EN[1] = 0x0
4859 12:17:36.006917 LP4Y_EN = 0x0
4860 12:17:36.007001 WORK_FSP = 0x0
4861 12:17:36.010884 WL = 0x3
4862 12:17:36.010969 RL = 0x3
4863 12:17:36.014218 BL = 0x2
4864 12:17:36.014304 RPST = 0x0
4865 12:17:36.017271 RD_PRE = 0x0
4866 12:17:36.017371 WR_PRE = 0x1
4867 12:17:36.020580 WR_PST = 0x0
4868 12:17:36.020664 DBI_WR = 0x0
4869 12:17:36.024136 DBI_RD = 0x0
4870 12:17:36.024228 OTF = 0x1
4871 12:17:36.027370 ===================================
4872 12:17:36.030400 ===================================
4873 12:17:36.033958 ANA top config
4874 12:17:36.037141 ===================================
4875 12:17:36.040320 DLL_ASYNC_EN = 0
4876 12:17:36.040416 ALL_SLAVE_EN = 1
4877 12:17:36.043602 NEW_RANK_MODE = 1
4878 12:17:36.047441 DLL_IDLE_MODE = 1
4879 12:17:36.050651 LP45_APHY_COMB_EN = 1
4880 12:17:36.050767 TX_ODT_DIS = 1
4881 12:17:36.053705 NEW_8X_MODE = 1
4882 12:17:36.057220 ===================================
4883 12:17:36.060829 ===================================
4884 12:17:36.063966 data_rate = 1866
4885 12:17:36.067358 CKR = 1
4886 12:17:36.070471 DQ_P2S_RATIO = 8
4887 12:17:36.073507 ===================================
4888 12:17:36.077354 CA_P2S_RATIO = 8
4889 12:17:36.077469 DQ_CA_OPEN = 0
4890 12:17:36.080217 DQ_SEMI_OPEN = 0
4891 12:17:36.084097 CA_SEMI_OPEN = 0
4892 12:17:36.086943 CA_FULL_RATE = 0
4893 12:17:36.090364 DQ_CKDIV4_EN = 1
4894 12:17:36.093886 CA_CKDIV4_EN = 1
4895 12:17:36.093968 CA_PREDIV_EN = 0
4896 12:17:36.096945 PH8_DLY = 0
4897 12:17:36.100426 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4898 12:17:36.104009 DQ_AAMCK_DIV = 4
4899 12:17:36.107018 CA_AAMCK_DIV = 4
4900 12:17:36.110063 CA_ADMCK_DIV = 4
4901 12:17:36.110145 DQ_TRACK_CA_EN = 0
4902 12:17:36.113929 CA_PICK = 933
4903 12:17:36.117023 CA_MCKIO = 933
4904 12:17:36.120444 MCKIO_SEMI = 0
4905 12:17:36.123526 PLL_FREQ = 3732
4906 12:17:36.126737 DQ_UI_PI_RATIO = 32
4907 12:17:36.130348 CA_UI_PI_RATIO = 0
4908 12:17:36.133414 ===================================
4909 12:17:36.137140 ===================================
4910 12:17:36.137222 memory_type:LPDDR4
4911 12:17:36.140200 GP_NUM : 10
4912 12:17:36.140338 SRAM_EN : 1
4913 12:17:36.143725 MD32_EN : 0
4914 12:17:36.146734 ===================================
4915 12:17:36.150093 [ANA_INIT] >>>>>>>>>>>>>>
4916 12:17:36.153349 <<<<<< [CONFIGURE PHASE]: ANA_TX
4917 12:17:36.156754 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4918 12:17:36.160021 ===================================
4919 12:17:36.163667 data_rate = 1866,PCW = 0X8f00
4920 12:17:36.166614 ===================================
4921 12:17:36.169939 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4922 12:17:36.173567 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4923 12:17:36.180105 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4924 12:17:36.183377 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4925 12:17:36.186458 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4926 12:17:36.190384 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4927 12:17:36.193366 [ANA_INIT] flow start
4928 12:17:36.196922 [ANA_INIT] PLL >>>>>>>>
4929 12:17:36.197029 [ANA_INIT] PLL <<<<<<<<
4930 12:17:36.199669 [ANA_INIT] MIDPI >>>>>>>>
4931 12:17:36.203316 [ANA_INIT] MIDPI <<<<<<<<
4932 12:17:36.203397 [ANA_INIT] DLL >>>>>>>>
4933 12:17:36.206590 [ANA_INIT] flow end
4934 12:17:36.210063 ============ LP4 DIFF to SE enter ============
4935 12:17:36.213365 ============ LP4 DIFF to SE exit ============
4936 12:17:36.216356 [ANA_INIT] <<<<<<<<<<<<<
4937 12:17:36.220025 [Flow] Enable top DCM control >>>>>
4938 12:17:36.223113 [Flow] Enable top DCM control <<<<<
4939 12:17:36.226796 Enable DLL master slave shuffle
4940 12:17:36.233594 ==============================================================
4941 12:17:36.233676 Gating Mode config
4942 12:17:36.240318 ==============================================================
4943 12:17:36.240414 Config description:
4944 12:17:36.250163 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4945 12:17:36.256792 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4946 12:17:36.263211 SELPH_MODE 0: By rank 1: By Phase
4947 12:17:36.266314 ==============================================================
4948 12:17:36.270054 GAT_TRACK_EN = 1
4949 12:17:36.273448 RX_GATING_MODE = 2
4950 12:17:36.276232 RX_GATING_TRACK_MODE = 2
4951 12:17:36.280075 SELPH_MODE = 1
4952 12:17:36.283266 PICG_EARLY_EN = 1
4953 12:17:36.286376 VALID_LAT_VALUE = 1
4954 12:17:36.293045 ==============================================================
4955 12:17:36.296405 Enter into Gating configuration >>>>
4956 12:17:36.299584 Exit from Gating configuration <<<<
4957 12:17:36.303243 Enter into DVFS_PRE_config >>>>>
4958 12:17:36.312619 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4959 12:17:36.316187 Exit from DVFS_PRE_config <<<<<
4960 12:17:36.319501 Enter into PICG configuration >>>>
4961 12:17:36.323103 Exit from PICG configuration <<<<
4962 12:17:36.326191 [RX_INPUT] configuration >>>>>
4963 12:17:36.326273 [RX_INPUT] configuration <<<<<
4964 12:17:36.332510 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4965 12:17:36.339387 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4966 12:17:36.342468 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4967 12:17:36.349472 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4968 12:17:36.356272 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4969 12:17:36.362595 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4970 12:17:36.366226 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4971 12:17:36.369254 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4972 12:17:36.376204 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4973 12:17:36.379357 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4974 12:17:36.382664 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4975 12:17:36.389159 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4976 12:17:36.392197 ===================================
4977 12:17:36.392339 LPDDR4 DRAM CONFIGURATION
4978 12:17:36.396157 ===================================
4979 12:17:36.399207 EX_ROW_EN[0] = 0x0
4980 12:17:36.399306 EX_ROW_EN[1] = 0x0
4981 12:17:36.402616 LP4Y_EN = 0x0
4982 12:17:36.402712 WORK_FSP = 0x0
4983 12:17:36.405755 WL = 0x3
4984 12:17:36.405834 RL = 0x3
4985 12:17:36.409115 BL = 0x2
4986 12:17:36.412220 RPST = 0x0
4987 12:17:36.412328 RD_PRE = 0x0
4988 12:17:36.415546 WR_PRE = 0x1
4989 12:17:36.415625 WR_PST = 0x0
4990 12:17:36.419165 DBI_WR = 0x0
4991 12:17:36.419245 DBI_RD = 0x0
4992 12:17:36.422222 OTF = 0x1
4993 12:17:36.426015 ===================================
4994 12:17:36.429113 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4995 12:17:36.432184 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4996 12:17:36.435724 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4997 12:17:36.438952 ===================================
4998 12:17:36.441992 LPDDR4 DRAM CONFIGURATION
4999 12:17:36.445781 ===================================
5000 12:17:36.448864 EX_ROW_EN[0] = 0x10
5001 12:17:36.448946 EX_ROW_EN[1] = 0x0
5002 12:17:36.452925 LP4Y_EN = 0x0
5003 12:17:36.453006 WORK_FSP = 0x0
5004 12:17:36.455357 WL = 0x3
5005 12:17:36.455438 RL = 0x3
5006 12:17:36.459066 BL = 0x2
5007 12:17:36.459147 RPST = 0x0
5008 12:17:36.462405 RD_PRE = 0x0
5009 12:17:36.462486 WR_PRE = 0x1
5010 12:17:36.465522 WR_PST = 0x0
5011 12:17:36.468982 DBI_WR = 0x0
5012 12:17:36.469063 DBI_RD = 0x0
5013 12:17:36.471964 OTF = 0x1
5014 12:17:36.475607 ===================================
5015 12:17:36.478907 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5016 12:17:36.483852 nWR fixed to 30
5017 12:17:36.487493 [ModeRegInit_LP4] CH0 RK0
5018 12:17:36.487573 [ModeRegInit_LP4] CH0 RK1
5019 12:17:36.490478 [ModeRegInit_LP4] CH1 RK0
5020 12:17:36.494028 [ModeRegInit_LP4] CH1 RK1
5021 12:17:36.494109 match AC timing 9
5022 12:17:36.500463 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5023 12:17:36.504278 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5024 12:17:36.507611 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5025 12:17:36.514050 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5026 12:17:36.517155 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5027 12:17:36.517237 ==
5028 12:17:36.520528 Dram Type= 6, Freq= 0, CH_0, rank 0
5029 12:17:36.524271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5030 12:17:36.524391 ==
5031 12:17:36.530837 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5032 12:17:36.536939 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5033 12:17:36.540544 [CA 0] Center 37 (6~68) winsize 63
5034 12:17:36.544097 [CA 1] Center 37 (7~68) winsize 62
5035 12:17:36.547045 [CA 2] Center 34 (4~65) winsize 62
5036 12:17:36.550335 [CA 3] Center 34 (3~65) winsize 63
5037 12:17:36.554076 [CA 4] Center 33 (3~64) winsize 62
5038 12:17:36.556963 [CA 5] Center 32 (2~62) winsize 61
5039 12:17:36.557044
5040 12:17:36.560727 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5041 12:17:36.560808
5042 12:17:36.563919 [CATrainingPosCal] consider 1 rank data
5043 12:17:36.567151 u2DelayCellTimex100 = 270/100 ps
5044 12:17:36.570419 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5045 12:17:36.573945 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5046 12:17:36.577062 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5047 12:17:36.580486 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5048 12:17:36.583755 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5049 12:17:36.587032 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5050 12:17:36.590467
5051 12:17:36.593657 CA PerBit enable=1, Macro0, CA PI delay=32
5052 12:17:36.593760
5053 12:17:36.597135 [CBTSetCACLKResult] CA Dly = 32
5054 12:17:36.597212 CS Dly: 5 (0~36)
5055 12:17:36.597275 ==
5056 12:17:36.599991 Dram Type= 6, Freq= 0, CH_0, rank 1
5057 12:17:36.603468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5058 12:17:36.603545 ==
5059 12:17:36.610090 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5060 12:17:36.616727 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5061 12:17:36.620033 [CA 0] Center 37 (6~68) winsize 63
5062 12:17:36.623333 [CA 1] Center 37 (7~68) winsize 62
5063 12:17:36.626576 [CA 2] Center 34 (4~65) winsize 62
5064 12:17:36.630373 [CA 3] Center 34 (3~65) winsize 63
5065 12:17:36.633700 [CA 4] Center 33 (3~63) winsize 61
5066 12:17:36.636555 [CA 5] Center 32 (2~62) winsize 61
5067 12:17:36.636630
5068 12:17:36.640243 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5069 12:17:36.640349
5070 12:17:36.643608 [CATrainingPosCal] consider 2 rank data
5071 12:17:36.646794 u2DelayCellTimex100 = 270/100 ps
5072 12:17:36.650138 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5073 12:17:36.653368 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5074 12:17:36.656988 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5075 12:17:36.659876 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5076 12:17:36.663362 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5077 12:17:36.670196 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5078 12:17:36.670270
5079 12:17:36.673521 CA PerBit enable=1, Macro0, CA PI delay=32
5080 12:17:36.673617
5081 12:17:36.676660 [CBTSetCACLKResult] CA Dly = 32
5082 12:17:36.676728 CS Dly: 5 (0~37)
5083 12:17:36.676789
5084 12:17:36.679748 ----->DramcWriteLeveling(PI) begin...
5085 12:17:36.679846 ==
5086 12:17:36.683529 Dram Type= 6, Freq= 0, CH_0, rank 0
5087 12:17:36.689718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 12:17:36.689794 ==
5089 12:17:36.693436 Write leveling (Byte 0): 32 => 32
5090 12:17:36.693506 Write leveling (Byte 1): 32 => 32
5091 12:17:36.696644 DramcWriteLeveling(PI) end<-----
5092 12:17:36.696738
5093 12:17:36.696825 ==
5094 12:17:36.699880 Dram Type= 6, Freq= 0, CH_0, rank 0
5095 12:17:36.706575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5096 12:17:36.706676 ==
5097 12:17:36.709956 [Gating] SW mode calibration
5098 12:17:36.716452 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5099 12:17:36.719682 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5100 12:17:36.726711 0 14 0 | B1->B0 | 2929 3434 | 1 1 | (0 0) (1 1)
5101 12:17:36.729906 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 12:17:36.733385 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 12:17:36.740209 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 12:17:36.743362 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 12:17:36.746303 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 12:17:36.750030 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5107 12:17:36.756886 0 14 28 | B1->B0 | 3333 2727 | 1 0 | (1 1) (1 0)
5108 12:17:36.760088 0 15 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
5109 12:17:36.762930 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 12:17:36.769736 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 12:17:36.773112 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 12:17:36.776230 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 12:17:36.783176 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 12:17:36.786414 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5115 12:17:36.789549 0 15 28 | B1->B0 | 2727 3838 | 0 0 | (0 0) (0 0)
5116 12:17:36.796066 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5117 12:17:36.799526 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 12:17:36.802943 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 12:17:36.809326 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 12:17:36.813203 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 12:17:36.816346 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 12:17:36.823169 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5123 12:17:36.826095 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5124 12:17:36.829805 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5125 12:17:36.836437 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 12:17:36.839331 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 12:17:36.843076 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 12:17:36.849397 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 12:17:36.852741 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 12:17:36.856135 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 12:17:36.862792 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 12:17:36.866574 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 12:17:36.869541 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 12:17:36.876411 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 12:17:36.879312 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 12:17:36.882792 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 12:17:36.889723 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 12:17:36.893036 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5139 12:17:36.896158 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5140 12:17:36.899236 Total UI for P1: 0, mck2ui 16
5141 12:17:36.903170 best dqsien dly found for B0: ( 1, 2, 24)
5142 12:17:36.906049 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5143 12:17:36.912988 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 12:17:36.916189 Total UI for P1: 0, mck2ui 16
5145 12:17:36.919411 best dqsien dly found for B1: ( 1, 3, 0)
5146 12:17:36.922511 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5147 12:17:36.926255 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5148 12:17:36.926358
5149 12:17:36.929346 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5150 12:17:36.932396 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5151 12:17:36.936192 [Gating] SW calibration Done
5152 12:17:36.936322 ==
5153 12:17:36.939357 Dram Type= 6, Freq= 0, CH_0, rank 0
5154 12:17:36.942287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5155 12:17:36.942369 ==
5156 12:17:36.946185 RX Vref Scan: 0
5157 12:17:36.946269
5158 12:17:36.946374 RX Vref 0 -> 0, step: 1
5159 12:17:36.946452
5160 12:17:36.949295 RX Delay -80 -> 252, step: 8
5161 12:17:36.952257 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5162 12:17:36.959266 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5163 12:17:36.962611 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5164 12:17:36.966061 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5165 12:17:36.969369 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5166 12:17:36.972501 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5167 12:17:36.975749 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5168 12:17:36.982734 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5169 12:17:36.985482 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5170 12:17:36.989381 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5171 12:17:36.992712 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5172 12:17:36.995765 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5173 12:17:36.999051 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5174 12:17:37.006282 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5175 12:17:37.009038 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5176 12:17:37.012513 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5177 12:17:37.012593 ==
5178 12:17:37.015773 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 12:17:37.019052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 12:17:37.019134 ==
5181 12:17:37.022198 DQS Delay:
5182 12:17:37.022279 DQS0 = 0, DQS1 = 0
5183 12:17:37.025516 DQM Delay:
5184 12:17:37.025597 DQM0 = 104, DQM1 = 94
5185 12:17:37.029182 DQ Delay:
5186 12:17:37.032317 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5187 12:17:37.035472 DQ4 =103, DQ5 =99, DQ6 =111, DQ7 =115
5188 12:17:37.035554 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5189 12:17:37.042163 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5190 12:17:37.042245
5191 12:17:37.042310
5192 12:17:37.042390 ==
5193 12:17:37.045680 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 12:17:37.048974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 12:17:37.049056 ==
5196 12:17:37.049120
5197 12:17:37.049179
5198 12:17:37.052202 TX Vref Scan disable
5199 12:17:37.052306 == TX Byte 0 ==
5200 12:17:37.059413 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5201 12:17:37.062127 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5202 12:17:37.062208 == TX Byte 1 ==
5203 12:17:37.068887 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5204 12:17:37.072316 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5205 12:17:37.072427 ==
5206 12:17:37.075910 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 12:17:37.078747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 12:17:37.078828 ==
5209 12:17:37.078892
5210 12:17:37.078951
5211 12:17:37.082048 TX Vref Scan disable
5212 12:17:37.085803 == TX Byte 0 ==
5213 12:17:37.088734 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5214 12:17:37.092470 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5215 12:17:37.095918 == TX Byte 1 ==
5216 12:17:37.098990 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5217 12:17:37.101877 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5218 12:17:37.101958
5219 12:17:37.105791 [DATLAT]
5220 12:17:37.105872 Freq=933, CH0 RK0
5221 12:17:37.105937
5222 12:17:37.108782 DATLAT Default: 0xd
5223 12:17:37.108863 0, 0xFFFF, sum = 0
5224 12:17:37.112487 1, 0xFFFF, sum = 0
5225 12:17:37.112570 2, 0xFFFF, sum = 0
5226 12:17:37.115299 3, 0xFFFF, sum = 0
5227 12:17:37.115420 4, 0xFFFF, sum = 0
5228 12:17:37.119019 5, 0xFFFF, sum = 0
5229 12:17:37.119101 6, 0xFFFF, sum = 0
5230 12:17:37.122014 7, 0xFFFF, sum = 0
5231 12:17:37.122097 8, 0xFFFF, sum = 0
5232 12:17:37.125357 9, 0xFFFF, sum = 0
5233 12:17:37.125439 10, 0x0, sum = 1
5234 12:17:37.128411 11, 0x0, sum = 2
5235 12:17:37.128494 12, 0x0, sum = 3
5236 12:17:37.132105 13, 0x0, sum = 4
5237 12:17:37.132187 best_step = 11
5238 12:17:37.132251
5239 12:17:37.132347 ==
5240 12:17:37.135398 Dram Type= 6, Freq= 0, CH_0, rank 0
5241 12:17:37.141705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5242 12:17:37.141787 ==
5243 12:17:37.141851 RX Vref Scan: 1
5244 12:17:37.141912
5245 12:17:37.145437 RX Vref 0 -> 0, step: 1
5246 12:17:37.145519
5247 12:17:37.148260 RX Delay -53 -> 252, step: 4
5248 12:17:37.148386
5249 12:17:37.151982 Set Vref, RX VrefLevel [Byte0]: 56
5250 12:17:37.154977 [Byte1]: 47
5251 12:17:37.155058
5252 12:17:37.158887 Final RX Vref Byte 0 = 56 to rank0
5253 12:17:37.162102 Final RX Vref Byte 1 = 47 to rank0
5254 12:17:37.165230 Final RX Vref Byte 0 = 56 to rank1
5255 12:17:37.168740 Final RX Vref Byte 1 = 47 to rank1==
5256 12:17:37.171934 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 12:17:37.175243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 12:17:37.175324 ==
5259 12:17:37.178134 DQS Delay:
5260 12:17:37.178214 DQS0 = 0, DQS1 = 0
5261 12:17:37.181787 DQM Delay:
5262 12:17:37.181868 DQM0 = 104, DQM1 = 94
5263 12:17:37.181932 DQ Delay:
5264 12:17:37.185105 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5265 12:17:37.188763 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5266 12:17:37.191447 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =88
5267 12:17:37.198298 DQ12 =100, DQ13 =98, DQ14 =106, DQ15 =102
5268 12:17:37.198379
5269 12:17:37.198443
5270 12:17:37.204694 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d25, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 407 ps
5271 12:17:37.208515 CH0 RK0: MR19=505, MR18=2D25
5272 12:17:37.214998 CH0_RK0: MR19=0x505, MR18=0x2D25, DQSOSC=407, MR23=63, INC=65, DEC=43
5273 12:17:37.215080
5274 12:17:37.218333 ----->DramcWriteLeveling(PI) begin...
5275 12:17:37.218415 ==
5276 12:17:37.221504 Dram Type= 6, Freq= 0, CH_0, rank 1
5277 12:17:37.224800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 12:17:37.224885 ==
5279 12:17:37.228090 Write leveling (Byte 0): 34 => 34
5280 12:17:37.231498 Write leveling (Byte 1): 29 => 29
5281 12:17:37.234925 DramcWriteLeveling(PI) end<-----
5282 12:17:37.235007
5283 12:17:37.235071 ==
5284 12:17:37.238194 Dram Type= 6, Freq= 0, CH_0, rank 1
5285 12:17:37.241343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 12:17:37.241425 ==
5287 12:17:37.244538 [Gating] SW mode calibration
5288 12:17:37.251343 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5289 12:17:37.258242 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5290 12:17:37.261170 0 14 0 | B1->B0 | 3232 3131 | 0 0 | (0 0) (0 0)
5291 12:17:37.265127 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 12:17:37.271811 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 12:17:37.274842 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 12:17:37.278035 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 12:17:37.285208 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 12:17:37.288097 0 14 24 | B1->B0 | 3333 3232 | 1 0 | (1 1) (0 0)
5297 12:17:37.291141 0 14 28 | B1->B0 | 2b2b 2d2d | 1 0 | (1 0) (0 0)
5298 12:17:37.298103 0 15 0 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5299 12:17:37.301120 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 12:17:37.304270 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 12:17:37.311243 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 12:17:37.314312 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 12:17:37.318078 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 12:17:37.324429 0 15 24 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
5305 12:17:37.328085 0 15 28 | B1->B0 | 3a3a 3939 | 0 0 | (0 0) (0 0)
5306 12:17:37.330994 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5307 12:17:37.337598 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 12:17:37.341132 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 12:17:37.344928 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 12:17:37.351412 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 12:17:37.354593 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 12:17:37.357756 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 12:17:37.364253 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5314 12:17:37.367311 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 12:17:37.370787 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 12:17:37.377155 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 12:17:37.380712 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 12:17:37.384246 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 12:17:37.390764 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 12:17:37.393975 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 12:17:37.397765 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 12:17:37.404110 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 12:17:37.407204 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 12:17:37.410788 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 12:17:37.417082 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 12:17:37.420282 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 12:17:37.424112 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 12:17:37.430504 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 12:17:37.433700 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5330 12:17:37.436957 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5331 12:17:37.440588 Total UI for P1: 0, mck2ui 16
5332 12:17:37.443667 best dqsien dly found for B0: ( 1, 2, 28)
5333 12:17:37.447308 Total UI for P1: 0, mck2ui 16
5334 12:17:37.450420 best dqsien dly found for B1: ( 1, 2, 28)
5335 12:17:37.453774 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5336 12:17:37.457275 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5337 12:17:37.457354
5338 12:17:37.460691 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5339 12:17:37.467018 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5340 12:17:37.467099 [Gating] SW calibration Done
5341 12:17:37.467162 ==
5342 12:17:37.470683 Dram Type= 6, Freq= 0, CH_0, rank 1
5343 12:17:37.476854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 12:17:37.476938 ==
5345 12:17:37.477003 RX Vref Scan: 0
5346 12:17:37.477062
5347 12:17:37.480707 RX Vref 0 -> 0, step: 1
5348 12:17:37.480787
5349 12:17:37.483890 RX Delay -80 -> 252, step: 8
5350 12:17:37.486906 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5351 12:17:37.490388 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5352 12:17:37.493650 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5353 12:17:37.496978 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5354 12:17:37.503711 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5355 12:17:37.506906 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5356 12:17:37.510857 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5357 12:17:37.513823 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5358 12:17:37.516837 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5359 12:17:37.520511 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5360 12:17:37.526721 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5361 12:17:37.530258 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5362 12:17:37.533740 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5363 12:17:37.536681 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5364 12:17:37.539936 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5365 12:17:37.543609 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5366 12:17:37.546654 ==
5367 12:17:37.550210 Dram Type= 6, Freq= 0, CH_0, rank 1
5368 12:17:37.553314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5369 12:17:37.553395 ==
5370 12:17:37.553460 DQS Delay:
5371 12:17:37.557289 DQS0 = 0, DQS1 = 0
5372 12:17:37.557370 DQM Delay:
5373 12:17:37.559830 DQM0 = 104, DQM1 = 94
5374 12:17:37.559910 DQ Delay:
5375 12:17:37.563228 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5376 12:17:37.567180 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5377 12:17:37.570027 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5378 12:17:37.573799 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99
5379 12:17:37.573880
5380 12:17:37.573944
5381 12:17:37.574003 ==
5382 12:17:37.576432 Dram Type= 6, Freq= 0, CH_0, rank 1
5383 12:17:37.580198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5384 12:17:37.583352 ==
5385 12:17:37.583434
5386 12:17:37.583497
5387 12:17:37.583556 TX Vref Scan disable
5388 12:17:37.586382 == TX Byte 0 ==
5389 12:17:37.590247 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5390 12:17:37.593494 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5391 12:17:37.596478 == TX Byte 1 ==
5392 12:17:37.599531 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5393 12:17:37.602853 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5394 12:17:37.606572 ==
5395 12:17:37.606654 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 12:17:37.613029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 12:17:37.613110 ==
5398 12:17:37.613174
5399 12:17:37.613233
5400 12:17:37.616779 TX Vref Scan disable
5401 12:17:37.616863 == TX Byte 0 ==
5402 12:17:37.623284 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5403 12:17:37.626147 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5404 12:17:37.626258 == TX Byte 1 ==
5405 12:17:37.633123 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5406 12:17:37.636194 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5407 12:17:37.636325
5408 12:17:37.636413 [DATLAT]
5409 12:17:37.639330 Freq=933, CH0 RK1
5410 12:17:37.639399
5411 12:17:37.639458 DATLAT Default: 0xb
5412 12:17:37.642979 0, 0xFFFF, sum = 0
5413 12:17:37.643055 1, 0xFFFF, sum = 0
5414 12:17:37.646092 2, 0xFFFF, sum = 0
5415 12:17:37.646174 3, 0xFFFF, sum = 0
5416 12:17:37.649284 4, 0xFFFF, sum = 0
5417 12:17:37.649362 5, 0xFFFF, sum = 0
5418 12:17:37.653125 6, 0xFFFF, sum = 0
5419 12:17:37.653195 7, 0xFFFF, sum = 0
5420 12:17:37.656022 8, 0xFFFF, sum = 0
5421 12:17:37.659811 9, 0xFFFF, sum = 0
5422 12:17:37.659890 10, 0x0, sum = 1
5423 12:17:37.659954 11, 0x0, sum = 2
5424 12:17:37.662945 12, 0x0, sum = 3
5425 12:17:37.663021 13, 0x0, sum = 4
5426 12:17:37.666118 best_step = 11
5427 12:17:37.666195
5428 12:17:37.666255 ==
5429 12:17:37.669836 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 12:17:37.672645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 12:17:37.672727 ==
5432 12:17:37.676467 RX Vref Scan: 0
5433 12:17:37.676544
5434 12:17:37.676612 RX Vref 0 -> 0, step: 1
5435 12:17:37.676674
5436 12:17:37.679538 RX Delay -45 -> 252, step: 4
5437 12:17:37.686369 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5438 12:17:37.689906 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5439 12:17:37.693065 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5440 12:17:37.696939 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5441 12:17:37.700448 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5442 12:17:37.706556 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5443 12:17:37.709715 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5444 12:17:37.713145 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5445 12:17:37.716300 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5446 12:17:37.719896 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5447 12:17:37.726627 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5448 12:17:37.729647 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5449 12:17:37.732915 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5450 12:17:37.736566 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5451 12:17:37.739941 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5452 12:17:37.746162 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5453 12:17:37.746243 ==
5454 12:17:37.749785 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 12:17:37.752763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 12:17:37.752844 ==
5457 12:17:37.752908 DQS Delay:
5458 12:17:37.756582 DQS0 = 0, DQS1 = 0
5459 12:17:37.756663 DQM Delay:
5460 12:17:37.759711 DQM0 = 104, DQM1 = 94
5461 12:17:37.759792 DQ Delay:
5462 12:17:37.762603 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =100
5463 12:17:37.766104 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5464 12:17:37.769314 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =88
5465 12:17:37.772608 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5466 12:17:37.772689
5467 12:17:37.772752
5468 12:17:37.782474 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5469 12:17:37.785995 CH0 RK1: MR19=505, MR18=2B04
5470 12:17:37.789060 CH0_RK1: MR19=0x505, MR18=0x2B04, DQSOSC=408, MR23=63, INC=65, DEC=43
5471 12:17:37.792727 [RxdqsGatingPostProcess] freq 933
5472 12:17:37.799282 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5473 12:17:37.802443 best DQS0 dly(2T, 0.5T) = (0, 10)
5474 12:17:37.805655 best DQS1 dly(2T, 0.5T) = (0, 11)
5475 12:17:37.809569 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5476 12:17:37.812795 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5477 12:17:37.816030 best DQS0 dly(2T, 0.5T) = (0, 10)
5478 12:17:37.819018 best DQS1 dly(2T, 0.5T) = (0, 10)
5479 12:17:37.822400 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5480 12:17:37.825487 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5481 12:17:37.829348 Pre-setting of DQS Precalculation
5482 12:17:37.832829 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5483 12:17:37.832898 ==
5484 12:17:37.835799 Dram Type= 6, Freq= 0, CH_1, rank 0
5485 12:17:37.839304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 12:17:37.839373 ==
5487 12:17:37.845740 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5488 12:17:37.852131 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5489 12:17:37.855399 [CA 0] Center 36 (6~67) winsize 62
5490 12:17:37.858993 [CA 1] Center 36 (6~67) winsize 62
5491 12:17:37.862656 [CA 2] Center 34 (4~65) winsize 62
5492 12:17:37.865401 [CA 3] Center 34 (4~65) winsize 62
5493 12:17:37.869222 [CA 4] Center 34 (4~64) winsize 61
5494 12:17:37.872126 [CA 5] Center 33 (3~64) winsize 62
5495 12:17:37.872195
5496 12:17:37.875635 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5497 12:17:37.875702
5498 12:17:37.878915 [CATrainingPosCal] consider 1 rank data
5499 12:17:37.882242 u2DelayCellTimex100 = 270/100 ps
5500 12:17:37.886255 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5501 12:17:37.889053 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5502 12:17:37.892132 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5503 12:17:37.895581 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5504 12:17:37.898862 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5505 12:17:37.901948 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5506 12:17:37.905899
5507 12:17:37.908815 CA PerBit enable=1, Macro0, CA PI delay=33
5508 12:17:37.908890
5509 12:17:37.912164 [CBTSetCACLKResult] CA Dly = 33
5510 12:17:37.912259 CS Dly: 6 (0~37)
5511 12:17:37.912338 ==
5512 12:17:37.915761 Dram Type= 6, Freq= 0, CH_1, rank 1
5513 12:17:37.919023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 12:17:37.919101 ==
5515 12:17:37.925458 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5516 12:17:37.932409 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5517 12:17:37.935551 [CA 0] Center 37 (6~68) winsize 63
5518 12:17:37.938777 [CA 1] Center 37 (6~68) winsize 63
5519 12:17:37.941650 [CA 2] Center 35 (4~66) winsize 63
5520 12:17:37.945700 [CA 3] Center 34 (4~65) winsize 62
5521 12:17:37.948709 [CA 4] Center 34 (4~65) winsize 62
5522 12:17:37.951844 [CA 5] Center 33 (3~64) winsize 62
5523 12:17:37.951921
5524 12:17:37.955326 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5525 12:17:37.955401
5526 12:17:37.958326 [CATrainingPosCal] consider 2 rank data
5527 12:17:37.961811 u2DelayCellTimex100 = 270/100 ps
5528 12:17:37.965440 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5529 12:17:37.968358 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5530 12:17:37.971851 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5531 12:17:37.975435 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5532 12:17:37.978607 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5533 12:17:37.984829 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5534 12:17:37.984904
5535 12:17:37.988247 CA PerBit enable=1, Macro0, CA PI delay=33
5536 12:17:37.988365
5537 12:17:37.991838 [CBTSetCACLKResult] CA Dly = 33
5538 12:17:37.991910 CS Dly: 7 (0~39)
5539 12:17:37.991970
5540 12:17:37.995078 ----->DramcWriteLeveling(PI) begin...
5541 12:17:37.995147 ==
5542 12:17:37.998154 Dram Type= 6, Freq= 0, CH_1, rank 0
5543 12:17:38.005166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 12:17:38.005239 ==
5545 12:17:38.008181 Write leveling (Byte 0): 24 => 24
5546 12:17:38.008283 Write leveling (Byte 1): 27 => 27
5547 12:17:38.011353 DramcWriteLeveling(PI) end<-----
5548 12:17:38.011429
5549 12:17:38.011488 ==
5550 12:17:38.014870 Dram Type= 6, Freq= 0, CH_1, rank 0
5551 12:17:38.021447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 12:17:38.021525 ==
5553 12:17:38.024951 [Gating] SW mode calibration
5554 12:17:38.031460 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5555 12:17:38.034723 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5556 12:17:38.041923 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 12:17:38.044897 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 12:17:38.048587 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 12:17:38.055099 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 12:17:38.058281 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 12:17:38.061248 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 12:17:38.068391 0 14 24 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 0)
5563 12:17:38.071503 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5564 12:17:38.074812 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 12:17:38.081467 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 12:17:38.084535 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 12:17:38.087995 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 12:17:38.091573 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 12:17:38.098190 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 12:17:38.101333 0 15 24 | B1->B0 | 2828 3535 | 0 0 | (0 0) (0 0)
5571 12:17:38.105042 0 15 28 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
5572 12:17:38.111243 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 12:17:38.114368 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 12:17:38.118017 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 12:17:38.124304 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 12:17:38.127882 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 12:17:38.131123 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 12:17:38.137971 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5579 12:17:38.141157 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5580 12:17:38.145114 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 12:17:38.151215 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 12:17:38.154921 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 12:17:38.158206 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 12:17:38.164532 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 12:17:38.167789 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 12:17:38.171381 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 12:17:38.177873 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 12:17:38.181118 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 12:17:38.184329 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 12:17:38.191579 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 12:17:38.194426 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 12:17:38.198139 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 12:17:38.204502 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 12:17:38.208163 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5595 12:17:38.211111 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5596 12:17:38.214171 Total UI for P1: 0, mck2ui 16
5597 12:17:38.217920 best dqsien dly found for B1: ( 1, 2, 24)
5598 12:17:38.221291 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5599 12:17:38.224262 Total UI for P1: 0, mck2ui 16
5600 12:17:38.227475 best dqsien dly found for B0: ( 1, 2, 28)
5601 12:17:38.230971 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5602 12:17:38.237271 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5603 12:17:38.237352
5604 12:17:38.241105 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5605 12:17:38.244412 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5606 12:17:38.247544 [Gating] SW calibration Done
5607 12:17:38.247625 ==
5608 12:17:38.250550 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 12:17:38.254015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 12:17:38.254096 ==
5611 12:17:38.257665 RX Vref Scan: 0
5612 12:17:38.257746
5613 12:17:38.257810 RX Vref 0 -> 0, step: 1
5614 12:17:38.257870
5615 12:17:38.260721 RX Delay -80 -> 252, step: 8
5616 12:17:38.263863 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5617 12:17:38.270324 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5618 12:17:38.274071 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5619 12:17:38.277197 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5620 12:17:38.280233 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5621 12:17:38.283629 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5622 12:17:38.287503 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5623 12:17:38.293475 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5624 12:17:38.296833 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5625 12:17:38.300530 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5626 12:17:38.303612 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5627 12:17:38.306719 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5628 12:17:38.310338 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5629 12:17:38.317142 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5630 12:17:38.320322 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5631 12:17:38.323586 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5632 12:17:38.323667 ==
5633 12:17:38.326848 Dram Type= 6, Freq= 0, CH_1, rank 0
5634 12:17:38.330423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5635 12:17:38.330508 ==
5636 12:17:38.333584 DQS Delay:
5637 12:17:38.333665 DQS0 = 0, DQS1 = 0
5638 12:17:38.336800 DQM Delay:
5639 12:17:38.336881 DQM0 = 102, DQM1 = 97
5640 12:17:38.336946 DQ Delay:
5641 12:17:38.340245 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5642 12:17:38.343721 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5643 12:17:38.346730 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5644 12:17:38.353417 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =103
5645 12:17:38.353499
5646 12:17:38.353563
5647 12:17:38.353622 ==
5648 12:17:38.356853 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 12:17:38.360007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 12:17:38.360088 ==
5651 12:17:38.360153
5652 12:17:38.360212
5653 12:17:38.363598 TX Vref Scan disable
5654 12:17:38.363679 == TX Byte 0 ==
5655 12:17:38.370290 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5656 12:17:38.373635 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5657 12:17:38.373716 == TX Byte 1 ==
5658 12:17:38.379890 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5659 12:17:38.383440 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5660 12:17:38.383521 ==
5661 12:17:38.386559 Dram Type= 6, Freq= 0, CH_1, rank 0
5662 12:17:38.395349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5663 12:17:38.395431 ==
5664 12:17:38.395495
5665 12:17:38.395555
5666 12:17:38.395612 TX Vref Scan disable
5667 12:17:38.396597 == TX Byte 0 ==
5668 12:17:38.400016 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5669 12:17:38.403600 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5670 12:17:38.406572 == TX Byte 1 ==
5671 12:17:38.409999 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5672 12:17:38.412953 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5673 12:17:38.413034
5674 12:17:38.416676 [DATLAT]
5675 12:17:38.416757 Freq=933, CH1 RK0
5676 12:17:38.416851
5677 12:17:38.419759 DATLAT Default: 0xd
5678 12:17:38.419839 0, 0xFFFF, sum = 0
5679 12:17:38.423056 1, 0xFFFF, sum = 0
5680 12:17:38.423138 2, 0xFFFF, sum = 0
5681 12:17:38.426983 3, 0xFFFF, sum = 0
5682 12:17:38.427065 4, 0xFFFF, sum = 0
5683 12:17:38.430060 5, 0xFFFF, sum = 0
5684 12:17:38.430142 6, 0xFFFF, sum = 0
5685 12:17:38.433237 7, 0xFFFF, sum = 0
5686 12:17:38.436260 8, 0xFFFF, sum = 0
5687 12:17:38.436369 9, 0xFFFF, sum = 0
5688 12:17:38.436435 10, 0x0, sum = 1
5689 12:17:38.439498 11, 0x0, sum = 2
5690 12:17:38.439596 12, 0x0, sum = 3
5691 12:17:38.443348 13, 0x0, sum = 4
5692 12:17:38.443431 best_step = 11
5693 12:17:38.443495
5694 12:17:38.443554 ==
5695 12:17:38.446368 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 12:17:38.453086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 12:17:38.453168 ==
5698 12:17:38.453232 RX Vref Scan: 1
5699 12:17:38.453291
5700 12:17:38.456412 RX Vref 0 -> 0, step: 1
5701 12:17:38.456493
5702 12:17:38.459467 RX Delay -45 -> 252, step: 4
5703 12:17:38.459547
5704 12:17:38.462754 Set Vref, RX VrefLevel [Byte0]: 53
5705 12:17:38.465978 [Byte1]: 51
5706 12:17:38.466058
5707 12:17:38.469849 Final RX Vref Byte 0 = 53 to rank0
5708 12:17:38.473004 Final RX Vref Byte 1 = 51 to rank0
5709 12:17:38.475965 Final RX Vref Byte 0 = 53 to rank1
5710 12:17:38.479796 Final RX Vref Byte 1 = 51 to rank1==
5711 12:17:38.482793 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 12:17:38.486131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 12:17:38.486213 ==
5714 12:17:38.489884 DQS Delay:
5715 12:17:38.489963 DQS0 = 0, DQS1 = 0
5716 12:17:38.492965 DQM Delay:
5717 12:17:38.493040 DQM0 = 103, DQM1 = 100
5718 12:17:38.493109 DQ Delay:
5719 12:17:38.496227 DQ0 =106, DQ1 =96, DQ2 =96, DQ3 =100
5720 12:17:38.499354 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5721 12:17:38.502820 DQ8 =90, DQ9 =92, DQ10 =98, DQ11 =92
5722 12:17:38.509332 DQ12 =106, DQ13 =106, DQ14 =108, DQ15 =108
5723 12:17:38.509411
5724 12:17:38.509474
5725 12:17:38.516090 [DQSOSCAuto] RK0, (LSB)MR18= 0x172f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5726 12:17:38.519200 CH1 RK0: MR19=505, MR18=172F
5727 12:17:38.525713 CH1_RK0: MR19=0x505, MR18=0x172F, DQSOSC=407, MR23=63, INC=65, DEC=43
5728 12:17:38.525796
5729 12:17:38.529415 ----->DramcWriteLeveling(PI) begin...
5730 12:17:38.529491 ==
5731 12:17:38.532708 Dram Type= 6, Freq= 0, CH_1, rank 1
5732 12:17:38.536400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 12:17:38.536485 ==
5734 12:17:38.539392 Write leveling (Byte 0): 25 => 25
5735 12:17:38.542632 Write leveling (Byte 1): 28 => 28
5736 12:17:38.545755 DramcWriteLeveling(PI) end<-----
5737 12:17:38.545836
5738 12:17:38.545899 ==
5739 12:17:38.548946 Dram Type= 6, Freq= 0, CH_1, rank 1
5740 12:17:38.552559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 12:17:38.552642 ==
5742 12:17:38.556146 [Gating] SW mode calibration
5743 12:17:38.562474 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5744 12:17:38.569009 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5745 12:17:38.572702 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 12:17:38.579558 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 12:17:38.582522 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 12:17:38.586168 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 12:17:38.592642 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 12:17:38.595799 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 12:17:38.598900 0 14 24 | B1->B0 | 2f2f 3030 | 1 1 | (1 0) (1 0)
5752 12:17:38.602945 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5753 12:17:38.608809 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 12:17:38.612120 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 12:17:38.615692 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 12:17:38.622057 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 12:17:38.625692 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 12:17:38.629137 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 12:17:38.635779 0 15 24 | B1->B0 | 3737 2e2e | 0 0 | (0 0) (0 0)
5760 12:17:38.639156 0 15 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (1 1)
5761 12:17:38.642345 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 12:17:38.648551 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 12:17:38.652015 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 12:17:38.655246 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 12:17:38.662062 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 12:17:38.665291 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 12:17:38.668636 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5768 12:17:38.675044 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 12:17:38.678396 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5770 12:17:38.682263 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 12:17:38.688533 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 12:17:38.691710 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 12:17:38.695216 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 12:17:38.702259 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 12:17:38.705245 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 12:17:38.708850 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 12:17:38.715362 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 12:17:38.718662 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 12:17:38.722048 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 12:17:38.728454 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 12:17:38.731821 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 12:17:38.734788 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 12:17:38.741535 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 12:17:38.744867 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5785 12:17:38.748121 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 12:17:38.751817 Total UI for P1: 0, mck2ui 16
5787 12:17:38.755091 best dqsien dly found for B0: ( 1, 2, 28)
5788 12:17:38.758285 Total UI for P1: 0, mck2ui 16
5789 12:17:38.761500 best dqsien dly found for B1: ( 1, 2, 28)
5790 12:17:38.765100 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5791 12:17:38.768185 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5792 12:17:38.768281
5793 12:17:38.771671 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5794 12:17:38.778084 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5795 12:17:38.778174 [Gating] SW calibration Done
5796 12:17:38.778241 ==
5797 12:17:38.781508 Dram Type= 6, Freq= 0, CH_1, rank 1
5798 12:17:38.787839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5799 12:17:38.787921 ==
5800 12:17:38.787985 RX Vref Scan: 0
5801 12:17:38.788046
5802 12:17:38.791770 RX Vref 0 -> 0, step: 1
5803 12:17:38.791851
5804 12:17:38.794888 RX Delay -80 -> 252, step: 8
5805 12:17:38.797890 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5806 12:17:38.801215 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5807 12:17:38.804858 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5808 12:17:38.808526 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5809 12:17:38.814485 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5810 12:17:38.817671 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5811 12:17:38.821480 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5812 12:17:38.824471 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5813 12:17:38.827787 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5814 12:17:38.831543 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5815 12:17:38.837976 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5816 12:17:38.841064 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5817 12:17:38.844989 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5818 12:17:38.848070 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5819 12:17:38.851140 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5820 12:17:38.857846 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5821 12:17:38.857928 ==
5822 12:17:38.861414 Dram Type= 6, Freq= 0, CH_1, rank 1
5823 12:17:38.864677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5824 12:17:38.864757 ==
5825 12:17:38.864822 DQS Delay:
5826 12:17:38.867785 DQS0 = 0, DQS1 = 0
5827 12:17:38.867866 DQM Delay:
5828 12:17:38.871022 DQM0 = 103, DQM1 = 98
5829 12:17:38.871103 DQ Delay:
5830 12:17:38.874144 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5831 12:17:38.877818 DQ4 =95, DQ5 =119, DQ6 =119, DQ7 =99
5832 12:17:38.881160 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5833 12:17:38.884473 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5834 12:17:38.884553
5835 12:17:38.884617
5836 12:17:38.884676 ==
5837 12:17:38.887867 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 12:17:38.894404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 12:17:38.894488 ==
5840 12:17:38.894552
5841 12:17:38.894611
5842 12:17:38.894667 TX Vref Scan disable
5843 12:17:38.897488 == TX Byte 0 ==
5844 12:17:38.901144 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5845 12:17:38.904304 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5846 12:17:38.907509 == TX Byte 1 ==
5847 12:17:38.911124 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5848 12:17:38.914289 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5849 12:17:38.917710 ==
5850 12:17:38.921033 Dram Type= 6, Freq= 0, CH_1, rank 1
5851 12:17:38.924269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5852 12:17:38.924388 ==
5853 12:17:38.924453
5854 12:17:38.924512
5855 12:17:38.927477 TX Vref Scan disable
5856 12:17:38.927558 == TX Byte 0 ==
5857 12:17:38.933970 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5858 12:17:38.937645 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5859 12:17:38.937727 == TX Byte 1 ==
5860 12:17:38.944006 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5861 12:17:38.947365 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5862 12:17:38.947445
5863 12:17:38.947509 [DATLAT]
5864 12:17:38.951179 Freq=933, CH1 RK1
5865 12:17:38.951260
5866 12:17:38.951324 DATLAT Default: 0xb
5867 12:17:38.954274 0, 0xFFFF, sum = 0
5868 12:17:38.954356 1, 0xFFFF, sum = 0
5869 12:17:38.957460 2, 0xFFFF, sum = 0
5870 12:17:38.957542 3, 0xFFFF, sum = 0
5871 12:17:38.960634 4, 0xFFFF, sum = 0
5872 12:17:38.960716 5, 0xFFFF, sum = 0
5873 12:17:38.963787 6, 0xFFFF, sum = 0
5874 12:17:38.967434 7, 0xFFFF, sum = 0
5875 12:17:38.967516 8, 0xFFFF, sum = 0
5876 12:17:38.970515 9, 0xFFFF, sum = 0
5877 12:17:38.970597 10, 0x0, sum = 1
5878 12:17:38.973913 11, 0x0, sum = 2
5879 12:17:38.973995 12, 0x0, sum = 3
5880 12:17:38.974060 13, 0x0, sum = 4
5881 12:17:38.977615 best_step = 11
5882 12:17:38.977696
5883 12:17:38.977759 ==
5884 12:17:38.980857 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 12:17:38.984069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 12:17:38.984153 ==
5887 12:17:38.987193 RX Vref Scan: 0
5888 12:17:38.987300
5889 12:17:38.987391 RX Vref 0 -> 0, step: 1
5890 12:17:38.987479
5891 12:17:38.990334 RX Delay -45 -> 252, step: 4
5892 12:17:38.998176 iDelay=199, Bit 0, Center 110 (27 ~ 194) 168
5893 12:17:39.001482 iDelay=199, Bit 1, Center 100 (19 ~ 182) 164
5894 12:17:39.004502 iDelay=199, Bit 2, Center 96 (15 ~ 178) 164
5895 12:17:39.007739 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5896 12:17:39.011554 iDelay=199, Bit 4, Center 100 (19 ~ 182) 164
5897 12:17:39.017800 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5898 12:17:39.021808 iDelay=199, Bit 6, Center 114 (31 ~ 198) 168
5899 12:17:39.024438 iDelay=199, Bit 7, Center 104 (19 ~ 190) 172
5900 12:17:39.027939 iDelay=199, Bit 8, Center 90 (7 ~ 174) 168
5901 12:17:39.030992 iDelay=199, Bit 9, Center 92 (7 ~ 178) 172
5902 12:17:39.034454 iDelay=199, Bit 10, Center 100 (15 ~ 186) 172
5903 12:17:39.040915 iDelay=199, Bit 11, Center 94 (11 ~ 178) 168
5904 12:17:39.044708 iDelay=199, Bit 12, Center 106 (15 ~ 198) 184
5905 12:17:39.048076 iDelay=199, Bit 13, Center 106 (23 ~ 190) 168
5906 12:17:39.051399 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5907 12:17:39.057772 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5908 12:17:39.057853 ==
5909 12:17:39.061024 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 12:17:39.064727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 12:17:39.064809 ==
5912 12:17:39.064873 DQS Delay:
5913 12:17:39.068058 DQS0 = 0, DQS1 = 0
5914 12:17:39.068138 DQM Delay:
5915 12:17:39.071067 DQM0 = 105, DQM1 = 100
5916 12:17:39.071148 DQ Delay:
5917 12:17:39.074795 DQ0 =110, DQ1 =100, DQ2 =96, DQ3 =100
5918 12:17:39.077582 DQ4 =100, DQ5 =116, DQ6 =114, DQ7 =104
5919 12:17:39.081358 DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =94
5920 12:17:39.084177 DQ12 =106, DQ13 =106, DQ14 =104, DQ15 =108
5921 12:17:39.084259
5922 12:17:39.084365
5923 12:17:39.094202 [DQSOSCAuto] RK1, (LSB)MR18= 0x2bfe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5924 12:17:39.097312 CH1 RK1: MR19=504, MR18=2BFE
5925 12:17:39.101044 CH1_RK1: MR19=0x504, MR18=0x2BFE, DQSOSC=408, MR23=63, INC=65, DEC=43
5926 12:17:39.104171 [RxdqsGatingPostProcess] freq 933
5927 12:17:39.110830 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5928 12:17:39.114394 best DQS0 dly(2T, 0.5T) = (0, 10)
5929 12:17:39.117231 best DQS1 dly(2T, 0.5T) = (0, 10)
5930 12:17:39.121048 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5931 12:17:39.124343 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5932 12:17:39.127688 best DQS0 dly(2T, 0.5T) = (0, 10)
5933 12:17:39.131012 best DQS1 dly(2T, 0.5T) = (0, 10)
5934 12:17:39.133912 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5935 12:17:39.137546 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5936 12:17:39.137626 Pre-setting of DQS Precalculation
5937 12:17:39.144225 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5938 12:17:39.150508 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5939 12:17:39.157310 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5940 12:17:39.157392
5941 12:17:39.157455
5942 12:17:39.160778 [Calibration Summary] 1866 Mbps
5943 12:17:39.163944 CH 0, Rank 0
5944 12:17:39.164025 SW Impedance : PASS
5945 12:17:39.167133 DUTY Scan : NO K
5946 12:17:39.170850 ZQ Calibration : PASS
5947 12:17:39.170931 Jitter Meter : NO K
5948 12:17:39.174120 CBT Training : PASS
5949 12:17:39.177427 Write leveling : PASS
5950 12:17:39.177508 RX DQS gating : PASS
5951 12:17:39.180509 RX DQ/DQS(RDDQC) : PASS
5952 12:17:39.183681 TX DQ/DQS : PASS
5953 12:17:39.183762 RX DATLAT : PASS
5954 12:17:39.187387 RX DQ/DQS(Engine): PASS
5955 12:17:39.187467 TX OE : NO K
5956 12:17:39.190406 All Pass.
5957 12:17:39.190486
5958 12:17:39.190549 CH 0, Rank 1
5959 12:17:39.193965 SW Impedance : PASS
5960 12:17:39.194045 DUTY Scan : NO K
5961 12:17:39.197485 ZQ Calibration : PASS
5962 12:17:39.200523 Jitter Meter : NO K
5963 12:17:39.200604 CBT Training : PASS
5964 12:17:39.203864 Write leveling : PASS
5965 12:17:39.206908 RX DQS gating : PASS
5966 12:17:39.206989 RX DQ/DQS(RDDQC) : PASS
5967 12:17:39.210611 TX DQ/DQS : PASS
5968 12:17:39.213551 RX DATLAT : PASS
5969 12:17:39.213649 RX DQ/DQS(Engine): PASS
5970 12:17:39.217325 TX OE : NO K
5971 12:17:39.217428 All Pass.
5972 12:17:39.217550
5973 12:17:39.220545 CH 1, Rank 0
5974 12:17:39.220614 SW Impedance : PASS
5975 12:17:39.223417 DUTY Scan : NO K
5976 12:17:39.227244 ZQ Calibration : PASS
5977 12:17:39.227337 Jitter Meter : NO K
5978 12:17:39.230523 CBT Training : PASS
5979 12:17:39.233646 Write leveling : PASS
5980 12:17:39.233713 RX DQS gating : PASS
5981 12:17:39.236867 RX DQ/DQS(RDDQC) : PASS
5982 12:17:39.240594 TX DQ/DQS : PASS
5983 12:17:39.240661 RX DATLAT : PASS
5984 12:17:39.243687 RX DQ/DQS(Engine): PASS
5985 12:17:39.243753 TX OE : NO K
5986 12:17:39.246822 All Pass.
5987 12:17:39.246914
5988 12:17:39.247003 CH 1, Rank 1
5989 12:17:39.250052 SW Impedance : PASS
5990 12:17:39.250117 DUTY Scan : NO K
5991 12:17:39.253942 ZQ Calibration : PASS
5992 12:17:39.256542 Jitter Meter : NO K
5993 12:17:39.256610 CBT Training : PASS
5994 12:17:39.259951 Write leveling : PASS
5995 12:17:39.264013 RX DQS gating : PASS
5996 12:17:39.264108 RX DQ/DQS(RDDQC) : PASS
5997 12:17:39.266882 TX DQ/DQS : PASS
5998 12:17:39.270136 RX DATLAT : PASS
5999 12:17:39.270210 RX DQ/DQS(Engine): PASS
6000 12:17:39.273526 TX OE : NO K
6001 12:17:39.273601 All Pass.
6002 12:17:39.273661
6003 12:17:39.276686 DramC Write-DBI off
6004 12:17:39.280151 PER_BANK_REFRESH: Hybrid Mode
6005 12:17:39.280260 TX_TRACKING: ON
6006 12:17:39.289991 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6007 12:17:39.293166 [FAST_K] Save calibration result to emmc
6008 12:17:39.296742 dramc_set_vcore_voltage set vcore to 650000
6009 12:17:39.300481 Read voltage for 400, 6
6010 12:17:39.300556 Vio18 = 0
6011 12:17:39.300625 Vcore = 650000
6012 12:17:39.303246 Vdram = 0
6013 12:17:39.303319 Vddq = 0
6014 12:17:39.303406 Vmddr = 0
6015 12:17:39.309859 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6016 12:17:39.313612 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6017 12:17:39.316637 MEM_TYPE=3, freq_sel=20
6018 12:17:39.320265 sv_algorithm_assistance_LP4_800
6019 12:17:39.323452 ============ PULL DRAM RESETB DOWN ============
6020 12:17:39.326488 ========== PULL DRAM RESETB DOWN end =========
6021 12:17:39.333121 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6022 12:17:39.336440 ===================================
6023 12:17:39.336509 LPDDR4 DRAM CONFIGURATION
6024 12:17:39.340137 ===================================
6025 12:17:39.343346 EX_ROW_EN[0] = 0x0
6026 12:17:39.346506 EX_ROW_EN[1] = 0x0
6027 12:17:39.346576 LP4Y_EN = 0x0
6028 12:17:39.350196 WORK_FSP = 0x0
6029 12:17:39.350263 WL = 0x2
6030 12:17:39.353491 RL = 0x2
6031 12:17:39.353558 BL = 0x2
6032 12:17:39.356645 RPST = 0x0
6033 12:17:39.356712 RD_PRE = 0x0
6034 12:17:39.360096 WR_PRE = 0x1
6035 12:17:39.360188 WR_PST = 0x0
6036 12:17:39.363740 DBI_WR = 0x0
6037 12:17:39.363831 DBI_RD = 0x0
6038 12:17:39.366741 OTF = 0x1
6039 12:17:39.370147 ===================================
6040 12:17:39.373306 ===================================
6041 12:17:39.373373 ANA top config
6042 12:17:39.376355 ===================================
6043 12:17:39.380000 DLL_ASYNC_EN = 0
6044 12:17:39.383050 ALL_SLAVE_EN = 1
6045 12:17:39.386302 NEW_RANK_MODE = 1
6046 12:17:39.386401 DLL_IDLE_MODE = 1
6047 12:17:39.389645 LP45_APHY_COMB_EN = 1
6048 12:17:39.392927 TX_ODT_DIS = 1
6049 12:17:39.396499 NEW_8X_MODE = 1
6050 12:17:39.399846 ===================================
6051 12:17:39.403077 ===================================
6052 12:17:39.406411 data_rate = 800
6053 12:17:39.406479 CKR = 1
6054 12:17:39.409660 DQ_P2S_RATIO = 4
6055 12:17:39.413234 ===================================
6056 12:17:39.416659 CA_P2S_RATIO = 4
6057 12:17:39.419955 DQ_CA_OPEN = 0
6058 12:17:39.423016 DQ_SEMI_OPEN = 1
6059 12:17:39.423112 CA_SEMI_OPEN = 1
6060 12:17:39.426270 CA_FULL_RATE = 0
6061 12:17:39.429702 DQ_CKDIV4_EN = 0
6062 12:17:39.432861 CA_CKDIV4_EN = 1
6063 12:17:39.436266 CA_PREDIV_EN = 0
6064 12:17:39.439555 PH8_DLY = 0
6065 12:17:39.439649 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6066 12:17:39.443284 DQ_AAMCK_DIV = 0
6067 12:17:39.446486 CA_AAMCK_DIV = 0
6068 12:17:39.449573 CA_ADMCK_DIV = 4
6069 12:17:39.453192 DQ_TRACK_CA_EN = 0
6070 12:17:39.456302 CA_PICK = 800
6071 12:17:39.456382 CA_MCKIO = 400
6072 12:17:39.459559 MCKIO_SEMI = 400
6073 12:17:39.462852 PLL_FREQ = 3016
6074 12:17:39.466088 DQ_UI_PI_RATIO = 32
6075 12:17:39.469827 CA_UI_PI_RATIO = 32
6076 12:17:39.473163 ===================================
6077 12:17:39.476306 ===================================
6078 12:17:39.479459 memory_type:LPDDR4
6079 12:17:39.479525 GP_NUM : 10
6080 12:17:39.483365 SRAM_EN : 1
6081 12:17:39.483460 MD32_EN : 0
6082 12:17:39.486209 ===================================
6083 12:17:39.489361 [ANA_INIT] >>>>>>>>>>>>>>
6084 12:17:39.493228 <<<<<< [CONFIGURE PHASE]: ANA_TX
6085 12:17:39.496447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6086 12:17:39.499685 ===================================
6087 12:17:39.502817 data_rate = 800,PCW = 0X7400
6088 12:17:39.506438 ===================================
6089 12:17:39.509567 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6090 12:17:39.516205 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6091 12:17:39.526151 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6092 12:17:39.529871 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6093 12:17:39.532493 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6094 12:17:39.535885 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6095 12:17:39.539645 [ANA_INIT] flow start
6096 12:17:39.542683 [ANA_INIT] PLL >>>>>>>>
6097 12:17:39.542781 [ANA_INIT] PLL <<<<<<<<
6098 12:17:39.546314 [ANA_INIT] MIDPI >>>>>>>>
6099 12:17:39.549274 [ANA_INIT] MIDPI <<<<<<<<
6100 12:17:39.552766 [ANA_INIT] DLL >>>>>>>>
6101 12:17:39.552841 [ANA_INIT] flow end
6102 12:17:39.556172 ============ LP4 DIFF to SE enter ============
6103 12:17:39.562459 ============ LP4 DIFF to SE exit ============
6104 12:17:39.562561 [ANA_INIT] <<<<<<<<<<<<<
6105 12:17:39.565697 [Flow] Enable top DCM control >>>>>
6106 12:17:39.569255 [Flow] Enable top DCM control <<<<<
6107 12:17:39.572354 Enable DLL master slave shuffle
6108 12:17:39.579355 ==============================================================
6109 12:17:39.579428 Gating Mode config
6110 12:17:39.586291 ==============================================================
6111 12:17:39.589338 Config description:
6112 12:17:39.595798 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6113 12:17:39.606131 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6114 12:17:39.609288 SELPH_MODE 0: By rank 1: By Phase
6115 12:17:39.616275 ==============================================================
6116 12:17:39.619368 GAT_TRACK_EN = 0
6117 12:17:39.619440 RX_GATING_MODE = 2
6118 12:17:39.622352 RX_GATING_TRACK_MODE = 2
6119 12:17:39.625607 SELPH_MODE = 1
6120 12:17:39.629028 PICG_EARLY_EN = 1
6121 12:17:39.632428 VALID_LAT_VALUE = 1
6122 12:17:39.639315 ==============================================================
6123 12:17:39.642314 Enter into Gating configuration >>>>
6124 12:17:39.646120 Exit from Gating configuration <<<<
6125 12:17:39.649379 Enter into DVFS_PRE_config >>>>>
6126 12:17:39.659156 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6127 12:17:39.662908 Exit from DVFS_PRE_config <<<<<
6128 12:17:39.665734 Enter into PICG configuration >>>>
6129 12:17:39.669202 Exit from PICG configuration <<<<
6130 12:17:39.672610 [RX_INPUT] configuration >>>>>
6131 12:17:39.672691 [RX_INPUT] configuration <<<<<
6132 12:17:39.679007 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6133 12:17:39.685977 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6134 12:17:39.689010 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6135 12:17:39.695836 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6136 12:17:39.702757 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6137 12:17:39.709096 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6138 12:17:39.712417 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6139 12:17:39.716005 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6140 12:17:39.722614 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6141 12:17:39.725737 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6142 12:17:39.728892 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6143 12:17:39.735979 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6144 12:17:39.738966 ===================================
6145 12:17:39.739048 LPDDR4 DRAM CONFIGURATION
6146 12:17:39.742437 ===================================
6147 12:17:39.746043 EX_ROW_EN[0] = 0x0
6148 12:17:39.746124 EX_ROW_EN[1] = 0x0
6149 12:17:39.748848 LP4Y_EN = 0x0
6150 12:17:39.752652 WORK_FSP = 0x0
6151 12:17:39.752733 WL = 0x2
6152 12:17:39.755274 RL = 0x2
6153 12:17:39.755355 BL = 0x2
6154 12:17:39.759031 RPST = 0x0
6155 12:17:39.759112 RD_PRE = 0x0
6156 12:17:39.762159 WR_PRE = 0x1
6157 12:17:39.762240 WR_PST = 0x0
6158 12:17:39.766077 DBI_WR = 0x0
6159 12:17:39.766158 DBI_RD = 0x0
6160 12:17:39.769182 OTF = 0x1
6161 12:17:39.772025 ===================================
6162 12:17:39.775363 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6163 12:17:39.779155 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6164 12:17:39.782400 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6165 12:17:39.785611 ===================================
6166 12:17:39.788866 LPDDR4 DRAM CONFIGURATION
6167 12:17:39.792479 ===================================
6168 12:17:39.795352 EX_ROW_EN[0] = 0x10
6169 12:17:39.795432 EX_ROW_EN[1] = 0x0
6170 12:17:39.799148 LP4Y_EN = 0x0
6171 12:17:39.799229 WORK_FSP = 0x0
6172 12:17:39.802188 WL = 0x2
6173 12:17:39.802283 RL = 0x2
6174 12:17:39.805488 BL = 0x2
6175 12:17:39.805558 RPST = 0x0
6176 12:17:39.808700 RD_PRE = 0x0
6177 12:17:39.808800 WR_PRE = 0x1
6178 12:17:39.812389 WR_PST = 0x0
6179 12:17:39.815657 DBI_WR = 0x0
6180 12:17:39.815752 DBI_RD = 0x0
6181 12:17:39.818786 OTF = 0x1
6182 12:17:39.822110 ===================================
6183 12:17:39.825157 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6184 12:17:39.830822 nWR fixed to 30
6185 12:17:39.833959 [ModeRegInit_LP4] CH0 RK0
6186 12:17:39.834062 [ModeRegInit_LP4] CH0 RK1
6187 12:17:39.837080 [ModeRegInit_LP4] CH1 RK0
6188 12:17:39.840505 [ModeRegInit_LP4] CH1 RK1
6189 12:17:39.840576 match AC timing 19
6190 12:17:39.847073 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6191 12:17:39.850996 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6192 12:17:39.853980 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6193 12:17:39.860495 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6194 12:17:39.864343 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6195 12:17:39.864438 ==
6196 12:17:39.867406 Dram Type= 6, Freq= 0, CH_0, rank 0
6197 12:17:39.870490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6198 12:17:39.870565 ==
6199 12:17:39.876907 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6200 12:17:39.883783 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6201 12:17:39.887007 [CA 0] Center 36 (8~64) winsize 57
6202 12:17:39.890324 [CA 1] Center 36 (8~64) winsize 57
6203 12:17:39.893950 [CA 2] Center 36 (8~64) winsize 57
6204 12:17:39.897121 [CA 3] Center 36 (8~64) winsize 57
6205 12:17:39.897194 [CA 4] Center 36 (8~64) winsize 57
6206 12:17:39.900384 [CA 5] Center 36 (8~64) winsize 57
6207 12:17:39.900450
6208 12:17:39.906700 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6209 12:17:39.906795
6210 12:17:39.910414 [CATrainingPosCal] consider 1 rank data
6211 12:17:39.913456 u2DelayCellTimex100 = 270/100 ps
6212 12:17:39.916952 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 12:17:39.920436 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 12:17:39.923778 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 12:17:39.927356 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 12:17:39.930253 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 12:17:39.933526 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 12:17:39.933601
6219 12:17:39.936805 CA PerBit enable=1, Macro0, CA PI delay=36
6220 12:17:39.936872
6221 12:17:39.939906 [CBTSetCACLKResult] CA Dly = 36
6222 12:17:39.943266 CS Dly: 1 (0~32)
6223 12:17:39.943374 ==
6224 12:17:39.947016 Dram Type= 6, Freq= 0, CH_0, rank 1
6225 12:17:39.949912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6226 12:17:39.950016 ==
6227 12:17:39.956778 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6228 12:17:39.960121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6229 12:17:39.963133 [CA 0] Center 36 (8~64) winsize 57
6230 12:17:39.966885 [CA 1] Center 36 (8~64) winsize 57
6231 12:17:39.970106 [CA 2] Center 36 (8~64) winsize 57
6232 12:17:39.973768 [CA 3] Center 36 (8~64) winsize 57
6233 12:17:39.976780 [CA 4] Center 36 (8~64) winsize 57
6234 12:17:39.979818 [CA 5] Center 36 (8~64) winsize 57
6235 12:17:39.979914
6236 12:17:39.982998 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6237 12:17:39.983104
6238 12:17:39.986771 [CATrainingPosCal] consider 2 rank data
6239 12:17:39.990100 u2DelayCellTimex100 = 270/100 ps
6240 12:17:39.993278 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 12:17:39.996311 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 12:17:40.003126 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 12:17:40.006409 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 12:17:40.009760 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 12:17:40.012931 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 12:17:40.013034
6247 12:17:40.016103 CA PerBit enable=1, Macro0, CA PI delay=36
6248 12:17:40.016208
6249 12:17:40.019775 [CBTSetCACLKResult] CA Dly = 36
6250 12:17:40.019877 CS Dly: 1 (0~32)
6251 12:17:40.019967
6252 12:17:40.026626 ----->DramcWriteLeveling(PI) begin...
6253 12:17:40.026728 ==
6254 12:17:40.029592 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 12:17:40.032766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 12:17:40.032835 ==
6257 12:17:40.036961 Write leveling (Byte 0): 40 => 8
6258 12:17:40.039417 Write leveling (Byte 1): 40 => 8
6259 12:17:40.042948 DramcWriteLeveling(PI) end<-----
6260 12:17:40.043016
6261 12:17:40.043105 ==
6262 12:17:40.046379 Dram Type= 6, Freq= 0, CH_0, rank 0
6263 12:17:40.049489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6264 12:17:40.049558 ==
6265 12:17:40.052566 [Gating] SW mode calibration
6266 12:17:40.059715 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6267 12:17:40.065917 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6268 12:17:40.069526 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6269 12:17:40.072715 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6270 12:17:40.079075 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 12:17:40.082595 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6272 12:17:40.086268 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 12:17:40.092458 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 12:17:40.095702 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 12:17:40.098891 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 12:17:40.102655 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 12:17:40.105922 Total UI for P1: 0, mck2ui 16
6278 12:17:40.109235 best dqsien dly found for B0: ( 0, 14, 24)
6279 12:17:40.112510 Total UI for P1: 0, mck2ui 16
6280 12:17:40.115806 best dqsien dly found for B1: ( 0, 14, 24)
6281 12:17:40.118858 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6282 12:17:40.125596 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6283 12:17:40.125677
6284 12:17:40.128741 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6285 12:17:40.132392 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6286 12:17:40.135894 [Gating] SW calibration Done
6287 12:17:40.135975 ==
6288 12:17:40.139067 Dram Type= 6, Freq= 0, CH_0, rank 0
6289 12:17:40.142281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 12:17:40.142363 ==
6291 12:17:40.145493 RX Vref Scan: 0
6292 12:17:40.145574
6293 12:17:40.145637 RX Vref 0 -> 0, step: 1
6294 12:17:40.145697
6295 12:17:40.149209 RX Delay -410 -> 252, step: 16
6296 12:17:40.152281 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6297 12:17:40.159204 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6298 12:17:40.162422 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6299 12:17:40.165976 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6300 12:17:40.168679 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6301 12:17:40.175479 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6302 12:17:40.178584 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6303 12:17:40.182201 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6304 12:17:40.185366 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6305 12:17:40.191975 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6306 12:17:40.195694 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6307 12:17:40.198989 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6308 12:17:40.202066 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6309 12:17:40.208910 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6310 12:17:40.212352 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6311 12:17:40.215546 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6312 12:17:40.215627 ==
6313 12:17:40.218836 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 12:17:40.225260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 12:17:40.225364 ==
6316 12:17:40.225429 DQS Delay:
6317 12:17:40.228818 DQS0 = 27, DQS1 = 35
6318 12:17:40.228897 DQM Delay:
6319 12:17:40.228961 DQM0 = 10, DQM1 = 12
6320 12:17:40.231963 DQ Delay:
6321 12:17:40.235250 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6322 12:17:40.235330 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6323 12:17:40.238836 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6324 12:17:40.241858 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6325 12:17:40.241938
6326 12:17:40.242001
6327 12:17:40.245607 ==
6328 12:17:40.248955 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 12:17:40.252159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 12:17:40.252294 ==
6331 12:17:40.252377
6332 12:17:40.252437
6333 12:17:40.254980 TX Vref Scan disable
6334 12:17:40.255059 == TX Byte 0 ==
6335 12:17:40.258428 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6336 12:17:40.265022 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6337 12:17:40.265112 == TX Byte 1 ==
6338 12:17:40.268851 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6339 12:17:40.275028 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6340 12:17:40.275108 ==
6341 12:17:40.278569 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 12:17:40.281507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 12:17:40.281613 ==
6344 12:17:40.281710
6345 12:17:40.281798
6346 12:17:40.285166 TX Vref Scan disable
6347 12:17:40.285246 == TX Byte 0 ==
6348 12:17:40.288246 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6349 12:17:40.295329 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6350 12:17:40.295409 == TX Byte 1 ==
6351 12:17:40.298505 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6352 12:17:40.304835 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6353 12:17:40.304952
6354 12:17:40.305045 [DATLAT]
6355 12:17:40.305135 Freq=400, CH0 RK0
6356 12:17:40.305222
6357 12:17:40.308228 DATLAT Default: 0xf
6358 12:17:40.311613 0, 0xFFFF, sum = 0
6359 12:17:40.311709 1, 0xFFFF, sum = 0
6360 12:17:40.315007 2, 0xFFFF, sum = 0
6361 12:17:40.315108 3, 0xFFFF, sum = 0
6362 12:17:40.318389 4, 0xFFFF, sum = 0
6363 12:17:40.318485 5, 0xFFFF, sum = 0
6364 12:17:40.321601 6, 0xFFFF, sum = 0
6365 12:17:40.321708 7, 0xFFFF, sum = 0
6366 12:17:40.324756 8, 0xFFFF, sum = 0
6367 12:17:40.324832 9, 0xFFFF, sum = 0
6368 12:17:40.328283 10, 0xFFFF, sum = 0
6369 12:17:40.328421 11, 0xFFFF, sum = 0
6370 12:17:40.331403 12, 0xFFFF, sum = 0
6371 12:17:40.331486 13, 0x0, sum = 1
6372 12:17:40.334641 14, 0x0, sum = 2
6373 12:17:40.334722 15, 0x0, sum = 3
6374 12:17:40.338391 16, 0x0, sum = 4
6375 12:17:40.338473 best_step = 14
6376 12:17:40.338536
6377 12:17:40.338596 ==
6378 12:17:40.341533 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 12:17:40.347909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 12:17:40.347990 ==
6381 12:17:40.348053 RX Vref Scan: 1
6382 12:17:40.348113
6383 12:17:40.351176 RX Vref 0 -> 0, step: 1
6384 12:17:40.351255
6385 12:17:40.354801 RX Delay -311 -> 252, step: 8
6386 12:17:40.354881
6387 12:17:40.358101 Set Vref, RX VrefLevel [Byte0]: 56
6388 12:17:40.361364 [Byte1]: 47
6389 12:17:40.361445
6390 12:17:40.364478 Final RX Vref Byte 0 = 56 to rank0
6391 12:17:40.368188 Final RX Vref Byte 1 = 47 to rank0
6392 12:17:40.371203 Final RX Vref Byte 0 = 56 to rank1
6393 12:17:40.374887 Final RX Vref Byte 1 = 47 to rank1==
6394 12:17:40.378102 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 12:17:40.381172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 12:17:40.381252 ==
6397 12:17:40.384340 DQS Delay:
6398 12:17:40.384420 DQS0 = 28, DQS1 = 36
6399 12:17:40.387995 DQM Delay:
6400 12:17:40.388075 DQM0 = 10, DQM1 = 13
6401 12:17:40.388138 DQ Delay:
6402 12:17:40.390989 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6403 12:17:40.394729 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6404 12:17:40.398011 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6405 12:17:40.401056 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6406 12:17:40.401137
6407 12:17:40.401200
6408 12:17:40.411129 [DQSOSCAuto] RK0, (LSB)MR18= 0xcab7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 384 ps
6409 12:17:40.411236 CH0 RK0: MR19=C0C, MR18=CAB7
6410 12:17:40.417714 CH0_RK0: MR19=0xC0C, MR18=0xCAB7, DQSOSC=384, MR23=63, INC=400, DEC=267
6411 12:17:40.417820 ==
6412 12:17:40.421097 Dram Type= 6, Freq= 0, CH_0, rank 1
6413 12:17:40.427927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 12:17:40.428034 ==
6415 12:17:40.435325 [Gating] SW mode calibration
6416 12:17:40.437766 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6417 12:17:40.441030 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6418 12:17:40.447911 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6419 12:17:40.450977 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6420 12:17:40.454591 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 12:17:40.460914 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6422 12:17:40.464378 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 12:17:40.467244 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 12:17:40.474302 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 12:17:40.478006 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 12:17:40.481023 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 12:17:40.484084 Total UI for P1: 0, mck2ui 16
6428 12:17:40.487370 best dqsien dly found for B0: ( 0, 14, 24)
6429 12:17:40.491142 Total UI for P1: 0, mck2ui 16
6430 12:17:40.494315 best dqsien dly found for B1: ( 0, 14, 24)
6431 12:17:40.497895 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6432 12:17:40.500670 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6433 12:17:40.500751
6434 12:17:40.504227 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6435 12:17:40.511255 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6436 12:17:40.511336 [Gating] SW calibration Done
6437 12:17:40.511400 ==
6438 12:17:40.514374 Dram Type= 6, Freq= 0, CH_0, rank 1
6439 12:17:40.520748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6440 12:17:40.520830 ==
6441 12:17:40.520895 RX Vref Scan: 0
6442 12:17:40.520956
6443 12:17:40.524399 RX Vref 0 -> 0, step: 1
6444 12:17:40.524480
6445 12:17:40.527383 RX Delay -410 -> 252, step: 16
6446 12:17:40.530911 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6447 12:17:40.534176 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6448 12:17:40.540923 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6449 12:17:40.544045 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6450 12:17:40.547072 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6451 12:17:40.550549 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6452 12:17:40.557312 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6453 12:17:40.560702 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6454 12:17:40.563696 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6455 12:17:40.567402 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6456 12:17:40.574170 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6457 12:17:40.577297 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6458 12:17:40.580480 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6459 12:17:40.583798 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6460 12:17:40.590236 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6461 12:17:40.594054 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6462 12:17:40.594130 ==
6463 12:17:40.597240 Dram Type= 6, Freq= 0, CH_0, rank 1
6464 12:17:40.600676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 12:17:40.600771 ==
6466 12:17:40.603632 DQS Delay:
6467 12:17:40.603703 DQS0 = 27, DQS1 = 35
6468 12:17:40.607090 DQM Delay:
6469 12:17:40.607186 DQM0 = 12, DQM1 = 12
6470 12:17:40.607273 DQ Delay:
6471 12:17:40.610621 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6472 12:17:40.613457 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6473 12:17:40.617329 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6474 12:17:40.620208 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6475 12:17:40.620350
6476 12:17:40.620416
6477 12:17:40.620474 ==
6478 12:17:40.623779 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 12:17:40.630502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 12:17:40.630602 ==
6481 12:17:40.630690
6482 12:17:40.630785
6483 12:17:40.630871 TX Vref Scan disable
6484 12:17:40.633856 == TX Byte 0 ==
6485 12:17:40.637066 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6486 12:17:40.639957 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6487 12:17:40.643393 == TX Byte 1 ==
6488 12:17:40.647234 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6489 12:17:40.650406 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6490 12:17:40.650496 ==
6491 12:17:40.653519 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 12:17:40.660585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 12:17:40.660669 ==
6494 12:17:40.660733
6495 12:17:40.660790
6496 12:17:40.660845 TX Vref Scan disable
6497 12:17:40.663491 == TX Byte 0 ==
6498 12:17:40.666963 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6499 12:17:40.670486 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6500 12:17:40.673530 == TX Byte 1 ==
6501 12:17:40.676678 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6502 12:17:40.680170 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6503 12:17:40.680273
6504 12:17:40.683098 [DATLAT]
6505 12:17:40.683201 Freq=400, CH0 RK1
6506 12:17:40.683288
6507 12:17:40.686358 DATLAT Default: 0xe
6508 12:17:40.686462 0, 0xFFFF, sum = 0
6509 12:17:40.690065 1, 0xFFFF, sum = 0
6510 12:17:40.690168 2, 0xFFFF, sum = 0
6511 12:17:40.693266 3, 0xFFFF, sum = 0
6512 12:17:40.693339 4, 0xFFFF, sum = 0
6513 12:17:40.696662 5, 0xFFFF, sum = 0
6514 12:17:40.696731 6, 0xFFFF, sum = 0
6515 12:17:40.699534 7, 0xFFFF, sum = 0
6516 12:17:40.699610 8, 0xFFFF, sum = 0
6517 12:17:40.702944 9, 0xFFFF, sum = 0
6518 12:17:40.703014 10, 0xFFFF, sum = 0
6519 12:17:40.706870 11, 0xFFFF, sum = 0
6520 12:17:40.709985 12, 0xFFFF, sum = 0
6521 12:17:40.710055 13, 0x0, sum = 1
6522 12:17:40.710114 14, 0x0, sum = 2
6523 12:17:40.713260 15, 0x0, sum = 3
6524 12:17:40.713333 16, 0x0, sum = 4
6525 12:17:40.716596 best_step = 14
6526 12:17:40.716689
6527 12:17:40.716778 ==
6528 12:17:40.719625 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 12:17:40.722797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 12:17:40.722879 ==
6531 12:17:40.726181 RX Vref Scan: 0
6532 12:17:40.726261
6533 12:17:40.726324 RX Vref 0 -> 0, step: 1
6534 12:17:40.729334
6535 12:17:40.729415 RX Delay -311 -> 252, step: 8
6536 12:17:40.737633 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6537 12:17:40.741459 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6538 12:17:40.744625 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6539 12:17:40.751075 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6540 12:17:40.754823 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6541 12:17:40.757509 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6542 12:17:40.761209 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6543 12:17:40.764388 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6544 12:17:40.770896 iDelay=217, Bit 8, Center -32 (-247 ~ 184) 432
6545 12:17:40.774197 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6546 12:17:40.777369 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6547 12:17:40.784520 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6548 12:17:40.787963 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6549 12:17:40.790812 iDelay=217, Bit 13, Center -16 (-231 ~ 200) 432
6550 12:17:40.793948 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6551 12:17:40.800909 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6552 12:17:40.800990 ==
6553 12:17:40.804117 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 12:17:40.807010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 12:17:40.807092 ==
6556 12:17:40.807156 DQS Delay:
6557 12:17:40.810692 DQS0 = 24, DQS1 = 36
6558 12:17:40.810773 DQM Delay:
6559 12:17:40.813827 DQM0 = 9, DQM1 = 14
6560 12:17:40.813908 DQ Delay:
6561 12:17:40.817448 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6562 12:17:40.820411 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6563 12:17:40.824246 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6564 12:17:40.827475 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6565 12:17:40.827548
6566 12:17:40.827610
6567 12:17:40.833915 [DQSOSCAuto] RK1, (LSB)MR18= 0xb556, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps
6568 12:17:40.837224 CH0 RK1: MR19=C0C, MR18=B556
6569 12:17:40.843613 CH0_RK1: MR19=0xC0C, MR18=0xB556, DQSOSC=387, MR23=63, INC=394, DEC=262
6570 12:17:40.847042 [RxdqsGatingPostProcess] freq 400
6571 12:17:40.853778 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6572 12:17:40.857011 best DQS0 dly(2T, 0.5T) = (0, 10)
6573 12:17:40.857083 best DQS1 dly(2T, 0.5T) = (0, 10)
6574 12:17:40.860231 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6575 12:17:40.863574 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6576 12:17:40.867219 best DQS0 dly(2T, 0.5T) = (0, 10)
6577 12:17:40.870235 best DQS1 dly(2T, 0.5T) = (0, 10)
6578 12:17:40.873437 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6579 12:17:40.877112 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6580 12:17:40.879866 Pre-setting of DQS Precalculation
6581 12:17:40.886823 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6582 12:17:40.886921 ==
6583 12:17:40.890103 Dram Type= 6, Freq= 0, CH_1, rank 0
6584 12:17:40.893613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 12:17:40.893685 ==
6586 12:17:40.899930 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6587 12:17:40.903077 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6588 12:17:40.906376 [CA 0] Center 36 (8~64) winsize 57
6589 12:17:40.910153 [CA 1] Center 36 (8~64) winsize 57
6590 12:17:40.913155 [CA 2] Center 36 (8~64) winsize 57
6591 12:17:40.916740 [CA 3] Center 36 (8~64) winsize 57
6592 12:17:40.920078 [CA 4] Center 36 (8~64) winsize 57
6593 12:17:40.923147 [CA 5] Center 36 (8~64) winsize 57
6594 12:17:40.923244
6595 12:17:40.926558 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6596 12:17:40.926655
6597 12:17:40.930121 [CATrainingPosCal] consider 1 rank data
6598 12:17:40.933171 u2DelayCellTimex100 = 270/100 ps
6599 12:17:40.936629 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 12:17:40.939655 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 12:17:40.946131 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 12:17:40.949925 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 12:17:40.952910 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 12:17:40.956147 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 12:17:40.956242
6606 12:17:40.959879 CA PerBit enable=1, Macro0, CA PI delay=36
6607 12:17:40.959972
6608 12:17:40.962803 [CBTSetCACLKResult] CA Dly = 36
6609 12:17:40.962897 CS Dly: 1 (0~32)
6610 12:17:40.965907 ==
6611 12:17:40.966006 Dram Type= 6, Freq= 0, CH_1, rank 1
6612 12:17:40.972825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 12:17:40.972902 ==
6614 12:17:40.976626 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6615 12:17:40.982685 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6616 12:17:40.986035 [CA 0] Center 36 (8~64) winsize 57
6617 12:17:40.989965 [CA 1] Center 36 (8~64) winsize 57
6618 12:17:40.992733 [CA 2] Center 36 (8~64) winsize 57
6619 12:17:40.995954 [CA 3] Center 36 (8~64) winsize 57
6620 12:17:40.999591 [CA 4] Center 36 (8~64) winsize 57
6621 12:17:41.002726 [CA 5] Center 36 (8~64) winsize 57
6622 12:17:41.002821
6623 12:17:41.006403 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6624 12:17:41.006472
6625 12:17:41.009635 [CATrainingPosCal] consider 2 rank data
6626 12:17:41.012795 u2DelayCellTimex100 = 270/100 ps
6627 12:17:41.015923 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 12:17:41.019165 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 12:17:41.022783 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 12:17:41.026029 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 12:17:41.029003 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 12:17:41.036067 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 12:17:41.036166
6634 12:17:41.039173 CA PerBit enable=1, Macro0, CA PI delay=36
6635 12:17:41.039267
6636 12:17:41.042645 [CBTSetCACLKResult] CA Dly = 36
6637 12:17:41.042738 CS Dly: 1 (0~32)
6638 12:17:41.042824
6639 12:17:41.045965 ----->DramcWriteLeveling(PI) begin...
6640 12:17:41.046060 ==
6641 12:17:41.049598 Dram Type= 6, Freq= 0, CH_1, rank 0
6642 12:17:41.055974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 12:17:41.056071 ==
6644 12:17:41.056159 Write leveling (Byte 0): 40 => 8
6645 12:17:41.059072 Write leveling (Byte 1): 40 => 8
6646 12:17:41.062682 DramcWriteLeveling(PI) end<-----
6647 12:17:41.062779
6648 12:17:41.062865 ==
6649 12:17:41.065753 Dram Type= 6, Freq= 0, CH_1, rank 0
6650 12:17:41.072243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 12:17:41.072352 ==
6652 12:17:41.075934 [Gating] SW mode calibration
6653 12:17:41.082349 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6654 12:17:41.085530 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6655 12:17:41.092191 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6656 12:17:41.095849 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6657 12:17:41.099125 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 12:17:41.105417 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6659 12:17:41.109074 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 12:17:41.112405 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 12:17:41.115485 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 12:17:41.122385 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 12:17:41.125401 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 12:17:41.129266 Total UI for P1: 0, mck2ui 16
6665 12:17:41.132366 best dqsien dly found for B0: ( 0, 14, 24)
6666 12:17:41.135643 Total UI for P1: 0, mck2ui 16
6667 12:17:41.138846 best dqsien dly found for B1: ( 0, 14, 24)
6668 12:17:41.142019 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6669 12:17:41.145647 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6670 12:17:41.145717
6671 12:17:41.148622 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6672 12:17:41.155206 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6673 12:17:41.155307 [Gating] SW calibration Done
6674 12:17:41.155397 ==
6675 12:17:41.159224 Dram Type= 6, Freq= 0, CH_1, rank 0
6676 12:17:41.165253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 12:17:41.165351 ==
6678 12:17:41.165439 RX Vref Scan: 0
6679 12:17:41.165515
6680 12:17:41.168851 RX Vref 0 -> 0, step: 1
6681 12:17:41.168921
6682 12:17:41.171717 RX Delay -410 -> 252, step: 16
6683 12:17:41.175433 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6684 12:17:41.178790 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6685 12:17:41.185597 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6686 12:17:41.188793 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6687 12:17:41.192059 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6688 12:17:41.195344 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6689 12:17:41.202261 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6690 12:17:41.205351 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6691 12:17:41.208768 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6692 12:17:41.212045 iDelay=230, Bit 9, Center -27 (-250 ~ 197) 448
6693 12:17:41.215223 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6694 12:17:41.222300 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6695 12:17:41.225647 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6696 12:17:41.228724 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6697 12:17:41.235690 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6698 12:17:41.238775 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6699 12:17:41.238872 ==
6700 12:17:41.242019 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 12:17:41.245397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 12:17:41.245491 ==
6703 12:17:41.248516 DQS Delay:
6704 12:17:41.248585 DQS0 = 19, DQS1 = 27
6705 12:17:41.248644 DQM Delay:
6706 12:17:41.252033 DQM0 = 4, DQM1 = 8
6707 12:17:41.252099 DQ Delay:
6708 12:17:41.255094 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6709 12:17:41.258801 DQ4 =0, DQ5 =16, DQ6 =8, DQ7 =0
6710 12:17:41.261906 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6711 12:17:41.265168 DQ12 =16, DQ13 =8, DQ14 =8, DQ15 =16
6712 12:17:41.265262
6713 12:17:41.265348
6714 12:17:41.265434 ==
6715 12:17:41.268305 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 12:17:41.272111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 12:17:41.272205 ==
6718 12:17:41.272300
6719 12:17:41.272359
6720 12:17:41.275020 TX Vref Scan disable
6721 12:17:41.278440 == TX Byte 0 ==
6722 12:17:41.281862 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6723 12:17:41.285314 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6724 12:17:41.285394 == TX Byte 1 ==
6725 12:17:41.291762 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6726 12:17:41.294931 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6727 12:17:41.295012 ==
6728 12:17:41.298403 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 12:17:41.301947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 12:17:41.302029 ==
6731 12:17:41.302093
6732 12:17:41.302153
6733 12:17:41.305331 TX Vref Scan disable
6734 12:17:41.308176 == TX Byte 0 ==
6735 12:17:41.312078 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6736 12:17:41.315209 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6737 12:17:41.318078 == TX Byte 1 ==
6738 12:17:41.321415 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6739 12:17:41.324846 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6740 12:17:41.324927
6741 12:17:41.324991 [DATLAT]
6742 12:17:41.328140 Freq=400, CH1 RK0
6743 12:17:41.328220
6744 12:17:41.328291 DATLAT Default: 0xf
6745 12:17:41.331352 0, 0xFFFF, sum = 0
6746 12:17:41.331435 1, 0xFFFF, sum = 0
6747 12:17:41.335354 2, 0xFFFF, sum = 0
6748 12:17:41.335452 3, 0xFFFF, sum = 0
6749 12:17:41.338648 4, 0xFFFF, sum = 0
6750 12:17:41.341831 5, 0xFFFF, sum = 0
6751 12:17:41.341913 6, 0xFFFF, sum = 0
6752 12:17:41.345065 7, 0xFFFF, sum = 0
6753 12:17:41.345147 8, 0xFFFF, sum = 0
6754 12:17:41.348394 9, 0xFFFF, sum = 0
6755 12:17:41.348486 10, 0xFFFF, sum = 0
6756 12:17:41.351655 11, 0xFFFF, sum = 0
6757 12:17:41.351736 12, 0xFFFF, sum = 0
6758 12:17:41.354873 13, 0x0, sum = 1
6759 12:17:41.354956 14, 0x0, sum = 2
6760 12:17:41.358211 15, 0x0, sum = 3
6761 12:17:41.358294 16, 0x0, sum = 4
6762 12:17:41.361294 best_step = 14
6763 12:17:41.361375
6764 12:17:41.361438 ==
6765 12:17:41.364803 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 12:17:41.367870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 12:17:41.367951 ==
6768 12:17:41.368014 RX Vref Scan: 1
6769 12:17:41.368074
6770 12:17:41.371753 RX Vref 0 -> 0, step: 1
6771 12:17:41.371886
6772 12:17:41.374794 RX Delay -295 -> 252, step: 8
6773 12:17:41.374875
6774 12:17:41.378010 Set Vref, RX VrefLevel [Byte0]: 53
6775 12:17:41.381183 [Byte1]: 51
6776 12:17:41.385548
6777 12:17:41.385629 Final RX Vref Byte 0 = 53 to rank0
6778 12:17:41.388661 Final RX Vref Byte 1 = 51 to rank0
6779 12:17:41.392161 Final RX Vref Byte 0 = 53 to rank1
6780 12:17:41.395041 Final RX Vref Byte 1 = 51 to rank1==
6781 12:17:41.398835 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 12:17:41.404970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 12:17:41.405052 ==
6784 12:17:41.405115 DQS Delay:
6785 12:17:41.408805 DQS0 = 32, DQS1 = 32
6786 12:17:41.408886 DQM Delay:
6787 12:17:41.408950 DQM0 = 14, DQM1 = 11
6788 12:17:41.411787 DQ Delay:
6789 12:17:41.415079 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6790 12:17:41.415160 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6791 12:17:41.418511 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6792 12:17:41.422043 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6793 12:17:41.422124
6794 12:17:41.425118
6795 12:17:41.431609 [DQSOSCAuto] RK0, (LSB)MR18= 0x8dc6, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6796 12:17:41.435308 CH1 RK0: MR19=C0C, MR18=8DC6
6797 12:17:41.441703 CH1_RK0: MR19=0xC0C, MR18=0x8DC6, DQSOSC=385, MR23=63, INC=398, DEC=265
6798 12:17:41.441785 ==
6799 12:17:41.445100 Dram Type= 6, Freq= 0, CH_1, rank 1
6800 12:17:41.448577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 12:17:41.448659 ==
6802 12:17:41.452451 [Gating] SW mode calibration
6803 12:17:41.458953 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6804 12:17:41.462242 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6805 12:17:41.468993 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6806 12:17:41.472031 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6807 12:17:41.475800 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6808 12:17:41.482042 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6809 12:17:41.485770 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 12:17:41.488917 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 12:17:41.495616 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 12:17:41.498580 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 12:17:41.502038 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6814 12:17:41.505082 Total UI for P1: 0, mck2ui 16
6815 12:17:41.508436 best dqsien dly found for B0: ( 0, 14, 24)
6816 12:17:41.512202 Total UI for P1: 0, mck2ui 16
6817 12:17:41.515307 best dqsien dly found for B1: ( 0, 14, 24)
6818 12:17:41.518576 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6819 12:17:41.521836 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6820 12:17:41.521915
6821 12:17:41.528570 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6822 12:17:41.531800 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6823 12:17:41.531898 [Gating] SW calibration Done
6824 12:17:41.535118 ==
6825 12:17:41.538138 Dram Type= 6, Freq= 0, CH_1, rank 1
6826 12:17:41.541682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6827 12:17:41.541779 ==
6828 12:17:41.541878 RX Vref Scan: 0
6829 12:17:41.541965
6830 12:17:41.545135 RX Vref 0 -> 0, step: 1
6831 12:17:41.545229
6832 12:17:41.548139 RX Delay -410 -> 252, step: 16
6833 12:17:41.551759 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6834 12:17:41.558230 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6835 12:17:41.561645 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6836 12:17:41.565410 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6837 12:17:41.568713 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6838 12:17:41.572022 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6839 12:17:41.578579 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6840 12:17:41.581777 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6841 12:17:41.584997 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6842 12:17:41.588049 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6843 12:17:41.595106 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6844 12:17:41.598405 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6845 12:17:41.601595 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6846 12:17:41.608741 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6847 12:17:41.611657 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6848 12:17:41.615013 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6849 12:17:41.615110 ==
6850 12:17:41.618528 Dram Type= 6, Freq= 0, CH_1, rank 1
6851 12:17:41.621740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 12:17:41.621817 ==
6853 12:17:41.625094 DQS Delay:
6854 12:17:41.625167 DQS0 = 35, DQS1 = 35
6855 12:17:41.628400 DQM Delay:
6856 12:17:41.628472 DQM0 = 17, DQM1 = 14
6857 12:17:41.631432 DQ Delay:
6858 12:17:41.631499 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6859 12:17:41.635220 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6860 12:17:41.638238 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6861 12:17:41.641497 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6862 12:17:41.641570
6863 12:17:41.641629
6864 12:17:41.644777 ==
6865 12:17:41.644869 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 12:17:41.651217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 12:17:41.651314 ==
6868 12:17:41.651404
6869 12:17:41.651487
6870 12:17:41.654803 TX Vref Scan disable
6871 12:17:41.654870 == TX Byte 0 ==
6872 12:17:41.658143 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6873 12:17:41.664367 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6874 12:17:41.664439 == TX Byte 1 ==
6875 12:17:41.667836 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6876 12:17:41.670995 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6877 12:17:41.674743 ==
6878 12:17:41.678024 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 12:17:41.681338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 12:17:41.681408 ==
6881 12:17:41.681468
6882 12:17:41.681525
6883 12:17:41.684788 TX Vref Scan disable
6884 12:17:41.684887 == TX Byte 0 ==
6885 12:17:41.687857 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6886 12:17:41.694204 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6887 12:17:41.694299 == TX Byte 1 ==
6888 12:17:41.698082 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6889 12:17:41.704760 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6890 12:17:41.704854
6891 12:17:41.704941 [DATLAT]
6892 12:17:41.705028 Freq=400, CH1 RK1
6893 12:17:41.705112
6894 12:17:41.707687 DATLAT Default: 0xe
6895 12:17:41.707777 0, 0xFFFF, sum = 0
6896 12:17:41.710971 1, 0xFFFF, sum = 0
6897 12:17:41.711064 2, 0xFFFF, sum = 0
6898 12:17:41.714118 3, 0xFFFF, sum = 0
6899 12:17:41.718005 4, 0xFFFF, sum = 0
6900 12:17:41.718099 5, 0xFFFF, sum = 0
6901 12:17:41.721251 6, 0xFFFF, sum = 0
6902 12:17:41.721353 7, 0xFFFF, sum = 0
6903 12:17:41.724234 8, 0xFFFF, sum = 0
6904 12:17:41.724367 9, 0xFFFF, sum = 0
6905 12:17:41.727732 10, 0xFFFF, sum = 0
6906 12:17:41.727810 11, 0xFFFF, sum = 0
6907 12:17:41.730752 12, 0xFFFF, sum = 0
6908 12:17:41.730851 13, 0x0, sum = 1
6909 12:17:41.734128 14, 0x0, sum = 2
6910 12:17:41.734225 15, 0x0, sum = 3
6911 12:17:41.737709 16, 0x0, sum = 4
6912 12:17:41.737813 best_step = 14
6913 12:17:41.737902
6914 12:17:41.737987 ==
6915 12:17:41.740846 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 12:17:41.744103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 12:17:41.747327 ==
6918 12:17:41.747400 RX Vref Scan: 0
6919 12:17:41.747459
6920 12:17:41.750657 RX Vref 0 -> 0, step: 1
6921 12:17:41.750747
6922 12:17:41.753671 RX Delay -311 -> 252, step: 8
6923 12:17:41.757123 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6924 12:17:41.764168 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6925 12:17:41.767398 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6926 12:17:41.770367 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6927 12:17:41.774011 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6928 12:17:41.780789 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6929 12:17:41.784050 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6930 12:17:41.787268 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6931 12:17:41.790583 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6932 12:17:41.797270 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6933 12:17:41.800572 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6934 12:17:41.803834 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6935 12:17:41.807352 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6936 12:17:41.813818 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6937 12:17:41.817030 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6938 12:17:41.820186 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6939 12:17:41.820292 ==
6940 12:17:41.823407 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 12:17:41.830547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 12:17:41.830630 ==
6943 12:17:41.830695 DQS Delay:
6944 12:17:41.833765 DQS0 = 28, DQS1 = 32
6945 12:17:41.833847 DQM Delay:
6946 12:17:41.833912 DQM0 = 11, DQM1 = 11
6947 12:17:41.837285 DQ Delay:
6948 12:17:41.840245 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6949 12:17:41.843903 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6950 12:17:41.843984 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6951 12:17:41.846931 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6952 12:17:41.850393
6953 12:17:41.850473
6954 12:17:41.856771 [DQSOSCAuto] RK1, (LSB)MR18= 0xc455, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6955 12:17:41.859931 CH1 RK1: MR19=C0C, MR18=C455
6956 12:17:41.867056 CH1_RK1: MR19=0xC0C, MR18=0xC455, DQSOSC=385, MR23=63, INC=398, DEC=265
6957 12:17:41.870541 [RxdqsGatingPostProcess] freq 400
6958 12:17:41.873316 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6959 12:17:41.876946 best DQS0 dly(2T, 0.5T) = (0, 10)
6960 12:17:41.879985 best DQS1 dly(2T, 0.5T) = (0, 10)
6961 12:17:41.883666 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6962 12:17:41.886800 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6963 12:17:41.890057 best DQS0 dly(2T, 0.5T) = (0, 10)
6964 12:17:41.893781 best DQS1 dly(2T, 0.5T) = (0, 10)
6965 12:17:41.896929 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6966 12:17:41.899843 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6967 12:17:41.903290 Pre-setting of DQS Precalculation
6968 12:17:41.906398 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6969 12:17:41.913124 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6970 12:17:41.923197 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6971 12:17:41.923279
6972 12:17:41.923343
6973 12:17:41.926534 [Calibration Summary] 800 Mbps
6974 12:17:41.926640 CH 0, Rank 0
6975 12:17:41.929678 SW Impedance : PASS
6976 12:17:41.929758 DUTY Scan : NO K
6977 12:17:41.932768 ZQ Calibration : PASS
6978 12:17:41.936422 Jitter Meter : NO K
6979 12:17:41.936503 CBT Training : PASS
6980 12:17:41.939901 Write leveling : PASS
6981 12:17:41.939982 RX DQS gating : PASS
6982 12:17:41.942799 RX DQ/DQS(RDDQC) : PASS
6983 12:17:41.946685 TX DQ/DQS : PASS
6984 12:17:41.946766 RX DATLAT : PASS
6985 12:17:41.949936 RX DQ/DQS(Engine): PASS
6986 12:17:41.952775 TX OE : NO K
6987 12:17:41.952856 All Pass.
6988 12:17:41.952920
6989 12:17:41.952979 CH 0, Rank 1
6990 12:17:41.956444 SW Impedance : PASS
6991 12:17:41.959627 DUTY Scan : NO K
6992 12:17:41.959708 ZQ Calibration : PASS
6993 12:17:41.963082 Jitter Meter : NO K
6994 12:17:41.966299 CBT Training : PASS
6995 12:17:41.966381 Write leveling : NO K
6996 12:17:41.970223 RX DQS gating : PASS
6997 12:17:41.973369 RX DQ/DQS(RDDQC) : PASS
6998 12:17:41.973450 TX DQ/DQS : PASS
6999 12:17:41.976617 RX DATLAT : PASS
7000 12:17:41.976698 RX DQ/DQS(Engine): PASS
7001 12:17:41.979730 TX OE : NO K
7002 12:17:41.979810 All Pass.
7003 12:17:41.979875
7004 12:17:41.982973 CH 1, Rank 0
7005 12:17:41.983054 SW Impedance : PASS
7006 12:17:41.986360 DUTY Scan : NO K
7007 12:17:41.989379 ZQ Calibration : PASS
7008 12:17:41.989460 Jitter Meter : NO K
7009 12:17:41.993152 CBT Training : PASS
7010 12:17:41.995854 Write leveling : PASS
7011 12:17:41.995942 RX DQS gating : PASS
7012 12:17:41.999525 RX DQ/DQS(RDDQC) : PASS
7013 12:17:42.002650 TX DQ/DQS : PASS
7014 12:17:42.002772 RX DATLAT : PASS
7015 12:17:42.006213 RX DQ/DQS(Engine): PASS
7016 12:17:42.009256 TX OE : NO K
7017 12:17:42.009337 All Pass.
7018 12:17:42.009401
7019 12:17:42.009460 CH 1, Rank 1
7020 12:17:42.012517 SW Impedance : PASS
7021 12:17:42.016100 DUTY Scan : NO K
7022 12:17:42.016180 ZQ Calibration : PASS
7023 12:17:42.019187 Jitter Meter : NO K
7024 12:17:42.022424 CBT Training : PASS
7025 12:17:42.022536 Write leveling : NO K
7026 12:17:42.025567 RX DQS gating : PASS
7027 12:17:42.029127 RX DQ/DQS(RDDQC) : PASS
7028 12:17:42.029232 TX DQ/DQS : PASS
7029 12:17:42.032493 RX DATLAT : PASS
7030 12:17:42.035695 RX DQ/DQS(Engine): PASS
7031 12:17:42.035794 TX OE : NO K
7032 12:17:42.038754 All Pass.
7033 12:17:42.038850
7034 12:17:42.038937 DramC Write-DBI off
7035 12:17:42.042373 PER_BANK_REFRESH: Hybrid Mode
7036 12:17:42.042477 TX_TRACKING: ON
7037 12:17:42.052543 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7038 12:17:42.056030 [FAST_K] Save calibration result to emmc
7039 12:17:42.058832 dramc_set_vcore_voltage set vcore to 725000
7040 12:17:42.061997 Read voltage for 1600, 0
7041 12:17:42.062068 Vio18 = 0
7042 12:17:42.065875 Vcore = 725000
7043 12:17:42.065973 Vdram = 0
7044 12:17:42.066060 Vddq = 0
7045 12:17:42.066144 Vmddr = 0
7046 12:17:42.072466 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7047 12:17:42.079081 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7048 12:17:42.079156 MEM_TYPE=3, freq_sel=13
7049 12:17:42.082534 sv_algorithm_assistance_LP4_3733
7050 12:17:42.085584 ============ PULL DRAM RESETB DOWN ============
7051 12:17:42.092130 ========== PULL DRAM RESETB DOWN end =========
7052 12:17:42.095342 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7053 12:17:42.098682 ===================================
7054 12:17:42.101930 LPDDR4 DRAM CONFIGURATION
7055 12:17:42.105567 ===================================
7056 12:17:42.105634 EX_ROW_EN[0] = 0x0
7057 12:17:42.108833 EX_ROW_EN[1] = 0x0
7058 12:17:42.108915 LP4Y_EN = 0x0
7059 12:17:42.112124 WORK_FSP = 0x1
7060 12:17:42.115670 WL = 0x5
7061 12:17:42.115751 RL = 0x5
7062 12:17:42.118847 BL = 0x2
7063 12:17:42.118931 RPST = 0x0
7064 12:17:42.122373 RD_PRE = 0x0
7065 12:17:42.122455 WR_PRE = 0x1
7066 12:17:42.125594 WR_PST = 0x1
7067 12:17:42.125676 DBI_WR = 0x0
7068 12:17:42.129018 DBI_RD = 0x0
7069 12:17:42.129099 OTF = 0x1
7070 12:17:42.132242 ===================================
7071 12:17:42.135342 ===================================
7072 12:17:42.138701 ANA top config
7073 12:17:42.142289 ===================================
7074 12:17:42.142370 DLL_ASYNC_EN = 0
7075 12:17:42.145305 ALL_SLAVE_EN = 0
7076 12:17:42.148602 NEW_RANK_MODE = 1
7077 12:17:42.151753 DLL_IDLE_MODE = 1
7078 12:17:42.151833 LP45_APHY_COMB_EN = 1
7079 12:17:42.155256 TX_ODT_DIS = 0
7080 12:17:42.158350 NEW_8X_MODE = 1
7081 12:17:42.162038 ===================================
7082 12:17:42.165048 ===================================
7083 12:17:42.168586 data_rate = 3200
7084 12:17:42.171763 CKR = 1
7085 12:17:42.175071 DQ_P2S_RATIO = 8
7086 12:17:42.178251 ===================================
7087 12:17:42.178332 CA_P2S_RATIO = 8
7088 12:17:42.181664 DQ_CA_OPEN = 0
7089 12:17:42.184744 DQ_SEMI_OPEN = 0
7090 12:17:42.188484 CA_SEMI_OPEN = 0
7091 12:17:42.191534 CA_FULL_RATE = 0
7092 12:17:42.195227 DQ_CKDIV4_EN = 0
7093 12:17:42.195308 CA_CKDIV4_EN = 0
7094 12:17:42.198504 CA_PREDIV_EN = 0
7095 12:17:42.201538 PH8_DLY = 12
7096 12:17:42.204797 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7097 12:17:42.208700 DQ_AAMCK_DIV = 4
7098 12:17:42.211335 CA_AAMCK_DIV = 4
7099 12:17:42.211416 CA_ADMCK_DIV = 4
7100 12:17:42.214986 DQ_TRACK_CA_EN = 0
7101 12:17:42.217992 CA_PICK = 1600
7102 12:17:42.221407 CA_MCKIO = 1600
7103 12:17:42.224586 MCKIO_SEMI = 0
7104 12:17:42.227793 PLL_FREQ = 3068
7105 12:17:42.231409 DQ_UI_PI_RATIO = 32
7106 12:17:42.235079 CA_UI_PI_RATIO = 0
7107 12:17:42.238250 ===================================
7108 12:17:42.241431 ===================================
7109 12:17:42.241512 memory_type:LPDDR4
7110 12:17:42.244499 GP_NUM : 10
7111 12:17:42.244581 SRAM_EN : 1
7112 12:17:42.247649 MD32_EN : 0
7113 12:17:42.251520 ===================================
7114 12:17:42.254820 [ANA_INIT] >>>>>>>>>>>>>>
7115 12:17:42.258142 <<<<<< [CONFIGURE PHASE]: ANA_TX
7116 12:17:42.261375 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7117 12:17:42.264700 ===================================
7118 12:17:42.267922 data_rate = 3200,PCW = 0X7600
7119 12:17:42.271057 ===================================
7120 12:17:42.274672 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7121 12:17:42.277473 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7122 12:17:42.284707 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7123 12:17:42.287527 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7124 12:17:42.291077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7125 12:17:42.294014 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7126 12:17:42.297300 [ANA_INIT] flow start
7127 12:17:42.301064 [ANA_INIT] PLL >>>>>>>>
7128 12:17:42.301155 [ANA_INIT] PLL <<<<<<<<
7129 12:17:42.304202 [ANA_INIT] MIDPI >>>>>>>>
7130 12:17:42.307688 [ANA_INIT] MIDPI <<<<<<<<
7131 12:17:42.307788 [ANA_INIT] DLL >>>>>>>>
7132 12:17:42.310941 [ANA_INIT] DLL <<<<<<<<
7133 12:17:42.314084 [ANA_INIT] flow end
7134 12:17:42.317413 ============ LP4 DIFF to SE enter ============
7135 12:17:42.321112 ============ LP4 DIFF to SE exit ============
7136 12:17:42.324322 [ANA_INIT] <<<<<<<<<<<<<
7137 12:17:42.327489 [Flow] Enable top DCM control >>>>>
7138 12:17:42.330669 [Flow] Enable top DCM control <<<<<
7139 12:17:42.334021 Enable DLL master slave shuffle
7140 12:17:42.337848 ==============================================================
7141 12:17:42.340485 Gating Mode config
7142 12:17:42.347188 ==============================================================
7143 12:17:42.347290 Config description:
7144 12:17:42.357247 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7145 12:17:42.363904 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7146 12:17:42.370265 SELPH_MODE 0: By rank 1: By Phase
7147 12:17:42.373511 ==============================================================
7148 12:17:42.377134 GAT_TRACK_EN = 1
7149 12:17:42.380383 RX_GATING_MODE = 2
7150 12:17:42.384026 RX_GATING_TRACK_MODE = 2
7151 12:17:42.386897 SELPH_MODE = 1
7152 12:17:42.390250 PICG_EARLY_EN = 1
7153 12:17:42.393739 VALID_LAT_VALUE = 1
7154 12:17:42.397048 ==============================================================
7155 12:17:42.400127 Enter into Gating configuration >>>>
7156 12:17:42.403412 Exit from Gating configuration <<<<
7157 12:17:42.406541 Enter into DVFS_PRE_config >>>>>
7158 12:17:42.420200 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7159 12:17:42.423505 Exit from DVFS_PRE_config <<<<<
7160 12:17:42.426556 Enter into PICG configuration >>>>
7161 12:17:42.426654 Exit from PICG configuration <<<<
7162 12:17:42.430311 [RX_INPUT] configuration >>>>>
7163 12:17:42.433506 [RX_INPUT] configuration <<<<<
7164 12:17:42.439933 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7165 12:17:42.443042 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7166 12:17:42.450054 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7167 12:17:42.456416 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7168 12:17:42.463367 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7169 12:17:42.470042 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7170 12:17:42.473572 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7171 12:17:42.476253 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7172 12:17:42.480011 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7173 12:17:42.486261 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7174 12:17:42.489778 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7175 12:17:42.492800 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7176 12:17:42.496460 ===================================
7177 12:17:42.499717 LPDDR4 DRAM CONFIGURATION
7178 12:17:42.503071 ===================================
7179 12:17:42.506793 EX_ROW_EN[0] = 0x0
7180 12:17:42.506896 EX_ROW_EN[1] = 0x0
7181 12:17:42.509739 LP4Y_EN = 0x0
7182 12:17:42.509824 WORK_FSP = 0x1
7183 12:17:42.512897 WL = 0x5
7184 12:17:42.513000 RL = 0x5
7185 12:17:42.516107 BL = 0x2
7186 12:17:42.516187 RPST = 0x0
7187 12:17:42.519914 RD_PRE = 0x0
7188 12:17:42.520010 WR_PRE = 0x1
7189 12:17:42.523518 WR_PST = 0x1
7190 12:17:42.523594 DBI_WR = 0x0
7191 12:17:42.526468 DBI_RD = 0x0
7192 12:17:42.526566 OTF = 0x1
7193 12:17:42.529596 ===================================
7194 12:17:42.536435 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7195 12:17:42.539823 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7196 12:17:42.542894 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7197 12:17:42.545976 ===================================
7198 12:17:42.549912 LPDDR4 DRAM CONFIGURATION
7199 12:17:42.552991 ===================================
7200 12:17:42.553063 EX_ROW_EN[0] = 0x10
7201 12:17:42.556169 EX_ROW_EN[1] = 0x0
7202 12:17:42.559392 LP4Y_EN = 0x0
7203 12:17:42.559462 WORK_FSP = 0x1
7204 12:17:42.563215 WL = 0x5
7205 12:17:42.563317 RL = 0x5
7206 12:17:42.566263 BL = 0x2
7207 12:17:42.566358 RPST = 0x0
7208 12:17:42.569441 RD_PRE = 0x0
7209 12:17:42.569512 WR_PRE = 0x1
7210 12:17:42.572738 WR_PST = 0x1
7211 12:17:42.572814 DBI_WR = 0x0
7212 12:17:42.576085 DBI_RD = 0x0
7213 12:17:42.576151 OTF = 0x1
7214 12:17:42.579264 ===================================
7215 12:17:42.586267 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7216 12:17:42.586342 ==
7217 12:17:42.589355 Dram Type= 6, Freq= 0, CH_0, rank 0
7218 12:17:42.593009 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7219 12:17:42.596539 ==
7220 12:17:42.596609 [Duty_Offset_Calibration]
7221 12:17:42.599790 B0:2 B1:1 CA:1
7222 12:17:42.599888
7223 12:17:42.603062 [DutyScan_Calibration_Flow] k_type=0
7224 12:17:42.611756
7225 12:17:42.611842 ==CLK 0==
7226 12:17:42.615006 Final CLK duty delay cell = 0
7227 12:17:42.618431 [0] MAX Duty = 5156%(X100), DQS PI = 22
7228 12:17:42.621656 [0] MIN Duty = 4876%(X100), DQS PI = 0
7229 12:17:42.621758 [0] AVG Duty = 5016%(X100)
7230 12:17:42.624839
7231 12:17:42.628110 CH0 CLK Duty spec in!! Max-Min= 280%
7232 12:17:42.631600 [DutyScan_Calibration_Flow] ====Done====
7233 12:17:42.631712
7234 12:17:42.634939 [DutyScan_Calibration_Flow] k_type=1
7235 12:17:42.650596
7236 12:17:42.650695 ==DQS 0 ==
7237 12:17:42.654044 Final DQS duty delay cell = -4
7238 12:17:42.657364 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7239 12:17:42.660744 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7240 12:17:42.663864 [-4] AVG Duty = 4891%(X100)
7241 12:17:42.663964
7242 12:17:42.664057 ==DQS 1 ==
7243 12:17:42.667099 Final DQS duty delay cell = 0
7244 12:17:42.671101 [0] MAX Duty = 5187%(X100), DQS PI = 4
7245 12:17:42.673888 [0] MIN Duty = 5031%(X100), DQS PI = 32
7246 12:17:42.677195 [0] AVG Duty = 5109%(X100)
7247 12:17:42.677270
7248 12:17:42.680786 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7249 12:17:42.680887
7250 12:17:42.684034 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7251 12:17:42.687217 [DutyScan_Calibration_Flow] ====Done====
7252 12:17:42.687321
7253 12:17:42.690420 [DutyScan_Calibration_Flow] k_type=3
7254 12:17:42.707539
7255 12:17:42.707639 ==DQM 0 ==
7256 12:17:42.710480 Final DQM duty delay cell = 0
7257 12:17:42.714245 [0] MAX Duty = 5187%(X100), DQS PI = 32
7258 12:17:42.717438 [0] MIN Duty = 4875%(X100), DQS PI = 58
7259 12:17:42.720487 [0] AVG Duty = 5031%(X100)
7260 12:17:42.720585
7261 12:17:42.720672 ==DQM 1 ==
7262 12:17:42.723895 Final DQM duty delay cell = -4
7263 12:17:42.727471 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7264 12:17:42.730950 [-4] MIN Duty = 4813%(X100), DQS PI = 14
7265 12:17:42.734340 [-4] AVG Duty = 4891%(X100)
7266 12:17:42.734435
7267 12:17:42.737130 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7268 12:17:42.737200
7269 12:17:42.740642 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7270 12:17:42.743968 [DutyScan_Calibration_Flow] ====Done====
7271 12:17:42.744065
7272 12:17:42.747168 [DutyScan_Calibration_Flow] k_type=2
7273 12:17:42.765385
7274 12:17:42.765489 ==DQ 0 ==
7275 12:17:42.768515 Final DQ duty delay cell = 0
7276 12:17:42.771884 [0] MAX Duty = 5062%(X100), DQS PI = 24
7277 12:17:42.774697 [0] MIN Duty = 4907%(X100), DQS PI = 0
7278 12:17:42.774793 [0] AVG Duty = 4984%(X100)
7279 12:17:42.774890
7280 12:17:42.778653 ==DQ 1 ==
7281 12:17:42.781710 Final DQ duty delay cell = 0
7282 12:17:42.784985 [0] MAX Duty = 5124%(X100), DQS PI = 22
7283 12:17:42.788217 [0] MIN Duty = 4907%(X100), DQS PI = 34
7284 12:17:42.788352 [0] AVG Duty = 5015%(X100)
7285 12:17:42.788436
7286 12:17:42.791473 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7287 12:17:42.794602
7288 12:17:42.798434 CH0 DQ 1 Duty spec in!! Max-Min= 217%
7289 12:17:42.801653 [DutyScan_Calibration_Flow] ====Done====
7290 12:17:42.801723 ==
7291 12:17:42.804918 Dram Type= 6, Freq= 0, CH_1, rank 0
7292 12:17:42.808102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7293 12:17:42.808198 ==
7294 12:17:42.811137 [Duty_Offset_Calibration]
7295 12:17:42.811238 B0:1 B1:0 CA:0
7296 12:17:42.811325
7297 12:17:42.814697 [DutyScan_Calibration_Flow] k_type=0
7298 12:17:42.824093
7299 12:17:42.824201 ==CLK 0==
7300 12:17:42.827797 Final CLK duty delay cell = -4
7301 12:17:42.830626 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7302 12:17:42.834236 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7303 12:17:42.837487 [-4] AVG Duty = 4906%(X100)
7304 12:17:42.837582
7305 12:17:42.840676 CH1 CLK Duty spec in!! Max-Min= 125%
7306 12:17:42.844274 [DutyScan_Calibration_Flow] ====Done====
7307 12:17:42.844408
7308 12:17:42.847349 [DutyScan_Calibration_Flow] k_type=1
7309 12:17:42.864097
7310 12:17:42.864202 ==DQS 0 ==
7311 12:17:42.867935 Final DQS duty delay cell = 0
7312 12:17:42.870877 [0] MAX Duty = 5094%(X100), DQS PI = 32
7313 12:17:42.874699 [0] MIN Duty = 4844%(X100), DQS PI = 46
7314 12:17:42.874796 [0] AVG Duty = 4969%(X100)
7315 12:17:42.877792
7316 12:17:42.877863 ==DQS 1 ==
7317 12:17:42.880924 Final DQS duty delay cell = 0
7318 12:17:42.884485 [0] MAX Duty = 5281%(X100), DQS PI = 18
7319 12:17:42.887422 [0] MIN Duty = 4969%(X100), DQS PI = 6
7320 12:17:42.887517 [0] AVG Duty = 5125%(X100)
7321 12:17:42.890806
7322 12:17:42.894274 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7323 12:17:42.894368
7324 12:17:42.897862 CH1 DQS 1 Duty spec in!! Max-Min= 312%
7325 12:17:42.900808 [DutyScan_Calibration_Flow] ====Done====
7326 12:17:42.900902
7327 12:17:42.904089 [DutyScan_Calibration_Flow] k_type=3
7328 12:17:42.921382
7329 12:17:42.921482 ==DQM 0 ==
7330 12:17:42.924257 Final DQM duty delay cell = 0
7331 12:17:42.927595 [0] MAX Duty = 5218%(X100), DQS PI = 18
7332 12:17:42.931391 [0] MIN Duty = 4969%(X100), DQS PI = 48
7333 12:17:42.934506 [0] AVG Duty = 5093%(X100)
7334 12:17:42.934605
7335 12:17:42.934693 ==DQM 1 ==
7336 12:17:42.937446 Final DQM duty delay cell = 0
7337 12:17:42.940979 [0] MAX Duty = 5093%(X100), DQS PI = 16
7338 12:17:42.944686 [0] MIN Duty = 4907%(X100), DQS PI = 32
7339 12:17:42.944761 [0] AVG Duty = 5000%(X100)
7340 12:17:42.948017
7341 12:17:42.951148 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7342 12:17:42.951249
7343 12:17:42.954297 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7344 12:17:42.957995 [DutyScan_Calibration_Flow] ====Done====
7345 12:17:42.958092
7346 12:17:42.961075 [DutyScan_Calibration_Flow] k_type=2
7347 12:17:42.977755
7348 12:17:42.977832 ==DQ 0 ==
7349 12:17:42.980467 Final DQ duty delay cell = -4
7350 12:17:42.984195 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7351 12:17:42.987377 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7352 12:17:42.990701 [-4] AVG Duty = 4953%(X100)
7353 12:17:42.990776
7354 12:17:42.990837 ==DQ 1 ==
7355 12:17:42.993929 Final DQ duty delay cell = 0
7356 12:17:42.997663 [0] MAX Duty = 5124%(X100), DQS PI = 18
7357 12:17:43.000583 [0] MIN Duty = 4938%(X100), DQS PI = 8
7358 12:17:43.000677 [0] AVG Duty = 5031%(X100)
7359 12:17:43.004096
7360 12:17:43.007119 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7361 12:17:43.007212
7362 12:17:43.010310 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7363 12:17:43.013597 [DutyScan_Calibration_Flow] ====Done====
7364 12:17:43.017321 nWR fixed to 30
7365 12:17:43.020483 [ModeRegInit_LP4] CH0 RK0
7366 12:17:43.020581 [ModeRegInit_LP4] CH0 RK1
7367 12:17:43.023581 [ModeRegInit_LP4] CH1 RK0
7368 12:17:43.027289 [ModeRegInit_LP4] CH1 RK1
7369 12:17:43.027385 match AC timing 5
7370 12:17:43.033890 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7371 12:17:43.037133 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7372 12:17:43.040479 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7373 12:17:43.046536 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7374 12:17:43.050048 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7375 12:17:43.050146 [MiockJmeterHQA]
7376 12:17:43.050241
7377 12:17:43.053703 [DramcMiockJmeter] u1RxGatingPI = 0
7378 12:17:43.056794 0 : 4362, 4137
7379 12:17:43.056865 4 : 4363, 4137
7380 12:17:43.059943 8 : 4252, 4027
7381 12:17:43.060037 12 : 4252, 4027
7382 12:17:43.063161 16 : 4252, 4027
7383 12:17:43.063254 20 : 4254, 4029
7384 12:17:43.063345 24 : 4252, 4026
7385 12:17:43.066207 28 : 4253, 4027
7386 12:17:43.066302 32 : 4365, 4140
7387 12:17:43.069958 36 : 4252, 4027
7388 12:17:43.070041 40 : 4255, 4029
7389 12:17:43.072976 44 : 4252, 4027
7390 12:17:43.073058 48 : 4363, 4137
7391 12:17:43.076647 52 : 4252, 4027
7392 12:17:43.076729 56 : 4363, 4138
7393 12:17:43.076794 60 : 4253, 4027
7394 12:17:43.080074 64 : 4250, 4027
7395 12:17:43.080156 68 : 4250, 4027
7396 12:17:43.083105 72 : 4252, 4029
7397 12:17:43.083188 76 : 4360, 4138
7398 12:17:43.086352 80 : 4250, 4027
7399 12:17:43.086434 84 : 4361, 4137
7400 12:17:43.090044 88 : 4250, 145
7401 12:17:43.090126 92 : 4252, 0
7402 12:17:43.090191 96 : 4253, 0
7403 12:17:43.093048 100 : 4363, 0
7404 12:17:43.093130 104 : 4361, 0
7405 12:17:43.093195 108 : 4363, 0
7406 12:17:43.096124 112 : 4250, 0
7407 12:17:43.096205 116 : 4250, 0
7408 12:17:43.099454 120 : 4250, 0
7409 12:17:43.099535 124 : 4252, 0
7410 12:17:43.099600 128 : 4250, 0
7411 12:17:43.102780 132 : 4250, 0
7412 12:17:43.102862 136 : 4252, 0
7413 12:17:43.106305 140 : 4250, 0
7414 12:17:43.106387 144 : 4250, 0
7415 12:17:43.106452 148 : 4252, 0
7416 12:17:43.109829 152 : 4250, 0
7417 12:17:43.109913 156 : 4361, 0
7418 12:17:43.109978 160 : 4250, 0
7419 12:17:43.112737 164 : 4253, 0
7420 12:17:43.112819 168 : 4360, 0
7421 12:17:43.116075 172 : 4250, 0
7422 12:17:43.116181 176 : 4250, 0
7423 12:17:43.116273 180 : 4250, 0
7424 12:17:43.119693 184 : 4250, 0
7425 12:17:43.119796 188 : 4253, 0
7426 12:17:43.123138 192 : 4360, 0
7427 12:17:43.123242 196 : 4250, 0
7428 12:17:43.123334 200 : 4250, 0
7429 12:17:43.126311 204 : 4361, 1330
7430 12:17:43.126413 208 : 4249, 3976
7431 12:17:43.129436 212 : 4250, 4026
7432 12:17:43.129507 216 : 4361, 4137
7433 12:17:43.132545 220 : 4360, 4138
7434 12:17:43.132617 224 : 4249, 4027
7435 12:17:43.136352 228 : 4363, 4140
7436 12:17:43.136421 232 : 4360, 4138
7437 12:17:43.139716 236 : 4252, 4027
7438 12:17:43.139814 240 : 4250, 4027
7439 12:17:43.143048 244 : 4252, 4029
7440 12:17:43.143144 248 : 4250, 4026
7441 12:17:43.143232 252 : 4250, 4027
7442 12:17:43.146174 256 : 4250, 4027
7443 12:17:43.146271 260 : 4252, 4029
7444 12:17:43.149379 264 : 4250, 4026
7445 12:17:43.149448 268 : 4360, 4138
7446 12:17:43.153070 272 : 4360, 4138
7447 12:17:43.153139 276 : 4249, 4027
7448 12:17:43.156073 280 : 4363, 4140
7449 12:17:43.156171 284 : 4360, 4137
7450 12:17:43.159380 288 : 4250, 4027
7451 12:17:43.159448 292 : 4253, 4027
7452 12:17:43.162557 296 : 4252, 4029
7453 12:17:43.162655 300 : 4250, 4026
7454 12:17:43.165833 304 : 4250, 4027
7455 12:17:43.165928 308 : 4250, 3904
7456 12:17:43.166019 312 : 4252, 1815
7457 12:17:43.169070
7458 12:17:43.169162 MIOCK jitter meter ch=0
7459 12:17:43.169251
7460 12:17:43.172747 1T = (312-88) = 224 dly cells
7461 12:17:43.179031 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7462 12:17:43.179131 ==
7463 12:17:43.182511 Dram Type= 6, Freq= 0, CH_0, rank 0
7464 12:17:43.186018 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7465 12:17:43.186092 ==
7466 12:17:43.192513 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7467 12:17:43.195814 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7468 12:17:43.198993 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7469 12:17:43.205902 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7470 12:17:43.215011 [CA 0] Center 42 (12~73) winsize 62
7471 12:17:43.218345 [CA 1] Center 42 (12~73) winsize 62
7472 12:17:43.221640 [CA 2] Center 38 (8~68) winsize 61
7473 12:17:43.224854 [CA 3] Center 37 (8~67) winsize 60
7474 12:17:43.228197 [CA 4] Center 36 (6~66) winsize 61
7475 12:17:43.231805 [CA 5] Center 35 (6~64) winsize 59
7476 12:17:43.231882
7477 12:17:43.235067 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7478 12:17:43.235169
7479 12:17:43.238607 [CATrainingPosCal] consider 1 rank data
7480 12:17:43.241955 u2DelayCellTimex100 = 290/100 ps
7481 12:17:43.245115 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7482 12:17:43.251451 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7483 12:17:43.254858 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7484 12:17:43.258539 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7485 12:17:43.261524 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7486 12:17:43.265264 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7487 12:17:43.265333
7488 12:17:43.268396 CA PerBit enable=1, Macro0, CA PI delay=35
7489 12:17:43.268464
7490 12:17:43.271342 [CBTSetCACLKResult] CA Dly = 35
7491 12:17:43.271440 CS Dly: 9 (0~40)
7492 12:17:43.278352 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7493 12:17:43.281559 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7494 12:17:43.281643 ==
7495 12:17:43.285154 Dram Type= 6, Freq= 0, CH_0, rank 1
7496 12:17:43.288193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7497 12:17:43.288357 ==
7498 12:17:43.295120 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7499 12:17:43.298458 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7500 12:17:43.304698 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7501 12:17:43.307798 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7502 12:17:43.318119 [CA 0] Center 43 (13~73) winsize 61
7503 12:17:43.322318 [CA 1] Center 42 (12~73) winsize 62
7504 12:17:43.325083 [CA 2] Center 37 (8~67) winsize 60
7505 12:17:43.328167 [CA 3] Center 37 (7~67) winsize 61
7506 12:17:43.331559 [CA 4] Center 35 (5~65) winsize 61
7507 12:17:43.334889 [CA 5] Center 35 (5~65) winsize 61
7508 12:17:43.334983
7509 12:17:43.338135 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7510 12:17:43.338247
7511 12:17:43.341481 [CATrainingPosCal] consider 2 rank data
7512 12:17:43.344774 u2DelayCellTimex100 = 290/100 ps
7513 12:17:43.348209 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7514 12:17:43.354929 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7515 12:17:43.358080 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7516 12:17:43.361389 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7517 12:17:43.364959 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7518 12:17:43.368207 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7519 12:17:43.368305
7520 12:17:43.371333 CA PerBit enable=1, Macro0, CA PI delay=35
7521 12:17:43.371408
7522 12:17:43.374888 [CBTSetCACLKResult] CA Dly = 35
7523 12:17:43.378195 CS Dly: 10 (0~42)
7524 12:17:43.381178 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7525 12:17:43.384988 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7526 12:17:43.385058
7527 12:17:43.387991 ----->DramcWriteLeveling(PI) begin...
7528 12:17:43.388067 ==
7529 12:17:43.391237 Dram Type= 6, Freq= 0, CH_0, rank 0
7530 12:17:43.394767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7531 12:17:43.398201 ==
7532 12:17:43.398268 Write leveling (Byte 0): 35 => 35
7533 12:17:43.401200 Write leveling (Byte 1): 29 => 29
7534 12:17:43.404866 DramcWriteLeveling(PI) end<-----
7535 12:17:43.404959
7536 12:17:43.405048 ==
7537 12:17:43.408032 Dram Type= 6, Freq= 0, CH_0, rank 0
7538 12:17:43.414732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 12:17:43.414828 ==
7540 12:17:43.418110 [Gating] SW mode calibration
7541 12:17:43.424426 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7542 12:17:43.427742 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7543 12:17:43.435010 1 4 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7544 12:17:43.437476 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7545 12:17:43.441345 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7546 12:17:43.447956 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7547 12:17:43.450950 1 4 16 | B1->B0 | 2424 3636 | 0 0 | (0 0) (0 0)
7548 12:17:43.454102 1 4 20 | B1->B0 | 3030 3737 | 0 1 | (0 0) (1 1)
7549 12:17:43.461089 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7550 12:17:43.464199 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7551 12:17:43.467791 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7552 12:17:43.474069 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7553 12:17:43.477543 1 5 8 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7554 12:17:43.480671 1 5 12 | B1->B0 | 3434 3231 | 1 1 | (1 1) (0 1)
7555 12:17:43.484137 1 5 16 | B1->B0 | 3434 2827 | 1 1 | (1 0) (0 0)
7556 12:17:43.490540 1 5 20 | B1->B0 | 2525 2a29 | 0 1 | (1 0) (0 0)
7557 12:17:43.493746 1 5 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7558 12:17:43.497288 1 5 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7559 12:17:43.503984 1 6 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7560 12:17:43.507219 1 6 4 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (1 1)
7561 12:17:43.510351 1 6 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
7562 12:17:43.517150 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7563 12:17:43.520392 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (1 1) (0 0)
7564 12:17:43.524226 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7565 12:17:43.530539 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 12:17:43.533707 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7567 12:17:43.537470 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 12:17:43.543586 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 12:17:43.546811 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 12:17:43.550634 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7571 12:17:43.557298 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7572 12:17:43.560114 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7573 12:17:43.563551 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 12:17:43.570160 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 12:17:43.573891 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 12:17:43.577188 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 12:17:43.583486 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 12:17:43.586787 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 12:17:43.590465 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 12:17:43.596732 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 12:17:43.600008 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 12:17:43.603419 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 12:17:43.609999 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 12:17:43.613076 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 12:17:43.616501 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7586 12:17:43.623236 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7587 12:17:43.626390 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7588 12:17:43.629740 Total UI for P1: 0, mck2ui 16
7589 12:17:43.632979 best dqsien dly found for B0: ( 1, 9, 10)
7590 12:17:43.636815 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7591 12:17:43.643071 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7592 12:17:43.643172 Total UI for P1: 0, mck2ui 16
7593 12:17:43.646284 best dqsien dly found for B1: ( 1, 9, 18)
7594 12:17:43.652812 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7595 12:17:43.656478 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7596 12:17:43.656551
7597 12:17:43.659354 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7598 12:17:43.663278 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7599 12:17:43.666289 [Gating] SW calibration Done
7600 12:17:43.666387 ==
7601 12:17:43.669954 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 12:17:43.673123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 12:17:43.673195 ==
7604 12:17:43.676404 RX Vref Scan: 0
7605 12:17:43.676482
7606 12:17:43.676543 RX Vref 0 -> 0, step: 1
7607 12:17:43.676600
7608 12:17:43.679393 RX Delay 0 -> 252, step: 8
7609 12:17:43.683326 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7610 12:17:43.689749 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7611 12:17:43.692977 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7612 12:17:43.696161 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7613 12:17:43.699378 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7614 12:17:43.703014 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7615 12:17:43.706728 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7616 12:17:43.713093 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7617 12:17:43.716418 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7618 12:17:43.719404 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7619 12:17:43.722967 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7620 12:17:43.726338 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7621 12:17:43.732834 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7622 12:17:43.735870 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7623 12:17:43.739570 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7624 12:17:43.743158 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7625 12:17:43.743258 ==
7626 12:17:43.746327 Dram Type= 6, Freq= 0, CH_0, rank 0
7627 12:17:43.752390 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7628 12:17:43.752467 ==
7629 12:17:43.752534 DQS Delay:
7630 12:17:43.756330 DQS0 = 0, DQS1 = 0
7631 12:17:43.756403 DQM Delay:
7632 12:17:43.759443 DQM0 = 136, DQM1 = 130
7633 12:17:43.759511 DQ Delay:
7634 12:17:43.762569 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7635 12:17:43.765677 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7636 12:17:43.769568 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7637 12:17:43.772648 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7638 12:17:43.772720
7639 12:17:43.772780
7640 12:17:43.772836 ==
7641 12:17:43.775851 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 12:17:43.782399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 12:17:43.782472 ==
7644 12:17:43.782533
7645 12:17:43.782621
7646 12:17:43.782705 TX Vref Scan disable
7647 12:17:43.785795 == TX Byte 0 ==
7648 12:17:43.788867 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7649 12:17:43.792596 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7650 12:17:43.795944 == TX Byte 1 ==
7651 12:17:43.799090 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7652 12:17:43.802247 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7653 12:17:43.806107 ==
7654 12:17:43.809371 Dram Type= 6, Freq= 0, CH_0, rank 0
7655 12:17:43.812352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7656 12:17:43.812423 ==
7657 12:17:43.825116
7658 12:17:43.828149 TX Vref early break, caculate TX vref
7659 12:17:43.831913 TX Vref=16, minBit 1, minWin=22, winSum=379
7660 12:17:43.834930 TX Vref=18, minBit 0, minWin=23, winSum=389
7661 12:17:43.838602 TX Vref=20, minBit 0, minWin=24, winSum=399
7662 12:17:43.842009 TX Vref=22, minBit 0, minWin=25, winSum=412
7663 12:17:43.845284 TX Vref=24, minBit 2, minWin=25, winSum=418
7664 12:17:43.851768 TX Vref=26, minBit 0, minWin=26, winSum=430
7665 12:17:43.854895 TX Vref=28, minBit 1, minWin=25, winSum=426
7666 12:17:43.858296 TX Vref=30, minBit 1, minWin=24, winSum=414
7667 12:17:43.861875 TX Vref=32, minBit 1, minWin=24, winSum=408
7668 12:17:43.864905 TX Vref=34, minBit 1, minWin=23, winSum=393
7669 12:17:43.871815 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 26
7670 12:17:43.871892
7671 12:17:43.875079 Final TX Range 0 Vref 26
7672 12:17:43.875152
7673 12:17:43.875218 ==
7674 12:17:43.878226 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 12:17:43.881444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 12:17:43.881540 ==
7677 12:17:43.881638
7678 12:17:43.881723
7679 12:17:43.884800 TX Vref Scan disable
7680 12:17:43.891466 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7681 12:17:43.891564 == TX Byte 0 ==
7682 12:17:43.895229 u2DelayCellOfst[0]=10 cells (3 PI)
7683 12:17:43.898334 u2DelayCellOfst[1]=13 cells (4 PI)
7684 12:17:43.901834 u2DelayCellOfst[2]=10 cells (3 PI)
7685 12:17:43.905006 u2DelayCellOfst[3]=10 cells (3 PI)
7686 12:17:43.908158 u2DelayCellOfst[4]=6 cells (2 PI)
7687 12:17:43.911506 u2DelayCellOfst[5]=0 cells (0 PI)
7688 12:17:43.914813 u2DelayCellOfst[6]=16 cells (5 PI)
7689 12:17:43.914907 u2DelayCellOfst[7]=16 cells (5 PI)
7690 12:17:43.921448 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7691 12:17:43.924985 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7692 12:17:43.925061 == TX Byte 1 ==
7693 12:17:43.928406 u2DelayCellOfst[8]=0 cells (0 PI)
7694 12:17:43.931536 u2DelayCellOfst[9]=3 cells (1 PI)
7695 12:17:43.934713 u2DelayCellOfst[10]=6 cells (2 PI)
7696 12:17:43.938363 u2DelayCellOfst[11]=6 cells (2 PI)
7697 12:17:43.941768 u2DelayCellOfst[12]=10 cells (3 PI)
7698 12:17:43.945089 u2DelayCellOfst[13]=10 cells (3 PI)
7699 12:17:43.948208 u2DelayCellOfst[14]=16 cells (5 PI)
7700 12:17:43.952099 u2DelayCellOfst[15]=10 cells (3 PI)
7701 12:17:43.955228 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7702 12:17:43.958244 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7703 12:17:43.961377 DramC Write-DBI on
7704 12:17:43.961447 ==
7705 12:17:43.964918 Dram Type= 6, Freq= 0, CH_0, rank 0
7706 12:17:43.968457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7707 12:17:43.968552 ==
7708 12:17:43.968643
7709 12:17:43.971322
7710 12:17:43.971420 TX Vref Scan disable
7711 12:17:43.974926 == TX Byte 0 ==
7712 12:17:43.978422 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7713 12:17:43.981390 == TX Byte 1 ==
7714 12:17:43.984582 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7715 12:17:43.984655 DramC Write-DBI off
7716 12:17:43.988362
7717 12:17:43.988448 [DATLAT]
7718 12:17:43.988509 Freq=1600, CH0 RK0
7719 12:17:43.988567
7720 12:17:43.991417 DATLAT Default: 0xf
7721 12:17:43.991512 0, 0xFFFF, sum = 0
7722 12:17:43.994988 1, 0xFFFF, sum = 0
7723 12:17:43.995085 2, 0xFFFF, sum = 0
7724 12:17:43.998119 3, 0xFFFF, sum = 0
7725 12:17:43.998192 4, 0xFFFF, sum = 0
7726 12:17:44.001698 5, 0xFFFF, sum = 0
7727 12:17:44.004860 6, 0xFFFF, sum = 0
7728 12:17:44.004930 7, 0xFFFF, sum = 0
7729 12:17:44.008275 8, 0xFFFF, sum = 0
7730 12:17:44.008384 9, 0xFFFF, sum = 0
7731 12:17:44.011104 10, 0xFFFF, sum = 0
7732 12:17:44.011192 11, 0xFFFF, sum = 0
7733 12:17:44.014794 12, 0xFFFF, sum = 0
7734 12:17:44.014870 13, 0xFFFF, sum = 0
7735 12:17:44.017950 14, 0x0, sum = 1
7736 12:17:44.018026 15, 0x0, sum = 2
7737 12:17:44.021295 16, 0x0, sum = 3
7738 12:17:44.021365 17, 0x0, sum = 4
7739 12:17:44.024480 best_step = 15
7740 12:17:44.024554
7741 12:17:44.024616 ==
7742 12:17:44.027653 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 12:17:44.031541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 12:17:44.031615 ==
7745 12:17:44.031682 RX Vref Scan: 1
7746 12:17:44.034637
7747 12:17:44.034730 Set Vref Range= 24 -> 127
7748 12:17:44.034816
7749 12:17:44.037466 RX Vref 24 -> 127, step: 1
7750 12:17:44.037565
7751 12:17:44.041188 RX Delay 27 -> 252, step: 4
7752 12:17:44.041270
7753 12:17:44.044670 Set Vref, RX VrefLevel [Byte0]: 24
7754 12:17:44.047453 [Byte1]: 24
7755 12:17:44.047527
7756 12:17:44.050780 Set Vref, RX VrefLevel [Byte0]: 25
7757 12:17:44.054222 [Byte1]: 25
7758 12:17:44.054318
7759 12:17:44.057450 Set Vref, RX VrefLevel [Byte0]: 26
7760 12:17:44.060712 [Byte1]: 26
7761 12:17:44.064618
7762 12:17:44.064688 Set Vref, RX VrefLevel [Byte0]: 27
7763 12:17:44.067809 [Byte1]: 27
7764 12:17:44.072320
7765 12:17:44.072395 Set Vref, RX VrefLevel [Byte0]: 28
7766 12:17:44.075766 [Byte1]: 28
7767 12:17:44.079523
7768 12:17:44.079595 Set Vref, RX VrefLevel [Byte0]: 29
7769 12:17:44.083104 [Byte1]: 29
7770 12:17:44.087136
7771 12:17:44.087208 Set Vref, RX VrefLevel [Byte0]: 30
7772 12:17:44.090624 [Byte1]: 30
7773 12:17:44.094785
7774 12:17:44.094862 Set Vref, RX VrefLevel [Byte0]: 31
7775 12:17:44.098487 [Byte1]: 31
7776 12:17:44.102156
7777 12:17:44.102229 Set Vref, RX VrefLevel [Byte0]: 32
7778 12:17:44.105965 [Byte1]: 32
7779 12:17:44.109655
7780 12:17:44.109725 Set Vref, RX VrefLevel [Byte0]: 33
7781 12:17:44.113330 [Byte1]: 33
7782 12:17:44.117398
7783 12:17:44.117467 Set Vref, RX VrefLevel [Byte0]: 34
7784 12:17:44.120804 [Byte1]: 34
7785 12:17:44.125289
7786 12:17:44.125391 Set Vref, RX VrefLevel [Byte0]: 35
7787 12:17:44.128318 [Byte1]: 35
7788 12:17:44.132854
7789 12:17:44.132928 Set Vref, RX VrefLevel [Byte0]: 36
7790 12:17:44.136024 [Byte1]: 36
7791 12:17:44.139944
7792 12:17:44.140043 Set Vref, RX VrefLevel [Byte0]: 37
7793 12:17:44.143526 [Byte1]: 37
7794 12:17:44.147877
7795 12:17:44.147975 Set Vref, RX VrefLevel [Byte0]: 38
7796 12:17:44.150678 [Byte1]: 38
7797 12:17:44.155150
7798 12:17:44.155282 Set Vref, RX VrefLevel [Byte0]: 39
7799 12:17:44.158578 [Byte1]: 39
7800 12:17:44.162873
7801 12:17:44.162970 Set Vref, RX VrefLevel [Byte0]: 40
7802 12:17:44.166399 [Byte1]: 40
7803 12:17:44.170057
7804 12:17:44.170146 Set Vref, RX VrefLevel [Byte0]: 41
7805 12:17:44.173791 [Byte1]: 41
7806 12:17:44.177676
7807 12:17:44.177771 Set Vref, RX VrefLevel [Byte0]: 42
7808 12:17:44.181157 [Byte1]: 42
7809 12:17:44.185030
7810 12:17:44.185102 Set Vref, RX VrefLevel [Byte0]: 43
7811 12:17:44.188912 [Byte1]: 43
7812 12:17:44.192662
7813 12:17:44.192732 Set Vref, RX VrefLevel [Byte0]: 44
7814 12:17:44.196173 [Byte1]: 44
7815 12:17:44.200615
7816 12:17:44.200692 Set Vref, RX VrefLevel [Byte0]: 45
7817 12:17:44.203568 [Byte1]: 45
7818 12:17:44.208440
7819 12:17:44.208534 Set Vref, RX VrefLevel [Byte0]: 46
7820 12:17:44.211020 [Byte1]: 46
7821 12:17:44.215487
7822 12:17:44.215580 Set Vref, RX VrefLevel [Byte0]: 47
7823 12:17:44.218457 [Byte1]: 47
7824 12:17:44.222877
7825 12:17:44.222975 Set Vref, RX VrefLevel [Byte0]: 48
7826 12:17:44.226205 [Byte1]: 48
7827 12:17:44.230403
7828 12:17:44.230473 Set Vref, RX VrefLevel [Byte0]: 49
7829 12:17:44.234091 [Byte1]: 49
7830 12:17:44.238107
7831 12:17:44.238202 Set Vref, RX VrefLevel [Byte0]: 50
7832 12:17:44.241402 [Byte1]: 50
7833 12:17:44.245761
7834 12:17:44.245838 Set Vref, RX VrefLevel [Byte0]: 51
7835 12:17:44.249004 [Byte1]: 51
7836 12:17:44.253114
7837 12:17:44.253185 Set Vref, RX VrefLevel [Byte0]: 52
7838 12:17:44.256212 [Byte1]: 52
7839 12:17:44.260525
7840 12:17:44.260595 Set Vref, RX VrefLevel [Byte0]: 53
7841 12:17:44.264007 [Byte1]: 53
7842 12:17:44.268147
7843 12:17:44.268258 Set Vref, RX VrefLevel [Byte0]: 54
7844 12:17:44.271395 [Byte1]: 54
7845 12:17:44.275382
7846 12:17:44.275460 Set Vref, RX VrefLevel [Byte0]: 55
7847 12:17:44.279154 [Byte1]: 55
7848 12:17:44.282948
7849 12:17:44.283019 Set Vref, RX VrefLevel [Byte0]: 56
7850 12:17:44.286547 [Byte1]: 56
7851 12:17:44.290835
7852 12:17:44.290939 Set Vref, RX VrefLevel [Byte0]: 57
7853 12:17:44.293968 [Byte1]: 57
7854 12:17:44.298386
7855 12:17:44.298455 Set Vref, RX VrefLevel [Byte0]: 58
7856 12:17:44.302093 [Byte1]: 58
7857 12:17:44.305759
7858 12:17:44.305834 Set Vref, RX VrefLevel [Byte0]: 59
7859 12:17:44.308856 [Byte1]: 59
7860 12:17:44.313328
7861 12:17:44.313431 Set Vref, RX VrefLevel [Byte0]: 60
7862 12:17:44.316880 [Byte1]: 60
7863 12:17:44.321040
7864 12:17:44.321161 Set Vref, RX VrefLevel [Byte0]: 61
7865 12:17:44.324477 [Byte1]: 61
7866 12:17:44.328373
7867 12:17:44.328472 Set Vref, RX VrefLevel [Byte0]: 62
7868 12:17:44.334639 [Byte1]: 62
7869 12:17:44.334783
7870 12:17:44.338402 Set Vref, RX VrefLevel [Byte0]: 63
7871 12:17:44.341861 [Byte1]: 63
7872 12:17:44.341971
7873 12:17:44.344914 Set Vref, RX VrefLevel [Byte0]: 64
7874 12:17:44.348226 [Byte1]: 64
7875 12:17:44.348403
7876 12:17:44.352277 Set Vref, RX VrefLevel [Byte0]: 65
7877 12:17:44.354756 [Byte1]: 65
7878 12:17:44.358867
7879 12:17:44.359099 Set Vref, RX VrefLevel [Byte0]: 66
7880 12:17:44.362128 [Byte1]: 66
7881 12:17:44.366504
7882 12:17:44.366749 Set Vref, RX VrefLevel [Byte0]: 67
7883 12:17:44.369631 [Byte1]: 67
7884 12:17:44.374094
7885 12:17:44.374433 Set Vref, RX VrefLevel [Byte0]: 68
7886 12:17:44.377181 [Byte1]: 68
7887 12:17:44.381670
7888 12:17:44.382135 Set Vref, RX VrefLevel [Byte0]: 69
7889 12:17:44.384739 [Byte1]: 69
7890 12:17:44.389204
7891 12:17:44.389578 Set Vref, RX VrefLevel [Byte0]: 70
7892 12:17:44.392484 [Byte1]: 70
7893 12:17:44.396553
7894 12:17:44.396921 Set Vref, RX VrefLevel [Byte0]: 71
7895 12:17:44.400106 [Byte1]: 71
7896 12:17:44.403874
7897 12:17:44.404236 Set Vref, RX VrefLevel [Byte0]: 72
7898 12:17:44.407190 [Byte1]: 72
7899 12:17:44.411866
7900 12:17:44.412216 Final RX Vref Byte 0 = 59 to rank0
7901 12:17:44.414840 Final RX Vref Byte 1 = 60 to rank0
7902 12:17:44.418601 Final RX Vref Byte 0 = 59 to rank1
7903 12:17:44.421536 Final RX Vref Byte 1 = 60 to rank1==
7904 12:17:44.424807 Dram Type= 6, Freq= 0, CH_0, rank 0
7905 12:17:44.431554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7906 12:17:44.431995 ==
7907 12:17:44.432383 DQS Delay:
7908 12:17:44.432713 DQS0 = 0, DQS1 = 0
7909 12:17:44.435020 DQM Delay:
7910 12:17:44.435452 DQM0 = 134, DQM1 = 128
7911 12:17:44.438265 DQ Delay:
7912 12:17:44.441814 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =130
7913 12:17:44.444728 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7914 12:17:44.448359 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
7915 12:17:44.451847 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =136
7916 12:17:44.452377
7917 12:17:44.452862
7918 12:17:44.453271
7919 12:17:44.454999 [DramC_TX_OE_Calibration] TA2
7920 12:17:44.457887 Original DQ_B0 (3 6) =30, OEN = 27
7921 12:17:44.461497 Original DQ_B1 (3 6) =30, OEN = 27
7922 12:17:44.464754 24, 0x0, End_B0=24 End_B1=24
7923 12:17:44.465186 25, 0x0, End_B0=25 End_B1=25
7924 12:17:44.467938 26, 0x0, End_B0=26 End_B1=26
7925 12:17:44.471574 27, 0x0, End_B0=27 End_B1=27
7926 12:17:44.474616 28, 0x0, End_B0=28 End_B1=28
7927 12:17:44.478333 29, 0x0, End_B0=29 End_B1=29
7928 12:17:44.478776 30, 0x0, End_B0=30 End_B1=30
7929 12:17:44.481625 31, 0x4141, End_B0=30 End_B1=30
7930 12:17:44.484857 Byte0 end_step=30 best_step=27
7931 12:17:44.487856 Byte1 end_step=30 best_step=27
7932 12:17:44.491366 Byte0 TX OE(2T, 0.5T) = (3, 3)
7933 12:17:44.491916 Byte1 TX OE(2T, 0.5T) = (3, 3)
7934 12:17:44.494755
7935 12:17:44.495166
7936 12:17:44.501172 [DQSOSCAuto] RK0, (LSB)MR18= 0x231f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
7937 12:17:44.504626 CH0 RK0: MR19=303, MR18=231F
7938 12:17:44.511259 CH0_RK0: MR19=0x303, MR18=0x231F, DQSOSC=392, MR23=63, INC=24, DEC=16
7939 12:17:44.511783
7940 12:17:44.514481 ----->DramcWriteLeveling(PI) begin...
7941 12:17:44.514915 ==
7942 12:17:44.518378 Dram Type= 6, Freq= 0, CH_0, rank 1
7943 12:17:44.520987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7944 12:17:44.521416 ==
7945 12:17:44.524557 Write leveling (Byte 0): 36 => 36
7946 12:17:44.527922 Write leveling (Byte 1): 29 => 29
7947 12:17:44.531196 DramcWriteLeveling(PI) end<-----
7948 12:17:44.531614
7949 12:17:44.531947 ==
7950 12:17:44.534299 Dram Type= 6, Freq= 0, CH_0, rank 1
7951 12:17:44.538306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7952 12:17:44.538807 ==
7953 12:17:44.541179 [Gating] SW mode calibration
7954 12:17:44.547972 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7955 12:17:44.554283 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7956 12:17:44.557381 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7957 12:17:44.560903 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7958 12:17:44.567454 1 4 8 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7959 12:17:44.571054 1 4 12 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
7960 12:17:44.574119 1 4 16 | B1->B0 | 2e2e 3635 | 0 1 | (0 0) (0 0)
7961 12:17:44.581163 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)
7962 12:17:44.584364 1 4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7963 12:17:44.587585 1 4 28 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
7964 12:17:44.594525 1 5 0 | B1->B0 | 3434 3939 | 1 0 | (1 1) (1 1)
7965 12:17:44.597796 1 5 4 | B1->B0 | 3434 3737 | 1 0 | (1 1) (1 1)
7966 12:17:44.600919 1 5 8 | B1->B0 | 3434 3737 | 1 1 | (1 1) (0 0)
7967 12:17:44.607411 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (0 0)
7968 12:17:44.610769 1 5 16 | B1->B0 | 2c2c 2a29 | 0 1 | (1 0) (1 0)
7969 12:17:44.613738 1 5 20 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7970 12:17:44.620656 1 5 24 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7971 12:17:44.623895 1 5 28 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7972 12:17:44.627007 1 6 0 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7973 12:17:44.633480 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
7974 12:17:44.637487 1 6 8 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7975 12:17:44.640674 1 6 12 | B1->B0 | 2323 3433 | 0 1 | (0 0) (0 0)
7976 12:17:44.646960 1 6 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7977 12:17:44.650205 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7978 12:17:44.653956 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7979 12:17:44.660079 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7980 12:17:44.663716 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7981 12:17:44.666781 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7982 12:17:44.673620 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7983 12:17:44.677084 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7984 12:17:44.680184 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7985 12:17:44.686794 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 12:17:44.690359 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 12:17:44.693780 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 12:17:44.700174 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 12:17:44.704079 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 12:17:44.707234 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 12:17:44.713915 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 12:17:44.716822 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 12:17:44.720398 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 12:17:44.723723 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 12:17:44.730339 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 12:17:44.733071 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 12:17:44.736607 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 12:17:44.743401 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7999 12:17:44.746495 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8000 12:17:44.749644 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8001 12:17:44.756480 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8002 12:17:44.759533 Total UI for P1: 0, mck2ui 16
8003 12:17:44.763175 best dqsien dly found for B0: ( 1, 9, 12)
8004 12:17:44.763256 Total UI for P1: 0, mck2ui 16
8005 12:17:44.769725 best dqsien dly found for B1: ( 1, 9, 12)
8006 12:17:44.773322 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8007 12:17:44.776547 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8008 12:17:44.776635
8009 12:17:44.779815 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8010 12:17:44.783018 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8011 12:17:44.786645 [Gating] SW calibration Done
8012 12:17:44.786726 ==
8013 12:17:44.789559 Dram Type= 6, Freq= 0, CH_0, rank 1
8014 12:17:44.792761 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8015 12:17:44.792843 ==
8016 12:17:44.796163 RX Vref Scan: 0
8017 12:17:44.796244
8018 12:17:44.799574 RX Vref 0 -> 0, step: 1
8019 12:17:44.799654
8020 12:17:44.799717 RX Delay 0 -> 252, step: 8
8021 12:17:44.802747 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8022 12:17:44.810024 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8023 12:17:44.813075 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8024 12:17:44.816373 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8025 12:17:44.819411 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8026 12:17:44.823005 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8027 12:17:44.829476 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8028 12:17:44.832551 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8029 12:17:44.835954 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8030 12:17:44.839489 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8031 12:17:44.842460 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8032 12:17:44.849146 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8033 12:17:44.852816 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8034 12:17:44.855993 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8035 12:17:44.859594 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8036 12:17:44.865951 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8037 12:17:44.866031 ==
8038 12:17:44.869163 Dram Type= 6, Freq= 0, CH_0, rank 1
8039 12:17:44.872733 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8040 12:17:44.872819 ==
8041 12:17:44.872888 DQS Delay:
8042 12:17:44.875671 DQS0 = 0, DQS1 = 0
8043 12:17:44.875750 DQM Delay:
8044 12:17:44.879401 DQM0 = 137, DQM1 = 130
8045 12:17:44.879480 DQ Delay:
8046 12:17:44.882643 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8047 12:17:44.885908 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8048 12:17:44.889125 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8049 12:17:44.892686 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8050 12:17:44.892765
8051 12:17:44.892827
8052 12:17:44.895874 ==
8053 12:17:44.895953 Dram Type= 6, Freq= 0, CH_0, rank 1
8054 12:17:44.902261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8055 12:17:44.902341 ==
8056 12:17:44.902404
8057 12:17:44.902461
8058 12:17:44.905441 TX Vref Scan disable
8059 12:17:44.905520 == TX Byte 0 ==
8060 12:17:44.909067 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8061 12:17:44.915893 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8062 12:17:44.915972 == TX Byte 1 ==
8063 12:17:44.919188 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8064 12:17:44.925388 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8065 12:17:44.925501 ==
8066 12:17:44.929128 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 12:17:44.932556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 12:17:44.932636 ==
8069 12:17:44.946391
8070 12:17:44.949291 TX Vref early break, caculate TX vref
8071 12:17:44.952944 TX Vref=16, minBit 3, minWin=22, winSum=387
8072 12:17:44.955790 TX Vref=18, minBit 1, minWin=23, winSum=396
8073 12:17:44.959018 TX Vref=20, minBit 0, minWin=24, winSum=404
8074 12:17:44.962693 TX Vref=22, minBit 1, minWin=24, winSum=408
8075 12:17:44.966085 TX Vref=24, minBit 7, minWin=24, winSum=416
8076 12:17:44.972854 TX Vref=26, minBit 3, minWin=25, winSum=423
8077 12:17:44.976092 TX Vref=28, minBit 3, minWin=25, winSum=424
8078 12:17:44.979684 TX Vref=30, minBit 4, minWin=25, winSum=418
8079 12:17:44.982541 TX Vref=32, minBit 3, minWin=24, winSum=412
8080 12:17:44.986123 TX Vref=34, minBit 0, minWin=24, winSum=398
8081 12:17:44.992681 [TxChooseVref] Worse bit 3, Min win 25, Win sum 424, Final Vref 28
8082 12:17:44.992761
8083 12:17:44.995955 Final TX Range 0 Vref 28
8084 12:17:44.996034
8085 12:17:44.996096 ==
8086 12:17:44.999512 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 12:17:45.002401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 12:17:45.002480 ==
8089 12:17:45.002542
8090 12:17:45.002599
8091 12:17:45.006395 TX Vref Scan disable
8092 12:17:45.012766 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8093 12:17:45.012845 == TX Byte 0 ==
8094 12:17:45.015848 u2DelayCellOfst[0]=13 cells (4 PI)
8095 12:17:45.019637 u2DelayCellOfst[1]=13 cells (4 PI)
8096 12:17:45.022529 u2DelayCellOfst[2]=10 cells (3 PI)
8097 12:17:45.026016 u2DelayCellOfst[3]=10 cells (3 PI)
8098 12:17:45.029014 u2DelayCellOfst[4]=6 cells (2 PI)
8099 12:17:45.032734 u2DelayCellOfst[5]=0 cells (0 PI)
8100 12:17:45.035592 u2DelayCellOfst[6]=16 cells (5 PI)
8101 12:17:45.035671 u2DelayCellOfst[7]=13 cells (4 PI)
8102 12:17:45.042817 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8103 12:17:45.046361 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8104 12:17:45.046440 == TX Byte 1 ==
8105 12:17:45.049319 u2DelayCellOfst[8]=0 cells (0 PI)
8106 12:17:45.052561 u2DelayCellOfst[9]=0 cells (0 PI)
8107 12:17:45.056417 u2DelayCellOfst[10]=6 cells (2 PI)
8108 12:17:45.059444 u2DelayCellOfst[11]=3 cells (1 PI)
8109 12:17:45.062705 u2DelayCellOfst[12]=10 cells (3 PI)
8110 12:17:45.065728 u2DelayCellOfst[13]=10 cells (3 PI)
8111 12:17:45.068861 u2DelayCellOfst[14]=13 cells (4 PI)
8112 12:17:45.072191 u2DelayCellOfst[15]=13 cells (4 PI)
8113 12:17:45.075678 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8114 12:17:45.082420 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8115 12:17:45.082500 DramC Write-DBI on
8116 12:17:45.082562 ==
8117 12:17:45.085700 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 12:17:45.088857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 12:17:45.088937 ==
8120 12:17:45.092494
8121 12:17:45.092598
8122 12:17:45.092688 TX Vref Scan disable
8123 12:17:45.095667 == TX Byte 0 ==
8124 12:17:45.098795 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8125 12:17:45.102124 == TX Byte 1 ==
8126 12:17:45.105716 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8127 12:17:45.105796 DramC Write-DBI off
8128 12:17:45.109307
8129 12:17:45.109385 [DATLAT]
8130 12:17:45.109448 Freq=1600, CH0 RK1
8131 12:17:45.109507
8132 12:17:45.112466 DATLAT Default: 0xf
8133 12:17:45.112545 0, 0xFFFF, sum = 0
8134 12:17:45.115646 1, 0xFFFF, sum = 0
8135 12:17:45.115728 2, 0xFFFF, sum = 0
8136 12:17:45.118891 3, 0xFFFF, sum = 0
8137 12:17:45.122078 4, 0xFFFF, sum = 0
8138 12:17:45.122160 5, 0xFFFF, sum = 0
8139 12:17:45.125235 6, 0xFFFF, sum = 0
8140 12:17:45.125315 7, 0xFFFF, sum = 0
8141 12:17:45.128886 8, 0xFFFF, sum = 0
8142 12:17:45.128969 9, 0xFFFF, sum = 0
8143 12:17:45.132475 10, 0xFFFF, sum = 0
8144 12:17:45.132550 11, 0xFFFF, sum = 0
8145 12:17:45.135710 12, 0xFFFF, sum = 0
8146 12:17:45.135782 13, 0xFFFF, sum = 0
8147 12:17:45.138978 14, 0x0, sum = 1
8148 12:17:45.139059 15, 0x0, sum = 2
8149 12:17:45.142037 16, 0x0, sum = 3
8150 12:17:45.142118 17, 0x0, sum = 4
8151 12:17:45.145299 best_step = 15
8152 12:17:45.145380
8153 12:17:45.145443 ==
8154 12:17:45.148890 Dram Type= 6, Freq= 0, CH_0, rank 1
8155 12:17:45.152458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8156 12:17:45.152543 ==
8157 12:17:45.155370 RX Vref Scan: 0
8158 12:17:45.155450
8159 12:17:45.155513 RX Vref 0 -> 0, step: 1
8160 12:17:45.155572
8161 12:17:45.158661 RX Delay 19 -> 252, step: 4
8162 12:17:45.161924 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8163 12:17:45.168574 iDelay=191, Bit 1, Center 136 (91 ~ 182) 92
8164 12:17:45.171817 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8165 12:17:45.175043 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8166 12:17:45.178858 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8167 12:17:45.182333 iDelay=191, Bit 5, Center 126 (71 ~ 182) 112
8168 12:17:45.188667 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8169 12:17:45.191796 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8170 12:17:45.195356 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8171 12:17:45.198816 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8172 12:17:45.201662 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8173 12:17:45.208508 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8174 12:17:45.211987 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8175 12:17:45.215090 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8176 12:17:45.218362 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8177 12:17:45.222181 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8178 12:17:45.225438 ==
8179 12:17:45.228687 Dram Type= 6, Freq= 0, CH_0, rank 1
8180 12:17:45.231876 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8181 12:17:45.231970 ==
8182 12:17:45.232063 DQS Delay:
8183 12:17:45.234829 DQS0 = 0, DQS1 = 0
8184 12:17:45.234909 DQM Delay:
8185 12:17:45.238419 DQM0 = 134, DQM1 = 127
8186 12:17:45.238499 DQ Delay:
8187 12:17:45.241646 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =132
8188 12:17:45.245012 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =140
8189 12:17:45.248476 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8190 12:17:45.251750 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
8191 12:17:45.251831
8192 12:17:45.251894
8193 12:17:45.251952
8194 12:17:45.254919 [DramC_TX_OE_Calibration] TA2
8195 12:17:45.258021 Original DQ_B0 (3 6) =30, OEN = 27
8196 12:17:45.261947 Original DQ_B1 (3 6) =30, OEN = 27
8197 12:17:45.265056 24, 0x0, End_B0=24 End_B1=24
8198 12:17:45.268190 25, 0x0, End_B0=25 End_B1=25
8199 12:17:45.268271 26, 0x0, End_B0=26 End_B1=26
8200 12:17:45.271708 27, 0x0, End_B0=27 End_B1=27
8201 12:17:45.274892 28, 0x0, End_B0=28 End_B1=28
8202 12:17:45.278247 29, 0x0, End_B0=29 End_B1=29
8203 12:17:45.281504 30, 0x0, End_B0=30 End_B1=30
8204 12:17:45.281586 31, 0x4141, End_B0=30 End_B1=30
8205 12:17:45.284936 Byte0 end_step=30 best_step=27
8206 12:17:45.288142 Byte1 end_step=30 best_step=27
8207 12:17:45.291346 Byte0 TX OE(2T, 0.5T) = (3, 3)
8208 12:17:45.294966 Byte1 TX OE(2T, 0.5T) = (3, 3)
8209 12:17:45.295046
8210 12:17:45.295110
8211 12:17:45.301131 [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8212 12:17:45.304810 CH0 RK1: MR19=303, MR18=2008
8213 12:17:45.311559 CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15
8214 12:17:45.314494 [RxdqsGatingPostProcess] freq 1600
8215 12:17:45.321305 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8216 12:17:45.321386 best DQS0 dly(2T, 0.5T) = (1, 1)
8217 12:17:45.324976 best DQS1 dly(2T, 0.5T) = (1, 1)
8218 12:17:45.327815 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8219 12:17:45.331458 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8220 12:17:45.334856 best DQS0 dly(2T, 0.5T) = (1, 1)
8221 12:17:45.338112 best DQS1 dly(2T, 0.5T) = (1, 1)
8222 12:17:45.341214 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8223 12:17:45.344746 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8224 12:17:45.347712 Pre-setting of DQS Precalculation
8225 12:17:45.351724 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8226 12:17:45.351805 ==
8227 12:17:45.354889 Dram Type= 6, Freq= 0, CH_1, rank 0
8228 12:17:45.361221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8229 12:17:45.361302 ==
8230 12:17:45.364536 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8231 12:17:45.367944 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8232 12:17:45.375028 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8233 12:17:45.381238 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8234 12:17:45.388751 [CA 0] Center 42 (13~72) winsize 60
8235 12:17:45.392073 [CA 1] Center 42 (12~72) winsize 61
8236 12:17:45.395322 [CA 2] Center 38 (9~68) winsize 60
8237 12:17:45.398604 [CA 3] Center 38 (9~67) winsize 59
8238 12:17:45.402303 [CA 4] Center 38 (9~68) winsize 60
8239 12:17:45.405202 [CA 5] Center 37 (8~67) winsize 60
8240 12:17:45.405282
8241 12:17:45.408814 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8242 12:17:45.408895
8243 12:17:45.411909 [CATrainingPosCal] consider 1 rank data
8244 12:17:45.415191 u2DelayCellTimex100 = 290/100 ps
8245 12:17:45.418282 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8246 12:17:45.425507 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8247 12:17:45.428506 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8248 12:17:45.432861 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8249 12:17:45.434971 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8250 12:17:45.438315 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8251 12:17:45.438396
8252 12:17:45.441796 CA PerBit enable=1, Macro0, CA PI delay=37
8253 12:17:45.441877
8254 12:17:45.445172 [CBTSetCACLKResult] CA Dly = 37
8255 12:17:45.448657 CS Dly: 10 (0~41)
8256 12:17:45.451909 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8257 12:17:45.455102 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8258 12:17:45.455183 ==
8259 12:17:45.458157 Dram Type= 6, Freq= 0, CH_1, rank 1
8260 12:17:45.461892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8261 12:17:45.464948 ==
8262 12:17:45.467980 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8263 12:17:45.471653 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8264 12:17:45.478121 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8265 12:17:45.481417 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8266 12:17:45.492109 [CA 0] Center 42 (13~72) winsize 60
8267 12:17:45.495214 [CA 1] Center 42 (13~72) winsize 60
8268 12:17:45.498408 [CA 2] Center 39 (9~69) winsize 61
8269 12:17:45.501851 [CA 3] Center 39 (10~68) winsize 59
8270 12:17:45.504880 [CA 4] Center 39 (9~69) winsize 61
8271 12:17:45.508602 [CA 5] Center 38 (9~68) winsize 60
8272 12:17:45.508683
8273 12:17:45.511879 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8274 12:17:45.511959
8275 12:17:45.515148 [CATrainingPosCal] consider 2 rank data
8276 12:17:45.518260 u2DelayCellTimex100 = 290/100 ps
8277 12:17:45.521737 CA0 delay=42 (13~72),Diff = 4 PI (13 cell)
8278 12:17:45.528643 CA1 delay=42 (13~72),Diff = 4 PI (13 cell)
8279 12:17:45.531893 CA2 delay=38 (9~68),Diff = 0 PI (0 cell)
8280 12:17:45.535589 CA3 delay=38 (10~67),Diff = 0 PI (0 cell)
8281 12:17:45.538698 CA4 delay=38 (9~68),Diff = 0 PI (0 cell)
8282 12:17:45.541773 CA5 delay=38 (9~67),Diff = 0 PI (0 cell)
8283 12:17:45.541853
8284 12:17:45.545153 CA PerBit enable=1, Macro0, CA PI delay=38
8285 12:17:45.545234
8286 12:17:45.548341 [CBTSetCACLKResult] CA Dly = 38
8287 12:17:45.551688 CS Dly: 12 (0~45)
8288 12:17:45.555078 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8289 12:17:45.558337 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8290 12:17:45.558417
8291 12:17:45.561349 ----->DramcWriteLeveling(PI) begin...
8292 12:17:45.561431 ==
8293 12:17:45.564928 Dram Type= 6, Freq= 0, CH_1, rank 0
8294 12:17:45.568183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8295 12:17:45.571559 ==
8296 12:17:45.571640 Write leveling (Byte 0): 25 => 25
8297 12:17:45.575104 Write leveling (Byte 1): 27 => 27
8298 12:17:45.578087 DramcWriteLeveling(PI) end<-----
8299 12:17:45.578167
8300 12:17:45.578229 ==
8301 12:17:45.581853 Dram Type= 6, Freq= 0, CH_1, rank 0
8302 12:17:45.588698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8303 12:17:45.588793 ==
8304 12:17:45.591485 [Gating] SW mode calibration
8305 12:17:45.598530 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8306 12:17:45.601566 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8307 12:17:45.608136 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8308 12:17:45.611562 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8309 12:17:45.614799 1 4 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
8310 12:17:45.621501 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8311 12:17:45.625099 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8312 12:17:45.628302 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8313 12:17:45.631547 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8314 12:17:45.638198 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8315 12:17:45.641595 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8316 12:17:45.644610 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8317 12:17:45.651718 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
8318 12:17:45.654978 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
8319 12:17:45.658194 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8320 12:17:45.664560 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 12:17:45.667885 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 12:17:45.671392 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 12:17:45.677730 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 12:17:45.681501 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 12:17:45.684439 1 6 8 | B1->B0 | 2424 3232 | 0 0 | (0 0) (1 1)
8326 12:17:45.691312 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8327 12:17:45.694652 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8328 12:17:45.697925 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8329 12:17:45.704290 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8330 12:17:45.707699 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8331 12:17:45.711314 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8332 12:17:45.717904 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8333 12:17:45.720969 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8334 12:17:45.724450 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8335 12:17:45.731026 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8336 12:17:45.734380 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 12:17:45.737916 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 12:17:45.744313 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 12:17:45.747723 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 12:17:45.751046 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 12:17:45.757640 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 12:17:45.761062 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 12:17:45.764570 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 12:17:45.770874 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 12:17:45.774077 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 12:17:45.777332 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 12:17:45.784587 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 12:17:45.787400 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 12:17:45.790912 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8350 12:17:45.794065 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8351 12:17:45.800973 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 12:17:45.804126 Total UI for P1: 0, mck2ui 16
8353 12:17:45.807421 best dqsien dly found for B0: ( 1, 9, 10)
8354 12:17:45.810409 Total UI for P1: 0, mck2ui 16
8355 12:17:45.813729 best dqsien dly found for B1: ( 1, 9, 10)
8356 12:17:45.816791 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8357 12:17:45.820157 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8358 12:17:45.820237
8359 12:17:45.823582 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8360 12:17:45.826979 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8361 12:17:45.830230 [Gating] SW calibration Done
8362 12:17:45.830310 ==
8363 12:17:45.833599 Dram Type= 6, Freq= 0, CH_1, rank 0
8364 12:17:45.836683 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8365 12:17:45.840249 ==
8366 12:17:45.840371 RX Vref Scan: 0
8367 12:17:45.840435
8368 12:17:45.843808 RX Vref 0 -> 0, step: 1
8369 12:17:45.843888
8370 12:17:45.843950 RX Delay 0 -> 252, step: 8
8371 12:17:45.850073 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8372 12:17:45.853097 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8373 12:17:45.857048 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8374 12:17:45.859914 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8375 12:17:45.863703 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8376 12:17:45.870235 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8377 12:17:45.873149 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8378 12:17:45.876454 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8379 12:17:45.879660 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8380 12:17:45.883372 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8381 12:17:45.889785 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8382 12:17:45.893063 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8383 12:17:45.896841 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8384 12:17:45.899529 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8385 12:17:45.906399 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8386 12:17:45.909538 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8387 12:17:45.909619 ==
8388 12:17:45.913042 Dram Type= 6, Freq= 0, CH_1, rank 0
8389 12:17:45.916428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8390 12:17:45.916510 ==
8391 12:17:45.916572 DQS Delay:
8392 12:17:45.919590 DQS0 = 0, DQS1 = 0
8393 12:17:45.919660 DQM Delay:
8394 12:17:45.922989 DQM0 = 135, DQM1 = 132
8395 12:17:45.923069 DQ Delay:
8396 12:17:45.926288 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8397 12:17:45.929369 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =135
8398 12:17:45.933204 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8399 12:17:45.939484 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8400 12:17:45.939558
8401 12:17:45.939627
8402 12:17:45.939685 ==
8403 12:17:45.943176 Dram Type= 6, Freq= 0, CH_1, rank 0
8404 12:17:45.946406 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8405 12:17:45.946475 ==
8406 12:17:45.946533
8407 12:17:45.946588
8408 12:17:45.949387 TX Vref Scan disable
8409 12:17:45.949457 == TX Byte 0 ==
8410 12:17:45.956096 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8411 12:17:45.959695 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8412 12:17:45.959762 == TX Byte 1 ==
8413 12:17:45.966377 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8414 12:17:45.969216 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8415 12:17:45.969286 ==
8416 12:17:45.972443 Dram Type= 6, Freq= 0, CH_1, rank 0
8417 12:17:45.976010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8418 12:17:45.976106 ==
8419 12:17:45.989138
8420 12:17:45.992638 TX Vref early break, caculate TX vref
8421 12:17:45.995987 TX Vref=16, minBit 0, minWin=22, winSum=378
8422 12:17:45.999786 TX Vref=18, minBit 1, minWin=23, winSum=388
8423 12:17:46.002852 TX Vref=20, minBit 0, minWin=24, winSum=397
8424 12:17:46.005998 TX Vref=22, minBit 0, minWin=24, winSum=404
8425 12:17:46.009630 TX Vref=24, minBit 0, minWin=25, winSum=420
8426 12:17:46.015948 TX Vref=26, minBit 1, minWin=25, winSum=424
8427 12:17:46.019151 TX Vref=28, minBit 0, minWin=25, winSum=426
8428 12:17:46.022304 TX Vref=30, minBit 0, minWin=25, winSum=420
8429 12:17:46.025672 TX Vref=32, minBit 2, minWin=24, winSum=415
8430 12:17:46.028923 TX Vref=34, minBit 0, minWin=24, winSum=403
8431 12:17:46.035901 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 28
8432 12:17:46.035977
8433 12:17:46.038978 Final TX Range 0 Vref 28
8434 12:17:46.039054
8435 12:17:46.039113 ==
8436 12:17:46.042227 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 12:17:46.045818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 12:17:46.045889 ==
8439 12:17:46.045949
8440 12:17:46.046005
8441 12:17:46.049033 TX Vref Scan disable
8442 12:17:46.055979 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8443 12:17:46.056062 == TX Byte 0 ==
8444 12:17:46.059234 u2DelayCellOfst[0]=16 cells (5 PI)
8445 12:17:46.062218 u2DelayCellOfst[1]=10 cells (3 PI)
8446 12:17:46.065795 u2DelayCellOfst[2]=0 cells (0 PI)
8447 12:17:46.068953 u2DelayCellOfst[3]=6 cells (2 PI)
8448 12:17:46.072203 u2DelayCellOfst[4]=6 cells (2 PI)
8449 12:17:46.076007 u2DelayCellOfst[5]=16 cells (5 PI)
8450 12:17:46.079239 u2DelayCellOfst[6]=16 cells (5 PI)
8451 12:17:46.079322 u2DelayCellOfst[7]=6 cells (2 PI)
8452 12:17:46.085472 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8453 12:17:46.088849 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8454 12:17:46.092128 == TX Byte 1 ==
8455 12:17:46.092210 u2DelayCellOfst[8]=0 cells (0 PI)
8456 12:17:46.095170 u2DelayCellOfst[9]=3 cells (1 PI)
8457 12:17:46.098700 u2DelayCellOfst[10]=13 cells (4 PI)
8458 12:17:46.101941 u2DelayCellOfst[11]=3 cells (1 PI)
8459 12:17:46.105385 u2DelayCellOfst[12]=16 cells (5 PI)
8460 12:17:46.108859 u2DelayCellOfst[13]=16 cells (5 PI)
8461 12:17:46.111963 u2DelayCellOfst[14]=20 cells (6 PI)
8462 12:17:46.115156 u2DelayCellOfst[15]=16 cells (5 PI)
8463 12:17:46.118514 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8464 12:17:46.125018 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8465 12:17:46.125105 DramC Write-DBI on
8466 12:17:46.125197 ==
8467 12:17:46.128432 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 12:17:46.131759 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 12:17:46.134973 ==
8470 12:17:46.135057
8471 12:17:46.135138
8472 12:17:46.135217 TX Vref Scan disable
8473 12:17:46.138899 == TX Byte 0 ==
8474 12:17:46.141880 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8475 12:17:46.145171 == TX Byte 1 ==
8476 12:17:46.148813 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8477 12:17:46.152040 DramC Write-DBI off
8478 12:17:46.152121
8479 12:17:46.152219 [DATLAT]
8480 12:17:46.152341 Freq=1600, CH1 RK0
8481 12:17:46.152433
8482 12:17:46.155678 DATLAT Default: 0xf
8483 12:17:46.155759 0, 0xFFFF, sum = 0
8484 12:17:46.158596 1, 0xFFFF, sum = 0
8485 12:17:46.158679 2, 0xFFFF, sum = 0
8486 12:17:46.162332 3, 0xFFFF, sum = 0
8487 12:17:46.165327 4, 0xFFFF, sum = 0
8488 12:17:46.165416 5, 0xFFFF, sum = 0
8489 12:17:46.168428 6, 0xFFFF, sum = 0
8490 12:17:46.168511 7, 0xFFFF, sum = 0
8491 12:17:46.172126 8, 0xFFFF, sum = 0
8492 12:17:46.172209 9, 0xFFFF, sum = 0
8493 12:17:46.175357 10, 0xFFFF, sum = 0
8494 12:17:46.175440 11, 0xFFFF, sum = 0
8495 12:17:46.178619 12, 0xFFFF, sum = 0
8496 12:17:46.178702 13, 0xFFFF, sum = 0
8497 12:17:46.181804 14, 0x0, sum = 1
8498 12:17:46.181887 15, 0x0, sum = 2
8499 12:17:46.185038 16, 0x0, sum = 3
8500 12:17:46.185120 17, 0x0, sum = 4
8501 12:17:46.188745 best_step = 15
8502 12:17:46.188827
8503 12:17:46.188909 ==
8504 12:17:46.191926 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 12:17:46.195335 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 12:17:46.195418 ==
8507 12:17:46.195501 RX Vref Scan: 1
8508 12:17:46.198475
8509 12:17:46.198556 Set Vref Range= 24 -> 127
8510 12:17:46.198638
8511 12:17:46.201624 RX Vref 24 -> 127, step: 1
8512 12:17:46.201711
8513 12:17:46.205163 RX Delay 27 -> 252, step: 4
8514 12:17:46.205247
8515 12:17:46.208855 Set Vref, RX VrefLevel [Byte0]: 24
8516 12:17:46.211958 [Byte1]: 24
8517 12:17:46.212040
8518 12:17:46.215070 Set Vref, RX VrefLevel [Byte0]: 25
8519 12:17:46.218853 [Byte1]: 25
8520 12:17:46.218934
8521 12:17:46.221384 Set Vref, RX VrefLevel [Byte0]: 26
8522 12:17:46.225066 [Byte1]: 26
8523 12:17:46.228914
8524 12:17:46.228995 Set Vref, RX VrefLevel [Byte0]: 27
8525 12:17:46.232022 [Byte1]: 27
8526 12:17:46.236103
8527 12:17:46.236184 Set Vref, RX VrefLevel [Byte0]: 28
8528 12:17:46.239398 [Byte1]: 28
8529 12:17:46.243660
8530 12:17:46.243741 Set Vref, RX VrefLevel [Byte0]: 29
8531 12:17:46.247092 [Byte1]: 29
8532 12:17:46.251594
8533 12:17:46.251675 Set Vref, RX VrefLevel [Byte0]: 30
8534 12:17:46.254754 [Byte1]: 30
8535 12:17:46.258697
8536 12:17:46.258779 Set Vref, RX VrefLevel [Byte0]: 31
8537 12:17:46.261951 [Byte1]: 31
8538 12:17:46.266474
8539 12:17:46.266555 Set Vref, RX VrefLevel [Byte0]: 32
8540 12:17:46.269622 [Byte1]: 32
8541 12:17:46.274401
8542 12:17:46.274482 Set Vref, RX VrefLevel [Byte0]: 33
8543 12:17:46.277334 [Byte1]: 33
8544 12:17:46.281725
8545 12:17:46.281807 Set Vref, RX VrefLevel [Byte0]: 34
8546 12:17:46.284961 [Byte1]: 34
8547 12:17:46.289326
8548 12:17:46.289407 Set Vref, RX VrefLevel [Byte0]: 35
8549 12:17:46.292220 [Byte1]: 35
8550 12:17:46.296648
8551 12:17:46.296730 Set Vref, RX VrefLevel [Byte0]: 36
8552 12:17:46.299823 [Byte1]: 36
8553 12:17:46.304203
8554 12:17:46.304365 Set Vref, RX VrefLevel [Byte0]: 37
8555 12:17:46.310942 [Byte1]: 37
8556 12:17:46.311024
8557 12:17:46.313782 Set Vref, RX VrefLevel [Byte0]: 38
8558 12:17:46.317051 [Byte1]: 38
8559 12:17:46.317133
8560 12:17:46.320796 Set Vref, RX VrefLevel [Byte0]: 39
8561 12:17:46.324022 [Byte1]: 39
8562 12:17:46.324133
8563 12:17:46.327111 Set Vref, RX VrefLevel [Byte0]: 40
8564 12:17:46.330875 [Byte1]: 40
8565 12:17:46.334537
8566 12:17:46.334619 Set Vref, RX VrefLevel [Byte0]: 41
8567 12:17:46.337520 [Byte1]: 41
8568 12:17:46.341609
8569 12:17:46.341690 Set Vref, RX VrefLevel [Byte0]: 42
8570 12:17:46.345269 [Byte1]: 42
8571 12:17:46.349155
8572 12:17:46.349236 Set Vref, RX VrefLevel [Byte0]: 43
8573 12:17:46.352818 [Byte1]: 43
8574 12:17:46.356944
8575 12:17:46.357050 Set Vref, RX VrefLevel [Byte0]: 44
8576 12:17:46.360244 [Byte1]: 44
8577 12:17:46.364489
8578 12:17:46.364571 Set Vref, RX VrefLevel [Byte0]: 45
8579 12:17:46.367961 [Byte1]: 45
8580 12:17:46.371831
8581 12:17:46.371937 Set Vref, RX VrefLevel [Byte0]: 46
8582 12:17:46.375058 [Byte1]: 46
8583 12:17:46.379441
8584 12:17:46.379565 Set Vref, RX VrefLevel [Byte0]: 47
8585 12:17:46.382421 [Byte1]: 47
8586 12:17:46.387037
8587 12:17:46.387114 Set Vref, RX VrefLevel [Byte0]: 48
8588 12:17:46.390040 [Byte1]: 48
8589 12:17:46.394771
8590 12:17:46.394853 Set Vref, RX VrefLevel [Byte0]: 49
8591 12:17:46.397641 [Byte1]: 49
8592 12:17:46.401931
8593 12:17:46.402013 Set Vref, RX VrefLevel [Byte0]: 50
8594 12:17:46.405397 [Byte1]: 50
8595 12:17:46.409643
8596 12:17:46.409725 Set Vref, RX VrefLevel [Byte0]: 51
8597 12:17:46.412884 [Byte1]: 51
8598 12:17:46.416935
8599 12:17:46.417017 Set Vref, RX VrefLevel [Byte0]: 52
8600 12:17:46.420477 [Byte1]: 52
8601 12:17:46.424596
8602 12:17:46.424701 Set Vref, RX VrefLevel [Byte0]: 53
8603 12:17:46.427845 [Byte1]: 53
8604 12:17:46.432175
8605 12:17:46.432252 Set Vref, RX VrefLevel [Byte0]: 54
8606 12:17:46.435408 [Byte1]: 54
8607 12:17:46.439918
8608 12:17:46.439990 Set Vref, RX VrefLevel [Byte0]: 55
8609 12:17:46.443095 [Byte1]: 55
8610 12:17:46.446927
8611 12:17:46.446994 Set Vref, RX VrefLevel [Byte0]: 56
8612 12:17:46.450747 [Byte1]: 56
8613 12:17:46.454631
8614 12:17:46.454706 Set Vref, RX VrefLevel [Byte0]: 57
8615 12:17:46.458094 [Byte1]: 57
8616 12:17:46.462468
8617 12:17:46.462542 Set Vref, RX VrefLevel [Byte0]: 58
8618 12:17:46.465599 [Byte1]: 58
8619 12:17:46.470120
8620 12:17:46.470189 Set Vref, RX VrefLevel [Byte0]: 59
8621 12:17:46.473349 [Byte1]: 59
8622 12:17:46.477051
8623 12:17:46.477134 Set Vref, RX VrefLevel [Byte0]: 60
8624 12:17:46.480277 [Byte1]: 60
8625 12:17:46.485076
8626 12:17:46.485162 Set Vref, RX VrefLevel [Byte0]: 61
8627 12:17:46.487917 [Byte1]: 61
8628 12:17:46.492577
8629 12:17:46.492659 Set Vref, RX VrefLevel [Byte0]: 62
8630 12:17:46.495646 [Byte1]: 62
8631 12:17:46.499789
8632 12:17:46.499871 Set Vref, RX VrefLevel [Byte0]: 63
8633 12:17:46.503335 [Byte1]: 63
8634 12:17:46.507806
8635 12:17:46.507887 Set Vref, RX VrefLevel [Byte0]: 64
8636 12:17:46.510457 [Byte1]: 64
8637 12:17:46.515098
8638 12:17:46.515180 Set Vref, RX VrefLevel [Byte0]: 65
8639 12:17:46.518003 [Byte1]: 65
8640 12:17:46.522687
8641 12:17:46.522768 Set Vref, RX VrefLevel [Byte0]: 66
8642 12:17:46.525685 [Byte1]: 66
8643 12:17:46.529925
8644 12:17:46.530007 Set Vref, RX VrefLevel [Byte0]: 67
8645 12:17:46.533308 [Byte1]: 67
8646 12:17:46.537554
8647 12:17:46.537661 Set Vref, RX VrefLevel [Byte0]: 68
8648 12:17:46.541223 [Byte1]: 68
8649 12:17:46.545115
8650 12:17:46.545197 Set Vref, RX VrefLevel [Byte0]: 69
8651 12:17:46.548539 [Byte1]: 69
8652 12:17:46.552974
8653 12:17:46.553057 Set Vref, RX VrefLevel [Byte0]: 70
8654 12:17:46.555969 [Byte1]: 70
8655 12:17:46.560584
8656 12:17:46.560691 Set Vref, RX VrefLevel [Byte0]: 71
8657 12:17:46.563556 [Byte1]: 71
8658 12:17:46.567688
8659 12:17:46.567769 Set Vref, RX VrefLevel [Byte0]: 72
8660 12:17:46.571017 [Byte1]: 72
8661 12:17:46.575419
8662 12:17:46.575501 Set Vref, RX VrefLevel [Byte0]: 73
8663 12:17:46.578943 [Byte1]: 73
8664 12:17:46.582825
8665 12:17:46.582906 Set Vref, RX VrefLevel [Byte0]: 74
8666 12:17:46.586148 [Byte1]: 74
8667 12:17:46.590436
8668 12:17:46.590513 Set Vref, RX VrefLevel [Byte0]: 75
8669 12:17:46.593470 [Byte1]: 75
8670 12:17:46.598275
8671 12:17:46.598350 Final RX Vref Byte 0 = 57 to rank0
8672 12:17:46.601317 Final RX Vref Byte 1 = 57 to rank0
8673 12:17:46.604427 Final RX Vref Byte 0 = 57 to rank1
8674 12:17:46.607627 Final RX Vref Byte 1 = 57 to rank1==
8675 12:17:46.611177 Dram Type= 6, Freq= 0, CH_1, rank 0
8676 12:17:46.617749 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8677 12:17:46.617824 ==
8678 12:17:46.617887 DQS Delay:
8679 12:17:46.617945 DQS0 = 0, DQS1 = 0
8680 12:17:46.621527 DQM Delay:
8681 12:17:46.621598 DQM0 = 134, DQM1 = 131
8682 12:17:46.624681 DQ Delay:
8683 12:17:46.627725 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8684 12:17:46.630975 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8685 12:17:46.634371 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8686 12:17:46.637835 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8687 12:17:46.637907
8688 12:17:46.637967
8689 12:17:46.638023
8690 12:17:46.641149 [DramC_TX_OE_Calibration] TA2
8691 12:17:46.644453 Original DQ_B0 (3 6) =30, OEN = 27
8692 12:17:46.647928 Original DQ_B1 (3 6) =30, OEN = 27
8693 12:17:46.650882 24, 0x0, End_B0=24 End_B1=24
8694 12:17:46.650956 25, 0x0, End_B0=25 End_B1=25
8695 12:17:46.655157 26, 0x0, End_B0=26 End_B1=26
8696 12:17:46.658479 27, 0x0, End_B0=27 End_B1=27
8697 12:17:46.660816 28, 0x0, End_B0=28 End_B1=28
8698 12:17:46.660896 29, 0x0, End_B0=29 End_B1=29
8699 12:17:46.664276 30, 0x0, End_B0=30 End_B1=30
8700 12:17:46.667689 31, 0x4141, End_B0=30 End_B1=30
8701 12:17:46.670820 Byte0 end_step=30 best_step=27
8702 12:17:46.674590 Byte1 end_step=30 best_step=27
8703 12:17:46.678069 Byte0 TX OE(2T, 0.5T) = (3, 3)
8704 12:17:46.678155 Byte1 TX OE(2T, 0.5T) = (3, 3)
8705 12:17:46.680952
8706 12:17:46.681033
8707 12:17:46.687432 [DQSOSCAuto] RK0, (LSB)MR18= 0x1724, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8708 12:17:46.691439 CH1 RK0: MR19=303, MR18=1724
8709 12:17:46.697779 CH1_RK0: MR19=0x303, MR18=0x1724, DQSOSC=391, MR23=63, INC=24, DEC=16
8710 12:17:46.697886
8711 12:17:46.700647 ----->DramcWriteLeveling(PI) begin...
8712 12:17:46.700730 ==
8713 12:17:46.704238 Dram Type= 6, Freq= 0, CH_1, rank 1
8714 12:17:46.707508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8715 12:17:46.707591 ==
8716 12:17:46.710726 Write leveling (Byte 0): 25 => 25
8717 12:17:46.714364 Write leveling (Byte 1): 28 => 28
8718 12:17:46.717363 DramcWriteLeveling(PI) end<-----
8719 12:17:46.717451
8720 12:17:46.717533 ==
8721 12:17:46.720818 Dram Type= 6, Freq= 0, CH_1, rank 1
8722 12:17:46.724531 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8723 12:17:46.724614 ==
8724 12:17:46.727399 [Gating] SW mode calibration
8725 12:17:46.734090 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8726 12:17:46.741202 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8727 12:17:46.744274 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8728 12:17:46.747649 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8729 12:17:46.754021 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8730 12:17:46.757855 1 4 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
8731 12:17:46.760651 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8732 12:17:46.767481 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8733 12:17:46.771158 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8734 12:17:46.774366 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8735 12:17:46.780739 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8736 12:17:46.784557 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8737 12:17:46.787431 1 5 8 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
8738 12:17:46.794099 1 5 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 1)
8739 12:17:46.797587 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8740 12:17:46.801109 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8741 12:17:46.807425 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8742 12:17:46.810863 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 12:17:46.813834 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 12:17:46.817826 1 6 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8745 12:17:46.824503 1 6 8 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
8746 12:17:46.827442 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8747 12:17:46.830784 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8748 12:17:46.837392 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8749 12:17:46.840549 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8750 12:17:46.844208 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 12:17:46.850712 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 12:17:46.853951 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8753 12:17:46.857070 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8754 12:17:46.863694 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8755 12:17:46.867343 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8756 12:17:46.870527 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8757 12:17:46.876988 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 12:17:46.880621 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 12:17:46.883730 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 12:17:46.890694 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 12:17:46.893951 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 12:17:46.897099 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 12:17:46.904156 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 12:17:46.907308 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 12:17:46.910664 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 12:17:46.916996 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 12:17:46.920173 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 12:17:46.923530 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8769 12:17:46.930480 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8770 12:17:46.933649 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8771 12:17:46.936836 Total UI for P1: 0, mck2ui 16
8772 12:17:46.940462 best dqsien dly found for B1: ( 1, 9, 6)
8773 12:17:46.943749 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8774 12:17:46.946950 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 12:17:46.950406 Total UI for P1: 0, mck2ui 16
8776 12:17:46.953856 best dqsien dly found for B0: ( 1, 9, 14)
8777 12:17:46.957560 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8778 12:17:46.960171 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8779 12:17:46.963872
8780 12:17:46.966989 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8781 12:17:46.970141 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8782 12:17:46.973718 [Gating] SW calibration Done
8783 12:17:46.973800 ==
8784 12:17:46.976920 Dram Type= 6, Freq= 0, CH_1, rank 1
8785 12:17:46.980790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8786 12:17:46.980873 ==
8787 12:17:46.980955 RX Vref Scan: 0
8788 12:17:46.983716
8789 12:17:46.983797 RX Vref 0 -> 0, step: 1
8790 12:17:46.983895
8791 12:17:46.986981 RX Delay 0 -> 252, step: 8
8792 12:17:46.990532 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8793 12:17:46.993749 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8794 12:17:47.000172 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8795 12:17:47.003264 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8796 12:17:47.006486 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8797 12:17:47.010449 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8798 12:17:47.013559 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8799 12:17:47.020294 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8800 12:17:47.023490 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8801 12:17:47.026839 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8802 12:17:47.030092 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8803 12:17:47.033379 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8804 12:17:47.039934 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8805 12:17:47.043093 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8806 12:17:47.046421 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8807 12:17:47.049757 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8808 12:17:47.049839 ==
8809 12:17:47.053414 Dram Type= 6, Freq= 0, CH_1, rank 1
8810 12:17:47.059790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8811 12:17:47.059873 ==
8812 12:17:47.059955 DQS Delay:
8813 12:17:47.062905 DQS0 = 0, DQS1 = 0
8814 12:17:47.062986 DQM Delay:
8815 12:17:47.063069 DQM0 = 136, DQM1 = 133
8816 12:17:47.066373 DQ Delay:
8817 12:17:47.069523 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8818 12:17:47.073103 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8819 12:17:47.076418 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8820 12:17:47.079541 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8821 12:17:47.079623
8822 12:17:47.079721
8823 12:17:47.079816 ==
8824 12:17:47.082877 Dram Type= 6, Freq= 0, CH_1, rank 1
8825 12:17:47.086625 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 12:17:47.089839 ==
8827 12:17:47.089922
8828 12:17:47.090003
8829 12:17:47.090080 TX Vref Scan disable
8830 12:17:47.092769 == TX Byte 0 ==
8831 12:17:47.096550 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8832 12:17:47.099803 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8833 12:17:47.102834 == TX Byte 1 ==
8834 12:17:47.106192 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8835 12:17:47.109859 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8836 12:17:47.113033 ==
8837 12:17:47.113115 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 12:17:47.119881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 12:17:47.119964 ==
8840 12:17:47.131973
8841 12:17:47.135345 TX Vref early break, caculate TX vref
8842 12:17:47.138080 TX Vref=16, minBit 0, minWin=23, winSum=384
8843 12:17:47.141941 TX Vref=18, minBit 1, minWin=24, winSum=394
8844 12:17:47.145263 TX Vref=20, minBit 0, minWin=24, winSum=398
8845 12:17:47.148325 TX Vref=22, minBit 0, minWin=25, winSum=412
8846 12:17:47.151660 TX Vref=24, minBit 0, minWin=25, winSum=418
8847 12:17:47.157941 TX Vref=26, minBit 0, minWin=25, winSum=423
8848 12:17:47.161655 TX Vref=28, minBit 0, minWin=25, winSum=428
8849 12:17:47.164997 TX Vref=30, minBit 1, minWin=25, winSum=420
8850 12:17:47.167858 TX Vref=32, minBit 1, minWin=25, winSum=412
8851 12:17:47.171454 TX Vref=34, minBit 6, minWin=23, winSum=403
8852 12:17:47.178203 [TxChooseVref] Worse bit 0, Min win 25, Win sum 428, Final Vref 28
8853 12:17:47.178281
8854 12:17:47.181389 Final TX Range 0 Vref 28
8855 12:17:47.181461
8856 12:17:47.181521 ==
8857 12:17:47.184659 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 12:17:47.187803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 12:17:47.187875 ==
8860 12:17:47.187941
8861 12:17:47.188000
8862 12:17:47.191392 TX Vref Scan disable
8863 12:17:47.198190 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8864 12:17:47.198272 == TX Byte 0 ==
8865 12:17:47.201244 u2DelayCellOfst[0]=20 cells (6 PI)
8866 12:17:47.204807 u2DelayCellOfst[1]=10 cells (3 PI)
8867 12:17:47.207920 u2DelayCellOfst[2]=0 cells (0 PI)
8868 12:17:47.211256 u2DelayCellOfst[3]=6 cells (2 PI)
8869 12:17:47.214848 u2DelayCellOfst[4]=10 cells (3 PI)
8870 12:17:47.218119 u2DelayCellOfst[5]=16 cells (5 PI)
8871 12:17:47.221320 u2DelayCellOfst[6]=16 cells (5 PI)
8872 12:17:47.221399 u2DelayCellOfst[7]=6 cells (2 PI)
8873 12:17:47.228384 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8874 12:17:47.231532 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8875 12:17:47.231613 == TX Byte 1 ==
8876 12:17:47.234589 u2DelayCellOfst[8]=0 cells (0 PI)
8877 12:17:47.237917 u2DelayCellOfst[9]=3 cells (1 PI)
8878 12:17:47.240950 u2DelayCellOfst[10]=10 cells (3 PI)
8879 12:17:47.244657 u2DelayCellOfst[11]=6 cells (2 PI)
8880 12:17:47.247685 u2DelayCellOfst[12]=13 cells (4 PI)
8881 12:17:47.251202 u2DelayCellOfst[13]=16 cells (5 PI)
8882 12:17:47.254280 u2DelayCellOfst[14]=16 cells (5 PI)
8883 12:17:47.258117 u2DelayCellOfst[15]=16 cells (5 PI)
8884 12:17:47.261437 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8885 12:17:47.267607 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8886 12:17:47.267680 DramC Write-DBI on
8887 12:17:47.267742 ==
8888 12:17:47.271560 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 12:17:47.274826 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 12:17:47.274904 ==
8891 12:17:47.277996
8892 12:17:47.278072
8893 12:17:47.278133 TX Vref Scan disable
8894 12:17:47.281094 == TX Byte 0 ==
8895 12:17:47.284755 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8896 12:17:47.287753 == TX Byte 1 ==
8897 12:17:47.291259 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8898 12:17:47.291353 DramC Write-DBI off
8899 12:17:47.291416
8900 12:17:47.294343 [DATLAT]
8901 12:17:47.294412 Freq=1600, CH1 RK1
8902 12:17:47.294478
8903 12:17:47.297607 DATLAT Default: 0xf
8904 12:17:47.297683 0, 0xFFFF, sum = 0
8905 12:17:47.301385 1, 0xFFFF, sum = 0
8906 12:17:47.301456 2, 0xFFFF, sum = 0
8907 12:17:47.304524 3, 0xFFFF, sum = 0
8908 12:17:47.304593 4, 0xFFFF, sum = 0
8909 12:17:47.307637 5, 0xFFFF, sum = 0
8910 12:17:47.307712 6, 0xFFFF, sum = 0
8911 12:17:47.311122 7, 0xFFFF, sum = 0
8912 12:17:47.314681 8, 0xFFFF, sum = 0
8913 12:17:47.314759 9, 0xFFFF, sum = 0
8914 12:17:47.317641 10, 0xFFFF, sum = 0
8915 12:17:47.317717 11, 0xFFFF, sum = 0
8916 12:17:47.320871 12, 0xFFFF, sum = 0
8917 12:17:47.320948 13, 0xFFFF, sum = 0
8918 12:17:47.324325 14, 0x0, sum = 1
8919 12:17:47.324411 15, 0x0, sum = 2
8920 12:17:47.328026 16, 0x0, sum = 3
8921 12:17:47.328097 17, 0x0, sum = 4
8922 12:17:47.331135 best_step = 15
8923 12:17:47.331211
8924 12:17:47.331272 ==
8925 12:17:47.333981 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 12:17:47.337589 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 12:17:47.337696 ==
8928 12:17:47.337787 RX Vref Scan: 0
8929 12:17:47.337874
8930 12:17:47.340725 RX Vref 0 -> 0, step: 1
8931 12:17:47.340795
8932 12:17:47.344264 RX Delay 19 -> 252, step: 4
8933 12:17:47.347477 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8934 12:17:47.351215 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8935 12:17:47.357279 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8936 12:17:47.360944 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8937 12:17:47.364255 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8938 12:17:47.367383 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8939 12:17:47.370866 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8940 12:17:47.377379 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8941 12:17:47.380714 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8942 12:17:47.384154 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8943 12:17:47.387504 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8944 12:17:47.390762 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8945 12:17:47.397328 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8946 12:17:47.401101 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8947 12:17:47.403812 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8948 12:17:47.407495 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8949 12:17:47.407573 ==
8950 12:17:47.410827 Dram Type= 6, Freq= 0, CH_1, rank 1
8951 12:17:47.417149 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8952 12:17:47.417229 ==
8953 12:17:47.417309 DQS Delay:
8954 12:17:47.420420 DQS0 = 0, DQS1 = 0
8955 12:17:47.420522 DQM Delay:
8956 12:17:47.420618 DQM0 = 134, DQM1 = 130
8957 12:17:47.423624 DQ Delay:
8958 12:17:47.427286 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8959 12:17:47.430993 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8960 12:17:47.434170 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8961 12:17:47.437501 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8962 12:17:47.437583
8963 12:17:47.437666
8964 12:17:47.437744
8965 12:17:47.440634 [DramC_TX_OE_Calibration] TA2
8966 12:17:47.444094 Original DQ_B0 (3 6) =30, OEN = 27
8967 12:17:47.447428 Original DQ_B1 (3 6) =30, OEN = 27
8968 12:17:47.450991 24, 0x0, End_B0=24 End_B1=24
8969 12:17:47.451166 25, 0x0, End_B0=25 End_B1=25
8970 12:17:47.453883 26, 0x0, End_B0=26 End_B1=26
8971 12:17:47.457124 27, 0x0, End_B0=27 End_B1=27
8972 12:17:47.460543 28, 0x0, End_B0=28 End_B1=28
8973 12:17:47.464084 29, 0x0, End_B0=29 End_B1=29
8974 12:17:47.464268 30, 0x0, End_B0=30 End_B1=30
8975 12:17:47.467239 31, 0x5151, End_B0=30 End_B1=30
8976 12:17:47.470435 Byte0 end_step=30 best_step=27
8977 12:17:47.473783 Byte1 end_step=30 best_step=27
8978 12:17:47.477651 Byte0 TX OE(2T, 0.5T) = (3, 3)
8979 12:17:47.480834 Byte1 TX OE(2T, 0.5T) = (3, 3)
8980 12:17:47.481089
8981 12:17:47.481284
8982 12:17:47.487377 [DQSOSCAuto] RK1, (LSB)MR18= 0x2006, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
8983 12:17:47.490931 CH1 RK1: MR19=303, MR18=2006
8984 12:17:47.497380 CH1_RK1: MR19=0x303, MR18=0x2006, DQSOSC=393, MR23=63, INC=23, DEC=15
8985 12:17:47.501245 [RxdqsGatingPostProcess] freq 1600
8986 12:17:47.504519 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8987 12:17:47.507451 best DQS0 dly(2T, 0.5T) = (1, 1)
8988 12:17:47.511269 best DQS1 dly(2T, 0.5T) = (1, 1)
8989 12:17:47.514325 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8990 12:17:47.517356 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8991 12:17:47.520825 best DQS0 dly(2T, 0.5T) = (1, 1)
8992 12:17:47.523986 best DQS1 dly(2T, 0.5T) = (1, 1)
8993 12:17:47.527189 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8994 12:17:47.531304 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8995 12:17:47.534032 Pre-setting of DQS Precalculation
8996 12:17:47.537192 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8997 12:17:47.543881 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8998 12:17:47.550894 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8999 12:17:47.553950
9000 12:17:47.554414
9001 12:17:47.554886 [Calibration Summary] 3200 Mbps
9002 12:17:47.557102 CH 0, Rank 0
9003 12:17:47.557566 SW Impedance : PASS
9004 12:17:47.560400 DUTY Scan : NO K
9005 12:17:47.563473 ZQ Calibration : PASS
9006 12:17:47.563980 Jitter Meter : NO K
9007 12:17:47.567662 CBT Training : PASS
9008 12:17:47.570307 Write leveling : PASS
9009 12:17:47.570774 RX DQS gating : PASS
9010 12:17:47.573487 RX DQ/DQS(RDDQC) : PASS
9011 12:17:47.577581 TX DQ/DQS : PASS
9012 12:17:47.578107 RX DATLAT : PASS
9013 12:17:47.580673 RX DQ/DQS(Engine): PASS
9014 12:17:47.584055 TX OE : PASS
9015 12:17:47.584539 All Pass.
9016 12:17:47.585007
9017 12:17:47.585409 CH 0, Rank 1
9018 12:17:47.587273 SW Impedance : PASS
9019 12:17:47.590620 DUTY Scan : NO K
9020 12:17:47.591168 ZQ Calibration : PASS
9021 12:17:47.593570 Jitter Meter : NO K
9022 12:17:47.596893 CBT Training : PASS
9023 12:17:47.597467 Write leveling : PASS
9024 12:17:47.599946 RX DQS gating : PASS
9025 12:17:47.603546 RX DQ/DQS(RDDQC) : PASS
9026 12:17:47.603969 TX DQ/DQS : PASS
9027 12:17:47.606660 RX DATLAT : PASS
9028 12:17:47.607105 RX DQ/DQS(Engine): PASS
9029 12:17:47.610088 TX OE : PASS
9030 12:17:47.610510 All Pass.
9031 12:17:47.610963
9032 12:17:47.613308 CH 1, Rank 0
9033 12:17:47.613855 SW Impedance : PASS
9034 12:17:47.617445 DUTY Scan : NO K
9035 12:17:47.620196 ZQ Calibration : PASS
9036 12:17:47.620685 Jitter Meter : NO K
9037 12:17:47.623180 CBT Training : PASS
9038 12:17:47.626938 Write leveling : PASS
9039 12:17:47.627390 RX DQS gating : PASS
9040 12:17:47.630595 RX DQ/DQS(RDDQC) : PASS
9041 12:17:47.633333 TX DQ/DQS : PASS
9042 12:17:47.633757 RX DATLAT : PASS
9043 12:17:47.636658 RX DQ/DQS(Engine): PASS
9044 12:17:47.640357 TX OE : PASS
9045 12:17:47.640785 All Pass.
9046 12:17:47.641210
9047 12:17:47.641641 CH 1, Rank 1
9048 12:17:47.643297 SW Impedance : PASS
9049 12:17:47.647153 DUTY Scan : NO K
9050 12:17:47.647577 ZQ Calibration : PASS
9051 12:17:47.650768 Jitter Meter : NO K
9052 12:17:47.653571 CBT Training : PASS
9053 12:17:47.654033 Write leveling : PASS
9054 12:17:47.656985 RX DQS gating : PASS
9055 12:17:47.657509 RX DQ/DQS(RDDQC) : PASS
9056 12:17:47.660004 TX DQ/DQS : PASS
9057 12:17:47.663706 RX DATLAT : PASS
9058 12:17:47.664137 RX DQ/DQS(Engine): PASS
9059 12:17:47.666968 TX OE : PASS
9060 12:17:47.667390 All Pass.
9061 12:17:47.667818
9062 12:17:47.670161 DramC Write-DBI on
9063 12:17:47.673988 PER_BANK_REFRESH: Hybrid Mode
9064 12:17:47.674520 TX_TRACKING: ON
9065 12:17:47.683860 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9066 12:17:47.690523 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9067 12:17:47.697237 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9068 12:17:47.700394 [FAST_K] Save calibration result to emmc
9069 12:17:47.703952 sync common calibartion params.
9070 12:17:47.706773 sync cbt_mode0:1, 1:1
9071 12:17:47.710689 dram_init: ddr_geometry: 2
9072 12:17:47.711245 dram_init: ddr_geometry: 2
9073 12:17:47.713244 dram_init: ddr_geometry: 2
9074 12:17:47.716654 0:dram_rank_size:100000000
9075 12:17:47.720706 1:dram_rank_size:100000000
9076 12:17:47.723330 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9077 12:17:47.726543 DFS_SHUFFLE_HW_MODE: ON
9078 12:17:47.730041 dramc_set_vcore_voltage set vcore to 725000
9079 12:17:47.733018 Read voltage for 1600, 0
9080 12:17:47.733473 Vio18 = 0
9081 12:17:47.733832 Vcore = 725000
9082 12:17:47.736524 Vdram = 0
9083 12:17:47.736975 Vddq = 0
9084 12:17:47.737330 Vmddr = 0
9085 12:17:47.739826 switch to 3200 Mbps bootup
9086 12:17:47.743443 [DramcRunTimeConfig]
9087 12:17:47.744038 PHYPLL
9088 12:17:47.744460 DPM_CONTROL_AFTERK: ON
9089 12:17:47.746754 PER_BANK_REFRESH: ON
9090 12:17:47.750318 REFRESH_OVERHEAD_REDUCTION: ON
9091 12:17:47.750863 CMD_PICG_NEW_MODE: OFF
9092 12:17:47.753120 XRTWTW_NEW_MODE: ON
9093 12:17:47.756638 XRTRTR_NEW_MODE: ON
9094 12:17:47.757098 TX_TRACKING: ON
9095 12:17:47.760363 RDSEL_TRACKING: OFF
9096 12:17:47.760924 DQS Precalculation for DVFS: ON
9097 12:17:47.763320 RX_TRACKING: OFF
9098 12:17:47.763800 HW_GATING DBG: ON
9099 12:17:47.766752 ZQCS_ENABLE_LP4: ON
9100 12:17:47.767325 RX_PICG_NEW_MODE: ON
9101 12:17:47.770311 TX_PICG_NEW_MODE: ON
9102 12:17:47.773177 ENABLE_RX_DCM_DPHY: ON
9103 12:17:47.776847 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9104 12:17:47.777308 DUMMY_READ_FOR_TRACKING: OFF
9105 12:17:47.779932 !!! SPM_CONTROL_AFTERK: OFF
9106 12:17:47.783685 !!! SPM could not control APHY
9107 12:17:47.787047 IMPEDANCE_TRACKING: ON
9108 12:17:47.787606 TEMP_SENSOR: ON
9109 12:17:47.790117 HW_SAVE_FOR_SR: OFF
9110 12:17:47.790678 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9111 12:17:47.796547 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9112 12:17:47.797113 Read ODT Tracking: ON
9113 12:17:47.799953 Refresh Rate DeBounce: ON
9114 12:17:47.800592 DFS_NO_QUEUE_FLUSH: ON
9115 12:17:47.803201 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9116 12:17:47.806570 ENABLE_DFS_RUNTIME_MRW: OFF
9117 12:17:47.809941 DDR_RESERVE_NEW_MODE: ON
9118 12:17:47.810500 MR_CBT_SWITCH_FREQ: ON
9119 12:17:47.813226 =========================
9120 12:17:47.832632 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9121 12:17:47.835948 dram_init: ddr_geometry: 2
9122 12:17:47.854117 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9123 12:17:47.857046 dram_init: dram init end (result: 0)
9124 12:17:47.864104 DRAM-K: Full calibration passed in 24429 msecs
9125 12:17:47.867474 MRC: failed to locate region type 0.
9126 12:17:47.868031 DRAM rank0 size:0x100000000,
9127 12:17:47.870757 DRAM rank1 size=0x100000000
9128 12:17:47.880764 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9129 12:17:47.886910 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9130 12:17:47.893508 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9131 12:17:47.900341 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9132 12:17:47.903889 DRAM rank0 size:0x100000000,
9133 12:17:47.907040 DRAM rank1 size=0x100000000
9134 12:17:47.907502 CBMEM:
9135 12:17:47.910465 IMD: root @ 0xfffff000 254 entries.
9136 12:17:47.913499 IMD: root @ 0xffffec00 62 entries.
9137 12:17:47.917276 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9138 12:17:47.923862 WARNING: RO_VPD is uninitialized or empty.
9139 12:17:47.927018 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9140 12:17:47.934152 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9141 12:17:47.946807 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9142 12:17:47.958426 BS: romstage times (exec / console): total (unknown) / 23967 ms
9143 12:17:47.958984
9144 12:17:47.959346
9145 12:17:47.968136 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9146 12:17:47.972099 ARM64: Exception handlers installed.
9147 12:17:47.975061 ARM64: Testing exception
9148 12:17:47.978191 ARM64: Done test exception
9149 12:17:47.978827 Enumerating buses...
9150 12:17:47.981486 Show all devs... Before device enumeration.
9151 12:17:47.984455 Root Device: enabled 1
9152 12:17:47.988104 CPU_CLUSTER: 0: enabled 1
9153 12:17:47.988712 CPU: 00: enabled 1
9154 12:17:47.991246 Compare with tree...
9155 12:17:47.991707 Root Device: enabled 1
9156 12:17:47.994389 CPU_CLUSTER: 0: enabled 1
9157 12:17:47.998408 CPU: 00: enabled 1
9158 12:17:47.998917 Root Device scanning...
9159 12:17:48.001492 scan_static_bus for Root Device
9160 12:17:48.004359 CPU_CLUSTER: 0 enabled
9161 12:17:48.008282 scan_static_bus for Root Device done
9162 12:17:48.011431 scan_bus: bus Root Device finished in 8 msecs
9163 12:17:48.011993 done
9164 12:17:48.018347 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9165 12:17:48.020855 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9166 12:17:48.027581 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9167 12:17:48.031307 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9168 12:17:48.034492 Allocating resources...
9169 12:17:48.037814 Reading resources...
9170 12:17:48.041239 Root Device read_resources bus 0 link: 0
9171 12:17:48.041695 DRAM rank0 size:0x100000000,
9172 12:17:48.045042 DRAM rank1 size=0x100000000
9173 12:17:48.047892 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9174 12:17:48.051169 CPU: 00 missing read_resources
9175 12:17:48.057261 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9176 12:17:48.061281 Root Device read_resources bus 0 link: 0 done
9177 12:17:48.061869 Done reading resources.
9178 12:17:48.068017 Show resources in subtree (Root Device)...After reading.
9179 12:17:48.071154 Root Device child on link 0 CPU_CLUSTER: 0
9180 12:17:48.074041 CPU_CLUSTER: 0 child on link 0 CPU: 00
9181 12:17:48.084439 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9182 12:17:48.084994 CPU: 00
9183 12:17:48.087277 Root Device assign_resources, bus 0 link: 0
9184 12:17:48.090862 CPU_CLUSTER: 0 missing set_resources
9185 12:17:48.097571 Root Device assign_resources, bus 0 link: 0 done
9186 12:17:48.098036 Done setting resources.
9187 12:17:48.104371 Show resources in subtree (Root Device)...After assigning values.
9188 12:17:48.107568 Root Device child on link 0 CPU_CLUSTER: 0
9189 12:17:48.110890 CPU_CLUSTER: 0 child on link 0 CPU: 00
9190 12:17:48.120459 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9191 12:17:48.121004 CPU: 00
9192 12:17:48.123484 Done allocating resources.
9193 12:17:48.126968 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9194 12:17:48.130262 Enabling resources...
9195 12:17:48.130787 done.
9196 12:17:48.136974 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9197 12:17:48.137436 Initializing devices...
9198 12:17:48.140316 Root Device init
9199 12:17:48.140831 init hardware done!
9200 12:17:48.143975 0x00000018: ctrlr->caps
9201 12:17:48.147255 52.000 MHz: ctrlr->f_max
9202 12:17:48.147818 0.400 MHz: ctrlr->f_min
9203 12:17:48.150312 0x40ff8080: ctrlr->voltages
9204 12:17:48.153897 sclk: 390625
9205 12:17:48.154353 Bus Width = 1
9206 12:17:48.154716 sclk: 390625
9207 12:17:48.156919 Bus Width = 1
9208 12:17:48.157502 Early init status = 3
9209 12:17:48.163901 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9210 12:17:48.167114 in-header: 03 fc 00 00 01 00 00 00
9211 12:17:48.167754 in-data: 00
9212 12:17:48.173613 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9213 12:17:48.176710 in-header: 03 fd 00 00 00 00 00 00
9214 12:17:48.180609 in-data:
9215 12:17:48.184189 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9216 12:17:48.187332 in-header: 03 fc 00 00 01 00 00 00
9217 12:17:48.190565 in-data: 00
9218 12:17:48.193501 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9219 12:17:48.199157 in-header: 03 fd 00 00 00 00 00 00
9220 12:17:48.201803 in-data:
9221 12:17:48.205611 [SSUSB] Setting up USB HOST controller...
9222 12:17:48.208912 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9223 12:17:48.212272 [SSUSB] phy power-on done.
9224 12:17:48.215404 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9225 12:17:48.221660 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9226 12:17:48.225461 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9227 12:17:48.231660 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9228 12:17:48.238225 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9229 12:17:48.245014 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9230 12:17:48.252389 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9231 12:17:48.258583 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9232 12:17:48.259216 SPM: binary array size = 0x9dc
9233 12:17:48.265449 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9234 12:17:48.271903 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9235 12:17:48.278370 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9236 12:17:48.282071 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9237 12:17:48.288223 configure_display: Starting display init
9238 12:17:48.321656 anx7625_power_on_init: Init interface.
9239 12:17:48.325726 anx7625_disable_pd_protocol: Disabled PD feature.
9240 12:17:48.328863 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9241 12:17:48.356747 anx7625_start_dp_work: Secure OCM version=00
9242 12:17:48.359774 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9243 12:17:48.374531 sp_tx_get_edid_block: EDID Block = 1
9244 12:17:48.476812 Extracted contents:
9245 12:17:48.480280 header: 00 ff ff ff ff ff ff 00
9246 12:17:48.483808 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9247 12:17:48.486688 version: 01 04
9248 12:17:48.490048 basic params: 95 1f 11 78 0a
9249 12:17:48.493324 chroma info: 76 90 94 55 54 90 27 21 50 54
9250 12:17:48.496812 established: 00 00 00
9251 12:17:48.503255 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9252 12:17:48.507141 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9253 12:17:48.513915 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9254 12:17:48.519686 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9255 12:17:48.526257 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9256 12:17:48.529968 extensions: 00
9257 12:17:48.530383 checksum: fb
9258 12:17:48.530711
9259 12:17:48.533343 Manufacturer: IVO Model 57d Serial Number 0
9260 12:17:48.536515 Made week 0 of 2020
9261 12:17:48.536931 EDID version: 1.4
9262 12:17:48.540052 Digital display
9263 12:17:48.542961 6 bits per primary color channel
9264 12:17:48.543383 DisplayPort interface
9265 12:17:48.546860 Maximum image size: 31 cm x 17 cm
9266 12:17:48.549683 Gamma: 220%
9267 12:17:48.550188 Check DPMS levels
9268 12:17:48.552804 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9269 12:17:48.559619 First detailed timing is preferred timing
9270 12:17:48.560038 Established timings supported:
9271 12:17:48.563076 Standard timings supported:
9272 12:17:48.566317 Detailed timings
9273 12:17:48.569768 Hex of detail: 383680a07038204018303c0035ae10000019
9274 12:17:48.573012 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9275 12:17:48.580096 0780 0798 07c8 0820 hborder 0
9276 12:17:48.583297 0438 043b 0447 0458 vborder 0
9277 12:17:48.586034 -hsync -vsync
9278 12:17:48.586450 Did detailed timing
9279 12:17:48.592951 Hex of detail: 000000000000000000000000000000000000
9280 12:17:48.596220 Manufacturer-specified data, tag 0
9281 12:17:48.599438 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9282 12:17:48.602957 ASCII string: InfoVision
9283 12:17:48.606154 Hex of detail: 000000fe00523134304e574635205248200a
9284 12:17:48.609460 ASCII string: R140NWF5 RH
9285 12:17:48.610012 Checksum
9286 12:17:48.612768 Checksum: 0xfb (valid)
9287 12:17:48.615910 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9288 12:17:48.619837 DSI data_rate: 832800000 bps
9289 12:17:48.625913 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9290 12:17:48.629188 anx7625_parse_edid: pixelclock(138800).
9291 12:17:48.632603 hactive(1920), hsync(48), hfp(24), hbp(88)
9292 12:17:48.636125 vactive(1080), vsync(12), vfp(3), vbp(17)
9293 12:17:48.639365 anx7625_dsi_config: config dsi.
9294 12:17:48.645497 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9295 12:17:48.658737 anx7625_dsi_config: success to config DSI
9296 12:17:48.662800 anx7625_dp_start: MIPI phy setup OK.
9297 12:17:48.665293 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9298 12:17:48.668836 mtk_ddp_mode_set invalid vrefresh 60
9299 12:17:48.672171 main_disp_path_setup
9300 12:17:48.672725 ovl_layer_smi_id_en
9301 12:17:48.675801 ovl_layer_smi_id_en
9302 12:17:48.676371 ccorr_config
9303 12:17:48.676727 aal_config
9304 12:17:48.678720 gamma_config
9305 12:17:48.679149 postmask_config
9306 12:17:48.682367 dither_config
9307 12:17:48.685275 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9308 12:17:48.691905 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9309 12:17:48.695180 Root Device init finished in 551 msecs
9310 12:17:48.698385 CPU_CLUSTER: 0 init
9311 12:17:48.704901 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9312 12:17:48.711595 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9313 12:17:48.712087 APU_MBOX 0x190000b0 = 0x10001
9314 12:17:48.715648 APU_MBOX 0x190001b0 = 0x10001
9315 12:17:48.718847 APU_MBOX 0x190005b0 = 0x10001
9316 12:17:48.721716 APU_MBOX 0x190006b0 = 0x10001
9317 12:17:48.728425 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9318 12:17:48.738056 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9319 12:17:48.750841 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9320 12:17:48.757095 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9321 12:17:48.768864 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9322 12:17:48.778215 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9323 12:17:48.781738 CPU_CLUSTER: 0 init finished in 81 msecs
9324 12:17:48.784463 Devices initialized
9325 12:17:48.787783 Show all devs... After init.
9326 12:17:48.788381 Root Device: enabled 1
9327 12:17:48.790771 CPU_CLUSTER: 0: enabled 1
9328 12:17:48.794534 CPU: 00: enabled 1
9329 12:17:48.797689 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9330 12:17:48.801255 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9331 12:17:48.804387 ELOG: NV offset 0x57f000 size 0x1000
9332 12:17:48.811128 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9333 12:17:48.817932 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9334 12:17:48.820726 ELOG: Event(17) added with size 13 at 2024-01-31 12:15:06 UTC
9335 12:17:48.824509 out: cmd=0x121: 03 db 21 01 00 00 00 00
9336 12:17:48.828220 in-header: 03 fb 00 00 2c 00 00 00
9337 12:17:48.841215 in-data: 64 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9338 12:17:48.848183 ELOG: Event(A1) added with size 10 at 2024-01-31 12:15:06 UTC
9339 12:17:48.854814 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9340 12:17:48.861253 ELOG: Event(A0) added with size 9 at 2024-01-31 12:15:06 UTC
9341 12:17:48.865014 elog_add_boot_reason: Logged dev mode boot
9342 12:17:48.867903 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9343 12:17:48.871204 Finalize devices...
9344 12:17:48.871752 Devices finalized
9345 12:17:48.878028 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9346 12:17:48.880875 Writing coreboot table at 0xffe64000
9347 12:17:48.884399 0. 000000000010a000-0000000000113fff: RAMSTAGE
9348 12:17:48.888260 1. 0000000040000000-00000000400fffff: RAM
9349 12:17:48.891580 2. 0000000040100000-000000004032afff: RAMSTAGE
9350 12:17:48.897789 3. 000000004032b000-00000000545fffff: RAM
9351 12:17:48.900732 4. 0000000054600000-000000005465ffff: BL31
9352 12:17:48.904627 5. 0000000054660000-00000000ffe63fff: RAM
9353 12:17:48.910574 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9354 12:17:48.914043 7. 0000000100000000-000000023fffffff: RAM
9355 12:17:48.914574 Passing 5 GPIOs to payload:
9356 12:17:48.920625 NAME | PORT | POLARITY | VALUE
9357 12:17:48.924171 EC in RW | 0x000000aa | low | undefined
9358 12:17:48.931082 EC interrupt | 0x00000005 | low | undefined
9359 12:17:48.934557 TPM interrupt | 0x000000ab | high | undefined
9360 12:17:48.937259 SD card detect | 0x00000011 | high | undefined
9361 12:17:48.944196 speaker enable | 0x00000093 | high | undefined
9362 12:17:48.947220 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9363 12:17:48.950329 in-header: 03 f9 00 00 02 00 00 00
9364 12:17:48.954173 in-data: 02 00
9365 12:17:48.954715 ADC[4]: Raw value=904726 ID=7
9366 12:17:48.957606 ADC[3]: Raw value=213441 ID=1
9367 12:17:48.960839 RAM Code: 0x71
9368 12:17:48.961295 ADC[6]: Raw value=75332 ID=0
9369 12:17:48.963848 ADC[5]: Raw value=212703 ID=1
9370 12:17:48.967110 SKU Code: 0x1
9371 12:17:48.970513 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3c49
9372 12:17:48.974182 coreboot table: 964 bytes.
9373 12:17:48.977424 IMD ROOT 0. 0xfffff000 0x00001000
9374 12:17:48.980418 IMD SMALL 1. 0xffffe000 0x00001000
9375 12:17:48.983559 RO MCACHE 2. 0xffffc000 0x00001104
9376 12:17:48.986569 CONSOLE 3. 0xfff7c000 0x00080000
9377 12:17:48.990389 FMAP 4. 0xfff7b000 0x00000452
9378 12:17:48.993853 TIME STAMP 5. 0xfff7a000 0x00000910
9379 12:17:48.996943 VBOOT WORK 6. 0xfff66000 0x00014000
9380 12:17:49.000170 RAMOOPS 7. 0xffe66000 0x00100000
9381 12:17:49.003633 COREBOOT 8. 0xffe64000 0x00002000
9382 12:17:49.004092 IMD small region:
9383 12:17:49.010011 IMD ROOT 0. 0xffffec00 0x00000400
9384 12:17:49.013114 VPD 1. 0xffffeb80 0x0000006c
9385 12:17:49.016371 MMC STATUS 2. 0xffffeb60 0x00000004
9386 12:17:49.020241 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9387 12:17:49.023607 Probing TPM: done!
9388 12:17:49.026992 Connected to device vid:did:rid of 1ae0:0028:00
9389 12:17:49.037030 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9390 12:17:49.040118 Initialized TPM device CR50 revision 0
9391 12:17:49.043968 Checking cr50 for pending updates
9392 12:17:49.047930 Reading cr50 TPM mode
9393 12:17:49.056454 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9394 12:17:49.063227 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9395 12:17:49.103087 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9396 12:17:49.106698 Checking segment from ROM address 0x40100000
9397 12:17:49.109902 Checking segment from ROM address 0x4010001c
9398 12:17:49.116459 Loading segment from ROM address 0x40100000
9399 12:17:49.117011 code (compression=0)
9400 12:17:49.126432 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9401 12:17:49.132776 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9402 12:17:49.133240 it's not compressed!
9403 12:17:49.139815 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9404 12:17:49.142730 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9405 12:17:49.164232 Loading segment from ROM address 0x4010001c
9406 12:17:49.164842 Entry Point 0x80000000
9407 12:17:49.167425 Loaded segments
9408 12:17:49.170384 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9409 12:17:49.177092 Jumping to boot code at 0x80000000(0xffe64000)
9410 12:17:49.183458 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9411 12:17:49.190309 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9412 12:17:49.197773 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9413 12:17:49.201557 Checking segment from ROM address 0x40100000
9414 12:17:49.204582 Checking segment from ROM address 0x4010001c
9415 12:17:49.211826 Loading segment from ROM address 0x40100000
9416 12:17:49.212423 code (compression=1)
9417 12:17:49.218111 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9418 12:17:49.228204 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9419 12:17:49.228805 using LZMA
9420 12:17:49.236663 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9421 12:17:49.243058 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9422 12:17:49.246456 Loading segment from ROM address 0x4010001c
9423 12:17:49.247033 Entry Point 0x54601000
9424 12:17:49.249760 Loaded segments
9425 12:17:49.253535 NOTICE: MT8192 bl31_setup
9426 12:17:49.260472 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9427 12:17:49.263882 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9428 12:17:49.266790 WARNING: region 0:
9429 12:17:49.270302 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9430 12:17:49.270847 WARNING: region 1:
9431 12:17:49.277214 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9432 12:17:49.280389 WARNING: region 2:
9433 12:17:49.283516 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9434 12:17:49.286866 WARNING: region 3:
9435 12:17:49.290073 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9436 12:17:49.293968 WARNING: region 4:
9437 12:17:49.299954 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9438 12:17:49.300564 WARNING: region 5:
9439 12:17:49.303366 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9440 12:17:49.307178 WARNING: region 6:
9441 12:17:49.309740 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9442 12:17:49.310199 WARNING: region 7:
9443 12:17:49.317006 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9444 12:17:49.323436 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9445 12:17:49.326678 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9446 12:17:49.329690 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9447 12:17:49.336532 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9448 12:17:49.339768 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9449 12:17:49.343232 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9450 12:17:49.349763 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9451 12:17:49.353300 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9452 12:17:49.356898 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9453 12:17:49.363187 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9454 12:17:49.366933 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9455 12:17:49.374007 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9456 12:17:49.377180 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9457 12:17:49.380212 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9458 12:17:49.386623 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9459 12:17:49.390043 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9460 12:17:49.394201 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9461 12:17:49.400706 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9462 12:17:49.403779 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9463 12:17:49.410298 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9464 12:17:49.413515 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9465 12:17:49.417244 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9466 12:17:49.423954 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9467 12:17:49.426898 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9468 12:17:49.433535 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9469 12:17:49.436700 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9470 12:17:49.440391 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9471 12:17:49.446947 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9472 12:17:49.450181 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9473 12:17:49.453508 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9474 12:17:49.460169 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9475 12:17:49.463261 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9476 12:17:49.467314 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9477 12:17:49.473448 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9478 12:17:49.477114 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9479 12:17:49.480538 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9480 12:17:49.484028 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9481 12:17:49.490377 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9482 12:17:49.493612 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9483 12:17:49.496837 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9484 12:17:49.500331 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9485 12:17:49.506826 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9486 12:17:49.510172 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9487 12:17:49.513437 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9488 12:17:49.517638 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9489 12:17:49.523719 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9490 12:17:49.527232 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9491 12:17:49.530155 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9492 12:17:49.537403 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9493 12:17:49.540659 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9494 12:17:49.543679 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9495 12:17:49.550935 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9496 12:17:49.553737 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9497 12:17:49.560946 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9498 12:17:49.563728 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9499 12:17:49.567136 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9500 12:17:49.574370 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9501 12:17:49.577409 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9502 12:17:49.584107 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9503 12:17:49.587187 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9504 12:17:49.593735 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9505 12:17:49.597046 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9506 12:17:49.603706 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9507 12:17:49.606682 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9508 12:17:49.610043 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9509 12:17:49.616856 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9510 12:17:49.620500 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9511 12:17:49.626950 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9512 12:17:49.630484 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9513 12:17:49.633671 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9514 12:17:49.640265 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9515 12:17:49.643649 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9516 12:17:49.650636 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9517 12:17:49.653845 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9518 12:17:49.659984 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9519 12:17:49.663832 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9520 12:17:49.667096 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9521 12:17:49.673338 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9522 12:17:49.677227 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9523 12:17:49.683726 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9524 12:17:49.687217 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9525 12:17:49.693731 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9526 12:17:49.697026 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9527 12:17:49.700683 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9528 12:17:49.707385 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9529 12:17:49.710710 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9530 12:17:49.717163 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9531 12:17:49.720879 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9532 12:17:49.727155 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9533 12:17:49.730849 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9534 12:17:49.733875 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9535 12:17:49.740682 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9536 12:17:49.743854 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9537 12:17:49.750278 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9538 12:17:49.753957 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9539 12:17:49.761054 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9540 12:17:49.764443 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9541 12:17:49.767706 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9542 12:17:49.770924 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9543 12:17:49.777529 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9544 12:17:49.781327 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9545 12:17:49.784643 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9546 12:17:49.790921 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9547 12:17:49.794162 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9548 12:17:49.801139 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9549 12:17:49.804612 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9550 12:17:49.807501 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9551 12:17:49.814210 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9552 12:17:49.817439 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9553 12:17:49.824452 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9554 12:17:49.827568 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9555 12:17:49.830710 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9556 12:17:49.837542 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9557 12:17:49.840687 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9558 12:17:49.844017 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9559 12:17:49.850647 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9560 12:17:49.853754 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9561 12:17:49.857241 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9562 12:17:49.864312 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9563 12:17:49.867412 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9564 12:17:49.870849 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9565 12:17:49.873975 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9566 12:17:49.881248 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9567 12:17:49.884360 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9568 12:17:49.887553 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9569 12:17:49.894506 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9570 12:17:49.897652 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9571 12:17:49.900799 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9572 12:17:49.907825 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9573 12:17:49.911671 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9574 12:17:49.917644 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9575 12:17:49.921569 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9576 12:17:49.924947 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9577 12:17:49.931012 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9578 12:17:49.934118 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9579 12:17:49.940886 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9580 12:17:49.944104 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9581 12:17:49.947691 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9582 12:17:49.954428 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9583 12:17:49.957855 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9584 12:17:49.961284 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9585 12:17:49.967748 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9586 12:17:49.970934 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9587 12:17:49.977630 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9588 12:17:49.981133 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9589 12:17:49.984178 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9590 12:17:49.990750 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9591 12:17:49.994111 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9592 12:17:50.000701 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9593 12:17:50.004025 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9594 12:17:50.007621 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9595 12:17:50.014226 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9596 12:17:50.017146 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9597 12:17:50.020833 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9598 12:17:50.027198 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9599 12:17:50.030434 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9600 12:17:50.037563 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9601 12:17:50.040604 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9602 12:17:50.044529 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9603 12:17:50.050981 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9604 12:17:50.054153 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9605 12:17:50.060553 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9606 12:17:50.063781 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9607 12:17:50.067662 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9608 12:17:50.074025 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9609 12:17:50.077328 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9610 12:17:50.080929 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9611 12:17:50.087590 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9612 12:17:50.090803 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9613 12:17:50.097168 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9614 12:17:50.100796 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9615 12:17:50.107070 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9616 12:17:50.111347 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9617 12:17:50.114126 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9618 12:17:50.120256 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9619 12:17:50.124057 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9620 12:17:50.127303 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9621 12:17:50.133711 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9622 12:17:50.137139 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9623 12:17:50.143643 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9624 12:17:50.146631 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9625 12:17:50.150424 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9626 12:17:50.157020 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9627 12:17:50.160236 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9628 12:17:50.166785 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9629 12:17:50.170212 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9630 12:17:50.173350 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9631 12:17:50.180098 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9632 12:17:50.183633 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9633 12:17:50.189811 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9634 12:17:50.193267 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9635 12:17:50.197009 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9636 12:17:50.203353 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9637 12:17:50.206703 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9638 12:17:50.213070 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9639 12:17:50.216369 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9640 12:17:50.223057 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9641 12:17:50.226808 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9642 12:17:50.229359 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9643 12:17:50.236091 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9644 12:17:50.239547 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9645 12:17:50.246155 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9646 12:17:50.249632 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9647 12:17:50.252711 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9648 12:17:50.259503 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9649 12:17:50.262696 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9650 12:17:50.269676 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9651 12:17:50.272900 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9652 12:17:50.276540 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9653 12:17:50.283018 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9654 12:17:50.286068 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9655 12:17:50.292573 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9656 12:17:50.296222 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9657 12:17:50.302682 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9658 12:17:50.305793 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9659 12:17:50.309004 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9660 12:17:50.315799 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9661 12:17:50.319295 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9662 12:17:50.326088 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9663 12:17:50.328973 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9664 12:17:50.336205 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9665 12:17:50.339389 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9666 12:17:50.342561 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9667 12:17:50.349305 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9668 12:17:50.352432 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9669 12:17:50.359592 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9670 12:17:50.362961 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9671 12:17:50.366045 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9672 12:17:50.372889 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9673 12:17:50.376041 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9674 12:17:50.379545 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9675 12:17:50.382350 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9676 12:17:50.389187 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9677 12:17:50.392464 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9678 12:17:50.396054 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9679 12:17:50.402537 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9680 12:17:50.405644 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9681 12:17:50.408993 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9682 12:17:50.415781 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9683 12:17:50.419065 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9684 12:17:50.422246 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9685 12:17:50.428770 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9686 12:17:50.432690 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9687 12:17:50.439440 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9688 12:17:50.442612 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9689 12:17:50.445726 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9690 12:17:50.452363 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9691 12:17:50.455484 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9692 12:17:50.459776 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9693 12:17:50.465745 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9694 12:17:50.469067 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9695 12:17:50.476229 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9696 12:17:50.478887 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9697 12:17:50.482332 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9698 12:17:50.489034 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9699 12:17:50.492214 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9700 12:17:50.495371 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9701 12:17:50.502497 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9702 12:17:50.505759 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9703 12:17:50.509137 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9704 12:17:50.515596 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9705 12:17:50.519073 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9706 12:17:50.525635 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9707 12:17:50.528974 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9708 12:17:50.532192 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9709 12:17:50.538740 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9710 12:17:50.542026 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9711 12:17:50.545257 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9712 12:17:50.551885 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9713 12:17:50.555233 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9714 12:17:50.558683 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9715 12:17:50.561837 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9716 12:17:50.569097 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9717 12:17:50.572358 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9718 12:17:50.575630 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9719 12:17:50.578812 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9720 12:17:50.581942 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9721 12:17:50.588808 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9722 12:17:50.592220 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9723 12:17:50.595134 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9724 12:17:50.601944 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9725 12:17:50.605103 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9726 12:17:50.608271 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9727 12:17:50.615227 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9728 12:17:50.618528 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9729 12:17:50.625468 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9730 12:17:50.628540 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9731 12:17:50.632112 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9732 12:17:50.638475 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9733 12:17:50.641741 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9734 12:17:50.648264 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9735 12:17:50.651444 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9736 12:17:50.654758 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9737 12:17:50.661629 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9738 12:17:50.664862 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9739 12:17:50.671313 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9740 12:17:50.675334 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9741 12:17:50.678737 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9742 12:17:50.685235 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9743 12:17:50.688831 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9744 12:17:50.695365 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9745 12:17:50.698195 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9746 12:17:50.701767 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9747 12:17:50.708245 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9748 12:17:50.711894 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9749 12:17:50.718297 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9750 12:17:50.721990 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9751 12:17:50.725518 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9752 12:17:50.731778 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9753 12:17:50.735142 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9754 12:17:50.742050 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9755 12:17:50.745244 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9756 12:17:50.751692 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9757 12:17:50.754726 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9758 12:17:50.758400 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9759 12:17:50.764513 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9760 12:17:50.768025 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9761 12:17:50.774721 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9762 12:17:50.777918 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9763 12:17:50.780928 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9764 12:17:50.787682 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9765 12:17:50.790843 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9766 12:17:50.797727 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9767 12:17:50.801204 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9768 12:17:50.804168 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9769 12:17:50.811172 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9770 12:17:50.814110 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9771 12:17:50.820946 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9772 12:17:50.824032 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9773 12:17:50.827657 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9774 12:17:50.834208 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9775 12:17:50.837612 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9776 12:17:50.844529 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9777 12:17:50.847899 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9778 12:17:50.854019 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9779 12:17:50.857808 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9780 12:17:50.861028 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9781 12:17:50.867601 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9782 12:17:50.870615 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9783 12:17:50.877608 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9784 12:17:50.880979 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9785 12:17:50.884179 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9786 12:17:50.891395 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9787 12:17:50.894933 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9788 12:17:50.900546 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9789 12:17:50.904563 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9790 12:17:50.907295 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9791 12:17:50.914183 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9792 12:17:50.917381 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9793 12:17:50.924472 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9794 12:17:50.927318 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9795 12:17:50.930688 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9796 12:17:50.937244 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9797 12:17:50.940706 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9798 12:17:50.947144 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9799 12:17:50.950919 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9800 12:17:50.957210 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9801 12:17:50.960828 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9802 12:17:50.963962 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9803 12:17:50.970948 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9804 12:17:50.974164 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9805 12:17:50.981038 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9806 12:17:50.984238 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9807 12:17:50.990859 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9808 12:17:50.993937 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9809 12:17:50.997601 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9810 12:17:51.004038 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9811 12:17:51.007400 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9812 12:17:51.014821 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9813 12:17:51.018060 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9814 12:17:51.024006 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9815 12:17:51.027831 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9816 12:17:51.030796 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9817 12:17:51.036938 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9818 12:17:51.040742 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9819 12:17:51.047242 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9820 12:17:51.050704 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9821 12:17:51.057360 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9822 12:17:51.060314 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9823 12:17:51.063272 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9824 12:17:51.070437 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9825 12:17:51.073555 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9826 12:17:51.079930 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9827 12:17:51.083619 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9828 12:17:51.090450 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9829 12:17:51.093465 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9830 12:17:51.096538 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9831 12:17:51.103688 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9832 12:17:51.106713 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9833 12:17:51.113619 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9834 12:17:51.116778 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9835 12:17:51.123325 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9836 12:17:51.127097 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9837 12:17:51.130377 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9838 12:17:51.136742 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9839 12:17:51.140624 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9840 12:17:51.147139 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9841 12:17:51.150215 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9842 12:17:51.157124 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9843 12:17:51.160615 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9844 12:17:51.167290 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9845 12:17:51.170886 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9846 12:17:51.173834 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9847 12:17:51.180419 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9848 12:17:51.183625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9849 12:17:51.190393 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9850 12:17:51.193918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9851 12:17:51.200367 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9852 12:17:51.203558 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9853 12:17:51.207221 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9854 12:17:51.213635 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9855 12:17:51.217313 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9856 12:17:51.223423 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9857 12:17:51.226804 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9858 12:17:51.233703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9859 12:17:51.237180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9860 12:17:51.244078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9861 12:17:51.247182 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9862 12:17:51.253836 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9863 12:17:51.257212 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9864 12:17:51.263808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9865 12:17:51.267115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9866 12:17:51.273843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9867 12:17:51.276723 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9868 12:17:51.283375 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9869 12:17:51.287249 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9870 12:17:51.293486 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9871 12:17:51.297130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9872 12:17:51.303351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9873 12:17:51.306863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9874 12:17:51.313678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9875 12:17:51.316688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9876 12:17:51.323644 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9877 12:17:51.326851 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9878 12:17:51.330240 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9879 12:17:51.333063 INFO: [APUAPC] vio 0
9880 12:17:51.340100 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9881 12:17:51.343112 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9882 12:17:51.346801 INFO: [APUAPC] D0_APC_0: 0x400510
9883 12:17:51.349744 INFO: [APUAPC] D0_APC_1: 0x0
9884 12:17:51.353641 INFO: [APUAPC] D0_APC_2: 0x1540
9885 12:17:51.356674 INFO: [APUAPC] D0_APC_3: 0x0
9886 12:17:51.359888 INFO: [APUAPC] D1_APC_0: 0xffffffff
9887 12:17:51.363152 INFO: [APUAPC] D1_APC_1: 0xffffffff
9888 12:17:51.366411 INFO: [APUAPC] D1_APC_2: 0x3fffff
9889 12:17:51.369476 INFO: [APUAPC] D1_APC_3: 0x0
9890 12:17:51.373274 INFO: [APUAPC] D2_APC_0: 0xffffffff
9891 12:17:51.376353 INFO: [APUAPC] D2_APC_1: 0xffffffff
9892 12:17:51.379713 INFO: [APUAPC] D2_APC_2: 0x3fffff
9893 12:17:51.380161 INFO: [APUAPC] D2_APC_3: 0x0
9894 12:17:51.386379 INFO: [APUAPC] D3_APC_0: 0xffffffff
9895 12:17:51.389912 INFO: [APUAPC] D3_APC_1: 0xffffffff
9896 12:17:51.392868 INFO: [APUAPC] D3_APC_2: 0x3fffff
9897 12:17:51.393090 INFO: [APUAPC] D3_APC_3: 0x0
9898 12:17:51.396088 INFO: [APUAPC] D4_APC_0: 0xffffffff
9899 12:17:51.399687 INFO: [APUAPC] D4_APC_1: 0xffffffff
9900 12:17:51.402428 INFO: [APUAPC] D4_APC_2: 0x3fffff
9901 12:17:51.406171 INFO: [APUAPC] D4_APC_3: 0x0
9902 12:17:51.409494 INFO: [APUAPC] D5_APC_0: 0xffffffff
9903 12:17:51.413135 INFO: [APUAPC] D5_APC_1: 0xffffffff
9904 12:17:51.416328 INFO: [APUAPC] D5_APC_2: 0x3fffff
9905 12:17:51.419384 INFO: [APUAPC] D5_APC_3: 0x0
9906 12:17:51.423405 INFO: [APUAPC] D6_APC_0: 0xffffffff
9907 12:17:51.425977 INFO: [APUAPC] D6_APC_1: 0xffffffff
9908 12:17:51.429676 INFO: [APUAPC] D6_APC_2: 0x3fffff
9909 12:17:51.433237 INFO: [APUAPC] D6_APC_3: 0x0
9910 12:17:51.436547 INFO: [APUAPC] D7_APC_0: 0xffffffff
9911 12:17:51.439851 INFO: [APUAPC] D7_APC_1: 0xffffffff
9912 12:17:51.443150 INFO: [APUAPC] D7_APC_2: 0x3fffff
9913 12:17:51.445913 INFO: [APUAPC] D7_APC_3: 0x0
9914 12:17:51.449404 INFO: [APUAPC] D8_APC_0: 0xffffffff
9915 12:17:51.452721 INFO: [APUAPC] D8_APC_1: 0xffffffff
9916 12:17:51.456163 INFO: [APUAPC] D8_APC_2: 0x3fffff
9917 12:17:51.459626 INFO: [APUAPC] D8_APC_3: 0x0
9918 12:17:51.462599 INFO: [APUAPC] D9_APC_0: 0xffffffff
9919 12:17:51.466260 INFO: [APUAPC] D9_APC_1: 0xffffffff
9920 12:17:51.469176 INFO: [APUAPC] D9_APC_2: 0x3fffff
9921 12:17:51.472557 INFO: [APUAPC] D9_APC_3: 0x0
9922 12:17:51.475754 INFO: [APUAPC] D10_APC_0: 0xffffffff
9923 12:17:51.479407 INFO: [APUAPC] D10_APC_1: 0xffffffff
9924 12:17:51.482425 INFO: [APUAPC] D10_APC_2: 0x3fffff
9925 12:17:51.486069 INFO: [APUAPC] D10_APC_3: 0x0
9926 12:17:51.489429 INFO: [APUAPC] D11_APC_0: 0xffffffff
9927 12:17:51.492635 INFO: [APUAPC] D11_APC_1: 0xffffffff
9928 12:17:51.495834 INFO: [APUAPC] D11_APC_2: 0x3fffff
9929 12:17:51.499353 INFO: [APUAPC] D11_APC_3: 0x0
9930 12:17:51.502550 INFO: [APUAPC] D12_APC_0: 0xffffffff
9931 12:17:51.506101 INFO: [APUAPC] D12_APC_1: 0xffffffff
9932 12:17:51.508753 INFO: [APUAPC] D12_APC_2: 0x3fffff
9933 12:17:51.512303 INFO: [APUAPC] D12_APC_3: 0x0
9934 12:17:51.515608 INFO: [APUAPC] D13_APC_0: 0xffffffff
9935 12:17:51.518894 INFO: [APUAPC] D13_APC_1: 0xffffffff
9936 12:17:51.522021 INFO: [APUAPC] D13_APC_2: 0x3fffff
9937 12:17:51.525882 INFO: [APUAPC] D13_APC_3: 0x0
9938 12:17:51.528945 INFO: [APUAPC] D14_APC_0: 0xffffffff
9939 12:17:51.532276 INFO: [APUAPC] D14_APC_1: 0xffffffff
9940 12:17:51.535401 INFO: [APUAPC] D14_APC_2: 0x3fffff
9941 12:17:51.538782 INFO: [APUAPC] D14_APC_3: 0x0
9942 12:17:51.542045 INFO: [APUAPC] D15_APC_0: 0xffffffff
9943 12:17:51.545079 INFO: [APUAPC] D15_APC_1: 0xffffffff
9944 12:17:51.548250 INFO: [APUAPC] D15_APC_2: 0x3fffff
9945 12:17:51.552161 INFO: [APUAPC] D15_APC_3: 0x0
9946 12:17:51.555481 INFO: [APUAPC] APC_CON: 0x4
9947 12:17:51.559181 INFO: [NOCDAPC] D0_APC_0: 0x0
9948 12:17:51.562414 INFO: [NOCDAPC] D0_APC_1: 0x0
9949 12:17:51.565511 INFO: [NOCDAPC] D1_APC_0: 0x0
9950 12:17:51.568611 INFO: [NOCDAPC] D1_APC_1: 0xfff
9951 12:17:51.568854 INFO: [NOCDAPC] D2_APC_0: 0x0
9952 12:17:51.571738 INFO: [NOCDAPC] D2_APC_1: 0xfff
9953 12:17:51.575731 INFO: [NOCDAPC] D3_APC_0: 0x0
9954 12:17:51.578599 INFO: [NOCDAPC] D3_APC_1: 0xfff
9955 12:17:51.582177 INFO: [NOCDAPC] D4_APC_0: 0x0
9956 12:17:51.585074 INFO: [NOCDAPC] D4_APC_1: 0xfff
9957 12:17:51.588399 INFO: [NOCDAPC] D5_APC_0: 0x0
9958 12:17:51.591605 INFO: [NOCDAPC] D5_APC_1: 0xfff
9959 12:17:51.595070 INFO: [NOCDAPC] D6_APC_0: 0x0
9960 12:17:51.598731 INFO: [NOCDAPC] D6_APC_1: 0xfff
9961 12:17:51.602268 INFO: [NOCDAPC] D7_APC_0: 0x0
9962 12:17:51.605006 INFO: [NOCDAPC] D7_APC_1: 0xfff
9963 12:17:51.605438 INFO: [NOCDAPC] D8_APC_0: 0x0
9964 12:17:51.608461 INFO: [NOCDAPC] D8_APC_1: 0xfff
9965 12:17:51.612024 INFO: [NOCDAPC] D9_APC_0: 0x0
9966 12:17:51.615364 INFO: [NOCDAPC] D9_APC_1: 0xfff
9967 12:17:51.618029 INFO: [NOCDAPC] D10_APC_0: 0x0
9968 12:17:51.621571 INFO: [NOCDAPC] D10_APC_1: 0xfff
9969 12:17:51.624853 INFO: [NOCDAPC] D11_APC_0: 0x0
9970 12:17:51.628445 INFO: [NOCDAPC] D11_APC_1: 0xfff
9971 12:17:51.631266 INFO: [NOCDAPC] D12_APC_0: 0x0
9972 12:17:51.634717 INFO: [NOCDAPC] D12_APC_1: 0xfff
9973 12:17:51.637912 INFO: [NOCDAPC] D13_APC_0: 0x0
9974 12:17:51.641804 INFO: [NOCDAPC] D13_APC_1: 0xfff
9975 12:17:51.644786 INFO: [NOCDAPC] D14_APC_0: 0x0
9976 12:17:51.647916 INFO: [NOCDAPC] D14_APC_1: 0xfff
9977 12:17:51.648382 INFO: [NOCDAPC] D15_APC_0: 0x0
9978 12:17:51.651777 INFO: [NOCDAPC] D15_APC_1: 0xfff
9979 12:17:51.654822 INFO: [NOCDAPC] APC_CON: 0x4
9980 12:17:51.657940 INFO: [APUAPC] set_apusys_apc done
9981 12:17:51.661315 INFO: [DEVAPC] devapc_init done
9982 12:17:51.664500 INFO: GICv3 without legacy support detected.
9983 12:17:51.671151 INFO: ARM GICv3 driver initialized in EL3
9984 12:17:51.674458 INFO: Maximum SPI INTID supported: 639
9985 12:17:51.677559 INFO: BL31: Initializing runtime services
9986 12:17:51.684280 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9987 12:17:51.688188 INFO: SPM: enable CPC mode
9988 12:17:51.690875 INFO: mcdi ready for mcusys-off-idle and system suspend
9989 12:17:51.697489 INFO: BL31: Preparing for EL3 exit to normal world
9990 12:17:51.700564 INFO: Entry point address = 0x80000000
9991 12:17:51.700693 INFO: SPSR = 0x8
9992 12:17:51.707721
9993 12:17:51.707832
9994 12:17:51.707919
9995 12:17:51.710479 Starting depthcharge on Spherion...
9996 12:17:51.710591
9997 12:17:51.710679 Wipe memory regions:
9998 12:17:51.710761
9999 12:17:51.711603 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10000 12:17:51.711739 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10001 12:17:51.711849 Setting prompt string to ['asurada:']
10002 12:17:51.711955 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10003 12:17:51.714454 [0x00000040000000, 0x00000054600000)
10004 12:17:51.836763
10005 12:17:51.837271 [0x00000054660000, 0x00000080000000)
10006 12:17:52.097010
10007 12:17:52.097541 [0x000000821a7280, 0x000000ffe64000)
10008 12:17:52.841514
10009 12:17:52.841643 [0x00000100000000, 0x00000240000000)
10010 12:17:54.732746
10011 12:17:54.735790 Initializing XHCI USB controller at 0x11200000.
10012 12:17:55.773200
10013 12:17:55.776596 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10014 12:17:55.777187
10015 12:17:55.777557
10016 12:17:55.777895
10017 12:17:55.778706 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10019 12:17:55.880008 asurada: tftpboot 192.168.201.1 12669521/tftp-deploy-8bw6ikvl/kernel/image.itb 12669521/tftp-deploy-8bw6ikvl/kernel/cmdline
10020 12:17:55.880707 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10021 12:17:55.881224 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10022 12:17:55.885935 tftpboot 192.168.201.1 12669521/tftp-deploy-8bw6ikvl/kernel/image.ittp-deploy-8bw6ikvl/kernel/cmdline
10023 12:17:55.886402
10024 12:17:55.886764 Waiting for link
10025 12:17:56.046492
10026 12:17:56.047052 R8152: Initializing
10027 12:17:56.047420
10028 12:17:56.049435 Version 9 (ocp_data = 6010)
10029 12:17:56.049896
10030 12:17:56.053371 R8152: Done initializing
10031 12:17:56.053830
10032 12:17:56.054188 Adding net device
10033 12:17:57.932141
10034 12:17:57.932745 done.
10035 12:17:57.933117
10036 12:17:57.933455 MAC: 00:e0:4c:78:7a:aa
10037 12:17:57.933781
10038 12:17:57.935099 Sending DHCP discover... done.
10039 12:17:57.935570
10040 12:17:57.938654 Waiting for reply... done.
10041 12:17:57.939110
10042 12:17:57.942259 Sending DHCP request... done.
10043 12:17:57.942721
10044 12:17:57.945269 Waiting for reply... done.
10045 12:17:57.945778
10046 12:17:57.946142 My ip is 192.168.201.12
10047 12:17:57.946478
10048 12:17:57.949122 The DHCP server ip is 192.168.201.1
10049 12:17:57.949578
10050 12:17:57.955721 TFTP server IP predefined by user: 192.168.201.1
10051 12:17:57.956275
10052 12:17:57.962432 Bootfile predefined by user: 12669521/tftp-deploy-8bw6ikvl/kernel/image.itb
10053 12:17:57.962967
10054 12:17:57.963331 Sending tftp read request... done.
10055 12:17:57.965554
10056 12:17:57.971849 Waiting for the transfer...
10057 12:17:57.972349
10058 12:17:58.355279 00000000 ################################################################
10059 12:17:58.355825
10060 12:17:58.736973 00080000 ################################################################
10061 12:17:58.737484
10062 12:17:59.088132 00100000 ################################################################
10063 12:17:59.088278
10064 12:17:59.382671 00180000 ################################################################
10065 12:17:59.382812
10066 12:17:59.680340 00200000 ################################################################
10067 12:17:59.680483
10068 12:17:59.976582 00280000 ################################################################
10069 12:17:59.976729
10070 12:18:00.277396 00300000 ################################################################
10071 12:18:00.277541
10072 12:18:00.575039 00380000 ################################################################
10073 12:18:00.575177
10074 12:18:00.871882 00400000 ################################################################
10075 12:18:00.872023
10076 12:18:01.162966 00480000 ################################################################
10077 12:18:01.163112
10078 12:18:01.463297 00500000 ################################################################
10079 12:18:01.463438
10080 12:18:01.756798 00580000 ################################################################
10081 12:18:01.756942
10082 12:18:02.053979 00600000 ################################################################
10083 12:18:02.054123
10084 12:18:02.341153 00680000 ################################################################
10085 12:18:02.341290
10086 12:18:02.639038 00700000 ################################################################
10087 12:18:02.639179
10088 12:18:02.923135 00780000 ################################################################
10089 12:18:02.923276
10090 12:18:03.208269 00800000 ################################################################
10091 12:18:03.208452
10092 12:18:03.481031 00880000 ################################################################
10093 12:18:03.481171
10094 12:18:03.748294 00900000 ################################################################
10095 12:18:03.748460
10096 12:18:04.034502 00980000 ################################################################
10097 12:18:04.034644
10098 12:18:04.303268 00a00000 ################################################################
10099 12:18:04.303408
10100 12:18:04.553493 00a80000 ################################################################
10101 12:18:04.553626
10102 12:18:04.803348 00b00000 ################################################################
10103 12:18:04.803482
10104 12:18:05.059827 00b80000 ################################################################
10105 12:18:05.059965
10106 12:18:05.357794 00c00000 ################################################################
10107 12:18:05.357941
10108 12:18:05.634232 00c80000 ################################################################
10109 12:18:05.634373
10110 12:18:05.916681 00d00000 ################################################################
10111 12:18:05.916822
10112 12:18:06.196887 00d80000 ################################################################
10113 12:18:06.197019
10114 12:18:06.467931 00e00000 ################################################################
10115 12:18:06.468062
10116 12:18:06.736223 00e80000 ################################################################
10117 12:18:06.736389
10118 12:18:07.001347 00f00000 ################################################################
10119 12:18:07.001538
10120 12:18:07.267254 00f80000 ################################################################
10121 12:18:07.267386
10122 12:18:07.548224 01000000 ################################################################
10123 12:18:07.548409
10124 12:18:07.829967 01080000 ################################################################
10125 12:18:07.830116
10126 12:18:08.099065 01100000 ################################################################
10127 12:18:08.099207
10128 12:18:08.387512 01180000 ################################################################
10129 12:18:08.387653
10130 12:18:08.684406 01200000 ################################################################
10131 12:18:08.684543
10132 12:18:08.984339 01280000 ################################################################
10133 12:18:08.984481
10134 12:18:09.286195 01300000 ################################################################
10135 12:18:09.286338
10136 12:18:09.669556 01380000 ################################################################
10137 12:18:09.670098
10138 12:18:10.088548 01400000 ################################################################
10139 12:18:10.089219
10140 12:18:10.493659 01480000 ################################################################
10141 12:18:10.494170
10142 12:18:10.820503 01500000 ################################################################
10143 12:18:10.820651
10144 12:18:11.116747 01580000 ################################################################
10145 12:18:11.116887
10146 12:18:11.406346 01600000 ################################################################
10147 12:18:11.406489
10148 12:18:11.702348 01680000 ################################################################
10149 12:18:11.702491
10150 12:18:11.996051 01700000 ################################################################
10151 12:18:11.996193
10152 12:18:12.294002 01780000 ################################################################
10153 12:18:12.294144
10154 12:18:12.596130 01800000 ################################################################
10155 12:18:12.596272
10156 12:18:12.897370 01880000 ################################################################
10157 12:18:12.897514
10158 12:18:13.199503 01900000 ################################################################
10159 12:18:13.199655
10160 12:18:13.501872 01980000 ################################################################
10161 12:18:13.502024
10162 12:18:13.792684 01a00000 ################################################################
10163 12:18:13.792830
10164 12:18:14.089430 01a80000 ################################################################
10165 12:18:14.089567
10166 12:18:14.409923 01b00000 ################################################################
10167 12:18:14.410060
10168 12:18:14.701621 01b80000 ################################################################
10169 12:18:14.701804
10170 12:18:15.020603 01c00000 ################################################################
10171 12:18:15.021134
10172 12:18:15.432411 01c80000 ################################################################
10173 12:18:15.432918
10174 12:18:15.778486 01d00000 ################################################################
10175 12:18:15.778641
10176 12:18:16.075012 01d80000 ################################################################
10177 12:18:16.075152
10178 12:18:16.367183 01e00000 ################################################################
10179 12:18:16.367328
10180 12:18:16.635383 01e80000 ################################################################
10181 12:18:16.635592
10182 12:18:16.889117 01f00000 ################################################################
10183 12:18:16.889254
10184 12:18:17.162763 01f80000 ################################################################
10185 12:18:17.162917
10186 12:18:17.447126 02000000 ################################################################
10187 12:18:17.447267
10188 12:18:17.739947 02080000 ################################################################
10189 12:18:17.740096
10190 12:18:18.027722 02100000 ################################################################
10191 12:18:18.027872
10192 12:18:18.283022 02180000 ################################################################
10193 12:18:18.283164
10194 12:18:18.571392 02200000 ################################################################
10195 12:18:18.571557
10196 12:18:18.868701 02280000 ################################################################
10197 12:18:18.868849
10198 12:18:19.158708 02300000 ################################################################
10199 12:18:19.158899
10200 12:18:19.419069 02380000 ################################################################
10201 12:18:19.419263
10202 12:18:19.704763 02400000 ################################################################
10203 12:18:19.704952
10204 12:18:19.995882 02480000 ################################################################
10205 12:18:19.996083
10206 12:18:20.302386 02500000 ################################################################
10207 12:18:20.302589
10208 12:18:20.586447 02580000 ################################################################
10209 12:18:20.586678
10210 12:18:20.882554 02600000 ################################################################
10211 12:18:20.882743
10212 12:18:21.153157 02680000 ################################################################
10213 12:18:21.153325
10214 12:18:21.410991 02700000 ################################################################
10215 12:18:21.411139
10216 12:18:21.682022 02780000 ################################################################
10217 12:18:21.682171
10218 12:18:21.942998 02800000 ################################################################
10219 12:18:21.943137
10220 12:18:22.202305 02880000 ################################################################
10221 12:18:22.202443
10222 12:18:22.464696 02900000 ################################################################
10223 12:18:22.464837
10224 12:18:22.719975 02980000 ################################################################
10225 12:18:22.720148
10226 12:18:22.982911 02a00000 ################################################################
10227 12:18:22.983059
10228 12:18:23.249053 02a80000 ################################################################
10229 12:18:23.249216
10230 12:18:23.503852 02b00000 ################################################################
10231 12:18:23.504000
10232 12:18:23.754380 02b80000 ################################################################
10233 12:18:23.754533
10234 12:18:24.002437 02c00000 ################################################################
10235 12:18:24.002590
10236 12:18:24.259886 02c80000 ################################################################
10237 12:18:24.260044
10238 12:18:24.512207 02d00000 ################################################################
10239 12:18:24.512399
10240 12:18:24.772137 02d80000 ################################################################
10241 12:18:24.772330
10242 12:18:25.031543 02e00000 ################################################################
10243 12:18:25.031678
10244 12:18:25.289815 02e80000 ################################################################
10245 12:18:25.289968
10246 12:18:25.567944 02f00000 ################################################################
10247 12:18:25.568099
10248 12:18:25.833824 02f80000 ################################################################
10249 12:18:25.833997
10250 12:18:26.113504 03000000 ################################################################
10251 12:18:26.113683
10252 12:18:26.393939 03080000 ################################################################
10253 12:18:26.394109
10254 12:18:26.678736 03100000 ################################################################
10255 12:18:26.678918
10256 12:18:26.941346 03180000 ################################################################
10257 12:18:26.941499
10258 12:18:27.223265 03200000 ################################################################
10259 12:18:27.223454
10260 12:18:27.509479 03280000 ################################################################
10261 12:18:27.509668
10262 12:18:27.783546 03300000 ################################################################
10263 12:18:27.783693
10264 12:18:28.064080 03380000 ################################################################
10265 12:18:28.064250
10266 12:18:28.318912 03400000 ################################################################
10267 12:18:28.319081
10268 12:18:28.579215 03480000 ################################################################
10269 12:18:28.579377
10270 12:18:28.843823 03500000 ################################################################
10271 12:18:28.843979
10272 12:18:29.099038 03580000 ################################################################
10273 12:18:29.099200
10274 12:18:29.354084 03600000 ################################################################
10275 12:18:29.354230
10276 12:18:29.616450 03680000 ################################################################
10277 12:18:29.616611
10278 12:18:29.895450 03700000 ################################################################
10279 12:18:29.895701
10280 12:18:30.226647 03780000 ################################################################
10281 12:18:30.226825
10282 12:18:30.561740 03800000 ################################################################
10283 12:18:30.561895
10284 12:18:30.809313 03880000 ################################################# done.
10285 12:18:30.809464
10286 12:18:30.812253 The bootfile was 59639974 bytes long.
10287 12:18:30.812348
10288 12:18:30.815836 Sending tftp read request... done.
10289 12:18:30.815929
10290 12:18:30.818955 Waiting for the transfer...
10291 12:18:30.819047
10292 12:18:30.819114 00000000 # done.
10293 12:18:30.819176
10294 12:18:30.829196 Command line loaded dynamically from TFTP file: 12669521/tftp-deploy-8bw6ikvl/kernel/cmdline
10295 12:18:30.829305
10296 12:18:30.842572 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10297 12:18:30.842691
10298 12:18:30.842759 Loading FIT.
10299 12:18:30.842821
10300 12:18:30.846044 Image ramdisk-1 has 47543377 bytes.
10301 12:18:30.846137
10302 12:18:30.848982 Image fdt-1 has 47278 bytes.
10303 12:18:30.849067
10304 12:18:30.852335 Image kernel-1 has 12047284 bytes.
10305 12:18:30.852421
10306 12:18:30.858768 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10307 12:18:30.858906
10308 12:18:30.879249 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10309 12:18:30.879432
10310 12:18:30.882978 Choosing best match conf-1 for compat google,spherion-rev2.
10311 12:18:30.888074
10312 12:18:30.892587 Connected to device vid:did:rid of 1ae0:0028:00
10313 12:18:30.900699
10314 12:18:30.903629 tpm_get_response: command 0x17b, return code 0x0
10315 12:18:30.903742
10316 12:18:30.907335 ec_init: CrosEC protocol v3 supported (256, 248)
10317 12:18:30.911044
10318 12:18:30.914483 tpm_cleanup: add release locality here.
10319 12:18:30.914596
10320 12:18:30.914694 Shutting down all USB controllers.
10321 12:18:30.917558
10322 12:18:30.917667 Removing current net device
10323 12:18:30.917764
10324 12:18:30.924307 Exiting depthcharge with code 4 at timestamp: 68463449
10325 12:18:30.924432
10326 12:18:30.927838 LZMA decompressing kernel-1 to 0x821a6718
10327 12:18:30.927951
10328 12:18:30.930962 LZMA decompressing kernel-1 to 0x40000000
10329 12:18:32.430378
10330 12:18:32.430532 jumping to kernel
10331 12:18:32.431055 end: 2.2.4 bootloader-commands (duration 00:00:41) [common]
10332 12:18:32.431158 start: 2.2.5 auto-login-action (timeout 00:03:45) [common]
10333 12:18:32.431236 Setting prompt string to ['Linux version [0-9]']
10334 12:18:32.431304 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10335 12:18:32.431373 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10336 12:18:32.512304
10337 12:18:32.515322 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10338 12:18:32.518829 start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10339 12:18:32.518920 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10340 12:18:32.519060 Setting prompt string to []
10341 12:18:32.519165 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10342 12:18:32.519241 Using line separator: #'\n'#
10343 12:18:32.519304 No login prompt set.
10344 12:18:32.519367 Parsing kernel messages
10345 12:18:32.519423 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10346 12:18:32.519526 [login-action] Waiting for messages, (timeout 00:03:44)
10347 12:18:32.538763 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j93261-arm64-gcc-10-defconfig-arm64-chromebook-cwjwh) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024
10348 12:18:32.542203 [ 0.000000] random: crng init done
10349 12:18:32.548916 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10350 12:18:32.552022 [ 0.000000] efi: UEFI not found.
10351 12:18:32.559001 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10352 12:18:32.565101 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10353 12:18:32.575528 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10354 12:18:32.584890 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10355 12:18:32.591988 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10356 12:18:32.598045 [ 0.000000] printk: bootconsole [mtk8250] enabled
10357 12:18:32.605128 [ 0.000000] NUMA: No NUMA configuration found
10358 12:18:32.611215 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10359 12:18:32.614603 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10360 12:18:32.618286 [ 0.000000] Zone ranges:
10361 12:18:32.624607 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10362 12:18:32.628005 [ 0.000000] DMA32 empty
10363 12:18:32.634284 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10364 12:18:32.638043 [ 0.000000] Movable zone start for each node
10365 12:18:32.641171 [ 0.000000] Early memory node ranges
10366 12:18:32.647484 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10367 12:18:32.654327 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10368 12:18:32.661181 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10369 12:18:32.667548 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10370 12:18:32.670851 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10371 12:18:32.680603 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10372 12:18:32.736699 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10373 12:18:32.743749 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10374 12:18:32.749721 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10375 12:18:32.753734 [ 0.000000] psci: probing for conduit method from DT.
10376 12:18:32.759752 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10377 12:18:32.763362 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10378 12:18:32.769964 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10379 12:18:32.773307 [ 0.000000] psci: SMC Calling Convention v1.2
10380 12:18:32.780035 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10381 12:18:32.783274 [ 0.000000] Detected VIPT I-cache on CPU0
10382 12:18:32.790150 [ 0.000000] CPU features: detected: GIC system register CPU interface
10383 12:18:32.796413 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10384 12:18:32.803267 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10385 12:18:32.809742 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10386 12:18:32.816195 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10387 12:18:32.823207 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10388 12:18:32.829739 [ 0.000000] alternatives: applying boot alternatives
10389 12:18:32.832947 [ 0.000000] Fallback order for Node 0: 0
10390 12:18:32.839971 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10391 12:18:32.843592 [ 0.000000] Policy zone: Normal
10392 12:18:32.859953 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10393 12:18:32.869874 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10394 12:18:32.880883 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10395 12:18:32.890968 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10396 12:18:32.897227 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10397 12:18:32.900726 <6>[ 0.000000] software IO TLB: area num 8.
10398 12:18:32.957759 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10399 12:18:33.106881 <6>[ 0.000000] Memory: 7920820K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 431948K reserved, 32768K cma-reserved)
10400 12:18:33.113402 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10401 12:18:33.120223 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10402 12:18:33.123486 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10403 12:18:33.130020 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10404 12:18:33.136844 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10405 12:18:33.140149 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10406 12:18:33.150380 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10407 12:18:33.156828 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10408 12:18:33.160203 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10409 12:18:33.168103 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10410 12:18:33.171480 <6>[ 0.000000] GICv3: 608 SPIs implemented
10411 12:18:33.178038 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10412 12:18:33.180990 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10413 12:18:33.184263 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10414 12:18:33.194357 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10415 12:18:33.204209 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10416 12:18:33.217911 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10417 12:18:33.223961 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10418 12:18:33.233569 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10419 12:18:33.246713 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10420 12:18:33.253269 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10421 12:18:33.259769 <6>[ 0.009233] Console: colour dummy device 80x25
10422 12:18:33.269734 <6>[ 0.013948] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10423 12:18:33.276575 <6>[ 0.024454] pid_max: default: 32768 minimum: 301
10424 12:18:33.279728 <6>[ 0.029326] LSM: Security Framework initializing
10425 12:18:33.286630 <6>[ 0.034264] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10426 12:18:33.296445 <6>[ 0.042077] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10427 12:18:33.302559 <6>[ 0.051487] cblist_init_generic: Setting adjustable number of callback queues.
10428 12:18:33.309387 <6>[ 0.058931] cblist_init_generic: Setting shift to 3 and lim to 1.
10429 12:18:33.319711 <6>[ 0.065270] cblist_init_generic: Setting adjustable number of callback queues.
10430 12:18:33.326483 <6>[ 0.072697] cblist_init_generic: Setting shift to 3 and lim to 1.
10431 12:18:33.329271 <6>[ 0.079138] rcu: Hierarchical SRCU implementation.
10432 12:18:33.336279 <6>[ 0.084155] rcu: Max phase no-delay instances is 1000.
10433 12:18:33.342710 <6>[ 0.091184] EFI services will not be available.
10434 12:18:33.346350 <6>[ 0.096137] smp: Bringing up secondary CPUs ...
10435 12:18:33.354239 <6>[ 0.101188] Detected VIPT I-cache on CPU1
10436 12:18:33.360738 <6>[ 0.101257] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10437 12:18:33.367059 <6>[ 0.101288] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10438 12:18:33.370687 <6>[ 0.101629] Detected VIPT I-cache on CPU2
10439 12:18:33.377389 <6>[ 0.101682] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10440 12:18:33.384069 <6>[ 0.101699] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10441 12:18:33.390487 <6>[ 0.101963] Detected VIPT I-cache on CPU3
10442 12:18:33.397229 <6>[ 0.102010] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10443 12:18:33.404083 <6>[ 0.102024] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10444 12:18:33.407338 <6>[ 0.102332] CPU features: detected: Spectre-v4
10445 12:18:33.414046 <6>[ 0.102339] CPU features: detected: Spectre-BHB
10446 12:18:33.417006 <6>[ 0.102345] Detected PIPT I-cache on CPU4
10447 12:18:33.423531 <6>[ 0.102401] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10448 12:18:33.430565 <6>[ 0.102418] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10449 12:18:33.436975 <6>[ 0.102710] Detected PIPT I-cache on CPU5
10450 12:18:33.443901 <6>[ 0.102775] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10451 12:18:33.450468 <6>[ 0.102793] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10452 12:18:33.453696 <6>[ 0.103074] Detected PIPT I-cache on CPU6
10453 12:18:33.460204 <6>[ 0.103139] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10454 12:18:33.467002 <6>[ 0.103157] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10455 12:18:33.473477 <6>[ 0.103451] Detected PIPT I-cache on CPU7
10456 12:18:33.480257 <6>[ 0.103515] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10457 12:18:33.486616 <6>[ 0.103532] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10458 12:18:33.489483 <6>[ 0.103578] smp: Brought up 1 node, 8 CPUs
10459 12:18:33.496333 <6>[ 0.244884] SMP: Total of 8 processors activated.
10460 12:18:33.499855 <6>[ 0.249805] CPU features: detected: 32-bit EL0 Support
10461 12:18:33.510037 <6>[ 0.255168] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10462 12:18:33.516427 <6>[ 0.264022] CPU features: detected: Common not Private translations
10463 12:18:33.523313 <6>[ 0.270498] CPU features: detected: CRC32 instructions
10464 12:18:33.526397 <6>[ 0.275849] CPU features: detected: RCpc load-acquire (LDAPR)
10465 12:18:33.533139 <6>[ 0.281846] CPU features: detected: LSE atomic instructions
10466 12:18:33.539523 <6>[ 0.287627] CPU features: detected: Privileged Access Never
10467 12:18:33.546492 <6>[ 0.293407] CPU features: detected: RAS Extension Support
10468 12:18:33.552825 <6>[ 0.299015] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10469 12:18:33.556468 <6>[ 0.306281] CPU: All CPU(s) started at EL2
10470 12:18:33.562541 <6>[ 0.310598] alternatives: applying system-wide alternatives
10471 12:18:33.571450 <6>[ 0.321317] devtmpfs: initialized
10472 12:18:33.584024 <6>[ 0.330212] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10473 12:18:33.593907 <6>[ 0.340174] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10474 12:18:33.600576 <6>[ 0.348392] pinctrl core: initialized pinctrl subsystem
10475 12:18:33.604306 <6>[ 0.355030] DMI not present or invalid.
10476 12:18:33.610789 <6>[ 0.359441] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10477 12:18:33.620212 <6>[ 0.366189] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10478 12:18:33.626903 <6>[ 0.373776] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10479 12:18:33.637191 <6>[ 0.382007] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10480 12:18:33.640345 <6>[ 0.390251] audit: initializing netlink subsys (disabled)
10481 12:18:33.650073 <5>[ 0.395944] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10482 12:18:33.657156 <6>[ 0.396640] thermal_sys: Registered thermal governor 'step_wise'
10483 12:18:33.663313 <6>[ 0.403911] thermal_sys: Registered thermal governor 'power_allocator'
10484 12:18:33.667273 <6>[ 0.410168] cpuidle: using governor menu
10485 12:18:33.673692 <6>[ 0.421127] NET: Registered PF_QIPCRTR protocol family
10486 12:18:33.680187 <6>[ 0.426602] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10487 12:18:33.683294 <6>[ 0.433707] ASID allocator initialised with 32768 entries
10488 12:18:33.690444 <6>[ 0.440263] Serial: AMBA PL011 UART driver
10489 12:18:33.699412 <4>[ 0.449019] Trying to register duplicate clock ID: 134
10490 12:18:33.753079 <6>[ 0.506200] KASLR enabled
10491 12:18:33.767657 <6>[ 0.513874] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10492 12:18:33.774098 <6>[ 0.520889] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10493 12:18:33.780995 <6>[ 0.527378] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10494 12:18:33.787964 <6>[ 0.534386] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10495 12:18:33.793969 <6>[ 0.540875] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10496 12:18:33.800951 <6>[ 0.547880] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10497 12:18:33.807367 <6>[ 0.554368] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10498 12:18:33.813944 <6>[ 0.561369] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10499 12:18:33.817632 <6>[ 0.568832] ACPI: Interpreter disabled.
10500 12:18:33.825956 <6>[ 0.575275] iommu: Default domain type: Translated
10501 12:18:33.832183 <6>[ 0.580388] iommu: DMA domain TLB invalidation policy: strict mode
10502 12:18:33.835536 <5>[ 0.587050] SCSI subsystem initialized
10503 12:18:33.842711 <6>[ 0.591294] usbcore: registered new interface driver usbfs
10504 12:18:33.849130 <6>[ 0.597023] usbcore: registered new interface driver hub
10505 12:18:33.852509 <6>[ 0.602576] usbcore: registered new device driver usb
10506 12:18:33.858898 <6>[ 0.608693] pps_core: LinuxPPS API ver. 1 registered
10507 12:18:33.869514 <6>[ 0.613888] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10508 12:18:33.872667 <6>[ 0.623231] PTP clock support registered
10509 12:18:33.875992 <6>[ 0.627472] EDAC MC: Ver: 3.0.0
10510 12:18:33.883498 <6>[ 0.632667] FPGA manager framework
10511 12:18:33.886268 <6>[ 0.636342] Advanced Linux Sound Architecture Driver Initialized.
10512 12:18:33.890043 <6>[ 0.643105] vgaarb: loaded
10513 12:18:33.897026 <6>[ 0.646248] clocksource: Switched to clocksource arch_sys_counter
10514 12:18:33.903995 <5>[ 0.652694] VFS: Disk quotas dquot_6.6.0
10515 12:18:33.910109 <6>[ 0.656883] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10516 12:18:33.913600 <6>[ 0.664072] pnp: PnP ACPI: disabled
10517 12:18:33.921363 <6>[ 0.670781] NET: Registered PF_INET protocol family
10518 12:18:33.930991 <6>[ 0.676372] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10519 12:18:33.942140 <6>[ 0.688682] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10520 12:18:33.952628 <6>[ 0.697498] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10521 12:18:33.958957 <6>[ 0.705469] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10522 12:18:33.965583 <6>[ 0.714170] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10523 12:18:33.977964 <6>[ 0.723928] TCP: Hash tables configured (established 65536 bind 65536)
10524 12:18:33.984476 <6>[ 0.730798] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10525 12:18:33.991607 <6>[ 0.737996] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10526 12:18:33.997814 <6>[ 0.745702] NET: Registered PF_UNIX/PF_LOCAL protocol family
10527 12:18:34.004274 <6>[ 0.751854] RPC: Registered named UNIX socket transport module.
10528 12:18:34.007493 <6>[ 0.758008] RPC: Registered udp transport module.
10529 12:18:34.014395 <6>[ 0.762938] RPC: Registered tcp transport module.
10530 12:18:34.020881 <6>[ 0.767870] RPC: Registered tcp NFSv4.1 backchannel transport module.
10531 12:18:34.024093 <6>[ 0.774533] PCI: CLS 0 bytes, default 64
10532 12:18:34.027279 <6>[ 0.778869] Unpacking initramfs...
10533 12:18:34.052516 <6>[ 0.798353] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10534 12:18:34.062594 <6>[ 0.807010] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10535 12:18:34.065415 <6>[ 0.815853] kvm [1]: IPA Size Limit: 40 bits
10536 12:18:34.072276 <6>[ 0.820380] kvm [1]: GICv3: no GICV resource entry
10537 12:18:34.075542 <6>[ 0.825399] kvm [1]: disabling GICv2 emulation
10538 12:18:34.082009 <6>[ 0.830083] kvm [1]: GIC system register CPU interface enabled
10539 12:18:34.085656 <6>[ 0.836244] kvm [1]: vgic interrupt IRQ18
10540 12:18:34.091766 <6>[ 0.840596] kvm [1]: VHE mode initialized successfully
10541 12:18:34.098625 <5>[ 0.847091] Initialise system trusted keyrings
10542 12:18:34.105423 <6>[ 0.851886] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10543 12:18:34.112447 <6>[ 0.861857] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10544 12:18:34.119281 <5>[ 0.868231] NFS: Registering the id_resolver key type
10545 12:18:34.122552 <5>[ 0.873531] Key type id_resolver registered
10546 12:18:34.128876 <5>[ 0.877946] Key type id_legacy registered
10547 12:18:34.135394 <6>[ 0.882224] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10548 12:18:34.142512 <6>[ 0.889146] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10549 12:18:34.148512 <6>[ 0.896843] 9p: Installing v9fs 9p2000 file system support
10550 12:18:34.185386 <5>[ 0.934713] Key type asymmetric registered
10551 12:18:34.188671 <5>[ 0.939043] Asymmetric key parser 'x509' registered
10552 12:18:34.198339 <6>[ 0.944176] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10553 12:18:34.202157 <6>[ 0.951789] io scheduler mq-deadline registered
10554 12:18:34.204992 <6>[ 0.956549] io scheduler kyber registered
10555 12:18:34.223707 <6>[ 0.973406] EINJ: ACPI disabled.
10556 12:18:34.255596 <4>[ 0.998449] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10557 12:18:34.265498 <4>[ 1.009078] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10558 12:18:34.280305 <6>[ 1.029688] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10559 12:18:34.288054 <6>[ 1.037526] printk: console [ttyS0] disabled
10560 12:18:34.315675 <6>[ 1.062175] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10561 12:18:34.322692 <6>[ 1.071646] printk: console [ttyS0] enabled
10562 12:18:34.325950 <6>[ 1.071646] printk: console [ttyS0] enabled
10563 12:18:34.332343 <6>[ 1.080540] printk: bootconsole [mtk8250] disabled
10564 12:18:34.336041 <6>[ 1.080540] printk: bootconsole [mtk8250] disabled
10565 12:18:34.342561 <6>[ 1.091551] SuperH (H)SCI(F) driver initialized
10566 12:18:34.345941 <6>[ 1.096814] msm_serial: driver initialized
10567 12:18:34.359733 <6>[ 1.105735] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10568 12:18:34.369443 <6>[ 1.114281] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10569 12:18:34.376463 <6>[ 1.122824] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10570 12:18:34.385961 <6>[ 1.131452] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10571 12:18:34.392447 <6>[ 1.140159] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10572 12:18:34.402617 <6>[ 1.148878] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10573 12:18:34.412582 <6>[ 1.157419] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10574 12:18:34.419885 <6>[ 1.166219] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10575 12:18:34.429318 <6>[ 1.174761] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10576 12:18:34.440586 <6>[ 1.190103] loop: module loaded
10577 12:18:34.447325 <6>[ 1.195951] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10578 12:18:34.469983 <4>[ 1.219117] mtk-pmic-keys: Failed to locate of_node [id: -1]
10579 12:18:34.476150 <6>[ 1.225922] megasas: 07.719.03.00-rc1
10580 12:18:34.486285 <6>[ 1.235438] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10581 12:18:34.492972 <6>[ 1.241629] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10582 12:18:34.508934 <6>[ 1.258208] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10583 12:18:34.565635 <6>[ 1.308429] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10584 12:18:36.012836 <6>[ 2.762261] Freeing initrd memory: 46428K
10585 12:18:36.023170 <6>[ 2.772555] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10586 12:18:36.033968 <6>[ 2.783298] tun: Universal TUN/TAP device driver, 1.6
10587 12:18:36.037343 <6>[ 2.789351] thunder_xcv, ver 1.0
10588 12:18:36.039979 <6>[ 2.792855] thunder_bgx, ver 1.0
10589 12:18:36.043530 <6>[ 2.796352] nicpf, ver 1.0
10590 12:18:36.054064 <6>[ 2.800360] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10591 12:18:36.057113 <6>[ 2.807837] hns3: Copyright (c) 2017 Huawei Corporation.
10592 12:18:36.060871 <6>[ 2.813423] hclge is initializing
10593 12:18:36.067104 <6>[ 2.816998] e1000: Intel(R) PRO/1000 Network Driver
10594 12:18:36.074507 <6>[ 2.822127] e1000: Copyright (c) 1999-2006 Intel Corporation.
10595 12:18:36.077534 <6>[ 2.828139] e1000e: Intel(R) PRO/1000 Network Driver
10596 12:18:36.083926 <6>[ 2.833355] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10597 12:18:36.090744 <6>[ 2.839543] igb: Intel(R) Gigabit Ethernet Network Driver
10598 12:18:36.097291 <6>[ 2.845193] igb: Copyright (c) 2007-2014 Intel Corporation.
10599 12:18:36.103743 <6>[ 2.851030] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10600 12:18:36.110648 <6>[ 2.857549] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10601 12:18:36.114038 <6>[ 2.864007] sky2: driver version 1.30
10602 12:18:36.120579 <6>[ 2.868999] VFIO - User Level meta-driver version: 0.3
10603 12:18:36.127907 <6>[ 2.877204] usbcore: registered new interface driver usb-storage
10604 12:18:36.133991 <6>[ 2.883676] usbcore: registered new device driver onboard-usb-hub
10605 12:18:36.143135 <6>[ 2.892837] mt6397-rtc mt6359-rtc: registered as rtc0
10606 12:18:36.152954 <6>[ 2.898303] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-31T12:15:53 UTC (1706703353)
10607 12:18:36.156017 <6>[ 2.907863] i2c_dev: i2c /dev entries driver
10608 12:18:36.172907 <6>[ 2.919486] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10609 12:18:36.192556 <6>[ 2.942476] cpu cpu0: EM: created perf domain
10610 12:18:36.196101 <6>[ 2.947427] cpu cpu4: EM: created perf domain
10611 12:18:36.203461 <6>[ 2.953007] sdhci: Secure Digital Host Controller Interface driver
10612 12:18:36.209600 <6>[ 2.959441] sdhci: Copyright(c) Pierre Ossman
10613 12:18:36.216533 <6>[ 2.964392] Synopsys Designware Multimedia Card Interface Driver
10614 12:18:36.220036 <6>[ 2.971007] mmc0: CQHCI version 5.10
10615 12:18:36.226182 <6>[ 2.971021] sdhci-pltfm: SDHCI platform and OF driver helper
10616 12:18:36.233084 <6>[ 2.981747] ledtrig-cpu: registered to indicate activity on CPUs
10617 12:18:36.239865 <6>[ 2.988709] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10618 12:18:36.246353 <6>[ 2.995767] usbcore: registered new interface driver usbhid
10619 12:18:36.249860 <6>[ 3.001589] usbhid: USB HID core driver
10620 12:18:36.259466 <6>[ 3.005780] spi_master spi0: will run message pump with realtime priority
10621 12:18:36.298687 <6>[ 3.041639] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10622 12:18:36.317050 <6>[ 3.056698] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10623 12:18:36.320250 <6>[ 3.070357] mmc0: Command Queue Engine enabled
10624 12:18:36.326958 <6>[ 3.075116] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10625 12:18:36.333693 <6>[ 3.082033] cros-ec-spi spi0.0: Chrome EC device registered
10626 12:18:36.336936 <6>[ 3.082344] mmcblk0: mmc0:0001 DA4128 116 GiB
10627 12:18:36.347777 <6>[ 3.097300] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10628 12:18:36.354623 <6>[ 3.104683] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10629 12:18:36.361251 <6>[ 3.110656] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10630 12:18:36.368439 <6>[ 3.116546] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10631 12:18:36.378294 <6>[ 3.122816] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10632 12:18:36.384842 <6>[ 3.133658] NET: Registered PF_PACKET protocol family
10633 12:18:36.387931 <6>[ 3.139061] 9pnet: Installing 9P2000 support
10634 12:18:36.395068 <5>[ 3.143624] Key type dns_resolver registered
10635 12:18:36.398178 <6>[ 3.148635] registered taskstats version 1
10636 12:18:36.404555 <5>[ 3.153028] Loading compiled-in X.509 certificates
10637 12:18:36.435334 <4>[ 3.178740] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10638 12:18:36.445480 <4>[ 3.189659] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10639 12:18:36.452058 <3>[ 3.200214] debugfs: File 'uA_load' in directory '/' already present!
10640 12:18:36.459131 <3>[ 3.206920] debugfs: File 'min_uV' in directory '/' already present!
10641 12:18:36.465309 <3>[ 3.213540] debugfs: File 'max_uV' in directory '/' already present!
10642 12:18:36.472017 <3>[ 3.220149] debugfs: File 'constraint_flags' in directory '/' already present!
10643 12:18:36.483169 <3>[ 3.229951] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10644 12:18:36.499785 <6>[ 3.249735] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10645 12:18:36.506375 <6>[ 3.256612] xhci-mtk 11200000.usb: xHCI Host Controller
10646 12:18:36.516801 <6>[ 3.262134] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10647 12:18:36.523144 <6>[ 3.270018] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10648 12:18:36.529768 <6>[ 3.279471] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10649 12:18:36.536388 <6>[ 3.285585] xhci-mtk 11200000.usb: xHCI Host Controller
10650 12:18:36.543006 <6>[ 3.291084] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10651 12:18:36.552499 <6>[ 3.298748] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10652 12:18:36.556250 <6>[ 3.306717] hub 1-0:1.0: USB hub found
10653 12:18:36.559274 <6>[ 3.310753] hub 1-0:1.0: 1 port detected
10654 12:18:36.569249 <6>[ 3.315076] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10655 12:18:36.572440 <6>[ 3.323939] hub 2-0:1.0: USB hub found
10656 12:18:36.575999 <6>[ 3.327965] hub 2-0:1.0: 1 port detected
10657 12:18:36.586066 <6>[ 3.335541] mtk-msdc 11f70000.mmc: Got CD GPIO
10658 12:18:36.600088 <6>[ 3.346701] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10659 12:18:36.606702 <6>[ 3.354842] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10660 12:18:36.616633 <4>[ 3.362773] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10661 12:18:36.627040 <6>[ 3.372312] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10662 12:18:36.633940 <6>[ 3.380391] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10663 12:18:36.640111 <6>[ 3.388415] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10664 12:18:36.649770 <6>[ 3.396327] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10665 12:18:36.656709 <6>[ 3.404160] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10666 12:18:36.666190 <6>[ 3.411978] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10667 12:18:36.676306 <6>[ 3.422445] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10668 12:18:36.682893 <6>[ 3.430799] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10669 12:18:36.693072 <6>[ 3.439166] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10670 12:18:36.699582 <6>[ 3.447507] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10671 12:18:36.709781 <6>[ 3.455857] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10672 12:18:36.716024 <6>[ 3.464198] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10673 12:18:36.726028 <6>[ 3.472548] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10674 12:18:36.732860 <6>[ 3.480887] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10675 12:18:36.743304 <6>[ 3.489234] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10676 12:18:36.749582 <6>[ 3.497574] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10677 12:18:36.759677 <6>[ 3.505913] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10678 12:18:36.766478 <6>[ 3.514251] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10679 12:18:36.776407 <6>[ 3.522592] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10680 12:18:36.786063 <6>[ 3.530930] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10681 12:18:36.792448 <6>[ 3.539269] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10682 12:18:36.799372 <6>[ 3.548045] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10683 12:18:36.805662 <6>[ 3.555232] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10684 12:18:36.812690 <6>[ 3.561996] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10685 12:18:36.819234 <6>[ 3.568747] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10686 12:18:36.826117 <6>[ 3.575688] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10687 12:18:36.835845 <6>[ 3.582547] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10688 12:18:36.845863 <6>[ 3.591680] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10689 12:18:36.855822 <6>[ 3.600820] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10690 12:18:36.866171 <6>[ 3.610120] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10691 12:18:36.876088 <6>[ 3.619587] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10692 12:18:36.882155 <6>[ 3.629056] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10693 12:18:36.892216 <6>[ 3.638175] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10694 12:18:36.902006 <6>[ 3.647640] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10695 12:18:36.912198 <6>[ 3.656758] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10696 12:18:36.921908 <6>[ 3.666051] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10697 12:18:36.931959 <6>[ 3.676211] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10698 12:18:36.941741 <6>[ 3.687709] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10699 12:18:36.968688 <6>[ 3.714779] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10700 12:18:36.996325 <6>[ 3.746217] hub 2-1:1.0: USB hub found
10701 12:18:36.999687 <6>[ 3.750699] hub 2-1:1.0: 3 ports detected
10702 12:18:37.008237 <6>[ 3.758073] hub 2-1:1.0: USB hub found
10703 12:18:37.011424 <6>[ 3.762540] hub 2-1:1.0: 3 ports detected
10704 12:18:37.120188 <6>[ 3.866540] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10705 12:18:37.274997 <6>[ 4.024626] hub 1-1:1.0: USB hub found
10706 12:18:37.278208 <6>[ 4.029129] hub 1-1:1.0: 4 ports detected
10707 12:18:37.288092 <6>[ 4.038139] hub 1-1:1.0: USB hub found
10708 12:18:37.291234 <6>[ 4.042651] hub 1-1:1.0: 4 ports detected
10709 12:18:37.359927 <6>[ 4.106722] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10710 12:18:37.611547 <6>[ 4.358548] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10711 12:18:37.744589 <6>[ 4.494333] hub 1-1.4:1.0: USB hub found
10712 12:18:37.747612 <6>[ 4.498981] hub 1-1.4:1.0: 2 ports detected
10713 12:18:37.756788 <6>[ 4.506944] hub 1-1.4:1.0: USB hub found
10714 12:18:37.760229 <6>[ 4.511533] hub 1-1.4:1.0: 2 ports detected
10715 12:18:38.056134 <6>[ 4.802564] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10716 12:18:38.247762 <6>[ 4.994563] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10717 12:18:49.228866 <6>[ 15.983579] ALSA device list:
10718 12:18:49.235779 <6>[ 15.986871] No soundcards found.
10719 12:18:49.243484 <6>[ 15.994852] Freeing unused kernel memory: 8448K
10720 12:18:49.246800 <6>[ 15.999849] Run /init as init process
10721 12:18:49.296720 <6>[ 16.047761] NET: Registered PF_INET6 protocol family
10722 12:18:49.303361 <6>[ 16.054014] Segment Routing with IPv6
10723 12:18:49.306625 <6>[ 16.057959] In-situ OAM (IOAM) with IPv6
10724 12:18:49.341478 <30>[ 16.073299] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10725 12:18:49.345221 <30>[ 16.097449] systemd[1]: Detected architecture arm64.
10726 12:18:49.348428
10727 12:18:49.352017 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10728 12:18:49.352134
10729 12:18:49.367017 <30>[ 16.118526] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10730 12:18:49.540538 <30>[ 16.288719] systemd[1]: Queued start job for default target Graphical Interface.
10731 12:18:49.584158 <30>[ 16.335357] systemd[1]: Created slice system-getty.slice.
10732 12:18:49.590592 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10733 12:18:49.607765 <30>[ 16.359075] systemd[1]: Created slice system-modprobe.slice.
10734 12:18:49.614380 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10735 12:18:49.632169 <30>[ 16.383791] systemd[1]: Created slice system-serial\x2dgetty.slice.
10736 12:18:49.642459 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10737 12:18:49.655531 <30>[ 16.406938] systemd[1]: Created slice User and Session Slice.
10738 12:18:49.662386 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10739 12:18:49.683187 <30>[ 16.431288] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10740 12:18:49.693239 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10741 12:18:49.710972 <30>[ 16.458700] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10742 12:18:49.717114 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10743 12:18:49.737801 <30>[ 16.482602] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10744 12:18:49.744433 <30>[ 16.494767] systemd[1]: Reached target Local Encrypted Volumes.
10745 12:18:49.751097 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10746 12:18:49.767796 <30>[ 16.519075] systemd[1]: Reached target Paths.
10747 12:18:49.770932 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10748 12:18:49.787037 <30>[ 16.538553] systemd[1]: Reached target Remote File Systems.
10749 12:18:49.793651 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10750 12:18:49.811382 <30>[ 16.562903] systemd[1]: Reached target Slices.
10751 12:18:49.818241 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10752 12:18:49.831024 <30>[ 16.582576] systemd[1]: Reached target Swap.
10753 12:18:49.834721 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10754 12:18:49.854769 <30>[ 16.603011] systemd[1]: Listening on initctl Compatibility Named Pipe.
10755 12:18:49.861488 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10756 12:18:49.868159 <30>[ 16.618229] systemd[1]: Listening on Journal Audit Socket.
10757 12:18:49.875058 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10758 12:18:49.887733 <30>[ 16.639018] systemd[1]: Listening on Journal Socket (/dev/log).
10759 12:18:49.894359 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10760 12:18:49.912643 <30>[ 16.663809] systemd[1]: Listening on Journal Socket.
10761 12:18:49.918767 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10762 12:18:49.935061 <30>[ 16.683238] systemd[1]: Listening on Network Service Netlink Socket.
10763 12:18:49.941405 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10764 12:18:49.955637 <30>[ 16.707079] systemd[1]: Listening on udev Control Socket.
10765 12:18:49.962204 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10766 12:18:49.980092 <30>[ 16.731602] systemd[1]: Listening on udev Kernel Socket.
10767 12:18:49.986583 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10768 12:18:50.027427 <30>[ 16.778855] systemd[1]: Mounting Huge Pages File System...
10769 12:18:50.034253 Mounting [0;1;39mHuge Pages File System[0m...
10770 12:18:50.053077 <30>[ 16.804591] systemd[1]: Mounting POSIX Message Queue File System...
10771 12:18:50.060089 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10772 12:18:50.081265 <30>[ 16.832463] systemd[1]: Mounting Kernel Debug File System...
10773 12:18:50.087567 Mounting [0;1;39mKernel Debug File System[0m...
10774 12:18:50.106836 <30>[ 16.854740] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10775 12:18:50.117770 <30>[ 16.866022] systemd[1]: Starting Create list of static device nodes for the current kernel...
10776 12:18:50.124665 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10777 12:18:50.141321 <30>[ 16.892937] systemd[1]: Starting Load Kernel Module configfs...
10778 12:18:50.148196 Starting [0;1;39mLoad Kernel Module configfs[0m...
10779 12:18:50.166897 <30>[ 16.918379] systemd[1]: Starting Load Kernel Module drm...
10780 12:18:50.173370 Starting [0;1;39mLoad Kernel Module drm[0m...
10781 12:18:50.191202 <30>[ 16.938820] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10782 12:18:50.205135 <30>[ 16.956241] systemd[1]: Starting Journal Service...
10783 12:18:50.208271 Starting [0;1;39mJournal Service[0m...
10784 12:18:50.227173 <30>[ 16.978563] systemd[1]: Starting Load Kernel Modules...
10785 12:18:50.233989 Starting [0;1;39mLoad Kernel Modules[0m...
10786 12:18:50.255255 <30>[ 17.003358] systemd[1]: Starting Remount Root and Kernel File Systems...
10787 12:18:50.261772 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10788 12:18:50.280304 <30>[ 17.031880] systemd[1]: Starting Coldplug All udev Devices...
10789 12:18:50.287385 Starting [0;1;39mColdplug All udev Devices[0m...
10790 12:18:50.309893 <30>[ 17.061264] systemd[1]: Started Journal Service.
10791 12:18:50.316878 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10792 12:18:50.333152 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10793 12:18:50.351940 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10794 12:18:50.367866 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10795 12:18:50.387776 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10796 12:18:50.405490 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10797 12:18:50.422016 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10798 12:18:50.441123 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10799 12:18:50.465234 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10800 12:18:50.483782 See 'systemctl status systemd-remount-fs.service' for details.
10801 12:18:50.529638 Mounting [0;1;39mKernel Configuration File System[0m...
10802 12:18:50.551918 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10803 12:18:50.564809 <46>[ 17.312961] systemd-journald[176]: Received client request to flush runtime journal.
10804 12:18:50.577991 Starting [0;1;39mLoad/Save Random Seed[0m...
10805 12:18:50.597616 Starting [0;1;39mApply Kernel Variables[0m...
10806 12:18:50.616708 Starting [0;1;39mCreate System Users[0m...
10807 12:18:50.634923 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10808 12:18:50.657075 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10809 12:18:50.680081 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10810 12:18:50.693119 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10811 12:18:50.708256 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10812 12:18:50.725337 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10813 12:18:50.768149 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10814 12:18:50.790439 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10815 12:18:50.803673 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10816 12:18:50.819125 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10817 12:18:50.838664 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10818 12:18:50.866277 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10819 12:18:50.886024 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10820 12:18:50.904013 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10821 12:18:50.930937 Starting [0;1;39mNetwork Service[0m...
10822 12:18:50.953765 Starting [0;1;39mNetwork Time Synchronization[0m...
10823 12:18:50.974858 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10824 12:18:50.992846 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10825 12:18:51.017984 Starting [0;1;39mNetwork Name Resolution[0m...
10826 12:18:51.032548 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10827 12:18:51.045748 <6>[ 17.793812] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10828 12:18:51.052516 <6>[ 17.802377] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10829 12:18:51.058933 <6>[ 17.805010] remoteproc remoteproc0: scp is available
10830 12:18:51.069127 <6>[ 17.811109] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10831 12:18:51.072158 <6>[ 17.815667] remoteproc remoteproc0: powering up scp
10832 12:18:51.082370 <6>[ 17.826074] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10833 12:18:51.088665 <6>[ 17.829549] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10834 12:18:51.095223 <6>[ 17.846569] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10835 12:18:51.102077 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10836 12:18:51.120314 <6>[ 17.871858] Bluetooth: Core ver 2.22
10837 12:18:51.127272 <6>[ 17.872012] usbcore: registered new device driver r8152-cfgselector
10838 12:18:51.130327 <6>[ 17.876190] NET: Registered PF_BLUETOOTH protocol family
10839 12:18:51.136835 <6>[ 17.883129] mc: Linux media interface: v0.10
10840 12:18:51.143942 <6>[ 17.888378] Bluetooth: HCI device and connection manager initialized
10841 12:18:51.146768 <6>[ 17.899174] Bluetooth: HCI socket layer initialized
10842 12:18:51.153873 <6>[ 17.899189] Bluetooth: L2CAP socket layer initialized
10843 12:18:51.159916 <6>[ 17.900050] videodev: Linux video capture interface: v2.00
10844 12:18:51.167141 [[0;32m OK [<6>[ 17.917957] Bluetooth: SCO socket layer initialized
10845 12:18:51.173401 <4>[ 17.918232] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10846 12:18:51.183408 0m] Found device<4>[ 17.931913] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10847 12:18:51.193797 [0;1;39m/dev/t<3>[ 17.936785] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10848 12:18:51.199984 <6>[ 17.937270] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10849 12:18:51.200111 tyS0[0m.
10850 12:18:51.209970 <3>[ 17.957248] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10851 12:18:51.219586 <3>[ 17.966522] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10852 12:18:51.226622 <6>[ 17.971126] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10853 12:18:51.232922 <6>[ 17.972779] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10854 12:18:51.239442 <6>[ 17.972829] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10855 12:18:51.246139 <6>[ 17.972840] remoteproc remoteproc0: remote processor scp is now up
10856 12:18:51.256200 <3>[ 17.980291] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10857 12:18:51.259914 <6>[ 17.981889] pci_bus 0000:00: root bus resource [bus 00-ff]
10858 12:18:51.269877 <6>[ 17.983739] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10859 12:18:51.276163 <3>[ 17.988775] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10860 12:18:51.286013 <6>[ 17.997197] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10861 12:18:51.293050 <6>[ 17.997206] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10862 12:18:51.299429 <6>[ 17.997281] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10863 12:18:51.310006 <3>[ 18.003858] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10864 12:18:51.316513 <6>[ 18.011823] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10865 12:18:51.319702 <6>[ 18.011923] pci 0000:00:00.0: supports D1 D2
10866 12:18:51.330895 <3>[ 18.017644] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10867 12:18:51.337562 <6>[ 18.025919] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10868 12:18:51.344297 <6>[ 18.027392] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10869 12:18:51.350920 <6>[ 18.027407] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10870 12:18:51.360813 <6>[ 18.028312] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10871 12:18:51.367131 <6>[ 18.029956] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10872 12:18:51.377386 <3>[ 18.034111] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10873 12:18:51.380684 <6>[ 18.041287] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10874 12:18:51.390921 <3>[ 18.051263] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10875 12:18:51.398347 <4>[ 18.053750] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10876 12:18:51.404454 <4>[ 18.053750] Fallback method does not support PEC.
10877 12:18:51.411704 <6>[ 18.057345] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10878 12:18:51.418694 <6>[ 18.058560] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10879 12:18:51.429333 <6>[ 18.062862] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10880 12:18:51.438915 <6>[ 18.063194] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10881 12:18:51.449073 <3>[ 18.065515] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10882 12:18:51.455430 <6>[ 18.072920] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10883 12:18:51.458690 <6>[ 18.074702] r8152 2-1.3:1.0 eth0: v1.12.13
10884 12:18:51.465411 <6>[ 18.074969] usbcore: registered new interface driver r8152
10885 12:18:51.472039 <3>[ 18.077429] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10886 12:18:51.481831 <3>[ 18.077437] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10887 12:18:51.488541 <6>[ 18.085540] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10888 12:18:51.491973 <6>[ 18.085666] pci 0000:01:00.0: supports D1 D2
10889 12:18:51.498383 <6>[ 18.086073] usbcore: registered new interface driver cdc_ether
10890 12:18:51.505060 <6>[ 18.087236] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10891 12:18:51.518567 <6>[ 18.088254] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10892 12:18:51.524881 <6>[ 18.088367] usbcore: registered new interface driver uvcvideo
10893 12:18:51.535378 <3>[ 18.089289] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 12:18:51.541432 <3>[ 18.090130] power_supply sbs-5-000b: driver failed to report `status' property: -6
10895 12:18:51.548386 <3>[ 18.092948] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10896 12:18:51.558037 <6>[ 18.100755] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10897 12:18:51.561144 <6>[ 18.101269] usbcore: registered new interface driver r8153_ecm
10898 12:18:51.571459 <3>[ 18.107502] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10899 12:18:51.578173 <6>[ 18.110404] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10900 12:18:51.585070 <6>[ 18.110461] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10901 12:18:51.594915 <6>[ 18.110464] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10902 12:18:51.601564 <6>[ 18.110473] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10903 12:18:51.610971 <6>[ 18.110485] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10904 12:18:51.618080 <6>[ 18.110498] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10905 12:18:51.624558 <6>[ 18.110511] pci 0000:00:00.0: PCI bridge to [bus 01]
10906 12:18:51.631231 <6>[ 18.110516] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10907 12:18:51.637786 <6>[ 18.110655] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10908 12:18:51.643963 <6>[ 18.111130] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10909 12:18:51.650332 <6>[ 18.111416] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10910 12:18:51.657352 <5>[ 18.134362] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10911 12:18:51.664076 <6>[ 18.137834] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10912 12:18:51.670215 <3>[ 18.138328] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10913 12:18:51.677132 <6>[ 18.139085] usbcore: registered new interface driver btusb
10914 12:18:51.683496 <6>[ 18.139174] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10915 12:18:51.693574 <4>[ 18.139955] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10916 12:18:51.700237 <3>[ 18.139963] Bluetooth: hci0: Failed to load firmware file (-2)
10917 12:18:51.707013 <3>[ 18.139966] Bluetooth: hci0: Failed to set up firmware (-2)
10918 12:18:51.716707 <4>[ 18.139971] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10919 12:18:51.723272 <5>[ 18.156754] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10920 12:18:51.730029 <3>[ 18.160047] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10921 12:18:51.740196 <3>[ 18.160052] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10922 12:18:51.746380 <3>[ 18.160103] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10923 12:18:51.756258 <3>[ 18.164317] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 12:18:51.763044 <3>[ 18.164986] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
10925 12:18:51.773237 <5>[ 18.167777] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10926 12:18:51.783175 <3>[ 18.179367] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 12:18:51.785946 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10928 12:18:51.804829 <4>[ 18.552794] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10929 12:18:51.814372 <3>[ 18.553547] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 12:18:51.818088 <6>[ 18.561746] cfg80211: failed to load regulatory.db
10931 12:18:51.873564 <6>[ 18.621983] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10932 12:18:51.880484 <6>[ 18.629500] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10933 12:18:51.892557 <3>[ 18.640965] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 12:18:51.904283 <6>[ 18.656207] mt7921e 0000:01:00.0: ASIC revision: 79610010
10935 12:18:51.922652 <3>[ 18.671098] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 12:18:51.940276 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10937 12:18:51.954018 <3>[ 18.702320] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 12:18:51.960571 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10939 12:18:51.975480 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10940 12:18:51.987461 <3>[ 18.735667] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 12:18:51.993842 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10942 12:18:52.006911 <6>[ 18.754780] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10943 12:18:52.007037 <6>[ 18.754780]
10944 12:18:52.015476 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10945 12:18:52.031974 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10946 12:18:52.050953 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10947 12:18:52.086874 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10948 12:18:52.109242 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10949 12:18:52.124342 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10950 12:18:52.140204 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10951 12:18:52.158421 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10952 12:18:52.170909 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10953 12:18:52.190858 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10954 12:18:52.203554 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10955 12:18:52.219441 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10956 12:18:52.276316 <6>[ 19.024603] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10957 12:18:52.282820 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10958 12:18:52.318464 Starting [0;1;39mUser Login Management[0m...
10959 12:18:52.339763 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10960 12:18:52.361722 Starting [0;1;39mPermit User Sessions[0m...
10961 12:18:52.370750 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10962 12:18:52.389777 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10963 12:18:52.410601 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10964 12:18:52.432150 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10965 12:18:52.447327 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10966 12:18:52.463803 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10967 12:18:52.471447 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10968 12:18:52.487789 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10969 12:18:52.533882 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10970 12:18:52.571351 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10971 12:18:52.617220
10972 12:18:52.617371
10973 12:18:52.620432 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10974 12:18:52.620517
10975 12:18:52.624059 debian-bullseye-arm64 login: root (automatic login)
10976 12:18:52.624137
10977 12:18:52.624201
10978 12:18:52.650299 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024 aarch64
10979 12:18:52.650432
10980 12:18:52.657009 The programs included with the Debian GNU/Linux system are free software;
10981 12:18:52.663676 the exact distribution terms for each program are described in the
10982 12:18:52.666940 individual files in /usr/share/doc/*/copyright.
10983 12:18:52.667024
10984 12:18:52.673450 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10985 12:18:52.676898 permitted by applicable law.
10986 12:18:52.677446 Matched prompt #10: / #
10988 12:18:52.677723 Setting prompt string to ['/ #']
10989 12:18:52.677816 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10991 12:18:52.678010 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10992 12:18:52.678134 start: 2.2.6 expect-shell-connection (timeout 00:03:24) [common]
10993 12:18:52.678203 Setting prompt string to ['/ #']
10994 12:18:52.678263 Forcing a shell prompt, looking for ['/ #']
10996 12:18:52.728459 / #
10997 12:18:52.728627 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10998 12:18:52.728738 Waiting using forced prompt support (timeout 00:02:30)
10999 12:18:52.733862
11000 12:18:52.734194 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11001 12:18:52.734311 start: 2.2.7 export-device-env (timeout 00:03:24) [common]
11002 12:18:52.734419 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11003 12:18:52.734504 end: 2.2 depthcharge-retry (duration 00:01:36) [common]
11004 12:18:52.734586 end: 2 depthcharge-action (duration 00:01:36) [common]
11005 12:18:52.734673 start: 3 lava-test-retry (timeout 00:05:00) [common]
11006 12:18:52.734768 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11007 12:18:52.734843 Using namespace: common
11009 12:18:52.835215 / # #
11010 12:18:52.835387 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11011 12:18:52.840526 #
11012 12:18:52.840807 Using /lava-12669521
11014 12:18:52.941164 / # export SHELL=/bin/sh
11015 12:18:52.941391 export SHELL=/bin/sh<6>[ 19.680491] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
11016 12:18:52.941474 <6>[ 19.691285] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
11017 12:18:52.946464
11019 12:18:53.046985 / # . /lava-12669521/environment
11020 12:18:53.051806 . /lava-12669521/environment
11022 12:18:53.152368 / # /lava-12669521/bin/lava-test-runner /lava-12669521/0
11023 12:18:53.152543 Test shell timeout: 10s (minimum of the action and connection timeout)
11024 12:18:53.152882 /lava-12669521/bin/lava-test-runner /lava-12669521/0<6>[ 19.883155] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11025 12:18:53.157901
11026 12:18:53.200476 + export TESTRUN_ID=0_cros-ec
11027 12:18:53.200628 +<8>[ 19.935795] <LAVA_SIGNAL_STARTRUN 0_cros-ec 12669521_1.5.2.3.1>
11028 12:18:53.200698 cd /lava-12669521/0/tests/0_cros-ec
11029 12:18:53.200758 + cat uuid
11030 12:18:53.200817 + UUID=12669521_1.5.2.3.1
11031 12:18:53.200875 + set +x
11032 12:18:53.200932 + python3 -m cros.runners.lava_runner -v
11033 12:18:53.201172 Received signal: <STARTRUN> 0_cros-ec 12669521_1.5.2.3.1
11034 12:18:53.201239 Starting test lava.0_cros-ec (12669521_1.5.2.3.1)
11035 12:18:53.201319 Skipping test definition patterns.
11036 12:18:53.576358 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
11037 12:18:53.586468 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11038 12:18:53.586580
11039 12:18:53.593037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11040 12:18:53.593299 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11042 12:18:53.599716 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
11043 12:18:53.606314 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11044 12:18:53.606398
11045 12:18:53.613286 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_ac<8
11046 12:18:53.613386 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'test_cros_ec_ac<8', 'result': 'unknown'}
11047 12:18:53.619537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_ac<8>[ 20.368657] <LAVA_SIGNAL_ENDRUN 0_cros-ec 12669521_1.5.2.3.1>
11048 12:18:53.619791 Received signal: <ENDRUN> 0_cros-ec 12669521_1.5.2.3.1
11049 12:18:53.619871 Ending use of test pattern.
11050 12:18:53.619934 Ending test lava.0_cros-ec (12669521_1.5.2.3.1), duration 0.42
11052 12:18:53.623438 cel_iio_data_is_valid RESULT=skip>
11053 12:18:53.627017 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
11054 12:18:53.632999 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11055 12:18:53.633081
11056 12:18:53.639936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11057 12:18:53.640190 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11059 12:18:53.646375 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11060 12:18:53.649571 Checks the standard ABI for the main Embedded Controller. ... ok
11061 12:18:53.652808
11062 12:18:53.656141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11063 12:18:53.656393 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11065 12:18:53.662868 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
11066 12:18:53.669907 Checks the main Embedded controller character device. ... ok
11067 12:18:53.669991
11068 12:18:53.672927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11069 12:18:53.673181 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11071 12:18:53.679373 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11072 12:18:53.686153 Checks basic comunication with the main Embedded controller. ... ok
11073 12:18:53.686237
11074 12:18:53.689539 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11076 12:18:53.692605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11077 12:18:53.696165 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11078 12:18:53.702794 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11079 12:18:53.702879
11080 12:18:53.709380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11081 12:18:53.709638 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11083 12:18:53.715976 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11084 12:18:53.722590 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11085 12:18:53.722676
11086 12:18:53.729009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11087 12:18:53.729267 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11089 12:18:53.735987 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11090 12:18:53.742638 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11091 12:18:53.742722
11092 12:18:53.746026 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11094 12:18:53.749139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11095 12:18:53.752256 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11096 12:18:53.759232 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11097 12:18:53.759315
11098 12:18:53.765941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11099 12:18:53.766195 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11101 12:18:53.772116 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11102 12:18:53.778954 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11103 12:18:53.779037
11104 12:18:53.785101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11105 12:18:53.785396 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11107 12:18:53.792151 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11108 12:18:53.798653 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11109 12:18:53.798737
11110 12:18:53.805442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11111 12:18:53.805699 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11113 12:18:53.808931 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11114 12:18:53.818784 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11115 12:18:53.818867
11116 12:18:53.821955 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11118 12:18:53.825164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11119 12:18:53.828274 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11120 12:18:53.838420 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11121 12:18:53.838504
11122 12:18:53.845011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11123 12:18:53.845266 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11125 12:18:53.851631 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11126 12:18:53.854775 Check the cros battery ABI. ... skipped 'No BAT found'
11127 12:18:53.854857
11128 12:18:53.861646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11129 12:18:53.861900 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11131 12:18:53.868185 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11132 12:18:53.874757 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11133 12:18:53.874840
11134 12:18:53.881803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11135 12:18:53.882060 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11137 12:18:53.888038 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11138 12:18:53.894877 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11139 12:18:53.894961
11140 12:18:53.901160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11141 12:18:53.901416 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11143 12:18:53.907919 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11144 12:18:53.914204 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11145 12:18:53.914286
11146 12:18:53.921103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11147 12:18:53.921185
11148 12:18:53.921421 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11150 12:18:53.927993 ----------------------------------------------------------------------
11151 12:18:53.928077 Ran 18 tests in 0.006s
11152 12:18:53.930922
11153 12:18:53.931003 OK (skipped=15)
11154 12:18:53.931068 + set +x
11155 12:18:53.934587 <LAVA_TEST_RUNNER EXIT>
11156 12:18:53.934842 ok: lava_test_shell seems to have completed
11157 12:18:53.935010 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11158 12:18:53.935109 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11159 12:18:53.935196 end: 3 lava-test-retry (duration 00:00:01) [common]
11160 12:18:53.935284 start: 4 finalize (timeout 00:08:02) [common]
11161 12:18:53.935374 start: 4.1 power-off (timeout 00:00:30) [common]
11162 12:18:53.935523 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11163 12:18:54.012069 >> Command sent successfully.
11164 12:18:54.014601 Returned 0 in 0 seconds
11165 12:18:54.115023 end: 4.1 power-off (duration 00:00:00) [common]
11167 12:18:54.115370 start: 4.2 read-feedback (timeout 00:08:01) [common]
11168 12:18:54.115644 Listened to connection for namespace 'common' for up to 1s
11169 12:18:55.116399 Finalising connection for namespace 'common'
11170 12:18:55.116572 Disconnecting from shell: Finalise
11171 12:18:55.116655 / #
11172 12:18:55.216977 end: 4.2 read-feedback (duration 00:00:01) [common]
11173 12:18:55.217154 end: 4 finalize (duration 00:00:01) [common]
11174 12:18:55.217271 Cleaning after the job
11175 12:18:55.217371 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669521/tftp-deploy-8bw6ikvl/ramdisk
11176 12:18:55.224007 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669521/tftp-deploy-8bw6ikvl/kernel
11177 12:18:55.233077 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669521/tftp-deploy-8bw6ikvl/dtb
11178 12:18:55.233246 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669521/tftp-deploy-8bw6ikvl/modules
11179 12:18:55.240704 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12669521
11180 12:18:55.359945 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12669521
11181 12:18:55.360123 Job finished correctly