Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 16
- Kernel Errors: 33
1 12:14:27.900105 lava-dispatcher, installed at version: 2023.10
2 12:14:27.900316 start: 0 validate
3 12:14:27.900447 Start time: 2024-01-31 12:14:27.900439+00:00 (UTC)
4 12:14:27.900563 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:14:27.900694 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 12:14:28.171912 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:14:28.172666 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:14:28.442478 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:14:28.443235 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:14:28.721883 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:14:28.722685 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:14:28.996992 validate duration: 1.10
14 12:14:28.998326 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:14:28.998862 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:14:28.999379 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:14:29.000040 Not decompressing ramdisk as can be used compressed.
18 12:14:29.000528 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 12:14:29.000909 saving as /var/lib/lava/dispatcher/tmp/12669522/tftp-deploy-c4g5e4u7/ramdisk/rootfs.cpio.gz
20 12:14:29.001265 total size: 43284872 (41 MB)
21 12:14:29.011183 progress 0 % (0 MB)
22 12:14:29.050624 progress 5 % (2 MB)
23 12:14:29.066632 progress 10 % (4 MB)
24 12:14:29.078503 progress 15 % (6 MB)
25 12:14:29.090839 progress 20 % (8 MB)
26 12:14:29.102721 progress 25 % (10 MB)
27 12:14:29.114600 progress 30 % (12 MB)
28 12:14:29.126777 progress 35 % (14 MB)
29 12:14:29.138668 progress 40 % (16 MB)
30 12:14:29.150936 progress 45 % (18 MB)
31 12:14:29.163163 progress 50 % (20 MB)
32 12:14:29.175016 progress 55 % (22 MB)
33 12:14:29.187248 progress 60 % (24 MB)
34 12:14:29.198546 progress 65 % (26 MB)
35 12:14:29.209861 progress 70 % (28 MB)
36 12:14:29.221244 progress 75 % (30 MB)
37 12:14:29.232837 progress 80 % (33 MB)
38 12:14:29.244420 progress 85 % (35 MB)
39 12:14:29.255534 progress 90 % (37 MB)
40 12:14:29.266403 progress 95 % (39 MB)
41 12:14:29.277421 progress 100 % (41 MB)
42 12:14:29.277672 41 MB downloaded in 0.28 s (149.33 MB/s)
43 12:14:29.277830 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:14:29.278072 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:14:29.278159 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:14:29.278242 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:14:29.278379 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 12:14:29.278447 saving as /var/lib/lava/dispatcher/tmp/12669522/tftp-deploy-c4g5e4u7/kernel/Image
50 12:14:29.278511 total size: 51532288 (49 MB)
51 12:14:29.278573 No compression specified
52 12:14:29.279843 progress 0 % (0 MB)
53 12:14:29.293734 progress 5 % (2 MB)
54 12:14:29.307340 progress 10 % (4 MB)
55 12:14:29.320839 progress 15 % (7 MB)
56 12:14:29.334372 progress 20 % (9 MB)
57 12:14:29.347964 progress 25 % (12 MB)
58 12:14:29.361194 progress 30 % (14 MB)
59 12:14:29.374610 progress 35 % (17 MB)
60 12:14:29.388206 progress 40 % (19 MB)
61 12:14:29.401541 progress 45 % (22 MB)
62 12:14:29.414915 progress 50 % (24 MB)
63 12:14:29.428236 progress 55 % (27 MB)
64 12:14:29.441879 progress 60 % (29 MB)
65 12:14:29.455548 progress 65 % (31 MB)
66 12:14:29.468638 progress 70 % (34 MB)
67 12:14:29.482087 progress 75 % (36 MB)
68 12:14:29.495658 progress 80 % (39 MB)
69 12:14:29.509091 progress 85 % (41 MB)
70 12:14:29.522349 progress 90 % (44 MB)
71 12:14:29.535434 progress 95 % (46 MB)
72 12:14:29.548411 progress 100 % (49 MB)
73 12:14:29.548618 49 MB downloaded in 0.27 s (181.95 MB/s)
74 12:14:29.548767 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:14:29.548998 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:14:29.549085 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:14:29.549176 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:14:29.549314 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 12:14:29.549383 saving as /var/lib/lava/dispatcher/tmp/12669522/tftp-deploy-c4g5e4u7/dtb/mt8192-asurada-spherion-r0.dtb
81 12:14:29.549444 total size: 47278 (0 MB)
82 12:14:29.549504 No compression specified
83 12:14:29.550591 progress 69 % (0 MB)
84 12:14:29.550861 progress 100 % (0 MB)
85 12:14:29.551018 0 MB downloaded in 0.00 s (28.71 MB/s)
86 12:14:29.551139 end: 1.3.1 http-download (duration 00:00:00) [common]
88 12:14:29.551359 end: 1.3 download-retry (duration 00:00:00) [common]
89 12:14:29.551443 start: 1.4 download-retry (timeout 00:09:59) [common]
90 12:14:29.551526 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 12:14:29.551639 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 12:14:29.551740 saving as /var/lib/lava/dispatcher/tmp/12669522/tftp-deploy-c4g5e4u7/modules/modules.tar
93 12:14:29.551814 total size: 8639916 (8 MB)
94 12:14:29.551875 Using unxz to decompress xz
95 12:14:29.556091 progress 0 % (0 MB)
96 12:14:29.577120 progress 5 % (0 MB)
97 12:14:29.600489 progress 10 % (0 MB)
98 12:14:29.623933 progress 15 % (1 MB)
99 12:14:29.647075 progress 20 % (1 MB)
100 12:14:29.670727 progress 25 % (2 MB)
101 12:14:29.698172 progress 30 % (2 MB)
102 12:14:29.722768 progress 35 % (2 MB)
103 12:14:29.746042 progress 40 % (3 MB)
104 12:14:29.769933 progress 45 % (3 MB)
105 12:14:29.795028 progress 50 % (4 MB)
106 12:14:29.821198 progress 55 % (4 MB)
107 12:14:29.845712 progress 60 % (4 MB)
108 12:14:29.870762 progress 65 % (5 MB)
109 12:14:29.895162 progress 70 % (5 MB)
110 12:14:29.918322 progress 75 % (6 MB)
111 12:14:29.945096 progress 80 % (6 MB)
112 12:14:29.972530 progress 85 % (7 MB)
113 12:14:29.997178 progress 90 % (7 MB)
114 12:14:30.026471 progress 95 % (7 MB)
115 12:14:30.054312 progress 100 % (8 MB)
116 12:14:30.060173 8 MB downloaded in 0.51 s (16.21 MB/s)
117 12:14:30.060433 end: 1.4.1 http-download (duration 00:00:01) [common]
119 12:14:30.060704 end: 1.4 download-retry (duration 00:00:01) [common]
120 12:14:30.060800 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 12:14:30.060899 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 12:14:30.060982 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 12:14:30.061074 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 12:14:30.061300 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_
125 12:14:30.061435 makedir: /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin
126 12:14:30.061542 makedir: /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/tests
127 12:14:30.061641 makedir: /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/results
128 12:14:30.061762 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-add-keys
129 12:14:30.061913 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-add-sources
130 12:14:30.062046 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-background-process-start
131 12:14:30.062175 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-background-process-stop
132 12:14:30.062306 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-common-functions
133 12:14:30.062433 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-echo-ipv4
134 12:14:30.062561 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-install-packages
135 12:14:30.062688 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-installed-packages
136 12:14:30.062813 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-os-build
137 12:14:30.062941 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-probe-channel
138 12:14:30.063070 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-probe-ip
139 12:14:30.063196 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-target-ip
140 12:14:30.063323 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-target-mac
141 12:14:30.063449 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-target-storage
142 12:14:30.063581 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-test-case
143 12:14:30.063716 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-test-event
144 12:14:30.063844 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-test-feedback
145 12:14:30.063971 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-test-raise
146 12:14:30.064100 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-test-reference
147 12:14:30.064229 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-test-runner
148 12:14:30.064356 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-test-set
149 12:14:30.064484 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-test-shell
150 12:14:30.064616 Updating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-install-packages (oe)
151 12:14:30.064769 Updating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/bin/lava-installed-packages (oe)
152 12:14:30.064896 Creating /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/environment
153 12:14:30.064996 LAVA metadata
154 12:14:30.065071 - LAVA_JOB_ID=12669522
155 12:14:30.065135 - LAVA_DISPATCHER_IP=192.168.201.1
156 12:14:30.065238 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 12:14:30.065305 skipped lava-vland-overlay
158 12:14:30.065380 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 12:14:30.065461 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 12:14:30.065529 skipped lava-multinode-overlay
161 12:14:30.065603 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 12:14:30.065689 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 12:14:30.065765 Loading test definitions
164 12:14:30.065857 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 12:14:30.065934 Using /lava-12669522 at stage 0
166 12:14:30.066249 uuid=12669522_1.5.2.3.1 testdef=None
167 12:14:30.066337 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 12:14:30.066424 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 12:14:30.066969 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 12:14:30.067192 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 12:14:30.067877 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 12:14:30.068107 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 12:14:30.068705 runner path: /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/0/tests/0_igt-kms-mediatek test_uuid 12669522_1.5.2.3.1
176 12:14:30.068866 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 12:14:30.069075 Creating lava-test-runner.conf files
179 12:14:30.069139 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12669522/lava-overlay-78pi2nc_/lava-12669522/0 for stage 0
180 12:14:30.069229 - 0_igt-kms-mediatek
181 12:14:30.069326 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 12:14:30.069414 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 12:14:30.076304 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 12:14:30.076409 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 12:14:30.076495 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 12:14:30.076580 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 12:14:30.076673 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 12:14:31.473368 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 12:14:31.473765 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 12:14:31.473885 extracting modules file /var/lib/lava/dispatcher/tmp/12669522/tftp-deploy-c4g5e4u7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12669522/extract-overlay-ramdisk-2o1cp2_f/ramdisk
191 12:14:31.700755 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 12:14:31.700918 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 12:14:31.701009 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12669522/compress-overlay-cfrg2k3n/overlay-1.5.2.4.tar.gz to ramdisk
194 12:14:31.701080 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12669522/compress-overlay-cfrg2k3n/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12669522/extract-overlay-ramdisk-2o1cp2_f/ramdisk
195 12:14:31.707895 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 12:14:31.708006 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 12:14:31.708097 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 12:14:31.708184 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 12:14:31.708261 Building ramdisk /var/lib/lava/dispatcher/tmp/12669522/extract-overlay-ramdisk-2o1cp2_f/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12669522/extract-overlay-ramdisk-2o1cp2_f/ramdisk
200 12:14:32.742913 >> 369992 blocks
201 12:14:38.453385 rename /var/lib/lava/dispatcher/tmp/12669522/extract-overlay-ramdisk-2o1cp2_f/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12669522/tftp-deploy-c4g5e4u7/ramdisk/ramdisk.cpio.gz
202 12:14:38.453839 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 12:14:38.453964 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 12:14:38.454070 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 12:14:38.454176 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12669522/tftp-deploy-c4g5e4u7/kernel/Image'
206 12:14:50.789696 Returned 0 in 12 seconds
207 12:14:50.890762 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12669522/tftp-deploy-c4g5e4u7/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12669522/tftp-deploy-c4g5e4u7/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12669522/tftp-deploy-c4g5e4u7/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12669522/tftp-deploy-c4g5e4u7/kernel/image.itb
208 12:14:51.762582 output: FIT description: Kernel Image image with one or more FDT blobs
209 12:14:51.762965 output: Created: Wed Jan 31 12:14:51 2024
210 12:14:51.763038 output: Image 0 (kernel-1)
211 12:14:51.763102 output: Description:
212 12:14:51.763164 output: Created: Wed Jan 31 12:14:51 2024
213 12:14:51.763224 output: Type: Kernel Image
214 12:14:51.763283 output: Compression: lzma compressed
215 12:14:51.763342 output: Data Size: 12047284 Bytes = 11764.93 KiB = 11.49 MiB
216 12:14:51.763401 output: Architecture: AArch64
217 12:14:51.763458 output: OS: Linux
218 12:14:51.763537 output: Load Address: 0x00000000
219 12:14:51.763592 output: Entry Point: 0x00000000
220 12:14:51.763648 output: Hash algo: crc32
221 12:14:51.763755 output: Hash value: 5a47eb78
222 12:14:51.763809 output: Image 1 (fdt-1)
223 12:14:51.763860 output: Description: mt8192-asurada-spherion-r0
224 12:14:51.763911 output: Created: Wed Jan 31 12:14:51 2024
225 12:14:51.763977 output: Type: Flat Device Tree
226 12:14:51.764031 output: Compression: uncompressed
227 12:14:51.764083 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 12:14:51.764135 output: Architecture: AArch64
229 12:14:51.764186 output: Hash algo: crc32
230 12:14:51.764238 output: Hash value: cc4352de
231 12:14:51.764289 output: Image 2 (ramdisk-1)
232 12:14:51.764340 output: Description: unavailable
233 12:14:51.764392 output: Created: Wed Jan 31 12:14:51 2024
234 12:14:51.764443 output: Type: RAMDisk Image
235 12:14:51.764495 output: Compression: Unknown Compression
236 12:14:51.764546 output: Data Size: 56437583 Bytes = 55114.83 KiB = 53.82 MiB
237 12:14:51.764598 output: Architecture: AArch64
238 12:14:51.764664 output: OS: Linux
239 12:14:51.764748 output: Load Address: unavailable
240 12:14:51.764799 output: Entry Point: unavailable
241 12:14:51.764851 output: Hash algo: crc32
242 12:14:51.764901 output: Hash value: a78bcb60
243 12:14:51.764952 output: Default Configuration: 'conf-1'
244 12:14:51.765003 output: Configuration 0 (conf-1)
245 12:14:51.765054 output: Description: mt8192-asurada-spherion-r0
246 12:14:51.765105 output: Kernel: kernel-1
247 12:14:51.765155 output: Init Ramdisk: ramdisk-1
248 12:14:51.765206 output: FDT: fdt-1
249 12:14:51.765257 output: Loadables: kernel-1
250 12:14:51.765308 output:
251 12:14:51.765501 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 12:14:51.765595 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 12:14:51.765703 end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
254 12:14:51.765799 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 12:14:51.765876 No LXC device requested
256 12:14:51.765955 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 12:14:51.766039 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 12:14:51.766115 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 12:14:51.766185 Checking files for TFTP limit of 4294967296 bytes.
260 12:14:51.766667 end: 1 tftp-deploy (duration 00:00:23) [common]
261 12:14:51.766768 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 12:14:51.766853 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 12:14:51.766975 substitutions:
264 12:14:51.767041 - {DTB}: 12669522/tftp-deploy-c4g5e4u7/dtb/mt8192-asurada-spherion-r0.dtb
265 12:14:51.767104 - {INITRD}: 12669522/tftp-deploy-c4g5e4u7/ramdisk/ramdisk.cpio.gz
266 12:14:51.767161 - {KERNEL}: 12669522/tftp-deploy-c4g5e4u7/kernel/Image
267 12:14:51.767217 - {LAVA_MAC}: None
268 12:14:51.767271 - {PRESEED_CONFIG}: None
269 12:14:51.767324 - {PRESEED_LOCAL}: None
270 12:14:51.767377 - {RAMDISK}: 12669522/tftp-deploy-c4g5e4u7/ramdisk/ramdisk.cpio.gz
271 12:14:51.767430 - {ROOT_PART}: None
272 12:14:51.767482 - {ROOT}: None
273 12:14:51.767534 - {SERVER_IP}: 192.168.201.1
274 12:14:51.767586 - {TEE}: None
275 12:14:51.767638 Parsed boot commands:
276 12:14:51.767729 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 12:14:51.767938 Parsed boot commands: tftpboot 192.168.201.1 12669522/tftp-deploy-c4g5e4u7/kernel/image.itb 12669522/tftp-deploy-c4g5e4u7/kernel/cmdline
278 12:14:51.768024 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 12:14:51.768110 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 12:14:51.768202 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 12:14:51.768287 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 12:14:51.768357 Not connected, no need to disconnect.
283 12:14:51.768429 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 12:14:51.768509 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 12:14:51.768573 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
286 12:14:51.772648 Setting prompt string to ['lava-test: # ']
287 12:14:51.773003 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 12:14:51.773110 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 12:14:51.773206 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 12:14:51.773313 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 12:14:51.773551 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
292 12:14:56.922095 >> Command sent successfully.
293 12:14:56.932825 Returned 0 in 5 seconds
294 12:14:57.034019 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 12:14:57.035496 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 12:14:57.036083 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 12:14:57.036526 Setting prompt string to 'Starting depthcharge on Spherion...'
299 12:14:57.036878 Changing prompt to 'Starting depthcharge on Spherion...'
300 12:14:57.037216 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 12:14:57.038388 [Enter `^Ec?' for help]
302 12:14:57.198846
303 12:14:57.199481
304 12:14:57.199958 F0: 102B 0000
305 12:14:57.200336
306 12:14:57.200646 F3: 1001 0000 [0200]
307 12:14:57.200958
308 12:14:57.202568 F3: 1001 0000
309 12:14:57.202997
310 12:14:57.203336 F7: 102D 0000
311 12:14:57.203653
312 12:14:57.204091 F1: 0000 0000
313 12:14:57.204414
314 12:14:57.205564 V0: 0000 0000 [0001]
315 12:14:57.205992
316 12:14:57.206333 00: 0007 8000
317 12:14:57.206667
318 12:14:57.209722 01: 0000 0000
319 12:14:57.210325
320 12:14:57.210702 BP: 0C00 0209 [0000]
321 12:14:57.211025
322 12:14:57.213366 G0: 1182 0000
323 12:14:57.213809
324 12:14:57.214151 EC: 0000 0021 [4000]
325 12:14:57.214471
326 12:14:57.216660 S7: 0000 0000 [0000]
327 12:14:57.217090
328 12:14:57.217436 CC: 0000 0000 [0001]
329 12:14:57.217755
330 12:14:57.221257 T0: 0000 0040 [010F]
331 12:14:57.221687
332 12:14:57.222025 Jump to BL
333 12:14:57.222341
334 12:14:57.245312
335 12:14:57.245831
336 12:14:57.246172
337 12:14:57.251715 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 12:14:57.255339 ARM64: Exception handlers installed.
339 12:14:57.258893 ARM64: Testing exception
340 12:14:57.261946 ARM64: Done test exception
341 12:14:57.269185 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 12:14:57.280367 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 12:14:57.288352 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 12:14:57.298896 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 12:14:57.302728 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 12:14:57.313211 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 12:14:57.323056 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 12:14:57.329660 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 12:14:57.347979 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 12:14:57.351866 WDT: Last reset was cold boot
351 12:14:57.354867 SPI1(PAD0) initialized at 2873684 Hz
352 12:14:57.358423 SPI5(PAD0) initialized at 992727 Hz
353 12:14:57.361544 VBOOT: Loading verstage.
354 12:14:57.367972 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 12:14:57.371800 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 12:14:57.374634 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 12:14:57.378058 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 12:14:57.385573 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 12:14:57.392430 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 12:14:57.403264 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 12:14:57.403848
362 12:14:57.404351
363 12:14:57.413440 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 12:14:57.416280 ARM64: Exception handlers installed.
365 12:14:57.419524 ARM64: Testing exception
366 12:14:57.419983 ARM64: Done test exception
367 12:14:57.426367 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 12:14:57.429494 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 12:14:57.445078 Probing TPM: . done!
370 12:14:57.445601 TPM ready after 0 ms
371 12:14:57.450743 Connected to device vid:did:rid of 1ae0:0028:00
372 12:14:57.460260 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 12:14:57.502286 Initialized TPM device CR50 revision 0
374 12:14:57.513639 tlcl_send_startup: Startup return code is 0
375 12:14:57.514209 TPM: setup succeeded
376 12:14:57.524915 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 12:14:57.533453 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 12:14:57.544162 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 12:14:57.552017 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 12:14:57.555570 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 12:14:57.559007 in-header: 03 07 00 00 08 00 00 00
382 12:14:57.562473 in-data: aa e4 47 04 13 02 00 00
383 12:14:57.565646 Chrome EC: UHEPI supported
384 12:14:57.572369 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 12:14:57.576060 in-header: 03 ad 00 00 08 00 00 00
386 12:14:57.578519 in-data: 00 20 20 08 00 00 00 00
387 12:14:57.579081 Phase 1
388 12:14:57.582565 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 12:14:57.588578 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 12:14:57.595542 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 12:14:57.598782 Recovery requested (1009000e)
392 12:14:57.603007 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 12:14:57.611226 tlcl_extend: response is 0
394 12:14:57.619533 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 12:14:57.625326 tlcl_extend: response is 0
396 12:14:57.631305 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 12:14:57.651644 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 12:14:57.658786 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 12:14:57.659363
400 12:14:57.659779
401 12:14:57.668887 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 12:14:57.671991 ARM64: Exception handlers installed.
403 12:14:57.672458 ARM64: Testing exception
404 12:14:57.675480 ARM64: Done test exception
405 12:14:57.697354 pmic_efuse_setting: Set efuses in 11 msecs
406 12:14:57.701323 pmwrap_interface_init: Select PMIF_VLD_RDY
407 12:14:57.707661 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 12:14:57.711474 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 12:14:57.715118 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 12:14:57.721094 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 12:14:57.725914 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 12:14:57.731943 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 12:14:57.735244 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 12:14:57.741431 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 12:14:57.745246 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 12:14:57.748370 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 12:14:57.755292 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 12:14:57.758642 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 12:14:57.761671 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 12:14:57.768603 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 12:14:57.775222 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 12:14:57.781899 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 12:14:57.785219 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 12:14:57.791864 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 12:14:57.798140 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 12:14:57.801648 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 12:14:57.809301 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 12:14:57.815982 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 12:14:57.819977 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 12:14:57.827365 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 12:14:57.830943 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 12:14:57.836173 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 12:14:57.839661 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 12:14:57.846601 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 12:14:57.849960 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 12:14:57.857718 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 12:14:57.861683 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 12:14:57.868032 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 12:14:57.870795 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 12:14:57.877653 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 12:14:57.880836 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 12:14:57.888152 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 12:14:57.891302 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 12:14:57.898120 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 12:14:57.901627 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 12:14:57.905713 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 12:14:57.908675 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 12:14:57.912290 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 12:14:57.918770 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 12:14:57.922405 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 12:14:57.926132 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 12:14:57.932416 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 12:14:57.935373 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 12:14:57.939157 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 12:14:57.945189 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 12:14:57.948399 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 12:14:57.952237 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 12:14:57.958751 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 12:14:57.969406 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 12:14:57.971890 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 12:14:57.982010 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 12:14:57.989398 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 12:14:57.995555 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 12:14:57.998638 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 12:14:58.002730 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 12:14:58.010619 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x1e
467 12:14:58.016288 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 12:14:58.020315 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
469 12:14:58.026396 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 12:14:58.033980 [RTC]rtc_get_frequency_meter,154: input=15, output=835
471 12:14:58.044177 [RTC]rtc_get_frequency_meter,154: input=7, output=709
472 12:14:58.053717 [RTC]rtc_get_frequency_meter,154: input=11, output=772
473 12:14:58.063078 [RTC]rtc_get_frequency_meter,154: input=13, output=804
474 12:14:58.072115 [RTC]rtc_get_frequency_meter,154: input=12, output=788
475 12:14:58.081677 [RTC]rtc_get_frequency_meter,154: input=12, output=788
476 12:14:58.091104 [RTC]rtc_get_frequency_meter,154: input=13, output=803
477 12:14:58.094732 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
478 12:14:58.101400 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
479 12:14:58.105333 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 12:14:58.108637 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 12:14:58.115614 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 12:14:58.118686 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 12:14:58.121613 ADC[4]: Raw value=905988 ID=7
484 12:14:58.122078 ADC[3]: Raw value=214021 ID=1
485 12:14:58.125518 RAM Code: 0x71
486 12:14:58.128905 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 12:14:58.134569 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 12:14:58.141332 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 12:14:58.147801 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 12:14:58.151381 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 12:14:58.154980 in-header: 03 07 00 00 08 00 00 00
492 12:14:58.158445 in-data: aa e4 47 04 13 02 00 00
493 12:14:58.162394 Chrome EC: UHEPI supported
494 12:14:58.168164 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 12:14:58.171431 in-header: 03 dd 00 00 08 00 00 00
496 12:14:58.174912 in-data: 90 20 60 08 00 00 00 00
497 12:14:58.178851 MRC: failed to locate region type 0.
498 12:14:58.185190 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 12:14:58.188013 DRAM-K: Running full calibration
500 12:14:58.194318 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 12:14:58.194899 header.status = 0x0
502 12:14:58.198024 header.version = 0x6 (expected: 0x6)
503 12:14:58.201237 header.size = 0xd00 (expected: 0xd00)
504 12:14:58.204559 header.flags = 0x0
505 12:14:58.211310 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 12:14:58.228420 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 12:14:58.235271 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 12:14:58.237863 dram_init: ddr_geometry: 2
509 12:14:58.241124 [EMI] MDL number = 2
510 12:14:58.241609 [EMI] Get MDL freq = 0
511 12:14:58.244860 dram_init: ddr_type: 0
512 12:14:58.245422 is_discrete_lpddr4: 1
513 12:14:58.248331 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 12:14:58.248900
515 12:14:58.249271
516 12:14:58.250944 [Bian_co] ETT version 0.0.0.1
517 12:14:58.258350 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 12:14:58.258918
519 12:14:58.261631 dramc_set_vcore_voltage set vcore to 650000
520 12:14:58.264943 Read voltage for 800, 4
521 12:14:58.265507 Vio18 = 0
522 12:14:58.265881 Vcore = 650000
523 12:14:58.267551 Vdram = 0
524 12:14:58.268056 Vddq = 0
525 12:14:58.268469 Vmddr = 0
526 12:14:58.271535 dram_init: config_dvfs: 1
527 12:14:58.274172 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 12:14:58.281054 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 12:14:58.284729 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
530 12:14:58.287604 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
531 12:14:58.291399 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
532 12:14:58.294690 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
533 12:14:58.297618 MEM_TYPE=3, freq_sel=18
534 12:14:58.301266 sv_algorithm_assistance_LP4_1600
535 12:14:58.304489 ============ PULL DRAM RESETB DOWN ============
536 12:14:58.311270 ========== PULL DRAM RESETB DOWN end =========
537 12:14:58.314596 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 12:14:58.317458 ===================================
539 12:14:58.320810 LPDDR4 DRAM CONFIGURATION
540 12:14:58.324615 ===================================
541 12:14:58.325190 EX_ROW_EN[0] = 0x0
542 12:14:58.328370 EX_ROW_EN[1] = 0x0
543 12:14:58.328945 LP4Y_EN = 0x0
544 12:14:58.331299 WORK_FSP = 0x0
545 12:14:58.331898 WL = 0x2
546 12:14:58.334436 RL = 0x2
547 12:14:58.334913 BL = 0x2
548 12:14:58.337649 RPST = 0x0
549 12:14:58.338124 RD_PRE = 0x0
550 12:14:58.340820 WR_PRE = 0x1
551 12:14:58.344647 WR_PST = 0x0
552 12:14:58.345218 DBI_WR = 0x0
553 12:14:58.348014 DBI_RD = 0x0
554 12:14:58.348590 OTF = 0x1
555 12:14:58.351101 ===================================
556 12:14:58.354209 ===================================
557 12:14:58.357566 ANA top config
558 12:14:58.358088 ===================================
559 12:14:58.361391 DLL_ASYNC_EN = 0
560 12:14:58.363724 ALL_SLAVE_EN = 1
561 12:14:58.367307 NEW_RANK_MODE = 1
562 12:14:58.370711 DLL_IDLE_MODE = 1
563 12:14:58.371237 LP45_APHY_COMB_EN = 1
564 12:14:58.373834 TX_ODT_DIS = 1
565 12:14:58.378168 NEW_8X_MODE = 1
566 12:14:58.380211 ===================================
567 12:14:58.383903 ===================================
568 12:14:58.387766 data_rate = 1600
569 12:14:58.390601 CKR = 1
570 12:14:58.393402 DQ_P2S_RATIO = 8
571 12:14:58.393832 ===================================
572 12:14:58.397325 CA_P2S_RATIO = 8
573 12:14:58.400531 DQ_CA_OPEN = 0
574 12:14:58.404061 DQ_SEMI_OPEN = 0
575 12:14:58.407219 CA_SEMI_OPEN = 0
576 12:14:58.410696 CA_FULL_RATE = 0
577 12:14:58.411271 DQ_CKDIV4_EN = 1
578 12:14:58.413756 CA_CKDIV4_EN = 1
579 12:14:58.416827 CA_PREDIV_EN = 0
580 12:14:58.420421 PH8_DLY = 0
581 12:14:58.423662 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 12:14:58.427729 DQ_AAMCK_DIV = 4
583 12:14:58.428291 CA_AAMCK_DIV = 4
584 12:14:58.430520 CA_ADMCK_DIV = 4
585 12:14:58.433601 DQ_TRACK_CA_EN = 0
586 12:14:58.437915 CA_PICK = 800
587 12:14:58.440239 CA_MCKIO = 800
588 12:14:58.444126 MCKIO_SEMI = 0
589 12:14:58.447095 PLL_FREQ = 3068
590 12:14:58.447660 DQ_UI_PI_RATIO = 32
591 12:14:58.450296 CA_UI_PI_RATIO = 0
592 12:14:58.453833 ===================================
593 12:14:58.457042 ===================================
594 12:14:58.460620 memory_type:LPDDR4
595 12:14:58.463827 GP_NUM : 10
596 12:14:58.464398 SRAM_EN : 1
597 12:14:58.466997 MD32_EN : 0
598 12:14:58.470671 ===================================
599 12:14:58.473139 [ANA_INIT] >>>>>>>>>>>>>>
600 12:14:58.473613 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 12:14:58.477118 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 12:14:58.480533 ===================================
603 12:14:58.483585 data_rate = 1600,PCW = 0X7600
604 12:14:58.487059 ===================================
605 12:14:58.490379 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 12:14:58.496636 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 12:14:58.503829 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 12:14:58.506711 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 12:14:58.509966 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 12:14:58.512865 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 12:14:58.516582 [ANA_INIT] flow start
612 12:14:58.517008 [ANA_INIT] PLL >>>>>>>>
613 12:14:58.519491 [ANA_INIT] PLL <<<<<<<<
614 12:14:58.522945 [ANA_INIT] MIDPI >>>>>>>>
615 12:14:58.526485 [ANA_INIT] MIDPI <<<<<<<<
616 12:14:58.526910 [ANA_INIT] DLL >>>>>>>>
617 12:14:58.529802 [ANA_INIT] flow end
618 12:14:58.532867 ============ LP4 DIFF to SE enter ============
619 12:14:58.536230 ============ LP4 DIFF to SE exit ============
620 12:14:58.540005 [ANA_INIT] <<<<<<<<<<<<<
621 12:14:58.543977 [Flow] Enable top DCM control >>>>>
622 12:14:58.546265 [Flow] Enable top DCM control <<<<<
623 12:14:58.549554 Enable DLL master slave shuffle
624 12:14:58.556241 ==============================================================
625 12:14:58.556678 Gating Mode config
626 12:14:58.563247 ==============================================================
627 12:14:58.563701 Config description:
628 12:14:58.573240 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 12:14:58.579732 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 12:14:58.586794 SELPH_MODE 0: By rank 1: By Phase
631 12:14:58.589344 ==============================================================
632 12:14:58.593025 GAT_TRACK_EN = 1
633 12:14:58.596099 RX_GATING_MODE = 2
634 12:14:58.599706 RX_GATING_TRACK_MODE = 2
635 12:14:58.603194 SELPH_MODE = 1
636 12:14:58.606531 PICG_EARLY_EN = 1
637 12:14:58.609240 VALID_LAT_VALUE = 1
638 12:14:58.612733 ==============================================================
639 12:14:58.616505 Enter into Gating configuration >>>>
640 12:14:58.619133 Exit from Gating configuration <<<<
641 12:14:58.623033 Enter into DVFS_PRE_config >>>>>
642 12:14:58.635792 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 12:14:58.638899 Exit from DVFS_PRE_config <<<<<
644 12:14:58.643140 Enter into PICG configuration >>>>
645 12:14:58.645752 Exit from PICG configuration <<<<
646 12:14:58.646177 [RX_INPUT] configuration >>>>>
647 12:14:58.649073 [RX_INPUT] configuration <<<<<
648 12:14:58.656528 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 12:14:58.659988 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 12:14:58.666805 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 12:14:58.674338 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 12:14:58.677586 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 12:14:58.684443 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 12:14:58.688435 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 12:14:58.691456 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 12:14:58.699373 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 12:14:58.702402 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 12:14:58.706853 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 12:14:58.709632 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 12:14:58.713770 ===================================
661 12:14:58.716606 LPDDR4 DRAM CONFIGURATION
662 12:14:58.720080 ===================================
663 12:14:58.720586 EX_ROW_EN[0] = 0x0
664 12:14:58.723562 EX_ROW_EN[1] = 0x0
665 12:14:58.724057 LP4Y_EN = 0x0
666 12:14:58.727328 WORK_FSP = 0x0
667 12:14:58.728009 WL = 0x2
668 12:14:58.731702 RL = 0x2
669 12:14:58.732239 BL = 0x2
670 12:14:58.734797 RPST = 0x0
671 12:14:58.735329 RD_PRE = 0x0
672 12:14:58.738239 WR_PRE = 0x1
673 12:14:58.738811 WR_PST = 0x0
674 12:14:58.739345 DBI_WR = 0x0
675 12:14:58.742851 DBI_RD = 0x0
676 12:14:58.743561 OTF = 0x1
677 12:14:58.746566 ===================================
678 12:14:58.749380 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 12:14:58.753867 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 12:14:58.760588 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 12:14:58.764631 ===================================
682 12:14:58.765193 LPDDR4 DRAM CONFIGURATION
683 12:14:58.768155 ===================================
684 12:14:58.772041 EX_ROW_EN[0] = 0x10
685 12:14:58.772499 EX_ROW_EN[1] = 0x0
686 12:14:58.775959 LP4Y_EN = 0x0
687 12:14:58.776400 WORK_FSP = 0x0
688 12:14:58.779481 WL = 0x2
689 12:14:58.779939 RL = 0x2
690 12:14:58.783122 BL = 0x2
691 12:14:58.783729 RPST = 0x0
692 12:14:58.784089 RD_PRE = 0x0
693 12:14:58.787071 WR_PRE = 0x1
694 12:14:58.787494 WR_PST = 0x0
695 12:14:58.790979 DBI_WR = 0x0
696 12:14:58.791569 DBI_RD = 0x0
697 12:14:58.793803 OTF = 0x1
698 12:14:58.796759 ===================================
699 12:14:58.804229 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 12:14:58.808154 nWR fixed to 40
701 12:14:58.808675 [ModeRegInit_LP4] CH0 RK0
702 12:14:58.811719 [ModeRegInit_LP4] CH0 RK1
703 12:14:58.812221 [ModeRegInit_LP4] CH1 RK0
704 12:14:58.815423 [ModeRegInit_LP4] CH1 RK1
705 12:14:58.818687 match AC timing 13
706 12:14:58.823192 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 12:14:58.827274 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 12:14:58.829036 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 12:14:58.835853 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 12:14:58.839495 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 12:14:58.842329 [EMI DOE] emi_dcm 0
712 12:14:58.845716 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 12:14:58.846192 ==
714 12:14:58.849136 Dram Type= 6, Freq= 0, CH_0, rank 0
715 12:14:58.852217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 12:14:58.852646 ==
717 12:14:58.858623 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 12:14:58.865718 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 12:14:58.874302 [CA 0] Center 37 (6~68) winsize 63
720 12:14:58.877324 [CA 1] Center 37 (6~68) winsize 63
721 12:14:58.880379 [CA 2] Center 34 (4~65) winsize 62
722 12:14:58.884007 [CA 3] Center 34 (4~65) winsize 62
723 12:14:58.888092 [CA 4] Center 33 (3~64) winsize 62
724 12:14:58.891402 [CA 5] Center 33 (3~64) winsize 62
725 12:14:58.891927
726 12:14:58.894474 [CmdBusTrainingLP45] Vref(ca) range 1: 32
727 12:14:58.895170
728 12:14:58.897560 [CATrainingPosCal] consider 1 rank data
729 12:14:58.901499 u2DelayCellTimex100 = 270/100 ps
730 12:14:58.904370 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
731 12:14:58.907617 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 12:14:58.912049 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 12:14:58.915894 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 12:14:58.921821 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
735 12:14:58.924853 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 12:14:58.925320
737 12:14:58.927803 CA PerBit enable=1, Macro0, CA PI delay=33
738 12:14:58.928268
739 12:14:58.931810 [CBTSetCACLKResult] CA Dly = 33
740 12:14:58.932384 CS Dly: 6 (0~37)
741 12:14:58.932759 ==
742 12:14:58.934211 Dram Type= 6, Freq= 0, CH_0, rank 1
743 12:14:58.941540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 12:14:58.942094 ==
745 12:14:58.945061 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 12:14:58.951439 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 12:14:58.960614 [CA 0] Center 37 (6~68) winsize 63
748 12:14:58.963837 [CA 1] Center 37 (7~68) winsize 62
749 12:14:58.967117 [CA 2] Center 34 (4~65) winsize 62
750 12:14:58.970097 [CA 3] Center 34 (4~65) winsize 62
751 12:14:58.973007 [CA 4] Center 33 (3~64) winsize 62
752 12:14:58.976586 [CA 5] Center 33 (3~64) winsize 62
753 12:14:58.977053
754 12:14:58.980172 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 12:14:58.980643
756 12:14:58.983309 [CATrainingPosCal] consider 2 rank data
757 12:14:58.986989 u2DelayCellTimex100 = 270/100 ps
758 12:14:58.990137 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
759 12:14:58.993642 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 12:14:58.998061 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 12:14:59.000847 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 12:14:59.004172 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
763 12:14:59.011464 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 12:14:59.012052
765 12:14:59.015486 CA PerBit enable=1, Macro0, CA PI delay=33
766 12:14:59.016167
767 12:14:59.016550 [CBTSetCACLKResult] CA Dly = 33
768 12:14:59.019506 CS Dly: 6 (0~38)
769 12:14:59.020035
770 12:14:59.022888 ----->DramcWriteLeveling(PI) begin...
771 12:14:59.023478 ==
772 12:14:59.026364 Dram Type= 6, Freq= 0, CH_0, rank 0
773 12:14:59.029401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 12:14:59.030022 ==
775 12:14:59.032869 Write leveling (Byte 0): 34 => 34
776 12:14:59.036338 Write leveling (Byte 1): 29 => 29
777 12:14:59.039870 DramcWriteLeveling(PI) end<-----
778 12:14:59.040431
779 12:14:59.040804 ==
780 12:14:59.042877 Dram Type= 6, Freq= 0, CH_0, rank 0
781 12:14:59.046808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 12:14:59.047376 ==
783 12:14:59.049930 [Gating] SW mode calibration
784 12:14:59.056358 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 12:14:59.063514 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 12:14:59.065940 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 12:14:59.069084 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 12:14:59.075846 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 12:14:59.080041 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 12:14:59.082820 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 12:14:59.089001 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 12:14:59.092164 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 12:14:59.095782 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 12:14:59.102107 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 12:14:59.105597 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 12:14:59.109576 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 12:14:59.115741 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 12:14:59.119234 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 12:14:59.122095 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 12:14:59.128593 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 12:14:59.131928 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 12:14:59.135452 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 12:14:59.142095 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
804 12:14:59.145130 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
805 12:14:59.148831 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 12:14:59.151904 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 12:14:59.159153 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 12:14:59.162157 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 12:14:59.165814 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 12:14:59.172257 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 12:14:59.175356 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 12:14:59.178875 0 9 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
813 12:14:59.185466 0 9 12 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
814 12:14:59.188178 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 12:14:59.191940 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 12:14:59.198341 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 12:14:59.201852 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 12:14:59.205589 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 12:14:59.209384 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
820 12:14:59.216407 0 10 8 | B1->B0 | 3131 2a2a | 1 0 | (1 0) (0 0)
821 12:14:59.220536 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
822 12:14:59.223378 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 12:14:59.227609 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 12:14:59.234845 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 12:14:59.238251 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 12:14:59.242310 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 12:14:59.245742 0 11 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
828 12:14:59.249217 0 11 8 | B1->B0 | 2625 3838 | 1 1 | (0 0) (0 0)
829 12:14:59.256809 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
830 12:14:59.260838 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 12:14:59.264219 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 12:14:59.267747 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 12:14:59.273378 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 12:14:59.277046 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 12:14:59.280598 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 12:14:59.287262 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 12:14:59.290655 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 12:14:59.293521 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 12:14:59.300411 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 12:14:59.304037 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 12:14:59.307013 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 12:14:59.310381 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 12:14:59.317037 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 12:14:59.322469 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 12:14:59.324131 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 12:14:59.328329 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 12:14:59.335331 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 12:14:59.339496 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 12:14:59.342295 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 12:14:59.345382 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 12:14:59.352330 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 12:14:59.356009 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 12:14:59.359270 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
854 12:14:59.362158 Total UI for P1: 0, mck2ui 16
855 12:14:59.366204 best dqsien dly found for B0: ( 0, 14, 8)
856 12:14:59.372383 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
857 12:14:59.372811 Total UI for P1: 0, mck2ui 16
858 12:14:59.379379 best dqsien dly found for B1: ( 0, 14, 10)
859 12:14:59.383220 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
860 12:14:59.386095 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
861 12:14:59.386618
862 12:14:59.388793 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 12:14:59.392742 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
864 12:14:59.396193 [Gating] SW calibration Done
865 12:14:59.396637 ==
866 12:14:59.399540 Dram Type= 6, Freq= 0, CH_0, rank 0
867 12:14:59.402887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
868 12:14:59.403523 ==
869 12:14:59.403988 RX Vref Scan: 0
870 12:14:59.406218
871 12:14:59.406731 RX Vref 0 -> 0, step: 1
872 12:14:59.407069
873 12:14:59.409956 RX Delay -130 -> 252, step: 16
874 12:14:59.413672 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
875 12:14:59.415924 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
876 12:14:59.422826 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
877 12:14:59.426497 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
878 12:14:59.429367 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
879 12:14:59.432411 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
880 12:14:59.435635 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
881 12:14:59.442359 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
882 12:14:59.445917 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
883 12:14:59.449576 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
884 12:14:59.452274 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
885 12:14:59.458818 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
886 12:14:59.462403 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
887 12:14:59.465968 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
888 12:14:59.468775 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
889 12:14:59.472302 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
890 12:14:59.472722 ==
891 12:14:59.476245 Dram Type= 6, Freq= 0, CH_0, rank 0
892 12:14:59.482228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
893 12:14:59.482742 ==
894 12:14:59.483079 DQS Delay:
895 12:14:59.485697 DQS0 = 0, DQS1 = 0
896 12:14:59.486245 DQM Delay:
897 12:14:59.486758 DQM0 = 86, DQM1 = 75
898 12:14:59.489694 DQ Delay:
899 12:14:59.492160 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
900 12:14:59.495964 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
901 12:14:59.499411 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
902 12:14:59.502446 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
903 12:14:59.502975
904 12:14:59.503311
905 12:14:59.503730 ==
906 12:14:59.505673 Dram Type= 6, Freq= 0, CH_0, rank 0
907 12:14:59.508480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 12:14:59.508905 ==
909 12:14:59.509239
910 12:14:59.509547
911 12:14:59.511759 TX Vref Scan disable
912 12:14:59.516073 == TX Byte 0 ==
913 12:14:59.519133 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
914 12:14:59.521787 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
915 12:14:59.525984 == TX Byte 1 ==
916 12:14:59.529459 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
917 12:14:59.532634 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
918 12:14:59.533155 ==
919 12:14:59.535535 Dram Type= 6, Freq= 0, CH_0, rank 0
920 12:14:59.538786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
921 12:14:59.542209 ==
922 12:14:59.553793 TX Vref=22, minBit 4, minWin=27, winSum=439
923 12:14:59.557108 TX Vref=24, minBit 5, minWin=27, winSum=440
924 12:14:59.560256 TX Vref=26, minBit 8, minWin=27, winSum=446
925 12:14:59.563403 TX Vref=28, minBit 8, minWin=27, winSum=447
926 12:14:59.566590 TX Vref=30, minBit 8, minWin=27, winSum=448
927 12:14:59.573488 TX Vref=32, minBit 4, minWin=27, winSum=445
928 12:14:59.576873 [TxChooseVref] Worse bit 8, Min win 27, Win sum 448, Final Vref 30
929 12:14:59.577296
930 12:14:59.580343 Final TX Range 1 Vref 30
931 12:14:59.580906
932 12:14:59.581252 ==
933 12:14:59.583378 Dram Type= 6, Freq= 0, CH_0, rank 0
934 12:14:59.586479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 12:14:59.586903 ==
936 12:14:59.590218
937 12:14:59.590723
938 12:14:59.591084 TX Vref Scan disable
939 12:14:59.593948 == TX Byte 0 ==
940 12:14:59.597710 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
941 12:14:59.600335 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
942 12:14:59.603591 == TX Byte 1 ==
943 12:14:59.607078 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
944 12:14:59.610305 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
945 12:14:59.610791
946 12:14:59.614093 [DATLAT]
947 12:14:59.614634 Freq=800, CH0 RK0
948 12:14:59.614976
949 12:14:59.617731 DATLAT Default: 0xa
950 12:14:59.618151 0, 0xFFFF, sum = 0
951 12:14:59.621670 1, 0xFFFF, sum = 0
952 12:14:59.622143 2, 0xFFFF, sum = 0
953 12:14:59.625420 3, 0xFFFF, sum = 0
954 12:14:59.625938 4, 0xFFFF, sum = 0
955 12:14:59.628734 5, 0xFFFF, sum = 0
956 12:14:59.629246 6, 0xFFFF, sum = 0
957 12:14:59.629657 7, 0xFFFF, sum = 0
958 12:14:59.632522 8, 0xFFFF, sum = 0
959 12:14:59.633087 9, 0x0, sum = 1
960 12:14:59.635812 10, 0x0, sum = 2
961 12:14:59.636383 11, 0x0, sum = 3
962 12:14:59.640117 12, 0x0, sum = 4
963 12:14:59.640559 best_step = 10
964 12:14:59.640894
965 12:14:59.641204 ==
966 12:14:59.643354 Dram Type= 6, Freq= 0, CH_0, rank 0
967 12:14:59.646969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
968 12:14:59.647543 ==
969 12:14:59.650576 RX Vref Scan: 1
970 12:14:59.651128
971 12:14:59.651473 Set Vref Range= 32 -> 127
972 12:14:59.651832
973 12:14:59.654244 RX Vref 32 -> 127, step: 1
974 12:14:59.654702
975 12:14:59.658222 RX Delay -111 -> 252, step: 8
976 12:14:59.658640
977 12:14:59.662244 Set Vref, RX VrefLevel [Byte0]: 32
978 12:14:59.665045 [Byte1]: 32
979 12:14:59.665519
980 12:14:59.669037 Set Vref, RX VrefLevel [Byte0]: 33
981 12:14:59.672596 [Byte1]: 33
982 12:14:59.673049
983 12:14:59.675798 Set Vref, RX VrefLevel [Byte0]: 34
984 12:14:59.679793 [Byte1]: 34
985 12:14:59.680225
986 12:14:59.683070 Set Vref, RX VrefLevel [Byte0]: 35
987 12:14:59.687298 [Byte1]: 35
988 12:14:59.687872
989 12:14:59.689782 Set Vref, RX VrefLevel [Byte0]: 36
990 12:14:59.693503 [Byte1]: 36
991 12:14:59.697560
992 12:14:59.697981 Set Vref, RX VrefLevel [Byte0]: 37
993 12:14:59.701124 [Byte1]: 37
994 12:14:59.704916
995 12:14:59.705343 Set Vref, RX VrefLevel [Byte0]: 38
996 12:14:59.708193 [Byte1]: 38
997 12:14:59.713307
998 12:14:59.715316 Set Vref, RX VrefLevel [Byte0]: 39
999 12:14:59.715784 [Byte1]: 39
1000 12:14:59.720323
1001 12:14:59.720740 Set Vref, RX VrefLevel [Byte0]: 40
1002 12:14:59.723150 [Byte1]: 40
1003 12:14:59.728397
1004 12:14:59.728909 Set Vref, RX VrefLevel [Byte0]: 41
1005 12:14:59.731555 [Byte1]: 41
1006 12:14:59.736055
1007 12:14:59.736473 Set Vref, RX VrefLevel [Byte0]: 42
1008 12:14:59.738679 [Byte1]: 42
1009 12:14:59.743175
1010 12:14:59.743588 Set Vref, RX VrefLevel [Byte0]: 43
1011 12:14:59.747399 [Byte1]: 43
1012 12:14:59.751786
1013 12:14:59.752256 Set Vref, RX VrefLevel [Byte0]: 44
1014 12:14:59.754356 [Byte1]: 44
1015 12:14:59.758553
1016 12:14:59.758972 Set Vref, RX VrefLevel [Byte0]: 45
1017 12:14:59.763380 [Byte1]: 45
1018 12:14:59.766491
1019 12:14:59.767106 Set Vref, RX VrefLevel [Byte0]: 46
1020 12:14:59.769682 [Byte1]: 46
1021 12:14:59.773782
1022 12:14:59.774207 Set Vref, RX VrefLevel [Byte0]: 47
1023 12:14:59.777292 [Byte1]: 47
1024 12:14:59.781331
1025 12:14:59.781766 Set Vref, RX VrefLevel [Byte0]: 48
1026 12:14:59.786142 [Byte1]: 48
1027 12:14:59.788924
1028 12:14:59.789357 Set Vref, RX VrefLevel [Byte0]: 49
1029 12:14:59.792385 [Byte1]: 49
1030 12:14:59.796397
1031 12:14:59.799577 Set Vref, RX VrefLevel [Byte0]: 50
1032 12:14:59.800039 [Byte1]: 50
1033 12:14:59.804179
1034 12:14:59.804629 Set Vref, RX VrefLevel [Byte0]: 51
1035 12:14:59.808433 [Byte1]: 51
1036 12:14:59.812185
1037 12:14:59.812700 Set Vref, RX VrefLevel [Byte0]: 52
1038 12:14:59.819263 [Byte1]: 52
1039 12:14:59.820146
1040 12:14:59.820500 Set Vref, RX VrefLevel [Byte0]: 53
1041 12:14:59.823554 [Byte1]: 53
1042 12:14:59.826808
1043 12:14:59.827265 Set Vref, RX VrefLevel [Byte0]: 54
1044 12:14:59.830647 [Byte1]: 54
1045 12:14:59.834721
1046 12:14:59.835248 Set Vref, RX VrefLevel [Byte0]: 55
1047 12:14:59.837839 [Byte1]: 55
1048 12:14:59.842636
1049 12:14:59.843159 Set Vref, RX VrefLevel [Byte0]: 56
1050 12:14:59.845612 [Byte1]: 56
1051 12:14:59.850463
1052 12:14:59.850875 Set Vref, RX VrefLevel [Byte0]: 57
1053 12:14:59.853651 [Byte1]: 57
1054 12:14:59.857460
1055 12:14:59.857872 Set Vref, RX VrefLevel [Byte0]: 58
1056 12:14:59.861068 [Byte1]: 58
1057 12:14:59.865107
1058 12:14:59.865519 Set Vref, RX VrefLevel [Byte0]: 59
1059 12:14:59.871491 [Byte1]: 59
1060 12:14:59.871870
1061 12:14:59.875616 Set Vref, RX VrefLevel [Byte0]: 60
1062 12:14:59.878825 [Byte1]: 60
1063 12:14:59.879115
1064 12:14:59.881992 Set Vref, RX VrefLevel [Byte0]: 61
1065 12:14:59.885416 [Byte1]: 61
1066 12:14:59.885565
1067 12:14:59.888859 Set Vref, RX VrefLevel [Byte0]: 62
1068 12:14:59.892103 [Byte1]: 62
1069 12:14:59.892216
1070 12:14:59.896157 Set Vref, RX VrefLevel [Byte0]: 63
1071 12:14:59.899852 [Byte1]: 63
1072 12:14:59.899964
1073 12:14:59.903760 Set Vref, RX VrefLevel [Byte0]: 64
1074 12:14:59.906888 [Byte1]: 64
1075 12:14:59.911801
1076 12:14:59.911913 Set Vref, RX VrefLevel [Byte0]: 65
1077 12:14:59.914389 [Byte1]: 65
1078 12:14:59.918270
1079 12:14:59.918382 Set Vref, RX VrefLevel [Byte0]: 66
1080 12:14:59.922206 [Byte1]: 66
1081 12:14:59.925769
1082 12:14:59.929284 Set Vref, RX VrefLevel [Byte0]: 67
1083 12:14:59.929406 [Byte1]: 67
1084 12:14:59.933478
1085 12:14:59.936835 Set Vref, RX VrefLevel [Byte0]: 68
1086 12:14:59.936973 [Byte1]: 68
1087 12:14:59.941491
1088 12:14:59.941644 Set Vref, RX VrefLevel [Byte0]: 69
1089 12:14:59.944446 [Byte1]: 69
1090 12:14:59.949677
1091 12:14:59.950086 Set Vref, RX VrefLevel [Byte0]: 70
1092 12:14:59.953475 [Byte1]: 70
1093 12:14:59.957038
1094 12:14:59.957483 Set Vref, RX VrefLevel [Byte0]: 71
1095 12:14:59.960991 [Byte1]: 71
1096 12:14:59.965099
1097 12:14:59.965637 Set Vref, RX VrefLevel [Byte0]: 72
1098 12:14:59.968211 [Byte1]: 72
1099 12:14:59.973014
1100 12:14:59.973556 Set Vref, RX VrefLevel [Byte0]: 73
1101 12:14:59.976650 [Byte1]: 73
1102 12:14:59.981012
1103 12:14:59.981422 Set Vref, RX VrefLevel [Byte0]: 74
1104 12:14:59.983601 [Byte1]: 74
1105 12:14:59.988549
1106 12:14:59.989065 Set Vref, RX VrefLevel [Byte0]: 75
1107 12:14:59.994351 [Byte1]: 75
1108 12:14:59.994893
1109 12:14:59.997806 Set Vref, RX VrefLevel [Byte0]: 76
1110 12:15:00.001451 [Byte1]: 76
1111 12:15:00.001979
1112 12:15:00.005039 Set Vref, RX VrefLevel [Byte0]: 77
1113 12:15:00.008705 [Byte1]: 77
1114 12:15:00.009143
1115 12:15:00.011826 Set Vref, RX VrefLevel [Byte0]: 78
1116 12:15:00.015478 [Byte1]: 78
1117 12:15:00.016099
1118 12:15:00.019356 Set Vref, RX VrefLevel [Byte0]: 79
1119 12:15:00.022347 [Byte1]: 79
1120 12:15:00.022783
1121 12:15:00.026178 Set Vref, RX VrefLevel [Byte0]: 80
1122 12:15:00.030990 [Byte1]: 80
1123 12:15:00.033758
1124 12:15:00.034278 Set Vref, RX VrefLevel [Byte0]: 81
1125 12:15:00.037853 [Byte1]: 81
1126 12:15:00.041275
1127 12:15:00.041777 Set Vref, RX VrefLevel [Byte0]: 82
1128 12:15:00.044588 [Byte1]: 82
1129 12:15:00.049168
1130 12:15:00.049696 Set Vref, RX VrefLevel [Byte0]: 83
1131 12:15:00.052194 [Byte1]: 83
1132 12:15:00.056499
1133 12:15:00.056911 Final RX Vref Byte 0 = 60 to rank0
1134 12:15:00.059726 Final RX Vref Byte 1 = 57 to rank0
1135 12:15:00.063639 Final RX Vref Byte 0 = 60 to rank1
1136 12:15:00.068071 Final RX Vref Byte 1 = 57 to rank1==
1137 12:15:00.070938 Dram Type= 6, Freq= 0, CH_0, rank 0
1138 12:15:00.074639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 12:15:00.075056 ==
1140 12:15:00.075463 DQS Delay:
1141 12:15:00.078387 DQS0 = 0, DQS1 = 0
1142 12:15:00.078801 DQM Delay:
1143 12:15:00.082000 DQM0 = 87, DQM1 = 75
1144 12:15:00.082521 DQ Delay:
1145 12:15:00.085280 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1146 12:15:00.088930 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1147 12:15:00.092885 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1148 12:15:00.096307 DQ12 =80, DQ13 =76, DQ14 =88, DQ15 =84
1149 12:15:00.096733
1150 12:15:00.097062
1151 12:15:00.103265 [DQSOSCAuto] RK0, (LSB)MR18= 0x4122, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1152 12:15:00.106866 CH0 RK0: MR19=606, MR18=4122
1153 12:15:00.114059 CH0_RK0: MR19=0x606, MR18=0x4122, DQSOSC=393, MR23=63, INC=95, DEC=63
1154 12:15:00.114622
1155 12:15:00.157339 ----->DramcWriteLeveling(PI) begin...
1156 12:15:00.157911 ==
1157 12:15:00.158276 Dram Type= 6, Freq= 0, CH_0, rank 1
1158 12:15:00.159211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1159 12:15:00.159880 ==
1160 12:15:00.160251 Write leveling (Byte 0): 32 => 32
1161 12:15:00.160585 Write leveling (Byte 1): 31 => 31
1162 12:15:00.160952 DramcWriteLeveling(PI) end<-----
1163 12:15:00.161271
1164 12:15:00.161782 ==
1165 12:15:00.162174 Dram Type= 6, Freq= 0, CH_0, rank 1
1166 12:15:00.162493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1167 12:15:00.162805 ==
1168 12:15:00.163197 [Gating] SW mode calibration
1169 12:15:00.163523 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1170 12:15:00.163891 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1171 12:15:00.167551 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1172 12:15:00.170998 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1173 12:15:00.171517 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1174 12:15:00.174478 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 12:15:00.177164 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 12:15:00.180491 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 12:15:00.187373 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 12:15:00.190788 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 12:15:00.193937 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 12:15:00.200668 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 12:15:00.203723 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 12:15:00.208130 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 12:15:00.214101 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 12:15:00.216553 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 12:15:00.220827 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 12:15:00.227084 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 12:15:00.230039 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 12:15:00.233191 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1189 12:15:00.240335 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1190 12:15:00.243045 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 12:15:00.246906 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 12:15:00.253231 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 12:15:00.256927 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 12:15:00.259751 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 12:15:00.267146 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 12:15:00.270508 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 12:15:00.273193 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1198 12:15:00.279763 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1199 12:15:00.283068 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 12:15:00.287076 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1201 12:15:00.293530 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1202 12:15:00.296409 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1203 12:15:00.299586 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1204 12:15:00.306412 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1205 12:15:00.309755 0 10 8 | B1->B0 | 2e2e 2525 | 0 0 | (0 0) (0 0)
1206 12:15:00.312566 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
1207 12:15:00.319753 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 12:15:00.322754 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 12:15:00.326098 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 12:15:00.332997 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 12:15:00.336180 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 12:15:00.339359 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 12:15:00.342834 0 11 8 | B1->B0 | 2c2c 3e3d | 0 1 | (0 0) (0 0)
1214 12:15:00.349013 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1215 12:15:00.352681 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 12:15:00.356355 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 12:15:00.363360 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 12:15:00.366266 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 12:15:00.369400 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 12:15:00.376844 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 12:15:00.379162 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1222 12:15:00.383036 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 12:15:00.389124 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 12:15:00.392228 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 12:15:00.395381 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 12:15:00.403061 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 12:15:00.405565 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 12:15:00.409401 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 12:15:00.415944 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 12:15:00.419417 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 12:15:00.422281 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 12:15:00.429764 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 12:15:00.432583 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 12:15:00.435560 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1235 12:15:00.442464 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1236 12:15:00.445323 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1237 12:15:00.448722 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1238 12:15:00.455353 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1239 12:15:00.456025 Total UI for P1: 0, mck2ui 16
1240 12:15:00.461704 best dqsien dly found for B0: ( 0, 14, 6)
1241 12:15:00.465405 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1242 12:15:00.469287 Total UI for P1: 0, mck2ui 16
1243 12:15:00.471934 best dqsien dly found for B1: ( 0, 14, 12)
1244 12:15:00.475517 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1245 12:15:00.478997 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
1246 12:15:00.479461
1247 12:15:00.482108 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1248 12:15:00.485253 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
1249 12:15:00.488957 [Gating] SW calibration Done
1250 12:15:00.489515 ==
1251 12:15:00.491999 Dram Type= 6, Freq= 0, CH_0, rank 1
1252 12:15:00.495445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1253 12:15:00.498116 ==
1254 12:15:00.498645 RX Vref Scan: 0
1255 12:15:00.499019
1256 12:15:00.501646 RX Vref 0 -> 0, step: 1
1257 12:15:00.502194
1258 12:15:00.504714 RX Delay -130 -> 252, step: 16
1259 12:15:00.508143 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1260 12:15:00.511839 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1261 12:15:00.515253 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1262 12:15:00.518647 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1263 12:15:00.525032 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1264 12:15:00.528584 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1265 12:15:00.532076 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1266 12:15:00.534897 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1267 12:15:00.538002 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1268 12:15:00.544766 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1269 12:15:00.548759 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1270 12:15:00.551364 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1271 12:15:00.554720 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1272 12:15:00.557871 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1273 12:15:00.564277 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1274 12:15:00.567766 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1275 12:15:00.568229 ==
1276 12:15:00.572082 Dram Type= 6, Freq= 0, CH_0, rank 1
1277 12:15:00.574761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1278 12:15:00.575362 ==
1279 12:15:00.577824 DQS Delay:
1280 12:15:00.578278 DQS0 = 0, DQS1 = 0
1281 12:15:00.578684 DQM Delay:
1282 12:15:00.581146 DQM0 = 86, DQM1 = 77
1283 12:15:00.581706 DQ Delay:
1284 12:15:00.584224 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1285 12:15:00.587729 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
1286 12:15:00.591791 DQ8 =61, DQ9 =61, DQ10 =85, DQ11 =69
1287 12:15:00.594324 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1288 12:15:00.594874
1289 12:15:00.595239
1290 12:15:00.595574 ==
1291 12:15:00.597532 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 12:15:00.604351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 12:15:00.604806 ==
1294 12:15:00.605163
1295 12:15:00.605526
1296 12:15:00.607135 TX Vref Scan disable
1297 12:15:00.607586 == TX Byte 0 ==
1298 12:15:00.610891 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1299 12:15:00.617309 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1300 12:15:00.617718 == TX Byte 1 ==
1301 12:15:00.620841 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1302 12:15:00.626881 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1303 12:15:00.627171 ==
1304 12:15:00.631645 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 12:15:00.633480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 12:15:00.633779 ==
1307 12:15:00.647235 TX Vref=22, minBit 9, minWin=27, winSum=445
1308 12:15:00.650301 TX Vref=24, minBit 9, minWin=27, winSum=447
1309 12:15:00.653810 TX Vref=26, minBit 3, minWin=27, winSum=448
1310 12:15:00.657103 TX Vref=28, minBit 9, minWin=27, winSum=448
1311 12:15:00.660144 TX Vref=30, minBit 9, minWin=27, winSum=446
1312 12:15:00.667778 TX Vref=32, minBit 9, minWin=27, winSum=448
1313 12:15:00.670026 [TxChooseVref] Worse bit 3, Min win 27, Win sum 448, Final Vref 26
1314 12:15:00.670438
1315 12:15:00.673061 Final TX Range 1 Vref 26
1316 12:15:00.673473
1317 12:15:00.673796 ==
1318 12:15:00.676553 Dram Type= 6, Freq= 0, CH_0, rank 1
1319 12:15:00.679866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1320 12:15:00.683230 ==
1321 12:15:00.683645
1322 12:15:00.684164
1323 12:15:00.684487 TX Vref Scan disable
1324 12:15:00.688139 == TX Byte 0 ==
1325 12:15:00.690283 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1326 12:15:00.693725 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1327 12:15:00.697314 == TX Byte 1 ==
1328 12:15:00.700017 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1329 12:15:00.707516 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1330 12:15:00.707999
1331 12:15:00.708326 [DATLAT]
1332 12:15:00.708634 Freq=800, CH0 RK1
1333 12:15:00.708933
1334 12:15:00.710129 DATLAT Default: 0xa
1335 12:15:00.710541 0, 0xFFFF, sum = 0
1336 12:15:00.713760 1, 0xFFFF, sum = 0
1337 12:15:00.714180 2, 0xFFFF, sum = 0
1338 12:15:00.717032 3, 0xFFFF, sum = 0
1339 12:15:00.719997 4, 0xFFFF, sum = 0
1340 12:15:00.720414 5, 0xFFFF, sum = 0
1341 12:15:00.723665 6, 0xFFFF, sum = 0
1342 12:15:00.724107 7, 0xFFFF, sum = 0
1343 12:15:00.727052 8, 0xFFFF, sum = 0
1344 12:15:00.727577 9, 0x0, sum = 1
1345 12:15:00.730447 10, 0x0, sum = 2
1346 12:15:00.730974 11, 0x0, sum = 3
1347 12:15:00.731311 12, 0x0, sum = 4
1348 12:15:00.733386 best_step = 10
1349 12:15:00.733799
1350 12:15:00.734123 ==
1351 12:15:00.737964 Dram Type= 6, Freq= 0, CH_0, rank 1
1352 12:15:00.740284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1353 12:15:00.740702 ==
1354 12:15:00.743601 RX Vref Scan: 0
1355 12:15:00.744164
1356 12:15:00.744498 RX Vref 0 -> 0, step: 1
1357 12:15:00.747098
1358 12:15:00.747725 RX Delay -111 -> 252, step: 8
1359 12:15:00.754260 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1360 12:15:00.756660 iDelay=209, Bit 1, Center 88 (-31 ~ 208) 240
1361 12:15:00.760020 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1362 12:15:00.763760 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1363 12:15:00.771437 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1364 12:15:00.773180 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1365 12:15:00.776639 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1366 12:15:00.779877 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1367 12:15:00.784348 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1368 12:15:00.789887 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1369 12:15:00.792979 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1370 12:15:00.796808 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1371 12:15:00.800435 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1372 12:15:00.803113 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1373 12:15:00.809603 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1374 12:15:00.813618 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1375 12:15:00.814151 ==
1376 12:15:00.816599 Dram Type= 6, Freq= 0, CH_0, rank 1
1377 12:15:00.820404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1378 12:15:00.820923 ==
1379 12:15:00.823248 DQS Delay:
1380 12:15:00.823657 DQS0 = 0, DQS1 = 0
1381 12:15:00.824026 DQM Delay:
1382 12:15:00.826165 DQM0 = 85, DQM1 = 77
1383 12:15:00.826680 DQ Delay:
1384 12:15:00.829537 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =84
1385 12:15:00.833181 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =92
1386 12:15:00.836567 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =68
1387 12:15:00.839924 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1388 12:15:00.840342
1389 12:15:00.840718
1390 12:15:00.849423 [DQSOSCAuto] RK1, (LSB)MR18= 0x4209, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
1391 12:15:00.852673 CH0 RK1: MR19=606, MR18=4209
1392 12:15:00.855913 CH0_RK1: MR19=0x606, MR18=0x4209, DQSOSC=393, MR23=63, INC=95, DEC=63
1393 12:15:00.860017 [RxdqsGatingPostProcess] freq 800
1394 12:15:00.866054 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1395 12:15:00.869171 Pre-setting of DQS Precalculation
1396 12:15:00.872280 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1397 12:15:00.875414 ==
1398 12:15:00.875923 Dram Type= 6, Freq= 0, CH_1, rank 0
1399 12:15:00.882303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1400 12:15:00.882866 ==
1401 12:15:00.885301 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1402 12:15:00.892027 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1403 12:15:00.902395 [CA 0] Center 36 (6~67) winsize 62
1404 12:15:00.905331 [CA 1] Center 36 (6~67) winsize 62
1405 12:15:00.908632 [CA 2] Center 34 (4~65) winsize 62
1406 12:15:00.912039 [CA 3] Center 34 (3~65) winsize 63
1407 12:15:00.915641 [CA 4] Center 34 (4~65) winsize 62
1408 12:15:00.919023 [CA 5] Center 34 (3~65) winsize 63
1409 12:15:00.919581
1410 12:15:00.921576 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1411 12:15:00.922033
1412 12:15:00.925126 [CATrainingPosCal] consider 1 rank data
1413 12:15:00.928894 u2DelayCellTimex100 = 270/100 ps
1414 12:15:00.932060 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1415 12:15:00.938937 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1416 12:15:00.941895 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1417 12:15:00.945593 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1418 12:15:00.948299 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1419 12:15:00.952408 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1420 12:15:00.952974
1421 12:15:00.955471 CA PerBit enable=1, Macro0, CA PI delay=34
1422 12:15:00.956069
1423 12:15:00.958641 [CBTSetCACLKResult] CA Dly = 34
1424 12:15:00.959102 CS Dly: 5 (0~36)
1425 12:15:00.961728 ==
1426 12:15:00.964687 Dram Type= 6, Freq= 0, CH_1, rank 1
1427 12:15:00.968725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1428 12:15:00.969297 ==
1429 12:15:00.972068 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1430 12:15:00.978526 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1431 12:15:00.988649 [CA 0] Center 36 (6~67) winsize 62
1432 12:15:00.991203 [CA 1] Center 37 (6~68) winsize 63
1433 12:15:00.995115 [CA 2] Center 34 (4~65) winsize 62
1434 12:15:00.998303 [CA 3] Center 34 (4~65) winsize 62
1435 12:15:01.002105 [CA 4] Center 34 (4~65) winsize 62
1436 12:15:01.005286 [CA 5] Center 34 (4~64) winsize 61
1437 12:15:01.005849
1438 12:15:01.008301 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1439 12:15:01.008773
1440 12:15:01.011909 [CATrainingPosCal] consider 2 rank data
1441 12:15:01.014955 u2DelayCellTimex100 = 270/100 ps
1442 12:15:01.018737 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1443 12:15:01.025124 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1444 12:15:01.028413 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1445 12:15:01.030946 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1446 12:15:01.034264 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1447 12:15:01.037737 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1448 12:15:01.038302
1449 12:15:01.041351 CA PerBit enable=1, Macro0, CA PI delay=34
1450 12:15:01.041812
1451 12:15:01.045477 [CBTSetCACLKResult] CA Dly = 34
1452 12:15:01.047893 CS Dly: 6 (0~38)
1453 12:15:01.048492
1454 12:15:01.051609 ----->DramcWriteLeveling(PI) begin...
1455 12:15:01.052228 ==
1456 12:15:01.054500 Dram Type= 6, Freq= 0, CH_1, rank 0
1457 12:15:01.057855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1458 12:15:01.058425 ==
1459 12:15:01.061446 Write leveling (Byte 0): 25 => 25
1460 12:15:01.064414 Write leveling (Byte 1): 31 => 31
1461 12:15:01.067713 DramcWriteLeveling(PI) end<-----
1462 12:15:01.068177
1463 12:15:01.068541 ==
1464 12:15:01.071577 Dram Type= 6, Freq= 0, CH_1, rank 0
1465 12:15:01.074443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1466 12:15:01.075011 ==
1467 12:15:01.078503 [Gating] SW mode calibration
1468 12:15:01.084439 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1469 12:15:01.091732 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1470 12:15:01.094506 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1471 12:15:01.098036 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1472 12:15:01.104565 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 12:15:01.107847 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 12:15:01.111143 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 12:15:01.117422 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 12:15:01.121000 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 12:15:01.124005 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 12:15:01.127414 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 12:15:01.134651 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 12:15:01.138328 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 12:15:01.140997 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 12:15:01.147360 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 12:15:01.151283 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 12:15:01.155153 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 12:15:01.160755 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 12:15:01.164155 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1487 12:15:01.166989 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1488 12:15:01.174121 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 12:15:01.177603 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 12:15:01.180675 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 12:15:01.187154 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 12:15:01.190836 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 12:15:01.194092 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 12:15:01.200222 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 12:15:01.203778 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1496 12:15:01.207366 0 9 8 | B1->B0 | 2c2c 2e2e | 1 1 | (1 1) (1 1)
1497 12:15:01.213369 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1498 12:15:01.217472 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1499 12:15:01.221007 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1500 12:15:01.226703 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1501 12:15:01.230380 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1502 12:15:01.233655 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1503 12:15:01.240114 0 10 4 | B1->B0 | 3333 3030 | 1 0 | (1 1) (0 1)
1504 12:15:01.243816 0 10 8 | B1->B0 | 2929 2929 | 0 0 | (1 1) (0 0)
1505 12:15:01.246922 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 12:15:01.253565 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 12:15:01.257029 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 12:15:01.260605 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 12:15:01.267127 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 12:15:01.270352 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 12:15:01.273552 0 11 4 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
1512 12:15:01.280074 0 11 8 | B1->B0 | 3a3a 4545 | 0 0 | (0 0) (0 0)
1513 12:15:01.283781 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 12:15:01.286535 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 12:15:01.293085 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 12:15:01.297037 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 12:15:01.300137 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 12:15:01.303814 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 12:15:01.309978 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1520 12:15:01.313460 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1521 12:15:01.316732 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 12:15:01.322988 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 12:15:01.326395 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 12:15:01.330174 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 12:15:01.336561 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 12:15:01.339839 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 12:15:01.343169 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 12:15:01.349486 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 12:15:01.353394 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 12:15:01.356622 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 12:15:01.362623 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 12:15:01.366142 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 12:15:01.370006 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 12:15:01.376698 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 12:15:01.379443 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1536 12:15:01.383383 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 12:15:01.385896 Total UI for P1: 0, mck2ui 16
1538 12:15:01.389460 best dqsien dly found for B0: ( 0, 14, 4)
1539 12:15:01.393072 Total UI for P1: 0, mck2ui 16
1540 12:15:01.396840 best dqsien dly found for B1: ( 0, 14, 4)
1541 12:15:01.399642 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1542 12:15:01.402876 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1543 12:15:01.403436
1544 12:15:01.409037 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1545 12:15:01.412226 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1546 12:15:01.412688 [Gating] SW calibration Done
1547 12:15:01.415933 ==
1548 12:15:01.419917 Dram Type= 6, Freq= 0, CH_1, rank 0
1549 12:15:01.422726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1550 12:15:01.423294 ==
1551 12:15:01.423667 RX Vref Scan: 0
1552 12:15:01.424098
1553 12:15:01.426187 RX Vref 0 -> 0, step: 1
1554 12:15:01.426749
1555 12:15:01.429583 RX Delay -130 -> 252, step: 16
1556 12:15:01.432939 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1557 12:15:01.435943 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1558 12:15:01.442296 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1559 12:15:01.445833 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1560 12:15:01.448712 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1561 12:15:01.452579 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1562 12:15:01.455507 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1563 12:15:01.461881 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1564 12:15:01.465350 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1565 12:15:01.468507 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1566 12:15:01.472390 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1567 12:15:01.475581 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1568 12:15:01.482141 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1569 12:15:01.485541 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1570 12:15:01.489100 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1571 12:15:01.492648 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1572 12:15:01.493220 ==
1573 12:15:01.495345 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 12:15:01.501886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 12:15:01.502444 ==
1576 12:15:01.502813 DQS Delay:
1577 12:15:01.505096 DQS0 = 0, DQS1 = 0
1578 12:15:01.505556 DQM Delay:
1579 12:15:01.505923 DQM0 = 88, DQM1 = 78
1580 12:15:01.508317 DQ Delay:
1581 12:15:01.511864 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1582 12:15:01.515102 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1583 12:15:01.519023 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1584 12:15:01.522287 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1585 12:15:01.522850
1586 12:15:01.523214
1587 12:15:01.523551 ==
1588 12:15:01.524813 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 12:15:01.528662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 12:15:01.529231 ==
1591 12:15:01.529600
1592 12:15:01.529943
1593 12:15:01.532067 TX Vref Scan disable
1594 12:15:01.535394 == TX Byte 0 ==
1595 12:15:01.538531 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1596 12:15:01.541613 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1597 12:15:01.545356 == TX Byte 1 ==
1598 12:15:01.548263 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1599 12:15:01.551843 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1600 12:15:01.552425 ==
1601 12:15:01.554889 Dram Type= 6, Freq= 0, CH_1, rank 0
1602 12:15:01.558069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1603 12:15:01.560960 ==
1604 12:15:01.573605 TX Vref=22, minBit 10, minWin=26, winSum=438
1605 12:15:01.576170 TX Vref=24, minBit 10, minWin=26, winSum=442
1606 12:15:01.579924 TX Vref=26, minBit 1, minWin=27, winSum=441
1607 12:15:01.582966 TX Vref=28, minBit 0, minWin=27, winSum=444
1608 12:15:01.586443 TX Vref=30, minBit 1, minWin=27, winSum=447
1609 12:15:01.593140 TX Vref=32, minBit 1, minWin=27, winSum=440
1610 12:15:01.596706 [TxChooseVref] Worse bit 1, Min win 27, Win sum 447, Final Vref 30
1611 12:15:01.597231
1612 12:15:01.599654 Final TX Range 1 Vref 30
1613 12:15:01.600220
1614 12:15:01.600555 ==
1615 12:15:01.603535 Dram Type= 6, Freq= 0, CH_1, rank 0
1616 12:15:01.606822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1617 12:15:01.610463 ==
1618 12:15:01.610982
1619 12:15:01.611315
1620 12:15:01.611630 TX Vref Scan disable
1621 12:15:01.614071 == TX Byte 0 ==
1622 12:15:01.616871 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1623 12:15:01.623874 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1624 12:15:01.624495 == TX Byte 1 ==
1625 12:15:01.627205 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1626 12:15:01.633540 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1627 12:15:01.634063
1628 12:15:01.634396 [DATLAT]
1629 12:15:01.634893 Freq=800, CH1 RK0
1630 12:15:01.635285
1631 12:15:01.637018 DATLAT Default: 0xa
1632 12:15:01.637541 0, 0xFFFF, sum = 0
1633 12:15:01.639766 1, 0xFFFF, sum = 0
1634 12:15:01.640189 2, 0xFFFF, sum = 0
1635 12:15:01.643788 3, 0xFFFF, sum = 0
1636 12:15:01.644316 4, 0xFFFF, sum = 0
1637 12:15:01.646549 5, 0xFFFF, sum = 0
1638 12:15:01.649760 6, 0xFFFF, sum = 0
1639 12:15:01.650259 7, 0xFFFF, sum = 0
1640 12:15:01.653538 8, 0xFFFF, sum = 0
1641 12:15:01.654070 9, 0x0, sum = 1
1642 12:15:01.654418 10, 0x0, sum = 2
1643 12:15:01.656847 11, 0x0, sum = 3
1644 12:15:01.657377 12, 0x0, sum = 4
1645 12:15:01.659838 best_step = 10
1646 12:15:01.660356
1647 12:15:01.660693 ==
1648 12:15:01.663142 Dram Type= 6, Freq= 0, CH_1, rank 0
1649 12:15:01.666733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1650 12:15:01.667324 ==
1651 12:15:01.669615 RX Vref Scan: 1
1652 12:15:01.670032
1653 12:15:01.673098 Set Vref Range= 32 -> 127
1654 12:15:01.673623
1655 12:15:01.673957 RX Vref 32 -> 127, step: 1
1656 12:15:01.674267
1657 12:15:01.676524 RX Delay -95 -> 252, step: 8
1658 12:15:01.676941
1659 12:15:01.680548 Set Vref, RX VrefLevel [Byte0]: 32
1660 12:15:01.682958 [Byte1]: 32
1661 12:15:01.686229
1662 12:15:01.686658 Set Vref, RX VrefLevel [Byte0]: 33
1663 12:15:01.689607 [Byte1]: 33
1664 12:15:01.693895
1665 12:15:01.694415 Set Vref, RX VrefLevel [Byte0]: 34
1666 12:15:01.697591 [Byte1]: 34
1667 12:15:01.701435
1668 12:15:01.701955 Set Vref, RX VrefLevel [Byte0]: 35
1669 12:15:01.705113 [Byte1]: 35
1670 12:15:01.708643
1671 12:15:01.709074 Set Vref, RX VrefLevel [Byte0]: 36
1672 12:15:01.712124 [Byte1]: 36
1673 12:15:01.717226
1674 12:15:01.717746 Set Vref, RX VrefLevel [Byte0]: 37
1675 12:15:01.720475 [Byte1]: 37
1676 12:15:01.724292
1677 12:15:01.724843 Set Vref, RX VrefLevel [Byte0]: 38
1678 12:15:01.727537 [Byte1]: 38
1679 12:15:01.731455
1680 12:15:01.731914 Set Vref, RX VrefLevel [Byte0]: 39
1681 12:15:01.735042 [Byte1]: 39
1682 12:15:01.739017
1683 12:15:01.739438 Set Vref, RX VrefLevel [Byte0]: 40
1684 12:15:01.742561 [Byte1]: 40
1685 12:15:01.747173
1686 12:15:01.747607 Set Vref, RX VrefLevel [Byte0]: 41
1687 12:15:01.749888 [Byte1]: 41
1688 12:15:01.754365
1689 12:15:01.754849 Set Vref, RX VrefLevel [Byte0]: 42
1690 12:15:01.757953 [Byte1]: 42
1691 12:15:01.762251
1692 12:15:01.762759 Set Vref, RX VrefLevel [Byte0]: 43
1693 12:15:01.765747 [Byte1]: 43
1694 12:15:01.770279
1695 12:15:01.770692 Set Vref, RX VrefLevel [Byte0]: 44
1696 12:15:01.772639 [Byte1]: 44
1697 12:15:01.777084
1698 12:15:01.777500 Set Vref, RX VrefLevel [Byte0]: 45
1699 12:15:01.780150 [Byte1]: 45
1700 12:15:01.784619
1701 12:15:01.785036 Set Vref, RX VrefLevel [Byte0]: 46
1702 12:15:01.788002 [Byte1]: 46
1703 12:15:01.792579
1704 12:15:01.792990 Set Vref, RX VrefLevel [Byte0]: 47
1705 12:15:01.795712 [Byte1]: 47
1706 12:15:01.799856
1707 12:15:01.800378 Set Vref, RX VrefLevel [Byte0]: 48
1708 12:15:01.802961 [Byte1]: 48
1709 12:15:01.808069
1710 12:15:01.808579 Set Vref, RX VrefLevel [Byte0]: 49
1711 12:15:01.811377 [Byte1]: 49
1712 12:15:01.815229
1713 12:15:01.815643 Set Vref, RX VrefLevel [Byte0]: 50
1714 12:15:01.818346 [Byte1]: 50
1715 12:15:01.823575
1716 12:15:01.824130 Set Vref, RX VrefLevel [Byte0]: 51
1717 12:15:01.825994 [Byte1]: 51
1718 12:15:01.830465
1719 12:15:01.831010 Set Vref, RX VrefLevel [Byte0]: 52
1720 12:15:01.834034 [Byte1]: 52
1721 12:15:01.837874
1722 12:15:01.838386 Set Vref, RX VrefLevel [Byte0]: 53
1723 12:15:01.841381 [Byte1]: 53
1724 12:15:01.845564
1725 12:15:01.846078 Set Vref, RX VrefLevel [Byte0]: 54
1726 12:15:01.849948 [Byte1]: 54
1727 12:15:01.853634
1728 12:15:01.854149 Set Vref, RX VrefLevel [Byte0]: 55
1729 12:15:01.856853 [Byte1]: 55
1730 12:15:01.860814
1731 12:15:01.861372 Set Vref, RX VrefLevel [Byte0]: 56
1732 12:15:01.864873 [Byte1]: 56
1733 12:15:01.869143
1734 12:15:01.869711 Set Vref, RX VrefLevel [Byte0]: 57
1735 12:15:01.871976 [Byte1]: 57
1736 12:15:01.876142
1737 12:15:01.876602 Set Vref, RX VrefLevel [Byte0]: 58
1738 12:15:01.879385 [Byte1]: 58
1739 12:15:01.884089
1740 12:15:01.884650 Set Vref, RX VrefLevel [Byte0]: 59
1741 12:15:01.886967 [Byte1]: 59
1742 12:15:01.891317
1743 12:15:01.891925 Set Vref, RX VrefLevel [Byte0]: 60
1744 12:15:01.895047 [Byte1]: 60
1745 12:15:01.898759
1746 12:15:01.899314 Set Vref, RX VrefLevel [Byte0]: 61
1747 12:15:01.902046 [Byte1]: 61
1748 12:15:01.906407
1749 12:15:01.906989 Set Vref, RX VrefLevel [Byte0]: 62
1750 12:15:01.909621 [Byte1]: 62
1751 12:15:01.914361
1752 12:15:01.914926 Set Vref, RX VrefLevel [Byte0]: 63
1753 12:15:01.917609 [Byte1]: 63
1754 12:15:01.922039
1755 12:15:01.922597 Set Vref, RX VrefLevel [Byte0]: 64
1756 12:15:01.925442 [Byte1]: 64
1757 12:15:01.929031
1758 12:15:01.929594 Set Vref, RX VrefLevel [Byte0]: 65
1759 12:15:01.932435 [Byte1]: 65
1760 12:15:01.938022
1761 12:15:01.938597 Set Vref, RX VrefLevel [Byte0]: 66
1762 12:15:01.939955 [Byte1]: 66
1763 12:15:01.944341
1764 12:15:01.944901 Set Vref, RX VrefLevel [Byte0]: 67
1765 12:15:01.947359 [Byte1]: 67
1766 12:15:01.952059
1767 12:15:01.955111 Set Vref, RX VrefLevel [Byte0]: 68
1768 12:15:01.955766 [Byte1]: 68
1769 12:15:01.959827
1770 12:15:01.960380 Set Vref, RX VrefLevel [Byte0]: 69
1771 12:15:01.962764 [Byte1]: 69
1772 12:15:01.967152
1773 12:15:01.967611 Set Vref, RX VrefLevel [Byte0]: 70
1774 12:15:01.970516 [Byte1]: 70
1775 12:15:01.974813
1776 12:15:01.975382 Set Vref, RX VrefLevel [Byte0]: 71
1777 12:15:01.978249 [Byte1]: 71
1778 12:15:01.982191
1779 12:15:01.982647 Set Vref, RX VrefLevel [Byte0]: 72
1780 12:15:01.985546 [Byte1]: 72
1781 12:15:01.990183
1782 12:15:01.990747 Set Vref, RX VrefLevel [Byte0]: 73
1783 12:15:01.993621 [Byte1]: 73
1784 12:15:01.997587
1785 12:15:01.998146 Set Vref, RX VrefLevel [Byte0]: 74
1786 12:15:02.000799 [Byte1]: 74
1787 12:15:02.005319
1788 12:15:02.005773 Final RX Vref Byte 0 = 56 to rank0
1789 12:15:02.008636 Final RX Vref Byte 1 = 62 to rank0
1790 12:15:02.012258 Final RX Vref Byte 0 = 56 to rank1
1791 12:15:02.015397 Final RX Vref Byte 1 = 62 to rank1==
1792 12:15:02.019394 Dram Type= 6, Freq= 0, CH_1, rank 0
1793 12:15:02.025651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1794 12:15:02.026218 ==
1795 12:15:02.026589 DQS Delay:
1796 12:15:02.026931 DQS0 = 0, DQS1 = 0
1797 12:15:02.028196 DQM Delay:
1798 12:15:02.028655 DQM0 = 87, DQM1 = 79
1799 12:15:02.032387 DQ Delay:
1800 12:15:02.035241 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1801 12:15:02.038692 DQ4 =84, DQ5 =100, DQ6 =100, DQ7 =80
1802 12:15:02.041379 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
1803 12:15:02.045031 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1804 12:15:02.045595
1805 12:15:02.045962
1806 12:15:02.051541 [DQSOSCAuto] RK0, (LSB)MR18= 0x301d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1807 12:15:02.054995 CH1 RK0: MR19=606, MR18=301D
1808 12:15:02.061507 CH1_RK0: MR19=0x606, MR18=0x301D, DQSOSC=397, MR23=63, INC=93, DEC=62
1809 12:15:02.061972
1810 12:15:02.065495 ----->DramcWriteLeveling(PI) begin...
1811 12:15:02.066067 ==
1812 12:15:02.067985 Dram Type= 6, Freq= 0, CH_1, rank 1
1813 12:15:02.071434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 12:15:02.072005 ==
1815 12:15:02.075005 Write leveling (Byte 0): 29 => 29
1816 12:15:02.078777 Write leveling (Byte 1): 30 => 30
1817 12:15:02.081059 DramcWriteLeveling(PI) end<-----
1818 12:15:02.081523
1819 12:15:02.081885 ==
1820 12:15:02.084393 Dram Type= 6, Freq= 0, CH_1, rank 1
1821 12:15:02.088720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1822 12:15:02.089281 ==
1823 12:15:02.091617 [Gating] SW mode calibration
1824 12:15:02.097667 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1825 12:15:02.104169 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1826 12:15:02.108310 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1827 12:15:02.115159 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1828 12:15:02.118804 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1829 12:15:02.120932 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 12:15:02.127971 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 12:15:02.131243 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 12:15:02.134369 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 12:15:02.141258 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 12:15:02.144241 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 12:15:02.148062 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 12:15:02.154749 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 12:15:02.157669 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 12:15:02.160706 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 12:15:02.164675 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 12:15:02.170951 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 12:15:02.174467 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 12:15:02.177821 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 12:15:02.184360 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1844 12:15:02.187958 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 12:15:02.191540 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 12:15:02.197554 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 12:15:02.201337 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 12:15:02.203883 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 12:15:02.210400 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 12:15:02.214269 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 12:15:02.216906 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 12:15:02.223894 0 9 8 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
1853 12:15:02.226914 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 12:15:02.230891 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 12:15:02.236968 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 12:15:02.240586 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1857 12:15:02.243432 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1858 12:15:02.251176 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1859 12:15:02.254314 0 10 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1860 12:15:02.256996 0 10 8 | B1->B0 | 2c2c 2e2e | 0 0 | (0 0) (0 0)
1861 12:15:02.263526 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 12:15:02.267208 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 12:15:02.270162 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 12:15:02.276970 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 12:15:02.280390 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 12:15:02.283300 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 12:15:02.290742 0 11 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1868 12:15:02.293101 0 11 8 | B1->B0 | 3c3c 3838 | 0 0 | (0 0) (0 0)
1869 12:15:02.296184 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 12:15:02.303054 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 12:15:02.306990 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 12:15:02.309546 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 12:15:02.316686 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1874 12:15:02.320142 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 12:15:02.323377 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1876 12:15:02.330513 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1877 12:15:02.333317 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 12:15:02.336266 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 12:15:02.342689 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 12:15:02.346570 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 12:15:02.349742 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 12:15:02.356248 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 12:15:02.359654 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 12:15:02.363253 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 12:15:02.369812 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 12:15:02.372431 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 12:15:02.376065 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 12:15:02.382799 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 12:15:02.386420 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 12:15:02.389282 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 12:15:02.396212 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 12:15:02.399843 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 12:15:02.402429 Total UI for P1: 0, mck2ui 16
1894 12:15:02.405798 best dqsien dly found for B0: ( 0, 14, 6)
1895 12:15:02.408883 Total UI for P1: 0, mck2ui 16
1896 12:15:02.412418 best dqsien dly found for B1: ( 0, 14, 6)
1897 12:15:02.416339 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1898 12:15:02.419604 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1899 12:15:02.420204
1900 12:15:02.422360 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1901 12:15:02.426070 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1902 12:15:02.428969 [Gating] SW calibration Done
1903 12:15:02.429533 ==
1904 12:15:02.432496 Dram Type= 6, Freq= 0, CH_1, rank 1
1905 12:15:02.436239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1906 12:15:02.436815 ==
1907 12:15:02.439357 RX Vref Scan: 0
1908 12:15:02.439852
1909 12:15:02.440226 RX Vref 0 -> 0, step: 1
1910 12:15:02.442230
1911 12:15:02.442691 RX Delay -130 -> 252, step: 16
1912 12:15:02.449197 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1913 12:15:02.452278 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1914 12:15:02.455593 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1915 12:15:02.459442 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1916 12:15:02.462658 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1917 12:15:02.468983 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1918 12:15:02.472625 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1919 12:15:02.475047 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1920 12:15:02.478905 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1921 12:15:02.482583 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1922 12:15:02.488515 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1923 12:15:02.491793 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1924 12:15:02.495004 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1925 12:15:02.498383 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1926 12:15:02.504916 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1927 12:15:02.508475 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1928 12:15:02.508939 ==
1929 12:15:02.511891 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 12:15:02.515410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 12:15:02.516104 ==
1932 12:15:02.518161 DQS Delay:
1933 12:15:02.518623 DQS0 = 0, DQS1 = 0
1934 12:15:02.518986 DQM Delay:
1935 12:15:02.522073 DQM0 = 87, DQM1 = 78
1936 12:15:02.522631 DQ Delay:
1937 12:15:02.524875 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1938 12:15:02.529042 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1939 12:15:02.531501 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1940 12:15:02.535436 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1941 12:15:02.536037
1942 12:15:02.536407
1943 12:15:02.536754 ==
1944 12:15:02.538632 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 12:15:02.545666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 12:15:02.546233 ==
1947 12:15:02.546704
1948 12:15:02.547072
1949 12:15:02.547544 TX Vref Scan disable
1950 12:15:02.548414 == TX Byte 0 ==
1951 12:15:02.551935 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1952 12:15:02.555089 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1953 12:15:02.558775 == TX Byte 1 ==
1954 12:15:02.561829 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1955 12:15:02.568358 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1956 12:15:02.568906 ==
1957 12:15:02.572242 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 12:15:02.575220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 12:15:02.575753 ==
1960 12:15:02.587662 TX Vref=22, minBit 8, minWin=27, winSum=445
1961 12:15:02.591050 TX Vref=24, minBit 10, minWin=27, winSum=449
1962 12:15:02.594457 TX Vref=26, minBit 8, minWin=27, winSum=452
1963 12:15:02.597749 TX Vref=28, minBit 13, minWin=27, winSum=451
1964 12:15:02.601693 TX Vref=30, minBit 13, minWin=27, winSum=452
1965 12:15:02.607907 TX Vref=32, minBit 8, minWin=27, winSum=447
1966 12:15:02.610665 [TxChooseVref] Worse bit 8, Min win 27, Win sum 452, Final Vref 26
1967 12:15:02.611148
1968 12:15:02.614279 Final TX Range 1 Vref 26
1969 12:15:02.614847
1970 12:15:02.615210 ==
1971 12:15:02.617974 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 12:15:02.620744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 12:15:02.624166 ==
1974 12:15:02.624626
1975 12:15:02.624989
1976 12:15:02.625324 TX Vref Scan disable
1977 12:15:02.627624 == TX Byte 0 ==
1978 12:15:02.630936 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1979 12:15:02.634966 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1980 12:15:02.637396 == TX Byte 1 ==
1981 12:15:02.640690 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1982 12:15:02.647392 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1983 12:15:02.647987
1984 12:15:02.648356 [DATLAT]
1985 12:15:02.648698 Freq=800, CH1 RK1
1986 12:15:02.649027
1987 12:15:02.650783 DATLAT Default: 0xa
1988 12:15:02.651242 0, 0xFFFF, sum = 0
1989 12:15:02.654460 1, 0xFFFF, sum = 0
1990 12:15:02.657016 2, 0xFFFF, sum = 0
1991 12:15:02.657487 3, 0xFFFF, sum = 0
1992 12:15:02.660934 4, 0xFFFF, sum = 0
1993 12:15:02.661507 5, 0xFFFF, sum = 0
1994 12:15:02.664061 6, 0xFFFF, sum = 0
1995 12:15:02.664528 7, 0xFFFF, sum = 0
1996 12:15:02.667539 8, 0xFFFF, sum = 0
1997 12:15:02.668134 9, 0x0, sum = 1
1998 12:15:02.671046 10, 0x0, sum = 2
1999 12:15:02.671614 11, 0x0, sum = 3
2000 12:15:02.672241 12, 0x0, sum = 4
2001 12:15:02.674116 best_step = 10
2002 12:15:02.674790
2003 12:15:02.675189 ==
2004 12:15:02.677715 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 12:15:02.680075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 12:15:02.680540 ==
2007 12:15:02.684066 RX Vref Scan: 0
2008 12:15:02.684625
2009 12:15:02.687072 RX Vref 0 -> 0, step: 1
2010 12:15:02.687526
2011 12:15:02.687934 RX Delay -95 -> 252, step: 8
2012 12:15:02.694443 iDelay=217, Bit 0, Center 96 (-15 ~ 208) 224
2013 12:15:02.697815 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2014 12:15:02.702099 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2015 12:15:02.704478 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2016 12:15:02.707476 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2017 12:15:02.714686 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2018 12:15:02.717444 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2019 12:15:02.720656 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2020 12:15:02.724499 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2021 12:15:02.727537 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2022 12:15:02.734689 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2023 12:15:02.737301 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2024 12:15:02.741067 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2025 12:15:02.744525 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2026 12:15:02.750775 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2027 12:15:02.754131 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2028 12:15:02.754742 ==
2029 12:15:02.757778 Dram Type= 6, Freq= 0, CH_1, rank 1
2030 12:15:02.760737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2031 12:15:02.761300 ==
2032 12:15:02.764624 DQS Delay:
2033 12:15:02.765182 DQS0 = 0, DQS1 = 0
2034 12:15:02.765548 DQM Delay:
2035 12:15:02.766875 DQM0 = 87, DQM1 = 79
2036 12:15:02.767330 DQ Delay:
2037 12:15:02.770559 DQ0 =96, DQ1 =80, DQ2 =76, DQ3 =84
2038 12:15:02.773654 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2039 12:15:02.777790 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
2040 12:15:02.781161 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2041 12:15:02.781719
2042 12:15:02.782081
2043 12:15:02.790693 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2044 12:15:02.791272 CH1 RK1: MR19=606, MR18=1A13
2045 12:15:02.797107 CH1_RK1: MR19=0x606, MR18=0x1A13, DQSOSC=403, MR23=63, INC=90, DEC=60
2046 12:15:02.800611 [RxdqsGatingPostProcess] freq 800
2047 12:15:02.807214 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2048 12:15:02.810616 Pre-setting of DQS Precalculation
2049 12:15:02.813649 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2050 12:15:02.821638 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2051 12:15:02.830176 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2052 12:15:02.830659
2053 12:15:02.831036
2054 12:15:02.833536 [Calibration Summary] 1600 Mbps
2055 12:15:02.834095 CH 0, Rank 0
2056 12:15:02.837107 SW Impedance : PASS
2057 12:15:02.837565 DUTY Scan : NO K
2058 12:15:02.839951 ZQ Calibration : PASS
2059 12:15:02.843341 Jitter Meter : NO K
2060 12:15:02.843852 CBT Training : PASS
2061 12:15:02.846407 Write leveling : PASS
2062 12:15:02.849695 RX DQS gating : PASS
2063 12:15:02.850151 RX DQ/DQS(RDDQC) : PASS
2064 12:15:02.853748 TX DQ/DQS : PASS
2065 12:15:02.858076 RX DATLAT : PASS
2066 12:15:02.858870 RX DQ/DQS(Engine): PASS
2067 12:15:02.860385 TX OE : NO K
2068 12:15:02.860845 All Pass.
2069 12:15:02.861209
2070 12:15:02.863151 CH 0, Rank 1
2071 12:15:02.863607 SW Impedance : PASS
2072 12:15:02.866478 DUTY Scan : NO K
2073 12:15:02.866960 ZQ Calibration : PASS
2074 12:15:02.869910 Jitter Meter : NO K
2075 12:15:02.873553 CBT Training : PASS
2076 12:15:02.874069 Write leveling : PASS
2077 12:15:02.876272 RX DQS gating : PASS
2078 12:15:02.879331 RX DQ/DQS(RDDQC) : PASS
2079 12:15:02.879805 TX DQ/DQS : PASS
2080 12:15:02.883391 RX DATLAT : PASS
2081 12:15:02.886291 RX DQ/DQS(Engine): PASS
2082 12:15:02.886752 TX OE : NO K
2083 12:15:02.889383 All Pass.
2084 12:15:02.889799
2085 12:15:02.890131 CH 1, Rank 0
2086 12:15:02.892967 SW Impedance : PASS
2087 12:15:02.893385 DUTY Scan : NO K
2088 12:15:02.896161 ZQ Calibration : PASS
2089 12:15:02.899940 Jitter Meter : NO K
2090 12:15:02.900358 CBT Training : PASS
2091 12:15:02.902543 Write leveling : PASS
2092 12:15:02.906964 RX DQS gating : PASS
2093 12:15:02.907383 RX DQ/DQS(RDDQC) : PASS
2094 12:15:02.909248 TX DQ/DQS : PASS
2095 12:15:02.912653 RX DATLAT : PASS
2096 12:15:02.913070 RX DQ/DQS(Engine): PASS
2097 12:15:02.916251 TX OE : NO K
2098 12:15:02.916669 All Pass.
2099 12:15:02.916999
2100 12:15:02.918978 CH 1, Rank 1
2101 12:15:02.919394 SW Impedance : PASS
2102 12:15:02.923834 DUTY Scan : NO K
2103 12:15:02.924355 ZQ Calibration : PASS
2104 12:15:02.925947 Jitter Meter : NO K
2105 12:15:02.930097 CBT Training : PASS
2106 12:15:02.930630 Write leveling : PASS
2107 12:15:02.933319 RX DQS gating : PASS
2108 12:15:02.935717 RX DQ/DQS(RDDQC) : PASS
2109 12:15:02.936161 TX DQ/DQS : PASS
2110 12:15:02.939558 RX DATLAT : PASS
2111 12:15:02.942755 RX DQ/DQS(Engine): PASS
2112 12:15:02.943229 TX OE : NO K
2113 12:15:02.945690 All Pass.
2114 12:15:02.946213
2115 12:15:02.946583 DramC Write-DBI off
2116 12:15:02.948754 PER_BANK_REFRESH: Hybrid Mode
2117 12:15:02.952628 TX_TRACKING: ON
2118 12:15:02.955539 [GetDramInforAfterCalByMRR] Vendor 6.
2119 12:15:02.959285 [GetDramInforAfterCalByMRR] Revision 606.
2120 12:15:02.962939 [GetDramInforAfterCalByMRR] Revision 2 0.
2121 12:15:02.963504 MR0 0x3b3b
2122 12:15:02.963947 MR8 0x5151
2123 12:15:02.969379 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2124 12:15:02.969945
2125 12:15:02.970315 MR0 0x3b3b
2126 12:15:02.970660 MR8 0x5151
2127 12:15:02.972624 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2128 12:15:02.973093
2129 12:15:02.982826 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2130 12:15:02.985687 [FAST_K] Save calibration result to emmc
2131 12:15:02.988958 [FAST_K] Save calibration result to emmc
2132 12:15:02.992092 dram_init: config_dvfs: 1
2133 12:15:02.996162 dramc_set_vcore_voltage set vcore to 662500
2134 12:15:02.999301 Read voltage for 1200, 2
2135 12:15:02.999898 Vio18 = 0
2136 12:15:03.000265 Vcore = 662500
2137 12:15:03.003236 Vdram = 0
2138 12:15:03.004001 Vddq = 0
2139 12:15:03.004377 Vmddr = 0
2140 12:15:03.008616 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2141 12:15:03.012049 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2142 12:15:03.015402 MEM_TYPE=3, freq_sel=15
2143 12:15:03.019052 sv_algorithm_assistance_LP4_1600
2144 12:15:03.021776 ============ PULL DRAM RESETB DOWN ============
2145 12:15:03.028673 ========== PULL DRAM RESETB DOWN end =========
2146 12:15:03.032164 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2147 12:15:03.035313 ===================================
2148 12:15:03.038837 LPDDR4 DRAM CONFIGURATION
2149 12:15:03.042014 ===================================
2150 12:15:03.042509 EX_ROW_EN[0] = 0x0
2151 12:15:03.045293 EX_ROW_EN[1] = 0x0
2152 12:15:03.045709 LP4Y_EN = 0x0
2153 12:15:03.048818 WORK_FSP = 0x0
2154 12:15:03.049233 WL = 0x4
2155 12:15:03.051847 RL = 0x4
2156 12:15:03.052295 BL = 0x2
2157 12:15:03.054990 RPST = 0x0
2158 12:15:03.055437 RD_PRE = 0x0
2159 12:15:03.059144 WR_PRE = 0x1
2160 12:15:03.059559 WR_PST = 0x0
2161 12:15:03.062250 DBI_WR = 0x0
2162 12:15:03.062666 DBI_RD = 0x0
2163 12:15:03.065953 OTF = 0x1
2164 12:15:03.068578 ===================================
2165 12:15:03.071724 ===================================
2166 12:15:03.072170 ANA top config
2167 12:15:03.075159 ===================================
2168 12:15:03.078856 DLL_ASYNC_EN = 0
2169 12:15:03.081673 ALL_SLAVE_EN = 0
2170 12:15:03.084763 NEW_RANK_MODE = 1
2171 12:15:03.088617 DLL_IDLE_MODE = 1
2172 12:15:03.089036 LP45_APHY_COMB_EN = 1
2173 12:15:03.091826 TX_ODT_DIS = 1
2174 12:15:03.094711 NEW_8X_MODE = 1
2175 12:15:03.097998 ===================================
2176 12:15:03.102211 ===================================
2177 12:15:03.105517 data_rate = 2400
2178 12:15:03.108008 CKR = 1
2179 12:15:03.108453 DQ_P2S_RATIO = 8
2180 12:15:03.111187 ===================================
2181 12:15:03.114877 CA_P2S_RATIO = 8
2182 12:15:03.118416 DQ_CA_OPEN = 0
2183 12:15:03.121563 DQ_SEMI_OPEN = 0
2184 12:15:03.124638 CA_SEMI_OPEN = 0
2185 12:15:03.127806 CA_FULL_RATE = 0
2186 12:15:03.128228 DQ_CKDIV4_EN = 0
2187 12:15:03.131444 CA_CKDIV4_EN = 0
2188 12:15:03.135236 CA_PREDIV_EN = 0
2189 12:15:03.138015 PH8_DLY = 17
2190 12:15:03.141453 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2191 12:15:03.145064 DQ_AAMCK_DIV = 4
2192 12:15:03.145482 CA_AAMCK_DIV = 4
2193 12:15:03.147807 CA_ADMCK_DIV = 4
2194 12:15:03.151040 DQ_TRACK_CA_EN = 0
2195 12:15:03.154137 CA_PICK = 1200
2196 12:15:03.158416 CA_MCKIO = 1200
2197 12:15:03.161330 MCKIO_SEMI = 0
2198 12:15:03.164815 PLL_FREQ = 2366
2199 12:15:03.168491 DQ_UI_PI_RATIO = 32
2200 12:15:03.168954 CA_UI_PI_RATIO = 0
2201 12:15:03.171250 ===================================
2202 12:15:03.174205 ===================================
2203 12:15:03.177630 memory_type:LPDDR4
2204 12:15:03.180921 GP_NUM : 10
2205 12:15:03.181381 SRAM_EN : 1
2206 12:15:03.184201 MD32_EN : 0
2207 12:15:03.187494 ===================================
2208 12:15:03.191784 [ANA_INIT] >>>>>>>>>>>>>>
2209 12:15:03.195000 <<<<<< [CONFIGURE PHASE]: ANA_TX
2210 12:15:03.197951 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2211 12:15:03.201096 ===================================
2212 12:15:03.201517 data_rate = 2400,PCW = 0X5b00
2213 12:15:03.203965 ===================================
2214 12:15:03.207649 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2215 12:15:03.214096 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2216 12:15:03.220717 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2217 12:15:03.223945 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2218 12:15:03.227193 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2219 12:15:03.230489 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2220 12:15:03.233717 [ANA_INIT] flow start
2221 12:15:03.237070 [ANA_INIT] PLL >>>>>>>>
2222 12:15:03.237629 [ANA_INIT] PLL <<<<<<<<
2223 12:15:03.240204 [ANA_INIT] MIDPI >>>>>>>>
2224 12:15:03.243663 [ANA_INIT] MIDPI <<<<<<<<
2225 12:15:03.244347 [ANA_INIT] DLL >>>>>>>>
2226 12:15:03.246905 [ANA_INIT] DLL <<<<<<<<
2227 12:15:03.250669 [ANA_INIT] flow end
2228 12:15:03.253742 ============ LP4 DIFF to SE enter ============
2229 12:15:03.257332 ============ LP4 DIFF to SE exit ============
2230 12:15:03.260642 [ANA_INIT] <<<<<<<<<<<<<
2231 12:15:03.264284 [Flow] Enable top DCM control >>>>>
2232 12:15:03.267627 [Flow] Enable top DCM control <<<<<
2233 12:15:03.270482 Enable DLL master slave shuffle
2234 12:15:03.273445 ==============================================================
2235 12:15:03.276777 Gating Mode config
2236 12:15:03.283857 ==============================================================
2237 12:15:03.284450 Config description:
2238 12:15:03.293143 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2239 12:15:03.300117 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2240 12:15:03.303545 SELPH_MODE 0: By rank 1: By Phase
2241 12:15:03.310008 ==============================================================
2242 12:15:03.313124 GAT_TRACK_EN = 1
2243 12:15:03.316584 RX_GATING_MODE = 2
2244 12:15:03.319961 RX_GATING_TRACK_MODE = 2
2245 12:15:03.323002 SELPH_MODE = 1
2246 12:15:03.326247 PICG_EARLY_EN = 1
2247 12:15:03.330629 VALID_LAT_VALUE = 1
2248 12:15:03.333098 ==============================================================
2249 12:15:03.337149 Enter into Gating configuration >>>>
2250 12:15:03.339696 Exit from Gating configuration <<<<
2251 12:15:03.343519 Enter into DVFS_PRE_config >>>>>
2252 12:15:03.356288 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2253 12:15:03.359719 Exit from DVFS_PRE_config <<<<<
2254 12:15:03.360274 Enter into PICG configuration >>>>
2255 12:15:03.363545 Exit from PICG configuration <<<<
2256 12:15:03.366487 [RX_INPUT] configuration >>>>>
2257 12:15:03.369640 [RX_INPUT] configuration <<<<<
2258 12:15:03.377038 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2259 12:15:03.379525 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2260 12:15:03.385742 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2261 12:15:03.393039 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2262 12:15:03.399259 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2263 12:15:03.406252 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2264 12:15:03.409214 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2265 12:15:03.412564 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2266 12:15:03.415979 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2267 12:15:03.422547 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2268 12:15:03.426074 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2269 12:15:03.429242 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2270 12:15:03.432646 ===================================
2271 12:15:03.436055 LPDDR4 DRAM CONFIGURATION
2272 12:15:03.439103 ===================================
2273 12:15:03.442440 EX_ROW_EN[0] = 0x0
2274 12:15:03.442995 EX_ROW_EN[1] = 0x0
2275 12:15:03.445778 LP4Y_EN = 0x0
2276 12:15:03.446234 WORK_FSP = 0x0
2277 12:15:03.448926 WL = 0x4
2278 12:15:03.449385 RL = 0x4
2279 12:15:03.452564 BL = 0x2
2280 12:15:03.453123 RPST = 0x0
2281 12:15:03.455831 RD_PRE = 0x0
2282 12:15:03.456388 WR_PRE = 0x1
2283 12:15:03.459149 WR_PST = 0x0
2284 12:15:03.459775 DBI_WR = 0x0
2285 12:15:03.462654 DBI_RD = 0x0
2286 12:15:03.463209 OTF = 0x1
2287 12:15:03.465708 ===================================
2288 12:15:03.472520 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2289 12:15:03.476093 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2290 12:15:03.478707 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2291 12:15:03.482502 ===================================
2292 12:15:03.485262 LPDDR4 DRAM CONFIGURATION
2293 12:15:03.489354 ===================================
2294 12:15:03.492388 EX_ROW_EN[0] = 0x10
2295 12:15:03.492841 EX_ROW_EN[1] = 0x0
2296 12:15:03.495801 LP4Y_EN = 0x0
2297 12:15:03.496251 WORK_FSP = 0x0
2298 12:15:03.499277 WL = 0x4
2299 12:15:03.499775 RL = 0x4
2300 12:15:03.501842 BL = 0x2
2301 12:15:03.502250 RPST = 0x0
2302 12:15:03.505415 RD_PRE = 0x0
2303 12:15:03.505868 WR_PRE = 0x1
2304 12:15:03.509339 WR_PST = 0x0
2305 12:15:03.509752 DBI_WR = 0x0
2306 12:15:03.511824 DBI_RD = 0x0
2307 12:15:03.512313 OTF = 0x1
2308 12:15:03.515665 ===================================
2309 12:15:03.522602 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2310 12:15:03.523121 ==
2311 12:15:03.525040 Dram Type= 6, Freq= 0, CH_0, rank 0
2312 12:15:03.528738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2313 12:15:03.532137 ==
2314 12:15:03.532644 [Duty_Offset_Calibration]
2315 12:15:03.535562 B0:1 B1:-1 CA:0
2316 12:15:03.536118
2317 12:15:03.539009 [DutyScan_Calibration_Flow] k_type=0
2318 12:15:03.546967
2319 12:15:03.547458 ==CLK 0==
2320 12:15:03.550740 Final CLK duty delay cell = 0
2321 12:15:03.554419 [0] MAX Duty = 5094%(X100), DQS PI = 16
2322 12:15:03.557624 [0] MIN Duty = 4875%(X100), DQS PI = 8
2323 12:15:03.558138 [0] AVG Duty = 4984%(X100)
2324 12:15:03.560906
2325 12:15:03.561422 CH0 CLK Duty spec in!! Max-Min= 219%
2326 12:15:03.568638 [DutyScan_Calibration_Flow] ====Done====
2327 12:15:03.569151
2328 12:15:03.571099 [DutyScan_Calibration_Flow] k_type=1
2329 12:15:03.585598
2330 12:15:03.586144 ==DQS 0 ==
2331 12:15:03.588912 Final DQS duty delay cell = -4
2332 12:15:03.592416 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2333 12:15:03.595661 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2334 12:15:03.599210 [-4] AVG Duty = 4968%(X100)
2335 12:15:03.599822
2336 12:15:03.600200 ==DQS 1 ==
2337 12:15:03.602351 Final DQS duty delay cell = 0
2338 12:15:03.606142 [0] MAX Duty = 5124%(X100), DQS PI = 6
2339 12:15:03.609232 [0] MIN Duty = 5000%(X100), DQS PI = 24
2340 12:15:03.612946 [0] AVG Duty = 5062%(X100)
2341 12:15:03.613450
2342 12:15:03.615590 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2343 12:15:03.616097
2344 12:15:03.619180 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2345 12:15:03.622523 [DutyScan_Calibration_Flow] ====Done====
2346 12:15:03.623083
2347 12:15:03.625966 [DutyScan_Calibration_Flow] k_type=3
2348 12:15:03.644160
2349 12:15:03.644717 ==DQM 0 ==
2350 12:15:03.646799 Final DQM duty delay cell = 0
2351 12:15:03.649963 [0] MAX Duty = 5062%(X100), DQS PI = 24
2352 12:15:03.654091 [0] MIN Duty = 4875%(X100), DQS PI = 8
2353 12:15:03.654718 [0] AVG Duty = 4968%(X100)
2354 12:15:03.657029
2355 12:15:03.657579 ==DQM 1 ==
2356 12:15:03.660404 Final DQM duty delay cell = 4
2357 12:15:03.663899 [4] MAX Duty = 5187%(X100), DQS PI = 14
2358 12:15:03.666950 [4] MIN Duty = 5000%(X100), DQS PI = 24
2359 12:15:03.667503 [4] AVG Duty = 5093%(X100)
2360 12:15:03.669994
2361 12:15:03.673668 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2362 12:15:03.674220
2363 12:15:03.677215 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2364 12:15:03.680773 [DutyScan_Calibration_Flow] ====Done====
2365 12:15:03.681304
2366 12:15:03.683888 [DutyScan_Calibration_Flow] k_type=2
2367 12:15:03.698666
2368 12:15:03.699222 ==DQ 0 ==
2369 12:15:03.701994 Final DQ duty delay cell = -4
2370 12:15:03.705349 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2371 12:15:03.708207 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2372 12:15:03.711817 [-4] AVG Duty = 4969%(X100)
2373 12:15:03.712368
2374 12:15:03.712808 ==DQ 1 ==
2375 12:15:03.714456 Final DQ duty delay cell = -4
2376 12:15:03.718108 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2377 12:15:03.721407 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2378 12:15:03.724849 [-4] AVG Duty = 4938%(X100)
2379 12:15:03.725393
2380 12:15:03.727617 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2381 12:15:03.728129
2382 12:15:03.731106 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2383 12:15:03.735839 [DutyScan_Calibration_Flow] ====Done====
2384 12:15:03.736401 ==
2385 12:15:03.738223 Dram Type= 6, Freq= 0, CH_1, rank 0
2386 12:15:03.741640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2387 12:15:03.742214 ==
2388 12:15:03.744538 [Duty_Offset_Calibration]
2389 12:15:03.744994 B0:-1 B1:1 CA:1
2390 12:15:03.748188
2391 12:15:03.751084 [DutyScan_Calibration_Flow] k_type=0
2392 12:15:03.759080
2393 12:15:03.759731 ==CLK 0==
2394 12:15:03.762128 Final CLK duty delay cell = 0
2395 12:15:03.765290 [0] MAX Duty = 5156%(X100), DQS PI = 20
2396 12:15:03.768618 [0] MIN Duty = 4969%(X100), DQS PI = 60
2397 12:15:03.769109 [0] AVG Duty = 5062%(X100)
2398 12:15:03.772447
2399 12:15:03.775904 CH1 CLK Duty spec in!! Max-Min= 187%
2400 12:15:03.778963 [DutyScan_Calibration_Flow] ====Done====
2401 12:15:03.779447
2402 12:15:03.782406 [DutyScan_Calibration_Flow] k_type=1
2403 12:15:03.798187
2404 12:15:03.798598 ==DQS 0 ==
2405 12:15:03.801845 Final DQS duty delay cell = 0
2406 12:15:03.804825 [0] MAX Duty = 5125%(X100), DQS PI = 16
2407 12:15:03.808532 [0] MIN Duty = 4907%(X100), DQS PI = 6
2408 12:15:03.808952 [0] AVG Duty = 5016%(X100)
2409 12:15:03.811836
2410 12:15:03.812307 ==DQS 1 ==
2411 12:15:03.814919 Final DQS duty delay cell = 0
2412 12:15:03.818069 [0] MAX Duty = 5062%(X100), DQS PI = 8
2413 12:15:03.821379 [0] MIN Duty = 4969%(X100), DQS PI = 56
2414 12:15:03.824673 [0] AVG Duty = 5015%(X100)
2415 12:15:03.825121
2416 12:15:03.828006 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2417 12:15:03.828424
2418 12:15:03.831012 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2419 12:15:03.834984 [DutyScan_Calibration_Flow] ====Done====
2420 12:15:03.835427
2421 12:15:03.838007 [DutyScan_Calibration_Flow] k_type=3
2422 12:15:03.854135
2423 12:15:03.854653 ==DQM 0 ==
2424 12:15:03.857213 Final DQM duty delay cell = -4
2425 12:15:03.860517 [-4] MAX Duty = 5062%(X100), DQS PI = 34
2426 12:15:03.863841 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2427 12:15:03.867290 [-4] AVG Duty = 4969%(X100)
2428 12:15:03.867738
2429 12:15:03.868111 ==DQM 1 ==
2430 12:15:03.870318 Final DQM duty delay cell = 0
2431 12:15:03.873962 [0] MAX Duty = 5156%(X100), DQS PI = 6
2432 12:15:03.876907 [0] MIN Duty = 5000%(X100), DQS PI = 28
2433 12:15:03.880473 [0] AVG Duty = 5078%(X100)
2434 12:15:03.881075
2435 12:15:03.883912 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2436 12:15:03.884324
2437 12:15:03.886889 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2438 12:15:03.890559 [DutyScan_Calibration_Flow] ====Done====
2439 12:15:03.891038
2440 12:15:03.893785 [DutyScan_Calibration_Flow] k_type=2
2441 12:15:03.910806
2442 12:15:03.911321 ==DQ 0 ==
2443 12:15:03.915167 Final DQ duty delay cell = 0
2444 12:15:03.917417 [0] MAX Duty = 5156%(X100), DQS PI = 28
2445 12:15:03.920251 [0] MIN Duty = 4907%(X100), DQS PI = 6
2446 12:15:03.920734 [0] AVG Duty = 5031%(X100)
2447 12:15:03.921148
2448 12:15:03.923776 ==DQ 1 ==
2449 12:15:03.927153 Final DQ duty delay cell = 0
2450 12:15:03.930300 [0] MAX Duty = 5124%(X100), DQS PI = 10
2451 12:15:03.933908 [0] MIN Duty = 4969%(X100), DQS PI = 0
2452 12:15:03.934327 [0] AVG Duty = 5046%(X100)
2453 12:15:03.934731
2454 12:15:03.937333 CH1 DQ 0 Duty spec in!! Max-Min= 249%
2455 12:15:03.937775
2456 12:15:03.944122 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2457 12:15:03.946720 [DutyScan_Calibration_Flow] ====Done====
2458 12:15:03.950162 nWR fixed to 30
2459 12:15:03.950539 [ModeRegInit_LP4] CH0 RK0
2460 12:15:03.953641 [ModeRegInit_LP4] CH0 RK1
2461 12:15:03.956507 [ModeRegInit_LP4] CH1 RK0
2462 12:15:03.957114 [ModeRegInit_LP4] CH1 RK1
2463 12:15:03.960058 match AC timing 7
2464 12:15:03.963618 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2465 12:15:03.970665 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2466 12:15:03.973375 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2467 12:15:03.979801 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2468 12:15:03.983401 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2469 12:15:03.983866 ==
2470 12:15:03.986361 Dram Type= 6, Freq= 0, CH_0, rank 0
2471 12:15:03.989588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2472 12:15:03.990192 ==
2473 12:15:03.996549 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2474 12:15:04.003085 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2475 12:15:04.010520 [CA 0] Center 39 (9~70) winsize 62
2476 12:15:04.013725 [CA 1] Center 39 (9~69) winsize 61
2477 12:15:04.017258 [CA 2] Center 35 (5~66) winsize 62
2478 12:15:04.020260 [CA 3] Center 35 (4~66) winsize 63
2479 12:15:04.024316 [CA 4] Center 33 (4~63) winsize 60
2480 12:15:04.026869 [CA 5] Center 33 (3~63) winsize 61
2481 12:15:04.027424
2482 12:15:04.031054 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2483 12:15:04.031616
2484 12:15:04.033837 [CATrainingPosCal] consider 1 rank data
2485 12:15:04.037173 u2DelayCellTimex100 = 270/100 ps
2486 12:15:04.040565 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2487 12:15:04.043895 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2488 12:15:04.050454 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2489 12:15:04.053448 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2490 12:15:04.056636 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2491 12:15:04.060392 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2492 12:15:04.060981
2493 12:15:04.063904 CA PerBit enable=1, Macro0, CA PI delay=33
2494 12:15:04.064461
2495 12:15:04.066718 [CBTSetCACLKResult] CA Dly = 33
2496 12:15:04.067177 CS Dly: 8 (0~39)
2497 12:15:04.069650 ==
2498 12:15:04.073459 Dram Type= 6, Freq= 0, CH_0, rank 1
2499 12:15:04.076609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2500 12:15:04.077073 ==
2501 12:15:04.079929 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2502 12:15:04.086493 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2503 12:15:04.096313 [CA 0] Center 39 (8~70) winsize 63
2504 12:15:04.099386 [CA 1] Center 39 (9~70) winsize 62
2505 12:15:04.102755 [CA 2] Center 35 (5~66) winsize 62
2506 12:15:04.105859 [CA 3] Center 34 (4~65) winsize 62
2507 12:15:04.109799 [CA 4] Center 33 (3~64) winsize 62
2508 12:15:04.112391 [CA 5] Center 33 (3~63) winsize 61
2509 12:15:04.113030
2510 12:15:04.116149 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2511 12:15:04.116614
2512 12:15:04.119345 [CATrainingPosCal] consider 2 rank data
2513 12:15:04.123143 u2DelayCellTimex100 = 270/100 ps
2514 12:15:04.125710 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2515 12:15:04.132013 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2516 12:15:04.135847 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2517 12:15:04.139515 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2518 12:15:04.142675 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2519 12:15:04.145234 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2520 12:15:04.145725
2521 12:15:04.148944 CA PerBit enable=1, Macro0, CA PI delay=33
2522 12:15:04.149566
2523 12:15:04.152176 [CBTSetCACLKResult] CA Dly = 33
2524 12:15:04.156116 CS Dly: 9 (0~41)
2525 12:15:04.156666
2526 12:15:04.159081 ----->DramcWriteLeveling(PI) begin...
2527 12:15:04.159710 ==
2528 12:15:04.161993 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 12:15:04.165945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 12:15:04.166513 ==
2531 12:15:04.169121 Write leveling (Byte 0): 34 => 34
2532 12:15:04.172407 Write leveling (Byte 1): 29 => 29
2533 12:15:04.175459 DramcWriteLeveling(PI) end<-----
2534 12:15:04.176144
2535 12:15:04.176521 ==
2536 12:15:04.178841 Dram Type= 6, Freq= 0, CH_0, rank 0
2537 12:15:04.182147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2538 12:15:04.182824 ==
2539 12:15:04.185495 [Gating] SW mode calibration
2540 12:15:04.192061 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2541 12:15:04.198897 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2542 12:15:04.202247 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
2543 12:15:04.205494 0 15 4 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2544 12:15:04.212216 0 15 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2545 12:15:04.215364 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 12:15:04.218455 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2547 12:15:04.225523 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2548 12:15:04.228536 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2549 12:15:04.231367 0 15 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
2550 12:15:04.238444 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
2551 12:15:04.241530 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2552 12:15:04.244657 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 12:15:04.251529 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 12:15:04.256108 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 12:15:04.257882 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2556 12:15:04.264867 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2557 12:15:04.268339 1 0 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
2558 12:15:04.271699 1 1 0 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2559 12:15:04.278025 1 1 4 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
2560 12:15:04.281549 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 12:15:04.285090 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 12:15:04.291187 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 12:15:04.294549 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 12:15:04.297448 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2565 12:15:04.304315 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2566 12:15:04.307640 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2567 12:15:04.311338 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2568 12:15:04.318152 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 12:15:04.320946 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 12:15:04.324607 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 12:15:04.327981 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 12:15:04.334260 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 12:15:04.337503 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 12:15:04.340841 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 12:15:04.348609 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 12:15:04.350881 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 12:15:04.354558 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 12:15:04.360722 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 12:15:04.364800 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 12:15:04.367733 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2581 12:15:04.374078 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2582 12:15:04.376853 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2583 12:15:04.380820 Total UI for P1: 0, mck2ui 16
2584 12:15:04.384139 best dqsien dly found for B0: ( 1, 3, 26)
2585 12:15:04.387302 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2586 12:15:04.394057 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2587 12:15:04.397597 Total UI for P1: 0, mck2ui 16
2588 12:15:04.401163 best dqsien dly found for B1: ( 1, 4, 2)
2589 12:15:04.403944 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2590 12:15:04.407033 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2591 12:15:04.407592
2592 12:15:04.410415 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2593 12:15:04.414070 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2594 12:15:04.417107 [Gating] SW calibration Done
2595 12:15:04.417665 ==
2596 12:15:04.420650 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 12:15:04.424457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 12:15:04.425018 ==
2599 12:15:04.426758 RX Vref Scan: 0
2600 12:15:04.427213
2601 12:15:04.427574 RX Vref 0 -> 0, step: 1
2602 12:15:04.430687
2603 12:15:04.431238 RX Delay -40 -> 252, step: 8
2604 12:15:04.437278 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2605 12:15:04.440276 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2606 12:15:04.444601 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2607 12:15:04.446790 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2608 12:15:04.450133 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2609 12:15:04.457173 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2610 12:15:04.460320 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2611 12:15:04.463367 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2612 12:15:04.467827 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2613 12:15:04.471124 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2614 12:15:04.476692 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2615 12:15:04.480116 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2616 12:15:04.483102 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2617 12:15:04.486249 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2618 12:15:04.489991 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2619 12:15:04.496856 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2620 12:15:04.497398 ==
2621 12:15:04.499713 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 12:15:04.503092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 12:15:04.503653 ==
2624 12:15:04.504115 DQS Delay:
2625 12:15:04.506808 DQS0 = 0, DQS1 = 0
2626 12:15:04.507391 DQM Delay:
2627 12:15:04.509585 DQM0 = 119, DQM1 = 107
2628 12:15:04.510076 DQ Delay:
2629 12:15:04.513526 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2630 12:15:04.516380 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2631 12:15:04.520386 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2632 12:15:04.523609 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2633 12:15:04.524222
2634 12:15:04.524586
2635 12:15:04.526530 ==
2636 12:15:04.527088 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 12:15:04.533456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 12:15:04.534016 ==
2639 12:15:04.534383
2640 12:15:04.534716
2641 12:15:04.536655 TX Vref Scan disable
2642 12:15:04.537131 == TX Byte 0 ==
2643 12:15:04.539452 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2644 12:15:04.546418 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2645 12:15:04.546879 == TX Byte 1 ==
2646 12:15:04.549446 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2647 12:15:04.556388 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2648 12:15:04.556849 ==
2649 12:15:04.559273 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 12:15:04.562777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 12:15:04.563411 ==
2652 12:15:04.575435 TX Vref=22, minBit 13, minWin=25, winSum=419
2653 12:15:04.578662 TX Vref=24, minBit 13, minWin=25, winSum=425
2654 12:15:04.581559 TX Vref=26, minBit 13, minWin=25, winSum=430
2655 12:15:04.585147 TX Vref=28, minBit 10, minWin=26, winSum=432
2656 12:15:04.588539 TX Vref=30, minBit 4, minWin=26, winSum=433
2657 12:15:04.595311 TX Vref=32, minBit 10, minWin=25, winSum=431
2658 12:15:04.598250 [TxChooseVref] Worse bit 4, Min win 26, Win sum 433, Final Vref 30
2659 12:15:04.598683
2660 12:15:04.601363 Final TX Range 1 Vref 30
2661 12:15:04.601778
2662 12:15:04.602158 ==
2663 12:15:04.604972 Dram Type= 6, Freq= 0, CH_0, rank 0
2664 12:15:04.608632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2665 12:15:04.611191 ==
2666 12:15:04.611566
2667 12:15:04.611941
2668 12:15:04.612266 TX Vref Scan disable
2669 12:15:04.615168 == TX Byte 0 ==
2670 12:15:04.618958 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2671 12:15:04.624934 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2672 12:15:04.625353 == TX Byte 1 ==
2673 12:15:04.629165 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2674 12:15:04.634691 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2675 12:15:04.635108
2676 12:15:04.635438 [DATLAT]
2677 12:15:04.635802 Freq=1200, CH0 RK0
2678 12:15:04.636119
2679 12:15:04.638400 DATLAT Default: 0xd
2680 12:15:04.641401 0, 0xFFFF, sum = 0
2681 12:15:04.641832 1, 0xFFFF, sum = 0
2682 12:15:04.644758 2, 0xFFFF, sum = 0
2683 12:15:04.645182 3, 0xFFFF, sum = 0
2684 12:15:04.647843 4, 0xFFFF, sum = 0
2685 12:15:04.648266 5, 0xFFFF, sum = 0
2686 12:15:04.651953 6, 0xFFFF, sum = 0
2687 12:15:04.652377 7, 0xFFFF, sum = 0
2688 12:15:04.654870 8, 0xFFFF, sum = 0
2689 12:15:04.655536 9, 0xFFFF, sum = 0
2690 12:15:04.658169 10, 0xFFFF, sum = 0
2691 12:15:04.658591 11, 0xFFFF, sum = 0
2692 12:15:04.661347 12, 0x0, sum = 1
2693 12:15:04.661771 13, 0x0, sum = 2
2694 12:15:04.665073 14, 0x0, sum = 3
2695 12:15:04.665603 15, 0x0, sum = 4
2696 12:15:04.668095 best_step = 13
2697 12:15:04.668513
2698 12:15:04.668844 ==
2699 12:15:04.671130 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 12:15:04.674627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 12:15:04.675046 ==
2702 12:15:04.675383 RX Vref Scan: 1
2703 12:15:04.678753
2704 12:15:04.679367 Set Vref Range= 32 -> 127
2705 12:15:04.679894
2706 12:15:04.681363 RX Vref 32 -> 127, step: 1
2707 12:15:04.681844
2708 12:15:04.684658 RX Delay -21 -> 252, step: 4
2709 12:15:04.685314
2710 12:15:04.687777 Set Vref, RX VrefLevel [Byte0]: 32
2711 12:15:04.691494 [Byte1]: 32
2712 12:15:04.691947
2713 12:15:04.694544 Set Vref, RX VrefLevel [Byte0]: 33
2714 12:15:04.697787 [Byte1]: 33
2715 12:15:04.701452
2716 12:15:04.701868 Set Vref, RX VrefLevel [Byte0]: 34
2717 12:15:04.704780 [Byte1]: 34
2718 12:15:04.709790
2719 12:15:04.710206 Set Vref, RX VrefLevel [Byte0]: 35
2720 12:15:04.712791 [Byte1]: 35
2721 12:15:04.716934
2722 12:15:04.717021 Set Vref, RX VrefLevel [Byte0]: 36
2723 12:15:04.720781 [Byte1]: 36
2724 12:15:04.725136
2725 12:15:04.725307 Set Vref, RX VrefLevel [Byte0]: 37
2726 12:15:04.729156 [Byte1]: 37
2727 12:15:04.733778
2728 12:15:04.733969 Set Vref, RX VrefLevel [Byte0]: 38
2729 12:15:04.736563 [Byte1]: 38
2730 12:15:04.740962
2731 12:15:04.741100 Set Vref, RX VrefLevel [Byte0]: 39
2732 12:15:04.744652 [Byte1]: 39
2733 12:15:04.748784
2734 12:15:04.748870 Set Vref, RX VrefLevel [Byte0]: 40
2735 12:15:04.752512 [Byte1]: 40
2736 12:15:04.756790
2737 12:15:04.756966 Set Vref, RX VrefLevel [Byte0]: 41
2738 12:15:04.760715 [Byte1]: 41
2739 12:15:04.764882
2740 12:15:04.765071 Set Vref, RX VrefLevel [Byte0]: 42
2741 12:15:04.768403 [Byte1]: 42
2742 12:15:04.773381
2743 12:15:04.773603 Set Vref, RX VrefLevel [Byte0]: 43
2744 12:15:04.776091 [Byte1]: 43
2745 12:15:04.780638
2746 12:15:04.780868 Set Vref, RX VrefLevel [Byte0]: 44
2747 12:15:04.784294 [Byte1]: 44
2748 12:15:04.789160
2749 12:15:04.789443 Set Vref, RX VrefLevel [Byte0]: 45
2750 12:15:04.792009 [Byte1]: 45
2751 12:15:04.797033
2752 12:15:04.797424 Set Vref, RX VrefLevel [Byte0]: 46
2753 12:15:04.800012 [Byte1]: 46
2754 12:15:04.804913
2755 12:15:04.805391 Set Vref, RX VrefLevel [Byte0]: 47
2756 12:15:04.808784 [Byte1]: 47
2757 12:15:04.812386
2758 12:15:04.812845 Set Vref, RX VrefLevel [Byte0]: 48
2759 12:15:04.815925 [Byte1]: 48
2760 12:15:04.820538
2761 12:15:04.821091 Set Vref, RX VrefLevel [Byte0]: 49
2762 12:15:04.824262 [Byte1]: 49
2763 12:15:04.828738
2764 12:15:04.829312 Set Vref, RX VrefLevel [Byte0]: 50
2765 12:15:04.832554 [Byte1]: 50
2766 12:15:04.836577
2767 12:15:04.837036 Set Vref, RX VrefLevel [Byte0]: 51
2768 12:15:04.839877 [Byte1]: 51
2769 12:15:04.844564
2770 12:15:04.845119 Set Vref, RX VrefLevel [Byte0]: 52
2771 12:15:04.848071 [Byte1]: 52
2772 12:15:04.852667
2773 12:15:04.853219 Set Vref, RX VrefLevel [Byte0]: 53
2774 12:15:04.855925 [Byte1]: 53
2775 12:15:04.860041
2776 12:15:04.863467 Set Vref, RX VrefLevel [Byte0]: 54
2777 12:15:04.866549 [Byte1]: 54
2778 12:15:04.867109
2779 12:15:04.869843 Set Vref, RX VrefLevel [Byte0]: 55
2780 12:15:04.874060 [Byte1]: 55
2781 12:15:04.874623
2782 12:15:04.876444 Set Vref, RX VrefLevel [Byte0]: 56
2783 12:15:04.880348 [Byte1]: 56
2784 12:15:04.884482
2785 12:15:04.885035 Set Vref, RX VrefLevel [Byte0]: 57
2786 12:15:04.887023 [Byte1]: 57
2787 12:15:04.892096
2788 12:15:04.892670 Set Vref, RX VrefLevel [Byte0]: 58
2789 12:15:04.895460 [Byte1]: 58
2790 12:15:04.900152
2791 12:15:04.900720 Set Vref, RX VrefLevel [Byte0]: 59
2792 12:15:04.903164 [Byte1]: 59
2793 12:15:04.907925
2794 12:15:04.908476 Set Vref, RX VrefLevel [Byte0]: 60
2795 12:15:04.911660 [Byte1]: 60
2796 12:15:04.916339
2797 12:15:04.916827 Set Vref, RX VrefLevel [Byte0]: 61
2798 12:15:04.919817 [Byte1]: 61
2799 12:15:04.924203
2800 12:15:04.924904 Set Vref, RX VrefLevel [Byte0]: 62
2801 12:15:04.927793 [Byte1]: 62
2802 12:15:04.931628
2803 12:15:04.932147 Set Vref, RX VrefLevel [Byte0]: 63
2804 12:15:04.935368 [Byte1]: 63
2805 12:15:04.939294
2806 12:15:04.939898 Set Vref, RX VrefLevel [Byte0]: 64
2807 12:15:04.942820 [Byte1]: 64
2808 12:15:04.948325
2809 12:15:04.948882 Set Vref, RX VrefLevel [Byte0]: 65
2810 12:15:04.951612 [Byte1]: 65
2811 12:15:04.957129
2812 12:15:04.957898 Set Vref, RX VrefLevel [Byte0]: 66
2813 12:15:04.958771 [Byte1]: 66
2814 12:15:04.963355
2815 12:15:04.963962 Set Vref, RX VrefLevel [Byte0]: 67
2816 12:15:04.967117 [Byte1]: 67
2817 12:15:04.971335
2818 12:15:04.971855 Set Vref, RX VrefLevel [Byte0]: 68
2819 12:15:04.974579 [Byte1]: 68
2820 12:15:04.979043
2821 12:15:04.979519 Set Vref, RX VrefLevel [Byte0]: 69
2822 12:15:04.982791 [Byte1]: 69
2823 12:15:04.986715
2824 12:15:04.987173 Set Vref, RX VrefLevel [Byte0]: 70
2825 12:15:04.990323 [Byte1]: 70
2826 12:15:04.995086
2827 12:15:04.995548 Set Vref, RX VrefLevel [Byte0]: 71
2828 12:15:04.998371 [Byte1]: 71
2829 12:15:05.002976
2830 12:15:05.003628 Set Vref, RX VrefLevel [Byte0]: 72
2831 12:15:05.006938 [Byte1]: 72
2832 12:15:05.011024
2833 12:15:05.011507 Set Vref, RX VrefLevel [Byte0]: 73
2834 12:15:05.014167 [Byte1]: 73
2835 12:15:05.019086
2836 12:15:05.019404 Set Vref, RX VrefLevel [Byte0]: 74
2837 12:15:05.021694 [Byte1]: 74
2838 12:15:05.026165
2839 12:15:05.026543 Set Vref, RX VrefLevel [Byte0]: 75
2840 12:15:05.029688 [Byte1]: 75
2841 12:15:05.034184
2842 12:15:05.034421 Set Vref, RX VrefLevel [Byte0]: 76
2843 12:15:05.037860 [Byte1]: 76
2844 12:15:05.042338
2845 12:15:05.042575 Final RX Vref Byte 0 = 61 to rank0
2846 12:15:05.045795 Final RX Vref Byte 1 = 49 to rank0
2847 12:15:05.049064 Final RX Vref Byte 0 = 61 to rank1
2848 12:15:05.052130 Final RX Vref Byte 1 = 49 to rank1==
2849 12:15:05.056526 Dram Type= 6, Freq= 0, CH_0, rank 0
2850 12:15:05.061862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2851 12:15:05.062102 ==
2852 12:15:05.062326 DQS Delay:
2853 12:15:05.062504 DQS0 = 0, DQS1 = 0
2854 12:15:05.065343 DQM Delay:
2855 12:15:05.065580 DQM0 = 119, DQM1 = 106
2856 12:15:05.068766 DQ Delay:
2857 12:15:05.072239 DQ0 =116, DQ1 =118, DQ2 =116, DQ3 =116
2858 12:15:05.075524 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =126
2859 12:15:05.078978 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
2860 12:15:05.082231 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116
2861 12:15:05.082468
2862 12:15:05.082682
2863 12:15:05.092332 [DQSOSCAuto] RK0, (LSB)MR18= 0x11fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2864 12:15:05.092575 CH0 RK0: MR19=403, MR18=11FD
2865 12:15:05.098426 CH0_RK0: MR19=0x403, MR18=0x11FD, DQSOSC=403, MR23=63, INC=40, DEC=26
2866 12:15:05.098732
2867 12:15:05.101687 ----->DramcWriteLeveling(PI) begin...
2868 12:15:05.101929 ==
2869 12:15:05.104930 Dram Type= 6, Freq= 0, CH_0, rank 1
2870 12:15:05.111536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2871 12:15:05.111834 ==
2872 12:15:05.114988 Write leveling (Byte 0): 33 => 33
2873 12:15:05.115224 Write leveling (Byte 1): 28 => 28
2874 12:15:05.118529 DramcWriteLeveling(PI) end<-----
2875 12:15:05.118914
2876 12:15:05.119252 ==
2877 12:15:05.122680 Dram Type= 6, Freq= 0, CH_0, rank 1
2878 12:15:05.128386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2879 12:15:05.128762 ==
2880 12:15:05.131453 [Gating] SW mode calibration
2881 12:15:05.139025 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2882 12:15:05.142495 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2883 12:15:05.147874 0 15 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2884 12:15:05.152080 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2885 12:15:05.155032 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2886 12:15:05.161315 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2887 12:15:05.165335 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2888 12:15:05.168569 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2889 12:15:05.175091 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2890 12:15:05.178816 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2891 12:15:05.181495 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2892 12:15:05.187778 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2893 12:15:05.190973 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2894 12:15:05.194285 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 12:15:05.200866 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 12:15:05.203938 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2897 12:15:05.207375 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2898 12:15:05.214171 1 0 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2899 12:15:05.217430 1 1 0 | B1->B0 | 3434 4444 | 0 0 | (0 0) (0 0)
2900 12:15:05.221420 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2901 12:15:05.227245 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 12:15:05.230895 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 12:15:05.234400 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 12:15:05.240563 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 12:15:05.243836 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 12:15:05.247480 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2907 12:15:05.254162 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2908 12:15:05.257548 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 12:15:05.261203 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 12:15:05.265061 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 12:15:05.282983 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 12:15:05.283538 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 12:15:05.284049 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 12:15:05.284913 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 12:15:05.288059 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 12:15:05.291295 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 12:15:05.297782 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 12:15:05.300726 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 12:15:05.304084 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 12:15:05.310567 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 12:15:05.313831 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 12:15:05.317064 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2923 12:15:05.323613 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2924 12:15:05.326887 Total UI for P1: 0, mck2ui 16
2925 12:15:05.330397 best dqsien dly found for B0: ( 1, 3, 28)
2926 12:15:05.333617 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 12:15:05.337489 Total UI for P1: 0, mck2ui 16
2928 12:15:05.340481 best dqsien dly found for B1: ( 1, 4, 0)
2929 12:15:05.343382 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2930 12:15:05.347313 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2931 12:15:05.347566
2932 12:15:05.350917 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2933 12:15:05.353772 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2934 12:15:05.356896 [Gating] SW calibration Done
2935 12:15:05.357165 ==
2936 12:15:05.360467 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 12:15:05.363588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 12:15:05.367603 ==
2939 12:15:05.367934 RX Vref Scan: 0
2940 12:15:05.368123
2941 12:15:05.369786 RX Vref 0 -> 0, step: 1
2942 12:15:05.370133
2943 12:15:05.373676 RX Delay -40 -> 252, step: 8
2944 12:15:05.377151 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2945 12:15:05.380246 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2946 12:15:05.383358 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2947 12:15:05.386664 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2948 12:15:05.393060 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2949 12:15:05.399080 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2950 12:15:05.400059 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2951 12:15:05.404204 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2952 12:15:05.406898 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2953 12:15:05.413460 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2954 12:15:05.417003 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2955 12:15:05.420297 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2956 12:15:05.423735 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2957 12:15:05.426691 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2958 12:15:05.433242 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2959 12:15:05.437273 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2960 12:15:05.437833 ==
2961 12:15:05.440414 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 12:15:05.443329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 12:15:05.443831 ==
2964 12:15:05.447210 DQS Delay:
2965 12:15:05.447806 DQS0 = 0, DQS1 = 0
2966 12:15:05.448183 DQM Delay:
2967 12:15:05.449950 DQM0 = 116, DQM1 = 108
2968 12:15:05.450412 DQ Delay:
2969 12:15:05.453994 DQ0 =111, DQ1 =123, DQ2 =111, DQ3 =115
2970 12:15:05.456603 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2971 12:15:05.460448 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2972 12:15:05.466709 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
2973 12:15:05.467284
2974 12:15:05.467650
2975 12:15:05.468161 ==
2976 12:15:05.469651 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 12:15:05.472997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 12:15:05.473483 ==
2979 12:15:05.473872
2980 12:15:05.474215
2981 12:15:05.476372 TX Vref Scan disable
2982 12:15:05.476831 == TX Byte 0 ==
2983 12:15:05.483417 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2984 12:15:05.486342 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2985 12:15:05.486885 == TX Byte 1 ==
2986 12:15:05.493061 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2987 12:15:05.496187 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2988 12:15:05.496609 ==
2989 12:15:05.499530 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 12:15:05.502859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 12:15:05.503296 ==
2992 12:15:05.516064 TX Vref=22, minBit 8, minWin=25, winSum=421
2993 12:15:05.520120 TX Vref=24, minBit 13, minWin=25, winSum=424
2994 12:15:05.522755 TX Vref=26, minBit 1, minWin=26, winSum=429
2995 12:15:05.526050 TX Vref=28, minBit 1, minWin=26, winSum=431
2996 12:15:05.528915 TX Vref=30, minBit 10, minWin=26, winSum=435
2997 12:15:05.535385 TX Vref=32, minBit 13, minWin=26, winSum=432
2998 12:15:05.539085 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 30
2999 12:15:05.539168
3000 12:15:05.542132 Final TX Range 1 Vref 30
3001 12:15:05.542214
3002 12:15:05.542280 ==
3003 12:15:05.545696 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 12:15:05.548945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 12:15:05.552393 ==
3006 12:15:05.552475
3007 12:15:05.552540
3008 12:15:05.552600 TX Vref Scan disable
3009 12:15:05.555980 == TX Byte 0 ==
3010 12:15:05.559643 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3011 12:15:05.565974 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3012 12:15:05.566089 == TX Byte 1 ==
3013 12:15:05.569120 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3014 12:15:05.575801 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3015 12:15:05.575883
3016 12:15:05.575947 [DATLAT]
3017 12:15:05.576022 Freq=1200, CH0 RK1
3018 12:15:05.576086
3019 12:15:05.579348 DATLAT Default: 0xd
3020 12:15:05.579435 0, 0xFFFF, sum = 0
3021 12:15:05.582527 1, 0xFFFF, sum = 0
3022 12:15:05.586009 2, 0xFFFF, sum = 0
3023 12:15:05.586113 3, 0xFFFF, sum = 0
3024 12:15:05.588680 4, 0xFFFF, sum = 0
3025 12:15:05.588786 5, 0xFFFF, sum = 0
3026 12:15:05.592585 6, 0xFFFF, sum = 0
3027 12:15:05.592697 7, 0xFFFF, sum = 0
3028 12:15:05.595737 8, 0xFFFF, sum = 0
3029 12:15:05.595849 9, 0xFFFF, sum = 0
3030 12:15:05.598681 10, 0xFFFF, sum = 0
3031 12:15:05.598804 11, 0xFFFF, sum = 0
3032 12:15:05.602568 12, 0x0, sum = 1
3033 12:15:05.602705 13, 0x0, sum = 2
3034 12:15:05.605943 14, 0x0, sum = 3
3035 12:15:05.606026 15, 0x0, sum = 4
3036 12:15:05.609006 best_step = 13
3037 12:15:05.609087
3038 12:15:05.609152 ==
3039 12:15:05.612356 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 12:15:05.615949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 12:15:05.616370 ==
3042 12:15:05.616703 RX Vref Scan: 0
3043 12:15:05.618942
3044 12:15:05.619355 RX Vref 0 -> 0, step: 1
3045 12:15:05.619723
3046 12:15:05.622510 RX Delay -21 -> 252, step: 4
3047 12:15:05.628722 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3048 12:15:05.632666 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3049 12:15:05.635834 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3050 12:15:05.639713 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3051 12:15:05.643165 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3052 12:15:05.646786 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3053 12:15:05.652683 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3054 12:15:05.656173 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3055 12:15:05.658999 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3056 12:15:05.662635 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3057 12:15:05.665976 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3058 12:15:05.672701 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3059 12:15:05.676273 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3060 12:15:05.679148 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3061 12:15:05.683317 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3062 12:15:05.686216 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3063 12:15:05.688980 ==
3064 12:15:05.692778 Dram Type= 6, Freq= 0, CH_0, rank 1
3065 12:15:05.696272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3066 12:15:05.696739 ==
3067 12:15:05.697113 DQS Delay:
3068 12:15:05.698967 DQS0 = 0, DQS1 = 0
3069 12:15:05.699429 DQM Delay:
3070 12:15:05.703213 DQM0 = 116, DQM1 = 107
3071 12:15:05.703824 DQ Delay:
3072 12:15:05.706097 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =112
3073 12:15:05.709430 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3074 12:15:05.712632 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3075 12:15:05.716164 DQ12 =112, DQ13 =114, DQ14 =118, DQ15 =116
3076 12:15:05.716721
3077 12:15:05.717092
3078 12:15:05.725635 [DQSOSCAuto] RK1, (LSB)MR18= 0xee8, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 404 ps
3079 12:15:05.726198 CH0 RK1: MR19=403, MR18=EE8
3080 12:15:05.732423 CH0_RK1: MR19=0x403, MR18=0xEE8, DQSOSC=404, MR23=63, INC=40, DEC=26
3081 12:15:05.735953 [RxdqsGatingPostProcess] freq 1200
3082 12:15:05.742751 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3083 12:15:05.745332 best DQS0 dly(2T, 0.5T) = (0, 11)
3084 12:15:05.749117 best DQS1 dly(2T, 0.5T) = (0, 12)
3085 12:15:05.752661 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3086 12:15:05.756140 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3087 12:15:05.759311 best DQS0 dly(2T, 0.5T) = (0, 11)
3088 12:15:05.760054 best DQS1 dly(2T, 0.5T) = (0, 12)
3089 12:15:05.763047 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3090 12:15:05.765568 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3091 12:15:05.769397 Pre-setting of DQS Precalculation
3092 12:15:05.775859 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3093 12:15:05.776428 ==
3094 12:15:05.778693 Dram Type= 6, Freq= 0, CH_1, rank 0
3095 12:15:05.781650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3096 12:15:05.782114 ==
3097 12:15:05.788787 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3098 12:15:05.795129 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3099 12:15:05.802438 [CA 0] Center 37 (7~68) winsize 62
3100 12:15:05.806369 [CA 1] Center 38 (8~68) winsize 61
3101 12:15:05.809328 [CA 2] Center 34 (4~64) winsize 61
3102 12:15:05.812785 [CA 3] Center 33 (3~64) winsize 62
3103 12:15:05.816164 [CA 4] Center 34 (4~64) winsize 61
3104 12:15:05.818828 [CA 5] Center 33 (3~64) winsize 62
3105 12:15:05.819293
3106 12:15:05.822468 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3107 12:15:05.823034
3108 12:15:05.825538 [CATrainingPosCal] consider 1 rank data
3109 12:15:05.828982 u2DelayCellTimex100 = 270/100 ps
3110 12:15:05.832137 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3111 12:15:05.839231 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3112 12:15:05.842565 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3113 12:15:05.845373 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3114 12:15:05.848991 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3115 12:15:05.852370 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3116 12:15:05.852833
3117 12:15:05.855894 CA PerBit enable=1, Macro0, CA PI delay=33
3118 12:15:05.856455
3119 12:15:05.859073 [CBTSetCACLKResult] CA Dly = 33
3120 12:15:05.859551 CS Dly: 5 (0~36)
3121 12:15:05.862098 ==
3122 12:15:05.865390 Dram Type= 6, Freq= 0, CH_1, rank 1
3123 12:15:05.868985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 12:15:05.869626 ==
3125 12:15:05.872099 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3126 12:15:05.878679 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3127 12:15:05.888307 [CA 0] Center 37 (7~68) winsize 62
3128 12:15:05.891877 [CA 1] Center 38 (8~68) winsize 61
3129 12:15:05.894615 [CA 2] Center 34 (4~65) winsize 62
3130 12:15:05.898247 [CA 3] Center 33 (3~64) winsize 62
3131 12:15:05.901130 [CA 4] Center 34 (4~65) winsize 62
3132 12:15:05.904586 [CA 5] Center 33 (3~64) winsize 62
3133 12:15:05.905156
3134 12:15:05.907720 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3135 12:15:05.908295
3136 12:15:05.911007 [CATrainingPosCal] consider 2 rank data
3137 12:15:05.915131 u2DelayCellTimex100 = 270/100 ps
3138 12:15:05.918351 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3139 12:15:05.924952 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3140 12:15:05.927721 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3141 12:15:05.930830 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3142 12:15:05.934712 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3143 12:15:05.937875 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3144 12:15:05.938444
3145 12:15:05.941031 CA PerBit enable=1, Macro0, CA PI delay=33
3146 12:15:05.941616
3147 12:15:05.944705 [CBTSetCACLKResult] CA Dly = 33
3148 12:15:05.945275 CS Dly: 7 (0~40)
3149 12:15:05.947450
3150 12:15:05.950687 ----->DramcWriteLeveling(PI) begin...
3151 12:15:05.951213 ==
3152 12:15:05.954132 Dram Type= 6, Freq= 0, CH_1, rank 0
3153 12:15:05.957326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3154 12:15:05.957796 ==
3155 12:15:05.960574 Write leveling (Byte 0): 24 => 24
3156 12:15:05.964334 Write leveling (Byte 1): 27 => 27
3157 12:15:05.967820 DramcWriteLeveling(PI) end<-----
3158 12:15:05.968593
3159 12:15:05.968987 ==
3160 12:15:05.971910 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 12:15:05.974424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 12:15:05.975019 ==
3163 12:15:05.977751 [Gating] SW mode calibration
3164 12:15:05.983981 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3165 12:15:05.990747 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3166 12:15:05.994126 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3167 12:15:05.997230 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3168 12:15:06.004360 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3169 12:15:06.007407 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3170 12:15:06.010407 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3171 12:15:06.016894 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3172 12:15:06.019983 0 15 24 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
3173 12:15:06.024046 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3174 12:15:06.030416 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3175 12:15:06.034022 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3176 12:15:06.036821 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3177 12:15:06.043598 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3178 12:15:06.046800 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3179 12:15:06.049960 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3180 12:15:06.056992 1 0 24 | B1->B0 | 2929 3636 | 0 1 | (0 0) (0 0)
3181 12:15:06.059965 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 12:15:06.063854 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3183 12:15:06.069886 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3184 12:15:06.073269 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 12:15:06.077014 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3186 12:15:06.083195 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3187 12:15:06.086948 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3188 12:15:06.090480 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3189 12:15:06.093670 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3190 12:15:06.100402 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 12:15:06.104147 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 12:15:06.106618 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 12:15:06.113576 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 12:15:06.116656 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 12:15:06.120100 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 12:15:06.127156 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3197 12:15:06.129958 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3198 12:15:06.133656 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 12:15:06.140411 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 12:15:06.143465 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 12:15:06.146674 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 12:15:06.153297 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 12:15:06.157004 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 12:15:06.159864 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3205 12:15:06.166287 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3206 12:15:06.170213 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 12:15:06.173326 Total UI for P1: 0, mck2ui 16
3208 12:15:06.176511 best dqsien dly found for B0: ( 1, 3, 26)
3209 12:15:06.179924 Total UI for P1: 0, mck2ui 16
3210 12:15:06.183280 best dqsien dly found for B1: ( 1, 3, 26)
3211 12:15:06.186219 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3212 12:15:06.189314 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3213 12:15:06.190029
3214 12:15:06.193026 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3215 12:15:06.196462 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3216 12:15:06.199615 [Gating] SW calibration Done
3217 12:15:06.200127 ==
3218 12:15:06.203092 Dram Type= 6, Freq= 0, CH_1, rank 0
3219 12:15:06.206643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3220 12:15:06.209419 ==
3221 12:15:06.209886 RX Vref Scan: 0
3222 12:15:06.210257
3223 12:15:06.213168 RX Vref 0 -> 0, step: 1
3224 12:15:06.213648
3225 12:15:06.214016 RX Delay -40 -> 252, step: 8
3226 12:15:06.220071 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3227 12:15:06.224143 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3228 12:15:06.226633 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3229 12:15:06.229999 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3230 12:15:06.233013 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3231 12:15:06.239468 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3232 12:15:06.242468 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3233 12:15:06.246643 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3234 12:15:06.249158 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
3235 12:15:06.252939 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3236 12:15:06.259391 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3237 12:15:06.262588 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3238 12:15:06.265707 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3239 12:15:06.269534 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3240 12:15:06.276289 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3241 12:15:06.279273 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3242 12:15:06.279920 ==
3243 12:15:06.282711 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 12:15:06.285839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 12:15:06.286415 ==
3246 12:15:06.289429 DQS Delay:
3247 12:15:06.289904 DQS0 = 0, DQS1 = 0
3248 12:15:06.290510 DQM Delay:
3249 12:15:06.292181 DQM0 = 117, DQM1 = 110
3250 12:15:06.292789 DQ Delay:
3251 12:15:06.295872 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3252 12:15:06.298944 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3253 12:15:06.302949 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =99
3254 12:15:06.305533 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3255 12:15:06.308664
3256 12:15:06.309316
3257 12:15:06.309698 ==
3258 12:15:06.312192 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 12:15:06.315903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 12:15:06.316474 ==
3261 12:15:06.316914
3262 12:15:06.317268
3263 12:15:06.319088 TX Vref Scan disable
3264 12:15:06.319761 == TX Byte 0 ==
3265 12:15:06.325333 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3266 12:15:06.329208 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3267 12:15:06.329772 == TX Byte 1 ==
3268 12:15:06.335649 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3269 12:15:06.338487 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3270 12:15:06.338953 ==
3271 12:15:06.342057 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 12:15:06.346184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 12:15:06.346651 ==
3274 12:15:06.358193 TX Vref=22, minBit 9, minWin=25, winSum=417
3275 12:15:06.361044 TX Vref=24, minBit 8, minWin=25, winSum=421
3276 12:15:06.364889 TX Vref=26, minBit 9, minWin=25, winSum=429
3277 12:15:06.367725 TX Vref=28, minBit 15, minWin=26, winSum=437
3278 12:15:06.371348 TX Vref=30, minBit 9, minWin=26, winSum=434
3279 12:15:06.377813 TX Vref=32, minBit 9, minWin=25, winSum=429
3280 12:15:06.381464 [TxChooseVref] Worse bit 15, Min win 26, Win sum 437, Final Vref 28
3281 12:15:06.382028
3282 12:15:06.384952 Final TX Range 1 Vref 28
3283 12:15:06.385510
3284 12:15:06.385880 ==
3285 12:15:06.387942 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 12:15:06.391080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 12:15:06.394902 ==
3288 12:15:06.395364
3289 12:15:06.395795
3290 12:15:06.396189 TX Vref Scan disable
3291 12:15:06.397524 == TX Byte 0 ==
3292 12:15:06.401330 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3293 12:15:06.407974 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3294 12:15:06.408433 == TX Byte 1 ==
3295 12:15:06.411043 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3296 12:15:06.417935 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3297 12:15:06.418462
3298 12:15:06.418831 [DATLAT]
3299 12:15:06.419177 Freq=1200, CH1 RK0
3300 12:15:06.419524
3301 12:15:06.421006 DATLAT Default: 0xd
3302 12:15:06.421465 0, 0xFFFF, sum = 0
3303 12:15:06.424558 1, 0xFFFF, sum = 0
3304 12:15:06.425131 2, 0xFFFF, sum = 0
3305 12:15:06.427917 3, 0xFFFF, sum = 0
3306 12:15:06.431287 4, 0xFFFF, sum = 0
3307 12:15:06.431799 5, 0xFFFF, sum = 0
3308 12:15:06.434762 6, 0xFFFF, sum = 0
3309 12:15:06.435479 7, 0xFFFF, sum = 0
3310 12:15:06.437666 8, 0xFFFF, sum = 0
3311 12:15:06.438168 9, 0xFFFF, sum = 0
3312 12:15:06.441113 10, 0xFFFF, sum = 0
3313 12:15:06.441688 11, 0xFFFF, sum = 0
3314 12:15:06.444889 12, 0x0, sum = 1
3315 12:15:06.445465 13, 0x0, sum = 2
3316 12:15:06.447735 14, 0x0, sum = 3
3317 12:15:06.448312 15, 0x0, sum = 4
3318 12:15:06.450528 best_step = 13
3319 12:15:06.450988
3320 12:15:06.451393 ==
3321 12:15:06.453996 Dram Type= 6, Freq= 0, CH_1, rank 0
3322 12:15:06.457793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3323 12:15:06.458363 ==
3324 12:15:06.458736 RX Vref Scan: 1
3325 12:15:06.461030
3326 12:15:06.461517 Set Vref Range= 32 -> 127
3327 12:15:06.461891
3328 12:15:06.464059 RX Vref 32 -> 127, step: 1
3329 12:15:06.464519
3330 12:15:06.467570 RX Delay -21 -> 252, step: 4
3331 12:15:06.468103
3332 12:15:06.470519 Set Vref, RX VrefLevel [Byte0]: 32
3333 12:15:06.474599 [Byte1]: 32
3334 12:15:06.475054
3335 12:15:06.477307 Set Vref, RX VrefLevel [Byte0]: 33
3336 12:15:06.480390 [Byte1]: 33
3337 12:15:06.484336
3338 12:15:06.484748 Set Vref, RX VrefLevel [Byte0]: 34
3339 12:15:06.487601 [Byte1]: 34
3340 12:15:06.491734
3341 12:15:06.491815 Set Vref, RX VrefLevel [Byte0]: 35
3342 12:15:06.495896 [Byte1]: 35
3343 12:15:06.499840
3344 12:15:06.500012 Set Vref, RX VrefLevel [Byte0]: 36
3345 12:15:06.503131 [Byte1]: 36
3346 12:15:06.507834
3347 12:15:06.507990 Set Vref, RX VrefLevel [Byte0]: 37
3348 12:15:06.511682 [Byte1]: 37
3349 12:15:06.515652
3350 12:15:06.515850 Set Vref, RX VrefLevel [Byte0]: 38
3351 12:15:06.519018 [Byte1]: 38
3352 12:15:06.523531
3353 12:15:06.523662 Set Vref, RX VrefLevel [Byte0]: 39
3354 12:15:06.526462 [Byte1]: 39
3355 12:15:06.531056
3356 12:15:06.531136 Set Vref, RX VrefLevel [Byte0]: 40
3357 12:15:06.534701 [Byte1]: 40
3358 12:15:06.540020
3359 12:15:06.540100 Set Vref, RX VrefLevel [Byte0]: 41
3360 12:15:06.542464 [Byte1]: 41
3361 12:15:06.547262
3362 12:15:06.547342 Set Vref, RX VrefLevel [Byte0]: 42
3363 12:15:06.550446 [Byte1]: 42
3364 12:15:06.555543
3365 12:15:06.555623 Set Vref, RX VrefLevel [Byte0]: 43
3366 12:15:06.558243 [Byte1]: 43
3367 12:15:06.562893
3368 12:15:06.562973 Set Vref, RX VrefLevel [Byte0]: 44
3369 12:15:06.566473 [Byte1]: 44
3370 12:15:06.571584
3371 12:15:06.571675 Set Vref, RX VrefLevel [Byte0]: 45
3372 12:15:06.574321 [Byte1]: 45
3373 12:15:06.578745
3374 12:15:06.578926 Set Vref, RX VrefLevel [Byte0]: 46
3375 12:15:06.582238 [Byte1]: 46
3376 12:15:06.587651
3377 12:15:06.588301 Set Vref, RX VrefLevel [Byte0]: 47
3378 12:15:06.590442 [Byte1]: 47
3379 12:15:06.594814
3380 12:15:06.595224 Set Vref, RX VrefLevel [Byte0]: 48
3381 12:15:06.598236 [Byte1]: 48
3382 12:15:06.603326
3383 12:15:06.603884 Set Vref, RX VrefLevel [Byte0]: 49
3384 12:15:06.606627 [Byte1]: 49
3385 12:15:06.611099
3386 12:15:06.611507 Set Vref, RX VrefLevel [Byte0]: 50
3387 12:15:06.614555 [Byte1]: 50
3388 12:15:06.618975
3389 12:15:06.619388 Set Vref, RX VrefLevel [Byte0]: 51
3390 12:15:06.621986 [Byte1]: 51
3391 12:15:06.627033
3392 12:15:06.627444 Set Vref, RX VrefLevel [Byte0]: 52
3393 12:15:06.629816 [Byte1]: 52
3394 12:15:06.634634
3395 12:15:06.635045 Set Vref, RX VrefLevel [Byte0]: 53
3396 12:15:06.637965 [Byte1]: 53
3397 12:15:06.642748
3398 12:15:06.646004 Set Vref, RX VrefLevel [Byte0]: 54
3399 12:15:06.649147 [Byte1]: 54
3400 12:15:06.649707
3401 12:15:06.652417 Set Vref, RX VrefLevel [Byte0]: 55
3402 12:15:06.655923 [Byte1]: 55
3403 12:15:06.656484
3404 12:15:06.659067 Set Vref, RX VrefLevel [Byte0]: 56
3405 12:15:06.662349 [Byte1]: 56
3406 12:15:06.666808
3407 12:15:06.667424 Set Vref, RX VrefLevel [Byte0]: 57
3408 12:15:06.669584 [Byte1]: 57
3409 12:15:06.674889
3410 12:15:06.675446 Set Vref, RX VrefLevel [Byte0]: 58
3411 12:15:06.677776 [Byte1]: 58
3412 12:15:06.682535
3413 12:15:06.683092 Set Vref, RX VrefLevel [Byte0]: 59
3414 12:15:06.686469 [Byte1]: 59
3415 12:15:06.690383
3416 12:15:06.690959 Set Vref, RX VrefLevel [Byte0]: 60
3417 12:15:06.694286 [Byte1]: 60
3418 12:15:06.698436
3419 12:15:06.698889 Set Vref, RX VrefLevel [Byte0]: 61
3420 12:15:06.701913 [Byte1]: 61
3421 12:15:06.705887
3422 12:15:06.706447 Set Vref, RX VrefLevel [Byte0]: 62
3423 12:15:06.709766 [Byte1]: 62
3424 12:15:06.714759
3425 12:15:06.715320 Set Vref, RX VrefLevel [Byte0]: 63
3426 12:15:06.717343 [Byte1]: 63
3427 12:15:06.722137
3428 12:15:06.722701 Set Vref, RX VrefLevel [Byte0]: 64
3429 12:15:06.726124 [Byte1]: 64
3430 12:15:06.729812
3431 12:15:06.730368 Set Vref, RX VrefLevel [Byte0]: 65
3432 12:15:06.733151 [Byte1]: 65
3433 12:15:06.737485
3434 12:15:06.738039 Set Vref, RX VrefLevel [Byte0]: 66
3435 12:15:06.741088 [Byte1]: 66
3436 12:15:06.745585
3437 12:15:06.746041 Set Vref, RX VrefLevel [Byte0]: 67
3438 12:15:06.749115 [Byte1]: 67
3439 12:15:06.754016
3440 12:15:06.754575 Set Vref, RX VrefLevel [Byte0]: 68
3441 12:15:06.756465 [Byte1]: 68
3442 12:15:06.761347
3443 12:15:06.761974 Set Vref, RX VrefLevel [Byte0]: 69
3444 12:15:06.764536 [Byte1]: 69
3445 12:15:06.769608
3446 12:15:06.770150 Final RX Vref Byte 0 = 50 to rank0
3447 12:15:06.772837 Final RX Vref Byte 1 = 56 to rank0
3448 12:15:06.775922 Final RX Vref Byte 0 = 50 to rank1
3449 12:15:06.779737 Final RX Vref Byte 1 = 56 to rank1==
3450 12:15:06.782518 Dram Type= 6, Freq= 0, CH_1, rank 0
3451 12:15:06.789854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3452 12:15:06.790431 ==
3453 12:15:06.790808 DQS Delay:
3454 12:15:06.791151 DQS0 = 0, DQS1 = 0
3455 12:15:06.792239 DQM Delay:
3456 12:15:06.792921 DQM0 = 117, DQM1 = 110
3457 12:15:06.796210 DQ Delay:
3458 12:15:06.799411 DQ0 =120, DQ1 =110, DQ2 =110, DQ3 =114
3459 12:15:06.802626 DQ4 =114, DQ5 =128, DQ6 =126, DQ7 =116
3460 12:15:06.806286 DQ8 =96, DQ9 =102, DQ10 =112, DQ11 =100
3461 12:15:06.809363 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3462 12:15:06.809964
3463 12:15:06.810345
3464 12:15:06.816136 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 407 ps
3465 12:15:06.818888 CH1 RK0: MR19=403, MR18=6F9
3466 12:15:06.826079 CH1_RK0: MR19=0x403, MR18=0x6F9, DQSOSC=407, MR23=63, INC=39, DEC=26
3467 12:15:06.826659
3468 12:15:06.829925 ----->DramcWriteLeveling(PI) begin...
3469 12:15:06.830500 ==
3470 12:15:06.832694 Dram Type= 6, Freq= 0, CH_1, rank 1
3471 12:15:06.836156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3472 12:15:06.838836 ==
3473 12:15:06.839315 Write leveling (Byte 0): 25 => 25
3474 12:15:06.842593 Write leveling (Byte 1): 29 => 29
3475 12:15:06.846182 DramcWriteLeveling(PI) end<-----
3476 12:15:06.846749
3477 12:15:06.847117 ==
3478 12:15:06.848624 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 12:15:06.855455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 12:15:06.856055 ==
3481 12:15:06.859735 [Gating] SW mode calibration
3482 12:15:06.865688 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3483 12:15:06.869169 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3484 12:15:06.876019 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3485 12:15:06.879396 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 12:15:06.881629 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 12:15:06.888320 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 12:15:06.892010 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3489 12:15:06.894912 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3490 12:15:06.901640 0 15 24 | B1->B0 | 2f2f 3434 | 0 0 | (0 1) (0 0)
3491 12:15:06.905246 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (1 0) (1 0)
3492 12:15:06.908294 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 12:15:06.915337 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 12:15:06.918003 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 12:15:06.923107 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 12:15:06.928095 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3497 12:15:06.931783 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 12:15:06.934247 1 0 24 | B1->B0 | 3c3c 2828 | 0 1 | (0 0) (0 0)
3499 12:15:06.940869 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 12:15:06.944634 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 12:15:06.947759 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 12:15:06.955007 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 12:15:06.958144 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 12:15:06.961033 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 12:15:06.967803 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 12:15:06.971412 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3507 12:15:06.974951 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3508 12:15:06.981199 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 12:15:06.984134 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 12:15:06.988306 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 12:15:06.994328 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 12:15:06.997283 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 12:15:07.000617 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 12:15:07.007924 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 12:15:07.010693 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 12:15:07.013841 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 12:15:07.020423 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 12:15:07.023565 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 12:15:07.027377 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 12:15:07.034170 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 12:15:07.036754 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 12:15:07.040172 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3523 12:15:07.046748 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3524 12:15:07.050075 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 12:15:07.053401 Total UI for P1: 0, mck2ui 16
3526 12:15:07.056925 best dqsien dly found for B0: ( 1, 3, 26)
3527 12:15:07.060211 Total UI for P1: 0, mck2ui 16
3528 12:15:07.063431 best dqsien dly found for B1: ( 1, 3, 26)
3529 12:15:07.066690 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3530 12:15:07.070046 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3531 12:15:07.070607
3532 12:15:07.073751 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3533 12:15:07.076487 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3534 12:15:07.080503 [Gating] SW calibration Done
3535 12:15:07.080976 ==
3536 12:15:07.084510 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 12:15:07.086514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 12:15:07.087074 ==
3539 12:15:07.089956 RX Vref Scan: 0
3540 12:15:07.090511
3541 12:15:07.093115 RX Vref 0 -> 0, step: 1
3542 12:15:07.093678
3543 12:15:07.094056 RX Delay -40 -> 252, step: 8
3544 12:15:07.100047 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3545 12:15:07.103106 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3546 12:15:07.106690 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3547 12:15:07.110321 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3548 12:15:07.113118 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3549 12:15:07.119437 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3550 12:15:07.123287 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3551 12:15:07.127012 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3552 12:15:07.129818 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3553 12:15:07.133167 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3554 12:15:07.140625 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3555 12:15:07.143271 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3556 12:15:07.146709 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3557 12:15:07.149542 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3558 12:15:07.156370 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3559 12:15:07.159786 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3560 12:15:07.160262 ==
3561 12:15:07.163032 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 12:15:07.166134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 12:15:07.166704 ==
3564 12:15:07.169285 DQS Delay:
3565 12:15:07.169747 DQS0 = 0, DQS1 = 0
3566 12:15:07.170112 DQM Delay:
3567 12:15:07.172679 DQM0 = 116, DQM1 = 110
3568 12:15:07.173140 DQ Delay:
3569 12:15:07.175925 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =111
3570 12:15:07.179323 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3571 12:15:07.182643 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =103
3572 12:15:07.189640 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3573 12:15:07.190213
3574 12:15:07.190586
3575 12:15:07.190932 ==
3576 12:15:07.192997 Dram Type= 6, Freq= 0, CH_1, rank 1
3577 12:15:07.196000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3578 12:15:07.196469 ==
3579 12:15:07.197015
3580 12:15:07.197594
3581 12:15:07.198934 TX Vref Scan disable
3582 12:15:07.199395 == TX Byte 0 ==
3583 12:15:07.205385 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3584 12:15:07.208676 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3585 12:15:07.209146 == TX Byte 1 ==
3586 12:15:07.215265 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3587 12:15:07.219820 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3588 12:15:07.220391 ==
3589 12:15:07.222915 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 12:15:07.225355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 12:15:07.225924 ==
3592 12:15:07.238218 TX Vref=22, minBit 8, minWin=25, winSum=420
3593 12:15:07.242678 TX Vref=24, minBit 8, minWin=25, winSum=425
3594 12:15:07.245591 TX Vref=26, minBit 8, minWin=25, winSum=431
3595 12:15:07.248375 TX Vref=28, minBit 8, minWin=26, winSum=432
3596 12:15:07.251865 TX Vref=30, minBit 8, minWin=26, winSum=430
3597 12:15:07.258884 TX Vref=32, minBit 9, minWin=25, winSum=429
3598 12:15:07.261981 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 28
3599 12:15:07.262446
3600 12:15:07.264825 Final TX Range 1 Vref 28
3601 12:15:07.265293
3602 12:15:07.265658 ==
3603 12:15:07.267892 Dram Type= 6, Freq= 0, CH_1, rank 1
3604 12:15:07.271351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3605 12:15:07.274559 ==
3606 12:15:07.275204
3607 12:15:07.275581
3608 12:15:07.275983 TX Vref Scan disable
3609 12:15:07.278047 == TX Byte 0 ==
3610 12:15:07.281490 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3611 12:15:07.288004 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3612 12:15:07.288423 == TX Byte 1 ==
3613 12:15:07.291507 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3614 12:15:07.298309 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3615 12:15:07.298732
3616 12:15:07.299061 [DATLAT]
3617 12:15:07.299367 Freq=1200, CH1 RK1
3618 12:15:07.299701
3619 12:15:07.301356 DATLAT Default: 0xd
3620 12:15:07.304426 0, 0xFFFF, sum = 0
3621 12:15:07.304905 1, 0xFFFF, sum = 0
3622 12:15:07.307983 2, 0xFFFF, sum = 0
3623 12:15:07.308407 3, 0xFFFF, sum = 0
3624 12:15:07.311019 4, 0xFFFF, sum = 0
3625 12:15:07.311442 5, 0xFFFF, sum = 0
3626 12:15:07.314275 6, 0xFFFF, sum = 0
3627 12:15:07.314697 7, 0xFFFF, sum = 0
3628 12:15:07.317816 8, 0xFFFF, sum = 0
3629 12:15:07.318240 9, 0xFFFF, sum = 0
3630 12:15:07.321116 10, 0xFFFF, sum = 0
3631 12:15:07.321578 11, 0xFFFF, sum = 0
3632 12:15:07.324975 12, 0x0, sum = 1
3633 12:15:07.325400 13, 0x0, sum = 2
3634 12:15:07.328092 14, 0x0, sum = 3
3635 12:15:07.328518 15, 0x0, sum = 4
3636 12:15:07.330594 best_step = 13
3637 12:15:07.331013
3638 12:15:07.331349 ==
3639 12:15:07.334184 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 12:15:07.337974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 12:15:07.338396 ==
3642 12:15:07.340639 RX Vref Scan: 0
3643 12:15:07.341144
3644 12:15:07.341482 RX Vref 0 -> 0, step: 1
3645 12:15:07.341795
3646 12:15:07.344411 RX Delay -21 -> 252, step: 4
3647 12:15:07.351045 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3648 12:15:07.354059 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3649 12:15:07.358103 iDelay=199, Bit 2, Center 108 (43 ~ 174) 132
3650 12:15:07.360384 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3651 12:15:07.364203 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3652 12:15:07.370558 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3653 12:15:07.373798 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3654 12:15:07.377268 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3655 12:15:07.380554 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3656 12:15:07.383307 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3657 12:15:07.390353 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3658 12:15:07.393708 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3659 12:15:07.396916 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3660 12:15:07.400002 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3661 12:15:07.407544 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3662 12:15:07.410688 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3663 12:15:07.411254 ==
3664 12:15:07.413986 Dram Type= 6, Freq= 0, CH_1, rank 1
3665 12:15:07.416654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3666 12:15:07.417121 ==
3667 12:15:07.417484 DQS Delay:
3668 12:15:07.420272 DQS0 = 0, DQS1 = 0
3669 12:15:07.420733 DQM Delay:
3670 12:15:07.423360 DQM0 = 117, DQM1 = 110
3671 12:15:07.423862 DQ Delay:
3672 12:15:07.426725 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3673 12:15:07.429929 DQ4 =116, DQ5 =126, DQ6 =130, DQ7 =116
3674 12:15:07.433664 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =100
3675 12:15:07.440359 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =120
3676 12:15:07.440926
3677 12:15:07.441296
3678 12:15:07.447176 [DQSOSCAuto] RK1, (LSB)MR18= 0xf5f0, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
3679 12:15:07.450070 CH1 RK1: MR19=303, MR18=F5F0
3680 12:15:07.457559 CH1_RK1: MR19=0x303, MR18=0xF5F0, DQSOSC=414, MR23=63, INC=38, DEC=25
3681 12:15:07.459529 [RxdqsGatingPostProcess] freq 1200
3682 12:15:07.463666 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3683 12:15:07.466290 best DQS0 dly(2T, 0.5T) = (0, 11)
3684 12:15:07.469292 best DQS1 dly(2T, 0.5T) = (0, 11)
3685 12:15:07.472340 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3686 12:15:07.476395 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3687 12:15:07.479520 best DQS0 dly(2T, 0.5T) = (0, 11)
3688 12:15:07.482763 best DQS1 dly(2T, 0.5T) = (0, 11)
3689 12:15:07.486166 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3690 12:15:07.489598 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3691 12:15:07.492672 Pre-setting of DQS Precalculation
3692 12:15:07.496208 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3693 12:15:07.505888 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3694 12:15:07.512884 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3695 12:15:07.513452
3696 12:15:07.513823
3697 12:15:07.515978 [Calibration Summary] 2400 Mbps
3698 12:15:07.516444 CH 0, Rank 0
3699 12:15:07.519515 SW Impedance : PASS
3700 12:15:07.520142 DUTY Scan : NO K
3701 12:15:07.523668 ZQ Calibration : PASS
3702 12:15:07.525998 Jitter Meter : NO K
3703 12:15:07.526576 CBT Training : PASS
3704 12:15:07.529070 Write leveling : PASS
3705 12:15:07.532436 RX DQS gating : PASS
3706 12:15:07.532897 RX DQ/DQS(RDDQC) : PASS
3707 12:15:07.535605 TX DQ/DQS : PASS
3708 12:15:07.539132 RX DATLAT : PASS
3709 12:15:07.539751 RX DQ/DQS(Engine): PASS
3710 12:15:07.542149 TX OE : NO K
3711 12:15:07.542717 All Pass.
3712 12:15:07.543086
3713 12:15:07.545552 CH 0, Rank 1
3714 12:15:07.546119 SW Impedance : PASS
3715 12:15:07.548892 DUTY Scan : NO K
3716 12:15:07.552066 ZQ Calibration : PASS
3717 12:15:07.552682 Jitter Meter : NO K
3718 12:15:07.556688 CBT Training : PASS
3719 12:15:07.559134 Write leveling : PASS
3720 12:15:07.559751 RX DQS gating : PASS
3721 12:15:07.562398 RX DQ/DQS(RDDQC) : PASS
3722 12:15:07.565357 TX DQ/DQS : PASS
3723 12:15:07.565927 RX DATLAT : PASS
3724 12:15:07.568577 RX DQ/DQS(Engine): PASS
3725 12:15:07.572471 TX OE : NO K
3726 12:15:07.573041 All Pass.
3727 12:15:07.573409
3728 12:15:07.573751 CH 1, Rank 0
3729 12:15:07.575106 SW Impedance : PASS
3730 12:15:07.579075 DUTY Scan : NO K
3731 12:15:07.579727 ZQ Calibration : PASS
3732 12:15:07.581926 Jitter Meter : NO K
3733 12:15:07.585105 CBT Training : PASS
3734 12:15:07.585567 Write leveling : PASS
3735 12:15:07.588527 RX DQS gating : PASS
3736 12:15:07.589091 RX DQ/DQS(RDDQC) : PASS
3737 12:15:07.592026 TX DQ/DQS : PASS
3738 12:15:07.595077 RX DATLAT : PASS
3739 12:15:07.595643 RX DQ/DQS(Engine): PASS
3740 12:15:07.598335 TX OE : NO K
3741 12:15:07.598849 All Pass.
3742 12:15:07.599420
3743 12:15:07.601183 CH 1, Rank 1
3744 12:15:07.601640 SW Impedance : PASS
3745 12:15:07.604524 DUTY Scan : NO K
3746 12:15:07.608012 ZQ Calibration : PASS
3747 12:15:07.608491 Jitter Meter : NO K
3748 12:15:07.611545 CBT Training : PASS
3749 12:15:07.614537 Write leveling : PASS
3750 12:15:07.615095 RX DQS gating : PASS
3751 12:15:07.617956 RX DQ/DQS(RDDQC) : PASS
3752 12:15:07.620999 TX DQ/DQS : PASS
3753 12:15:07.621469 RX DATLAT : PASS
3754 12:15:07.624852 RX DQ/DQS(Engine): PASS
3755 12:15:07.628387 TX OE : NO K
3756 12:15:07.628868 All Pass.
3757 12:15:07.629240
3758 12:15:07.631340 DramC Write-DBI off
3759 12:15:07.631832 PER_BANK_REFRESH: Hybrid Mode
3760 12:15:07.634603 TX_TRACKING: ON
3761 12:15:07.641023 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3762 12:15:07.647517 [FAST_K] Save calibration result to emmc
3763 12:15:07.650892 dramc_set_vcore_voltage set vcore to 650000
3764 12:15:07.651454 Read voltage for 600, 5
3765 12:15:07.653943 Vio18 = 0
3766 12:15:07.654406 Vcore = 650000
3767 12:15:07.654772 Vdram = 0
3768 12:15:07.657173 Vddq = 0
3769 12:15:07.657637 Vmddr = 0
3770 12:15:07.660445 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3771 12:15:07.668043 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3772 12:15:07.670923 MEM_TYPE=3, freq_sel=19
3773 12:15:07.673771 sv_algorithm_assistance_LP4_1600
3774 12:15:07.676804 ============ PULL DRAM RESETB DOWN ============
3775 12:15:07.680630 ========== PULL DRAM RESETB DOWN end =========
3776 12:15:07.686752 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3777 12:15:07.690726 ===================================
3778 12:15:07.691153 LPDDR4 DRAM CONFIGURATION
3779 12:15:07.693738 ===================================
3780 12:15:07.696966 EX_ROW_EN[0] = 0x0
3781 12:15:07.700259 EX_ROW_EN[1] = 0x0
3782 12:15:07.700682 LP4Y_EN = 0x0
3783 12:15:07.703982 WORK_FSP = 0x0
3784 12:15:07.704492 WL = 0x2
3785 12:15:07.706467 RL = 0x2
3786 12:15:07.706888 BL = 0x2
3787 12:15:07.709962 RPST = 0x0
3788 12:15:07.710384 RD_PRE = 0x0
3789 12:15:07.713234 WR_PRE = 0x1
3790 12:15:07.713652 WR_PST = 0x0
3791 12:15:07.716716 DBI_WR = 0x0
3792 12:15:07.717138 DBI_RD = 0x0
3793 12:15:07.719766 OTF = 0x1
3794 12:15:07.723241 ===================================
3795 12:15:07.726754 ===================================
3796 12:15:07.727177 ANA top config
3797 12:15:07.729906 ===================================
3798 12:15:07.733052 DLL_ASYNC_EN = 0
3799 12:15:07.736589 ALL_SLAVE_EN = 1
3800 12:15:07.739594 NEW_RANK_MODE = 1
3801 12:15:07.740069 DLL_IDLE_MODE = 1
3802 12:15:07.743100 LP45_APHY_COMB_EN = 1
3803 12:15:07.746929 TX_ODT_DIS = 1
3804 12:15:07.749581 NEW_8X_MODE = 1
3805 12:15:07.753232 ===================================
3806 12:15:07.756184 ===================================
3807 12:15:07.759664 data_rate = 1200
3808 12:15:07.759786 CKR = 1
3809 12:15:07.762799 DQ_P2S_RATIO = 8
3810 12:15:07.765850 ===================================
3811 12:15:07.769557 CA_P2S_RATIO = 8
3812 12:15:07.772587 DQ_CA_OPEN = 0
3813 12:15:07.776136 DQ_SEMI_OPEN = 0
3814 12:15:07.779602 CA_SEMI_OPEN = 0
3815 12:15:07.779690 CA_FULL_RATE = 0
3816 12:15:07.782305 DQ_CKDIV4_EN = 1
3817 12:15:07.785694 CA_CKDIV4_EN = 1
3818 12:15:07.789293 CA_PREDIV_EN = 0
3819 12:15:07.792275 PH8_DLY = 0
3820 12:15:07.795296 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3821 12:15:07.795398 DQ_AAMCK_DIV = 4
3822 12:15:07.799390 CA_AAMCK_DIV = 4
3823 12:15:07.802990 CA_ADMCK_DIV = 4
3824 12:15:07.805229 DQ_TRACK_CA_EN = 0
3825 12:15:07.808987 CA_PICK = 600
3826 12:15:07.812386 CA_MCKIO = 600
3827 12:15:07.815494 MCKIO_SEMI = 0
3828 12:15:07.815646 PLL_FREQ = 2288
3829 12:15:07.818953 DQ_UI_PI_RATIO = 32
3830 12:15:07.822287 CA_UI_PI_RATIO = 0
3831 12:15:07.825262 ===================================
3832 12:15:07.828811 ===================================
3833 12:15:07.831939 memory_type:LPDDR4
3834 12:15:07.835420 GP_NUM : 10
3835 12:15:07.835752 SRAM_EN : 1
3836 12:15:07.838796 MD32_EN : 0
3837 12:15:07.842488 ===================================
3838 12:15:07.842956 [ANA_INIT] >>>>>>>>>>>>>>
3839 12:15:07.845400 <<<<<< [CONFIGURE PHASE]: ANA_TX
3840 12:15:07.848545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3841 12:15:07.852382 ===================================
3842 12:15:07.856239 data_rate = 1200,PCW = 0X5800
3843 12:15:07.859215 ===================================
3844 12:15:07.862035 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3845 12:15:07.869035 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3846 12:15:07.875245 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3847 12:15:07.878461 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3848 12:15:07.882014 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3849 12:15:07.885184 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3850 12:15:07.888463 [ANA_INIT] flow start
3851 12:15:07.888888 [ANA_INIT] PLL >>>>>>>>
3852 12:15:07.891618 [ANA_INIT] PLL <<<<<<<<
3853 12:15:07.895378 [ANA_INIT] MIDPI >>>>>>>>
3854 12:15:07.895844 [ANA_INIT] MIDPI <<<<<<<<
3855 12:15:07.898396 [ANA_INIT] DLL >>>>>>>>
3856 12:15:07.901702 [ANA_INIT] flow end
3857 12:15:07.905393 ============ LP4 DIFF to SE enter ============
3858 12:15:07.908150 ============ LP4 DIFF to SE exit ============
3859 12:15:07.911714 [ANA_INIT] <<<<<<<<<<<<<
3860 12:15:07.914698 [Flow] Enable top DCM control >>>>>
3861 12:15:07.917936 [Flow] Enable top DCM control <<<<<
3862 12:15:07.921602 Enable DLL master slave shuffle
3863 12:15:07.928190 ==============================================================
3864 12:15:07.928758 Gating Mode config
3865 12:15:07.934886 ==============================================================
3866 12:15:07.935480 Config description:
3867 12:15:07.944468 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3868 12:15:07.951080 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3869 12:15:07.958157 SELPH_MODE 0: By rank 1: By Phase
3870 12:15:07.961051 ==============================================================
3871 12:15:07.964395 GAT_TRACK_EN = 1
3872 12:15:07.967596 RX_GATING_MODE = 2
3873 12:15:07.971062 RX_GATING_TRACK_MODE = 2
3874 12:15:07.973876 SELPH_MODE = 1
3875 12:15:07.977843 PICG_EARLY_EN = 1
3876 12:15:07.981374 VALID_LAT_VALUE = 1
3877 12:15:07.987470 ==============================================================
3878 12:15:07.991098 Enter into Gating configuration >>>>
3879 12:15:07.993463 Exit from Gating configuration <<<<
3880 12:15:07.997002 Enter into DVFS_PRE_config >>>>>
3881 12:15:08.006978 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3882 12:15:08.011041 Exit from DVFS_PRE_config <<<<<
3883 12:15:08.013585 Enter into PICG configuration >>>>
3884 12:15:08.017005 Exit from PICG configuration <<<<
3885 12:15:08.020288 [RX_INPUT] configuration >>>>>
3886 12:15:08.020753 [RX_INPUT] configuration <<<<<
3887 12:15:08.026950 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3888 12:15:08.033875 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3889 12:15:08.037000 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3890 12:15:08.043468 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3891 12:15:08.049965 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3892 12:15:08.056978 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3893 12:15:08.060555 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3894 12:15:08.062963 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3895 12:15:08.070189 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3896 12:15:08.073192 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3897 12:15:08.076202 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3898 12:15:08.083333 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3899 12:15:08.086732 ===================================
3900 12:15:08.087197 LPDDR4 DRAM CONFIGURATION
3901 12:15:08.089740 ===================================
3902 12:15:08.092631 EX_ROW_EN[0] = 0x0
3903 12:15:08.096270 EX_ROW_EN[1] = 0x0
3904 12:15:08.096841 LP4Y_EN = 0x0
3905 12:15:08.099246 WORK_FSP = 0x0
3906 12:15:08.099750 WL = 0x2
3907 12:15:08.102539 RL = 0x2
3908 12:15:08.102999 BL = 0x2
3909 12:15:08.105676 RPST = 0x0
3910 12:15:08.106154 RD_PRE = 0x0
3911 12:15:08.109257 WR_PRE = 0x1
3912 12:15:08.109715 WR_PST = 0x0
3913 12:15:08.113667 DBI_WR = 0x0
3914 12:15:08.114250 DBI_RD = 0x0
3915 12:15:08.116319 OTF = 0x1
3916 12:15:08.119742 ===================================
3917 12:15:08.123229 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3918 12:15:08.125416 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3919 12:15:08.132244 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3920 12:15:08.135878 ===================================
3921 12:15:08.136397 LPDDR4 DRAM CONFIGURATION
3922 12:15:08.139769 ===================================
3923 12:15:08.142760 EX_ROW_EN[0] = 0x10
3924 12:15:08.145774 EX_ROW_EN[1] = 0x0
3925 12:15:08.146340 LP4Y_EN = 0x0
3926 12:15:08.148922 WORK_FSP = 0x0
3927 12:15:08.149478 WL = 0x2
3928 12:15:08.152412 RL = 0x2
3929 12:15:08.152976 BL = 0x2
3930 12:15:08.155067 RPST = 0x0
3931 12:15:08.155531 RD_PRE = 0x0
3932 12:15:08.158836 WR_PRE = 0x1
3933 12:15:08.159396 WR_PST = 0x0
3934 12:15:08.162548 DBI_WR = 0x0
3935 12:15:08.163108 DBI_RD = 0x0
3936 12:15:08.165232 OTF = 0x1
3937 12:15:08.169842 ===================================
3938 12:15:08.175722 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3939 12:15:08.178418 nWR fixed to 30
3940 12:15:08.182016 [ModeRegInit_LP4] CH0 RK0
3941 12:15:08.182575 [ModeRegInit_LP4] CH0 RK1
3942 12:15:08.184609 [ModeRegInit_LP4] CH1 RK0
3943 12:15:08.189135 [ModeRegInit_LP4] CH1 RK1
3944 12:15:08.189704 match AC timing 17
3945 12:15:08.194719 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3946 12:15:08.198201 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3947 12:15:08.201585 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3948 12:15:08.208063 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3949 12:15:08.211593 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3950 12:15:08.212108 ==
3951 12:15:08.214834 Dram Type= 6, Freq= 0, CH_0, rank 0
3952 12:15:08.218166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3953 12:15:08.218652 ==
3954 12:15:08.225220 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3955 12:15:08.231523 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3956 12:15:08.234497 [CA 0] Center 36 (6~66) winsize 61
3957 12:15:08.237911 [CA 1] Center 36 (6~66) winsize 61
3958 12:15:08.241481 [CA 2] Center 34 (4~65) winsize 62
3959 12:15:08.245196 [CA 3] Center 34 (3~65) winsize 63
3960 12:15:08.247991 [CA 4] Center 33 (3~64) winsize 62
3961 12:15:08.251147 [CA 5] Center 33 (3~64) winsize 62
3962 12:15:08.251818
3963 12:15:08.254268 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3964 12:15:08.254730
3965 12:15:08.258841 [CATrainingPosCal] consider 1 rank data
3966 12:15:08.261558 u2DelayCellTimex100 = 270/100 ps
3967 12:15:08.265425 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3968 12:15:08.267836 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3969 12:15:08.271633 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3970 12:15:08.274348 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3971 12:15:08.277959 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3972 12:15:08.284494 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3973 12:15:08.285056
3974 12:15:08.288010 CA PerBit enable=1, Macro0, CA PI delay=33
3975 12:15:08.288571
3976 12:15:08.290686 [CBTSetCACLKResult] CA Dly = 33
3977 12:15:08.291244 CS Dly: 6 (0~37)
3978 12:15:08.291616 ==
3979 12:15:08.294241 Dram Type= 6, Freq= 0, CH_0, rank 1
3980 12:15:08.297738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3981 12:15:08.300474 ==
3982 12:15:08.303874 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3983 12:15:08.311217 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3984 12:15:08.314328 [CA 0] Center 35 (5~66) winsize 62
3985 12:15:08.316910 [CA 1] Center 35 (5~66) winsize 62
3986 12:15:08.320304 [CA 2] Center 34 (4~64) winsize 61
3987 12:15:08.323837 [CA 3] Center 33 (3~64) winsize 62
3988 12:15:08.327125 [CA 4] Center 33 (3~64) winsize 62
3989 12:15:08.330498 [CA 5] Center 33 (2~64) winsize 63
3990 12:15:08.330962
3991 12:15:08.333750 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3992 12:15:08.334313
3993 12:15:08.336887 [CATrainingPosCal] consider 2 rank data
3994 12:15:08.340355 u2DelayCellTimex100 = 270/100 ps
3995 12:15:08.343849 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3996 12:15:08.347744 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3997 12:15:08.353603 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3998 12:15:08.356538 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3999 12:15:08.360025 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4000 12:15:08.364018 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4001 12:15:08.364443
4002 12:15:08.366915 CA PerBit enable=1, Macro0, CA PI delay=33
4003 12:15:08.367507
4004 12:15:08.370754 [CBTSetCACLKResult] CA Dly = 33
4005 12:15:08.371305 CS Dly: 5 (0~36)
4006 12:15:08.371811
4007 12:15:08.373109 ----->DramcWriteLeveling(PI) begin...
4008 12:15:08.377257 ==
4009 12:15:08.379785 Dram Type= 6, Freq= 0, CH_0, rank 0
4010 12:15:08.383213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4011 12:15:08.383855 ==
4012 12:15:08.386618 Write leveling (Byte 0): 37 => 37
4013 12:15:08.390750 Write leveling (Byte 1): 30 => 30
4014 12:15:08.394099 DramcWriteLeveling(PI) end<-----
4015 12:15:08.394522
4016 12:15:08.394854 ==
4017 12:15:08.396611 Dram Type= 6, Freq= 0, CH_0, rank 0
4018 12:15:08.399854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 12:15:08.400290 ==
4020 12:15:08.402823 [Gating] SW mode calibration
4021 12:15:08.409630 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4022 12:15:08.416435 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4023 12:15:08.419723 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4024 12:15:08.423990 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4025 12:15:08.426599 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4026 12:15:08.432906 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
4027 12:15:08.436278 0 9 16 | B1->B0 | 3030 2626 | 0 0 | (0 1) (0 0)
4028 12:15:08.440482 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 12:15:08.446933 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 12:15:08.449316 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 12:15:08.454028 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 12:15:08.459436 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 12:15:08.463058 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 12:15:08.466230 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 12:15:08.472851 0 10 16 | B1->B0 | 3737 4343 | 0 0 | (1 1) (0 0)
4036 12:15:08.475781 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 12:15:08.484060 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 12:15:08.486231 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 12:15:08.490234 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 12:15:08.492277 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 12:15:08.499109 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 12:15:08.502393 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4043 12:15:08.505951 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4044 12:15:08.512493 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 12:15:08.516066 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 12:15:08.519350 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 12:15:08.525596 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 12:15:08.528755 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 12:15:08.532514 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 12:15:08.538877 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 12:15:08.541628 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 12:15:08.545163 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 12:15:08.552429 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 12:15:08.554733 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 12:15:08.558628 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 12:15:08.564631 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 12:15:08.568636 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 12:15:08.571922 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 12:15:08.578594 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 12:15:08.581894 Total UI for P1: 0, mck2ui 16
4061 12:15:08.584842 best dqsien dly found for B0: ( 0, 13, 14)
4062 12:15:08.589354 Total UI for P1: 0, mck2ui 16
4063 12:15:08.591185 best dqsien dly found for B1: ( 0, 13, 14)
4064 12:15:08.594643 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4065 12:15:08.599182 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4066 12:15:08.599643
4067 12:15:08.601075 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4068 12:15:08.604308 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4069 12:15:08.607858 [Gating] SW calibration Done
4070 12:15:08.608431 ==
4071 12:15:08.611346 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 12:15:08.613973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 12:15:08.617975 ==
4074 12:15:08.618467 RX Vref Scan: 0
4075 12:15:08.618838
4076 12:15:08.620587 RX Vref 0 -> 0, step: 1
4077 12:15:08.621048
4078 12:15:08.624192 RX Delay -230 -> 252, step: 16
4079 12:15:08.627321 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4080 12:15:08.631168 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4081 12:15:08.634397 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4082 12:15:08.641149 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4083 12:15:08.643772 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4084 12:15:08.647527 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4085 12:15:08.650846 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4086 12:15:08.654123 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4087 12:15:08.660377 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4088 12:15:08.664073 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4089 12:15:08.667330 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4090 12:15:08.670519 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4091 12:15:08.676713 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4092 12:15:08.680182 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4093 12:15:08.683783 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4094 12:15:08.687022 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4095 12:15:08.690320 ==
4096 12:15:08.693402 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 12:15:08.696908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 12:15:08.697486 ==
4099 12:15:08.697889 DQS Delay:
4100 12:15:08.700005 DQS0 = 0, DQS1 = 0
4101 12:15:08.700465 DQM Delay:
4102 12:15:08.703253 DQM0 = 44, DQM1 = 34
4103 12:15:08.703765 DQ Delay:
4104 12:15:08.707128 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4105 12:15:08.709887 DQ4 =49, DQ5 =41, DQ6 =49, DQ7 =49
4106 12:15:08.713328 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4107 12:15:08.716565 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4108 12:15:08.717044
4109 12:15:08.717523
4110 12:15:08.717978 ==
4111 12:15:08.719649 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 12:15:08.722564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 12:15:08.723043 ==
4114 12:15:08.723526
4115 12:15:08.724021
4116 12:15:08.726287 TX Vref Scan disable
4117 12:15:08.729760 == TX Byte 0 ==
4118 12:15:08.732431 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4119 12:15:08.736273 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4120 12:15:08.739896 == TX Byte 1 ==
4121 12:15:08.743392 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4122 12:15:08.745925 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4123 12:15:08.746506 ==
4124 12:15:08.749413 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 12:15:08.755862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 12:15:08.756458 ==
4127 12:15:08.756954
4128 12:15:08.757406
4129 12:15:08.758937 TX Vref Scan disable
4130 12:15:08.759410 == TX Byte 0 ==
4131 12:15:08.765685 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4132 12:15:08.769064 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4133 12:15:08.771616 == TX Byte 1 ==
4134 12:15:08.775107 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4135 12:15:08.778566 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4136 12:15:08.779126
4137 12:15:08.779498 [DATLAT]
4138 12:15:08.782109 Freq=600, CH0 RK0
4139 12:15:08.782666
4140 12:15:08.786317 DATLAT Default: 0x9
4141 12:15:08.786949 0, 0xFFFF, sum = 0
4142 12:15:08.788761 1, 0xFFFF, sum = 0
4143 12:15:08.789236 2, 0xFFFF, sum = 0
4144 12:15:08.792292 3, 0xFFFF, sum = 0
4145 12:15:08.792857 4, 0xFFFF, sum = 0
4146 12:15:08.795428 5, 0xFFFF, sum = 0
4147 12:15:08.796051 6, 0xFFFF, sum = 0
4148 12:15:08.798050 7, 0xFFFF, sum = 0
4149 12:15:08.798620 8, 0x0, sum = 1
4150 12:15:08.801999 9, 0x0, sum = 2
4151 12:15:08.802569 10, 0x0, sum = 3
4152 12:15:08.804627 11, 0x0, sum = 4
4153 12:15:08.805102 best_step = 9
4154 12:15:08.805475
4155 12:15:08.805820 ==
4156 12:15:08.808017 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 12:15:08.811751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 12:15:08.812330 ==
4159 12:15:08.814885 RX Vref Scan: 1
4160 12:15:08.815449
4161 12:15:08.818801 RX Vref 0 -> 0, step: 1
4162 12:15:08.819392
4163 12:15:08.819951 RX Delay -195 -> 252, step: 8
4164 12:15:08.821411
4165 12:15:08.821924 Set Vref, RX VrefLevel [Byte0]: 61
4166 12:15:08.824350 [Byte1]: 49
4167 12:15:08.829629
4168 12:15:08.830188 Final RX Vref Byte 0 = 61 to rank0
4169 12:15:08.834299 Final RX Vref Byte 1 = 49 to rank0
4170 12:15:08.836559 Final RX Vref Byte 0 = 61 to rank1
4171 12:15:08.839778 Final RX Vref Byte 1 = 49 to rank1==
4172 12:15:08.842979 Dram Type= 6, Freq= 0, CH_0, rank 0
4173 12:15:08.849635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 12:15:08.850203 ==
4175 12:15:08.850576 DQS Delay:
4176 12:15:08.850916 DQS0 = 0, DQS1 = 0
4177 12:15:08.853178 DQM Delay:
4178 12:15:08.853643 DQM0 = 44, DQM1 = 32
4179 12:15:08.856102 DQ Delay:
4180 12:15:08.859304 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4181 12:15:08.863077 DQ4 =48, DQ5 =32, DQ6 =52, DQ7 =52
4182 12:15:08.863636 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =24
4183 12:15:08.869217 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4184 12:15:08.869937
4185 12:15:08.870322
4186 12:15:08.876037 [DQSOSCAuto] RK0, (LSB)MR18= 0x6840, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 390 ps
4187 12:15:08.879346 CH0 RK0: MR19=808, MR18=6840
4188 12:15:08.886039 CH0_RK0: MR19=0x808, MR18=0x6840, DQSOSC=390, MR23=63, INC=172, DEC=114
4189 12:15:08.886606
4190 12:15:08.889167 ----->DramcWriteLeveling(PI) begin...
4191 12:15:08.889731 ==
4192 12:15:08.892531 Dram Type= 6, Freq= 0, CH_0, rank 1
4193 12:15:08.895553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 12:15:08.896155 ==
4195 12:15:08.899033 Write leveling (Byte 0): 32 => 32
4196 12:15:08.903654 Write leveling (Byte 1): 30 => 30
4197 12:15:08.905313 DramcWriteLeveling(PI) end<-----
4198 12:15:08.905780
4199 12:15:08.906149 ==
4200 12:15:08.908998 Dram Type= 6, Freq= 0, CH_0, rank 1
4201 12:15:08.911841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 12:15:08.915920 ==
4203 12:15:08.916508 [Gating] SW mode calibration
4204 12:15:08.922830 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4205 12:15:08.929217 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4206 12:15:08.931796 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4207 12:15:08.938366 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4208 12:15:08.941713 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4209 12:15:08.945287 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
4210 12:15:08.951696 0 9 16 | B1->B0 | 2d2d 2424 | 0 1 | (1 1) (1 0)
4211 12:15:08.954636 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 12:15:08.958299 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 12:15:08.965275 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 12:15:08.968386 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 12:15:08.971510 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 12:15:08.977994 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 12:15:08.981613 0 10 12 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
4218 12:15:08.984347 0 10 16 | B1->B0 | 3a3a 3d3d | 0 1 | (0 0) (1 1)
4219 12:15:08.991769 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 12:15:08.994851 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 12:15:08.998329 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 12:15:09.004446 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 12:15:09.007785 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 12:15:09.011036 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 12:15:09.017476 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4226 12:15:09.020756 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4227 12:15:09.024174 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 12:15:09.030754 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 12:15:09.034474 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 12:15:09.037412 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 12:15:09.044465 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 12:15:09.047216 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 12:15:09.050348 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 12:15:09.057502 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 12:15:09.060558 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 12:15:09.064071 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 12:15:09.070197 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 12:15:09.073809 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 12:15:09.076792 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 12:15:09.083201 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 12:15:09.087427 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4242 12:15:09.090116 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4243 12:15:09.093151 Total UI for P1: 0, mck2ui 16
4244 12:15:09.096302 best dqsien dly found for B0: ( 0, 13, 12)
4245 12:15:09.102804 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 12:15:09.106305 Total UI for P1: 0, mck2ui 16
4247 12:15:09.110304 best dqsien dly found for B1: ( 0, 13, 16)
4248 12:15:09.112648 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4249 12:15:09.116042 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4250 12:15:09.116520
4251 12:15:09.119092 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4252 12:15:09.122489 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4253 12:15:09.125593 [Gating] SW calibration Done
4254 12:15:09.126144 ==
4255 12:15:09.129239 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 12:15:09.132370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 12:15:09.132850 ==
4258 12:15:09.136250 RX Vref Scan: 0
4259 12:15:09.136829
4260 12:15:09.139018 RX Vref 0 -> 0, step: 1
4261 12:15:09.139493
4262 12:15:09.142431 RX Delay -230 -> 252, step: 16
4263 12:15:09.145433 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4264 12:15:09.148795 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4265 12:15:09.152311 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4266 12:15:09.159394 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4267 12:15:09.162133 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4268 12:15:09.165225 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4269 12:15:09.168800 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4270 12:15:09.171791 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4271 12:15:09.178725 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4272 12:15:09.182197 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4273 12:15:09.184822 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4274 12:15:09.188814 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4275 12:15:09.194807 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4276 12:15:09.198115 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4277 12:15:09.201600 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4278 12:15:09.204491 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4279 12:15:09.207893 ==
4280 12:15:09.211595 Dram Type= 6, Freq= 0, CH_0, rank 1
4281 12:15:09.214331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4282 12:15:09.214752 ==
4283 12:15:09.215084 DQS Delay:
4284 12:15:09.217957 DQS0 = 0, DQS1 = 0
4285 12:15:09.218377 DQM Delay:
4286 12:15:09.221351 DQM0 = 41, DQM1 = 34
4287 12:15:09.221768 DQ Delay:
4288 12:15:09.224526 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4289 12:15:09.227656 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4290 12:15:09.231423 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4291 12:15:09.234661 DQ12 =33, DQ13 =49, DQ14 =49, DQ15 =33
4292 12:15:09.235076
4293 12:15:09.235402
4294 12:15:09.235755 ==
4295 12:15:09.238136 Dram Type= 6, Freq= 0, CH_0, rank 1
4296 12:15:09.240824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4297 12:15:09.241242 ==
4298 12:15:09.241574
4299 12:15:09.241880
4300 12:15:09.244584 TX Vref Scan disable
4301 12:15:09.247618 == TX Byte 0 ==
4302 12:15:09.250956 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4303 12:15:09.254319 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4304 12:15:09.257245 == TX Byte 1 ==
4305 12:15:09.261125 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4306 12:15:09.263877 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4307 12:15:09.263959 ==
4308 12:15:09.267493 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 12:15:09.273996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 12:15:09.274077 ==
4311 12:15:09.274140
4312 12:15:09.274199
4313 12:15:09.274256 TX Vref Scan disable
4314 12:15:09.277692 == TX Byte 0 ==
4315 12:15:09.281360 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4316 12:15:09.287842 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4317 12:15:09.287928 == TX Byte 1 ==
4318 12:15:09.290995 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4319 12:15:09.297489 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4320 12:15:09.297570
4321 12:15:09.297634 [DATLAT]
4322 12:15:09.297693 Freq=600, CH0 RK1
4323 12:15:09.297750
4324 12:15:09.300787 DATLAT Default: 0x9
4325 12:15:09.304661 0, 0xFFFF, sum = 0
4326 12:15:09.304750 1, 0xFFFF, sum = 0
4327 12:15:09.307613 2, 0xFFFF, sum = 0
4328 12:15:09.307732 3, 0xFFFF, sum = 0
4329 12:15:09.311725 4, 0xFFFF, sum = 0
4330 12:15:09.312151 5, 0xFFFF, sum = 0
4331 12:15:09.314233 6, 0xFFFF, sum = 0
4332 12:15:09.314653 7, 0xFFFF, sum = 0
4333 12:15:09.318075 8, 0x0, sum = 1
4334 12:15:09.318497 9, 0x0, sum = 2
4335 12:15:09.321028 10, 0x0, sum = 3
4336 12:15:09.321447 11, 0x0, sum = 4
4337 12:15:09.321787 best_step = 9
4338 12:15:09.322096
4339 12:15:09.324292 ==
4340 12:15:09.328145 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 12:15:09.331417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 12:15:09.331874 ==
4343 12:15:09.332212 RX Vref Scan: 0
4344 12:15:09.332516
4345 12:15:09.334264 RX Vref 0 -> 0, step: 1
4346 12:15:09.334676
4347 12:15:09.337458 RX Delay -179 -> 252, step: 8
4348 12:15:09.344877 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4349 12:15:09.347636 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4350 12:15:09.350821 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4351 12:15:09.354190 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4352 12:15:09.357471 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4353 12:15:09.364568 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4354 12:15:09.368062 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4355 12:15:09.371045 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4356 12:15:09.374367 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4357 12:15:09.381055 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4358 12:15:09.384061 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4359 12:15:09.387626 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4360 12:15:09.390443 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4361 12:15:09.397658 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4362 12:15:09.400492 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4363 12:15:09.403612 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4364 12:15:09.404212 ==
4365 12:15:09.407091 Dram Type= 6, Freq= 0, CH_0, rank 1
4366 12:15:09.409914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 12:15:09.413647 ==
4368 12:15:09.414149 DQS Delay:
4369 12:15:09.414519 DQS0 = 0, DQS1 = 0
4370 12:15:09.417020 DQM Delay:
4371 12:15:09.417479 DQM0 = 41, DQM1 = 37
4372 12:15:09.419879 DQ Delay:
4373 12:15:09.420336 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4374 12:15:09.423717 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4375 12:15:09.426575 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4376 12:15:09.430163 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4377 12:15:09.433015
4378 12:15:09.433470
4379 12:15:09.439606 [DQSOSCAuto] RK1, (LSB)MR18= 0x6114, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4380 12:15:09.443404 CH0 RK1: MR19=808, MR18=6114
4381 12:15:09.449784 CH0_RK1: MR19=0x808, MR18=0x6114, DQSOSC=391, MR23=63, INC=171, DEC=114
4382 12:15:09.452748 [RxdqsGatingPostProcess] freq 600
4383 12:15:09.455833 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4384 12:15:09.459447 Pre-setting of DQS Precalculation
4385 12:15:09.466476 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4386 12:15:09.466984 ==
4387 12:15:09.469381 Dram Type= 6, Freq= 0, CH_1, rank 0
4388 12:15:09.472840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 12:15:09.473263 ==
4390 12:15:09.479239 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4391 12:15:09.486213 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4392 12:15:09.489291 [CA 0] Center 35 (5~66) winsize 62
4393 12:15:09.492861 [CA 1] Center 35 (5~66) winsize 62
4394 12:15:09.495321 [CA 2] Center 34 (3~65) winsize 63
4395 12:15:09.498630 [CA 3] Center 33 (3~64) winsize 62
4396 12:15:09.502214 [CA 4] Center 34 (4~64) winsize 61
4397 12:15:09.505864 [CA 5] Center 33 (3~64) winsize 62
4398 12:15:09.506491
4399 12:15:09.508660 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4400 12:15:09.509079
4401 12:15:09.512177 [CATrainingPosCal] consider 1 rank data
4402 12:15:09.515778 u2DelayCellTimex100 = 270/100 ps
4403 12:15:09.518298 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4404 12:15:09.521950 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4405 12:15:09.525244 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4406 12:15:09.528500 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4407 12:15:09.531648 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4408 12:15:09.535825 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4409 12:15:09.536347
4410 12:15:09.541892 CA PerBit enable=1, Macro0, CA PI delay=33
4411 12:15:09.542424
4412 12:15:09.545450 [CBTSetCACLKResult] CA Dly = 33
4413 12:15:09.545976 CS Dly: 5 (0~36)
4414 12:15:09.546313 ==
4415 12:15:09.548286 Dram Type= 6, Freq= 0, CH_1, rank 1
4416 12:15:09.551596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4417 12:15:09.552048 ==
4418 12:15:09.558947 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4419 12:15:09.565094 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4420 12:15:09.568288 [CA 0] Center 35 (5~66) winsize 62
4421 12:15:09.571948 [CA 1] Center 36 (6~66) winsize 61
4422 12:15:09.574842 [CA 2] Center 34 (4~65) winsize 62
4423 12:15:09.577879 [CA 3] Center 34 (4~64) winsize 61
4424 12:15:09.581218 [CA 4] Center 34 (4~65) winsize 62
4425 12:15:09.584656 [CA 5] Center 34 (3~65) winsize 63
4426 12:15:09.585075
4427 12:15:09.588022 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4428 12:15:09.588545
4429 12:15:09.591337 [CATrainingPosCal] consider 2 rank data
4430 12:15:09.594965 u2DelayCellTimex100 = 270/100 ps
4431 12:15:09.599479 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4432 12:15:09.600885 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4433 12:15:09.604335 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4434 12:15:09.611036 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4435 12:15:09.614045 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4436 12:15:09.618060 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4437 12:15:09.618581
4438 12:15:09.620772 CA PerBit enable=1, Macro0, CA PI delay=33
4439 12:15:09.621190
4440 12:15:09.625011 [CBTSetCACLKResult] CA Dly = 33
4441 12:15:09.625432 CS Dly: 5 (0~37)
4442 12:15:09.625769
4443 12:15:09.627317 ----->DramcWriteLeveling(PI) begin...
4444 12:15:09.627787 ==
4445 12:15:09.631094 Dram Type= 6, Freq= 0, CH_1, rank 0
4446 12:15:09.637515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4447 12:15:09.638026 ==
4448 12:15:09.640662 Write leveling (Byte 0): 31 => 31
4449 12:15:09.643977 Write leveling (Byte 1): 30 => 30
4450 12:15:09.644394 DramcWriteLeveling(PI) end<-----
4451 12:15:09.647621
4452 12:15:09.648137 ==
4453 12:15:09.652209 Dram Type= 6, Freq= 0, CH_1, rank 0
4454 12:15:09.654602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4455 12:15:09.655133 ==
4456 12:15:09.657564 [Gating] SW mode calibration
4457 12:15:09.664103 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4458 12:15:09.667534 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4459 12:15:09.674283 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4460 12:15:09.677433 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4461 12:15:09.681392 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4462 12:15:09.687234 0 9 12 | B1->B0 | 2e2e 2f2f | 1 1 | (1 1) (1 1)
4463 12:15:09.690962 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4464 12:15:09.694183 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 12:15:09.700341 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 12:15:09.704049 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 12:15:09.706816 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 12:15:09.713824 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 12:15:09.717195 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 12:15:09.720179 0 10 12 | B1->B0 | 2727 4141 | 0 0 | (0 0) (1 1)
4471 12:15:09.726905 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 12:15:09.730472 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 12:15:09.733714 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 12:15:09.740500 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 12:15:09.743033 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 12:15:09.746932 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 12:15:09.753888 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 12:15:09.756347 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4479 12:15:09.759311 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 12:15:09.766364 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 12:15:09.769565 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 12:15:09.773247 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 12:15:09.779982 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 12:15:09.783454 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 12:15:09.785989 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 12:15:09.793052 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 12:15:09.795840 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 12:15:09.799844 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 12:15:09.806315 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 12:15:09.809346 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 12:15:09.812910 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 12:15:09.819296 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 12:15:09.822665 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 12:15:09.825385 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4495 12:15:09.832805 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 12:15:09.835408 Total UI for P1: 0, mck2ui 16
4497 12:15:09.839634 best dqsien dly found for B0: ( 0, 13, 12)
4498 12:15:09.842520 Total UI for P1: 0, mck2ui 16
4499 12:15:09.845697 best dqsien dly found for B1: ( 0, 13, 14)
4500 12:15:09.849284 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4501 12:15:09.852461 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4502 12:15:09.853026
4503 12:15:09.855977 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4504 12:15:09.858871 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4505 12:15:09.862139 [Gating] SW calibration Done
4506 12:15:09.862706 ==
4507 12:15:09.865917 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 12:15:09.869343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 12:15:09.869915 ==
4510 12:15:09.872349 RX Vref Scan: 0
4511 12:15:09.872912
4512 12:15:09.875295 RX Vref 0 -> 0, step: 1
4513 12:15:09.875899
4514 12:15:09.876277 RX Delay -230 -> 252, step: 16
4515 12:15:09.882802 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4516 12:15:09.885472 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4517 12:15:09.888528 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4518 12:15:09.891363 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4519 12:15:09.897968 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4520 12:15:09.901534 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4521 12:15:09.904981 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4522 12:15:09.908633 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4523 12:15:09.914821 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4524 12:15:09.918109 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4525 12:15:09.921522 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4526 12:15:09.924587 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4527 12:15:09.932071 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4528 12:15:09.934778 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4529 12:15:09.937771 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4530 12:15:09.941632 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4531 12:15:09.942327 ==
4532 12:15:09.944435 Dram Type= 6, Freq= 0, CH_1, rank 0
4533 12:15:09.951116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4534 12:15:09.951713 ==
4535 12:15:09.952100 DQS Delay:
4536 12:15:09.955247 DQS0 = 0, DQS1 = 0
4537 12:15:09.955847 DQM Delay:
4538 12:15:09.956226 DQM0 = 45, DQM1 = 38
4539 12:15:09.958066 DQ Delay:
4540 12:15:09.961267 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4541 12:15:09.964530 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4542 12:15:09.967814 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25
4543 12:15:09.971119 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4544 12:15:09.971713
4545 12:15:09.972089
4546 12:15:09.972433 ==
4547 12:15:09.974563 Dram Type= 6, Freq= 0, CH_1, rank 0
4548 12:15:09.977922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4549 12:15:09.978393 ==
4550 12:15:09.978763
4551 12:15:09.979103
4552 12:15:09.981292 TX Vref Scan disable
4553 12:15:09.981758 == TX Byte 0 ==
4554 12:15:09.987757 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4555 12:15:09.991246 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4556 12:15:09.991847 == TX Byte 1 ==
4557 12:15:09.997657 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4558 12:15:10.001168 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4559 12:15:10.001635 ==
4560 12:15:10.004532 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 12:15:10.007601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 12:15:10.008199 ==
4563 12:15:10.010997
4564 12:15:10.011473
4565 12:15:10.011902 TX Vref Scan disable
4566 12:15:10.014102 == TX Byte 0 ==
4567 12:15:10.018072 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4568 12:15:10.024441 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4569 12:15:10.024934 == TX Byte 1 ==
4570 12:15:10.027408 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4571 12:15:10.034595 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4572 12:15:10.035166
4573 12:15:10.035537 [DATLAT]
4574 12:15:10.035950 Freq=600, CH1 RK0
4575 12:15:10.036295
4576 12:15:10.037741 DATLAT Default: 0x9
4577 12:15:10.038209 0, 0xFFFF, sum = 0
4578 12:15:10.041436 1, 0xFFFF, sum = 0
4579 12:15:10.042023 2, 0xFFFF, sum = 0
4580 12:15:10.044141 3, 0xFFFF, sum = 0
4581 12:15:10.047904 4, 0xFFFF, sum = 0
4582 12:15:10.048469 5, 0xFFFF, sum = 0
4583 12:15:10.051379 6, 0xFFFF, sum = 0
4584 12:15:10.052014 7, 0xFFFF, sum = 0
4585 12:15:10.054590 8, 0x0, sum = 1
4586 12:15:10.055133 9, 0x0, sum = 2
4587 12:15:10.055515 10, 0x0, sum = 3
4588 12:15:10.057132 11, 0x0, sum = 4
4589 12:15:10.057603 best_step = 9
4590 12:15:10.057972
4591 12:15:10.058317 ==
4592 12:15:10.061513 Dram Type= 6, Freq= 0, CH_1, rank 0
4593 12:15:10.067432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 12:15:10.067955 ==
4595 12:15:10.068335 RX Vref Scan: 1
4596 12:15:10.068683
4597 12:15:10.070565 RX Vref 0 -> 0, step: 1
4598 12:15:10.071123
4599 12:15:10.074248 RX Delay -195 -> 252, step: 8
4600 12:15:10.074806
4601 12:15:10.077849 Set Vref, RX VrefLevel [Byte0]: 50
4602 12:15:10.080731 [Byte1]: 56
4603 12:15:10.081295
4604 12:15:10.083924 Final RX Vref Byte 0 = 50 to rank0
4605 12:15:10.087549 Final RX Vref Byte 1 = 56 to rank0
4606 12:15:10.090653 Final RX Vref Byte 0 = 50 to rank1
4607 12:15:10.094073 Final RX Vref Byte 1 = 56 to rank1==
4608 12:15:10.097571 Dram Type= 6, Freq= 0, CH_1, rank 0
4609 12:15:10.100494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 12:15:10.100962 ==
4611 12:15:10.104243 DQS Delay:
4612 12:15:10.104707 DQS0 = 0, DQS1 = 0
4613 12:15:10.106988 DQM Delay:
4614 12:15:10.107571 DQM0 = 45, DQM1 = 35
4615 12:15:10.108024 DQ Delay:
4616 12:15:10.110330 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =40
4617 12:15:10.113368 DQ4 =44, DQ5 =52, DQ6 =52, DQ7 =44
4618 12:15:10.117061 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =24
4619 12:15:10.119935 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4620 12:15:10.120430
4621 12:15:10.120803
4622 12:15:10.130334 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d32, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4623 12:15:10.134015 CH1 RK0: MR19=808, MR18=4D32
4624 12:15:10.140206 CH1_RK0: MR19=0x808, MR18=0x4D32, DQSOSC=395, MR23=63, INC=168, DEC=112
4625 12:15:10.140772
4626 12:15:10.143139 ----->DramcWriteLeveling(PI) begin...
4627 12:15:10.143734 ==
4628 12:15:10.146822 Dram Type= 6, Freq= 0, CH_1, rank 1
4629 12:15:10.149797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4630 12:15:10.150269 ==
4631 12:15:10.153405 Write leveling (Byte 0): 30 => 30
4632 12:15:10.156412 Write leveling (Byte 1): 30 => 30
4633 12:15:10.159819 DramcWriteLeveling(PI) end<-----
4634 12:15:10.160285
4635 12:15:10.160656 ==
4636 12:15:10.162930 Dram Type= 6, Freq= 0, CH_1, rank 1
4637 12:15:10.166287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 12:15:10.166853 ==
4639 12:15:10.169490 [Gating] SW mode calibration
4640 12:15:10.175805 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4641 12:15:10.182812 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4642 12:15:10.185850 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4643 12:15:10.192355 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4644 12:15:10.195576 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4645 12:15:10.199341 0 9 12 | B1->B0 | 3030 3333 | 1 1 | (0 0) (1 0)
4646 12:15:10.205842 0 9 16 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
4647 12:15:10.208877 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 12:15:10.212283 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 12:15:10.218762 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 12:15:10.222102 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 12:15:10.225479 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 12:15:10.232149 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 12:15:10.235406 0 10 12 | B1->B0 | 3131 2a2a | 0 1 | (1 1) (0 0)
4654 12:15:10.239044 0 10 16 | B1->B0 | 4646 4141 | 0 1 | (0 0) (0 0)
4655 12:15:10.245438 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 12:15:10.248442 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 12:15:10.251971 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 12:15:10.258264 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 12:15:10.261563 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 12:15:10.265104 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 12:15:10.268856 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4662 12:15:10.275871 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 12:15:10.278167 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 12:15:10.282119 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 12:15:10.288158 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 12:15:10.291844 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 12:15:10.294786 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 12:15:10.301576 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 12:15:10.304711 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 12:15:10.308294 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 12:15:10.314762 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 12:15:10.319076 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 12:15:10.321281 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 12:15:10.327765 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 12:15:10.331461 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 12:15:10.335518 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 12:15:10.341910 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4678 12:15:10.343984 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 12:15:10.347761 Total UI for P1: 0, mck2ui 16
4680 12:15:10.350910 best dqsien dly found for B0: ( 0, 13, 12)
4681 12:15:10.354721 Total UI for P1: 0, mck2ui 16
4682 12:15:10.357406 best dqsien dly found for B1: ( 0, 13, 12)
4683 12:15:10.360531 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4684 12:15:10.364254 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4685 12:15:10.364996
4686 12:15:10.370642 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4687 12:15:10.374969 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4688 12:15:10.375532 [Gating] SW calibration Done
4689 12:15:10.377862 ==
4690 12:15:10.381030 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 12:15:10.384031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 12:15:10.384593 ==
4693 12:15:10.384968 RX Vref Scan: 0
4694 12:15:10.385313
4695 12:15:10.387297 RX Vref 0 -> 0, step: 1
4696 12:15:10.387906
4697 12:15:10.390460 RX Delay -230 -> 252, step: 16
4698 12:15:10.393871 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4699 12:15:10.396914 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4700 12:15:10.404478 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4701 12:15:10.407151 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4702 12:15:10.410474 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4703 12:15:10.413378 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4704 12:15:10.420356 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4705 12:15:10.423884 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4706 12:15:10.426709 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4707 12:15:10.430339 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4708 12:15:10.434092 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4709 12:15:10.440450 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4710 12:15:10.444263 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4711 12:15:10.447654 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4712 12:15:10.450096 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4713 12:15:10.457409 iDelay=218, Bit 15, Center 41 (-134 ~ 217) 352
4714 12:15:10.457870 ==
4715 12:15:10.459557 Dram Type= 6, Freq= 0, CH_1, rank 1
4716 12:15:10.463416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4717 12:15:10.464026 ==
4718 12:15:10.464399 DQS Delay:
4719 12:15:10.466587 DQS0 = 0, DQS1 = 0
4720 12:15:10.467148 DQM Delay:
4721 12:15:10.469638 DQM0 = 39, DQM1 = 35
4722 12:15:10.470095 DQ Delay:
4723 12:15:10.473174 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =41
4724 12:15:10.475977 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4725 12:15:10.479339 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4726 12:15:10.482826 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4727 12:15:10.483388
4728 12:15:10.483793
4729 12:15:10.484136 ==
4730 12:15:10.486543 Dram Type= 6, Freq= 0, CH_1, rank 1
4731 12:15:10.492770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4732 12:15:10.493296 ==
4733 12:15:10.493631
4734 12:15:10.493936
4735 12:15:10.494230 TX Vref Scan disable
4736 12:15:10.496232 == TX Byte 0 ==
4737 12:15:10.499659 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4738 12:15:10.506161 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4739 12:15:10.506643 == TX Byte 1 ==
4740 12:15:10.509083 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4741 12:15:10.515807 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4742 12:15:10.516230 ==
4743 12:15:10.520069 Dram Type= 6, Freq= 0, CH_1, rank 1
4744 12:15:10.523149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4745 12:15:10.523569 ==
4746 12:15:10.523972
4747 12:15:10.524291
4748 12:15:10.525694 TX Vref Scan disable
4749 12:15:10.528918 == TX Byte 0 ==
4750 12:15:10.532233 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4751 12:15:10.535616 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4752 12:15:10.538828 == TX Byte 1 ==
4753 12:15:10.541994 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4754 12:15:10.545288 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4755 12:15:10.545708
4756 12:15:10.546038 [DATLAT]
4757 12:15:10.548502 Freq=600, CH1 RK1
4758 12:15:10.548800
4759 12:15:10.552480 DATLAT Default: 0x9
4760 12:15:10.552898 0, 0xFFFF, sum = 0
4761 12:15:10.555429 1, 0xFFFF, sum = 0
4762 12:15:10.555745 2, 0xFFFF, sum = 0
4763 12:15:10.559491 3, 0xFFFF, sum = 0
4764 12:15:10.559871 4, 0xFFFF, sum = 0
4765 12:15:10.562095 5, 0xFFFF, sum = 0
4766 12:15:10.562492 6, 0xFFFF, sum = 0
4767 12:15:10.565339 7, 0xFFFF, sum = 0
4768 12:15:10.565738 8, 0x0, sum = 1
4769 12:15:10.568343 9, 0x0, sum = 2
4770 12:15:10.568641 10, 0x0, sum = 3
4771 12:15:10.571793 11, 0x0, sum = 4
4772 12:15:10.572245 best_step = 9
4773 12:15:10.572552
4774 12:15:10.572875 ==
4775 12:15:10.575077 Dram Type= 6, Freq= 0, CH_1, rank 1
4776 12:15:10.578181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4777 12:15:10.578477 ==
4778 12:15:10.581681 RX Vref Scan: 0
4779 12:15:10.581994
4780 12:15:10.584883 RX Vref 0 -> 0, step: 1
4781 12:15:10.585175
4782 12:15:10.585409 RX Delay -195 -> 252, step: 8
4783 12:15:10.593192 iDelay=213, Bit 0, Center 44 (-107 ~ 196) 304
4784 12:15:10.596546 iDelay=213, Bit 1, Center 36 (-115 ~ 188) 304
4785 12:15:10.599699 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4786 12:15:10.602677 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4787 12:15:10.610459 iDelay=213, Bit 4, Center 40 (-115 ~ 196) 312
4788 12:15:10.612927 iDelay=213, Bit 5, Center 52 (-99 ~ 204) 304
4789 12:15:10.615916 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4790 12:15:10.619413 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4791 12:15:10.622874 iDelay=213, Bit 8, Center 20 (-139 ~ 180) 320
4792 12:15:10.629739 iDelay=213, Bit 9, Center 20 (-139 ~ 180) 320
4793 12:15:10.633309 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4794 12:15:10.636542 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4795 12:15:10.639517 iDelay=213, Bit 12, Center 44 (-115 ~ 204) 320
4796 12:15:10.646312 iDelay=213, Bit 13, Center 40 (-115 ~ 196) 312
4797 12:15:10.649089 iDelay=213, Bit 14, Center 40 (-115 ~ 196) 312
4798 12:15:10.652955 iDelay=213, Bit 15, Center 44 (-115 ~ 204) 320
4799 12:15:10.653481 ==
4800 12:15:10.655761 Dram Type= 6, Freq= 0, CH_1, rank 1
4801 12:15:10.662640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4802 12:15:10.663206 ==
4803 12:15:10.663573 DQS Delay:
4804 12:15:10.663959 DQS0 = 0, DQS1 = 0
4805 12:15:10.665984 DQM Delay:
4806 12:15:10.666549 DQM0 = 43, DQM1 = 33
4807 12:15:10.668735 DQ Delay:
4808 12:15:10.672737 DQ0 =44, DQ1 =36, DQ2 =32, DQ3 =40
4809 12:15:10.675730 DQ4 =40, DQ5 =52, DQ6 =60, DQ7 =40
4810 12:15:10.679525 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4811 12:15:10.682609 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4812 12:15:10.683165
4813 12:15:10.683537
4814 12:15:10.689548 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4815 12:15:10.692204 CH1 RK1: MR19=808, MR18=2B21
4816 12:15:10.699068 CH1_RK1: MR19=0x808, MR18=0x2B21, DQSOSC=401, MR23=63, INC=163, DEC=108
4817 12:15:10.701966 [RxdqsGatingPostProcess] freq 600
4818 12:15:10.705256 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4819 12:15:10.708507 Pre-setting of DQS Precalculation
4820 12:15:10.715008 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4821 12:15:10.722324 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4822 12:15:10.728807 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4823 12:15:10.729650
4824 12:15:10.730117
4825 12:15:10.731551 [Calibration Summary] 1200 Mbps
4826 12:15:10.732086 CH 0, Rank 0
4827 12:15:10.735195 SW Impedance : PASS
4828 12:15:10.738905 DUTY Scan : NO K
4829 12:15:10.739465 ZQ Calibration : PASS
4830 12:15:10.741937 Jitter Meter : NO K
4831 12:15:10.745395 CBT Training : PASS
4832 12:15:10.745982 Write leveling : PASS
4833 12:15:10.748154 RX DQS gating : PASS
4834 12:15:10.752122 RX DQ/DQS(RDDQC) : PASS
4835 12:15:10.752684 TX DQ/DQS : PASS
4836 12:15:10.754993 RX DATLAT : PASS
4837 12:15:10.758341 RX DQ/DQS(Engine): PASS
4838 12:15:10.758806 TX OE : NO K
4839 12:15:10.761685 All Pass.
4840 12:15:10.762150
4841 12:15:10.762517 CH 0, Rank 1
4842 12:15:10.765097 SW Impedance : PASS
4843 12:15:10.765657 DUTY Scan : NO K
4844 12:15:10.768398 ZQ Calibration : PASS
4845 12:15:10.772171 Jitter Meter : NO K
4846 12:15:10.772727 CBT Training : PASS
4847 12:15:10.774984 Write leveling : PASS
4848 12:15:10.777995 RX DQS gating : PASS
4849 12:15:10.778462 RX DQ/DQS(RDDQC) : PASS
4850 12:15:10.781547 TX DQ/DQS : PASS
4851 12:15:10.784603 RX DATLAT : PASS
4852 12:15:10.785163 RX DQ/DQS(Engine): PASS
4853 12:15:10.787976 TX OE : NO K
4854 12:15:10.788541 All Pass.
4855 12:15:10.788914
4856 12:15:10.791718 CH 1, Rank 0
4857 12:15:10.792301 SW Impedance : PASS
4858 12:15:10.795292 DUTY Scan : NO K
4859 12:15:10.795905 ZQ Calibration : PASS
4860 12:15:10.797685 Jitter Meter : NO K
4861 12:15:10.801137 CBT Training : PASS
4862 12:15:10.801714 Write leveling : PASS
4863 12:15:10.804840 RX DQS gating : PASS
4864 12:15:10.807714 RX DQ/DQS(RDDQC) : PASS
4865 12:15:10.808288 TX DQ/DQS : PASS
4866 12:15:10.812332 RX DATLAT : PASS
4867 12:15:10.813997 RX DQ/DQS(Engine): PASS
4868 12:15:10.814460 TX OE : NO K
4869 12:15:10.817916 All Pass.
4870 12:15:10.818474
4871 12:15:10.818844 CH 1, Rank 1
4872 12:15:10.820735 SW Impedance : PASS
4873 12:15:10.821297 DUTY Scan : NO K
4874 12:15:10.824678 ZQ Calibration : PASS
4875 12:15:10.827638 Jitter Meter : NO K
4876 12:15:10.828141 CBT Training : PASS
4877 12:15:10.830501 Write leveling : PASS
4878 12:15:10.833796 RX DQS gating : PASS
4879 12:15:10.834380 RX DQ/DQS(RDDQC) : PASS
4880 12:15:10.837135 TX DQ/DQS : PASS
4881 12:15:10.840595 RX DATLAT : PASS
4882 12:15:10.841019 RX DQ/DQS(Engine): PASS
4883 12:15:10.844007 TX OE : NO K
4884 12:15:10.844429 All Pass.
4885 12:15:10.844766
4886 12:15:10.846994 DramC Write-DBI off
4887 12:15:10.851110 PER_BANK_REFRESH: Hybrid Mode
4888 12:15:10.851634 TX_TRACKING: ON
4889 12:15:10.860727 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4890 12:15:10.864122 [FAST_K] Save calibration result to emmc
4891 12:15:10.866774 dramc_set_vcore_voltage set vcore to 662500
4892 12:15:10.870335 Read voltage for 933, 3
4893 12:15:10.870749 Vio18 = 0
4894 12:15:10.871080 Vcore = 662500
4895 12:15:10.873671 Vdram = 0
4896 12:15:10.874026 Vddq = 0
4897 12:15:10.874332 Vmddr = 0
4898 12:15:10.880093 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4899 12:15:10.883594 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4900 12:15:10.887305 MEM_TYPE=3, freq_sel=17
4901 12:15:10.890441 sv_algorithm_assistance_LP4_1600
4902 12:15:10.893265 ============ PULL DRAM RESETB DOWN ============
4903 12:15:10.899736 ========== PULL DRAM RESETB DOWN end =========
4904 12:15:10.903066 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4905 12:15:10.906536 ===================================
4906 12:15:10.909817 LPDDR4 DRAM CONFIGURATION
4907 12:15:10.913333 ===================================
4908 12:15:10.913813 EX_ROW_EN[0] = 0x0
4909 12:15:10.916216 EX_ROW_EN[1] = 0x0
4910 12:15:10.916904 LP4Y_EN = 0x0
4911 12:15:10.920019 WORK_FSP = 0x0
4912 12:15:10.920578 WL = 0x3
4913 12:15:10.922570 RL = 0x3
4914 12:15:10.923028 BL = 0x2
4915 12:15:10.926137 RPST = 0x0
4916 12:15:10.926694 RD_PRE = 0x0
4917 12:15:10.930033 WR_PRE = 0x1
4918 12:15:10.932408 WR_PST = 0x0
4919 12:15:10.932870 DBI_WR = 0x0
4920 12:15:10.935853 DBI_RD = 0x0
4921 12:15:10.936314 OTF = 0x1
4922 12:15:10.938965 ===================================
4923 12:15:10.942313 ===================================
4924 12:15:10.946267 ANA top config
4925 12:15:10.949206 ===================================
4926 12:15:10.949766 DLL_ASYNC_EN = 0
4927 12:15:10.952258 ALL_SLAVE_EN = 1
4928 12:15:10.955648 NEW_RANK_MODE = 1
4929 12:15:10.958905 DLL_IDLE_MODE = 1
4930 12:15:10.959464 LP45_APHY_COMB_EN = 1
4931 12:15:10.962119 TX_ODT_DIS = 1
4932 12:15:10.965290 NEW_8X_MODE = 1
4933 12:15:10.968609 ===================================
4934 12:15:10.972424 ===================================
4935 12:15:10.975628 data_rate = 1866
4936 12:15:10.979263 CKR = 1
4937 12:15:10.981794 DQ_P2S_RATIO = 8
4938 12:15:10.985482 ===================================
4939 12:15:10.986046 CA_P2S_RATIO = 8
4940 12:15:10.988110 DQ_CA_OPEN = 0
4941 12:15:10.991643 DQ_SEMI_OPEN = 0
4942 12:15:10.994982 CA_SEMI_OPEN = 0
4943 12:15:10.998186 CA_FULL_RATE = 0
4944 12:15:11.002058 DQ_CKDIV4_EN = 1
4945 12:15:11.005494 CA_CKDIV4_EN = 1
4946 12:15:11.005957 CA_PREDIV_EN = 0
4947 12:15:11.008123 PH8_DLY = 0
4948 12:15:11.011323 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4949 12:15:11.014559 DQ_AAMCK_DIV = 4
4950 12:15:11.018181 CA_AAMCK_DIV = 4
4951 12:15:11.021128 CA_ADMCK_DIV = 4
4952 12:15:11.021557 DQ_TRACK_CA_EN = 0
4953 12:15:11.024225 CA_PICK = 933
4954 12:15:11.027569 CA_MCKIO = 933
4955 12:15:11.031166 MCKIO_SEMI = 0
4956 12:15:11.034847 PLL_FREQ = 3732
4957 12:15:11.037857 DQ_UI_PI_RATIO = 32
4958 12:15:11.041213 CA_UI_PI_RATIO = 0
4959 12:15:11.044421 ===================================
4960 12:15:11.047937 ===================================
4961 12:15:11.048497 memory_type:LPDDR4
4962 12:15:11.050843 GP_NUM : 10
4963 12:15:11.054417 SRAM_EN : 1
4964 12:15:11.054978 MD32_EN : 0
4965 12:15:11.057427 ===================================
4966 12:15:11.060334 [ANA_INIT] >>>>>>>>>>>>>>
4967 12:15:11.064324 <<<<<< [CONFIGURE PHASE]: ANA_TX
4968 12:15:11.067334 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4969 12:15:11.070864 ===================================
4970 12:15:11.074838 data_rate = 1866,PCW = 0X8f00
4971 12:15:11.077090 ===================================
4972 12:15:11.080780 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4973 12:15:11.083828 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4974 12:15:11.090446 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4975 12:15:11.093803 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4976 12:15:11.100150 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4977 12:15:11.104025 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4978 12:15:11.104651 [ANA_INIT] flow start
4979 12:15:11.106801 [ANA_INIT] PLL >>>>>>>>
4980 12:15:11.110388 [ANA_INIT] PLL <<<<<<<<
4981 12:15:11.110800 [ANA_INIT] MIDPI >>>>>>>>
4982 12:15:11.113554 [ANA_INIT] MIDPI <<<<<<<<
4983 12:15:11.116883 [ANA_INIT] DLL >>>>>>>>
4984 12:15:11.117294 [ANA_INIT] flow end
4985 12:15:11.120540 ============ LP4 DIFF to SE enter ============
4986 12:15:11.127170 ============ LP4 DIFF to SE exit ============
4987 12:15:11.127586 [ANA_INIT] <<<<<<<<<<<<<
4988 12:15:11.130065 [Flow] Enable top DCM control >>>>>
4989 12:15:11.133266 [Flow] Enable top DCM control <<<<<
4990 12:15:11.136692 Enable DLL master slave shuffle
4991 12:15:11.143166 ==============================================================
4992 12:15:11.146946 Gating Mode config
4993 12:15:11.150346 ==============================================================
4994 12:15:11.153822 Config description:
4995 12:15:11.163556 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4996 12:15:11.169917 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4997 12:15:11.172980 SELPH_MODE 0: By rank 1: By Phase
4998 12:15:11.179217 ==============================================================
4999 12:15:11.182890 GAT_TRACK_EN = 1
5000 12:15:11.186446 RX_GATING_MODE = 2
5001 12:15:11.189461 RX_GATING_TRACK_MODE = 2
5002 12:15:11.189967 SELPH_MODE = 1
5003 12:15:11.192500 PICG_EARLY_EN = 1
5004 12:15:11.196193 VALID_LAT_VALUE = 1
5005 12:15:11.202863 ==============================================================
5006 12:15:11.205752 Enter into Gating configuration >>>>
5007 12:15:11.209136 Exit from Gating configuration <<<<
5008 12:15:11.212533 Enter into DVFS_PRE_config >>>>>
5009 12:15:11.222134 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5010 12:15:11.225858 Exit from DVFS_PRE_config <<<<<
5011 12:15:11.229301 Enter into PICG configuration >>>>
5012 12:15:11.232143 Exit from PICG configuration <<<<
5013 12:15:11.235734 [RX_INPUT] configuration >>>>>
5014 12:15:11.239494 [RX_INPUT] configuration <<<<<
5015 12:15:11.242482 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5016 12:15:11.249047 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5017 12:15:11.255534 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5018 12:15:11.262192 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5019 12:15:11.268246 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5020 12:15:11.275521 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5021 12:15:11.278199 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5022 12:15:11.281717 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5023 12:15:11.285026 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5024 12:15:11.291301 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5025 12:15:11.294861 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5026 12:15:11.298210 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5027 12:15:11.301556 ===================================
5028 12:15:11.305036 LPDDR4 DRAM CONFIGURATION
5029 12:15:11.307998 ===================================
5030 12:15:11.308414 EX_ROW_EN[0] = 0x0
5031 12:15:11.311384 EX_ROW_EN[1] = 0x0
5032 12:15:11.315362 LP4Y_EN = 0x0
5033 12:15:11.315814 WORK_FSP = 0x0
5034 12:15:11.317992 WL = 0x3
5035 12:15:11.318591 RL = 0x3
5036 12:15:11.321380 BL = 0x2
5037 12:15:11.321798 RPST = 0x0
5038 12:15:11.325218 RD_PRE = 0x0
5039 12:15:11.325636 WR_PRE = 0x1
5040 12:15:11.327819 WR_PST = 0x0
5041 12:15:11.328238 DBI_WR = 0x0
5042 12:15:11.331106 DBI_RD = 0x0
5043 12:15:11.331535 OTF = 0x1
5044 12:15:11.334884 ===================================
5045 12:15:11.338397 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5046 12:15:11.344648 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5047 12:15:11.347927 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5048 12:15:11.351041 ===================================
5049 12:15:11.353873 LPDDR4 DRAM CONFIGURATION
5050 12:15:11.357778 ===================================
5051 12:15:11.357868 EX_ROW_EN[0] = 0x10
5052 12:15:11.361291 EX_ROW_EN[1] = 0x0
5053 12:15:11.361397 LP4Y_EN = 0x0
5054 12:15:11.363951 WORK_FSP = 0x0
5055 12:15:11.367211 WL = 0x3
5056 12:15:11.367310 RL = 0x3
5057 12:15:11.371187 BL = 0x2
5058 12:15:11.371330 RPST = 0x0
5059 12:15:11.374045 RD_PRE = 0x0
5060 12:15:11.374155 WR_PRE = 0x1
5061 12:15:11.377052 WR_PST = 0x0
5062 12:15:11.377197 DBI_WR = 0x0
5063 12:15:11.380573 DBI_RD = 0x0
5064 12:15:11.380687 OTF = 0x1
5065 12:15:11.383931 ===================================
5066 12:15:11.390639 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5067 12:15:11.394626 nWR fixed to 30
5068 12:15:11.397896 [ModeRegInit_LP4] CH0 RK0
5069 12:15:11.398153 [ModeRegInit_LP4] CH0 RK1
5070 12:15:11.401346 [ModeRegInit_LP4] CH1 RK0
5071 12:15:11.405076 [ModeRegInit_LP4] CH1 RK1
5072 12:15:11.405512 match AC timing 9
5073 12:15:11.412693 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5074 12:15:11.414646 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5075 12:15:11.418130 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5076 12:15:11.424655 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5077 12:15:11.427841 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5078 12:15:11.428376 ==
5079 12:15:11.431206 Dram Type= 6, Freq= 0, CH_0, rank 0
5080 12:15:11.434479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5081 12:15:11.435075 ==
5082 12:15:11.441747 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5083 12:15:11.447937 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5084 12:15:11.451107 [CA 0] Center 37 (7~68) winsize 62
5085 12:15:11.454367 [CA 1] Center 37 (7~68) winsize 62
5086 12:15:11.457996 [CA 2] Center 34 (4~65) winsize 62
5087 12:15:11.460594 [CA 3] Center 35 (5~65) winsize 61
5088 12:15:11.464307 [CA 4] Center 33 (3~64) winsize 62
5089 12:15:11.467393 [CA 5] Center 33 (3~64) winsize 62
5090 12:15:11.467898
5091 12:15:11.470706 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5092 12:15:11.471168
5093 12:15:11.473774 [CATrainingPosCal] consider 1 rank data
5094 12:15:11.477253 u2DelayCellTimex100 = 270/100 ps
5095 12:15:11.480884 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5096 12:15:11.485177 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5097 12:15:11.487080 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5098 12:15:11.494495 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5099 12:15:11.497568 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5100 12:15:11.500842 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5101 12:15:11.501432
5102 12:15:11.503765 CA PerBit enable=1, Macro0, CA PI delay=33
5103 12:15:11.504422
5104 12:15:11.506593 [CBTSetCACLKResult] CA Dly = 33
5105 12:15:11.507321 CS Dly: 7 (0~38)
5106 12:15:11.507748 ==
5107 12:15:11.510294 Dram Type= 6, Freq= 0, CH_0, rank 1
5108 12:15:11.516680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 12:15:11.517167 ==
5110 12:15:11.520251 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5111 12:15:11.526514 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5112 12:15:11.531767 [CA 0] Center 37 (7~68) winsize 62
5113 12:15:11.533257 [CA 1] Center 37 (7~68) winsize 62
5114 12:15:11.536714 [CA 2] Center 34 (4~65) winsize 62
5115 12:15:11.540199 [CA 3] Center 34 (4~65) winsize 62
5116 12:15:11.543123 [CA 4] Center 33 (3~64) winsize 62
5117 12:15:11.546571 [CA 5] Center 33 (3~63) winsize 61
5118 12:15:11.547112
5119 12:15:11.549892 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5120 12:15:11.550353
5121 12:15:11.553081 [CATrainingPosCal] consider 2 rank data
5122 12:15:11.557060 u2DelayCellTimex100 = 270/100 ps
5123 12:15:11.563469 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5124 12:15:11.566413 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5125 12:15:11.569522 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5126 12:15:11.572864 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5127 12:15:11.576076 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5128 12:15:11.580298 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5129 12:15:11.580859
5130 12:15:11.582748 CA PerBit enable=1, Macro0, CA PI delay=33
5131 12:15:11.583209
5132 12:15:11.586168 [CBTSetCACLKResult] CA Dly = 33
5133 12:15:11.589307 CS Dly: 7 (0~39)
5134 12:15:11.589884
5135 12:15:11.592416 ----->DramcWriteLeveling(PI) begin...
5136 12:15:11.592996 ==
5137 12:15:11.595748 Dram Type= 6, Freq= 0, CH_0, rank 0
5138 12:15:11.599157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5139 12:15:11.599767 ==
5140 12:15:11.602827 Write leveling (Byte 0): 32 => 32
5141 12:15:11.605498 Write leveling (Byte 1): 28 => 28
5142 12:15:11.609924 DramcWriteLeveling(PI) end<-----
5143 12:15:11.610496
5144 12:15:11.610866 ==
5145 12:15:11.612217 Dram Type= 6, Freq= 0, CH_0, rank 0
5146 12:15:11.615452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 12:15:11.616312 ==
5148 12:15:11.618792 [Gating] SW mode calibration
5149 12:15:11.625416 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5150 12:15:11.632148 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5151 12:15:11.636023 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
5152 12:15:11.642043 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5153 12:15:11.644975 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 12:15:11.648260 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 12:15:11.655639 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 12:15:11.658733 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 12:15:11.661831 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5158 12:15:11.668337 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
5159 12:15:11.671713 0 15 0 | B1->B0 | 3131 2323 | 0 0 | (0 1) (1 0)
5160 12:15:11.675112 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5161 12:15:11.681581 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 12:15:11.684518 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 12:15:11.688102 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 12:15:11.695029 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 12:15:11.698442 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 12:15:11.701662 0 15 28 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5167 12:15:11.707924 1 0 0 | B1->B0 | 3333 4646 | 0 0 | (1 1) (0 0)
5168 12:15:11.711490 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 12:15:11.714306 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 12:15:11.721878 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 12:15:11.724699 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 12:15:11.727765 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 12:15:11.731760 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 12:15:11.737695 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5175 12:15:11.741217 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5176 12:15:11.744543 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5177 12:15:11.751050 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 12:15:11.754846 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 12:15:11.757695 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 12:15:11.763984 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 12:15:11.767487 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 12:15:11.770637 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 12:15:11.777511 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 12:15:11.781063 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 12:15:11.784048 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 12:15:11.791032 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 12:15:11.794105 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 12:15:11.797610 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 12:15:11.804155 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 12:15:11.807052 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5191 12:15:11.810153 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5192 12:15:11.813783 Total UI for P1: 0, mck2ui 16
5193 12:15:11.816819 best dqsien dly found for B0: ( 1, 2, 28)
5194 12:15:11.823801 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 12:15:11.827048 Total UI for P1: 0, mck2ui 16
5196 12:15:11.829860 best dqsien dly found for B1: ( 1, 3, 0)
5197 12:15:11.833314 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5198 12:15:11.836652 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5199 12:15:11.837112
5200 12:15:11.840711 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5201 12:15:11.843147 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5202 12:15:11.846722 [Gating] SW calibration Done
5203 12:15:11.847281 ==
5204 12:15:11.850383 Dram Type= 6, Freq= 0, CH_0, rank 0
5205 12:15:11.853495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5206 12:15:11.853957 ==
5207 12:15:11.856348 RX Vref Scan: 0
5208 12:15:11.856762
5209 12:15:11.860466 RX Vref 0 -> 0, step: 1
5210 12:15:11.860979
5211 12:15:11.861448 RX Delay -80 -> 252, step: 8
5212 12:15:11.866388 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5213 12:15:11.870310 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5214 12:15:11.873146 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5215 12:15:11.876877 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5216 12:15:11.879850 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5217 12:15:11.883068 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5218 12:15:11.890208 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5219 12:15:11.893193 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5220 12:15:11.896327 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5221 12:15:11.899710 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5222 12:15:11.902991 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5223 12:15:11.909520 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5224 12:15:11.912738 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5225 12:15:11.915901 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5226 12:15:11.919001 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5227 12:15:11.922394 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5228 12:15:11.922840 ==
5229 12:15:11.925558 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 12:15:11.932172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 12:15:11.932639 ==
5232 12:15:11.933011 DQS Delay:
5233 12:15:11.935445 DQS0 = 0, DQS1 = 0
5234 12:15:11.935938 DQM Delay:
5235 12:15:11.938526 DQM0 = 97, DQM1 = 86
5236 12:15:11.938972 DQ Delay:
5237 12:15:11.942547 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5238 12:15:11.945443 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5239 12:15:11.949255 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5240 12:15:11.952278 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5241 12:15:11.952888
5242 12:15:11.953267
5243 12:15:11.953612 ==
5244 12:15:11.955985 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 12:15:11.959110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 12:15:11.959704 ==
5247 12:15:11.960097
5248 12:15:11.960442
5249 12:15:11.962265 TX Vref Scan disable
5250 12:15:11.965269 == TX Byte 0 ==
5251 12:15:11.968502 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5252 12:15:11.971956 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5253 12:15:11.975315 == TX Byte 1 ==
5254 12:15:11.979625 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5255 12:15:11.981909 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5256 12:15:11.982357 ==
5257 12:15:11.986457 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 12:15:11.992024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 12:15:11.992546 ==
5260 12:15:11.992884
5261 12:15:11.993193
5262 12:15:11.993489 TX Vref Scan disable
5263 12:15:11.995514 == TX Byte 0 ==
5264 12:15:11.999110 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5265 12:15:12.005803 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5266 12:15:12.006329 == TX Byte 1 ==
5267 12:15:12.008681 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5268 12:15:12.015345 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5269 12:15:12.015816
5270 12:15:12.016157 [DATLAT]
5271 12:15:12.016469 Freq=933, CH0 RK0
5272 12:15:12.016771
5273 12:15:12.018504 DATLAT Default: 0xd
5274 12:15:12.018921 0, 0xFFFF, sum = 0
5275 12:15:12.022053 1, 0xFFFF, sum = 0
5276 12:15:12.025393 2, 0xFFFF, sum = 0
5277 12:15:12.025815 3, 0xFFFF, sum = 0
5278 12:15:12.028948 4, 0xFFFF, sum = 0
5279 12:15:12.029372 5, 0xFFFF, sum = 0
5280 12:15:12.031894 6, 0xFFFF, sum = 0
5281 12:15:12.032318 7, 0xFFFF, sum = 0
5282 12:15:12.036670 8, 0xFFFF, sum = 0
5283 12:15:12.037193 9, 0xFFFF, sum = 0
5284 12:15:12.038799 10, 0x0, sum = 1
5285 12:15:12.039237 11, 0x0, sum = 2
5286 12:15:12.042047 12, 0x0, sum = 3
5287 12:15:12.042567 13, 0x0, sum = 4
5288 12:15:12.044952 best_step = 11
5289 12:15:12.045368
5290 12:15:12.045699 ==
5291 12:15:12.049173 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 12:15:12.051474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 12:15:12.051998 ==
5294 12:15:12.052341 RX Vref Scan: 1
5295 12:15:12.054741
5296 12:15:12.055154 RX Vref 0 -> 0, step: 1
5297 12:15:12.055482
5298 12:15:12.058411 RX Delay -69 -> 252, step: 4
5299 12:15:12.058828
5300 12:15:12.061198 Set Vref, RX VrefLevel [Byte0]: 61
5301 12:15:12.064776 [Byte1]: 49
5302 12:15:12.068166
5303 12:15:12.068581 Final RX Vref Byte 0 = 61 to rank0
5304 12:15:12.071568 Final RX Vref Byte 1 = 49 to rank0
5305 12:15:12.074856 Final RX Vref Byte 0 = 61 to rank1
5306 12:15:12.077897 Final RX Vref Byte 1 = 49 to rank1==
5307 12:15:12.081843 Dram Type= 6, Freq= 0, CH_0, rank 0
5308 12:15:12.088169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5309 12:15:12.088595 ==
5310 12:15:12.088930 DQS Delay:
5311 12:15:12.091436 DQS0 = 0, DQS1 = 0
5312 12:15:12.091889 DQM Delay:
5313 12:15:12.092224 DQM0 = 97, DQM1 = 85
5314 12:15:12.094713 DQ Delay:
5315 12:15:12.098745 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5316 12:15:12.101302 DQ4 =96, DQ5 =88, DQ6 =108, DQ7 =106
5317 12:15:12.104399 DQ8 =76, DQ9 =74, DQ10 =84, DQ11 =80
5318 12:15:12.107618 DQ12 =88, DQ13 =88, DQ14 =98, DQ15 =92
5319 12:15:12.108101
5320 12:15:12.108428
5321 12:15:12.114405 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5322 12:15:12.117978 CH0 RK0: MR19=505, MR18=2E15
5323 12:15:12.123821 CH0_RK0: MR19=0x505, MR18=0x2E15, DQSOSC=407, MR23=63, INC=65, DEC=43
5324 12:15:12.124243
5325 12:15:12.127550 ----->DramcWriteLeveling(PI) begin...
5326 12:15:12.128151 ==
5327 12:15:12.130733 Dram Type= 6, Freq= 0, CH_0, rank 1
5328 12:15:12.135656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5329 12:15:12.136498 ==
5330 12:15:12.137310 Write leveling (Byte 0): 32 => 32
5331 12:15:12.140527 Write leveling (Byte 1): 30 => 30
5332 12:15:12.144598 DramcWriteLeveling(PI) end<-----
5333 12:15:12.145118
5334 12:15:12.145454 ==
5335 12:15:12.147615 Dram Type= 6, Freq= 0, CH_0, rank 1
5336 12:15:12.151535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 12:15:12.153954 ==
5338 12:15:12.154467 [Gating] SW mode calibration
5339 12:15:12.163965 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5340 12:15:12.167454 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5341 12:15:12.170194 0 14 0 | B1->B0 | 2e2e 3333 | 0 0 | (0 0) (0 0)
5342 12:15:12.177142 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 12:15:12.180449 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 12:15:12.183990 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 12:15:12.190303 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 12:15:12.194023 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 12:15:12.196860 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 12:15:12.204143 0 14 28 | B1->B0 | 3232 2b2b | 1 1 | (1 1) (1 1)
5349 12:15:12.206722 0 15 0 | B1->B0 | 2f2f 2525 | 0 0 | (1 1) (0 0)
5350 12:15:12.210091 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 12:15:12.216899 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 12:15:12.219995 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 12:15:12.223542 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 12:15:12.230385 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 12:15:12.233534 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 12:15:12.236770 0 15 28 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
5357 12:15:12.242630 1 0 0 | B1->B0 | 3a3a 4242 | 1 0 | (0 0) (0 0)
5358 12:15:12.246805 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 12:15:12.249506 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 12:15:12.256087 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 12:15:12.260373 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 12:15:12.266190 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 12:15:12.268842 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 12:15:12.272580 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5365 12:15:12.279220 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5366 12:15:12.282093 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 12:15:12.286721 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 12:15:12.292082 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 12:15:12.296114 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 12:15:12.299023 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 12:15:12.306032 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 12:15:12.309525 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 12:15:12.311939 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 12:15:12.318246 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 12:15:12.321404 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 12:15:12.325141 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 12:15:12.331886 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 12:15:12.334612 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 12:15:12.338381 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 12:15:12.345039 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5381 12:15:12.348440 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5382 12:15:12.351769 Total UI for P1: 0, mck2ui 16
5383 12:15:12.355235 best dqsien dly found for B0: ( 1, 2, 28)
5384 12:15:12.358247 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 12:15:12.361241 Total UI for P1: 0, mck2ui 16
5386 12:15:12.364362 best dqsien dly found for B1: ( 1, 2, 30)
5387 12:15:12.367930 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5388 12:15:12.371174 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5389 12:15:12.371790
5390 12:15:12.378191 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5391 12:15:12.380969 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5392 12:15:12.381524 [Gating] SW calibration Done
5393 12:15:12.384016 ==
5394 12:15:12.387863 Dram Type= 6, Freq= 0, CH_0, rank 1
5395 12:15:12.390722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5396 12:15:12.391289 ==
5397 12:15:12.391854 RX Vref Scan: 0
5398 12:15:12.392220
5399 12:15:12.394635 RX Vref 0 -> 0, step: 1
5400 12:15:12.395205
5401 12:15:12.397822 RX Delay -80 -> 252, step: 8
5402 12:15:12.400821 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5403 12:15:12.403879 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5404 12:15:12.407628 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5405 12:15:12.414260 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5406 12:15:12.417493 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5407 12:15:12.420478 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5408 12:15:12.423648 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5409 12:15:12.427100 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5410 12:15:12.434440 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5411 12:15:12.437543 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5412 12:15:12.440445 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5413 12:15:12.443220 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5414 12:15:12.446753 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5415 12:15:12.453645 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5416 12:15:12.456934 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5417 12:15:12.460901 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5418 12:15:12.461369 ==
5419 12:15:12.463240 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 12:15:12.466685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 12:15:12.467217 ==
5422 12:15:12.469993 DQS Delay:
5423 12:15:12.470458 DQS0 = 0, DQS1 = 0
5424 12:15:12.473839 DQM Delay:
5425 12:15:12.474414 DQM0 = 97, DQM1 = 87
5426 12:15:12.474786 DQ Delay:
5427 12:15:12.477239 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5428 12:15:12.479764 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5429 12:15:12.483413 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5430 12:15:12.486407 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5431 12:15:12.486977
5432 12:15:12.487351
5433 12:15:12.490123 ==
5434 12:15:12.493767 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 12:15:12.496026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 12:15:12.496528 ==
5437 12:15:12.496896
5438 12:15:12.497239
5439 12:15:12.499293 TX Vref Scan disable
5440 12:15:12.499794 == TX Byte 0 ==
5441 12:15:12.502835 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5442 12:15:12.509078 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5443 12:15:12.509500 == TX Byte 1 ==
5444 12:15:12.516027 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5445 12:15:12.519083 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5446 12:15:12.519500 ==
5447 12:15:12.522744 Dram Type= 6, Freq= 0, CH_0, rank 1
5448 12:15:12.526544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5449 12:15:12.526966 ==
5450 12:15:12.527298
5451 12:15:12.527608
5452 12:15:12.529277 TX Vref Scan disable
5453 12:15:12.532416 == TX Byte 0 ==
5454 12:15:12.535522 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5455 12:15:12.539208 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5456 12:15:12.543054 == TX Byte 1 ==
5457 12:15:12.546070 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5458 12:15:12.548834 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5459 12:15:12.549254
5460 12:15:12.552235 [DATLAT]
5461 12:15:12.552655 Freq=933, CH0 RK1
5462 12:15:12.552989
5463 12:15:12.555546 DATLAT Default: 0xb
5464 12:15:12.556116 0, 0xFFFF, sum = 0
5465 12:15:12.558750 1, 0xFFFF, sum = 0
5466 12:15:12.559268 2, 0xFFFF, sum = 0
5467 12:15:12.561907 3, 0xFFFF, sum = 0
5468 12:15:12.562336 4, 0xFFFF, sum = 0
5469 12:15:12.565068 5, 0xFFFF, sum = 0
5470 12:15:12.565493 6, 0xFFFF, sum = 0
5471 12:15:12.568648 7, 0xFFFF, sum = 0
5472 12:15:12.569073 8, 0xFFFF, sum = 0
5473 12:15:12.572665 9, 0xFFFF, sum = 0
5474 12:15:12.573188 10, 0x0, sum = 1
5475 12:15:12.575704 11, 0x0, sum = 2
5476 12:15:12.576152 12, 0x0, sum = 3
5477 12:15:12.578624 13, 0x0, sum = 4
5478 12:15:12.579148 best_step = 11
5479 12:15:12.579485
5480 12:15:12.579853 ==
5481 12:15:12.582237 Dram Type= 6, Freq= 0, CH_0, rank 1
5482 12:15:12.588951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5483 12:15:12.589470 ==
5484 12:15:12.589805 RX Vref Scan: 0
5485 12:15:12.590114
5486 12:15:12.591556 RX Vref 0 -> 0, step: 1
5487 12:15:12.592064
5488 12:15:12.595497 RX Delay -61 -> 252, step: 4
5489 12:15:12.598676 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5490 12:15:12.605705 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5491 12:15:12.608472 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5492 12:15:12.611640 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5493 12:15:12.615510 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5494 12:15:12.618174 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5495 12:15:12.621490 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5496 12:15:12.627664 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5497 12:15:12.632200 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5498 12:15:12.634554 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5499 12:15:12.638151 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5500 12:15:12.641091 iDelay=203, Bit 11, Center 78 (-13 ~ 170) 184
5501 12:15:12.648334 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5502 12:15:12.651244 iDelay=203, Bit 13, Center 92 (-5 ~ 190) 196
5503 12:15:12.654422 iDelay=203, Bit 14, Center 98 (11 ~ 186) 176
5504 12:15:12.657501 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5505 12:15:12.657925 ==
5506 12:15:12.661665 Dram Type= 6, Freq= 0, CH_0, rank 1
5507 12:15:12.667617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5508 12:15:12.668258 ==
5509 12:15:12.668611 DQS Delay:
5510 12:15:12.671073 DQS0 = 0, DQS1 = 0
5511 12:15:12.671597 DQM Delay:
5512 12:15:12.671998 DQM0 = 95, DQM1 = 86
5513 12:15:12.674015 DQ Delay:
5514 12:15:12.679123 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
5515 12:15:12.681150 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5516 12:15:12.684051 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =78
5517 12:15:12.688096 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =92
5518 12:15:12.688613
5519 12:15:12.688953
5520 12:15:12.694318 [DQSOSCAuto] RK1, (LSB)MR18= 0x2bfb, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5521 12:15:12.697051 CH0 RK1: MR19=504, MR18=2BFB
5522 12:15:12.704002 CH0_RK1: MR19=0x504, MR18=0x2BFB, DQSOSC=408, MR23=63, INC=65, DEC=43
5523 12:15:12.707184 [RxdqsGatingPostProcess] freq 933
5524 12:15:12.713981 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5525 12:15:12.714538 best DQS0 dly(2T, 0.5T) = (0, 10)
5526 12:15:12.716623 best DQS1 dly(2T, 0.5T) = (0, 11)
5527 12:15:12.720673 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5528 12:15:12.723260 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5529 12:15:12.727101 best DQS0 dly(2T, 0.5T) = (0, 10)
5530 12:15:12.730271 best DQS1 dly(2T, 0.5T) = (0, 10)
5531 12:15:12.733225 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5532 12:15:12.736198 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5533 12:15:12.739415 Pre-setting of DQS Precalculation
5534 12:15:12.746514 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5535 12:15:12.746944 ==
5536 12:15:12.749722 Dram Type= 6, Freq= 0, CH_1, rank 0
5537 12:15:12.752879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5538 12:15:12.753306 ==
5539 12:15:12.759772 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5540 12:15:12.763320 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5541 12:15:12.767390 [CA 0] Center 37 (7~67) winsize 61
5542 12:15:12.770269 [CA 1] Center 37 (7~68) winsize 62
5543 12:15:12.774254 [CA 2] Center 34 (4~65) winsize 62
5544 12:15:12.777014 [CA 3] Center 33 (3~64) winsize 62
5545 12:15:12.780468 [CA 4] Center 34 (4~65) winsize 62
5546 12:15:12.783727 [CA 5] Center 33 (3~64) winsize 62
5547 12:15:12.784150
5548 12:15:12.787027 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5549 12:15:12.787565
5550 12:15:12.789859 [CATrainingPosCal] consider 1 rank data
5551 12:15:12.794014 u2DelayCellTimex100 = 270/100 ps
5552 12:15:12.798395 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5553 12:15:12.803170 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5554 12:15:12.807068 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5555 12:15:12.809633 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5556 12:15:12.813396 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5557 12:15:12.816371 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5558 12:15:12.816908
5559 12:15:12.819917 CA PerBit enable=1, Macro0, CA PI delay=33
5560 12:15:12.820449
5561 12:15:12.823732 [CBTSetCACLKResult] CA Dly = 33
5562 12:15:12.826878 CS Dly: 6 (0~37)
5563 12:15:12.827300 ==
5564 12:15:12.829415 Dram Type= 6, Freq= 0, CH_1, rank 1
5565 12:15:12.833360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5566 12:15:12.833879 ==
5567 12:15:12.839331 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5568 12:15:12.845677 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5569 12:15:12.849577 [CA 0] Center 37 (7~67) winsize 61
5570 12:15:12.852482 [CA 1] Center 37 (7~68) winsize 62
5571 12:15:12.856136 [CA 2] Center 34 (4~65) winsize 62
5572 12:15:12.859131 [CA 3] Center 34 (3~65) winsize 63
5573 12:15:12.862349 [CA 4] Center 34 (3~65) winsize 63
5574 12:15:12.866191 [CA 5] Center 33 (3~64) winsize 62
5575 12:15:12.866662
5576 12:15:12.869305 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5577 12:15:12.869873
5578 12:15:12.872549 [CATrainingPosCal] consider 2 rank data
5579 12:15:12.876386 u2DelayCellTimex100 = 270/100 ps
5580 12:15:12.878735 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5581 12:15:12.882821 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5582 12:15:12.885877 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5583 12:15:12.888942 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5584 12:15:12.891869 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5585 12:15:12.895586 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5586 12:15:12.896044
5587 12:15:12.902703 CA PerBit enable=1, Macro0, CA PI delay=33
5588 12:15:12.903242
5589 12:15:12.903587 [CBTSetCACLKResult] CA Dly = 33
5590 12:15:12.905810 CS Dly: 7 (0~39)
5591 12:15:12.906339
5592 12:15:12.908319 ----->DramcWriteLeveling(PI) begin...
5593 12:15:12.908750 ==
5594 12:15:12.911886 Dram Type= 6, Freq= 0, CH_1, rank 0
5595 12:15:12.915436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5596 12:15:12.916010 ==
5597 12:15:12.919147 Write leveling (Byte 0): 27 => 27
5598 12:15:12.922227 Write leveling (Byte 1): 29 => 29
5599 12:15:12.925301 DramcWriteLeveling(PI) end<-----
5600 12:15:12.925727
5601 12:15:12.926060 ==
5602 12:15:12.928259 Dram Type= 6, Freq= 0, CH_1, rank 0
5603 12:15:12.935507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5604 12:15:12.936050 ==
5605 12:15:12.936395 [Gating] SW mode calibration
5606 12:15:12.945012 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5607 12:15:12.948147 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5608 12:15:12.951842 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 12:15:12.957967 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 12:15:12.961989 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 12:15:12.965062 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 12:15:12.971646 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 12:15:12.974320 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5614 12:15:12.977882 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
5615 12:15:12.984256 0 14 28 | B1->B0 | 3131 2c2c | 0 0 | (0 0) (0 0)
5616 12:15:12.988045 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 12:15:12.991005 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 12:15:12.997621 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 12:15:13.001298 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 12:15:13.004447 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 12:15:13.011089 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 12:15:13.014734 0 15 24 | B1->B0 | 2524 2525 | 1 0 | (0 0) (0 0)
5623 12:15:13.017445 0 15 28 | B1->B0 | 3939 3d3d | 0 0 | (0 0) (0 0)
5624 12:15:13.023986 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 12:15:13.027451 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 12:15:13.030671 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 12:15:13.037454 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 12:15:13.041135 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 12:15:13.043624 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 12:15:13.050519 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5631 12:15:13.054012 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5632 12:15:13.056975 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 12:15:13.063339 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 12:15:13.066651 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 12:15:13.070740 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 12:15:13.076678 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 12:15:13.080308 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 12:15:13.083174 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 12:15:13.090423 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 12:15:13.093171 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 12:15:13.096638 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 12:15:13.103049 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 12:15:13.106868 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 12:15:13.109413 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 12:15:13.116549 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 12:15:13.119773 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 12:15:13.122800 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5648 12:15:13.127146 Total UI for P1: 0, mck2ui 16
5649 12:15:13.129165 best dqsien dly found for B0: ( 1, 2, 26)
5650 12:15:13.136371 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 12:15:13.139221 Total UI for P1: 0, mck2ui 16
5652 12:15:13.142765 best dqsien dly found for B1: ( 1, 2, 28)
5653 12:15:13.146315 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5654 12:15:13.149576 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5655 12:15:13.150060
5656 12:15:13.152416 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5657 12:15:13.155892 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5658 12:15:13.159350 [Gating] SW calibration Done
5659 12:15:13.159903 ==
5660 12:15:13.162371 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 12:15:13.165431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 12:15:13.165855 ==
5663 12:15:13.169180 RX Vref Scan: 0
5664 12:15:13.169595
5665 12:15:13.171970 RX Vref 0 -> 0, step: 1
5666 12:15:13.172385
5667 12:15:13.172716 RX Delay -80 -> 252, step: 8
5668 12:15:13.179122 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5669 12:15:13.182105 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5670 12:15:13.185234 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5671 12:15:13.188937 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5672 12:15:13.192993 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5673 12:15:13.198587 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5674 12:15:13.202129 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5675 12:15:13.205373 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5676 12:15:13.209062 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5677 12:15:13.212191 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5678 12:15:13.215337 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5679 12:15:13.221822 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5680 12:15:13.224725 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5681 12:15:13.228724 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5682 12:15:13.231893 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5683 12:15:13.235949 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5684 12:15:13.236411 ==
5685 12:15:13.238205 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 12:15:13.244825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 12:15:13.245471 ==
5688 12:15:13.245827 DQS Delay:
5689 12:15:13.248052 DQS0 = 0, DQS1 = 0
5690 12:15:13.248471 DQM Delay:
5691 12:15:13.251132 DQM0 = 101, DQM1 = 91
5692 12:15:13.251553 DQ Delay:
5693 12:15:13.255016 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99
5694 12:15:13.258011 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5695 12:15:13.261311 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =79
5696 12:15:13.265107 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5697 12:15:13.265534
5698 12:15:13.265871
5699 12:15:13.266181 ==
5700 12:15:13.268394 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 12:15:13.271301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 12:15:13.271872 ==
5703 12:15:13.272214
5704 12:15:13.272528
5705 12:15:13.274790 TX Vref Scan disable
5706 12:15:13.278184 == TX Byte 0 ==
5707 12:15:13.281002 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5708 12:15:13.284318 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5709 12:15:13.288252 == TX Byte 1 ==
5710 12:15:13.291258 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5711 12:15:13.294205 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5712 12:15:13.294776 ==
5713 12:15:13.298181 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 12:15:13.304664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 12:15:13.305239 ==
5716 12:15:13.305609
5717 12:15:13.305951
5718 12:15:13.306282 TX Vref Scan disable
5719 12:15:13.308844 == TX Byte 0 ==
5720 12:15:13.311725 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5721 12:15:13.318282 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5722 12:15:13.318855 == TX Byte 1 ==
5723 12:15:13.321276 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5724 12:15:13.328888 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5725 12:15:13.329661
5726 12:15:13.330066 [DATLAT]
5727 12:15:13.330412 Freq=933, CH1 RK0
5728 12:15:13.330835
5729 12:15:13.331556 DATLAT Default: 0xd
5730 12:15:13.331966 0, 0xFFFF, sum = 0
5731 12:15:13.334960 1, 0xFFFF, sum = 0
5732 12:15:13.337554 2, 0xFFFF, sum = 0
5733 12:15:13.338024 3, 0xFFFF, sum = 0
5734 12:15:13.340927 4, 0xFFFF, sum = 0
5735 12:15:13.341553 5, 0xFFFF, sum = 0
5736 12:15:13.343953 6, 0xFFFF, sum = 0
5737 12:15:13.344401 7, 0xFFFF, sum = 0
5738 12:15:13.347226 8, 0xFFFF, sum = 0
5739 12:15:13.347742 9, 0xFFFF, sum = 0
5740 12:15:13.350724 10, 0x0, sum = 1
5741 12:15:13.351148 11, 0x0, sum = 2
5742 12:15:13.353887 12, 0x0, sum = 3
5743 12:15:13.354418 13, 0x0, sum = 4
5744 12:15:13.357302 best_step = 11
5745 12:15:13.357821
5746 12:15:13.358157 ==
5747 12:15:13.361284 Dram Type= 6, Freq= 0, CH_1, rank 0
5748 12:15:13.363934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 12:15:13.364358 ==
5750 12:15:13.367076 RX Vref Scan: 1
5751 12:15:13.367495
5752 12:15:13.367914 RX Vref 0 -> 0, step: 1
5753 12:15:13.368237
5754 12:15:13.371194 RX Delay -61 -> 252, step: 4
5755 12:15:13.371763
5756 12:15:13.373881 Set Vref, RX VrefLevel [Byte0]: 50
5757 12:15:13.376622 [Byte1]: 56
5758 12:15:13.380795
5759 12:15:13.381308 Final RX Vref Byte 0 = 50 to rank0
5760 12:15:13.383898 Final RX Vref Byte 1 = 56 to rank0
5761 12:15:13.388056 Final RX Vref Byte 0 = 50 to rank1
5762 12:15:13.391516 Final RX Vref Byte 1 = 56 to rank1==
5763 12:15:13.393948 Dram Type= 6, Freq= 0, CH_1, rank 0
5764 12:15:13.400909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 12:15:13.401431 ==
5766 12:15:13.401768 DQS Delay:
5767 12:15:13.402079 DQS0 = 0, DQS1 = 0
5768 12:15:13.404489 DQM Delay:
5769 12:15:13.405006 DQM0 = 101, DQM1 = 94
5770 12:15:13.407270 DQ Delay:
5771 12:15:13.410672 DQ0 =106, DQ1 =98, DQ2 =92, DQ3 =98
5772 12:15:13.414470 DQ4 =100, DQ5 =110, DQ6 =110, DQ7 =96
5773 12:15:13.416864 DQ8 =82, DQ9 =88, DQ10 =96, DQ11 =84
5774 12:15:13.420601 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =104
5775 12:15:13.421136
5776 12:15:13.421472
5777 12:15:13.427340 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f0f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5778 12:15:13.430006 CH1 RK0: MR19=505, MR18=1F0F
5779 12:15:13.436683 CH1_RK0: MR19=0x505, MR18=0x1F0F, DQSOSC=412, MR23=63, INC=63, DEC=42
5780 12:15:13.437202
5781 12:15:13.439909 ----->DramcWriteLeveling(PI) begin...
5782 12:15:13.440335 ==
5783 12:15:13.443338 Dram Type= 6, Freq= 0, CH_1, rank 1
5784 12:15:13.446374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 12:15:13.449763 ==
5786 12:15:13.453170 Write leveling (Byte 0): 27 => 27
5787 12:15:13.453689 Write leveling (Byte 1): 30 => 30
5788 12:15:13.456303 DramcWriteLeveling(PI) end<-----
5789 12:15:13.456745
5790 12:15:13.457079 ==
5791 12:15:13.459441 Dram Type= 6, Freq= 0, CH_1, rank 1
5792 12:15:13.466168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 12:15:13.466674 ==
5794 12:15:13.470222 [Gating] SW mode calibration
5795 12:15:13.476275 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5796 12:15:13.479458 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5797 12:15:13.485913 0 14 0 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
5798 12:15:13.489813 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 12:15:13.493252 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 12:15:13.499502 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 12:15:13.503170 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 12:15:13.505947 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 12:15:13.512253 0 14 24 | B1->B0 | 3131 3434 | 1 1 | (1 0) (1 0)
5804 12:15:13.516234 0 14 28 | B1->B0 | 2929 3232 | 1 0 | (1 0) (0 1)
5805 12:15:13.519806 0 15 0 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
5806 12:15:13.525929 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 12:15:13.529379 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 12:15:13.532375 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 12:15:13.538353 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 12:15:13.541725 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 12:15:13.545964 0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5812 12:15:13.551648 0 15 28 | B1->B0 | 4444 3232 | 0 0 | (0 0) (0 0)
5813 12:15:13.555408 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5814 12:15:13.559099 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 12:15:13.564988 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 12:15:13.569113 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 12:15:13.571529 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 12:15:13.578798 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 12:15:13.581898 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 12:15:13.584777 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5821 12:15:13.591823 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5822 12:15:13.595033 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 12:15:13.599305 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 12:15:13.605154 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 12:15:13.607736 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 12:15:13.610946 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 12:15:13.617751 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 12:15:13.621265 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 12:15:13.624370 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 12:15:13.631242 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 12:15:13.634151 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 12:15:13.637561 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 12:15:13.644839 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 12:15:13.647589 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 12:15:13.650724 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5836 12:15:13.657330 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5837 12:15:13.657908 Total UI for P1: 0, mck2ui 16
5838 12:15:13.663863 best dqsien dly found for B1: ( 1, 2, 24)
5839 12:15:13.667391 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 12:15:13.670924 Total UI for P1: 0, mck2ui 16
5841 12:15:13.674259 best dqsien dly found for B0: ( 1, 2, 26)
5842 12:15:13.677162 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5843 12:15:13.680448 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5844 12:15:13.680911
5845 12:15:13.684072 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5846 12:15:13.687706 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5847 12:15:13.691464 [Gating] SW calibration Done
5848 12:15:13.692082 ==
5849 12:15:13.693870 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 12:15:13.697364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 12:15:13.700305 ==
5852 12:15:13.700771 RX Vref Scan: 0
5853 12:15:13.701140
5854 12:15:13.704197 RX Vref 0 -> 0, step: 1
5855 12:15:13.704760
5856 12:15:13.707841 RX Delay -80 -> 252, step: 8
5857 12:15:13.710270 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5858 12:15:13.713802 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5859 12:15:13.716736 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5860 12:15:13.720705 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5861 12:15:13.724221 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5862 12:15:13.730777 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5863 12:15:13.734132 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5864 12:15:13.737410 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5865 12:15:13.740525 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5866 12:15:13.743557 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5867 12:15:13.750416 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5868 12:15:13.753474 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5869 12:15:13.756427 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5870 12:15:13.760020 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5871 12:15:13.764015 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5872 12:15:13.769722 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5873 12:15:13.770283 ==
5874 12:15:13.773454 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 12:15:13.776737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 12:15:13.777209 ==
5877 12:15:13.777580 DQS Delay:
5878 12:15:13.779635 DQS0 = 0, DQS1 = 0
5879 12:15:13.780147 DQM Delay:
5880 12:15:13.783011 DQM0 = 100, DQM1 = 92
5881 12:15:13.783573 DQ Delay:
5882 12:15:13.786149 DQ0 =107, DQ1 =95, DQ2 =87, DQ3 =99
5883 12:15:13.789443 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5884 12:15:13.792715 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =83
5885 12:15:13.795812 DQ12 =103, DQ13 =99, DQ14 =95, DQ15 =103
5886 12:15:13.796232
5887 12:15:13.796569
5888 12:15:13.796883 ==
5889 12:15:13.799189 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 12:15:13.806234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 12:15:13.806817 ==
5892 12:15:13.807170
5893 12:15:13.807486
5894 12:15:13.807820 TX Vref Scan disable
5895 12:15:13.808926 == TX Byte 0 ==
5896 12:15:13.812926 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5897 12:15:13.819095 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5898 12:15:13.819556 == TX Byte 1 ==
5899 12:15:13.822374 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5900 12:15:13.829276 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5901 12:15:13.829795 ==
5902 12:15:13.832210 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 12:15:13.836154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 12:15:13.836583 ==
5905 12:15:13.836920
5906 12:15:13.837233
5907 12:15:13.838628 TX Vref Scan disable
5908 12:15:13.839193 == TX Byte 0 ==
5909 12:15:13.845463 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5910 12:15:13.849314 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5911 12:15:13.852007 == TX Byte 1 ==
5912 12:15:13.855308 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5913 12:15:13.858348 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5914 12:15:13.858771
5915 12:15:13.859105 [DATLAT]
5916 12:15:13.861871 Freq=933, CH1 RK1
5917 12:15:13.862294
5918 12:15:13.862632 DATLAT Default: 0xb
5919 12:15:13.865368 0, 0xFFFF, sum = 0
5920 12:15:13.868781 1, 0xFFFF, sum = 0
5921 12:15:13.869208 2, 0xFFFF, sum = 0
5922 12:15:13.871765 3, 0xFFFF, sum = 0
5923 12:15:13.872194 4, 0xFFFF, sum = 0
5924 12:15:13.875350 5, 0xFFFF, sum = 0
5925 12:15:13.875936 6, 0xFFFF, sum = 0
5926 12:15:13.878740 7, 0xFFFF, sum = 0
5927 12:15:13.879275 8, 0xFFFF, sum = 0
5928 12:15:13.882583 9, 0xFFFF, sum = 0
5929 12:15:13.883117 10, 0x0, sum = 1
5930 12:15:13.886123 11, 0x0, sum = 2
5931 12:15:13.886657 12, 0x0, sum = 3
5932 12:15:13.888829 13, 0x0, sum = 4
5933 12:15:13.889260 best_step = 11
5934 12:15:13.889596
5935 12:15:13.889909 ==
5936 12:15:13.892141 Dram Type= 6, Freq= 0, CH_1, rank 1
5937 12:15:13.895085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5938 12:15:13.895746 ==
5939 12:15:13.898560 RX Vref Scan: 0
5940 12:15:13.899087
5941 12:15:13.902198 RX Vref 0 -> 0, step: 1
5942 12:15:13.902726
5943 12:15:13.903065 RX Delay -61 -> 252, step: 4
5944 12:15:13.909802 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
5945 12:15:13.912780 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5946 12:15:13.916170 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5947 12:15:13.919617 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5948 12:15:13.923834 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
5949 12:15:13.929651 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5950 12:15:13.933082 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5951 12:15:13.936089 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
5952 12:15:13.940267 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
5953 12:15:13.943342 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5954 12:15:13.946730 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
5955 12:15:13.952988 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5956 12:15:13.956215 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
5957 12:15:13.959820 iDelay=207, Bit 13, Center 100 (7 ~ 194) 188
5958 12:15:13.962592 iDelay=207, Bit 14, Center 102 (11 ~ 194) 184
5959 12:15:13.968984 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
5960 12:15:13.969447 ==
5961 12:15:13.972313 Dram Type= 6, Freq= 0, CH_1, rank 1
5962 12:15:13.975903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5963 12:15:13.976366 ==
5964 12:15:13.976735 DQS Delay:
5965 12:15:13.978587 DQS0 = 0, DQS1 = 0
5966 12:15:13.979003 DQM Delay:
5967 12:15:13.981895 DQM0 = 101, DQM1 = 94
5968 12:15:13.981977 DQ Delay:
5969 12:15:13.985335 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =98
5970 12:15:13.988661 DQ4 =100, DQ5 =110, DQ6 =114, DQ7 =98
5971 12:15:13.991834 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =84
5972 12:15:13.994943 DQ12 =102, DQ13 =100, DQ14 =102, DQ15 =102
5973 12:15:13.995065
5974 12:15:13.995140
5975 12:15:14.005062 [DQSOSCAuto] RK1, (LSB)MR18= 0x701, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
5976 12:15:14.005145 CH1 RK1: MR19=505, MR18=701
5977 12:15:14.011333 CH1_RK1: MR19=0x505, MR18=0x701, DQSOSC=419, MR23=63, INC=61, DEC=41
5978 12:15:14.014709 [RxdqsGatingPostProcess] freq 933
5979 12:15:14.021455 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5980 12:15:14.024824 best DQS0 dly(2T, 0.5T) = (0, 10)
5981 12:15:14.027623 best DQS1 dly(2T, 0.5T) = (0, 10)
5982 12:15:14.031869 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5983 12:15:14.034535 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5984 12:15:14.037989 best DQS0 dly(2T, 0.5T) = (0, 10)
5985 12:15:14.041727 best DQS1 dly(2T, 0.5T) = (0, 10)
5986 12:15:14.041838 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5987 12:15:14.045279 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5988 12:15:14.047659 Pre-setting of DQS Precalculation
5989 12:15:14.054635 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5990 12:15:14.061093 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5991 12:15:14.067437 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5992 12:15:14.067519
5993 12:15:14.067583
5994 12:15:14.071407 [Calibration Summary] 1866 Mbps
5995 12:15:14.074026 CH 0, Rank 0
5996 12:15:14.074107 SW Impedance : PASS
5997 12:15:14.077795 DUTY Scan : NO K
5998 12:15:14.081179 ZQ Calibration : PASS
5999 12:15:14.081260 Jitter Meter : NO K
6000 12:15:14.084015 CBT Training : PASS
6001 12:15:14.087605 Write leveling : PASS
6002 12:15:14.087713 RX DQS gating : PASS
6003 12:15:14.090841 RX DQ/DQS(RDDQC) : PASS
6004 12:15:14.094465 TX DQ/DQS : PASS
6005 12:15:14.094639 RX DATLAT : PASS
6006 12:15:14.097279 RX DQ/DQS(Engine): PASS
6007 12:15:14.100489 TX OE : NO K
6008 12:15:14.100596 All Pass.
6009 12:15:14.100663
6010 12:15:14.100722 CH 0, Rank 1
6011 12:15:14.103770 SW Impedance : PASS
6012 12:15:14.106996 DUTY Scan : NO K
6013 12:15:14.107164 ZQ Calibration : PASS
6014 12:15:14.110543 Jitter Meter : NO K
6015 12:15:14.110658 CBT Training : PASS
6016 12:15:14.114028 Write leveling : PASS
6017 12:15:14.117156 RX DQS gating : PASS
6018 12:15:14.117238 RX DQ/DQS(RDDQC) : PASS
6019 12:15:14.120659 TX DQ/DQS : PASS
6020 12:15:14.124572 RX DATLAT : PASS
6021 12:15:14.124991 RX DQ/DQS(Engine): PASS
6022 12:15:14.128049 TX OE : NO K
6023 12:15:14.128468 All Pass.
6024 12:15:14.128799
6025 12:15:14.130396 CH 1, Rank 0
6026 12:15:14.130814 SW Impedance : PASS
6027 12:15:14.133995 DUTY Scan : NO K
6028 12:15:14.137147 ZQ Calibration : PASS
6029 12:15:14.137565 Jitter Meter : NO K
6030 12:15:14.140707 CBT Training : PASS
6031 12:15:14.143735 Write leveling : PASS
6032 12:15:14.144159 RX DQS gating : PASS
6033 12:15:14.147063 RX DQ/DQS(RDDQC) : PASS
6034 12:15:14.150903 TX DQ/DQS : PASS
6035 12:15:14.151427 RX DATLAT : PASS
6036 12:15:14.153971 RX DQ/DQS(Engine): PASS
6037 12:15:14.157039 TX OE : NO K
6038 12:15:14.157459 All Pass.
6039 12:15:14.157806
6040 12:15:14.158145 CH 1, Rank 1
6041 12:15:14.160500 SW Impedance : PASS
6042 12:15:14.164424 DUTY Scan : NO K
6043 12:15:14.164943 ZQ Calibration : PASS
6044 12:15:14.166686 Jitter Meter : NO K
6045 12:15:14.171181 CBT Training : PASS
6046 12:15:14.171747 Write leveling : PASS
6047 12:15:14.173971 RX DQS gating : PASS
6048 12:15:14.174490 RX DQ/DQS(RDDQC) : PASS
6049 12:15:14.176646 TX DQ/DQS : PASS
6050 12:15:14.180159 RX DATLAT : PASS
6051 12:15:14.180654 RX DQ/DQS(Engine): PASS
6052 12:15:14.184435 TX OE : NO K
6053 12:15:14.184985 All Pass.
6054 12:15:14.185320
6055 12:15:14.186764 DramC Write-DBI off
6056 12:15:14.190618 PER_BANK_REFRESH: Hybrid Mode
6057 12:15:14.191291 TX_TRACKING: ON
6058 12:15:14.199822 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6059 12:15:14.204132 [FAST_K] Save calibration result to emmc
6060 12:15:14.206492 dramc_set_vcore_voltage set vcore to 650000
6061 12:15:14.210331 Read voltage for 400, 6
6062 12:15:14.210890 Vio18 = 0
6063 12:15:14.212961 Vcore = 650000
6064 12:15:14.213419 Vdram = 0
6065 12:15:14.213789 Vddq = 0
6066 12:15:14.214129 Vmddr = 0
6067 12:15:14.219650 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6068 12:15:14.226227 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6069 12:15:14.226791 MEM_TYPE=3, freq_sel=20
6070 12:15:14.229549 sv_algorithm_assistance_LP4_800
6071 12:15:14.232545 ============ PULL DRAM RESETB DOWN ============
6072 12:15:14.239258 ========== PULL DRAM RESETB DOWN end =========
6073 12:15:14.242997 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6074 12:15:14.246665 ===================================
6075 12:15:14.249980 LPDDR4 DRAM CONFIGURATION
6076 12:15:14.253745 ===================================
6077 12:15:14.254309 EX_ROW_EN[0] = 0x0
6078 12:15:14.256359 EX_ROW_EN[1] = 0x0
6079 12:15:14.256825 LP4Y_EN = 0x0
6080 12:15:14.259361 WORK_FSP = 0x0
6081 12:15:14.259966 WL = 0x2
6082 12:15:14.263071 RL = 0x2
6083 12:15:14.263625 BL = 0x2
6084 12:15:14.265958 RPST = 0x0
6085 12:15:14.269328 RD_PRE = 0x0
6086 12:15:14.269787 WR_PRE = 0x1
6087 12:15:14.273100 WR_PST = 0x0
6088 12:15:14.273662 DBI_WR = 0x0
6089 12:15:14.275839 DBI_RD = 0x0
6090 12:15:14.276395 OTF = 0x1
6091 12:15:14.279363 ===================================
6092 12:15:14.283177 ===================================
6093 12:15:14.286787 ANA top config
6094 12:15:14.289556 ===================================
6095 12:15:14.290143 DLL_ASYNC_EN = 0
6096 12:15:14.292891 ALL_SLAVE_EN = 1
6097 12:15:14.295630 NEW_RANK_MODE = 1
6098 12:15:14.299218 DLL_IDLE_MODE = 1
6099 12:15:14.299877 LP45_APHY_COMB_EN = 1
6100 12:15:14.303132 TX_ODT_DIS = 1
6101 12:15:14.305880 NEW_8X_MODE = 1
6102 12:15:14.309146 ===================================
6103 12:15:14.312122 ===================================
6104 12:15:14.316010 data_rate = 800
6105 12:15:14.319119 CKR = 1
6106 12:15:14.322482 DQ_P2S_RATIO = 4
6107 12:15:14.325702 ===================================
6108 12:15:14.326262 CA_P2S_RATIO = 4
6109 12:15:14.328790 DQ_CA_OPEN = 0
6110 12:15:14.332227 DQ_SEMI_OPEN = 1
6111 12:15:14.335108 CA_SEMI_OPEN = 1
6112 12:15:14.338918 CA_FULL_RATE = 0
6113 12:15:14.342388 DQ_CKDIV4_EN = 0
6114 12:15:14.342956 CA_CKDIV4_EN = 1
6115 12:15:14.345199 CA_PREDIV_EN = 0
6116 12:15:14.348557 PH8_DLY = 0
6117 12:15:14.351587 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6118 12:15:14.355925 DQ_AAMCK_DIV = 0
6119 12:15:14.358236 CA_AAMCK_DIV = 0
6120 12:15:14.358794 CA_ADMCK_DIV = 4
6121 12:15:14.361794 DQ_TRACK_CA_EN = 0
6122 12:15:14.366148 CA_PICK = 800
6123 12:15:14.367944 CA_MCKIO = 400
6124 12:15:14.371651 MCKIO_SEMI = 400
6125 12:15:14.374972 PLL_FREQ = 3016
6126 12:15:14.378844 DQ_UI_PI_RATIO = 32
6127 12:15:14.381059 CA_UI_PI_RATIO = 32
6128 12:15:14.384767 ===================================
6129 12:15:14.388211 ===================================
6130 12:15:14.388772 memory_type:LPDDR4
6131 12:15:14.391715 GP_NUM : 10
6132 12:15:14.394820 SRAM_EN : 1
6133 12:15:14.395375 MD32_EN : 0
6134 12:15:14.398154 ===================================
6135 12:15:14.401169 [ANA_INIT] >>>>>>>>>>>>>>
6136 12:15:14.404512 <<<<<< [CONFIGURE PHASE]: ANA_TX
6137 12:15:14.408652 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6138 12:15:14.411258 ===================================
6139 12:15:14.415106 data_rate = 800,PCW = 0X7400
6140 12:15:14.418779 ===================================
6141 12:15:14.421387 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6142 12:15:14.424579 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6143 12:15:14.437637 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6144 12:15:14.440896 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6145 12:15:14.444270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6146 12:15:14.447626 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6147 12:15:14.451430 [ANA_INIT] flow start
6148 12:15:14.454279 [ANA_INIT] PLL >>>>>>>>
6149 12:15:14.454735 [ANA_INIT] PLL <<<<<<<<
6150 12:15:14.457046 [ANA_INIT] MIDPI >>>>>>>>
6151 12:15:14.460860 [ANA_INIT] MIDPI <<<<<<<<
6152 12:15:14.461419 [ANA_INIT] DLL >>>>>>>>
6153 12:15:14.463894 [ANA_INIT] flow end
6154 12:15:14.467068 ============ LP4 DIFF to SE enter ============
6155 12:15:14.470338 ============ LP4 DIFF to SE exit ============
6156 12:15:14.474215 [ANA_INIT] <<<<<<<<<<<<<
6157 12:15:14.478369 [Flow] Enable top DCM control >>>>>
6158 12:15:14.480370 [Flow] Enable top DCM control <<<<<
6159 12:15:14.484032 Enable DLL master slave shuffle
6160 12:15:14.490566 ==============================================================
6161 12:15:14.491125 Gating Mode config
6162 12:15:14.496996 ==============================================================
6163 12:15:14.499965 Config description:
6164 12:15:14.507420 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6165 12:15:14.513584 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6166 12:15:14.520265 SELPH_MODE 0: By rank 1: By Phase
6167 12:15:14.526988 ==============================================================
6168 12:15:14.529452 GAT_TRACK_EN = 0
6169 12:15:14.529874 RX_GATING_MODE = 2
6170 12:15:14.533516 RX_GATING_TRACK_MODE = 2
6171 12:15:14.536198 SELPH_MODE = 1
6172 12:15:14.539882 PICG_EARLY_EN = 1
6173 12:15:14.543482 VALID_LAT_VALUE = 1
6174 12:15:14.549820 ==============================================================
6175 12:15:14.553054 Enter into Gating configuration >>>>
6176 12:15:14.556311 Exit from Gating configuration <<<<
6177 12:15:14.559754 Enter into DVFS_PRE_config >>>>>
6178 12:15:14.569473 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6179 12:15:14.573043 Exit from DVFS_PRE_config <<<<<
6180 12:15:14.576190 Enter into PICG configuration >>>>
6181 12:15:14.579464 Exit from PICG configuration <<<<
6182 12:15:14.583340 [RX_INPUT] configuration >>>>>
6183 12:15:14.586032 [RX_INPUT] configuration <<<<<
6184 12:15:14.589559 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6185 12:15:14.595747 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6186 12:15:14.602396 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6187 12:15:14.609979 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6188 12:15:14.612177 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6189 12:15:14.619616 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6190 12:15:14.622593 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6191 12:15:14.628936 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6192 12:15:14.632052 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6193 12:15:14.635892 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6194 12:15:14.638638 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6195 12:15:14.645603 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6196 12:15:14.648762 ===================================
6197 12:15:14.651885 LPDDR4 DRAM CONFIGURATION
6198 12:15:14.655282 ===================================
6199 12:15:14.655782 EX_ROW_EN[0] = 0x0
6200 12:15:14.658738 EX_ROW_EN[1] = 0x0
6201 12:15:14.659195 LP4Y_EN = 0x0
6202 12:15:14.662621 WORK_FSP = 0x0
6203 12:15:14.663381 WL = 0x2
6204 12:15:14.664984 RL = 0x2
6205 12:15:14.665452 BL = 0x2
6206 12:15:14.669075 RPST = 0x0
6207 12:15:14.669633 RD_PRE = 0x0
6208 12:15:14.672141 WR_PRE = 0x1
6209 12:15:14.672597 WR_PST = 0x0
6210 12:15:14.675327 DBI_WR = 0x0
6211 12:15:14.675940 DBI_RD = 0x0
6212 12:15:14.679308 OTF = 0x1
6213 12:15:14.681901 ===================================
6214 12:15:14.685315 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6215 12:15:14.688635 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6216 12:15:14.695183 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6217 12:15:14.698412 ===================================
6218 12:15:14.701281 LPDDR4 DRAM CONFIGURATION
6219 12:15:14.705227 ===================================
6220 12:15:14.705784 EX_ROW_EN[0] = 0x10
6221 12:15:14.708162 EX_ROW_EN[1] = 0x0
6222 12:15:14.708621 LP4Y_EN = 0x0
6223 12:15:14.712124 WORK_FSP = 0x0
6224 12:15:14.712684 WL = 0x2
6225 12:15:14.714619 RL = 0x2
6226 12:15:14.715075 BL = 0x2
6227 12:15:14.718177 RPST = 0x0
6228 12:15:14.718730 RD_PRE = 0x0
6229 12:15:14.721536 WR_PRE = 0x1
6230 12:15:14.722115 WR_PST = 0x0
6231 12:15:14.724443 DBI_WR = 0x0
6232 12:15:14.724902 DBI_RD = 0x0
6233 12:15:14.727902 OTF = 0x1
6234 12:15:14.731732 ===================================
6235 12:15:14.737817 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6236 12:15:14.742224 nWR fixed to 30
6237 12:15:14.744333 [ModeRegInit_LP4] CH0 RK0
6238 12:15:14.744792 [ModeRegInit_LP4] CH0 RK1
6239 12:15:14.747567 [ModeRegInit_LP4] CH1 RK0
6240 12:15:14.751304 [ModeRegInit_LP4] CH1 RK1
6241 12:15:14.751932 match AC timing 19
6242 12:15:14.757776 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6243 12:15:14.761242 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6244 12:15:14.764190 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6245 12:15:14.770950 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6246 12:15:14.774444 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6247 12:15:14.775002 ==
6248 12:15:14.778077 Dram Type= 6, Freq= 0, CH_0, rank 0
6249 12:15:14.780868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6250 12:15:14.781425 ==
6251 12:15:14.787488 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6252 12:15:14.794035 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6253 12:15:14.797435 [CA 0] Center 36 (8~64) winsize 57
6254 12:15:14.800957 [CA 1] Center 36 (8~64) winsize 57
6255 12:15:14.803743 [CA 2] Center 36 (8~64) winsize 57
6256 12:15:14.807763 [CA 3] Center 36 (8~64) winsize 57
6257 12:15:14.811300 [CA 4] Center 36 (8~64) winsize 57
6258 12:15:14.811896 [CA 5] Center 36 (8~64) winsize 57
6259 12:15:14.814027
6260 12:15:14.817506 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6261 12:15:14.818062
6262 12:15:14.820403 [CATrainingPosCal] consider 1 rank data
6263 12:15:14.823539 u2DelayCellTimex100 = 270/100 ps
6264 12:15:14.826975 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 12:15:14.830175 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 12:15:14.833771 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 12:15:14.836858 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 12:15:14.840196 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 12:15:14.843250 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 12:15:14.843745
6271 12:15:14.849810 CA PerBit enable=1, Macro0, CA PI delay=36
6272 12:15:14.850270
6273 12:15:14.850632 [CBTSetCACLKResult] CA Dly = 36
6274 12:15:14.853521 CS Dly: 1 (0~32)
6275 12:15:14.853975 ==
6276 12:15:14.856641 Dram Type= 6, Freq= 0, CH_0, rank 1
6277 12:15:14.860138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 12:15:14.860704 ==
6279 12:15:14.866656 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6280 12:15:14.873441 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6281 12:15:14.876470 [CA 0] Center 36 (8~64) winsize 57
6282 12:15:14.879857 [CA 1] Center 36 (8~64) winsize 57
6283 12:15:14.882637 [CA 2] Center 36 (8~64) winsize 57
6284 12:15:14.886584 [CA 3] Center 36 (8~64) winsize 57
6285 12:15:14.887133 [CA 4] Center 36 (8~64) winsize 57
6286 12:15:14.889403 [CA 5] Center 36 (8~64) winsize 57
6287 12:15:14.889872
6288 12:15:14.896200 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6289 12:15:14.896979
6290 12:15:14.899563 [CATrainingPosCal] consider 2 rank data
6291 12:15:14.902927 u2DelayCellTimex100 = 270/100 ps
6292 12:15:14.906342 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 12:15:14.909269 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 12:15:14.912950 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 12:15:14.915868 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 12:15:14.919214 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 12:15:14.923238 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 12:15:14.923651
6299 12:15:14.926230 CA PerBit enable=1, Macro0, CA PI delay=36
6300 12:15:14.926640
6301 12:15:14.929965 [CBTSetCACLKResult] CA Dly = 36
6302 12:15:14.932657 CS Dly: 1 (0~32)
6303 12:15:14.933288
6304 12:15:14.935941 ----->DramcWriteLeveling(PI) begin...
6305 12:15:14.936337 ==
6306 12:15:14.939567 Dram Type= 6, Freq= 0, CH_0, rank 0
6307 12:15:14.942316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6308 12:15:14.943029 ==
6309 12:15:14.945574 Write leveling (Byte 0): 40 => 8
6310 12:15:14.949496 Write leveling (Byte 1): 32 => 0
6311 12:15:14.952351 DramcWriteLeveling(PI) end<-----
6312 12:15:14.952999
6313 12:15:14.953434 ==
6314 12:15:14.955490 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 12:15:14.959355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 12:15:14.959815 ==
6317 12:15:14.962099 [Gating] SW mode calibration
6318 12:15:14.968783 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6319 12:15:14.975590 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6320 12:15:14.979667 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6321 12:15:14.985247 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6322 12:15:14.988476 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6323 12:15:14.992339 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6324 12:15:14.999176 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6325 12:15:15.001911 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 12:15:15.005615 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6327 12:15:15.011855 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6328 12:15:15.015108 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6329 12:15:15.018079 Total UI for P1: 0, mck2ui 16
6330 12:15:15.021675 best dqsien dly found for B0: ( 0, 14, 24)
6331 12:15:15.024791 Total UI for P1: 0, mck2ui 16
6332 12:15:15.028590 best dqsien dly found for B1: ( 0, 14, 24)
6333 12:15:15.032138 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6334 12:15:15.035200 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6335 12:15:15.035663
6336 12:15:15.037999 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6337 12:15:15.042222 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6338 12:15:15.044558 [Gating] SW calibration Done
6339 12:15:15.045017 ==
6340 12:15:15.048010 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 12:15:15.051246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 12:15:15.054515 ==
6343 12:15:15.054975 RX Vref Scan: 0
6344 12:15:15.055333
6345 12:15:15.058204 RX Vref 0 -> 0, step: 1
6346 12:15:15.059001
6347 12:15:15.061048 RX Delay -410 -> 252, step: 16
6348 12:15:15.065067 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6349 12:15:15.067757 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6350 12:15:15.071619 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6351 12:15:15.077653 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6352 12:15:15.081602 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6353 12:15:15.084819 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6354 12:15:15.087383 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6355 12:15:15.094980 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6356 12:15:15.097436 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6357 12:15:15.100718 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6358 12:15:15.107520 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6359 12:15:15.111029 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6360 12:15:15.113934 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6361 12:15:15.117432 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6362 12:15:15.124253 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6363 12:15:15.126865 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6364 12:15:15.127459 ==
6365 12:15:15.130508 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 12:15:15.133272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 12:15:15.133736 ==
6368 12:15:15.136653 DQS Delay:
6369 12:15:15.137118 DQS0 = 43, DQS1 = 59
6370 12:15:15.140617 DQM Delay:
6371 12:15:15.141179 DQM0 = 11, DQM1 = 12
6372 12:15:15.141545 DQ Delay:
6373 12:15:15.143836 DQ0 =16, DQ1 =8, DQ2 =8, DQ3 =0
6374 12:15:15.147033 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6375 12:15:15.149994 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6376 12:15:15.153295 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6377 12:15:15.153766
6378 12:15:15.154187
6379 12:15:15.154580 ==
6380 12:15:15.157149 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 12:15:15.163053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 12:15:15.163521 ==
6383 12:15:15.163939
6384 12:15:15.164284
6385 12:15:15.164617 TX Vref Scan disable
6386 12:15:15.166147 == TX Byte 0 ==
6387 12:15:15.170356 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6388 12:15:15.172969 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6389 12:15:15.176077 == TX Byte 1 ==
6390 12:15:15.179810 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6391 12:15:15.183391 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6392 12:15:15.187039 ==
6393 12:15:15.190362 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 12:15:15.194485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 12:15:15.195055 ==
6396 12:15:15.195427
6397 12:15:15.195809
6398 12:15:15.196502 TX Vref Scan disable
6399 12:15:15.196858 == TX Byte 0 ==
6400 12:15:15.199848 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6401 12:15:15.206075 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6402 12:15:15.206644 == TX Byte 1 ==
6403 12:15:15.210133 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6404 12:15:15.215833 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6405 12:15:15.216398
6406 12:15:15.216765 [DATLAT]
6407 12:15:15.219448 Freq=400, CH0 RK0
6408 12:15:15.220063
6409 12:15:15.220439 DATLAT Default: 0xf
6410 12:15:15.222853 0, 0xFFFF, sum = 0
6411 12:15:15.223424 1, 0xFFFF, sum = 0
6412 12:15:15.226132 2, 0xFFFF, sum = 0
6413 12:15:15.226705 3, 0xFFFF, sum = 0
6414 12:15:15.229737 4, 0xFFFF, sum = 0
6415 12:15:15.230311 5, 0xFFFF, sum = 0
6416 12:15:15.232294 6, 0xFFFF, sum = 0
6417 12:15:15.232808 7, 0xFFFF, sum = 0
6418 12:15:15.235542 8, 0xFFFF, sum = 0
6419 12:15:15.236073 9, 0xFFFF, sum = 0
6420 12:15:15.239085 10, 0xFFFF, sum = 0
6421 12:15:15.239742 11, 0xFFFF, sum = 0
6422 12:15:15.242589 12, 0xFFFF, sum = 0
6423 12:15:15.243059 13, 0x0, sum = 1
6424 12:15:15.245434 14, 0x0, sum = 2
6425 12:15:15.246009 15, 0x0, sum = 3
6426 12:15:15.248509 16, 0x0, sum = 4
6427 12:15:15.248979 best_step = 14
6428 12:15:15.249344
6429 12:15:15.249684 ==
6430 12:15:15.252175 Dram Type= 6, Freq= 0, CH_0, rank 0
6431 12:15:15.258928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 12:15:15.259617 ==
6433 12:15:15.260056 RX Vref Scan: 1
6434 12:15:15.260411
6435 12:15:15.262676 RX Vref 0 -> 0, step: 1
6436 12:15:15.263289
6437 12:15:15.265197 RX Delay -359 -> 252, step: 8
6438 12:15:15.265660
6439 12:15:15.268446 Set Vref, RX VrefLevel [Byte0]: 61
6440 12:15:15.271934 [Byte1]: 49
6441 12:15:15.275867
6442 12:15:15.276435 Final RX Vref Byte 0 = 61 to rank0
6443 12:15:15.278917 Final RX Vref Byte 1 = 49 to rank0
6444 12:15:15.281511 Final RX Vref Byte 0 = 61 to rank1
6445 12:15:15.285196 Final RX Vref Byte 1 = 49 to rank1==
6446 12:15:15.288484 Dram Type= 6, Freq= 0, CH_0, rank 0
6447 12:15:15.296052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 12:15:15.296621 ==
6449 12:15:15.296993 DQS Delay:
6450 12:15:15.297979 DQS0 = 48, DQS1 = 60
6451 12:15:15.298440 DQM Delay:
6452 12:15:15.298806 DQM0 = 11, DQM1 = 12
6453 12:15:15.301551 DQ Delay:
6454 12:15:15.305298 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6455 12:15:15.307822 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6456 12:15:15.308284 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6457 12:15:15.315390 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6458 12:15:15.316098
6459 12:15:15.316491
6460 12:15:15.321367 [DQSOSCAuto] RK0, (LSB)MR18= 0xb87b, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 386 ps
6461 12:15:15.324659 CH0 RK0: MR19=C0C, MR18=B87B
6462 12:15:15.331413 CH0_RK0: MR19=0xC0C, MR18=0xB87B, DQSOSC=386, MR23=63, INC=396, DEC=264
6463 12:15:15.332042 ==
6464 12:15:15.334043 Dram Type= 6, Freq= 0, CH_0, rank 1
6465 12:15:15.338328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 12:15:15.338900 ==
6467 12:15:15.340710 [Gating] SW mode calibration
6468 12:15:15.348004 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6469 12:15:15.353771 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6470 12:15:15.357616 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6471 12:15:15.363620 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6472 12:15:15.367154 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6473 12:15:15.370455 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6474 12:15:15.374199 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 12:15:15.381072 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 12:15:15.383875 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 12:15:15.390382 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6478 12:15:15.393591 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6479 12:15:15.396880 Total UI for P1: 0, mck2ui 16
6480 12:15:15.400534 best dqsien dly found for B0: ( 0, 14, 24)
6481 12:15:15.403180 Total UI for P1: 0, mck2ui 16
6482 12:15:15.406860 best dqsien dly found for B1: ( 0, 14, 24)
6483 12:15:15.410475 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6484 12:15:15.414070 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6485 12:15:15.414635
6486 12:15:15.417411 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6487 12:15:15.419868 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6488 12:15:15.423410 [Gating] SW calibration Done
6489 12:15:15.424023 ==
6490 12:15:15.426984 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 12:15:15.429690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 12:15:15.433024 ==
6493 12:15:15.433560 RX Vref Scan: 0
6494 12:15:15.433935
6495 12:15:15.436584 RX Vref 0 -> 0, step: 1
6496 12:15:15.437043
6497 12:15:15.439248 RX Delay -410 -> 252, step: 16
6498 12:15:15.443068 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6499 12:15:15.446208 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6500 12:15:15.449457 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6501 12:15:15.456775 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6502 12:15:15.459740 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6503 12:15:15.463378 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6504 12:15:15.466450 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6505 12:15:15.472825 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6506 12:15:15.476443 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6507 12:15:15.479047 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6508 12:15:15.482290 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6509 12:15:15.489019 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6510 12:15:15.492253 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6511 12:15:15.496185 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6512 12:15:15.502331 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6513 12:15:15.505468 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6514 12:15:15.505929 ==
6515 12:15:15.509037 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 12:15:15.511786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 12:15:15.512247 ==
6518 12:15:15.515060 DQS Delay:
6519 12:15:15.515555 DQS0 = 43, DQS1 = 59
6520 12:15:15.518464 DQM Delay:
6521 12:15:15.519024 DQM0 = 9, DQM1 = 16
6522 12:15:15.519389 DQ Delay:
6523 12:15:15.522609 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6524 12:15:15.525165 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6525 12:15:15.528645 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6526 12:15:15.531934 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6527 12:15:15.532489
6528 12:15:15.532864
6529 12:15:15.533294 ==
6530 12:15:15.534980 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 12:15:15.541686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 12:15:15.542149 ==
6533 12:15:15.542518
6534 12:15:15.542856
6535 12:15:15.543180 TX Vref Scan disable
6536 12:15:15.544806 == TX Byte 0 ==
6537 12:15:15.549203 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6538 12:15:15.551648 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6539 12:15:15.555446 == TX Byte 1 ==
6540 12:15:15.558418 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6541 12:15:15.561447 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6542 12:15:15.562007 ==
6543 12:15:15.564702 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 12:15:15.571825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 12:15:15.572395 ==
6546 12:15:15.572849
6547 12:15:15.573199
6548 12:15:15.573527 TX Vref Scan disable
6549 12:15:15.574619 == TX Byte 0 ==
6550 12:15:15.577612 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6551 12:15:15.581039 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6552 12:15:15.584681 == TX Byte 1 ==
6553 12:15:15.588179 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6554 12:15:15.591086 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6555 12:15:15.591616
6556 12:15:15.594527 [DATLAT]
6557 12:15:15.595050 Freq=400, CH0 RK1
6558 12:15:15.595390
6559 12:15:15.598357 DATLAT Default: 0xe
6560 12:15:15.598885 0, 0xFFFF, sum = 0
6561 12:15:15.601526 1, 0xFFFF, sum = 0
6562 12:15:15.601996 2, 0xFFFF, sum = 0
6563 12:15:15.604596 3, 0xFFFF, sum = 0
6564 12:15:15.605062 4, 0xFFFF, sum = 0
6565 12:15:15.608103 5, 0xFFFF, sum = 0
6566 12:15:15.608572 6, 0xFFFF, sum = 0
6567 12:15:15.611924 7, 0xFFFF, sum = 0
6568 12:15:15.615120 8, 0xFFFF, sum = 0
6569 12:15:15.615589 9, 0xFFFF, sum = 0
6570 12:15:15.617875 10, 0xFFFF, sum = 0
6571 12:15:15.618448 11, 0xFFFF, sum = 0
6572 12:15:15.621208 12, 0xFFFF, sum = 0
6573 12:15:15.621677 13, 0x0, sum = 1
6574 12:15:15.624607 14, 0x0, sum = 2
6575 12:15:15.625197 15, 0x0, sum = 3
6576 12:15:15.628491 16, 0x0, sum = 4
6577 12:15:15.629061 best_step = 14
6578 12:15:15.629429
6579 12:15:15.629768 ==
6580 12:15:15.630897 Dram Type= 6, Freq= 0, CH_0, rank 1
6581 12:15:15.633702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6582 12:15:15.634185 ==
6583 12:15:15.637634 RX Vref Scan: 0
6584 12:15:15.638093
6585 12:15:15.640384 RX Vref 0 -> 0, step: 1
6586 12:15:15.640846
6587 12:15:15.641210 RX Delay -359 -> 252, step: 8
6588 12:15:15.649547 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6589 12:15:15.652905 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6590 12:15:15.655996 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6591 12:15:15.660601 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6592 12:15:15.666049 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6593 12:15:15.669407 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6594 12:15:15.673291 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6595 12:15:15.679114 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6596 12:15:15.682822 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6597 12:15:15.686003 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6598 12:15:15.689281 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6599 12:15:15.696131 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6600 12:15:15.699940 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6601 12:15:15.703281 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6602 12:15:15.706540 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6603 12:15:15.712174 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6604 12:15:15.712643 ==
6605 12:15:15.715931 Dram Type= 6, Freq= 0, CH_0, rank 1
6606 12:15:15.719124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6607 12:15:15.719761 ==
6608 12:15:15.720148 DQS Delay:
6609 12:15:15.722559 DQS0 = 44, DQS1 = 60
6610 12:15:15.723128 DQM Delay:
6611 12:15:15.725565 DQM0 = 7, DQM1 = 15
6612 12:15:15.726025 DQ Delay:
6613 12:15:15.729416 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6614 12:15:15.732323 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6615 12:15:15.735724 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6616 12:15:15.739244 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6617 12:15:15.739746
6618 12:15:15.740127
6619 12:15:15.746033 [DQSOSCAuto] RK1, (LSB)MR18= 0xb943, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6620 12:15:15.750425 CH0 RK1: MR19=C0C, MR18=B943
6621 12:15:15.755475 CH0_RK1: MR19=0xC0C, MR18=0xB943, DQSOSC=386, MR23=63, INC=396, DEC=264
6622 12:15:15.759028 [RxdqsGatingPostProcess] freq 400
6623 12:15:15.765116 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6624 12:15:15.768645 best DQS0 dly(2T, 0.5T) = (0, 10)
6625 12:15:15.769216 best DQS1 dly(2T, 0.5T) = (0, 10)
6626 12:15:15.771915 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6627 12:15:15.775034 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6628 12:15:15.778515 best DQS0 dly(2T, 0.5T) = (0, 10)
6629 12:15:15.782094 best DQS1 dly(2T, 0.5T) = (0, 10)
6630 12:15:15.784882 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6631 12:15:15.787937 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6632 12:15:15.791968 Pre-setting of DQS Precalculation
6633 12:15:15.798398 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6634 12:15:15.798964 ==
6635 12:15:15.802000 Dram Type= 6, Freq= 0, CH_1, rank 0
6636 12:15:15.804719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 12:15:15.805186 ==
6638 12:15:15.811309 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6639 12:15:15.818530 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6640 12:15:15.821271 [CA 0] Center 36 (8~64) winsize 57
6641 12:15:15.821868 [CA 1] Center 36 (8~64) winsize 57
6642 12:15:15.825860 [CA 2] Center 36 (8~64) winsize 57
6643 12:15:15.827848 [CA 3] Center 36 (8~64) winsize 57
6644 12:15:15.832347 [CA 4] Center 36 (8~64) winsize 57
6645 12:15:15.835029 [CA 5] Center 36 (8~64) winsize 57
6646 12:15:15.835528
6647 12:15:15.837805 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6648 12:15:15.838269
6649 12:15:15.844233 [CATrainingPosCal] consider 1 rank data
6650 12:15:15.844693 u2DelayCellTimex100 = 270/100 ps
6651 12:15:15.847601 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 12:15:15.854477 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 12:15:15.858094 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 12:15:15.860959 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 12:15:15.864203 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 12:15:15.867663 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 12:15:15.868297
6658 12:15:15.870677 CA PerBit enable=1, Macro0, CA PI delay=36
6659 12:15:15.871249
6660 12:15:15.875084 [CBTSetCACLKResult] CA Dly = 36
6661 12:15:15.877588 CS Dly: 1 (0~32)
6662 12:15:15.878148 ==
6663 12:15:15.881137 Dram Type= 6, Freq= 0, CH_1, rank 1
6664 12:15:15.883928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 12:15:15.884509 ==
6666 12:15:15.890403 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6667 12:15:15.894672 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6668 12:15:15.897138 [CA 0] Center 36 (8~64) winsize 57
6669 12:15:15.900619 [CA 1] Center 36 (8~64) winsize 57
6670 12:15:15.903904 [CA 2] Center 36 (8~64) winsize 57
6671 12:15:15.907399 [CA 3] Center 36 (8~64) winsize 57
6672 12:15:15.910056 [CA 4] Center 36 (8~64) winsize 57
6673 12:15:15.913859 [CA 5] Center 36 (8~64) winsize 57
6674 12:15:15.914421
6675 12:15:15.916766 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6676 12:15:15.917228
6677 12:15:15.920487 [CATrainingPosCal] consider 2 rank data
6678 12:15:15.923757 u2DelayCellTimex100 = 270/100 ps
6679 12:15:15.927420 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 12:15:15.931139 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 12:15:15.936701 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 12:15:15.940208 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 12:15:15.943565 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 12:15:15.946833 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 12:15:15.947398
6686 12:15:15.950295 CA PerBit enable=1, Macro0, CA PI delay=36
6687 12:15:15.950858
6688 12:15:15.953446 [CBTSetCACLKResult] CA Dly = 36
6689 12:15:15.954017 CS Dly: 1 (0~32)
6690 12:15:15.954388
6691 12:15:15.960099 ----->DramcWriteLeveling(PI) begin...
6692 12:15:15.960668 ==
6693 12:15:15.962865 Dram Type= 6, Freq= 0, CH_1, rank 0
6694 12:15:15.966961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6695 12:15:15.967530 ==
6696 12:15:15.970001 Write leveling (Byte 0): 40 => 8
6697 12:15:15.973074 Write leveling (Byte 1): 32 => 0
6698 12:15:15.976168 DramcWriteLeveling(PI) end<-----
6699 12:15:15.976629
6700 12:15:15.976996 ==
6701 12:15:15.979590 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 12:15:15.983074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 12:15:15.983542 ==
6704 12:15:15.986473 [Gating] SW mode calibration
6705 12:15:15.992450 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6706 12:15:15.999259 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6707 12:15:16.002334 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6708 12:15:16.006009 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6709 12:15:16.012380 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6710 12:15:16.015775 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6711 12:15:16.018717 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6712 12:15:16.025558 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 12:15:16.029277 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6714 12:15:16.032198 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6715 12:15:16.038725 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6716 12:15:16.039150 Total UI for P1: 0, mck2ui 16
6717 12:15:16.045449 best dqsien dly found for B0: ( 0, 14, 24)
6718 12:15:16.045876 Total UI for P1: 0, mck2ui 16
6719 12:15:16.051900 best dqsien dly found for B1: ( 0, 14, 24)
6720 12:15:16.055253 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6721 12:15:16.058628 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6722 12:15:16.059059
6723 12:15:16.061844 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6724 12:15:16.065363 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6725 12:15:16.068741 [Gating] SW calibration Done
6726 12:15:16.069175 ==
6727 12:15:16.071491 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 12:15:16.075309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 12:15:16.075773 ==
6730 12:15:16.078208 RX Vref Scan: 0
6731 12:15:16.078628
6732 12:15:16.078960 RX Vref 0 -> 0, step: 1
6733 12:15:16.079271
6734 12:15:16.081448 RX Delay -410 -> 252, step: 16
6735 12:15:16.088108 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6736 12:15:16.091469 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6737 12:15:16.095605 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6738 12:15:16.099002 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6739 12:15:16.104930 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6740 12:15:16.108191 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6741 12:15:16.112085 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6742 12:15:16.115029 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6743 12:15:16.121373 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6744 12:15:16.125101 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6745 12:15:16.128193 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6746 12:15:16.131024 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6747 12:15:16.138290 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6748 12:15:16.141035 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6749 12:15:16.144796 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6750 12:15:16.151199 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6751 12:15:16.151617 ==
6752 12:15:16.154678 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 12:15:16.157994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 12:15:16.158513 ==
6755 12:15:16.158846 DQS Delay:
6756 12:15:16.160863 DQS0 = 43, DQS1 = 51
6757 12:15:16.161278 DQM Delay:
6758 12:15:16.164663 DQM0 = 12, DQM1 = 14
6759 12:15:16.165200 DQ Delay:
6760 12:15:16.167808 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6761 12:15:16.170747 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6762 12:15:16.174330 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6763 12:15:16.177946 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6764 12:15:16.178468
6765 12:15:16.178802
6766 12:15:16.179107 ==
6767 12:15:16.181072 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 12:15:16.183996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 12:15:16.184430 ==
6770 12:15:16.184863
6771 12:15:16.185273
6772 12:15:16.187913 TX Vref Scan disable
6773 12:15:16.190618 == TX Byte 0 ==
6774 12:15:16.194207 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6775 12:15:16.197805 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6776 12:15:16.200524 == TX Byte 1 ==
6777 12:15:16.203636 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6778 12:15:16.207375 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6779 12:15:16.207981 ==
6780 12:15:16.210793 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 12:15:16.213929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 12:15:16.214467 ==
6783 12:15:16.216775
6784 12:15:16.217198
6785 12:15:16.217629 TX Vref Scan disable
6786 12:15:16.220630 == TX Byte 0 ==
6787 12:15:16.223637 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6788 12:15:16.227008 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6789 12:15:16.230454 == TX Byte 1 ==
6790 12:15:16.233665 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6791 12:15:16.236549 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6792 12:15:16.236967
6793 12:15:16.239842 [DATLAT]
6794 12:15:16.240263 Freq=400, CH1 RK0
6795 12:15:16.240702
6796 12:15:16.243187 DATLAT Default: 0xf
6797 12:15:16.243607 0, 0xFFFF, sum = 0
6798 12:15:16.246564 1, 0xFFFF, sum = 0
6799 12:15:16.246992 2, 0xFFFF, sum = 0
6800 12:15:16.250306 3, 0xFFFF, sum = 0
6801 12:15:16.250760 4, 0xFFFF, sum = 0
6802 12:15:16.253258 5, 0xFFFF, sum = 0
6803 12:15:16.253684 6, 0xFFFF, sum = 0
6804 12:15:16.257196 7, 0xFFFF, sum = 0
6805 12:15:16.257776 8, 0xFFFF, sum = 0
6806 12:15:16.259777 9, 0xFFFF, sum = 0
6807 12:15:16.260204 10, 0xFFFF, sum = 0
6808 12:15:16.262707 11, 0xFFFF, sum = 0
6809 12:15:16.266979 12, 0xFFFF, sum = 0
6810 12:15:16.267513 13, 0x0, sum = 1
6811 12:15:16.267901 14, 0x0, sum = 2
6812 12:15:16.270303 15, 0x0, sum = 3
6813 12:15:16.270726 16, 0x0, sum = 4
6814 12:15:16.272908 best_step = 14
6815 12:15:16.273369
6816 12:15:16.273737 ==
6817 12:15:16.276419 Dram Type= 6, Freq= 0, CH_1, rank 0
6818 12:15:16.279702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 12:15:16.280208 ==
6820 12:15:16.282592 RX Vref Scan: 1
6821 12:15:16.283050
6822 12:15:16.283419 RX Vref 0 -> 0, step: 1
6823 12:15:16.286634
6824 12:15:16.287190 RX Delay -343 -> 252, step: 8
6825 12:15:16.287560
6826 12:15:16.289365 Set Vref, RX VrefLevel [Byte0]: 50
6827 12:15:16.292954 [Byte1]: 56
6828 12:15:16.298714
6829 12:15:16.299277 Final RX Vref Byte 0 = 50 to rank0
6830 12:15:16.301832 Final RX Vref Byte 1 = 56 to rank0
6831 12:15:16.304490 Final RX Vref Byte 0 = 50 to rank1
6832 12:15:16.307621 Final RX Vref Byte 1 = 56 to rank1==
6833 12:15:16.311181 Dram Type= 6, Freq= 0, CH_1, rank 0
6834 12:15:16.317534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 12:15:16.318095 ==
6836 12:15:16.318583 DQS Delay:
6837 12:15:16.320979 DQS0 = 44, DQS1 = 56
6838 12:15:16.321440 DQM Delay:
6839 12:15:16.321808 DQM0 = 9, DQM1 = 14
6840 12:15:16.324368 DQ Delay:
6841 12:15:16.328028 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6842 12:15:16.331360 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =4
6843 12:15:16.331970 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6844 12:15:16.333854 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6845 12:15:16.337041
6846 12:15:16.337499
6847 12:15:16.343973 [DQSOSCAuto] RK0, (LSB)MR18= 0x976e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6848 12:15:16.347905 CH1 RK0: MR19=C0C, MR18=976E
6849 12:15:16.353853 CH1_RK0: MR19=0xC0C, MR18=0x976E, DQSOSC=390, MR23=63, INC=388, DEC=258
6850 12:15:16.354317 ==
6851 12:15:16.357738 Dram Type= 6, Freq= 0, CH_1, rank 1
6852 12:15:16.360223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 12:15:16.360690 ==
6854 12:15:16.363848 [Gating] SW mode calibration
6855 12:15:16.370589 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6856 12:15:16.376625 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6857 12:15:16.380250 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6858 12:15:16.384269 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6859 12:15:16.390285 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6860 12:15:16.393139 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6861 12:15:16.396225 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6862 12:15:16.403776 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 12:15:16.406779 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6864 12:15:16.409866 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6865 12:15:16.416169 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6866 12:15:16.419483 Total UI for P1: 0, mck2ui 16
6867 12:15:16.422552 best dqsien dly found for B0: ( 0, 14, 24)
6868 12:15:16.425795 Total UI for P1: 0, mck2ui 16
6869 12:15:16.429617 best dqsien dly found for B1: ( 0, 14, 24)
6870 12:15:16.432576 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6871 12:15:16.436104 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6872 12:15:16.436580
6873 12:15:16.438983 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6874 12:15:16.442673 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6875 12:15:16.445690 [Gating] SW calibration Done
6876 12:15:16.446165 ==
6877 12:15:16.449658 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 12:15:16.452794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 12:15:16.453299 ==
6880 12:15:16.455821 RX Vref Scan: 0
6881 12:15:16.456281
6882 12:15:16.459869 RX Vref 0 -> 0, step: 1
6883 12:15:16.460434
6884 12:15:16.460803 RX Delay -410 -> 252, step: 16
6885 12:15:16.466751 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6886 12:15:16.470315 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6887 12:15:16.472939 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6888 12:15:16.478659 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6889 12:15:16.482031 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6890 12:15:16.485469 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6891 12:15:16.488554 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6892 12:15:16.495553 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6893 12:15:16.499099 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6894 12:15:16.502012 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6895 12:15:16.506179 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6896 12:15:16.512895 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6897 12:15:16.515223 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6898 12:15:16.518427 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6899 12:15:16.524846 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6900 12:15:16.529036 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6901 12:15:16.529606 ==
6902 12:15:16.531749 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 12:15:16.535259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 12:15:16.535783 ==
6905 12:15:16.538319 DQS Delay:
6906 12:15:16.538778 DQS0 = 51, DQS1 = 59
6907 12:15:16.539161 DQM Delay:
6908 12:15:16.541749 DQM0 = 19, DQM1 = 22
6909 12:15:16.542304 DQ Delay:
6910 12:15:16.544579 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6911 12:15:16.547785 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6912 12:15:16.551747 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6913 12:15:16.554961 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
6914 12:15:16.555522
6915 12:15:16.556001
6916 12:15:16.556353 ==
6917 12:15:16.557630 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 12:15:16.564482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 12:15:16.564943 ==
6920 12:15:16.565307
6921 12:15:16.565644
6922 12:15:16.565969 TX Vref Scan disable
6923 12:15:16.567877 == TX Byte 0 ==
6924 12:15:16.571188 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6925 12:15:16.574313 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6926 12:15:16.577639 == TX Byte 1 ==
6927 12:15:16.580673 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6928 12:15:16.584374 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6929 12:15:16.588122 ==
6930 12:15:16.590565 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 12:15:16.593924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 12:15:16.594420 ==
6933 12:15:16.594787
6934 12:15:16.595123
6935 12:15:16.597118 TX Vref Scan disable
6936 12:15:16.597578 == TX Byte 0 ==
6937 12:15:16.600300 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6938 12:15:16.607425 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6939 12:15:16.608039 == TX Byte 1 ==
6940 12:15:16.611220 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6941 12:15:16.617289 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6942 12:15:16.617918
6943 12:15:16.618292 [DATLAT]
6944 12:15:16.618633 Freq=400, CH1 RK1
6945 12:15:16.618969
6946 12:15:16.620355 DATLAT Default: 0xe
6947 12:15:16.620817 0, 0xFFFF, sum = 0
6948 12:15:16.623816 1, 0xFFFF, sum = 0
6949 12:15:16.626831 2, 0xFFFF, sum = 0
6950 12:15:16.627301 3, 0xFFFF, sum = 0
6951 12:15:16.630594 4, 0xFFFF, sum = 0
6952 12:15:16.631166 5, 0xFFFF, sum = 0
6953 12:15:16.633619 6, 0xFFFF, sum = 0
6954 12:15:16.634192 7, 0xFFFF, sum = 0
6955 12:15:16.636990 8, 0xFFFF, sum = 0
6956 12:15:16.637460 9, 0xFFFF, sum = 0
6957 12:15:16.639903 10, 0xFFFF, sum = 0
6958 12:15:16.640375 11, 0xFFFF, sum = 0
6959 12:15:16.643603 12, 0xFFFF, sum = 0
6960 12:15:16.644325 13, 0x0, sum = 1
6961 12:15:16.647654 14, 0x0, sum = 2
6962 12:15:16.648175 15, 0x0, sum = 3
6963 12:15:16.650340 16, 0x0, sum = 4
6964 12:15:16.650826 best_step = 14
6965 12:15:16.651192
6966 12:15:16.651531 ==
6967 12:15:16.653429 Dram Type= 6, Freq= 0, CH_1, rank 1
6968 12:15:16.656380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6969 12:15:16.660150 ==
6970 12:15:16.660621 RX Vref Scan: 0
6971 12:15:16.661098
6972 12:15:16.663411 RX Vref 0 -> 0, step: 1
6973 12:15:16.663936
6974 12:15:16.667311 RX Delay -359 -> 252, step: 8
6975 12:15:16.673023 iDelay=225, Bit 0, Center -28 (-271 ~ 216) 488
6976 12:15:16.677067 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
6977 12:15:16.679837 iDelay=225, Bit 2, Center -44 (-287 ~ 200) 488
6978 12:15:16.682959 iDelay=225, Bit 3, Center -36 (-271 ~ 200) 472
6979 12:15:16.690401 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
6980 12:15:16.692958 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
6981 12:15:16.696415 iDelay=225, Bit 6, Center -20 (-263 ~ 224) 488
6982 12:15:16.699894 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
6983 12:15:16.706584 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
6984 12:15:16.709785 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
6985 12:15:16.713167 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
6986 12:15:16.716002 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
6987 12:15:16.722856 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
6988 12:15:16.726389 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6989 12:15:16.729889 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6990 12:15:16.735828 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
6991 12:15:16.736406 ==
6992 12:15:16.739196 Dram Type= 6, Freq= 0, CH_1, rank 1
6993 12:15:16.742786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6994 12:15:16.743403 ==
6995 12:15:16.743923 DQS Delay:
6996 12:15:16.745930 DQS0 = 44, DQS1 = 56
6997 12:15:16.746362 DQM Delay:
6998 12:15:16.749667 DQM0 = 11, DQM1 = 11
6999 12:15:16.750189 DQ Delay:
7000 12:15:16.752162 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7001 12:15:16.755771 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
7002 12:15:16.759831 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7003 12:15:16.762434 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
7004 12:15:16.762953
7005 12:15:16.763288
7006 12:15:16.769397 [DQSOSCAuto] RK1, (LSB)MR18= 0x6653, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 396 ps
7007 12:15:16.772030 CH1 RK1: MR19=C0C, MR18=6653
7008 12:15:16.778889 CH1_RK1: MR19=0xC0C, MR18=0x6653, DQSOSC=396, MR23=63, INC=376, DEC=251
7009 12:15:16.782503 [RxdqsGatingPostProcess] freq 400
7010 12:15:16.789471 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7011 12:15:16.790036 best DQS0 dly(2T, 0.5T) = (0, 10)
7012 12:15:16.792032 best DQS1 dly(2T, 0.5T) = (0, 10)
7013 12:15:16.796699 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7014 12:15:16.799102 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7015 12:15:16.802320 best DQS0 dly(2T, 0.5T) = (0, 10)
7016 12:15:16.805246 best DQS1 dly(2T, 0.5T) = (0, 10)
7017 12:15:16.808406 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7018 12:15:16.812255 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7019 12:15:16.815270 Pre-setting of DQS Precalculation
7020 12:15:16.822139 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7021 12:15:16.828324 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7022 12:15:16.835630 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7023 12:15:16.836221
7024 12:15:16.836758
7025 12:15:16.838335 [Calibration Summary] 800 Mbps
7026 12:15:16.838872 CH 0, Rank 0
7027 12:15:16.841905 SW Impedance : PASS
7028 12:15:16.845803 DUTY Scan : NO K
7029 12:15:16.846440 ZQ Calibration : PASS
7030 12:15:16.848253 Jitter Meter : NO K
7031 12:15:16.851431 CBT Training : PASS
7032 12:15:16.851932 Write leveling : PASS
7033 12:15:16.854701 RX DQS gating : PASS
7034 12:15:16.858656 RX DQ/DQS(RDDQC) : PASS
7035 12:15:16.859221 TX DQ/DQS : PASS
7036 12:15:16.861552 RX DATLAT : PASS
7037 12:15:16.862122 RX DQ/DQS(Engine): PASS
7038 12:15:16.864687 TX OE : NO K
7039 12:15:16.865155 All Pass.
7040 12:15:16.865519
7041 12:15:16.867755 CH 0, Rank 1
7042 12:15:16.868214 SW Impedance : PASS
7043 12:15:16.871406 DUTY Scan : NO K
7044 12:15:16.874879 ZQ Calibration : PASS
7045 12:15:16.875445 Jitter Meter : NO K
7046 12:15:16.878149 CBT Training : PASS
7047 12:15:16.881940 Write leveling : NO K
7048 12:15:16.882584 RX DQS gating : PASS
7049 12:15:16.885051 RX DQ/DQS(RDDQC) : PASS
7050 12:15:16.888055 TX DQ/DQS : PASS
7051 12:15:16.888656 RX DATLAT : PASS
7052 12:15:16.891242 RX DQ/DQS(Engine): PASS
7053 12:15:16.894176 TX OE : NO K
7054 12:15:16.894642 All Pass.
7055 12:15:16.895011
7056 12:15:16.895348 CH 1, Rank 0
7057 12:15:16.898448 SW Impedance : PASS
7058 12:15:16.901125 DUTY Scan : NO K
7059 12:15:16.901593 ZQ Calibration : PASS
7060 12:15:16.904696 Jitter Meter : NO K
7061 12:15:16.907279 CBT Training : PASS
7062 12:15:16.907795 Write leveling : PASS
7063 12:15:16.911566 RX DQS gating : PASS
7064 12:15:16.913961 RX DQ/DQS(RDDQC) : PASS
7065 12:15:16.914424 TX DQ/DQS : PASS
7066 12:15:16.917505 RX DATLAT : PASS
7067 12:15:16.920745 RX DQ/DQS(Engine): PASS
7068 12:15:16.921208 TX OE : NO K
7069 12:15:16.924271 All Pass.
7070 12:15:16.924854
7071 12:15:16.925233 CH 1, Rank 1
7072 12:15:16.927165 SW Impedance : PASS
7073 12:15:16.927626 DUTY Scan : NO K
7074 12:15:16.930905 ZQ Calibration : PASS
7075 12:15:16.933600 Jitter Meter : NO K
7076 12:15:16.934058 CBT Training : PASS
7077 12:15:16.937100 Write leveling : NO K
7078 12:15:16.937582 RX DQS gating : PASS
7079 12:15:16.941763 RX DQ/DQS(RDDQC) : PASS
7080 12:15:16.944059 TX DQ/DQS : PASS
7081 12:15:16.944621 RX DATLAT : PASS
7082 12:15:16.947566 RX DQ/DQS(Engine): PASS
7083 12:15:16.950153 TX OE : NO K
7084 12:15:16.950616 All Pass.
7085 12:15:16.950984
7086 12:15:16.953595 DramC Write-DBI off
7087 12:15:16.954069 PER_BANK_REFRESH: Hybrid Mode
7088 12:15:16.957253 TX_TRACKING: ON
7089 12:15:16.967580 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7090 12:15:16.970566 [FAST_K] Save calibration result to emmc
7091 12:15:16.973136 dramc_set_vcore_voltage set vcore to 725000
7092 12:15:16.977070 Read voltage for 1600, 0
7093 12:15:16.977646 Vio18 = 0
7094 12:15:16.978020 Vcore = 725000
7095 12:15:16.980033 Vdram = 0
7096 12:15:16.980494 Vddq = 0
7097 12:15:16.980865 Vmddr = 0
7098 12:15:16.986444 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7099 12:15:16.990156 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7100 12:15:16.993162 MEM_TYPE=3, freq_sel=13
7101 12:15:16.996386 sv_algorithm_assistance_LP4_3733
7102 12:15:16.999945 ============ PULL DRAM RESETB DOWN ============
7103 12:15:17.003968 ========== PULL DRAM RESETB DOWN end =========
7104 12:15:17.009890 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7105 12:15:17.012950 ===================================
7106 12:15:17.013510 LPDDR4 DRAM CONFIGURATION
7107 12:15:17.016565 ===================================
7108 12:15:17.020573 EX_ROW_EN[0] = 0x0
7109 12:15:17.022789 EX_ROW_EN[1] = 0x0
7110 12:15:17.023251 LP4Y_EN = 0x0
7111 12:15:17.026707 WORK_FSP = 0x1
7112 12:15:17.027273 WL = 0x5
7113 12:15:17.029974 RL = 0x5
7114 12:15:17.030537 BL = 0x2
7115 12:15:17.033231 RPST = 0x0
7116 12:15:17.033792 RD_PRE = 0x0
7117 12:15:17.036687 WR_PRE = 0x1
7118 12:15:17.037183 WR_PST = 0x1
7119 12:15:17.039294 DBI_WR = 0x0
7120 12:15:17.039797 DBI_RD = 0x0
7121 12:15:17.043087 OTF = 0x1
7122 12:15:17.045952 ===================================
7123 12:15:17.049588 ===================================
7124 12:15:17.050095 ANA top config
7125 12:15:17.052903 ===================================
7126 12:15:17.057098 DLL_ASYNC_EN = 0
7127 12:15:17.059431 ALL_SLAVE_EN = 0
7128 12:15:17.062835 NEW_RANK_MODE = 1
7129 12:15:17.063396 DLL_IDLE_MODE = 1
7130 12:15:17.066842 LP45_APHY_COMB_EN = 1
7131 12:15:17.069437 TX_ODT_DIS = 0
7132 12:15:17.072619 NEW_8X_MODE = 1
7133 12:15:17.076115 ===================================
7134 12:15:17.079323 ===================================
7135 12:15:17.083185 data_rate = 3200
7136 12:15:17.085578 CKR = 1
7137 12:15:17.086039 DQ_P2S_RATIO = 8
7138 12:15:17.089297 ===================================
7139 12:15:17.092849 CA_P2S_RATIO = 8
7140 12:15:17.095908 DQ_CA_OPEN = 0
7141 12:15:17.099725 DQ_SEMI_OPEN = 0
7142 12:15:17.102341 CA_SEMI_OPEN = 0
7143 12:15:17.105821 CA_FULL_RATE = 0
7144 12:15:17.106433 DQ_CKDIV4_EN = 0
7145 12:15:17.109587 CA_CKDIV4_EN = 0
7146 12:15:17.112406 CA_PREDIV_EN = 0
7147 12:15:17.115590 PH8_DLY = 12
7148 12:15:17.119005 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7149 12:15:17.122266 DQ_AAMCK_DIV = 4
7150 12:15:17.122853 CA_AAMCK_DIV = 4
7151 12:15:17.125767 CA_ADMCK_DIV = 4
7152 12:15:17.128332 DQ_TRACK_CA_EN = 0
7153 12:15:17.131837 CA_PICK = 1600
7154 12:15:17.135668 CA_MCKIO = 1600
7155 12:15:17.138500 MCKIO_SEMI = 0
7156 12:15:17.142122 PLL_FREQ = 3068
7157 12:15:17.145220 DQ_UI_PI_RATIO = 32
7158 12:15:17.145899 CA_UI_PI_RATIO = 0
7159 12:15:17.149434 ===================================
7160 12:15:17.151388 ===================================
7161 12:15:17.155426 memory_type:LPDDR4
7162 12:15:17.158135 GP_NUM : 10
7163 12:15:17.158635 SRAM_EN : 1
7164 12:15:17.161644 MD32_EN : 0
7165 12:15:17.164902 ===================================
7166 12:15:17.168176 [ANA_INIT] >>>>>>>>>>>>>>
7167 12:15:17.171146 <<<<<< [CONFIGURE PHASE]: ANA_TX
7168 12:15:17.174890 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7169 12:15:17.177760 ===================================
7170 12:15:17.178243 data_rate = 3200,PCW = 0X7600
7171 12:15:17.181219 ===================================
7172 12:15:17.184701 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7173 12:15:17.191402 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7174 12:15:17.198034 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7175 12:15:17.201471 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7176 12:15:17.204490 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7177 12:15:17.207956 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7178 12:15:17.211019 [ANA_INIT] flow start
7179 12:15:17.214790 [ANA_INIT] PLL >>>>>>>>
7180 12:15:17.215243 [ANA_INIT] PLL <<<<<<<<
7181 12:15:17.217576 [ANA_INIT] MIDPI >>>>>>>>
7182 12:15:17.221162 [ANA_INIT] MIDPI <<<<<<<<
7183 12:15:17.221754 [ANA_INIT] DLL >>>>>>>>
7184 12:15:17.224719 [ANA_INIT] DLL <<<<<<<<
7185 12:15:17.227476 [ANA_INIT] flow end
7186 12:15:17.231330 ============ LP4 DIFF to SE enter ============
7187 12:15:17.234875 ============ LP4 DIFF to SE exit ============
7188 12:15:17.237893 [ANA_INIT] <<<<<<<<<<<<<
7189 12:15:17.241647 [Flow] Enable top DCM control >>>>>
7190 12:15:17.244421 [Flow] Enable top DCM control <<<<<
7191 12:15:17.247770 Enable DLL master slave shuffle
7192 12:15:17.250812 ==============================================================
7193 12:15:17.254274 Gating Mode config
7194 12:15:17.261008 ==============================================================
7195 12:15:17.261487 Config description:
7196 12:15:17.271029 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7197 12:15:17.276824 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7198 12:15:17.283981 SELPH_MODE 0: By rank 1: By Phase
7199 12:15:17.287283 ==============================================================
7200 12:15:17.290352 GAT_TRACK_EN = 1
7201 12:15:17.293670 RX_GATING_MODE = 2
7202 12:15:17.296676 RX_GATING_TRACK_MODE = 2
7203 12:15:17.300949 SELPH_MODE = 1
7204 12:15:17.303777 PICG_EARLY_EN = 1
7205 12:15:17.306738 VALID_LAT_VALUE = 1
7206 12:15:17.310572 ==============================================================
7207 12:15:17.313077 Enter into Gating configuration >>>>
7208 12:15:17.316883 Exit from Gating configuration <<<<
7209 12:15:17.321061 Enter into DVFS_PRE_config >>>>>
7210 12:15:17.333109 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7211 12:15:17.336280 Exit from DVFS_PRE_config <<<<<
7212 12:15:17.339494 Enter into PICG configuration >>>>
7213 12:15:17.343251 Exit from PICG configuration <<<<
7214 12:15:17.343831 [RX_INPUT] configuration >>>>>
7215 12:15:17.346204 [RX_INPUT] configuration <<<<<
7216 12:15:17.352905 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7217 12:15:17.355976 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7218 12:15:17.362963 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7219 12:15:17.369922 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7220 12:15:17.375777 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7221 12:15:17.382494 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7222 12:15:17.386247 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7223 12:15:17.388886 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7224 12:15:17.395407 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7225 12:15:17.399272 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7226 12:15:17.402307 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7227 12:15:17.409109 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7228 12:15:17.412604 ===================================
7229 12:15:17.413154 LPDDR4 DRAM CONFIGURATION
7230 12:15:17.415523 ===================================
7231 12:15:17.419384 EX_ROW_EN[0] = 0x0
7232 12:15:17.419953 EX_ROW_EN[1] = 0x0
7233 12:15:17.422066 LP4Y_EN = 0x0
7234 12:15:17.422585 WORK_FSP = 0x1
7235 12:15:17.425428 WL = 0x5
7236 12:15:17.428627 RL = 0x5
7237 12:15:17.429070 BL = 0x2
7238 12:15:17.432054 RPST = 0x0
7239 12:15:17.432615 RD_PRE = 0x0
7240 12:15:17.435307 WR_PRE = 0x1
7241 12:15:17.435895 WR_PST = 0x1
7242 12:15:17.438449 DBI_WR = 0x0
7243 12:15:17.438910 DBI_RD = 0x0
7244 12:15:17.441962 OTF = 0x1
7245 12:15:17.445376 ===================================
7246 12:15:17.448476 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7247 12:15:17.451466 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7248 12:15:17.458706 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7249 12:15:17.461783 ===================================
7250 12:15:17.462355 LPDDR4 DRAM CONFIGURATION
7251 12:15:17.464961 ===================================
7252 12:15:17.468199 EX_ROW_EN[0] = 0x10
7253 12:15:17.468755 EX_ROW_EN[1] = 0x0
7254 12:15:17.471822 LP4Y_EN = 0x0
7255 12:15:17.472321 WORK_FSP = 0x1
7256 12:15:17.475270 WL = 0x5
7257 12:15:17.477975 RL = 0x5
7258 12:15:17.478447 BL = 0x2
7259 12:15:17.481236 RPST = 0x0
7260 12:15:17.481707 RD_PRE = 0x0
7261 12:15:17.484708 WR_PRE = 0x1
7262 12:15:17.485210 WR_PST = 0x1
7263 12:15:17.487980 DBI_WR = 0x0
7264 12:15:17.488456 DBI_RD = 0x0
7265 12:15:17.491605 OTF = 0x1
7266 12:15:17.494960 ===================================
7267 12:15:17.501784 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7268 12:15:17.502352 ==
7269 12:15:17.504507 Dram Type= 6, Freq= 0, CH_0, rank 0
7270 12:15:17.508041 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7271 12:15:17.508517 ==
7272 12:15:17.511305 [Duty_Offset_Calibration]
7273 12:15:17.511829 B0:1 B1:-1 CA:0
7274 12:15:17.512489
7275 12:15:17.514134 [DutyScan_Calibration_Flow] k_type=0
7276 12:15:17.525285
7277 12:15:17.525844 ==CLK 0==
7278 12:15:17.528274 Final CLK duty delay cell = 0
7279 12:15:17.532382 [0] MAX Duty = 5124%(X100), DQS PI = 22
7280 12:15:17.534876 [0] MIN Duty = 4875%(X100), DQS PI = 10
7281 12:15:17.535437 [0] AVG Duty = 4999%(X100)
7282 12:15:17.537879
7283 12:15:17.541281 CH0 CLK Duty spec in!! Max-Min= 249%
7284 12:15:17.545055 [DutyScan_Calibration_Flow] ====Done====
7285 12:15:17.545626
7286 12:15:17.548557 [DutyScan_Calibration_Flow] k_type=1
7287 12:15:17.563839
7288 12:15:17.564399 ==DQS 0 ==
7289 12:15:17.567560 Final DQS duty delay cell = -4
7290 12:15:17.571109 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7291 12:15:17.574252 [-4] MIN Duty = 4844%(X100), DQS PI = 56
7292 12:15:17.577531 [-4] AVG Duty = 4906%(X100)
7293 12:15:17.578142
7294 12:15:17.578659 ==DQS 1 ==
7295 12:15:17.580621 Final DQS duty delay cell = 0
7296 12:15:17.583617 [0] MAX Duty = 5187%(X100), DQS PI = 4
7297 12:15:17.587441 [0] MIN Duty = 5031%(X100), DQS PI = 18
7298 12:15:17.590639 [0] AVG Duty = 5109%(X100)
7299 12:15:17.591205
7300 12:15:17.595007 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7301 12:15:17.595402
7302 12:15:17.596998 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7303 12:15:17.600216 [DutyScan_Calibration_Flow] ====Done====
7304 12:15:17.600508
7305 12:15:17.603743 [DutyScan_Calibration_Flow] k_type=3
7306 12:15:17.621777
7307 12:15:17.622470 ==DQM 0 ==
7308 12:15:17.624520 Final DQM duty delay cell = 0
7309 12:15:17.628502 [0] MAX Duty = 5124%(X100), DQS PI = 20
7310 12:15:17.632065 [0] MIN Duty = 4907%(X100), DQS PI = 10
7311 12:15:17.634708 [0] AVG Duty = 5015%(X100)
7312 12:15:17.635264
7313 12:15:17.635625 ==DQM 1 ==
7314 12:15:17.638158 Final DQM duty delay cell = 0
7315 12:15:17.641394 [0] MAX Duty = 5000%(X100), DQS PI = 2
7316 12:15:17.644986 [0] MIN Duty = 4813%(X100), DQS PI = 20
7317 12:15:17.648036 [0] AVG Duty = 4906%(X100)
7318 12:15:17.648594
7319 12:15:17.651107 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7320 12:15:17.651596
7321 12:15:17.654320 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7322 12:15:17.658159 [DutyScan_Calibration_Flow] ====Done====
7323 12:15:17.658703
7324 12:15:17.661800 [DutyScan_Calibration_Flow] k_type=2
7325 12:15:17.678158
7326 12:15:17.678707 ==DQ 0 ==
7327 12:15:17.681164 Final DQ duty delay cell = -4
7328 12:15:17.684900 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7329 12:15:17.687728 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7330 12:15:17.691006 [-4] AVG Duty = 4953%(X100)
7331 12:15:17.691461
7332 12:15:17.691876 ==DQ 1 ==
7333 12:15:17.694994 Final DQ duty delay cell = 0
7334 12:15:17.698062 [0] MAX Duty = 5125%(X100), DQS PI = 4
7335 12:15:17.702171 [0] MIN Duty = 5000%(X100), DQS PI = 36
7336 12:15:17.704087 [0] AVG Duty = 5062%(X100)
7337 12:15:17.704541
7338 12:15:17.707790 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7339 12:15:17.708251
7340 12:15:17.711080 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7341 12:15:17.714199 [DutyScan_Calibration_Flow] ====Done====
7342 12:15:17.714774 ==
7343 12:15:17.718162 Dram Type= 6, Freq= 0, CH_1, rank 0
7344 12:15:17.720981 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7345 12:15:17.721541 ==
7346 12:15:17.724052 [Duty_Offset_Calibration]
7347 12:15:17.724531 B0:-1 B1:1 CA:2
7348 12:15:17.724895
7349 12:15:17.727060 [DutyScan_Calibration_Flow] k_type=0
7350 12:15:17.738433
7351 12:15:17.739077 ==CLK 0==
7352 12:15:17.741888 Final CLK duty delay cell = 0
7353 12:15:17.745281 [0] MAX Duty = 5187%(X100), DQS PI = 22
7354 12:15:17.748432 [0] MIN Duty = 5031%(X100), DQS PI = 14
7355 12:15:17.751419 [0] AVG Duty = 5109%(X100)
7356 12:15:17.751998
7357 12:15:17.755118 CH1 CLK Duty spec in!! Max-Min= 156%
7358 12:15:17.758372 [DutyScan_Calibration_Flow] ====Done====
7359 12:15:17.758923
7360 12:15:17.761795 [DutyScan_Calibration_Flow] k_type=1
7361 12:15:17.778649
7362 12:15:17.779202 ==DQS 0 ==
7363 12:15:17.781607 Final DQS duty delay cell = 0
7364 12:15:17.785141 [0] MAX Duty = 5156%(X100), DQS PI = 20
7365 12:15:17.789192 [0] MIN Duty = 4907%(X100), DQS PI = 42
7366 12:15:17.791097 [0] AVG Duty = 5031%(X100)
7367 12:15:17.791572
7368 12:15:17.792101 ==DQS 1 ==
7369 12:15:17.794797 Final DQS duty delay cell = 0
7370 12:15:17.798500 [0] MAX Duty = 5093%(X100), DQS PI = 6
7371 12:15:17.801333 [0] MIN Duty = 4969%(X100), DQS PI = 26
7372 12:15:17.804254 [0] AVG Duty = 5031%(X100)
7373 12:15:17.804728
7374 12:15:17.808239 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7375 12:15:17.808714
7376 12:15:17.811399 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7377 12:15:17.814267 [DutyScan_Calibration_Flow] ====Done====
7378 12:15:17.814744
7379 12:15:17.817694 [DutyScan_Calibration_Flow] k_type=3
7380 12:15:17.836038
7381 12:15:17.836608 ==DQM 0 ==
7382 12:15:17.838531 Final DQM duty delay cell = 0
7383 12:15:17.842253 [0] MAX Duty = 5187%(X100), DQS PI = 4
7384 12:15:17.845048 [0] MIN Duty = 5031%(X100), DQS PI = 40
7385 12:15:17.848403 [0] AVG Duty = 5109%(X100)
7386 12:15:17.848875
7387 12:15:17.849380 ==DQM 1 ==
7388 12:15:17.851205 Final DQM duty delay cell = 0
7389 12:15:17.855136 [0] MAX Duty = 5187%(X100), DQS PI = 34
7390 12:15:17.859191 [0] MIN Duty = 4969%(X100), DQS PI = 0
7391 12:15:17.861492 [0] AVG Duty = 5078%(X100)
7392 12:15:17.862065
7393 12:15:17.864528 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7394 12:15:17.865000
7395 12:15:17.868318 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7396 12:15:17.871448 [DutyScan_Calibration_Flow] ====Done====
7397 12:15:17.872070
7398 12:15:17.874236 [DutyScan_Calibration_Flow] k_type=2
7399 12:15:17.892088
7400 12:15:17.892652 ==DQ 0 ==
7401 12:15:17.895858 Final DQ duty delay cell = 0
7402 12:15:17.899115 [0] MAX Duty = 5156%(X100), DQS PI = 0
7403 12:15:17.902229 [0] MIN Duty = 4906%(X100), DQS PI = 40
7404 12:15:17.902789 [0] AVG Duty = 5031%(X100)
7405 12:15:17.903157
7406 12:15:17.905664 ==DQ 1 ==
7407 12:15:17.908479 Final DQ duty delay cell = 0
7408 12:15:17.912565 [0] MAX Duty = 5156%(X100), DQS PI = 42
7409 12:15:17.915381 [0] MIN Duty = 4969%(X100), DQS PI = 26
7410 12:15:17.915978 [0] AVG Duty = 5062%(X100)
7411 12:15:17.916344
7412 12:15:17.918741 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7413 12:15:17.921630
7414 12:15:17.925506 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7415 12:15:17.928193 [DutyScan_Calibration_Flow] ====Done====
7416 12:15:17.931751 nWR fixed to 30
7417 12:15:17.932310 [ModeRegInit_LP4] CH0 RK0
7418 12:15:17.934836 [ModeRegInit_LP4] CH0 RK1
7419 12:15:17.937856 [ModeRegInit_LP4] CH1 RK0
7420 12:15:17.942126 [ModeRegInit_LP4] CH1 RK1
7421 12:15:17.942691 match AC timing 5
7422 12:15:17.948245 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7423 12:15:17.951171 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7424 12:15:17.954940 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7425 12:15:17.961277 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7426 12:15:17.964259 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7427 12:15:17.964726 [MiockJmeterHQA]
7428 12:15:17.965091
7429 12:15:17.967816 [DramcMiockJmeter] u1RxGatingPI = 0
7430 12:15:17.970696 0 : 4252, 4027
7431 12:15:17.971159 4 : 4253, 4026
7432 12:15:17.974716 8 : 4363, 4137
7433 12:15:17.975290 12 : 4363, 4137
7434 12:15:17.975668 16 : 4363, 4138
7435 12:15:17.977905 20 : 4253, 4027
7436 12:15:17.978480 24 : 4252, 4027
7437 12:15:17.981178 28 : 4252, 4027
7438 12:15:17.981747 32 : 4252, 4027
7439 12:15:17.984917 36 : 4255, 4029
7440 12:15:17.985482 40 : 4363, 4137
7441 12:15:17.987974 44 : 4252, 4027
7442 12:15:17.988438 48 : 4253, 4026
7443 12:15:17.988808 52 : 4252, 4027
7444 12:15:17.991505 56 : 4254, 4029
7445 12:15:17.992130 60 : 4253, 4027
7446 12:15:17.994405 64 : 4360, 4137
7447 12:15:17.994972 68 : 4361, 4137
7448 12:15:17.997409 72 : 4250, 4027
7449 12:15:17.997975 76 : 4250, 4027
7450 12:15:18.000766 80 : 4250, 4027
7451 12:15:18.001357 84 : 4250, 4027
7452 12:15:18.001734 88 : 4252, 4027
7453 12:15:18.003984 92 : 4360, 412
7454 12:15:18.004448 96 : 4252, 0
7455 12:15:18.007814 100 : 4360, 0
7456 12:15:18.008277 104 : 4361, 0
7457 12:15:18.008645 108 : 4360, 0
7458 12:15:18.011044 112 : 4249, 0
7459 12:15:18.011617 116 : 4250, 0
7460 12:15:18.014527 120 : 4250, 0
7461 12:15:18.015109 124 : 4252, 0
7462 12:15:18.015485 128 : 4250, 0
7463 12:15:18.017147 132 : 4250, 0
7464 12:15:18.017611 136 : 4250, 0
7465 12:15:18.020463 140 : 4250, 0
7466 12:15:18.020928 144 : 4250, 0
7467 12:15:18.021299 148 : 4252, 0
7468 12:15:18.024262 152 : 4361, 0
7469 12:15:18.024823 156 : 4361, 0
7470 12:15:18.027270 160 : 4363, 0
7471 12:15:18.027757 164 : 4249, 0
7472 12:15:18.028133 168 : 4250, 0
7473 12:15:18.031114 172 : 4250, 0
7474 12:15:18.031732 176 : 4249, 0
7475 12:15:18.032119 180 : 4250, 0
7476 12:15:18.033718 184 : 4250, 0
7477 12:15:18.034184 188 : 4252, 0
7478 12:15:18.037160 192 : 4250, 0
7479 12:15:18.037629 196 : 4360, 0
7480 12:15:18.037996 200 : 4250, 0
7481 12:15:18.040535 204 : 4360, 0
7482 12:15:18.040999 208 : 4361, 0
7483 12:15:18.043618 212 : 4250, 0
7484 12:15:18.044234 216 : 4249, 0
7485 12:15:18.044609 220 : 4250, 0
7486 12:15:18.047484 224 : 4250, 315
7487 12:15:18.048100 228 : 4250, 3546
7488 12:15:18.051349 232 : 4250, 4027
7489 12:15:18.052001 236 : 4361, 4137
7490 12:15:18.053589 240 : 4250, 4027
7491 12:15:18.054054 244 : 4250, 4027
7492 12:15:18.056685 248 : 4250, 4026
7493 12:15:18.057152 252 : 4253, 4029
7494 12:15:18.060504 256 : 4250, 4027
7495 12:15:18.061074 260 : 4250, 4027
7496 12:15:18.063542 264 : 4361, 4137
7497 12:15:18.064149 268 : 4250, 4026
7498 12:15:18.064530 272 : 4250, 4027
7499 12:15:18.066889 276 : 4360, 4138
7500 12:15:18.067452 280 : 4250, 4027
7501 12:15:18.070192 284 : 4250, 4027
7502 12:15:18.070660 288 : 4363, 4139
7503 12:15:18.073158 292 : 4250, 4027
7504 12:15:18.073653 296 : 4250, 4027
7505 12:15:18.076430 300 : 4250, 4027
7506 12:15:18.076956 304 : 4252, 4029
7507 12:15:18.079811 308 : 4250, 4027
7508 12:15:18.080320 312 : 4250, 4027
7509 12:15:18.083537 316 : 4361, 4137
7510 12:15:18.084041 320 : 4250, 4026
7511 12:15:18.086642 324 : 4250, 4027
7512 12:15:18.087197 328 : 4360, 4138
7513 12:15:18.089726 332 : 4253, 4027
7514 12:15:18.090144 336 : 4250, 3726
7515 12:15:18.090535 340 : 4363, 2090
7516 12:15:18.093651
7517 12:15:18.094084 MIOCK jitter meter ch=0
7518 12:15:18.094426
7519 12:15:18.097103 1T = (340-92) = 248 dly cells
7520 12:15:18.103909 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7521 12:15:18.104360 ==
7522 12:15:18.106915 Dram Type= 6, Freq= 0, CH_0, rank 0
7523 12:15:18.109517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7524 12:15:18.109598 ==
7525 12:15:18.116093 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7526 12:15:18.119661 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7527 12:15:18.122561 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7528 12:15:18.129640 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7529 12:15:18.139390 [CA 0] Center 43 (13~74) winsize 62
7530 12:15:18.142104 [CA 1] Center 43 (13~74) winsize 62
7531 12:15:18.145187 [CA 2] Center 39 (10~69) winsize 60
7532 12:15:18.148484 [CA 3] Center 39 (9~69) winsize 61
7533 12:15:18.151376 [CA 4] Center 37 (8~66) winsize 59
7534 12:15:18.155543 [CA 5] Center 36 (7~66) winsize 60
7535 12:15:18.156023
7536 12:15:18.158535 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7537 12:15:18.158984
7538 12:15:18.165610 [CATrainingPosCal] consider 1 rank data
7539 12:15:18.166019 u2DelayCellTimex100 = 262/100 ps
7540 12:15:18.171957 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7541 12:15:18.175532 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7542 12:15:18.178261 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7543 12:15:18.182128 CA3 delay=39 (9~69),Diff = 3 PI (11 cell)
7544 12:15:18.184998 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7545 12:15:18.188491 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7546 12:15:18.188917
7547 12:15:18.191733 CA PerBit enable=1, Macro0, CA PI delay=36
7548 12:15:18.192162
7549 12:15:18.194751 [CBTSetCACLKResult] CA Dly = 36
7550 12:15:18.198088 CS Dly: 11 (0~42)
7551 12:15:18.201516 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7552 12:15:18.204876 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7553 12:15:18.205353 ==
7554 12:15:18.208300 Dram Type= 6, Freq= 0, CH_0, rank 1
7555 12:15:18.215101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7556 12:15:18.215743 ==
7557 12:15:18.217716 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7558 12:15:18.225449 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7559 12:15:18.228195 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7560 12:15:18.234394 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7561 12:15:18.242764 [CA 0] Center 42 (12~73) winsize 62
7562 12:15:18.245592 [CA 1] Center 43 (13~73) winsize 61
7563 12:15:18.249632 [CA 2] Center 37 (8~67) winsize 60
7564 12:15:18.252638 [CA 3] Center 37 (7~67) winsize 61
7565 12:15:18.255914 [CA 4] Center 35 (6~65) winsize 60
7566 12:15:18.258933 [CA 5] Center 35 (5~65) winsize 61
7567 12:15:18.259360
7568 12:15:18.262408 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7569 12:15:18.262872
7570 12:15:18.265793 [CATrainingPosCal] consider 2 rank data
7571 12:15:18.269549 u2DelayCellTimex100 = 262/100 ps
7572 12:15:18.275643 CA0 delay=43 (13~73),Diff = 7 PI (26 cell)
7573 12:15:18.278697 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7574 12:15:18.282675 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7575 12:15:18.285067 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7576 12:15:18.289017 CA4 delay=36 (8~65),Diff = 0 PI (0 cell)
7577 12:15:18.291928 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7578 12:15:18.292354
7579 12:15:18.295359 CA PerBit enable=1, Macro0, CA PI delay=36
7580 12:15:18.295955
7581 12:15:18.299263 [CBTSetCACLKResult] CA Dly = 36
7582 12:15:18.302074 CS Dly: 11 (0~43)
7583 12:15:18.305448 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7584 12:15:18.308833 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7585 12:15:18.309280
7586 12:15:18.311894 ----->DramcWriteLeveling(PI) begin...
7587 12:15:18.312335 ==
7588 12:15:18.315045 Dram Type= 6, Freq= 0, CH_0, rank 0
7589 12:15:18.322188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7590 12:15:18.322724 ==
7591 12:15:18.325007 Write leveling (Byte 0): 37 => 37
7592 12:15:18.327930 Write leveling (Byte 1): 27 => 27
7593 12:15:18.331581 DramcWriteLeveling(PI) end<-----
7594 12:15:18.332156
7595 12:15:18.332549 ==
7596 12:15:18.334965 Dram Type= 6, Freq= 0, CH_0, rank 0
7597 12:15:18.337933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7598 12:15:18.338453 ==
7599 12:15:18.341815 [Gating] SW mode calibration
7600 12:15:18.348051 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7601 12:15:18.352302 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7602 12:15:18.357983 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 12:15:18.361211 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 12:15:18.368742 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 12:15:18.371708 1 4 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7606 12:15:18.374247 1 4 16 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7607 12:15:18.377777 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7608 12:15:18.384201 1 4 24 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
7609 12:15:18.387403 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7610 12:15:18.390863 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 12:15:18.398132 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7612 12:15:18.400775 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7613 12:15:18.407339 1 5 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 0)
7614 12:15:18.410780 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7615 12:15:18.414373 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7616 12:15:18.420402 1 5 24 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
7617 12:15:18.424115 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 12:15:18.427130 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 12:15:18.433550 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 12:15:18.437196 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7621 12:15:18.439928 1 6 12 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7622 12:15:18.446839 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7623 12:15:18.450147 1 6 20 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7624 12:15:18.453694 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7625 12:15:18.460741 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 12:15:18.463372 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 12:15:18.467026 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 12:15:18.473361 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 12:15:18.476174 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7630 12:15:18.480120 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7631 12:15:18.486552 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7632 12:15:18.489703 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7633 12:15:18.493661 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 12:15:18.500040 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 12:15:18.502871 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 12:15:18.507001 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 12:15:18.513040 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 12:15:18.516308 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 12:15:18.520349 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 12:15:18.526438 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 12:15:18.529369 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 12:15:18.532772 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 12:15:18.539252 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 12:15:18.542640 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7645 12:15:18.545780 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7646 12:15:18.552587 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7647 12:15:18.553143 Total UI for P1: 0, mck2ui 16
7648 12:15:18.559516 best dqsien dly found for B0: ( 1, 9, 10)
7649 12:15:18.562567 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7650 12:15:18.565506 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7651 12:15:18.568433 Total UI for P1: 0, mck2ui 16
7652 12:15:18.572073 best dqsien dly found for B1: ( 1, 9, 20)
7653 12:15:18.576059 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7654 12:15:18.578933 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7655 12:15:18.579492
7656 12:15:18.585893 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7657 12:15:18.589094 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7658 12:15:18.589561 [Gating] SW calibration Done
7659 12:15:18.592405 ==
7660 12:15:18.595553 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 12:15:18.599108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 12:15:18.599580 ==
7663 12:15:18.599994 RX Vref Scan: 0
7664 12:15:18.600342
7665 12:15:18.602190 RX Vref 0 -> 0, step: 1
7666 12:15:18.602649
7667 12:15:18.605169 RX Delay 0 -> 252, step: 8
7668 12:15:18.608826 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7669 12:15:18.611642 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7670 12:15:18.615481 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7671 12:15:18.622047 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7672 12:15:18.624748 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7673 12:15:18.628771 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7674 12:15:18.631617 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7675 12:15:18.635149 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7676 12:15:18.641726 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7677 12:15:18.644478 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7678 12:15:18.647905 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7679 12:15:18.651394 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7680 12:15:18.657934 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7681 12:15:18.661169 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7682 12:15:18.664630 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7683 12:15:18.667668 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7684 12:15:18.668271 ==
7685 12:15:18.670839 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 12:15:18.677641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 12:15:18.678208 ==
7688 12:15:18.678579 DQS Delay:
7689 12:15:18.681630 DQS0 = 0, DQS1 = 0
7690 12:15:18.682188 DQM Delay:
7691 12:15:18.682563 DQM0 = 136, DQM1 = 127
7692 12:15:18.684747 DQ Delay:
7693 12:15:18.687488 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7694 12:15:18.690695 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7695 12:15:18.694094 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7696 12:15:18.697360 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
7697 12:15:18.697832
7698 12:15:18.698200
7699 12:15:18.698544 ==
7700 12:15:18.701149 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 12:15:18.707063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 12:15:18.707630 ==
7703 12:15:18.708046
7704 12:15:18.708390
7705 12:15:18.708721 TX Vref Scan disable
7706 12:15:18.710405 == TX Byte 0 ==
7707 12:15:18.714021 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7708 12:15:18.720935 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7709 12:15:18.721501 == TX Byte 1 ==
7710 12:15:18.724096 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7711 12:15:18.730552 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7712 12:15:18.731116 ==
7713 12:15:18.733232 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 12:15:18.736681 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 12:15:18.737254 ==
7716 12:15:18.750079
7717 12:15:18.753893 TX Vref early break, caculate TX vref
7718 12:15:18.756724 TX Vref=16, minBit 4, minWin=22, winSum=372
7719 12:15:18.760139 TX Vref=18, minBit 0, minWin=23, winSum=379
7720 12:15:18.763578 TX Vref=20, minBit 14, minWin=23, winSum=392
7721 12:15:18.766437 TX Vref=22, minBit 4, minWin=24, winSum=405
7722 12:15:18.773315 TX Vref=24, minBit 5, minWin=24, winSum=406
7723 12:15:18.776583 TX Vref=26, minBit 1, minWin=25, winSum=416
7724 12:15:18.779945 TX Vref=28, minBit 1, minWin=25, winSum=417
7725 12:15:18.783049 TX Vref=30, minBit 0, minWin=24, winSum=406
7726 12:15:18.786574 TX Vref=32, minBit 0, minWin=24, winSum=398
7727 12:15:18.790381 TX Vref=34, minBit 0, minWin=23, winSum=392
7728 12:15:18.796980 [TxChooseVref] Worse bit 1, Min win 25, Win sum 417, Final Vref 28
7729 12:15:18.797548
7730 12:15:18.800379 Final TX Range 0 Vref 28
7731 12:15:18.800945
7732 12:15:18.801310 ==
7733 12:15:18.802839 Dram Type= 6, Freq= 0, CH_0, rank 0
7734 12:15:18.806939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7735 12:15:18.807502 ==
7736 12:15:18.807939
7737 12:15:18.808316
7738 12:15:18.809128 TX Vref Scan disable
7739 12:15:18.816281 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7740 12:15:18.817004 == TX Byte 0 ==
7741 12:15:18.819580 u2DelayCellOfst[0]=14 cells (4 PI)
7742 12:15:18.823551 u2DelayCellOfst[1]=18 cells (5 PI)
7743 12:15:18.826049 u2DelayCellOfst[2]=14 cells (4 PI)
7744 12:15:18.829732 u2DelayCellOfst[3]=14 cells (4 PI)
7745 12:15:18.832562 u2DelayCellOfst[4]=11 cells (3 PI)
7746 12:15:18.836875 u2DelayCellOfst[5]=0 cells (0 PI)
7747 12:15:18.839368 u2DelayCellOfst[6]=22 cells (6 PI)
7748 12:15:18.842882 u2DelayCellOfst[7]=22 cells (6 PI)
7749 12:15:18.846117 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7750 12:15:18.849424 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7751 12:15:18.852637 == TX Byte 1 ==
7752 12:15:18.855309 u2DelayCellOfst[8]=0 cells (0 PI)
7753 12:15:18.858582 u2DelayCellOfst[9]=0 cells (0 PI)
7754 12:15:18.861963 u2DelayCellOfst[10]=3 cells (1 PI)
7755 12:15:18.865724 u2DelayCellOfst[11]=0 cells (0 PI)
7756 12:15:18.869519 u2DelayCellOfst[12]=11 cells (3 PI)
7757 12:15:18.870265 u2DelayCellOfst[13]=11 cells (3 PI)
7758 12:15:18.871841 u2DelayCellOfst[14]=14 cells (4 PI)
7759 12:15:18.875563 u2DelayCellOfst[15]=7 cells (2 PI)
7760 12:15:18.882343 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7761 12:15:18.885344 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7762 12:15:18.885807 DramC Write-DBI on
7763 12:15:18.889340 ==
7764 12:15:18.892036 Dram Type= 6, Freq= 0, CH_0, rank 0
7765 12:15:18.895713 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7766 12:15:18.896242 ==
7767 12:15:18.896585
7768 12:15:18.896903
7769 12:15:18.898294 TX Vref Scan disable
7770 12:15:18.898713 == TX Byte 0 ==
7771 12:15:18.905322 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7772 12:15:18.905883 == TX Byte 1 ==
7773 12:15:18.908251 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7774 12:15:18.911991 DramC Write-DBI off
7775 12:15:18.912508
7776 12:15:18.912842 [DATLAT]
7777 12:15:18.915142 Freq=1600, CH0 RK0
7778 12:15:18.915568
7779 12:15:18.915942 DATLAT Default: 0xf
7780 12:15:18.918606 0, 0xFFFF, sum = 0
7781 12:15:18.919179 1, 0xFFFF, sum = 0
7782 12:15:18.921705 2, 0xFFFF, sum = 0
7783 12:15:18.922178 3, 0xFFFF, sum = 0
7784 12:15:18.924940 4, 0xFFFF, sum = 0
7785 12:15:18.927864 5, 0xFFFF, sum = 0
7786 12:15:18.928299 6, 0xFFFF, sum = 0
7787 12:15:18.931909 7, 0xFFFF, sum = 0
7788 12:15:18.932426 8, 0xFFFF, sum = 0
7789 12:15:18.934971 9, 0xFFFF, sum = 0
7790 12:15:18.935492 10, 0xFFFF, sum = 0
7791 12:15:18.938912 11, 0xFFFF, sum = 0
7792 12:15:18.939440 12, 0xFFFF, sum = 0
7793 12:15:18.941695 13, 0xFFFF, sum = 0
7794 12:15:18.942162 14, 0x0, sum = 1
7795 12:15:18.944455 15, 0x0, sum = 2
7796 12:15:18.944921 16, 0x0, sum = 3
7797 12:15:18.948175 17, 0x0, sum = 4
7798 12:15:18.948598 best_step = 15
7799 12:15:18.948957
7800 12:15:18.949359 ==
7801 12:15:18.951718 Dram Type= 6, Freq= 0, CH_0, rank 0
7802 12:15:18.954951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7803 12:15:18.958318 ==
7804 12:15:18.958778 RX Vref Scan: 1
7805 12:15:18.959140
7806 12:15:18.961359 Set Vref Range= 24 -> 127
7807 12:15:18.961830
7808 12:15:18.962195 RX Vref 24 -> 127, step: 1
7809 12:15:18.965218
7810 12:15:18.965787 RX Delay 19 -> 252, step: 4
7811 12:15:18.966158
7812 12:15:18.968164 Set Vref, RX VrefLevel [Byte0]: 24
7813 12:15:18.971040 [Byte1]: 24
7814 12:15:18.974748
7815 12:15:18.975257 Set Vref, RX VrefLevel [Byte0]: 25
7816 12:15:18.978752 [Byte1]: 25
7817 12:15:18.982345
7818 12:15:18.982874 Set Vref, RX VrefLevel [Byte0]: 26
7819 12:15:18.985691 [Byte1]: 26
7820 12:15:18.990068
7821 12:15:18.990495 Set Vref, RX VrefLevel [Byte0]: 27
7822 12:15:18.993957 [Byte1]: 27
7823 12:15:18.998115
7824 12:15:18.998783 Set Vref, RX VrefLevel [Byte0]: 28
7825 12:15:19.000934 [Byte1]: 28
7826 12:15:19.005019
7827 12:15:19.005556 Set Vref, RX VrefLevel [Byte0]: 29
7828 12:15:19.008976 [Byte1]: 29
7829 12:15:19.012890
7830 12:15:19.013303 Set Vref, RX VrefLevel [Byte0]: 30
7831 12:15:19.017010 [Byte1]: 30
7832 12:15:19.020785
7833 12:15:19.021301 Set Vref, RX VrefLevel [Byte0]: 31
7834 12:15:19.023578 [Byte1]: 31
7835 12:15:19.028248
7836 12:15:19.028763 Set Vref, RX VrefLevel [Byte0]: 32
7837 12:15:19.031338 [Byte1]: 32
7838 12:15:19.036046
7839 12:15:19.036562 Set Vref, RX VrefLevel [Byte0]: 33
7840 12:15:19.038875 [Byte1]: 33
7841 12:15:19.043340
7842 12:15:19.043811 Set Vref, RX VrefLevel [Byte0]: 34
7843 12:15:19.046401 [Byte1]: 34
7844 12:15:19.050857
7845 12:15:19.051331 Set Vref, RX VrefLevel [Byte0]: 35
7846 12:15:19.054027 [Byte1]: 35
7847 12:15:19.058454
7848 12:15:19.058927 Set Vref, RX VrefLevel [Byte0]: 36
7849 12:15:19.061821 [Byte1]: 36
7850 12:15:19.066180
7851 12:15:19.066708 Set Vref, RX VrefLevel [Byte0]: 37
7852 12:15:19.068790 [Byte1]: 37
7853 12:15:19.073408
7854 12:15:19.073932 Set Vref, RX VrefLevel [Byte0]: 38
7855 12:15:19.076387 [Byte1]: 38
7856 12:15:19.081155
7857 12:15:19.081681 Set Vref, RX VrefLevel [Byte0]: 39
7858 12:15:19.084014 [Byte1]: 39
7859 12:15:19.088872
7860 12:15:19.089397 Set Vref, RX VrefLevel [Byte0]: 40
7861 12:15:19.092002 [Byte1]: 40
7862 12:15:19.095787
7863 12:15:19.096324 Set Vref, RX VrefLevel [Byte0]: 41
7864 12:15:19.099359 [Byte1]: 41
7865 12:15:19.103829
7866 12:15:19.104352 Set Vref, RX VrefLevel [Byte0]: 42
7867 12:15:19.107144 [Byte1]: 42
7868 12:15:19.111187
7869 12:15:19.111611 Set Vref, RX VrefLevel [Byte0]: 43
7870 12:15:19.115174 [Byte1]: 43
7871 12:15:19.119134
7872 12:15:19.119649 Set Vref, RX VrefLevel [Byte0]: 44
7873 12:15:19.122969 [Byte1]: 44
7874 12:15:19.126562
7875 12:15:19.127078 Set Vref, RX VrefLevel [Byte0]: 45
7876 12:15:19.130044 [Byte1]: 45
7877 12:15:19.134394
7878 12:15:19.134952 Set Vref, RX VrefLevel [Byte0]: 46
7879 12:15:19.137104 [Byte1]: 46
7880 12:15:19.142245
7881 12:15:19.142708 Set Vref, RX VrefLevel [Byte0]: 47
7882 12:15:19.144885 [Byte1]: 47
7883 12:15:19.149617
7884 12:15:19.150174 Set Vref, RX VrefLevel [Byte0]: 48
7885 12:15:19.152409 [Byte1]: 48
7886 12:15:19.157049
7887 12:15:19.157672 Set Vref, RX VrefLevel [Byte0]: 49
7888 12:15:19.160153 [Byte1]: 49
7889 12:15:19.164245
7890 12:15:19.164816 Set Vref, RX VrefLevel [Byte0]: 50
7891 12:15:19.167434 [Byte1]: 50
7892 12:15:19.172417
7893 12:15:19.172881 Set Vref, RX VrefLevel [Byte0]: 51
7894 12:15:19.175531 [Byte1]: 51
7895 12:15:19.181078
7896 12:15:19.181662 Set Vref, RX VrefLevel [Byte0]: 52
7897 12:15:19.183519 [Byte1]: 52
7898 12:15:19.187476
7899 12:15:19.188091 Set Vref, RX VrefLevel [Byte0]: 53
7900 12:15:19.190571 [Byte1]: 53
7901 12:15:19.195608
7902 12:15:19.196211 Set Vref, RX VrefLevel [Byte0]: 54
7903 12:15:19.197608 [Byte1]: 54
7904 12:15:19.202391
7905 12:15:19.202947 Set Vref, RX VrefLevel [Byte0]: 55
7906 12:15:19.205589 [Byte1]: 55
7907 12:15:19.209987
7908 12:15:19.210454 Set Vref, RX VrefLevel [Byte0]: 56
7909 12:15:19.213102 [Byte1]: 56
7910 12:15:19.217215
7911 12:15:19.217773 Set Vref, RX VrefLevel [Byte0]: 57
7912 12:15:19.220988 [Byte1]: 57
7913 12:15:19.226394
7914 12:15:19.226948 Set Vref, RX VrefLevel [Byte0]: 58
7915 12:15:19.228052 [Byte1]: 58
7916 12:15:19.232417
7917 12:15:19.232882 Set Vref, RX VrefLevel [Byte0]: 59
7918 12:15:19.236049 [Byte1]: 59
7919 12:15:19.240607
7920 12:15:19.241165 Set Vref, RX VrefLevel [Byte0]: 60
7921 12:15:19.244042 [Byte1]: 60
7922 12:15:19.248203
7923 12:15:19.248761 Set Vref, RX VrefLevel [Byte0]: 61
7924 12:15:19.251469 [Byte1]: 61
7925 12:15:19.255297
7926 12:15:19.255897 Set Vref, RX VrefLevel [Byte0]: 62
7927 12:15:19.258490 [Byte1]: 62
7928 12:15:19.263097
7929 12:15:19.263655 Set Vref, RX VrefLevel [Byte0]: 63
7930 12:15:19.265732 [Byte1]: 63
7931 12:15:19.270245
7932 12:15:19.270805 Set Vref, RX VrefLevel [Byte0]: 64
7933 12:15:19.273467 [Byte1]: 64
7934 12:15:19.277376
7935 12:15:19.277835 Set Vref, RX VrefLevel [Byte0]: 65
7936 12:15:19.281579 [Byte1]: 65
7937 12:15:19.286288
7938 12:15:19.286842 Set Vref, RX VrefLevel [Byte0]: 66
7939 12:15:19.288763 [Byte1]: 66
7940 12:15:19.293492
7941 12:15:19.294040 Set Vref, RX VrefLevel [Byte0]: 67
7942 12:15:19.296343 [Byte1]: 67
7943 12:15:19.300968
7944 12:15:19.301454 Set Vref, RX VrefLevel [Byte0]: 68
7945 12:15:19.303842 [Byte1]: 68
7946 12:15:19.307943
7947 12:15:19.308429 Set Vref, RX VrefLevel [Byte0]: 69
7948 12:15:19.311233 [Byte1]: 69
7949 12:15:19.316010
7950 12:15:19.316890 Set Vref, RX VrefLevel [Byte0]: 70
7951 12:15:19.319787 [Byte1]: 70
7952 12:15:19.323736
7953 12:15:19.324513 Set Vref, RX VrefLevel [Byte0]: 71
7954 12:15:19.326152 [Byte1]: 71
7955 12:15:19.330320
7956 12:15:19.330736 Set Vref, RX VrefLevel [Byte0]: 72
7957 12:15:19.334013 [Byte1]: 72
7958 12:15:19.338491
7959 12:15:19.339061 Set Vref, RX VrefLevel [Byte0]: 73
7960 12:15:19.341462 [Byte1]: 73
7961 12:15:19.346700
7962 12:15:19.347225 Set Vref, RX VrefLevel [Byte0]: 74
7963 12:15:19.349035 [Byte1]: 74
7964 12:15:19.354163
7965 12:15:19.354577 Set Vref, RX VrefLevel [Byte0]: 75
7966 12:15:19.356636 [Byte1]: 75
7967 12:15:19.361738
7968 12:15:19.362150 Set Vref, RX VrefLevel [Byte0]: 76
7969 12:15:19.364435 [Byte1]: 76
7970 12:15:19.368776
7971 12:15:19.369299 Set Vref, RX VrefLevel [Byte0]: 77
7972 12:15:19.372296 [Byte1]: 77
7973 12:15:19.376305
7974 12:15:19.376830 Set Vref, RX VrefLevel [Byte0]: 78
7975 12:15:19.379993 [Byte1]: 78
7976 12:15:19.384268
7977 12:15:19.384682 Final RX Vref Byte 0 = 64 to rank0
7978 12:15:19.386991 Final RX Vref Byte 1 = 58 to rank0
7979 12:15:19.390432 Final RX Vref Byte 0 = 64 to rank1
7980 12:15:19.393941 Final RX Vref Byte 1 = 58 to rank1==
7981 12:15:19.397348 Dram Type= 6, Freq= 0, CH_0, rank 0
7982 12:15:19.404067 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7983 12:15:19.404590 ==
7984 12:15:19.404923 DQS Delay:
7985 12:15:19.407299 DQS0 = 0, DQS1 = 0
7986 12:15:19.407879 DQM Delay:
7987 12:15:19.408224 DQM0 = 133, DQM1 = 122
7988 12:15:19.410536 DQ Delay:
7989 12:15:19.413400 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
7990 12:15:19.416850 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
7991 12:15:19.420360 DQ8 =114, DQ9 =112, DQ10 =122, DQ11 =116
7992 12:15:19.424214 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =130
7993 12:15:19.424635
7994 12:15:19.424960
7995 12:15:19.425268
7996 12:15:19.427035 [DramC_TX_OE_Calibration] TA2
7997 12:15:19.430493 Original DQ_B0 (3 6) =30, OEN = 27
7998 12:15:19.433525 Original DQ_B1 (3 6) =30, OEN = 27
7999 12:15:19.436637 24, 0x0, End_B0=24 End_B1=24
8000 12:15:19.440292 25, 0x0, End_B0=25 End_B1=25
8001 12:15:19.440815 26, 0x0, End_B0=26 End_B1=26
8002 12:15:19.442810 27, 0x0, End_B0=27 End_B1=27
8003 12:15:19.447061 28, 0x0, End_B0=28 End_B1=28
8004 12:15:19.449873 29, 0x0, End_B0=29 End_B1=29
8005 12:15:19.450403 30, 0x0, End_B0=30 End_B1=30
8006 12:15:19.452990 31, 0x4141, End_B0=30 End_B1=30
8007 12:15:19.456960 Byte0 end_step=30 best_step=27
8008 12:15:19.459616 Byte1 end_step=30 best_step=27
8009 12:15:19.462943 Byte0 TX OE(2T, 0.5T) = (3, 3)
8010 12:15:19.467120 Byte1 TX OE(2T, 0.5T) = (3, 3)
8011 12:15:19.467636
8012 12:15:19.468025
8013 12:15:19.472883 [DQSOSCAuto] RK0, (LSB)MR18= 0x2011, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
8014 12:15:19.477089 CH0 RK0: MR19=303, MR18=2011
8015 12:15:19.482875 CH0_RK0: MR19=0x303, MR18=0x2011, DQSOSC=393, MR23=63, INC=23, DEC=15
8016 12:15:19.483382
8017 12:15:19.485914 ----->DramcWriteLeveling(PI) begin...
8018 12:15:19.486473 ==
8019 12:15:19.489328 Dram Type= 6, Freq= 0, CH_0, rank 1
8020 12:15:19.492358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8021 12:15:19.492809 ==
8022 12:15:19.496158 Write leveling (Byte 0): 36 => 36
8023 12:15:19.499086 Write leveling (Byte 1): 28 => 28
8024 12:15:19.502627 DramcWriteLeveling(PI) end<-----
8025 12:15:19.503145
8026 12:15:19.503473 ==
8027 12:15:19.506335 Dram Type= 6, Freq= 0, CH_0, rank 1
8028 12:15:19.512049 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 12:15:19.512554 ==
8030 12:15:19.512882 [Gating] SW mode calibration
8031 12:15:19.522850 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8032 12:15:19.525199 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8033 12:15:19.530201 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 12:15:19.535272 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 12:15:19.539347 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 12:15:19.541873 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8037 12:15:19.549047 1 4 16 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
8038 12:15:19.552049 1 4 20 | B1->B0 | 2c2b 3434 | 1 1 | (0 0) (1 1)
8039 12:15:19.555414 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8040 12:15:19.562003 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8041 12:15:19.566036 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8042 12:15:19.569663 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8043 12:15:19.575574 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8044 12:15:19.578489 1 5 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
8045 12:15:19.582132 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
8046 12:15:19.588203 1 5 20 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8047 12:15:19.591460 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8048 12:15:19.595115 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 12:15:19.601384 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 12:15:19.604521 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8051 12:15:19.608163 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 12:15:19.614359 1 6 12 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
8053 12:15:19.617975 1 6 16 | B1->B0 | 2828 4545 | 0 0 | (0 0) (0 0)
8054 12:15:19.621169 1 6 20 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
8055 12:15:19.627806 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 12:15:19.631816 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 12:15:19.634965 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 12:15:19.641740 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 12:15:19.644172 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 12:15:19.648188 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8061 12:15:19.654558 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8062 12:15:19.657905 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8063 12:15:19.661218 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 12:15:19.666996 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 12:15:19.670597 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 12:15:19.674233 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 12:15:19.680614 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 12:15:19.684293 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 12:15:19.687613 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 12:15:19.694054 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 12:15:19.696831 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 12:15:19.700582 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 12:15:19.706927 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 12:15:19.709929 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 12:15:19.713703 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8076 12:15:19.720260 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8077 12:15:19.723248 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8078 12:15:19.727161 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 12:15:19.730229 Total UI for P1: 0, mck2ui 16
8080 12:15:19.733590 best dqsien dly found for B0: ( 1, 9, 12)
8081 12:15:19.736539 Total UI for P1: 0, mck2ui 16
8082 12:15:19.740439 best dqsien dly found for B1: ( 1, 9, 18)
8083 12:15:19.742890 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8084 12:15:19.746943 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8085 12:15:19.749743
8086 12:15:19.753122 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8087 12:15:19.756679 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8088 12:15:19.760093 [Gating] SW calibration Done
8089 12:15:19.760574 ==
8090 12:15:19.763398 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 12:15:19.766403 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 12:15:19.766921 ==
8093 12:15:19.769666 RX Vref Scan: 0
8094 12:15:19.770121
8095 12:15:19.770485 RX Vref 0 -> 0, step: 1
8096 12:15:19.770948
8097 12:15:19.773620 RX Delay 0 -> 252, step: 8
8098 12:15:19.776681 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8099 12:15:19.779385 iDelay=200, Bit 1, Center 139 (80 ~ 199) 120
8100 12:15:19.786258 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8101 12:15:19.789989 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8102 12:15:19.793002 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8103 12:15:19.795968 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8104 12:15:19.799856 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8105 12:15:19.805835 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8106 12:15:19.808963 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8107 12:15:19.812254 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8108 12:15:19.815761 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8109 12:15:19.822143 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8110 12:15:19.826342 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8111 12:15:19.828625 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8112 12:15:19.832907 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8113 12:15:19.835588 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8114 12:15:19.838881 ==
8115 12:15:19.842388 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 12:15:19.845691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 12:15:19.846263 ==
8118 12:15:19.846639 DQS Delay:
8119 12:15:19.848415 DQS0 = 0, DQS1 = 0
8120 12:15:19.848878 DQM Delay:
8121 12:15:19.852516 DQM0 = 133, DQM1 = 129
8122 12:15:19.853072 DQ Delay:
8123 12:15:19.855394 DQ0 =135, DQ1 =139, DQ2 =127, DQ3 =127
8124 12:15:19.858650 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8125 12:15:19.862793 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =127
8126 12:15:19.865195 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8127 12:15:19.865754
8128 12:15:19.866127
8129 12:15:19.866471 ==
8130 12:15:19.868249 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 12:15:19.874734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 12:15:19.875204 ==
8133 12:15:19.875577
8134 12:15:19.875965
8135 12:15:19.878398 TX Vref Scan disable
8136 12:15:19.878861 == TX Byte 0 ==
8137 12:15:19.881685 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8138 12:15:19.888668 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8139 12:15:19.889190 == TX Byte 1 ==
8140 12:15:19.892681 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8141 12:15:19.898327 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8142 12:15:19.898835 ==
8143 12:15:19.901610 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 12:15:19.904912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 12:15:19.905433 ==
8146 12:15:19.919060
8147 12:15:19.921999 TX Vref early break, caculate TX vref
8148 12:15:19.925603 TX Vref=16, minBit 2, minWin=22, winSum=377
8149 12:15:19.928627 TX Vref=18, minBit 0, minWin=23, winSum=384
8150 12:15:19.931898 TX Vref=20, minBit 1, minWin=23, winSum=395
8151 12:15:19.935179 TX Vref=22, minBit 1, minWin=23, winSum=402
8152 12:15:19.941625 TX Vref=24, minBit 6, minWin=24, winSum=409
8153 12:15:19.944640 TX Vref=26, minBit 7, minWin=24, winSum=413
8154 12:15:19.948180 TX Vref=28, minBit 4, minWin=24, winSum=413
8155 12:15:19.951847 TX Vref=30, minBit 1, minWin=24, winSum=405
8156 12:15:19.955454 TX Vref=32, minBit 7, minWin=23, winSum=396
8157 12:15:19.958282 TX Vref=34, minBit 3, minWin=23, winSum=390
8158 12:15:19.964597 [TxChooseVref] Worse bit 7, Min win 24, Win sum 413, Final Vref 26
8159 12:15:19.965056
8160 12:15:19.968166 Final TX Range 0 Vref 26
8161 12:15:19.968625
8162 12:15:19.968988 ==
8163 12:15:19.971438 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 12:15:19.974716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 12:15:19.975238 ==
8166 12:15:19.975662
8167 12:15:19.976054
8168 12:15:19.978338 TX Vref Scan disable
8169 12:15:19.984124 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8170 12:15:19.984622 == TX Byte 0 ==
8171 12:15:19.988257 u2DelayCellOfst[0]=11 cells (3 PI)
8172 12:15:19.991189 u2DelayCellOfst[1]=14 cells (4 PI)
8173 12:15:19.994096 u2DelayCellOfst[2]=11 cells (3 PI)
8174 12:15:19.997292 u2DelayCellOfst[3]=14 cells (4 PI)
8175 12:15:20.000663 u2DelayCellOfst[4]=7 cells (2 PI)
8176 12:15:20.004176 u2DelayCellOfst[5]=0 cells (0 PI)
8177 12:15:20.007559 u2DelayCellOfst[6]=14 cells (4 PI)
8178 12:15:20.010874 u2DelayCellOfst[7]=18 cells (5 PI)
8179 12:15:20.014410 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8180 12:15:20.018639 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8181 12:15:20.020442 == TX Byte 1 ==
8182 12:15:20.023800 u2DelayCellOfst[8]=0 cells (0 PI)
8183 12:15:20.028251 u2DelayCellOfst[9]=3 cells (1 PI)
8184 12:15:20.031254 u2DelayCellOfst[10]=7 cells (2 PI)
8185 12:15:20.034136 u2DelayCellOfst[11]=3 cells (1 PI)
8186 12:15:20.034651 u2DelayCellOfst[12]=14 cells (4 PI)
8187 12:15:20.037023 u2DelayCellOfst[13]=11 cells (3 PI)
8188 12:15:20.041354 u2DelayCellOfst[14]=18 cells (5 PI)
8189 12:15:20.043877 u2DelayCellOfst[15]=11 cells (3 PI)
8190 12:15:20.050908 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8191 12:15:20.053973 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8192 12:15:20.054541 DramC Write-DBI on
8193 12:15:20.056833 ==
8194 12:15:20.060512 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 12:15:20.063851 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 12:15:20.064281 ==
8197 12:15:20.064624
8198 12:15:20.064937
8199 12:15:20.067217 TX Vref Scan disable
8200 12:15:20.067639 == TX Byte 0 ==
8201 12:15:20.073454 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8202 12:15:20.073882 == TX Byte 1 ==
8203 12:15:20.077152 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8204 12:15:20.080330 DramC Write-DBI off
8205 12:15:20.081035
8206 12:15:20.081449 [DATLAT]
8207 12:15:20.083223 Freq=1600, CH0 RK1
8208 12:15:20.083725
8209 12:15:20.084106 DATLAT Default: 0xf
8210 12:15:20.086520 0, 0xFFFF, sum = 0
8211 12:15:20.087070 1, 0xFFFF, sum = 0
8212 12:15:20.089766 2, 0xFFFF, sum = 0
8213 12:15:20.090233 3, 0xFFFF, sum = 0
8214 12:15:20.093240 4, 0xFFFF, sum = 0
8215 12:15:20.093671 5, 0xFFFF, sum = 0
8216 12:15:20.096530 6, 0xFFFF, sum = 0
8217 12:15:20.099965 7, 0xFFFF, sum = 0
8218 12:15:20.100398 8, 0xFFFF, sum = 0
8219 12:15:20.103792 9, 0xFFFF, sum = 0
8220 12:15:20.104306 10, 0xFFFF, sum = 0
8221 12:15:20.106776 11, 0xFFFF, sum = 0
8222 12:15:20.107302 12, 0xFFFF, sum = 0
8223 12:15:20.110517 13, 0xFFFF, sum = 0
8224 12:15:20.110961 14, 0x0, sum = 1
8225 12:15:20.113591 15, 0x0, sum = 2
8226 12:15:20.114117 16, 0x0, sum = 3
8227 12:15:20.117054 17, 0x0, sum = 4
8228 12:15:20.117583 best_step = 15
8229 12:15:20.117923
8230 12:15:20.118238 ==
8231 12:15:20.119610 Dram Type= 6, Freq= 0, CH_0, rank 1
8232 12:15:20.123120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8233 12:15:20.126072 ==
8234 12:15:20.126595 RX Vref Scan: 0
8235 12:15:20.126935
8236 12:15:20.129244 RX Vref 0 -> 0, step: 1
8237 12:15:20.129667
8238 12:15:20.132678 RX Delay 11 -> 252, step: 4
8239 12:15:20.136080 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8240 12:15:20.140576 iDelay=195, Bit 1, Center 136 (83 ~ 190) 108
8241 12:15:20.142656 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8242 12:15:20.149505 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8243 12:15:20.153024 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8244 12:15:20.156089 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8245 12:15:20.158974 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8246 12:15:20.162622 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8247 12:15:20.169465 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8248 12:15:20.172610 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8249 12:15:20.176085 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8250 12:15:20.178955 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8251 12:15:20.182855 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8252 12:15:20.189385 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8253 12:15:20.192741 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8254 12:15:20.195374 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8255 12:15:20.195891 ==
8256 12:15:20.198748 Dram Type= 6, Freq= 0, CH_0, rank 1
8257 12:15:20.201946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8258 12:15:20.205500 ==
8259 12:15:20.206059 DQS Delay:
8260 12:15:20.206432 DQS0 = 0, DQS1 = 0
8261 12:15:20.208522 DQM Delay:
8262 12:15:20.209010 DQM0 = 130, DQM1 = 125
8263 12:15:20.211849 DQ Delay:
8264 12:15:20.215274 DQ0 =128, DQ1 =136, DQ2 =126, DQ3 =128
8265 12:15:20.218714 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8266 12:15:20.222142 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8267 12:15:20.225020 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8268 12:15:20.225492
8269 12:15:20.225859
8270 12:15:20.226198
8271 12:15:20.228676 [DramC_TX_OE_Calibration] TA2
8272 12:15:20.231823 Original DQ_B0 (3 6) =30, OEN = 27
8273 12:15:20.235087 Original DQ_B1 (3 6) =30, OEN = 27
8274 12:15:20.238452 24, 0x0, End_B0=24 End_B1=24
8275 12:15:20.238980 25, 0x0, End_B0=25 End_B1=25
8276 12:15:20.241388 26, 0x0, End_B0=26 End_B1=26
8277 12:15:20.244543 27, 0x0, End_B0=27 End_B1=27
8278 12:15:20.248383 28, 0x0, End_B0=28 End_B1=28
8279 12:15:20.251943 29, 0x0, End_B0=29 End_B1=29
8280 12:15:20.252468 30, 0x0, End_B0=30 End_B1=30
8281 12:15:20.254604 31, 0x4545, End_B0=30 End_B1=30
8282 12:15:20.257973 Byte0 end_step=30 best_step=27
8283 12:15:20.261789 Byte1 end_step=30 best_step=27
8284 12:15:20.264627 Byte0 TX OE(2T, 0.5T) = (3, 3)
8285 12:15:20.267620 Byte1 TX OE(2T, 0.5T) = (3, 3)
8286 12:15:20.268079
8287 12:15:20.268417
8288 12:15:20.274485 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f02, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8289 12:15:20.278015 CH0 RK1: MR19=303, MR18=1F02
8290 12:15:20.284249 CH0_RK1: MR19=0x303, MR18=0x1F02, DQSOSC=394, MR23=63, INC=23, DEC=15
8291 12:15:20.287798 [RxdqsGatingPostProcess] freq 1600
8292 12:15:20.290868 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8293 12:15:20.294492 best DQS0 dly(2T, 0.5T) = (1, 1)
8294 12:15:20.297409 best DQS1 dly(2T, 0.5T) = (1, 1)
8295 12:15:20.300216 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8296 12:15:20.304045 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8297 12:15:20.307838 best DQS0 dly(2T, 0.5T) = (1, 1)
8298 12:15:20.311393 best DQS1 dly(2T, 0.5T) = (1, 1)
8299 12:15:20.313875 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8300 12:15:20.317200 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8301 12:15:20.321189 Pre-setting of DQS Precalculation
8302 12:15:20.324385 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8303 12:15:20.324958 ==
8304 12:15:20.327620 Dram Type= 6, Freq= 0, CH_1, rank 0
8305 12:15:20.333642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 12:15:20.334146 ==
8307 12:15:20.336967 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8308 12:15:20.344322 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8309 12:15:20.347274 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8310 12:15:20.353883 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8311 12:15:20.361067 [CA 0] Center 42 (13~72) winsize 60
8312 12:15:20.364347 [CA 1] Center 42 (13~72) winsize 60
8313 12:15:20.367733 [CA 2] Center 38 (9~67) winsize 59
8314 12:15:20.371124 [CA 3] Center 36 (7~66) winsize 60
8315 12:15:20.374539 [CA 4] Center 38 (9~67) winsize 59
8316 12:15:20.378192 [CA 5] Center 37 (8~67) winsize 60
8317 12:15:20.378924
8318 12:15:20.381255 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8319 12:15:20.381726
8320 12:15:20.384409 [CATrainingPosCal] consider 1 rank data
8321 12:15:20.388099 u2DelayCellTimex100 = 262/100 ps
8322 12:15:20.394789 CA0 delay=42 (13~72),Diff = 6 PI (22 cell)
8323 12:15:20.397606 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8324 12:15:20.400848 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8325 12:15:20.404326 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8326 12:15:20.407871 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8327 12:15:20.410603 CA5 delay=37 (8~67),Diff = 1 PI (3 cell)
8328 12:15:20.411180
8329 12:15:20.414231 CA PerBit enable=1, Macro0, CA PI delay=36
8330 12:15:20.414891
8331 12:15:20.417308 [CBTSetCACLKResult] CA Dly = 36
8332 12:15:20.420952 CS Dly: 9 (0~40)
8333 12:15:20.424046 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8334 12:15:20.427105 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8335 12:15:20.427690 ==
8336 12:15:20.430589 Dram Type= 6, Freq= 0, CH_1, rank 1
8337 12:15:20.437351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 12:15:20.437768 ==
8339 12:15:20.440362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8340 12:15:20.446735 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8341 12:15:20.450572 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8342 12:15:20.457212 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8343 12:15:20.464701 [CA 0] Center 42 (13~72) winsize 60
8344 12:15:20.467481 [CA 1] Center 42 (13~72) winsize 60
8345 12:15:20.471181 [CA 2] Center 37 (8~67) winsize 60
8346 12:15:20.474205 [CA 3] Center 37 (8~66) winsize 59
8347 12:15:20.478407 [CA 4] Center 37 (8~67) winsize 60
8348 12:15:20.481833 [CA 5] Center 37 (7~67) winsize 61
8349 12:15:20.482348
8350 12:15:20.484474 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8351 12:15:20.484889
8352 12:15:20.487772 [CATrainingPosCal] consider 2 rank data
8353 12:15:20.491208 u2DelayCellTimex100 = 262/100 ps
8354 12:15:20.497403 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8355 12:15:20.500634 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8356 12:15:20.504051 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8357 12:15:20.508118 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8358 12:15:20.510490 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8359 12:15:20.514392 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8360 12:15:20.514904
8361 12:15:20.518329 CA PerBit enable=1, Macro0, CA PI delay=37
8362 12:15:20.518846
8363 12:15:20.520573 [CBTSetCACLKResult] CA Dly = 37
8364 12:15:20.523956 CS Dly: 11 (0~44)
8365 12:15:20.528368 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8366 12:15:20.530335 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8367 12:15:20.530765
8368 12:15:20.534621 ----->DramcWriteLeveling(PI) begin...
8369 12:15:20.535215 ==
8370 12:15:20.537157 Dram Type= 6, Freq= 0, CH_1, rank 0
8371 12:15:20.543767 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8372 12:15:20.544310 ==
8373 12:15:20.546915 Write leveling (Byte 0): 23 => 23
8374 12:15:20.550102 Write leveling (Byte 1): 27 => 27
8375 12:15:20.553431 DramcWriteLeveling(PI) end<-----
8376 12:15:20.553861
8377 12:15:20.554240 ==
8378 12:15:20.557118 Dram Type= 6, Freq= 0, CH_1, rank 0
8379 12:15:20.559780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 12:15:20.560201 ==
8381 12:15:20.563004 [Gating] SW mode calibration
8382 12:15:20.569597 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8383 12:15:20.576547 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8384 12:15:20.579585 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 12:15:20.583112 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 12:15:20.589854 1 4 8 | B1->B0 | 2322 2423 | 1 1 | (0 0) (1 1)
8387 12:15:20.593150 1 4 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8388 12:15:20.596193 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 12:15:20.602574 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 12:15:20.606143 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 12:15:20.609891 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 12:15:20.615588 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 12:15:20.619316 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 12:15:20.622371 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8395 12:15:20.629052 1 5 12 | B1->B0 | 2e2e 2525 | 0 1 | (0 1) (1 0)
8396 12:15:20.632079 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 12:15:20.635836 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 12:15:20.641994 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 12:15:20.645116 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 12:15:20.648712 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 12:15:20.655240 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 12:15:20.658745 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 12:15:20.661882 1 6 12 | B1->B0 | 4141 4545 | 1 0 | (0 0) (0 0)
8404 12:15:20.668837 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 12:15:20.672236 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 12:15:20.675230 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 12:15:20.681968 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 12:15:20.684802 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 12:15:20.688487 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 12:15:20.695060 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 12:15:20.698171 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8412 12:15:20.701617 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 12:15:20.709178 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 12:15:20.711316 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 12:15:20.714463 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 12:15:20.721646 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 12:15:20.724516 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 12:15:20.727865 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 12:15:20.735012 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 12:15:20.738290 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 12:15:20.741362 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 12:15:20.747753 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 12:15:20.750550 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 12:15:20.754186 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 12:15:20.761033 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 12:15:20.764107 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8427 12:15:20.767402 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8428 12:15:20.774032 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8429 12:15:20.774605 Total UI for P1: 0, mck2ui 16
8430 12:15:20.780446 best dqsien dly found for B0: ( 1, 9, 10)
8431 12:15:20.784612 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 12:15:20.787529 Total UI for P1: 0, mck2ui 16
8433 12:15:20.790708 best dqsien dly found for B1: ( 1, 9, 12)
8434 12:15:20.793632 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8435 12:15:20.797101 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8436 12:15:20.797662
8437 12:15:20.800186 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8438 12:15:20.804111 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8439 12:15:20.806867 [Gating] SW calibration Done
8440 12:15:20.807449 ==
8441 12:15:20.810488 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 12:15:20.813822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 12:15:20.816774 ==
8444 12:15:20.817234 RX Vref Scan: 0
8445 12:15:20.817597
8446 12:15:20.820812 RX Vref 0 -> 0, step: 1
8447 12:15:20.821373
8448 12:15:20.823490 RX Delay 0 -> 252, step: 8
8449 12:15:20.826597 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8450 12:15:20.830038 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8451 12:15:20.833603 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8452 12:15:20.836648 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8453 12:15:20.843486 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8454 12:15:20.846735 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8455 12:15:20.850402 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8456 12:15:20.853072 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8457 12:15:20.856370 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8458 12:15:20.863305 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8459 12:15:20.866563 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8460 12:15:20.869868 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8461 12:15:20.873589 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8462 12:15:20.876198 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8463 12:15:20.883231 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8464 12:15:20.886631 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8465 12:15:20.887047 ==
8466 12:15:20.889527 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 12:15:20.892593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 12:15:20.893117 ==
8469 12:15:20.895798 DQS Delay:
8470 12:15:20.896319 DQS0 = 0, DQS1 = 0
8471 12:15:20.899348 DQM Delay:
8472 12:15:20.899827 DQM0 = 137, DQM1 = 129
8473 12:15:20.900166 DQ Delay:
8474 12:15:20.902412 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =135
8475 12:15:20.909640 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8476 12:15:20.912577 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8477 12:15:20.916056 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
8478 12:15:20.916587
8479 12:15:20.916916
8480 12:15:20.917221 ==
8481 12:15:20.918903 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 12:15:20.922342 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 12:15:20.922865 ==
8484 12:15:20.923200
8485 12:15:20.923512
8486 12:15:20.925528 TX Vref Scan disable
8487 12:15:20.928964 == TX Byte 0 ==
8488 12:15:20.932986 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8489 12:15:20.935906 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8490 12:15:20.939041 == TX Byte 1 ==
8491 12:15:20.942742 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8492 12:15:20.945280 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8493 12:15:20.945765 ==
8494 12:15:20.948252 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 12:15:20.954941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 12:15:20.955442 ==
8497 12:15:20.966825
8498 12:15:20.969865 TX Vref early break, caculate TX vref
8499 12:15:20.973190 TX Vref=16, minBit 0, minWin=21, winSum=372
8500 12:15:20.976471 TX Vref=18, minBit 0, minWin=22, winSum=382
8501 12:15:20.979961 TX Vref=20, minBit 0, minWin=23, winSum=393
8502 12:15:20.983816 TX Vref=22, minBit 0, minWin=23, winSum=398
8503 12:15:20.987328 TX Vref=24, minBit 0, minWin=24, winSum=410
8504 12:15:20.993085 TX Vref=26, minBit 0, minWin=24, winSum=417
8505 12:15:20.996492 TX Vref=28, minBit 0, minWin=23, winSum=416
8506 12:15:20.999724 TX Vref=30, minBit 0, minWin=23, winSum=408
8507 12:15:21.003107 TX Vref=32, minBit 0, minWin=23, winSum=397
8508 12:15:21.006710 TX Vref=34, minBit 5, minWin=22, winSum=391
8509 12:15:21.013090 [TxChooseVref] Worse bit 0, Min win 24, Win sum 417, Final Vref 26
8510 12:15:21.013640
8511 12:15:21.016326 Final TX Range 0 Vref 26
8512 12:15:21.016902
8513 12:15:21.017267 ==
8514 12:15:21.019405 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 12:15:21.023108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 12:15:21.023717 ==
8517 12:15:21.024108
8518 12:15:21.024451
8519 12:15:21.025629 TX Vref Scan disable
8520 12:15:21.032533 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8521 12:15:21.033099 == TX Byte 0 ==
8522 12:15:21.036556 u2DelayCellOfst[0]=18 cells (5 PI)
8523 12:15:21.039453 u2DelayCellOfst[1]=14 cells (4 PI)
8524 12:15:21.042707 u2DelayCellOfst[2]=0 cells (0 PI)
8525 12:15:21.045797 u2DelayCellOfst[3]=7 cells (2 PI)
8526 12:15:21.049413 u2DelayCellOfst[4]=11 cells (3 PI)
8527 12:15:21.052592 u2DelayCellOfst[5]=22 cells (6 PI)
8528 12:15:21.056092 u2DelayCellOfst[6]=22 cells (6 PI)
8529 12:15:21.058974 u2DelayCellOfst[7]=7 cells (2 PI)
8530 12:15:21.062486 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8531 12:15:21.065432 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8532 12:15:21.069102 == TX Byte 1 ==
8533 12:15:21.072117 u2DelayCellOfst[8]=0 cells (0 PI)
8534 12:15:21.075145 u2DelayCellOfst[9]=3 cells (1 PI)
8535 12:15:21.079171 u2DelayCellOfst[10]=11 cells (3 PI)
8536 12:15:21.079633 u2DelayCellOfst[11]=3 cells (1 PI)
8537 12:15:21.081835 u2DelayCellOfst[12]=18 cells (5 PI)
8538 12:15:21.085058 u2DelayCellOfst[13]=18 cells (5 PI)
8539 12:15:21.088974 u2DelayCellOfst[14]=18 cells (5 PI)
8540 12:15:21.091948 u2DelayCellOfst[15]=18 cells (5 PI)
8541 12:15:21.098185 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8542 12:15:21.101822 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8543 12:15:21.102284 DramC Write-DBI on
8544 12:15:21.102646 ==
8545 12:15:21.106081 Dram Type= 6, Freq= 0, CH_1, rank 0
8546 12:15:21.112191 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8547 12:15:21.112698 ==
8548 12:15:21.113059
8549 12:15:21.113398
8550 12:15:21.114944 TX Vref Scan disable
8551 12:15:21.115414 == TX Byte 0 ==
8552 12:15:21.121769 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8553 12:15:21.122298 == TX Byte 1 ==
8554 12:15:21.125633 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8555 12:15:21.127962 DramC Write-DBI off
8556 12:15:21.128377
8557 12:15:21.128705 [DATLAT]
8558 12:15:21.131373 Freq=1600, CH1 RK0
8559 12:15:21.131984
8560 12:15:21.132337 DATLAT Default: 0xf
8561 12:15:21.134711 0, 0xFFFF, sum = 0
8562 12:15:21.135244 1, 0xFFFF, sum = 0
8563 12:15:21.138198 2, 0xFFFF, sum = 0
8564 12:15:21.138620 3, 0xFFFF, sum = 0
8565 12:15:21.141562 4, 0xFFFF, sum = 0
8566 12:15:21.142086 5, 0xFFFF, sum = 0
8567 12:15:21.145159 6, 0xFFFF, sum = 0
8568 12:15:21.145688 7, 0xFFFF, sum = 0
8569 12:15:21.147854 8, 0xFFFF, sum = 0
8570 12:15:21.151221 9, 0xFFFF, sum = 0
8571 12:15:21.151775 10, 0xFFFF, sum = 0
8572 12:15:21.155256 11, 0xFFFF, sum = 0
8573 12:15:21.155831 12, 0xFFFF, sum = 0
8574 12:15:21.158140 13, 0xFFFF, sum = 0
8575 12:15:21.158565 14, 0x0, sum = 1
8576 12:15:21.161131 15, 0x0, sum = 2
8577 12:15:21.161555 16, 0x0, sum = 3
8578 12:15:21.164374 17, 0x0, sum = 4
8579 12:15:21.164796 best_step = 15
8580 12:15:21.165122
8581 12:15:21.165428 ==
8582 12:15:21.167910 Dram Type= 6, Freq= 0, CH_1, rank 0
8583 12:15:21.171622 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8584 12:15:21.173953 ==
8585 12:15:21.174370 RX Vref Scan: 1
8586 12:15:21.174696
8587 12:15:21.177901 Set Vref Range= 24 -> 127
8588 12:15:21.178317
8589 12:15:21.180600 RX Vref 24 -> 127, step: 1
8590 12:15:21.181014
8591 12:15:21.181382 RX Delay 11 -> 252, step: 4
8592 12:15:21.181778
8593 12:15:21.184255 Set Vref, RX VrefLevel [Byte0]: 24
8594 12:15:21.187180 [Byte1]: 24
8595 12:15:21.191104
8596 12:15:21.191625 Set Vref, RX VrefLevel [Byte0]: 25
8597 12:15:21.194744 [Byte1]: 25
8598 12:15:21.198632
8599 12:15:21.199158 Set Vref, RX VrefLevel [Byte0]: 26
8600 12:15:21.202078 [Byte1]: 26
8601 12:15:21.206694
8602 12:15:21.207213 Set Vref, RX VrefLevel [Byte0]: 27
8603 12:15:21.209780 [Byte1]: 27
8604 12:15:21.214380
8605 12:15:21.214912 Set Vref, RX VrefLevel [Byte0]: 28
8606 12:15:21.217113 [Byte1]: 28
8607 12:15:21.221712
8608 12:15:21.222126 Set Vref, RX VrefLevel [Byte0]: 29
8609 12:15:21.228134 [Byte1]: 29
8610 12:15:21.228635
8611 12:15:21.231764 Set Vref, RX VrefLevel [Byte0]: 30
8612 12:15:21.234750 [Byte1]: 30
8613 12:15:21.235280
8614 12:15:21.238307 Set Vref, RX VrefLevel [Byte0]: 31
8615 12:15:21.241510 [Byte1]: 31
8616 12:15:21.245062
8617 12:15:21.245585 Set Vref, RX VrefLevel [Byte0]: 32
8618 12:15:21.248145 [Byte1]: 32
8619 12:15:21.252670
8620 12:15:21.253184 Set Vref, RX VrefLevel [Byte0]: 33
8621 12:15:21.255523 [Byte1]: 33
8622 12:15:21.259914
8623 12:15:21.260426 Set Vref, RX VrefLevel [Byte0]: 34
8624 12:15:21.263317 [Byte1]: 34
8625 12:15:21.267483
8626 12:15:21.268042 Set Vref, RX VrefLevel [Byte0]: 35
8627 12:15:21.270461 [Byte1]: 35
8628 12:15:21.275140
8629 12:15:21.275738 Set Vref, RX VrefLevel [Byte0]: 36
8630 12:15:21.279354 [Byte1]: 36
8631 12:15:21.282685
8632 12:15:21.283201 Set Vref, RX VrefLevel [Byte0]: 37
8633 12:15:21.286696 [Byte1]: 37
8634 12:15:21.290592
8635 12:15:21.291117 Set Vref, RX VrefLevel [Byte0]: 38
8636 12:15:21.293866 [Byte1]: 38
8637 12:15:21.298429
8638 12:15:21.298866 Set Vref, RX VrefLevel [Byte0]: 39
8639 12:15:21.300960 [Byte1]: 39
8640 12:15:21.305050
8641 12:15:21.305484 Set Vref, RX VrefLevel [Byte0]: 40
8642 12:15:21.308650 [Byte1]: 40
8643 12:15:21.312687
8644 12:15:21.313099 Set Vref, RX VrefLevel [Byte0]: 41
8645 12:15:21.316700 [Byte1]: 41
8646 12:15:21.320747
8647 12:15:21.321284 Set Vref, RX VrefLevel [Byte0]: 42
8648 12:15:21.327371 [Byte1]: 42
8649 12:15:21.328015
8650 12:15:21.330384 Set Vref, RX VrefLevel [Byte0]: 43
8651 12:15:21.333849 [Byte1]: 43
8652 12:15:21.334347
8653 12:15:21.337946 Set Vref, RX VrefLevel [Byte0]: 44
8654 12:15:21.340969 [Byte1]: 44
8655 12:15:21.341564
8656 12:15:21.344400 Set Vref, RX VrefLevel [Byte0]: 45
8657 12:15:21.347028 [Byte1]: 45
8658 12:15:21.351071
8659 12:15:21.351526 Set Vref, RX VrefLevel [Byte0]: 46
8660 12:15:21.354282 [Byte1]: 46
8661 12:15:21.358808
8662 12:15:21.359366 Set Vref, RX VrefLevel [Byte0]: 47
8663 12:15:21.362112 [Byte1]: 47
8664 12:15:21.365999
8665 12:15:21.366453 Set Vref, RX VrefLevel [Byte0]: 48
8666 12:15:21.369359 [Byte1]: 48
8667 12:15:21.373870
8668 12:15:21.374436 Set Vref, RX VrefLevel [Byte0]: 49
8669 12:15:21.377032 [Byte1]: 49
8670 12:15:21.382509
8671 12:15:21.383088 Set Vref, RX VrefLevel [Byte0]: 50
8672 12:15:21.385380 [Byte1]: 50
8673 12:15:21.389399
8674 12:15:21.389956 Set Vref, RX VrefLevel [Byte0]: 51
8675 12:15:21.392976 [Byte1]: 51
8676 12:15:21.397148
8677 12:15:21.397633 Set Vref, RX VrefLevel [Byte0]: 52
8678 12:15:21.400136 [Byte1]: 52
8679 12:15:21.404272
8680 12:15:21.404857 Set Vref, RX VrefLevel [Byte0]: 53
8681 12:15:21.407591 [Byte1]: 53
8682 12:15:21.411970
8683 12:15:21.412534 Set Vref, RX VrefLevel [Byte0]: 54
8684 12:15:21.415233 [Byte1]: 54
8685 12:15:21.420056
8686 12:15:21.420514 Set Vref, RX VrefLevel [Byte0]: 55
8687 12:15:21.422789 [Byte1]: 55
8688 12:15:21.427845
8689 12:15:21.428412 Set Vref, RX VrefLevel [Byte0]: 56
8690 12:15:21.430255 [Byte1]: 56
8691 12:15:21.434613
8692 12:15:21.435071 Set Vref, RX VrefLevel [Byte0]: 57
8693 12:15:21.438569 [Byte1]: 57
8694 12:15:21.442528
8695 12:15:21.443101 Set Vref, RX VrefLevel [Byte0]: 58
8696 12:15:21.445936 [Byte1]: 58
8697 12:15:21.450976
8698 12:15:21.451509 Set Vref, RX VrefLevel [Byte0]: 59
8699 12:15:21.454201 [Byte1]: 59
8700 12:15:21.458513
8701 12:15:21.459071 Set Vref, RX VrefLevel [Byte0]: 60
8702 12:15:21.461236 [Byte1]: 60
8703 12:15:21.465857
8704 12:15:21.466318 Set Vref, RX VrefLevel [Byte0]: 61
8705 12:15:21.469165 [Byte1]: 61
8706 12:15:21.472930
8707 12:15:21.473389 Set Vref, RX VrefLevel [Byte0]: 62
8708 12:15:21.477100 [Byte1]: 62
8709 12:15:21.480567
8710 12:15:21.481024 Set Vref, RX VrefLevel [Byte0]: 63
8711 12:15:21.483556 [Byte1]: 63
8712 12:15:21.488004
8713 12:15:21.488420 Set Vref, RX VrefLevel [Byte0]: 64
8714 12:15:21.491207 [Byte1]: 64
8715 12:15:21.495731
8716 12:15:21.496142 Set Vref, RX VrefLevel [Byte0]: 65
8717 12:15:21.499785 [Byte1]: 65
8718 12:15:21.503622
8719 12:15:21.504397 Set Vref, RX VrefLevel [Byte0]: 66
8720 12:15:21.506321 [Byte1]: 66
8721 12:15:21.510879
8722 12:15:21.511390 Set Vref, RX VrefLevel [Byte0]: 67
8723 12:15:21.514495 [Byte1]: 67
8724 12:15:21.519087
8725 12:15:21.519743 Set Vref, RX VrefLevel [Byte0]: 68
8726 12:15:21.525115 [Byte1]: 68
8727 12:15:21.525835
8728 12:15:21.528156 Set Vref, RX VrefLevel [Byte0]: 69
8729 12:15:21.531709 [Byte1]: 69
8730 12:15:21.532127
8731 12:15:21.535039 Set Vref, RX VrefLevel [Byte0]: 70
8732 12:15:21.538468 [Byte1]: 70
8733 12:15:21.541379
8734 12:15:21.541894 Set Vref, RX VrefLevel [Byte0]: 71
8735 12:15:21.544953 [Byte1]: 71
8736 12:15:21.549440
8737 12:15:21.549854 Set Vref, RX VrefLevel [Byte0]: 72
8738 12:15:21.552266 [Byte1]: 72
8739 12:15:21.556725
8740 12:15:21.557238 Set Vref, RX VrefLevel [Byte0]: 73
8741 12:15:21.559742 [Byte1]: 73
8742 12:15:21.564871
8743 12:15:21.565285 Set Vref, RX VrefLevel [Byte0]: 74
8744 12:15:21.567436 [Byte1]: 74
8745 12:15:21.571754
8746 12:15:21.572183 Set Vref, RX VrefLevel [Byte0]: 75
8747 12:15:21.576439 [Byte1]: 75
8748 12:15:21.580004
8749 12:15:21.580581 Final RX Vref Byte 0 = 53 to rank0
8750 12:15:21.583059 Final RX Vref Byte 1 = 60 to rank0
8751 12:15:21.585802 Final RX Vref Byte 0 = 53 to rank1
8752 12:15:21.588973 Final RX Vref Byte 1 = 60 to rank1==
8753 12:15:21.592797 Dram Type= 6, Freq= 0, CH_1, rank 0
8754 12:15:21.599807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8755 12:15:21.600330 ==
8756 12:15:21.600665 DQS Delay:
8757 12:15:21.603187 DQS0 = 0, DQS1 = 0
8758 12:15:21.603600 DQM Delay:
8759 12:15:21.603963 DQM0 = 133, DQM1 = 128
8760 12:15:21.606366 DQ Delay:
8761 12:15:21.609070 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8762 12:15:21.612542 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =128
8763 12:15:21.616077 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =120
8764 12:15:21.618921 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8765 12:15:21.619347
8766 12:15:21.619708
8767 12:15:21.620036
8768 12:15:21.622972 [DramC_TX_OE_Calibration] TA2
8769 12:15:21.625889 Original DQ_B0 (3 6) =30, OEN = 27
8770 12:15:21.629150 Original DQ_B1 (3 6) =30, OEN = 27
8771 12:15:21.632132 24, 0x0, End_B0=24 End_B1=24
8772 12:15:21.632585 25, 0x0, End_B0=25 End_B1=25
8773 12:15:21.635413 26, 0x0, End_B0=26 End_B1=26
8774 12:15:21.639018 27, 0x0, End_B0=27 End_B1=27
8775 12:15:21.642832 28, 0x0, End_B0=28 End_B1=28
8776 12:15:21.645202 29, 0x0, End_B0=29 End_B1=29
8777 12:15:21.645624 30, 0x0, End_B0=30 End_B1=30
8778 12:15:21.648601 31, 0x4141, End_B0=30 End_B1=30
8779 12:15:21.652286 Byte0 end_step=30 best_step=27
8780 12:15:21.655574 Byte1 end_step=30 best_step=27
8781 12:15:21.658800 Byte0 TX OE(2T, 0.5T) = (3, 3)
8782 12:15:21.661872 Byte1 TX OE(2T, 0.5T) = (3, 3)
8783 12:15:21.662291
8784 12:15:21.662696
8785 12:15:21.668581 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
8786 12:15:21.671899 CH1 RK0: MR19=303, MR18=1A0F
8787 12:15:21.679223 CH1_RK0: MR19=0x303, MR18=0x1A0F, DQSOSC=396, MR23=63, INC=23, DEC=15
8788 12:15:21.679939
8789 12:15:21.682379 ----->DramcWriteLeveling(PI) begin...
8790 12:15:21.682799 ==
8791 12:15:21.685055 Dram Type= 6, Freq= 0, CH_1, rank 1
8792 12:15:21.688137 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8793 12:15:21.688557 ==
8794 12:15:21.691933 Write leveling (Byte 0): 23 => 23
8795 12:15:21.695799 Write leveling (Byte 1): 29 => 29
8796 12:15:21.698460 DramcWriteLeveling(PI) end<-----
8797 12:15:21.699031
8798 12:15:21.699527 ==
8799 12:15:21.701439 Dram Type= 6, Freq= 0, CH_1, rank 1
8800 12:15:21.704874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8801 12:15:21.708599 ==
8802 12:15:21.709118 [Gating] SW mode calibration
8803 12:15:21.717998 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8804 12:15:21.721590 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8805 12:15:21.724252 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 12:15:21.731771 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 12:15:21.734913 1 4 8 | B1->B0 | 2626 2323 | 1 0 | (1 1) (0 0)
8808 12:15:21.738270 1 4 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
8809 12:15:21.744586 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8810 12:15:21.747394 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8811 12:15:21.751052 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8812 12:15:21.757783 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8813 12:15:21.760854 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8814 12:15:21.764136 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 12:15:21.770407 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8816 12:15:21.774572 1 5 12 | B1->B0 | 2323 3434 | 0 1 | (1 0) (1 0)
8817 12:15:21.777510 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 12:15:21.783610 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8819 12:15:21.787817 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 12:15:21.790146 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 12:15:21.797338 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 12:15:21.801068 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 12:15:21.803819 1 6 8 | B1->B0 | 2d2d 2323 | 1 0 | (0 0) (0 0)
8824 12:15:21.810912 1 6 12 | B1->B0 | 4646 2525 | 0 0 | (0 0) (0 0)
8825 12:15:21.815031 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 12:15:21.817069 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 12:15:21.823607 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8828 12:15:21.826815 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 12:15:21.830312 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 12:15:21.836380 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 12:15:21.839945 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 12:15:21.843571 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8833 12:15:21.849999 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 12:15:21.853792 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 12:15:21.856547 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 12:15:21.862836 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 12:15:21.867199 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 12:15:21.869872 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 12:15:21.876134 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 12:15:21.879770 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 12:15:21.883214 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 12:15:21.889369 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 12:15:21.893070 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 12:15:21.896023 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 12:15:21.902428 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 12:15:21.906290 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 12:15:21.909222 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8848 12:15:21.915597 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8849 12:15:21.918771 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 12:15:21.923229 Total UI for P1: 0, mck2ui 16
8851 12:15:21.925848 best dqsien dly found for B0: ( 1, 9, 10)
8852 12:15:21.930025 Total UI for P1: 0, mck2ui 16
8853 12:15:21.932541 best dqsien dly found for B1: ( 1, 9, 10)
8854 12:15:21.935651 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8855 12:15:21.938540 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8856 12:15:21.938957
8857 12:15:21.943122 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8858 12:15:21.948443 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8859 12:15:21.948961 [Gating] SW calibration Done
8860 12:15:21.949294 ==
8861 12:15:21.952349 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 12:15:21.959466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 12:15:21.960030 ==
8864 12:15:21.960390 RX Vref Scan: 0
8865 12:15:21.960700
8866 12:15:21.961516 RX Vref 0 -> 0, step: 1
8867 12:15:21.961926
8868 12:15:21.966104 RX Delay 0 -> 252, step: 8
8869 12:15:21.968219 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8870 12:15:21.972190 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8871 12:15:21.974884 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8872 12:15:21.981520 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8873 12:15:21.985375 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8874 12:15:21.987803 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8875 12:15:21.991523 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8876 12:15:21.994877 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8877 12:15:22.001823 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8878 12:15:22.004864 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8879 12:15:22.008083 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8880 12:15:22.011719 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8881 12:15:22.014650 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8882 12:15:22.021688 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8883 12:15:22.024709 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8884 12:15:22.028012 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8885 12:15:22.028588 ==
8886 12:15:22.031084 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 12:15:22.034327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 12:15:22.037827 ==
8889 12:15:22.038395 DQS Delay:
8890 12:15:22.038767 DQS0 = 0, DQS1 = 0
8891 12:15:22.040778 DQM Delay:
8892 12:15:22.041285 DQM0 = 137, DQM1 = 130
8893 12:15:22.044793 DQ Delay:
8894 12:15:22.048011 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8895 12:15:22.050976 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8896 12:15:22.053949 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8897 12:15:22.057364 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8898 12:15:22.058007
8899 12:15:22.058389
8900 12:15:22.058727 ==
8901 12:15:22.061197 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 12:15:22.064724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 12:15:22.065189 ==
8904 12:15:22.067232
8905 12:15:22.067827
8906 12:15:22.068204 TX Vref Scan disable
8907 12:15:22.070682 == TX Byte 0 ==
8908 12:15:22.073869 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8909 12:15:22.077223 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8910 12:15:22.080447 == TX Byte 1 ==
8911 12:15:22.083645 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8912 12:15:22.087811 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8913 12:15:22.088228 ==
8914 12:15:22.090803 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 12:15:22.097267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 12:15:22.097817 ==
8917 12:15:22.110731
8918 12:15:22.113753 TX Vref early break, caculate TX vref
8919 12:15:22.117511 TX Vref=16, minBit 0, minWin=22, winSum=376
8920 12:15:22.120874 TX Vref=18, minBit 0, minWin=22, winSum=385
8921 12:15:22.123451 TX Vref=20, minBit 0, minWin=23, winSum=392
8922 12:15:22.127035 TX Vref=22, minBit 5, minWin=23, winSum=402
8923 12:15:22.130404 TX Vref=24, minBit 0, minWin=24, winSum=408
8924 12:15:22.136888 TX Vref=26, minBit 5, minWin=24, winSum=414
8925 12:15:22.140575 TX Vref=28, minBit 0, minWin=24, winSum=413
8926 12:15:22.144161 TX Vref=30, minBit 0, minWin=24, winSum=411
8927 12:15:22.146569 TX Vref=32, minBit 0, minWin=23, winSum=401
8928 12:15:22.149970 TX Vref=34, minBit 0, minWin=21, winSum=394
8929 12:15:22.156479 TX Vref=36, minBit 0, minWin=21, winSum=380
8930 12:15:22.159985 [TxChooseVref] Worse bit 5, Min win 24, Win sum 414, Final Vref 26
8931 12:15:22.160542
8932 12:15:22.163607 Final TX Range 0 Vref 26
8933 12:15:22.164141
8934 12:15:22.164506 ==
8935 12:15:22.167032 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 12:15:22.170592 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 12:15:22.171159 ==
8938 12:15:22.173282
8939 12:15:22.173742
8940 12:15:22.174166 TX Vref Scan disable
8941 12:15:22.179928 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8942 12:15:22.180407 == TX Byte 0 ==
8943 12:15:22.183069 u2DelayCellOfst[0]=18 cells (5 PI)
8944 12:15:22.186854 u2DelayCellOfst[1]=11 cells (3 PI)
8945 12:15:22.189606 u2DelayCellOfst[2]=0 cells (0 PI)
8946 12:15:22.192746 u2DelayCellOfst[3]=7 cells (2 PI)
8947 12:15:22.196456 u2DelayCellOfst[4]=7 cells (2 PI)
8948 12:15:22.199858 u2DelayCellOfst[5]=22 cells (6 PI)
8949 12:15:22.203213 u2DelayCellOfst[6]=18 cells (5 PI)
8950 12:15:22.206330 u2DelayCellOfst[7]=3 cells (1 PI)
8951 12:15:22.209568 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8952 12:15:22.213251 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8953 12:15:22.216256 == TX Byte 1 ==
8954 12:15:22.219169 u2DelayCellOfst[8]=0 cells (0 PI)
8955 12:15:22.223200 u2DelayCellOfst[9]=7 cells (2 PI)
8956 12:15:22.226396 u2DelayCellOfst[10]=14 cells (4 PI)
8957 12:15:22.229181 u2DelayCellOfst[11]=7 cells (2 PI)
8958 12:15:22.232837 u2DelayCellOfst[12]=18 cells (5 PI)
8959 12:15:22.233390 u2DelayCellOfst[13]=18 cells (5 PI)
8960 12:15:22.235897 u2DelayCellOfst[14]=18 cells (5 PI)
8961 12:15:22.239570 u2DelayCellOfst[15]=18 cells (5 PI)
8962 12:15:22.246230 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8963 12:15:22.249074 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8964 12:15:22.252276 DramC Write-DBI on
8965 12:15:22.252739 ==
8966 12:15:22.256082 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 12:15:22.259316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 12:15:22.259933 ==
8969 12:15:22.260311
8970 12:15:22.260653
8971 12:15:22.262323 TX Vref Scan disable
8972 12:15:22.262783 == TX Byte 0 ==
8973 12:15:22.269022 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8974 12:15:22.269588 == TX Byte 1 ==
8975 12:15:22.272609 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8976 12:15:22.275611 DramC Write-DBI off
8977 12:15:22.276114
8978 12:15:22.276485 [DATLAT]
8979 12:15:22.278603 Freq=1600, CH1 RK1
8980 12:15:22.279065
8981 12:15:22.279431 DATLAT Default: 0xf
8982 12:15:22.282543 0, 0xFFFF, sum = 0
8983 12:15:22.283118 1, 0xFFFF, sum = 0
8984 12:15:22.285418 2, 0xFFFF, sum = 0
8985 12:15:22.289187 3, 0xFFFF, sum = 0
8986 12:15:22.289653 4, 0xFFFF, sum = 0
8987 12:15:22.292732 5, 0xFFFF, sum = 0
8988 12:15:22.293203 6, 0xFFFF, sum = 0
8989 12:15:22.295656 7, 0xFFFF, sum = 0
8990 12:15:22.296274 8, 0xFFFF, sum = 0
8991 12:15:22.298844 9, 0xFFFF, sum = 0
8992 12:15:22.299427 10, 0xFFFF, sum = 0
8993 12:15:22.303082 11, 0xFFFF, sum = 0
8994 12:15:22.303656 12, 0xFFFF, sum = 0
8995 12:15:22.304940 13, 0xFFFF, sum = 0
8996 12:15:22.305351 14, 0x0, sum = 1
8997 12:15:22.308482 15, 0x0, sum = 2
8998 12:15:22.308969 16, 0x0, sum = 3
8999 12:15:22.311746 17, 0x0, sum = 4
9000 12:15:22.312328 best_step = 15
9001 12:15:22.312694
9002 12:15:22.313033 ==
9003 12:15:22.315173 Dram Type= 6, Freq= 0, CH_1, rank 1
9004 12:15:22.321974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9005 12:15:22.322544 ==
9006 12:15:22.322918 RX Vref Scan: 0
9007 12:15:22.323265
9008 12:15:22.324581 RX Vref 0 -> 0, step: 1
9009 12:15:22.325044
9010 12:15:22.327909 RX Delay 11 -> 252, step: 4
9011 12:15:22.331659 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9012 12:15:22.335001 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9013 12:15:22.338227 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9014 12:15:22.344739 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9015 12:15:22.348325 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9016 12:15:22.351138 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9017 12:15:22.354869 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9018 12:15:22.357754 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9019 12:15:22.364266 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9020 12:15:22.368571 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9021 12:15:22.371663 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9022 12:15:22.374549 iDelay=203, Bit 11, Center 118 (63 ~ 174) 112
9023 12:15:22.381371 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9024 12:15:22.384362 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9025 12:15:22.387908 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9026 12:15:22.391221 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9027 12:15:22.391826 ==
9028 12:15:22.393939 Dram Type= 6, Freq= 0, CH_1, rank 1
9029 12:15:22.400921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9030 12:15:22.401487 ==
9031 12:15:22.401913 DQS Delay:
9032 12:15:22.404089 DQS0 = 0, DQS1 = 0
9033 12:15:22.404555 DQM Delay:
9034 12:15:22.404926 DQM0 = 133, DQM1 = 126
9035 12:15:22.407228 DQ Delay:
9036 12:15:22.411644 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9037 12:15:22.414457 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9038 12:15:22.417874 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =118
9039 12:15:22.421613 DQ12 =136, DQ13 =134, DQ14 =134, DQ15 =138
9040 12:15:22.422184
9041 12:15:22.422558
9042 12:15:22.422901
9043 12:15:22.424130 [DramC_TX_OE_Calibration] TA2
9044 12:15:22.427360 Original DQ_B0 (3 6) =30, OEN = 27
9045 12:15:22.430836 Original DQ_B1 (3 6) =30, OEN = 27
9046 12:15:22.433450 24, 0x0, End_B0=24 End_B1=24
9047 12:15:22.437195 25, 0x0, End_B0=25 End_B1=25
9048 12:15:22.437670 26, 0x0, End_B0=26 End_B1=26
9049 12:15:22.440229 27, 0x0, End_B0=27 End_B1=27
9050 12:15:22.443782 28, 0x0, End_B0=28 End_B1=28
9051 12:15:22.447156 29, 0x0, End_B0=29 End_B1=29
9052 12:15:22.447627 30, 0x0, End_B0=30 End_B1=30
9053 12:15:22.449888 31, 0x4141, End_B0=30 End_B1=30
9054 12:15:22.453443 Byte0 end_step=30 best_step=27
9055 12:15:22.456597 Byte1 end_step=30 best_step=27
9056 12:15:22.460371 Byte0 TX OE(2T, 0.5T) = (3, 3)
9057 12:15:22.463633 Byte1 TX OE(2T, 0.5T) = (3, 3)
9058 12:15:22.464337
9059 12:15:22.464715
9060 12:15:22.470784 [DQSOSCAuto] RK1, (LSB)MR18= 0xc08, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
9061 12:15:22.473383 CH1 RK1: MR19=303, MR18=C08
9062 12:15:22.479599 CH1_RK1: MR19=0x303, MR18=0xC08, DQSOSC=403, MR23=63, INC=22, DEC=15
9063 12:15:22.483937 [RxdqsGatingPostProcess] freq 1600
9064 12:15:22.486617 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9065 12:15:22.489906 best DQS0 dly(2T, 0.5T) = (1, 1)
9066 12:15:22.493340 best DQS1 dly(2T, 0.5T) = (1, 1)
9067 12:15:22.496130 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9068 12:15:22.500249 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9069 12:15:22.502953 best DQS0 dly(2T, 0.5T) = (1, 1)
9070 12:15:22.506025 best DQS1 dly(2T, 0.5T) = (1, 1)
9071 12:15:22.509537 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9072 12:15:22.513321 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9073 12:15:22.516406 Pre-setting of DQS Precalculation
9074 12:15:22.520014 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9075 12:15:22.529123 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9076 12:15:22.535961 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9077 12:15:22.536725
9078 12:15:22.537113
9079 12:15:22.540248 [Calibration Summary] 3200 Mbps
9080 12:15:22.540780 CH 0, Rank 0
9081 12:15:22.542326 SW Impedance : PASS
9082 12:15:22.542787 DUTY Scan : NO K
9083 12:15:22.545590 ZQ Calibration : PASS
9084 12:15:22.549550 Jitter Meter : NO K
9085 12:15:22.550014 CBT Training : PASS
9086 12:15:22.552223 Write leveling : PASS
9087 12:15:22.555926 RX DQS gating : PASS
9088 12:15:22.556388 RX DQ/DQS(RDDQC) : PASS
9089 12:15:22.558883 TX DQ/DQS : PASS
9090 12:15:22.562493 RX DATLAT : PASS
9091 12:15:22.563049 RX DQ/DQS(Engine): PASS
9092 12:15:22.565345 TX OE : PASS
9093 12:15:22.565766 All Pass.
9094 12:15:22.566097
9095 12:15:22.568709 CH 0, Rank 1
9096 12:15:22.569126 SW Impedance : PASS
9097 12:15:22.572014 DUTY Scan : NO K
9098 12:15:22.575512 ZQ Calibration : PASS
9099 12:15:22.576156 Jitter Meter : NO K
9100 12:15:22.578939 CBT Training : PASS
9101 12:15:22.579357 Write leveling : PASS
9102 12:15:22.582265 RX DQS gating : PASS
9103 12:15:22.585601 RX DQ/DQS(RDDQC) : PASS
9104 12:15:22.586017 TX DQ/DQS : PASS
9105 12:15:22.588587 RX DATLAT : PASS
9106 12:15:22.591877 RX DQ/DQS(Engine): PASS
9107 12:15:22.592295 TX OE : PASS
9108 12:15:22.595566 All Pass.
9109 12:15:22.596026
9110 12:15:22.596359 CH 1, Rank 0
9111 12:15:22.598403 SW Impedance : PASS
9112 12:15:22.598822 DUTY Scan : NO K
9113 12:15:22.602112 ZQ Calibration : PASS
9114 12:15:22.605504 Jitter Meter : NO K
9115 12:15:22.606023 CBT Training : PASS
9116 12:15:22.608179 Write leveling : PASS
9117 12:15:22.611395 RX DQS gating : PASS
9118 12:15:22.611886 RX DQ/DQS(RDDQC) : PASS
9119 12:15:22.615302 TX DQ/DQS : PASS
9120 12:15:22.618676 RX DATLAT : PASS
9121 12:15:22.619192 RX DQ/DQS(Engine): PASS
9122 12:15:22.622326 TX OE : PASS
9123 12:15:22.622889 All Pass.
9124 12:15:22.623257
9125 12:15:22.625264 CH 1, Rank 1
9126 12:15:22.625728 SW Impedance : PASS
9127 12:15:22.628843 DUTY Scan : NO K
9128 12:15:22.631868 ZQ Calibration : PASS
9129 12:15:22.632383 Jitter Meter : NO K
9130 12:15:22.635010 CBT Training : PASS
9131 12:15:22.638267 Write leveling : PASS
9132 12:15:22.638729 RX DQS gating : PASS
9133 12:15:22.641526 RX DQ/DQS(RDDQC) : PASS
9134 12:15:22.645339 TX DQ/DQS : PASS
9135 12:15:22.645907 RX DATLAT : PASS
9136 12:15:22.648499 RX DQ/DQS(Engine): PASS
9137 12:15:22.649049 TX OE : PASS
9138 12:15:22.652162 All Pass.
9139 12:15:22.652629
9140 12:15:22.653018 DramC Write-DBI on
9141 12:15:22.654584 PER_BANK_REFRESH: Hybrid Mode
9142 12:15:22.658059 TX_TRACKING: ON
9143 12:15:22.664499 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9144 12:15:22.674605 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9145 12:15:22.680845 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9146 12:15:22.684389 [FAST_K] Save calibration result to emmc
9147 12:15:22.687377 sync common calibartion params.
9148 12:15:22.690683 sync cbt_mode0:1, 1:1
9149 12:15:22.691401 dram_init: ddr_geometry: 2
9150 12:15:22.694584 dram_init: ddr_geometry: 2
9151 12:15:22.697479 dram_init: ddr_geometry: 2
9152 12:15:22.698063 0:dram_rank_size:100000000
9153 12:15:22.701113 1:dram_rank_size:100000000
9154 12:15:22.707564 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9155 12:15:22.711099 DFS_SHUFFLE_HW_MODE: ON
9156 12:15:22.713764 dramc_set_vcore_voltage set vcore to 725000
9157 12:15:22.714330 Read voltage for 1600, 0
9158 12:15:22.716953 Vio18 = 0
9159 12:15:22.717411 Vcore = 725000
9160 12:15:22.717778 Vdram = 0
9161 12:15:22.720744 Vddq = 0
9162 12:15:22.721264 Vmddr = 0
9163 12:15:22.723996 switch to 3200 Mbps bootup
9164 12:15:22.724561 [DramcRunTimeConfig]
9165 12:15:22.724946 PHYPLL
9166 12:15:22.727109 DPM_CONTROL_AFTERK: ON
9167 12:15:22.730821 PER_BANK_REFRESH: ON
9168 12:15:22.731385 REFRESH_OVERHEAD_REDUCTION: ON
9169 12:15:22.733897 CMD_PICG_NEW_MODE: OFF
9170 12:15:22.737653 XRTWTW_NEW_MODE: ON
9171 12:15:22.738227 XRTRTR_NEW_MODE: ON
9172 12:15:22.740514 TX_TRACKING: ON
9173 12:15:22.740977 RDSEL_TRACKING: OFF
9174 12:15:22.743442 DQS Precalculation for DVFS: ON
9175 12:15:22.743994 RX_TRACKING: OFF
9176 12:15:22.747236 HW_GATING DBG: ON
9177 12:15:22.750141 ZQCS_ENABLE_LP4: ON
9178 12:15:22.750604 RX_PICG_NEW_MODE: ON
9179 12:15:22.753967 TX_PICG_NEW_MODE: ON
9180 12:15:22.754535 ENABLE_RX_DCM_DPHY: ON
9181 12:15:22.757475 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9182 12:15:22.760043 DUMMY_READ_FOR_TRACKING: OFF
9183 12:15:22.763752 !!! SPM_CONTROL_AFTERK: OFF
9184 12:15:22.767304 !!! SPM could not control APHY
9185 12:15:22.767813 IMPEDANCE_TRACKING: ON
9186 12:15:22.769961 TEMP_SENSOR: ON
9187 12:15:22.770421 HW_SAVE_FOR_SR: OFF
9188 12:15:22.773434 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9189 12:15:22.777083 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9190 12:15:22.780040 Read ODT Tracking: ON
9191 12:15:22.783563 Refresh Rate DeBounce: ON
9192 12:15:22.784196 DFS_NO_QUEUE_FLUSH: ON
9193 12:15:22.786668 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9194 12:15:22.789919 ENABLE_DFS_RUNTIME_MRW: OFF
9195 12:15:22.792999 DDR_RESERVE_NEW_MODE: ON
9196 12:15:22.793463 MR_CBT_SWITCH_FREQ: ON
9197 12:15:22.796248 =========================
9198 12:15:22.815436 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9199 12:15:22.818511 dram_init: ddr_geometry: 2
9200 12:15:22.836796 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9201 12:15:22.840257 dram_init: dram init end (result: 0)
9202 12:15:22.846676 DRAM-K: Full calibration passed in 24646 msecs
9203 12:15:22.849881 MRC: failed to locate region type 0.
9204 12:15:22.850378 DRAM rank0 size:0x100000000,
9205 12:15:22.853095 DRAM rank1 size=0x100000000
9206 12:15:22.862786 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9207 12:15:22.870478 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9208 12:15:22.876619 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9209 12:15:22.886466 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9210 12:15:22.887037 DRAM rank0 size:0x100000000,
9211 12:15:22.889371 DRAM rank1 size=0x100000000
9212 12:15:22.889938 CBMEM:
9213 12:15:22.892575 IMD: root @ 0xfffff000 254 entries.
9214 12:15:22.896300 IMD: root @ 0xffffec00 62 entries.
9215 12:15:22.899155 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9216 12:15:22.906145 WARNING: RO_VPD is uninitialized or empty.
9217 12:15:22.909205 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9218 12:15:22.917352 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9219 12:15:22.929911 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9220 12:15:22.941109 BS: romstage times (exec / console): total (unknown) / 24134 ms
9221 12:15:22.941674
9222 12:15:22.942042
9223 12:15:22.950843 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9224 12:15:22.954065 ARM64: Exception handlers installed.
9225 12:15:22.957409 ARM64: Testing exception
9226 12:15:22.960892 ARM64: Done test exception
9227 12:15:22.961361 Enumerating buses...
9228 12:15:22.964050 Show all devs... Before device enumeration.
9229 12:15:22.967958 Root Device: enabled 1
9230 12:15:22.970834 CPU_CLUSTER: 0: enabled 1
9231 12:15:22.971547 CPU: 00: enabled 1
9232 12:15:22.973983 Compare with tree...
9233 12:15:22.974551 Root Device: enabled 1
9234 12:15:22.976859 CPU_CLUSTER: 0: enabled 1
9235 12:15:22.981641 CPU: 00: enabled 1
9236 12:15:22.982213 Root Device scanning...
9237 12:15:22.983524 scan_static_bus for Root Device
9238 12:15:22.987618 CPU_CLUSTER: 0 enabled
9239 12:15:22.990043 scan_static_bus for Root Device done
9240 12:15:22.993604 scan_bus: bus Root Device finished in 8 msecs
9241 12:15:22.994347 done
9242 12:15:23.000623 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9243 12:15:23.004162 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9244 12:15:23.009719 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9245 12:15:23.016733 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9246 12:15:23.017258 Allocating resources...
9247 12:15:23.020665 Reading resources...
9248 12:15:23.022989 Root Device read_resources bus 0 link: 0
9249 12:15:23.026296 DRAM rank0 size:0x100000000,
9250 12:15:23.026857 DRAM rank1 size=0x100000000
9251 12:15:23.033236 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9252 12:15:23.033765 CPU: 00 missing read_resources
9253 12:15:23.039706 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9254 12:15:23.043433 Root Device read_resources bus 0 link: 0 done
9255 12:15:23.046449 Done reading resources.
9256 12:15:23.049677 Show resources in subtree (Root Device)...After reading.
9257 12:15:23.052985 Root Device child on link 0 CPU_CLUSTER: 0
9258 12:15:23.056069 CPU_CLUSTER: 0 child on link 0 CPU: 00
9259 12:15:23.065757 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9260 12:15:23.066310 CPU: 00
9261 12:15:23.073258 Root Device assign_resources, bus 0 link: 0
9262 12:15:23.075665 CPU_CLUSTER: 0 missing set_resources
9263 12:15:23.078769 Root Device assign_resources, bus 0 link: 0 done
9264 12:15:23.082275 Done setting resources.
9265 12:15:23.086116 Show resources in subtree (Root Device)...After assigning values.
9266 12:15:23.088966 Root Device child on link 0 CPU_CLUSTER: 0
9267 12:15:23.095746 CPU_CLUSTER: 0 child on link 0 CPU: 00
9268 12:15:23.101903 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9269 12:15:23.105456 CPU: 00
9270 12:15:23.105972 Done allocating resources.
9271 12:15:23.112107 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9272 12:15:23.112624 Enabling resources...
9273 12:15:23.115367 done.
9274 12:15:23.118967 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9275 12:15:23.121924 Initializing devices...
9276 12:15:23.122444 Root Device init
9277 12:15:23.124981 init hardware done!
9278 12:15:23.125401 0x00000018: ctrlr->caps
9279 12:15:23.128839 52.000 MHz: ctrlr->f_max
9280 12:15:23.131639 0.400 MHz: ctrlr->f_min
9281 12:15:23.135337 0x40ff8080: ctrlr->voltages
9282 12:15:23.135909 sclk: 390625
9283 12:15:23.136256 Bus Width = 1
9284 12:15:23.138486 sclk: 390625
9285 12:15:23.139004 Bus Width = 1
9286 12:15:23.141717 Early init status = 3
9287 12:15:23.144840 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9288 12:15:23.148937 in-header: 03 fc 00 00 01 00 00 00
9289 12:15:23.152321 in-data: 00
9290 12:15:23.155141 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9291 12:15:23.161200 in-header: 03 fd 00 00 00 00 00 00
9292 12:15:23.163632 in-data:
9293 12:15:23.166718 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9294 12:15:23.170584 in-header: 03 fc 00 00 01 00 00 00
9295 12:15:23.174119 in-data: 00
9296 12:15:23.177473 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9297 12:15:23.182917 in-header: 03 fd 00 00 00 00 00 00
9298 12:15:23.186551 in-data:
9299 12:15:23.189997 [SSUSB] Setting up USB HOST controller...
9300 12:15:23.193612 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9301 12:15:23.196296 [SSUSB] phy power-on done.
9302 12:15:23.199556 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9303 12:15:23.206402 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9304 12:15:23.209404 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9305 12:15:23.216737 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9306 12:15:23.223100 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9307 12:15:23.228973 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9308 12:15:23.235807 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9309 12:15:23.242970 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9310 12:15:23.246063 SPM: binary array size = 0x9dc
9311 12:15:23.249029 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9312 12:15:23.255829 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9313 12:15:23.262020 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9314 12:15:23.268922 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9315 12:15:23.271915 configure_display: Starting display init
9316 12:15:23.306165 anx7625_power_on_init: Init interface.
9317 12:15:23.309936 anx7625_disable_pd_protocol: Disabled PD feature.
9318 12:15:23.316196 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9319 12:15:23.340511 anx7625_start_dp_work: Secure OCM version=00
9320 12:15:23.344164 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9321 12:15:23.358873 sp_tx_get_edid_block: EDID Block = 1
9322 12:15:23.461974 Extracted contents:
9323 12:15:23.464766 header: 00 ff ff ff ff ff ff 00
9324 12:15:23.468470 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9325 12:15:23.471542 version: 01 04
9326 12:15:23.474748 basic params: 95 1f 11 78 0a
9327 12:15:23.477781 chroma info: 76 90 94 55 54 90 27 21 50 54
9328 12:15:23.481563 established: 00 00 00
9329 12:15:23.488007 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9330 12:15:23.494554 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9331 12:15:23.497501 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9332 12:15:23.504148 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9333 12:15:23.510552 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9334 12:15:23.514415 extensions: 00
9335 12:15:23.514977 checksum: fb
9336 12:15:23.515347
9337 12:15:23.520941 Manufacturer: IVO Model 57d Serial Number 0
9338 12:15:23.521510 Made week 0 of 2020
9339 12:15:23.524370 EDID version: 1.4
9340 12:15:23.524830 Digital display
9341 12:15:23.527030 6 bits per primary color channel
9342 12:15:23.527502 DisplayPort interface
9343 12:15:23.530398 Maximum image size: 31 cm x 17 cm
9344 12:15:23.533570 Gamma: 220%
9345 12:15:23.534030 Check DPMS levels
9346 12:15:23.540754 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9347 12:15:23.544517 First detailed timing is preferred timing
9348 12:15:23.545269 Established timings supported:
9349 12:15:23.546828 Standard timings supported:
9350 12:15:23.550431 Detailed timings
9351 12:15:23.553659 Hex of detail: 383680a07038204018303c0035ae10000019
9352 12:15:23.560299 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9353 12:15:23.563824 0780 0798 07c8 0820 hborder 0
9354 12:15:23.566749 0438 043b 0447 0458 vborder 0
9355 12:15:23.570529 -hsync -vsync
9356 12:15:23.571133 Did detailed timing
9357 12:15:23.577478 Hex of detail: 000000000000000000000000000000000000
9358 12:15:23.580263 Manufacturer-specified data, tag 0
9359 12:15:23.584425 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9360 12:15:23.586973 ASCII string: InfoVision
9361 12:15:23.590332 Hex of detail: 000000fe00523134304e574635205248200a
9362 12:15:23.593029 ASCII string: R140NWF5 RH
9363 12:15:23.593493 Checksum
9364 12:15:23.596494 Checksum: 0xfb (valid)
9365 12:15:23.599630 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9366 12:15:23.603075 DSI data_rate: 832800000 bps
9367 12:15:23.609613 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9368 12:15:23.613252 anx7625_parse_edid: pixelclock(138800).
9369 12:15:23.616383 hactive(1920), hsync(48), hfp(24), hbp(88)
9370 12:15:23.619658 vactive(1080), vsync(12), vfp(3), vbp(17)
9371 12:15:23.622690 anx7625_dsi_config: config dsi.
9372 12:15:23.628958 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9373 12:15:23.643288 anx7625_dsi_config: success to config DSI
9374 12:15:23.646801 anx7625_dp_start: MIPI phy setup OK.
9375 12:15:23.649894 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9376 12:15:23.653770 mtk_ddp_mode_set invalid vrefresh 60
9377 12:15:23.657317 main_disp_path_setup
9378 12:15:23.658025 ovl_layer_smi_id_en
9379 12:15:23.660133 ovl_layer_smi_id_en
9380 12:15:23.660550 ccorr_config
9381 12:15:23.660877 aal_config
9382 12:15:23.663117 gamma_config
9383 12:15:23.663529 postmask_config
9384 12:15:23.666677 dither_config
9385 12:15:23.670073 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9386 12:15:23.676216 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9387 12:15:23.679647 Root Device init finished in 553 msecs
9388 12:15:23.683348 CPU_CLUSTER: 0 init
9389 12:15:23.689787 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9390 12:15:23.696689 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9391 12:15:23.697111 APU_MBOX 0x190000b0 = 0x10001
9392 12:15:23.699642 APU_MBOX 0x190001b0 = 0x10001
9393 12:15:23.702941 APU_MBOX 0x190005b0 = 0x10001
9394 12:15:23.706584 APU_MBOX 0x190006b0 = 0x10001
9395 12:15:23.712604 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9396 12:15:23.722488 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9397 12:15:23.735124 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9398 12:15:23.741331 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9399 12:15:23.752939 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9400 12:15:23.762261 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9401 12:15:23.765739 CPU_CLUSTER: 0 init finished in 81 msecs
9402 12:15:23.769014 Devices initialized
9403 12:15:23.772583 Show all devs... After init.
9404 12:15:23.773118 Root Device: enabled 1
9405 12:15:23.776504 CPU_CLUSTER: 0: enabled 1
9406 12:15:23.778743 CPU: 00: enabled 1
9407 12:15:23.782190 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9408 12:15:23.785940 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9409 12:15:23.788704 ELOG: NV offset 0x57f000 size 0x1000
9410 12:15:23.795445 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9411 12:15:23.801627 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9412 12:15:23.805807 ELOG: Event(17) added with size 13 at 2024-01-31 12:15:23 UTC
9413 12:15:23.808980 out: cmd=0x121: 03 db 21 01 00 00 00 00
9414 12:15:23.813021 in-header: 03 aa 00 00 2c 00 00 00
9415 12:15:23.825836 in-data: b5 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9416 12:15:23.832320 ELOG: Event(A1) added with size 10 at 2024-01-31 12:15:23 UTC
9417 12:15:23.839082 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9418 12:15:23.845743 ELOG: Event(A0) added with size 9 at 2024-01-31 12:15:23 UTC
9419 12:15:23.848947 elog_add_boot_reason: Logged dev mode boot
9420 12:15:23.852481 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9421 12:15:23.856423 Finalize devices...
9422 12:15:23.856885 Devices finalized
9423 12:15:23.862961 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9424 12:15:23.865761 Writing coreboot table at 0xffe64000
9425 12:15:23.868738 0. 000000000010a000-0000000000113fff: RAMSTAGE
9426 12:15:23.872377 1. 0000000040000000-00000000400fffff: RAM
9427 12:15:23.878869 2. 0000000040100000-000000004032afff: RAMSTAGE
9428 12:15:23.882261 3. 000000004032b000-00000000545fffff: RAM
9429 12:15:23.885556 4. 0000000054600000-000000005465ffff: BL31
9430 12:15:23.888638 5. 0000000054660000-00000000ffe63fff: RAM
9431 12:15:23.895860 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9432 12:15:23.899029 7. 0000000100000000-000000023fffffff: RAM
9433 12:15:23.901849 Passing 5 GPIOs to payload:
9434 12:15:23.904872 NAME | PORT | POLARITY | VALUE
9435 12:15:23.908409 EC in RW | 0x000000aa | low | undefined
9436 12:15:23.915471 EC interrupt | 0x00000005 | low | undefined
9437 12:15:23.918514 TPM interrupt | 0x000000ab | high | undefined
9438 12:15:23.925168 SD card detect | 0x00000011 | high | undefined
9439 12:15:23.928143 speaker enable | 0x00000093 | high | undefined
9440 12:15:23.931776 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9441 12:15:23.934781 in-header: 03 f9 00 00 02 00 00 00
9442 12:15:23.938322 in-data: 02 00
9443 12:15:23.938889 ADC[4]: Raw value=901552 ID=7
9444 12:15:23.941488 ADC[3]: Raw value=214021 ID=1
9445 12:15:23.944607 RAM Code: 0x71
9446 12:15:23.945072 ADC[6]: Raw value=75406 ID=0
9447 12:15:23.948230 ADC[5]: Raw value=212912 ID=1
9448 12:15:23.951249 SKU Code: 0x1
9449 12:15:23.954578 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3c95
9450 12:15:23.957927 coreboot table: 964 bytes.
9451 12:15:23.961821 IMD ROOT 0. 0xfffff000 0x00001000
9452 12:15:23.964524 IMD SMALL 1. 0xffffe000 0x00001000
9453 12:15:23.968236 RO MCACHE 2. 0xffffc000 0x00001104
9454 12:15:23.971174 CONSOLE 3. 0xfff7c000 0x00080000
9455 12:15:23.974514 FMAP 4. 0xfff7b000 0x00000452
9456 12:15:23.978158 TIME STAMP 5. 0xfff7a000 0x00000910
9457 12:15:23.981551 VBOOT WORK 6. 0xfff66000 0x00014000
9458 12:15:23.985109 RAMOOPS 7. 0xffe66000 0x00100000
9459 12:15:23.987619 COREBOOT 8. 0xffe64000 0x00002000
9460 12:15:23.991036 IMD small region:
9461 12:15:23.994812 IMD ROOT 0. 0xffffec00 0x00000400
9462 12:15:23.997881 VPD 1. 0xffffeb80 0x0000006c
9463 12:15:24.001265 MMC STATUS 2. 0xffffeb60 0x00000004
9464 12:15:24.004548 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9465 12:15:24.008276 Probing TPM: done!
9466 12:15:24.011835 Connected to device vid:did:rid of 1ae0:0028:00
9467 12:15:24.021334 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9468 12:15:24.024631 Initialized TPM device CR50 revision 0
9469 12:15:24.027930 Checking cr50 for pending updates
9470 12:15:24.031913 Reading cr50 TPM mode
9471 12:15:24.041219 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9472 12:15:24.047405 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9473 12:15:24.087740 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9474 12:15:24.090999 Checking segment from ROM address 0x40100000
9475 12:15:24.094811 Checking segment from ROM address 0x4010001c
9476 12:15:24.101276 Loading segment from ROM address 0x40100000
9477 12:15:24.101845 code (compression=0)
9478 12:15:24.111153 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9479 12:15:24.117342 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9480 12:15:24.117910 it's not compressed!
9481 12:15:24.123824 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9482 12:15:24.130542 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9483 12:15:24.147912 Loading segment from ROM address 0x4010001c
9484 12:15:24.148467 Entry Point 0x80000000
9485 12:15:24.151476 Loaded segments
9486 12:15:24.154614 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9487 12:15:24.160997 Jumping to boot code at 0x80000000(0xffe64000)
9488 12:15:24.167407 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9489 12:15:24.174574 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9490 12:15:24.182613 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9491 12:15:24.185338 Checking segment from ROM address 0x40100000
9492 12:15:24.189224 Checking segment from ROM address 0x4010001c
9493 12:15:24.195343 Loading segment from ROM address 0x40100000
9494 12:15:24.195854 code (compression=1)
9495 12:15:24.202419 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9496 12:15:24.211928 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9497 12:15:24.212394 using LZMA
9498 12:15:24.220312 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9499 12:15:24.227335 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9500 12:15:24.230928 Loading segment from ROM address 0x4010001c
9501 12:15:24.231494 Entry Point 0x54601000
9502 12:15:24.234017 Loaded segments
9503 12:15:24.237326 NOTICE: MT8192 bl31_setup
9504 12:15:24.244742 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9505 12:15:24.247958 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9506 12:15:24.250921 WARNING: region 0:
9507 12:15:24.254930 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9508 12:15:24.255498 WARNING: region 1:
9509 12:15:24.260965 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9510 12:15:24.264195 WARNING: region 2:
9511 12:15:24.267242 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9512 12:15:24.270918 WARNING: region 3:
9513 12:15:24.273878 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9514 12:15:24.277441 WARNING: region 4:
9515 12:15:24.283832 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9516 12:15:24.284380 WARNING: region 5:
9517 12:15:24.287520 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9518 12:15:24.290625 WARNING: region 6:
9519 12:15:24.295656 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9520 12:15:24.297694 WARNING: region 7:
9521 12:15:24.300198 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9522 12:15:24.307081 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9523 12:15:24.310427 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9524 12:15:24.313270 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9525 12:15:24.320727 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9526 12:15:24.323016 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9527 12:15:24.330088 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9528 12:15:24.333138 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9529 12:15:24.336380 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9530 12:15:24.343451 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9531 12:15:24.346512 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9532 12:15:24.352770 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9533 12:15:24.356338 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9534 12:15:24.359628 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9535 12:15:24.366779 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9536 12:15:24.369480 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9537 12:15:24.373109 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9538 12:15:24.379207 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9539 12:15:24.382580 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9540 12:15:24.389394 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9541 12:15:24.392487 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9542 12:15:24.396184 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9543 12:15:24.402979 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9544 12:15:24.406019 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9545 12:15:24.409148 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9546 12:15:24.415908 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9547 12:15:24.419101 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9548 12:15:24.426156 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9549 12:15:24.429485 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9550 12:15:24.435933 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9551 12:15:24.439190 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9552 12:15:24.442972 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9553 12:15:24.449601 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9554 12:15:24.452354 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9555 12:15:24.456365 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9556 12:15:24.458829 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9557 12:15:24.465619 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9558 12:15:24.469099 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9559 12:15:24.472197 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9560 12:15:24.475883 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9561 12:15:24.482909 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9562 12:15:24.485591 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9563 12:15:24.488788 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9564 12:15:24.492211 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9565 12:15:24.498947 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9566 12:15:24.502357 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9567 12:15:24.505646 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9568 12:15:24.512308 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9569 12:15:24.516066 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9570 12:15:24.519494 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9571 12:15:24.526248 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9572 12:15:24.528983 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9573 12:15:24.535867 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9574 12:15:24.539843 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9575 12:15:24.542538 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9576 12:15:24.549072 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9577 12:15:24.553068 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9578 12:15:24.558818 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9579 12:15:24.562241 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9580 12:15:24.569088 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9581 12:15:24.572901 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9582 12:15:24.579113 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9583 12:15:24.582760 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9584 12:15:24.585770 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9585 12:15:24.591951 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9586 12:15:24.595348 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9587 12:15:24.601884 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9588 12:15:24.605320 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9589 12:15:24.611826 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9590 12:15:24.615464 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9591 12:15:24.618724 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9592 12:15:24.625070 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9593 12:15:24.628271 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9594 12:15:24.634843 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9595 12:15:24.638471 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9596 12:15:24.645559 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9597 12:15:24.648294 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9598 12:15:24.655135 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9599 12:15:24.658478 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9600 12:15:24.665147 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9601 12:15:24.668269 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9602 12:15:24.672446 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9603 12:15:24.678146 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9604 12:15:24.681225 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9605 12:15:24.688463 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9606 12:15:24.691335 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9607 12:15:24.697780 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9608 12:15:24.700621 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9609 12:15:24.703876 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9610 12:15:24.710604 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9611 12:15:24.713970 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9612 12:15:24.720552 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9613 12:15:24.723937 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9614 12:15:24.730696 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9615 12:15:24.734135 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9616 12:15:24.740281 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9617 12:15:24.743767 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9618 12:15:24.747154 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9619 12:15:24.753603 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9620 12:15:24.757063 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9621 12:15:24.760589 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9622 12:15:24.763875 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9623 12:15:24.770369 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9624 12:15:24.774096 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9625 12:15:24.780474 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9626 12:15:24.784031 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9627 12:15:24.787106 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9628 12:15:24.794055 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9629 12:15:24.797539 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9630 12:15:24.804165 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9631 12:15:24.807485 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9632 12:15:24.811354 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9633 12:15:24.817214 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9634 12:15:24.820626 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9635 12:15:24.826939 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9636 12:15:24.830133 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9637 12:15:24.833919 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9638 12:15:24.837094 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9639 12:15:24.844245 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9640 12:15:24.847529 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9641 12:15:24.850105 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9642 12:15:24.856831 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9643 12:15:24.860256 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9644 12:15:24.863694 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9645 12:15:24.866532 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9646 12:15:24.874706 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9647 12:15:24.877146 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9648 12:15:24.883537 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9649 12:15:24.886886 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9650 12:15:24.893135 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9651 12:15:24.896924 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9652 12:15:24.899512 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9653 12:15:24.906653 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9654 12:15:24.909976 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9655 12:15:24.913574 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9656 12:15:24.920126 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9657 12:15:24.923402 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9658 12:15:24.929514 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9659 12:15:24.932836 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9660 12:15:24.936461 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9661 12:15:24.943095 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9662 12:15:24.946666 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9663 12:15:24.952589 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9664 12:15:24.955984 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9665 12:15:24.959573 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9666 12:15:24.966002 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9667 12:15:24.969311 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9668 12:15:24.976071 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9669 12:15:24.979470 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9670 12:15:24.982711 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9671 12:15:24.988930 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9672 12:15:24.993049 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9673 12:15:24.999203 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9674 12:15:25.002474 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9675 12:15:25.005915 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9676 12:15:25.012583 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9677 12:15:25.015936 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9678 12:15:25.022530 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9679 12:15:25.025704 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9680 12:15:25.029531 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9681 12:15:25.035918 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9682 12:15:25.038679 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9683 12:15:25.045461 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9684 12:15:25.049100 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9685 12:15:25.052162 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9686 12:15:25.058787 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9687 12:15:25.062126 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9688 12:15:25.068217 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9689 12:15:25.071535 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9690 12:15:25.075355 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9691 12:15:25.081344 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9692 12:15:25.084924 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9693 12:15:25.091768 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9694 12:15:25.094919 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9695 12:15:25.098646 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9696 12:15:25.105049 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9697 12:15:25.108439 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9698 12:15:25.115129 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9699 12:15:25.118108 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9700 12:15:25.121342 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9701 12:15:25.127939 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9702 12:15:25.131625 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9703 12:15:25.138514 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9704 12:15:25.141641 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9705 12:15:25.144474 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9706 12:15:25.151374 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9707 12:15:25.154423 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9708 12:15:25.157922 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9709 12:15:25.164621 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9710 12:15:25.167949 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9711 12:15:25.174059 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9712 12:15:25.177259 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9713 12:15:25.184032 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9714 12:15:25.187030 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9715 12:15:25.190470 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9716 12:15:25.197051 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9717 12:15:25.200031 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9718 12:15:25.206636 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9719 12:15:25.210458 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9720 12:15:25.216886 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9721 12:15:25.220245 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9722 12:15:25.223336 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9723 12:15:25.230327 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9724 12:15:25.233165 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9725 12:15:25.240249 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9726 12:15:25.243392 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9727 12:15:25.249446 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9728 12:15:25.252756 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9729 12:15:25.259273 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9730 12:15:25.262735 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9731 12:15:25.266683 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9732 12:15:25.272457 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9733 12:15:25.275844 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9734 12:15:25.282788 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9735 12:15:25.286421 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9736 12:15:25.292171 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9737 12:15:25.295853 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9738 12:15:25.298726 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9739 12:15:25.305286 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9740 12:15:25.308436 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9741 12:15:25.315366 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9742 12:15:25.318659 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9743 12:15:25.325145 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9744 12:15:25.328785 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9745 12:15:25.332003 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9746 12:15:25.339006 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9747 12:15:25.341552 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9748 12:15:25.348019 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9749 12:15:25.351728 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9750 12:15:25.358242 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9751 12:15:25.361501 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9752 12:15:25.365324 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9753 12:15:25.368074 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9754 12:15:25.371928 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9755 12:15:25.378458 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9756 12:15:25.381687 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9757 12:15:25.384718 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9758 12:15:25.391460 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9759 12:15:25.394373 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9760 12:15:25.401304 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9761 12:15:25.404615 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9762 12:15:25.409474 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9763 12:15:25.414763 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9764 12:15:25.417401 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9765 12:15:25.421269 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9766 12:15:25.427266 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9767 12:15:25.430802 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9768 12:15:25.437175 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9769 12:15:25.440645 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9770 12:15:25.443916 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9771 12:15:25.451180 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9772 12:15:25.453843 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9773 12:15:25.457107 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9774 12:15:25.464490 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9775 12:15:25.467304 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9776 12:15:25.473809 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9777 12:15:25.477563 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9778 12:15:25.480419 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9779 12:15:25.486598 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9780 12:15:25.489848 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9781 12:15:25.493118 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9782 12:15:25.500283 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9783 12:15:25.503466 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9784 12:15:25.510437 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9785 12:15:25.513804 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9786 12:15:25.516515 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9787 12:15:25.523419 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9788 12:15:25.527202 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9789 12:15:25.529989 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9790 12:15:25.537114 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9791 12:15:25.539575 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9792 12:15:25.543119 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9793 12:15:25.547206 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9794 12:15:25.553271 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9795 12:15:25.556143 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9796 12:15:25.560101 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9797 12:15:25.563403 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9798 12:15:25.569468 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9799 12:15:25.573273 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9800 12:15:25.576153 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9801 12:15:25.579785 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9802 12:15:25.586344 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9803 12:15:25.589683 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9804 12:15:25.593360 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9805 12:15:25.599551 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9806 12:15:25.603654 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9807 12:15:25.608864 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9808 12:15:25.612613 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9809 12:15:25.619627 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9810 12:15:25.622597 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9811 12:15:25.625711 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9812 12:15:25.632144 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9813 12:15:25.635935 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9814 12:15:25.642540 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9815 12:15:25.645893 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9816 12:15:25.648915 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9817 12:15:25.655537 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9818 12:15:25.659008 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9819 12:15:25.665787 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9820 12:15:25.668262 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9821 12:15:25.675309 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9822 12:15:25.679118 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9823 12:15:25.682145 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9824 12:15:25.688530 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9825 12:15:25.692257 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9826 12:15:25.698820 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9827 12:15:25.701850 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9828 12:15:25.704567 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9829 12:15:25.712024 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9830 12:15:25.715764 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9831 12:15:25.721718 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9832 12:15:25.725151 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9833 12:15:25.731299 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9834 12:15:25.734636 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9835 12:15:25.738477 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9836 12:15:25.745794 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9837 12:15:25.747895 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9838 12:15:25.754282 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9839 12:15:25.757510 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9840 12:15:25.761062 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9841 12:15:25.767876 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9842 12:15:25.770772 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9843 12:15:25.777475 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9844 12:15:25.780906 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9845 12:15:25.784134 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9846 12:15:25.790865 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9847 12:15:25.794251 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9848 12:15:25.800627 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9849 12:15:25.804307 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9850 12:15:25.810854 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9851 12:15:25.814349 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9852 12:15:25.817029 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9853 12:15:25.824391 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9854 12:15:25.826938 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9855 12:15:25.834003 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9856 12:15:25.837423 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9857 12:15:25.843584 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9858 12:15:25.846914 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9859 12:15:25.849853 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9860 12:15:25.857277 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9861 12:15:25.860371 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9862 12:15:25.867350 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9863 12:15:25.869822 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9864 12:15:25.873232 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9865 12:15:25.879929 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9866 12:15:25.883741 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9867 12:15:25.889866 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9868 12:15:25.893192 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9869 12:15:25.896847 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9870 12:15:25.903219 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9871 12:15:25.906774 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9872 12:15:25.912912 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9873 12:15:25.916556 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9874 12:15:25.922854 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9875 12:15:25.926788 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9876 12:15:25.929271 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9877 12:15:25.935940 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9878 12:15:25.939716 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9879 12:15:25.946636 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9880 12:15:25.949615 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9881 12:15:25.955574 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9882 12:15:25.959737 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9883 12:15:25.965806 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9884 12:15:25.968701 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9885 12:15:25.972445 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9886 12:15:25.978579 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9887 12:15:25.981699 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9888 12:15:25.988579 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9889 12:15:25.991497 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9890 12:15:25.998011 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9891 12:15:26.002183 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9892 12:15:26.008101 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9893 12:15:26.011381 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9894 12:15:26.014998 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9895 12:15:26.021687 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9896 12:15:26.024802 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9897 12:15:26.031076 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9898 12:15:26.034611 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9899 12:15:26.041179 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9900 12:15:26.044803 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9901 12:15:26.051360 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9902 12:15:26.054773 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9903 12:15:26.057798 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9904 12:15:26.064888 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9905 12:15:26.068341 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9906 12:15:26.074525 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9907 12:15:26.077484 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9908 12:15:26.084561 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9909 12:15:26.088795 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9910 12:15:26.094025 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9911 12:15:26.097286 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9912 12:15:26.100689 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9913 12:15:26.108172 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9914 12:15:26.111796 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9915 12:15:26.117281 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9916 12:15:26.121392 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9917 12:15:26.127500 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9918 12:15:26.130814 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9919 12:15:26.136981 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9920 12:15:26.140292 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9921 12:15:26.143912 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9922 12:15:26.150730 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9923 12:15:26.153772 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9924 12:15:26.160158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9925 12:15:26.163911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9926 12:15:26.167434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9927 12:15:26.173264 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9928 12:15:26.177646 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9929 12:15:26.183443 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9930 12:15:26.186964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9931 12:15:26.193281 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9932 12:15:26.196666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9933 12:15:26.203226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9934 12:15:26.207353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9935 12:15:26.213140 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9936 12:15:26.216318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9937 12:15:26.223100 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9938 12:15:26.226491 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9939 12:15:26.233039 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9940 12:15:26.236334 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9941 12:15:26.242630 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9942 12:15:26.246271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9943 12:15:26.252379 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9944 12:15:26.255803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9945 12:15:26.262568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9946 12:15:26.265929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9947 12:15:26.273167 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9948 12:15:26.276022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9949 12:15:26.282749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9950 12:15:26.286345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9951 12:15:26.292292 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9952 12:15:26.295162 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9953 12:15:26.302004 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9954 12:15:26.309165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9955 12:15:26.312437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9956 12:15:26.315102 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9957 12:15:26.318641 INFO: [APUAPC] vio 0
9958 12:15:26.321898 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9959 12:15:26.328408 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9960 12:15:26.331762 INFO: [APUAPC] D0_APC_0: 0x400510
9961 12:15:26.335570 INFO: [APUAPC] D0_APC_1: 0x0
9962 12:15:26.338398 INFO: [APUAPC] D0_APC_2: 0x1540
9963 12:15:26.338963 INFO: [APUAPC] D0_APC_3: 0x0
9964 12:15:26.345134 INFO: [APUAPC] D1_APC_0: 0xffffffff
9965 12:15:26.348354 INFO: [APUAPC] D1_APC_1: 0xffffffff
9966 12:15:26.351550 INFO: [APUAPC] D1_APC_2: 0x3fffff
9967 12:15:26.352158 INFO: [APUAPC] D1_APC_3: 0x0
9968 12:15:26.355429 INFO: [APUAPC] D2_APC_0: 0xffffffff
9969 12:15:26.358167 INFO: [APUAPC] D2_APC_1: 0xffffffff
9970 12:15:26.361808 INFO: [APUAPC] D2_APC_2: 0x3fffff
9971 12:15:26.365024 INFO: [APUAPC] D2_APC_3: 0x0
9972 12:15:26.368071 INFO: [APUAPC] D3_APC_0: 0xffffffff
9973 12:15:26.371076 INFO: [APUAPC] D3_APC_1: 0xffffffff
9974 12:15:26.375794 INFO: [APUAPC] D3_APC_2: 0x3fffff
9975 12:15:26.378489 INFO: [APUAPC] D3_APC_3: 0x0
9976 12:15:26.381649 INFO: [APUAPC] D4_APC_0: 0xffffffff
9977 12:15:26.384884 INFO: [APUAPC] D4_APC_1: 0xffffffff
9978 12:15:26.388022 INFO: [APUAPC] D4_APC_2: 0x3fffff
9979 12:15:26.391288 INFO: [APUAPC] D4_APC_3: 0x0
9980 12:15:26.394410 INFO: [APUAPC] D5_APC_0: 0xffffffff
9981 12:15:26.397881 INFO: [APUAPC] D5_APC_1: 0xffffffff
9982 12:15:26.401065 INFO: [APUAPC] D5_APC_2: 0x3fffff
9983 12:15:26.404851 INFO: [APUAPC] D5_APC_3: 0x0
9984 12:15:26.407616 INFO: [APUAPC] D6_APC_0: 0xffffffff
9985 12:15:26.410865 INFO: [APUAPC] D6_APC_1: 0xffffffff
9986 12:15:26.414401 INFO: [APUAPC] D6_APC_2: 0x3fffff
9987 12:15:26.418623 INFO: [APUAPC] D6_APC_3: 0x0
9988 12:15:26.420907 INFO: [APUAPC] D7_APC_0: 0xffffffff
9989 12:15:26.424184 INFO: [APUAPC] D7_APC_1: 0xffffffff
9990 12:15:26.427506 INFO: [APUAPC] D7_APC_2: 0x3fffff
9991 12:15:26.431484 INFO: [APUAPC] D7_APC_3: 0x0
9992 12:15:26.434239 INFO: [APUAPC] D8_APC_0: 0xffffffff
9993 12:15:26.438660 INFO: [APUAPC] D8_APC_1: 0xffffffff
9994 12:15:26.440806 INFO: [APUAPC] D8_APC_2: 0x3fffff
9995 12:15:26.444424 INFO: [APUAPC] D8_APC_3: 0x0
9996 12:15:26.447280 INFO: [APUAPC] D9_APC_0: 0xffffffff
9997 12:15:26.450708 INFO: [APUAPC] D9_APC_1: 0xffffffff
9998 12:15:26.454361 INFO: [APUAPC] D9_APC_2: 0x3fffff
9999 12:15:26.457043 INFO: [APUAPC] D9_APC_3: 0x0
10000 12:15:26.460861 INFO: [APUAPC] D10_APC_0: 0xffffffff
10001 12:15:26.463653 INFO: [APUAPC] D10_APC_1: 0xffffffff
10002 12:15:26.467867 INFO: [APUAPC] D10_APC_2: 0x3fffff
10003 12:15:26.470270 INFO: [APUAPC] D10_APC_3: 0x0
10004 12:15:26.473500 INFO: [APUAPC] D11_APC_0: 0xffffffff
10005 12:15:26.477469 INFO: [APUAPC] D11_APC_1: 0xffffffff
10006 12:15:26.482408 INFO: [APUAPC] D11_APC_2: 0x3fffff
10007 12:15:26.483635 INFO: [APUAPC] D11_APC_3: 0x0
10008 12:15:26.486703 INFO: [APUAPC] D12_APC_0: 0xffffffff
10009 12:15:26.490219 INFO: [APUAPC] D12_APC_1: 0xffffffff
10010 12:15:26.493331 INFO: [APUAPC] D12_APC_2: 0x3fffff
10011 12:15:26.496962 INFO: [APUAPC] D12_APC_3: 0x0
10012 12:15:26.500287 INFO: [APUAPC] D13_APC_0: 0xffffffff
10013 12:15:26.503376 INFO: [APUAPC] D13_APC_1: 0xffffffff
10014 12:15:26.506612 INFO: [APUAPC] D13_APC_2: 0x3fffff
10015 12:15:26.510080 INFO: [APUAPC] D13_APC_3: 0x0
10016 12:15:26.513100 INFO: [APUAPC] D14_APC_0: 0xffffffff
10017 12:15:26.516525 INFO: [APUAPC] D14_APC_1: 0xffffffff
10018 12:15:26.519990 INFO: [APUAPC] D14_APC_2: 0x3fffff
10019 12:15:26.523587 INFO: [APUAPC] D14_APC_3: 0x0
10020 12:15:26.526685 INFO: [APUAPC] D15_APC_0: 0xffffffff
10021 12:15:26.530061 INFO: [APUAPC] D15_APC_1: 0xffffffff
10022 12:15:26.533228 INFO: [APUAPC] D15_APC_2: 0x3fffff
10023 12:15:26.536772 INFO: [APUAPC] D15_APC_3: 0x0
10024 12:15:26.539723 INFO: [APUAPC] APC_CON: 0x4
10025 12:15:26.543230 INFO: [NOCDAPC] D0_APC_0: 0x0
10026 12:15:26.546646 INFO: [NOCDAPC] D0_APC_1: 0x0
10027 12:15:26.549326 INFO: [NOCDAPC] D1_APC_0: 0x0
10028 12:15:26.552988 INFO: [NOCDAPC] D1_APC_1: 0xfff
10029 12:15:26.556959 INFO: [NOCDAPC] D2_APC_0: 0x0
10030 12:15:26.557443 INFO: [NOCDAPC] D2_APC_1: 0xfff
10031 12:15:26.560008 INFO: [NOCDAPC] D3_APC_0: 0x0
10032 12:15:26.562666 INFO: [NOCDAPC] D3_APC_1: 0xfff
10033 12:15:26.566535 INFO: [NOCDAPC] D4_APC_0: 0x0
10034 12:15:26.569287 INFO: [NOCDAPC] D4_APC_1: 0xfff
10035 12:15:26.572538 INFO: [NOCDAPC] D5_APC_0: 0x0
10036 12:15:26.575624 INFO: [NOCDAPC] D5_APC_1: 0xfff
10037 12:15:26.579402 INFO: [NOCDAPC] D6_APC_0: 0x0
10038 12:15:26.582674 INFO: [NOCDAPC] D6_APC_1: 0xfff
10039 12:15:26.585646 INFO: [NOCDAPC] D7_APC_0: 0x0
10040 12:15:26.589321 INFO: [NOCDAPC] D7_APC_1: 0xfff
10041 12:15:26.592385 INFO: [NOCDAPC] D8_APC_0: 0x0
10042 12:15:26.595526 INFO: [NOCDAPC] D8_APC_1: 0xfff
10043 12:15:26.596274 INFO: [NOCDAPC] D9_APC_0: 0x0
10044 12:15:26.599091 INFO: [NOCDAPC] D9_APC_1: 0xfff
10045 12:15:26.602406 INFO: [NOCDAPC] D10_APC_0: 0x0
10046 12:15:26.606460 INFO: [NOCDAPC] D10_APC_1: 0xfff
10047 12:15:26.609020 INFO: [NOCDAPC] D11_APC_0: 0x0
10048 12:15:26.612038 INFO: [NOCDAPC] D11_APC_1: 0xfff
10049 12:15:26.615797 INFO: [NOCDAPC] D12_APC_0: 0x0
10050 12:15:26.618434 INFO: [NOCDAPC] D12_APC_1: 0xfff
10051 12:15:26.622115 INFO: [NOCDAPC] D13_APC_0: 0x0
10052 12:15:26.625169 INFO: [NOCDAPC] D13_APC_1: 0xfff
10053 12:15:26.628259 INFO: [NOCDAPC] D14_APC_0: 0x0
10054 12:15:26.631944 INFO: [NOCDAPC] D14_APC_1: 0xfff
10055 12:15:26.635648 INFO: [NOCDAPC] D15_APC_0: 0x0
10056 12:15:26.638522 INFO: [NOCDAPC] D15_APC_1: 0xfff
10057 12:15:26.641707 INFO: [NOCDAPC] APC_CON: 0x4
10058 12:15:26.644725 INFO: [APUAPC] set_apusys_apc done
10059 12:15:26.648360 INFO: [DEVAPC] devapc_init done
10060 12:15:26.651254 INFO: GICv3 without legacy support detected.
10061 12:15:26.654864 INFO: ARM GICv3 driver initialized in EL3
10062 12:15:26.657757 INFO: Maximum SPI INTID supported: 639
10063 12:15:26.661508 INFO: BL31: Initializing runtime services
10064 12:15:26.668099 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10065 12:15:26.671259 INFO: SPM: enable CPC mode
10066 12:15:26.674587 INFO: mcdi ready for mcusys-off-idle and system suspend
10067 12:15:26.681516 INFO: BL31: Preparing for EL3 exit to normal world
10068 12:15:26.684808 INFO: Entry point address = 0x80000000
10069 12:15:26.687837 INFO: SPSR = 0x8
10070 12:15:26.692164
10071 12:15:26.692720
10072 12:15:26.693089
10073 12:15:26.695923 Starting depthcharge on Spherion...
10074 12:15:26.696482
10075 12:15:26.696995 Wipe memory regions:
10076 12:15:26.697557
10077 12:15:26.700246 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10078 12:15:26.700804 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10079 12:15:26.701474 Setting prompt string to ['asurada:']
10080 12:15:26.701948 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10081 12:15:26.702675 [0x00000040000000, 0x00000054600000)
10082 12:15:26.821253
10083 12:15:26.821809 [0x00000054660000, 0x00000080000000)
10084 12:15:27.081520
10085 12:15:27.082075 [0x000000821a7280, 0x000000ffe64000)
10086 12:15:27.826845
10087 12:15:27.827400 [0x00000100000000, 0x00000240000000)
10088 12:15:29.717214
10089 12:15:29.720746 Initializing XHCI USB controller at 0x11200000.
10090 12:15:30.701468
10091 12:15:30.702023 R8152: Initializing
10092 12:15:30.702397
10093 12:15:30.705777 Version 9 (ocp_data = 6010)
10094 12:15:30.706343
10095 12:15:30.708042 R8152: Done initializing
10096 12:15:30.708508
10097 12:15:30.708879 Adding net device
10098 12:15:31.106369
10099 12:15:31.110245 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10100 12:15:31.110809
10101 12:15:31.111198
10102 12:15:31.111542
10103 12:15:31.112406 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10105 12:15:31.213758 asurada: tftpboot 192.168.201.1 12669522/tftp-deploy-c4g5e4u7/kernel/image.itb 12669522/tftp-deploy-c4g5e4u7/kernel/cmdline
10106 12:15:31.214374 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10107 12:15:31.214827 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10108 12:15:31.219623 tftpboot 192.168.201.1 12669522/tftp-deploy-c4g5e4u7/kernel/image.ittp-deploy-c4g5e4u7/kernel/cmdline
10109 12:15:31.220198
10110 12:15:31.220539 Waiting for link
10111 12:15:31.421392
10112 12:15:31.421957 done.
10113 12:15:31.422334
10114 12:15:31.422686 MAC: f4:f5:e8:50:de:0a
10115 12:15:31.423118
10116 12:15:31.423979 Sending DHCP discover... done.
10117 12:15:31.424376
10118 12:15:31.428566 Waiting for reply... done.
10119 12:15:31.429122
10120 12:15:31.431491 Sending DHCP request... done.
10121 12:15:31.432003
10122 12:15:31.434835 Waiting for reply... done.
10123 12:15:31.435394
10124 12:15:31.435829 My ip is 192.168.201.14
10125 12:15:31.436192
10126 12:15:31.438223 The DHCP server ip is 192.168.201.1
10127 12:15:31.438785
10128 12:15:31.444408 TFTP server IP predefined by user: 192.168.201.1
10129 12:15:31.445017
10130 12:15:31.451196 Bootfile predefined by user: 12669522/tftp-deploy-c4g5e4u7/kernel/image.itb
10131 12:15:31.451812
10132 12:15:31.453950 Sending tftp read request... done.
10133 12:15:31.454434
10134 12:15:31.461135 Waiting for the transfer...
10135 12:15:31.461633
10136 12:15:31.812913 00000000 ################################################################
10137 12:15:31.813061
10138 12:15:32.082568 00080000 ################################################################
10139 12:15:32.082704
10140 12:15:32.353159 00100000 ################################################################
10141 12:15:32.353306
10142 12:15:32.621281 00180000 ################################################################
10143 12:15:32.621426
10144 12:15:32.878335 00200000 ################################################################
10145 12:15:32.878477
10146 12:15:33.148045 00280000 ################################################################
10147 12:15:33.148185
10148 12:15:33.416986 00300000 ################################################################
10149 12:15:33.417135
10150 12:15:33.672572 00380000 ################################################################
10151 12:15:33.672713
10152 12:15:33.908288 00400000 ################################################################
10153 12:15:33.908424
10154 12:15:34.142567 00480000 ################################################################
10155 12:15:34.142705
10156 12:15:34.370072 00500000 ################################################################
10157 12:15:34.370206
10158 12:15:34.617605 00580000 ################################################################
10159 12:15:34.617752
10160 12:15:34.864878 00600000 ################################################################
10161 12:15:34.865018
10162 12:15:35.103011 00680000 ################################################################
10163 12:15:35.103149
10164 12:15:35.338077 00700000 ################################################################
10165 12:15:35.338214
10166 12:15:35.569474 00780000 ################################################################
10167 12:15:35.569633
10168 12:15:35.811211 00800000 ################################################################
10169 12:15:35.811355
10170 12:15:36.041636 00880000 ################################################################
10171 12:15:36.041769
10172 12:15:36.283686 00900000 ################################################################
10173 12:15:36.283817
10174 12:15:36.526688 00980000 ################################################################
10175 12:15:36.526827
10176 12:15:36.763666 00a00000 ################################################################
10177 12:15:36.763965
10178 12:15:37.031576 00a80000 ################################################################
10179 12:15:37.031724
10180 12:15:37.287898 00b00000 ################################################################
10181 12:15:37.288031
10182 12:15:37.537739 00b80000 ################################################################
10183 12:15:37.537880
10184 12:15:37.796410 00c00000 ################################################################
10185 12:15:37.796554
10186 12:15:38.062005 00c80000 ################################################################
10187 12:15:38.062148
10188 12:15:38.329614 00d00000 ################################################################
10189 12:15:38.329754
10190 12:15:38.595409 00d80000 ################################################################
10191 12:15:38.595553
10192 12:15:38.866201 00e00000 ################################################################
10193 12:15:38.866344
10194 12:15:39.133778 00e80000 ################################################################
10195 12:15:39.133921
10196 12:15:39.391583 00f00000 ################################################################
10197 12:15:39.391759
10198 12:15:39.624801 00f80000 ################################################################
10199 12:15:39.624938
10200 12:15:39.865792 01000000 ################################################################
10201 12:15:39.865927
10202 12:15:40.114819 01080000 ################################################################
10203 12:15:40.114963
10204 12:15:40.373740 01100000 ################################################################
10205 12:15:40.373882
10206 12:15:40.629014 01180000 ################################################################
10207 12:15:40.629152
10208 12:15:40.884008 01200000 ################################################################
10209 12:15:40.884149
10210 12:15:41.138613 01280000 ################################################################
10211 12:15:41.138755
10212 12:15:41.404674 01300000 ################################################################
10213 12:15:41.404855
10214 12:15:41.668717 01380000 ################################################################
10215 12:15:41.668859
10216 12:15:41.932406 01400000 ################################################################
10217 12:15:41.932541
10218 12:15:42.194897 01480000 ################################################################
10219 12:15:42.195056
10220 12:15:42.438180 01500000 ################################################################
10221 12:15:42.438343
10222 12:15:42.687585 01580000 ################################################################
10223 12:15:42.687780
10224 12:15:42.933107 01600000 ################################################################
10225 12:15:42.933243
10226 12:15:43.186194 01680000 ################################################################
10227 12:15:43.186358
10228 12:15:43.441190 01700000 ################################################################
10229 12:15:43.441362
10230 12:15:43.703100 01780000 ################################################################
10231 12:15:43.703245
10232 12:15:43.939855 01800000 ################################################################
10233 12:15:43.939990
10234 12:15:44.202158 01880000 ################################################################
10235 12:15:44.202293
10236 12:15:44.453536 01900000 ################################################################
10237 12:15:44.453681
10238 12:15:44.723763 01980000 ################################################################
10239 12:15:44.723907
10240 12:15:44.993970 01a00000 ################################################################
10241 12:15:44.994133
10242 12:15:45.254168 01a80000 ################################################################
10243 12:15:45.254338
10244 12:15:45.505266 01b00000 ################################################################
10245 12:15:45.505438
10246 12:15:45.759110 01b80000 ################################################################
10247 12:15:45.759259
10248 12:15:46.024261 01c00000 ################################################################
10249 12:15:46.024406
10250 12:15:46.266289 01c80000 ################################################################
10251 12:15:46.266429
10252 12:15:46.537761 01d00000 ################################################################
10253 12:15:46.537903
10254 12:15:46.805909 01d80000 ################################################################
10255 12:15:46.806087
10256 12:15:47.068626 01e00000 ################################################################
10257 12:15:47.068767
10258 12:15:47.304496 01e80000 ################################################################
10259 12:15:47.304629
10260 12:15:47.556003 01f00000 ################################################################
10261 12:15:47.556141
10262 12:15:47.819227 01f80000 ################################################################
10263 12:15:47.819365
10264 12:15:48.078585 02000000 ################################################################
10265 12:15:48.078726
10266 12:15:48.319020 02080000 ################################################################
10267 12:15:48.319160
10268 12:15:48.580613 02100000 ################################################################
10269 12:15:48.580763
10270 12:15:48.839842 02180000 ################################################################
10271 12:15:48.839980
10272 12:15:49.104433 02200000 ################################################################
10273 12:15:49.104578
10274 12:15:49.376242 02280000 ################################################################
10275 12:15:49.376381
10276 12:15:49.645534 02300000 ################################################################
10277 12:15:49.645671
10278 12:15:49.915054 02380000 ################################################################
10279 12:15:49.915192
10280 12:15:50.185960 02400000 ################################################################
10281 12:15:50.186099
10282 12:15:50.455795 02480000 ################################################################
10283 12:15:50.455944
10284 12:15:50.727590 02500000 ################################################################
10285 12:15:50.727765
10286 12:15:50.992512 02580000 ################################################################
10287 12:15:50.992656
10288 12:15:51.259300 02600000 ################################################################
10289 12:15:51.259452
10290 12:15:51.530302 02680000 ################################################################
10291 12:15:51.530441
10292 12:15:51.783994 02700000 ################################################################
10293 12:15:51.784128
10294 12:15:52.024187 02780000 ################################################################
10295 12:15:52.024324
10296 12:15:52.282075 02800000 ################################################################
10297 12:15:52.282220
10298 12:15:52.552335 02880000 ################################################################
10299 12:15:52.552473
10300 12:15:52.824143 02900000 ################################################################
10301 12:15:52.824277
10302 12:15:53.096620 02980000 ################################################################
10303 12:15:53.096764
10304 12:15:53.349359 02a00000 ################################################################
10305 12:15:53.349507
10306 12:15:53.596444 02a80000 ################################################################
10307 12:15:53.596579
10308 12:15:53.863475 02b00000 ################################################################
10309 12:15:53.863649
10310 12:15:54.092638 02b80000 ################################################################
10311 12:15:54.092769
10312 12:15:54.343592 02c00000 ################################################################
10313 12:15:54.343872
10314 12:15:54.600761 02c80000 ################################################################
10315 12:15:54.600924
10316 12:15:54.873023 02d00000 ################################################################
10317 12:15:54.873160
10318 12:15:55.145395 02d80000 ################################################################
10319 12:15:55.145527
10320 12:15:55.401465 02e00000 ################################################################
10321 12:15:55.401630
10322 12:15:55.670060 02e80000 ################################################################
10323 12:15:55.670226
10324 12:15:55.938901 02f00000 ################################################################
10325 12:15:55.939058
10326 12:15:56.173780 02f80000 ################################################################
10327 12:15:56.173934
10328 12:15:56.429046 03000000 ################################################################
10329 12:15:56.429190
10330 12:15:56.661875 03080000 ################################################################
10331 12:15:56.662020
10332 12:15:56.894581 03100000 ################################################################
10333 12:15:56.894738
10334 12:15:57.124312 03180000 ################################################################
10335 12:15:57.124467
10336 12:15:57.360962 03200000 ################################################################
10337 12:15:57.361095
10338 12:15:57.614100 03280000 ################################################################
10339 12:15:57.614260
10340 12:15:57.884081 03300000 ################################################################
10341 12:15:57.884244
10342 12:15:58.151470 03380000 ################################################################
10343 12:15:58.151627
10344 12:15:58.410101 03400000 ################################################################
10345 12:15:58.410263
10346 12:15:58.652508 03480000 ################################################################
10347 12:15:58.652667
10348 12:15:58.918524 03500000 ################################################################
10349 12:15:58.918691
10350 12:15:59.191211 03580000 ################################################################
10351 12:15:59.191369
10352 12:15:59.442163 03600000 ################################################################
10353 12:15:59.442327
10354 12:15:59.678322 03680000 ################################################################
10355 12:15:59.678481
10356 12:15:59.928775 03700000 ################################################################
10357 12:15:59.928914
10358 12:16:00.171389 03780000 ################################################################
10359 12:16:00.171549
10360 12:16:00.402227 03800000 ################################################################
10361 12:16:00.402401
10362 12:16:00.642782 03880000 ################################################################
10363 12:16:00.642918
10364 12:16:00.881865 03900000 ################################################################
10365 12:16:00.882026
10366 12:16:01.108560 03980000 ################################################################
10367 12:16:01.108717
10368 12:16:01.335500 03a00000 ################################################################
10369 12:16:01.335654
10370 12:16:01.573911 03a80000 ################################################################
10371 12:16:01.574068
10372 12:16:01.827997 03b00000 ################################################################
10373 12:16:01.828153
10374 12:16:02.084619 03b80000 ################################################################
10375 12:16:02.084760
10376 12:16:02.337657 03c00000 ################################################################
10377 12:16:02.337796
10378 12:16:02.575399 03c80000 ################################################################
10379 12:16:02.575564
10380 12:16:02.836044 03d00000 ################################################################
10381 12:16:02.836205
10382 12:16:03.086710 03d80000 ################################################################
10383 12:16:03.086849
10384 12:16:03.331635 03e00000 ################################################################
10385 12:16:03.331781
10386 12:16:03.573909 03e80000 ################################################################
10387 12:16:03.574045
10388 12:16:03.838847 03f00000 ################################################################
10389 12:16:03.839005
10390 12:16:04.071406 03f80000 ################################################################
10391 12:16:04.071562
10392 12:16:04.307293 04000000 ################################################################
10393 12:16:04.307464
10394 12:16:04.550507 04080000 ################################################################
10395 12:16:04.550641
10396 12:16:04.733225 04100000 ############################################## done.
10397 12:16:04.733352
10398 12:16:04.737235 The bootfile was 68534178 bytes long.
10399 12:16:04.737326
10400 12:16:04.740254 Sending tftp read request... done.
10401 12:16:04.740342
10402 12:16:04.740411 Waiting for the transfer...
10403 12:16:04.740476
10404 12:16:04.743196 00000000 # done.
10405 12:16:04.743293
10406 12:16:04.750026 Command line loaded dynamically from TFTP file: 12669522/tftp-deploy-c4g5e4u7/kernel/cmdline
10407 12:16:04.750212
10408 12:16:04.762999 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10409 12:16:04.763223
10410 12:16:04.766462 Loading FIT.
10411 12:16:04.766679
10412 12:16:04.769593 Image ramdisk-1 has 56437583 bytes.
10413 12:16:04.769850
10414 12:16:04.772827 Image fdt-1 has 47278 bytes.
10415 12:16:04.773009
10416 12:16:04.773145 Image kernel-1 has 12047284 bytes.
10417 12:16:04.775956
10418 12:16:04.783016 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10419 12:16:04.783347
10420 12:16:04.802971 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10421 12:16:04.803723
10422 12:16:04.806500 Choosing best match conf-1 for compat google,spherion-rev2.
10423 12:16:04.811195
10424 12:16:04.815735 Connected to device vid:did:rid of 1ae0:0028:00
10425 12:16:04.822688
10426 12:16:04.825486 tpm_get_response: command 0x17b, return code 0x0
10427 12:16:04.825955
10428 12:16:04.828704 ec_init: CrosEC protocol v3 supported (256, 248)
10429 12:16:04.833023
10430 12:16:04.836243 tpm_cleanup: add release locality here.
10431 12:16:04.836713
10432 12:16:04.837078 Shutting down all USB controllers.
10433 12:16:04.840243
10434 12:16:04.840860 Removing current net device
10435 12:16:04.841239
10436 12:16:04.847132 Exiting depthcharge with code 4 at timestamp: 67597348
10437 12:16:04.847731
10438 12:16:04.849746 LZMA decompressing kernel-1 to 0x821a6718
10439 12:16:04.850289
10440 12:16:04.853112 LZMA decompressing kernel-1 to 0x40000000
10441 12:16:06.353049
10442 12:16:06.353602 jumping to kernel
10443 12:16:06.355770 end: 2.2.4 bootloader-commands (duration 00:00:40) [common]
10444 12:16:06.356351 start: 2.2.5 auto-login-action (timeout 00:03:45) [common]
10445 12:16:06.356762 Setting prompt string to ['Linux version [0-9]']
10446 12:16:06.357193 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10447 12:16:06.357572 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10448 12:16:06.434853
10449 12:16:06.438422 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10450 12:16:06.442249 start: 2.2.5.1 login-action (timeout 00:03:45) [common]
10451 12:16:06.442823 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10452 12:16:06.443251 Setting prompt string to []
10453 12:16:06.443709 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10454 12:16:06.444128 Using line separator: #'\n'#
10455 12:16:06.444481 No login prompt set.
10456 12:16:06.444916 Parsing kernel messages
10457 12:16:06.445267 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10458 12:16:06.445855 [login-action] Waiting for messages, (timeout 00:03:45)
10459 12:16:06.461464 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j93261-arm64-gcc-10-defconfig-arm64-chromebook-cwjwh) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024
10460 12:16:06.464431 [ 0.000000] random: crng init done
10461 12:16:06.471810 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10462 12:16:06.474357 [ 0.000000] efi: UEFI not found.
10463 12:16:06.481301 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10464 12:16:06.488329 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10465 12:16:06.497677 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10466 12:16:06.507905 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10467 12:16:06.514305 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10468 12:16:06.520764 [ 0.000000] printk: bootconsole [mtk8250] enabled
10469 12:16:06.527288 [ 0.000000] NUMA: No NUMA configuration found
10470 12:16:06.534215 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10471 12:16:06.536997 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10472 12:16:06.541426 [ 0.000000] Zone ranges:
10473 12:16:06.547819 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10474 12:16:06.550419 [ 0.000000] DMA32 empty
10475 12:16:06.557202 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10476 12:16:06.560056 [ 0.000000] Movable zone start for each node
10477 12:16:06.563284 [ 0.000000] Early memory node ranges
10478 12:16:06.569878 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10479 12:16:06.576414 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10480 12:16:06.582932 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10481 12:16:06.589923 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10482 12:16:06.596722 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10483 12:16:06.602648 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10484 12:16:06.659555 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10485 12:16:06.666538 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10486 12:16:06.672602 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10487 12:16:06.676572 [ 0.000000] psci: probing for conduit method from DT.
10488 12:16:06.682684 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10489 12:16:06.685633 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10490 12:16:06.692914 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10491 12:16:06.695137 [ 0.000000] psci: SMC Calling Convention v1.2
10492 12:16:06.702046 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10493 12:16:06.705186 [ 0.000000] Detected VIPT I-cache on CPU0
10494 12:16:06.711897 [ 0.000000] CPU features: detected: GIC system register CPU interface
10495 12:16:06.720021 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10496 12:16:06.725275 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10497 12:16:06.732265 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10498 12:16:06.741714 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10499 12:16:06.748255 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10500 12:16:06.751662 [ 0.000000] alternatives: applying boot alternatives
10501 12:16:06.757846 [ 0.000000] Fallback order for Node 0: 0
10502 12:16:06.765163 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10503 12:16:06.767962 [ 0.000000] Policy zone: Normal
10504 12:16:06.781138 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10505 12:16:06.791278 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10506 12:16:06.803846 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10507 12:16:06.813603 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10508 12:16:06.819946 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10509 12:16:06.823153 <6>[ 0.000000] software IO TLB: area num 8.
10510 12:16:06.879743 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10511 12:16:07.028476 <6>[ 0.000000] Memory: 7912140K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 440628K reserved, 32768K cma-reserved)
10512 12:16:07.035126 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10513 12:16:07.041532 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10514 12:16:07.044683 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10515 12:16:07.051710 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10516 12:16:07.058490 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10517 12:16:07.061245 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10518 12:16:07.072080 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10519 12:16:07.078396 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10520 12:16:07.084570 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10521 12:16:07.091221 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10522 12:16:07.094091 <6>[ 0.000000] GICv3: 608 SPIs implemented
10523 12:16:07.097930 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10524 12:16:07.103840 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10525 12:16:07.107648 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10526 12:16:07.113863 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10527 12:16:07.127059 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10528 12:16:07.140537 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10529 12:16:07.147043 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10530 12:16:07.155000 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10531 12:16:07.168163 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10532 12:16:07.174870 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10533 12:16:07.182141 <6>[ 0.009187] Console: colour dummy device 80x25
10534 12:16:07.191420 <6>[ 0.013915] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10535 12:16:07.198559 <6>[ 0.024357] pid_max: default: 32768 minimum: 301
10536 12:16:07.201246 <6>[ 0.029228] LSM: Security Framework initializing
10537 12:16:07.207832 <6>[ 0.034169] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10538 12:16:07.217405 <6>[ 0.041983] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10539 12:16:07.227495 <6>[ 0.051399] cblist_init_generic: Setting adjustable number of callback queues.
10540 12:16:07.230538 <6>[ 0.058887] cblist_init_generic: Setting shift to 3 and lim to 1.
10541 12:16:07.240584 <6>[ 0.065225] cblist_init_generic: Setting adjustable number of callback queues.
10542 12:16:07.246790 <6>[ 0.072652] cblist_init_generic: Setting shift to 3 and lim to 1.
10543 12:16:07.250589 <6>[ 0.079055] rcu: Hierarchical SRCU implementation.
10544 12:16:07.256784 <6>[ 0.084070] rcu: Max phase no-delay instances is 1000.
10545 12:16:07.263495 <6>[ 0.091127] EFI services will not be available.
10546 12:16:07.267240 <6>[ 0.096113] smp: Bringing up secondary CPUs ...
10547 12:16:07.275910 <6>[ 0.101192] Detected VIPT I-cache on CPU1
10548 12:16:07.282558 <6>[ 0.101261] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10549 12:16:07.288567 <6>[ 0.101292] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10550 12:16:07.292604 <6>[ 0.101633] Detected VIPT I-cache on CPU2
10551 12:16:07.302022 <6>[ 0.101682] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10552 12:16:07.308637 <6>[ 0.101699] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10553 12:16:07.312057 <6>[ 0.101952] Detected VIPT I-cache on CPU3
10554 12:16:07.319251 <6>[ 0.101998] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10555 12:16:07.325374 <6>[ 0.102012] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10556 12:16:07.331741 <6>[ 0.102317] CPU features: detected: Spectre-v4
10557 12:16:07.335508 <6>[ 0.102324] CPU features: detected: Spectre-BHB
10558 12:16:07.338187 <6>[ 0.102329] Detected PIPT I-cache on CPU4
10559 12:16:07.344589 <6>[ 0.102385] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10560 12:16:07.351666 <6>[ 0.102402] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10561 12:16:07.357728 <6>[ 0.102695] Detected PIPT I-cache on CPU5
10562 12:16:07.365054 <6>[ 0.102757] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10563 12:16:07.370887 <6>[ 0.102776] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10564 12:16:07.374500 <6>[ 0.103056] Detected PIPT I-cache on CPU6
10565 12:16:07.384659 <6>[ 0.103121] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10566 12:16:07.391013 <6>[ 0.103139] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10567 12:16:07.394121 <6>[ 0.103436] Detected PIPT I-cache on CPU7
10568 12:16:07.400853 <6>[ 0.103500] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10569 12:16:07.407463 <6>[ 0.103516] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10570 12:16:07.410241 <6>[ 0.103563] smp: Brought up 1 node, 8 CPUs
10571 12:16:07.417017 <6>[ 0.244857] SMP: Total of 8 processors activated.
10572 12:16:07.423765 <6>[ 0.249808] CPU features: detected: 32-bit EL0 Support
10573 12:16:07.429668 <6>[ 0.255171] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10574 12:16:07.436328 <6>[ 0.264026] CPU features: detected: Common not Private translations
10575 12:16:07.443166 <6>[ 0.270502] CPU features: detected: CRC32 instructions
10576 12:16:07.450216 <6>[ 0.275886] CPU features: detected: RCpc load-acquire (LDAPR)
10577 12:16:07.456712 <6>[ 0.281846] CPU features: detected: LSE atomic instructions
10578 12:16:07.459756 <6>[ 0.287663] CPU features: detected: Privileged Access Never
10579 12:16:07.466693 <6>[ 0.293443] CPU features: detected: RAS Extension Support
10580 12:16:07.473069 <6>[ 0.299087] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10581 12:16:07.476257 <6>[ 0.306300] CPU: All CPU(s) started at EL2
10582 12:16:07.483193 <6>[ 0.310643] alternatives: applying system-wide alternatives
10583 12:16:07.493358 <6>[ 0.321356] devtmpfs: initialized
10584 12:16:07.509303 <6>[ 0.330345] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10585 12:16:07.515559 <6>[ 0.340308] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10586 12:16:07.522649 <6>[ 0.348568] pinctrl core: initialized pinctrl subsystem
10587 12:16:07.525737 <6>[ 0.355213] DMI not present or invalid.
10588 12:16:07.531985 <6>[ 0.359627] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10589 12:16:07.542337 <6>[ 0.366507] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10590 12:16:07.549042 <6>[ 0.374093] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10591 12:16:07.559021 <6>[ 0.382328] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10592 12:16:07.565321 <6>[ 0.390569] audit: initializing netlink subsys (disabled)
10593 12:16:07.571782 <5>[ 0.396260] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10594 12:16:07.578113 <6>[ 0.396956] thermal_sys: Registered thermal governor 'step_wise'
10595 12:16:07.585457 <6>[ 0.404229] thermal_sys: Registered thermal governor 'power_allocator'
10596 12:16:07.587878 <6>[ 0.410482] cpuidle: using governor menu
10597 12:16:07.595280 <6>[ 0.421443] NET: Registered PF_QIPCRTR protocol family
10598 12:16:07.600915 <6>[ 0.426919] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10599 12:16:07.607427 <6>[ 0.434020] ASID allocator initialised with 32768 entries
10600 12:16:07.610675 <6>[ 0.440586] Serial: AMBA PL011 UART driver
10601 12:16:07.621238 <4>[ 0.449367] Trying to register duplicate clock ID: 134
10602 12:16:07.677174 <6>[ 0.508799] KASLR enabled
10603 12:16:07.691726 <6>[ 0.516631] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10604 12:16:07.698616 <6>[ 0.523642] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10605 12:16:07.705332 <6>[ 0.530128] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10606 12:16:07.712063 <6>[ 0.537133] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10607 12:16:07.718886 <6>[ 0.543617] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10608 12:16:07.725019 <6>[ 0.550620] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10609 12:16:07.731726 <6>[ 0.557105] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10610 12:16:07.737849 <6>[ 0.564108] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10611 12:16:07.741349 <6>[ 0.571625] ACPI: Interpreter disabled.
10612 12:16:07.749916 <6>[ 0.578051] iommu: Default domain type: Translated
10613 12:16:07.756560 <6>[ 0.583165] iommu: DMA domain TLB invalidation policy: strict mode
10614 12:16:07.759891 <5>[ 0.589827] SCSI subsystem initialized
10615 12:16:07.766385 <6>[ 0.593986] usbcore: registered new interface driver usbfs
10616 12:16:07.773138 <6>[ 0.599720] usbcore: registered new interface driver hub
10617 12:16:07.776238 <6>[ 0.605272] usbcore: registered new device driver usb
10618 12:16:07.783908 <6>[ 0.611382] pps_core: LinuxPPS API ver. 1 registered
10619 12:16:07.793107 <6>[ 0.616576] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10620 12:16:07.796620 <6>[ 0.625923] PTP clock support registered
10621 12:16:07.799838 <6>[ 0.630166] EDAC MC: Ver: 3.0.0
10622 12:16:07.807407 <6>[ 0.635336] FPGA manager framework
10623 12:16:07.813814 <6>[ 0.639018] Advanced Linux Sound Architecture Driver Initialized.
10624 12:16:07.817118 <6>[ 0.645798] vgaarb: loaded
10625 12:16:07.823906 <6>[ 0.648948] clocksource: Switched to clocksource arch_sys_counter
10626 12:16:07.826925 <5>[ 0.655388] VFS: Disk quotas dquot_6.6.0
10627 12:16:07.833256 <6>[ 0.659577] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10628 12:16:07.836932 <6>[ 0.666764] pnp: PnP ACPI: disabled
10629 12:16:07.845451 <6>[ 0.673494] NET: Registered PF_INET protocol family
10630 12:16:07.855079 <6>[ 0.679083] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10631 12:16:07.867076 <6>[ 0.691374] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10632 12:16:07.876642 <6>[ 0.700188] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10633 12:16:07.883153 <6>[ 0.708161] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10634 12:16:07.892715 <6>[ 0.716863] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10635 12:16:07.899469 <6>[ 0.726580] TCP: Hash tables configured (established 65536 bind 65536)
10636 12:16:07.905968 <6>[ 0.733440] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10637 12:16:07.916002 <6>[ 0.740640] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10638 12:16:07.922339 <6>[ 0.748345] NET: Registered PF_UNIX/PF_LOCAL protocol family
10639 12:16:07.930034 <6>[ 0.754518] RPC: Registered named UNIX socket transport module.
10640 12:16:07.932297 <6>[ 0.760670] RPC: Registered udp transport module.
10641 12:16:07.938795 <6>[ 0.765601] RPC: Registered tcp transport module.
10642 12:16:07.945625 <6>[ 0.770533] RPC: Registered tcp NFSv4.1 backchannel transport module.
10643 12:16:07.949292 <6>[ 0.777202] PCI: CLS 0 bytes, default 64
10644 12:16:07.952486 <6>[ 0.781590] Unpacking initramfs...
10645 12:16:07.968831 <6>[ 0.793541] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10646 12:16:07.978991 <6>[ 0.802203] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10647 12:16:07.982538 <6>[ 0.811056] kvm [1]: IPA Size Limit: 40 bits
10648 12:16:07.988898 <6>[ 0.815583] kvm [1]: GICv3: no GICV resource entry
10649 12:16:07.991649 <6>[ 0.820605] kvm [1]: disabling GICv2 emulation
10650 12:16:07.998686 <6>[ 0.825292] kvm [1]: GIC system register CPU interface enabled
10651 12:16:08.002313 <6>[ 0.831464] kvm [1]: vgic interrupt IRQ18
10652 12:16:08.008194 <6>[ 0.835820] kvm [1]: VHE mode initialized successfully
10653 12:16:08.015207 <5>[ 0.842330] Initialise system trusted keyrings
10654 12:16:08.021962 <6>[ 0.847123] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10655 12:16:08.028962 <6>[ 0.857123] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10656 12:16:08.036163 <5>[ 0.863502] NFS: Registering the id_resolver key type
10657 12:16:08.039502 <5>[ 0.868803] Key type id_resolver registered
10658 12:16:08.045950 <5>[ 0.873218] Key type id_legacy registered
10659 12:16:08.052542 <6>[ 0.877496] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10660 12:16:08.058718 <6>[ 0.884414] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10661 12:16:08.065152 <6>[ 0.892129] 9p: Installing v9fs 9p2000 file system support
10662 12:16:08.102435 <5>[ 0.930286] Key type asymmetric registered
10663 12:16:08.105255 <5>[ 0.934618] Asymmetric key parser 'x509' registered
10664 12:16:08.115214 <6>[ 0.939755] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10665 12:16:08.118412 <6>[ 0.947369] io scheduler mq-deadline registered
10666 12:16:08.121652 <6>[ 0.952147] io scheduler kyber registered
10667 12:16:08.141465 <6>[ 0.969139] EINJ: ACPI disabled.
10668 12:16:08.173333 <4>[ 0.994348] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10669 12:16:08.182917 <4>[ 1.004988] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10670 12:16:08.198077 <6>[ 1.025734] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10671 12:16:08.205535 <6>[ 1.033707] printk: console [ttyS0] disabled
10672 12:16:08.233752 <6>[ 1.058357] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10673 12:16:08.240873 <6>[ 1.067833] printk: console [ttyS0] enabled
10674 12:16:08.243400 <6>[ 1.067833] printk: console [ttyS0] enabled
10675 12:16:08.249824 <6>[ 1.076732] printk: bootconsole [mtk8250] disabled
10676 12:16:08.253605 <6>[ 1.076732] printk: bootconsole [mtk8250] disabled
10677 12:16:08.260299 <6>[ 1.087985] SuperH (H)SCI(F) driver initialized
10678 12:16:08.263252 <6>[ 1.093282] msm_serial: driver initialized
10679 12:16:08.277541 <6>[ 1.102267] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10680 12:16:08.287641 <6>[ 1.110812] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10681 12:16:08.293738 <6>[ 1.119354] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10682 12:16:08.304202 <6>[ 1.127983] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10683 12:16:08.314063 <6>[ 1.136691] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10684 12:16:08.320372 <6>[ 1.145404] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10685 12:16:08.330424 <6>[ 1.153944] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10686 12:16:08.337278 <6>[ 1.162746] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10687 12:16:08.347252 <6>[ 1.171295] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10688 12:16:08.359245 <6>[ 1.187065] loop: module loaded
10689 12:16:08.365566 <6>[ 1.193147] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10690 12:16:08.388423 <4>[ 1.216526] mtk-pmic-keys: Failed to locate of_node [id: -1]
10691 12:16:08.395073 <6>[ 1.223473] megasas: 07.719.03.00-rc1
10692 12:16:08.405212 <6>[ 1.232968] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10693 12:16:08.416287 <6>[ 1.244319] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10694 12:16:08.432577 <6>[ 1.260693] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10695 12:16:08.493545 <6>[ 1.314530] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10696 12:16:10.365948 <6>[ 3.193719] Freeing initrd memory: 55112K
10697 12:16:10.376079 <6>[ 3.203976] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10698 12:16:10.386906 <6>[ 3.214932] tun: Universal TUN/TAP device driver, 1.6
10699 12:16:10.389920 <6>[ 3.220999] thunder_xcv, ver 1.0
10700 12:16:10.393108 <6>[ 3.224491] thunder_bgx, ver 1.0
10701 12:16:10.397374 <6>[ 3.227990] nicpf, ver 1.0
10702 12:16:10.406924 <6>[ 3.232000] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10703 12:16:10.410926 <6>[ 3.239475] hns3: Copyright (c) 2017 Huawei Corporation.
10704 12:16:10.416739 <6>[ 3.245060] hclge is initializing
10705 12:16:10.420657 <6>[ 3.248636] e1000: Intel(R) PRO/1000 Network Driver
10706 12:16:10.426678 <6>[ 3.253766] e1000: Copyright (c) 1999-2006 Intel Corporation.
10707 12:16:10.429821 <6>[ 3.259782] e1000e: Intel(R) PRO/1000 Network Driver
10708 12:16:10.437360 <6>[ 3.264998] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10709 12:16:10.443356 <6>[ 3.271183] igb: Intel(R) Gigabit Ethernet Network Driver
10710 12:16:10.450464 <6>[ 3.276833] igb: Copyright (c) 2007-2014 Intel Corporation.
10711 12:16:10.457221 <6>[ 3.282668] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10712 12:16:10.463655 <6>[ 3.289186] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10713 12:16:10.466945 <6>[ 3.295650] sky2: driver version 1.30
10714 12:16:10.473834 <6>[ 3.300639] VFIO - User Level meta-driver version: 0.3
10715 12:16:10.480551 <6>[ 3.308832] usbcore: registered new interface driver usb-storage
10716 12:16:10.487574 <6>[ 3.315285] usbcore: registered new device driver onboard-usb-hub
10717 12:16:10.496336 <6>[ 3.324431] mt6397-rtc mt6359-rtc: registered as rtc0
10718 12:16:10.506111 <6>[ 3.329899] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-31T12:16:10 UTC (1706703370)
10719 12:16:10.510353 <6>[ 3.339466] i2c_dev: i2c /dev entries driver
10720 12:16:10.525983 <6>[ 3.351212] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10721 12:16:10.547251 <6>[ 3.375209] cpu cpu0: EM: created perf domain
10722 12:16:10.550381 <6>[ 3.380151] cpu cpu4: EM: created perf domain
10723 12:16:10.557238 <6>[ 3.385728] sdhci: Secure Digital Host Controller Interface driver
10724 12:16:10.564807 <6>[ 3.392159] sdhci: Copyright(c) Pierre Ossman
10725 12:16:10.571021 <6>[ 3.397116] Synopsys Designware Multimedia Card Interface Driver
10726 12:16:10.577324 <6>[ 3.403757] sdhci-pltfm: SDHCI platform and OF driver helper
10727 12:16:10.581611 <6>[ 3.403800] mmc0: CQHCI version 5.10
10728 12:16:10.587389 <6>[ 3.414025] ledtrig-cpu: registered to indicate activity on CPUs
10729 12:16:10.594029 <6>[ 3.421150] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10730 12:16:10.600331 <6>[ 3.428207] usbcore: registered new interface driver usbhid
10731 12:16:10.604023 <6>[ 3.434029] usbhid: USB HID core driver
10732 12:16:10.613599 <6>[ 3.438229] spi_master spi0: will run message pump with realtime priority
10733 12:16:10.656168 <6>[ 3.477485] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10734 12:16:10.675617 <6>[ 3.493172] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10735 12:16:10.681693 <6>[ 3.508020] cros-ec-spi spi0.0: Chrome EC device registered
10736 12:16:10.685161 <6>[ 3.514034] mmc0: Command Queue Engine enabled
10737 12:16:10.692367 <6>[ 3.518777] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10738 12:16:10.698624 <6>[ 3.526245] mmcblk0: mmc0:0001 DA4128 116 GiB
10739 12:16:10.706935 <6>[ 3.535693] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10740 12:16:10.714669 <6>[ 3.543182] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10741 12:16:10.724589 <6>[ 3.547017] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10742 12:16:10.728145 <6>[ 3.549094] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10743 12:16:10.734526 <6>[ 3.558966] NET: Registered PF_PACKET protocol family
10744 12:16:10.741011 <6>[ 3.563577] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10745 12:16:10.745844 <6>[ 3.568301] 9pnet: Installing 9P2000 support
10746 12:16:10.751072 <5>[ 3.579311] Key type dns_resolver registered
10747 12:16:10.755007 <6>[ 3.584281] registered taskstats version 1
10748 12:16:10.760883 <5>[ 3.588666] Loading compiled-in X.509 certificates
10749 12:16:10.790206 <4>[ 3.610722] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10750 12:16:10.799070 <4>[ 3.621471] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10751 12:16:10.805432 <3>[ 3.632002] debugfs: File 'uA_load' in directory '/' already present!
10752 12:16:10.812312 <3>[ 3.638758] debugfs: File 'min_uV' in directory '/' already present!
10753 12:16:10.818854 <3>[ 3.645375] debugfs: File 'max_uV' in directory '/' already present!
10754 12:16:10.825133 <3>[ 3.651986] debugfs: File 'constraint_flags' in directory '/' already present!
10755 12:16:10.837368 <3>[ 3.661594] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10756 12:16:10.846036 <6>[ 3.674181] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10757 12:16:10.853033 <6>[ 3.680930] xhci-mtk 11200000.usb: xHCI Host Controller
10758 12:16:10.859309 <6>[ 3.686435] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10759 12:16:10.869561 <6>[ 3.694279] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10760 12:16:10.876123 <6>[ 3.703707] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10761 12:16:10.882866 <6>[ 3.709782] xhci-mtk 11200000.usb: xHCI Host Controller
10762 12:16:10.889217 <6>[ 3.715257] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10763 12:16:10.896134 <6>[ 3.722902] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10764 12:16:10.902146 <6>[ 3.730561] hub 1-0:1.0: USB hub found
10765 12:16:10.905631 <6>[ 3.734568] hub 1-0:1.0: 1 port detected
10766 12:16:10.915835 <6>[ 3.738833] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10767 12:16:10.919571 <6>[ 3.747460] hub 2-0:1.0: USB hub found
10768 12:16:10.922204 <6>[ 3.751476] hub 2-0:1.0: 1 port detected
10769 12:16:10.931832 <6>[ 3.759433] mtk-msdc 11f70000.mmc: Got CD GPIO
10770 12:16:10.944618 <6>[ 3.769113] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10771 12:16:10.951267 <6>[ 3.777131] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10772 12:16:10.960381 <4>[ 3.785040] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10773 12:16:10.971156 <6>[ 3.794567] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10774 12:16:10.977418 <6>[ 3.802645] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10775 12:16:10.983903 <6>[ 3.810745] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10776 12:16:10.993663 <6>[ 3.818670] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10777 12:16:11.000261 <6>[ 3.826487] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10778 12:16:11.010907 <6>[ 3.834304] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10779 12:16:11.020153 <6>[ 3.844801] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10780 12:16:11.026636 <6>[ 3.853182] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10781 12:16:11.036655 <6>[ 3.861523] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10782 12:16:11.047062 <6>[ 3.869863] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10783 12:16:11.052852 <6>[ 3.878204] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10784 12:16:11.062977 <6>[ 3.886543] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10785 12:16:11.069567 <6>[ 3.894881] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10786 12:16:11.079450 <6>[ 3.903219] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10787 12:16:11.086308 <6>[ 3.911558] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10788 12:16:11.095835 <6>[ 3.919896] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10789 12:16:11.102961 <6>[ 3.928241] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10790 12:16:11.112430 <6>[ 3.936580] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10791 12:16:11.119244 <6>[ 3.944919] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10792 12:16:11.129191 <6>[ 3.953259] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10793 12:16:11.135575 <6>[ 3.961598] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10794 12:16:11.142637 <6>[ 3.970391] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10795 12:16:11.149169 <6>[ 3.977564] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10796 12:16:11.156366 <6>[ 3.984331] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10797 12:16:11.166243 <6>[ 3.991098] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10798 12:16:11.172509 <6>[ 3.998033] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10799 12:16:11.179354 <6>[ 4.004883] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10800 12:16:11.188858 <6>[ 4.014012] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10801 12:16:11.198330 <6>[ 4.023131] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10802 12:16:11.208268 <6>[ 4.032431] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10803 12:16:11.218586 <6>[ 4.041899] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10804 12:16:11.228613 <6>[ 4.051368] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10805 12:16:11.238543 <6>[ 4.060488] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10806 12:16:11.245450 <6>[ 4.069953] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10807 12:16:11.254805 <6>[ 4.079071] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10808 12:16:11.264346 <6>[ 4.088364] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10809 12:16:11.274424 <6>[ 4.098524] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10810 12:16:11.285341 <6>[ 4.110004] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10811 12:16:11.312430 <6>[ 4.137492] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10812 12:16:11.340365 <6>[ 4.168621] hub 2-1:1.0: USB hub found
10813 12:16:11.343299 <6>[ 4.173057] hub 2-1:1.0: 3 ports detected
10814 12:16:11.352205 <6>[ 4.180490] hub 2-1:1.0: USB hub found
10815 12:16:11.355734 <6>[ 4.184820] hub 2-1:1.0: 3 ports detected
10816 12:16:11.464119 <6>[ 4.289242] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10817 12:16:11.618968 <6>[ 4.447126] hub 1-1:1.0: USB hub found
10818 12:16:11.623542 <6>[ 4.451637] hub 1-1:1.0: 4 ports detected
10819 12:16:11.632150 <6>[ 4.460458] hub 1-1:1.0: USB hub found
10820 12:16:11.636466 <6>[ 4.464789] hub 1-1:1.0: 4 ports detected
10821 12:16:11.956846 <6>[ 4.781232] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10822 12:16:12.087070 <6>[ 4.915487] hub 1-1.1:1.0: USB hub found
10823 12:16:12.090742 <6>[ 4.919834] hub 1-1.1:1.0: 4 ports detected
10824 12:16:12.203988 <6>[ 5.029355] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10825 12:16:12.336259 <6>[ 5.164836] hub 1-1.4:1.0: USB hub found
10826 12:16:12.339963 <6>[ 5.169476] hub 1-1.4:1.0: 2 ports detected
10827 12:16:12.349200 <6>[ 5.177302] hub 1-1.4:1.0: USB hub found
10828 12:16:12.352288 <6>[ 5.181898] hub 1-1.4:1.0: 2 ports detected
10829 12:16:12.415637 <6>[ 5.241241] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10830 12:16:12.648338 <6>[ 5.473246] usb 1-1.4.1: new high-speed USB device number 6 using xhci-mtk
10831 12:16:12.840372 <6>[ 5.665248] usb 1-1.4.2: new high-speed USB device number 7 using xhci-mtk
10832 12:16:23.565403 <6>[ 16.398257] ALSA device list:
10833 12:16:23.571668 <6>[ 16.401548] No soundcards found.
10834 12:16:23.579833 <6>[ 16.409524] Freeing unused kernel memory: 8448K
10835 12:16:23.583030 <6>[ 16.414536] Run /init as init process
10836 12:16:23.629271 <6>[ 16.458727] NET: Registered PF_INET6 protocol family
10837 12:16:23.632875 <6>[ 16.464742] Segment Routing with IPv6
10838 12:16:23.639275 <6>[ 16.468687] In-situ OAM (IOAM) with IPv6
10839 12:16:23.673078 <30>[ 16.482314] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10840 12:16:23.675944 <30>[ 16.506051] systemd[1]: Detected architecture arm64.
10841 12:16:23.676494
10842 12:16:23.681886 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10843 12:16:23.682427
10844 12:16:23.695487 <30>[ 16.525396] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10845 12:16:23.824191 <30>[ 16.650799] systemd[1]: Queued start job for default target Graphical Interface.
10846 12:16:23.848181 <30>[ 16.678018] systemd[1]: Created slice system-getty.slice.
10847 12:16:23.854726 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10848 12:16:23.871816 <30>[ 16.701620] systemd[1]: Created slice system-modprobe.slice.
10849 12:16:23.878631 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10850 12:16:23.896549 <30>[ 16.726316] systemd[1]: Created slice system-serial\x2dgetty.slice.
10851 12:16:23.906778 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10852 12:16:23.920895 <30>[ 16.750155] systemd[1]: Created slice User and Session Slice.
10853 12:16:23.927346 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10854 12:16:23.947478 <30>[ 16.773822] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10855 12:16:23.957283 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10856 12:16:23.975551 <30>[ 16.801771] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10857 12:16:23.985127 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10858 12:16:24.006373 <30>[ 16.829662] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10859 12:16:24.012808 <30>[ 16.841965] systemd[1]: Reached target Local Encrypted Volumes.
10860 12:16:24.019562 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10861 12:16:24.035357 <30>[ 16.865249] systemd[1]: Reached target Paths.
10862 12:16:24.038944 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10863 12:16:24.056357 <30>[ 16.885225] systemd[1]: Reached target Remote File Systems.
10864 12:16:24.061725 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10865 12:16:24.079634 <30>[ 16.909651] systemd[1]: Reached target Slices.
10866 12:16:24.086594 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10867 12:16:24.099668 <30>[ 16.929261] systemd[1]: Reached target Swap.
10868 12:16:24.103159 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10869 12:16:24.123304 <30>[ 16.949700] systemd[1]: Listening on initctl Compatibility Named Pipe.
10870 12:16:24.129836 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10871 12:16:24.136255 <30>[ 16.964848] systemd[1]: Listening on Journal Audit Socket.
10872 12:16:24.143167 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10873 12:16:24.156038 <30>[ 16.985715] systemd[1]: Listening on Journal Socket (/dev/log).
10874 12:16:24.163835 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10875 12:16:24.181302 <30>[ 17.010479] systemd[1]: Listening on Journal Socket.
10876 12:16:24.187991 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10877 12:16:24.200341 <30>[ 17.029822] systemd[1]: Listening on udev Control Socket.
10878 12:16:24.206397 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10879 12:16:24.224412 <30>[ 17.054267] systemd[1]: Listening on udev Kernel Socket.
10880 12:16:24.231176 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10881 12:16:24.271313 <30>[ 17.101319] systemd[1]: Mounting Huge Pages File System...
10882 12:16:24.278473 Mounting [0;1;39mHuge Pages File System[0m...
10883 12:16:24.295122 <30>[ 17.124766] systemd[1]: Mounting POSIX Message Queue File System...
10884 12:16:24.301639 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10885 12:16:24.352030 <30>[ 17.181371] systemd[1]: Mounting Kernel Debug File System...
10886 12:16:24.358809 Mounting [0;1;39mKernel Debug File System[0m...
10887 12:16:24.375002 <30>[ 17.201665] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10888 12:16:24.388030 <30>[ 17.214371] systemd[1]: Starting Create list of static device nodes for the current kernel...
10889 12:16:24.395010 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10890 12:16:24.415787 <30>[ 17.245726] systemd[1]: Starting Load Kernel Module configfs...
10891 12:16:24.422586 Starting [0;1;39mLoad Kernel Module configfs[0m...
10892 12:16:24.439587 <30>[ 17.269601] systemd[1]: Starting Load Kernel Module drm...
10893 12:16:24.446817 Starting [0;1;39mLoad Kernel Module drm[0m...
10894 12:16:24.463750 <30>[ 17.289633] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10895 12:16:24.478142 <30>[ 17.307328] systemd[1]: Starting Journal Service...
10896 12:16:24.484177 Starting [0;1;39mJournal Service[0m...
10897 12:16:24.504480 <30>[ 17.334565] systemd[1]: Starting Load Kernel Modules...
10898 12:16:24.511511 Starting [0;1;39mLoad Kernel Modules[0m...
10899 12:16:24.556383 <30>[ 17.382292] systemd[1]: Starting Remount Root and Kernel File Systems...
10900 12:16:24.562308 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10901 12:16:24.578119 <30>[ 17.408102] systemd[1]: Starting Coldplug All udev Devices...
10902 12:16:24.585231 Starting [0;1;39mColdplug All udev Devices[0m...
10903 12:16:24.602969 <30>[ 17.432391] systemd[1]: Started Journal Service.
10904 12:16:24.608984 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10905 12:16:24.625487 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10906 12:16:24.644608 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10907 12:16:24.665008 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10908 12:16:24.684842 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10909 12:16:24.701471 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10910 12:16:24.718268 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10911 12:16:24.737406 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10912 12:16:24.757479 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10913 12:16:24.775415 See 'systemctl status systemd-remount-fs.service' for details.
10914 12:16:24.819598 Mounting [0;1;39mKernel Configuration File System[0m...
10915 12:16:24.840300 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10916 12:16:24.852621 <46>[ 17.679379] systemd-journald[188]: Received client request to flush runtime journal.
10917 12:16:24.864036 Starting [0;1;39mLoad/Save Random Seed[0m...
10918 12:16:24.885028 Starting [0;1;39mApply Kernel Variables[0m...
10919 12:16:24.909154 Starting [0;1;39mCreate System Users[0m...
10920 12:16:24.930920 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10921 12:16:24.953205 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10922 12:16:24.972786 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10923 12:16:24.990165 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10924 12:16:25.005145 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10925 12:16:25.021021 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10926 12:16:25.061174 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10927 12:16:25.084035 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10928 12:16:25.096571 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10929 12:16:25.111150 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10930 12:16:25.143545 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10931 12:16:25.168501 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10932 12:16:25.188733 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10933 12:16:25.212996 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10934 12:16:25.285541 Starting [0;1;39mNetwork Time Synchronization[0m...
10935 12:16:25.307668 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10936 12:16:25.325504 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10937 12:16:25.347832 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10938 12:16:25.373401 <6>[ 18.199745] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10939 12:16:25.383101 <6>[ 18.207745] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10940 12:16:25.389535 <6>[ 18.216481] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10941 12:16:25.396412 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10942 12:16:25.406932 <6>[ 18.233484] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10943 12:16:25.414978 <6>[ 18.244350] remoteproc remoteproc0: scp is available
10944 12:16:25.421166 <6>[ 18.250153] remoteproc remoteproc0: powering up scp
10945 12:16:25.430580 [[0;32m OK [<6>[ 18.256618] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10946 12:16:25.438049 0m] Reached targ<6>[ 18.266904] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10947 12:16:25.440447 et [0;1;39mSystem Time Set[0m.
10948 12:16:25.455819 <4>[ 18.281968] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10949 12:16:25.458938 <6>[ 18.289379] mc: Linux media interface: v0.10
10950 12:16:25.468409 <3>[ 18.292566] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10951 12:16:25.475415 <3>[ 18.302627] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10952 12:16:25.481641 <4>[ 18.303930] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10953 12:16:25.488302 <6>[ 18.304159] usbcore: registered new device driver r8152-cfgselector
10954 12:16:25.497837 [[0;32m OK [<6>[ 18.305406] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10955 12:16:25.508376 0m] Reached targ<3>[ 18.310756] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10956 12:16:25.515027 et [0;1;39mSyst<6>[ 18.325875] videodev: Linux video capture interface: v2.00
10957 12:16:25.525260 em Time Synchron<3>[ 18.333860] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10958 12:16:25.525815 ized[0m.
10959 12:16:25.535381 <4>[ 18.339244] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10960 12:16:25.538103 <4>[ 18.339244] Fallback method does not support PEC.
10961 12:16:25.545046 <6>[ 18.347431] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10962 12:16:25.554857 <3>[ 18.350251] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10963 12:16:25.562015 <3>[ 18.350257] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10964 12:16:25.569434 <3>[ 18.350267] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10965 12:16:25.579117 <3>[ 18.350273] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10966 12:16:25.588951 <3>[ 18.357821] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 12:16:25.598741 <6>[ 18.359164] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10968 12:16:25.602787 <6>[ 18.359920] pci_bus 0000:00: root bus resource [bus 00-ff]
10969 12:16:25.613140 <3>[ 18.374613] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10970 12:16:25.619214 <6>[ 18.381519] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10971 12:16:25.625681 <3>[ 18.389407] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10972 12:16:25.636126 <6>[ 18.397571] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10973 12:16:25.645998 <6>[ 18.399796] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10974 12:16:25.652508 <6>[ 18.399805] remoteproc remoteproc0: remote processor scp is now up
10975 12:16:25.658578 <6>[ 18.399819] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10976 12:16:25.668968 <3>[ 18.402755] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10977 12:16:25.675527 <3>[ 18.403622] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10978 12:16:25.682167 <3>[ 18.405531] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10979 12:16:25.692593 <3>[ 18.405538] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10980 12:16:25.699375 <6>[ 18.405761] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10981 12:16:25.710400 <3>[ 18.413409] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10982 12:16:25.716940 <3>[ 18.413434] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10983 12:16:25.723619 <3>[ 18.413439] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10984 12:16:25.733528 <3>[ 18.413447] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10985 12:16:25.741301 <3>[ 18.413453] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10986 12:16:25.747382 <6>[ 18.414413] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10987 12:16:25.754146 <6>[ 18.418345] r8152-cfgselector 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10988 12:16:25.764355 <3>[ 18.423073] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10989 12:16:25.770865 <6>[ 18.432843] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10990 12:16:25.781489 <3>[ 18.444884] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10991 12:16:25.784143 <6>[ 18.446589] pci 0000:00:00.0: supports D1 D2
10992 12:16:25.791268 <6>[ 18.446591] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10993 12:16:25.798321 <6>[ 18.447686] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10994 12:16:25.808519 <6>[ 18.450504] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10995 12:16:25.819466 <6>[ 18.472689] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10996 12:16:25.822415 <6>[ 18.480391] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10997 12:16:25.832567 <6>[ 18.490666] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10998 12:16:25.839238 <6>[ 18.493798] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10999 12:16:25.842133 <6>[ 18.503608] Bluetooth: Core ver 2.22
11000 12:16:25.849000 <6>[ 18.510227] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11001 12:16:25.859262 <6>[ 18.510244] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11002 12:16:25.865367 <6>[ 18.511318] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11003 12:16:25.878897 <6>[ 18.512446] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11004 12:16:25.882032 <6>[ 18.512586] usbcore: registered new interface driver uvcvideo
11005 12:16:25.892031 <3>[ 18.517693] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11006 12:16:25.898193 <6>[ 18.518436] NET: Registered PF_BLUETOOTH protocol family
11007 12:16:25.904982 <3>[ 18.518510] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11008 12:16:25.914602 <3>[ 18.519433] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11009 12:16:25.925385 <4>[ 18.523929] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11010 12:16:25.931617 <4>[ 18.523939] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11011 12:16:25.938498 <6>[ 18.526513] pci 0000:01:00.0: supports D1 D2
11012 12:16:25.945659 <6>[ 18.535424] Bluetooth: HCI device and connection manager initialized
11013 12:16:25.951156 <6>[ 18.543501] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11014 12:16:25.957680 <6>[ 18.544005] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11015 12:16:25.964033 <3>[ 18.546078] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11016 12:16:25.971473 <6>[ 18.551603] Bluetooth: HCI socket layer initialized
11017 12:16:25.977751 <6>[ 18.569166] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11018 12:16:25.987800 <3>[ 18.570144] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11019 12:16:25.990421 <6>[ 18.573109] r8152 1-1.1.1:1.0 eth0: v1.12.13
11020 12:16:25.997287 <6>[ 18.573203] usbcore: registered new interface driver r8152
11021 12:16:26.000542 <6>[ 18.575968] Bluetooth: L2CAP socket layer initialized
11022 12:16:26.010968 <6>[ 18.582144] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11023 12:16:26.013805 <6>[ 18.590640] Bluetooth: SCO socket layer initialized
11024 12:16:26.020481 <6>[ 18.591001] usbcore: registered new interface driver cdc_ether
11025 12:16:26.030538 <3>[ 18.591494] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11026 12:16:26.037354 <6>[ 18.598705] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11027 12:16:26.043444 <6>[ 18.598889] usbcore: registered new interface driver r8153_ecm
11028 12:16:26.050456 <6>[ 18.628030] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
11029 12:16:26.060357 <6>[ 18.634586] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11030 12:16:26.064386 <6>[ 18.667127] usbcore: registered new interface driver btusb
11031 12:16:26.073694 <4>[ 18.667933] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11032 12:16:26.080139 <3>[ 18.667950] Bluetooth: hci0: Failed to load firmware file (-2)
11033 12:16:26.087341 <3>[ 18.667957] Bluetooth: hci0: Failed to set up firmware (-2)
11034 12:16:26.097043 <4>[ 18.667964] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11035 12:16:26.106680 <6>[ 18.674108] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11036 12:16:26.112570 <6>[ 18.940254] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11037 12:16:26.119575 Startin<6>[ 18.948519] pci 0000:00:00.0: PCI bridge to [bus 01]
11038 12:16:26.129527 g [0;1;39mLoad/<6>[ 18.955110] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11039 12:16:26.136109 Save Screen …o<6>[ 18.964716] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11040 12:16:26.146001 f leds:white:kbd<6>[ 18.972999] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11041 12:16:26.152567 _backlight[0m..<6>[ 18.980494] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11042 12:16:26.153162 .
11043 12:16:26.173505 <5>[ 18.999500] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11044 12:16:26.179643 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11045 12:16:26.191292 <5>[ 19.016835] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11046 12:16:26.197705 <5>[ 19.024246] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11047 12:16:26.207093 <4>[ 19.032749] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11048 12:16:26.213268 <6>[ 19.041731] cfg80211: failed to load regulatory.db
11049 12:16:26.233104 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11050 12:16:26.254873 <6>[ 19.082084] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11051 12:16:26.262139 <6>[ 19.089583] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11052 12:16:26.286349 <6>[ 19.116253] mt7921e 0000:01:00.0: ASIC revision: 79610010
11053 12:16:26.351538 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11054 12:16:26.367951 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11055 12:16:26.391794 [[0;32m OK [0m] Started [0;<6>[ 19.217004] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
11056 12:16:26.392354 <6>[ 19.217004]
11057 12:16:26.398450 1;39mDiscard unused blocks once a week[0m.
11058 12:16:26.414817 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11059 12:16:26.431544 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11060 12:16:26.455444 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11061 12:16:26.467543 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11062 12:16:26.483237 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11063 12:16:26.502874 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11064 12:16:26.536446 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11065 12:16:26.573498 Starting [0;1;39mUser Login Management[0m...
11066 12:16:26.589825 Starting [0;1;39mPermit User Sessions[0m...
11067 12:16:26.608280 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11068 12:16:26.624582 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11069 12:16:26.644002 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11070 12:16:26.658277 <6>[ 19.484665] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
11071 12:16:26.665181 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11072 12:16:26.712848 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11073 12:16:26.733848 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11074 12:16:26.752096 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11075 12:16:26.768018 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11076 12:16:26.783944 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11077 12:16:26.836638 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11078 12:16:26.871622 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11079 12:16:26.912207
11080 12:16:26.912941
11081 12:16:26.915247 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11082 12:16:26.915750
11083 12:16:26.918344 debian-bullseye-arm64 login: root (automatic login)
11084 12:16:26.918912
11085 12:16:26.919280
11086 12:16:26.935527 Linux debian-bullseye-arm64 6.1.72-cip13 #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024 aarch64
11087 12:16:26.936132
11088 12:16:26.941884 The programs included with the Debian GNU/Linux system are free software;
11089 12:16:26.948315 the exact distribution terms for each program are described in the
11090 12:16:26.951760 individual files in /usr/share/doc/*/copyright.
11091 12:16:26.952318
11092 12:16:26.959746 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11093 12:16:26.961563 permitted by applicable law.
11094 12:16:26.963026 Matched prompt #10: / #
11096 12:16:26.964291 Setting prompt string to ['/ #']
11097 12:16:26.964765 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11099 12:16:26.965815 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11100 12:16:26.966305 start: 2.2.6 expect-shell-connection (timeout 00:03:25) [common]
11101 12:16:26.966678 Setting prompt string to ['/ #']
11102 12:16:26.967013 Forcing a shell prompt, looking for ['/ #']
11104 12:16:27.017849 / #
11105 12:16:27.018498 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11106 12:16:27.019110 Waiting using forced prompt support (timeout 00:02:30)
11107 12:16:27.024412
11108 12:16:27.025517 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11109 12:16:27.026065 start: 2.2.7 export-device-env (timeout 00:03:25) [common]
11110 12:16:27.026563 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11111 12:16:27.027021 end: 2.2 depthcharge-retry (duration 00:01:35) [common]
11112 12:16:27.027465 end: 2 depthcharge-action (duration 00:01:35) [common]
11113 12:16:27.028001 start: 3 lava-test-retry (timeout 00:08:02) [common]
11114 12:16:27.028486 start: 3.1 lava-test-shell (timeout 00:08:02) [common]
11115 12:16:27.028888 Using namespace: common
11117 12:16:27.130146 / # #
11118 12:16:27.130801 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11119 12:16:27.137094 #
11120 12:16:27.137971 Using /lava-12669522
11122 12:16:27.239225 / # export SHELL=/bin/sh
11123 12:16:27.245756 export SHELL=/bin/sh
11125 12:16:27.347371 / # . /lava-12669522/environment
11126 12:16:27.354005 . /lava-12669522/environment
11128 12:16:27.456160 / # /lava-12669522/bin/lava-test-runner /lava-12669522/0
11129 12:16:27.456790 Test shell timeout: 10s (minimum of the action and connection timeout)
11130 12:16:27.463418 /lava-12669522/bin/lava-test-runner /lava-12669522/0
11131 12:16:27.491401 + export TESTRUN_ID=0_igt-kms-me<8>[ 20.319327] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 12669522_1.5.2.3.1>
11132 12:16:27.492324 Received signal: <STARTRUN> 0_igt-kms-mediatek 12669522_1.5.2.3.1
11133 12:16:27.492742 Starting test lava.0_igt-kms-mediatek (12669522_1.5.2.3.1)
11134 12:16:27.493182 Skipping test definition patterns.
11135 12:16:27.494407 diatek
11136 12:16:27.497112 + cd /lava-12669522/0/tests/0_igt-kms-mediatek
11137 12:16:27.497579 + cat uuid
11138 12:16:27.500605 + UUID=12669522_1.5.2.3.1
11139 12:16:27.501141 + set +x
11140 12:16:27.507353 + IGT_F<6>[ 20.336531] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11141 12:16:27.520462 ORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getsta<8>[ 20.349556] <LAVA_SIGNAL_TESTSET START core_auth>
11142 12:16:27.521357 Received signal: <TESTSET> START core_auth
11143 12:16:27.521768 Starting test_set core_auth
11144 12:16:27.530479 ts core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11145 12:16:27.539566 <14>[ 20.369698] [IGT] core_auth: executing
11146 12:16:27.546353 IGT-Version: 1.2<14>[ 20.374043] [IGT] core_auth: starting subtest getclient-simple
11147 12:16:27.556413 7.1-g621c2d3 (aa<14>[ 20.381651] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11148 12:16:27.559416 rch64) (Linux: 6<14>[ 20.390021] [IGT] core_auth: exiting, ret=0
11149 12:16:27.562492 .1.72-cip13 aarch64)
11150 12:16:27.565711 Starting subtest: getclient-simple
11151 12:16:27.575899 Opened device: /dev/dr<8>[ 20.401530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11152 12:16:27.576467 i/card0
11153 12:16:27.577117 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11155 12:16:27.579039 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11156 12:16:27.593072 <14>[ 20.422802] [IGT] core_auth: executing
11157 12:16:27.599165 IGT-Version: 1.2<14>[ 20.427140] [IGT] core_auth: starting subtest getclient-master-drop
11158 12:16:27.609689 7.1-g621c2d3 (aa<14>[ 20.435202] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11159 12:16:27.615370 rch64) (Linux: 6<14>[ 20.443963] [IGT] core_auth: exiting, ret=0
11160 12:16:27.615986 .1.72-cip13 aarch64)
11161 12:16:27.625736 Starting subtest: getclien<8>[ 20.453903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11162 12:16:27.626589 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11164 12:16:27.628431 t-master-drop
11165 12:16:27.632637 Opened device: /dev/dri/card0
11166 12:16:27.635392 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11167 12:16:27.643413 <14>[ 20.473488] [IGT] core_auth: executing
11168 12:16:27.650676 IGT-Version: 1.2<14>[ 20.478053] [IGT] core_auth: starting subtest basic-auth
11169 12:16:27.656438 7.1-g621c2d3 (aa<14>[ 20.485054] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11170 12:16:27.663836 rch64) (Linux: 6<14>[ 20.492828] [IGT] core_auth: exiting, ret=0
11171 12:16:27.666230 .1.72-cip13 aarch64)
11172 12:16:27.673383 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11174 12:16:27.676390 Opened device: /dev/dri/ca<8>[ 20.502876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11175 12:16:27.676983 rd0
11176 12:16:27.677352 Starting subtest: basic-auth
11177 12:16:27.682749 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11178 12:16:27.692262 <14>[ 20.521774] [IGT] core_auth: executing
11179 12:16:27.698134 IGT-Version: 1.2<14>[ 20.526270] [IGT] core_auth: starting subtest many-magics
11180 12:16:27.701483 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11181 12:16:27.711536 Opened device: /dev/dri/ca<14>[ 20.540127] [IGT] core_auth: finished subtest many-magics, SUCCESS
11182 12:16:27.712144 rd0
11183 12:16:27.717897 Starting su<14>[ 20.546778] [IGT] core_auth: exiting, ret=0
11184 12:16:27.718461 btest: many-magics
11185 12:16:27.724383 Reopening device failed after 1020 opens
11186 12:16:27.731049 [<8>[ 20.557052] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11187 12:16:27.731901 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11189 12:16:27.737896 1mSubtest many-magics: SUCCESS (<8>[ 20.567151] <LAVA_SIGNAL_TESTSET STOP>
11190 12:16:27.738364 0.007s)[0m
11191 12:16:27.739019 Received signal: <TESTSET> STOP
11192 12:16:27.739404 Closing test_set core_auth
11193 12:16:27.766778 <14>[ 20.596778] [IGT] core_getclient: executing
11194 12:16:27.773489 IGT-Version: 1.2<14>[ 20.601657] [IGT] core_getclient: exiting, ret=0
11195 12:16:27.776732 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11196 12:16:27.786374 Opened dev<8>[ 20.613317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11197 12:16:27.786939 ice: /dev/dri/card0
11198 12:16:27.787587 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11200 12:16:27.789450 SUCCESS (0.006s)
11201 12:16:27.815114 <14>[ 20.645207] [IGT] core_getstats: executing
11202 12:16:27.821998 IGT-Version: 1.2<14>[ 20.650067] [IGT] core_getstats: exiting, ret=0
11203 12:16:27.824680 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11204 12:16:27.834764 Opened dev<8>[ 20.661466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11205 12:16:27.835323 ice: /dev/dri/card0
11206 12:16:27.836096 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11208 12:16:27.838436 SUCCESS (0.006s)
11209 12:16:27.863306 <14>[ 20.693498] [IGT] core_getversion: executing
11210 12:16:27.869992 IGT-Version: 1.2<14>[ 20.698444] [IGT] core_getversion: exiting, ret=0
11211 12:16:27.873843 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11212 12:16:27.883408 Opened dev<8>[ 20.709804] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11213 12:16:27.884030 ice: /dev/dri/card0
11214 12:16:27.884687 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11216 12:16:27.886076 SUCCESS (0.006s)
11217 12:16:27.925289 <14>[ 20.755069] [IGT] core_setmaster_vs_auth: executing
11218 12:16:27.931624 IGT-Version: 1.2<14>[ 20.760657] [IGT] core_setmaster_vs_auth: exiting, ret=0
11219 12:16:27.938746 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11220 12:16:27.947643 Opened device: /dev/dri/ca<8>[ 20.773845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11221 12:16:27.948243 rd0
11222 12:16:27.948603 SUCCESS (0.007s)
11223 12:16:27.949219 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11225 12:16:27.967419 <8>[ 20.797585] <LAVA_SIGNAL_TESTSET START drm_read>
11226 12:16:27.968312 Received signal: <TESTSET> START drm_read
11227 12:16:27.968705 Starting test_set drm_read
11228 12:16:27.984657 <14>[ 20.814521] [IGT] drm_read: executing
11229 12:16:27.991097 IGT-Version: 1.2<14>[ 20.819002] [IGT] drm_read: exiting, ret=77
11230 12:16:27.995003 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11231 12:16:28.001018 Opened dev<8>[ 20.829461] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11232 12:16:28.001864 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11234 12:16:28.004196 ice: /dev/dri/card0
11235 12:16:28.007943 No KMS driver or no outputs, pipes: 8, outputs: 0
11236 12:16:28.013976 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11237 12:16:28.017429 <14>[ 20.849578] [IGT] drm_read: executing
11238 12:16:28.023937 IGT-Version: 1.2<14>[ 20.854151] [IGT] drm_read: exiting, ret=77
11239 12:16:28.030685 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11240 12:16:28.036922 Opened dev<8>[ 20.865039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11241 12:16:28.037781 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11243 12:16:28.040350 ice: /dev/dri/card0
11244 12:16:28.043584 No KMS driver or no outputs, pipes: 8, outputs: 0
11245 12:16:28.046614 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11246 12:16:28.054330 <14>[ 20.884549] [IGT] drm_read: executing
11247 12:16:28.060721 IGT-Version: 1.2<14>[ 20.889042] [IGT] drm_read: exiting, ret=77
11248 12:16:28.064136 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11249 12:16:28.071160 Opened dev<8>[ 20.900056] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11250 12:16:28.072058 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11252 12:16:28.073840 ice: /dev/dri/card0
11253 12:16:28.077465 No KMS driver or no outputs, pipes: 8, outputs: 0
11254 12:16:28.080871 [1mSubtest empty-block: SKIP (0.000s)[0m
11255 12:16:28.091504 <14>[ 20.921759] [IGT] drm_read: executing
11256 12:16:28.098307 IGT-Version: 1.2<14>[ 20.926315] [IGT] drm_read: exiting, ret=77
11257 12:16:28.101205 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11258 12:16:28.108449 Opened dev<8>[ 20.937106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11259 12:16:28.109194 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11261 12:16:28.113068 ice: /dev/dri/card0
11262 12:16:28.115453 No KMS driver or no outputs, pipes: 8, outputs: 0
11263 12:16:28.121304 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11264 12:16:28.136275 <14>[ 20.966273] [IGT] drm_read: executing
11265 12:16:28.142606 IGT-Version: 1.2<14>[ 20.970992] [IGT] drm_read: exiting, ret=77
11266 12:16:28.146484 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11267 12:16:28.155484 Opened dev<8>[ 20.981799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11268 12:16:28.156124 ice: /dev/dri/card0
11269 12:16:28.156785 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11271 12:16:28.158938 No KMS driver or no outputs, pipes: 8, outputs: 0
11272 12:16:28.166062 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11273 12:16:28.175198 <14>[ 21.004808] [IGT] drm_read: executing
11274 12:16:28.181083 IGT-Version: 1.2<14>[ 21.009386] [IGT] drm_read: exiting, ret=77
11275 12:16:28.184244 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11276 12:16:28.194826 Opened dev<8>[ 21.019948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11277 12:16:28.195389 ice: /dev/dri/card0
11278 12:16:28.196081 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11280 12:16:28.197523 No KMS driver or no outputs, pipes: 8, outputs: 0
11281 12:16:28.204304 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11282 12:16:28.212302 <14>[ 21.042564] [IGT] drm_read: executing
11283 12:16:28.219116 IGT-Version: 1.2<14>[ 21.047074] [IGT] drm_read: exiting, ret=77
11284 12:16:28.222317 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11285 12:16:28.231801 Opened dev<8>[ 21.058145] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11286 12:16:28.232645 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11288 12:16:28.235833 ice: /dev/dri/ca<8>[ 21.067206] <LAVA_SIGNAL_TESTSET STOP>
11289 12:16:28.236385 rd0
11290 12:16:28.237033 Received signal: <TESTSET> STOP
11291 12:16:28.237403 Closing test_set drm_read
11292 12:16:28.242187 No KMS driver or no outputs, pipes: 8, outputs: 0
11293 12:16:28.245583 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11294 12:16:28.266058 <8>[ 21.096657] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11295 12:16:28.266886 Received signal: <TESTSET> START kms_addfb_basic
11296 12:16:28.267281 Starting test_set kms_addfb_basic
11297 12:16:28.294117 <14>[ 21.124017] [IGT] kms_addfb_basic: executing
11298 12:16:28.307494 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarc<14>[ 21.133698] [IGT] kms_addfb_basic: starting subtest unused-handle
11299 12:16:39.245205 h64)
11300 12:16:39.246581 Opened dev<14>[ 21.141219] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11301 12:16:39.247242 ice: /dev/dri/card0
11302 12:16:39.247893 Starting subtest: unused-handle
11303 12:16:39.248487 [1mSubtest unused-handle: SUCCESS (0.000s)[0m
11304 12:16:39.249066 <14>[ 21.158722] [IGT] kms_addfb_basic: exiting, ret=0
11305 12:16:39.249650 Test requirement not met in function igt_require_i915, file ../l<8>[ 21.168976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11306 12:16:39.250235 ib/drmtest.c:720:
11307 12:16:39.250800 Test requirement: is_i915_device(fd)
11308 12:16:39.251370 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11309 12:16:39.251972 Test<14>[ 21.188624] [IGT] kms_addfb_basic: executing
11310 12:16:39.252553 requirement: is_i915_device(fd)
11311 12:16:39.253110 No KMS driver or no outputs, p<14>[ 21.197978] [IGT] kms_addfb_basic: starting subtest unused-pitches
11312 12:16:39.253683 ipes: 8, outputs<14>[ 21.205914] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11313 12:16:39.254248 : 0
11314 12:16:39.254804 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11315 12:16:39.255360 Opened device: /dev/d<14>[ 21.222599] [IGT] kms_addfb_basic: exiting, ret=0
11316 12:16:39.255944 ri/card0
11317 12:16:39.256497 Starting subtest: unused-pitches
11318 12:16:39.257050 [1mSubtest unused-pitches: SUCCESS <8>[ 21.233942] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11319 12:16:39.257611 (0.000s)[0m
11320 12:16:39.258163 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11321 12:16:39.258724 Test requirement: is_i915_device(fd)
11322 12:16:39.259273 Test requirement not met <14>[ 21.254867] [IGT] kms_addfb_basic: executing
11323 12:16:39.259869 in function igt_require_i915, file ../lib/drmtest.c:720:
11324 12:16:39.260428 Test r<14>[ 21.265103] [IGT] kms_addfb_basic: starting subtest unused-offsets
11325 12:16:39.260989 equirement: is_i<14>[ 21.272807] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11326 12:16:39.261539 915_device(fd)
11327 12:16:39.262099 No KMS driver or no outputs, pipes: 8, outputs: 0
11328 12:16:39.262656 IGT-Version: 1.27.1-g621c2d3 <14>[ 21.289633] [IGT] kms_addfb_basic: exiting, ret=0
11329 12:16:39.263211 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11330 12:16:39.263793 Opened device: /dev/dri/card0
11331 12:16:39.264347 Starting<8>[ 21.300867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11332 12:16:39.264894 subtest: unused-offsets
11333 12:16:39.265443 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11334 12:16:39.265985 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11335 12:16:39.266538 T<14>[ 21.322016] [IGT] kms_addfb_basic: executing
11336 12:16:39.267084 est requirement: is_i915_device(fd)
11337 12:16:39.267626 Test requirement not met in<14>[ 21.332040] [IGT] kms_addfb_basic: starting subtest unused-modifier
11338 12:16:39.268208 function igt_re<14>[ 21.339959] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11339 12:16:39.268709 quire_i915, file ../lib/drmtest.c:720:
11340 12:16:39.269208 Test requirement: is_i915_device(fd)
11341 12:16:39.269713 No KMS driver or n<14>[ 21.356689] [IGT] kms_addfb_basic: exiting, ret=0
11342 12:16:39.270120 o outputs, pipes: 8, outputs: 0
11343 12:16:39.270476 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: <8>[ 21.368089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11344 12:16:39.270833 6.1.72-cip13 aarch64)
11345 12:16:39.271200 Opened device: /dev/dri/card0
11346 12:16:39.271549 Starting subtest: unused-modifier
11347 12:16:39.271926 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11348 12:16:39.272284 Test requirement not<14>[ 21.388913] [IGT] kms_addfb_basic: executing
11349 12:16:39.272654 met in function igt_require_i915, file ../lib/drmtest.c:720:
11350 12:16:39.273014 T<14>[ 21.399216] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11351 12:16:39.273376 est requirement:<14>[ 21.407561] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11352 12:16:39.273731 is_i915_device(fd)
11353 12:16:39.274083 Test requirement not met in function igt_require_i915, file ../lib/drmtest.<14>[ 21.424360] [IGT] kms_addfb_basic: exiting, ret=77
11354 12:16:39.274443 c:720:
11355 12:16:39.274798 Test requirement: is_i915_device(fd)
11356 12:16:39.275089 No KMS driver or no outputs, pipes<8>[ 21.435883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11357 12:16:39.275361 : 8, outputs: 0
11358 12:16:39.275626 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11359 12:16:39.275913 Opened device: /dev/dri/card0
11360 12:16:39.276183 Starting subtest: clobberred-modifier
11361 12:16:39.276450 Tes<14>[ 21.457284] [IGT] kms_addfb_basic: executing
11362 12:16:39.276722 t requirement not met in function igt_require_i915, file ../lib/<14>[ 21.467425] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11363 12:16:39.276996 drmtest.c:720:
11364 12:16:39.277264 <14>[ 21.476445] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11365 12:16:39.277563 Test requirement: is_i915_device(fd)
11366 12:16:39.277838 [1mSubtest clobberred-modifier: SKIP (0.000s)[0m
11367 12:16:39.278112 Test r<14>[ 21.493771] [IGT] kms_addfb_basic: exiting, ret=77
11368 12:16:39.278634 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11370 12:16:39.279555 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11372 12:16:39.280365 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11374 12:16:39.281081 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11376 12:16:39.281794 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11378 12:16:39.282529 equirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11379 12:16:39.282766 Tes<8>[ 21.505257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11380 12:16:39.282944 t requirement: is_i915_device(fd)
11381 12:16:39.283118 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11382 12:16:39.283292 Test requirement: is_i915_device(fd)
11383 12:16:39.283508 No K<14>[ 21.527627] [IGT] kms_addfb_basic: executing
11384 12:16:39.283750 MS driver or no outputs, pipes: 8, outputs: 0
11385 12:16:39.283933 IGT-Version: 1.27<14>[ 21.537584] [IGT] kms_addfb_basic: starting subtest legacy-format
11386 12:16:39.284147 .1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11387 12:16:39.284363 Opened device: /dev/dri/car<14>[ 21.551675] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11388 12:16:39.284576 d0
11389 12:16:39.284743 Starting subtest: invalid-smem-bo-on-discrete
11390 12:16:39.284916 Test requirement not met in function igt_requ<14>[ 21.567313] [IGT] kms_addfb_basic: exiting, ret=0
11391 12:16:39.285056 ire_intel, file ../lib/drmtest.c:715:
11392 12:16:39.285196 Test requirement: is_intel_device(fd)
11393 12:16:39.285336 [<8>[ 21.579029] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11394 12:16:39.285476 1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11395 12:16:39.285652 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11396 12:16:39.285827 Test requirement: i<14>[ 21.599594] [IGT] kms_addfb_basic: executing
11397 12:16:39.286001 s_i915_device(fd)
11398 12:16:39.286140 Test requirement not met in function igt_require_i915, file .<14>[ 21.611887] [IGT] kms_addfb_basic: starting subtest no-handle
11399 12:16:39.286282 ./lib/drmtest.c:<14>[ 21.618686] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11400 12:16:39.286458 720:
11401 12:16:39.286635 Test requirement: is_i915_device(fd)
11402 12:16:39.286809 No KMS driver or no outputs, pipes: <14>[ 21.632625] [IGT] kms_addfb_basic: exiting, ret=0
11403 12:16:39.286985 8, outputs: 0
11404 12:16:39.287162 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch<8>[ 21.644873] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11405 12:16:39.287336 64)
11406 12:16:39.287475 Opened device: /dev/dri/card0
11407 12:16:39.287649 Starting subtest: legacy-format
11408 12:16:39.287832 Successfully fuzzed 10000 {bpp, depth} variations
11409 12:16:39.288023 [1mSubtest legacy-format: SUCCESS (0.006s)[0m
11410 12:16:39.288191 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11411 12:16:39.288306 Test<14>[ 21.674272] [IGT] kms_addfb_basic: executing
11412 12:16:39.288411 requirement: is_i915_device(fd)
11413 12:16:39.288515 Test requirement not met in function igt_require_i915, file ..<14>[ 21.686772] [IGT] kms_addfb_basic: starting subtest basic
11414 12:16:39.288621 /lib/drmtest.c:7<14>[ 21.693623] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11415 12:16:39.288724 20:
11416 12:16:39.288828 Test requirement: is_i915_device(fd)
11417 12:16:39.288931 No KMS driver or no outputs, pipes: 8<14>[ 21.707814] [IGT] kms_addfb_basic: exiting, ret=0
11418 12:16:39.289034 , outputs: 0
11419 12:16:39.289135 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch6<8>[ 21.719490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11420 12:16:39.289237 4)
11421 12:16:39.289339 Opened device: /dev/dri/card0
11422 12:16:39.289441 Starting subtest: no-handle
11423 12:16:39.289541 [1mSubtest no-handle: SUCCESS (0.000s)[0m
11424 12:16:39.289642 Test requirement not met in functio<14>[ 21.738936] [IGT] kms_addfb_basic: executing
11425 12:16:39.289744 n igt_require_i915, file ../lib/drmtest.c:720:
11426 12:16:39.289846 Test requirement: is_i915_device<14>[ 21.750544] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11427 12:16:39.289949 (fd)
11428 12:16:39.290034 Test requi<14>[ 21.757450] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11429 12:16:39.290121 rement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11430 12:16:39.290208 Test re<14>[ 21.771700] [IGT] kms_addfb_basic: exiting, ret=0
11431 12:16:39.290294 quirement: is_i915_device(fd)
11432 12:16:39.290380 No KMS driver or no outputs, pipes: 8, outputs: 0<8>[ 21.784019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11433 12:16:39.290469
11434 12:16:39.290555 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11435 12:16:39.290641 Opened device: /dev/dri/card0
11436 12:16:39.290726 Starting subtest: basic
11437 12:16:39.290812 [1mSubtest basic: SUCCESS (0.00<14>[ 21.804977] [IGT] kms_addfb_basic: executing
11438 12:16:39.290899 0s)[0m
11439 12:16:39.290987 Test requirement not met in function igt_require_i915, file ../lib/drmt<14>[ 21.816681] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11440 12:16:39.291074 est.c:720:
11441 12:16:39.291159 Test<14>[ 21.823706] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11442 12:16:39.291246 requirement: is_i915_device(fd)
11443 12:16:39.291332 Test requirement not met in function igt_requi<14>[ 21.838155] [IGT] kms_addfb_basic: exiting, ret=0
11444 12:16:39.291419 re_i915, file ../lib/drmtest.c:720:
11445 12:16:39.291504 Test requirement: is_i915_device(fd)
11446 12:16:39.291784 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11448 12:16:39.292081 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11450 12:16:39.292376 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11452 12:16:39.292672 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11454 12:16:39.292962 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11456 12:16:39.293271 No KM<8>[ 21.850272] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11457 12:16:39.293377 S driver or no outputs, pipes: 8, outputs: 0
11458 12:16:39.293472 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11459 12:16:39.293564 Opened device: /dev/dri/card0
11460 12:16:39.293653 Starting subt<14>[ 21.871255] [IGT] kms_addfb_basic: executing
11461 12:16:39.293744 est: bad-pitch-0
11462 12:16:39.293832 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11463 12:16:39.293920 Test requiremen<14>[ 21.883384] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11464 12:16:39.294009 t not met in fun<14>[ 21.890236] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11465 12:16:39.294098 ction igt_require_i915, file ../lib/drmtest.c:720:
11466 12:16:39.294185 Test requirement: is_i915_de<14>[ 21.904600] [IGT] kms_addfb_basic: exiting, ret=0
11467 12:16:39.294273 vice(fd)
11468 12:16:39.294359 Test requirement not met in function igt_require_i915, file ../lib/drm<8>[ 21.916756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11469 12:16:39.294448 test.c:720:
11470 12:16:39.294533 Test requirement: is_i915_device(fd)
11471 12:16:39.294620 No KMS driver or no outputs, pipes: 8, outputs: 0
11472 12:16:39.294707 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11473 12:16:39.294794 Opened device: /dev/dri/card0
11474 12:16:39.294892 Starting subtest: bad-pitch-32
11475 12:16:39.294968 [1mSubtest bad-pitch<14>[ 21.946303] [IGT] kms_addfb_basic: executing
11476 12:16:39.295043 -32: SUCCESS (0.000s)[0m
11477 12:16:39.295121 Test requirement not met in function igt_require_i915, file ../lib/dr<14>[ 21.958847] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11478 12:16:39.295198 mtest.c:720:
11479 12:16:39.295273 Te<14>[ 21.966465] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11480 12:16:39.295348 st requirement: is_i915_device(fd)
11481 12:16:39.295422 Test requirement not met in function igt_req<14>[ 21.981593] [IGT] kms_addfb_basic: exiting, ret=0
11482 12:16:39.295497 uire_i915, file ../lib/drmtest.c:720:
11483 12:16:39.295572 Test requirement: is_i915_device(fd)
11484 12:16:39.295647 No <8>[ 21.992667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11485 12:16:39.295740 KMS driver or no outputs, pipes: 8, outputs: 0
11486 12:16:39.295817 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11487 12:16:39.295893 Opened device: /dev/dri/card0
11488 12:16:39.295969 Starting su<14>[ 22.013628] [IGT] kms_addfb_basic: executing
11489 12:16:39.296044 btest: bad-pitch-63
11490 12:16:39.296118 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11491 12:16:39.296194 Test requir<14>[ 22.026232] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11492 12:16:39.296271 ement not met in<14>[ 22.033283] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11493 12:16:39.296348 function igt_require_i915, file ../lib/drmtest.c:720:
11494 12:16:39.296423 Test requirement: is_i91<14>[ 22.047694] [IGT] kms_addfb_basic: exiting, ret=0
11495 12:16:39.296499 5_device(fd)
11496 12:16:39.296576 Test requirement not met in function igt_require_i915, file ../lib<8>[ 22.060076] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11497 12:16:39.296652 /drmtest.c:720:
11498 12:16:39.296726 Test requirement: is_i915_device(fd)
11499 12:16:39.296802 No KMS driver or no outputs, pipes: 8, outputs: 0
11500 12:16:39.296878 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-<14>[ 22.080870] [IGT] kms_addfb_basic: executing
11501 12:16:39.296955 cip13 aarch64)
11502 12:16:39.297029 Opened device: /dev/dri/card0
11503 12:16:39.297104 Starting subtest: bad-pitch-128
11504 12:16:39.297179 <14>[ 22.093005] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11505 12:16:39.297256 [1mSubtest bad-<14>[ 22.100073] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11506 12:16:39.297331 pitch-128: SUCCESS (0.000s)[0m
11507 12:16:39.297407 Test requirement not met in function igt_requir<14>[ 22.114613] [IGT] kms_addfb_basic: exiting, ret=0
11508 12:16:39.297484 e_i915, file ../lib/drmtest.c:720:
11509 12:16:39.297559 Test requirement: is_i915_device(fd)
11510 12:16:39.297634 Test r<8>[ 22.126986] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11511 12:16:39.297710 equirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11512 12:16:39.297785 Test requirement: is_i915_device(fd)
11513 12:16:39.297861 No KMS driver or no outputs, pipes: 8, output<14>[ 22.148180] [IGT] kms_addfb_basic: executing
11514 12:16:39.297937 s: 0
11515 12:16:39.298012 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11516 12:16:39.298087 Open<14>[ 22.160100] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11517 12:16:39.298163 ed device: /dev/<14>[ 22.167201] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11518 12:16:39.298238 dri/card0
11519 12:16:39.298313 Starting subtest: bad-pitch-256
11520 12:16:39.298388 [1mSubtest bad-pitch-256: SUCCESS (<14>[ 22.181715] [IGT] kms_addfb_basic: exiting, ret=0
11521 12:16:39.298464 0.000s)[0m
11522 12:16:39.298542 Test requirement not met in function igt_require_i915, file ../lib/<8>[ 22.193899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11523 12:16:39.298619 drmtest.c:720:
11524 12:16:39.298693 Test requirement: is_i915_device(fd)
11525 12:16:39.298769 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11526 12:16:39.299030 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11528 12:16:39.299284 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11530 12:16:39.299538 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11532 12:16:39.299815 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11534 12:16:39.300065 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11536 12:16:39.300290 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11538 12:16:39.300526 Test requirement: is_i9<14>[ 22.214949] [IGT] kms_addfb_basic: executing
11539 12:16:39.300607 15_device(fd)
11540 12:16:39.300681 No KMS driver or no outputs, pipes: 8, outputs: 0
11541 12:16:39.300754 IGT-Version: 1<14>[ 22.226892] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11542 12:16:39.300824 .27.1-g621c2d3 (<14>[ 22.234126] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11543 12:16:39.300896 aarch64) (Linux: 6.1.72-cip13 aarch64)
11544 12:16:39.300965 Opened device: /dev/dri/card0
11545 12:16:39.301033 Starting <14>[ 22.248747] [IGT] kms_addfb_basic: exiting, ret=0
11546 12:16:39.301101 subtest: bad-pitch-1024
11547 12:16:39.301169 [1mSubtest bad-pitch-1024: SUCCESS (0.000s)[0m
11548 12:16:39.301237 Test <8>[ 22.260864] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11549 12:16:39.301306 requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11550 12:16:39.301373 Test requirement: is_i915_device(fd)
11551 12:16:39.301441 Test requirement not met in <14>[ 22.281512] [IGT] kms_addfb_basic: executing
11552 12:16:39.301509 function igt_require_i915, file ../lib/drmtest.c:720:
11553 12:16:39.301577 Test requirement: is_i915_device(fd)
11554 12:16:39.301644 No KMS driver or no<14>[ 22.294771] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11555 12:16:39.301714 outputs, pipes:<14>[ 22.303294] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11556 12:16:39.301781 8, outputs: 0
11557 12:16:39.301848 IGT-Version: 1.27.1-g621c2d3 (aa<14>[ 22.316476] [IGT] kms_addfb_basic: exiting, ret=0
11558 12:16:39.301916 rch64) (Linux: 6.1.72-cip13 aarch64)
11559 12:16:39.301983 Opened device: /dev/dri/card0
11560 12:16:39.302050 Starting su<8>[ 22.327871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11561 12:16:39.302118 btest: bad-pitch-999
11562 12:16:39.302184 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11563 12:16:39.302252 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11564 12:16:39.302320 Test r<14>[ 22.349253] [IGT] kms_addfb_basic: executing
11565 12:16:39.302388 equirement: is_i915_device(fd)
11566 12:16:39.302454 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720<14>[ 22.363355] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11567 12:16:39.302524 :
11568 12:16:39.302591 Test requirem<14>[ 22.371468] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11569 12:16:39.302659 ent: is_i915_device(fd)
11570 12:16:39.302727 No KMS driver or no outputs, pipes: 8, <14>[ 22.384464] [IGT] kms_addfb_basic: exiting, ret=0
11571 12:16:39.302796 outputs: 0
11572 12:16:39.302863 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)<8>[ 22.396916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11573 12:16:39.302932
11574 12:16:39.302999 Opened device: /dev/dri/card0
11575 12:16:39.303066 Starting subtest: bad-pitch-65536
11576 12:16:39.303133 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11577 12:16:39.303201 Test requirement not met in function igt_<14>[ 22.418236] [IGT] kms_addfb_basic: executing
11578 12:16:39.303269 require_i915, file ../lib/drmtest.c:720:
11579 12:16:39.303336 Test requirement: is_i915_device(fd)
11580 12:16:39.303403 Test requirement not met in func<14>[ 22.432251] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11581 12:16:39.303471 tion igt_require<14>[ 22.440743] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11582 12:16:39.303539 _i915, file ../lib/drmtest.c:720:
11583 12:16:39.303607 Test requirem<14>[ 22.453931] [IGT] kms_addfb_basic: exiting, ret=0
11584 12:16:39.303685 ent: is_i915_device(fd)
11585 12:16:39.303791 No KMS driver or no outputs, pipes: 8, outputs: 0
11586 12:16:39.303897 IGT-<8>[ 22.465046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11587 12:16:39.303989 Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11588 12:16:39.304059 Opened device: /dev/dri/card0
11589 12:16:39.304128 Starting subtest: invalid-get-prop-any
11590 12:16:39.304195 [1mSubtest invalid-get<14>[ 22.486587] [IGT] kms_addfb_basic: executing
11591 12:16:39.304262 -prop-any: SUCCESS (0.000s)[0m
11592 12:16:39.304331 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:72<14>[ 22.500878] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11593 12:16:39.304400 0:
11594 12:16:39.304468 Test require<14>[ 22.508946] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11595 12:16:39.304537 ment: is_i915_device(fd)
11596 12:16:39.304603 Test requirement not m<14>[ 22.521668] [IGT] kms_addfb_basic: exiting, ret=0
11597 12:16:39.304671 et in function igt_require_i915, file ../lib/drmtest.c:720:
11598 12:16:39.304739 Test requirement: i<8>[ 22.533029] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11599 12:16:39.304807 s_i915_device(fd)
11600 12:16:39.304881 No KMS driver or no outputs, pipes: 8, outputs: 0
11601 12:16:39.304942 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11602 12:16:39.305003 Opened device: /dev/<14>[ 22.554293] [IGT] kms_addfb_basic: executing
11603 12:16:39.305065 dri/card0
11604 12:16:39.305124 Starting subtest: invalid-get-prop
11605 12:16:39.305184 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
11606 12:16:39.305422 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11608 12:16:39.305627 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11610 12:16:39.305830 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11612 12:16:39.306038 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11614 12:16:39.306242 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11616 12:16:39.306453 Test requirement not met in f<14>[ 22.570434] [IGT] kms_addfb_basic: starting subtest master-rmfb
11617 12:16:39.306525 unction igt_requ<14>[ 22.577328] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11618 12:16:39.306590 ire_i915, file ../lib/drmtest.c:<14>[ 22.587769] [IGT] kms_addfb_basic: exiting, ret=0
11619 12:16:39.306654 720:
11620 12:16:39.306717 Test requirement: is_i915_device(fd)
11621 12:16:39.306780 Test requirement not<8>[ 22.599053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11622 12:16:39.306843 met in function igt_require_i915, file ../lib/drmtest.c:720:
11623 12:16:39.306905 Test requirement: is_i915_device(fd)
11624 12:16:39.306967 No KMS driver or no outputs, pipes: 8, outp<14>[ 22.618483] [IGT] kms_addfb_basic: executing
11625 12:16:39.307030 uts: 0
11626 12:16:39.307089 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11627 12:16:39.307150 Opened device: /dev/dri/card0
11628 12:16:39.307211 Starting subtest: invalid-set-prop-<14>[ 22.635483] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11629 12:16:39.307273 any
11630 12:16:39.307332 [1mSubtest<14>[ 22.643378] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11631 12:16:39.307394 invalid-set-pro<14>[ 22.652964] [IGT] kms_addfb_basic: exiting, ret=0
11632 12:16:39.307454 p-any: SUCCESS (0.000s)[0m
11633 12:16:39.307515 Test requirement not met in functio<8>[ 22.664360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11634 12:16:39.307577 n igt_require_i915, file ../lib/drmtest.c:720:
11635 12:16:39.307638 Test requirement: is_i915_device(fd)
11636 12:16:39.307715 Test requirement not met in function igt_require_i915, fil<14>[ 22.684868] [IGT] kms_addfb_basic: executing
11637 12:16:39.307778 e ../lib/drmtest.c:720:
11638 12:16:39.307839 Test requirement: is_i915_device(fd)
11639 12:16:39.307899 No KMS driver or no outputs, pipes: 8, outputs: 0
11640 12:16:39.307961 IGT-Version: 1.27.1-g621c2d3 (<14>[ 22.702425] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11641 12:16:39.308023 aarch64) (Linux: 6.1.72-cip13 aarch64)
11642 12:16:39.308083 Opened device: /dev/dri/<14>[ 22.715041] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11643 12:16:39.308145 card0
11644 12:16:39.308204 Starting <14>[ 22.723150] [IGT] kms_addfb_basic: exiting, ret=98
11645 12:16:39.308265 subtest: invalid-set-prop
11646 12:16:39.308325 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11647 12:16:39.308385 T<8>[ 22.734919] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11648 12:16:39.308446 est requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11649 12:16:39.308507 Test requirement: is_i915_device(fd)
11650 12:16:39.308567 Test requirement not met in function igt_require_i915, f<14>[ 22.759062] [IGT] kms_addfb_basic: executing
11651 12:16:39.308628 ile ../lib/drmtest.c:720:
11652 12:16:39.308689 Test requirement: is_i915_device(fd)
11653 12:16:39.308750 No KMS driver or no outputs, pipes: 8, outputs: 0
11654 12:16:39.308811 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linu<14>[ 22.776730] [IGT] kms_addfb_basic: exiting, ret=77
11655 12:16:39.308872 x: 6.1.72-cip13 aarch64)
11656 12:16:39.308932 Opened device: /dev/dri/card0
11657 12:16:39.308992 Startin<8>[ 22.788445] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11658 12:16:39.309053 g subtest: master-rmfb
11659 12:16:39.309113 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11660 12:16:39.309173 Test requirement not met in function igt_require_i915, file ../lib/drmtes<14>[ 22.809148] [IGT] kms_addfb_basic: executing
11661 12:16:39.309235 t.c:720:
11662 12:16:39.309294 Test requirement: is_i915_device(fd)
11663 12:16:39.309354 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11664 12:16:39.309415 Test requirement: is_i915_dev<14>[ 22.827061] [IGT] kms_addfb_basic: exiting, ret=77
11665 12:16:39.309476 ice(fd)
11666 12:16:39.309535 No KMS driver or no outputs, pipes: 8, outputs: 0
11667 12:16:39.309595 IGT-Version: 1.27.1-<8>[ 22.840018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11668 12:16:39.309656 g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11669 12:16:39.309715 Opened device: /dev/dri/card0
11670 12:16:39.309775 Starting subtest: addfb25-modifier-no-flag
11671 12:16:39.309835 [1mSubtest addfb25<14>[ 22.860823] [IGT] kms_addfb_basic: executing
11672 12:16:39.309905 -modifier-no-flag: SUCCESS (0.000s)[0m
11673 12:16:39.309961 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11674 12:16:39.310017 Test requirement: is_i915_device(fd)<14>[ 22.878132] [IGT] kms_addfb_basic: exiting, ret=77
11675 12:16:39.310072
11676 12:16:39.310126 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:7<8>[ 22.890176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11677 12:16:39.310183 20:
11678 12:16:39.310260 Test requirement: is_i915_device(fd)
11679 12:16:39.310317 No KMS driver or no outputs, pipes: 8, outputs: 0
11680 12:16:39.310373 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11681 12:16:39.310428 Opened devic<14>[ 22.915183] [IGT] kms_addfb_basic: executing
11682 12:16:39.310484 e: /dev/dri/card0
11683 12:16:39.310539 Starting subtest: addfb25-bad-modifier
11684 12:16:39.310770 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11686 12:16:39.310957 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11688 12:16:39.311143 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11690 12:16:39.311329 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11692 12:16:39.311513 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11694 12:16:39.311706 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11696 12:16:39.311903 (kms_addfb_basic:438) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addf<14>[ 22.932907] [IGT] kms_addfb_basic: exiting, ret=77
11697 12:16:39.311967 b_basic.c:662:
11698 12:16:39.312026 (kms_addfb_basic:438) CRITICAL: Failed assertion<8>[ 22.944578] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11699 12:16:39.312085 : igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11700 12:16:39.312144 (kms_addfb_basic:4<14>[ 22.967674] [IGT] kms_addfb_basic: executing
11701 12:16:39.312200 38) CRITICAL: error: 0 != -1
11702 12:16:39.312257 Stack trace:
11703 12:16:39.312313 #0 ../lib/igt_core.c:1971 __igt_fail_assert()
11704 12:16:39.312368 #1 [<unknown>+0xde8e47e0]
11705 12:16:39.312423 #2 [<unknown>+0xde8e6278]
11706 12:16:39.312478 #3 [<un<14>[ 22.985223] [IGT] kms_addfb_basic: exiting, ret=77
11707 12:16:39.312533 known>+0xde8e167c]
11708 12:16:39.312587 #4 [__libc_start_main+0xe8]
11709 12:16:39.312642 #5 [<unknow<8>[ 22.997077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11710 12:16:39.312697 n>+0xde8e16b4]
11711 12:16:39.312752 #6 [<unknown>+0xde8e16b4]
11712 12:16:39.312806 Subtest addfb25-bad-modifier failed.
11713 12:16:39.312860 **** DEBUG ****
11714 12:16:39.312915 (kms_addfb_basic:438) ioctl_wrappers-DEBUG: <14>[ 23.017071] [IGT] kms_addfb_basic: executing
11715 12:16:39.312970 Test requirement passed: igt_has_fb_modifiers(fd)
11716 12:16:39.313026 (kms_addfb_basic:438) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/<14>[ 23.035118] [IGT] kms_addfb_basic: exiting, ret=77
11717 12:16:39.313081 kms_addfb_basic.c:662:
11718 12:16:39.313136 (kms_addfb_basic:438) CRITICAL: Failed assertion: igt_io<8>[ 23.045819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11719 12:16:39.313193 ctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11720 12:16:39.313249 (kms_addfb_basic:438) CRITICAL: error: 0 !<14>[ 23.070365] [IGT] kms_addfb_basic: executing
11721 12:16:39.313304 = -1
11722 12:16:39.313358 (kms_addfb_basic:438) igt_core-INFO: Stack trace:
11723 12:16:39.313413 (kms_addfb_basic:438) igt_core-INFO: #0 ../lib/igt_core.c:1971 __igt_fail_assert()
11724 12:16:39.313468 (kms_addfb_basic:<14>[ 23.088735] [IGT] kms_addfb_basic: exiting, ret=77
11725 12:16:39.313524 438) igt_core-INFO: #1 [<unknown>+0xde8e47e0]
11726 12:16:39.313579 (kms_addfb_basi<8>[ 23.100547] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11727 12:16:39.313634 c:438) igt_core-INFO: #2 [<unknown>+0xde8e6278]
11728 12:16:39.313689 (kms_addfb_basic:438) igt_core-INFO: #3 [<unknown>+0xde8e167c]
11729 12:16:39.313744 (kms_addfb_basic:438) igt_core-INFO: #4 [<14>[ 23.121222] [IGT] kms_addfb_basic: executing
11730 12:16:39.313798 __libc_start_main+0xe8]
11731 12:16:39.313852 (kms_addfb_basic:438) igt_core-INFO: #5 [<unknown>+0xde8e16b4]
11732 12:16:39.313907 (kms_addfb_basic:438) igt_core-INFO: #6 [<unknown>+<14>[ 23.139551] [IGT] kms_addfb_basic: exiting, ret=77
11733 12:16:39.313962 0xde8e16b4]
11734 12:16:39.314018 **** END ****
11735 12:16:39.314073 [1mSubtest addfb25-bad-modifier: FAIL (0.005s)[0<8>[ 23.150329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11736 12:16:39.314128 m
11737 12:16:39.314183 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11738 12:16:39.314238 Test requirement: is_i915_device(fd)
11739 12:16:39.314292 Test requirement not met in function igt_require_i91<14>[ 23.172804] [IGT] kms_addfb_basic: executing
11740 12:16:39.314348 5, file ../lib/drmtest.c:720:
11741 12:16:39.314403 Test requirement: is_i915_device(fd)
11742 12:16:39.314457 No KMS driver or no outputs, pipes: 8, outputs: 0
11743 12:16:39.314513 IGT-Version: 1.27.1-g621c2d3 (aarch64) (<14>[ 23.190951] [IGT] kms_addfb_basic: exiting, ret=77
11744 12:16:39.314568 Linux: 6.1.72-cip13 aarch64)
11745 12:16:39.314622 Opened device: /dev/dri/card0
11746 12:16:39.314676 Tes<8>[ 23.202807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11747 12:16:39.314731 t requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11748 12:16:39.314786 Test requirement: is_i915_device(fd)
11749 12:16:39.314840 [1mSubtest addfb25-x-tile<14>[ 23.221447] [IGT] kms_addfb_basic: executing
11750 12:16:39.314905 d-mismatch-legacy: SKIP (0.000s)[0m
11751 12:16:39.314958 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11752 12:16:39.315012 Test requirement: is_i915_device(fd)
11753 12:16:39.315065 N<14>[ 23.239406] [IGT] kms_addfb_basic: exiting, ret=77
11754 12:16:39.315119 o KMS driver or no outputs, pipes: 8, outputs: 0
11755 12:16:39.315173 IGT-Version: 1.27.1-g621c2d3 (<8>[ 23.252271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11756 12:16:39.315226 aarch64) (Linux: 6.1.72-cip13 aarch64)
11757 12:16:39.315280 Opened device: /dev/dri/card0
11758 12:16:39.315333 Test requirement not met in function igt_require_i915, file ../lib/drmtes<14>[ 23.271982] [IGT] kms_addfb_basic: executing
11759 12:16:39.315387 t.c:720:
11760 12:16:39.315440 Test requirement: is_i915_device(fd)
11761 12:16:39.315675 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11763 12:16:39.315866 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11765 12:16:39.316048 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11767 12:16:39.316231 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11769 12:16:39.316415 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11771 12:16:39.316597 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11773 12:16:39.316786 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11775 12:16:39.316984 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11776 12:16:39.317048 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11777 12:16:39.317108 Test requirement: is_i915_device(fd)
11778 12:16:39.317165 No KMS driver or no outputs, pipes: 8, outputs: 0
11779 12:16:39.317221 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11780 12:16:39.317277 Opened device: /dev/dri/card0
11781 12:16:39.317332 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11782 12:16:39.317386 Test requirement: is_i915_device(fd)
11783 12:16:39.317440 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11784 12:16:39.317494 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11785 12:16:39.317549 Test requirement: is_i915_device(fd)
11786 12:16:39.317604 No KMS driver or no outputs, pipes: 8, outputs: 0
11787 12:16:39.317658 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11788 12:16:39.317712 Opened device: /dev/dri/card0
11789 12:16:39.317767 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11790 12:16:39.317822 Test requirement: is_i915_device(fd)
11791 12:16:39.317875 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11792 12:16:39.317929 Test requirement: is_i915_device(fd)
11793 12:16:39.317983 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11794 12:16:39.318037 No KMS driver or no outputs, pipes: 8, outputs: 0
11795 12:16:39.318091 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11796 12:16:39.318144 Opened device: /dev/dri/card0
11797 12:16:39.318197 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11798 12:16:39.318251 Test requirement: is_i915_device(fd)
11799 12:16:39.318304 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11800 12:16:39.318358 Test requirement: is_i915_device(fd)
11801 12:16:39.318411 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11802 12:16:39.318465 No KMS driver or no outputs, pipes: 8, outputs: 0
11803 12:16:39.318520 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11804 12:16:39.318573 Opened device: /dev/dri/card0
11805 12:16:39.318627 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11806 12:16:39.318682 Test requirement: is_i915_device(fd)
11807 12:16:39.318735 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11808 12:16:39.318789 Test requirement: is_i915_device(fd)
11809 12:16:39.318843 [1mSubtest tile-pitch-mismatch: SKIP (0.000s)[0m
11810 12:16:39.318914 No KMS driver or no outputs, pipes: 8, outputs: 0
11811 12:16:39.318972 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11812 12:16:39.319026 Opened device: /dev/dri/card0
11813 12:16:39.319080 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11814 12:16:39.319134 Test requirement: is_i915_device(fd)
11815 12:16:39.319187 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11816 12:16:39.319241 Test requirement: is_i915_device(fd)
11817 12:16:39.319295 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11818 12:16:39.319349 No KMS driver or no outputs, pipes: 8, outputs: 0
11819 12:16:39.319402 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11820 12:16:39.319456 Opened device: /dev/dri/card0
11821 12:16:39.319510 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11822 12:16:39.319565 Test requirement: is_i915_device(fd)
11823 12:16:39.319618 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11824 12:16:39.319679 Test requirement: is_i915_device(fd)
11825 12:16:39.319773 No KMS driver or no outputs, pipes: 8, outputs: 0
11826 12:16:39.319827 [1mSubtest size-max: SKIP (0.000s)[0m
11827 12:16:39.319881 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11828 12:16:39.319934 Opened device: /dev/dri/card0
11829 12:16:39.319988 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11830 12:16:39.320042 Test requirement: is_i915_device(fd)
11831 12:16:39.320095 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11832 12:16:39.320149 Test requirement: is_i915_device(fd)
11833 12:16:39.320203 No KMS driver or no outputs, pipes: 8, outputs: 0
11834 12:16:39.320257 [1mSubtest too-wide: SKIP (0.000s)[0m
11835 12:16:39.320310 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11836 12:16:39.320363 Opened device: /dev/dri/card0
11837 12:16:39.320416 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11838 12:16:39.320470 Test requirement: is_i915_device(fd)
11839 12:16:39.320522 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11840 12:16:39.320576 Test requirement: is_i915_device(fd)
11841 12:16:39.320628 No KMS driver or no outputs, pipes: 8, outputs: 0
11842 12:16:39.320682 [1mSubtest too-high: SKIP (0.000s)[0m
11843 12:16:39.320734 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11844 12:16:39.320787 Opened device: /dev/dri/card0
11845 12:16:39.320840 Test requirement not met in function igt_require_i915, file ../lib/<14>[ 23.622778] [IGT] kms_addfb_basic: exiting, ret=77
11846 12:16:39.320894 drmtest.c:720:
11847 12:16:39.320947 Test requirement: is_i915_device(fd)
11848 12:16:39.321185 Test requirement not met i<8>[ 23.635941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11849 12:16:39.321245 n function igt_require_i915, file ../lib/drmtest.c:720:
11850 12:16:39.321299 Test requirement: is_i915_device(fd)
11851 12:16:39.321353 No KMS driver or no outputs, pipes: 8, outputs: 0<14>[ 23.654928] [IGT] kms_addfb_basic: executing
11852 12:16:39.321408
11853 12:16:39.321461 [1mSubtest bo-too-small: SKIP (0.000s)[0m
11854 12:16:39.321514 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11855 12:16:39.321567 Opened device: /dev/dri/car<14>[ 23.672594] [IGT] kms_addfb_basic: exiting, ret=77
11856 12:16:39.321621 d0
11857 12:16:39.321673 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c<8>[ 23.683482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11858 12:16:39.321727 :720:
11859 12:16:39.321780 Test requirement: is_i915_device(fd)
11860 12:16:39.321833 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11861 12:16:39.321886 Test requirement<14>[ 23.703636] [IGT] kms_addfb_basic: executing
11862 12:16:39.321939 : is_i915_device(fd)
11863 12:16:39.321991 No KMS driver or no outputs, pipes: 8, outputs: 0
11864 12:16:39.322045 [1mSubtest small-bo: SKIP (0.000s)[0m
11865 12:16:39.322098 IGT-Version: 1.27.1-g621c2d3 (<14>[ 23.721164] [IGT] kms_addfb_basic: exiting, ret=77
11866 12:16:39.322150 aarch64) (Linux: 6.1.72-cip13 aarch64)
11867 12:16:39.322205 Opened device: /dev/dri/<8>[ 23.731825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11868 12:16:39.322259 card0
11869 12:16:39.322312 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11870 12:16:39.322365 Test requirement: is_i915_device(fd)
11871 12:16:39.322419 Test requirement<14>[ 23.752336] [IGT] kms_addfb_basic: executing
11872 12:16:39.322473 not met in function igt_require_i915, file ../lib/drmtest.c:720:
11873 12:16:39.322526 Test requirement: is_i915_device(fd)
11874 12:16:39.322579 No KMS driver or no outputs, pipes: 8, outputs: 0
11875 12:16:39.322633 [1m<14>[ 23.769883] [IGT] kms_addfb_basic: exiting, ret=77
11876 12:16:39.322686 Subtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11877 12:16:39.322739 IGT-Versi<8>[ 23.781862] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11878 12:16:39.322792 on: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11879 12:16:39.322846 Opened device: /dev/dri/card0
11880 12:16:39.322899 Test requirement not met in function igt_require_i91<14>[ 23.801464] [IGT] kms_addfb_basic: executing
11881 12:16:39.322953 5, file ../lib/drmtest.c:720:
11882 12:16:39.323006 Test requirement: is_i915_device(fd)
11883 12:16:39.323059 Test requirement not met in function igt_require_i915, file ../lib/drmtest.<14>[ 23.819341] [IGT] kms_addfb_basic: exiting, ret=77
11884 12:16:39.323113 c:720:
11885 12:16:39.323166 Test requirement: is_i915_device(fd)
11886 12:16:39.323219 No KMS driver or no outputs, pipes<8>[ 23.830414] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11887 12:16:39.323274 : 8, outputs: 0
11888 12:16:39.323326 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.000s)[0m
11889 12:16:39.323379 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11890 12:16:39.323432 Op<14>[ 23.851981] [IGT] kms_addfb_basic: executing
11891 12:16:39.323485 ened device: /dev/dri/card0
11892 12:16:39.323538 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11893 12:16:39.323592 Test requirement: is_i915_device(fd)
11894 12:16:39.323667 Test requi<14>[ 23.869335] [IGT] kms_addfb_basic: exiting, ret=77
11895 12:16:39.323736 rement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11896 12:16:39.323791 Test re<8>[ 23.881447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11897 12:16:39.323845 quirement: is_i915_device(fd)
11898 12:16:39.323899 No KMS driver or no outputs, pipes: 8, outputs: 0
11899 12:16:39.323953 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11900 12:16:39.324007 IGT-Version: 1.27.1-g621c2d3 (aarch64)<14>[ 23.906042] [IGT] kms_addfb_basic: executing
11901 12:16:39.324060 (Linux: 6.1.72-cip13 aarch64)
11902 12:16:39.324113 Opened device: /dev/dri/card0
11903 12:16:39.324166 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11904 12:16:39.324219 Test requireme<14>[ 23.923669] [IGT] kms_addfb_basic: exiting, ret=77
11905 12:16:39.324273 nt: is_i915_device(fd)
11906 12:16:39.324327 Test requirement not met in function igt<8>[ 23.935711] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11907 12:16:39.324381 _require_i915, f<8>[ 23.944190] <LAVA_SIGNAL_TESTSET STOP>
11908 12:16:39.324435 ile ../lib/drmtest.c:720:
11909 12:16:39.324488 Test requirement: is_i915_device(fd)
11910 12:16:39.324541 No KMS driver or no outputs, pipes: 8, outputs: 0
11911 12:16:39.324595 [1mSubtest addfb25-y-tiled-small-legacy: SKIP (0.000s)[0m
11912 12:16:39.324652 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11913 12:16:39.324705 Opened device: /dev/dri/card0
11914 12:16:39.324758 Test requirement not met i<8>[ 23.973762] <LAVA_SIGNAL_TESTSET START kms_atomic>
11915 12:16:39.324812 n function igt_require_i915, file ../lib/drmtest.c:720:
11916 12:16:39.324865 Test requirement: is_i915_device(fd)
11917 12:16:39.324918 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11918 12:16:39.325155 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11920 12:16:39.325337 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11922 12:16:39.325518 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11924 12:16:39.325701 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11926 12:16:39.325881 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11928 12:16:39.326063 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11930 12:16:39.326242 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11932 12:16:39.326421 Received signal: <TESTSET> STOP
11933 12:16:39.326483 Closing test_set kms_addfb_basic
11934 12:16:39.326563 Received signal: <TESTSET> START kms_atomic
11935 12:16:39.326623 Starting test_set kms_atomic
11936 12:16:39.326712 Test requirement: is_i915_device(fd)
11937 12:16:39.326773 No KMS driver or no outputs, pipes: 8, o<14>[ 24.001026] [IGT] kms_atomic: executing
11938 12:16:39.326831 utputs: 0
11939 12:16:39.326886 [1mS<14>[ 24.007026] [IGT] kms_atomic: exiting, ret=77
11940 12:16:39.326941 ubtest addfb25-4-tiled: SKIP (0.000s)[0m
11941 12:16:39.326995 IGT-Version: 1.27.1-g621c2d3 (aarch64<8>[ 24.018358] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11942 12:16:39.327051 ) (Linux: 6.1.72-cip13 aarch64)
11943 12:16:39.327104 Opened device: /dev/dri/card0
11944 12:16:39.327159 No KMS driver or no outputs, pipes: 8, outputs: 0
11945 12:16:39.327213 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
11946 12:16:39.327266 <14>[ 24.050325] [IGT] kms_atomic: executing
11947 12:16:39.327321 IGT-Version: 1.2<14>[ 24.055210] [IGT] kms_atomic: exiting, ret=77
11948 12:16:39.327374 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11949 12:16:39.327430 Opened device: /dev/dri/ca<8>[ 24.066462] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11950 12:16:39.327485 rd0
11951 12:16:39.327537 No KMS driver or no outputs, pipes: 8, outputs: 0
11952 12:16:39.327591 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
11953 12:16:39.327645 <14>[ 24.098662] [IGT] kms_atomic: executing
11954 12:16:39.327754 IGT-Version: 1.2<14>[ 24.103541] [IGT] kms_atomic: exiting, ret=77
11955 12:16:39.327811 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11956 12:16:39.327866 Opened dev<8>[ 24.114669] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11957 12:16:39.327923 ice: /dev/dri/card0
11958 12:16:39.327977 No KMS driver or no outputs, pipes: 8, outputs: 0
11959 12:16:39.328032 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
11960 12:16:39.328085 <14>[ 24.139000] [IGT] kms_atomic: executing
11961 12:16:39.328139 IGT-Version: 1.2<14>[ 24.143585] [IGT] kms_atomic: exiting, ret=77
11962 12:16:39.328192 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11963 12:16:39.328247 Opened dev<8>[ 24.154879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11964 12:16:39.328301 ice: /dev/dri/card0
11965 12:16:39.328353 No KMS driver or no outputs, pipes: 8, outputs: 0
11966 12:16:39.328407 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
11967 12:16:39.328460 <14>[ 24.177402] [IGT] kms_atomic: executing
11968 12:16:39.328514 IGT-Version: 1.2<14>[ 24.182176] [IGT] kms_atomic: exiting, ret=77
11969 12:16:39.328567 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11970 12:16:39.328622 Opened dev<8>[ 24.193476] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11971 12:16:39.328676 ice: /dev/dri/card0
11972 12:16:39.328729 No KMS driver or no outputs, pipes: 8, outputs: 0
11973 12:16:39.328783 [1mSubtest test-only: SKIP (0.000s)[0m
11974 12:16:39.328836 <14>[ 24.215425] [IGT] kms_atomic: executing
11975 12:16:39.328890 IGT-Version: 1.2<14>[ 24.220039] [IGT] kms_atomic: exiting, ret=77
11976 12:16:39.328943 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11977 12:16:39.328997 Opened dev<8>[ 24.231340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11978 12:16:39.329051 ice: /dev/dri/card0
11979 12:16:39.329103 No KMS driver or no outputs, pipes: 8, outputs: 0
11980 12:16:39.329157 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
11981 12:16:39.329210 <14>[ 24.251018] [IGT] kms_atomic: executing
11982 12:16:39.329263 IGT-Version: 1.2<14>[ 24.255638] [IGT] kms_atomic: exiting, ret=77
11983 12:16:39.329317 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11984 12:16:39.329372 Opened device: /dev/dri/ca<8>[ 24.267419] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11985 12:16:39.329426 rd0
11986 12:16:39.329479 No KMS driver or no outputs, pipes: 8, outputs: 0
11987 12:16:39.329532 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
11988 12:16:39.329586 <14>[ 24.288673] [IGT] kms_atomic: executing
11989 12:16:39.329640 IGT-Version: 1.2<14>[ 24.293476] [IGT] kms_atomic: exiting, ret=77
11990 12:16:39.329694 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11991 12:16:39.329749 Opened device: /dev/dri/ca<8>[ 24.305124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11992 12:16:39.329804 rd0
11993 12:16:39.329857 No KMS driver or no outputs, pipes: 8, outputs: 0
11994 12:16:39.329911 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
11995 12:16:39.329964 <14>[ 24.326544] [IGT] kms_atomic: executing
11996 12:16:39.330017 IGT-Version: 1.2<14>[ 24.331140] [IGT] kms_atomic: exiting, ret=77
11997 12:16:39.330070 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
11998 12:16:39.330125 Opened device: /dev/dri/ca<8>[ 24.343179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
11999 12:16:39.330179 rd0
12000 12:16:39.330232 No KMS driver or no outputs, pipes: 8, outputs: 0
12001 12:16:39.330285 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
12002 12:16:39.330339 <14>[ 24.363971] [IGT] kms_atomic: executing
12003 12:16:39.330392 IGT-Version: 1.2<14>[ 24.368597] [IGT] kms_atomic: exiting, ret=77
12004 12:16:39.330446 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12005 12:16:39.330501 Opened device: /dev/dri/ca<8>[ 24.379933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
12006 12:16:39.330555 rd0
12007 12:16:39.330607 No KMS driver or no outputs, pipes: 8, outputs: 0
12008 12:16:39.330661 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
12009 12:16:39.330891 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
12011 12:16:39.331075 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
12013 12:16:39.331257 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
12015 12:16:39.331437 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
12017 12:16:39.331621 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
12019 12:16:39.331851 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
12021 12:16:39.332034 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
12023 12:16:39.332213 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
12025 12:16:39.332392 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
12027 12:16:39.332569 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
12029 12:16:39.332772 <14>[ 24.401658] [IGT] kms_atomic: executing
12030 12:16:39.332837 IGT-Version: 1.2<14>[ 24.406284] [IGT] kms_atomic: exiting, ret=77
12031 12:16:39.332897 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12032 12:16:39.332955 Opened device: /dev/dri/ca<8>[ 24.418240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
12033 12:16:39.333013 rd0
12034 12:16:39.333068 No KMS driver or no outputs, pipes: 8, outputs: 0
12035 12:16:39.333123 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
12036 12:16:39.333178 <14>[ 24.441477] [IGT] kms_atomic: executing
12037 12:16:39.333232 IGT-Version: 1.2<14>[ 24.446081] [IGT] kms_atomic: exiting, ret=77
12038 12:16:39.333287 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12039 12:16:39.333341 Opened dev<8>[ 24.457427] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic_plane_damage RESULT=skip>
12040 12:16:39.333396 ice: /dev/dri/card0
12041 12:16:39.333450 No KMS driv<8>[ 24.466627] <LAVA_SIGNAL_TESTSET STOP>
12042 12:16:39.333505 er or no outputs, pipes: 8, outputs: 0
12043 12:16:39.333559 [1mSubtest atomic_plane_damage: SKIP (0.000s)[0m
12044 12:16:39.333614 <8>[ 24.497227] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12045 12:16:39.333668 <14>[ 24.531027] [IGT] kms_flip_event_leak: executing
12046 12:16:39.333722 IGT-Version: 1.2<14>[ 24.536650] [IGT] kms_flip_event_leak: exiting, ret=77
12047 12:16:39.333775 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12048 12:16:39.333830 Opened device: /dev/dri/card0
12049 12:16:39.333883 No KMS driv<8>[ 24.550422] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12050 12:16:39.333938 er or no outputs, pipes: 8, outp<8>[ 24.559699] <LAVA_SIGNAL_TESTSET STOP>
12051 12:16:39.333991 uts: 0
12052 12:16:39.334044 [1mSubtest basic: SKIP (0.000s)[0m
12053 12:16:39.334098 <8>[ 24.590837] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12054 12:16:39.334152 <14>[ 24.622964] [IGT] kms_prop_blob: executing
12055 12:16:39.334205 IGT-Version: 1.2<14>[ 24.627966] [IGT] kms_prop_blob: starting subtest basic
12056 12:16:39.334259 7.1-g621c2d3 (aa<14>[ 24.634814] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12057 12:16:39.334313 rch64) (Linux: 6<14>[ 24.642547] [IGT] kms_prop_blob: exiting, ret=0
12058 12:16:39.334367 .1.72-cip13 aarch64)
12059 12:16:39.334420 Opened device: /dev/dri/card0
12060 12:16:39.334474 Starting subtest: basic
12061 12:16:39.334527 [<8>[ 24.654724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12062 12:16:39.334580 1mSubtest basic: SUCCESS (0.000s)[0m
12063 12:16:39.334634 <14>[ 24.676810] [IGT] kms_prop_blob: executing
12064 12:16:39.334688 IGT-Version: 1.2<14>[ 24.681560] [IGT] kms_prop_blob: starting subtest blob-prop-core
12065 12:16:39.334741 7.1-g621c2d3 (aa<14>[ 24.689236] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12066 12:16:39.334796 rch64) (Linux: 6<14>[ 24.697781] [IGT] kms_prop_blob: exiting, ret=0
12067 12:16:39.334849 .1.72-cip13 aarch64)
12068 12:16:39.334903 Opened device: /dev/dri/card0
12069 12:16:39.334956 Starting su<8>[ 24.709329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12070 12:16:39.335010 btest: blob-prop-core
12071 12:16:39.335062 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
12072 12:16:39.335115 <14>[ 24.728983] [IGT] kms_prop_blob: executing
12073 12:16:39.335168 IGT-Version: 1.2<14>[ 24.733760] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12074 12:16:39.335222 7.1-g621c2d3 (aa<14>[ 24.741830] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12075 12:16:39.335277 rch64) (Linux: 6<14>[ 24.750742] [IGT] kms_prop_blob: exiting, ret=0
12076 12:16:39.335331 .1.72-cip13 aarch64)
12077 12:16:39.335384 Opened device: /dev/dri/card0
12078 12:16:39.335437 Starting su<8>[ 24.762061] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12079 12:16:39.335491 btest: blob-prop-validate
12080 12:16:39.335544 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12081 12:16:39.335597 <14>[ 24.782605] [IGT] kms_prop_blob: executing
12082 12:16:39.335650 IGT-Version: 1.2<14>[ 24.787362] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12083 12:16:39.335737 7.1-g621c2d3 (aa<14>[ 24.795374] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12084 12:16:39.335807 rch64) (Linux: 6<14>[ 24.804214] [IGT] kms_prop_blob: exiting, ret=0
12085 12:16:39.335861 .1.72-cip13 aarch64)
12086 12:16:39.335914 Opened device: /dev/dri/card0
12087 12:16:39.335968 Starting su<8>[ 24.815461] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12088 12:16:39.336022 btest: blob-prop-lifetime
12089 12:16:39.336075 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12090 12:16:39.336128 <14>[ 24.835601] [IGT] kms_prop_blob: executing
12091 12:16:39.336181 IGT-Version: 1.2<14>[ 24.840342] [IGT] kms_prop_blob: starting subtest blob-multiple
12092 12:16:39.336235 7.1-g621c2d3 (aa<14>[ 24.847965] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12093 12:16:39.336290 rch64) (Linux: 6<14>[ 24.856348] [IGT] kms_prop_blob: exiting, ret=0
12094 12:16:39.336343 .1.72-cip13 aarch64)
12095 12:16:39.336396 Opened device: /dev/dri/card0
12096 12:16:39.336450 Starting su<8>[ 24.867647] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12097 12:16:39.336503 btest: blob-multiple
12098 12:16:39.336555 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12099 12:16:39.336609 <14>[ 24.887577] [IGT] kms_prop_blob: executing
12100 12:16:39.336837 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
12102 12:16:39.337017 Received signal: <TESTCASE> TEST_CASE_ID=atomic_plane_damage RESULT=skip
12104 12:16:39.337196 Received signal: <TESTSET> STOP
12105 12:16:39.337259 Closing test_set kms_atomic
12106 12:16:39.337341 Received signal: <TESTSET> START kms_flip_event_leak
12107 12:16:39.337401 Starting test_set kms_flip_event_leak
12108 12:16:39.337481 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12110 12:16:39.337660 Received signal: <TESTSET> STOP
12111 12:16:39.337721 Closing test_set kms_flip_event_leak
12112 12:16:39.337801 Received signal: <TESTSET> START kms_prop_blob
12113 12:16:39.337861 Starting test_set kms_prop_blob
12114 12:16:39.337941 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12116 12:16:39.338119 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12118 12:16:39.338298 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12120 12:16:39.338476 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12122 12:16:39.338655 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12124 12:16:39.338842 IGT-Version: 1.2<14>[ 24.892361] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12125 12:16:39.338905 7.1-g621c2d3 (aa<14>[ 24.900478] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12126 12:16:39.338965 rch64) (Linux: 6<14>[ 24.909578] [IGT] kms_prop_blob: exiting, ret=0
12127 12:16:39.339022 .1.72-cip13 aarch64)
12128 12:16:39.339078 Opened device: /dev/dri/card0
12129 12:16:39.339133 Starting su<8>[ 24.921214] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12130 12:16:39.339188 btest: invalid-get-prop-any
12131 12:16:39.339242 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12132 12:16:39.339296 <14>[ 24.941007] [IGT] kms_prop_blob: executing
12133 12:16:39.339350 IGT-Version: 1.2<14>[ 24.945890] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12134 12:16:39.339406 7.1-g621c2d3 (aa<14>[ 24.953759] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12135 12:16:39.339462 rch64) (Linux: 6<14>[ 24.962391] [IGT] kms_prop_blob: exiting, ret=0
12136 12:16:39.339516 .1.72-cip13 aarch64)
12137 12:16:39.339570 Opened device: /dev/dri/card0
12138 12:16:39.339624 Starting su<8>[ 24.973629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12139 12:16:39.339688 btest: invalid-get-prop
12140 12:16:39.339782 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12141 12:16:39.339836 <14>[ 24.996266] [IGT] kms_prop_blob: executing
12142 12:16:39.339890 IGT-Version: 1.2<14>[ 25.001096] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12143 12:16:39.339944 7.1-g621c2d3 (aa<14>[ 25.009167] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12144 12:16:39.340000 rch64) (Linux: 6<14>[ 25.018323] [IGT] kms_prop_blob: exiting, ret=0
12145 12:16:39.340054 .1.72-cip13 aarch64)
12146 12:16:39.340107 Opened device: /dev/dri/card0
12147 12:16:39.340162 Starting su<8>[ 25.029604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12148 12:16:39.340215 btest: invalid-set-prop-any
12149 12:16:39.340269 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12150 12:16:39.340322 <14>[ 25.052215] [IGT] kms_prop_blob: executing
12151 12:16:39.340376 IGT-Version: 1.2<14>[ 25.057017] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12152 12:16:39.340430 7.1-g621c2d3 (aa<14>[ 25.064782] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12153 12:16:39.340485 rch64) (Linux: 6<14>[ 25.073653] [IGT] kms_prop_blob: exiting, ret=0
12154 12:16:39.340538 .1.72-cip13 aarch64)
12155 12:16:39.340591 Opened device: /dev/dri/card0
12156 12:16:39.340644 Starting su<8>[ 25.084726] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12157 12:16:39.340752 btest: invalid-set-prop
12158 12:16:39.340831 [1mSub<8>[ 25.094141] <LAVA_SIGNAL_TESTSET STOP>
12159 12:16:39.340899 test invalid-set-prop: SUCCESS (0.000s)[0m
12160 12:16:39.340954 <8>[ 25.115435] <LAVA_SIGNAL_TESTSET START kms_setmode>
12161 12:16:39.341008 <14>[ 25.133023] [IGT] kms_setmode: executing
12162 12:16:39.341062 IGT-Version: 1.2<14>[ 25.137687] [IGT] kms_setmode: starting subtest basic
12163 12:16:39.341116 7.1-g621c2d3 (aa<14>[ 25.144320] [IGT] kms_setmode: finished subtest basic, SKIP
12164 12:16:39.341172 rch64) (Linux: 6<14>[ 25.151697] [IGT] kms_setmode: exiting, ret=77
12165 12:16:39.341227 .1.72-cip13 aarch64)
12166 12:16:39.341281 Opened device: /dev/dri/card0
12167 12:16:39.341335 Starting su<8>[ 25.162677] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12168 12:16:39.341389 btest: basic
12169 12:16:39.341442 No dynamic tests executed.
12170 12:16:39.341495 [1mSubtest basic: SKIP (0.000s)[0m
12171 12:16:39.341548 <14>[ 25.181790] [IGT] kms_setmode: executing
12172 12:16:39.341602 IGT-Version: 1.2<14>[ 25.186411] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12173 12:16:39.341655 7.1-g621c2d3 (aa<14>[ 25.194615] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12174 12:16:39.341710 rch64) (Linux: 6<14>[ 25.203520] [IGT] kms_setmode: exiting, ret=77
12175 12:16:39.341763 .1.72-cip13 aarch64)
12176 12:16:39.341816 Opened device: /dev/dri/card0
12177 12:16:39.341870 Starting su<8>[ 25.214886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12178 12:16:39.341923 btest: basic-clone-single-crtc
12179 12:16:39.341975 No dynamic tests executed.
12180 12:16:39.342028 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12181 12:16:39.342081 <14>[ 25.235493] [IGT] kms_setmode: executing
12182 12:16:39.342134 IGT-Version: 1.2<14>[ 25.240190] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12183 12:16:39.342188 7.1-g621c2d3 (aa<14>[ 25.248613] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12184 12:16:39.342243 rch64) (Linux: 6<14>[ 25.257714] [IGT] kms_setmode: exiting, ret=77
12185 12:16:39.342296 .1.72-cip13 aarch64)
12186 12:16:39.342350 Opened device: /dev/dri/card0
12187 12:16:39.342403 Starting su<8>[ 25.268846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12188 12:16:39.342456 btest: invalid-clone-single-crtc
12189 12:16:39.342509 No dynamic tests executed.
12190 12:16:39.342562 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12191 12:16:39.342615 <14>[ 25.289634] [IGT] kms_setmode: executing
12192 12:16:39.342669 IGT-Version: 1.2<14>[ 25.294240] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12193 12:16:39.342899 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12195 12:16:39.343081 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12197 12:16:39.343264 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12199 12:16:39.343447 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12201 12:16:39.343627 Received signal: <TESTSET> STOP
12202 12:16:39.343723 Closing test_set kms_prop_blob
12203 12:16:39.343821 Received signal: <TESTSET> START kms_setmode
12204 12:16:39.343882 Starting test_set kms_setmode
12205 12:16:39.343963 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12207 12:16:39.344142 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12209 12:16:39.344322 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12211 12:16:39.344511 7.1-g621c2d3 (aa<14>[ 25.302880] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12212 12:16:39.344577 rch64) (Linux: 6<14>[ 25.312219] [IGT] kms_setmode: exiting, ret=77
12213 12:16:39.344636 .1.72-cip13 aarch64)
12214 12:16:39.344694 Opened device: /dev/dri/card0
12215 12:16:39.344750 Starting su<8>[ 25.323647] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12216 12:16:39.344806 btest: invalid-clone-exclusive-crtc
12217 12:16:39.344859 No dynamic tests executed.
12218 12:16:39.344914 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12219 12:16:39.344968 <14>[ 25.344520] [IGT] kms_setmode: executing
12220 12:16:39.345022 IGT-Version: 1.2<14>[ 25.349376] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12221 12:16:39.345076 <14>[ 25.357346] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12222 12:16:39.345130 7.1-g621c2d3 (aa<14>[ 25.364623] [IGT] kms_setmode: exiting, ret=77
12223 12:16:39.345186 rch64) (Linux: 6.1.72-cip13 aarch64)
12224 12:16:39.345240 Opened device: /dev/dri/ca<8>[ 25.375477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12225 12:16:39.345295 rd0
12226 12:16:39.345347 Starting subtest: clone-exclusive-crtc
12227 12:16:39.345400 No dynamic tests executed.
12228 12:16:39.345454 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12229 12:16:39.345506 <14>[ 25.396121] [IGT] kms_setmode: executing
12230 12:16:39.345560 IGT-Version: 1.2<14>[ 25.400737] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12231 12:16:39.345613 7.1-g621c2d3 (aa<14>[ 25.409890] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12232 12:16:39.345669 rch64) (Linux: 6<14>[ 25.419738] [IGT] kms_setmode: exiting, ret=77
12233 12:16:39.345722 .1.72-cip13 aarch64)
12234 12:16:39.345775 Opened device: /dev/dri/card0
12235 12:16:39.345829 Starting su<8>[ 25.430128] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12236 12:16:39.345883 btest: invalid-c<8>[ 25.441707] <LAVA_SIGNAL_TESTSET STOP>
12237 12:16:39.345935 lone-single-crtc-stealing
12238 12:16:39.345988 No dynamic tests executed.
12239 12:16:39.346041 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12240 12:16:39.346094 <8>[ 25.460966] <LAVA_SIGNAL_TESTSET START kms_vblank>
12241 12:16:39.346146 <14>[ 25.481211] [IGT] kms_vblank: executing
12242 12:16:39.346200 IGT-Version: 1.2<14>[ 25.485902] [IGT] kms_vblank: exiting, ret=77
12243 12:16:39.346253 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12244 12:16:39.346307 Opened dev<8>[ 25.496824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12245 12:16:39.346361 ice: /dev/dri/card0
12246 12:16:39.346413 No KMS driver or no outputs, pipes: 8, outputs: 0
12247 12:16:39.346467 [1mSubtest invalid: SKIP (0.000s)[0m
12248 12:16:39.346520 <14>[ 25.516036] [IGT] kms_vblank: executing
12249 12:16:39.346573 IGT-Version: 1.2<14>[ 25.520766] [IGT] kms_vblank: exiting, ret=77
12250 12:16:39.346626 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12251 12:16:39.346680 Opened dev<8>[ 25.531894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12252 12:16:39.346733 ice: /dev/dri/card0
12253 12:16:39.346785 No KMS driver or no outputs, pipes: 8, outputs: 0
12254 12:16:39.346839 [1mSubtest crtc-id: SKIP (0.000s)[0m
12255 12:16:39.346893 <14>[ 25.550804] [IGT] kms_vblank: executing
12256 12:16:39.346946 IGT-Version: 1.2<14>[ 25.555666] [IGT] kms_vblank: exiting, ret=77
12257 12:16:39.346999 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12258 12:16:39.347054 Opened dev<8>[ 25.565975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip>
12259 12:16:39.347108 ice: /dev/dri/card0
12260 12:16:39.347160 No KMS driver or no outputs, pipes: 8, outputs: 0
12261 12:16:39.347214 [1mSubtest pipe-A-accuracy-idle: SKIP (0.000s)[0m
12262 12:16:39.347267 <14>[ 25.597277] [IGT] kms_vblank: executing
12263 12:16:39.347319 IGT-Version: 1.2<14>[ 25.602331] [IGT] kms_vblank: exiting, ret=77
12264 12:16:39.347372 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12265 12:16:39.347426 Opened device: /dev/dri/card0
12266 12:16:39.347479 No KMS driv<8>[ 25.615618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle RESULT=skip>
12267 12:16:39.347533 er or no outputs, pipes: 8, outputs: 0
12268 12:16:39.347586 [1mSubtest pipe-A-query-idle: SKIP (0.000s)[0m
12269 12:16:39.347638 <14>[ 25.638388] [IGT] kms_vblank: executing
12270 12:16:39.347727 IGT-Version: 1.2<14>[ 25.643111] [IGT] kms_vblank: exiting, ret=77
12271 12:16:39.347795 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12272 12:16:39.347850 Opened dev<8>[ 25.654156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip>
12273 12:16:39.347904 ice: /dev/dri/card0
12274 12:16:39.347956 No KMS driver or no outputs, pipes: 8, outputs: 0
12275 12:16:39.348010 [1mSubtest pipe-A-query-idle-hang: SKIP (0.000s)[0m
12276 12:16:39.348063 <14>[ 25.674153] [IGT] kms_vblank: executing
12277 12:16:39.348115 IGT-Version: 1.2<14>[ 25.678897] [IGT] kms_vblank: exiting, ret=77
12278 12:16:39.348168 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12279 12:16:39.348222 Opened device: /dev/dri/card0
12280 12:16:39.348276 No KMS driv<8>[ 25.691514] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked RESULT=skip>
12281 12:16:39.348329 er or no outputs, pipes: 8, outputs: 0
12282 12:16:39.348381 [1mSubtest pipe-A-query-forked: SKIP (0.000s)[0m
12283 12:16:39.348611 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12285 12:16:39.348797 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12287 12:16:39.348978 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12289 12:16:39.349160 Received signal: <TESTSET> STOP
12290 12:16:39.349222 Closing test_set kms_setmode
12291 12:16:39.349303 Received signal: <TESTSET> START kms_vblank
12292 12:16:39.349364 Starting test_set kms_vblank
12293 12:16:39.349443 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12295 12:16:39.349622 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12297 12:16:39.349800 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip
12299 12:16:39.349980 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle RESULT=skip
12301 12:16:39.350160 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip
12303 12:16:39.350338 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked RESULT=skip
12305 12:16:39.350526 <14>[ 25.713745] [IGT] kms_vblank: executing
12306 12:16:39.350590 IGT-Version: 1.2<14>[ 25.718609] [IGT] kms_vblank: exiting, ret=77
12307 12:16:39.350649 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12308 12:16:39.350708 Opened device: /dev/dri/ca<8>[ 25.729808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip>
12309 12:16:39.350764 rd0
12310 12:16:39.350819 No KMS driver or no outputs, pipes: 8, outputs: 0
12311 12:16:39.350875 [1mSubtest pipe-A-query-forked-hang: SKIP (0.000s)[0m
12312 12:16:41.955142 <14>[ 25.751871] [IGT] kms_vblank: executing
12313 12:16:41.955747 IGT-Version: 1.2<14>[ 25.756690] [IGT] kms_vblank: exiting, ret=77
12314 12:16:41.956144 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12315 12:16:41.956504 Opened device: /dev/dri/ca<8>[ 25.768510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy RESULT=skip>
12316 12:16:41.956848 rd0
12317 12:16:41.957175 No KMS driver or no outputs, pipes: 8, outputs: 0
12318 12:16:41.957501 [1mSubtest pipe-A-query-busy: SKIP (0.000s)[0m
12319 12:16:41.957840 <14>[ 25.788984] [IGT] kms_vblank: executing
12320 12:16:41.958371 IGT-Version: 1.2<14>[ 25.793754] [IGT] kms_vblank: exiting, ret=77
12321 12:16:41.958720 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12322 12:16:41.959048 Opened device: /dev/dri/ca<8>[ 25.805729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip>
12323 12:16:41.959367 rd0
12324 12:16:41.959706 No KMS driver or no outputs, pipes: 8, outputs: 0
12325 12:16:41.960043 [1mSubtest pipe-A-query-busy-hang: SKIP (0.000s)[0m
12326 12:16:41.960351 <14>[ 25.828999] [IGT] kms_vblank: executing
12327 12:16:41.960658 IGT-Version: 1.2<14>[ 25.833730] [IGT] kms_vblank: exiting, ret=77
12328 12:16:41.960962 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12329 12:16:41.961276 Opened dev<8>[ 25.844610] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip>
12330 12:16:41.961585 ice: /dev/dri/card0
12331 12:16:41.961891 No KMS driver or no outputs, pipes: 8, outputs: 0
12332 12:16:41.962195 [1mSubtest pipe-A-query-forked-busy: SKIP (0.000s)[0m
12333 12:16:41.962495 <14>[ 25.868148] [IGT] kms_vblank: executing
12334 12:16:41.962801 IGT-Version: 1.2<14>[ 25.872854] [IGT] kms_vblank: exiting, ret=77
12335 12:16:41.963108 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12336 12:16:41.963418 Opened dev<8>[ 25.884078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip>
12337 12:16:41.963768 ice: /dev/dri/card0
12338 12:16:41.964079 No KMS driver or no outputs, pipes: 8, outputs: 0
12339 12:16:41.964389 [1mSubtest pipe-A-query-forked-busy-hang: SKIP (0.000s)[0m
12340 12:16:41.964694 <14>[ 25.904367] [IGT] kms_vblank: executing
12341 12:16:41.964999 IGT-Version: 1.2<14>[ 25.909213] [IGT] kms_vblank: exiting, ret=77
12342 12:16:41.965303 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12343 12:16:41.965616 Opened dev<8>[ 25.920140] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle RESULT=skip>
12344 12:16:41.965923 ice: /dev/dri/card0
12345 12:16:41.966224 No KMS driver or no outputs, pipes: 8, outputs: 0
12346 12:16:41.966527 [1mSubtest pipe-A-wait-idle: SKIP (0.000s)[0m
12347 12:16:41.966829 <14>[ 25.940125] [IGT] kms_vblank: executing
12348 12:16:41.967131 IGT-Version: 1.2<14>[ 25.944867] [IGT] kms_vblank: exiting, ret=77
12349 12:16:41.967434 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12350 12:16:41.967779 Opened device: /dev/dri/ca<8>[ 25.956551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip>
12351 12:16:41.968095 rd0
12352 12:16:41.968393 No KMS driver or no outputs, pipes: 8, outputs: 0
12353 12:16:41.968691 [1mSubtest pipe-A-wait-idle-hang: SKIP (0.000s)[0m
12354 12:16:41.968965 <14>[ 25.978968] [IGT] kms_vblank: executing
12355 12:16:41.969239 IGT-Version: 1.2<14>[ 25.983751] [IGT] kms_vblank: exiting, ret=77
12356 12:16:41.969515 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12357 12:16:41.969798 Opened dev<8>[ 25.994837] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked RESULT=skip>
12358 12:16:41.970075 ice: /dev/dri/card0
12359 12:16:41.970349 No KMS driver or no outputs, pipes: 8, outputs: 0
12360 12:16:41.970626 [1mSubtest pipe-A-wait-forked: SKIP (0.000s)[0m
12361 12:16:41.970901 <14>[ 26.014846] [IGT] kms_vblank: executing
12362 12:16:41.971175 IGT-Version: 1.2<14>[ 26.019611] [IGT] kms_vblank: exiting, ret=77
12363 12:16:41.971449 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12364 12:16:41.971806 Opened dev<8>[ 26.030613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip>
12365 12:16:41.972109 ice: /dev/dri/card0
12366 12:16:41.972389 No KMS driver or no outputs, pipes: 8, outputs: 0
12367 12:16:41.972670 [1mSubtest pipe-A-wait-forked-hang: SKIP (0.000s)[0m
12368 12:16:41.972948 <14>[ 26.051151] [IGT] kms_vblank: executing
12369 12:16:41.973222 IGT-Version: 1.2<14>[ 26.055996] [IGT] kms_vblank: exiting, ret=77
12370 12:16:41.973502 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12371 12:16:41.973784 Opened dev<8>[ 26.066911] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy RESULT=skip>
12372 12:16:41.974064 ice: /dev/dri/card0
12373 12:16:41.974337 No KMS driver or no outputs, pipes: 8, outputs: 0
12374 12:16:41.974616 [1mSubtest pipe-A-wait-busy: SKIP (0.000s)[0m
12375 12:16:41.974894 <14>[ 26.086503] [IGT] kms_vblank: executing
12376 12:16:41.975174 IGT-Version: 1.2<14>[ 26.091232] [IGT] kms_vblank: exiting, ret=77
12377 12:16:41.975805 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip
12379 12:16:41.976793 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy RESULT=skip
12381 12:16:41.977832 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip
12383 12:16:41.978850 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip
12385 12:16:41.979844 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip
12387 12:16:41.980797 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle RESULT=skip
12389 12:16:41.981745 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip
12391 12:16:41.982677 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked RESULT=skip
12393 12:16:41.983564 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip
12395 12:16:41.984310 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy RESULT=skip
12397 12:16:41.985185 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12398 12:16:41.985462 Opened device: /dev/dri/ca<8>[ 26.102595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip>
12399 12:16:41.985769 rd0
12400 12:16:41.986060 No KMS driver or no outputs, pipes: 8, outputs: 0
12401 12:16:41.986353 [1mSubtest pipe-A-wait-busy-hang: SKIP (0.000s)[0m
12402 12:16:41.986641 <14>[ 26.127018] [IGT] kms_vblank: executing
12403 12:16:41.986926 IGT-Version: 1.2<14>[ 26.131761] [IGT] kms_vblank: exiting, ret=77
12404 12:16:41.987274 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12405 12:16:41.987561 Opened device: /dev/dri/ca<8>[ 26.143387] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip>
12406 12:16:41.987895 rd0
12407 12:16:41.988178 No KMS driver or no outputs, pipes: 8, outputs: 0
12408 12:16:41.988462 [1mSubtest pipe-A-wait-forked-busy: SKIP (0.000s)[0m
12409 12:16:41.988673 <14>[ 26.166431] [IGT] kms_vblank: executing
12410 12:16:41.988884 IGT-Version: 1.2<14>[ 26.171257] [IGT] kms_vblank: exiting, ret=77
12411 12:16:41.989095 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12412 12:16:41.989362 Opened device: /dev/dri/ca<8>[ 26.182607] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip>
12413 12:16:41.989625 rd0
12414 12:16:41.989885 No KMS driver or no outputs, pipes: 8, outputs: 0
12415 12:16:41.990146 [1mSubtest pipe-A-wait-forked-busy-hang: SKIP (0.000s)[0m
12416 12:16:41.990354 <14>[ 26.203865] [IGT] kms_vblank: executing
12417 12:16:41.990566 IGT-Version: 1.2<14>[ 26.208611] [IGT] kms_vblank: exiting, ret=77
12418 12:16:41.990777 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12419 12:16:41.990991 Opened dev<8>[ 26.219171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip>
12420 12:16:41.991202 ice: /dev/dri/card0
12421 12:16:41.991412 No KMS driver or no outputs, pipes: 8, outputs: 0
12422 12:16:41.991700 [1mSubtest pipe-A-ts-continuation-idle: SKIP (0.000s)[0m
12423 12:16:41.991966 <14>[ 26.251249] [IGT] kms_vblank: executing
12424 12:16:41.992228 IGT-Version: 1.2<14>[ 26.256362] [IGT] kms_vblank: exiting, ret=77
12425 12:16:41.992489 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12426 12:16:41.992755 Opened device: /dev/dri/card0
12427 12:16:41.993013 No KMS driv<8>[ 26.269191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip>
12428 12:16:41.993273 er or no outputs, pipes: 8, outputs: 0
12429 12:16:41.993521 [1mSubtest pipe-A-ts-continuation-idle-hang: SKIP (0.000s)[0m
12430 12:16:41.993726 <14>[ 26.291470] [IGT] kms_vblank: executing
12431 12:16:41.993932 IGT-Version: 1.2<14>[ 26.296272] [IGT] kms_vblank: exiting, ret=77
12432 12:16:41.994138 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12433 12:16:41.994350 Opened device: /dev/dri/ca<8>[ 26.308019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip>
12434 12:16:41.994520 rd0
12435 12:16:41.994686 No KMS driver or no outputs, pipes: 8, outputs: 0
12436 12:16:41.994896 [1mSubtest pipe-A-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12437 12:16:41.995105 <14>[ 26.329560] [IGT] kms_vblank: executing
12438 12:16:41.995314 IGT-Version: 1.2<14>[ 26.334369] [IGT] kms_vblank: exiting, ret=77
12439 12:16:41.995522 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12440 12:16:41.995751 Opened device: /dev/dri/ca<8>[ 26.345709] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip>
12441 12:16:41.995964 rd0
12442 12:16:41.996130 No KMS driver or no outputs, pipes: 8, outputs: 0
12443 12:16:41.996341 [1mSubtest pipe-A-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12444 12:16:41.996548 <14>[ 26.368233] [IGT] kms_vblank: executing
12445 12:16:41.996766 IGT-Version: 1.2<14>[ 26.373056] [IGT] kms_vblank: exiting, ret=77
12446 12:16:41.996975 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12447 12:16:41.997145 Opened device: /dev/dri/ca<8>[ 26.384604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip>
12448 12:16:41.997315 rd0
12449 12:16:41.997522 No KMS driver or no outputs, pipes: 8, outputs: 0
12450 12:16:41.997691 [1mSubtest pipe-A-ts-continuation-suspend: SKIP (0.000s)[0m
12451 12:16:41.997859 <14>[ 26.406337] [IGT] kms_vblank: executing
12452 12:16:41.998066 IGT-Version: 1.2<14>[ 26.411096] [IGT] kms_vblank: exiting, ret=77
12453 12:16:41.998275 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12454 12:16:41.998451 Opened device: /dev/dri/ca<8>[ 26.423126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip>
12455 12:16:41.998627 rd0
12456 12:16:41.998765 No KMS driver or no outputs, pipes: 8, outputs: 0
12457 12:16:41.998905 [1mSubtest pipe-A-ts-continuation-modeset: SKIP (0.000s)[0m
12458 12:16:41.999045 <14>[ 26.454964] [IGT] kms_vblank: executing
12459 12:16:41.999184 IGT-Version: 1.2<14>[ 26.460101] [IGT] kms_vblank: exiting, ret=77
12460 12:16:41.999323 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12461 12:16:41.999500 Opened device: /dev/dri/card0
12462 12:16:41.999682 No KMS driv<8>[ 26.472655] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip>
12463 12:16:41.999827 er or no outputs, pipes: 8, outputs: 0
12464 12:16:42.000001 [1mSubtest pipe-A-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12465 12:16:42.000140 <14>[ 26.496693] [IGT] kms_vblank: executing
12466 12:16:42.000480 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip
12468 12:16:42.000896 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip
12470 12:16:42.001312 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip
12472 12:16:42.001771 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip
12474 12:16:42.002230 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip
12476 12:16:42.002796 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip
12478 12:16:42.003368 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip
12480 12:16:42.003833 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip
12482 12:16:42.004197 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip
12484 12:16:42.004548 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip
12486 12:16:42.005010 IGT-Version: 1.2<14>[ 26.501583] [IGT] kms_vblank: exiting, ret=77
12487 12:16:42.005164 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12488 12:16:42.005294 Opened device: /dev/dri/ca<8>[ 26.512977] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip>
12489 12:16:42.005421 rd0
12490 12:16:42.005574 No KMS driver or no outputs, pipes: 8, outputs: 0
12491 12:16:42.005728 [1mSubtest pipe-A-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12492 12:16:42.005880 <14>[ 26.535077] [IGT] kms_vblank: executing
12493 12:16:42.006032 IGT-Version: 1.2<14>[ 26.539806] [IGT] kms_vblank: exiting, ret=77
12494 12:16:42.006184 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12495 12:16:42.006338 Opened dev<8>[ 26.550936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip>
12496 12:16:42.006491 ice: /dev/dri/card0
12497 12:16:42.006641 No KMS driver or no outputs, pipes: 8, outputs: 0
12498 12:16:42.006793 [1mSubtest pipe-B-accuracy-idle: SKIP (0.000s)[0m
12499 12:16:42.006941 <14>[ 26.570913] [IGT] kms_vblank: executing
12500 12:16:42.007091 IGT-Version: 1.2<14>[ 26.575711] [IGT] kms_vblank: exiting, ret=77
12501 12:16:42.007241 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12502 12:16:42.007394 Opened dev<8>[ 26.585927] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle RESULT=skip>
12503 12:16:42.007544 ice: /dev/dri/card0
12504 12:16:42.007705 No KMS driver or no outputs, pipes: 8, outputs: 0
12505 12:16:42.007857 [1mSubtest pipe-B-query-idle: SKIP (0.000s)[0m
12506 12:16:42.008022 <14>[ 26.617598] [IGT] kms_vblank: executing
12507 12:16:42.008173 IGT-Version: 1.2<14>[ 26.622696] [IGT] kms_vblank: exiting, ret=77
12508 12:16:42.008322 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12509 12:16:42.008479 Opened device: /dev/dri/card0
12510 12:16:42.008610 No KMS driv<8>[ 26.635509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip>
12511 12:16:42.008743 er or no outputs, pipes: 8, outputs: 0
12512 12:16:42.008847 [1mSubtest pipe-B-query-idle-hang: SKIP (0.000s)[0m
12513 12:16:42.008952 <14>[ 26.659843] [IGT] kms_vblank: executing
12514 12:16:42.009057 IGT-Version: 1.2<14>[ 26.664588] [IGT] kms_vblank: exiting, ret=77
12515 12:16:42.009187 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12516 12:16:42.009321 Opened dev<8>[ 26.674782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked RESULT=skip>
12517 12:16:42.009453 ice: /dev/dri/card0
12518 12:16:42.009588 No KMS driver or no outputs, pipes: 8, outputs: 0
12519 12:16:42.009715 [1mSubtest pipe-B-query-forked: SKIP (0.000s)[0m
12520 12:16:42.009843 <14>[ 26.706455] [IGT] kms_vblank: executing
12521 12:16:42.009962 IGT-Version: 1.2<14>[ 26.711416] [IGT] kms_vblank: exiting, ret=77
12522 12:16:42.010080 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12523 12:16:42.010203 Opened device: /dev/dri/ca<8>[ 26.722826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip>
12524 12:16:42.010320 rd0
12525 12:16:42.010436 No KMS driver or no outputs, pipes: 8, outputs: 0
12526 12:16:42.010555 [1mSubtest pipe-B-query-forked-hang: SKIP (0.000s)[0m
12527 12:16:42.010671 <14>[ 26.747069] [IGT] kms_vblank: executing
12528 12:16:42.010788 IGT-Version: 1.2<14>[ 26.751811] [IGT] kms_vblank: exiting, ret=77
12529 12:16:42.010904 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12530 12:16:42.011025 Opened dev<8>[ 26.762736] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy RESULT=skip>
12531 12:16:42.011142 ice: /dev/dri/card0
12532 12:16:42.011258 No KMS driver or no outputs, pipes: 8, outputs: 0
12533 12:16:42.011375 [1mSubtest pipe-B-query-busy: SKIP (0.000s)[0m
12534 12:16:42.011490 <14>[ 26.785441] [IGT] kms_vblank: executing
12535 12:16:42.011607 IGT-Version: 1.2<14>[ 26.790200] [IGT] kms_vblank: exiting, ret=77
12536 12:16:42.011738 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12537 12:16:42.011860 Opened dev<8>[ 26.800805] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip>
12538 12:16:42.011978 ice: /dev/dri/card0
12539 12:16:42.012085 No KMS driver or no outputs, pipes: 8, outputs: 0
12540 12:16:42.012163 [1mSubtest pipe-B-query-busy-hang: SKIP (0.000s)[0m
12541 12:16:42.012239 <14>[ 26.820978] [IGT] kms_vblank: executing
12542 12:16:42.012315 IGT-Version: 1.2<14>[ 26.825787] [IGT] kms_vblank: exiting, ret=77
12543 12:16:42.012390 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12544 12:16:42.012468 Opened dev<8>[ 26.836604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip>
12545 12:16:42.012545 ice: /dev/dri/card0
12546 12:16:42.012620 No KMS driver or no outputs, pipes: 8, outputs: 0
12547 12:16:42.012695 [1mSubtest pipe-B-query-forked-busy: SKIP (0.000s)[0m
12548 12:16:42.012771 <14>[ 26.857416] [IGT] kms_vblank: executing
12549 12:16:42.012846 IGT-Version: 1.2<14>[ 26.862137] [IGT] kms_vblank: exiting, ret=77
12550 12:16:42.012922 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12551 12:16:42.012998 Opened device: /dev/dri/ca<8>[ 26.874243] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip>
12552 12:16:42.013075 rd0
12553 12:16:42.013149 No KMS driver or no outputs, pipes: 8, outputs: 0
12554 12:16:42.013225 [1mSubtest pipe-B-query-forked-busy-hang: SKIP (0.000s)[0m
12555 12:16:42.013301 <14>[ 26.898877] [IGT] kms_vblank: executing
12556 12:16:42.013376 IGT-Version: 1.2<14>[ 26.903606] [IGT] kms_vblank: exiting, ret=77
12557 12:16:42.013457 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12558 12:16:42.013708 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip
12560 12:16:42.013937 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip
12562 12:16:42.014165 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle RESULT=skip
12564 12:16:42.014394 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip
12566 12:16:42.014621 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked RESULT=skip
12568 12:16:42.014848 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip
12570 12:16:42.015075 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy RESULT=skip
12572 12:16:42.015299 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip
12574 12:16:42.015523 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip
12576 12:16:42.015769 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip
12578 12:16:42.016021 Opened dev<8>[ 26.914654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle RESULT=skip>
12579 12:16:42.016146 ice: /dev/dri/card0
12580 12:16:42.016225 No KMS driver or no outputs, pipes: 8, outputs: 0
12581 12:16:42.016299 [1mSubtest pipe-B-wait-idle: SKIP (0.000s)[0m
12582 12:16:42.016370 <14>[ 26.937186] [IGT] kms_vblank: executing
12583 12:16:42.016441 IGT-Version: 1.2<14>[ 26.941936] [IGT] kms_vblank: exiting, ret=77
12584 12:16:42.016511 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12585 12:16:42.016582 Opened dev<8>[ 26.952618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip>
12586 12:16:42.016652 ice: /dev/dri/card0
12587 12:16:42.016719 No KMS driver or no outputs, pipes: 8, outputs: 0
12588 12:16:42.016788 [1mSubtest pipe-B-wait-idle-hang: SKIP (0.000s)[0m
12589 12:16:42.016855 <14>[ 26.972828] [IGT] kms_vblank: executing
12590 12:16:42.016923 IGT-Version: 1.2<14>[ 26.977645] [IGT] kms_vblank: exiting, ret=77
12591 12:16:42.016990 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12592 12:16:42.017059 Opened dev<8>[ 26.988642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked RESULT=skip>
12593 12:16:42.017128 ice: /dev/dri/card0
12594 12:16:42.017196 No KMS driver or no outputs, pipes: 8, outputs: 0
12595 12:16:42.017264 [1mSubtest pipe-B-wait-forked: SKIP (0.000s)[0m
12596 12:16:42.017331 <14>[ 27.008683] [IGT] kms_vblank: executing
12597 12:16:42.017398 IGT-Version: 1.2<14>[ 27.013703] [IGT] kms_vblank: exiting, ret=77
12598 12:16:42.017466 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12599 12:16:42.017534 Opened dev<8>[ 27.024484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip>
12600 12:16:42.017603 ice: /dev/dri/card0
12601 12:16:42.017669 No KMS driver or no outputs, pipes: 8, outputs: 0
12602 12:16:42.017752 [1mSubtest pipe-B-wait-forked-hang: SKIP (0.000s)[0m
12603 12:16:42.017824 <14>[ 27.047787] [IGT] kms_vblank: executing
12604 12:16:42.017892 IGT-Version: 1.2<14>[ 27.052548] [IGT] kms_vblank: exiting, ret=77
12605 12:16:42.017959 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12606 12:16:42.018028 Opened device: /dev/dri/ca<8>[ 27.064223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy RESULT=skip>
12607 12:16:42.018097 rd0
12608 12:16:42.018163 No KMS driver or no outputs, pipes: 8, outputs: 0
12609 12:16:42.018230 [1mSubtest pipe-B-wait-busy: SKIP (0.000s)[0m
12610 12:16:42.018296 <14>[ 27.084408] [IGT] kms_vblank: executing
12611 12:16:42.018364 IGT-Version: 1.2<14>[ 27.089248] [IGT] kms_vblank: exiting, ret=77
12612 12:16:42.018440 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12613 12:16:42.018503 Opened device: /dev/dri/ca<8>[ 27.100845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip>
12614 12:16:42.018564 rd0
12615 12:16:42.018624 No KMS driver or no outputs, pipes: 8, outputs: 0
12616 12:16:42.018685 [1mSubtest pipe-B-wait-busy-hang: SKIP (0.000s)[0m
12617 12:16:42.018746 <14>[ 27.121761] [IGT] kms_vblank: executing
12618 12:16:42.018806 IGT-Version: 1.2<14>[ 27.126693] [IGT] kms_vblank: exiting, ret=77
12619 12:16:42.018866 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12620 12:16:42.018928 Opened device: /dev/dri/ca<8>[ 27.138477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip>
12621 12:16:42.018988 rd0
12622 12:16:42.019047 No KMS driver or no outputs, pipes: 8, outputs: 0
12623 12:16:42.019108 [1mSubtest pipe-B-wait-forked-busy: SKIP (0.000s)[0m
12624 12:16:42.019168 <14>[ 27.162654] [IGT] kms_vblank: executing
12625 12:16:42.019228 IGT-Version: 1.2<14>[ 27.167394] [IGT] kms_vblank: exiting, ret=77
12626 12:16:42.019288 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12627 12:16:42.019350 Opened dev<8>[ 27.178533] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip>
12628 12:16:42.019411 ice: /dev/dri/card0
12629 12:16:42.019470 No KMS driver or no outputs, pipes: 8, outputs: 0
12630 12:16:42.019530 [1mSubtest pipe-B-wait-forked-busy-hang: SKIP (0.000s)[0m
12631 12:16:42.019591 <14>[ 27.202713] [IGT] kms_vblank: executing
12632 12:16:42.019651 IGT-Version: 1.2<14>[ 27.207448] [IGT] kms_vblank: exiting, ret=77
12633 12:16:42.019725 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12634 12:16:42.019788 Opened dev<8>[ 27.218597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip>
12635 12:16:42.019849 ice: /dev/dri/card0
12636 12:16:42.019908 No KMS driver or no outputs, pipes: 8, outputs: 0
12637 12:16:42.019969 [1mSubtest pipe-B-ts-continuation-idle: SKIP (0.000s)[0m
12638 12:16:42.020029 <14>[ 27.242600] [IGT] kms_vblank: executing
12639 12:16:42.020089 IGT-Version: 1.2<14>[ 27.247337] [IGT] kms_vblank: exiting, ret=77
12640 12:16:42.020148 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12641 12:16:42.020210 Opened dev<8>[ 27.258214] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip>
12642 12:16:42.020271 ice: /dev/dri/card0
12643 12:16:42.020331 No KMS driver or no outputs, pipes: 8, outputs: 0
12644 12:16:42.020391 [1mSubtest pipe-B-ts-continuation-idle-hang: SKIP (0.000s)[0m
12645 12:16:42.020452 <14>[ 27.282889] [IGT] kms_vblank: executing
12646 12:16:42.020512 IGT-Version: 1.2<14>[ 27.287792] [IGT] kms_vblank: exiting, ret=77
12647 12:16:42.020572 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12648 12:16:42.020813 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle RESULT=skip
12650 12:16:42.021023 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip
12652 12:16:42.021279 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked RESULT=skip
12654 12:16:42.021494 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip
12656 12:16:42.021702 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy RESULT=skip
12658 12:16:42.021948 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip
12660 12:16:42.022202 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip
12662 12:16:42.022415 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip
12664 12:16:42.022622 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip
12666 12:16:42.022875 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip
12668 12:16:42.023096 Opened dev<8>[ 27.298752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip>
12669 12:16:42.023169 ice: /dev/dri/card0
12670 12:16:42.023242 No KMS driver or no outputs, pipes: 8, outputs: 0
12671 12:16:42.023310 [1mSubtest pipe-B-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12672 12:16:42.023375 <14>[ 27.322762] [IGT] kms_vblank: executing
12673 12:16:42.023438 IGT-Version: 1.2<14>[ 27.327528] [IGT] kms_vblank: exiting, ret=77
12674 12:16:42.023517 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12675 12:16:42.023609 Opened device: /dev/dri/ca<8>[ 27.339120] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip>
12676 12:16:42.023700 rd0
12677 12:16:42.023760 No KMS driver or no outputs, pipes: 8, outputs: 0
12678 12:16:42.023817 [1mSubtest pipe-B-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12679 12:16:42.023873 <14>[ 27.363327] [IGT] kms_vblank: executing
12680 12:16:42.023962 IGT-Version: 1.2<14>[ 27.368100] [IGT] kms_vblank: exiting, ret=77
12681 12:16:42.024047 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12682 12:16:42.024137 Opened dev<8>[ 27.378916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip>
12683 12:16:42.024223 ice: /dev/dri/card0
12684 12:16:42.024307 No KMS driver or no outputs, pipes: 8, outputs: 0
12685 12:16:42.024397 [1mSubtest pipe-B-ts-continuation-suspend: SKIP (0.000s)[0m
12686 12:16:42.024483 <14>[ 27.400235] [IGT] kms_vblank: executing
12687 12:16:42.024560 IGT-Version: 1.2<14>[ 27.405004] [IGT] kms_vblank: exiting, ret=77
12688 12:16:42.024618 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12689 12:16:42.024682 Opened dev<8>[ 27.415867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip>
12690 12:16:42.024740 ice: /dev/dri/card0
12691 12:16:42.024796 No KMS driver or no outputs, pipes: 8, outputs: 0
12692 12:16:42.024852 [1mSubtest pipe-B-ts-continuation-modeset: SKIP (0.000s)[0m
12693 12:16:42.024908 <14>[ 27.437044] [IGT] kms_vblank: executing
12694 12:16:42.024964 IGT-Version: 1.2<14>[ 27.441790] [IGT] kms_vblank: exiting, ret=77
12695 12:16:42.025019 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12696 12:16:42.025075 Opened dev<8>[ 27.452010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip>
12697 12:16:42.025131 ice: /dev/dri/card0
12698 12:16:42.025185 No KMS driver or no outputs, pipes: 8, outputs: 0
12699 12:16:42.025249 [1mSubtest pipe-B-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12700 12:16:42.025305 <14>[ 27.484726] [IGT] kms_vblank: executing
12701 12:16:42.025359 IGT-Version: 1.2<14>[ 27.490040] [IGT] kms_vblank: exiting, ret=77
12702 12:16:42.025414 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12703 12:16:42.025470 Opened device: /dev/dri/card0
12704 12:16:42.025526 No KMS driv<8>[ 27.502486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip>
12705 12:16:42.025582 er or no outputs, pipes: 8, outputs: 0
12706 12:16:42.025637 [1mSubtest pipe-B-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12707 12:16:42.025692 <14>[ 27.528200] [IGT] kms_vblank: executing
12708 12:16:42.025747 IGT-Version: 1.2<14>[ 27.532988] [IGT] kms_vblank: exiting, ret=77
12709 12:16:42.025802 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12710 12:16:42.025858 Opened dev<8>[ 27.543805] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip>
12711 12:16:42.025913 ice: /dev/dri/card0
12712 12:16:42.025974 No KMS driver or no outputs, pipes: 8, outputs: 0
12713 12:16:42.026062 [1mSubtest pipe-C-accuracy-idle: SKIP (0.000s)[0m
12714 12:16:42.026147 <14>[ 27.566366] [IGT] kms_vblank: executing
12715 12:16:42.026220 IGT-Version: 1.2<14>[ 27.571112] [IGT] kms_vblank: exiting, ret=77
12716 12:16:42.026276 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12717 12:16:42.026333 Opened device: /dev/dri/ca<8>[ 27.582941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle RESULT=skip>
12718 12:16:42.026390 rd0
12719 12:16:42.026453 No KMS driver or no outputs, pipes: 8, outputs: 0
12720 12:16:42.026511 [1mSubtest pipe-C-query-idle: SKIP (0.000s)[0m
12721 12:16:42.026566 <14>[ 27.605649] [IGT] kms_vblank: executing
12722 12:16:42.026621 IGT-Version: 1.2<14>[ 27.610552] [IGT] kms_vblank: exiting, ret=77
12723 12:16:42.026677 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12724 12:16:42.026733 Opened device: /dev/dri/ca<8>[ 27.622305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip>
12725 12:16:42.026789 rd0
12726 12:16:42.026843 No KMS driver or no outputs, pipes: 8, outputs: 0
12727 12:16:42.026897 [1mSubtest pipe-C-query-idle-hang: SKIP (0.000s)[0m
12728 12:16:42.026952 <14>[ 27.646479] [IGT] kms_vblank: executing
12729 12:16:42.027007 IGT-Version: 1.2<14>[ 27.651231] [IGT] kms_vblank: exiting, ret=77
12730 12:16:42.027062 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12731 12:16:42.027118 Opened dev<8>[ 27.662228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked RESULT=skip>
12732 12:16:42.027176 ice: /dev/dri/card0
12733 12:16:42.027237 No KMS driver or no outputs, pipes: 8, outputs: 0
12734 12:16:42.027294 [1mSubtest pipe-C-query-forked: SKIP (0.000s)[0m
12735 12:16:42.027349 <14>[ 27.682177] [IGT] kms_vblank: executing
12736 12:16:42.027404 IGT-Version: 1.2<14>[ 27.686966] [IGT] kms_vblank: exiting, ret=77
12737 12:16:42.027459 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12738 12:16:42.027696 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip
12740 12:16:42.027892 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip
12742 12:16:42.028083 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip
12744 12:16:42.028272 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip
12746 12:16:42.028471 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip
12748 12:16:42.028685 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip
12750 12:16:42.028864 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip
12752 12:16:42.029043 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle RESULT=skip
12754 12:16:42.029221 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip
12756 12:16:42.029396 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked RESULT=skip
12758 12:16:42.029597 Opened device: /dev/dri/ca<8>[ 27.699345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip>
12759 12:16:42.029675 rd0
12760 12:16:42.029732 No KMS driver or no outputs, pipes: 8, outputs: 0
12761 12:16:42.029789 [1mSubtest pipe-C-query-forked-hang: SKIP (0.000s)[0m
12762 12:16:42.029845 <14>[ 27.720292] [IGT] kms_vblank: executing
12763 12:16:42.029923 IGT-Version: 1.2<14>[ 27.725067] [IGT] kms_vblank: exiting, ret=77
12764 12:16:42.029989 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12765 12:16:42.030044 Opened dev<8>[ 27.735932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy RESULT=skip>
12766 12:16:42.030098 ice: /dev/dri/card0
12767 12:16:42.030151 No KMS driver or no outputs, pipes: 8, outputs: 0
12768 12:16:42.030205 [1mSubtest pipe-C-query-busy: SKIP (0.000s)[0m
12769 12:16:42.030258 <14>[ 27.755942] [IGT] kms_vblank: executing
12770 12:16:42.030311 IGT-Version: 1.2<14>[ 27.760667] [IGT] kms_vblank: exiting, ret=77
12771 12:16:42.030364 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12772 12:16:42.030419 Opened dev<8>[ 27.771691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip>
12773 12:16:42.030473 ice: /dev/dri/card0
12774 12:16:42.030526 No KMS driver or no outputs, pipes: 8, outputs: 0
12775 12:16:42.030579 [1mSubtest pipe-C-query-busy-hang: SKIP (0.000s)[0m
12776 12:16:42.030632 <14>[ 27.794222] [IGT] kms_vblank: executing
12777 12:16:42.030686 IGT-Version: 1.2<14>[ 27.798976] [IGT] kms_vblank: exiting, ret=77
12778 12:16:42.030739 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12779 12:16:42.030793 Opened dev<8>[ 27.810103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip>
12780 12:16:42.030846 ice: /dev/dri/card0
12781 12:16:42.030899 No KMS driver or no outputs, pipes: 8, outputs: 0
12782 12:16:42.030952 [1mSubtest pipe-C-query-forked-busy: SKIP (0.000s)[0m
12783 12:16:42.031005 <14>[ 27.830644] [IGT] kms_vblank: executing
12784 12:16:42.031058 IGT-Version: 1.2<14>[ 27.835407] [IGT] kms_vblank: exiting, ret=77
12785 12:16:42.031111 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12786 12:16:42.031165 Opened dev<8>[ 27.846312] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip>
12787 12:16:42.031219 ice: /dev/dri/card0
12788 12:16:42.031271 No KMS driver or no outputs, pipes: 8, outputs: 0
12789 12:16:42.031325 [1mSubtest pipe-C-query-forked-busy-hang: SKIP (0.000s)[0m
12790 12:16:42.031378 <14>[ 27.867670] [IGT] kms_vblank: executing
12791 12:16:42.031431 IGT-Version: 1.2<14>[ 27.872476] [IGT] kms_vblank: exiting, ret=77
12792 12:16:42.031483 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12793 12:16:42.031538 Opened device: /dev/dri/ca<8>[ 27.884402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle RESULT=skip>
12794 12:16:42.031592 rd0
12795 12:16:42.031644 No KMS driver or no outputs, pipes: 8, outputs: 0
12796 12:16:42.031718 [1mSubtest pipe-C-wait-idle: SKIP (0.000s)[0m
12797 12:16:42.031773 <14>[ 27.904450] [IGT] kms_vblank: executing
12798 12:16:42.031828 IGT-Version: 1.2<14>[ 27.909323] [IGT] kms_vblank: exiting, ret=77
12799 12:16:42.031881 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12800 12:16:42.031937 Opened dev<8>[ 27.920235] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip>
12801 12:16:42.031992 ice: /dev/dri/card0
12802 12:16:42.032045 No KMS driver or no outputs, pipes: 8, outputs: 0
12803 12:16:42.032100 [1mSubtest pipe-C-wait-idle-hang: SKIP (0.000s)[0m
12804 12:16:42.032154 <14>[ 27.940845] [IGT] kms_vblank: executing
12805 12:16:42.032208 IGT-Version: 1.2<14>[ 27.945778] [IGT] kms_vblank: exiting, ret=77
12806 12:16:42.032262 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12807 12:16:42.032317 Opened device: /dev/dri/ca<8>[ 27.957301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked RESULT=skip>
12808 12:16:42.032372 rd0
12809 12:16:42.032425 No KMS driver or no outputs, pipes: 8, outputs: 0
12810 12:16:42.032479 [1mSubtest pipe-C-wait-forked: SKIP (0.000s)[0m
12811 12:16:42.032533 <14>[ 27.978157] [IGT] kms_vblank: executing
12812 12:16:42.032587 IGT-Version: 1.2<14>[ 27.982886] [IGT] kms_vblank: exiting, ret=77
12813 12:16:42.032642 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12814 12:16:42.032696 Opened dev<8>[ 27.993845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip>
12815 12:16:42.032750 ice: /dev/dri/card0
12816 12:16:42.032804 No KMS driver or no outputs, pipes: 8, outputs: 0
12817 12:16:42.032858 [1mSubtest pipe-C-wait-forked-hang: SKIP (0.000s)[0m
12818 12:16:42.032911 <14>[ 28.016713] [IGT] kms_vblank: executing
12819 12:16:42.032965 IGT-Version: 1.2<14>[ 28.021610] [IGT] kms_vblank: exiting, ret=77
12820 12:16:42.033019 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12821 12:16:42.033074 Opened device: /dev/dri/ca<8>[ 28.033359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy RESULT=skip>
12822 12:16:42.033129 rd0
12823 12:16:42.033182 No KMS driver or no outputs, pipes: 8, outputs: 0
12824 12:16:42.033236 [1mSubtest pipe-C-wait-busy: SKIP (0.000s)[0m
12825 12:16:42.033289 <14>[ 28.053262] [IGT] kms_vblank: executing
12826 12:16:42.033342 IGT-Version: 1.2<14>[ 28.058026] [IGT] kms_vblank: exiting, ret=77
12827 12:16:42.033396 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12828 12:16:42.033451 Opened dev<8>[ 28.068911] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip>
12829 12:16:42.033506 ice: /dev/dri/card0
12830 12:16:42.033559 No KMS driver or no outputs, pipes: 8, outputs: 0
12831 12:16:42.033788 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip
12833 12:16:42.033972 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy RESULT=skip
12835 12:16:42.034154 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip
12837 12:16:42.034338 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip
12839 12:16:42.034521 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip
12841 12:16:42.034701 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle RESULT=skip
12843 12:16:42.034881 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip
12845 12:16:42.035063 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked RESULT=skip
12847 12:16:42.035243 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip
12849 12:16:42.035421 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy RESULT=skip
12851 12:16:42.035602 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip
12853 12:16:42.035808 [1mSubtest pipe-C-wait-busy-hang: SKIP (0.000s)[0m
12854 12:16:42.035871 <14>[ 28.089605] [IGT] kms_vblank: executing
12855 12:16:42.035931 IGT-Version: 1.2<14>[ 28.094344] [IGT] kms_vblank: exiting, ret=77
12856 12:16:42.035988 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12857 12:16:42.036046 Opened dev<8>[ 28.105103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip>
12858 12:16:42.036104 ice: /dev/dri/card0
12859 12:16:42.036159 No KMS driver or no outputs, pipes: 8, outputs: 0
12860 12:16:42.036215 [1mSubtest pipe-C-wait-forked-busy: SKIP (0.000s)[0m
12861 12:16:42.036269 <14>[ 28.125007] [IGT] kms_vblank: executing
12862 12:16:42.036323 IGT-Version: 1.2<14>[ 28.129752] [IGT] kms_vblank: exiting, ret=77
12863 12:16:42.036377 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12864 12:16:42.036432 Opened device: /dev/dri/ca<8>[ 28.141543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip>
12865 12:16:42.036487 rd0
12866 12:16:42.036541 No KMS driver or no outputs, pipes: 8, outputs: 0
12867 12:16:42.036596 [1mSubtest pipe-C-wait-forked-busy-hang: SKIP (0.000s)[0m
12868 12:16:42.036651 <14>[ 28.166522] [IGT] kms_vblank: executing
12869 12:16:42.036704 IGT-Version: 1.2<14>[ 28.171219] [IGT] kms_vblank: exiting, ret=77
12870 12:16:42.036758 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12871 12:16:42.036813 Opened dev<8>[ 28.182334] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip>
12872 12:16:42.036868 ice: /dev/dri/card0
12873 12:16:42.036921 No KMS driver or no outputs, pipes: 8, outputs: 0
12874 12:16:42.036974 [1mSubtest pipe-C-ts-continuation-idle: SKIP (0.000s)[0m
12875 12:16:42.037027 <14>[ 28.205428] [IGT] kms_vblank: executing
12876 12:16:42.037082 IGT-Version: 1.2<14>[ 28.210192] [IGT] kms_vblank: exiting, ret=77
12877 12:16:42.037135 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12878 12:16:42.037204 Opened dev<8>[ 28.221148] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip>
12879 12:16:42.037260 ice: /dev/dri/card0
12880 12:16:42.037314 No KMS driver or no outputs, pipes: 8, outputs: 0
12881 12:16:42.037368 [1mSubtest pipe-C-ts-continuation-idle-hang: SKIP (0.000s)[0m
12882 12:16:42.037422 <14>[ 28.242455] [IGT] kms_vblank: executing
12883 12:16:42.037476 IGT-Version: 1.2<14>[ 28.247247] [IGT] kms_vblank: exiting, ret=77
12884 12:16:42.037530 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12885 12:16:42.037584 Opened device: /dev/dri/ca<8>[ 28.259286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip>
12886 12:16:42.037639 rd0
12887 12:16:42.037692 No KMS driver or no outputs, pipes: 8, outputs: 0
12888 12:16:42.037746 [1mSubtest pipe-C-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12889 12:16:42.037801 <14>[ 28.290364] [IGT] kms_vblank: executing
12890 12:16:42.037855 IGT-Version: 1.2<14>[ 28.295480] [IGT] kms_vblank: exiting, ret=77
12891 12:16:42.037908 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12892 12:16:42.037963 Opened device: /dev/dri/ca<8>[ 28.306513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip>
12893 12:16:42.038017 rd0
12894 12:16:42.038070 No KMS driver or no outputs, pipes: 8, outputs: 0
12895 12:16:42.038137 [1mSubtest pipe-C-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12896 12:16:42.038196 <14>[ 28.332089] [IGT] kms_vblank: executing
12897 12:16:42.038251 IGT-Version: 1.2<14>[ 28.336915] [IGT] kms_vblank: exiting, ret=77
12898 12:16:42.038304 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12899 12:16:42.038360 Opened dev<8>[ 28.348049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip>
12900 12:16:42.038415 ice: /dev/dri/card0
12901 12:16:42.038468 No KMS driver or no outputs, pipes: 8, outputs: 0
12902 12:16:42.038522 [1mSubtest pipe-C-ts-continuation-suspend: SKIP (0.000s)[0m
12903 12:16:42.038576 <14>[ 28.368849] [IGT] kms_vblank: executing
12904 12:16:42.038630 IGT-Version: 1.2<14>[ 28.373615] [IGT] kms_vblank: exiting, ret=77
12905 12:16:42.038683 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12906 12:16:42.038739 Opened device: /dev/dri/ca<8>[ 28.385467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip>
12907 12:16:42.038793 rd0
12908 12:16:42.038846 No KMS driver or no outputs, pipes: 8, outputs: 0
12909 12:16:42.038900 [1mSubtest pipe-C-ts-continuation-modeset: SKIP (0.000s)[0m
12910 12:16:42.038954 <14>[ 28.406914] [IGT] kms_vblank: executing
12911 12:16:42.039007 IGT-Version: 1.2<14>[ 28.411700] [IGT] kms_vblank: exiting, ret=77
12912 12:16:42.039061 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12913 12:16:42.039116 Opened device: /dev/dri/ca<8>[ 28.423010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip>
12914 12:16:42.039170 rd0
12915 12:16:42.039223 No KMS driver or no outputs, pipes: 8, outputs: 0
12916 12:16:42.039278 [1mSubtest pipe-C-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12917 12:16:42.039331 <14>[ 28.445849] [IGT] kms_vblank: executing
12918 12:16:42.039385 IGT-Version: 1.2<14>[ 28.450626] [IGT] kms_vblank: exiting, ret=77
12919 12:16:42.039438 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12920 12:16:42.039494 Opened device: /dev/dri/ca<8>[ 28.462340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip>
12921 12:16:42.039548 rd0
12922 12:16:42.039777 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip
12924 12:16:42.039962 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip
12926 12:16:42.040149 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip
12928 12:16:42.040333 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip
12930 12:16:42.040513 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip
12932 12:16:42.040693 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip
12934 12:16:42.040874 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip
12936 12:16:42.041054 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip
12938 12:16:42.041233 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip
12940 12:16:42.041412 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip
12942 12:16:42.041604 No KMS driver or no outputs, pipes: 8, outputs: 0
12943 12:16:42.041667 [1mSubtest pipe-C-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12944 12:16:42.041726 <14>[ 28.487206] [IGT] kms_vblank: executing
12945 12:16:42.041784 IGT-Version: 1.2<14>[ 28.491996] [IGT] kms_vblank: exiting, ret=77
12946 12:16:42.041839 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12947 12:16:42.041895 Opened dev<8>[ 28.502534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip>
12948 12:16:42.041950 ice: /dev/dri/card0
12949 12:16:42.042004 No KMS driver or no outputs, pipes: 8, outputs: 0
12950 12:16:42.042058 [1mSubtest pipe-D-accuracy-idle: SKIP (0.000s)[0m
12951 12:16:42.042112 <14>[ 28.526052] [IGT] kms_vblank: executing
12952 12:16:42.042171 IGT-Version: 1.2<14>[ 28.530776] [IGT] kms_vblank: exiting, ret=77
12953 12:16:42.042225 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12954 12:16:42.042281 Opened device: /dev/dri/ca<8>[ 28.542028] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle RESULT=skip>
12955 12:16:42.042335 rd0
12956 12:16:42.042388 No KMS driver or no outputs, pipes: 8, outputs: 0
12957 12:16:42.042442 [1mSubtest pipe-D-query-idle: SKIP (0.000s)[0m
12958 12:16:42.042495 <14>[ 28.563038] [IGT] kms_vblank: executing
12959 12:16:42.042548 IGT-Version: 1.2<14>[ 28.567759] [IGT] kms_vblank: exiting, ret=77
12960 12:16:42.042602 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12961 12:16:42.042691 Opened device: /dev/dri/ca<8>[ 28.579341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip>
12962 12:16:42.042777 rd0
12963 12:16:42.042833 No KMS driver or no outputs, pipes: 8, outputs: 0
12964 12:16:42.042888 [1mSubtest pipe-D-query-idle-hang: SKIP (0.000s)[0m
12965 12:16:42.042942 <14>[ 28.601119] [IGT] kms_vblank: executing
12966 12:16:42.042997 IGT-Version: 1.2<14>[ 28.605818] [IGT] kms_vblank: exiting, ret=77
12967 12:16:42.043051 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12968 12:16:42.043106 Opened dev<8>[ 28.616851] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked RESULT=skip>
12969 12:16:42.043161 ice: /dev/dri/card0
12970 12:16:42.043214 No KMS driver or no outputs, pipes: 8, outputs: 0
12971 12:16:42.043269 [1mSubtest pipe-D-query-forked: SKIP (0.000s)[0m
12972 12:16:42.043322 <14>[ 28.639534] [IGT] kms_vblank: executing
12973 12:16:42.043377 IGT-Version: 1.2<14>[ 28.644331] [IGT] kms_vblank: exiting, ret=77
12974 12:16:42.043431 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12975 12:16:42.043486 Opened dev<8>[ 28.655382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip>
12976 12:16:42.043540 ice: /dev/dri/card0
12977 12:16:42.043593 No KMS driver or no outputs, pipes: 8, outputs: 0
12978 12:16:42.043647 [1mSubtest pipe-D-query-forked-hang: SKIP (0.000s)[0m
12979 12:16:42.043746 <14>[ 28.675688] [IGT] kms_vblank: executing
12980 12:16:42.043800 IGT-Version: 1.2<14>[ 28.680417] [IGT] kms_vblank: exiting, ret=77
12981 12:16:42.043854 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12982 12:16:42.043909 Opened device: /dev/dri/card0
12983 12:16:42.043962 No KMS driv<8>[ 28.693263] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy RESULT=skip>
12984 12:16:42.044017 er or no outputs, pipes: 8, outputs: 0
12985 12:16:42.044070 [1mSubtest pipe-D-query-busy: SKIP (0.000s)[0m
12986 12:16:42.044124 <14>[ 28.714923] [IGT] kms_vblank: executing
12987 12:16:42.044177 IGT-Version: 1.2<14>[ 28.719715] [IGT] kms_vblank: exiting, ret=77
12988 12:16:42.044230 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12989 12:16:42.044285 Opened device: /dev/dri/ca<8>[ 28.730949] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip>
12990 12:16:42.044340 rd0
12991 12:16:42.044392 No KMS driver or no outputs, pipes: 8, outputs: 0
12992 12:16:42.044446 [1mSubtest pipe-D-query-busy-hang: SKIP (0.000s)[0m
12993 12:16:42.044499 <14>[ 28.752657] [IGT] kms_vblank: executing
12994 12:16:42.044552 IGT-Version: 1.2<14>[ 28.757516] [IGT] kms_vblank: exiting, ret=77
12995 12:16:42.044605 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
12996 12:16:42.044660 Opened dev<8>[ 28.768144] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip>
12997 12:16:42.044715 ice: /dev/dri/card0
12998 12:16:42.044768 No KMS driver or no outputs, pipes: 8, outputs: 0
12999 12:16:42.044822 [1mSubtest pipe-D-query-forked-busy: SKIP (0.000s)[0m
13000 12:16:42.044875 <14>[ 28.788819] [IGT] kms_vblank: executing
13001 12:16:42.044929 IGT-Version: 1.2<14>[ 28.793689] [IGT] kms_vblank: exiting, ret=77
13002 12:16:42.044983 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13003 12:16:42.045038 Opened dev<8>[ 28.804838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip>
13004 12:16:42.045093 ice: /dev/dri/card0
13005 12:16:42.045147 No KMS driver or no outputs, pipes: 8, outputs: 0
13006 12:16:42.045201 [1mSubtest pipe-D-query-forked-busy-hang: SKIP (0.000s)[0m
13007 12:16:42.045254 <14>[ 28.825447] [IGT] kms_vblank: executing
13008 12:16:42.045308 IGT-Version: 1.2<14>[ 28.830221] [IGT] kms_vblank: exiting, ret=77
13009 12:16:42.045361 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13010 12:16:42.045416 Opened device: /dev/dri/ca<8>[ 28.842094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle RESULT=skip>
13011 12:16:42.045470 rd0
13012 12:16:42.045523 No KMS driver or no outputs, pipes: 8, outputs: 0
13013 12:16:42.045577 [1mSubtest pipe-D-wait-idle: SKIP (0.000s)[0m
13014 12:16:42.045806 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip
13016 12:16:42.045989 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle RESULT=skip
13018 12:16:42.046170 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip
13020 12:16:42.046351 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked RESULT=skip
13022 12:16:42.046532 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip
13024 12:16:42.046715 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy RESULT=skip
13026 12:16:42.046895 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip
13028 12:16:42.047074 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip
13030 12:16:42.047255 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip
13032 12:16:42.047434 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle RESULT=skip
13034 12:16:42.047623 <14>[ 28.862324] [IGT] kms_vblank: executing
13035 12:16:42.047726 IGT-Version: 1.2<14>[ 28.867110] [IGT] kms_vblank: exiting, ret=77
13036 12:16:42.047786 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13037 12:16:42.047844 Opened dev<8>[ 28.878134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip>
13038 12:16:42.047900 ice: /dev/dri/card0
13039 12:16:42.047955 No KMS driver or no outputs, pipes: 8, outputs: 0
13040 12:16:42.048010 [1mSubtest pipe-D-wait-idle-hang: SKIP (0.000s)[0m
13041 12:16:42.048065 <14>[ 28.900922] [IGT] kms_vblank: executing
13042 12:16:42.048123 IGT-Version: 1.2<14>[ 28.905680] [IGT] kms_vblank: exiting, ret=77
13043 12:16:42.048218 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13044 12:16:42.048274 Opened dev<8>[ 28.916790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked RESULT=skip>
13045 12:16:42.048328 ice: /dev/dri/card0
13046 12:16:42.048381 No KMS driver or no outputs, pipes: 8, outputs: 0
13047 12:16:42.048435 [1mSubtest pipe-D-wait-forked: SKIP (0.000s)[0m
13048 12:16:42.048490 <14>[ 28.936660] [IGT] kms_vblank: executing
13049 12:16:42.048544 IGT-Version: 1.2<14>[ 28.941607] [IGT] kms_vblank: exiting, ret=77
13050 12:16:42.048598 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13051 12:16:42.048652 Opened dev<8>[ 28.952363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip>
13052 12:16:42.048706 ice: /dev/dri/card0
13053 12:16:42.048759 No KMS driver or no outputs, pipes: 8, outputs: 0
13054 12:16:42.048813 [1mSubtest pipe-D-wait-forked-hang: SKIP (0.000s)[0m
13055 12:16:42.048867 <14>[ 28.972674] [IGT] kms_vblank: executing
13056 12:16:42.048921 IGT-Version: 1.2<14>[ 28.977503] [IGT] kms_vblank: exiting, ret=77
13057 12:16:42.048975 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13058 12:16:42.049029 Opened dev<8>[ 28.988317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy RESULT=skip>
13059 12:16:42.049085 ice: /dev/dri/card0
13060 12:16:42.049138 No KMS driver or no outputs, pipes: 8, outputs: 0
13061 12:16:42.049192 [1mSubtest pipe-D-wait-busy: SKIP (0.000s)[0m
13062 12:16:42.049245 <14>[ 29.008757] [IGT] kms_vblank: executing
13063 12:16:42.049298 IGT-Version: 1.2<14>[ 29.013601] [IGT] kms_vblank: exiting, ret=77
13064 12:16:42.049352 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13065 12:16:42.049406 Opened dev<8>[ 29.024437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip>
13066 12:16:42.049461 ice: /dev/dri/card0
13067 12:16:42.049513 No KMS driver or no outputs, pipes: 8, outputs: 0
13068 12:16:42.049567 [1mSubtest pipe-D-wait-busy-hang: SKIP (0.000s)[0m
13069 12:16:42.049620 <14>[ 29.044723] [IGT] kms_vblank: executing
13070 12:16:42.049674 IGT-Version: 1.2<14>[ 29.049638] [IGT] kms_vblank: exiting, ret=77
13071 12:16:42.049728 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13072 12:16:42.049783 Opened dev<8>[ 29.060456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip>
13073 12:16:42.049836 ice: /dev/dri/card0
13074 12:16:42.049889 No KMS driver or no outputs, pipes: 8, outputs: 0
13075 12:16:42.049943 [1mSubtest pipe-D-wait-forked-busy: SKIP (0.000s)[0m
13076 12:16:42.049996 <14>[ 29.083726] [IGT] kms_vblank: executing
13077 12:16:42.050049 IGT-Version: 1.2<14>[ 29.088477] [IGT] kms_vblank: exiting, ret=77
13078 12:16:42.050103 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13079 12:16:42.050199 Opened dev<8>[ 29.099261] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip>
13080 12:16:42.050254 ice: /dev/dri/card0
13081 12:16:42.050307 No KMS driver or no outputs, pipes: 8, outputs: 0
13082 12:16:42.050361 [1mSubtest pipe-D-wait-forked-busy-hang: SKIP (0.000s)[0m
13083 12:16:42.050415 <14>[ 29.120249] [IGT] kms_vblank: executing
13084 12:16:42.050468 IGT-Version: 1.2<14>[ 29.125013] [IGT] kms_vblank: exiting, ret=77
13085 12:16:42.050522 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13086 12:16:42.050576 Opened dev<8>[ 29.136161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip>
13087 12:16:42.050631 ice: /dev/dri/card0
13088 12:16:42.050683 No KMS driver or no outputs, pipes: 8, outputs: 0
13089 12:16:42.050737 [1mSubtest pipe-D-ts-continuation-idle: SKIP (0.000s)[0m
13090 12:16:42.050791 <14>[ 29.166320] [IGT] kms_vblank: executing
13091 12:16:42.050845 IGT-Version: 1.2<14>[ 29.171428] [IGT] kms_vblank: exiting, ret=77
13092 12:16:42.050898 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13093 12:16:42.050953 Opened dev<8>[ 29.182263] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip>
13094 12:16:42.051007 ice: /dev/dri/card0
13095 12:16:42.051059 No KMS driver or no outputs, pipes: 8, outputs: 0
13096 12:16:42.051113 [1mSubtest pipe-D-ts-continuation-idle-hang: SKIP (0.000s)[0m
13097 12:16:42.051167 <14>[ 29.204114] [IGT] kms_vblank: executing
13098 12:16:42.051220 IGT-Version: 1.2<14>[ 29.208931] [IGT] kms_vblank: exiting, ret=77
13099 12:16:42.051273 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13100 12:16:42.051328 Opened device: /dev/dri/ca<8>[ 29.220550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip>
13101 12:16:42.051382 rd0
13102 12:16:42.051435 No KMS driver or no outputs, pipes: 8, outputs: 0
13103 12:16:42.051489 [1mSubtest pipe-D-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13104 12:16:42.051543 <14>[ 29.242578] [IGT] kms_vblank: executing
13105 12:16:42.051790 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip
13107 12:16:42.051971 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked RESULT=skip
13109 12:16:42.052153 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip
13111 12:16:42.052335 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy RESULT=skip
13113 12:16:42.052514 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip
13115 12:16:42.052711 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip
13117 12:16:42.052895 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip
13119 12:16:42.053076 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip
13121 12:16:42.053254 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip
13123 12:16:42.053433 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip
13125 12:16:42.053621 IGT-Version: 1.2<14>[ 29.247401] [IGT] kms_vblank: exiting, ret=77
13126 12:16:42.053684 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13127 12:16:42.053743 Opened device: /dev/dri/ca<8>[ 29.259071] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip>
13128 12:16:42.053801 rd0
13129 12:16:42.053856 No KMS driver or no outputs, pipes: 8, outputs: 0
13130 12:16:42.053912 [1mSubtest pipe-D-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13131 12:16:42.053967 <14>[ 29.281117] [IGT] kms_vblank: executing
13132 12:16:42.054022 IGT-Version: 1.2<14>[ 29.285822] [IGT] kms_vblank: exiting, ret=77
13133 12:16:42.054076 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13134 12:16:42.054159 Opened dev<8>[ 29.296932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip>
13135 12:16:42.054275 ice: /dev/dri/card0
13136 12:16:42.054346 No KMS driver or no outputs, pipes: 8, outputs: 0
13137 12:16:42.054400 [1mSubtest pipe-D-ts-continuation-suspend: SKIP (0.000s)[0m
13138 12:16:42.054453 <14>[ 29.317827] [IGT] kms_vblank: executing
13139 12:16:42.054507 IGT-Version: 1.2<14>[ 29.322579] [IGT] kms_vblank: exiting, ret=77
13140 12:16:42.054561 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13141 12:16:42.054616 Opened device: /dev/dri/ca<8>[ 29.334486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip>
13142 12:16:42.054671 rd0
13143 12:16:42.054725 No KMS driver or no outputs, pipes: 8, outputs: 0
13144 12:16:42.054779 [1mSubtest pipe-D-ts-continuation-modeset: SKIP (0.000s)[0m
13145 12:16:42.054833 <14>[ 29.358979] [IGT] kms_vblank: executing
13146 12:16:42.054887 IGT-Version: 1.2<14>[ 29.363738] [IGT] kms_vblank: exiting, ret=77
13147 12:16:42.054940 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13148 12:16:42.054995 Opened device: /dev/dri/ca<8>[ 29.375300] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip>
13149 12:16:42.055049 rd0
13150 12:16:42.055102 No KMS driver or no outputs, pipes: 8, outputs: 0
13151 12:16:42.055156 [1mSubtest pipe-D-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13152 12:16:42.055210 <14>[ 29.397422] [IGT] kms_vblank: executing
13153 12:16:42.055263 IGT-Version: 1.2<14>[ 29.402190] [IGT] kms_vblank: exiting, ret=77
13154 12:16:42.055317 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13155 12:16:42.055372 Opened device: /dev/dri/ca<8>[ 29.413794] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip>
13156 12:16:42.055427 rd0
13157 12:16:42.055479 No KMS driver or no outputs, pipes: 8, outputs: 0
13158 12:16:42.055533 [1mSubtest pipe-D-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13159 12:16:42.055587 <14>[ 29.439338] [IGT] kms_vblank: executing
13160 12:16:42.055640 IGT-Version: 1.2<14>[ 29.444068] [IGT] kms_vblank: exiting, ret=77
13161 12:16:42.055727 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13162 12:16:42.055796 Opened dev<8>[ 29.454940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip>
13163 12:16:42.055851 ice: /dev/dri/card0
13164 12:16:42.055904 No KMS driver or no outputs, pipes: 8, outputs: 0
13165 12:16:42.055958 [1mSubtest pipe-E-accuracy-idle: SKIP (0.000s)[0m
13166 12:16:42.056011 <14>[ 29.475349] [IGT] kms_vblank: executing
13167 12:16:42.056063 IGT-Version: 1.2<14>[ 29.480123] [IGT] kms_vblank: exiting, ret=77
13168 12:16:42.056139 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13169 12:16:42.056209 Opened dev<8>[ 29.491014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle RESULT=skip>
13170 12:16:42.056262 ice: /dev/dri/card0
13171 12:16:42.056315 No KMS driver or no outputs, pipes: 8, outputs: 0
13172 12:16:42.056369 [1mSubtest pipe-E-query-idle: SKIP (0.000s)[0m
13173 12:16:42.056422 <14>[ 29.510925] [IGT] kms_vblank: executing
13174 12:16:42.056475 IGT-Version: 1.2<14>[ 29.515686] [IGT] kms_vblank: exiting, ret=77
13175 12:16:42.056528 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13176 12:16:42.056584 Opened dev<8>[ 29.526558] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip>
13177 12:16:42.056638 ice: /dev/dri/card0
13178 12:16:42.056690 No KMS driver or no outputs, pipes: 8, outputs: 0
13179 12:16:42.056744 [1mSubtest pipe-E-query-idle-hang: SKIP (0.000s)[0m
13180 12:16:42.056797 <14>[ 29.546976] [IGT] kms_vblank: executing
13181 12:16:42.056850 IGT-Version: 1.2<14>[ 29.551737] [IGT] kms_vblank: exiting, ret=77
13182 12:16:42.056904 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13183 12:16:42.056958 Opened dev<8>[ 29.562788] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked RESULT=skip>
13184 12:16:42.057012 ice: /dev/dri/card0
13185 12:16:42.057065 No KMS driver or no outputs, pipes: 8, outputs: 0
13186 12:16:42.057118 [1mSubtest pipe-E-query-forked: SKIP (0.000s)[0m
13187 12:16:42.057172 <14>[ 29.582626] [IGT] kms_vblank: executing
13188 12:16:42.057225 IGT-Version: 1.2<14>[ 29.587518] [IGT] kms_vblank: exiting, ret=77
13189 12:16:42.057278 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13190 12:16:42.057332 Opened device: /dev/dri/ca<8>[ 29.599081] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip>
13191 12:16:42.057386 rd0
13192 12:16:42.057440 No KMS driver or no outputs, pipes: 8, outputs: 0
13193 12:16:42.057494 [1mSubtest pipe-E-query-forked-hang: SKIP (0.000s)[0m
13194 12:16:42.057547 <14>[ 29.621619] [IGT] kms_vblank: executing
13195 12:16:42.057776 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip
13197 12:16:42.057958 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip
13199 12:16:42.058145 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip
13201 12:16:42.058368 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip
13203 12:16:42.058555 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip
13205 12:16:42.058739 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip
13207 12:16:42.058922 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle RESULT=skip
13209 12:16:42.059103 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip
13211 12:16:42.059283 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked RESULT=skip
13213 12:16:42.059463 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip
13215 12:16:42.059652 IGT-Version: 1.2<14>[ 29.626364] [IGT] kms_vblank: exiting, ret=77
13216 12:16:42.059794 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13217 12:16:42.059855 Opened dev<8>[ 29.637342] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy RESULT=skip>
13218 12:16:42.059914 ice: /dev/dri/card0
13219 12:16:42.059970 No KMS driver or no outputs, pipes: 8, outputs: 0
13220 12:16:42.060026 [1mSubtest pipe-E-query-busy: SKIP (0.000s)[0m
13221 12:16:42.060080 <14>[ 29.656806] [IGT] kms_vblank: executing
13222 12:16:42.060166 IGT-Version: 1.2<14>[ 29.661648] [IGT] kms_vblank: exiting, ret=77
13223 12:16:42.060236 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13224 12:16:42.060291 Opened dev<8>[ 29.672580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip>
13225 12:16:42.060346 ice: /dev/dri/card0
13226 12:16:42.060399 No KMS driver or no outputs, pipes: 8, outputs: 0
13227 12:16:42.060453 [1mSubtest pipe-E-query-busy-hang: SKIP (0.000s)[0m
13228 12:16:42.060506 <14>[ 29.692864] [IGT] kms_vblank: executing
13229 12:16:42.060560 IGT-Version: 1.2<14>[ 29.697619] [IGT] kms_vblank: exiting, ret=77
13230 12:16:42.060614 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13231 12:16:42.060670 Opened dev<8>[ 29.708393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip>
13232 12:16:42.060725 ice: /dev/dri/card0
13233 12:16:42.060778 No KMS driver or no outputs, pipes: 8, outputs: 0
13234 12:16:42.060832 [1mSubtest pipe-E-query-forked-busy: SKIP (0.000s)[0m
13235 12:16:42.060885 <14>[ 29.732103] [IGT] kms_vblank: executing
13236 12:16:42.060939 IGT-Version: 1.2<14>[ 29.736872] [IGT] kms_vblank: exiting, ret=77
13237 12:16:42.060992 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13238 12:16:42.061047 Opened dev<8>[ 29.747845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip>
13239 12:16:42.061101 ice: /dev/dri/card0
13240 12:16:42.061154 No KMS driver or no outputs, pipes: 8, outputs: 0
13241 12:16:42.061208 [1mSubtest pipe-E-query-forked-busy-hang: SKIP (0.000s)[0m
13242 12:16:42.061261 <14>[ 29.778291] [IGT] kms_vblank: executing
13243 12:16:42.061315 IGT-Version: 1.2<14>[ 29.783458] [IGT] kms_vblank: exiting, ret=77
13244 12:16:42.061368 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13245 12:16:42.061422 Opened dev<8>[ 29.794437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle RESULT=skip>
13246 12:16:42.061476 ice: /dev/dri/card0
13247 12:16:42.061529 No KMS driver or no outputs, pipes: 8, outputs: 0
13248 12:16:42.061582 [1mSubtest pipe-E-wait-idle: SKIP (0.000s)[0m
13249 12:16:42.061635 <14>[ 29.814764] [IGT] kms_vblank: executing
13250 12:16:42.061688 IGT-Version: 1.2<14>[ 29.819510] [IGT] kms_vblank: exiting, ret=77
13251 12:16:42.061740 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13252 12:16:42.061795 Opened dev<8>[ 29.830337] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip>
13253 12:16:42.061849 ice: /dev/dri/card0
13254 12:16:42.061901 No KMS driver or no outputs, pipes: 8, outputs: 0
13255 12:16:42.061954 [1mSubtest pipe-E-wait-idle-hang: SKIP (0.000s)[0m
13256 12:16:42.062008 <14>[ 29.850707] [IGT] kms_vblank: executing
13257 12:16:42.062062 IGT-Version: 1.2<14>[ 29.855465] [IGT] kms_vblank: exiting, ret=77
13258 12:16:42.062119 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13259 12:16:42.062175 Opened dev<8>[ 29.866668] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked RESULT=skip>
13260 12:16:42.062229 ice: /dev/dri/card0
13261 12:16:42.062282 No KMS driver or no outputs, pipes: 8, outputs: 0
13262 12:16:42.062336 [1mSubtest pipe-E-wait-forked: SKIP (0.000s)[0m
13263 12:16:42.062390 <14>[ 29.886736] [IGT] kms_vblank: executing
13264 12:16:42.062443 IGT-Version: 1.2<14>[ 29.891573] [IGT] kms_vblank: exiting, ret=77
13265 12:16:42.062496 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13266 12:16:42.062550 Opened dev<8>[ 29.902714] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip>
13267 12:16:42.062604 ice: /dev/dri/card0
13268 12:16:42.062657 No KMS driver or no outputs, pipes: 8, outputs: 0
13269 12:16:42.062711 [1mSubtest pipe-E-wait-forked-hang: SKIP (0.000s)[0m
13270 12:16:42.062764 <14>[ 29.923045] [IGT] kms_vblank: executing
13271 12:16:42.062817 IGT-Version: 1.2<14>[ 29.927821] [IGT] kms_vblank: exiting, ret=77
13272 12:16:42.062871 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13273 12:16:42.062924 Opened dev<8>[ 29.938954] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy RESULT=skip>
13274 12:16:42.062978 ice: /dev/dri/card0
13275 12:16:42.063031 No KMS driver or no outputs, pipes: 8, outputs: 0
13276 12:16:42.063085 [1mSubtest pipe-E-wait-busy: SKIP (0.000s)[0m
13277 12:16:42.063138 <14>[ 29.958544] [IGT] kms_vblank: executing
13278 12:16:42.063191 IGT-Version: 1.2<14>[ 29.963304] [IGT] kms_vblank: exiting, ret=77
13279 12:16:42.063244 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13280 12:16:42.063298 Opened dev<8>[ 29.974418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip>
13281 12:16:42.063351 ice: /dev/dri/card0
13282 12:16:42.063404 No KMS driver or no outputs, pipes: 8, outputs: 0
13283 12:16:42.063457 [1mSubtest pipe-E-wait-busy-hang: SKIP (0.000s)[0m
13284 12:16:42.063510 <14>[ 29.997053] [IGT] kms_vblank: executing
13285 12:16:42.063563 IGT-Version: 1.2<14>[ 30.001818] [IGT] kms_vblank: exiting, ret=77
13286 12:16:42.063616 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13287 12:16:42.063852 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy RESULT=skip
13289 12:16:42.064035 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip
13291 12:16:42.064222 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip
13293 12:16:42.893779 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip
13295 12:16:42.895645 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle RESULT=skip
13297 12:16:42.897389 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip
13299 12:16:42.899059 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked RESULT=skip
13301 12:16:42.900728 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip
13303 12:16:42.902367 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy RESULT=skip
13305 12:16:42.904004 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip
13307 12:16:42.905693 Opened dev<8>[ 30.012408] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip>
13308 12:16:42.906251 ice: /dev/dri/card0
13309 12:16:42.906763 No KMS driver or no outputs, pipes: 8, outputs: 0
13310 12:16:42.907273 [1mSubtest pipe-E-wait-forked-busy: SKIP (0.000s)[0m
13311 12:16:42.907799 <14>[ 30.033240] [IGT] kms_vblank: executing
13312 12:16:42.908304 IGT-Version: 1.2<14>[ 30.037995] [IGT] kms_vblank: exiting, ret=77
13313 12:16:42.908805 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13314 12:16:42.909322 Opened dev<8>[ 30.049032] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip>
13315 12:16:42.909827 ice: /dev/dri/card0
13316 12:16:42.910319 No KMS driver or no outputs, pipes: 8, outputs: 0
13317 12:16:42.910818 [1mSubtest pipe-E-wait-forked-busy-hang: SKIP (0.000s)[0m
13318 12:16:42.911316 <14>[ 30.069774] [IGT] kms_vblank: executing
13319 12:16:42.911858 IGT-Version: 1.2<14>[ 30.074530] [IGT] kms_vblank: exiting, ret=77
13320 12:16:42.912357 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13321 12:16:42.912866 Opened device: /dev/dri/ca<8>[ 30.085955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip>
13322 12:16:42.913368 rd0
13323 12:16:42.913862 No KMS driver or no outputs, pipes: 8, outputs: 0
13324 12:16:42.914363 [1mSubtest pipe-E-ts-continuation-idle: SKIP (0.000s)[0m
13325 12:16:42.914853 <14>[ 30.110693] [IGT] kms_vblank: executing
13326 12:16:42.915345 IGT-Version: 1.2<14>[ 30.115422] [IGT] kms_vblank: exiting, ret=77
13327 12:16:42.915858 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13328 12:16:42.916366 Opened dev<8>[ 30.126351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip>
13329 12:16:42.916861 ice: /dev/dri/card0
13330 12:16:42.917341 No KMS driver or no outputs, pipes: 8, outputs: 0
13331 12:16:42.917832 [1mSubtest pipe-E-ts-continuation-idle-hang: SKIP (0.000s)[0m
13332 12:16:42.918322 <14>[ 30.150930] [IGT] kms_vblank: executing
13333 12:16:42.918813 IGT-Version: 1.2<14>[ 30.155670] [IGT] kms_vblank: exiting, ret=77
13334 12:16:42.919234 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13335 12:16:42.919586 Opened dev<8>[ 30.166531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip>
13336 12:16:42.919984 ice: /dev/dri/card0
13337 12:16:42.920332 No KMS driver or no outputs, pipes: 8, outputs: 0
13338 12:16:42.920678 [1mSubtest pipe-E-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13339 12:16:42.921020 <14>[ 30.190552] [IGT] kms_vblank: executing
13340 12:16:42.921369 IGT-Version: 1.2<14>[ 30.195300] [IGT] kms_vblank: exiting, ret=77
13341 12:16:42.921713 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13342 12:16:42.922067 Opened dev<8>[ 30.206233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip>
13343 12:16:42.922421 ice: /dev/dri/card0
13344 12:16:42.922765 No KMS driver or no outputs, pipes: 8, outputs: 0
13345 12:16:42.923113 [1mSubtest pipe-E-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13346 12:16:42.923457 <14>[ 30.230755] [IGT] kms_vblank: executing
13347 12:16:42.923828 IGT-Version: 1.2<14>[ 30.235501] [IGT] kms_vblank: exiting, ret=77
13348 12:16:42.924154 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13349 12:16:42.924423 Opened dev<8>[ 30.245958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip>
13350 12:16:42.924687 ice: /dev/dri/card0
13351 12:16:42.924944 No KMS driver or no outputs, pipes: 8, outputs: 0
13352 12:16:42.925205 [1mSubtest pipe-E-ts-continuation-suspend: SKIP (0.000s)[0m
13353 12:16:42.925467 <14>[ 30.277936] [IGT] kms_vblank: executing
13354 12:16:42.925729 IGT-Version: 1.2<14>[ 30.283068] [IGT] kms_vblank: exiting, ret=77
13355 12:16:42.925990 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13356 12:16:42.926257 Opened device: /dev/dri/ca<8>[ 30.294315] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip>
13357 12:16:42.926520 rd0
13358 12:16:42.926789 No KMS driver or no outputs, pipes: 8, outputs: 0
13359 12:16:42.927053 [1mSubtest pipe-E-ts-continuation-modeset: SKIP (0.000s)[0m
13360 12:16:42.927316 <14>[ 30.319032] [IGT] kms_vblank: executing
13361 12:16:42.927580 IGT-Version: 1.2<14>[ 30.323743] [IGT] kms_vblank: exiting, ret=77
13362 12:16:42.927858 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13363 12:16:42.928131 Opened dev<8>[ 30.334886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip>
13364 12:16:42.928397 ice: /dev/dri/card0
13365 12:16:42.928658 No KMS driver or no outputs, pipes: 8, outputs: 0
13366 12:16:42.928918 [1mSubtest pipe-E-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13367 12:16:42.929159 <14>[ 30.356376] [IGT] kms_vblank: executing
13368 12:16:42.929369 IGT-Version: 1.2<14>[ 30.361232] [IGT] kms_vblank: exiting, ret=77
13369 12:16:42.929577 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13370 12:16:42.929793 Opened dev<8>[ 30.371950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip>
13371 12:16:42.930007 ice: /dev/dri/card0
13372 12:16:42.930193 No KMS driver or no outputs, pipes: 8, outputs: 0
13373 12:16:42.930362 [1mSubtest pipe-E-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13374 12:16:42.930528 <14>[ 30.393543] [IGT] kms_vblank: executing
13375 12:16:42.930690 IGT-Version: 1.2<14>[ 30.398302] [IGT] kms_vblank: exiting, ret=77
13376 12:16:42.930853 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13377 12:16:42.931281 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip
13379 12:16:42.931983 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip
13381 12:16:42.932475 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip
13383 12:16:42.932961 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip
13385 12:16:42.933576 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip
13387 12:16:42.934066 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip
13389 12:16:42.934471 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip
13391 12:16:42.934873 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip
13393 12:16:42.935274 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip
13395 12:16:42.935845 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip
13397 12:16:42.936311 Opened device: /dev/dri/ca<8>[ 30.409983] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip>
13398 12:16:42.936444 rd0
13399 12:16:42.936587 No KMS driver or no outputs, pipes: 8, outputs: 0
13400 12:16:42.936730 [1mSubtest pipe-F-accuracy-idle: SKIP (0.000s)[0m
13401 12:16:42.936869 <14>[ 30.433302] [IGT] kms_vblank: executing
13402 12:16:42.937043 IGT-Version: 1.2<14>[ 30.438077] [IGT] kms_vblank: exiting, ret=77
13403 12:16:42.937217 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13404 12:16:42.937394 Opened dev<8>[ 30.449119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle RESULT=skip>
13405 12:16:42.937567 ice: /dev/dri/card0
13406 12:16:42.937739 No KMS driver or no outputs, pipes: 8, outputs: 0
13407 12:16:42.937912 [1mSubtest pipe-F-query-idle: SKIP (0.000s)[0m
13408 12:16:42.938087 <14>[ 30.470892] [IGT] kms_vblank: executing
13409 12:16:42.938259 IGT-Version: 1.2<14>[ 30.475668] [IGT] kms_vblank: exiting, ret=77
13410 12:16:42.938429 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13411 12:16:42.938604 Opened dev<8>[ 30.486393] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip>
13412 12:16:42.938776 ice: /dev/dri/card0
13413 12:16:42.938945 No KMS driver or no outputs, pipes: 8, outputs: 0
13414 12:16:42.939085 [1mSubtest pipe-F-query-idle-hang: SKIP (0.000s)[0m
13415 12:16:42.939201 <14>[ 30.507240] [IGT] kms_vblank: executing
13416 12:16:42.939318 IGT-Version: 1.2<14>[ 30.511978] [IGT] kms_vblank: exiting, ret=77
13417 12:16:42.939464 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13418 12:16:42.939615 Opened device: /dev/dri/ca<8>[ 30.523445] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked RESULT=skip>
13419 12:16:42.939773 rd0
13420 12:16:42.939926 No KMS driver or no outputs, pipes: 8, outputs: 0
13421 12:16:42.940076 [1mSubtest pipe-F-query-forked: SKIP (0.000s)[0m
13422 12:16:42.940193 <14>[ 30.544920] [IGT] kms_vblank: executing
13423 12:16:42.940311 IGT-Version: 1.2<14>[ 30.549690] [IGT] kms_vblank: exiting, ret=77
13424 12:16:42.940458 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13425 12:16:42.940577 Opened device: /dev/dri/ca<8>[ 30.561495] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip>
13426 12:16:42.940726 rd0
13427 12:16:42.940841 No KMS driver or no outputs, pipes: 8, outputs: 0
13428 12:16:42.940959 [1mSubtest pipe-F-query-forked-hang: SKIP (0.000s)[0m
13429 12:16:42.941104 <14>[ 30.582612] [IGT] kms_vblank: executing
13430 12:16:42.941249 IGT-Version: 1.2<14>[ 30.587433] [IGT] kms_vblank: exiting, ret=77
13431 12:16:42.941364 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13432 12:16:42.941482 Opened dev<8>[ 30.598430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy RESULT=skip>
13433 12:16:42.941628 ice: /dev/dri/card0
13434 12:16:42.941743 No KMS driver or no outputs, pipes: 8, outputs: 0
13435 12:16:42.941889 [1mSubtest pipe-F-query-busy: SKIP (0.000s)[0m
13436 12:16:42.942005 <14>[ 30.620680] [IGT] kms_vblank: executing
13437 12:16:42.942125 IGT-Version: 1.2<14>[ 30.625592] [IGT] kms_vblank: exiting, ret=77
13438 12:16:42.942271 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13439 12:16:42.942420 Opened device: /dev/dri/ca<8>[ 30.636831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip>
13440 12:16:42.942537 rd0
13441 12:16:42.942651 No KMS driver or no outputs, pipes: 8, outputs: 0
13442 12:16:42.942797 [1mSubtest pipe-F-query-busy-hang: SKIP (0.000s)[0m
13443 12:16:42.942942 <14>[ 30.658122] [IGT] kms_vblank: executing
13444 12:16:42.943088 IGT-Version: 1.2<14>[ 30.662884] [IGT] kms_vblank: exiting, ret=77
13445 12:16:42.943234 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13446 12:16:42.943383 Opened device: /dev/dri/ca<8>[ 30.674128] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip>
13447 12:16:42.943529 rd0
13448 12:16:42.943683 No KMS driver or no outputs, pipes: 8, outputs: 0
13449 12:16:42.943833 [1mSubtest pipe-F-query-forked-busy: SKIP (0.000s)[0m
13450 12:16:42.943978 <14>[ 30.695741] [IGT] kms_vblank: executing
13451 12:16:42.944128 IGT-Version: 1.2<14>[ 30.700472] [IGT] kms_vblank: exiting, ret=77
13452 12:16:42.944256 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13453 12:16:42.944387 Opened device: /dev/dri/ca<8>[ 30.712352] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip>
13454 12:16:42.944516 rd0
13455 12:16:42.944642 No KMS driver or no outputs, pipes: 8, outputs: 0
13456 12:16:42.944770 [1mSubtest pipe-F-query-forked-busy-hang: SKIP (0.000s)[0m
13457 12:16:42.944872 <14>[ 30.733546] [IGT] kms_vblank: executing
13458 12:16:42.944974 IGT-Version: 1.2<14>[ 30.738370] [IGT] kms_vblank: exiting, ret=77
13459 12:16:42.945076 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13460 12:16:42.945180 Opened device: /dev/dri/ca<8>[ 30.750190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle RESULT=skip>
13461 12:16:42.945283 rd0
13462 12:16:42.945409 No KMS driver or no outputs, pipes: 8, outputs: 0
13463 12:16:42.945536 [1mSubtest pipe-F-wait-idle: SKIP (0.000s)[0m
13464 12:16:42.945662 <14>[ 30.770721] [IGT] kms_vblank: executing
13465 12:16:42.945789 IGT-Version: 1.2<14>[ 30.775456] [IGT] kms_vblank: exiting, ret=77
13466 12:16:42.945915 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13467 12:16:42.946045 Opened dev<8>[ 30.786535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip>
13468 12:16:42.946173 ice: /dev/dri/card0
13469 12:16:42.946491 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip
13471 12:16:42.946909 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle RESULT=skip
13473 12:16:42.947330 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip
13475 12:16:42.947761 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked RESULT=skip
13477 12:16:42.948067 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip
13479 12:16:42.948370 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy RESULT=skip
13481 12:16:42.948787 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip
13483 12:16:42.949168 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip
13485 12:16:42.949438 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip
13487 12:16:42.949781 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle RESULT=skip
13489 12:16:42.950152 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip
13491 12:16:42.950534 No KMS driver or no outputs, pipes: 8, outputs: 0
13492 12:16:42.950653 [1mSubtest pipe-F-wait-idle-hang: SKIP (0.000s)[0m
13493 12:16:42.950773 <14>[ 30.807143] [IGT] kms_vblank: executing
13494 12:16:42.950890 IGT-Version: 1.2<14>[ 30.811861] [IGT] kms_vblank: exiting, ret=77
13495 12:16:42.951009 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13496 12:16:42.951128 Opened device: /dev/dri/ca<8>[ 30.823411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked RESULT=skip>
13497 12:16:42.951245 rd0
13498 12:16:42.951359 No KMS driver or no outputs, pipes: 8, outputs: 0
13499 12:16:42.951475 [1mSubtest pipe-F-wait-forked: SKIP (0.000s)[0m
13500 12:16:42.951589 <14>[ 30.844583] [IGT] kms_vblank: executing
13501 12:16:42.951714 IGT-Version: 1.2<14>[ 30.849458] [IGT] kms_vblank: exiting, ret=77
13502 12:16:42.951830 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13503 12:16:42.951948 Opened dev<8>[ 30.860253] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip>
13504 12:16:42.952064 ice: /dev/dri/card0
13505 12:16:42.952177 No KMS driver or no outputs, pipes: 8, outputs: 0
13506 12:16:42.952292 [1mSubtest pipe-F-wait-forked-hang: SKIP (0.000s)[0m
13507 12:16:42.952406 <14>[ 30.880712] [IGT] kms_vblank: executing
13508 12:16:42.952520 IGT-Version: 1.2<14>[ 30.885587] [IGT] kms_vblank: exiting, ret=77
13509 12:16:42.952634 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13510 12:16:42.952750 Opened device: /dev/dri/ca<8>[ 30.897259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy RESULT=skip>
13511 12:16:42.952865 rd0
13512 12:16:42.952979 No KMS driver or no outputs, pipes: 8, outputs: 0
13513 12:16:42.953093 [1mSubtest pipe-F-wait-busy: SKIP (0.000s)[0m
13514 12:16:42.953206 <14>[ 30.917685] [IGT] kms_vblank: executing
13515 12:16:42.953319 IGT-Version: 1.2<14>[ 30.922493] [IGT] kms_vblank: exiting, ret=77
13516 12:16:42.953432 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13517 12:16:42.953548 Opened dev<8>[ 30.933715] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip>
13518 12:16:42.953661 ice: /dev/dri/card0
13519 12:16:42.953772 No KMS driver or no outputs, pipes: 8, outputs: 0
13520 12:16:42.953885 [1mSubtest pipe-F-wait-busy-hang: SKIP (0.000s)[0m
13521 12:16:42.954000 <14>[ 30.953575] [IGT] kms_vblank: executing
13522 12:16:42.954116 IGT-Version: 1.2<14>[ 30.958351] [IGT] kms_vblank: exiting, ret=77
13523 12:16:42.954218 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13524 12:16:42.954323 Opened dev<8>[ 30.969339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip>
13525 12:16:42.954425 ice: /dev/dri/card0
13526 12:16:42.954527 No KMS driver or no outputs, pipes: 8, outputs: 0
13527 12:16:42.954629 [1mSubtest pipe-F-wait-forked-busy: SKIP (0.000s)[0m
13528 12:16:42.954737 <14>[ 30.989567] [IGT] kms_vblank: executing
13529 12:16:42.954842 IGT-Version: 1.2<14>[ 30.994364] [IGT] kms_vblank: exiting, ret=77
13530 12:16:42.954944 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13531 12:16:42.955050 Opened dev<8>[ 31.005477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip>
13532 12:16:42.955153 ice: /dev/dri/card0
13533 12:16:42.955254 No KMS driver or no outputs, pipes: 8, outputs: 0
13534 12:16:42.955357 [1mSubtest pipe-F-wait-forked-busy-hang: SKIP (0.000s)[0m
13535 12:16:42.955458 <14>[ 31.026113] [IGT] kms_vblank: executing
13536 12:16:42.955559 IGT-Version: 1.2<14>[ 31.030852] [IGT] kms_vblank: exiting, ret=77
13537 12:16:42.955661 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13538 12:16:42.955774 Opened device: /dev/dri/ca<8>[ 31.042114] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip>
13539 12:16:42.955877 rd0
13540 12:16:42.955977 No KMS driver or no outputs, pipes: 8, outputs: 0
13541 12:16:42.956091 [1mSubtest pipe-F-ts-continuation-idle: SKIP (0.000s)[0m
13542 12:16:42.956202 <14>[ 31.064035] [IGT] kms_vblank: executing
13543 12:16:42.956301 IGT-Version: 1.2<14>[ 31.068738] [IGT] kms_vblank: exiting, ret=77
13544 12:16:42.956395 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13545 12:16:42.956493 Opened dev<8>[ 31.079832] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip>
13546 12:16:42.956586 ice: /dev/dri/card0
13547 12:16:42.956678 No KMS driver or no outputs, pipes: 8, outputs: 0
13548 12:16:42.956772 [1mSubtest pipe-F-ts-continuation-idle-hang: SKIP (0.000s)[0m
13549 12:16:42.956864 <14>[ 31.103976] [IGT] kms_vblank: executing
13550 12:16:42.956957 IGT-Version: 1.2<14>[ 31.108749] [IGT] kms_vblank: exiting, ret=77
13551 12:16:42.957049 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13552 12:16:42.957146 Opened dev<8>[ 31.119741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip>
13553 12:16:42.957238 ice: /dev/dri/card0
13554 12:16:42.957329 No KMS driver or no outputs, pipes: 8, outputs: 0
13555 12:16:42.957422 [1mSubtest pipe-F-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13556 12:16:42.957514 <14>[ 31.150245] [IGT] kms_vblank: executing
13557 12:16:42.957606 IGT-Version: 1.2<14>[ 31.155642] [IGT] kms_vblank: exiting, ret=77
13558 12:16:42.957698 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13559 12:16:42.957794 Opened device: /dev/dri/ca<8>[ 31.166707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip>
13560 12:16:42.957886 rd0
13561 12:16:42.957978 No KMS driver or no outputs, pipes: 8, outputs: 0
13562 12:16:42.958251 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked RESULT=skip
13564 12:16:42.958563 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip
13566 12:16:42.958875 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy RESULT=skip
13568 12:16:42.959185 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip
13570 12:16:42.959467 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip
13572 12:16:42.959760 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip
13574 12:16:42.960044 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip
13576 12:16:42.960324 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip
13578 12:16:42.960604 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip
13580 12:16:42.960887 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip
13582 12:16:42.961179 [1mSubtest pipe-F-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13583 12:16:42.961270 <14>[ 31.192089] [IGT] kms_vblank: executing
13584 12:16:42.961359 IGT-Version: 1.2<14>[ 31.196824] [IGT] kms_vblank: exiting, ret=77
13585 12:16:42.961445 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13586 12:16:42.961534 Opened dev<8>[ 31.208020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip>
13587 12:16:42.961620 ice: /dev/dri/card0
13588 12:16:42.961704 No KMS driver or no outputs, pipes: 8, outputs: 0
13589 12:16:42.961790 [1mSubtest pipe-F-ts-continuation-suspend: SKIP (0.000s)[0m
13590 12:16:42.961874 <14>[ 31.231978] [IGT] kms_vblank: executing
13591 12:16:42.961959 IGT-Version: 1.2<14>[ 31.236737] [IGT] kms_vblank: exiting, ret=77
13592 12:16:42.962043 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13593 12:16:42.962130 Opened dev<8>[ 31.247648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip>
13594 12:16:42.962215 ice: /dev/dri/card0
13595 12:16:42.962298 No KMS driver or no outputs, pipes: 8, outputs: 0
13596 12:16:42.962382 [1mSubtest pipe-F-ts-continuation-modeset: SKIP (0.000s)[0m
13597 12:16:42.962466 <14>[ 31.269256] [IGT] kms_vblank: executing
13598 12:16:42.962550 IGT-Version: 1.2<14>[ 31.274008] [IGT] kms_vblank: exiting, ret=77
13599 12:16:42.962634 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13600 12:16:42.962721 Opened dev<8>[ 31.284991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip>
13601 12:16:42.962804 ice: /dev/dri/card0
13602 12:16:42.962887 No KMS driver or no outputs, pipes: 8, outputs: 0
13603 12:16:42.962972 [1mSubtest pipe-F-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13604 12:16:42.963055 <14>[ 31.306436] [IGT] kms_vblank: executing
13605 12:16:42.963139 IGT-Version: 1.2<14>[ 31.311255] [IGT] kms_vblank: exiting, ret=77
13606 12:16:42.963223 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13607 12:16:42.963311 Opened device: /dev/dri/ca<8>[ 31.323775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip>
13608 12:16:42.963394 rd0
13609 12:16:42.963477 No KMS driver or no outputs, pipes: 8, outputs: 0
13610 12:16:42.963561 [1mSubtest pipe-F-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13611 12:16:42.963645 <14>[ 31.345853] [IGT] kms_vblank: executing
13612 12:16:42.963737 IGT-Version: 1.2<14>[ 31.350597] [IGT] kms_vblank: exiting, ret=77
13613 12:16:42.963822 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13614 12:16:42.963909 Opened dev<8>[ 31.361786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip>
13615 12:16:42.963992 ice: /dev/dri/card0
13616 12:16:42.964088 No KMS driver or no outputs, pipes: 8, outputs: 0
13617 12:16:42.964171 [1mSubtest pipe-G-accuracy-idle: SKIP (0.000s)[0m
13618 12:16:42.964252 <14>[ 31.382059] [IGT] kms_vblank: executing
13619 12:16:42.964334 IGT-Version: 1.2<14>[ 31.386775] [IGT] kms_vblank: exiting, ret=77
13620 12:16:42.964416 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13621 12:16:42.964501 Opened device: /dev/dri/ca<8>[ 31.398448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle RESULT=skip>
13622 12:16:42.964583 rd0
13623 12:16:42.964664 No KMS driver or no outputs, pipes: 8, outputs: 0
13624 12:16:42.964746 [1mSubtest pipe-G-query-idle: SKIP (0.000s)[0m
13625 12:16:42.964827 <14>[ 31.419114] [IGT] kms_vblank: executing
13626 12:16:42.964909 IGT-Version: 1.2<14>[ 31.423892] [IGT] kms_vblank: exiting, ret=77
13627 12:16:42.964990 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13628 12:16:42.965075 Opened device: /dev/dri/ca<8>[ 31.435995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip>
13629 12:16:42.965157 rd0
13630 12:16:42.965237 No KMS driver or no outputs, pipes: 8, outputs: 0
13631 12:16:42.965319 [1mSubtest pipe-G-query-idle-hang: SKIP (0.000s)[0m
13632 12:16:42.965401 <14>[ 31.456739] [IGT] kms_vblank: executing
13633 12:16:42.965483 IGT-Version: 1.2<14>[ 31.461710] [IGT] kms_vblank: exiting, ret=77
13634 12:16:42.965564 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13635 12:16:42.965650 Opened device: /dev/dri/ca<8>[ 31.473116] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked RESULT=skip>
13636 12:16:42.965731 rd0
13637 12:16:42.965812 No KMS driver or no outputs, pipes: 8, outputs: 0
13638 12:16:42.965894 [1mSubtest pipe-G-query-forked: SKIP (0.000s)[0m
13639 12:16:42.965975 <14>[ 31.493999] [IGT] kms_vblank: executing
13640 12:16:42.966057 IGT-Version: 1.2<14>[ 31.498738] [IGT] kms_vblank: exiting, ret=77
13641 12:16:42.966139 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13642 12:16:42.966224 Opened device: /dev/dri/ca<8>[ 31.510755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip>
13643 12:16:42.966305 rd0
13644 12:16:42.966386 No KMS driver or no outputs, pipes: 8, outputs: 0
13645 12:16:42.966468 [1mSubtest pipe-G-query-forked-hang: SKIP (0.000s)[0m
13646 12:16:42.966549 <14>[ 31.535171] [IGT] kms_vblank: executing
13647 12:16:42.966631 IGT-Version: 1.2<14>[ 31.539900] [IGT] kms_vblank: exiting, ret=77
13648 12:16:42.966713 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13649 12:16:42.966797 Opened dev<8>[ 31.551101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy RESULT=skip>
13650 12:16:42.966879 ice: /dev/dri/card0
13651 12:16:42.966960 No KMS driver or no outputs, pipes: 8, outputs: 0
13652 12:16:42.967219 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip
13654 12:16:42.967495 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip
13656 12:16:42.967788 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip
13658 12:16:42.967969 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip
13660 12:16:42.968192 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip
13662 12:16:42.968372 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle RESULT=skip
13664 12:16:42.968550 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip
13666 12:16:42.968727 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked RESULT=skip
13668 12:16:42.968905 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip
13670 12:16:42.969083 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy RESULT=skip
13672 12:16:42.969273 [1mSubtest pipe-G-query-busy: SKIP (0.000s)[0m
13673 12:16:42.969336 <14>[ 31.570538] [IGT] kms_vblank: executing
13674 12:16:42.969394 IGT-Version: 1.2<14>[ 31.575277] [IGT] kms_vblank: exiting, ret=77
13675 12:16:42.969452 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13676 12:16:42.969509 Opened device: /dev/dri/ca<8>[ 31.586636] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip>
13677 12:16:42.969564 rd0
13678 12:16:42.969618 No KMS driver or no outputs, pipes: 8, outputs: 0
13679 12:16:42.969673 [1mSubtest pipe-G-query-busy-hang: SKIP (0.000s)[0m
13680 12:16:42.969727 <14>[ 31.611074] [IGT] kms_vblank: executing
13681 12:16:42.969780 IGT-Version: 1.2<14>[ 31.615807] [IGT] kms_vblank: exiting, ret=77
13682 12:16:42.969833 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13683 12:16:42.969888 Opened dev<8>[ 31.626583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip>
13684 12:16:42.969942 ice: /dev/dri/card0
13685 12:16:42.969995 No KMS driver or no outputs, pipes: 8, outputs: 0
13686 12:16:42.970048 [1mSubtest pipe-G-query-forked-busy: SKIP (0.000s)[0m
13687 12:16:42.970102 <14>[ 31.650626] [IGT] kms_vblank: executing
13688 12:16:42.970155 IGT-Version: 1.2<14>[ 31.655363] [IGT] kms_vblank: exiting, ret=77
13689 12:16:42.970208 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13690 12:16:42.970262 Opened device: /dev/dri/ca<8>[ 31.666989] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip>
13691 12:16:42.970316 rd0
13692 12:16:42.970367 No KMS driver or no outputs, pipes: 8, outputs: 0
13693 12:16:42.970421 [1mSubtest pipe-G-query-forked-busy-hang: SKIP (0.000s)[0m
13694 12:16:42.970474 <14>[ 31.698071] [IGT] kms_vblank: executing
13695 12:16:42.970527 IGT-Version: 1.2<14>[ 31.703238] [IGT] kms_vblank: exiting, ret=77
13696 12:16:42.970580 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13697 12:16:42.970633 Opened device: /dev/dri/ca<8>[ 31.714377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle RESULT=skip>
13698 12:16:42.970687 rd0
13699 12:16:42.970739 No KMS driver or no outputs, pipes: 8, outputs: 0
13700 12:16:42.970792 [1mSubtest pipe-G-wait-idle: SKIP (0.000s)[0m
13701 12:16:42.970845 <14>[ 31.736243] [IGT] kms_vblank: executing
13702 12:16:42.970897 IGT-Version: 1.2<14>[ 31.741042] [IGT] kms_vblank: exiting, ret=77
13703 12:16:42.970950 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13704 12:16:42.971004 Opened dev<8>[ 31.751978] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip>
13705 12:16:42.971072 ice: /dev/dri/card0
13706 12:16:42.971126 No KMS driver or no outputs, pipes: 8, outputs: 0
13707 12:16:42.971179 [1mSubtest pipe-G-wait-idle-hang: SKIP (0.000s)[0m
13708 12:16:42.971232 <14>[ 31.772098] [IGT] kms_vblank: executing
13709 12:16:42.971285 IGT-Version: 1.2<14>[ 31.776811] [IGT] kms_vblank: exiting, ret=77
13710 12:16:42.971338 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13711 12:16:42.971391 Opened dev<8>[ 31.787919] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked RESULT=skip>
13712 12:16:42.971445 ice: /dev/dri/card0
13713 12:16:42.971496 No KMS driver or no outputs, pipes: 8, outputs: 0
13714 12:16:42.971549 [1mSubtest pipe-G-wait-forked: SKIP (0.000s)[0m
13715 12:16:42.971601 <14>[ 31.807968] [IGT] kms_vblank: executing
13716 12:16:42.971654 IGT-Version: 1.2<14>[ 31.812707] [IGT] kms_vblank: exiting, ret=77
13717 12:16:42.971755 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13718 12:16:42.971810 Opened dev<8>[ 31.823640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip>
13719 12:16:42.971864 ice: /dev/dri/card0
13720 12:16:42.971915 No KMS driver or no outputs, pipes: 8, outputs: 0
13721 12:16:42.971968 [1mSubtest pipe-G-wait-forked-hang: SKIP (0.000s)[0m
13722 12:16:42.972020 <14>[ 31.843981] [IGT] kms_vblank: executing
13723 12:16:42.972072 IGT-Version: 1.2<14>[ 31.848673] [IGT] kms_vblank: exiting, ret=77
13724 12:16:42.972125 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13725 12:16:42.972179 Opened dev<8>[ 31.859750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy RESULT=skip>
13726 12:16:42.972233 ice: /dev/dri/card0
13727 12:16:42.972285 No KMS driver or no outputs, pipes: 8, outputs: 0
13728 12:16:42.972338 [1mSubtest pipe-G-wait-busy: SKIP (0.000s)[0m
13729 12:16:42.972390 <14>[ 31.879778] [IGT] kms_vblank: executing
13730 12:16:42.972442 IGT-Version: 1.2<14>[ 31.884527] [IGT] kms_vblank: exiting, ret=77
13731 12:16:42.972495 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13732 12:16:42.972549 Opened device: /dev/dri/ca<8>[ 31.896439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip>
13733 12:16:42.972602 rd0
13734 12:16:42.972654 No KMS driver or no outputs, pipes: 8, outputs: 0
13735 12:16:42.972707 [1mSubtest pipe-G-wait-busy-hang: SKIP (0.000s)[0m
13736 12:16:42.972760 <14>[ 31.916973] [IGT] kms_vblank: executing
13737 12:16:42.972812 IGT-Version: 1.2<14>[ 31.921688] [IGT] kms_vblank: exiting, ret=77
13738 12:16:42.972865 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13739 12:16:42.972919 Opened dev<8>[ 31.932562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip>
13740 12:16:42.972971 ice: /dev/dri/card0
13741 12:16:42.973023 No KMS driver or no outputs, pipes: 8, outputs: 0
13742 12:16:42.973076 [1mSubtest pipe-G-wait-forked-busy: SKIP (0.000s)[0m
13743 12:16:42.973128 <14>[ 31.955913] [IGT] kms_vblank: executing
13744 12:16:42.973356 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip
13746 12:16:42.973539 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip
13748 12:16:42.973718 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip
13750 12:16:42.973899 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle RESULT=skip
13752 12:16:42.974078 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip
13754 12:16:42.974257 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked RESULT=skip
13756 12:16:42.974435 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip
13758 12:16:42.974614 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy RESULT=skip
13760 12:16:42.974794 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip
13762 12:16:42.974972 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip
13764 12:16:42.975173 IGT-Version: 1.2<14>[ 31.960658] [IGT] kms_vblank: exiting, ret=77
13765 12:16:42.975239 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13766 12:16:42.975300 Opened dev<8>[ 31.971683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip>
13767 12:16:42.975357 ice: /dev/dri/card0
13768 12:16:42.975413 No KMS driver or no outputs, pipes: 8, outputs: 0
13769 12:16:42.975468 [1mSubtest pipe-G-wait-forked-busy-hang: SKIP (0.000s)[0m
13770 12:16:42.975523 <14>[ 31.992877] [IGT] kms_vblank: executing
13771 12:16:42.975576 IGT-Version: 1.2<14>[ 31.997685] [IGT] kms_vblank: exiting, ret=77
13772 12:16:42.975629 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13773 12:16:42.975729 Opened device: /dev/dri/ca<8>[ 32.009507] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip>
13774 12:16:42.975785 rd0
13775 12:16:42.975838 No KMS driver or no outputs, pipes: 8, outputs: 0
13776 12:16:42.975892 [1mSubtest pipe-G-ts-continuation-idle: SKIP (0.000s)[0m
13777 12:16:42.975946 <14>[ 32.031011] [IGT] kms_vblank: executing
13778 12:16:42.975999 IGT-Version: 1.2<14>[ 32.035762] [IGT] kms_vblank: exiting, ret=77
13779 12:16:42.976052 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13780 12:16:42.976106 Opened device: /dev/dri/card0
13781 12:16:42.976159 No KMS driver or no outputs, pipes: 8, outputs: 0
13782 12:16:42.976212 [1mSubt<8>[ 32.053263] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip>
13783 12:16:42.976266 est pipe-G-ts-continuation-idle-hang: SKIP (0.000s)[0m
13784 12:16:42.976319 <14>[ 32.089213] [IGT] kms_vblank: executing
13785 12:16:42.976372 IGT-Version: 1.2<14>[ 32.094275] [IGT] kms_vblank: exiting, ret=77
13786 12:16:42.976425 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13787 12:16:42.976478 Opened device: /dev/dri/ca<8>[ 32.105854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip>
13788 12:16:42.976532 rd0
13789 12:16:42.976584 No KMS driver or no outputs, pipes: 8, outputs: 0
13790 12:16:42.976638 [1mSubtest pipe-G-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13791 12:16:42.976690 <14>[ 32.138373] [IGT] kms_vblank: executing
13792 12:16:42.976743 IGT-Version: 1.2<14>[ 32.143458] [IGT] kms_vblank: exiting, ret=77
13793 12:16:42.976796 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13794 12:16:42.976850 Opened device: /dev/dri/ca<8>[ 32.154683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip>
13795 12:16:42.976903 rd0
13796 12:16:42.976955 No KMS driver or no outputs, pipes: 8, outputs: 0
13797 12:16:42.977008 [1mSubtest pipe-G-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13798 12:16:42.977060 <14>[ 32.180077] [IGT] kms_vblank: executing
13799 12:16:42.977112 IGT-Version: 1.2<14>[ 32.184843] [IGT] kms_vblank: exiting, ret=77
13800 12:16:42.977165 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13801 12:16:42.977218 Opened dev<8>[ 32.195372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip>
13802 12:16:42.977271 ice: /dev/dri/card0
13803 12:16:42.977323 No KMS driver or no outputs, pipes: 8, outputs: 0
13804 12:16:42.977375 [1mSubtest pipe-G-ts-continuation-suspend: SKIP (0.000s)[0m
13805 12:16:42.977428 <14>[ 32.227263] [IGT] kms_vblank: executing
13806 12:16:42.977480 IGT-Version: 1.2<14>[ 32.232401] [IGT] kms_vblank: exiting, ret=77
13807 12:16:42.977532 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13808 12:16:42.977586 Opened dev<8>[ 32.243400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip>
13809 12:16:42.977639 ice: /dev/dri/card0
13810 12:16:42.977690 No KMS driver or no outputs, pipes: 8, outputs: 0
13811 12:16:42.977743 [1mSubtest pipe-G-ts-continuation-modeset: SKIP (0.000s)[0m
13812 12:16:42.977795 <14>[ 32.264651] [IGT] kms_vblank: executing
13813 12:16:42.977847 IGT-Version: 1.2<14>[ 32.269571] [IGT] kms_vblank: exiting, ret=77
13814 12:16:42.977898 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13815 12:16:42.977952 Opened dev<8>[ 32.280427] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip>
13816 12:16:42.978005 ice: /dev/dri/card0
13817 12:16:42.978057 No KMS driver or no outputs, pipes: 8, outputs: 0
13818 12:16:42.978110 [1mSubtest pipe-G-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13819 12:16:42.978162 <14>[ 32.301792] [IGT] kms_vblank: executing
13820 12:16:42.978214 IGT-Version: 1.2<14>[ 32.306778] [IGT] kms_vblank: exiting, ret=77
13821 12:16:42.978266 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13822 12:16:42.978319 Opened device: /dev/dri/ca<8>[ 32.318454] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip>
13823 12:16:42.978372 rd0
13824 12:16:42.978424 No KMS driver or no outputs, pipes: 8, outputs: 0
13825 12:16:42.978477 [1mSubtest pipe-G-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13826 12:16:42.978530 <14>[ 32.344209] [IGT] kms_vblank: executing
13827 12:16:42.978583 IGT-Version: 1.2<14>[ 32.349082] [IGT] kms_vblank: exiting, ret=77
13828 12:16:42.978635 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13829 12:16:42.978689 Opened dev<8>[ 32.360204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip>
13830 12:16:42.978743 ice: /dev/dri/card0
13831 12:16:42.978794 No KMS driver or no outputs, pipes: 8, outputs: 0
13832 12:16:42.978847 [1mSubtest pipe-H-accuracy-idle: SKIP (0.000s)[0m
13833 12:16:42.979074 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip
13835 12:16:42.979252 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip
13837 12:16:42.979429 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip
13839 12:16:42.979609 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip
13841 12:16:42.979838 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip
13843 12:16:42.980017 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip
13845 12:16:42.980194 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip
13847 12:16:42.980371 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip
13849 12:16:42.980546 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip
13851 12:16:42.980721 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip
13853 12:16:42.980920 <14>[ 32.380480] [IGT] kms_vblank: executing
13854 12:16:42.980983 IGT-Version: 1.2<14>[ 32.385345] [IGT] kms_vblank: exiting, ret=77
13855 12:16:42.981041 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13856 12:16:42.981098 Opened dev<8>[ 32.396210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle RESULT=skip>
13857 12:16:42.981155 ice: /dev/dri/card0
13858 12:16:42.981209 No KMS driver or no outputs, pipes: 8, outputs: 0
13859 12:16:42.981263 [1mSubtest pipe-H-query-idle: SKIP (0.000s)[0m
13860 12:16:42.981316 <14>[ 32.416083] [IGT] kms_vblank: executing
13861 12:16:42.981369 IGT-Version: 1.2<14>[ 32.420804] [IGT] kms_vblank: exiting, ret=77
13862 12:16:42.981423 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13863 12:16:42.981477 Opened dev<8>[ 32.431968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip>
13864 12:16:42.981530 ice: /dev/dri/card0
13865 12:16:42.981581 No KMS driver or no outputs, pipes: 8, outputs: 0
13866 12:16:42.981634 [1mSubtest pipe-H-query-idle-hang: SKIP (0.000s)[0m
13867 12:16:42.981687 <14>[ 32.452329] [IGT] kms_vblank: executing
13868 12:16:42.981739 IGT-Version: 1.2<14>[ 32.457131] [IGT] kms_vblank: exiting, ret=77
13869 12:16:42.981791 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13870 12:16:42.981845 Opened dev<8>[ 32.468206] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked RESULT=skip>
13871 12:16:42.981898 ice: /dev/dri/card0
13872 12:16:42.981950 No KMS driver or no outputs, pipes: 8, outputs: 0
13873 12:16:42.982002 [1mSubtest pipe-H-query-forked: SKIP (0.000s)[0m
13874 12:16:42.982054 <14>[ 32.488091] [IGT] kms_vblank: executing
13875 12:16:42.982106 IGT-Version: 1.2<14>[ 32.492836] [IGT] kms_vblank: exiting, ret=77
13876 12:16:42.982159 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13877 12:16:42.982212 Opened device: /dev/dri/ca<8>[ 32.504722] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip>
13878 12:16:42.982265 rd0
13879 12:16:42.982317 No KMS driver or no outputs, pipes: 8, outputs: 0
13880 12:16:42.982369 [1mSubtest pipe-H-query-forked-hang: SKIP (0.000s)[0m
13881 12:16:42.982421 <14>[ 32.525730] [IGT] kms_vblank: executing
13882 12:16:42.982473 IGT-Version: 1.2<14>[ 32.530515] [IGT] kms_vblank: exiting, ret=77
13883 12:16:42.982525 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13884 12:16:42.982578 Opened dev<8>[ 32.541646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy RESULT=skip>
13885 12:16:42.982631 ice: /dev/dri/card0
13886 12:16:42.982683 No KMS driver or no outputs, pipes: 8, outputs: 0
13887 12:16:42.982735 [1mSubtest pipe-H-query-busy: SKIP (0.000s)[0m
13888 12:16:42.982786 <14>[ 32.560805] [IGT] kms_vblank: executing
13889 12:16:42.982839 IGT-Version: 1.2<14>[ 32.565640] [IGT] kms_vblank: exiting, ret=77
13890 12:16:42.982891 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13891 12:16:42.982944 Opened device: /dev/dri/ca<8>[ 32.577476] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip>
13892 12:16:42.982997 rd0
13893 12:16:42.983048 No KMS driver or no outputs, pipes: 8, outputs: 0
13894 12:16:42.983101 [1mSubtest pipe-H-query-busy-hang: SKIP (0.000s)[0m
13895 12:16:42.983153 <14>[ 32.598535] [IGT] kms_vblank: executing
13896 12:16:42.983204 IGT-Version: 1.2<14>[ 32.603275] [IGT] kms_vblank: exiting, ret=77
13897 12:16:42.983257 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13898 12:16:42.983310 Opened device: /dev/dri/ca<8>[ 32.615139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip>
13899 12:16:42.983363 rd0
13900 12:16:42.983414 No KMS driver or no outputs, pipes: 8, outputs: 0
13901 12:16:42.983466 [1mSubtest pipe-H-query-forked-busy: SKIP (0.000s)[0m
13902 12:16:42.983518 <14>[ 32.636360] [IGT] kms_vblank: executing
13903 12:16:42.983570 IGT-Version: 1.2<14>[ 32.641204] [IGT] kms_vblank: exiting, ret=77
13904 12:16:42.983622 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13905 12:16:42.983683 Opened dev<8>[ 32.652123] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip>
13906 12:16:42.983777 ice: /dev/dri/card0
13907 12:16:42.983828 No KMS driver or no outputs, pipes: 8, outputs: 0
13908 12:16:42.983880 [1mSubtest pipe-H-query-forked-busy-hang: SKIP (0.000s)[0m
13909 12:16:42.983932 <14>[ 32.672852] [IGT] kms_vblank: executing
13910 12:16:42.983985 IGT-Version: 1.2<14>[ 32.677661] [IGT] kms_vblank: exiting, ret=77
13911 12:16:42.984037 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13912 12:16:42.984090 Opened device: /dev/dri/ca<8>[ 32.689586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle RESULT=skip>
13913 12:16:42.984143 rd0
13914 12:16:42.984195 No KMS driver or no outputs, pipes: 8, outputs: 0
13915 12:16:42.984247 [1mSubtest pipe-H-wait-idle: SKIP (0.000s)[0m
13916 12:16:42.984298 <14>[ 32.709699] [IGT] kms_vblank: executing
13917 12:16:42.984350 IGT-Version: 1.2<14>[ 32.714495] [IGT] kms_vblank: exiting, ret=77
13918 12:16:42.984403 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13919 12:16:42.984456 Opened device: /dev/dri/ca<8>[ 32.726683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip>
13920 12:16:42.984509 rd0
13921 12:16:42.984561 No KMS driver or no outputs, pipes: 8, outputs: 0
13922 12:16:42.984613 [1mSubtest pipe-H-wait-idle-hang: SKIP (0.000s)[0m
13923 12:16:42.984665 <14>[ 32.747575] [IGT] kms_vblank: executing
13924 12:16:42.984717 IGT-Version: 1.2<14>[ 32.752439] [IGT] kms_vblank: exiting, ret=77
13925 12:16:42.984944 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle RESULT=skip
13927 12:16:42.985121 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip
13929 12:16:42.985300 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked RESULT=skip
13931 12:16:42.985480 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip
13933 12:16:42.985658 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy RESULT=skip
13935 12:16:42.985835 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip
13937 12:16:42.986012 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip
13939 12:16:42.986189 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip
13941 12:16:42.986365 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle RESULT=skip
13943 12:16:42.986541 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip
13945 12:16:42.986728 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13946 12:16:42.986792 Opened dev<8>[ 32.763485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked RESULT=skip>
13947 12:16:42.986850 ice: /dev/dri/card0
13948 12:16:42.986905 No KMS driver or no outputs, pipes: 8, outputs: 0
13949 12:16:42.986960 [1mSubtest pipe-H-wait-forked: SKIP (0.000s)[0m
13950 12:16:42.987013 <14>[ 32.783294] [IGT] kms_vblank: executing
13951 12:16:42.987067 IGT-Version: 1.2<14>[ 32.788049] [IGT] kms_vblank: exiting, ret=77
13952 12:16:42.987120 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13953 12:16:42.987174 Opened device: /dev/dri/ca<8>[ 32.799385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip>
13954 12:16:42.987228 rd0
13955 12:16:42.987280 No KMS driver or no outputs, pipes: 8, outputs: 0
13956 12:16:42.987332 [1mSubtest pipe-H-wait-forked-hang: SKIP (0.000s)[0m
13957 12:16:42.987385 <14>[ 32.830325] [IGT] kms_vblank: executing
13958 12:16:42.987438 IGT-Version: 1.2<14>[ 32.835439] [IGT] kms_vblank: exiting, ret=77
13959 12:16:42.987490 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13960 12:16:42.987544 Opened dev<8>[ 32.846392] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy RESULT=skip>
13961 12:16:42.987597 ice: /dev/dri/card0
13962 12:16:42.987648 No KMS driver or no outputs, pipes: 8, outputs: 0
13963 12:16:42.987764 [1mSubtest pipe-H-wait-busy: SKIP (0.000s)[0m
13964 12:16:42.987846 <14>[ 32.866696] [IGT] kms_vblank: executing
13965 12:16:42.987929 IGT-Version: 1.2<14>[ 32.871442] [IGT] kms_vblank: exiting, ret=77
13966 12:16:42.988011 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13967 12:16:42.988097 Opened device: /dev/dri/ca<8>[ 32.882786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip>
13968 12:16:42.988179 rd0
13969 12:16:42.988260 No KMS driver or no outputs, pipes: 8, outputs: 0
13970 12:16:42.988342 [1mSubtest pipe-H-wait-busy-hang: SKIP (0.000s)[0m
13971 12:16:42.988424 <14>[ 32.907028] [IGT] kms_vblank: executing
13972 12:16:42.988507 IGT-Version: 1.2<14>[ 32.911816] [IGT] kms_vblank: exiting, ret=77
13973 12:16:42.988591 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13974 12:16:42.988649 Opened dev<8>[ 32.922860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip>
13975 12:16:42.988705 ice: /dev/dri/card0
13976 12:16:42.988757 No KMS driver or no outputs, pipes: 8, outputs: 0
13977 12:16:42.988811 [1mSubtest pipe-H-wait-forked-busy: SKIP (0.000s)[0m
13978 12:16:42.988863 <14>[ 32.946779] [IGT] kms_vblank: executing
13979 12:16:42.988916 IGT-Version: 1.2<14>[ 32.951513] [IGT] kms_vblank: exiting, ret=77
13980 12:16:42.988972 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13981 12:16:42.989025 Opened dev<8>[ 32.962505] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip>
13982 12:16:42.989079 ice: /dev/dri/card0
13983 12:16:42.989130 No KMS driver or no outputs, pipes: 8, outputs: 0
13984 12:16:42.989182 [1mSubtest pipe-H-wait-forked-busy-hang: SKIP (0.000s)[0m
13985 12:16:42.989235 <14>[ 32.986526] [IGT] kms_vblank: executing
13986 12:16:42.989287 IGT-Version: 1.2<14>[ 32.991229] [IGT] kms_vblank: exiting, ret=77
13987 12:16:42.989339 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13988 12:16:42.989392 Opened device: /dev/dri/ca<8>[ 33.002622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip>
13989 12:16:42.989445 rd0
13990 12:16:42.989497 No KMS driver or no outputs, pipes: 8, outputs: 0
13991 12:16:42.989550 [1mSubtest pipe-H-ts-continuation-idle: SKIP (0.000s)[0m
13992 12:16:42.989602 <14>[ 33.027235] [IGT] kms_vblank: executing
13993 12:16:42.989654 IGT-Version: 1.2<14>[ 33.032038] [IGT] kms_vblank: exiting, ret=77
13994 12:16:42.989707 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
13995 12:16:42.989759 Opened dev<8>[ 33.043166] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip>
13996 12:16:42.989812 ice: /dev/dri/card0
13997 12:16:42.989864 No KMS driver or no outputs, pipes: 8, outputs: 0
13998 12:16:42.989917 [1mSubtest pipe-H-ts-continuation-idle-hang: SKIP (0.000s)[0m
13999 12:16:42.989969 <14>[ 33.064124] [IGT] kms_vblank: executing
14000 12:16:42.990021 IGT-Version: 1.2<14>[ 33.068854] [IGT] kms_vblank: exiting, ret=77
14001 12:16:42.990073 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
14002 12:16:42.990127 Opened device: /dev/dri/ca<8>[ 33.080900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip>
14003 12:16:42.990183 rd0
14004 12:16:42.990234 No KMS driver or no outputs, pipes: 8, outputs: 0
14005 12:16:42.990286 [1mSubtest pipe-H-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
14006 12:16:42.990339 <14>[ 33.102471] [IGT] kms_vblank: executing
14007 12:16:42.990391 IGT-Version: 1.2<14>[ 33.107245] [IGT] kms_vblank: exiting, ret=77
14008 12:16:42.990444 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
14009 12:16:42.990497 Opened device: /dev/dri/ca<8>[ 33.119324] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip>
14010 12:16:42.990550 rd0
14011 12:16:42.990601 No KMS driver or no outputs, pipes: 8, outputs: 0
14012 12:16:42.990653 [1mSubtest pipe-H-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
14013 12:16:42.990705 <14>[ 33.144092] [IGT] kms_vblank: executing
14014 12:16:42.990757 IGT-Version: 1.2<14>[ 33.148847] [IGT] kms_vblank: exiting, ret=77
14015 12:16:42.990809 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
14016 12:16:42.991037 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked RESULT=skip
14018 12:16:42.991219 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip
14020 12:16:42.991397 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy RESULT=skip
14022 12:16:42.991574 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip
14024 12:16:42.991796 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip
14026 12:16:42.991975 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip
14028 12:16:42.992154 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip
14030 12:16:42.992330 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip
14032 12:16:42.992510 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip
14034 12:16:42.992686 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip
14036 12:16:42.992869 Opened dev<8>[ 33.159900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip>
14037 12:16:42.992931 ice: /dev/dri/card0
14038 12:16:42.992988 No KMS driver or no outputs, pipes: 8, outputs: 0
14039 12:16:42.993044 [1mSubtest pipe-H-ts-continuation-suspend: SKIP (0.000s)[0m
14040 12:16:42.993098 <14>[ 33.183753] [IGT] kms_vblank: executing
14041 12:16:42.993151 IGT-Version: 1.2<14>[ 33.188531] [IGT] kms_vblank: exiting, ret=77
14042 12:16:42.993204 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
14043 12:16:42.993259 Opened dev<8>[ 33.199541] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip>
14044 12:16:42.993312 ice: /dev/dri/card0
14045 12:16:42.993363 No KMS driver or no outputs, pipes: 8, outputs: 0
14046 12:16:42.993416 [1mSubtest pipe-H-ts-continuation-modeset: SKIP (0.000s)[0m
14047 12:16:42.993469 <14>[ 33.221065] [IGT] kms_vblank: executing
14048 12:16:42.993521 IGT-Version: 1.2<14>[ 33.225822] [IGT] kms_vblank: exiting, ret=77
14049 12:16:42.993573 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
14050 12:16:42.993626 Opened dev<8>[ 33.236590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip>
14051 12:16:42.993680 ice: /dev/dri/card0
14052 12:16:42.993731 No KMS driver or no outputs, pipes: 8, outputs: 0
14053 12:16:42.993783 [1mSubtest pipe-H-ts-continuation-modeset-hang: SKIP (0.000s)[0m
14054 12:16:42.993836 <14>[ 33.258206] [IGT] kms_vblank: executing
14055 12:16:42.993888 IGT-Version: 1.2<14>[ 33.263005] [IGT] kms_vblank: exiting, ret=77
14056 12:16:42.993940 7.1-g621c2d3 (aarch64) (Linux: 6.1.72-cip13 aarch64)
14057 12:16:42.993993 Opened device: /dev/dri/card0
14058 12:16:42.994045 No KMS driv<8>[ 33.275997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip>
14059 12:16:42.994099 er or no outputs, pipes: 8, outp<8>[ 33.287596] <LAVA_SIGNAL_TESTSET STOP>
14060 12:16:42.994152 uts: 0
14061 12:16:42.994203 [1mSubt<8>[ 33.293469] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 12669522_1.5.2.3.1>
14062 12:16:42.994255 est pipe-H-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
14063 12:16:42.994307 + set +x
14064 12:16:42.994360 <LAVA_TEST_RUNNER EXIT>
14065 12:16:42.994588 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip
14067 12:16:42.994762 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip
14069 12:16:42.994938 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip
14071 12:16:42.995114 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip
14073 12:16:42.995292 Received signal: <TESTSET> STOP
14074 12:16:42.995352 Closing test_set kms_vblank
14075 12:16:42.995429 Received signal: <ENDRUN> 0_igt-kms-mediatek 12669522_1.5.2.3.1
14076 12:16:42.995499 Ending use of test pattern.
14077 12:16:42.995555 Ending test lava.0_igt-kms-mediatek (12669522_1.5.2.3.1), duration 15.50
14079 12:16:42.995913 ok: lava_test_shell seems to have completed
14080 12:16:42.999725 addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic_plane_damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
pipe-A-accuracy-idle:
result: skip
set: kms_vblank
pipe-A-query-busy:
result: skip
set: kms_vblank
pipe-A-query-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked:
result: skip
set: kms_vblank
pipe-A-query-forked-busy:
result: skip
set: kms_vblank
pipe-A-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked-hang:
result: skip
set: kms_vblank
pipe-A-query-idle:
result: skip
set: kms_vblank
pipe-A-query-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-A-wait-busy:
result: skip
set: kms_vblank
pipe-A-wait-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked-hang:
result: skip
set: kms_vblank
pipe-A-wait-idle:
result: skip
set: kms_vblank
pipe-A-wait-idle-hang:
result: skip
set: kms_vblank
pipe-B-accuracy-idle:
result: skip
set: kms_vblank
pipe-B-query-busy:
result: skip
set: kms_vblank
pipe-B-query-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked:
result: skip
set: kms_vblank
pipe-B-query-forked-busy:
result: skip
set: kms_vblank
pipe-B-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked-hang:
result: skip
set: kms_vblank
pipe-B-query-idle:
result: skip
set: kms_vblank
pipe-B-query-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-B-wait-busy:
result: skip
set: kms_vblank
pipe-B-wait-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked-hang:
result: skip
set: kms_vblank
pipe-B-wait-idle:
result: skip
set: kms_vblank
pipe-B-wait-idle-hang:
result: skip
set: kms_vblank
pipe-C-accuracy-idle:
result: skip
set: kms_vblank
pipe-C-query-busy:
result: skip
set: kms_vblank
pipe-C-query-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked:
result: skip
set: kms_vblank
pipe-C-query-forked-busy:
result: skip
set: kms_vblank
pipe-C-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked-hang:
result: skip
set: kms_vblank
pipe-C-query-idle:
result: skip
set: kms_vblank
pipe-C-query-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-C-wait-busy:
result: skip
set: kms_vblank
pipe-C-wait-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked-hang:
result: skip
set: kms_vblank
pipe-C-wait-idle:
result: skip
set: kms_vblank
pipe-C-wait-idle-hang:
result: skip
set: kms_vblank
pipe-D-accuracy-idle:
result: skip
set: kms_vblank
pipe-D-query-busy:
result: skip
set: kms_vblank
pipe-D-query-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked:
result: skip
set: kms_vblank
pipe-D-query-forked-busy:
result: skip
set: kms_vblank
pipe-D-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked-hang:
result: skip
set: kms_vblank
pipe-D-query-idle:
result: skip
set: kms_vblank
pipe-D-query-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-D-wait-busy:
result: skip
set: kms_vblank
pipe-D-wait-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked-hang:
result: skip
set: kms_vblank
pipe-D-wait-idle:
result: skip
set: kms_vblank
pipe-D-wait-idle-hang:
result: skip
set: kms_vblank
pipe-E-accuracy-idle:
result: skip
set: kms_vblank
pipe-E-query-busy:
result: skip
set: kms_vblank
pipe-E-query-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked:
result: skip
set: kms_vblank
pipe-E-query-forked-busy:
result: skip
set: kms_vblank
pipe-E-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked-hang:
result: skip
set: kms_vblank
pipe-E-query-idle:
result: skip
set: kms_vblank
pipe-E-query-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-E-wait-busy:
result: skip
set: kms_vblank
pipe-E-wait-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked-hang:
result: skip
set: kms_vblank
pipe-E-wait-idle:
result: skip
set: kms_vblank
pipe-E-wait-idle-hang:
result: skip
set: kms_vblank
pipe-F-accuracy-idle:
result: skip
set: kms_vblank
pipe-F-query-busy:
result: skip
set: kms_vblank
pipe-F-query-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked:
result: skip
set: kms_vblank
pipe-F-query-forked-busy:
result: skip
set: kms_vblank
pipe-F-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked-hang:
result: skip
set: kms_vblank
pipe-F-query-idle:
result: skip
set: kms_vblank
pipe-F-query-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-F-wait-busy:
result: skip
set: kms_vblank
pipe-F-wait-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked-hang:
result: skip
set: kms_vblank
pipe-F-wait-idle:
result: skip
set: kms_vblank
pipe-F-wait-idle-hang:
result: skip
set: kms_vblank
pipe-G-accuracy-idle:
result: skip
set: kms_vblank
pipe-G-query-busy:
result: skip
set: kms_vblank
pipe-G-query-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked:
result: skip
set: kms_vblank
pipe-G-query-forked-busy:
result: skip
set: kms_vblank
pipe-G-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked-hang:
result: skip
set: kms_vblank
pipe-G-query-idle:
result: skip
set: kms_vblank
pipe-G-query-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-G-wait-busy:
result: skip
set: kms_vblank
pipe-G-wait-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked-hang:
result: skip
set: kms_vblank
pipe-G-wait-idle:
result: skip
set: kms_vblank
pipe-G-wait-idle-hang:
result: skip
set: kms_vblank
pipe-H-accuracy-idle:
result: skip
set: kms_vblank
pipe-H-query-busy:
result: skip
set: kms_vblank
pipe-H-query-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked:
result: skip
set: kms_vblank
pipe-H-query-forked-busy:
result: skip
set: kms_vblank
pipe-H-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked-hang:
result: skip
set: kms_vblank
pipe-H-query-idle:
result: skip
set: kms_vblank
pipe-H-query-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-H-wait-busy:
result: skip
set: kms_vblank
pipe-H-wait-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked-hang:
result: skip
set: kms_vblank
pipe-H-wait-idle:
result: skip
set: kms_vblank
pipe-H-wait-idle-hang:
result: skip
set: kms_vblank
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
14081 12:16:42.999955 end: 3.1 lava-test-shell (duration 00:00:16) [common]
14082 12:16:43.000042 end: 3 lava-test-retry (duration 00:00:16) [common]
14083 12:16:43.000130 start: 4 finalize (timeout 00:07:46) [common]
14084 12:16:43.000217 start: 4.1 power-off (timeout 00:00:30) [common]
14085 12:16:43.000364 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
14086 12:16:43.077879 >> Command sent successfully.
14087 12:16:43.083186 Returned 0 in 0 seconds
14088 12:16:43.184221 end: 4.1 power-off (duration 00:00:00) [common]
14090 12:16:43.185774 start: 4.2 read-feedback (timeout 00:07:46) [common]
14091 12:16:43.186965 Listened to connection for namespace 'common' for up to 1s
14092 12:16:44.187716 Finalising connection for namespace 'common'
14093 12:16:44.188397 Disconnecting from shell: Finalise
14094 12:16:44.188803 / #
14095 12:16:44.289854 end: 4.2 read-feedback (duration 00:00:01) [common]
14096 12:16:44.290576 end: 4 finalize (duration 00:00:01) [common]
14097 12:16:44.291179 Cleaning after the job
14098 12:16:44.291735 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669522/tftp-deploy-c4g5e4u7/ramdisk
14099 12:16:44.325281 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669522/tftp-deploy-c4g5e4u7/kernel
14100 12:16:44.341696 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669522/tftp-deploy-c4g5e4u7/dtb
14101 12:16:44.341968 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669522/tftp-deploy-c4g5e4u7/modules
14102 12:16:44.351416 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12669522
14103 12:16:44.469001 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12669522
14104 12:16:44.469180 Job finished correctly