Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Boot result: PASS
- Errors: 0
- Kernel Warnings: 17
- Kernel Errors: 34
1 12:15:17.491017 lava-dispatcher, installed at version: 2023.10
2 12:15:17.491217 start: 0 validate
3 12:15:17.491350 Start time: 2024-01-31 12:15:17.491343+00:00 (UTC)
4 12:15:17.491511 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:15:17.491648 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20231214.0%2Farm64%2Finitrd.cpio.gz exists
6 12:15:17.762937 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:15:17.763716 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 12:15:18.033919 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:15:18.034684 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 12:15:18.312105 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:15:18.312888 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20231214.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 12:15:18.582673 Using caching service: 'http://localhost/cache/?uri=%s'
13 12:15:18.582955 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.72-cip13-32-gf60d2e8cb51c%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 12:15:18.852103 validate duration: 1.36
16 12:15:18.852350 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 12:15:18.852448 start: 1.1 download-retry (timeout 00:10:00) [common]
18 12:15:18.852538 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 12:15:18.852663 Not decompressing ramdisk as can be used compressed.
20 12:15:18.852749 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20231214.0/arm64/initrd.cpio.gz
21 12:15:18.852817 saving as /var/lib/lava/dispatcher/tmp/12669531/tftp-deploy-vtw011t9/ramdisk/initrd.cpio.gz
22 12:15:18.852882 total size: 5628325 (5 MB)
23 12:15:18.853966 progress 0 % (0 MB)
24 12:15:18.855795 progress 5 % (0 MB)
25 12:15:18.857407 progress 10 % (0 MB)
26 12:15:18.858836 progress 15 % (0 MB)
27 12:15:18.860490 progress 20 % (1 MB)
28 12:15:18.861940 progress 25 % (1 MB)
29 12:15:18.863566 progress 30 % (1 MB)
30 12:15:18.865121 progress 35 % (1 MB)
31 12:15:18.866527 progress 40 % (2 MB)
32 12:15:18.868184 progress 45 % (2 MB)
33 12:15:18.869570 progress 50 % (2 MB)
34 12:15:18.871124 progress 55 % (2 MB)
35 12:15:18.872712 progress 60 % (3 MB)
36 12:15:18.874092 progress 65 % (3 MB)
37 12:15:18.875713 progress 70 % (3 MB)
38 12:15:18.877102 progress 75 % (4 MB)
39 12:15:18.878646 progress 80 % (4 MB)
40 12:15:18.880076 progress 85 % (4 MB)
41 12:15:18.881645 progress 90 % (4 MB)
42 12:15:18.883191 progress 95 % (5 MB)
43 12:15:18.884635 progress 100 % (5 MB)
44 12:15:18.884842 5 MB downloaded in 0.03 s (167.94 MB/s)
45 12:15:18.884989 end: 1.1.1 http-download (duration 00:00:00) [common]
47 12:15:18.885229 end: 1.1 download-retry (duration 00:00:00) [common]
48 12:15:18.885314 start: 1.2 download-retry (timeout 00:10:00) [common]
49 12:15:18.885395 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 12:15:18.885523 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 12:15:18.885593 saving as /var/lib/lava/dispatcher/tmp/12669531/tftp-deploy-vtw011t9/kernel/Image
52 12:15:18.885653 total size: 51532288 (49 MB)
53 12:15:18.885713 No compression specified
54 12:15:18.886781 progress 0 % (0 MB)
55 12:15:18.900028 progress 5 % (2 MB)
56 12:15:18.913552 progress 10 % (4 MB)
57 12:15:18.926784 progress 15 % (7 MB)
58 12:15:18.940279 progress 20 % (9 MB)
59 12:15:18.953707 progress 25 % (12 MB)
60 12:15:18.966952 progress 30 % (14 MB)
61 12:15:18.980465 progress 35 % (17 MB)
62 12:15:18.993760 progress 40 % (19 MB)
63 12:15:19.006844 progress 45 % (22 MB)
64 12:15:19.020310 progress 50 % (24 MB)
65 12:15:19.033635 progress 55 % (27 MB)
66 12:15:19.047274 progress 60 % (29 MB)
67 12:15:19.060867 progress 65 % (31 MB)
68 12:15:19.074050 progress 70 % (34 MB)
69 12:15:19.087424 progress 75 % (36 MB)
70 12:15:19.100647 progress 80 % (39 MB)
71 12:15:19.113704 progress 85 % (41 MB)
72 12:15:19.126949 progress 90 % (44 MB)
73 12:15:19.140178 progress 95 % (46 MB)
74 12:15:19.153238 progress 100 % (49 MB)
75 12:15:19.153454 49 MB downloaded in 0.27 s (183.52 MB/s)
76 12:15:19.153604 end: 1.2.1 http-download (duration 00:00:00) [common]
78 12:15:19.153840 end: 1.2 download-retry (duration 00:00:00) [common]
79 12:15:19.153925 start: 1.3 download-retry (timeout 00:10:00) [common]
80 12:15:19.154012 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 12:15:19.154147 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 12:15:19.154217 saving as /var/lib/lava/dispatcher/tmp/12669531/tftp-deploy-vtw011t9/dtb/mt8192-asurada-spherion-r0.dtb
83 12:15:19.154277 total size: 47278 (0 MB)
84 12:15:19.154337 No compression specified
85 12:15:19.155533 progress 69 % (0 MB)
86 12:15:19.155805 progress 100 % (0 MB)
87 12:15:19.155961 0 MB downloaded in 0.00 s (26.81 MB/s)
88 12:15:19.156080 end: 1.3.1 http-download (duration 00:00:00) [common]
90 12:15:19.156297 end: 1.3 download-retry (duration 00:00:00) [common]
91 12:15:19.156383 start: 1.4 download-retry (timeout 00:10:00) [common]
92 12:15:19.156465 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 12:15:19.156578 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20231214.0/arm64/full.rootfs.tar.xz
94 12:15:19.156644 saving as /var/lib/lava/dispatcher/tmp/12669531/tftp-deploy-vtw011t9/nfsrootfs/full.rootfs.tar
95 12:15:19.156707 total size: 198084472 (188 MB)
96 12:15:19.156767 Using unxz to decompress xz
97 12:15:19.160998 progress 0 % (0 MB)
98 12:15:19.722866 progress 5 % (9 MB)
99 12:15:20.217535 progress 10 % (18 MB)
100 12:15:20.805872 progress 15 % (28 MB)
101 12:15:21.092042 progress 20 % (37 MB)
102 12:15:21.555402 progress 25 % (47 MB)
103 12:15:22.127973 progress 30 % (56 MB)
104 12:15:22.683950 progress 35 % (66 MB)
105 12:15:23.267849 progress 40 % (75 MB)
106 12:15:23.866954 progress 45 % (85 MB)
107 12:15:24.470914 progress 50 % (94 MB)
108 12:15:25.075923 progress 55 % (103 MB)
109 12:15:25.725684 progress 60 % (113 MB)
110 12:15:26.097282 progress 65 % (122 MB)
111 12:15:26.188667 progress 70 % (132 MB)
112 12:15:26.329244 progress 75 % (141 MB)
113 12:15:26.404729 progress 80 % (151 MB)
114 12:15:26.454086 progress 85 % (160 MB)
115 12:15:26.548032 progress 90 % (170 MB)
116 12:15:26.908332 progress 95 % (179 MB)
117 12:15:27.480030 progress 100 % (188 MB)
118 12:15:27.484724 188 MB downloaded in 8.33 s (22.68 MB/s)
119 12:15:27.484988 end: 1.4.1 http-download (duration 00:00:08) [common]
121 12:15:27.485260 end: 1.4 download-retry (duration 00:00:08) [common]
122 12:15:27.485351 start: 1.5 download-retry (timeout 00:09:51) [common]
123 12:15:27.485438 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 12:15:27.485595 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 12:15:27.485667 saving as /var/lib/lava/dispatcher/tmp/12669531/tftp-deploy-vtw011t9/modules/modules.tar
126 12:15:27.485730 total size: 8639916 (8 MB)
127 12:15:27.485793 Using unxz to decompress xz
128 12:15:27.490084 progress 0 % (0 MB)
129 12:15:27.510964 progress 5 % (0 MB)
130 12:15:27.534238 progress 10 % (0 MB)
131 12:15:27.557424 progress 15 % (1 MB)
132 12:15:27.580806 progress 20 % (1 MB)
133 12:15:27.604482 progress 25 % (2 MB)
134 12:15:27.631369 progress 30 % (2 MB)
135 12:15:27.655261 progress 35 % (2 MB)
136 12:15:27.678384 progress 40 % (3 MB)
137 12:15:27.702896 progress 45 % (3 MB)
138 12:15:27.727632 progress 50 % (4 MB)
139 12:15:27.753423 progress 55 % (4 MB)
140 12:15:27.778082 progress 60 % (4 MB)
141 12:15:27.803349 progress 65 % (5 MB)
142 12:15:27.827858 progress 70 % (5 MB)
143 12:15:27.850935 progress 75 % (6 MB)
144 12:15:27.878119 progress 80 % (6 MB)
145 12:15:27.905402 progress 85 % (7 MB)
146 12:15:27.929831 progress 90 % (7 MB)
147 12:15:27.959580 progress 95 % (7 MB)
148 12:15:27.987876 progress 100 % (8 MB)
149 12:15:27.993728 8 MB downloaded in 0.51 s (16.22 MB/s)
150 12:15:27.993973 end: 1.5.1 http-download (duration 00:00:01) [common]
152 12:15:27.994236 end: 1.5 download-retry (duration 00:00:01) [common]
153 12:15:27.994330 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 12:15:27.994425 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 12:15:31.594578 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12669531/extract-nfsrootfs-kiz8_ci8
156 12:15:31.594779 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 12:15:31.594881 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 12:15:31.595044 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk
159 12:15:31.595178 makedir: /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin
160 12:15:31.595279 makedir: /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/tests
161 12:15:31.595773 makedir: /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/results
162 12:15:31.595882 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-add-keys
163 12:15:31.596028 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-add-sources
164 12:15:31.596158 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-background-process-start
165 12:15:31.596284 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-background-process-stop
166 12:15:31.596406 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-common-functions
167 12:15:31.596530 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-echo-ipv4
168 12:15:31.596652 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-install-packages
169 12:15:31.596775 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-installed-packages
170 12:15:31.596895 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-os-build
171 12:15:31.597016 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-probe-channel
172 12:15:31.597137 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-probe-ip
173 12:15:31.597258 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-target-ip
174 12:15:31.597381 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-target-mac
175 12:15:31.597508 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-target-storage
176 12:15:31.597633 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-test-case
177 12:15:31.597758 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-test-event
178 12:15:31.597880 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-test-feedback
179 12:15:31.598002 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-test-raise
180 12:15:31.598123 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-test-reference
181 12:15:31.598244 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-test-runner
182 12:15:31.598366 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-test-set
183 12:15:31.598490 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-test-shell
184 12:15:31.598613 Updating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-add-keys (debian)
185 12:15:31.598764 Updating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-add-sources (debian)
186 12:15:31.598902 Updating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-install-packages (debian)
187 12:15:31.599041 Updating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-installed-packages (debian)
188 12:15:31.599178 Updating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/bin/lava-os-build (debian)
189 12:15:31.599298 Creating /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/environment
190 12:15:31.599450 LAVA metadata
191 12:15:31.599534 - LAVA_JOB_ID=12669531
192 12:15:31.599616 - LAVA_DISPATCHER_IP=192.168.201.1
193 12:15:31.599744 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 12:15:31.599819 skipped lava-vland-overlay
195 12:15:31.599938 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 12:15:31.600060 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 12:15:31.600168 skipped lava-multinode-overlay
198 12:15:31.600285 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 12:15:31.600407 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 12:15:31.600517 Loading test definitions
201 12:15:31.600652 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 12:15:31.600760 Using /lava-12669531 at stage 0
203 12:15:31.601144 uuid=12669531_1.6.2.3.1 testdef=None
204 12:15:31.601266 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 12:15:31.601390 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 12:15:31.602055 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 12:15:31.602416 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 12:15:31.602989 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 12:15:31.603244 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 12:15:31.604060 runner path: /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/0/tests/0_timesync-off test_uuid 12669531_1.6.2.3.1
213 12:15:31.604227 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 12:15:31.604480 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 12:15:31.604562 Using /lava-12669531 at stage 0
217 12:15:31.604710 Fetching tests from https://github.com/kernelci/test-definitions.git
218 12:15:31.604822 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/0/tests/1_kselftest-alsa'
219 12:15:39.270467 Running '/usr/bin/git checkout kernelci.org
220 12:15:39.418863 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 12:15:39.419688 uuid=12669531_1.6.2.3.5 testdef=None
222 12:15:39.419861 end: 1.6.2.3.5 git-repo-action (duration 00:00:08) [common]
224 12:15:39.420149 start: 1.6.2.3.6 test-overlay (timeout 00:09:39) [common]
225 12:15:39.420930 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 12:15:39.421189 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:39) [common]
228 12:15:39.422781 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 12:15:39.423167 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:39) [common]
231 12:15:39.424200 runner path: /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/0/tests/1_kselftest-alsa test_uuid 12669531_1.6.2.3.5
232 12:15:39.424304 BOARD='mt8192-asurada-spherion-r0'
233 12:15:39.424381 BRANCH='cip-gitlab'
234 12:15:39.424460 SKIPFILE='/dev/null'
235 12:15:39.424538 SKIP_INSTALL='True'
236 12:15:39.424614 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 12:15:39.424693 TST_CASENAME=''
238 12:15:39.424787 TST_CMDFILES='alsa'
239 12:15:39.424991 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 12:15:39.425345 Creating lava-test-runner.conf files
242 12:15:39.425447 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12669531/lava-overlay-e0en6sgk/lava-12669531/0 for stage 0
243 12:15:39.425587 - 0_timesync-off
244 12:15:39.425688 - 1_kselftest-alsa
245 12:15:39.425812 end: 1.6.2.3 test-definition (duration 00:00:08) [common]
246 12:15:39.425917 start: 1.6.2.4 compress-overlay (timeout 00:09:39) [common]
247 12:15:47.021630 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 12:15:47.021815 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:32) [common]
249 12:15:47.021923 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 12:15:47.022044 end: 1.6.2 lava-overlay (duration 00:00:15) [common]
251 12:15:47.022148 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:32) [common]
252 12:15:47.191858 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 12:15:47.192247 start: 1.6.4 extract-modules (timeout 00:09:32) [common]
254 12:15:47.192379 extracting modules file /var/lib/lava/dispatcher/tmp/12669531/tftp-deploy-vtw011t9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12669531/extract-nfsrootfs-kiz8_ci8
255 12:15:47.412480 extracting modules file /var/lib/lava/dispatcher/tmp/12669531/tftp-deploy-vtw011t9/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12669531/extract-overlay-ramdisk-e3niivxo/ramdisk
256 12:15:47.638198 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 12:15:47.638368 start: 1.6.5 apply-overlay-tftp (timeout 00:09:31) [common]
258 12:15:47.638479 [common] Applying overlay to NFS
259 12:15:47.638560 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12669531/compress-overlay-3a06ntui/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12669531/extract-nfsrootfs-kiz8_ci8
260 12:15:48.572099 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 12:15:48.572259 start: 1.6.6 configure-preseed-file (timeout 00:09:30) [common]
262 12:15:48.572372 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 12:15:48.572476 start: 1.6.7 compress-ramdisk (timeout 00:09:30) [common]
264 12:15:48.572570 Building ramdisk /var/lib/lava/dispatcher/tmp/12669531/extract-overlay-ramdisk-e3niivxo/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12669531/extract-overlay-ramdisk-e3niivxo/ramdisk
265 12:15:48.943704 >> 130539 blocks
266 12:15:51.033016 rename /var/lib/lava/dispatcher/tmp/12669531/extract-overlay-ramdisk-e3niivxo/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12669531/tftp-deploy-vtw011t9/ramdisk/ramdisk.cpio.gz
267 12:15:51.033525 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 12:15:51.033720 start: 1.6.8 prepare-kernel (timeout 00:09:28) [common]
269 12:15:51.033918 start: 1.6.8.1 prepare-fit (timeout 00:09:28) [common]
270 12:15:51.034107 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12669531/tftp-deploy-vtw011t9/kernel/Image'
271 12:16:03.669119 Returned 0 in 12 seconds
272 12:16:03.770182 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12669531/tftp-deploy-vtw011t9/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12669531/tftp-deploy-vtw011t9/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12669531/tftp-deploy-vtw011t9/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12669531/tftp-deploy-vtw011t9/kernel/image.itb
273 12:16:04.143014 output: FIT description: Kernel Image image with one or more FDT blobs
274 12:16:04.143467 output: Created: Wed Jan 31 12:16:04 2024
275 12:16:04.143574 output: Image 0 (kernel-1)
276 12:16:04.143679 output: Description:
277 12:16:04.143782 output: Created: Wed Jan 31 12:16:04 2024
278 12:16:04.143880 output: Type: Kernel Image
279 12:16:04.143977 output: Compression: lzma compressed
280 12:16:04.144072 output: Data Size: 12047284 Bytes = 11764.93 KiB = 11.49 MiB
281 12:16:04.144173 output: Architecture: AArch64
282 12:16:04.144270 output: OS: Linux
283 12:16:04.144369 output: Load Address: 0x00000000
284 12:16:04.144467 output: Entry Point: 0x00000000
285 12:16:04.144566 output: Hash algo: crc32
286 12:16:04.144661 output: Hash value: 5a47eb78
287 12:16:04.144759 output: Image 1 (fdt-1)
288 12:16:04.144854 output: Description: mt8192-asurada-spherion-r0
289 12:16:04.144949 output: Created: Wed Jan 31 12:16:04 2024
290 12:16:04.145043 output: Type: Flat Device Tree
291 12:16:04.145135 output: Compression: uncompressed
292 12:16:04.145231 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 12:16:04.145325 output: Architecture: AArch64
294 12:16:04.145418 output: Hash algo: crc32
295 12:16:04.145509 output: Hash value: cc4352de
296 12:16:04.145600 output: Image 2 (ramdisk-1)
297 12:16:04.145690 output: Description: unavailable
298 12:16:04.145785 output: Created: Wed Jan 31 12:16:04 2024
299 12:16:04.145879 output: Type: RAMDisk Image
300 12:16:04.145971 output: Compression: Unknown Compression
301 12:16:04.146063 output: Data Size: 18756686 Bytes = 18317.08 KiB = 17.89 MiB
302 12:16:04.146154 output: Architecture: AArch64
303 12:16:04.146249 output: OS: Linux
304 12:16:04.146342 output: Load Address: unavailable
305 12:16:04.146415 output: Entry Point: unavailable
306 12:16:04.146488 output: Hash algo: crc32
307 12:16:04.146579 output: Hash value: 8e892564
308 12:16:04.146670 output: Default Configuration: 'conf-1'
309 12:16:04.146761 output: Configuration 0 (conf-1)
310 12:16:04.146851 output: Description: mt8192-asurada-spherion-r0
311 12:16:04.146941 output: Kernel: kernel-1
312 12:16:04.147031 output: Init Ramdisk: ramdisk-1
313 12:16:04.147121 output: FDT: fdt-1
314 12:16:04.147211 output: Loadables: kernel-1
315 12:16:04.147301 output:
316 12:16:04.147597 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 12:16:04.147746 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 12:16:04.147905 end: 1.6 prepare-tftp-overlay (duration 00:00:36) [common]
319 12:16:04.148053 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:15) [common]
320 12:16:04.148167 No LXC device requested
321 12:16:04.148289 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 12:16:04.148428 start: 1.8 deploy-device-env (timeout 00:09:15) [common]
323 12:16:04.148553 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 12:16:04.148662 Checking files for TFTP limit of 4294967296 bytes.
325 12:16:04.149324 end: 1 tftp-deploy (duration 00:00:45) [common]
326 12:16:04.149471 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 12:16:04.149603 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 12:16:04.149787 substitutions:
329 12:16:04.149885 - {DTB}: 12669531/tftp-deploy-vtw011t9/dtb/mt8192-asurada-spherion-r0.dtb
330 12:16:04.149987 - {INITRD}: 12669531/tftp-deploy-vtw011t9/ramdisk/ramdisk.cpio.gz
331 12:16:04.150088 - {KERNEL}: 12669531/tftp-deploy-vtw011t9/kernel/Image
332 12:16:04.150187 - {LAVA_MAC}: None
333 12:16:04.150284 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12669531/extract-nfsrootfs-kiz8_ci8
334 12:16:04.150380 - {NFS_SERVER_IP}: 192.168.201.1
335 12:16:04.150475 - {PRESEED_CONFIG}: None
336 12:16:04.150569 - {PRESEED_LOCAL}: None
337 12:16:04.150663 - {RAMDISK}: 12669531/tftp-deploy-vtw011t9/ramdisk/ramdisk.cpio.gz
338 12:16:04.150757 - {ROOT_PART}: None
339 12:16:04.150851 - {ROOT}: None
340 12:16:04.150944 - {SERVER_IP}: 192.168.201.1
341 12:16:04.151037 - {TEE}: None
342 12:16:04.151129 Parsed boot commands:
343 12:16:04.151222 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 12:16:04.151498 Parsed boot commands: tftpboot 192.168.201.1 12669531/tftp-deploy-vtw011t9/kernel/image.itb 12669531/tftp-deploy-vtw011t9/kernel/cmdline
345 12:16:04.151623 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 12:16:04.151751 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 12:16:04.151889 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 12:16:04.152021 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 12:16:04.152130 Not connected, no need to disconnect.
350 12:16:04.152249 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 12:16:04.152375 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 12:16:04.152479 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 12:16:04.156709 Setting prompt string to ['lava-test: # ']
354 12:16:04.157096 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 12:16:04.157222 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 12:16:04.157339 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 12:16:04.157471 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 12:16:04.157812 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
359 12:16:09.306913 >> Command sent successfully.
360 12:16:09.317563 Returned 0 in 5 seconds
361 12:16:09.418841 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 12:16:09.420284 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 12:16:09.420806 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 12:16:09.421269 Setting prompt string to 'Starting depthcharge on Spherion...'
366 12:16:09.421749 Changing prompt to 'Starting depthcharge on Spherion...'
367 12:16:09.422105 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 12:16:09.423296 [Enter `^Ec?' for help]
369 12:16:09.584141
370 12:16:09.584637
371 12:16:09.585127 F0: 102B 0000
372 12:16:09.585522
373 12:16:09.585835 F3: 1001 0000 [0200]
374 12:16:09.586140
375 12:16:09.587818 F3: 1001 0000
376 12:16:09.588282
377 12:16:09.588754 F7: 102D 0000
378 12:16:09.589089
379 12:16:09.589403 F1: 0000 0000
380 12:16:09.591266
381 12:16:09.591840 V0: 0000 0000 [0001]
382 12:16:09.592246
383 12:16:09.592570 00: 0007 8000
384 12:16:09.592904
385 12:16:09.595000 01: 0000 0000
386 12:16:09.595508
387 12:16:09.595999 BP: 0C00 0209 [0000]
388 12:16:09.596334
389 12:16:09.598413 G0: 1182 0000
390 12:16:09.599023
391 12:16:09.599670 EC: 0000 0021 [4000]
392 12:16:09.600171
393 12:16:09.602131 S7: 0000 0000 [0000]
394 12:16:09.602571
395 12:16:09.602906 CC: 0000 0000 [0001]
396 12:16:09.603318
397 12:16:09.605644 T0: 0000 0040 [010F]
398 12:16:09.606076
399 12:16:09.606411 Jump to BL
400 12:16:09.606729
401 12:16:09.630861
402 12:16:09.631284
403 12:16:09.631742
404 12:16:09.637483 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 12:16:09.640969 ARM64: Exception handlers installed.
406 12:16:09.644751 ARM64: Testing exception
407 12:16:09.648885 ARM64: Done test exception
408 12:16:09.656124 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 12:16:09.666309 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 12:16:09.673246 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 12:16:09.683192 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 12:16:09.689685 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 12:16:09.696858 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 12:16:09.708107 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 12:16:09.714689 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 12:16:09.733854 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 12:16:09.737078 WDT: Last reset was cold boot
418 12:16:09.741163 SPI1(PAD0) initialized at 2873684 Hz
419 12:16:09.743918 SPI5(PAD0) initialized at 992727 Hz
420 12:16:09.747551 VBOOT: Loading verstage.
421 12:16:09.753942 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 12:16:09.756704 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 12:16:09.760230 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 12:16:09.763246 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 12:16:09.771222 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 12:16:09.777612 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 12:16:09.788802 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 12:16:09.789294
429 12:16:09.789644
430 12:16:09.798627 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 12:16:09.802803 ARM64: Exception handlers installed.
432 12:16:09.805580 ARM64: Testing exception
433 12:16:09.805941 ARM64: Done test exception
434 12:16:09.812435 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 12:16:09.815761 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 12:16:09.829733 Probing TPM: . done!
437 12:16:09.830053 TPM ready after 0 ms
438 12:16:09.838600 Connected to device vid:did:rid of 1ae0:0028:00
439 12:16:09.845230 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 12:16:09.902110 Initialized TPM device CR50 revision 0
441 12:16:09.913891 tlcl_send_startup: Startup return code is 0
442 12:16:09.914322 TPM: setup succeeded
443 12:16:09.925462 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 12:16:09.934131 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 12:16:09.946258 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 12:16:09.956304 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 12:16:09.959470 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 12:16:09.965290 in-header: 03 07 00 00 08 00 00 00
449 12:16:09.968801 in-data: aa e4 47 04 13 02 00 00
450 12:16:09.971910 Chrome EC: UHEPI supported
451 12:16:09.979455 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 12:16:09.982964 in-header: 03 95 00 00 08 00 00 00
453 12:16:09.988397 in-data: 18 20 20 08 00 00 00 00
454 12:16:09.988825 Phase 1
455 12:16:09.990758 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 12:16:09.998319 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 12:16:10.002119 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 12:16:10.005801 Recovery requested (1009000e)
459 12:16:10.013288 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 12:16:10.018954 tlcl_extend: response is 0
461 12:16:10.028275 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 12:16:10.034219 tlcl_extend: response is 0
463 12:16:10.040846 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 12:16:10.060661 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 12:16:10.067765 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 12:16:10.068326
467 12:16:10.068672
468 12:16:10.077545 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 12:16:10.080407 ARM64: Exception handlers installed.
470 12:16:10.084008 ARM64: Testing exception
471 12:16:10.084438 ARM64: Done test exception
472 12:16:10.106243 pmic_efuse_setting: Set efuses in 11 msecs
473 12:16:10.109540 pmwrap_interface_init: Select PMIF_VLD_RDY
474 12:16:10.116578 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 12:16:10.119233 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 12:16:10.126195 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 12:16:10.129765 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 12:16:10.132998 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 12:16:10.139940 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 12:16:10.143434 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 12:16:10.150828 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 12:16:10.154412 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 12:16:10.158921 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 12:16:10.161636 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 12:16:10.169202 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 12:16:10.173263 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 12:16:10.180486 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 12:16:10.183677 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 12:16:10.190962 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 12:16:10.194606 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 12:16:10.201784 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 12:16:10.205573 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 12:16:10.213191 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 12:16:10.216453 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 12:16:10.224502 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 12:16:10.232049 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 12:16:10.235727 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 12:16:10.238459 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 12:16:10.245634 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 12:16:10.249085 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 12:16:10.256152 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 12:16:10.260010 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 12:16:10.263401 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 12:16:10.271192 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 12:16:10.274613 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 12:16:10.278494 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 12:16:10.285814 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 12:16:10.289291 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 12:16:10.296697 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 12:16:10.300558 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 12:16:10.303982 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 12:16:10.311123 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 12:16:10.315612 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 12:16:10.318426 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 12:16:10.322251 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 12:16:10.325675 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 12:16:10.333280 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 12:16:10.336507 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 12:16:10.339881 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 12:16:10.343817 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 12:16:10.347072 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 12:16:10.354746 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 12:16:10.357716 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 12:16:10.361743 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 12:16:10.369030 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 12:16:10.376471 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 12:16:10.383573 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 12:16:10.390919 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 12:16:10.398310 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 12:16:10.402822 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 12:16:10.409996 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 12:16:10.412760 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 12:16:10.420319 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
534 12:16:10.423349 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 12:16:10.431342 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 12:16:10.434358 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 12:16:10.443827 [RTC]rtc_get_frequency_meter,154: input=15, output=852
538 12:16:10.453637 [RTC]rtc_get_frequency_meter,154: input=7, output=724
539 12:16:10.462335 [RTC]rtc_get_frequency_meter,154: input=11, output=788
540 12:16:10.471860 [RTC]rtc_get_frequency_meter,154: input=13, output=820
541 12:16:10.482088 [RTC]rtc_get_frequency_meter,154: input=12, output=804
542 12:16:10.491049 [RTC]rtc_get_frequency_meter,154: input=11, output=788
543 12:16:10.500747 [RTC]rtc_get_frequency_meter,154: input=12, output=804
544 12:16:10.504686 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 12:16:10.511394 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 12:16:10.514950 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 12:16:10.519061 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 12:16:10.522461 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 12:16:10.526514 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 12:16:10.530073 ADC[4]: Raw value=903325 ID=7
551 12:16:10.533728 ADC[3]: Raw value=213916 ID=1
552 12:16:10.534181 RAM Code: 0x71
553 12:16:10.537538 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 12:16:10.544523 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 12:16:10.552009 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 12:16:10.559223 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 12:16:10.562296 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 12:16:10.566016 in-header: 03 07 00 00 08 00 00 00
559 12:16:10.569714 in-data: aa e4 47 04 13 02 00 00
560 12:16:10.570262 Chrome EC: UHEPI supported
561 12:16:10.577260 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 12:16:10.580914 in-header: 03 95 00 00 08 00 00 00
563 12:16:10.584776 in-data: 18 20 20 08 00 00 00 00
564 12:16:10.587676 MRC: failed to locate region type 0.
565 12:16:10.595277 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 12:16:10.598620 DRAM-K: Running full calibration
567 12:16:10.603177 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 12:16:10.606360 header.status = 0x0
569 12:16:10.610178 header.version = 0x6 (expected: 0x6)
570 12:16:10.613028 header.size = 0xd00 (expected: 0xd00)
571 12:16:10.613493 header.flags = 0x0
572 12:16:10.620078 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 12:16:10.638702 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 12:16:10.645449 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 12:16:10.648572 dram_init: ddr_geometry: 2
576 12:16:10.649173 [EMI] MDL number = 2
577 12:16:10.653028 [EMI] Get MDL freq = 0
578 12:16:10.653457 dram_init: ddr_type: 0
579 12:16:10.655731 is_discrete_lpddr4: 1
580 12:16:10.660274 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 12:16:10.660720
582 12:16:10.661057
583 12:16:10.663236 [Bian_co] ETT version 0.0.0.1
584 12:16:10.666971 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 12:16:10.667500
586 12:16:10.670786 dramc_set_vcore_voltage set vcore to 650000
587 12:16:10.671217 Read voltage for 800, 4
588 12:16:10.673890 Vio18 = 0
589 12:16:10.674318 Vcore = 650000
590 12:16:10.674658 Vdram = 0
591 12:16:10.677517 Vddq = 0
592 12:16:10.677948 Vmddr = 0
593 12:16:10.680704 dram_init: config_dvfs: 1
594 12:16:10.684340 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 12:16:10.691672 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 12:16:10.694040 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 12:16:10.697997 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 12:16:10.701277 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 12:16:10.705014 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 12:16:10.708509 MEM_TYPE=3, freq_sel=18
601 12:16:10.708956 sv_algorithm_assistance_LP4_1600
602 12:16:10.716192 ============ PULL DRAM RESETB DOWN ============
603 12:16:10.719958 ========== PULL DRAM RESETB DOWN end =========
604 12:16:10.722712 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 12:16:10.726608 ===================================
606 12:16:10.729919 LPDDR4 DRAM CONFIGURATION
607 12:16:10.733695 ===================================
608 12:16:10.734410 EX_ROW_EN[0] = 0x0
609 12:16:10.736997 EX_ROW_EN[1] = 0x0
610 12:16:10.737484 LP4Y_EN = 0x0
611 12:16:10.740598 WORK_FSP = 0x0
612 12:16:10.741046 WL = 0x2
613 12:16:10.743957 RL = 0x2
614 12:16:10.744383 BL = 0x2
615 12:16:10.747349 RPST = 0x0
616 12:16:10.747808 RD_PRE = 0x0
617 12:16:10.750424 WR_PRE = 0x1
618 12:16:10.751040 WR_PST = 0x0
619 12:16:10.753987 DBI_WR = 0x0
620 12:16:10.754414 DBI_RD = 0x0
621 12:16:10.757108 OTF = 0x1
622 12:16:10.760446 ===================================
623 12:16:10.764067 ===================================
624 12:16:10.764631 ANA top config
625 12:16:10.767448 ===================================
626 12:16:10.770581 DLL_ASYNC_EN = 0
627 12:16:10.773857 ALL_SLAVE_EN = 1
628 12:16:10.777453 NEW_RANK_MODE = 1
629 12:16:10.780199 DLL_IDLE_MODE = 1
630 12:16:10.780677 LP45_APHY_COMB_EN = 1
631 12:16:10.783775 TX_ODT_DIS = 1
632 12:16:10.787054 NEW_8X_MODE = 1
633 12:16:10.790022 ===================================
634 12:16:10.794383 ===================================
635 12:16:10.796950 data_rate = 1600
636 12:16:10.800135 CKR = 1
637 12:16:10.800564 DQ_P2S_RATIO = 8
638 12:16:10.803168 ===================================
639 12:16:10.807156 CA_P2S_RATIO = 8
640 12:16:10.810853 DQ_CA_OPEN = 0
641 12:16:10.814765 DQ_SEMI_OPEN = 0
642 12:16:10.817247 CA_SEMI_OPEN = 0
643 12:16:10.817678 CA_FULL_RATE = 0
644 12:16:10.820954 DQ_CKDIV4_EN = 1
645 12:16:10.824729 CA_CKDIV4_EN = 1
646 12:16:10.827065 CA_PREDIV_EN = 0
647 12:16:10.831247 PH8_DLY = 0
648 12:16:10.833866 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 12:16:10.834298 DQ_AAMCK_DIV = 4
650 12:16:10.837805 CA_AAMCK_DIV = 4
651 12:16:10.840431 CA_ADMCK_DIV = 4
652 12:16:10.843719 DQ_TRACK_CA_EN = 0
653 12:16:10.846848 CA_PICK = 800
654 12:16:10.850997 CA_MCKIO = 800
655 12:16:10.851611 MCKIO_SEMI = 0
656 12:16:10.854001 PLL_FREQ = 3068
657 12:16:10.857631 DQ_UI_PI_RATIO = 32
658 12:16:10.861341 CA_UI_PI_RATIO = 0
659 12:16:10.865098 ===================================
660 12:16:10.869321 ===================================
661 12:16:10.869757 memory_type:LPDDR4
662 12:16:10.872620 GP_NUM : 10
663 12:16:10.873049 SRAM_EN : 1
664 12:16:10.876158 MD32_EN : 0
665 12:16:10.879955 ===================================
666 12:16:10.880388 [ANA_INIT] >>>>>>>>>>>>>>
667 12:16:10.883945 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 12:16:10.887229 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 12:16:10.890997 ===================================
670 12:16:10.894371 data_rate = 1600,PCW = 0X7600
671 12:16:10.898376 ===================================
672 12:16:10.900846 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 12:16:10.904578 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 12:16:10.911078 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 12:16:10.917374 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 12:16:10.921029 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 12:16:10.923951 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 12:16:10.924382 [ANA_INIT] flow start
679 12:16:10.927476 [ANA_INIT] PLL >>>>>>>>
680 12:16:10.931075 [ANA_INIT] PLL <<<<<<<<
681 12:16:10.931637 [ANA_INIT] MIDPI >>>>>>>>
682 12:16:10.933779 [ANA_INIT] MIDPI <<<<<<<<
683 12:16:10.937283 [ANA_INIT] DLL >>>>>>>>
684 12:16:10.937716 [ANA_INIT] flow end
685 12:16:10.943831 ============ LP4 DIFF to SE enter ============
686 12:16:10.947857 ============ LP4 DIFF to SE exit ============
687 12:16:10.948286 [ANA_INIT] <<<<<<<<<<<<<
688 12:16:10.950679 [Flow] Enable top DCM control >>>>>
689 12:16:10.954190 [Flow] Enable top DCM control <<<<<
690 12:16:10.957361 Enable DLL master slave shuffle
691 12:16:10.964132 ==============================================================
692 12:16:10.967046 Gating Mode config
693 12:16:10.970548 ==============================================================
694 12:16:10.974327 Config description:
695 12:16:10.984194 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 12:16:10.990328 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 12:16:10.993951 SELPH_MODE 0: By rank 1: By Phase
698 12:16:11.000238 ==============================================================
699 12:16:11.003867 GAT_TRACK_EN = 1
700 12:16:11.007356 RX_GATING_MODE = 2
701 12:16:11.010093 RX_GATING_TRACK_MODE = 2
702 12:16:11.010537 SELPH_MODE = 1
703 12:16:11.013555 PICG_EARLY_EN = 1
704 12:16:11.017009 VALID_LAT_VALUE = 1
705 12:16:11.023587 ==============================================================
706 12:16:11.026996 Enter into Gating configuration >>>>
707 12:16:11.030356 Exit from Gating configuration <<<<
708 12:16:11.033227 Enter into DVFS_PRE_config >>>>>
709 12:16:11.043510 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 12:16:11.046729 Exit from DVFS_PRE_config <<<<<
711 12:16:11.050648 Enter into PICG configuration >>>>
712 12:16:11.053902 Exit from PICG configuration <<<<
713 12:16:11.057000 [RX_INPUT] configuration >>>>>
714 12:16:11.060830 [RX_INPUT] configuration <<<<<
715 12:16:11.063643 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 12:16:11.070778 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 12:16:11.077396 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 12:16:11.083546 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 12:16:11.086916 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 12:16:11.093677 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 12:16:11.096930 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 12:16:11.103226 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 12:16:11.106973 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 12:16:11.110751 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 12:16:11.113743 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 12:16:11.120132 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 12:16:11.124413 ===================================
728 12:16:11.124912 LPDDR4 DRAM CONFIGURATION
729 12:16:11.126751 ===================================
730 12:16:11.130593 EX_ROW_EN[0] = 0x0
731 12:16:11.133406 EX_ROW_EN[1] = 0x0
732 12:16:11.133994 LP4Y_EN = 0x0
733 12:16:11.137189 WORK_FSP = 0x0
734 12:16:11.137628 WL = 0x2
735 12:16:11.139987 RL = 0x2
736 12:16:11.140416 BL = 0x2
737 12:16:11.143397 RPST = 0x0
738 12:16:11.143923 RD_PRE = 0x0
739 12:16:11.146943 WR_PRE = 0x1
740 12:16:11.147475 WR_PST = 0x0
741 12:16:11.150133 DBI_WR = 0x0
742 12:16:11.150576 DBI_RD = 0x0
743 12:16:11.153078 OTF = 0x1
744 12:16:11.156611 ===================================
745 12:16:11.159988 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 12:16:11.163764 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 12:16:11.170401 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 12:16:11.174039 ===================================
749 12:16:11.174600 LPDDR4 DRAM CONFIGURATION
750 12:16:11.176354 ===================================
751 12:16:11.180743 EX_ROW_EN[0] = 0x10
752 12:16:11.182768 EX_ROW_EN[1] = 0x0
753 12:16:11.183217 LP4Y_EN = 0x0
754 12:16:11.187218 WORK_FSP = 0x0
755 12:16:11.187707 WL = 0x2
756 12:16:11.189489 RL = 0x2
757 12:16:11.189934 BL = 0x2
758 12:16:11.193115 RPST = 0x0
759 12:16:11.193561 RD_PRE = 0x0
760 12:16:11.196498 WR_PRE = 0x1
761 12:16:11.196945 WR_PST = 0x0
762 12:16:11.199821 DBI_WR = 0x0
763 12:16:11.200265 DBI_RD = 0x0
764 12:16:11.203211 OTF = 0x1
765 12:16:11.206496 ===================================
766 12:16:11.212822 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 12:16:11.216287 nWR fixed to 40
768 12:16:11.216863 [ModeRegInit_LP4] CH0 RK0
769 12:16:11.219548 [ModeRegInit_LP4] CH0 RK1
770 12:16:11.222854 [ModeRegInit_LP4] CH1 RK0
771 12:16:11.226755 [ModeRegInit_LP4] CH1 RK1
772 12:16:11.227308 match AC timing 13
773 12:16:11.230645 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 12:16:11.236418 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 12:16:11.239843 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 12:16:11.246548 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 12:16:11.249541 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 12:16:11.250063 [EMI DOE] emi_dcm 0
779 12:16:11.256386 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 12:16:11.256910 ==
781 12:16:11.261071 Dram Type= 6, Freq= 0, CH_0, rank 0
782 12:16:11.263223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 12:16:11.263708 ==
784 12:16:11.269619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 12:16:11.272920 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 12:16:11.283427 [CA 0] Center 37 (7~68) winsize 62
787 12:16:11.286718 [CA 1] Center 37 (6~68) winsize 63
788 12:16:11.289944 [CA 2] Center 34 (4~65) winsize 62
789 12:16:11.293572 [CA 3] Center 35 (4~66) winsize 63
790 12:16:11.296668 [CA 4] Center 33 (3~64) winsize 62
791 12:16:11.300357 [CA 5] Center 33 (3~64) winsize 62
792 12:16:11.300780
793 12:16:11.303633 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 12:16:11.304071
795 12:16:11.306877 [CATrainingPosCal] consider 1 rank data
796 12:16:11.310163 u2DelayCellTimex100 = 270/100 ps
797 12:16:11.313120 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 12:16:11.320234 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 12:16:11.323025 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 12:16:11.326169 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
801 12:16:11.329635 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 12:16:11.332845 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 12:16:11.333293
804 12:16:11.336432 CA PerBit enable=1, Macro0, CA PI delay=33
805 12:16:11.336877
806 12:16:11.339551 [CBTSetCACLKResult] CA Dly = 33
807 12:16:11.339998 CS Dly: 5 (0~36)
808 12:16:11.342790 ==
809 12:16:11.346388 Dram Type= 6, Freq= 0, CH_0, rank 1
810 12:16:11.349981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 12:16:11.350475 ==
812 12:16:11.352764 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 12:16:11.359413 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 12:16:11.369620 [CA 0] Center 38 (7~69) winsize 63
815 12:16:11.372823 [CA 1] Center 37 (7~68) winsize 62
816 12:16:11.376058 [CA 2] Center 35 (4~66) winsize 63
817 12:16:11.379582 [CA 3] Center 35 (4~66) winsize 63
818 12:16:11.382889 [CA 4] Center 34 (3~65) winsize 63
819 12:16:11.386278 [CA 5] Center 33 (3~64) winsize 62
820 12:16:11.386726
821 12:16:11.389300 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 12:16:11.389740
823 12:16:11.393262 [CATrainingPosCal] consider 2 rank data
824 12:16:11.396023 u2DelayCellTimex100 = 270/100 ps
825 12:16:11.399358 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 12:16:11.406199 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 12:16:11.409240 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 12:16:11.412382 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
829 12:16:11.416206 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 12:16:11.419058 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 12:16:11.419515
832 12:16:11.422545 CA PerBit enable=1, Macro0, CA PI delay=33
833 12:16:11.422969
834 12:16:11.426024 [CBTSetCACLKResult] CA Dly = 33
835 12:16:11.426553 CS Dly: 6 (0~38)
836 12:16:11.429459
837 12:16:11.432822 ----->DramcWriteLeveling(PI) begin...
838 12:16:11.433341 ==
839 12:16:11.437034 Dram Type= 6, Freq= 0, CH_0, rank 0
840 12:16:11.439761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 12:16:11.440187 ==
842 12:16:11.443621 Write leveling (Byte 0): 31 => 31
843 12:16:11.444046 Write leveling (Byte 1): 29 => 29
844 12:16:11.447265 DramcWriteLeveling(PI) end<-----
845 12:16:11.447729
846 12:16:11.448064 ==
847 12:16:11.451242 Dram Type= 6, Freq= 0, CH_0, rank 0
848 12:16:11.454799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 12:16:11.457610 ==
850 12:16:11.458138 [Gating] SW mode calibration
851 12:16:11.464461 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 12:16:11.472012 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 12:16:11.475180 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 12:16:11.481396 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 12:16:11.484836 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
856 12:16:11.488337 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 12:16:11.491451 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 12:16:11.498200 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 12:16:11.501718 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 12:16:11.504939 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 12:16:11.511534 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 12:16:11.514799 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 12:16:11.518001 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 12:16:11.524464 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 12:16:11.528256 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 12:16:11.531573 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 12:16:11.537994 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 12:16:11.541645 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 12:16:11.544700 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 12:16:11.551247 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 12:16:11.554516 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 12:16:11.558903 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 12:16:11.564309 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 12:16:11.568043 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 12:16:11.571477 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 12:16:11.577765 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 12:16:11.580927 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 12:16:11.584435 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 12:16:11.591332 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
880 12:16:11.594255 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
881 12:16:11.598300 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 12:16:11.604202 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 12:16:11.607774 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 12:16:11.611069 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 12:16:11.617423 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 12:16:11.620881 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
887 12:16:11.624036 0 10 8 | B1->B0 | 3333 2a2a | 1 0 | (1 0) (0 0)
888 12:16:11.630951 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
889 12:16:11.634052 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 12:16:11.637691 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 12:16:11.641331 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 12:16:11.647715 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 12:16:11.650897 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 12:16:11.654166 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
895 12:16:11.660738 0 11 8 | B1->B0 | 2828 4545 | 0 0 | (0 0) (0 0)
896 12:16:11.664012 0 11 12 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
897 12:16:11.667584 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 12:16:11.674432 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 12:16:11.677728 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 12:16:11.680952 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 12:16:11.687216 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 12:16:11.690684 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 12:16:11.694292 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 12:16:11.700764 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 12:16:11.704206 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 12:16:11.707782 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 12:16:11.714001 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 12:16:11.717274 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 12:16:11.720746 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 12:16:11.727142 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 12:16:11.730251 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 12:16:11.733939 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 12:16:11.740172 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 12:16:11.744137 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 12:16:11.747277 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 12:16:11.753822 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 12:16:11.756947 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 12:16:11.760271 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 12:16:11.766987 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 12:16:11.770514 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
921 12:16:11.774270 Total UI for P1: 0, mck2ui 16
922 12:16:11.777079 best dqsien dly found for B0: ( 0, 14, 8)
923 12:16:11.780347 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 12:16:11.783883 Total UI for P1: 0, mck2ui 16
925 12:16:11.786880 best dqsien dly found for B1: ( 0, 14, 12)
926 12:16:11.790183 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
927 12:16:11.793358 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
928 12:16:11.793801
929 12:16:11.796803 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 12:16:11.803602 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
931 12:16:11.804036 [Gating] SW calibration Done
932 12:16:11.804400 ==
933 12:16:11.807489 Dram Type= 6, Freq= 0, CH_0, rank 0
934 12:16:11.810709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 12:16:11.813862 ==
936 12:16:11.814401 RX Vref Scan: 0
937 12:16:11.814785
938 12:16:11.817149 RX Vref 0 -> 0, step: 1
939 12:16:11.817573
940 12:16:11.821021 RX Delay -130 -> 252, step: 16
941 12:16:11.823750 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
942 12:16:11.827530 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
943 12:16:11.830443 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
944 12:16:11.834195 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
945 12:16:11.840730 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
946 12:16:11.843684 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
947 12:16:11.847813 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
948 12:16:11.851341 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
949 12:16:11.853845 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
950 12:16:11.860692 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
951 12:16:11.863786 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
952 12:16:11.867274 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
953 12:16:11.870508 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
954 12:16:11.874275 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
955 12:16:11.880464 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
956 12:16:11.883783 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
957 12:16:11.884215 ==
958 12:16:11.886818 Dram Type= 6, Freq= 0, CH_0, rank 0
959 12:16:11.890309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 12:16:11.890742 ==
961 12:16:11.893464 DQS Delay:
962 12:16:11.893912 DQS0 = 0, DQS1 = 0
963 12:16:11.894251 DQM Delay:
964 12:16:11.897052 DQM0 = 89, DQM1 = 77
965 12:16:11.897481 DQ Delay:
966 12:16:11.901448 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
967 12:16:11.903729 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
968 12:16:11.906910 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
969 12:16:11.910462 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
970 12:16:11.910961
971 12:16:11.911304
972 12:16:11.911760 ==
973 12:16:11.913493 Dram Type= 6, Freq= 0, CH_0, rank 0
974 12:16:11.920251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 12:16:11.920684 ==
976 12:16:11.921024
977 12:16:11.921337
978 12:16:11.921712 TX Vref Scan disable
979 12:16:11.923871 == TX Byte 0 ==
980 12:16:11.927023 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
981 12:16:11.934041 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
982 12:16:11.934532 == TX Byte 1 ==
983 12:16:11.937220 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
984 12:16:11.944082 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
985 12:16:11.944515 ==
986 12:16:11.947053 Dram Type= 6, Freq= 0, CH_0, rank 0
987 12:16:11.950405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 12:16:11.950842 ==
989 12:16:11.962820 TX Vref=22, minBit 0, minWin=26, winSum=436
990 12:16:11.966436 TX Vref=24, minBit 0, minWin=27, winSum=442
991 12:16:11.969695 TX Vref=26, minBit 1, minWin=27, winSum=448
992 12:16:11.972596 TX Vref=28, minBit 0, minWin=28, winSum=453
993 12:16:11.976149 TX Vref=30, minBit 3, minWin=27, winSum=449
994 12:16:11.983074 TX Vref=32, minBit 2, minWin=27, winSum=452
995 12:16:11.987090 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 28
996 12:16:11.987566
997 12:16:11.989725 Final TX Range 1 Vref 28
998 12:16:11.990250
999 12:16:11.990594 ==
1000 12:16:11.992633 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 12:16:11.996543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 12:16:11.997053 ==
1003 12:16:11.999446
1004 12:16:11.999971
1005 12:16:12.000318 TX Vref Scan disable
1006 12:16:12.002913 == TX Byte 0 ==
1007 12:16:12.006288 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1008 12:16:12.009678 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1009 12:16:12.013221 == TX Byte 1 ==
1010 12:16:12.016424 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1011 12:16:12.019572 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1012 12:16:12.023198
1013 12:16:12.023662 [DATLAT]
1014 12:16:12.024004 Freq=800, CH0 RK0
1015 12:16:12.024322
1016 12:16:12.026413 DATLAT Default: 0xa
1017 12:16:12.026925 0, 0xFFFF, sum = 0
1018 12:16:12.029662 1, 0xFFFF, sum = 0
1019 12:16:12.030213 2, 0xFFFF, sum = 0
1020 12:16:12.033197 3, 0xFFFF, sum = 0
1021 12:16:12.033703 4, 0xFFFF, sum = 0
1022 12:16:12.036054 5, 0xFFFF, sum = 0
1023 12:16:12.039719 6, 0xFFFF, sum = 0
1024 12:16:12.040165 7, 0xFFFF, sum = 0
1025 12:16:12.042759 8, 0xFFFF, sum = 0
1026 12:16:12.043181 9, 0x0, sum = 1
1027 12:16:12.043577 10, 0x0, sum = 2
1028 12:16:12.045866 11, 0x0, sum = 3
1029 12:16:12.046381 12, 0x0, sum = 4
1030 12:16:12.049755 best_step = 10
1031 12:16:12.050166
1032 12:16:12.050494 ==
1033 12:16:12.052951 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 12:16:12.055887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 12:16:12.056304 ==
1036 12:16:12.059694 RX Vref Scan: 1
1037 12:16:12.060181
1038 12:16:12.060512 Set Vref Range= 32 -> 127
1039 12:16:12.062346
1040 12:16:12.062761 RX Vref 32 -> 127, step: 1
1041 12:16:12.063091
1042 12:16:12.066642 RX Delay -95 -> 252, step: 8
1043 12:16:12.067151
1044 12:16:12.069444 Set Vref, RX VrefLevel [Byte0]: 32
1045 12:16:12.072645 [Byte1]: 32
1046 12:16:12.073148
1047 12:16:12.076357 Set Vref, RX VrefLevel [Byte0]: 33
1048 12:16:12.079433 [Byte1]: 33
1049 12:16:12.083344
1050 12:16:12.084058 Set Vref, RX VrefLevel [Byte0]: 34
1051 12:16:12.086315 [Byte1]: 34
1052 12:16:12.090734
1053 12:16:12.091149 Set Vref, RX VrefLevel [Byte0]: 35
1054 12:16:12.094187 [Byte1]: 35
1055 12:16:12.098398
1056 12:16:12.098809 Set Vref, RX VrefLevel [Byte0]: 36
1057 12:16:12.102365 [Byte1]: 36
1058 12:16:12.105737
1059 12:16:12.106204 Set Vref, RX VrefLevel [Byte0]: 37
1060 12:16:12.109575 [Byte1]: 37
1061 12:16:12.113929
1062 12:16:12.114578 Set Vref, RX VrefLevel [Byte0]: 38
1063 12:16:12.117754 [Byte1]: 38
1064 12:16:12.121298
1065 12:16:12.121711 Set Vref, RX VrefLevel [Byte0]: 39
1066 12:16:12.124960 [Byte1]: 39
1067 12:16:12.129173
1068 12:16:12.129662 Set Vref, RX VrefLevel [Byte0]: 40
1069 12:16:12.132514 [Byte1]: 40
1070 12:16:12.136620
1071 12:16:12.137029 Set Vref, RX VrefLevel [Byte0]: 41
1072 12:16:12.140144 [Byte1]: 41
1073 12:16:12.144702
1074 12:16:12.145234 Set Vref, RX VrefLevel [Byte0]: 42
1075 12:16:12.147201 [Byte1]: 42
1076 12:16:12.151332
1077 12:16:12.151794 Set Vref, RX VrefLevel [Byte0]: 43
1078 12:16:12.154899 [Byte1]: 43
1079 12:16:12.158976
1080 12:16:12.159520 Set Vref, RX VrefLevel [Byte0]: 44
1081 12:16:12.162260 [Byte1]: 44
1082 12:16:12.166642
1083 12:16:12.167152 Set Vref, RX VrefLevel [Byte0]: 45
1084 12:16:12.169974 [Byte1]: 45
1085 12:16:12.174402
1086 12:16:12.174845 Set Vref, RX VrefLevel [Byte0]: 46
1087 12:16:12.177844 [Byte1]: 46
1088 12:16:12.181789
1089 12:16:12.182210 Set Vref, RX VrefLevel [Byte0]: 47
1090 12:16:12.185431 [Byte1]: 47
1091 12:16:12.189754
1092 12:16:12.190203 Set Vref, RX VrefLevel [Byte0]: 48
1093 12:16:12.193213 [Byte1]: 48
1094 12:16:12.196977
1095 12:16:12.197399 Set Vref, RX VrefLevel [Byte0]: 49
1096 12:16:12.200651 [Byte1]: 49
1097 12:16:12.204747
1098 12:16:12.205170 Set Vref, RX VrefLevel [Byte0]: 50
1099 12:16:12.208007 [Byte1]: 50
1100 12:16:12.212259
1101 12:16:12.212677 Set Vref, RX VrefLevel [Byte0]: 51
1102 12:16:12.215392 [Byte1]: 51
1103 12:16:12.219971
1104 12:16:12.220440 Set Vref, RX VrefLevel [Byte0]: 52
1105 12:16:12.223127 [Byte1]: 52
1106 12:16:12.227719
1107 12:16:12.228132 Set Vref, RX VrefLevel [Byte0]: 53
1108 12:16:12.230969 [Byte1]: 53
1109 12:16:12.235329
1110 12:16:12.235780 Set Vref, RX VrefLevel [Byte0]: 54
1111 12:16:12.238007 [Byte1]: 54
1112 12:16:12.242745
1113 12:16:12.243184 Set Vref, RX VrefLevel [Byte0]: 55
1114 12:16:12.245964 [Byte1]: 55
1115 12:16:12.250691
1116 12:16:12.251211 Set Vref, RX VrefLevel [Byte0]: 56
1117 12:16:12.253705 [Byte1]: 56
1118 12:16:12.258405
1119 12:16:12.258930 Set Vref, RX VrefLevel [Byte0]: 57
1120 12:16:12.261730 [Byte1]: 57
1121 12:16:12.265385
1122 12:16:12.265800 Set Vref, RX VrefLevel [Byte0]: 58
1123 12:16:12.271887 [Byte1]: 58
1124 12:16:12.272411
1125 12:16:12.275143 Set Vref, RX VrefLevel [Byte0]: 59
1126 12:16:12.278407 [Byte1]: 59
1127 12:16:12.278900
1128 12:16:12.281602 Set Vref, RX VrefLevel [Byte0]: 60
1129 12:16:12.284901 [Byte1]: 60
1130 12:16:12.288489
1131 12:16:12.288907 Set Vref, RX VrefLevel [Byte0]: 61
1132 12:16:12.291353 [Byte1]: 61
1133 12:16:12.295768
1134 12:16:12.296185 Set Vref, RX VrefLevel [Byte0]: 62
1135 12:16:12.299401 [Byte1]: 62
1136 12:16:12.303662
1137 12:16:12.304090 Set Vref, RX VrefLevel [Byte0]: 63
1138 12:16:12.306690 [Byte1]: 63
1139 12:16:12.310783
1140 12:16:12.311244 Set Vref, RX VrefLevel [Byte0]: 64
1141 12:16:12.314281 [Byte1]: 64
1142 12:16:12.319160
1143 12:16:12.319745 Set Vref, RX VrefLevel [Byte0]: 65
1144 12:16:12.321713 [Byte1]: 65
1145 12:16:12.326105
1146 12:16:12.326524 Set Vref, RX VrefLevel [Byte0]: 66
1147 12:16:12.329303 [Byte1]: 66
1148 12:16:12.333946
1149 12:16:12.334370 Set Vref, RX VrefLevel [Byte0]: 67
1150 12:16:12.337098 [Byte1]: 67
1151 12:16:12.341520
1152 12:16:12.341939 Set Vref, RX VrefLevel [Byte0]: 68
1153 12:16:12.344653 [Byte1]: 68
1154 12:16:12.349142
1155 12:16:12.349658 Set Vref, RX VrefLevel [Byte0]: 69
1156 12:16:12.352702 [Byte1]: 69
1157 12:16:12.356947
1158 12:16:12.357414 Set Vref, RX VrefLevel [Byte0]: 70
1159 12:16:12.359827 [Byte1]: 70
1160 12:16:12.364596
1161 12:16:12.365084 Set Vref, RX VrefLevel [Byte0]: 71
1162 12:16:12.368234 [Byte1]: 71
1163 12:16:12.371912
1164 12:16:12.372396 Set Vref, RX VrefLevel [Byte0]: 72
1165 12:16:12.375344 [Byte1]: 72
1166 12:16:12.379412
1167 12:16:12.379914 Set Vref, RX VrefLevel [Byte0]: 73
1168 12:16:12.383170 [Byte1]: 73
1169 12:16:12.387338
1170 12:16:12.387796 Final RX Vref Byte 0 = 55 to rank0
1171 12:16:12.390451 Final RX Vref Byte 1 = 60 to rank0
1172 12:16:12.393606 Final RX Vref Byte 0 = 55 to rank1
1173 12:16:12.397092 Final RX Vref Byte 1 = 60 to rank1==
1174 12:16:12.400242 Dram Type= 6, Freq= 0, CH_0, rank 0
1175 12:16:12.406714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1176 12:16:12.407155 ==
1177 12:16:12.407653 DQS Delay:
1178 12:16:12.410044 DQS0 = 0, DQS1 = 0
1179 12:16:12.410480 DQM Delay:
1180 12:16:12.410926 DQM0 = 88, DQM1 = 76
1181 12:16:12.413528 DQ Delay:
1182 12:16:12.416621 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1183 12:16:12.420554 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1184 12:16:12.423862 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =72
1185 12:16:12.427157 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1186 12:16:12.427756
1187 12:16:12.428233
1188 12:16:12.433735 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
1189 12:16:12.436891 CH0 RK0: MR19=606, MR18=2D27
1190 12:16:12.443593 CH0_RK0: MR19=0x606, MR18=0x2D27, DQSOSC=398, MR23=63, INC=93, DEC=62
1191 12:16:12.444126
1192 12:16:12.446856 ----->DramcWriteLeveling(PI) begin...
1193 12:16:12.447445 ==
1194 12:16:12.450020 Dram Type= 6, Freq= 0, CH_0, rank 1
1195 12:16:12.453823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1196 12:16:12.454369 ==
1197 12:16:12.456563 Write leveling (Byte 0): 30 => 30
1198 12:16:12.460877 Write leveling (Byte 1): 26 => 26
1199 12:16:12.463412 DramcWriteLeveling(PI) end<-----
1200 12:16:12.463953
1201 12:16:12.464415 ==
1202 12:16:12.466735 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 12:16:12.470382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 12:16:12.470919 ==
1205 12:16:12.473427 [Gating] SW mode calibration
1206 12:16:12.480139 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1207 12:16:12.486312 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1208 12:16:12.489796 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1209 12:16:12.493166 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1210 12:16:12.537612 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1211 12:16:12.538567 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1212 12:16:12.538963 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 12:16:12.539427 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 12:16:12.539794 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 12:16:12.540144 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 12:16:12.540639 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 12:16:12.540980 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 12:16:12.541299 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 12:16:12.541611 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 12:16:12.565332 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 12:16:12.566233 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 12:16:12.566738 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 12:16:12.567171 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 12:16:12.567575 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 12:16:12.567914 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1226 12:16:12.569555 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1227 12:16:12.572944 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 12:16:12.579252 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 12:16:12.582838 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 12:16:12.586301 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 12:16:12.593092 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 12:16:12.596600 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 12:16:12.599503 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
1234 12:16:12.606653 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
1235 12:16:12.609307 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1236 12:16:12.612751 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 12:16:12.619962 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 12:16:12.622342 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 12:16:12.625684 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 12:16:12.629153 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 12:16:12.636073 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
1242 12:16:12.638915 0 10 8 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (1 0)
1243 12:16:12.642384 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1244 12:16:12.649116 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 12:16:12.652227 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 12:16:12.655422 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 12:16:12.662527 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 12:16:12.665437 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 12:16:12.669243 0 11 4 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
1250 12:16:12.675497 0 11 8 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
1251 12:16:12.678688 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1252 12:16:12.682413 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 12:16:12.686509 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 12:16:12.693890 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 12:16:12.697204 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 12:16:12.700871 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 12:16:12.703972 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1258 12:16:12.711378 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1259 12:16:12.714630 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 12:16:12.718076 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 12:16:12.721590 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 12:16:12.728676 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 12:16:12.731480 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 12:16:12.735212 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 12:16:12.741428 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 12:16:12.744912 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 12:16:12.748406 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 12:16:12.755312 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 12:16:12.757864 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 12:16:12.761250 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 12:16:12.768219 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 12:16:12.771514 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 12:16:12.774724 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1274 12:16:12.777976 Total UI for P1: 0, mck2ui 16
1275 12:16:12.781432 best dqsien dly found for B0: ( 0, 14, 2)
1276 12:16:12.787892 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1277 12:16:12.790870 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 12:16:12.794193 Total UI for P1: 0, mck2ui 16
1279 12:16:12.797726 best dqsien dly found for B1: ( 0, 14, 6)
1280 12:16:12.801429 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1281 12:16:12.804502 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1282 12:16:12.804921
1283 12:16:12.807347 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1284 12:16:12.811496 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1285 12:16:12.814764 [Gating] SW calibration Done
1286 12:16:12.815179 ==
1287 12:16:12.818533 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 12:16:12.820610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 12:16:12.824463 ==
1290 12:16:12.824952 RX Vref Scan: 0
1291 12:16:12.825287
1292 12:16:12.827319 RX Vref 0 -> 0, step: 1
1293 12:16:12.827770
1294 12:16:12.830953 RX Delay -130 -> 252, step: 16
1295 12:16:12.834132 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1296 12:16:12.837480 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1297 12:16:12.841186 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1298 12:16:12.844230 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1299 12:16:12.850774 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1300 12:16:12.854236 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1301 12:16:12.857281 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1302 12:16:12.860454 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1303 12:16:12.864033 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1304 12:16:12.870604 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1305 12:16:12.874270 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1306 12:16:12.877530 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1307 12:16:12.880729 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1308 12:16:12.883714 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1309 12:16:12.890851 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1310 12:16:12.893851 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1311 12:16:12.894275 ==
1312 12:16:12.897151 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 12:16:12.900559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1314 12:16:12.900984 ==
1315 12:16:12.903696 DQS Delay:
1316 12:16:12.904236 DQS0 = 0, DQS1 = 0
1317 12:16:12.907207 DQM Delay:
1318 12:16:12.907671 DQM0 = 85, DQM1 = 77
1319 12:16:12.908009 DQ Delay:
1320 12:16:12.911075 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1321 12:16:12.913401 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
1322 12:16:12.917064 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1323 12:16:12.920354 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1324 12:16:12.920775
1325 12:16:12.921110
1326 12:16:12.921425 ==
1327 12:16:12.923259 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 12:16:12.930239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 12:16:12.930822 ==
1330 12:16:12.931167
1331 12:16:12.931529
1332 12:16:12.933602 TX Vref Scan disable
1333 12:16:12.934075 == TX Byte 0 ==
1334 12:16:12.936599 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1335 12:16:12.943217 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1336 12:16:12.943835 == TX Byte 1 ==
1337 12:16:12.946967 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1338 12:16:12.953023 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1339 12:16:12.953608 ==
1340 12:16:12.956599 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 12:16:12.959800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 12:16:12.960220 ==
1343 12:16:12.973464 TX Vref=22, minBit 0, minWin=27, winSum=438
1344 12:16:12.977043 TX Vref=24, minBit 0, minWin=27, winSum=444
1345 12:16:12.979753 TX Vref=26, minBit 2, minWin=27, winSum=447
1346 12:16:12.983754 TX Vref=28, minBit 2, minWin=27, winSum=453
1347 12:16:12.986583 TX Vref=30, minBit 2, minWin=27, winSum=446
1348 12:16:12.990253 TX Vref=32, minBit 6, minWin=27, winSum=449
1349 12:16:12.996823 [TxChooseVref] Worse bit 2, Min win 27, Win sum 453, Final Vref 28
1350 12:16:12.997244
1351 12:16:13.000082 Final TX Range 1 Vref 28
1352 12:16:13.000501
1353 12:16:13.000832 ==
1354 12:16:13.004060 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 12:16:13.006799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 12:16:13.007214 ==
1357 12:16:13.007601
1358 12:16:13.009901
1359 12:16:13.010314 TX Vref Scan disable
1360 12:16:13.013391 == TX Byte 0 ==
1361 12:16:13.016930 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1362 12:16:13.023543 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1363 12:16:13.023962 == TX Byte 1 ==
1364 12:16:13.026824 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1365 12:16:13.033011 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1366 12:16:13.033460
1367 12:16:13.033787 [DATLAT]
1368 12:16:13.034092 Freq=800, CH0 RK1
1369 12:16:13.034386
1370 12:16:13.036657 DATLAT Default: 0xa
1371 12:16:13.036954 0, 0xFFFF, sum = 0
1372 12:16:13.039351 1, 0xFFFF, sum = 0
1373 12:16:13.043384 2, 0xFFFF, sum = 0
1374 12:16:13.043684 3, 0xFFFF, sum = 0
1375 12:16:13.046797 4, 0xFFFF, sum = 0
1376 12:16:13.047199 5, 0xFFFF, sum = 0
1377 12:16:13.049441 6, 0xFFFF, sum = 0
1378 12:16:13.049739 7, 0xFFFF, sum = 0
1379 12:16:13.053842 8, 0xFFFF, sum = 0
1380 12:16:13.054247 9, 0x0, sum = 1
1381 12:16:13.056411 10, 0x0, sum = 2
1382 12:16:13.056711 11, 0x0, sum = 3
1383 12:16:13.056984 12, 0x0, sum = 4
1384 12:16:13.059781 best_step = 10
1385 12:16:13.060207
1386 12:16:13.060454 ==
1387 12:16:13.062662 Dram Type= 6, Freq= 0, CH_0, rank 1
1388 12:16:13.066021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1389 12:16:13.066316 ==
1390 12:16:13.069514 RX Vref Scan: 0
1391 12:16:13.069810
1392 12:16:13.070043 RX Vref 0 -> 0, step: 1
1393 12:16:13.072637
1394 12:16:13.073030 RX Delay -95 -> 252, step: 8
1395 12:16:13.080119 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1396 12:16:13.083016 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1397 12:16:13.086269 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1398 12:16:13.089844 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1399 12:16:13.093026 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1400 12:16:13.099663 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1401 12:16:13.102892 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1402 12:16:13.106183 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1403 12:16:13.110142 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1404 12:16:13.113483 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1405 12:16:13.119474 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1406 12:16:13.123138 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1407 12:16:13.126078 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1408 12:16:13.129842 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1409 12:16:13.136746 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1410 12:16:13.139645 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1411 12:16:13.139939 ==
1412 12:16:13.143080 Dram Type= 6, Freq= 0, CH_0, rank 1
1413 12:16:13.146083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 12:16:13.146310 ==
1415 12:16:13.149378 DQS Delay:
1416 12:16:13.149603 DQS0 = 0, DQS1 = 0
1417 12:16:13.149783 DQM Delay:
1418 12:16:13.152534 DQM0 = 86, DQM1 = 77
1419 12:16:13.152760 DQ Delay:
1420 12:16:13.156637 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1421 12:16:13.159315 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1422 12:16:13.163319 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1423 12:16:13.165759 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1424 12:16:13.165982
1425 12:16:13.166156
1426 12:16:13.175846 [DQSOSCAuto] RK1, (LSB)MR18= 0x2420, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1427 12:16:13.176004 CH0 RK1: MR19=606, MR18=2420
1428 12:16:13.182393 CH0_RK1: MR19=0x606, MR18=0x2420, DQSOSC=400, MR23=63, INC=92, DEC=61
1429 12:16:13.185466 [RxdqsGatingPostProcess] freq 800
1430 12:16:13.192861 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1431 12:16:13.195391 Pre-setting of DQS Precalculation
1432 12:16:13.198876 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1433 12:16:13.198979 ==
1434 12:16:13.202632 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 12:16:13.208804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 12:16:13.209000 ==
1437 12:16:13.212056 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1438 12:16:13.218619 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1439 12:16:13.228546 [CA 0] Center 37 (6~68) winsize 63
1440 12:16:13.231499 [CA 1] Center 37 (6~68) winsize 63
1441 12:16:13.234972 [CA 2] Center 35 (5~65) winsize 61
1442 12:16:13.238239 [CA 3] Center 34 (4~65) winsize 62
1443 12:16:13.241342 [CA 4] Center 34 (4~65) winsize 62
1444 12:16:13.244843 [CA 5] Center 33 (3~64) winsize 62
1445 12:16:13.245016
1446 12:16:13.248249 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1447 12:16:13.248447
1448 12:16:13.251953 [CATrainingPosCal] consider 1 rank data
1449 12:16:13.255045 u2DelayCellTimex100 = 270/100 ps
1450 12:16:13.258378 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1451 12:16:13.262499 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1452 12:16:13.268330 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1453 12:16:13.271920 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1454 12:16:13.275031 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1455 12:16:13.278418 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1456 12:16:13.278980
1457 12:16:13.281720 CA PerBit enable=1, Macro0, CA PI delay=33
1458 12:16:13.282183
1459 12:16:13.284915 [CBTSetCACLKResult] CA Dly = 33
1460 12:16:13.285336 CS Dly: 4 (0~35)
1461 12:16:13.288073 ==
1462 12:16:13.291684 Dram Type= 6, Freq= 0, CH_1, rank 1
1463 12:16:13.294497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1464 12:16:13.294920 ==
1465 12:16:13.301051 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1466 12:16:13.304384 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1467 12:16:13.314856 [CA 0] Center 36 (6~67) winsize 62
1468 12:16:13.317982 [CA 1] Center 36 (6~67) winsize 62
1469 12:16:13.321267 [CA 2] Center 34 (4~65) winsize 62
1470 12:16:13.325030 [CA 3] Center 33 (3~64) winsize 62
1471 12:16:13.327836 [CA 4] Center 34 (3~65) winsize 63
1472 12:16:13.331191 [CA 5] Center 34 (3~65) winsize 63
1473 12:16:13.331822
1474 12:16:13.334590 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1475 12:16:13.335156
1476 12:16:13.337528 [CATrainingPosCal] consider 2 rank data
1477 12:16:13.341222 u2DelayCellTimex100 = 270/100 ps
1478 12:16:13.344118 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1479 12:16:13.348068 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1480 12:16:13.352881 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1481 12:16:13.355762 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1482 12:16:13.359536 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1483 12:16:13.363449 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1484 12:16:13.363957
1485 12:16:13.369999 CA PerBit enable=1, Macro0, CA PI delay=33
1486 12:16:13.370422
1487 12:16:13.370758 [CBTSetCACLKResult] CA Dly = 33
1488 12:16:13.373031 CS Dly: 5 (0~38)
1489 12:16:13.373569
1490 12:16:13.376869 ----->DramcWriteLeveling(PI) begin...
1491 12:16:13.377484 ==
1492 12:16:13.381286 Dram Type= 6, Freq= 0, CH_1, rank 0
1493 12:16:13.383863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1494 12:16:13.384376 ==
1495 12:16:13.387136 Write leveling (Byte 0): 25 => 25
1496 12:16:13.390751 Write leveling (Byte 1): 29 => 29
1497 12:16:13.394525 DramcWriteLeveling(PI) end<-----
1498 12:16:13.394948
1499 12:16:13.395283 ==
1500 12:16:13.397146 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 12:16:13.400779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 12:16:13.401202 ==
1503 12:16:13.404283 [Gating] SW mode calibration
1504 12:16:13.410961 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1505 12:16:13.417287 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1506 12:16:13.420460 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1507 12:16:13.423351 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1508 12:16:13.430550 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 12:16:13.434059 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 12:16:13.437141 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 12:16:13.443970 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 12:16:13.447086 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 12:16:13.450443 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 12:16:13.456870 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 12:16:13.461353 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 12:16:13.463745 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 12:16:13.470629 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 12:16:13.474108 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 12:16:13.477316 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 12:16:13.484117 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 12:16:13.486706 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 12:16:13.490493 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1523 12:16:13.496557 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1524 12:16:13.500951 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1525 12:16:13.503482 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 12:16:13.506825 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 12:16:13.514145 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 12:16:13.516855 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 12:16:13.520235 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 12:16:13.526488 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 12:16:13.530510 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 12:16:13.534031 0 9 8 | B1->B0 | 2d2d 3333 | 0 1 | (1 1) (1 1)
1533 12:16:13.540031 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 12:16:13.543313 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 12:16:13.546379 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 12:16:13.553316 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 12:16:13.556486 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 12:16:13.559537 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 12:16:13.566144 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
1540 12:16:13.569451 0 10 8 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
1541 12:16:13.573342 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 12:16:13.579536 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 12:16:13.583462 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 12:16:13.586646 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 12:16:13.592778 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 12:16:13.596041 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 12:16:13.599522 0 11 4 | B1->B0 | 2727 2f2f | 0 0 | (0 0) (0 0)
1548 12:16:13.606338 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1549 12:16:13.609675 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 12:16:13.612859 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 12:16:13.619480 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 12:16:13.623127 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 12:16:13.625560 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 12:16:13.632201 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 12:16:13.635784 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 12:16:13.639324 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 12:16:13.646021 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 12:16:13.648797 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 12:16:13.652507 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 12:16:13.659216 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 12:16:13.662209 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 12:16:13.665539 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 12:16:13.672304 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 12:16:13.676020 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 12:16:13.678831 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 12:16:13.685741 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 12:16:13.689144 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 12:16:13.691807 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 12:16:13.699839 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 12:16:13.702279 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 12:16:13.705162 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 12:16:13.711785 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1573 12:16:13.712350 Total UI for P1: 0, mck2ui 16
1574 12:16:13.718814 best dqsien dly found for B0: ( 0, 14, 6)
1575 12:16:13.722055 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 12:16:13.725059 Total UI for P1: 0, mck2ui 16
1577 12:16:13.728382 best dqsien dly found for B1: ( 0, 14, 8)
1578 12:16:13.732065 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1579 12:16:13.735145 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1580 12:16:13.735682
1581 12:16:13.739038 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1582 12:16:13.742374 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1583 12:16:13.745288 [Gating] SW calibration Done
1584 12:16:13.745808 ==
1585 12:16:13.749046 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 12:16:13.751923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 12:16:13.752391 ==
1588 12:16:13.754900 RX Vref Scan: 0
1589 12:16:13.755318
1590 12:16:13.758439 RX Vref 0 -> 0, step: 1
1591 12:16:13.758953
1592 12:16:13.759288 RX Delay -130 -> 252, step: 16
1593 12:16:13.765081 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1594 12:16:13.768281 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1595 12:16:13.772013 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1596 12:16:13.775024 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1597 12:16:13.778582 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1598 12:16:13.785095 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1599 12:16:13.788687 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1600 12:16:13.791515 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1601 12:16:13.795315 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1602 12:16:13.798809 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1603 12:16:13.804982 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1604 12:16:13.808338 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1605 12:16:13.811654 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1606 12:16:13.815117 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1607 12:16:13.818168 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1608 12:16:13.825446 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1609 12:16:13.826054 ==
1610 12:16:13.828121 Dram Type= 6, Freq= 0, CH_1, rank 0
1611 12:16:13.831428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1612 12:16:13.831852 ==
1613 12:16:13.832182 DQS Delay:
1614 12:16:13.834630 DQS0 = 0, DQS1 = 0
1615 12:16:13.835041 DQM Delay:
1616 12:16:13.838030 DQM0 = 85, DQM1 = 79
1617 12:16:13.838443 DQ Delay:
1618 12:16:13.841168 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1619 12:16:13.845259 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1620 12:16:13.848308 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1621 12:16:13.851570 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1622 12:16:13.851986
1623 12:16:13.852313
1624 12:16:13.852615 ==
1625 12:16:13.854564 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 12:16:13.858239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 12:16:13.861807 ==
1628 12:16:13.862327
1629 12:16:13.862660
1630 12:16:13.862968 TX Vref Scan disable
1631 12:16:13.864517 == TX Byte 0 ==
1632 12:16:13.867825 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1633 12:16:13.871669 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1634 12:16:13.874584 == TX Byte 1 ==
1635 12:16:13.877912 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1636 12:16:13.881428 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1637 12:16:13.884490 ==
1638 12:16:13.887854 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 12:16:13.891119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 12:16:13.891594 ==
1641 12:16:13.904199 TX Vref=22, minBit 2, minWin=26, winSum=435
1642 12:16:13.906828 TX Vref=24, minBit 2, minWin=27, winSum=445
1643 12:16:13.910543 TX Vref=26, minBit 5, minWin=27, winSum=450
1644 12:16:13.913794 TX Vref=28, minBit 2, minWin=27, winSum=455
1645 12:16:13.916809 TX Vref=30, minBit 6, minWin=27, winSum=454
1646 12:16:13.923978 TX Vref=32, minBit 0, minWin=27, winSum=451
1647 12:16:13.927142 [TxChooseVref] Worse bit 2, Min win 27, Win sum 455, Final Vref 28
1648 12:16:13.927677
1649 12:16:13.931783 Final TX Range 1 Vref 28
1650 12:16:13.932298
1651 12:16:13.932632 ==
1652 12:16:13.934285 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 12:16:13.938016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 12:16:13.938539 ==
1655 12:16:13.938877
1656 12:16:13.939186
1657 12:16:13.940638 TX Vref Scan disable
1658 12:16:13.944185 == TX Byte 0 ==
1659 12:16:13.947284 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1660 12:16:13.950692 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1661 12:16:13.955839 == TX Byte 1 ==
1662 12:16:13.957218 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1663 12:16:13.960808 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1664 12:16:13.961330
1665 12:16:13.963876 [DATLAT]
1666 12:16:13.964298 Freq=800, CH1 RK0
1667 12:16:13.964640
1668 12:16:13.967565 DATLAT Default: 0xa
1669 12:16:13.968074 0, 0xFFFF, sum = 0
1670 12:16:13.970871 1, 0xFFFF, sum = 0
1671 12:16:13.971623 2, 0xFFFF, sum = 0
1672 12:16:13.973590 3, 0xFFFF, sum = 0
1673 12:16:13.974162 4, 0xFFFF, sum = 0
1674 12:16:13.978235 5, 0xFFFF, sum = 0
1675 12:16:13.978760 6, 0xFFFF, sum = 0
1676 12:16:13.981268 7, 0xFFFF, sum = 0
1677 12:16:13.983866 8, 0xFFFF, sum = 0
1678 12:16:13.984293 9, 0x0, sum = 1
1679 12:16:13.984634 10, 0x0, sum = 2
1680 12:16:13.987253 11, 0x0, sum = 3
1681 12:16:13.987742 12, 0x0, sum = 4
1682 12:16:13.990203 best_step = 10
1683 12:16:13.990687
1684 12:16:13.991028 ==
1685 12:16:13.994304 Dram Type= 6, Freq= 0, CH_1, rank 0
1686 12:16:13.997214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1687 12:16:13.997891 ==
1688 12:16:14.000458 RX Vref Scan: 1
1689 12:16:14.000909
1690 12:16:14.001242 Set Vref Range= 32 -> 127
1691 12:16:14.001552
1692 12:16:14.003563 RX Vref 32 -> 127, step: 1
1693 12:16:14.003983
1694 12:16:14.006848 RX Delay -95 -> 252, step: 8
1695 12:16:14.007264
1696 12:16:14.010268 Set Vref, RX VrefLevel [Byte0]: 32
1697 12:16:14.013525 [Byte1]: 32
1698 12:16:14.014036
1699 12:16:14.017900 Set Vref, RX VrefLevel [Byte0]: 33
1700 12:16:14.019918 [Byte1]: 33
1701 12:16:14.024183
1702 12:16:14.024598 Set Vref, RX VrefLevel [Byte0]: 34
1703 12:16:14.027414 [Byte1]: 34
1704 12:16:14.031430
1705 12:16:14.031876 Set Vref, RX VrefLevel [Byte0]: 35
1706 12:16:14.034768 [Byte1]: 35
1707 12:16:14.039329
1708 12:16:14.039880 Set Vref, RX VrefLevel [Byte0]: 36
1709 12:16:14.042292 [Byte1]: 36
1710 12:16:14.047045
1711 12:16:14.047492 Set Vref, RX VrefLevel [Byte0]: 37
1712 12:16:14.050227 [Byte1]: 37
1713 12:16:14.054268
1714 12:16:14.054688 Set Vref, RX VrefLevel [Byte0]: 38
1715 12:16:14.057848 [Byte1]: 38
1716 12:16:14.062029
1717 12:16:14.062546 Set Vref, RX VrefLevel [Byte0]: 39
1718 12:16:14.065297 [Byte1]: 39
1719 12:16:14.069913
1720 12:16:14.070327 Set Vref, RX VrefLevel [Byte0]: 40
1721 12:16:14.073177 [Byte1]: 40
1722 12:16:14.077238
1723 12:16:14.077833 Set Vref, RX VrefLevel [Byte0]: 41
1724 12:16:14.080490 [Byte1]: 41
1725 12:16:14.084861
1726 12:16:14.085278 Set Vref, RX VrefLevel [Byte0]: 42
1727 12:16:14.088255 [Byte1]: 42
1728 12:16:14.093241
1729 12:16:14.093962 Set Vref, RX VrefLevel [Byte0]: 43
1730 12:16:14.095560 [Byte1]: 43
1731 12:16:14.100361
1732 12:16:14.100886 Set Vref, RX VrefLevel [Byte0]: 44
1733 12:16:14.103316 [Byte1]: 44
1734 12:16:14.107557
1735 12:16:14.108057 Set Vref, RX VrefLevel [Byte0]: 45
1736 12:16:14.110903 [Byte1]: 45
1737 12:16:14.114941
1738 12:16:14.115539 Set Vref, RX VrefLevel [Byte0]: 46
1739 12:16:14.118391 [Byte1]: 46
1740 12:16:14.122995
1741 12:16:14.123475 Set Vref, RX VrefLevel [Byte0]: 47
1742 12:16:14.125952 [Byte1]: 47
1743 12:16:14.130611
1744 12:16:14.131218 Set Vref, RX VrefLevel [Byte0]: 48
1745 12:16:14.133355 [Byte1]: 48
1746 12:16:14.137834
1747 12:16:14.138248 Set Vref, RX VrefLevel [Byte0]: 49
1748 12:16:14.141261 [Byte1]: 49
1749 12:16:14.145561
1750 12:16:14.146081 Set Vref, RX VrefLevel [Byte0]: 50
1751 12:16:14.148961 [Byte1]: 50
1752 12:16:14.153526
1753 12:16:14.153943 Set Vref, RX VrefLevel [Byte0]: 51
1754 12:16:14.156792 [Byte1]: 51
1755 12:16:14.160753
1756 12:16:14.161171 Set Vref, RX VrefLevel [Byte0]: 52
1757 12:16:14.164041 [Byte1]: 52
1758 12:16:14.168766
1759 12:16:14.169285 Set Vref, RX VrefLevel [Byte0]: 53
1760 12:16:14.171891 [Byte1]: 53
1761 12:16:14.175923
1762 12:16:14.176338 Set Vref, RX VrefLevel [Byte0]: 54
1763 12:16:14.179494 [Byte1]: 54
1764 12:16:14.183639
1765 12:16:14.184157 Set Vref, RX VrefLevel [Byte0]: 55
1766 12:16:14.186758 [Byte1]: 55
1767 12:16:14.191197
1768 12:16:14.191771 Set Vref, RX VrefLevel [Byte0]: 56
1769 12:16:14.196363 [Byte1]: 56
1770 12:16:14.198953
1771 12:16:14.199396 Set Vref, RX VrefLevel [Byte0]: 57
1772 12:16:14.202912 [Byte1]: 57
1773 12:16:14.206702
1774 12:16:14.207120 Set Vref, RX VrefLevel [Byte0]: 58
1775 12:16:14.212867 [Byte1]: 58
1776 12:16:14.213286
1777 12:16:14.216088 Set Vref, RX VrefLevel [Byte0]: 59
1778 12:16:14.219216 [Byte1]: 59
1779 12:16:14.219659
1780 12:16:14.222762 Set Vref, RX VrefLevel [Byte0]: 60
1781 12:16:14.226399 [Byte1]: 60
1782 12:16:14.226865
1783 12:16:14.229593 Set Vref, RX VrefLevel [Byte0]: 61
1784 12:16:14.232688 [Byte1]: 61
1785 12:16:14.236544
1786 12:16:14.236965 Set Vref, RX VrefLevel [Byte0]: 62
1787 12:16:14.239950 [Byte1]: 62
1788 12:16:14.244361
1789 12:16:14.244800 Set Vref, RX VrefLevel [Byte0]: 63
1790 12:16:14.248087 [Byte1]: 63
1791 12:16:14.252274
1792 12:16:14.252693 Set Vref, RX VrefLevel [Byte0]: 64
1793 12:16:14.255146 [Byte1]: 64
1794 12:16:14.259599
1795 12:16:14.260117 Set Vref, RX VrefLevel [Byte0]: 65
1796 12:16:14.263411 [Byte1]: 65
1797 12:16:14.267233
1798 12:16:14.267840 Set Vref, RX VrefLevel [Byte0]: 66
1799 12:16:14.270164 [Byte1]: 66
1800 12:16:14.275543
1801 12:16:14.276130 Set Vref, RX VrefLevel [Byte0]: 67
1802 12:16:14.278048 [Byte1]: 67
1803 12:16:14.282707
1804 12:16:14.283226 Set Vref, RX VrefLevel [Byte0]: 68
1805 12:16:14.286242 [Byte1]: 68
1806 12:16:14.289718
1807 12:16:14.290134 Set Vref, RX VrefLevel [Byte0]: 69
1808 12:16:14.293086 [Byte1]: 69
1809 12:16:14.297908
1810 12:16:14.298418 Set Vref, RX VrefLevel [Byte0]: 70
1811 12:16:14.300737 [Byte1]: 70
1812 12:16:14.306467
1813 12:16:14.306974 Set Vref, RX VrefLevel [Byte0]: 71
1814 12:16:14.308368 [Byte1]: 71
1815 12:16:14.312935
1816 12:16:14.313441 Set Vref, RX VrefLevel [Byte0]: 72
1817 12:16:14.315806 [Byte1]: 72
1818 12:16:14.320252
1819 12:16:14.320762 Set Vref, RX VrefLevel [Byte0]: 73
1820 12:16:14.323508 [Byte1]: 73
1821 12:16:14.327908
1822 12:16:14.328346 Set Vref, RX VrefLevel [Byte0]: 74
1823 12:16:14.330953 [Byte1]: 74
1824 12:16:14.335954
1825 12:16:14.336470 Final RX Vref Byte 0 = 58 to rank0
1826 12:16:14.338702 Final RX Vref Byte 1 = 53 to rank0
1827 12:16:14.342181 Final RX Vref Byte 0 = 58 to rank1
1828 12:16:14.345813 Final RX Vref Byte 1 = 53 to rank1==
1829 12:16:14.348782 Dram Type= 6, Freq= 0, CH_1, rank 0
1830 12:16:14.356050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1831 12:16:14.356474 ==
1832 12:16:14.356808 DQS Delay:
1833 12:16:14.357115 DQS0 = 0, DQS1 = 0
1834 12:16:14.358990 DQM Delay:
1835 12:16:14.359451 DQM0 = 86, DQM1 = 80
1836 12:16:14.362513 DQ Delay:
1837 12:16:14.365771 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1838 12:16:14.368804 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =80
1839 12:16:14.372421 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =76
1840 12:16:14.375432 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1841 12:16:14.375943
1842 12:16:14.376276
1843 12:16:14.382592 [DQSOSCAuto] RK0, (LSB)MR18= 0x162a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
1844 12:16:14.385434 CH1 RK0: MR19=606, MR18=162A
1845 12:16:14.391670 CH1_RK0: MR19=0x606, MR18=0x162A, DQSOSC=399, MR23=63, INC=92, DEC=61
1846 12:16:14.392214
1847 12:16:14.395012 ----->DramcWriteLeveling(PI) begin...
1848 12:16:14.395593 ==
1849 12:16:14.398221 Dram Type= 6, Freq= 0, CH_1, rank 1
1850 12:16:14.401901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1851 12:16:14.402316 ==
1852 12:16:14.404927 Write leveling (Byte 0): 27 => 27
1853 12:16:14.408515 Write leveling (Byte 1): 28 => 28
1854 12:16:14.411536 DramcWriteLeveling(PI) end<-----
1855 12:16:14.411950
1856 12:16:14.412280 ==
1857 12:16:14.415014 Dram Type= 6, Freq= 0, CH_1, rank 1
1858 12:16:14.418373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1859 12:16:14.418787 ==
1860 12:16:14.421935 [Gating] SW mode calibration
1861 12:16:14.428585 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1862 12:16:14.436198 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1863 12:16:14.438523 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1864 12:16:14.444819 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1865 12:16:14.448170 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1866 12:16:14.451841 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 12:16:14.458148 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 12:16:14.460913 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 12:16:14.464822 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 12:16:14.471044 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 12:16:14.474633 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 12:16:14.477894 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 12:16:14.480824 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 12:16:14.487831 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 12:16:14.490805 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 12:16:14.494001 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 12:16:14.500848 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 12:16:14.504498 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1879 12:16:14.507373 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1880 12:16:14.513851 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1881 12:16:14.517118 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 12:16:14.520932 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 12:16:14.527287 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 12:16:14.530659 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 12:16:14.534022 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 12:16:14.541062 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 12:16:14.544317 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1888 12:16:14.547685 0 9 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1889 12:16:14.554056 0 9 8 | B1->B0 | 2b2b 3434 | 0 1 | (1 1) (1 1)
1890 12:16:14.557640 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 12:16:14.560714 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 12:16:14.567397 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 12:16:14.570216 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 12:16:14.573852 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 12:16:14.580760 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 12:16:14.584087 0 10 4 | B1->B0 | 3434 2e2e | 0 0 | (0 1) (1 1)
1897 12:16:14.587183 0 10 8 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
1898 12:16:14.593745 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 12:16:14.596997 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 12:16:14.600008 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 12:16:14.606969 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 12:16:14.610099 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 12:16:14.613459 0 11 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1904 12:16:14.620576 0 11 4 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
1905 12:16:14.623304 0 11 8 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
1906 12:16:14.626850 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 12:16:14.633595 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 12:16:14.636713 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 12:16:14.639803 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 12:16:14.643218 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 12:16:14.650110 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1912 12:16:14.653838 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1913 12:16:14.657205 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 12:16:14.663771 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 12:16:14.666717 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 12:16:14.670174 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 12:16:14.676946 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 12:16:14.680145 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 12:16:14.683527 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 12:16:14.690331 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 12:16:14.693359 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 12:16:14.696317 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 12:16:14.703159 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 12:16:14.706446 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 12:16:14.709965 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 12:16:14.716186 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 12:16:14.720666 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1928 12:16:14.723610 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1929 12:16:14.730471 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 12:16:14.730979 Total UI for P1: 0, mck2ui 16
1931 12:16:14.736820 best dqsien dly found for B0: ( 0, 14, 2)
1932 12:16:14.737365 Total UI for P1: 0, mck2ui 16
1933 12:16:14.743040 best dqsien dly found for B1: ( 0, 14, 6)
1934 12:16:14.746558 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1935 12:16:14.749915 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1936 12:16:14.750549
1937 12:16:14.753193 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1938 12:16:14.756865 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1939 12:16:14.760961 [Gating] SW calibration Done
1940 12:16:14.761534 ==
1941 12:16:14.763318 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 12:16:14.767233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 12:16:14.767868 ==
1944 12:16:14.769821 RX Vref Scan: 0
1945 12:16:14.770283
1946 12:16:14.770653 RX Vref 0 -> 0, step: 1
1947 12:16:14.771001
1948 12:16:14.773297 RX Delay -130 -> 252, step: 16
1949 12:16:14.776804 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1950 12:16:14.783067 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1951 12:16:14.786462 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1952 12:16:14.789932 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1953 12:16:14.793854 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1954 12:16:14.796095 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1955 12:16:14.803444 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1956 12:16:14.806643 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1957 12:16:14.809510 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1958 12:16:14.812951 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1959 12:16:14.815951 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1960 12:16:14.822765 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1961 12:16:14.826364 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1962 12:16:14.829316 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1963 12:16:14.832943 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1964 12:16:14.839740 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1965 12:16:14.840272 ==
1966 12:16:14.843461 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 12:16:14.845851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 12:16:14.846319 ==
1969 12:16:14.846690 DQS Delay:
1970 12:16:14.849328 DQS0 = 0, DQS1 = 0
1971 12:16:14.849747 DQM Delay:
1972 12:16:14.852728 DQM0 = 82, DQM1 = 79
1973 12:16:14.853150 DQ Delay:
1974 12:16:14.855742 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1975 12:16:14.859335 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =85
1976 12:16:14.863179 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1977 12:16:14.866030 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1978 12:16:14.866573
1979 12:16:14.866920
1980 12:16:14.867236 ==
1981 12:16:14.869638 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 12:16:14.872719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 12:16:14.873143 ==
1984 12:16:14.873559
1985 12:16:14.873885
1986 12:16:14.875898 TX Vref Scan disable
1987 12:16:14.879190 == TX Byte 0 ==
1988 12:16:14.882720 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1989 12:16:14.886531 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1990 12:16:14.889016 == TX Byte 1 ==
1991 12:16:14.892447 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1992 12:16:14.895923 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1993 12:16:14.896483 ==
1994 12:16:14.899334 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 12:16:14.906064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 12:16:14.906601 ==
1997 12:16:14.916970 TX Vref=22, minBit 1, minWin=27, winSum=449
1998 12:16:14.920647 TX Vref=24, minBit 1, minWin=27, winSum=451
1999 12:16:14.923764 TX Vref=26, minBit 0, minWin=28, winSum=454
2000 12:16:14.927412 TX Vref=28, minBit 5, minWin=27, winSum=453
2001 12:16:14.930906 TX Vref=30, minBit 5, minWin=27, winSum=454
2002 12:16:14.937032 TX Vref=32, minBit 5, minWin=27, winSum=455
2003 12:16:14.940028 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 26
2004 12:16:14.940464
2005 12:16:14.943672 Final TX Range 1 Vref 26
2006 12:16:14.944094
2007 12:16:14.944430 ==
2008 12:16:14.946718 Dram Type= 6, Freq= 0, CH_1, rank 1
2009 12:16:14.950394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2010 12:16:14.953331 ==
2011 12:16:14.953567
2012 12:16:14.953748
2013 12:16:14.953914 TX Vref Scan disable
2014 12:16:14.956895 == TX Byte 0 ==
2015 12:16:14.960052 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2016 12:16:14.966682 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2017 12:16:14.966866 == TX Byte 1 ==
2018 12:16:14.969915 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2019 12:16:14.977259 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2020 12:16:14.977417
2021 12:16:14.977519 [DATLAT]
2022 12:16:14.977594 Freq=800, CH1 RK1
2023 12:16:14.977667
2024 12:16:14.979779 DATLAT Default: 0xa
2025 12:16:14.979883 0, 0xFFFF, sum = 0
2026 12:16:14.983541 1, 0xFFFF, sum = 0
2027 12:16:14.983714 2, 0xFFFF, sum = 0
2028 12:16:14.987018 3, 0xFFFF, sum = 0
2029 12:16:14.990222 4, 0xFFFF, sum = 0
2030 12:16:14.990385 5, 0xFFFF, sum = 0
2031 12:16:14.993793 6, 0xFFFF, sum = 0
2032 12:16:14.994241 7, 0xFFFF, sum = 0
2033 12:16:14.997032 8, 0xFFFF, sum = 0
2034 12:16:14.997479 9, 0x0, sum = 1
2035 12:16:14.997829 10, 0x0, sum = 2
2036 12:16:15.000684 11, 0x0, sum = 3
2037 12:16:15.001203 12, 0x0, sum = 4
2038 12:16:15.003952 best_step = 10
2039 12:16:15.004371
2040 12:16:15.004700 ==
2041 12:16:15.007064 Dram Type= 6, Freq= 0, CH_1, rank 1
2042 12:16:15.010767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2043 12:16:15.011288 ==
2044 12:16:15.013695 RX Vref Scan: 0
2045 12:16:15.014210
2046 12:16:15.014548 RX Vref 0 -> 0, step: 1
2047 12:16:15.016626
2048 12:16:15.017096 RX Delay -95 -> 252, step: 8
2049 12:16:15.023904 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2050 12:16:15.027408 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2051 12:16:15.030362 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2052 12:16:15.033984 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2053 12:16:15.037087 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2054 12:16:15.044270 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2055 12:16:15.047404 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2056 12:16:15.050502 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2057 12:16:15.054110 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2058 12:16:15.057072 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2059 12:16:15.063976 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2060 12:16:15.066852 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2061 12:16:15.070575 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2062 12:16:15.073868 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2063 12:16:15.080212 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2064 12:16:15.083525 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2065 12:16:15.084057 ==
2066 12:16:15.086986 Dram Type= 6, Freq= 0, CH_1, rank 1
2067 12:16:15.090471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2068 12:16:15.091001 ==
2069 12:16:15.091457 DQS Delay:
2070 12:16:15.093768 DQS0 = 0, DQS1 = 0
2071 12:16:15.094187 DQM Delay:
2072 12:16:15.096654 DQM0 = 86, DQM1 = 81
2073 12:16:15.097080 DQ Delay:
2074 12:16:15.100250 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2075 12:16:15.103574 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2076 12:16:15.106801 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =76
2077 12:16:15.110373 DQ12 =88, DQ13 =92, DQ14 =88, DQ15 =88
2078 12:16:15.110915
2079 12:16:15.111255
2080 12:16:15.120102 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c37, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2081 12:16:15.120619 CH1 RK1: MR19=606, MR18=1C37
2082 12:16:15.127196 CH1_RK1: MR19=0x606, MR18=0x1C37, DQSOSC=395, MR23=63, INC=94, DEC=63
2083 12:16:15.130411 [RxdqsGatingPostProcess] freq 800
2084 12:16:15.136801 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2085 12:16:15.141132 Pre-setting of DQS Precalculation
2086 12:16:15.143413 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2087 12:16:15.150357 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2088 12:16:15.159753 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2089 12:16:15.160209
2090 12:16:15.160562
2091 12:16:15.163182 [Calibration Summary] 1600 Mbps
2092 12:16:15.163647 CH 0, Rank 0
2093 12:16:15.166555 SW Impedance : PASS
2094 12:16:15.166987 DUTY Scan : NO K
2095 12:16:15.170304 ZQ Calibration : PASS
2096 12:16:15.170726 Jitter Meter : NO K
2097 12:16:15.172881 CBT Training : PASS
2098 12:16:15.176431 Write leveling : PASS
2099 12:16:15.176848 RX DQS gating : PASS
2100 12:16:15.179535 RX DQ/DQS(RDDQC) : PASS
2101 12:16:15.182938 TX DQ/DQS : PASS
2102 12:16:15.183502 RX DATLAT : PASS
2103 12:16:15.186407 RX DQ/DQS(Engine): PASS
2104 12:16:15.189777 TX OE : NO K
2105 12:16:15.190196 All Pass.
2106 12:16:15.190547
2107 12:16:15.190859 CH 0, Rank 1
2108 12:16:15.192811 SW Impedance : PASS
2109 12:16:15.195988 DUTY Scan : NO K
2110 12:16:15.196409 ZQ Calibration : PASS
2111 12:16:15.199297 Jitter Meter : NO K
2112 12:16:15.202858 CBT Training : PASS
2113 12:16:15.203278 Write leveling : PASS
2114 12:16:15.206304 RX DQS gating : PASS
2115 12:16:15.209644 RX DQ/DQS(RDDQC) : PASS
2116 12:16:15.210172 TX DQ/DQS : PASS
2117 12:16:15.212793 RX DATLAT : PASS
2118 12:16:15.216049 RX DQ/DQS(Engine): PASS
2119 12:16:15.216473 TX OE : NO K
2120 12:16:15.216815 All Pass.
2121 12:16:15.219714
2122 12:16:15.220137 CH 1, Rank 0
2123 12:16:15.223080 SW Impedance : PASS
2124 12:16:15.223663 DUTY Scan : NO K
2125 12:16:15.225899 ZQ Calibration : PASS
2126 12:16:15.226511 Jitter Meter : NO K
2127 12:16:15.229817 CBT Training : PASS
2128 12:16:15.233080 Write leveling : PASS
2129 12:16:15.233653 RX DQS gating : PASS
2130 12:16:15.236059 RX DQ/DQS(RDDQC) : PASS
2131 12:16:15.239256 TX DQ/DQS : PASS
2132 12:16:15.239724 RX DATLAT : PASS
2133 12:16:15.242637 RX DQ/DQS(Engine): PASS
2134 12:16:15.246652 TX OE : NO K
2135 12:16:15.247077 All Pass.
2136 12:16:15.247460
2137 12:16:15.247781 CH 1, Rank 1
2138 12:16:15.249265 SW Impedance : PASS
2139 12:16:15.252530 DUTY Scan : NO K
2140 12:16:15.252951 ZQ Calibration : PASS
2141 12:16:15.255609 Jitter Meter : NO K
2142 12:16:15.258890 CBT Training : PASS
2143 12:16:15.259311 Write leveling : PASS
2144 12:16:15.262652 RX DQS gating : PASS
2145 12:16:15.266133 RX DQ/DQS(RDDQC) : PASS
2146 12:16:15.266702 TX DQ/DQS : PASS
2147 12:16:15.269186 RX DATLAT : PASS
2148 12:16:15.272481 RX DQ/DQS(Engine): PASS
2149 12:16:15.272909 TX OE : NO K
2150 12:16:15.273249 All Pass.
2151 12:16:15.275546
2152 12:16:15.275963 DramC Write-DBI off
2153 12:16:15.279055 PER_BANK_REFRESH: Hybrid Mode
2154 12:16:15.279631 TX_TRACKING: ON
2155 12:16:15.282576 [GetDramInforAfterCalByMRR] Vendor 6.
2156 12:16:15.286264 [GetDramInforAfterCalByMRR] Revision 606.
2157 12:16:15.293533 [GetDramInforAfterCalByMRR] Revision 2 0.
2158 12:16:15.294067 MR0 0x3b3b
2159 12:16:15.294408 MR8 0x5151
2160 12:16:15.295326 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2161 12:16:15.295782
2162 12:16:15.298961 MR0 0x3b3b
2163 12:16:15.299563 MR8 0x5151
2164 12:16:15.302393 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2165 12:16:15.302816
2166 12:16:15.312589 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2167 12:16:15.316019 [FAST_K] Save calibration result to emmc
2168 12:16:15.318652 [FAST_K] Save calibration result to emmc
2169 12:16:15.322373 dram_init: config_dvfs: 1
2170 12:16:15.325376 dramc_set_vcore_voltage set vcore to 662500
2171 12:16:15.328738 Read voltage for 1200, 2
2172 12:16:15.329195 Vio18 = 0
2173 12:16:15.329544 Vcore = 662500
2174 12:16:15.331925 Vdram = 0
2175 12:16:15.332347 Vddq = 0
2176 12:16:15.332680 Vmddr = 0
2177 12:16:15.338635 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2178 12:16:15.342187 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2179 12:16:15.346286 MEM_TYPE=3, freq_sel=15
2180 12:16:15.349144 sv_algorithm_assistance_LP4_1600
2181 12:16:15.352307 ============ PULL DRAM RESETB DOWN ============
2182 12:16:15.355481 ========== PULL DRAM RESETB DOWN end =========
2183 12:16:15.362166 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2184 12:16:15.365661 ===================================
2185 12:16:15.366178 LPDDR4 DRAM CONFIGURATION
2186 12:16:15.369164 ===================================
2187 12:16:15.371804 EX_ROW_EN[0] = 0x0
2188 12:16:15.375176 EX_ROW_EN[1] = 0x0
2189 12:16:15.375745 LP4Y_EN = 0x0
2190 12:16:15.378286 WORK_FSP = 0x0
2191 12:16:15.378727 WL = 0x4
2192 12:16:15.382329 RL = 0x4
2193 12:16:15.382752 BL = 0x2
2194 12:16:15.385491 RPST = 0x0
2195 12:16:15.386022 RD_PRE = 0x0
2196 12:16:15.388204 WR_PRE = 0x1
2197 12:16:15.388628 WR_PST = 0x0
2198 12:16:15.392083 DBI_WR = 0x0
2199 12:16:15.392615 DBI_RD = 0x0
2200 12:16:15.395157 OTF = 0x1
2201 12:16:15.398787 ===================================
2202 12:16:15.401785 ===================================
2203 12:16:15.402210 ANA top config
2204 12:16:15.405359 ===================================
2205 12:16:15.408772 DLL_ASYNC_EN = 0
2206 12:16:15.412063 ALL_SLAVE_EN = 0
2207 12:16:15.415239 NEW_RANK_MODE = 1
2208 12:16:15.415844 DLL_IDLE_MODE = 1
2209 12:16:15.418124 LP45_APHY_COMB_EN = 1
2210 12:16:15.421737 TX_ODT_DIS = 1
2211 12:16:15.424833 NEW_8X_MODE = 1
2212 12:16:15.428417 ===================================
2213 12:16:15.431650 ===================================
2214 12:16:15.435527 data_rate = 2400
2215 12:16:15.436048 CKR = 1
2216 12:16:15.437881 DQ_P2S_RATIO = 8
2217 12:16:15.441264 ===================================
2218 12:16:15.444387 CA_P2S_RATIO = 8
2219 12:16:15.448038 DQ_CA_OPEN = 0
2220 12:16:15.451449 DQ_SEMI_OPEN = 0
2221 12:16:15.455305 CA_SEMI_OPEN = 0
2222 12:16:15.455873 CA_FULL_RATE = 0
2223 12:16:15.457691 DQ_CKDIV4_EN = 0
2224 12:16:15.461352 CA_CKDIV4_EN = 0
2225 12:16:15.464871 CA_PREDIV_EN = 0
2226 12:16:15.468062 PH8_DLY = 17
2227 12:16:15.471223 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2228 12:16:15.471831 DQ_AAMCK_DIV = 4
2229 12:16:15.475027 CA_AAMCK_DIV = 4
2230 12:16:15.478509 CA_ADMCK_DIV = 4
2231 12:16:15.481701 DQ_TRACK_CA_EN = 0
2232 12:16:15.485310 CA_PICK = 1200
2233 12:16:15.488426 CA_MCKIO = 1200
2234 12:16:15.491240 MCKIO_SEMI = 0
2235 12:16:15.491856 PLL_FREQ = 2366
2236 12:16:15.494247 DQ_UI_PI_RATIO = 32
2237 12:16:15.497889 CA_UI_PI_RATIO = 0
2238 12:16:15.501260 ===================================
2239 12:16:15.504755 ===================================
2240 12:16:15.507566 memory_type:LPDDR4
2241 12:16:15.510535 GP_NUM : 10
2242 12:16:15.510952 SRAM_EN : 1
2243 12:16:15.514314 MD32_EN : 0
2244 12:16:15.518076 ===================================
2245 12:16:15.518601 [ANA_INIT] >>>>>>>>>>>>>>
2246 12:16:15.521108 <<<<<< [CONFIGURE PHASE]: ANA_TX
2247 12:16:15.524067 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2248 12:16:15.527611 ===================================
2249 12:16:15.530934 data_rate = 2400,PCW = 0X5b00
2250 12:16:15.534636 ===================================
2251 12:16:15.537648 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2252 12:16:15.544250 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2253 12:16:15.550942 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2254 12:16:15.554907 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2255 12:16:15.557016 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2256 12:16:15.561092 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2257 12:16:15.564221 [ANA_INIT] flow start
2258 12:16:15.564684 [ANA_INIT] PLL >>>>>>>>
2259 12:16:15.568083 [ANA_INIT] PLL <<<<<<<<
2260 12:16:15.570851 [ANA_INIT] MIDPI >>>>>>>>
2261 12:16:15.571356 [ANA_INIT] MIDPI <<<<<<<<
2262 12:16:15.574231 [ANA_INIT] DLL >>>>>>>>
2263 12:16:15.577614 [ANA_INIT] DLL <<<<<<<<
2264 12:16:15.578172 [ANA_INIT] flow end
2265 12:16:15.584452 ============ LP4 DIFF to SE enter ============
2266 12:16:15.587491 ============ LP4 DIFF to SE exit ============
2267 12:16:15.590672 [ANA_INIT] <<<<<<<<<<<<<
2268 12:16:15.594505 [Flow] Enable top DCM control >>>>>
2269 12:16:15.596937 [Flow] Enable top DCM control <<<<<
2270 12:16:15.597401 Enable DLL master slave shuffle
2271 12:16:15.603638 ==============================================================
2272 12:16:15.607294 Gating Mode config
2273 12:16:15.610428 ==============================================================
2274 12:16:15.613484 Config description:
2275 12:16:15.624347 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2276 12:16:15.630383 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2277 12:16:15.633900 SELPH_MODE 0: By rank 1: By Phase
2278 12:16:15.640357 ==============================================================
2279 12:16:15.643839 GAT_TRACK_EN = 1
2280 12:16:15.646934 RX_GATING_MODE = 2
2281 12:16:15.650590 RX_GATING_TRACK_MODE = 2
2282 12:16:15.653717 SELPH_MODE = 1
2283 12:16:15.654335 PICG_EARLY_EN = 1
2284 12:16:15.656531 VALID_LAT_VALUE = 1
2285 12:16:15.663982 ==============================================================
2286 12:16:15.667038 Enter into Gating configuration >>>>
2287 12:16:15.670222 Exit from Gating configuration <<<<
2288 12:16:15.673131 Enter into DVFS_PRE_config >>>>>
2289 12:16:15.684037 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2290 12:16:15.686359 Exit from DVFS_PRE_config <<<<<
2291 12:16:15.690242 Enter into PICG configuration >>>>
2292 12:16:15.692936 Exit from PICG configuration <<<<
2293 12:16:15.696629 [RX_INPUT] configuration >>>>>
2294 12:16:15.700215 [RX_INPUT] configuration <<<<<
2295 12:16:15.703261 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2296 12:16:15.709689 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2297 12:16:15.717342 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2298 12:16:15.722983 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2299 12:16:15.730359 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2300 12:16:15.735953 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2301 12:16:15.739462 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2302 12:16:15.742872 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2303 12:16:15.746023 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2304 12:16:15.749912 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2305 12:16:15.756370 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2306 12:16:15.759208 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2307 12:16:15.762744 ===================================
2308 12:16:15.766057 LPDDR4 DRAM CONFIGURATION
2309 12:16:15.769303 ===================================
2310 12:16:15.769871 EX_ROW_EN[0] = 0x0
2311 12:16:15.772335 EX_ROW_EN[1] = 0x0
2312 12:16:15.772820 LP4Y_EN = 0x0
2313 12:16:15.775842 WORK_FSP = 0x0
2314 12:16:15.779480 WL = 0x4
2315 12:16:15.780034 RL = 0x4
2316 12:16:15.783281 BL = 0x2
2317 12:16:15.783903 RPST = 0x0
2318 12:16:15.785834 RD_PRE = 0x0
2319 12:16:15.786397 WR_PRE = 0x1
2320 12:16:15.788932 WR_PST = 0x0
2321 12:16:15.789390 DBI_WR = 0x0
2322 12:16:15.792212 DBI_RD = 0x0
2323 12:16:15.792671 OTF = 0x1
2324 12:16:15.795531 ===================================
2325 12:16:15.799279 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2326 12:16:15.806275 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2327 12:16:15.809463 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2328 12:16:15.812294 ===================================
2329 12:16:15.816353 LPDDR4 DRAM CONFIGURATION
2330 12:16:15.818738 ===================================
2331 12:16:15.819521 EX_ROW_EN[0] = 0x10
2332 12:16:15.821893 EX_ROW_EN[1] = 0x0
2333 12:16:15.822386 LP4Y_EN = 0x0
2334 12:16:15.825456 WORK_FSP = 0x0
2335 12:16:15.825875 WL = 0x4
2336 12:16:15.829466 RL = 0x4
2337 12:16:15.832067 BL = 0x2
2338 12:16:15.832487 RPST = 0x0
2339 12:16:15.835544 RD_PRE = 0x0
2340 12:16:15.836062 WR_PRE = 0x1
2341 12:16:15.838949 WR_PST = 0x0
2342 12:16:15.839533 DBI_WR = 0x0
2343 12:16:15.841908 DBI_RD = 0x0
2344 12:16:15.842327 OTF = 0x1
2345 12:16:15.845139 ===================================
2346 12:16:15.851858 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2347 12:16:15.852278 ==
2348 12:16:15.855214 Dram Type= 6, Freq= 0, CH_0, rank 0
2349 12:16:15.858507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2350 12:16:15.858946 ==
2351 12:16:15.861819 [Duty_Offset_Calibration]
2352 12:16:15.865339 B0:2 B1:0 CA:4
2353 12:16:15.865853
2354 12:16:15.868248 [DutyScan_Calibration_Flow] k_type=0
2355 12:16:15.875756
2356 12:16:15.876315 ==CLK 0==
2357 12:16:15.879401 Final CLK duty delay cell = -4
2358 12:16:15.882387 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2359 12:16:15.885641 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2360 12:16:15.888620 [-4] AVG Duty = 4937%(X100)
2361 12:16:15.889033
2362 12:16:15.891924 CH0 CLK Duty spec in!! Max-Min= 187%
2363 12:16:15.895643 [DutyScan_Calibration_Flow] ====Done====
2364 12:16:15.896057
2365 12:16:15.898893 [DutyScan_Calibration_Flow] k_type=1
2366 12:16:15.916039
2367 12:16:15.916547 ==DQS 0 ==
2368 12:16:15.918733 Final DQS duty delay cell = 0
2369 12:16:15.922227 [0] MAX Duty = 5156%(X100), DQS PI = 18
2370 12:16:15.925104 [0] MIN Duty = 5093%(X100), DQS PI = 2
2371 12:16:15.925520 [0] AVG Duty = 5124%(X100)
2372 12:16:15.928315
2373 12:16:15.928722 ==DQS 1 ==
2374 12:16:15.932096 Final DQS duty delay cell = 0
2375 12:16:15.935546 [0] MAX Duty = 5125%(X100), DQS PI = 50
2376 12:16:15.938908 [0] MIN Duty = 5000%(X100), DQS PI = 0
2377 12:16:15.939512 [0] AVG Duty = 5062%(X100)
2378 12:16:15.942041
2379 12:16:15.945572 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2380 12:16:15.945990
2381 12:16:15.949106 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2382 12:16:15.952044 [DutyScan_Calibration_Flow] ====Done====
2383 12:16:15.952632
2384 12:16:15.955005 [DutyScan_Calibration_Flow] k_type=3
2385 12:16:15.971475
2386 12:16:15.971979 ==DQM 0 ==
2387 12:16:15.974969 Final DQM duty delay cell = 0
2388 12:16:15.978279 [0] MAX Duty = 5125%(X100), DQS PI = 20
2389 12:16:15.981374 [0] MIN Duty = 4844%(X100), DQS PI = 54
2390 12:16:15.984621 [0] AVG Duty = 4984%(X100)
2391 12:16:15.985034
2392 12:16:15.985362 ==DQM 1 ==
2393 12:16:15.988126 Final DQM duty delay cell = 0
2394 12:16:15.991473 [0] MAX Duty = 5000%(X100), DQS PI = 6
2395 12:16:15.994648 [0] MIN Duty = 4875%(X100), DQS PI = 18
2396 12:16:15.998729 [0] AVG Duty = 4937%(X100)
2397 12:16:15.999254
2398 12:16:16.001124 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2399 12:16:16.001566
2400 12:16:16.005063 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2401 12:16:16.008494 [DutyScan_Calibration_Flow] ====Done====
2402 12:16:16.009029
2403 12:16:16.011862 [DutyScan_Calibration_Flow] k_type=2
2404 12:16:16.028423
2405 12:16:16.028939 ==DQ 0 ==
2406 12:16:16.031521 Final DQ duty delay cell = 0
2407 12:16:16.034964 [0] MAX Duty = 5125%(X100), DQS PI = 18
2408 12:16:16.038293 [0] MIN Duty = 4969%(X100), DQS PI = 56
2409 12:16:16.038954 [0] AVG Duty = 5047%(X100)
2410 12:16:16.041468
2411 12:16:16.041878 ==DQ 1 ==
2412 12:16:16.044527 Final DQ duty delay cell = 0
2413 12:16:16.047842 [0] MAX Duty = 5156%(X100), DQS PI = 4
2414 12:16:16.052072 [0] MIN Duty = 4907%(X100), DQS PI = 18
2415 12:16:16.052589 [0] AVG Duty = 5031%(X100)
2416 12:16:16.052921
2417 12:16:16.054805 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2418 12:16:16.058151
2419 12:16:16.061141 CH0 DQ 1 Duty spec in!! Max-Min= 249%
2420 12:16:16.064851 [DutyScan_Calibration_Flow] ====Done====
2421 12:16:16.065427 ==
2422 12:16:16.068098 Dram Type= 6, Freq= 0, CH_1, rank 0
2423 12:16:16.071323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2424 12:16:16.071886 ==
2425 12:16:16.074293 [Duty_Offset_Calibration]
2426 12:16:16.074707 B0:0 B1:-1 CA:3
2427 12:16:16.075036
2428 12:16:16.077839 [DutyScan_Calibration_Flow] k_type=0
2429 12:16:16.087644
2430 12:16:16.088156 ==CLK 0==
2431 12:16:16.090861 Final CLK duty delay cell = -4
2432 12:16:16.093866 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2433 12:16:16.097058 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2434 12:16:16.100229 [-4] AVG Duty = 4953%(X100)
2435 12:16:16.100659
2436 12:16:16.103568 CH1 CLK Duty spec in!! Max-Min= 93%
2437 12:16:16.106854 [DutyScan_Calibration_Flow] ====Done====
2438 12:16:16.107513
2439 12:16:16.111052 [DutyScan_Calibration_Flow] k_type=1
2440 12:16:16.126653
2441 12:16:16.127160 ==DQS 0 ==
2442 12:16:16.131012 Final DQS duty delay cell = 0
2443 12:16:16.133590 [0] MAX Duty = 5187%(X100), DQS PI = 18
2444 12:16:16.136953 [0] MIN Duty = 4907%(X100), DQS PI = 38
2445 12:16:16.140362 [0] AVG Duty = 5047%(X100)
2446 12:16:16.140883
2447 12:16:16.141214 ==DQS 1 ==
2448 12:16:16.142999 Final DQS duty delay cell = 0
2449 12:16:16.146740 [0] MAX Duty = 5156%(X100), DQS PI = 8
2450 12:16:16.150280 [0] MIN Duty = 5031%(X100), DQS PI = 18
2451 12:16:16.153105 [0] AVG Duty = 5093%(X100)
2452 12:16:16.153618
2453 12:16:16.156846 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2454 12:16:16.157362
2455 12:16:16.159966 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2456 12:16:16.164066 [DutyScan_Calibration_Flow] ====Done====
2457 12:16:16.164583
2458 12:16:16.166209 [DutyScan_Calibration_Flow] k_type=3
2459 12:16:16.183949
2460 12:16:16.184460 ==DQM 0 ==
2461 12:16:16.186583 Final DQM duty delay cell = 0
2462 12:16:16.189995 [0] MAX Duty = 5031%(X100), DQS PI = 26
2463 12:16:16.193507 [0] MIN Duty = 4782%(X100), DQS PI = 38
2464 12:16:16.196999 [0] AVG Duty = 4906%(X100)
2465 12:16:16.197565
2466 12:16:16.197893 ==DQM 1 ==
2467 12:16:16.199473 Final DQM duty delay cell = 0
2468 12:16:16.202965 [0] MAX Duty = 4969%(X100), DQS PI = 32
2469 12:16:16.206106 [0] MIN Duty = 4844%(X100), DQS PI = 0
2470 12:16:16.210194 [0] AVG Duty = 4906%(X100)
2471 12:16:16.210704
2472 12:16:16.212745 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2473 12:16:16.213166
2474 12:16:16.216343 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2475 12:16:16.220087 [DutyScan_Calibration_Flow] ====Done====
2476 12:16:16.220616
2477 12:16:16.222819 [DutyScan_Calibration_Flow] k_type=2
2478 12:16:16.238908
2479 12:16:16.239623 ==DQ 0 ==
2480 12:16:16.242214 Final DQ duty delay cell = -4
2481 12:16:16.245334 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2482 12:16:16.249370 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2483 12:16:16.252205 [-4] AVG Duty = 4922%(X100)
2484 12:16:16.252740
2485 12:16:16.253134 ==DQ 1 ==
2486 12:16:16.255334 Final DQ duty delay cell = 0
2487 12:16:16.258791 [0] MAX Duty = 5031%(X100), DQS PI = 34
2488 12:16:16.261731 [0] MIN Duty = 4844%(X100), DQS PI = 62
2489 12:16:16.265362 [0] AVG Duty = 4937%(X100)
2490 12:16:16.265780
2491 12:16:16.268767 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2492 12:16:16.269187
2493 12:16:16.271834 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2494 12:16:16.275678 [DutyScan_Calibration_Flow] ====Done====
2495 12:16:16.278553 nWR fixed to 30
2496 12:16:16.281993 [ModeRegInit_LP4] CH0 RK0
2497 12:16:16.282513 [ModeRegInit_LP4] CH0 RK1
2498 12:16:16.285034 [ModeRegInit_LP4] CH1 RK0
2499 12:16:16.289086 [ModeRegInit_LP4] CH1 RK1
2500 12:16:16.289620 match AC timing 7
2501 12:16:16.295487 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2502 12:16:16.298614 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2503 12:16:16.302483 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2504 12:16:16.308424 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2505 12:16:16.311473 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2506 12:16:16.311915 ==
2507 12:16:16.315230 Dram Type= 6, Freq= 0, CH_0, rank 0
2508 12:16:16.318357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 12:16:16.318798 ==
2510 12:16:16.324782 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2511 12:16:16.331560 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2512 12:16:16.339307 [CA 0] Center 39 (9~70) winsize 62
2513 12:16:16.342410 [CA 1] Center 39 (9~70) winsize 62
2514 12:16:16.345834 [CA 2] Center 35 (5~66) winsize 62
2515 12:16:16.349426 [CA 3] Center 35 (5~66) winsize 62
2516 12:16:16.352968 [CA 4] Center 33 (3~64) winsize 62
2517 12:16:16.356228 [CA 5] Center 33 (3~63) winsize 61
2518 12:16:16.356751
2519 12:16:16.359148 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2520 12:16:16.359745
2521 12:16:16.362665 [CATrainingPosCal] consider 1 rank data
2522 12:16:16.366188 u2DelayCellTimex100 = 270/100 ps
2523 12:16:16.369833 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2524 12:16:16.375593 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2525 12:16:16.379316 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2526 12:16:16.382738 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2527 12:16:16.386194 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2528 12:16:16.389205 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2529 12:16:16.389739
2530 12:16:16.392769 CA PerBit enable=1, Macro0, CA PI delay=33
2531 12:16:16.393221
2532 12:16:16.395588 [CBTSetCACLKResult] CA Dly = 33
2533 12:16:16.396022 CS Dly: 7 (0~38)
2534 12:16:16.396470 ==
2535 12:16:16.399223 Dram Type= 6, Freq= 0, CH_0, rank 1
2536 12:16:16.406091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2537 12:16:16.406528 ==
2538 12:16:16.408692 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2539 12:16:16.415296 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2540 12:16:16.424944 [CA 0] Center 39 (9~70) winsize 62
2541 12:16:16.428759 [CA 1] Center 39 (9~70) winsize 62
2542 12:16:16.431871 [CA 2] Center 35 (5~66) winsize 62
2543 12:16:16.435078 [CA 3] Center 35 (5~66) winsize 62
2544 12:16:16.438255 [CA 4] Center 34 (4~65) winsize 62
2545 12:16:16.441896 [CA 5] Center 33 (3~64) winsize 62
2546 12:16:16.442431
2547 12:16:16.444914 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2548 12:16:16.445398
2549 12:16:16.448621 [CATrainingPosCal] consider 2 rank data
2550 12:16:16.452116 u2DelayCellTimex100 = 270/100 ps
2551 12:16:16.455099 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2552 12:16:16.458203 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2553 12:16:16.465462 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2554 12:16:16.468319 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2555 12:16:16.471762 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2556 12:16:16.474807 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2557 12:16:16.475319
2558 12:16:16.478181 CA PerBit enable=1, Macro0, CA PI delay=33
2559 12:16:16.478600
2560 12:16:16.481554 [CBTSetCACLKResult] CA Dly = 33
2561 12:16:16.481973 CS Dly: 8 (0~41)
2562 12:16:16.482302
2563 12:16:16.485608 ----->DramcWriteLeveling(PI) begin...
2564 12:16:16.488565 ==
2565 12:16:16.489085 Dram Type= 6, Freq= 0, CH_0, rank 0
2566 12:16:16.495098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2567 12:16:16.495689 ==
2568 12:16:16.498102 Write leveling (Byte 0): 31 => 31
2569 12:16:16.502445 Write leveling (Byte 1): 26 => 26
2570 12:16:16.504776 DramcWriteLeveling(PI) end<-----
2571 12:16:16.505202
2572 12:16:16.505532 ==
2573 12:16:16.508029 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 12:16:16.511741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 12:16:16.512268 ==
2576 12:16:16.514784 [Gating] SW mode calibration
2577 12:16:16.522239 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2578 12:16:16.525101 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2579 12:16:16.531568 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2580 12:16:16.534904 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2581 12:16:16.538455 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 12:16:16.545463 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 12:16:16.548471 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 12:16:16.551540 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 12:16:16.558190 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
2586 12:16:16.561254 0 15 28 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
2587 12:16:16.564625 1 0 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
2588 12:16:16.572078 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2589 12:16:16.574390 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 12:16:16.577720 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 12:16:16.584736 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 12:16:16.587745 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 12:16:16.591563 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2594 12:16:16.597868 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2595 12:16:16.601153 1 1 0 | B1->B0 | 2727 4646 | 1 0 | (0 0) (0 0)
2596 12:16:16.604952 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 12:16:16.611413 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 12:16:16.614730 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 12:16:16.617980 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 12:16:16.624311 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 12:16:16.627465 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 12:16:16.631522 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2603 12:16:16.637851 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2604 12:16:16.641740 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 12:16:16.643918 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 12:16:16.651603 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 12:16:16.653768 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 12:16:16.657687 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 12:16:16.663941 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 12:16:16.667294 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 12:16:16.670610 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 12:16:16.677577 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 12:16:16.681862 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 12:16:16.683935 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 12:16:16.690702 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 12:16:16.693591 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 12:16:16.697196 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2618 12:16:16.703995 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2619 12:16:16.706867 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2620 12:16:16.710494 Total UI for P1: 0, mck2ui 16
2621 12:16:16.714047 best dqsien dly found for B0: ( 1, 3, 26)
2622 12:16:16.716987 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 12:16:16.720628 Total UI for P1: 0, mck2ui 16
2624 12:16:16.723329 best dqsien dly found for B1: ( 1, 4, 0)
2625 12:16:16.727003 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2626 12:16:16.730226 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2627 12:16:16.730746
2628 12:16:16.733486 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2629 12:16:16.740516 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2630 12:16:16.741040 [Gating] SW calibration Done
2631 12:16:16.741380 ==
2632 12:16:16.743189 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 12:16:16.749986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 12:16:16.750522 ==
2635 12:16:16.750861 RX Vref Scan: 0
2636 12:16:16.751172
2637 12:16:16.753566 RX Vref 0 -> 0, step: 1
2638 12:16:16.753986
2639 12:16:16.757207 RX Delay -40 -> 252, step: 8
2640 12:16:16.759911 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2641 12:16:16.763824 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2642 12:16:16.766712 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2643 12:16:16.774055 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2644 12:16:16.777200 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2645 12:16:16.780265 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2646 12:16:16.783442 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2647 12:16:16.786741 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2648 12:16:16.793139 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2649 12:16:16.796697 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2650 12:16:16.799927 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2651 12:16:16.803954 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2652 12:16:16.806665 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2653 12:16:16.813153 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2654 12:16:16.816557 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2655 12:16:16.819863 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2656 12:16:16.820467 ==
2657 12:16:16.823033 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 12:16:16.826568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 12:16:16.827139 ==
2660 12:16:16.829738 DQS Delay:
2661 12:16:16.830200 DQS0 = 0, DQS1 = 0
2662 12:16:16.833192 DQM Delay:
2663 12:16:16.833609 DQM0 = 118, DQM1 = 108
2664 12:16:16.833944 DQ Delay:
2665 12:16:16.839532 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =115
2666 12:16:16.842802 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2667 12:16:16.846480 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2668 12:16:16.849193 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =115
2669 12:16:16.849611
2670 12:16:16.849939
2671 12:16:16.850241 ==
2672 12:16:16.852576 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 12:16:16.856070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 12:16:16.856487 ==
2675 12:16:16.856856
2676 12:16:16.857322
2677 12:16:16.859456 TX Vref Scan disable
2678 12:16:16.862593 == TX Byte 0 ==
2679 12:16:16.866794 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2680 12:16:16.870033 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2681 12:16:16.873055 == TX Byte 1 ==
2682 12:16:16.876225 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2683 12:16:16.879673 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2684 12:16:16.880093 ==
2685 12:16:16.882775 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 12:16:16.886809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 12:16:16.890218 ==
2688 12:16:16.900028 TX Vref=22, minBit 5, minWin=25, winSum=413
2689 12:16:16.903340 TX Vref=24, minBit 1, minWin=25, winSum=411
2690 12:16:16.906152 TX Vref=26, minBit 3, minWin=25, winSum=418
2691 12:16:16.910254 TX Vref=28, minBit 1, minWin=26, winSum=429
2692 12:16:16.913281 TX Vref=30, minBit 0, minWin=26, winSum=428
2693 12:16:16.920094 TX Vref=32, minBit 0, minWin=26, winSum=429
2694 12:16:16.922509 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
2695 12:16:16.922932
2696 12:16:16.926647 Final TX Range 1 Vref 28
2697 12:16:16.927175
2698 12:16:16.927569 ==
2699 12:16:16.929421 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 12:16:16.932447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 12:16:16.932868 ==
2702 12:16:16.935679
2703 12:16:16.936161
2704 12:16:16.936599 TX Vref Scan disable
2705 12:16:16.938905 == TX Byte 0 ==
2706 12:16:16.942511 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2707 12:16:16.949823 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2708 12:16:16.950351 == TX Byte 1 ==
2709 12:16:16.952570 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2710 12:16:16.959340 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2711 12:16:16.959922
2712 12:16:16.960256 [DATLAT]
2713 12:16:16.960565 Freq=1200, CH0 RK0
2714 12:16:16.960866
2715 12:16:16.962671 DATLAT Default: 0xd
2716 12:16:16.965957 0, 0xFFFF, sum = 0
2717 12:16:16.966489 1, 0xFFFF, sum = 0
2718 12:16:16.969091 2, 0xFFFF, sum = 0
2719 12:16:16.969622 3, 0xFFFF, sum = 0
2720 12:16:16.972600 4, 0xFFFF, sum = 0
2721 12:16:16.973134 5, 0xFFFF, sum = 0
2722 12:16:16.975563 6, 0xFFFF, sum = 0
2723 12:16:16.975991 7, 0xFFFF, sum = 0
2724 12:16:16.979094 8, 0xFFFF, sum = 0
2725 12:16:16.979560 9, 0xFFFF, sum = 0
2726 12:16:16.982304 10, 0xFFFF, sum = 0
2727 12:16:16.982731 11, 0xFFFF, sum = 0
2728 12:16:16.985828 12, 0x0, sum = 1
2729 12:16:16.986360 13, 0x0, sum = 2
2730 12:16:16.989054 14, 0x0, sum = 3
2731 12:16:16.989479 15, 0x0, sum = 4
2732 12:16:16.992160 best_step = 13
2733 12:16:16.992687
2734 12:16:16.993022 ==
2735 12:16:16.995959 Dram Type= 6, Freq= 0, CH_0, rank 0
2736 12:16:16.998996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2737 12:16:16.999557 ==
2738 12:16:16.999901 RX Vref Scan: 1
2739 12:16:17.002727
2740 12:16:17.003250 Set Vref Range= 32 -> 127
2741 12:16:17.003624
2742 12:16:17.005615 RX Vref 32 -> 127, step: 1
2743 12:16:17.006138
2744 12:16:17.008559 RX Delay -21 -> 252, step: 4
2745 12:16:17.008976
2746 12:16:17.012601 Set Vref, RX VrefLevel [Byte0]: 32
2747 12:16:17.015609 [Byte1]: 32
2748 12:16:17.016130
2749 12:16:17.019019 Set Vref, RX VrefLevel [Byte0]: 33
2750 12:16:17.022389 [Byte1]: 33
2751 12:16:17.025858
2752 12:16:17.026382 Set Vref, RX VrefLevel [Byte0]: 34
2753 12:16:17.029077 [Byte1]: 34
2754 12:16:17.033837
2755 12:16:17.034406 Set Vref, RX VrefLevel [Byte0]: 35
2756 12:16:17.037621 [Byte1]: 35
2757 12:16:17.041526
2758 12:16:17.042047 Set Vref, RX VrefLevel [Byte0]: 36
2759 12:16:17.044860 [Byte1]: 36
2760 12:16:17.049644
2761 12:16:17.050164 Set Vref, RX VrefLevel [Byte0]: 37
2762 12:16:17.053045 [Byte1]: 37
2763 12:16:17.058001
2764 12:16:17.058517 Set Vref, RX VrefLevel [Byte0]: 38
2765 12:16:17.060858 [Byte1]: 38
2766 12:16:17.065708
2767 12:16:17.066281 Set Vref, RX VrefLevel [Byte0]: 39
2768 12:16:17.068955 [Byte1]: 39
2769 12:16:17.073763
2770 12:16:17.074281 Set Vref, RX VrefLevel [Byte0]: 40
2771 12:16:17.076513 [Byte1]: 40
2772 12:16:17.081447
2773 12:16:17.082028 Set Vref, RX VrefLevel [Byte0]: 41
2774 12:16:17.084349 [Byte1]: 41
2775 12:16:17.089132
2776 12:16:17.089657 Set Vref, RX VrefLevel [Byte0]: 42
2777 12:16:17.093316 [Byte1]: 42
2778 12:16:17.097143
2779 12:16:17.097556 Set Vref, RX VrefLevel [Byte0]: 43
2780 12:16:17.100236 [Byte1]: 43
2781 12:16:17.106179
2782 12:16:17.106740 Set Vref, RX VrefLevel [Byte0]: 44
2783 12:16:17.108351 [Byte1]: 44
2784 12:16:17.114333
2785 12:16:17.114855 Set Vref, RX VrefLevel [Byte0]: 45
2786 12:16:17.116074 [Byte1]: 45
2787 12:16:17.121107
2788 12:16:17.121633 Set Vref, RX VrefLevel [Byte0]: 46
2789 12:16:17.123989 [Byte1]: 46
2790 12:16:17.129022
2791 12:16:17.129436 Set Vref, RX VrefLevel [Byte0]: 47
2792 12:16:17.131953 [Byte1]: 47
2793 12:16:17.136807
2794 12:16:17.137506 Set Vref, RX VrefLevel [Byte0]: 48
2795 12:16:17.139925 [Byte1]: 48
2796 12:16:17.144649
2797 12:16:17.145066 Set Vref, RX VrefLevel [Byte0]: 49
2798 12:16:17.147678 [Byte1]: 49
2799 12:16:17.152625
2800 12:16:17.153150 Set Vref, RX VrefLevel [Byte0]: 50
2801 12:16:17.156161 [Byte1]: 50
2802 12:16:17.160370
2803 12:16:17.160890 Set Vref, RX VrefLevel [Byte0]: 51
2804 12:16:17.164302 [Byte1]: 51
2805 12:16:17.168779
2806 12:16:17.169300 Set Vref, RX VrefLevel [Byte0]: 52
2807 12:16:17.172006 [Byte1]: 52
2808 12:16:17.176659
2809 12:16:17.177186 Set Vref, RX VrefLevel [Byte0]: 53
2810 12:16:17.180284 [Byte1]: 53
2811 12:16:17.184433
2812 12:16:17.184954 Set Vref, RX VrefLevel [Byte0]: 54
2813 12:16:17.188022 [Byte1]: 54
2814 12:16:17.192321
2815 12:16:17.192845 Set Vref, RX VrefLevel [Byte0]: 55
2816 12:16:17.195419 [Byte1]: 55
2817 12:16:17.200088
2818 12:16:17.200506 Set Vref, RX VrefLevel [Byte0]: 56
2819 12:16:17.203342 [Byte1]: 56
2820 12:16:17.207980
2821 12:16:17.208416 Set Vref, RX VrefLevel [Byte0]: 57
2822 12:16:17.211336 [Byte1]: 57
2823 12:16:17.216601
2824 12:16:17.217144 Set Vref, RX VrefLevel [Byte0]: 58
2825 12:16:17.219661 [Byte1]: 58
2826 12:16:17.223992
2827 12:16:17.224405 Set Vref, RX VrefLevel [Byte0]: 59
2828 12:16:17.227078 [Byte1]: 59
2829 12:16:17.232407
2830 12:16:17.232822 Set Vref, RX VrefLevel [Byte0]: 60
2831 12:16:17.238839 [Byte1]: 60
2832 12:16:17.239407
2833 12:16:17.241634 Set Vref, RX VrefLevel [Byte0]: 61
2834 12:16:17.244796 [Byte1]: 61
2835 12:16:17.245214
2836 12:16:17.248294 Set Vref, RX VrefLevel [Byte0]: 62
2837 12:16:17.251451 [Byte1]: 62
2838 12:16:17.255429
2839 12:16:17.255958 Set Vref, RX VrefLevel [Byte0]: 63
2840 12:16:17.259195 [Byte1]: 63
2841 12:16:17.264022
2842 12:16:17.264543 Set Vref, RX VrefLevel [Byte0]: 64
2843 12:16:17.266969 [Byte1]: 64
2844 12:16:17.271998
2845 12:16:17.272561 Set Vref, RX VrefLevel [Byte0]: 65
2846 12:16:17.275097 [Byte1]: 65
2847 12:16:17.280163
2848 12:16:17.280722 Set Vref, RX VrefLevel [Byte0]: 66
2849 12:16:17.282970 [Byte1]: 66
2850 12:16:17.287481
2851 12:16:17.288022 Set Vref, RX VrefLevel [Byte0]: 67
2852 12:16:17.291219 [Byte1]: 67
2853 12:16:17.295401
2854 12:16:17.295934 Set Vref, RX VrefLevel [Byte0]: 68
2855 12:16:17.298865 [Byte1]: 68
2856 12:16:17.303397
2857 12:16:17.303917 Set Vref, RX VrefLevel [Byte0]: 69
2858 12:16:17.306321 [Byte1]: 69
2859 12:16:17.311064
2860 12:16:17.311500 Final RX Vref Byte 0 = 53 to rank0
2861 12:16:17.314752 Final RX Vref Byte 1 = 59 to rank0
2862 12:16:17.318163 Final RX Vref Byte 0 = 53 to rank1
2863 12:16:17.321554 Final RX Vref Byte 1 = 59 to rank1==
2864 12:16:17.324324 Dram Type= 6, Freq= 0, CH_0, rank 0
2865 12:16:17.331440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2866 12:16:17.331969 ==
2867 12:16:17.332306 DQS Delay:
2868 12:16:17.332612 DQS0 = 0, DQS1 = 0
2869 12:16:17.334641 DQM Delay:
2870 12:16:17.335052 DQM0 = 117, DQM1 = 105
2871 12:16:17.337981 DQ Delay:
2872 12:16:17.341149 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2873 12:16:17.344253 DQ4 =120, DQ5 =110, DQ6 =124, DQ7 =120
2874 12:16:17.347703 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2875 12:16:17.351506 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2876 12:16:17.352051
2877 12:16:17.352392
2878 12:16:17.357505 [DQSOSCAuto] RK0, (LSB)MR18= 0xfffb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
2879 12:16:17.361251 CH0 RK0: MR19=303, MR18=FFFB
2880 12:16:17.367321 CH0_RK0: MR19=0x303, MR18=0xFFFB, DQSOSC=410, MR23=63, INC=39, DEC=26
2881 12:16:17.367878
2882 12:16:17.371046 ----->DramcWriteLeveling(PI) begin...
2883 12:16:17.371504 ==
2884 12:16:17.374815 Dram Type= 6, Freq= 0, CH_0, rank 1
2885 12:16:17.377523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2886 12:16:17.380523 ==
2887 12:16:17.380943 Write leveling (Byte 0): 33 => 33
2888 12:16:17.384095 Write leveling (Byte 1): 27 => 27
2889 12:16:17.387812 DramcWriteLeveling(PI) end<-----
2890 12:16:17.388227
2891 12:16:17.388552 ==
2892 12:16:17.391476 Dram Type= 6, Freq= 0, CH_0, rank 1
2893 12:16:17.397441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2894 12:16:17.397981 ==
2895 12:16:17.400822 [Gating] SW mode calibration
2896 12:16:17.407468 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2897 12:16:17.411504 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2898 12:16:17.417569 0 15 0 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
2899 12:16:17.420669 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2900 12:16:17.425670 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 12:16:17.430666 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2902 12:16:17.434119 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2903 12:16:17.437247 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2904 12:16:17.443630 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2905 12:16:17.447190 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
2906 12:16:17.450744 1 0 0 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
2907 12:16:17.454543 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 12:16:17.460605 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 12:16:17.463541 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 12:16:17.467126 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 12:16:17.473866 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 12:16:17.477729 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2913 12:16:17.480350 1 0 28 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
2914 12:16:17.487605 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2915 12:16:17.490166 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 12:16:17.493664 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 12:16:17.500422 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 12:16:17.503777 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 12:16:17.506923 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2920 12:16:17.513795 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2921 12:16:17.516731 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2922 12:16:17.520351 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 12:16:17.527161 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 12:16:17.530906 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 12:16:17.533743 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 12:16:17.540659 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 12:16:17.543544 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 12:16:17.546936 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 12:16:17.553309 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 12:16:17.556540 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 12:16:17.560334 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 12:16:17.566952 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 12:16:17.570096 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 12:16:17.573496 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 12:16:17.580145 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 12:16:17.583731 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2937 12:16:17.586898 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2938 12:16:17.589925 Total UI for P1: 0, mck2ui 16
2939 12:16:17.593204 best dqsien dly found for B0: ( 1, 3, 24)
2940 12:16:17.599328 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 12:16:17.599877 Total UI for P1: 0, mck2ui 16
2942 12:16:17.606385 best dqsien dly found for B1: ( 1, 3, 28)
2943 12:16:17.610154 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2944 12:16:17.613193 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2945 12:16:17.613606
2946 12:16:17.615956 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2947 12:16:17.619708 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2948 12:16:17.623062 [Gating] SW calibration Done
2949 12:16:17.623596 ==
2950 12:16:17.625676 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 12:16:17.630319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 12:16:17.630839 ==
2953 12:16:17.632194 RX Vref Scan: 0
2954 12:16:17.632617
2955 12:16:17.632948 RX Vref 0 -> 0, step: 1
2956 12:16:17.633262
2957 12:16:17.635547 RX Delay -40 -> 252, step: 8
2958 12:16:17.642743 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2959 12:16:17.645470 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2960 12:16:17.648997 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2961 12:16:17.652677 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2962 12:16:17.655746 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2963 12:16:17.659576 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2964 12:16:17.665572 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2965 12:16:17.668959 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2966 12:16:17.672624 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2967 12:16:17.675571 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2968 12:16:17.678881 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2969 12:16:17.685073 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2970 12:16:17.688785 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2971 12:16:17.692295 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2972 12:16:17.695114 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2973 12:16:17.702158 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2974 12:16:17.702692 ==
2975 12:16:17.705390 Dram Type= 6, Freq= 0, CH_0, rank 1
2976 12:16:17.708455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 12:16:17.709005 ==
2978 12:16:17.709443 DQS Delay:
2979 12:16:17.711474 DQS0 = 0, DQS1 = 0
2980 12:16:17.711911 DQM Delay:
2981 12:16:17.715073 DQM0 = 116, DQM1 = 109
2982 12:16:17.715533 DQ Delay:
2983 12:16:17.719167 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2984 12:16:17.721375 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =119
2985 12:16:17.724943 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2986 12:16:17.728580 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =115
2987 12:16:17.729001
2988 12:16:17.731412
2989 12:16:17.731843 ==
2990 12:16:17.734568 Dram Type= 6, Freq= 0, CH_0, rank 1
2991 12:16:17.737949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2992 12:16:17.738372 ==
2993 12:16:17.738708
2994 12:16:17.739024
2995 12:16:17.741371 TX Vref Scan disable
2996 12:16:17.741984 == TX Byte 0 ==
2997 12:16:17.748013 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2998 12:16:17.751481 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2999 12:16:17.751908 == TX Byte 1 ==
3000 12:16:17.757872 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3001 12:16:17.760880 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3002 12:16:17.761109 ==
3003 12:16:17.764540 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 12:16:17.767631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 12:16:17.767816 ==
3006 12:16:17.780110 TX Vref=22, minBit 1, minWin=25, winSum=416
3007 12:16:17.783372 TX Vref=24, minBit 1, minWin=26, winSum=423
3008 12:16:17.787886 TX Vref=26, minBit 10, minWin=25, winSum=423
3009 12:16:17.789649 TX Vref=28, minBit 10, minWin=26, winSum=428
3010 12:16:17.793349 TX Vref=30, minBit 10, minWin=26, winSum=428
3011 12:16:17.800233 TX Vref=32, minBit 13, minWin=25, winSum=425
3012 12:16:17.802905 [TxChooseVref] Worse bit 10, Min win 26, Win sum 428, Final Vref 28
3013 12:16:17.806750
3014 12:16:17.806832 Final TX Range 1 Vref 28
3015 12:16:17.806897
3016 12:16:17.806957 ==
3017 12:16:17.809776 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 12:16:17.816225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 12:16:17.816310 ==
3020 12:16:17.816376
3021 12:16:17.816437
3022 12:16:17.816495 TX Vref Scan disable
3023 12:16:17.820565 == TX Byte 0 ==
3024 12:16:17.823534 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3025 12:16:17.830281 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3026 12:16:17.830392 == TX Byte 1 ==
3027 12:16:17.834036 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3028 12:16:17.840428 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3029 12:16:17.840591
3030 12:16:17.840668 [DATLAT]
3031 12:16:17.840735 Freq=1200, CH0 RK1
3032 12:16:17.840800
3033 12:16:17.843688 DATLAT Default: 0xd
3034 12:16:17.843818 0, 0xFFFF, sum = 0
3035 12:16:17.847316 1, 0xFFFF, sum = 0
3036 12:16:17.850645 2, 0xFFFF, sum = 0
3037 12:16:17.850823 3, 0xFFFF, sum = 0
3038 12:16:17.853833 4, 0xFFFF, sum = 0
3039 12:16:17.853983 5, 0xFFFF, sum = 0
3040 12:16:17.856798 6, 0xFFFF, sum = 0
3041 12:16:17.856960 7, 0xFFFF, sum = 0
3042 12:16:17.860411 8, 0xFFFF, sum = 0
3043 12:16:17.860626 9, 0xFFFF, sum = 0
3044 12:16:17.863444 10, 0xFFFF, sum = 0
3045 12:16:17.863630 11, 0xFFFF, sum = 0
3046 12:16:17.867234 12, 0x0, sum = 1
3047 12:16:17.867464 13, 0x0, sum = 2
3048 12:16:17.870299 14, 0x0, sum = 3
3049 12:16:17.870564 15, 0x0, sum = 4
3050 12:16:17.870748 best_step = 13
3051 12:16:17.873643
3052 12:16:17.873888 ==
3053 12:16:17.877015 Dram Type= 6, Freq= 0, CH_0, rank 1
3054 12:16:17.880114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3055 12:16:17.880390 ==
3056 12:16:17.880550 RX Vref Scan: 0
3057 12:16:17.880697
3058 12:16:17.883808 RX Vref 0 -> 0, step: 1
3059 12:16:17.884024
3060 12:16:17.886928 RX Delay -21 -> 252, step: 4
3061 12:16:17.891464 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3062 12:16:17.897353 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3063 12:16:17.900739 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3064 12:16:17.903971 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3065 12:16:17.907332 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3066 12:16:17.910115 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3067 12:16:17.917049 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3068 12:16:17.920132 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3069 12:16:17.923995 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3070 12:16:17.927308 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3071 12:16:17.930081 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3072 12:16:17.936718 iDelay=195, Bit 11, Center 100 (31 ~ 170) 140
3073 12:16:17.940326 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3074 12:16:17.943955 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3075 12:16:17.946940 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3076 12:16:17.953699 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3077 12:16:17.954214 ==
3078 12:16:17.957209 Dram Type= 6, Freq= 0, CH_0, rank 1
3079 12:16:17.960598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3080 12:16:17.961133 ==
3081 12:16:17.961475 DQS Delay:
3082 12:16:17.963393 DQS0 = 0, DQS1 = 0
3083 12:16:17.963927 DQM Delay:
3084 12:16:17.967267 DQM0 = 116, DQM1 = 106
3085 12:16:17.967851 DQ Delay:
3086 12:16:17.970121 DQ0 =114, DQ1 =116, DQ2 =112, DQ3 =112
3087 12:16:17.973562 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3088 12:16:17.977119 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
3089 12:16:17.979917 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =112
3090 12:16:17.980354
3091 12:16:17.980736
3092 12:16:17.990005 [DQSOSCAuto] RK1, (LSB)MR18= 0xfaf7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
3093 12:16:17.993321 CH0 RK1: MR19=303, MR18=FAF7
3094 12:16:17.996450 CH0_RK1: MR19=0x303, MR18=0xFAF7, DQSOSC=412, MR23=63, INC=38, DEC=25
3095 12:16:17.999879 [RxdqsGatingPostProcess] freq 1200
3096 12:16:18.007030 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3097 12:16:18.009664 best DQS0 dly(2T, 0.5T) = (0, 11)
3098 12:16:18.013357 best DQS1 dly(2T, 0.5T) = (0, 12)
3099 12:16:18.016952 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3100 12:16:18.019855 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3101 12:16:18.022977 best DQS0 dly(2T, 0.5T) = (0, 11)
3102 12:16:18.026609 best DQS1 dly(2T, 0.5T) = (0, 11)
3103 12:16:18.029296 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3104 12:16:18.033664 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3105 12:16:18.036517 Pre-setting of DQS Precalculation
3106 12:16:18.039741 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3107 12:16:18.040275 ==
3108 12:16:18.043259 Dram Type= 6, Freq= 0, CH_1, rank 0
3109 12:16:18.046381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3110 12:16:18.046913 ==
3111 12:16:18.052885 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3112 12:16:18.059262 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3113 12:16:18.067285 [CA 0] Center 38 (8~68) winsize 61
3114 12:16:18.071171 [CA 1] Center 37 (7~68) winsize 62
3115 12:16:18.073800 [CA 2] Center 35 (5~65) winsize 61
3116 12:16:18.077898 [CA 3] Center 34 (4~64) winsize 61
3117 12:16:18.080414 [CA 4] Center 34 (4~65) winsize 62
3118 12:16:18.084474 [CA 5] Center 34 (4~64) winsize 61
3119 12:16:18.085000
3120 12:16:18.087047 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3121 12:16:18.087513
3122 12:16:18.090465 [CATrainingPosCal] consider 1 rank data
3123 12:16:18.094140 u2DelayCellTimex100 = 270/100 ps
3124 12:16:18.097212 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3125 12:16:18.100393 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3126 12:16:18.107283 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3127 12:16:18.110595 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3128 12:16:18.113646 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3129 12:16:18.117189 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3130 12:16:18.117725
3131 12:16:18.120088 CA PerBit enable=1, Macro0, CA PI delay=34
3132 12:16:18.120512
3133 12:16:18.123528 [CBTSetCACLKResult] CA Dly = 34
3134 12:16:18.123956 CS Dly: 4 (0~35)
3135 12:16:18.127439 ==
3136 12:16:18.127973 Dram Type= 6, Freq= 0, CH_1, rank 1
3137 12:16:18.134003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 12:16:18.134536 ==
3139 12:16:18.137061 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3140 12:16:18.144081 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3141 12:16:18.152994 [CA 0] Center 37 (7~68) winsize 62
3142 12:16:18.156097 [CA 1] Center 38 (8~68) winsize 61
3143 12:16:18.159460 [CA 2] Center 35 (5~65) winsize 61
3144 12:16:18.162911 [CA 3] Center 33 (3~64) winsize 62
3145 12:16:18.166210 [CA 4] Center 34 (4~64) winsize 61
3146 12:16:18.169449 [CA 5] Center 33 (4~63) winsize 60
3147 12:16:18.169981
3148 12:16:18.172751 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3149 12:16:18.173177
3150 12:16:18.176227 [CATrainingPosCal] consider 2 rank data
3151 12:16:18.179691 u2DelayCellTimex100 = 270/100 ps
3152 12:16:18.182316 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3153 12:16:18.189524 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3154 12:16:18.192518 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3155 12:16:18.195726 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3156 12:16:18.198851 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3157 12:16:18.202506 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3158 12:16:18.203040
3159 12:16:18.205896 CA PerBit enable=1, Macro0, CA PI delay=33
3160 12:16:18.206605
3161 12:16:18.209052 [CBTSetCACLKResult] CA Dly = 33
3162 12:16:18.212110 CS Dly: 6 (0~39)
3163 12:16:18.212532
3164 12:16:18.215430 ----->DramcWriteLeveling(PI) begin...
3165 12:16:18.215864 ==
3166 12:16:18.218901 Dram Type= 6, Freq= 0, CH_1, rank 0
3167 12:16:18.222413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3168 12:16:18.222946 ==
3169 12:16:18.225630 Write leveling (Byte 0): 25 => 25
3170 12:16:18.228650 Write leveling (Byte 1): 26 => 26
3171 12:16:18.231916 DramcWriteLeveling(PI) end<-----
3172 12:16:18.232412
3173 12:16:18.232846 ==
3174 12:16:18.235393 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 12:16:18.238895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3176 12:16:18.239325 ==
3177 12:16:18.242642 [Gating] SW mode calibration
3178 12:16:18.248636 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3179 12:16:18.255447 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3180 12:16:18.258926 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3181 12:16:18.262084 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 12:16:18.268519 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 12:16:18.271750 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 12:16:18.275224 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 12:16:18.282306 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3186 12:16:18.285466 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3187 12:16:18.288662 0 15 28 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
3188 12:16:18.295668 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 12:16:18.298777 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 12:16:18.301873 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 12:16:18.309334 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 12:16:18.311396 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 12:16:18.315056 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 12:16:18.321933 1 0 24 | B1->B0 | 2525 2b2b | 0 0 | (0 0) (0 0)
3195 12:16:18.324634 1 0 28 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
3196 12:16:18.328628 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 12:16:18.334644 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 12:16:18.337929 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 12:16:18.341829 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 12:16:18.348036 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 12:16:18.351143 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 12:16:18.354682 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 12:16:18.361408 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3204 12:16:18.364776 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 12:16:18.367945 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 12:16:18.371786 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 12:16:18.377448 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 12:16:18.380827 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 12:16:18.387722 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 12:16:18.391234 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 12:16:18.394202 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 12:16:18.397580 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 12:16:18.404383 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 12:16:18.407717 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 12:16:18.410790 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 12:16:18.417492 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 12:16:18.420906 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 12:16:18.423988 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 12:16:18.430684 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3220 12:16:18.433795 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 12:16:18.437320 Total UI for P1: 0, mck2ui 16
3222 12:16:18.440360 best dqsien dly found for B0: ( 1, 3, 28)
3223 12:16:18.443688 Total UI for P1: 0, mck2ui 16
3224 12:16:18.447494 best dqsien dly found for B1: ( 1, 3, 28)
3225 12:16:18.451666 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3226 12:16:18.453850 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3227 12:16:18.454368
3228 12:16:18.457043 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3229 12:16:18.460726 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3230 12:16:18.463826 [Gating] SW calibration Done
3231 12:16:18.464249 ==
3232 12:16:18.467314 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 12:16:18.473640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 12:16:18.474055 ==
3235 12:16:18.474381 RX Vref Scan: 0
3236 12:16:18.474684
3237 12:16:18.477220 RX Vref 0 -> 0, step: 1
3238 12:16:18.477942
3239 12:16:18.480203 RX Delay -40 -> 252, step: 8
3240 12:16:18.483723 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3241 12:16:18.487418 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3242 12:16:18.490332 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3243 12:16:18.496681 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3244 12:16:18.499955 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3245 12:16:18.504746 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3246 12:16:18.506580 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3247 12:16:18.510283 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3248 12:16:18.513852 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3249 12:16:18.519744 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3250 12:16:18.522997 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3251 12:16:18.527440 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3252 12:16:18.530094 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3253 12:16:18.536808 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3254 12:16:18.540782 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3255 12:16:18.543324 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3256 12:16:18.543795 ==
3257 12:16:18.546471 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 12:16:18.549623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 12:16:18.550055 ==
3260 12:16:18.553029 DQS Delay:
3261 12:16:18.553451 DQS0 = 0, DQS1 = 0
3262 12:16:18.556563 DQM Delay:
3263 12:16:18.557089 DQM0 = 116, DQM1 = 113
3264 12:16:18.557430 DQ Delay:
3265 12:16:18.563161 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3266 12:16:18.566330 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3267 12:16:18.569837 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3268 12:16:18.573153 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3269 12:16:18.573586
3270 12:16:18.573920
3271 12:16:18.574232 ==
3272 12:16:18.576175 Dram Type= 6, Freq= 0, CH_1, rank 0
3273 12:16:18.579832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3274 12:16:18.580296 ==
3275 12:16:18.580635
3276 12:16:18.580950
3277 12:16:18.582786 TX Vref Scan disable
3278 12:16:18.586271 == TX Byte 0 ==
3279 12:16:18.589422 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3280 12:16:18.592959 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3281 12:16:18.596240 == TX Byte 1 ==
3282 12:16:18.599199 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3283 12:16:18.602406 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3284 12:16:18.602834 ==
3285 12:16:18.605971 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 12:16:18.612523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 12:16:18.613051 ==
3288 12:16:18.622950 TX Vref=22, minBit 11, minWin=24, winSum=411
3289 12:16:18.626336 TX Vref=24, minBit 9, minWin=23, winSum=410
3290 12:16:18.629277 TX Vref=26, minBit 11, minWin=24, winSum=418
3291 12:16:18.632636 TX Vref=28, minBit 9, minWin=25, winSum=421
3292 12:16:18.636248 TX Vref=30, minBit 0, minWin=26, winSum=424
3293 12:16:18.642821 TX Vref=32, minBit 9, minWin=25, winSum=421
3294 12:16:18.646206 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 30
3295 12:16:18.646738
3296 12:16:18.649435 Final TX Range 1 Vref 30
3297 12:16:18.649860
3298 12:16:18.650198 ==
3299 12:16:18.652561 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 12:16:18.656493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 12:16:18.659719 ==
3302 12:16:18.660298
3303 12:16:18.660808
3304 12:16:18.661174 TX Vref Scan disable
3305 12:16:18.662639 == TX Byte 0 ==
3306 12:16:18.666151 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3307 12:16:18.669240 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3308 12:16:18.672872 == TX Byte 1 ==
3309 12:16:18.676747 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3310 12:16:18.682847 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3311 12:16:18.683271
3312 12:16:18.683651 [DATLAT]
3313 12:16:18.683963 Freq=1200, CH1 RK0
3314 12:16:18.684263
3315 12:16:18.685774 DATLAT Default: 0xd
3316 12:16:18.686197 0, 0xFFFF, sum = 0
3317 12:16:18.689689 1, 0xFFFF, sum = 0
3318 12:16:18.690120 2, 0xFFFF, sum = 0
3319 12:16:18.692658 3, 0xFFFF, sum = 0
3320 12:16:18.696365 4, 0xFFFF, sum = 0
3321 12:16:18.696897 5, 0xFFFF, sum = 0
3322 12:16:18.699617 6, 0xFFFF, sum = 0
3323 12:16:18.700155 7, 0xFFFF, sum = 0
3324 12:16:18.702494 8, 0xFFFF, sum = 0
3325 12:16:18.703013 9, 0xFFFF, sum = 0
3326 12:16:18.705691 10, 0xFFFF, sum = 0
3327 12:16:18.706159 11, 0xFFFF, sum = 0
3328 12:16:18.709151 12, 0x0, sum = 1
3329 12:16:18.709609 13, 0x0, sum = 2
3330 12:16:18.712628 14, 0x0, sum = 3
3331 12:16:18.713149 15, 0x0, sum = 4
3332 12:16:18.713520 best_step = 13
3333 12:16:18.715585
3334 12:16:18.716140 ==
3335 12:16:18.718899 Dram Type= 6, Freq= 0, CH_1, rank 0
3336 12:16:18.722558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3337 12:16:18.723084 ==
3338 12:16:18.723606 RX Vref Scan: 1
3339 12:16:18.724019
3340 12:16:18.725838 Set Vref Range= 32 -> 127
3341 12:16:18.726261
3342 12:16:18.729262 RX Vref 32 -> 127, step: 1
3343 12:16:18.729790
3344 12:16:18.732167 RX Delay -13 -> 252, step: 4
3345 12:16:18.732594
3346 12:16:18.735869 Set Vref, RX VrefLevel [Byte0]: 32
3347 12:16:18.739174 [Byte1]: 32
3348 12:16:18.739693
3349 12:16:18.742301 Set Vref, RX VrefLevel [Byte0]: 33
3350 12:16:18.745657 [Byte1]: 33
3351 12:16:18.749161
3352 12:16:18.749669 Set Vref, RX VrefLevel [Byte0]: 34
3353 12:16:18.752152 [Byte1]: 34
3354 12:16:18.756872
3355 12:16:18.757392 Set Vref, RX VrefLevel [Byte0]: 35
3356 12:16:18.760656 [Byte1]: 35
3357 12:16:18.764541
3358 12:16:18.764972 Set Vref, RX VrefLevel [Byte0]: 36
3359 12:16:18.768308 [Byte1]: 36
3360 12:16:18.772473
3361 12:16:18.772986 Set Vref, RX VrefLevel [Byte0]: 37
3362 12:16:18.775902 [Byte1]: 37
3363 12:16:18.780330
3364 12:16:18.780842 Set Vref, RX VrefLevel [Byte0]: 38
3365 12:16:18.783660 [Byte1]: 38
3366 12:16:18.788240
3367 12:16:18.788626 Set Vref, RX VrefLevel [Byte0]: 39
3368 12:16:18.792183 [Byte1]: 39
3369 12:16:18.796143
3370 12:16:18.796400 Set Vref, RX VrefLevel [Byte0]: 40
3371 12:16:18.799341 [Byte1]: 40
3372 12:16:18.803646
3373 12:16:18.803884 Set Vref, RX VrefLevel [Byte0]: 41
3374 12:16:18.807230 [Byte1]: 41
3375 12:16:18.812027
3376 12:16:18.812284 Set Vref, RX VrefLevel [Byte0]: 42
3377 12:16:18.815806 [Byte1]: 42
3378 12:16:18.820255
3379 12:16:18.820662 Set Vref, RX VrefLevel [Byte0]: 43
3380 12:16:18.822974 [Byte1]: 43
3381 12:16:18.827667
3382 12:16:18.828101 Set Vref, RX VrefLevel [Byte0]: 44
3383 12:16:18.831154 [Byte1]: 44
3384 12:16:18.835539
3385 12:16:18.835946 Set Vref, RX VrefLevel [Byte0]: 45
3386 12:16:18.839244 [Byte1]: 45
3387 12:16:18.844084
3388 12:16:18.844593 Set Vref, RX VrefLevel [Byte0]: 46
3389 12:16:18.847003 [Byte1]: 46
3390 12:16:18.851509
3391 12:16:18.852013 Set Vref, RX VrefLevel [Byte0]: 47
3392 12:16:18.855038 [Byte1]: 47
3393 12:16:18.859496
3394 12:16:18.860022 Set Vref, RX VrefLevel [Byte0]: 48
3395 12:16:18.863279 [Byte1]: 48
3396 12:16:18.867568
3397 12:16:18.868072 Set Vref, RX VrefLevel [Byte0]: 49
3398 12:16:18.870549 [Byte1]: 49
3399 12:16:18.875348
3400 12:16:18.875921 Set Vref, RX VrefLevel [Byte0]: 50
3401 12:16:18.879095 [Byte1]: 50
3402 12:16:18.882982
3403 12:16:18.883462 Set Vref, RX VrefLevel [Byte0]: 51
3404 12:16:18.886786 [Byte1]: 51
3405 12:16:18.890783
3406 12:16:18.891406 Set Vref, RX VrefLevel [Byte0]: 52
3407 12:16:18.894202 [Byte1]: 52
3408 12:16:18.898721
3409 12:16:18.899129 Set Vref, RX VrefLevel [Byte0]: 53
3410 12:16:18.901937 [Byte1]: 53
3411 12:16:18.906699
3412 12:16:18.907103 Set Vref, RX VrefLevel [Byte0]: 54
3413 12:16:18.910249 [Byte1]: 54
3414 12:16:18.914527
3415 12:16:18.915047 Set Vref, RX VrefLevel [Byte0]: 55
3416 12:16:18.918134 [Byte1]: 55
3417 12:16:18.922867
3418 12:16:18.923420 Set Vref, RX VrefLevel [Byte0]: 56
3419 12:16:18.925726 [Byte1]: 56
3420 12:16:18.930180
3421 12:16:18.930707 Set Vref, RX VrefLevel [Byte0]: 57
3422 12:16:18.934022 [Byte1]: 57
3423 12:16:18.938045
3424 12:16:18.938462 Set Vref, RX VrefLevel [Byte0]: 58
3425 12:16:18.941550 [Byte1]: 58
3426 12:16:18.945897
3427 12:16:18.946431 Set Vref, RX VrefLevel [Byte0]: 59
3428 12:16:18.949998 [Byte1]: 59
3429 12:16:18.954037
3430 12:16:18.954556 Set Vref, RX VrefLevel [Byte0]: 60
3431 12:16:18.957463 [Byte1]: 60
3432 12:16:18.961781
3433 12:16:18.962304 Set Vref, RX VrefLevel [Byte0]: 61
3434 12:16:18.965435 [Byte1]: 61
3435 12:16:18.969660
3436 12:16:18.970221 Set Vref, RX VrefLevel [Byte0]: 62
3437 12:16:18.973220 [Byte1]: 62
3438 12:16:18.977673
3439 12:16:18.978220 Set Vref, RX VrefLevel [Byte0]: 63
3440 12:16:18.980765 [Byte1]: 63
3441 12:16:18.985601
3442 12:16:18.986123 Set Vref, RX VrefLevel [Byte0]: 64
3443 12:16:18.989060 [Byte1]: 64
3444 12:16:18.993458
3445 12:16:18.993979 Final RX Vref Byte 0 = 51 to rank0
3446 12:16:18.996286 Final RX Vref Byte 1 = 51 to rank0
3447 12:16:19.000044 Final RX Vref Byte 0 = 51 to rank1
3448 12:16:19.003198 Final RX Vref Byte 1 = 51 to rank1==
3449 12:16:19.006651 Dram Type= 6, Freq= 0, CH_1, rank 0
3450 12:16:19.013262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3451 12:16:19.013764 ==
3452 12:16:19.014099 DQS Delay:
3453 12:16:19.014408 DQS0 = 0, DQS1 = 0
3454 12:16:19.016713 DQM Delay:
3455 12:16:19.017132 DQM0 = 114, DQM1 = 112
3456 12:16:19.019757 DQ Delay:
3457 12:16:19.023444 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3458 12:16:19.026596 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3459 12:16:19.029977 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3460 12:16:19.033259 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =120
3461 12:16:19.033677
3462 12:16:19.034005
3463 12:16:19.043007 [DQSOSCAuto] RK0, (LSB)MR18= 0xeffc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
3464 12:16:19.043580 CH1 RK0: MR19=303, MR18=EFFC
3465 12:16:19.049705 CH1_RK0: MR19=0x303, MR18=0xEFFC, DQSOSC=411, MR23=63, INC=38, DEC=25
3466 12:16:19.050252
3467 12:16:19.053403 ----->DramcWriteLeveling(PI) begin...
3468 12:16:19.053939 ==
3469 12:16:19.056286 Dram Type= 6, Freq= 0, CH_1, rank 1
3470 12:16:19.063407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3471 12:16:19.063954 ==
3472 12:16:19.066260 Write leveling (Byte 0): 25 => 25
3473 12:16:19.069473 Write leveling (Byte 1): 28 => 28
3474 12:16:19.069997 DramcWriteLeveling(PI) end<-----
3475 12:16:19.070332
3476 12:16:19.072859 ==
3477 12:16:19.076271 Dram Type= 6, Freq= 0, CH_1, rank 1
3478 12:16:19.080145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 12:16:19.080671 ==
3480 12:16:19.082824 [Gating] SW mode calibration
3481 12:16:19.089340 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3482 12:16:19.092914 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3483 12:16:19.099398 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3484 12:16:19.102413 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 12:16:19.105926 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 12:16:19.112579 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 12:16:19.115776 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 12:16:19.119060 0 15 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3489 12:16:19.125924 0 15 24 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
3490 12:16:19.129328 0 15 28 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
3491 12:16:19.132078 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 12:16:19.139208 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 12:16:19.142473 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 12:16:19.145663 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 12:16:19.151777 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 12:16:19.155855 1 0 20 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3497 12:16:19.158439 1 0 24 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
3498 12:16:19.165791 1 0 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
3499 12:16:19.168965 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 12:16:19.172033 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 12:16:19.178728 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 12:16:19.182211 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 12:16:19.185359 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 12:16:19.192003 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 12:16:19.195620 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3506 12:16:19.198709 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3507 12:16:19.205286 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 12:16:19.208062 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 12:16:19.212097 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 12:16:19.218432 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 12:16:19.221669 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 12:16:19.225301 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 12:16:19.231493 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 12:16:19.234670 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 12:16:19.238403 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 12:16:19.245576 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 12:16:19.247739 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 12:16:19.251102 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 12:16:19.258002 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 12:16:19.261101 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3521 12:16:19.263938 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3522 12:16:19.271526 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3523 12:16:19.272043 Total UI for P1: 0, mck2ui 16
3524 12:16:19.277402 best dqsien dly found for B0: ( 1, 3, 22)
3525 12:16:19.280674 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 12:16:19.284058 Total UI for P1: 0, mck2ui 16
3527 12:16:19.287141 best dqsien dly found for B1: ( 1, 3, 28)
3528 12:16:19.290656 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3529 12:16:19.293806 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3530 12:16:19.294344
3531 12:16:19.297058 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3532 12:16:19.300102 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3533 12:16:19.303742 [Gating] SW calibration Done
3534 12:16:19.304264 ==
3535 12:16:19.307249 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 12:16:19.313905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 12:16:19.314432 ==
3538 12:16:19.314764 RX Vref Scan: 0
3539 12:16:19.315064
3540 12:16:19.316519 RX Vref 0 -> 0, step: 1
3541 12:16:19.316989
3542 12:16:19.319798 RX Delay -40 -> 252, step: 8
3543 12:16:19.323148 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3544 12:16:19.326361 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3545 12:16:19.329840 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3546 12:16:19.336494 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3547 12:16:19.339233 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3548 12:16:19.342787 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3549 12:16:19.345545 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3550 12:16:19.349154 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3551 12:16:19.355922 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3552 12:16:19.359188 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3553 12:16:19.362511 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3554 12:16:19.365680 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3555 12:16:19.372259 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3556 12:16:19.375431 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3557 12:16:19.378743 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3558 12:16:19.381923 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3559 12:16:19.382338 ==
3560 12:16:19.385451 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 12:16:19.392146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 12:16:19.392683 ==
3563 12:16:19.393013 DQS Delay:
3564 12:16:19.395112 DQS0 = 0, DQS1 = 0
3565 12:16:19.395551 DQM Delay:
3566 12:16:19.395878 DQM0 = 114, DQM1 = 111
3567 12:16:19.398083 DQ Delay:
3568 12:16:19.401513 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3569 12:16:19.405452 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =115
3570 12:16:19.408353 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3571 12:16:19.411653 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3572 12:16:19.412168
3573 12:16:19.412497
3574 12:16:19.412798 ==
3575 12:16:19.415323 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 12:16:19.421104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 12:16:19.421600 ==
3578 12:16:19.421928
3579 12:16:19.422228
3580 12:16:19.422517 TX Vref Scan disable
3581 12:16:19.424569 == TX Byte 0 ==
3582 12:16:19.428122 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3583 12:16:19.434462 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3584 12:16:19.434993 == TX Byte 1 ==
3585 12:16:19.438001 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3586 12:16:19.444474 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3587 12:16:19.445037 ==
3588 12:16:19.447809 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 12:16:19.450874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 12:16:19.451290 ==
3591 12:16:19.462114 TX Vref=22, minBit 1, minWin=25, winSum=421
3592 12:16:19.465758 TX Vref=24, minBit 9, minWin=25, winSum=423
3593 12:16:19.469225 TX Vref=26, minBit 9, minWin=25, winSum=426
3594 12:16:19.472311 TX Vref=28, minBit 1, minWin=26, winSum=430
3595 12:16:19.475773 TX Vref=30, minBit 7, minWin=26, winSum=434
3596 12:16:19.482167 TX Vref=32, minBit 2, minWin=26, winSum=435
3597 12:16:19.485421 [TxChooseVref] Worse bit 2, Min win 26, Win sum 435, Final Vref 32
3598 12:16:19.485903
3599 12:16:19.490027 Final TX Range 1 Vref 32
3600 12:16:19.490552
3601 12:16:19.490882 ==
3602 12:16:19.491943 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 12:16:19.495610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 12:16:19.498999 ==
3605 12:16:19.499591
3606 12:16:19.499957
3607 12:16:19.500288 TX Vref Scan disable
3608 12:16:19.502244 == TX Byte 0 ==
3609 12:16:19.505470 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3610 12:16:19.512286 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3611 12:16:19.512717 == TX Byte 1 ==
3612 12:16:19.515427 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3613 12:16:19.521534 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3614 12:16:19.522030
3615 12:16:19.522416 [DATLAT]
3616 12:16:19.522736 Freq=1200, CH1 RK1
3617 12:16:19.523031
3618 12:16:19.524999 DATLAT Default: 0xd
3619 12:16:19.528406 0, 0xFFFF, sum = 0
3620 12:16:19.528828 1, 0xFFFF, sum = 0
3621 12:16:19.531916 2, 0xFFFF, sum = 0
3622 12:16:19.532335 3, 0xFFFF, sum = 0
3623 12:16:19.535150 4, 0xFFFF, sum = 0
3624 12:16:19.535604 5, 0xFFFF, sum = 0
3625 12:16:19.538460 6, 0xFFFF, sum = 0
3626 12:16:19.538999 7, 0xFFFF, sum = 0
3627 12:16:19.542055 8, 0xFFFF, sum = 0
3628 12:16:19.542477 9, 0xFFFF, sum = 0
3629 12:16:19.544603 10, 0xFFFF, sum = 0
3630 12:16:19.545021 11, 0xFFFF, sum = 0
3631 12:16:19.548073 12, 0x0, sum = 1
3632 12:16:19.548494 13, 0x0, sum = 2
3633 12:16:19.551223 14, 0x0, sum = 3
3634 12:16:19.551686 15, 0x0, sum = 4
3635 12:16:19.554513 best_step = 13
3636 12:16:19.554924
3637 12:16:19.555251 ==
3638 12:16:19.557607 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 12:16:19.561250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 12:16:19.561816 ==
3641 12:16:19.564395 RX Vref Scan: 0
3642 12:16:19.564805
3643 12:16:19.565155 RX Vref 0 -> 0, step: 1
3644 12:16:19.565478
3645 12:16:19.567856 RX Delay -13 -> 252, step: 4
3646 12:16:19.574178 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3647 12:16:19.577512 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3648 12:16:19.580660 iDelay=195, Bit 2, Center 108 (43 ~ 174) 132
3649 12:16:19.583903 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3650 12:16:19.587702 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3651 12:16:19.593865 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3652 12:16:19.597542 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3653 12:16:19.600646 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3654 12:16:19.603812 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3655 12:16:19.610967 iDelay=195, Bit 9, Center 104 (43 ~ 166) 124
3656 12:16:19.613903 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3657 12:16:19.617020 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3658 12:16:19.620607 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3659 12:16:19.623672 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3660 12:16:19.630539 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3661 12:16:19.633192 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3662 12:16:19.633609 ==
3663 12:16:19.636700 Dram Type= 6, Freq= 0, CH_1, rank 1
3664 12:16:19.640041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3665 12:16:19.640503 ==
3666 12:16:19.643534 DQS Delay:
3667 12:16:19.644048 DQS0 = 0, DQS1 = 0
3668 12:16:19.646651 DQM Delay:
3669 12:16:19.647175 DQM0 = 115, DQM1 = 112
3670 12:16:19.647636 DQ Delay:
3671 12:16:19.650852 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =114
3672 12:16:19.656693 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3673 12:16:19.659946 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3674 12:16:19.663549 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =122
3675 12:16:19.664103
3676 12:16:19.664461
3677 12:16:19.669400 [DQSOSCAuto] RK1, (LSB)MR18= 0xf608, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
3678 12:16:19.673023 CH1 RK1: MR19=304, MR18=F608
3679 12:16:19.679788 CH1_RK1: MR19=0x304, MR18=0xF608, DQSOSC=406, MR23=63, INC=39, DEC=26
3680 12:16:19.682813 [RxdqsGatingPostProcess] freq 1200
3681 12:16:19.689420 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3682 12:16:19.692713 best DQS0 dly(2T, 0.5T) = (0, 11)
3683 12:16:19.696059 best DQS1 dly(2T, 0.5T) = (0, 11)
3684 12:16:19.696482 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3685 12:16:19.698882 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3686 12:16:19.702675 best DQS0 dly(2T, 0.5T) = (0, 11)
3687 12:16:19.706825 best DQS1 dly(2T, 0.5T) = (0, 11)
3688 12:16:19.709043 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3689 12:16:19.712589 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3690 12:16:19.715552 Pre-setting of DQS Precalculation
3691 12:16:19.722097 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3692 12:16:19.729820 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3693 12:16:19.735440 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3694 12:16:19.736013
3695 12:16:19.736381
3696 12:16:19.739033 [Calibration Summary] 2400 Mbps
3697 12:16:19.739645 CH 0, Rank 0
3698 12:16:19.743423 SW Impedance : PASS
3699 12:16:19.745627 DUTY Scan : NO K
3700 12:16:19.746257 ZQ Calibration : PASS
3701 12:16:19.749744 Jitter Meter : NO K
3702 12:16:19.751997 CBT Training : PASS
3703 12:16:19.752457 Write leveling : PASS
3704 12:16:19.755466 RX DQS gating : PASS
3705 12:16:19.759168 RX DQ/DQS(RDDQC) : PASS
3706 12:16:19.759776 TX DQ/DQS : PASS
3707 12:16:19.762756 RX DATLAT : PASS
3708 12:16:19.765354 RX DQ/DQS(Engine): PASS
3709 12:16:19.765913 TX OE : NO K
3710 12:16:19.768353 All Pass.
3711 12:16:19.768876
3712 12:16:19.769239 CH 0, Rank 1
3713 12:16:19.772326 SW Impedance : PASS
3714 12:16:19.772889 DUTY Scan : NO K
3715 12:16:19.775762 ZQ Calibration : PASS
3716 12:16:19.778882 Jitter Meter : NO K
3717 12:16:19.779527 CBT Training : PASS
3718 12:16:19.782255 Write leveling : PASS
3719 12:16:19.785179 RX DQS gating : PASS
3720 12:16:19.785650 RX DQ/DQS(RDDQC) : PASS
3721 12:16:19.788333 TX DQ/DQS : PASS
3722 12:16:19.792213 RX DATLAT : PASS
3723 12:16:19.792765 RX DQ/DQS(Engine): PASS
3724 12:16:19.795632 TX OE : NO K
3725 12:16:19.796188 All Pass.
3726 12:16:19.796635
3727 12:16:19.798145 CH 1, Rank 0
3728 12:16:19.798598 SW Impedance : PASS
3729 12:16:19.801459 DUTY Scan : NO K
3730 12:16:19.801917 ZQ Calibration : PASS
3731 12:16:19.805126 Jitter Meter : NO K
3732 12:16:19.808349 CBT Training : PASS
3733 12:16:19.808955 Write leveling : PASS
3734 12:16:19.811631 RX DQS gating : PASS
3735 12:16:19.814737 RX DQ/DQS(RDDQC) : PASS
3736 12:16:19.815154 TX DQ/DQS : PASS
3737 12:16:19.818156 RX DATLAT : PASS
3738 12:16:19.821438 RX DQ/DQS(Engine): PASS
3739 12:16:19.821894 TX OE : NO K
3740 12:16:19.825155 All Pass.
3741 12:16:19.825716
3742 12:16:19.826079 CH 1, Rank 1
3743 12:16:19.827912 SW Impedance : PASS
3744 12:16:19.828370 DUTY Scan : NO K
3745 12:16:19.831139 ZQ Calibration : PASS
3746 12:16:19.834344 Jitter Meter : NO K
3747 12:16:19.834763 CBT Training : PASS
3748 12:16:19.838113 Write leveling : PASS
3749 12:16:19.842768 RX DQS gating : PASS
3750 12:16:19.843293 RX DQ/DQS(RDDQC) : PASS
3751 12:16:19.844068 TX DQ/DQS : PASS
3752 12:16:19.848182 RX DATLAT : PASS
3753 12:16:19.848748 RX DQ/DQS(Engine): PASS
3754 12:16:19.851154 TX OE : NO K
3755 12:16:19.851780 All Pass.
3756 12:16:19.852156
3757 12:16:19.854473 DramC Write-DBI off
3758 12:16:19.857917 PER_BANK_REFRESH: Hybrid Mode
3759 12:16:19.858492 TX_TRACKING: ON
3760 12:16:19.867959 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3761 12:16:19.871357 [FAST_K] Save calibration result to emmc
3762 12:16:19.874810 dramc_set_vcore_voltage set vcore to 650000
3763 12:16:19.877510 Read voltage for 600, 5
3764 12:16:19.877972 Vio18 = 0
3765 12:16:19.878335 Vcore = 650000
3766 12:16:19.881511 Vdram = 0
3767 12:16:19.882074 Vddq = 0
3768 12:16:19.882439 Vmddr = 0
3769 12:16:19.889002 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3770 12:16:19.890446 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3771 12:16:19.894215 MEM_TYPE=3, freq_sel=19
3772 12:16:19.897427 sv_algorithm_assistance_LP4_1600
3773 12:16:19.901143 ============ PULL DRAM RESETB DOWN ============
3774 12:16:19.903613 ========== PULL DRAM RESETB DOWN end =========
3775 12:16:19.910277 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3776 12:16:19.914339 ===================================
3777 12:16:19.917350 LPDDR4 DRAM CONFIGURATION
3778 12:16:19.920605 ===================================
3779 12:16:19.921186 EX_ROW_EN[0] = 0x0
3780 12:16:19.924592 EX_ROW_EN[1] = 0x0
3781 12:16:19.925047 LP4Y_EN = 0x0
3782 12:16:19.926952 WORK_FSP = 0x0
3783 12:16:19.927395 WL = 0x2
3784 12:16:19.930034 RL = 0x2
3785 12:16:19.930452 BL = 0x2
3786 12:16:19.933241 RPST = 0x0
3787 12:16:19.933658 RD_PRE = 0x0
3788 12:16:19.937226 WR_PRE = 0x1
3789 12:16:19.937642 WR_PST = 0x0
3790 12:16:19.940277 DBI_WR = 0x0
3791 12:16:19.943525 DBI_RD = 0x0
3792 12:16:19.944055 OTF = 0x1
3793 12:16:19.946905 ===================================
3794 12:16:19.950125 ===================================
3795 12:16:19.950660 ANA top config
3796 12:16:19.953501 ===================================
3797 12:16:19.956979 DLL_ASYNC_EN = 0
3798 12:16:19.959562 ALL_SLAVE_EN = 1
3799 12:16:19.962979 NEW_RANK_MODE = 1
3800 12:16:19.966627 DLL_IDLE_MODE = 1
3801 12:16:19.967152 LP45_APHY_COMB_EN = 1
3802 12:16:19.969712 TX_ODT_DIS = 1
3803 12:16:19.973800 NEW_8X_MODE = 1
3804 12:16:19.977147 ===================================
3805 12:16:19.979479 ===================================
3806 12:16:19.982788 data_rate = 1200
3807 12:16:19.985855 CKR = 1
3808 12:16:19.989087 DQ_P2S_RATIO = 8
3809 12:16:19.992740 ===================================
3810 12:16:19.993271 CA_P2S_RATIO = 8
3811 12:16:19.995611 DQ_CA_OPEN = 0
3812 12:16:19.999823 DQ_SEMI_OPEN = 0
3813 12:16:20.003002 CA_SEMI_OPEN = 0
3814 12:16:20.006395 CA_FULL_RATE = 0
3815 12:16:20.008798 DQ_CKDIV4_EN = 1
3816 12:16:20.009261 CA_CKDIV4_EN = 1
3817 12:16:20.012870 CA_PREDIV_EN = 0
3818 12:16:20.015791 PH8_DLY = 0
3819 12:16:20.019034 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3820 12:16:20.022561 DQ_AAMCK_DIV = 4
3821 12:16:20.025226 CA_AAMCK_DIV = 4
3822 12:16:20.028443 CA_ADMCK_DIV = 4
3823 12:16:20.028862 DQ_TRACK_CA_EN = 0
3824 12:16:20.031834 CA_PICK = 600
3825 12:16:20.035226 CA_MCKIO = 600
3826 12:16:20.038574 MCKIO_SEMI = 0
3827 12:16:20.041533 PLL_FREQ = 2288
3828 12:16:20.045238 DQ_UI_PI_RATIO = 32
3829 12:16:20.048218 CA_UI_PI_RATIO = 0
3830 12:16:20.051855 ===================================
3831 12:16:20.054995 ===================================
3832 12:16:20.055565 memory_type:LPDDR4
3833 12:16:20.058086 GP_NUM : 10
3834 12:16:20.061347 SRAM_EN : 1
3835 12:16:20.061881 MD32_EN : 0
3836 12:16:20.065315 ===================================
3837 12:16:20.067957 [ANA_INIT] >>>>>>>>>>>>>>
3838 12:16:20.071977 <<<<<< [CONFIGURE PHASE]: ANA_TX
3839 12:16:20.074589 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3840 12:16:20.078152 ===================================
3841 12:16:20.082119 data_rate = 1200,PCW = 0X5800
3842 12:16:20.084158 ===================================
3843 12:16:20.088071 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3844 12:16:20.091066 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3845 12:16:20.097538 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3846 12:16:20.100907 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3847 12:16:20.107343 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3848 12:16:20.110312 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3849 12:16:20.110731 [ANA_INIT] flow start
3850 12:16:20.114302 [ANA_INIT] PLL >>>>>>>>
3851 12:16:20.117505 [ANA_INIT] PLL <<<<<<<<
3852 12:16:20.118038 [ANA_INIT] MIDPI >>>>>>>>
3853 12:16:20.121095 [ANA_INIT] MIDPI <<<<<<<<
3854 12:16:20.123866 [ANA_INIT] DLL >>>>>>>>
3855 12:16:20.124489 [ANA_INIT] flow end
3856 12:16:20.127099 ============ LP4 DIFF to SE enter ============
3857 12:16:20.133934 ============ LP4 DIFF to SE exit ============
3858 12:16:20.134466 [ANA_INIT] <<<<<<<<<<<<<
3859 12:16:20.137353 [Flow] Enable top DCM control >>>>>
3860 12:16:20.140675 [Flow] Enable top DCM control <<<<<
3861 12:16:20.143699 Enable DLL master slave shuffle
3862 12:16:20.150746 ==============================================================
3863 12:16:20.153483 Gating Mode config
3864 12:16:20.157408 ==============================================================
3865 12:16:20.160337 Config description:
3866 12:16:20.169912 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3867 12:16:20.176600 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3868 12:16:20.179759 SELPH_MODE 0: By rank 1: By Phase
3869 12:16:20.186489 ==============================================================
3870 12:16:20.189672 GAT_TRACK_EN = 1
3871 12:16:20.193545 RX_GATING_MODE = 2
3872 12:16:20.196417 RX_GATING_TRACK_MODE = 2
3873 12:16:20.200635 SELPH_MODE = 1
3874 12:16:20.201169 PICG_EARLY_EN = 1
3875 12:16:20.203183 VALID_LAT_VALUE = 1
3876 12:16:20.209531 ==============================================================
3877 12:16:20.212775 Enter into Gating configuration >>>>
3878 12:16:20.215990 Exit from Gating configuration <<<<
3879 12:16:20.219619 Enter into DVFS_PRE_config >>>>>
3880 12:16:20.229248 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3881 12:16:20.233899 Exit from DVFS_PRE_config <<<<<
3882 12:16:20.235856 Enter into PICG configuration >>>>
3883 12:16:20.239503 Exit from PICG configuration <<<<
3884 12:16:20.242658 [RX_INPUT] configuration >>>>>
3885 12:16:20.245552 [RX_INPUT] configuration <<<<<
3886 12:16:20.252101 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3887 12:16:20.255749 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3888 12:16:20.262179 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3889 12:16:20.269021 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3890 12:16:20.275194 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3891 12:16:20.281993 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3892 12:16:20.284901 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3893 12:16:20.288273 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3894 12:16:20.291672 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3895 12:16:20.298359 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3896 12:16:20.301598 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3897 12:16:20.304730 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3898 12:16:20.308329 ===================================
3899 12:16:20.311202 LPDDR4 DRAM CONFIGURATION
3900 12:16:20.315309 ===================================
3901 12:16:20.317922 EX_ROW_EN[0] = 0x0
3902 12:16:20.318451 EX_ROW_EN[1] = 0x0
3903 12:16:20.321675 LP4Y_EN = 0x0
3904 12:16:20.322203 WORK_FSP = 0x0
3905 12:16:20.324827 WL = 0x2
3906 12:16:20.325318 RL = 0x2
3907 12:16:20.327770 BL = 0x2
3908 12:16:20.328190 RPST = 0x0
3909 12:16:20.331749 RD_PRE = 0x0
3910 12:16:20.332278 WR_PRE = 0x1
3911 12:16:20.333969 WR_PST = 0x0
3912 12:16:20.337524 DBI_WR = 0x0
3913 12:16:20.338075 DBI_RD = 0x0
3914 12:16:20.342264 OTF = 0x1
3915 12:16:20.343781 ===================================
3916 12:16:20.347327 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3917 12:16:20.350691 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3918 12:16:20.353701 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3919 12:16:20.357637 ===================================
3920 12:16:20.361000 LPDDR4 DRAM CONFIGURATION
3921 12:16:20.364045 ===================================
3922 12:16:20.367163 EX_ROW_EN[0] = 0x10
3923 12:16:20.367716 EX_ROW_EN[1] = 0x0
3924 12:16:20.370535 LP4Y_EN = 0x0
3925 12:16:20.370949 WORK_FSP = 0x0
3926 12:16:20.373449 WL = 0x2
3927 12:16:20.373816 RL = 0x2
3928 12:16:20.377329 BL = 0x2
3929 12:16:20.377847 RPST = 0x0
3930 12:16:20.380104 RD_PRE = 0x0
3931 12:16:20.383818 WR_PRE = 0x1
3932 12:16:20.384342 WR_PST = 0x0
3933 12:16:20.387058 DBI_WR = 0x0
3934 12:16:20.387624 DBI_RD = 0x0
3935 12:16:20.390294 OTF = 0x1
3936 12:16:20.393487 ===================================
3937 12:16:20.397043 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3938 12:16:20.403237 nWR fixed to 30
3939 12:16:20.405250 [ModeRegInit_LP4] CH0 RK0
3940 12:16:20.405668 [ModeRegInit_LP4] CH0 RK1
3941 12:16:20.409138 [ModeRegInit_LP4] CH1 RK0
3942 12:16:20.412086 [ModeRegInit_LP4] CH1 RK1
3943 12:16:20.412612 match AC timing 17
3944 12:16:20.418741 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3945 12:16:20.422296 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3946 12:16:20.425267 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3947 12:16:20.432619 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3948 12:16:20.435557 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3949 12:16:20.435980 ==
3950 12:16:20.438178 Dram Type= 6, Freq= 0, CH_0, rank 0
3951 12:16:20.441548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3952 12:16:20.444899 ==
3953 12:16:20.448653 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3954 12:16:20.454466 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3955 12:16:20.458320 [CA 0] Center 36 (6~67) winsize 62
3956 12:16:20.461676 [CA 1] Center 36 (5~67) winsize 63
3957 12:16:20.464676 [CA 2] Center 34 (4~65) winsize 62
3958 12:16:20.468300 [CA 3] Center 34 (4~65) winsize 62
3959 12:16:20.470944 [CA 4] Center 33 (3~64) winsize 62
3960 12:16:20.474313 [CA 5] Center 33 (3~64) winsize 62
3961 12:16:20.474848
3962 12:16:20.478267 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3963 12:16:20.478840
3964 12:16:20.480808 [CATrainingPosCal] consider 1 rank data
3965 12:16:20.484089 u2DelayCellTimex100 = 270/100 ps
3966 12:16:20.487567 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3967 12:16:20.490875 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3968 12:16:20.497469 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3969 12:16:20.500901 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3970 12:16:20.504306 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3971 12:16:20.507226 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3972 12:16:20.507672
3973 12:16:20.510275 CA PerBit enable=1, Macro0, CA PI delay=33
3974 12:16:20.510696
3975 12:16:20.513967 [CBTSetCACLKResult] CA Dly = 33
3976 12:16:20.514497 CS Dly: 5 (0~36)
3977 12:16:20.517167 ==
3978 12:16:20.520442 Dram Type= 6, Freq= 0, CH_0, rank 1
3979 12:16:20.523729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 12:16:20.524250 ==
3981 12:16:20.530525 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3982 12:16:20.533695 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3983 12:16:20.537324 [CA 0] Center 36 (6~67) winsize 62
3984 12:16:20.540465 [CA 1] Center 36 (6~67) winsize 62
3985 12:16:20.544255 [CA 2] Center 34 (4~65) winsize 62
3986 12:16:20.547811 [CA 3] Center 34 (4~65) winsize 62
3987 12:16:20.550509 [CA 4] Center 34 (4~64) winsize 61
3988 12:16:20.553846 [CA 5] Center 33 (3~64) winsize 62
3989 12:16:20.554262
3990 12:16:20.557771 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3991 12:16:20.558317
3992 12:16:20.560310 [CATrainingPosCal] consider 2 rank data
3993 12:16:20.563737 u2DelayCellTimex100 = 270/100 ps
3994 12:16:39.232121 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3995 12:16:39.232634 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3996 12:16:39.233000 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3997 12:16:39.233338 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3998 12:16:39.233661 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3999 12:16:39.233978 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4000 12:16:39.234289
4001 12:16:39.234595 CA PerBit enable=1, Macro0, CA PI delay=33
4002 12:16:39.234900
4003 12:16:39.235200 [CBTSetCACLKResult] CA Dly = 33
4004 12:16:39.235611 CS Dly: 5 (0~37)
4005 12:16:39.235932
4006 12:16:39.236234 ----->DramcWriteLeveling(PI) begin...
4007 12:16:39.236542 ==
4008 12:16:39.236845 Dram Type= 6, Freq= 0, CH_0, rank 0
4009 12:16:39.237162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4010 12:16:39.237461 ==
4011 12:16:39.237670 Write leveling (Byte 0): 32 => 32
4012 12:16:39.237721 Write leveling (Byte 1): 28 => 28
4013 12:16:39.237773 DramcWriteLeveling(PI) end<-----
4014 12:16:39.237824
4015 12:16:39.237875 ==
4016 12:16:39.237935 Dram Type= 6, Freq= 0, CH_0, rank 0
4017 12:16:39.237989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 12:16:39.238057 ==
4019 12:16:39.238109 [Gating] SW mode calibration
4020 12:16:39.238175 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4021 12:16:39.238228 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4022 12:16:39.238279 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4023 12:16:39.238330 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4024 12:16:39.238382 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4025 12:16:39.238433 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
4026 12:16:39.238484 0 9 16 | B1->B0 | 2f2f 2525 | 0 0 | (0 1) (0 0)
4027 12:16:39.238536 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 12:16:39.238587 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 12:16:39.238638 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 12:16:39.238689 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 12:16:39.238740 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 12:16:39.238792 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 12:16:39.238842 0 10 12 | B1->B0 | 2727 2e2e | 1 1 | (0 0) (0 0)
4034 12:16:39.238893 0 10 16 | B1->B0 | 3d3d 4545 | 0 0 | (0 0) (0 0)
4035 12:16:39.238944 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 12:16:39.238995 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 12:16:39.239046 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 12:16:39.239097 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 12:16:39.239147 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 12:16:39.239212 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 12:16:39.239268 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4042 12:16:39.239319 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4043 12:16:39.239399 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 12:16:39.239478 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 12:16:39.239529 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 12:16:39.239580 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 12:16:39.239631 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 12:16:39.239682 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 12:16:39.239733 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 12:16:39.239784 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 12:16:39.239834 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 12:16:39.239885 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 12:16:39.239936 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 12:16:39.239987 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 12:16:39.240038 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 12:16:39.240089 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 12:16:39.240139 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 12:16:39.240190 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4059 12:16:39.240241 Total UI for P1: 0, mck2ui 16
4060 12:16:39.240292 best dqsien dly found for B0: ( 0, 13, 14)
4061 12:16:39.240344 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 12:16:39.240395 Total UI for P1: 0, mck2ui 16
4063 12:16:39.240446 best dqsien dly found for B1: ( 0, 13, 18)
4064 12:16:39.240497 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4065 12:16:39.240548 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4066 12:16:39.240599
4067 12:16:39.240649 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4068 12:16:39.240701 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4069 12:16:39.240752 [Gating] SW calibration Done
4070 12:16:39.240802 ==
4071 12:16:39.240853 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 12:16:39.240904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 12:16:39.240955 ==
4074 12:16:39.241006 RX Vref Scan: 0
4075 12:16:39.241057
4076 12:16:39.241107 RX Vref 0 -> 0, step: 1
4077 12:16:39.241157
4078 12:16:39.241208 RX Delay -230 -> 252, step: 16
4079 12:16:39.241259 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4080 12:16:39.241310 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4081 12:16:39.241360 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4082 12:16:39.241410 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4083 12:16:39.241461 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4084 12:16:39.241512 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4085 12:16:39.241563 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4086 12:16:39.241613 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4087 12:16:39.241664 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4088 12:16:39.241715 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4089 12:16:39.241765 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4090 12:16:39.241816 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4091 12:16:39.241866 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4092 12:16:39.241917 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4093 12:16:39.241968 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4094 12:16:39.242019 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4095 12:16:39.242070 ==
4096 12:16:39.242326 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 12:16:39.242384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 12:16:39.242462 ==
4099 12:16:39.242544 DQS Delay:
4100 12:16:39.242627 DQS0 = 0, DQS1 = 0
4101 12:16:39.242680 DQM Delay:
4102 12:16:39.242733 DQM0 = 40, DQM1 = 33
4103 12:16:39.242785 DQ Delay:
4104 12:16:39.242838 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4105 12:16:39.242904 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4106 12:16:39.242955 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4107 12:16:39.243006 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4108 12:16:39.243057
4109 12:16:39.243108
4110 12:16:39.243159 ==
4111 12:16:39.243210 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 12:16:39.243262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 12:16:39.243315 ==
4114 12:16:39.243392
4115 12:16:39.243471
4116 12:16:39.243553 TX Vref Scan disable
4117 12:16:39.243605 == TX Byte 0 ==
4118 12:16:39.243656 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4119 12:16:39.243708 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4120 12:16:39.243760 == TX Byte 1 ==
4121 12:16:39.243812 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4122 12:16:39.243863 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4123 12:16:39.243914 ==
4124 12:16:39.243966 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 12:16:39.244018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 12:16:39.244070 ==
4127 12:16:39.244121
4128 12:16:39.244172
4129 12:16:39.244223 TX Vref Scan disable
4130 12:16:39.244275 == TX Byte 0 ==
4131 12:16:39.244326 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4132 12:16:39.244378 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4133 12:16:39.244429 == TX Byte 1 ==
4134 12:16:39.244481 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4135 12:16:39.244532 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4136 12:16:39.244583
4137 12:16:39.244635 [DATLAT]
4138 12:16:39.244686 Freq=600, CH0 RK0
4139 12:16:39.244737
4140 12:16:39.244788 DATLAT Default: 0x9
4141 12:16:39.244840 0, 0xFFFF, sum = 0
4142 12:16:39.244893 1, 0xFFFF, sum = 0
4143 12:16:39.244946 2, 0xFFFF, sum = 0
4144 12:16:39.244998 3, 0xFFFF, sum = 0
4145 12:16:39.245050 4, 0xFFFF, sum = 0
4146 12:16:39.245102 5, 0xFFFF, sum = 0
4147 12:16:39.245154 6, 0xFFFF, sum = 0
4148 12:16:39.245206 7, 0xFFFF, sum = 0
4149 12:16:39.245259 8, 0x0, sum = 1
4150 12:16:39.245311 9, 0x0, sum = 2
4151 12:16:39.245363 10, 0x0, sum = 3
4152 12:16:39.245415 11, 0x0, sum = 4
4153 12:16:39.245467 best_step = 9
4154 12:16:39.245519
4155 12:16:39.245569 ==
4156 12:16:39.245620 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 12:16:39.245672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 12:16:39.245724 ==
4159 12:16:39.245775 RX Vref Scan: 1
4160 12:16:39.245827
4161 12:16:39.245878 RX Vref 0 -> 0, step: 1
4162 12:16:39.245929
4163 12:16:39.245980 RX Delay -195 -> 252, step: 8
4164 12:16:39.246032
4165 12:16:39.246083 Set Vref, RX VrefLevel [Byte0]: 53
4166 12:16:39.246135 [Byte1]: 59
4167 12:16:39.246186
4168 12:16:39.246237 Final RX Vref Byte 0 = 53 to rank0
4169 12:16:39.246289 Final RX Vref Byte 1 = 59 to rank0
4170 12:16:39.246341 Final RX Vref Byte 0 = 53 to rank1
4171 12:16:39.246392 Final RX Vref Byte 1 = 59 to rank1==
4172 12:16:39.246471 Dram Type= 6, Freq= 0, CH_0, rank 0
4173 12:16:39.246523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 12:16:39.246575 ==
4175 12:16:39.246626 DQS Delay:
4176 12:16:39.246677 DQS0 = 0, DQS1 = 0
4177 12:16:39.246728 DQM Delay:
4178 12:16:39.246779 DQM0 = 41, DQM1 = 33
4179 12:16:39.246831 DQ Delay:
4180 12:16:39.246882 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =36
4181 12:16:39.246933 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =44
4182 12:16:39.246984 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4183 12:16:39.247036 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4184 12:16:39.247087
4185 12:16:39.247138
4186 12:16:39.247189 [DQSOSCAuto] RK0, (LSB)MR18= 0x4239, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
4187 12:16:39.247243 CH0 RK0: MR19=808, MR18=4239
4188 12:16:39.247294 CH0_RK0: MR19=0x808, MR18=0x4239, DQSOSC=397, MR23=63, INC=166, DEC=110
4189 12:16:39.247346
4190 12:16:39.247426 ----->DramcWriteLeveling(PI) begin...
4191 12:16:39.247506 ==
4192 12:16:39.247558 Dram Type= 6, Freq= 0, CH_0, rank 1
4193 12:16:39.247609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 12:16:39.247661 ==
4195 12:16:39.247713 Write leveling (Byte 0): 34 => 34
4196 12:16:39.247764 Write leveling (Byte 1): 30 => 30
4197 12:16:39.247816 DramcWriteLeveling(PI) end<-----
4198 12:16:39.247867
4199 12:16:39.247919 ==
4200 12:16:39.247970 Dram Type= 6, Freq= 0, CH_0, rank 1
4201 12:16:39.248022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 12:16:39.248074 ==
4203 12:16:39.248125 [Gating] SW mode calibration
4204 12:16:39.248178 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4205 12:16:39.248230 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4206 12:16:39.248282 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4207 12:16:39.248335 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4208 12:16:39.248387 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4209 12:16:39.248438 0 9 12 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
4210 12:16:39.248490 0 9 16 | B1->B0 | 2f2f 2626 | 0 0 | (1 1) (0 0)
4211 12:16:39.248542 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 12:16:39.248594 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 12:16:39.248645 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 12:16:39.248698 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 12:16:39.248749 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 12:16:39.248800 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 12:16:39.248852 0 10 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
4218 12:16:39.248903 0 10 16 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
4219 12:16:39.248954 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 12:16:39.249006 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 12:16:39.249057 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 12:16:39.249109 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 12:16:39.249160 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 12:16:39.249212 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 12:16:39.249263 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 12:16:39.249314 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 12:16:39.249366 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 12:16:39.249417 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 12:16:39.249469 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 12:16:39.249520 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 12:16:39.249571 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 12:16:39.249811 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 12:16:39.249922 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 12:16:39.249975 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 12:16:39.250028 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 12:16:39.250081 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 12:16:39.250134 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 12:16:39.250186 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 12:16:39.250238 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 12:16:39.250291 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4241 12:16:39.250343 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4242 12:16:39.250408 Total UI for P1: 0, mck2ui 16
4243 12:16:39.250460 best dqsien dly found for B0: ( 0, 13, 8)
4244 12:16:39.250512 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 12:16:39.250564 Total UI for P1: 0, mck2ui 16
4246 12:16:39.250616 best dqsien dly found for B1: ( 0, 13, 14)
4247 12:16:39.250667 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4248 12:16:39.250719 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4249 12:16:39.250770
4250 12:16:39.250821 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4251 12:16:39.250873 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4252 12:16:39.250924 [Gating] SW calibration Done
4253 12:16:39.250976 ==
4254 12:16:39.251028 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 12:16:39.251079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 12:16:39.251131 ==
4257 12:16:39.251182 RX Vref Scan: 0
4258 12:16:39.251233
4259 12:16:39.251284 RX Vref 0 -> 0, step: 1
4260 12:16:39.251335
4261 12:16:39.251444 RX Delay -230 -> 252, step: 16
4262 12:16:39.251497 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4263 12:16:39.251549 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4264 12:16:39.251600 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4265 12:16:39.251652 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4266 12:16:39.251703 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4267 12:16:39.251754 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4268 12:16:39.251805 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4269 12:16:39.251857 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4270 12:16:39.251908 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4271 12:16:39.251959 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4272 12:16:39.252010 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4273 12:16:39.252061 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4274 12:16:39.252129 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4275 12:16:39.252202 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4276 12:16:39.252253 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4277 12:16:39.252305 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4278 12:16:39.252356 ==
4279 12:16:39.252408 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 12:16:39.252459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 12:16:39.252511 ==
4282 12:16:39.252562 DQS Delay:
4283 12:16:39.252613 DQS0 = 0, DQS1 = 0
4284 12:16:39.252665 DQM Delay:
4285 12:16:39.252716 DQM0 = 40, DQM1 = 31
4286 12:16:39.252767 DQ Delay:
4287 12:16:39.252838 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4288 12:16:39.252891 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4289 12:16:39.252942 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4290 12:16:39.252994 DQ12 =41, DQ13 =33, DQ14 =41, DQ15 =41
4291 12:16:39.253046
4292 12:16:39.253097
4293 12:16:39.253148 ==
4294 12:16:39.253200 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 12:16:39.253252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 12:16:39.253304 ==
4297 12:16:39.253356
4298 12:16:39.253407
4299 12:16:39.253458 TX Vref Scan disable
4300 12:16:39.253509 == TX Byte 0 ==
4301 12:16:39.253561 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4302 12:16:39.253613 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4303 12:16:39.253664 == TX Byte 1 ==
4304 12:16:39.253716 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4305 12:16:39.253768 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4306 12:16:39.253819 ==
4307 12:16:39.253870 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 12:16:39.253922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 12:16:39.253974 ==
4310 12:16:39.254025
4311 12:16:39.254076
4312 12:16:39.254127 TX Vref Scan disable
4313 12:16:39.254178 == TX Byte 0 ==
4314 12:16:39.254230 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4315 12:16:39.254281 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4316 12:16:39.254333 == TX Byte 1 ==
4317 12:16:39.254384 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4318 12:16:39.254436 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4319 12:16:39.254487
4320 12:16:39.254537 [DATLAT]
4321 12:16:39.254589 Freq=600, CH0 RK1
4322 12:16:39.254640
4323 12:16:39.254691 DATLAT Default: 0x9
4324 12:16:39.254742 0, 0xFFFF, sum = 0
4325 12:16:39.254795 1, 0xFFFF, sum = 0
4326 12:16:39.254867 2, 0xFFFF, sum = 0
4327 12:16:39.254922 3, 0xFFFF, sum = 0
4328 12:16:39.254975 4, 0xFFFF, sum = 0
4329 12:16:39.255027 5, 0xFFFF, sum = 0
4330 12:16:39.255079 6, 0xFFFF, sum = 0
4331 12:16:39.255131 7, 0xFFFF, sum = 0
4332 12:16:39.255183 8, 0x0, sum = 1
4333 12:16:39.255236 9, 0x0, sum = 2
4334 12:16:39.255288 10, 0x0, sum = 3
4335 12:16:39.255340 11, 0x0, sum = 4
4336 12:16:39.255424 best_step = 9
4337 12:16:39.255503
4338 12:16:39.255554 ==
4339 12:16:39.255606 Dram Type= 6, Freq= 0, CH_0, rank 1
4340 12:16:39.255658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 12:16:39.255709 ==
4342 12:16:39.255761 RX Vref Scan: 0
4343 12:16:39.255812
4344 12:16:39.255863 RX Vref 0 -> 0, step: 1
4345 12:16:39.255914
4346 12:16:39.255965 RX Delay -195 -> 252, step: 8
4347 12:16:39.256017 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4348 12:16:39.256068 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4349 12:16:39.256120 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4350 12:16:39.256171 iDelay=197, Bit 3, Center 40 (-107 ~ 188) 296
4351 12:16:39.256223 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4352 12:16:39.256274 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4353 12:16:39.256326 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4354 12:16:39.256377 iDelay=197, Bit 7, Center 48 (-99 ~ 196) 296
4355 12:16:39.256428 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4356 12:16:39.256479 iDelay=197, Bit 9, Center 16 (-139 ~ 172) 312
4357 12:16:39.256531 iDelay=197, Bit 10, Center 36 (-123 ~ 196) 320
4358 12:16:39.256582 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4359 12:16:39.256634 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4360 12:16:39.256685 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4361 12:16:39.256736 iDelay=197, Bit 14, Center 44 (-107 ~ 196) 304
4362 12:16:39.256787 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4363 12:16:39.256848 ==
4364 12:16:39.257183 Dram Type= 6, Freq= 0, CH_0, rank 1
4365 12:16:39.257264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 12:16:39.257319 ==
4367 12:16:39.257373 DQS Delay:
4368 12:16:39.257425 DQS0 = 0, DQS1 = 0
4369 12:16:39.257478 DQM Delay:
4370 12:16:39.257531 DQM0 = 41, DQM1 = 33
4371 12:16:39.257583 DQ Delay:
4372 12:16:39.257636 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4373 12:16:39.257700 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =48
4374 12:16:39.257752 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4375 12:16:39.257802 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4376 12:16:39.257854
4377 12:16:39.257904
4378 12:16:39.257955 [DQSOSCAuto] RK1, (LSB)MR18= 0x4440, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4379 12:16:39.258007 CH0 RK1: MR19=808, MR18=4440
4380 12:16:39.258059 CH0_RK1: MR19=0x808, MR18=0x4440, DQSOSC=396, MR23=63, INC=167, DEC=111
4381 12:16:39.258111 [RxdqsGatingPostProcess] freq 600
4382 12:16:39.258162 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4383 12:16:39.258214 Pre-setting of DQS Precalculation
4384 12:16:39.258265 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4385 12:16:39.258316 ==
4386 12:16:39.258367 Dram Type= 6, Freq= 0, CH_1, rank 0
4387 12:16:39.258418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 12:16:39.258469 ==
4389 12:16:39.258520 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4390 12:16:39.258571 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4391 12:16:39.258622 [CA 0] Center 36 (6~66) winsize 61
4392 12:16:39.258689 [CA 1] Center 36 (6~66) winsize 61
4393 12:16:39.258757 [CA 2] Center 34 (4~65) winsize 62
4394 12:16:39.258808 [CA 3] Center 34 (3~65) winsize 63
4395 12:16:39.258858 [CA 4] Center 34 (4~65) winsize 62
4396 12:16:39.258909 [CA 5] Center 33 (3~64) winsize 62
4397 12:16:39.258960
4398 12:16:39.259011 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4399 12:16:39.259062
4400 12:16:39.259114 [CATrainingPosCal] consider 1 rank data
4401 12:16:39.259166 u2DelayCellTimex100 = 270/100 ps
4402 12:16:39.259216 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4403 12:16:39.259268 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4404 12:16:39.259318 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4405 12:16:39.259400 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4406 12:16:39.259479 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4407 12:16:39.259530 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4408 12:16:39.259581
4409 12:16:39.259632 CA PerBit enable=1, Macro0, CA PI delay=33
4410 12:16:39.259683
4411 12:16:39.259734 [CBTSetCACLKResult] CA Dly = 33
4412 12:16:39.259785 CS Dly: 4 (0~35)
4413 12:16:39.259836 ==
4414 12:16:39.259887 Dram Type= 6, Freq= 0, CH_1, rank 1
4415 12:16:39.259938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 12:16:39.259990 ==
4417 12:16:39.260041 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4418 12:16:39.260092 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4419 12:16:39.260143 [CA 0] Center 35 (5~66) winsize 62
4420 12:16:39.260194 [CA 1] Center 36 (6~66) winsize 61
4421 12:16:39.260245 [CA 2] Center 34 (4~65) winsize 62
4422 12:16:39.260295 [CA 3] Center 33 (3~64) winsize 62
4423 12:16:39.260346 [CA 4] Center 34 (3~65) winsize 63
4424 12:16:39.260397 [CA 5] Center 33 (3~64) winsize 62
4425 12:16:39.260448
4426 12:16:39.260498 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4427 12:16:39.260550
4428 12:16:39.260601 [CATrainingPosCal] consider 2 rank data
4429 12:16:39.260652 u2DelayCellTimex100 = 270/100 ps
4430 12:16:39.260703 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4431 12:16:39.260754 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4432 12:16:39.260805 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 12:16:39.260856 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4434 12:16:39.260907 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4435 12:16:39.260997 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4436 12:16:39.261080
4437 12:16:39.261131 CA PerBit enable=1, Macro0, CA PI delay=33
4438 12:16:39.261182
4439 12:16:39.261233 [CBTSetCACLKResult] CA Dly = 33
4440 12:16:39.261285 CS Dly: 5 (0~37)
4441 12:16:39.261336
4442 12:16:39.261387 ----->DramcWriteLeveling(PI) begin...
4443 12:16:39.261439 ==
4444 12:16:39.261490 Dram Type= 6, Freq= 0, CH_1, rank 0
4445 12:16:39.261542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4446 12:16:39.261593 ==
4447 12:16:39.261644 Write leveling (Byte 0): 29 => 29
4448 12:16:39.261695 Write leveling (Byte 1): 29 => 29
4449 12:16:39.261747 DramcWriteLeveling(PI) end<-----
4450 12:16:39.261797
4451 12:16:39.261847 ==
4452 12:16:39.261898 Dram Type= 6, Freq= 0, CH_1, rank 0
4453 12:16:39.261949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 12:16:39.262000 ==
4455 12:16:39.262051 [Gating] SW mode calibration
4456 12:16:39.262102 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4457 12:16:39.262154 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4458 12:16:39.262205 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4459 12:16:39.262257 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4460 12:16:39.262309 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4461 12:16:39.262360 0 9 12 | B1->B0 | 3030 2d2d | 1 0 | (1 0) (0 1)
4462 12:16:39.262411 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4463 12:16:39.262461 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 12:16:39.262512 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 12:16:39.262563 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 12:16:39.262614 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 12:16:39.262665 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 12:16:39.262716 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4469 12:16:39.262767 0 10 12 | B1->B0 | 3232 3737 | 0 0 | (0 0) (0 0)
4470 12:16:39.262818 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 12:16:39.262870 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 12:16:39.262920 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 12:16:39.262972 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 12:16:39.263023 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 12:16:39.263074 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 12:16:39.263125 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 12:16:39.263177 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4478 12:16:39.263228 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 12:16:39.263468 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 12:16:39.263578 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 12:16:39.263632 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 12:16:39.263684 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 12:16:39.263737 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 12:16:39.263790 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 12:16:39.263842 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 12:16:39.263894 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 12:16:39.263946 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 12:16:39.264011 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 12:16:39.264062 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 12:16:39.264113 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 12:16:39.264164 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 12:16:39.264214 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 12:16:39.264265 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4494 12:16:39.264316 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 12:16:39.264367 Total UI for P1: 0, mck2ui 16
4496 12:16:39.264418 best dqsien dly found for B0: ( 0, 13, 12)
4497 12:16:39.264469 Total UI for P1: 0, mck2ui 16
4498 12:16:39.264521 best dqsien dly found for B1: ( 0, 13, 12)
4499 12:16:39.264572 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4500 12:16:39.264623 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4501 12:16:39.264674
4502 12:16:39.264726 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4503 12:16:39.264777 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4504 12:16:39.264828 [Gating] SW calibration Done
4505 12:16:39.264879 ==
4506 12:16:39.264931 Dram Type= 6, Freq= 0, CH_1, rank 0
4507 12:16:39.264982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4508 12:16:39.265034 ==
4509 12:16:39.265101 RX Vref Scan: 0
4510 12:16:39.265167
4511 12:16:39.265218 RX Vref 0 -> 0, step: 1
4512 12:16:39.265269
4513 12:16:39.265320 RX Delay -230 -> 252, step: 16
4514 12:16:39.265373 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4515 12:16:39.265425 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4516 12:16:39.265476 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4517 12:16:39.265527 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4518 12:16:39.265577 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4519 12:16:39.265628 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4520 12:16:39.265679 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4521 12:16:39.265729 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4522 12:16:39.265780 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4523 12:16:39.265830 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4524 12:16:39.265881 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4525 12:16:39.265932 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4526 12:16:39.265983 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4527 12:16:39.266034 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4528 12:16:39.266085 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4529 12:16:39.266136 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4530 12:16:39.266186 ==
4531 12:16:39.266238 Dram Type= 6, Freq= 0, CH_1, rank 0
4532 12:16:39.266290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4533 12:16:39.266341 ==
4534 12:16:39.266392 DQS Delay:
4535 12:16:39.266443 DQS0 = 0, DQS1 = 0
4536 12:16:39.266494 DQM Delay:
4537 12:16:39.266545 DQM0 = 43, DQM1 = 39
4538 12:16:39.266596 DQ Delay:
4539 12:16:39.266647 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4540 12:16:39.266698 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4541 12:16:39.266749 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4542 12:16:39.266800 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4543 12:16:39.266851
4544 12:16:39.266902
4545 12:16:39.266953 ==
4546 12:16:39.267003 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 12:16:39.267055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 12:16:39.267107 ==
4549 12:16:39.267157
4550 12:16:39.267208
4551 12:16:39.267258 TX Vref Scan disable
4552 12:16:39.267310 == TX Byte 0 ==
4553 12:16:39.267366 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4554 12:16:39.267470 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4555 12:16:39.267522 == TX Byte 1 ==
4556 12:16:39.267574 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4557 12:16:39.267626 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4558 12:16:39.267677 ==
4559 12:16:39.267729 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 12:16:39.267780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 12:16:39.267831 ==
4562 12:16:39.267882
4563 12:16:39.267932
4564 12:16:39.267983 TX Vref Scan disable
4565 12:16:39.268035 == TX Byte 0 ==
4566 12:16:39.268086 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4567 12:16:39.268138 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4568 12:16:39.268189 == TX Byte 1 ==
4569 12:16:39.268240 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4570 12:16:39.268291 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4571 12:16:39.268342
4572 12:16:39.268393 [DATLAT]
4573 12:16:39.268444 Freq=600, CH1 RK0
4574 12:16:39.268495
4575 12:16:39.268546 DATLAT Default: 0x9
4576 12:16:39.268597 0, 0xFFFF, sum = 0
4577 12:16:39.268649 1, 0xFFFF, sum = 0
4578 12:16:39.268701 2, 0xFFFF, sum = 0
4579 12:16:39.268753 3, 0xFFFF, sum = 0
4580 12:16:39.268805 4, 0xFFFF, sum = 0
4581 12:16:39.268856 5, 0xFFFF, sum = 0
4582 12:16:39.268908 6, 0xFFFF, sum = 0
4583 12:16:39.268960 7, 0xFFFF, sum = 0
4584 12:16:39.269011 8, 0x0, sum = 1
4585 12:16:39.269084 9, 0x0, sum = 2
4586 12:16:39.269171 10, 0x0, sum = 3
4587 12:16:39.269277 11, 0x0, sum = 4
4588 12:16:39.269332 best_step = 9
4589 12:16:39.269384
4590 12:16:39.269435 ==
4591 12:16:39.269486 Dram Type= 6, Freq= 0, CH_1, rank 0
4592 12:16:39.269539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 12:16:39.269590 ==
4594 12:16:39.269642 RX Vref Scan: 1
4595 12:16:39.269693
4596 12:16:39.269745 RX Vref 0 -> 0, step: 1
4597 12:16:39.269795
4598 12:16:39.269847 RX Delay -179 -> 252, step: 8
4599 12:16:39.269899
4600 12:16:39.269950 Set Vref, RX VrefLevel [Byte0]: 51
4601 12:16:39.270001 [Byte1]: 51
4602 12:16:39.270052
4603 12:16:39.270103 Final RX Vref Byte 0 = 51 to rank0
4604 12:16:39.270155 Final RX Vref Byte 1 = 51 to rank0
4605 12:16:39.270206 Final RX Vref Byte 0 = 51 to rank1
4606 12:16:39.270258 Final RX Vref Byte 1 = 51 to rank1==
4607 12:16:39.270309 Dram Type= 6, Freq= 0, CH_1, rank 0
4608 12:16:39.270360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 12:16:39.270412 ==
4610 12:16:39.270463 DQS Delay:
4611 12:16:39.270514 DQS0 = 0, DQS1 = 0
4612 12:16:39.270566 DQM Delay:
4613 12:16:39.270617 DQM0 = 42, DQM1 = 35
4614 12:16:39.270668 DQ Delay:
4615 12:16:39.270719 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4616 12:16:39.270771 DQ4 =36, DQ5 =48, DQ6 =56, DQ7 =36
4617 12:16:39.270822 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4618 12:16:39.271061 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4619 12:16:39.271171
4620 12:16:39.271238
4621 12:16:39.271289 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a44, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4622 12:16:39.271342 CH1 RK0: MR19=808, MR18=2A44
4623 12:16:39.271437 CH1_RK0: MR19=0x808, MR18=0x2A44, DQSOSC=396, MR23=63, INC=167, DEC=111
4624 12:16:39.271491
4625 12:16:39.271544 ----->DramcWriteLeveling(PI) begin...
4626 12:16:39.271610 ==
4627 12:16:39.271662 Dram Type= 6, Freq= 0, CH_1, rank 1
4628 12:16:39.271713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4629 12:16:39.271765 ==
4630 12:16:39.271816 Write leveling (Byte 0): 30 => 30
4631 12:16:39.271868 Write leveling (Byte 1): 29 => 29
4632 12:16:39.271919 DramcWriteLeveling(PI) end<-----
4633 12:16:39.272001
4634 12:16:39.272067 ==
4635 12:16:39.272122 Dram Type= 6, Freq= 0, CH_1, rank 1
4636 12:16:39.272175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4637 12:16:39.272227 ==
4638 12:16:39.272279 [Gating] SW mode calibration
4639 12:16:39.272331 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4640 12:16:39.272385 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4641 12:16:39.272437 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4642 12:16:39.272489 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4643 12:16:39.272540 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4644 12:16:39.272592 0 9 12 | B1->B0 | 3030 2d2d | 1 0 | (1 1) (0 0)
4645 12:16:39.272661 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 12:16:39.272715 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 12:16:39.272767 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 12:16:39.272819 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 12:16:39.272870 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 12:16:39.272922 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 12:16:39.272973 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4652 12:16:39.273025 0 10 12 | B1->B0 | 2f2f 3d3d | 0 0 | (0 0) (0 0)
4653 12:16:39.273116 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 12:16:39.273182 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 12:16:39.273234 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 12:16:39.273299 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 12:16:39.273350 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 12:16:39.273402 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 12:16:39.273452 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 12:16:39.273503 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4661 12:16:39.273554 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 12:16:39.273605 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 12:16:39.273656 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 12:16:39.273707 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 12:16:39.273759 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 12:16:39.273809 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 12:16:39.273861 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 12:16:39.273913 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 12:16:39.273963 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 12:16:39.274014 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 12:16:39.274065 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 12:16:39.274116 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 12:16:39.274168 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 12:16:39.274218 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 12:16:39.274269 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4676 12:16:39.274320 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4677 12:16:39.274371 Total UI for P1: 0, mck2ui 16
4678 12:16:39.274422 best dqsien dly found for B0: ( 0, 13, 8)
4679 12:16:39.274473 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 12:16:39.274524 Total UI for P1: 0, mck2ui 16
4681 12:16:39.274575 best dqsien dly found for B1: ( 0, 13, 12)
4682 12:16:39.274626 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4683 12:16:39.274677 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4684 12:16:39.274728
4685 12:16:39.274779 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4686 12:16:39.274831 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4687 12:16:39.274882 [Gating] SW calibration Done
4688 12:16:39.274934 ==
4689 12:16:39.274985 Dram Type= 6, Freq= 0, CH_1, rank 1
4690 12:16:39.275036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 12:16:39.275087 ==
4692 12:16:39.275138 RX Vref Scan: 0
4693 12:16:39.275189
4694 12:16:39.275239 RX Vref 0 -> 0, step: 1
4695 12:16:39.275290
4696 12:16:39.275341 RX Delay -230 -> 252, step: 16
4697 12:16:39.275422 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4698 12:16:39.275486 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4699 12:16:39.275537 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4700 12:16:39.275588 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4701 12:16:39.275639 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4702 12:16:39.275690 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4703 12:16:39.275741 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4704 12:16:39.275792 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4705 12:16:39.275843 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4706 12:16:39.275893 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4707 12:16:39.275944 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4708 12:16:39.275995 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4709 12:16:39.276046 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4710 12:16:39.276097 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4711 12:16:39.276147 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4712 12:16:39.276198 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4713 12:16:39.276248 ==
4714 12:16:39.276322 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 12:16:39.276387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 12:16:39.276438 ==
4717 12:16:39.276489 DQS Delay:
4718 12:16:39.276542 DQS0 = 0, DQS1 = 0
4719 12:16:39.276594 DQM Delay:
4720 12:16:39.276645 DQM0 = 42, DQM1 = 39
4721 12:16:39.276696 DQ Delay:
4722 12:16:39.276938 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4723 12:16:39.277015 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4724 12:16:39.277082 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4725 12:16:39.277133 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4726 12:16:39.277184
4727 12:16:39.277235
4728 12:16:39.277296 ==
4729 12:16:39.277353 Dram Type= 6, Freq= 0, CH_1, rank 1
4730 12:16:39.277405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4731 12:16:39.277457 ==
4732 12:16:39.277509
4733 12:16:39.277559
4734 12:16:39.277610 TX Vref Scan disable
4735 12:16:39.277662 == TX Byte 0 ==
4736 12:16:39.277713 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4737 12:16:39.277765 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4738 12:16:39.277816 == TX Byte 1 ==
4739 12:16:39.277867 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4740 12:16:39.277917 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4741 12:16:39.277968 ==
4742 12:16:39.278019 Dram Type= 6, Freq= 0, CH_1, rank 1
4743 12:16:39.278070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4744 12:16:39.278122 ==
4745 12:16:39.278173
4746 12:16:39.278223
4747 12:16:39.278274 TX Vref Scan disable
4748 12:16:39.278325 == TX Byte 0 ==
4749 12:16:39.278376 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4750 12:16:39.278427 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4751 12:16:39.278478 == TX Byte 1 ==
4752 12:16:39.278530 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4753 12:16:39.278581 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4754 12:16:39.278632
4755 12:16:39.278682 [DATLAT]
4756 12:16:39.278734 Freq=600, CH1 RK1
4757 12:16:39.278785
4758 12:16:39.278836 DATLAT Default: 0x9
4759 12:16:39.278886 0, 0xFFFF, sum = 0
4760 12:16:39.278938 1, 0xFFFF, sum = 0
4761 12:16:39.278991 2, 0xFFFF, sum = 0
4762 12:16:39.279042 3, 0xFFFF, sum = 0
4763 12:16:39.279094 4, 0xFFFF, sum = 0
4764 12:16:39.279145 5, 0xFFFF, sum = 0
4765 12:16:39.279197 6, 0xFFFF, sum = 0
4766 12:16:39.279248 7, 0xFFFF, sum = 0
4767 12:16:39.279315 8, 0x0, sum = 1
4768 12:16:39.279398 9, 0x0, sum = 2
4769 12:16:39.279452 10, 0x0, sum = 3
4770 12:16:39.279505 11, 0x0, sum = 4
4771 12:16:39.279556 best_step = 9
4772 12:16:39.279608
4773 12:16:39.279659 ==
4774 12:16:39.279711 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 12:16:39.279762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 12:16:39.279814 ==
4777 12:16:39.279865 RX Vref Scan: 0
4778 12:16:39.279916
4779 12:16:39.279967 RX Vref 0 -> 0, step: 1
4780 12:16:39.280018
4781 12:16:39.280069 RX Delay -179 -> 252, step: 8
4782 12:16:39.280121 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4783 12:16:39.280172 iDelay=205, Bit 1, Center 32 (-131 ~ 196) 328
4784 12:16:39.280223 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4785 12:16:39.280274 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4786 12:16:39.280324 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4787 12:16:39.280375 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4788 12:16:39.280426 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4789 12:16:39.280477 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4790 12:16:39.280528 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4791 12:16:39.280579 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4792 12:16:39.280630 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4793 12:16:39.280681 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4794 12:16:39.280733 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4795 12:16:39.280784 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4796 12:16:39.280834 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4797 12:16:39.280885 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4798 12:16:39.280935 ==
4799 12:16:39.280986 Dram Type= 6, Freq= 0, CH_1, rank 1
4800 12:16:39.281037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4801 12:16:39.281088 ==
4802 12:16:39.281140 DQS Delay:
4803 12:16:39.281190 DQS0 = 0, DQS1 = 0
4804 12:16:39.281241 DQM Delay:
4805 12:16:39.281298 DQM0 = 37, DQM1 = 35
4806 12:16:39.281387 DQ Delay:
4807 12:16:39.281448 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4808 12:16:39.281501 DQ4 =36, DQ5 =44, DQ6 =48, DQ7 =32
4809 12:16:39.281553 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4810 12:16:39.281605 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4811 12:16:39.281655
4812 12:16:39.281706
4813 12:16:39.281757 [DQSOSCAuto] RK1, (LSB)MR18= 0x3055, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4814 12:16:39.281809 CH1 RK1: MR19=808, MR18=3055
4815 12:16:39.281861 CH1_RK1: MR19=0x808, MR18=0x3055, DQSOSC=393, MR23=63, INC=169, DEC=113
4816 12:16:39.281912 [RxdqsGatingPostProcess] freq 600
4817 12:16:39.281963 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4818 12:16:39.282014 Pre-setting of DQS Precalculation
4819 12:16:39.282064 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4820 12:16:39.282116 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4821 12:16:39.282167 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4822 12:16:39.282218
4823 12:16:39.282270
4824 12:16:39.282321 [Calibration Summary] 1200 Mbps
4825 12:16:39.282372 CH 0, Rank 0
4826 12:16:39.282424 SW Impedance : PASS
4827 12:16:39.282475 DUTY Scan : NO K
4828 12:16:39.282526 ZQ Calibration : PASS
4829 12:16:39.282577 Jitter Meter : NO K
4830 12:16:39.282628 CBT Training : PASS
4831 12:16:39.282679 Write leveling : PASS
4832 12:16:39.282730 RX DQS gating : PASS
4833 12:16:39.282782 RX DQ/DQS(RDDQC) : PASS
4834 12:16:39.282833 TX DQ/DQS : PASS
4835 12:16:39.282884 RX DATLAT : PASS
4836 12:16:39.282935 RX DQ/DQS(Engine): PASS
4837 12:16:39.282986 TX OE : NO K
4838 12:16:39.283037 All Pass.
4839 12:16:39.283088
4840 12:16:39.283170 CH 0, Rank 1
4841 12:16:39.283241 SW Impedance : PASS
4842 12:16:39.283321 DUTY Scan : NO K
4843 12:16:39.283430 ZQ Calibration : PASS
4844 12:16:39.283483 Jitter Meter : NO K
4845 12:16:39.283534 CBT Training : PASS
4846 12:16:39.283586 Write leveling : PASS
4847 12:16:39.283637 RX DQS gating : PASS
4848 12:16:39.283687 RX DQ/DQS(RDDQC) : PASS
4849 12:16:39.283762 TX DQ/DQS : PASS
4850 12:16:39.283850 RX DATLAT : PASS
4851 12:16:39.283938 RX DQ/DQS(Engine): PASS
4852 12:16:39.284025 TX OE : NO K
4853 12:16:39.284106 All Pass.
4854 12:16:39.284185
4855 12:16:39.284269 CH 1, Rank 0
4856 12:16:39.284349 SW Impedance : PASS
4857 12:16:39.284429 DUTY Scan : NO K
4858 12:16:39.284508 ZQ Calibration : PASS
4859 12:16:39.284587 Jitter Meter : NO K
4860 12:16:39.284666 CBT Training : PASS
4861 12:16:39.284745 Write leveling : PASS
4862 12:16:39.284824 RX DQS gating : PASS
4863 12:16:39.284903 RX DQ/DQS(RDDQC) : PASS
4864 12:16:39.284982 TX DQ/DQS : PASS
4865 12:16:39.285062 RX DATLAT : PASS
4866 12:16:39.285141 RX DQ/DQS(Engine): PASS
4867 12:16:39.285220 TX OE : NO K
4868 12:16:39.285299 All Pass.
4869 12:16:39.285378
4870 12:16:39.285456 CH 1, Rank 1
4871 12:16:39.285535 SW Impedance : PASS
4872 12:16:39.285614 DUTY Scan : NO K
4873 12:16:39.285693 ZQ Calibration : PASS
4874 12:16:39.285772 Jitter Meter : NO K
4875 12:16:39.286043 CBT Training : PASS
4876 12:16:39.286127 Write leveling : PASS
4877 12:16:39.286208 RX DQS gating : PASS
4878 12:16:39.286287 RX DQ/DQS(RDDQC) : PASS
4879 12:16:39.286366 TX DQ/DQS : PASS
4880 12:16:39.286446 RX DATLAT : PASS
4881 12:16:39.286525 RX DQ/DQS(Engine): PASS
4882 12:16:39.286604 TX OE : NO K
4883 12:16:39.286683 All Pass.
4884 12:16:39.286761
4885 12:16:39.286840 DramC Write-DBI off
4886 12:16:39.286919 PER_BANK_REFRESH: Hybrid Mode
4887 12:16:39.286998 TX_TRACKING: ON
4888 12:16:39.287079 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4889 12:16:39.287159 [FAST_K] Save calibration result to emmc
4890 12:16:39.287239 dramc_set_vcore_voltage set vcore to 662500
4891 12:16:39.287318 Read voltage for 933, 3
4892 12:16:39.287437 Vio18 = 0
4893 12:16:39.287517 Vcore = 662500
4894 12:16:39.287596 Vdram = 0
4895 12:16:39.287674 Vddq = 0
4896 12:16:39.287753 Vmddr = 0
4897 12:16:39.287832 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4898 12:16:39.287913 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4899 12:16:39.287993 MEM_TYPE=3, freq_sel=17
4900 12:16:39.288072 sv_algorithm_assistance_LP4_1600
4901 12:16:39.288151 ============ PULL DRAM RESETB DOWN ============
4902 12:16:39.288232 ========== PULL DRAM RESETB DOWN end =========
4903 12:16:39.288312 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4904 12:16:39.288391 ===================================
4905 12:16:39.288471 LPDDR4 DRAM CONFIGURATION
4906 12:16:39.288550 ===================================
4907 12:16:39.288629 EX_ROW_EN[0] = 0x0
4908 12:16:39.288708 EX_ROW_EN[1] = 0x0
4909 12:16:39.288787 LP4Y_EN = 0x0
4910 12:16:39.288866 WORK_FSP = 0x0
4911 12:16:39.288945 WL = 0x3
4912 12:16:39.289024 RL = 0x3
4913 12:16:39.289102 BL = 0x2
4914 12:16:39.289181 RPST = 0x0
4915 12:16:39.289260 RD_PRE = 0x0
4916 12:16:39.289339 WR_PRE = 0x1
4917 12:16:39.289417 WR_PST = 0x0
4918 12:16:39.289496 DBI_WR = 0x0
4919 12:16:39.289575 DBI_RD = 0x0
4920 12:16:39.289654 OTF = 0x1
4921 12:16:39.289733 ===================================
4922 12:16:39.289813 ===================================
4923 12:16:39.289893 ANA top config
4924 12:16:39.289971 ===================================
4925 12:16:39.290051 DLL_ASYNC_EN = 0
4926 12:16:39.290130 ALL_SLAVE_EN = 1
4927 12:16:39.290209 NEW_RANK_MODE = 1
4928 12:16:39.290289 DLL_IDLE_MODE = 1
4929 12:16:39.290368 LP45_APHY_COMB_EN = 1
4930 12:16:39.290447 TX_ODT_DIS = 1
4931 12:16:39.290526 NEW_8X_MODE = 1
4932 12:16:39.290606 ===================================
4933 12:16:39.290685 ===================================
4934 12:16:39.290765 data_rate = 1866
4935 12:16:39.290844 CKR = 1
4936 12:16:39.290923 DQ_P2S_RATIO = 8
4937 12:16:39.291002 ===================================
4938 12:16:39.291081 CA_P2S_RATIO = 8
4939 12:16:39.291161 DQ_CA_OPEN = 0
4940 12:16:39.291240 DQ_SEMI_OPEN = 0
4941 12:16:39.291318 CA_SEMI_OPEN = 0
4942 12:16:39.291443 CA_FULL_RATE = 0
4943 12:16:39.291527 DQ_CKDIV4_EN = 1
4944 12:16:39.291620 CA_CKDIV4_EN = 1
4945 12:16:39.291699 CA_PREDIV_EN = 0
4946 12:16:39.291777 PH8_DLY = 0
4947 12:16:39.291831 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4948 12:16:39.291882 DQ_AAMCK_DIV = 4
4949 12:16:39.291934 CA_AAMCK_DIV = 4
4950 12:16:39.291985 CA_ADMCK_DIV = 4
4951 12:16:39.292036 DQ_TRACK_CA_EN = 0
4952 12:16:39.292087 CA_PICK = 933
4953 12:16:39.292137 CA_MCKIO = 933
4954 12:16:39.292188 MCKIO_SEMI = 0
4955 12:16:39.292239 PLL_FREQ = 3732
4956 12:16:39.292290 DQ_UI_PI_RATIO = 32
4957 12:16:39.292340 CA_UI_PI_RATIO = 0
4958 12:16:39.292392 ===================================
4959 12:16:39.292444 ===================================
4960 12:16:39.292495 memory_type:LPDDR4
4961 12:16:39.292546 GP_NUM : 10
4962 12:16:39.292597 SRAM_EN : 1
4963 12:16:39.292647 MD32_EN : 0
4964 12:16:39.292698 ===================================
4965 12:16:39.292749 [ANA_INIT] >>>>>>>>>>>>>>
4966 12:16:39.292800 <<<<<< [CONFIGURE PHASE]: ANA_TX
4967 12:16:39.292852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4968 12:16:39.292903 ===================================
4969 12:16:39.292954 data_rate = 1866,PCW = 0X8f00
4970 12:16:39.293005 ===================================
4971 12:16:39.293057 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4972 12:16:39.293108 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4973 12:16:39.293159 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4974 12:16:39.293211 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4975 12:16:39.293275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4976 12:16:39.293327 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4977 12:16:39.293378 [ANA_INIT] flow start
4978 12:16:39.293429 [ANA_INIT] PLL >>>>>>>>
4979 12:16:39.293480 [ANA_INIT] PLL <<<<<<<<
4980 12:16:39.293531 [ANA_INIT] MIDPI >>>>>>>>
4981 12:16:39.293581 [ANA_INIT] MIDPI <<<<<<<<
4982 12:16:39.293632 [ANA_INIT] DLL >>>>>>>>
4983 12:16:39.293683 [ANA_INIT] flow end
4984 12:16:39.293734 ============ LP4 DIFF to SE enter ============
4985 12:16:39.293785 ============ LP4 DIFF to SE exit ============
4986 12:16:39.293837 [ANA_INIT] <<<<<<<<<<<<<
4987 12:16:39.293888 [Flow] Enable top DCM control >>>>>
4988 12:16:39.293959 [Flow] Enable top DCM control <<<<<
4989 12:16:39.294013 Enable DLL master slave shuffle
4990 12:16:39.294081 ==============================================================
4991 12:16:39.294135 Gating Mode config
4992 12:16:39.294190 ==============================================================
4993 12:16:39.294254 Config description:
4994 12:16:39.294318 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4995 12:16:39.630450 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4996 12:16:39.630986 SELPH_MODE 0: By rank 1: By Phase
4997 12:16:39.631348 ==============================================================
4998 12:16:39.632156 GAT_TRACK_EN = 1
4999 12:16:39.632525 RX_GATING_MODE = 2
5000 12:16:39.632857 RX_GATING_TRACK_MODE = 2
5001 12:16:39.633172 SELPH_MODE = 1
5002 12:16:39.633482 PICG_EARLY_EN = 1
5003 12:16:39.633786 VALID_LAT_VALUE = 1
5004 12:16:39.634089 ==============================================================
5005 12:16:39.634394 Enter into Gating configuration >>>>
5006 12:16:39.634694 Exit from Gating configuration <<<<
5007 12:16:39.634994 Enter into DVFS_PRE_config >>>>>
5008 12:16:39.635294 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5009 12:16:39.635665 Exit from DVFS_PRE_config <<<<<
5010 12:16:39.635968 Enter into PICG configuration >>>>
5011 12:16:39.636267 Exit from PICG configuration <<<<
5012 12:16:39.636562 [RX_INPUT] configuration >>>>>
5013 12:16:39.636856 [RX_INPUT] configuration <<<<<
5014 12:16:39.637151 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5015 12:16:39.637452 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5016 12:16:39.637750 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5017 12:16:39.638050 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5018 12:16:39.638345 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5019 12:16:39.638664 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5020 12:16:39.639021 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5021 12:16:39.639324 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5022 12:16:39.639670 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5023 12:16:39.639970 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5024 12:16:39.640376 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5025 12:16:39.640686 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5026 12:16:39.640987 ===================================
5027 12:16:39.641291 LPDDR4 DRAM CONFIGURATION
5028 12:16:39.641591 ===================================
5029 12:16:39.641890 EX_ROW_EN[0] = 0x0
5030 12:16:39.642183 EX_ROW_EN[1] = 0x0
5031 12:16:39.642479 LP4Y_EN = 0x0
5032 12:16:39.642776 WORK_FSP = 0x0
5033 12:16:39.643070 WL = 0x3
5034 12:16:39.643382 RL = 0x3
5035 12:16:39.643684 BL = 0x2
5036 12:16:39.643974 RPST = 0x0
5037 12:16:39.644265 RD_PRE = 0x0
5038 12:16:39.644554 WR_PRE = 0x1
5039 12:16:39.644844 WR_PST = 0x0
5040 12:16:39.645136 DBI_WR = 0x0
5041 12:16:39.645424 DBI_RD = 0x0
5042 12:16:39.645716 OTF = 0x1
5043 12:16:39.646006 ===================================
5044 12:16:39.646304 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5045 12:16:39.646596 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5046 12:16:39.646889 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5047 12:16:39.647181 ===================================
5048 12:16:39.647498 LPDDR4 DRAM CONFIGURATION
5049 12:16:39.647796 ===================================
5050 12:16:39.648092 EX_ROW_EN[0] = 0x10
5051 12:16:39.648385 EX_ROW_EN[1] = 0x0
5052 12:16:39.648681 LP4Y_EN = 0x0
5053 12:16:39.648947 WORK_FSP = 0x0
5054 12:16:39.649210 WL = 0x3
5055 12:16:39.649477 RL = 0x3
5056 12:16:39.649740 BL = 0x2
5057 12:16:39.650008 RPST = 0x0
5058 12:16:39.650273 RD_PRE = 0x0
5059 12:16:39.650541 WR_PRE = 0x1
5060 12:16:39.650807 WR_PST = 0x0
5061 12:16:39.651069 DBI_WR = 0x0
5062 12:16:39.651335 DBI_RD = 0x0
5063 12:16:39.651620 OTF = 0x1
5064 12:16:39.651889 ===================================
5065 12:16:39.652159 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5066 12:16:39.652431 nWR fixed to 30
5067 12:16:39.652705 [ModeRegInit_LP4] CH0 RK0
5068 12:16:39.652975 [ModeRegInit_LP4] CH0 RK1
5069 12:16:39.653240 [ModeRegInit_LP4] CH1 RK0
5070 12:16:39.653507 [ModeRegInit_LP4] CH1 RK1
5071 12:16:39.653775 match AC timing 9
5072 12:16:39.654043 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5073 12:16:39.654310 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5074 12:16:39.654578 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5075 12:16:39.654846 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5076 12:16:39.655115 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5077 12:16:39.655400 ==
5078 12:16:39.655677 Dram Type= 6, Freq= 0, CH_0, rank 0
5079 12:16:39.655948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5080 12:16:39.656221 ==
5081 12:16:39.656493 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5082 12:16:39.656769 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5083 12:16:39.657042 [CA 0] Center 37 (7~68) winsize 62
5084 12:16:39.657311 [CA 1] Center 37 (7~68) winsize 62
5085 12:16:39.657578 [CA 2] Center 34 (4~65) winsize 62
5086 12:16:39.657845 [CA 3] Center 34 (4~65) winsize 62
5087 12:16:39.658112 [CA 4] Center 33 (3~64) winsize 62
5088 12:16:39.658380 [CA 5] Center 32 (2~63) winsize 62
5089 12:16:39.658630
5090 12:16:39.658821 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5091 12:16:39.659013
5092 12:16:39.659204 [CATrainingPosCal] consider 1 rank data
5093 12:16:39.659411 u2DelayCellTimex100 = 270/100 ps
5094 12:16:39.659606 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5095 12:16:39.659797 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5096 12:16:39.659989 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5097 12:16:39.660182 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5098 12:16:39.660373 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5099 12:16:39.660566 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5100 12:16:39.660758
5101 12:16:39.660950 CA PerBit enable=1, Macro0, CA PI delay=32
5102 12:16:39.661144
5103 12:16:39.661334 [CBTSetCACLKResult] CA Dly = 32
5104 12:16:39.661541 CS Dly: 6 (0~37)
5105 12:16:39.661748 ==
5106 12:16:39.661947 Dram Type= 6, Freq= 0, CH_0, rank 1
5107 12:16:39.662141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5108 12:16:39.662336 ==
5109 12:16:39.662531 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5110 12:16:39.662726 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5111 12:16:39.662919 [CA 0] Center 37 (7~68) winsize 62
5112 12:16:39.663112 [CA 1] Center 37 (7~68) winsize 62
5113 12:16:39.663636 [CA 2] Center 35 (5~65) winsize 61
5114 12:16:39.663803 [CA 3] Center 34 (4~65) winsize 62
5115 12:16:39.663952 [CA 4] Center 33 (3~64) winsize 62
5116 12:16:39.664100 [CA 5] Center 32 (2~63) winsize 62
5117 12:16:39.664247
5118 12:16:39.664392 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5119 12:16:39.664539
5120 12:16:39.664684 [CATrainingPosCal] consider 2 rank data
5121 12:16:39.664829 u2DelayCellTimex100 = 270/100 ps
5122 12:16:39.664974 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5123 12:16:39.665118 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5124 12:16:39.665264 CA2 delay=35 (5~65),Diff = 3 PI (18 cell)
5125 12:16:39.665407 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5126 12:16:39.665549 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5127 12:16:39.665692 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5128 12:16:39.665836
5129 12:16:39.665979 CA PerBit enable=1, Macro0, CA PI delay=32
5130 12:16:39.666123
5131 12:16:39.666265 [CBTSetCACLKResult] CA Dly = 32
5132 12:16:39.666409 CS Dly: 7 (0~39)
5133 12:16:39.666554
5134 12:16:39.666698 ----->DramcWriteLeveling(PI) begin...
5135 12:16:39.666847 ==
5136 12:16:39.666992 Dram Type= 6, Freq= 0, CH_0, rank 0
5137 12:16:39.667138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5138 12:16:39.667285 ==
5139 12:16:39.667445 Write leveling (Byte 0): 33 => 33
5140 12:16:39.667592 Write leveling (Byte 1): 28 => 28
5141 12:16:39.667737 DramcWriteLeveling(PI) end<-----
5142 12:16:39.667882
5143 12:16:39.668027 ==
5144 12:16:39.668173 Dram Type= 6, Freq= 0, CH_0, rank 0
5145 12:16:39.668318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 12:16:39.668466 ==
5147 12:16:39.668611 [Gating] SW mode calibration
5148 12:16:39.668729 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5149 12:16:39.668847 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5150 12:16:39.668964 0 14 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
5151 12:16:39.669081 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 12:16:39.669196 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 12:16:39.669314 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 12:16:39.669431 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 12:16:39.669549 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5156 12:16:39.669665 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 12:16:39.669782 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5158 12:16:39.669900 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5159 12:16:39.670017 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5160 12:16:39.670134 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 12:16:39.670250 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 12:16:39.670367 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 12:16:39.670484 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5164 12:16:39.670600 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 12:16:39.670716 0 15 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
5166 12:16:39.670834 1 0 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5167 12:16:39.670950 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 12:16:39.671068 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 12:16:39.671184 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 12:16:39.671303 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 12:16:39.671433 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 12:16:39.671552 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 12:16:39.671667 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5174 12:16:39.671785 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5175 12:16:39.671901 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 12:16:39.672018 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 12:16:39.672135 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 12:16:39.672252 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 12:16:39.672369 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 12:16:39.672485 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 12:16:39.672602 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 12:16:39.672718 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 12:16:39.672834 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 12:16:39.672949 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 12:16:39.673065 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 12:16:39.673181 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 12:16:39.673298 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 12:16:39.673414 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 12:16:39.673531 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5190 12:16:39.673684 Total UI for P1: 0, mck2ui 16
5191 12:16:39.673787 best dqsien dly found for B0: ( 1, 2, 26)
5192 12:16:39.673886 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5193 12:16:39.673983 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 12:16:39.674080 Total UI for P1: 0, mck2ui 16
5195 12:16:39.674179 best dqsien dly found for B1: ( 1, 2, 30)
5196 12:16:39.674282 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5197 12:16:39.674387 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5198 12:16:39.674485
5199 12:16:39.674583 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5200 12:16:39.674681 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5201 12:16:39.674778 [Gating] SW calibration Done
5202 12:16:39.674876 ==
5203 12:16:39.674974 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 12:16:39.675072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 12:16:39.675170 ==
5206 12:16:39.675266 RX Vref Scan: 0
5207 12:16:39.675379
5208 12:16:39.675482 RX Vref 0 -> 0, step: 1
5209 12:16:39.675580
5210 12:16:39.675676 RX Delay -80 -> 252, step: 8
5211 12:16:39.675773 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5212 12:16:39.675871 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5213 12:16:39.675968 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5214 12:16:39.676065 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5215 12:16:39.676161 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5216 12:16:39.676259 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5217 12:16:39.676357 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5218 12:16:39.676681 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5219 12:16:39.676789 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5220 12:16:39.676889 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5221 12:16:39.676988 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5222 12:16:39.677087 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5223 12:16:39.677184 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5224 12:16:39.677282 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5225 12:16:39.677380 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5226 12:16:39.677477 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5227 12:16:39.677574 ==
5228 12:16:39.677672 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 12:16:39.677770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 12:16:39.677868 ==
5231 12:16:39.677966 DQS Delay:
5232 12:16:39.678064 DQS0 = 0, DQS1 = 0
5233 12:16:39.678167 DQM Delay:
5234 12:16:39.678265 DQM0 = 99, DQM1 = 88
5235 12:16:39.678363 DQ Delay:
5236 12:16:39.678461 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5237 12:16:39.678568 DQ4 =103, DQ5 =91, DQ6 =111, DQ7 =103
5238 12:16:39.678652 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5239 12:16:39.678735 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5240 12:16:39.678819
5241 12:16:39.678903
5242 12:16:39.678985 ==
5243 12:16:39.679068 Dram Type= 6, Freq= 0, CH_0, rank 0
5244 12:16:39.679152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5245 12:16:39.679236 ==
5246 12:16:39.679321
5247 12:16:39.679419
5248 12:16:39.679504 TX Vref Scan disable
5249 12:16:39.679588 == TX Byte 0 ==
5250 12:16:39.679672 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5251 12:16:39.679756 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5252 12:16:39.679841 == TX Byte 1 ==
5253 12:16:39.679924 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5254 12:16:39.680008 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5255 12:16:39.680091 ==
5256 12:16:39.680175 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 12:16:39.680271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 12:16:39.680363 ==
5259 12:16:39.680448
5260 12:16:39.680532
5261 12:16:39.680615 TX Vref Scan disable
5262 12:16:39.680700 == TX Byte 0 ==
5263 12:16:39.680784 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5264 12:16:39.680868 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5265 12:16:39.680952 == TX Byte 1 ==
5266 12:16:39.681036 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5267 12:16:39.681119 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5268 12:16:39.681201
5269 12:16:39.681285 [DATLAT]
5270 12:16:39.681368 Freq=933, CH0 RK0
5271 12:16:39.681452
5272 12:16:39.681535 DATLAT Default: 0xd
5273 12:16:39.681619 0, 0xFFFF, sum = 0
5274 12:16:39.681704 1, 0xFFFF, sum = 0
5275 12:16:39.681790 2, 0xFFFF, sum = 0
5276 12:16:39.681874 3, 0xFFFF, sum = 0
5277 12:16:39.681960 4, 0xFFFF, sum = 0
5278 12:16:39.682044 5, 0xFFFF, sum = 0
5279 12:16:39.682135 6, 0xFFFF, sum = 0
5280 12:16:39.682223 7, 0xFFFF, sum = 0
5281 12:16:39.682309 8, 0xFFFF, sum = 0
5282 12:16:39.682393 9, 0xFFFF, sum = 0
5283 12:16:39.682479 10, 0x0, sum = 1
5284 12:16:39.682564 11, 0x0, sum = 2
5285 12:16:39.682649 12, 0x0, sum = 3
5286 12:16:39.682734 13, 0x0, sum = 4
5287 12:16:39.682819 best_step = 11
5288 12:16:39.682902
5289 12:16:39.682986 ==
5290 12:16:39.683069 Dram Type= 6, Freq= 0, CH_0, rank 0
5291 12:16:39.683154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 12:16:39.683238 ==
5293 12:16:39.683322 RX Vref Scan: 1
5294 12:16:39.683434
5295 12:16:39.683535 RX Vref 0 -> 0, step: 1
5296 12:16:39.683610
5297 12:16:39.683683 RX Delay -61 -> 252, step: 4
5298 12:16:39.683758
5299 12:16:39.683831 Set Vref, RX VrefLevel [Byte0]: 53
5300 12:16:39.683906 [Byte1]: 59
5301 12:16:39.683981
5302 12:16:39.684054 Final RX Vref Byte 0 = 53 to rank0
5303 12:16:39.684128 Final RX Vref Byte 1 = 59 to rank0
5304 12:16:39.684212 Final RX Vref Byte 0 = 53 to rank1
5305 12:16:39.684287 Final RX Vref Byte 1 = 59 to rank1==
5306 12:16:39.684361 Dram Type= 6, Freq= 0, CH_0, rank 0
5307 12:16:39.684434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 12:16:39.684509 ==
5309 12:16:39.684582 DQS Delay:
5310 12:16:39.684656 DQS0 = 0, DQS1 = 0
5311 12:16:39.684730 DQM Delay:
5312 12:16:39.684803 DQM0 = 98, DQM1 = 87
5313 12:16:39.684877 DQ Delay:
5314 12:16:39.684968 DQ0 =100, DQ1 =98, DQ2 =94, DQ3 =96
5315 12:16:39.685045 DQ4 =100, DQ5 =90, DQ6 =106, DQ7 =104
5316 12:16:39.685119 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =84
5317 12:16:39.685193 DQ12 =96, DQ13 =90, DQ14 =98, DQ15 =92
5318 12:16:39.685267
5319 12:16:39.685340
5320 12:16:39.685412 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d17, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 412 ps
5321 12:16:39.685488 CH0 RK0: MR19=505, MR18=1D17
5322 12:16:39.685562 CH0_RK0: MR19=0x505, MR18=0x1D17, DQSOSC=412, MR23=63, INC=63, DEC=42
5323 12:16:39.685635
5324 12:16:39.685708 ----->DramcWriteLeveling(PI) begin...
5325 12:16:39.685784 ==
5326 12:16:39.685858 Dram Type= 6, Freq= 0, CH_0, rank 1
5327 12:16:39.685933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5328 12:16:39.686006 ==
5329 12:16:39.686081 Write leveling (Byte 0): 32 => 32
5330 12:16:39.686155 Write leveling (Byte 1): 31 => 31
5331 12:16:39.686229 DramcWriteLeveling(PI) end<-----
5332 12:16:39.686302
5333 12:16:39.686375 ==
5334 12:16:39.686449 Dram Type= 6, Freq= 0, CH_0, rank 1
5335 12:16:39.686523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 12:16:39.686596 ==
5337 12:16:39.686670 [Gating] SW mode calibration
5338 12:16:39.686745 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5339 12:16:39.686819 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5340 12:16:39.686893 0 14 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
5341 12:16:39.686968 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 12:16:39.687041 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 12:16:39.687115 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 12:16:39.687189 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 12:16:39.687262 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5346 12:16:39.687336 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5347 12:16:39.687419 0 14 28 | B1->B0 | 3434 2b2b | 1 1 | (0 0) (0 0)
5348 12:16:39.687493 0 15 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
5349 12:16:39.687566 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 12:16:39.687640 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 12:16:39.687713 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 12:16:39.687787 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 12:16:39.687860 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 12:16:39.687933 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5355 12:16:39.688007 0 15 28 | B1->B0 | 2a2a 3a3a | 0 0 | (0 0) (0 0)
5356 12:16:39.688080 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5357 12:16:39.688364 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 12:16:39.688450 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 12:16:39.688526 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 12:16:39.688610 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 12:16:39.688676 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 12:16:39.688742 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 12:16:39.688807 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5364 12:16:39.688872 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5365 12:16:39.688937 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 12:16:39.689001 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 12:16:39.689066 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 12:16:39.689131 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 12:16:39.689196 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 12:16:39.689261 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 12:16:39.689325 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 12:16:39.689389 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 12:16:39.689454 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 12:16:39.689518 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 12:16:39.689582 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 12:16:39.689646 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 12:16:39.689709 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 12:16:39.689774 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5379 12:16:39.689838 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5380 12:16:39.689902 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5381 12:16:39.689967 Total UI for P1: 0, mck2ui 16
5382 12:16:39.690033 best dqsien dly found for B0: ( 1, 2, 26)
5383 12:16:39.690098 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 12:16:39.690167 Total UI for P1: 0, mck2ui 16
5385 12:16:39.690234 best dqsien dly found for B1: ( 1, 2, 30)
5386 12:16:39.690299 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5387 12:16:39.690365 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5388 12:16:39.690429
5389 12:16:39.690492 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5390 12:16:39.690557 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5391 12:16:39.690622 [Gating] SW calibration Done
5392 12:16:39.690687 ==
5393 12:16:39.690752 Dram Type= 6, Freq= 0, CH_0, rank 1
5394 12:16:39.690816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5395 12:16:39.690882 ==
5396 12:16:39.690946 RX Vref Scan: 0
5397 12:16:39.691014
5398 12:16:39.691078 RX Vref 0 -> 0, step: 1
5399 12:16:39.691143
5400 12:16:39.691207 RX Delay -80 -> 252, step: 8
5401 12:16:39.691272 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5402 12:16:39.691336 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5403 12:16:39.691414 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5404 12:16:39.691481 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5405 12:16:39.691545 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5406 12:16:39.691610 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5407 12:16:39.691675 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5408 12:16:39.691739 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5409 12:16:39.691804 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5410 12:16:39.691868 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5411 12:16:39.691933 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5412 12:16:39.691997 iDelay=200, Bit 11, Center 87 (0 ~ 175) 176
5413 12:16:39.692062 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5414 12:16:39.692127 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5415 12:16:39.692218 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5416 12:16:39.692320 iDelay=200, Bit 15, Center 99 (8 ~ 191) 184
5417 12:16:39.692430 ==
5418 12:16:39.692536 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 12:16:39.692615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 12:16:39.692682 ==
5421 12:16:39.692748 DQS Delay:
5422 12:16:39.692813 DQS0 = 0, DQS1 = 0
5423 12:16:39.692878 DQM Delay:
5424 12:16:39.692943 DQM0 = 97, DQM1 = 90
5425 12:16:39.693008 DQ Delay:
5426 12:16:39.693073 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5427 12:16:39.693138 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5428 12:16:39.693202 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =87
5429 12:16:39.693267 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =99
5430 12:16:39.693332
5431 12:16:39.693395
5432 12:16:39.693459 ==
5433 12:16:39.693524 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 12:16:39.693597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 12:16:39.693656 ==
5436 12:16:39.693713
5437 12:16:39.693771
5438 12:16:39.693830 TX Vref Scan disable
5439 12:16:39.693889 == TX Byte 0 ==
5440 12:16:39.693961 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5441 12:16:39.694022 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5442 12:16:39.694081 == TX Byte 1 ==
5443 12:16:39.694141 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5444 12:16:39.694204 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5445 12:16:39.694262 ==
5446 12:16:39.694321 Dram Type= 6, Freq= 0, CH_0, rank 1
5447 12:16:39.694379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5448 12:16:39.694438 ==
5449 12:16:39.694496
5450 12:16:39.694554
5451 12:16:39.694612 TX Vref Scan disable
5452 12:16:39.694670 == TX Byte 0 ==
5453 12:16:39.694728 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5454 12:16:39.694786 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5455 12:16:39.694844 == TX Byte 1 ==
5456 12:16:39.694903 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5457 12:16:39.694960 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5458 12:16:39.695018
5459 12:16:39.695076 [DATLAT]
5460 12:16:39.695134 Freq=933, CH0 RK1
5461 12:16:39.695192
5462 12:16:39.695249 DATLAT Default: 0xb
5463 12:16:39.695307 0, 0xFFFF, sum = 0
5464 12:16:39.695377 1, 0xFFFF, sum = 0
5465 12:16:39.695442 2, 0xFFFF, sum = 0
5466 12:16:39.695502 3, 0xFFFF, sum = 0
5467 12:16:39.695561 4, 0xFFFF, sum = 0
5468 12:16:39.695620 5, 0xFFFF, sum = 0
5469 12:16:39.695679 6, 0xFFFF, sum = 0
5470 12:16:39.695738 7, 0xFFFF, sum = 0
5471 12:16:39.695797 8, 0xFFFF, sum = 0
5472 12:16:39.695856 9, 0xFFFF, sum = 0
5473 12:16:39.695914 10, 0x0, sum = 1
5474 12:16:39.695974 11, 0x0, sum = 2
5475 12:16:39.696033 12, 0x0, sum = 3
5476 12:16:39.696092 13, 0x0, sum = 4
5477 12:16:39.696151 best_step = 11
5478 12:16:39.696215
5479 12:16:39.696273 ==
5480 12:16:39.696331 Dram Type= 6, Freq= 0, CH_0, rank 1
5481 12:16:39.696390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5482 12:16:39.696450 ==
5483 12:16:39.696509 RX Vref Scan: 0
5484 12:16:39.696567
5485 12:16:39.696625 RX Vref 0 -> 0, step: 1
5486 12:16:39.696682
5487 12:16:39.696741 RX Delay -61 -> 252, step: 4
5488 12:16:39.696799 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5489 12:16:39.697058 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5490 12:16:39.697127 iDelay=195, Bit 2, Center 92 (3 ~ 182) 180
5491 12:16:39.697187 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5492 12:16:39.697245 iDelay=195, Bit 4, Center 100 (7 ~ 194) 188
5493 12:16:39.697303 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5494 12:16:39.697362 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
5495 12:16:39.697421 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5496 12:16:39.697480 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5497 12:16:39.697538 iDelay=195, Bit 9, Center 78 (-5 ~ 162) 168
5498 12:16:39.697596 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5499 12:16:39.697655 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5500 12:16:39.697713 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5501 12:16:39.697770 iDelay=195, Bit 13, Center 94 (3 ~ 186) 184
5502 12:16:39.697829 iDelay=195, Bit 14, Center 100 (15 ~ 186) 172
5503 12:16:39.697887 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5504 12:16:39.697945 ==
5505 12:16:39.698004 Dram Type= 6, Freq= 0, CH_0, rank 1
5506 12:16:39.698062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 12:16:39.698122 ==
5508 12:16:39.698199 DQS Delay:
5509 12:16:39.698297 DQS0 = 0, DQS1 = 0
5510 12:16:39.698361 DQM Delay:
5511 12:16:39.698420 DQM0 = 97, DQM1 = 89
5512 12:16:39.698479 DQ Delay:
5513 12:16:39.698538 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5514 12:16:39.698604 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =106
5515 12:16:39.698657 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =84
5516 12:16:39.698710 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =94
5517 12:16:39.698763
5518 12:16:39.698815
5519 12:16:39.698868 [DQSOSCAuto] RK1, (LSB)MR18= 0x110f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5520 12:16:39.698922 CH0 RK1: MR19=505, MR18=110F
5521 12:16:39.698977 CH0_RK1: MR19=0x505, MR18=0x110F, DQSOSC=416, MR23=63, INC=62, DEC=41
5522 12:16:39.699031 [RxdqsGatingPostProcess] freq 933
5523 12:16:39.699085 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5524 12:16:39.699138 best DQS0 dly(2T, 0.5T) = (0, 10)
5525 12:16:39.699191 best DQS1 dly(2T, 0.5T) = (0, 10)
5526 12:16:39.699244 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5527 12:16:39.699296 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5528 12:16:39.699349 best DQS0 dly(2T, 0.5T) = (0, 10)
5529 12:16:39.699411 best DQS1 dly(2T, 0.5T) = (0, 10)
5530 12:16:39.699465 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5531 12:16:39.699518 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5532 12:16:39.699571 Pre-setting of DQS Precalculation
5533 12:16:39.699624 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5534 12:16:39.699676 ==
5535 12:16:39.699730 Dram Type= 6, Freq= 0, CH_1, rank 0
5536 12:16:39.699783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 12:16:39.699837 ==
5538 12:16:39.699890 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5539 12:16:39.699943 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5540 12:16:39.699997 [CA 0] Center 36 (6~67) winsize 62
5541 12:16:39.700050 [CA 1] Center 36 (6~67) winsize 62
5542 12:16:39.700102 [CA 2] Center 34 (4~65) winsize 62
5543 12:16:39.700155 [CA 3] Center 34 (4~64) winsize 61
5544 12:16:39.700208 [CA 4] Center 34 (4~65) winsize 62
5545 12:16:39.700262 [CA 5] Center 33 (3~64) winsize 62
5546 12:16:39.700314
5547 12:16:39.700367 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5548 12:16:39.700420
5549 12:16:39.700473 [CATrainingPosCal] consider 1 rank data
5550 12:16:39.700527 u2DelayCellTimex100 = 270/100 ps
5551 12:16:39.700579 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5552 12:16:39.700632 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5553 12:16:39.700684 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5554 12:16:39.700737 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5555 12:16:39.700789 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5556 12:16:39.700842 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5557 12:16:39.700894
5558 12:16:39.700947 CA PerBit enable=1, Macro0, CA PI delay=33
5559 12:16:39.701001
5560 12:16:39.701053 [CBTSetCACLKResult] CA Dly = 33
5561 12:16:39.701106 CS Dly: 5 (0~36)
5562 12:16:39.701159 ==
5563 12:16:39.701212 Dram Type= 6, Freq= 0, CH_1, rank 1
5564 12:16:39.701265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5565 12:16:39.701318 ==
5566 12:16:39.701371 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5567 12:16:39.701424 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5568 12:16:39.701478 [CA 0] Center 36 (6~67) winsize 62
5569 12:16:39.701530 [CA 1] Center 36 (6~67) winsize 62
5570 12:16:39.701583 [CA 2] Center 34 (4~65) winsize 62
5571 12:16:39.701636 [CA 3] Center 33 (3~64) winsize 62
5572 12:16:39.701689 [CA 4] Center 34 (3~65) winsize 63
5573 12:16:39.701741 [CA 5] Center 33 (3~64) winsize 62
5574 12:16:39.701794
5575 12:16:39.701846 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5576 12:16:39.701899
5577 12:16:39.701951 [CATrainingPosCal] consider 2 rank data
5578 12:16:39.702004 u2DelayCellTimex100 = 270/100 ps
5579 12:16:39.702057 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5580 12:16:39.702110 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5581 12:16:39.702163 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5582 12:16:39.702222 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5583 12:16:39.702292 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5584 12:16:39.702358 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5585 12:16:39.702450
5586 12:16:39.702508 CA PerBit enable=1, Macro0, CA PI delay=33
5587 12:16:39.702563
5588 12:16:39.702617 [CBTSetCACLKResult] CA Dly = 33
5589 12:16:39.702671 CS Dly: 6 (0~38)
5590 12:16:39.702724
5591 12:16:39.702777 ----->DramcWriteLeveling(PI) begin...
5592 12:16:39.702831 ==
5593 12:16:39.702885 Dram Type= 6, Freq= 0, CH_1, rank 0
5594 12:16:39.702939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5595 12:16:39.702992 ==
5596 12:16:39.703045 Write leveling (Byte 0): 26 => 26
5597 12:16:39.703098 Write leveling (Byte 1): 26 => 26
5598 12:16:39.703151 DramcWriteLeveling(PI) end<-----
5599 12:16:39.703206
5600 12:16:39.703258 ==
5601 12:16:39.703311 Dram Type= 6, Freq= 0, CH_1, rank 0
5602 12:16:39.703372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5603 12:16:39.703428 ==
5604 12:16:39.703481 [Gating] SW mode calibration
5605 12:16:39.703534 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5606 12:16:39.703600 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5607 12:16:39.703653 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5608 12:16:39.703900 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 12:16:39.703958 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 12:16:39.704012 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 12:16:39.704064 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 12:16:39.704117 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 12:16:39.704169 0 14 24 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 1)
5614 12:16:39.704221 0 14 28 | B1->B0 | 2b2b 2525 | 0 0 | (1 0) (0 0)
5615 12:16:39.704273 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5616 12:16:39.704324 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 12:16:39.704376 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 12:16:39.704427 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 12:16:39.704479 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 12:16:39.704531 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 12:16:39.704582 0 15 24 | B1->B0 | 2525 2424 | 0 1 | (0 0) (0 0)
5622 12:16:39.704633 0 15 28 | B1->B0 | 3535 3c3c | 0 0 | (0 0) (0 0)
5623 12:16:39.704709 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 12:16:39.704779 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 12:16:39.704871 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 12:16:39.704963 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 12:16:39.705052 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 12:16:39.705141 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 12:16:39.705230 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5630 12:16:39.705317 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5631 12:16:39.705402 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 12:16:39.705484 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 12:16:39.705565 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 12:16:39.705648 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 12:16:39.705736 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 12:16:39.705819 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 12:16:39.705901 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 12:16:39.705987 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 12:16:39.706069 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 12:16:39.706164 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 12:16:39.706250 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 12:16:39.706339 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 12:16:39.706425 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 12:16:39.706507 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 12:16:39.706592 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5646 12:16:39.706674 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5647 12:16:39.706755 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5648 12:16:39.706836 Total UI for P1: 0, mck2ui 16
5649 12:16:39.706918 best dqsien dly found for B0: ( 1, 2, 26)
5650 12:16:39.707000 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 12:16:39.707081 Total UI for P1: 0, mck2ui 16
5652 12:16:39.707162 best dqsien dly found for B1: ( 1, 2, 28)
5653 12:16:39.707244 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5654 12:16:39.707325 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5655 12:16:39.707451
5656 12:16:39.707533 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5657 12:16:39.707615 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5658 12:16:39.707696 [Gating] SW calibration Done
5659 12:16:39.707777 ==
5660 12:16:39.707858 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 12:16:39.707940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 12:16:39.708021 ==
5663 12:16:39.708101 RX Vref Scan: 0
5664 12:16:39.708180
5665 12:16:39.708235 RX Vref 0 -> 0, step: 1
5666 12:16:39.708288
5667 12:16:39.708341 RX Delay -80 -> 252, step: 8
5668 12:16:39.708394 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5669 12:16:39.708446 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5670 12:16:39.708499 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5671 12:16:39.708553 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5672 12:16:39.708605 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5673 12:16:39.708658 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5674 12:16:39.708710 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5675 12:16:39.708762 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5676 12:16:39.708814 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5677 12:16:39.708866 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5678 12:16:39.708917 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5679 12:16:39.708969 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5680 12:16:39.709021 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5681 12:16:39.709073 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5682 12:16:39.709125 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5683 12:16:39.709176 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5684 12:16:39.709228 ==
5685 12:16:39.709280 Dram Type= 6, Freq= 0, CH_1, rank 0
5686 12:16:39.709332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5687 12:16:39.709384 ==
5688 12:16:39.709436 DQS Delay:
5689 12:16:39.709488 DQS0 = 0, DQS1 = 0
5690 12:16:39.709540 DQM Delay:
5691 12:16:39.709592 DQM0 = 99, DQM1 = 96
5692 12:16:39.709644 DQ Delay:
5693 12:16:39.709696 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5694 12:16:39.709749 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5695 12:16:39.709800 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5696 12:16:39.709852 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5697 12:16:39.709904
5698 12:16:39.709956
5699 12:16:39.710007 ==
5700 12:16:39.710059 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 12:16:39.710111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 12:16:39.710176 ==
5703 12:16:39.710260
5704 12:16:39.710340
5705 12:16:39.710420 TX Vref Scan disable
5706 12:16:39.710501 == TX Byte 0 ==
5707 12:16:39.710583 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5708 12:16:39.710664 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5709 12:16:39.710745 == TX Byte 1 ==
5710 12:16:39.710826 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5711 12:16:39.710908 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5712 12:16:39.710988 ==
5713 12:16:39.711069 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 12:16:39.711150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 12:16:39.711231 ==
5716 12:16:39.711311
5717 12:16:39.711419
5718 12:16:39.711487 TX Vref Scan disable
5719 12:16:39.711734 == TX Byte 0 ==
5720 12:16:39.711793 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5721 12:16:39.711847 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5722 12:16:39.711900 == TX Byte 1 ==
5723 12:16:39.711952 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5724 12:16:39.712005 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5725 12:16:39.712057
5726 12:16:39.712108 [DATLAT]
5727 12:16:39.712165 Freq=933, CH1 RK0
5728 12:16:39.712219
5729 12:16:39.712271 DATLAT Default: 0xd
5730 12:16:39.712323 0, 0xFFFF, sum = 0
5731 12:16:39.712376 1, 0xFFFF, sum = 0
5732 12:16:39.712430 2, 0xFFFF, sum = 0
5733 12:16:39.712483 3, 0xFFFF, sum = 0
5734 12:16:39.712535 4, 0xFFFF, sum = 0
5735 12:16:39.712588 5, 0xFFFF, sum = 0
5736 12:16:39.712640 6, 0xFFFF, sum = 0
5737 12:16:39.712693 7, 0xFFFF, sum = 0
5738 12:16:39.712745 8, 0xFFFF, sum = 0
5739 12:16:39.712797 9, 0xFFFF, sum = 0
5740 12:16:39.712850 10, 0x0, sum = 1
5741 12:16:39.712904 11, 0x0, sum = 2
5742 12:16:39.712956 12, 0x0, sum = 3
5743 12:16:39.713009 13, 0x0, sum = 4
5744 12:16:39.713061 best_step = 11
5745 12:16:39.713113
5746 12:16:39.713165 ==
5747 12:16:39.713217 Dram Type= 6, Freq= 0, CH_1, rank 0
5748 12:16:39.713268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 12:16:39.713321 ==
5750 12:16:39.713373 RX Vref Scan: 1
5751 12:16:39.713425
5752 12:16:39.713476 RX Vref 0 -> 0, step: 1
5753 12:16:39.713528
5754 12:16:39.713579 RX Delay -53 -> 252, step: 4
5755 12:16:39.713632
5756 12:16:39.713684 Set Vref, RX VrefLevel [Byte0]: 51
5757 12:16:39.713737 [Byte1]: 51
5758 12:16:39.713789
5759 12:16:39.713841 Final RX Vref Byte 0 = 51 to rank0
5760 12:16:39.713894 Final RX Vref Byte 1 = 51 to rank0
5761 12:16:39.713946 Final RX Vref Byte 0 = 51 to rank1
5762 12:16:39.713998 Final RX Vref Byte 1 = 51 to rank1==
5763 12:16:39.714050 Dram Type= 6, Freq= 0, CH_1, rank 0
5764 12:16:39.714101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5765 12:16:39.714156 ==
5766 12:16:39.714249 DQS Delay:
5767 12:16:39.714300 DQS0 = 0, DQS1 = 0
5768 12:16:39.714353 DQM Delay:
5769 12:16:39.714405 DQM0 = 98, DQM1 = 94
5770 12:16:39.714457 DQ Delay:
5771 12:16:39.714510 DQ0 =104, DQ1 =92, DQ2 =88, DQ3 =100
5772 12:16:39.714562 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =90
5773 12:16:39.714614 DQ8 =82, DQ9 =84, DQ10 =94, DQ11 =88
5774 12:16:39.714666 DQ12 =104, DQ13 =102, DQ14 =100, DQ15 =104
5775 12:16:39.714718
5776 12:16:39.714770
5777 12:16:39.714821 [DQSOSCAuto] RK0, (LSB)MR18= 0x919, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 419 ps
5778 12:16:39.714874 CH1 RK0: MR19=505, MR18=919
5779 12:16:39.714925 CH1_RK0: MR19=0x505, MR18=0x919, DQSOSC=413, MR23=63, INC=63, DEC=42
5780 12:16:39.714977
5781 12:16:39.715029 ----->DramcWriteLeveling(PI) begin...
5782 12:16:39.715082 ==
5783 12:16:39.715134 Dram Type= 6, Freq= 0, CH_1, rank 1
5784 12:16:39.715186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 12:16:39.715238 ==
5786 12:16:39.715291 Write leveling (Byte 0): 27 => 27
5787 12:16:39.715342 Write leveling (Byte 1): 27 => 27
5788 12:16:39.715427 DramcWriteLeveling(PI) end<-----
5789 12:16:39.715511
5790 12:16:39.715572 ==
5791 12:16:39.715634 Dram Type= 6, Freq= 0, CH_1, rank 1
5792 12:16:39.715690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 12:16:39.715742 ==
5794 12:16:39.715794 [Gating] SW mode calibration
5795 12:16:39.715855 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5796 12:16:39.715938 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5797 12:16:39.716026 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 12:16:39.716110 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 12:16:39.716185 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 12:16:39.716264 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 12:16:39.716362 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 12:16:39.716450 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 12:16:39.716535 0 14 24 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
5804 12:16:39.716624 0 14 28 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
5805 12:16:39.716706 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 12:16:39.716788 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 12:16:39.716873 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 12:16:39.716957 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 12:16:39.717039 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 12:16:39.717120 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 12:16:39.717202 0 15 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5812 12:16:39.717283 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5813 12:16:39.717364 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 12:16:39.717446 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 12:16:39.717527 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 12:16:39.717608 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 12:16:39.717689 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 12:16:39.717771 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 12:16:39.717852 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5820 12:16:39.717933 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5821 12:16:39.718014 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 12:16:39.718095 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 12:16:39.718177 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 12:16:39.718258 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 12:16:39.718339 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 12:16:39.718420 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 12:16:39.718501 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 12:16:39.718582 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 12:16:39.718664 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 12:16:39.718745 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 12:16:39.718827 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 12:16:39.718908 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 12:16:39.718989 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 12:16:39.719070 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 12:16:39.719151 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 12:16:39.719232 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5837 12:16:39.719313 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 12:16:39.719623 Total UI for P1: 0, mck2ui 16
5839 12:16:39.719684 best dqsien dly found for B0: ( 1, 2, 28)
5840 12:16:39.719739 Total UI for P1: 0, mck2ui 16
5841 12:16:39.719792 best dqsien dly found for B1: ( 1, 2, 28)
5842 12:16:39.719845 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5843 12:16:39.719898 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5844 12:16:39.719950
5845 12:16:39.720002 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5846 12:16:39.720055 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5847 12:16:39.720107 [Gating] SW calibration Done
5848 12:16:39.720159 ==
5849 12:16:39.720211 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 12:16:39.720264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 12:16:39.720316 ==
5852 12:16:39.720368 RX Vref Scan: 0
5853 12:16:39.720420
5854 12:16:39.720472 RX Vref 0 -> 0, step: 1
5855 12:16:39.720524
5856 12:16:39.720575 RX Delay -80 -> 252, step: 8
5857 12:16:39.720628 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5858 12:16:39.720680 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5859 12:16:39.720732 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5860 12:16:39.720784 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5861 12:16:39.720835 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5862 12:16:39.720887 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5863 12:16:39.720938 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5864 12:16:39.720990 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5865 12:16:39.721042 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5866 12:16:39.721094 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5867 12:16:39.721146 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5868 12:16:39.721199 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5869 12:16:39.721250 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5870 12:16:39.721302 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5871 12:16:39.721354 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5872 12:16:39.721405 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5873 12:16:39.721457 ==
5874 12:16:39.721509 Dram Type= 6, Freq= 0, CH_1, rank 1
5875 12:16:39.721561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5876 12:16:39.721613 ==
5877 12:16:39.721665 DQS Delay:
5878 12:16:39.721717 DQS0 = 0, DQS1 = 0
5879 12:16:39.721769 DQM Delay:
5880 12:16:39.721821 DQM0 = 97, DQM1 = 94
5881 12:16:39.721873 DQ Delay:
5882 12:16:39.721925 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5883 12:16:39.721977 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5884 12:16:39.722029 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5885 12:16:39.722081 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5886 12:16:39.722133
5887 12:16:39.722184
5888 12:16:39.722235 ==
5889 12:16:39.722287 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 12:16:39.722339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 12:16:39.722392 ==
5892 12:16:39.722443
5893 12:16:39.722494
5894 12:16:39.722544 TX Vref Scan disable
5895 12:16:39.722596 == TX Byte 0 ==
5896 12:16:39.722648 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5897 12:16:39.722700 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5898 12:16:39.722753 == TX Byte 1 ==
5899 12:16:39.722804 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5900 12:16:39.722857 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5901 12:16:39.722908 ==
5902 12:16:39.722961 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 12:16:39.723013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 12:16:39.723065 ==
5905 12:16:39.723117
5906 12:16:39.723168
5907 12:16:39.723219 TX Vref Scan disable
5908 12:16:39.723271 == TX Byte 0 ==
5909 12:16:39.723324 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5910 12:16:39.723386 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5911 12:16:39.723439 == TX Byte 1 ==
5912 12:16:39.723491 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5913 12:16:39.723544 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5914 12:16:39.723595
5915 12:16:39.723648 [DATLAT]
5916 12:16:39.723699 Freq=933, CH1 RK1
5917 12:16:39.723753
5918 12:16:39.723804 DATLAT Default: 0xb
5919 12:16:39.723857 0, 0xFFFF, sum = 0
5920 12:16:39.723910 1, 0xFFFF, sum = 0
5921 12:16:39.723963 2, 0xFFFF, sum = 0
5922 12:16:39.724015 3, 0xFFFF, sum = 0
5923 12:16:39.724068 4, 0xFFFF, sum = 0
5924 12:16:39.724120 5, 0xFFFF, sum = 0
5925 12:16:39.724173 6, 0xFFFF, sum = 0
5926 12:16:39.724226 7, 0xFFFF, sum = 0
5927 12:16:39.724278 8, 0xFFFF, sum = 0
5928 12:16:39.724330 9, 0xFFFF, sum = 0
5929 12:16:39.724382 10, 0x0, sum = 1
5930 12:16:39.724435 11, 0x0, sum = 2
5931 12:16:39.724487 12, 0x0, sum = 3
5932 12:16:39.724539 13, 0x0, sum = 4
5933 12:16:39.724591 best_step = 11
5934 12:16:39.724643
5935 12:16:39.724694 ==
5936 12:16:39.724746 Dram Type= 6, Freq= 0, CH_1, rank 1
5937 12:16:39.724798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5938 12:16:39.724851 ==
5939 12:16:39.724903 RX Vref Scan: 0
5940 12:16:39.724955
5941 12:16:39.725007 RX Vref 0 -> 0, step: 1
5942 12:16:39.725058
5943 12:16:39.725110 RX Delay -61 -> 252, step: 4
5944 12:16:39.725161 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5945 12:16:39.725213 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5946 12:16:39.725265 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5947 12:16:39.725317 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5948 12:16:39.725369 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5949 12:16:39.725420 iDelay=199, Bit 5, Center 104 (11 ~ 198) 188
5950 12:16:39.725473 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5951 12:16:39.725524 iDelay=199, Bit 7, Center 94 (-1 ~ 190) 192
5952 12:16:39.725577 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5953 12:16:39.725628 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5954 12:16:39.725680 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5955 12:16:39.725732 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5956 12:16:39.725783 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5957 12:16:39.725835 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5958 12:16:39.725887 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5959 12:16:39.725938 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5960 12:16:39.725990 ==
5961 12:16:39.726042 Dram Type= 6, Freq= 0, CH_1, rank 1
5962 12:16:39.726094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5963 12:16:39.726146 ==
5964 12:16:39.726198 DQS Delay:
5965 12:16:39.726250 DQS0 = 0, DQS1 = 0
5966 12:16:39.726301 DQM Delay:
5967 12:16:39.726353 DQM0 = 96, DQM1 = 92
5968 12:16:39.726405 DQ Delay:
5969 12:16:39.726457 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =94
5970 12:16:39.726509 DQ4 =96, DQ5 =104, DQ6 =104, DQ7 =94
5971 12:16:39.726561 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5972 12:16:39.726613 DQ12 =100, DQ13 =100, DQ14 =96, DQ15 =102
5973 12:16:39.726665
5974 12:16:39.726716
5975 12:16:39.726768 [DQSOSCAuto] RK1, (LSB)MR18= 0xf26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 417 ps
5976 12:16:39.726821 CH1 RK1: MR19=505, MR18=F26
5977 12:16:39.726873 CH1_RK1: MR19=0x505, MR18=0xF26, DQSOSC=409, MR23=63, INC=64, DEC=43
5978 12:16:39.726926 [RxdqsGatingPostProcess] freq 933
5979 12:16:39.727171 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5980 12:16:39.727233 best DQS0 dly(2T, 0.5T) = (0, 10)
5981 12:16:39.727287 best DQS1 dly(2T, 0.5T) = (0, 10)
5982 12:16:39.727340 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5983 12:16:39.727406 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5984 12:16:39.727460 best DQS0 dly(2T, 0.5T) = (0, 10)
5985 12:16:39.727512 best DQS1 dly(2T, 0.5T) = (0, 10)
5986 12:16:39.727564 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5987 12:16:39.727616 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5988 12:16:39.727668 Pre-setting of DQS Precalculation
5989 12:16:39.727721 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5990 12:16:40.494465 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5991 12:16:40.495019 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5992 12:16:40.495423
5993 12:16:40.495767
5994 12:16:40.496086 [Calibration Summary] 1866 Mbps
5995 12:16:40.496402 CH 0, Rank 0
5996 12:16:40.496671 SW Impedance : PASS
5997 12:16:40.496724 DUTY Scan : NO K
5998 12:16:40.496776 ZQ Calibration : PASS
5999 12:16:40.496828 Jitter Meter : NO K
6000 12:16:40.496880 CBT Training : PASS
6001 12:16:40.496931 Write leveling : PASS
6002 12:16:40.496982 RX DQS gating : PASS
6003 12:16:40.497033 RX DQ/DQS(RDDQC) : PASS
6004 12:16:40.497083 TX DQ/DQS : PASS
6005 12:16:40.497134 RX DATLAT : PASS
6006 12:16:40.497184 RX DQ/DQS(Engine): PASS
6007 12:16:40.497235 TX OE : NO K
6008 12:16:40.497287 All Pass.
6009 12:16:40.497337
6010 12:16:40.497388 CH 0, Rank 1
6011 12:16:40.497439 SW Impedance : PASS
6012 12:16:40.497506 DUTY Scan : NO K
6013 12:16:40.497569 ZQ Calibration : PASS
6014 12:16:40.497619 Jitter Meter : NO K
6015 12:16:40.497669 CBT Training : PASS
6016 12:16:40.497720 Write leveling : PASS
6017 12:16:40.497771 RX DQS gating : PASS
6018 12:16:40.497837 RX DQ/DQS(RDDQC) : PASS
6019 12:16:40.497888 TX DQ/DQS : PASS
6020 12:16:40.497952 RX DATLAT : PASS
6021 12:16:40.498002 RX DQ/DQS(Engine): PASS
6022 12:16:40.498052 TX OE : NO K
6023 12:16:40.498103 All Pass.
6024 12:16:40.498153
6025 12:16:40.498203 CH 1, Rank 0
6026 12:16:40.498253 SW Impedance : PASS
6027 12:16:40.498303 DUTY Scan : NO K
6028 12:16:40.498354 ZQ Calibration : PASS
6029 12:16:40.498403 Jitter Meter : NO K
6030 12:16:40.498454 CBT Training : PASS
6031 12:16:40.498504 Write leveling : PASS
6032 12:16:40.498554 RX DQS gating : PASS
6033 12:16:40.498604 RX DQ/DQS(RDDQC) : PASS
6034 12:16:40.498654 TX DQ/DQS : PASS
6035 12:16:40.498704 RX DATLAT : PASS
6036 12:16:40.498754 RX DQ/DQS(Engine): PASS
6037 12:16:40.498804 TX OE : NO K
6038 12:16:40.498855 All Pass.
6039 12:16:40.498905
6040 12:16:40.498954 CH 1, Rank 1
6041 12:16:40.499004 SW Impedance : PASS
6042 12:16:40.499054 DUTY Scan : NO K
6043 12:16:40.499104 ZQ Calibration : PASS
6044 12:16:40.499154 Jitter Meter : NO K
6045 12:16:40.499204 CBT Training : PASS
6046 12:16:40.499254 Write leveling : PASS
6047 12:16:40.499304 RX DQS gating : PASS
6048 12:16:40.499354 RX DQ/DQS(RDDQC) : PASS
6049 12:16:40.499408 TX DQ/DQS : PASS
6050 12:16:40.499459 RX DATLAT : PASS
6051 12:16:40.499509 RX DQ/DQS(Engine): PASS
6052 12:16:40.499559 TX OE : NO K
6053 12:16:40.499609 All Pass.
6054 12:16:40.499658
6055 12:16:40.499708 DramC Write-DBI off
6056 12:16:40.499758 PER_BANK_REFRESH: Hybrid Mode
6057 12:16:40.499808 TX_TRACKING: ON
6058 12:16:40.499859 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6059 12:16:40.499910 [FAST_K] Save calibration result to emmc
6060 12:16:40.499961 dramc_set_vcore_voltage set vcore to 650000
6061 12:16:40.500011 Read voltage for 400, 6
6062 12:16:40.500061 Vio18 = 0
6063 12:16:40.500112 Vcore = 650000
6064 12:16:40.500162 Vdram = 0
6065 12:16:40.500212 Vddq = 0
6066 12:16:40.500262 Vmddr = 0
6067 12:16:40.500312 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6068 12:16:40.500364 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6069 12:16:40.500415 MEM_TYPE=3, freq_sel=20
6070 12:16:40.500465 sv_algorithm_assistance_LP4_800
6071 12:16:40.500516 ============ PULL DRAM RESETB DOWN ============
6072 12:16:40.500567 ========== PULL DRAM RESETB DOWN end =========
6073 12:16:40.500618 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6074 12:16:40.500668 ===================================
6075 12:16:40.500719 LPDDR4 DRAM CONFIGURATION
6076 12:16:40.500770 ===================================
6077 12:16:40.500820 EX_ROW_EN[0] = 0x0
6078 12:16:40.500870 EX_ROW_EN[1] = 0x0
6079 12:16:40.500920 LP4Y_EN = 0x0
6080 12:16:40.500971 WORK_FSP = 0x0
6081 12:16:40.501021 WL = 0x2
6082 12:16:40.501071 RL = 0x2
6083 12:16:40.501120 BL = 0x2
6084 12:16:40.501170 RPST = 0x0
6085 12:16:40.501219 RD_PRE = 0x0
6086 12:16:40.501269 WR_PRE = 0x1
6087 12:16:40.501319 WR_PST = 0x0
6088 12:16:40.501370 DBI_WR = 0x0
6089 12:16:40.501420 DBI_RD = 0x0
6090 12:16:40.501469 OTF = 0x1
6091 12:16:40.501520 ===================================
6092 12:16:40.501571 ===================================
6093 12:16:40.501621 ANA top config
6094 12:16:40.501671 ===================================
6095 12:16:40.501722 DLL_ASYNC_EN = 0
6096 12:16:40.501772 ALL_SLAVE_EN = 1
6097 12:16:40.501821 NEW_RANK_MODE = 1
6098 12:16:40.501873 DLL_IDLE_MODE = 1
6099 12:16:40.501924 LP45_APHY_COMB_EN = 1
6100 12:16:40.501977 TX_ODT_DIS = 1
6101 12:16:40.502028 NEW_8X_MODE = 1
6102 12:16:40.502079 ===================================
6103 12:16:40.502130 ===================================
6104 12:16:40.502181 data_rate = 800
6105 12:16:40.502232 CKR = 1
6106 12:16:40.502282 DQ_P2S_RATIO = 4
6107 12:16:40.502332 ===================================
6108 12:16:40.502383 CA_P2S_RATIO = 4
6109 12:16:40.502434 DQ_CA_OPEN = 0
6110 12:16:40.502484 DQ_SEMI_OPEN = 1
6111 12:16:40.502534 CA_SEMI_OPEN = 1
6112 12:16:40.502585 CA_FULL_RATE = 0
6113 12:16:40.502635 DQ_CKDIV4_EN = 0
6114 12:16:40.502685 CA_CKDIV4_EN = 1
6115 12:16:40.502736 CA_PREDIV_EN = 0
6116 12:16:40.502786 PH8_DLY = 0
6117 12:16:40.502837 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6118 12:16:40.502887 DQ_AAMCK_DIV = 0
6119 12:16:40.502938 CA_AAMCK_DIV = 0
6120 12:16:40.502988 CA_ADMCK_DIV = 4
6121 12:16:40.503039 DQ_TRACK_CA_EN = 0
6122 12:16:40.503090 CA_PICK = 800
6123 12:16:40.503141 CA_MCKIO = 400
6124 12:16:40.503436 MCKIO_SEMI = 400
6125 12:16:40.503561 PLL_FREQ = 3016
6126 12:16:40.503666 DQ_UI_PI_RATIO = 32
6127 12:16:40.503769 CA_UI_PI_RATIO = 32
6128 12:16:40.503873 ===================================
6129 12:16:40.503973 ===================================
6130 12:16:40.504063 memory_type:LPDDR4
6131 12:16:40.504140 GP_NUM : 10
6132 12:16:40.504194 SRAM_EN : 1
6133 12:16:40.504246 MD32_EN : 0
6134 12:16:40.504298 ===================================
6135 12:16:40.504350 [ANA_INIT] >>>>>>>>>>>>>>
6136 12:16:40.504402 <<<<<< [CONFIGURE PHASE]: ANA_TX
6137 12:16:40.504453 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6138 12:16:40.504505 ===================================
6139 12:16:40.504555 data_rate = 800,PCW = 0X7400
6140 12:16:40.504607 ===================================
6141 12:16:40.504658 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6142 12:16:40.504710 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6143 12:16:40.504762 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6144 12:16:40.504814 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6145 12:16:40.504865 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6146 12:16:40.504916 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6147 12:16:40.504966 [ANA_INIT] flow start
6148 12:16:40.505017 [ANA_INIT] PLL >>>>>>>>
6149 12:16:40.505069 [ANA_INIT] PLL <<<<<<<<
6150 12:16:40.505120 [ANA_INIT] MIDPI >>>>>>>>
6151 12:16:40.505171 [ANA_INIT] MIDPI <<<<<<<<
6152 12:16:40.505221 [ANA_INIT] DLL >>>>>>>>
6153 12:16:40.505272 [ANA_INIT] flow end
6154 12:16:40.505323 ============ LP4 DIFF to SE enter ============
6155 12:16:40.505375 ============ LP4 DIFF to SE exit ============
6156 12:16:40.505426 [ANA_INIT] <<<<<<<<<<<<<
6157 12:16:40.505477 [Flow] Enable top DCM control >>>>>
6158 12:16:40.505528 [Flow] Enable top DCM control <<<<<
6159 12:16:40.505579 Enable DLL master slave shuffle
6160 12:16:40.505629 ==============================================================
6161 12:16:40.505680 Gating Mode config
6162 12:16:40.505732 ==============================================================
6163 12:16:40.505783 Config description:
6164 12:16:40.505834 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6165 12:16:40.505886 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6166 12:16:40.505937 SELPH_MODE 0: By rank 1: By Phase
6167 12:16:40.505988 ==============================================================
6168 12:16:40.506039 GAT_TRACK_EN = 0
6169 12:16:40.506090 RX_GATING_MODE = 2
6170 12:16:40.506140 RX_GATING_TRACK_MODE = 2
6171 12:16:40.506190 SELPH_MODE = 1
6172 12:16:40.506241 PICG_EARLY_EN = 1
6173 12:16:40.506291 VALID_LAT_VALUE = 1
6174 12:16:40.506342 ==============================================================
6175 12:16:40.506393 Enter into Gating configuration >>>>
6176 12:16:40.506444 Exit from Gating configuration <<<<
6177 12:16:40.506494 Enter into DVFS_PRE_config >>>>>
6178 12:16:40.506546 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6179 12:16:40.506598 Exit from DVFS_PRE_config <<<<<
6180 12:16:40.506648 Enter into PICG configuration >>>>
6181 12:16:40.506699 Exit from PICG configuration <<<<
6182 12:16:40.506750 [RX_INPUT] configuration >>>>>
6183 12:16:40.506801 [RX_INPUT] configuration <<<<<
6184 12:16:40.506852 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6185 12:16:40.506903 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6186 12:16:40.506954 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6187 12:16:40.507005 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6188 12:16:40.507057 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6189 12:16:40.507108 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6190 12:16:40.507160 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6191 12:16:40.507210 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6192 12:16:40.507262 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6193 12:16:40.507313 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6194 12:16:40.507368 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6195 12:16:40.507419 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6196 12:16:40.507471 ===================================
6197 12:16:40.507522 LPDDR4 DRAM CONFIGURATION
6198 12:16:40.507573 ===================================
6199 12:16:40.507624 EX_ROW_EN[0] = 0x0
6200 12:16:40.507675 EX_ROW_EN[1] = 0x0
6201 12:16:40.507726 LP4Y_EN = 0x0
6202 12:16:40.507777 WORK_FSP = 0x0
6203 12:16:40.507827 WL = 0x2
6204 12:16:40.507878 RL = 0x2
6205 12:16:40.507928 BL = 0x2
6206 12:16:40.507978 RPST = 0x0
6207 12:16:40.508029 RD_PRE = 0x0
6208 12:16:40.508079 WR_PRE = 0x1
6209 12:16:40.508129 WR_PST = 0x0
6210 12:16:40.508179 DBI_WR = 0x0
6211 12:16:40.508230 DBI_RD = 0x0
6212 12:16:40.508280 OTF = 0x1
6213 12:16:40.508331 ===================================
6214 12:16:40.508381 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6215 12:16:40.508432 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6216 12:16:40.508483 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6217 12:16:40.508535 ===================================
6218 12:16:40.508585 LPDDR4 DRAM CONFIGURATION
6219 12:16:40.508636 ===================================
6220 12:16:40.508687 EX_ROW_EN[0] = 0x10
6221 12:16:40.508737 EX_ROW_EN[1] = 0x0
6222 12:16:40.508788 LP4Y_EN = 0x0
6223 12:16:40.508838 WORK_FSP = 0x0
6224 12:16:40.508889 WL = 0x2
6225 12:16:40.508939 RL = 0x2
6226 12:16:40.508989 BL = 0x2
6227 12:16:40.509039 RPST = 0x0
6228 12:16:40.509090 RD_PRE = 0x0
6229 12:16:40.509141 WR_PRE = 0x1
6230 12:16:40.509191 WR_PST = 0x0
6231 12:16:40.509443 DBI_WR = 0x0
6232 12:16:40.509541 DBI_RD = 0x0
6233 12:16:40.509624 OTF = 0x1
6234 12:16:40.509706 ===================================
6235 12:16:40.509789 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6236 12:16:40.509870 nWR fixed to 30
6237 12:16:40.509964 [ModeRegInit_LP4] CH0 RK0
6238 12:16:40.510044 [ModeRegInit_LP4] CH0 RK1
6239 12:16:40.510123 [ModeRegInit_LP4] CH1 RK0
6240 12:16:40.510202 [ModeRegInit_LP4] CH1 RK1
6241 12:16:40.510280 match AC timing 19
6242 12:16:40.510363 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6243 12:16:40.510442 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6244 12:16:40.510522 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6245 12:16:40.510603 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6246 12:16:40.510682 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6247 12:16:40.510761 ==
6248 12:16:40.510841 Dram Type= 6, Freq= 0, CH_0, rank 0
6249 12:16:40.510920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6250 12:16:40.510999 ==
6251 12:16:40.511079 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6252 12:16:40.511159 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6253 12:16:40.511239 [CA 0] Center 36 (8~64) winsize 57
6254 12:16:40.511318 [CA 1] Center 36 (8~64) winsize 57
6255 12:16:40.511435 [CA 2] Center 36 (8~64) winsize 57
6256 12:16:40.511515 [CA 3] Center 36 (8~64) winsize 57
6257 12:16:40.511594 [CA 4] Center 36 (8~64) winsize 57
6258 12:16:40.511673 [CA 5] Center 36 (8~64) winsize 57
6259 12:16:40.511752
6260 12:16:40.511831 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6261 12:16:40.511910
6262 12:16:40.511988 [CATrainingPosCal] consider 1 rank data
6263 12:16:40.512068 u2DelayCellTimex100 = 270/100 ps
6264 12:16:40.512147 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 12:16:40.512227 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 12:16:40.512306 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 12:16:40.512385 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 12:16:40.512464 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 12:16:40.512544 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 12:16:40.512622
6271 12:16:40.512701 CA PerBit enable=1, Macro0, CA PI delay=36
6272 12:16:40.512779
6273 12:16:40.512858 [CBTSetCACLKResult] CA Dly = 36
6274 12:16:40.512937 CS Dly: 1 (0~32)
6275 12:16:40.513021 ==
6276 12:16:40.513102 Dram Type= 6, Freq= 0, CH_0, rank 1
6277 12:16:40.513182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 12:16:40.513261 ==
6279 12:16:40.513341 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6280 12:16:40.513422 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6281 12:16:40.513501 [CA 0] Center 36 (8~64) winsize 57
6282 12:16:40.513580 [CA 1] Center 36 (8~64) winsize 57
6283 12:16:40.513659 [CA 2] Center 36 (8~64) winsize 57
6284 12:16:40.513738 [CA 3] Center 36 (8~64) winsize 57
6285 12:16:40.513817 [CA 4] Center 36 (8~64) winsize 57
6286 12:16:40.513896 [CA 5] Center 36 (8~64) winsize 57
6287 12:16:40.513975
6288 12:16:40.514054 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6289 12:16:40.514133
6290 12:16:40.514212 [CATrainingPosCal] consider 2 rank data
6291 12:16:40.514291 u2DelayCellTimex100 = 270/100 ps
6292 12:16:40.514370 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 12:16:40.514449 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 12:16:40.514529 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 12:16:40.514608 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 12:16:40.514688 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 12:16:40.514767 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 12:16:40.514845
6299 12:16:40.514924 CA PerBit enable=1, Macro0, CA PI delay=36
6300 12:16:40.515003
6301 12:16:40.515100 [CBTSetCACLKResult] CA Dly = 36
6302 12:16:40.515192 CS Dly: 1 (0~32)
6303 12:16:40.515271
6304 12:16:40.515350 ----->DramcWriteLeveling(PI) begin...
6305 12:16:40.515453 ==
6306 12:16:40.515506 Dram Type= 6, Freq= 0, CH_0, rank 0
6307 12:16:40.515558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6308 12:16:40.515609 ==
6309 12:16:40.515661 Write leveling (Byte 0): 40 => 8
6310 12:16:40.515712 Write leveling (Byte 1): 40 => 8
6311 12:16:40.515764 DramcWriteLeveling(PI) end<-----
6312 12:16:40.515815
6313 12:16:40.515866 ==
6314 12:16:40.515917 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 12:16:40.515968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 12:16:40.516019 ==
6317 12:16:40.516069 [Gating] SW mode calibration
6318 12:16:40.516121 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6319 12:16:40.516173 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6320 12:16:40.516224 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6321 12:16:40.516276 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6322 12:16:40.516327 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6323 12:16:40.516378 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6324 12:16:40.516429 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6325 12:16:40.516481 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6326 12:16:40.516532 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6327 12:16:40.516582 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6328 12:16:40.516634 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6329 12:16:40.516685 Total UI for P1: 0, mck2ui 16
6330 12:16:40.516736 best dqsien dly found for B0: ( 0, 14, 24)
6331 12:16:40.516788 Total UI for P1: 0, mck2ui 16
6332 12:16:40.516839 best dqsien dly found for B1: ( 0, 14, 24)
6333 12:16:40.516890 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6334 12:16:40.516941 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6335 12:16:40.516992
6336 12:16:40.517043 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6337 12:16:40.517095 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6338 12:16:40.517145 [Gating] SW calibration Done
6339 12:16:40.517197 ==
6340 12:16:40.517248 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 12:16:40.517299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 12:16:40.517350 ==
6343 12:16:40.517400 RX Vref Scan: 0
6344 12:16:40.517450
6345 12:16:40.517500 RX Vref 0 -> 0, step: 1
6346 12:16:40.517551
6347 12:16:40.517601 RX Delay -410 -> 252, step: 16
6348 12:16:40.517652 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6349 12:16:40.517704 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6350 12:16:40.517755 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6351 12:16:40.517806 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6352 12:16:40.518046 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6353 12:16:40.518127 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6354 12:16:40.518180 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6355 12:16:40.518232 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6356 12:16:40.518284 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6357 12:16:40.518336 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6358 12:16:40.518388 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6359 12:16:40.518440 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6360 12:16:40.518491 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6361 12:16:40.518569 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6362 12:16:40.518620 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6363 12:16:40.518672 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6364 12:16:40.518723 ==
6365 12:16:40.518774 Dram Type= 6, Freq= 0, CH_0, rank 0
6366 12:16:40.518825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6367 12:16:40.518877 ==
6368 12:16:40.518928 DQS Delay:
6369 12:16:40.518979 DQS0 = 35, DQS1 = 59
6370 12:16:40.519031 DQM Delay:
6371 12:16:40.519081 DQM0 = 4, DQM1 = 17
6372 12:16:40.519132 DQ Delay:
6373 12:16:40.519183 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6374 12:16:40.519235 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6375 12:16:40.519286 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6376 12:16:40.519337 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6377 12:16:40.519402
6378 12:16:40.519454
6379 12:16:40.519505 ==
6380 12:16:40.519557 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 12:16:40.519608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 12:16:40.519660 ==
6383 12:16:40.519712
6384 12:16:40.519762
6385 12:16:40.519813 TX Vref Scan disable
6386 12:16:40.519865 == TX Byte 0 ==
6387 12:16:40.519916 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6388 12:16:40.519968 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6389 12:16:40.520019 == TX Byte 1 ==
6390 12:16:40.520070 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6391 12:16:40.520122 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6392 12:16:40.520172 ==
6393 12:16:40.520224 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 12:16:40.520275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 12:16:40.520326 ==
6396 12:16:40.520377
6397 12:16:40.520428
6398 12:16:40.520479 TX Vref Scan disable
6399 12:16:40.520531 == TX Byte 0 ==
6400 12:16:40.520582 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6401 12:16:40.520634 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6402 12:16:40.520686 == TX Byte 1 ==
6403 12:16:40.520739 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6404 12:16:40.520791 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6405 12:16:40.520841
6406 12:16:40.520892 [DATLAT]
6407 12:16:40.520943 Freq=400, CH0 RK0
6408 12:16:40.520995
6409 12:16:40.521046 DATLAT Default: 0xf
6410 12:16:40.521097 0, 0xFFFF, sum = 0
6411 12:16:40.521150 1, 0xFFFF, sum = 0
6412 12:16:40.521203 2, 0xFFFF, sum = 0
6413 12:16:40.521255 3, 0xFFFF, sum = 0
6414 12:16:40.521307 4, 0xFFFF, sum = 0
6415 12:16:40.521359 5, 0xFFFF, sum = 0
6416 12:16:40.521411 6, 0xFFFF, sum = 0
6417 12:16:40.521463 7, 0xFFFF, sum = 0
6418 12:16:40.521515 8, 0xFFFF, sum = 0
6419 12:16:40.521566 9, 0xFFFF, sum = 0
6420 12:16:40.521617 10, 0xFFFF, sum = 0
6421 12:16:40.521669 11, 0xFFFF, sum = 0
6422 12:16:40.521721 12, 0xFFFF, sum = 0
6423 12:16:40.521773 13, 0x0, sum = 1
6424 12:16:40.521825 14, 0x0, sum = 2
6425 12:16:40.521877 15, 0x0, sum = 3
6426 12:16:40.521929 16, 0x0, sum = 4
6427 12:16:40.521980 best_step = 14
6428 12:16:40.522031
6429 12:16:40.522082 ==
6430 12:16:40.522133 Dram Type= 6, Freq= 0, CH_0, rank 0
6431 12:16:40.522185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 12:16:40.522236 ==
6433 12:16:40.522287 RX Vref Scan: 1
6434 12:16:40.522338
6435 12:16:40.522389 RX Vref 0 -> 0, step: 1
6436 12:16:40.522439
6437 12:16:40.522490 RX Delay -359 -> 252, step: 8
6438 12:16:40.522541
6439 12:16:40.522592 Set Vref, RX VrefLevel [Byte0]: 53
6440 12:16:40.522644 [Byte1]: 59
6441 12:16:40.522695
6442 12:16:40.522754 Final RX Vref Byte 0 = 53 to rank0
6443 12:16:40.522810 Final RX Vref Byte 1 = 59 to rank0
6444 12:16:40.522864 Final RX Vref Byte 0 = 53 to rank1
6445 12:16:40.522919 Final RX Vref Byte 1 = 59 to rank1==
6446 12:16:40.522971 Dram Type= 6, Freq= 0, CH_0, rank 0
6447 12:16:40.523023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 12:16:40.523075 ==
6449 12:16:40.523126 DQS Delay:
6450 12:16:40.523176 DQS0 = 44, DQS1 = 60
6451 12:16:40.523228 DQM Delay:
6452 12:16:40.523279 DQM0 = 10, DQM1 = 16
6453 12:16:40.523330 DQ Delay:
6454 12:16:40.523422 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6455 12:16:40.523475 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6456 12:16:40.523525 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6457 12:16:40.523576 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6458 12:16:40.523627
6459 12:16:40.523678
6460 12:16:40.523729 [DQSOSCAuto] RK0, (LSB)MR18= 0x968a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6461 12:16:40.523781 CH0 RK0: MR19=C0C, MR18=968A
6462 12:16:40.523832 CH0_RK0: MR19=0xC0C, MR18=0x968A, DQSOSC=391, MR23=63, INC=386, DEC=257
6463 12:16:40.523884 ==
6464 12:16:40.523935 Dram Type= 6, Freq= 0, CH_0, rank 1
6465 12:16:40.523986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 12:16:40.524038 ==
6467 12:16:40.524089 [Gating] SW mode calibration
6468 12:16:40.524140 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6469 12:16:40.524192 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6470 12:16:40.524244 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6471 12:16:40.524295 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6472 12:16:40.524346 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6473 12:16:40.524398 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6474 12:16:40.524448 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 12:16:40.524499 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6476 12:16:40.524550 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6477 12:16:40.524601 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6478 12:16:40.524652 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6479 12:16:40.524702 Total UI for P1: 0, mck2ui 16
6480 12:16:40.524753 best dqsien dly found for B0: ( 0, 14, 24)
6481 12:16:40.524804 Total UI for P1: 0, mck2ui 16
6482 12:16:40.524856 best dqsien dly found for B1: ( 0, 14, 24)
6483 12:16:40.524907 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6484 12:16:40.524958 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6485 12:16:40.525010
6486 12:16:40.525063 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6487 12:16:40.525115 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6488 12:16:40.525166 [Gating] SW calibration Done
6489 12:16:40.525217 ==
6490 12:16:40.525269 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 12:16:40.525321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 12:16:40.525372 ==
6493 12:16:40.525423 RX Vref Scan: 0
6494 12:16:40.525474
6495 12:16:40.525714 RX Vref 0 -> 0, step: 1
6496 12:16:40.525772
6497 12:16:40.525824 RX Delay -410 -> 252, step: 16
6498 12:16:40.525877 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6499 12:16:40.525929 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6500 12:16:40.525980 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6501 12:16:40.526032 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6502 12:16:40.526083 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6503 12:16:40.526135 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6504 12:16:40.526186 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6505 12:16:40.526237 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6506 12:16:40.526288 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6507 12:16:40.526339 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6508 12:16:40.526390 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6509 12:16:40.526441 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6510 12:16:40.526492 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6511 12:16:40.526543 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6512 12:16:40.526593 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6513 12:16:40.526643 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6514 12:16:40.526694 ==
6515 12:16:40.526745 Dram Type= 6, Freq= 0, CH_0, rank 1
6516 12:16:40.526797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6517 12:16:40.526848 ==
6518 12:16:40.526899 DQS Delay:
6519 12:16:40.526950 DQS0 = 35, DQS1 = 51
6520 12:16:40.527002 DQM Delay:
6521 12:16:40.527053 DQM0 = 7, DQM1 = 10
6522 12:16:40.527104 DQ Delay:
6523 12:16:40.527155 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6524 12:16:40.527208 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6525 12:16:40.527259 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6526 12:16:40.527310 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6527 12:16:40.527369
6528 12:16:40.527426
6529 12:16:40.527477 ==
6530 12:16:40.527528 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 12:16:40.527580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 12:16:40.527631 ==
6533 12:16:40.527683
6534 12:16:40.527733
6535 12:16:40.527784 TX Vref Scan disable
6536 12:16:40.527836 == TX Byte 0 ==
6537 12:16:40.527887 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6538 12:16:40.527938 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6539 12:16:40.527990 == TX Byte 1 ==
6540 12:16:40.528041 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6541 12:16:40.528092 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6542 12:16:40.528142 ==
6543 12:16:40.528193 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 12:16:40.528245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 12:16:40.528296 ==
6546 12:16:40.528347
6547 12:16:40.528398
6548 12:16:40.528448 TX Vref Scan disable
6549 12:16:40.528500 == TX Byte 0 ==
6550 12:16:40.528564 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6551 12:16:40.528614 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6552 12:16:40.528664 == TX Byte 1 ==
6553 12:16:40.528714 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6554 12:16:40.528764 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6555 12:16:40.528814
6556 12:16:40.528864 [DATLAT]
6557 12:16:40.528914 Freq=400, CH0 RK1
6558 12:16:40.528964
6559 12:16:40.529014 DATLAT Default: 0xe
6560 12:16:40.529064 0, 0xFFFF, sum = 0
6561 12:16:40.529115 1, 0xFFFF, sum = 0
6562 12:16:40.529167 2, 0xFFFF, sum = 0
6563 12:16:40.529218 3, 0xFFFF, sum = 0
6564 12:16:40.529268 4, 0xFFFF, sum = 0
6565 12:16:40.529319 5, 0xFFFF, sum = 0
6566 12:16:40.529369 6, 0xFFFF, sum = 0
6567 12:16:40.529421 7, 0xFFFF, sum = 0
6568 12:16:40.529472 8, 0xFFFF, sum = 0
6569 12:16:40.529523 9, 0xFFFF, sum = 0
6570 12:16:40.529574 10, 0xFFFF, sum = 0
6571 12:16:40.529624 11, 0xFFFF, sum = 0
6572 12:16:40.529675 12, 0xFFFF, sum = 0
6573 12:16:40.529726 13, 0x0, sum = 1
6574 12:16:40.529776 14, 0x0, sum = 2
6575 12:16:40.529827 15, 0x0, sum = 3
6576 12:16:40.529878 16, 0x0, sum = 4
6577 12:16:40.529929 best_step = 14
6578 12:16:40.529979
6579 12:16:40.530030 ==
6580 12:16:40.530080 Dram Type= 6, Freq= 0, CH_0, rank 1
6581 12:16:40.530131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6582 12:16:40.530182 ==
6583 12:16:40.530232 RX Vref Scan: 0
6584 12:16:40.530282
6585 12:16:40.530331 RX Vref 0 -> 0, step: 1
6586 12:16:40.530381
6587 12:16:40.530431 RX Delay -343 -> 252, step: 8
6588 12:16:40.530481 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6589 12:16:40.530532 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6590 12:16:40.530582 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6591 12:16:40.530632 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6592 12:16:40.530682 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6593 12:16:40.530732 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6594 12:16:40.530782 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6595 12:16:40.530832 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6596 12:16:40.530882 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6597 12:16:40.530932 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6598 12:16:40.530982 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6599 12:16:40.531032 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6600 12:16:40.531082 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6601 12:16:40.531131 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6602 12:16:40.531181 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6603 12:16:40.531231 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6604 12:16:40.531281 ==
6605 12:16:40.531331 Dram Type= 6, Freq= 0, CH_0, rank 1
6606 12:16:40.531422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6607 12:16:40.531475 ==
6608 12:16:40.531526 DQS Delay:
6609 12:16:40.531577 DQS0 = 44, DQS1 = 60
6610 12:16:40.531628 DQM Delay:
6611 12:16:40.531678 DQM0 = 9, DQM1 = 15
6612 12:16:40.531728 DQ Delay:
6613 12:16:40.531779 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6614 12:16:40.531830 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6615 12:16:40.531880 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6616 12:16:40.531930 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6617 12:16:40.531980
6618 12:16:40.532030
6619 12:16:40.532080 [DQSOSCAuto] RK1, (LSB)MR18= 0x8984, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6620 12:16:40.532131 CH0 RK1: MR19=C0C, MR18=8984
6621 12:16:40.532182 CH0_RK1: MR19=0xC0C, MR18=0x8984, DQSOSC=392, MR23=63, INC=384, DEC=256
6622 12:16:40.532233 [RxdqsGatingPostProcess] freq 400
6623 12:16:40.532283 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6624 12:16:40.532334 best DQS0 dly(2T, 0.5T) = (0, 10)
6625 12:16:40.532384 best DQS1 dly(2T, 0.5T) = (0, 10)
6626 12:16:40.532434 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6627 12:16:40.532484 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6628 12:16:40.532533 best DQS0 dly(2T, 0.5T) = (0, 10)
6629 12:16:40.532583 best DQS1 dly(2T, 0.5T) = (0, 10)
6630 12:16:40.532633 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6631 12:16:40.532878 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6632 12:16:40.532948 Pre-setting of DQS Precalculation
6633 12:16:40.533052 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6634 12:16:40.533154 ==
6635 12:16:40.533256 Dram Type= 6, Freq= 0, CH_1, rank 0
6636 12:16:40.533357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 12:16:40.533445 ==
6638 12:16:40.533508 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6639 12:16:40.533560 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6640 12:16:40.533612 [CA 0] Center 36 (8~64) winsize 57
6641 12:16:40.533669 [CA 1] Center 36 (8~64) winsize 57
6642 12:16:40.533720 [CA 2] Center 36 (8~64) winsize 57
6643 12:16:40.533771 [CA 3] Center 36 (8~64) winsize 57
6644 12:16:40.533821 [CA 4] Center 36 (8~64) winsize 57
6645 12:16:40.533872 [CA 5] Center 36 (8~64) winsize 57
6646 12:16:40.533923
6647 12:16:40.533974 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6648 12:16:40.534024
6649 12:16:40.534074 [CATrainingPosCal] consider 1 rank data
6650 12:16:40.534125 u2DelayCellTimex100 = 270/100 ps
6651 12:16:40.534175 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 12:16:40.534226 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 12:16:40.534276 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 12:16:40.534329 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 12:16:40.534380 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 12:16:40.534430 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 12:16:40.534480
6658 12:16:40.534545 CA PerBit enable=1, Macro0, CA PI delay=36
6659 12:16:40.534597
6660 12:16:40.534648 [CBTSetCACLKResult] CA Dly = 36
6661 12:16:40.534707 CS Dly: 1 (0~32)
6662 12:16:40.534760 ==
6663 12:16:40.534811 Dram Type= 6, Freq= 0, CH_1, rank 1
6664 12:16:40.534862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 12:16:40.534923 ==
6666 12:16:40.534975 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6667 12:16:40.535026 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6668 12:16:40.535086 [CA 0] Center 36 (8~64) winsize 57
6669 12:16:40.535166 [CA 1] Center 36 (8~64) winsize 57
6670 12:16:40.535246 [CA 2] Center 36 (8~64) winsize 57
6671 12:16:40.535328 [CA 3] Center 36 (8~64) winsize 57
6672 12:16:40.535446 [CA 4] Center 36 (8~64) winsize 57
6673 12:16:40.535500 [CA 5] Center 36 (8~64) winsize 57
6674 12:16:40.535551
6675 12:16:40.535602 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6676 12:16:40.535656
6677 12:16:40.535707 [CATrainingPosCal] consider 2 rank data
6678 12:16:40.535758 u2DelayCellTimex100 = 270/100 ps
6679 12:16:40.535811 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 12:16:40.535862 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 12:16:40.535913 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 12:16:40.535963 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 12:16:40.536014 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 12:16:40.536064 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 12:16:40.536116
6686 12:16:40.536166 CA PerBit enable=1, Macro0, CA PI delay=36
6687 12:16:40.536216
6688 12:16:40.536266 [CBTSetCACLKResult] CA Dly = 36
6689 12:16:40.536317 CS Dly: 1 (0~32)
6690 12:16:40.536367
6691 12:16:40.536418 ----->DramcWriteLeveling(PI) begin...
6692 12:16:40.536469 ==
6693 12:16:40.536521 Dram Type= 6, Freq= 0, CH_1, rank 0
6694 12:16:40.536571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6695 12:16:40.536622 ==
6696 12:16:40.536672 Write leveling (Byte 0): 40 => 8
6697 12:16:40.536722 Write leveling (Byte 1): 40 => 8
6698 12:16:40.536772 DramcWriteLeveling(PI) end<-----
6699 12:16:40.536823
6700 12:16:40.536872 ==
6701 12:16:40.536922 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 12:16:40.536973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 12:16:40.537023 ==
6704 12:16:40.537074 [Gating] SW mode calibration
6705 12:16:40.537124 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6706 12:16:40.537176 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6707 12:16:40.537227 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6708 12:16:40.537278 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6709 12:16:40.537328 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6710 12:16:40.537379 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6711 12:16:40.537429 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6712 12:16:40.537479 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6713 12:16:40.537530 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6714 12:16:40.537580 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6715 12:16:40.537631 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6716 12:16:40.537681 Total UI for P1: 0, mck2ui 16
6717 12:16:40.537732 best dqsien dly found for B0: ( 0, 14, 24)
6718 12:16:40.537783 Total UI for P1: 0, mck2ui 16
6719 12:16:40.537834 best dqsien dly found for B1: ( 0, 14, 24)
6720 12:16:40.537884 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6721 12:16:40.537935 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6722 12:16:40.537986
6723 12:16:40.538036 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6724 12:16:40.538087 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6725 12:16:40.538138 [Gating] SW calibration Done
6726 12:16:40.538190 ==
6727 12:16:40.538242 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 12:16:40.538292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 12:16:40.538343 ==
6730 12:16:40.538393 RX Vref Scan: 0
6731 12:16:40.538443
6732 12:16:40.538493 RX Vref 0 -> 0, step: 1
6733 12:16:40.538543
6734 12:16:40.538593 RX Delay -410 -> 252, step: 16
6735 12:16:40.538643 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6736 12:16:40.538694 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6737 12:16:40.538744 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6738 12:16:40.538795 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6739 12:16:40.538845 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6740 12:16:40.538895 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6741 12:16:40.538945 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6742 12:16:40.538996 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6743 12:16:40.539046 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6744 12:16:40.539097 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6745 12:16:40.539148 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6746 12:16:40.539198 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6747 12:16:40.539248 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6748 12:16:40.539299 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6749 12:16:40.539541 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6750 12:16:40.539634 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6751 12:16:40.539737 ==
6752 12:16:40.539840 Dram Type= 6, Freq= 0, CH_1, rank 0
6753 12:16:40.539943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6754 12:16:40.540044 ==
6755 12:16:40.540133 DQS Delay:
6756 12:16:40.540214 DQS0 = 35, DQS1 = 51
6757 12:16:40.540268 DQM Delay:
6758 12:16:40.540319 DQM0 = 6, DQM1 = 14
6759 12:16:40.540370 DQ Delay:
6760 12:16:40.540421 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6761 12:16:40.540472 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6762 12:16:40.540523 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6763 12:16:40.540575 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =16
6764 12:16:40.540626
6765 12:16:40.540676
6766 12:16:40.540739 ==
6767 12:16:40.540791 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 12:16:40.540842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 12:16:40.540895 ==
6770 12:16:40.540946
6771 12:16:40.540997
6772 12:16:40.541047 TX Vref Scan disable
6773 12:16:40.541099 == TX Byte 0 ==
6774 12:16:40.541151 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6775 12:16:40.541203 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6776 12:16:40.541255 == TX Byte 1 ==
6777 12:16:40.541307 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6778 12:16:40.541358 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6779 12:16:40.541409 ==
6780 12:16:40.541461 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 12:16:40.541513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 12:16:40.541565 ==
6783 12:16:40.541617
6784 12:16:40.541668
6785 12:16:40.541718 TX Vref Scan disable
6786 12:16:40.541770 == TX Byte 0 ==
6787 12:16:40.541821 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6788 12:16:40.541873 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6789 12:16:40.541923 == TX Byte 1 ==
6790 12:16:40.541975 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6791 12:16:40.542026 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6792 12:16:40.542077
6793 12:16:40.542128 [DATLAT]
6794 12:16:40.542179 Freq=400, CH1 RK0
6795 12:16:40.542231
6796 12:16:40.542283 DATLAT Default: 0xf
6797 12:16:40.542334 0, 0xFFFF, sum = 0
6798 12:16:40.542387 1, 0xFFFF, sum = 0
6799 12:16:40.542439 2, 0xFFFF, sum = 0
6800 12:16:40.542491 3, 0xFFFF, sum = 0
6801 12:16:40.542543 4, 0xFFFF, sum = 0
6802 12:16:40.542596 5, 0xFFFF, sum = 0
6803 12:16:40.542648 6, 0xFFFF, sum = 0
6804 12:16:40.542700 7, 0xFFFF, sum = 0
6805 12:16:40.542751 8, 0xFFFF, sum = 0
6806 12:16:40.542803 9, 0xFFFF, sum = 0
6807 12:16:40.542856 10, 0xFFFF, sum = 0
6808 12:16:40.542909 11, 0xFFFF, sum = 0
6809 12:16:40.542960 12, 0xFFFF, sum = 0
6810 12:16:40.543012 13, 0x0, sum = 1
6811 12:16:40.543071 14, 0x0, sum = 2
6812 12:16:40.543132 15, 0x0, sum = 3
6813 12:16:40.543185 16, 0x0, sum = 4
6814 12:16:40.543237 best_step = 14
6815 12:16:40.543289
6816 12:16:40.543340 ==
6817 12:16:40.543440 Dram Type= 6, Freq= 0, CH_1, rank 0
6818 12:16:40.543493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 12:16:40.543545 ==
6820 12:16:40.543596 RX Vref Scan: 1
6821 12:16:40.543650
6822 12:16:40.543702 RX Vref 0 -> 0, step: 1
6823 12:16:40.543754
6824 12:16:40.543804 RX Delay -343 -> 252, step: 8
6825 12:16:40.543856
6826 12:16:40.543908 Set Vref, RX VrefLevel [Byte0]: 51
6827 12:16:40.543960 [Byte1]: 51
6828 12:16:40.544012
6829 12:16:40.544063 Final RX Vref Byte 0 = 51 to rank0
6830 12:16:40.544115 Final RX Vref Byte 1 = 51 to rank0
6831 12:16:40.544167 Final RX Vref Byte 0 = 51 to rank1
6832 12:16:40.544218 Final RX Vref Byte 1 = 51 to rank1==
6833 12:16:40.544269 Dram Type= 6, Freq= 0, CH_1, rank 0
6834 12:16:40.544320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 12:16:40.544372 ==
6836 12:16:40.544423 DQS Delay:
6837 12:16:40.544479 DQS0 = 44, DQS1 = 52
6838 12:16:40.544530 DQM Delay:
6839 12:16:40.544582 DQM0 = 10, DQM1 = 10
6840 12:16:40.544633 DQ Delay:
6841 12:16:40.544688 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6842 12:16:40.544740 DQ4 =4, DQ5 =20, DQ6 =20, DQ7 =4
6843 12:16:40.544791 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6844 12:16:40.544843 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6845 12:16:40.544893
6846 12:16:40.544945
6847 12:16:40.545000 [DQSOSCAuto] RK0, (LSB)MR18= 0x628a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
6848 12:16:40.545082 CH1 RK0: MR19=C0C, MR18=628A
6849 12:16:40.545165 CH1_RK0: MR19=0xC0C, MR18=0x628A, DQSOSC=392, MR23=63, INC=384, DEC=256
6850 12:16:40.545227 ==
6851 12:16:40.545280 Dram Type= 6, Freq= 0, CH_1, rank 1
6852 12:16:40.545333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 12:16:40.545387 ==
6854 12:16:40.545440 [Gating] SW mode calibration
6855 12:16:40.545492 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6856 12:16:40.545544 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6857 12:16:40.545600 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6858 12:16:40.545652 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6859 12:16:40.545704 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6860 12:16:40.545757 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6861 12:16:40.545809 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6862 12:16:40.545861 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6863 12:16:40.545912 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6864 12:16:40.545969 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6865 12:16:40.546021 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6866 12:16:40.546072 Total UI for P1: 0, mck2ui 16
6867 12:16:40.546126 best dqsien dly found for B0: ( 0, 14, 24)
6868 12:16:40.546178 Total UI for P1: 0, mck2ui 16
6869 12:16:40.546229 best dqsien dly found for B1: ( 0, 14, 24)
6870 12:16:40.546280 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6871 12:16:40.546332 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6872 12:16:40.546382
6873 12:16:40.546433 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6874 12:16:40.546485 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6875 12:16:40.546536 [Gating] SW calibration Done
6876 12:16:40.546587 ==
6877 12:16:40.546639 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 12:16:40.546690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 12:16:40.546753 ==
6880 12:16:40.546834 RX Vref Scan: 0
6881 12:16:40.546917
6882 12:16:40.546983 RX Vref 0 -> 0, step: 1
6883 12:16:40.547036
6884 12:16:40.547089 RX Delay -410 -> 252, step: 16
6885 12:16:40.547171 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6886 12:16:40.547252 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6887 12:16:40.547335 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6888 12:16:40.547447 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6889 12:16:40.547501 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6890 12:16:40.547553 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6891 12:16:40.547604 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6892 12:16:40.547656 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6893 12:16:40.547904 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6894 12:16:40.547996 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6895 12:16:40.548102 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6896 12:16:40.548207 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6897 12:16:40.548312 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6898 12:16:40.548407 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6899 12:16:40.548497 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6900 12:16:40.548559 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6901 12:16:40.548612 ==
6902 12:16:40.548664 Dram Type= 6, Freq= 0, CH_1, rank 1
6903 12:16:40.548716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6904 12:16:40.548768 ==
6905 12:16:40.548820 DQS Delay:
6906 12:16:40.548871 DQS0 = 43, DQS1 = 51
6907 12:16:40.548922 DQM Delay:
6908 12:16:40.548973 DQM0 = 10, DQM1 = 15
6909 12:16:40.549024 DQ Delay:
6910 12:16:40.549076 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6911 12:16:40.549127 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6912 12:16:40.549178 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6913 12:16:40.549229 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6914 12:16:40.549281
6915 12:16:40.549332
6916 12:16:40.549382 ==
6917 12:16:40.549433 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 12:16:40.549485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 12:16:40.549536 ==
6920 12:16:40.549587
6921 12:16:40.549637
6922 12:16:40.549688 TX Vref Scan disable
6923 12:16:40.549739 == TX Byte 0 ==
6924 12:16:40.549790 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6925 12:16:40.549842 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6926 12:16:40.549893 == TX Byte 1 ==
6927 12:16:40.549944 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6928 12:16:40.549997 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6929 12:16:40.550048 ==
6930 12:16:40.550098 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 12:16:40.550150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 12:16:40.550202 ==
6933 12:16:40.550252
6934 12:16:40.550303
6935 12:16:40.550354 TX Vref Scan disable
6936 12:16:40.550405 == TX Byte 0 ==
6937 12:16:40.550456 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6938 12:16:40.550507 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6939 12:16:40.550558 == TX Byte 1 ==
6940 12:16:40.550609 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6941 12:16:40.550660 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6942 12:16:40.550711
6943 12:16:40.550762 [DATLAT]
6944 12:16:40.550813 Freq=400, CH1 RK1
6945 12:16:40.550865
6946 12:16:40.550935 DATLAT Default: 0xe
6947 12:16:40.550990 0, 0xFFFF, sum = 0
6948 12:16:40.551043 1, 0xFFFF, sum = 0
6949 12:16:40.551095 2, 0xFFFF, sum = 0
6950 12:16:40.551147 3, 0xFFFF, sum = 0
6951 12:16:40.551200 4, 0xFFFF, sum = 0
6952 12:16:40.551253 5, 0xFFFF, sum = 0
6953 12:16:40.551305 6, 0xFFFF, sum = 0
6954 12:16:40.551357 7, 0xFFFF, sum = 0
6955 12:16:40.551459 8, 0xFFFF, sum = 0
6956 12:16:40.551512 9, 0xFFFF, sum = 0
6957 12:16:40.551564 10, 0xFFFF, sum = 0
6958 12:16:40.551616 11, 0xFFFF, sum = 0
6959 12:16:40.551669 12, 0xFFFF, sum = 0
6960 12:16:40.551721 13, 0x0, sum = 1
6961 12:16:40.551773 14, 0x0, sum = 2
6962 12:16:40.551824 15, 0x0, sum = 3
6963 12:16:40.551876 16, 0x0, sum = 4
6964 12:16:40.551928 best_step = 14
6965 12:16:40.551979
6966 12:16:40.552030 ==
6967 12:16:40.552082 Dram Type= 6, Freq= 0, CH_1, rank 1
6968 12:16:40.552134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6969 12:16:40.552185 ==
6970 12:16:40.552237 RX Vref Scan: 0
6971 12:16:40.552288
6972 12:16:40.552340 RX Vref 0 -> 0, step: 1
6973 12:16:40.552392
6974 12:16:40.552442 RX Delay -343 -> 252, step: 8
6975 12:16:40.552494 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6976 12:16:40.552546 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6977 12:16:40.552597 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6978 12:16:40.552649 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6979 12:16:40.552699 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6980 12:16:40.552750 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6981 12:16:40.552801 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6982 12:16:40.552853 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6983 12:16:40.552904 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6984 12:16:40.552955 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6985 12:16:40.553006 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6986 12:16:40.553057 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6987 12:16:40.553108 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6988 12:16:40.553160 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6989 12:16:40.553211 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6990 12:16:40.553262 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6991 12:16:40.553313 ==
6992 12:16:40.553365 Dram Type= 6, Freq= 0, CH_1, rank 1
6993 12:16:40.553416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6994 12:16:40.553467 ==
6995 12:16:40.553518 DQS Delay:
6996 12:16:40.553569 DQS0 = 48, DQS1 = 52
6997 12:16:40.553620 DQM Delay:
6998 12:16:40.553672 DQM0 = 12, DQM1 = 10
6999 12:16:40.553723 DQ Delay:
7000 12:16:40.553773 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7001 12:16:40.553824 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
7002 12:16:40.553875 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
7003 12:16:40.553927 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7004 12:16:40.553977
7005 12:16:40.554028
7006 12:16:40.554079 [DQSOSCAuto] RK1, (LSB)MR18= 0x72aa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
7007 12:16:40.554131 CH1 RK1: MR19=C0C, MR18=72AA
7008 12:16:40.554183 CH1_RK1: MR19=0xC0C, MR18=0x72AA, DQSOSC=388, MR23=63, INC=392, DEC=261
7009 12:16:40.554235 [RxdqsGatingPostProcess] freq 400
7010 12:16:40.739863 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7011 12:16:40.740394 best DQS0 dly(2T, 0.5T) = (0, 10)
7012 12:16:40.740752 best DQS1 dly(2T, 0.5T) = (0, 10)
7013 12:16:40.741085 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7014 12:16:40.741403 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7015 12:16:40.741717 best DQS0 dly(2T, 0.5T) = (0, 10)
7016 12:16:40.742022 best DQS1 dly(2T, 0.5T) = (0, 10)
7017 12:16:40.742324 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7018 12:16:40.742625 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7019 12:16:40.742924 Pre-setting of DQS Precalculation
7020 12:16:40.743222 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7021 12:16:40.743655 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7022 12:16:40.743976 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7023 12:16:40.744282
7024 12:16:40.744581
7025 12:16:40.744876 [Calibration Summary] 800 Mbps
7026 12:16:40.745175 CH 0, Rank 0
7027 12:16:40.745490 SW Impedance : PASS
7028 12:16:40.745829 DUTY Scan : NO K
7029 12:16:40.746129 ZQ Calibration : PASS
7030 12:16:40.746505 Jitter Meter : NO K
7031 12:16:40.746996 CBT Training : PASS
7032 12:16:40.747344 Write leveling : PASS
7033 12:16:40.748142 RX DQS gating : PASS
7034 12:16:40.748806 RX DQ/DQS(RDDQC) : PASS
7035 12:16:40.749482 TX DQ/DQS : PASS
7036 12:16:40.750148 RX DATLAT : PASS
7037 12:16:40.750767 RX DQ/DQS(Engine): PASS
7038 12:16:40.751244 TX OE : NO K
7039 12:16:40.751762 All Pass.
7040 12:16:40.752228
7041 12:16:40.752689 CH 0, Rank 1
7042 12:16:40.753149 SW Impedance : PASS
7043 12:16:40.753611 DUTY Scan : NO K
7044 12:16:40.754070 ZQ Calibration : PASS
7045 12:16:40.754526 Jitter Meter : NO K
7046 12:16:40.754984 CBT Training : PASS
7047 12:16:40.755471 Write leveling : NO K
7048 12:16:40.755933 RX DQS gating : PASS
7049 12:16:40.756389 RX DQ/DQS(RDDQC) : PASS
7050 12:16:40.756847 TX DQ/DQS : PASS
7051 12:16:40.757306 RX DATLAT : PASS
7052 12:16:40.757762 RX DQ/DQS(Engine): PASS
7053 12:16:40.758217 TX OE : NO K
7054 12:16:40.758678 All Pass.
7055 12:16:40.759089
7056 12:16:40.759508 CH 1, Rank 0
7057 12:16:40.759792 SW Impedance : PASS
7058 12:16:40.760062 DUTY Scan : NO K
7059 12:16:40.760327 ZQ Calibration : PASS
7060 12:16:40.760592 Jitter Meter : NO K
7061 12:16:40.760858 CBT Training : PASS
7062 12:16:40.761124 Write leveling : PASS
7063 12:16:40.761388 RX DQS gating : PASS
7064 12:16:40.761649 RX DQ/DQS(RDDQC) : PASS
7065 12:16:40.761912 TX DQ/DQS : PASS
7066 12:16:40.762177 RX DATLAT : PASS
7067 12:16:40.762440 RX DQ/DQS(Engine): PASS
7068 12:16:40.762701 TX OE : NO K
7069 12:16:40.763066 All Pass.
7070 12:16:40.763341
7071 12:16:40.763651 CH 1, Rank 1
7072 12:16:40.763918 SW Impedance : PASS
7073 12:16:40.764184 DUTY Scan : NO K
7074 12:16:40.764449 ZQ Calibration : PASS
7075 12:16:40.764715 Jitter Meter : NO K
7076 12:16:40.764980 CBT Training : PASS
7077 12:16:40.765244 Write leveling : NO K
7078 12:16:40.765508 RX DQS gating : PASS
7079 12:16:40.765815 RX DQ/DQS(RDDQC) : PASS
7080 12:16:40.766098 TX DQ/DQS : PASS
7081 12:16:40.766368 RX DATLAT : PASS
7082 12:16:40.766635 RX DQ/DQS(Engine): PASS
7083 12:16:40.766899 TX OE : NO K
7084 12:16:40.767166 All Pass.
7085 12:16:40.767455
7086 12:16:40.767723 DramC Write-DBI off
7087 12:16:40.768072 PER_BANK_REFRESH: Hybrid Mode
7088 12:16:40.768350 TX_TRACKING: ON
7089 12:16:40.768609 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7090 12:16:40.768802 [FAST_K] Save calibration result to emmc
7091 12:16:40.768993 dramc_set_vcore_voltage set vcore to 725000
7092 12:16:40.769184 Read voltage for 1600, 0
7093 12:16:40.769372 Vio18 = 0
7094 12:16:40.769563 Vcore = 725000
7095 12:16:40.769752 Vdram = 0
7096 12:16:40.769938 Vddq = 0
7097 12:16:40.770124 Vmddr = 0
7098 12:16:40.770309 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7099 12:16:40.770503 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7100 12:16:40.770694 MEM_TYPE=3, freq_sel=13
7101 12:16:40.770884 sv_algorithm_assistance_LP4_3733
7102 12:16:40.771073 ============ PULL DRAM RESETB DOWN ============
7103 12:16:40.771266 ========== PULL DRAM RESETB DOWN end =========
7104 12:16:40.771483 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7105 12:16:40.771676 ===================================
7106 12:16:40.771866 LPDDR4 DRAM CONFIGURATION
7107 12:16:40.772173 ===================================
7108 12:16:40.772428 EX_ROW_EN[0] = 0x0
7109 12:16:40.772630 EX_ROW_EN[1] = 0x0
7110 12:16:40.772824 LP4Y_EN = 0x0
7111 12:16:40.773016 WORK_FSP = 0x1
7112 12:16:40.773209 WL = 0x5
7113 12:16:40.773400 RL = 0x5
7114 12:16:40.773593 BL = 0x2
7115 12:16:40.773735 RPST = 0x0
7116 12:16:40.773878 RD_PRE = 0x0
7117 12:16:40.774021 WR_PRE = 0x1
7118 12:16:40.774165 WR_PST = 0x1
7119 12:16:40.774308 DBI_WR = 0x0
7120 12:16:40.774453 DBI_RD = 0x0
7121 12:16:40.774597 OTF = 0x1
7122 12:16:40.774742 ===================================
7123 12:16:40.774889 ===================================
7124 12:16:40.775033 ANA top config
7125 12:16:40.775176 ===================================
7126 12:16:40.775320 DLL_ASYNC_EN = 0
7127 12:16:40.775495 ALL_SLAVE_EN = 0
7128 12:16:40.775640 NEW_RANK_MODE = 1
7129 12:16:40.775786 DLL_IDLE_MODE = 1
7130 12:16:40.775929 LP45_APHY_COMB_EN = 1
7131 12:16:40.776072 TX_ODT_DIS = 0
7132 12:16:40.776216 NEW_8X_MODE = 1
7133 12:16:40.776360 ===================================
7134 12:16:40.776503 ===================================
7135 12:16:40.776647 data_rate = 3200
7136 12:16:40.776791 CKR = 1
7137 12:16:40.776934 DQ_P2S_RATIO = 8
7138 12:16:40.777079 ===================================
7139 12:16:40.777222 CA_P2S_RATIO = 8
7140 12:16:40.777365 DQ_CA_OPEN = 0
7141 12:16:40.777509 DQ_SEMI_OPEN = 0
7142 12:16:40.777651 CA_SEMI_OPEN = 0
7143 12:16:40.777795 CA_FULL_RATE = 0
7144 12:16:40.777937 DQ_CKDIV4_EN = 0
7145 12:16:40.778080 CA_CKDIV4_EN = 0
7146 12:16:40.778222 CA_PREDIV_EN = 0
7147 12:16:40.778365 PH8_DLY = 12
7148 12:16:40.778522 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7149 12:16:40.778638 DQ_AAMCK_DIV = 4
7150 12:16:40.778753 CA_AAMCK_DIV = 4
7151 12:16:40.778868 CA_ADMCK_DIV = 4
7152 12:16:40.778983 DQ_TRACK_CA_EN = 0
7153 12:16:40.779098 CA_PICK = 1600
7154 12:16:40.779213 CA_MCKIO = 1600
7155 12:16:40.779327 MCKIO_SEMI = 0
7156 12:16:40.779463 PLL_FREQ = 3068
7157 12:16:40.779582 DQ_UI_PI_RATIO = 32
7158 12:16:40.779709 CA_UI_PI_RATIO = 0
7159 12:16:40.779832 ===================================
7160 12:16:40.779949 ===================================
7161 12:16:40.780065 memory_type:LPDDR4
7162 12:16:40.780181 GP_NUM : 10
7163 12:16:40.780296 SRAM_EN : 1
7164 12:16:40.780411 MD32_EN : 0
7165 12:16:40.780526 ===================================
7166 12:16:40.780642 [ANA_INIT] >>>>>>>>>>>>>>
7167 12:16:40.780757 <<<<<< [CONFIGURE PHASE]: ANA_TX
7168 12:16:40.780873 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7169 12:16:40.780989 ===================================
7170 12:16:40.781104 data_rate = 3200,PCW = 0X7600
7171 12:16:40.781221 ===================================
7172 12:16:40.781337 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7173 12:16:40.781453 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7174 12:16:40.781570 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7175 12:16:40.781687 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7176 12:16:40.781857 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7177 12:16:40.782289 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7178 12:16:40.782512 [ANA_INIT] flow start
7179 12:16:40.782762 [ANA_INIT] PLL >>>>>>>>
7180 12:16:40.783009 [ANA_INIT] PLL <<<<<<<<
7181 12:16:40.783253 [ANA_INIT] MIDPI >>>>>>>>
7182 12:16:40.783490 [ANA_INIT] MIDPI <<<<<<<<
7183 12:16:40.783658 [ANA_INIT] DLL >>>>>>>>
7184 12:16:40.783761 [ANA_INIT] DLL <<<<<<<<
7185 12:16:40.783861 [ANA_INIT] flow end
7186 12:16:40.783959 ============ LP4 DIFF to SE enter ============
7187 12:16:40.784058 ============ LP4 DIFF to SE exit ============
7188 12:16:40.784157 [ANA_INIT] <<<<<<<<<<<<<
7189 12:16:40.784254 [Flow] Enable top DCM control >>>>>
7190 12:16:40.784351 [Flow] Enable top DCM control <<<<<
7191 12:16:40.784448 Enable DLL master slave shuffle
7192 12:16:40.784545 ==============================================================
7193 12:16:40.784643 Gating Mode config
7194 12:16:40.784741 ==============================================================
7195 12:16:40.784838 Config description:
7196 12:16:40.784935 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7197 12:16:40.785035 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7198 12:16:40.785134 SELPH_MODE 0: By rank 1: By Phase
7199 12:16:40.785232 ==============================================================
7200 12:16:40.785329 GAT_TRACK_EN = 1
7201 12:16:40.785426 RX_GATING_MODE = 2
7202 12:16:40.785524 RX_GATING_TRACK_MODE = 2
7203 12:16:40.785619 SELPH_MODE = 1
7204 12:16:40.785716 PICG_EARLY_EN = 1
7205 12:16:40.785812 VALID_LAT_VALUE = 1
7206 12:16:40.785909 ==============================================================
7207 12:16:40.786007 Enter into Gating configuration >>>>
7208 12:16:40.786104 Exit from Gating configuration <<<<
7209 12:16:40.786200 Enter into DVFS_PRE_config >>>>>
7210 12:16:40.786297 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7211 12:16:40.786396 Exit from DVFS_PRE_config <<<<<
7212 12:16:40.786492 Enter into PICG configuration >>>>
7213 12:16:40.786589 Exit from PICG configuration <<<<
7214 12:16:40.786686 [RX_INPUT] configuration >>>>>
7215 12:16:40.786782 [RX_INPUT] configuration <<<<<
7216 12:16:40.786878 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7217 12:16:40.786974 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7218 12:16:40.787071 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7219 12:16:40.787168 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7220 12:16:40.787264 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7221 12:16:40.787369 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7222 12:16:40.787469 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7223 12:16:40.787565 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7224 12:16:40.787662 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7225 12:16:40.787760 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7226 12:16:40.787856 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7227 12:16:40.787953 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7228 12:16:40.788050 ===================================
7229 12:16:40.788147 LPDDR4 DRAM CONFIGURATION
7230 12:16:40.788243 ===================================
7231 12:16:40.788340 EX_ROW_EN[0] = 0x0
7232 12:16:40.788436 EX_ROW_EN[1] = 0x0
7233 12:16:40.788532 LP4Y_EN = 0x0
7234 12:16:40.788631 WORK_FSP = 0x1
7235 12:16:40.788714 WL = 0x5
7236 12:16:40.788795 RL = 0x5
7237 12:16:40.788877 BL = 0x2
7238 12:16:40.788961 RPST = 0x0
7239 12:16:40.789043 RD_PRE = 0x0
7240 12:16:40.789126 WR_PRE = 0x1
7241 12:16:40.789207 WR_PST = 0x1
7242 12:16:40.789290 DBI_WR = 0x0
7243 12:16:40.789372 DBI_RD = 0x0
7244 12:16:40.789454 OTF = 0x1
7245 12:16:40.789536 ===================================
7246 12:16:40.789620 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7247 12:16:40.789704 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7248 12:16:40.789788 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7249 12:16:40.789871 ===================================
7250 12:16:40.789955 LPDDR4 DRAM CONFIGURATION
7251 12:16:40.790038 ===================================
7252 12:16:40.790121 EX_ROW_EN[0] = 0x10
7253 12:16:40.790205 EX_ROW_EN[1] = 0x0
7254 12:16:40.790288 LP4Y_EN = 0x0
7255 12:16:40.790370 WORK_FSP = 0x1
7256 12:16:40.790453 WL = 0x5
7257 12:16:40.790535 RL = 0x5
7258 12:16:40.790617 BL = 0x2
7259 12:16:40.790699 RPST = 0x0
7260 12:16:40.790781 RD_PRE = 0x0
7261 12:16:40.790863 WR_PRE = 0x1
7262 12:16:40.790945 WR_PST = 0x1
7263 12:16:40.791026 DBI_WR = 0x0
7264 12:16:40.791109 DBI_RD = 0x0
7265 12:16:40.791190 OTF = 0x1
7266 12:16:40.791273 ===================================
7267 12:16:40.791356 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7268 12:16:40.791451 ==
7269 12:16:40.791534 Dram Type= 6, Freq= 0, CH_0, rank 0
7270 12:16:40.791617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7271 12:16:40.791701 ==
7272 12:16:40.791784 [Duty_Offset_Calibration]
7273 12:16:40.791867 B0:2 B1:0 CA:4
7274 12:16:40.791950
7275 12:16:40.792033 [DutyScan_Calibration_Flow] k_type=0
7276 12:16:40.792115
7277 12:16:40.792197 ==CLK 0==
7278 12:16:40.792280 Final CLK duty delay cell = -4
7279 12:16:40.792363 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7280 12:16:40.792446 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7281 12:16:40.792530 [-4] AVG Duty = 4937%(X100)
7282 12:16:40.792613
7283 12:16:40.792696 CH0 CLK Duty spec in!! Max-Min= 187%
7284 12:16:40.792780 [DutyScan_Calibration_Flow] ====Done====
7285 12:16:40.792863
7286 12:16:40.792945 [DutyScan_Calibration_Flow] k_type=1
7287 12:16:40.793029
7288 12:16:40.793110 ==DQS 0 ==
7289 12:16:40.793194 Final DQS duty delay cell = 0
7290 12:16:40.793277 [0] MAX Duty = 5218%(X100), DQS PI = 22
7291 12:16:40.793360 [0] MIN Duty = 5093%(X100), DQS PI = 8
7292 12:16:40.793442 [0] AVG Duty = 5155%(X100)
7293 12:16:40.793535
7294 12:16:40.793609 ==DQS 1 ==
7295 12:16:40.793682 Final DQS duty delay cell = 0
7296 12:16:40.793970 [0] MAX Duty = 5187%(X100), DQS PI = 2
7297 12:16:40.794110 [0] MIN Duty = 4969%(X100), DQS PI = 10
7298 12:16:40.794261 [0] AVG Duty = 5078%(X100)
7299 12:16:40.794410
7300 12:16:40.794558 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7301 12:16:40.794694
7302 12:16:40.794812 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7303 12:16:40.794936 [DutyScan_Calibration_Flow] ====Done====
7304 12:16:40.795053
7305 12:16:40.795167 [DutyScan_Calibration_Flow] k_type=3
7306 12:16:40.795279
7307 12:16:40.795401 ==DQM 0 ==
7308 12:16:40.795479 Final DQM duty delay cell = 0
7309 12:16:40.795554 [0] MAX Duty = 5124%(X100), DQS PI = 20
7310 12:16:40.795628 [0] MIN Duty = 4875%(X100), DQS PI = 56
7311 12:16:40.795701 [0] AVG Duty = 4999%(X100)
7312 12:16:40.795774
7313 12:16:40.795846 ==DQM 1 ==
7314 12:16:40.795919 Final DQM duty delay cell = 0
7315 12:16:40.795992 [0] MAX Duty = 5000%(X100), DQS PI = 2
7316 12:16:40.796064 [0] MIN Duty = 4844%(X100), DQS PI = 14
7317 12:16:40.796137 [0] AVG Duty = 4922%(X100)
7318 12:16:40.796209
7319 12:16:40.796281 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7320 12:16:40.796354
7321 12:16:40.796426 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7322 12:16:40.796499 [DutyScan_Calibration_Flow] ====Done====
7323 12:16:40.796573
7324 12:16:40.796645 [DutyScan_Calibration_Flow] k_type=2
7325 12:16:40.796718
7326 12:16:40.796790 ==DQ 0 ==
7327 12:16:40.796862 Final DQ duty delay cell = 0
7328 12:16:40.796935 [0] MAX Duty = 5124%(X100), DQS PI = 20
7329 12:16:40.797008 [0] MIN Duty = 4938%(X100), DQS PI = 12
7330 12:16:40.797081 [0] AVG Duty = 5031%(X100)
7331 12:16:40.797153
7332 12:16:40.797225 ==DQ 1 ==
7333 12:16:40.797298 Final DQ duty delay cell = 0
7334 12:16:40.797370 [0] MAX Duty = 5187%(X100), DQS PI = 4
7335 12:16:40.797443 [0] MIN Duty = 4907%(X100), DQS PI = 34
7336 12:16:40.797515 [0] AVG Duty = 5047%(X100)
7337 12:16:40.797587
7338 12:16:40.797658 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7339 12:16:40.797730
7340 12:16:40.797802 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7341 12:16:40.797874 [DutyScan_Calibration_Flow] ====Done====
7342 12:16:40.797947 ==
7343 12:16:40.798019 Dram Type= 6, Freq= 0, CH_1, rank 0
7344 12:16:40.798092 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7345 12:16:40.798164 ==
7346 12:16:40.798237 [Duty_Offset_Calibration]
7347 12:16:40.798309 B0:0 B1:-1 CA:3
7348 12:16:40.798381
7349 12:16:40.798454 [DutyScan_Calibration_Flow] k_type=0
7350 12:16:40.798538
7351 12:16:40.798602 ==CLK 0==
7352 12:16:40.798666 Final CLK duty delay cell = 0
7353 12:16:40.798731 [0] MAX Duty = 5187%(X100), DQS PI = 4
7354 12:16:40.798795 [0] MIN Duty = 5031%(X100), DQS PI = 38
7355 12:16:40.798860 [0] AVG Duty = 5109%(X100)
7356 12:16:40.798924
7357 12:16:40.798987 CH1 CLK Duty spec in!! Max-Min= 156%
7358 12:16:40.799052 [DutyScan_Calibration_Flow] ====Done====
7359 12:16:40.799116
7360 12:16:40.799180 [DutyScan_Calibration_Flow] k_type=1
7361 12:16:40.799244
7362 12:16:40.799307 ==DQS 0 ==
7363 12:16:40.799377 Final DQS duty delay cell = 0
7364 12:16:40.799443 [0] MAX Duty = 5218%(X100), DQS PI = 20
7365 12:16:40.799508 [0] MIN Duty = 4907%(X100), DQS PI = 58
7366 12:16:40.799572 [0] AVG Duty = 5062%(X100)
7367 12:16:40.799635
7368 12:16:40.799699 ==DQS 1 ==
7369 12:16:40.799763 Final DQS duty delay cell = -4
7370 12:16:40.799827 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7371 12:16:40.799891 [-4] MIN Duty = 4844%(X100), DQS PI = 16
7372 12:16:40.799955 [-4] AVG Duty = 4922%(X100)
7373 12:16:40.800019
7374 12:16:40.800083 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7375 12:16:40.800147
7376 12:16:40.800211 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7377 12:16:40.800274 [DutyScan_Calibration_Flow] ====Done====
7378 12:16:40.800338
7379 12:16:40.800401 [DutyScan_Calibration_Flow] k_type=3
7380 12:16:40.800465
7381 12:16:40.800528 ==DQM 0 ==
7382 12:16:40.800592 Final DQM duty delay cell = 0
7383 12:16:40.800657 [0] MAX Duty = 5062%(X100), DQS PI = 30
7384 12:16:40.800721 [0] MIN Duty = 4782%(X100), DQS PI = 38
7385 12:16:40.800784 [0] AVG Duty = 4922%(X100)
7386 12:16:40.800847
7387 12:16:40.800911 ==DQM 1 ==
7388 12:16:40.800974 Final DQM duty delay cell = 0
7389 12:16:40.801039 [0] MAX Duty = 5000%(X100), DQS PI = 30
7390 12:16:40.801102 [0] MIN Duty = 4813%(X100), DQS PI = 0
7391 12:16:40.801166 [0] AVG Duty = 4906%(X100)
7392 12:16:40.801230
7393 12:16:40.801294 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7394 12:16:40.801358
7395 12:16:40.801421 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7396 12:16:40.801485 [DutyScan_Calibration_Flow] ====Done====
7397 12:16:40.801548
7398 12:16:40.801612 [DutyScan_Calibration_Flow] k_type=2
7399 12:16:40.801675
7400 12:16:40.801738 ==DQ 0 ==
7401 12:16:40.801802 Final DQ duty delay cell = -4
7402 12:16:40.801866 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7403 12:16:40.801931 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7404 12:16:40.801997 [-4] AVG Duty = 4891%(X100)
7405 12:16:40.802062
7406 12:16:40.802125 ==DQ 1 ==
7407 12:16:40.802189 Final DQ duty delay cell = 0
7408 12:16:40.802253 [0] MAX Duty = 5062%(X100), DQS PI = 32
7409 12:16:40.802318 [0] MIN Duty = 4875%(X100), DQS PI = 58
7410 12:16:40.802381 [0] AVG Duty = 4968%(X100)
7411 12:16:40.802445
7412 12:16:40.802508 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7413 12:16:40.802571
7414 12:16:40.802634 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7415 12:16:40.802698 [DutyScan_Calibration_Flow] ====Done====
7416 12:16:40.802761 nWR fixed to 30
7417 12:16:40.802825 [ModeRegInit_LP4] CH0 RK0
7418 12:16:40.802889 [ModeRegInit_LP4] CH0 RK1
7419 12:16:40.802952 [ModeRegInit_LP4] CH1 RK0
7420 12:16:40.803014 [ModeRegInit_LP4] CH1 RK1
7421 12:16:40.803078 match AC timing 5
7422 12:16:40.803141 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7423 12:16:40.803205 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7424 12:16:40.803270 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7425 12:16:40.803333 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7426 12:16:40.803403 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7427 12:16:40.803468 [MiockJmeterHQA]
7428 12:16:40.803544
7429 12:16:40.803600 [DramcMiockJmeter] u1RxGatingPI = 0
7430 12:16:40.803658 0 : 4252, 4027
7431 12:16:40.803716 4 : 4258, 4026
7432 12:16:40.803776 8 : 4368, 4140
7433 12:16:40.803834 12 : 4368, 4140
7434 12:16:40.803893 16 : 4363, 4138
7435 12:16:40.803951 20 : 4252, 4027
7436 12:16:40.804009 24 : 4253, 4027
7437 12:16:40.804067 28 : 4253, 4026
7438 12:16:40.804125 32 : 4363, 4138
7439 12:16:40.804183 36 : 4252, 4027
7440 12:16:40.804249 40 : 4363, 4137
7441 12:16:40.804315 44 : 4252, 4027
7442 12:16:40.804380 48 : 4255, 4029
7443 12:16:40.804442 52 : 4252, 4027
7444 12:16:40.804502 56 : 4255, 4029
7445 12:16:40.804561 60 : 4250, 4026
7446 12:16:40.804631 64 : 4250, 4027
7447 12:16:40.804694 68 : 4363, 4139
7448 12:16:40.804753 72 : 4250, 4027
7449 12:16:40.804816 76 : 4253, 4029
7450 12:16:40.804875 80 : 4250, 4027
7451 12:16:40.804933 84 : 4360, 4138
7452 12:16:40.804998 88 : 4250, 4026
7453 12:16:40.805058 92 : 4360, 4138
7454 12:16:40.805116 96 : 4249, 3258
7455 12:16:40.805177 100 : 4250, 0
7456 12:16:40.805237 104 : 4252, 0
7457 12:16:40.805296 108 : 4252, 0
7458 12:16:40.805354 112 : 4250, 0
7459 12:16:40.805413 116 : 4253, 0
7460 12:16:40.805472 120 : 4360, 0
7461 12:16:40.805530 124 : 4250, 0
7462 12:16:40.805589 128 : 4250, 0
7463 12:16:40.805647 132 : 4361, 0
7464 12:16:40.805705 136 : 4361, 0
7465 12:16:40.805763 140 : 4363, 0
7466 12:16:40.805821 144 : 4250, 0
7467 12:16:40.805879 148 : 4250, 0
7468 12:16:40.805937 152 : 4250, 0
7469 12:16:40.806199 156 : 4252, 0
7470 12:16:40.806309 160 : 4250, 0
7471 12:16:40.806429 164 : 4250, 0
7472 12:16:40.806549 168 : 4252, 0
7473 12:16:40.806669 172 : 4360, 0
7474 12:16:40.806777 176 : 4250, 0
7475 12:16:40.806879 180 : 4250, 0
7476 12:16:40.806947 184 : 4249, 0
7477 12:16:40.807007 188 : 4361, 0
7478 12:16:40.807066 192 : 4360, 0
7479 12:16:40.807124 196 : 4250, 0
7480 12:16:40.807182 200 : 4250, 0
7481 12:16:40.807241 204 : 4250, 0
7482 12:16:40.807299 208 : 4252, 0
7483 12:16:40.807358 212 : 4252, 0
7484 12:16:40.807428 216 : 4250, 0
7485 12:16:40.807486 220 : 4252, 533
7486 12:16:40.807546 224 : 4250, 3939
7487 12:16:40.807605 228 : 4250, 4027
7488 12:16:40.807663 232 : 4250, 4027
7489 12:16:40.807722 236 : 4250, 4027
7490 12:16:40.807780 240 : 4250, 4026
7491 12:16:40.807838 244 : 4250, 4027
7492 12:16:40.807896 248 : 4250, 4027
7493 12:16:40.807954 252 : 4252, 4029
7494 12:16:40.808014 256 : 4250, 4026
7495 12:16:40.808072 260 : 4360, 4138
7496 12:16:40.808130 264 : 4361, 4138
7497 12:16:40.808188 268 : 4250, 4027
7498 12:16:40.808247 272 : 4363, 4140
7499 12:16:40.808305 276 : 4250, 4026
7500 12:16:40.808364 280 : 4250, 4027
7501 12:16:40.808422 284 : 4250, 4027
7502 12:16:40.808481 288 : 4252, 4029
7503 12:16:40.808549 292 : 4250, 4026
7504 12:16:40.808603 296 : 4250, 4027
7505 12:16:40.808656 300 : 4250, 4027
7506 12:16:40.808708 304 : 4252, 4029
7507 12:16:40.808761 308 : 4250, 4026
7508 12:16:40.808814 312 : 4361, 4137
7509 12:16:40.808867 316 : 4360, 4138
7510 12:16:40.808920 320 : 4250, 4027
7511 12:16:40.808973 324 : 4363, 4140
7512 12:16:40.809025 328 : 4250, 4026
7513 12:16:40.809079 332 : 4250, 4008
7514 12:16:40.809132 336 : 4249, 2062
7515 12:16:40.809184
7516 12:16:40.809237 MIOCK jitter meter ch=0
7517 12:16:40.809289
7518 12:16:40.809341 1T = (336-100) = 236 dly cells
7519 12:16:40.809394 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7520 12:16:40.809447 ==
7521 12:16:40.809499 Dram Type= 6, Freq= 0, CH_0, rank 0
7522 12:16:40.809552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7523 12:16:40.809605 ==
7524 12:16:40.809656 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7525 12:16:40.809709 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7526 12:16:40.809761 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7527 12:16:40.809814 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7528 12:16:40.809867 [CA 0] Center 43 (13~73) winsize 61
7529 12:16:40.809920 [CA 1] Center 42 (12~73) winsize 62
7530 12:16:40.809972 [CA 2] Center 38 (9~67) winsize 59
7531 12:16:40.810025 [CA 3] Center 37 (8~67) winsize 60
7532 12:16:40.810077 [CA 4] Center 36 (6~66) winsize 61
7533 12:16:40.810129 [CA 5] Center 35 (5~66) winsize 62
7534 12:16:40.810181
7535 12:16:40.810233 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7536 12:16:40.810287
7537 12:16:40.810339 [CATrainingPosCal] consider 1 rank data
7538 12:16:40.810391 u2DelayCellTimex100 = 275/100 ps
7539 12:16:40.810443 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7540 12:16:40.810496 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7541 12:16:40.810548 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7542 12:16:40.810601 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7543 12:16:40.810653 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7544 12:16:40.810705 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7545 12:16:40.810757
7546 12:16:40.810809 CA PerBit enable=1, Macro0, CA PI delay=35
7547 12:16:40.810861
7548 12:16:40.810912 [CBTSetCACLKResult] CA Dly = 35
7549 12:16:40.810964 CS Dly: 11 (0~42)
7550 12:16:40.811016 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7551 12:16:40.811068 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7552 12:16:40.811120 ==
7553 12:16:40.811173 Dram Type= 6, Freq= 0, CH_0, rank 1
7554 12:16:40.811225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7555 12:16:40.811278 ==
7556 12:16:40.811330 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7557 12:16:40.811392 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7558 12:16:40.811445 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7559 12:16:40.811497 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7560 12:16:40.811550 [CA 0] Center 43 (13~74) winsize 62
7561 12:16:40.811602 [CA 1] Center 43 (13~73) winsize 61
7562 12:16:40.811655 [CA 2] Center 38 (9~68) winsize 60
7563 12:16:40.811707 [CA 3] Center 38 (9~68) winsize 60
7564 12:16:40.811759 [CA 4] Center 36 (6~67) winsize 62
7565 12:16:40.811811 [CA 5] Center 36 (6~66) winsize 61
7566 12:16:40.811863
7567 12:16:40.811915 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7568 12:16:40.811967
7569 12:16:40.812019 [CATrainingPosCal] consider 2 rank data
7570 12:16:40.812072 u2DelayCellTimex100 = 275/100 ps
7571 12:16:40.812124 CA0 delay=43 (13~73),Diff = 7 PI (24 cell)
7572 12:16:40.812177 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7573 12:16:40.812229 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7574 12:16:40.812282 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7575 12:16:40.812334 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7576 12:16:40.812386 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7577 12:16:40.812438
7578 12:16:40.812490 CA PerBit enable=1, Macro0, CA PI delay=36
7579 12:16:40.812542
7580 12:16:40.812594 [CBTSetCACLKResult] CA Dly = 36
7581 12:16:40.812646 CS Dly: 11 (0~43)
7582 12:16:40.812698 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7583 12:16:40.812750 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7584 12:16:40.812802
7585 12:16:40.812854 ----->DramcWriteLeveling(PI) begin...
7586 12:16:40.812907 ==
7587 12:16:40.812960 Dram Type= 6, Freq= 0, CH_0, rank 0
7588 12:16:40.813012 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7589 12:16:40.813064 ==
7590 12:16:40.813117 Write leveling (Byte 0): 34 => 34
7591 12:16:40.813169 Write leveling (Byte 1): 28 => 28
7592 12:16:40.813221 DramcWriteLeveling(PI) end<-----
7593 12:16:40.813273
7594 12:16:40.813325 ==
7595 12:16:40.813377 Dram Type= 6, Freq= 0, CH_0, rank 0
7596 12:16:40.813429 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7597 12:16:40.813482 ==
7598 12:16:40.813533 [Gating] SW mode calibration
7599 12:16:40.813598 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7600 12:16:40.813650 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7601 12:16:40.813701 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 12:16:40.813753 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 12:16:40.813804 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7604 12:16:40.813968 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7605 12:16:40.814026 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7606 12:16:40.814078 1 4 20 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
7607 12:16:40.814129 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7608 12:16:40.814181 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7609 12:16:40.814428 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7610 12:16:40.814519 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 12:16:40.814625 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7612 12:16:40.814731 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
7613 12:16:40.814837 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7614 12:16:40.814932 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
7615 12:16:40.815023 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 12:16:40.815086 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 12:16:40.815138 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 12:16:40.815190 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 12:16:40.815244 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7620 12:16:40.815297 1 6 12 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7621 12:16:40.815349 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7622 12:16:40.815408 1 6 20 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
7623 12:16:40.815464 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 12:16:40.815516 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 12:16:40.815567 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 12:16:40.815625 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 12:16:40.815677 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 12:16:40.815728 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7629 12:16:40.815783 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7630 12:16:40.815836 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7631 12:16:40.815887 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 12:16:40.815939 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 12:16:40.815993 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 12:16:40.816045 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 12:16:40.816096 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 12:16:40.816148 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 12:16:40.816202 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 12:16:40.816254 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 12:16:40.816305 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 12:16:40.816360 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 12:16:40.816412 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 12:16:40.816464 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 12:16:40.816515 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7644 12:16:40.816566 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7645 12:16:40.816618 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7646 12:16:40.816670 Total UI for P1: 0, mck2ui 16
7647 12:16:40.816722 best dqsien dly found for B0: ( 1, 9, 10)
7648 12:16:40.816773 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7649 12:16:40.816824 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 12:16:40.816876 Total UI for P1: 0, mck2ui 16
7651 12:16:40.816927 best dqsien dly found for B1: ( 1, 9, 20)
7652 12:16:40.816978 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7653 12:16:40.817030 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7654 12:16:40.817082
7655 12:16:40.817132 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7656 12:16:40.817184 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7657 12:16:40.817235 [Gating] SW calibration Done
7658 12:16:40.817285 ==
7659 12:16:40.817336 Dram Type= 6, Freq= 0, CH_0, rank 0
7660 12:16:40.817387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7661 12:16:40.817438 ==
7662 12:16:40.817489 RX Vref Scan: 0
7663 12:16:40.817540
7664 12:16:40.817590 RX Vref 0 -> 0, step: 1
7665 12:16:40.817641
7666 12:16:40.817692 RX Delay 0 -> 252, step: 8
7667 12:16:40.817744 iDelay=192, Bit 0, Center 135 (80 ~ 191) 112
7668 12:16:40.817795 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7669 12:16:40.817847 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7670 12:16:40.817898 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7671 12:16:40.817949 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7672 12:16:40.818000 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7673 12:16:40.818051 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7674 12:16:40.818102 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7675 12:16:40.818153 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7676 12:16:40.818204 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7677 12:16:40.818255 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7678 12:16:40.818306 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7679 12:16:40.818357 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7680 12:16:40.818408 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7681 12:16:40.818459 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7682 12:16:40.818510 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7683 12:16:40.818563 ==
7684 12:16:40.818615 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 12:16:40.818666 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 12:16:40.818718 ==
7687 12:16:40.818768 DQS Delay:
7688 12:16:40.818819 DQS0 = 0, DQS1 = 0
7689 12:16:40.818870 DQM Delay:
7690 12:16:40.818921 DQM0 = 131, DQM1 = 126
7691 12:16:40.818972 DQ Delay:
7692 12:16:40.819023 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =123
7693 12:16:40.819075 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7694 12:16:40.819126 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
7695 12:16:40.819177 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7696 12:16:40.819228
7697 12:16:40.819279
7698 12:16:40.819329 ==
7699 12:16:40.819388 Dram Type= 6, Freq= 0, CH_0, rank 0
7700 12:16:40.819441 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7701 12:16:40.819492 ==
7702 12:16:40.819543
7703 12:16:40.819593
7704 12:16:40.819644 TX Vref Scan disable
7705 12:16:40.819695 == TX Byte 0 ==
7706 12:16:40.819747 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7707 12:16:40.819799 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7708 12:16:40.819850 == TX Byte 1 ==
7709 12:16:40.819901 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7710 12:16:40.819954 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7711 12:16:40.820005 ==
7712 12:16:40.820056 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 12:16:40.820108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 12:16:40.820159 ==
7715 12:16:40.820210
7716 12:16:40.820261 TX Vref early break, caculate TX vref
7717 12:16:40.820312 TX Vref=16, minBit 1, minWin=22, winSum=369
7718 12:16:40.820559 TX Vref=18, minBit 7, minWin=22, winSum=383
7719 12:16:40.820661 TX Vref=20, minBit 8, minWin=23, winSum=392
7720 12:16:40.820768 TX Vref=22, minBit 8, minWin=23, winSum=401
7721 12:16:40.820873 TX Vref=24, minBit 1, minWin=24, winSum=409
7722 12:16:40.820979 TX Vref=26, minBit 1, minWin=25, winSum=415
7723 12:16:40.821081 TX Vref=28, minBit 0, minWin=25, winSum=422
7724 12:16:40.821172 TX Vref=30, minBit 1, minWin=25, winSum=419
7725 12:16:40.821252 TX Vref=32, minBit 4, minWin=24, winSum=411
7726 12:16:40.821306 TX Vref=34, minBit 0, minWin=24, winSum=400
7727 12:16:40.821358 TX Vref=36, minBit 0, minWin=23, winSum=390
7728 12:16:40.821411 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 28
7729 12:16:40.821463
7730 12:16:40.821515 Final TX Range 0 Vref 28
7731 12:16:40.821567
7732 12:16:40.821617 ==
7733 12:16:40.821669 Dram Type= 6, Freq= 0, CH_0, rank 0
7734 12:16:40.821721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7735 12:16:40.821772 ==
7736 12:16:40.821823
7737 12:16:40.821874
7738 12:16:40.821924 TX Vref Scan disable
7739 12:16:40.821976 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7740 12:16:40.822027 == TX Byte 0 ==
7741 12:16:40.822079 u2DelayCellOfst[0]=10 cells (3 PI)
7742 12:16:40.822130 u2DelayCellOfst[1]=14 cells (4 PI)
7743 12:16:40.822181 u2DelayCellOfst[2]=7 cells (2 PI)
7744 12:16:40.822232 u2DelayCellOfst[3]=10 cells (3 PI)
7745 12:16:40.822283 u2DelayCellOfst[4]=7 cells (2 PI)
7746 12:16:40.822334 u2DelayCellOfst[5]=0 cells (0 PI)
7747 12:16:40.822385 u2DelayCellOfst[6]=17 cells (5 PI)
7748 12:16:40.822436 u2DelayCellOfst[7]=14 cells (4 PI)
7749 12:16:40.822487 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7750 12:16:40.822539 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7751 12:16:40.822590 == TX Byte 1 ==
7752 12:16:40.822641 u2DelayCellOfst[8]=0 cells (0 PI)
7753 12:16:40.822692 u2DelayCellOfst[9]=0 cells (0 PI)
7754 12:16:40.822743 u2DelayCellOfst[10]=7 cells (2 PI)
7755 12:16:40.822793 u2DelayCellOfst[11]=3 cells (1 PI)
7756 12:16:40.822844 u2DelayCellOfst[12]=10 cells (3 PI)
7757 12:16:40.822894 u2DelayCellOfst[13]=10 cells (3 PI)
7758 12:16:40.822945 u2DelayCellOfst[14]=17 cells (5 PI)
7759 12:16:40.822995 u2DelayCellOfst[15]=10 cells (3 PI)
7760 12:16:40.823046 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7761 12:16:40.823097 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7762 12:16:40.823147 DramC Write-DBI on
7763 12:16:40.823199 ==
7764 12:16:40.823251 Dram Type= 6, Freq= 0, CH_0, rank 0
7765 12:16:40.823302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7766 12:16:40.823353 ==
7767 12:16:40.823412
7768 12:16:40.823463
7769 12:16:40.823513 TX Vref Scan disable
7770 12:16:40.823564 == TX Byte 0 ==
7771 12:16:40.823616 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7772 12:16:40.823667 == TX Byte 1 ==
7773 12:16:40.823718 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7774 12:16:40.823770 DramC Write-DBI off
7775 12:16:40.823831
7776 12:16:40.823894 [DATLAT]
7777 12:16:40.823954 Freq=1600, CH0 RK0
7778 12:16:40.824028
7779 12:16:40.824104 DATLAT Default: 0xf
7780 12:16:40.824158 0, 0xFFFF, sum = 0
7781 12:16:40.824211 1, 0xFFFF, sum = 0
7782 12:16:40.824264 2, 0xFFFF, sum = 0
7783 12:16:40.824316 3, 0xFFFF, sum = 0
7784 12:16:40.824368 4, 0xFFFF, sum = 0
7785 12:16:40.824419 5, 0xFFFF, sum = 0
7786 12:16:40.824471 6, 0xFFFF, sum = 0
7787 12:16:40.824523 7, 0xFFFF, sum = 0
7788 12:16:40.824575 8, 0xFFFF, sum = 0
7789 12:16:40.824627 9, 0xFFFF, sum = 0
7790 12:16:40.824678 10, 0xFFFF, sum = 0
7791 12:16:40.824730 11, 0xFFFF, sum = 0
7792 12:16:40.824782 12, 0xFFFF, sum = 0
7793 12:16:40.824834 13, 0xFFFF, sum = 0
7794 12:16:40.824887 14, 0x0, sum = 1
7795 12:16:40.824939 15, 0x0, sum = 2
7796 12:16:40.824990 16, 0x0, sum = 3
7797 12:16:40.825042 17, 0x0, sum = 4
7798 12:16:40.825095 best_step = 15
7799 12:16:40.825146
7800 12:16:40.825197 ==
7801 12:16:40.825249 Dram Type= 6, Freq= 0, CH_0, rank 0
7802 12:16:40.825300 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7803 12:16:40.825351 ==
7804 12:16:40.825403 RX Vref Scan: 1
7805 12:16:40.825454
7806 12:16:40.825505 Set Vref Range= 24 -> 127
7807 12:16:40.825556
7808 12:16:40.825610 RX Vref 24 -> 127, step: 1
7809 12:16:40.825662
7810 12:16:40.825713 RX Delay 11 -> 252, step: 4
7811 12:16:40.825765
7812 12:16:40.825816 Set Vref, RX VrefLevel [Byte0]: 24
7813 12:16:40.825868 [Byte1]: 24
7814 12:16:40.825919
7815 12:16:40.825970 Set Vref, RX VrefLevel [Byte0]: 25
7816 12:16:40.826020 [Byte1]: 25
7817 12:16:40.826072
7818 12:16:40.826122 Set Vref, RX VrefLevel [Byte0]: 26
7819 12:16:40.826174 [Byte1]: 26
7820 12:16:40.826225
7821 12:16:40.826276 Set Vref, RX VrefLevel [Byte0]: 27
7822 12:16:40.826327 [Byte1]: 27
7823 12:16:40.826377
7824 12:16:40.826428 Set Vref, RX VrefLevel [Byte0]: 28
7825 12:16:40.826480 [Byte1]: 28
7826 12:16:40.826531
7827 12:16:40.826581 Set Vref, RX VrefLevel [Byte0]: 29
7828 12:16:40.826632 [Byte1]: 29
7829 12:16:40.826683
7830 12:16:40.826734 Set Vref, RX VrefLevel [Byte0]: 30
7831 12:16:40.826785 [Byte1]: 30
7832 12:16:40.826836
7833 12:16:40.826887 Set Vref, RX VrefLevel [Byte0]: 31
7834 12:16:40.826939 [Byte1]: 31
7835 12:16:40.826990
7836 12:16:40.827040 Set Vref, RX VrefLevel [Byte0]: 32
7837 12:16:40.827091 [Byte1]: 32
7838 12:16:40.827143
7839 12:16:40.827193 Set Vref, RX VrefLevel [Byte0]: 33
7840 12:16:40.827245 [Byte1]: 33
7841 12:16:40.827296
7842 12:16:40.827346 Set Vref, RX VrefLevel [Byte0]: 34
7843 12:16:40.827403 [Byte1]: 34
7844 12:16:40.827454
7845 12:16:40.827505 Set Vref, RX VrefLevel [Byte0]: 35
7846 12:16:40.827556 [Byte1]: 35
7847 12:16:40.827606
7848 12:16:40.827657 Set Vref, RX VrefLevel [Byte0]: 36
7849 12:16:40.827708 [Byte1]: 36
7850 12:16:40.827759
7851 12:16:40.827810 Set Vref, RX VrefLevel [Byte0]: 37
7852 12:16:40.827862 [Byte1]: 37
7853 12:16:40.827914
7854 12:16:40.827964 Set Vref, RX VrefLevel [Byte0]: 38
7855 12:16:40.828016 [Byte1]: 38
7856 12:16:40.828067
7857 12:16:40.828117 Set Vref, RX VrefLevel [Byte0]: 39
7858 12:16:40.828169 [Byte1]: 39
7859 12:16:40.828220
7860 12:16:40.828271 Set Vref, RX VrefLevel [Byte0]: 40
7861 12:16:40.828323 [Byte1]: 40
7862 12:16:40.828374
7863 12:16:40.828425 Set Vref, RX VrefLevel [Byte0]: 41
7864 12:16:40.828477 [Byte1]: 41
7865 12:16:40.828528
7866 12:16:40.828579 Set Vref, RX VrefLevel [Byte0]: 42
7867 12:16:40.828630 [Byte1]: 42
7868 12:16:40.828682
7869 12:16:40.828732 Set Vref, RX VrefLevel [Byte0]: 43
7870 12:16:40.828784 [Byte1]: 43
7871 12:16:40.828835
7872 12:16:40.828886 Set Vref, RX VrefLevel [Byte0]: 44
7873 12:16:40.828937 [Byte1]: 44
7874 12:16:40.828988
7875 12:16:40.829039 Set Vref, RX VrefLevel [Byte0]: 45
7876 12:16:40.829287 [Byte1]: 45
7877 12:16:40.829383
7878 12:16:40.829488 Set Vref, RX VrefLevel [Byte0]: 46
7879 12:16:40.829593 [Byte1]: 46
7880 12:16:40.829697
7881 12:16:40.829791 Set Vref, RX VrefLevel [Byte0]: 47
7882 12:16:40.829880 [Byte1]: 47
7883 12:16:40.829942
7884 12:16:40.829995 Set Vref, RX VrefLevel [Byte0]: 48
7885 12:16:40.830047 [Byte1]: 48
7886 12:16:40.830099
7887 12:16:40.830151 Set Vref, RX VrefLevel [Byte0]: 49
7888 12:16:40.830202 [Byte1]: 49
7889 12:16:40.830254
7890 12:16:40.830306 Set Vref, RX VrefLevel [Byte0]: 50
7891 12:16:40.830357 [Byte1]: 50
7892 12:16:40.830408
7893 12:16:40.830460 Set Vref, RX VrefLevel [Byte0]: 51
7894 12:16:40.830512 [Byte1]: 51
7895 12:16:40.830563
7896 12:16:40.830614 Set Vref, RX VrefLevel [Byte0]: 52
7897 12:16:40.830666 [Byte1]: 52
7898 12:16:40.830717
7899 12:16:40.830769 Set Vref, RX VrefLevel [Byte0]: 53
7900 12:16:40.830821 [Byte1]: 53
7901 12:16:40.830871
7902 12:16:40.830923 Set Vref, RX VrefLevel [Byte0]: 54
7903 12:16:40.830974 [Byte1]: 54
7904 12:16:40.831025
7905 12:16:40.831076 Set Vref, RX VrefLevel [Byte0]: 55
7906 12:16:40.831127 [Byte1]: 55
7907 12:16:40.831178
7908 12:16:40.831230 Set Vref, RX VrefLevel [Byte0]: 56
7909 12:16:40.831280 [Byte1]: 56
7910 12:16:40.831331
7911 12:16:40.831389 Set Vref, RX VrefLevel [Byte0]: 57
7912 12:16:40.831442 [Byte1]: 57
7913 12:16:40.831493
7914 12:16:40.831544 Set Vref, RX VrefLevel [Byte0]: 58
7915 12:16:40.831595 [Byte1]: 58
7916 12:16:40.831645
7917 12:16:40.831697 Set Vref, RX VrefLevel [Byte0]: 59
7918 12:16:40.831748 [Byte1]: 59
7919 12:16:40.831799
7920 12:16:40.831850 Set Vref, RX VrefLevel [Byte0]: 60
7921 12:16:40.831902 [Byte1]: 60
7922 12:16:40.831952
7923 12:16:40.832004 Set Vref, RX VrefLevel [Byte0]: 61
7924 12:16:40.832055 [Byte1]: 61
7925 12:16:40.832106
7926 12:16:40.832158 Set Vref, RX VrefLevel [Byte0]: 62
7927 12:16:40.832209 [Byte1]: 62
7928 12:16:40.832259
7929 12:16:40.832310 Set Vref, RX VrefLevel [Byte0]: 63
7930 12:16:40.832361 [Byte1]: 63
7931 12:16:40.832412
7932 12:16:40.832463 Set Vref, RX VrefLevel [Byte0]: 64
7933 12:16:40.832515 [Byte1]: 64
7934 12:16:40.832566
7935 12:16:40.832616 Set Vref, RX VrefLevel [Byte0]: 65
7936 12:16:40.832668 [Byte1]: 65
7937 12:16:40.832720
7938 12:16:40.832771 Set Vref, RX VrefLevel [Byte0]: 66
7939 12:16:40.832822 [Byte1]: 66
7940 12:16:40.832873
7941 12:16:40.832925 Set Vref, RX VrefLevel [Byte0]: 67
7942 12:16:40.832976 [Byte1]: 67
7943 12:16:40.833027
7944 12:16:40.833078 Set Vref, RX VrefLevel [Byte0]: 68
7945 12:16:40.833129 [Byte1]: 68
7946 12:16:40.833180
7947 12:16:40.833231 Set Vref, RX VrefLevel [Byte0]: 69
7948 12:16:40.833283 [Byte1]: 69
7949 12:16:40.833334
7950 12:16:40.833385 Set Vref, RX VrefLevel [Byte0]: 70
7951 12:16:40.833436 [Byte1]: 70
7952 12:16:40.833487
7953 12:16:40.833538 Set Vref, RX VrefLevel [Byte0]: 71
7954 12:16:40.833589 [Byte1]: 71
7955 12:16:40.833640
7956 12:16:40.833691 Set Vref, RX VrefLevel [Byte0]: 72
7957 12:16:40.833743 [Byte1]: 72
7958 12:16:40.833793
7959 12:16:40.833844 Set Vref, RX VrefLevel [Byte0]: 73
7960 12:16:40.833896 [Byte1]: 73
7961 12:16:40.833947
7962 12:16:40.833997 Final RX Vref Byte 0 = 62 to rank0
7963 12:16:40.834048 Final RX Vref Byte 1 = 61 to rank0
7964 12:16:40.834099 Final RX Vref Byte 0 = 62 to rank1
7965 12:16:40.834150 Final RX Vref Byte 1 = 61 to rank1==
7966 12:16:40.834201 Dram Type= 6, Freq= 0, CH_0, rank 0
7967 12:16:40.834252 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7968 12:16:40.834304 ==
7969 12:16:40.834356 DQS Delay:
7970 12:16:40.834407 DQS0 = 0, DQS1 = 0
7971 12:16:40.834458 DQM Delay:
7972 12:16:40.834510 DQM0 = 129, DQM1 = 123
7973 12:16:40.834561 DQ Delay:
7974 12:16:40.834612 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7975 12:16:40.834664 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =136
7976 12:16:40.834715 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =120
7977 12:16:40.834766 DQ12 =130, DQ13 =130, DQ14 =132, DQ15 =128
7978 12:16:40.834818
7979 12:16:40.834869
7980 12:16:40.834919
7981 12:16:40.834970 [DramC_TX_OE_Calibration] TA2
7982 12:16:40.835022 Original DQ_B0 (3 6) =30, OEN = 27
7983 12:16:40.835073 Original DQ_B1 (3 6) =30, OEN = 27
7984 12:16:40.835125 24, 0x0, End_B0=24 End_B1=24
7985 12:16:40.835177 25, 0x0, End_B0=25 End_B1=25
7986 12:16:40.835230 26, 0x0, End_B0=26 End_B1=26
7987 12:16:40.835281 27, 0x0, End_B0=27 End_B1=27
7988 12:16:40.835334 28, 0x0, End_B0=28 End_B1=28
7989 12:16:40.835394 29, 0x0, End_B0=29 End_B1=29
7990 12:16:40.835447 30, 0x0, End_B0=30 End_B1=30
7991 12:16:40.835499 31, 0x4141, End_B0=30 End_B1=30
7992 12:16:40.835551 Byte0 end_step=30 best_step=27
7993 12:16:40.835602 Byte1 end_step=30 best_step=27
7994 12:16:40.835654 Byte0 TX OE(2T, 0.5T) = (3, 3)
7995 12:16:40.835705 Byte1 TX OE(2T, 0.5T) = (3, 3)
7996 12:16:40.835756
7997 12:16:40.835807
7998 12:16:40.835858 [DQSOSCAuto] RK0, (LSB)MR18= 0x1816, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
7999 12:16:40.835910 CH0 RK0: MR19=303, MR18=1816
8000 12:16:40.835961 CH0_RK0: MR19=0x303, MR18=0x1816, DQSOSC=397, MR23=63, INC=23, DEC=15
8001 12:16:40.836013
8002 12:16:40.836064 ----->DramcWriteLeveling(PI) begin...
8003 12:16:40.836117 ==
8004 12:16:40.836168 Dram Type= 6, Freq= 0, CH_0, rank 1
8005 12:16:40.836220 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8006 12:16:40.836272 ==
8007 12:16:40.836324 Write leveling (Byte 0): 35 => 35
8008 12:16:40.836376 Write leveling (Byte 1): 29 => 29
8009 12:16:40.836427 DramcWriteLeveling(PI) end<-----
8010 12:16:40.836478
8011 12:16:40.836529 ==
8012 12:16:40.836580 Dram Type= 6, Freq= 0, CH_0, rank 1
8013 12:16:40.836632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 12:16:40.836684 ==
8015 12:16:40.836735 [Gating] SW mode calibration
8016 12:16:40.836787 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8017 12:16:40.836839 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8018 12:16:41.197222 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 12:16:41.197752 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8020 12:16:41.198113 1 4 8 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8021 12:16:41.198451 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8022 12:16:41.198634 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8023 12:16:41.198955 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8024 12:16:41.199083 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8025 12:16:41.199193 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8026 12:16:41.199301 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8027 12:16:41.199434 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8028 12:16:41.199541 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8029 12:16:41.199628 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 1)
8030 12:16:41.199684 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8031 12:16:41.199736 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
8032 12:16:41.199788 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8033 12:16:41.199840 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 12:16:41.199891 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 12:16:41.199942 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 12:16:41.199993 1 6 8 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
8037 12:16:41.200044 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8038 12:16:41.200095 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
8039 12:16:41.200145 1 6 20 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
8040 12:16:41.200196 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 12:16:41.200247 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8042 12:16:41.200297 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8043 12:16:41.200348 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 12:16:41.200399 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8045 12:16:41.200449 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8046 12:16:41.200500 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8047 12:16:41.200550 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8048 12:16:41.200600 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 12:16:41.200651 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 12:16:41.200702 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 12:16:41.200752 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 12:16:41.200803 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 12:16:41.200853 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 12:16:41.200904 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 12:16:41.200954 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 12:16:41.201004 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 12:16:41.201055 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 12:16:41.201105 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 12:16:41.201155 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 12:16:41.201205 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8061 12:16:41.201256 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8062 12:16:41.201307 Total UI for P1: 0, mck2ui 16
8063 12:16:41.201358 best dqsien dly found for B0: ( 1, 9, 8)
8064 12:16:41.201410 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8065 12:16:41.201461 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8066 12:16:41.201511 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 12:16:41.201562 Total UI for P1: 0, mck2ui 16
8068 12:16:41.201612 best dqsien dly found for B1: ( 1, 9, 20)
8069 12:16:41.201663 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8070 12:16:41.201714 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8071 12:16:41.201765
8072 12:16:41.201816 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8073 12:16:41.201867 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8074 12:16:41.201918 [Gating] SW calibration Done
8075 12:16:41.201969 ==
8076 12:16:41.202020 Dram Type= 6, Freq= 0, CH_0, rank 1
8077 12:16:41.202071 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8078 12:16:41.202122 ==
8079 12:16:41.202173 RX Vref Scan: 0
8080 12:16:41.202224
8081 12:16:41.202274 RX Vref 0 -> 0, step: 1
8082 12:16:41.202325
8083 12:16:41.202375 RX Delay 0 -> 252, step: 8
8084 12:16:41.202426 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8085 12:16:41.202477 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8086 12:16:41.202527 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8087 12:16:41.202578 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8088 12:16:41.202630 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8089 12:16:41.202680 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8090 12:16:41.202730 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8091 12:16:41.202810 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8092 12:16:41.202912 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8093 12:16:41.202991 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8094 12:16:41.203042 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8095 12:16:41.203094 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8096 12:16:41.203145 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8097 12:16:41.203195 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8098 12:16:41.203246 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8099 12:16:41.203296 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8100 12:16:41.203347 ==
8101 12:16:41.203438 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 12:16:41.203490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 12:16:41.203557 ==
8104 12:16:41.203611 DQS Delay:
8105 12:16:41.203665 DQS0 = 0, DQS1 = 0
8106 12:16:41.203720 DQM Delay:
8107 12:16:41.203774 DQM0 = 133, DQM1 = 124
8108 12:16:41.203828 DQ Delay:
8109 12:16:41.203882 DQ0 =127, DQ1 =135, DQ2 =131, DQ3 =131
8110 12:16:41.203937 DQ4 =139, DQ5 =119, DQ6 =143, DQ7 =143
8111 12:16:41.203990 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =115
8112 12:16:41.204044 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8113 12:16:41.204098
8114 12:16:41.204152
8115 12:16:41.204204 ==
8116 12:16:41.204259 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 12:16:41.204314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 12:16:41.204368 ==
8119 12:16:41.204422
8120 12:16:41.204476
8121 12:16:41.204529 TX Vref Scan disable
8122 12:16:41.204584 == TX Byte 0 ==
8123 12:16:41.204638 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8124 12:16:41.204692 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8125 12:16:41.204747 == TX Byte 1 ==
8126 12:16:41.204819 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8127 12:16:41.204911 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8128 12:16:41.204971 ==
8129 12:16:41.205223 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 12:16:41.205317 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 12:16:41.205413 ==
8132 12:16:41.205504
8133 12:16:41.205562 TX Vref early break, caculate TX vref
8134 12:16:41.205619 TX Vref=16, minBit 9, minWin=22, winSum=380
8135 12:16:41.205675 TX Vref=18, minBit 9, minWin=23, winSum=393
8136 12:16:41.205730 TX Vref=20, minBit 2, minWin=24, winSum=397
8137 12:16:41.205784 TX Vref=22, minBit 2, minWin=24, winSum=403
8138 12:16:41.205839 TX Vref=24, minBit 1, minWin=25, winSum=411
8139 12:16:41.205894 TX Vref=26, minBit 0, minWin=26, winSum=422
8140 12:16:41.205949 TX Vref=28, minBit 4, minWin=25, winSum=422
8141 12:16:41.206003 TX Vref=30, minBit 3, minWin=25, winSum=419
8142 12:16:41.206058 TX Vref=32, minBit 1, minWin=24, winSum=408
8143 12:16:41.206113 TX Vref=34, minBit 0, minWin=24, winSum=401
8144 12:16:41.206168 TX Vref=36, minBit 0, minWin=24, winSum=393
8145 12:16:41.206223 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 26
8146 12:16:41.206279
8147 12:16:41.206334 Final TX Range 0 Vref 26
8148 12:16:41.206389
8149 12:16:41.206443 ==
8150 12:16:41.206498 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 12:16:41.206553 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 12:16:41.206608 ==
8153 12:16:41.206662
8154 12:16:41.206716
8155 12:16:41.206770 TX Vref Scan disable
8156 12:16:41.206824 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8157 12:16:41.206879 == TX Byte 0 ==
8158 12:16:41.206933 u2DelayCellOfst[0]=14 cells (4 PI)
8159 12:16:41.206988 u2DelayCellOfst[1]=17 cells (5 PI)
8160 12:16:41.207042 u2DelayCellOfst[2]=10 cells (3 PI)
8161 12:16:41.207097 u2DelayCellOfst[3]=14 cells (4 PI)
8162 12:16:41.207151 u2DelayCellOfst[4]=10 cells (3 PI)
8163 12:16:41.207205 u2DelayCellOfst[5]=0 cells (0 PI)
8164 12:16:41.207258 u2DelayCellOfst[6]=17 cells (5 PI)
8165 12:16:41.207312 u2DelayCellOfst[7]=17 cells (5 PI)
8166 12:16:41.207373 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8167 12:16:41.207428 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8168 12:16:41.207482 == TX Byte 1 ==
8169 12:16:41.207536 u2DelayCellOfst[8]=0 cells (0 PI)
8170 12:16:41.207590 u2DelayCellOfst[9]=0 cells (0 PI)
8171 12:16:41.207644 u2DelayCellOfst[10]=7 cells (2 PI)
8172 12:16:41.207698 u2DelayCellOfst[11]=3 cells (1 PI)
8173 12:16:41.207751 u2DelayCellOfst[12]=10 cells (3 PI)
8174 12:16:41.207806 u2DelayCellOfst[13]=10 cells (3 PI)
8175 12:16:41.207860 u2DelayCellOfst[14]=14 cells (4 PI)
8176 12:16:41.207915 u2DelayCellOfst[15]=14 cells (4 PI)
8177 12:16:41.207969 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8178 12:16:41.208023 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8179 12:16:41.208077 DramC Write-DBI on
8180 12:16:41.208131 ==
8181 12:16:41.208185 Dram Type= 6, Freq= 0, CH_0, rank 1
8182 12:16:41.208240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8183 12:16:41.208295 ==
8184 12:16:41.208349
8185 12:16:41.208404
8186 12:16:41.208458 TX Vref Scan disable
8187 12:16:41.208513 == TX Byte 0 ==
8188 12:16:41.208566 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8189 12:16:41.208621 == TX Byte 1 ==
8190 12:16:41.208676 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8191 12:16:41.208729 DramC Write-DBI off
8192 12:16:41.208783
8193 12:16:41.208837 [DATLAT]
8194 12:16:41.208891 Freq=1600, CH0 RK1
8195 12:16:41.208946
8196 12:16:41.208999 DATLAT Default: 0xf
8197 12:16:41.209053 0, 0xFFFF, sum = 0
8198 12:16:41.209109 1, 0xFFFF, sum = 0
8199 12:16:41.209165 2, 0xFFFF, sum = 0
8200 12:16:41.209220 3, 0xFFFF, sum = 0
8201 12:16:41.209275 4, 0xFFFF, sum = 0
8202 12:16:41.209330 5, 0xFFFF, sum = 0
8203 12:16:41.209386 6, 0xFFFF, sum = 0
8204 12:16:41.209441 7, 0xFFFF, sum = 0
8205 12:16:41.209496 8, 0xFFFF, sum = 0
8206 12:16:41.209552 9, 0xFFFF, sum = 0
8207 12:16:41.209607 10, 0xFFFF, sum = 0
8208 12:16:41.209661 11, 0xFFFF, sum = 0
8209 12:16:41.209716 12, 0xFFFF, sum = 0
8210 12:16:41.209770 13, 0xFFFF, sum = 0
8211 12:16:41.209825 14, 0x0, sum = 1
8212 12:16:41.209880 15, 0x0, sum = 2
8213 12:16:41.209935 16, 0x0, sum = 3
8214 12:16:41.209990 17, 0x0, sum = 4
8215 12:16:41.210045 best_step = 15
8216 12:16:41.210099
8217 12:16:41.210153 ==
8218 12:16:41.210208 Dram Type= 6, Freq= 0, CH_0, rank 1
8219 12:16:41.210263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8220 12:16:41.210317 ==
8221 12:16:41.210372 RX Vref Scan: 0
8222 12:16:41.210426
8223 12:16:41.210480 RX Vref 0 -> 0, step: 1
8224 12:16:41.210534
8225 12:16:41.210587 RX Delay 11 -> 252, step: 4
8226 12:16:41.210642 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8227 12:16:41.210697 iDelay=191, Bit 1, Center 132 (83 ~ 182) 100
8228 12:16:41.210751 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8229 12:16:41.210805 iDelay=191, Bit 3, Center 128 (79 ~ 178) 100
8230 12:16:41.210859 iDelay=191, Bit 4, Center 130 (83 ~ 178) 96
8231 12:16:41.210914 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8232 12:16:41.210968 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8233 12:16:41.211022 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8234 12:16:41.211077 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8235 12:16:41.211131 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8236 12:16:41.211185 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8237 12:16:41.211239 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8238 12:16:41.211293 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8239 12:16:41.211347 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8240 12:16:41.211407 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8241 12:16:41.211461 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8242 12:16:41.211515 ==
8243 12:16:41.211569 Dram Type= 6, Freq= 0, CH_0, rank 1
8244 12:16:41.211624 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8245 12:16:41.211679 ==
8246 12:16:41.211734 DQS Delay:
8247 12:16:41.211788 DQS0 = 0, DQS1 = 0
8248 12:16:41.211842 DQM Delay:
8249 12:16:41.211896 DQM0 = 129, DQM1 = 123
8250 12:16:41.211950 DQ Delay:
8251 12:16:41.212005 DQ0 =126, DQ1 =132, DQ2 =124, DQ3 =128
8252 12:16:41.212060 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =134
8253 12:16:41.212114 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8254 12:16:41.212168 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =130
8255 12:16:41.212223
8256 12:16:41.212276
8257 12:16:41.212330
8258 12:16:41.212383 [DramC_TX_OE_Calibration] TA2
8259 12:16:41.212438 Original DQ_B0 (3 6) =30, OEN = 27
8260 12:16:41.212493 Original DQ_B1 (3 6) =30, OEN = 27
8261 12:16:41.212548 24, 0x0, End_B0=24 End_B1=24
8262 12:16:41.212603 25, 0x0, End_B0=25 End_B1=25
8263 12:16:41.212658 26, 0x0, End_B0=26 End_B1=26
8264 12:16:41.212713 27, 0x0, End_B0=27 End_B1=27
8265 12:16:41.212768 28, 0x0, End_B0=28 End_B1=28
8266 12:16:41.212822 29, 0x0, End_B0=29 End_B1=29
8267 12:16:41.212878 30, 0x0, End_B0=30 End_B1=30
8268 12:16:41.212932 31, 0x4141, End_B0=30 End_B1=30
8269 12:16:41.212988 Byte0 end_step=30 best_step=27
8270 12:16:41.213042 Byte1 end_step=30 best_step=27
8271 12:16:41.213292 Byte0 TX OE(2T, 0.5T) = (3, 3)
8272 12:16:41.213354 Byte1 TX OE(2T, 0.5T) = (3, 3)
8273 12:16:41.213410
8274 12:16:41.213465
8275 12:16:41.213520 [DQSOSCAuto] RK1, (LSB)MR18= 0x110f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 401 ps
8276 12:16:41.213575 CH0 RK1: MR19=303, MR18=110F
8277 12:16:41.213630 CH0_RK1: MR19=0x303, MR18=0x110F, DQSOSC=401, MR23=63, INC=22, DEC=15
8278 12:16:41.213685 [RxdqsGatingPostProcess] freq 1600
8279 12:16:41.213739 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8280 12:16:41.213794 best DQS0 dly(2T, 0.5T) = (1, 1)
8281 12:16:41.213849 best DQS1 dly(2T, 0.5T) = (1, 1)
8282 12:16:41.213903 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8283 12:16:41.213957 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8284 12:16:41.214012 best DQS0 dly(2T, 0.5T) = (1, 1)
8285 12:16:41.214066 best DQS1 dly(2T, 0.5T) = (1, 1)
8286 12:16:41.214120 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8287 12:16:41.214174 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8288 12:16:41.214229 Pre-setting of DQS Precalculation
8289 12:16:41.214284 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8290 12:16:41.214338 ==
8291 12:16:41.214393 Dram Type= 6, Freq= 0, CH_1, rank 0
8292 12:16:41.214448 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 12:16:41.214503 ==
8294 12:16:41.214557 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8295 12:16:41.214611 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8296 12:16:41.214666 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8297 12:16:41.214720 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8298 12:16:41.214774 [CA 0] Center 42 (12~72) winsize 61
8299 12:16:41.214829 [CA 1] Center 42 (12~72) winsize 61
8300 12:16:41.214883 [CA 2] Center 38 (9~68) winsize 60
8301 12:16:41.214938 [CA 3] Center 37 (7~67) winsize 61
8302 12:16:41.215003 [CA 4] Center 38 (8~68) winsize 61
8303 12:16:41.215068 [CA 5] Center 36 (7~66) winsize 60
8304 12:16:41.215123
8305 12:16:41.215177 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8306 12:16:41.215231
8307 12:16:41.215285 [CATrainingPosCal] consider 1 rank data
8308 12:16:41.215340 u2DelayCellTimex100 = 275/100 ps
8309 12:16:41.215402 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8310 12:16:41.215457 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8311 12:16:41.215511 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
8312 12:16:41.215566 CA3 delay=37 (7~67),Diff = 1 PI (3 cell)
8313 12:16:41.215620 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8314 12:16:41.215674 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8315 12:16:41.215729
8316 12:16:41.215783 CA PerBit enable=1, Macro0, CA PI delay=36
8317 12:16:41.215837
8318 12:16:41.215891 [CBTSetCACLKResult] CA Dly = 36
8319 12:16:41.215946 CS Dly: 8 (0~39)
8320 12:16:41.216000 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8321 12:16:41.216055 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8322 12:16:41.216109 ==
8323 12:16:41.216163 Dram Type= 6, Freq= 0, CH_1, rank 1
8324 12:16:41.216217 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8325 12:16:41.216272 ==
8326 12:16:41.216326 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8327 12:16:41.216380 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8328 12:16:41.216435 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8329 12:16:41.216490 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8330 12:16:41.216545 [CA 0] Center 42 (12~72) winsize 61
8331 12:16:41.216599 [CA 1] Center 42 (13~71) winsize 59
8332 12:16:41.216653 [CA 2] Center 37 (8~67) winsize 60
8333 12:16:41.216707 [CA 3] Center 36 (8~65) winsize 58
8334 12:16:41.216761 [CA 4] Center 37 (7~67) winsize 61
8335 12:16:41.216816 [CA 5] Center 36 (6~66) winsize 61
8336 12:16:41.216869
8337 12:16:41.216923 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8338 12:16:41.216977
8339 12:16:41.217031 [CATrainingPosCal] consider 2 rank data
8340 12:16:41.217086 u2DelayCellTimex100 = 275/100 ps
8341 12:16:41.217141 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8342 12:16:41.217195 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8343 12:16:41.217249 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8344 12:16:41.217303 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8345 12:16:41.217357 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8346 12:16:41.217410 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8347 12:16:41.217464
8348 12:16:41.217517 CA PerBit enable=1, Macro0, CA PI delay=36
8349 12:16:41.217571
8350 12:16:41.217625 [CBTSetCACLKResult] CA Dly = 36
8351 12:16:41.217679 CS Dly: 9 (0~42)
8352 12:16:41.217733 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8353 12:16:41.217787 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8354 12:16:41.217841
8355 12:16:41.217895 ----->DramcWriteLeveling(PI) begin...
8356 12:16:41.217950 ==
8357 12:16:41.218004 Dram Type= 6, Freq= 0, CH_1, rank 0
8358 12:16:41.218059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8359 12:16:41.218114 ==
8360 12:16:41.218168 Write leveling (Byte 0): 23 => 23
8361 12:16:41.218221 Write leveling (Byte 1): 27 => 27
8362 12:16:41.218275 DramcWriteLeveling(PI) end<-----
8363 12:16:41.218329
8364 12:16:41.218383 ==
8365 12:16:41.218436 Dram Type= 6, Freq= 0, CH_1, rank 0
8366 12:16:41.218489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8367 12:16:41.218543 ==
8368 12:16:41.218596 [Gating] SW mode calibration
8369 12:16:41.218650 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8370 12:16:41.218704 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8371 12:16:41.218759 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 12:16:41.218814 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 12:16:41.218867 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 12:16:41.218921 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8375 12:16:41.218975 1 4 16 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8376 12:16:41.219028 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 12:16:41.219081 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 12:16:41.219135 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8379 12:16:41.219188 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8380 12:16:41.219242 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8381 12:16:41.219296 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8382 12:16:41.219350 1 5 12 | B1->B0 | 3333 2525 | 1 0 | (1 0) (1 0)
8383 12:16:41.219599 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8384 12:16:41.219660 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 12:16:41.219728 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 12:16:41.219784 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 12:16:41.219838 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8388 12:16:41.219892 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8389 12:16:41.219946 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8390 12:16:41.220001 1 6 12 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)
8391 12:16:41.220055 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 12:16:41.220109 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 12:16:41.220162 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 12:16:41.220216 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 12:16:41.220269 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8396 12:16:41.220324 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 12:16:41.220379 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 12:16:41.220433 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8399 12:16:41.220486 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8400 12:16:41.220539 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 12:16:41.220593 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 12:16:41.220646 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 12:16:41.220700 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 12:16:41.220753 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 12:16:41.220807 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 12:16:41.220860 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 12:16:41.220915 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 12:16:41.220969 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 12:16:41.221022 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 12:16:41.221076 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 12:16:41.221130 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 12:16:41.221184 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 12:16:41.221238 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8414 12:16:41.221292 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8415 12:16:41.221346 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8416 12:16:41.221400 Total UI for P1: 0, mck2ui 16
8417 12:16:41.221454 best dqsien dly found for B0: ( 1, 9, 10)
8418 12:16:41.221509 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 12:16:41.221563 Total UI for P1: 0, mck2ui 16
8420 12:16:41.221617 best dqsien dly found for B1: ( 1, 9, 14)
8421 12:16:41.221671 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8422 12:16:41.221725 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8423 12:16:41.221779
8424 12:16:41.221833 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8425 12:16:41.221888 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8426 12:16:41.221942 [Gating] SW calibration Done
8427 12:16:41.221996 ==
8428 12:16:41.222050 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 12:16:41.222104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 12:16:41.222159 ==
8431 12:16:41.222212 RX Vref Scan: 0
8432 12:16:41.222267
8433 12:16:41.222321 RX Vref 0 -> 0, step: 1
8434 12:16:41.222374
8435 12:16:41.222428 RX Delay 0 -> 252, step: 8
8436 12:16:41.222485 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8437 12:16:41.222541 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8438 12:16:41.222599 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8439 12:16:41.222659 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8440 12:16:41.222717 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8441 12:16:41.222773 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8442 12:16:41.222827 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8443 12:16:41.222882 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8444 12:16:41.222948 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8445 12:16:41.223003 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8446 12:16:41.223057 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8447 12:16:41.223115 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8448 12:16:41.223169 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8449 12:16:41.223223 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8450 12:16:41.223281 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8451 12:16:41.223335 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8452 12:16:41.223396 ==
8453 12:16:41.223454 Dram Type= 6, Freq= 0, CH_1, rank 0
8454 12:16:41.223509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8455 12:16:41.223564 ==
8456 12:16:41.223618 DQS Delay:
8457 12:16:41.223678 DQS0 = 0, DQS1 = 0
8458 12:16:41.223733 DQM Delay:
8459 12:16:41.223787 DQM0 = 136, DQM1 = 130
8460 12:16:41.223841 DQ Delay:
8461 12:16:41.223894 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =139
8462 12:16:41.223949 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =131
8463 12:16:41.224002 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8464 12:16:41.224056 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8465 12:16:41.224110
8466 12:16:41.224163
8467 12:16:41.224217 ==
8468 12:16:41.224271 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 12:16:41.224325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 12:16:41.224379 ==
8471 12:16:41.224433
8472 12:16:41.224493
8473 12:16:41.224546 TX Vref Scan disable
8474 12:16:41.224600 == TX Byte 0 ==
8475 12:16:41.224654 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8476 12:16:41.224708 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8477 12:16:41.224762 == TX Byte 1 ==
8478 12:16:41.224815 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8479 12:16:41.224868 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8480 12:16:41.224922 ==
8481 12:16:41.224976 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 12:16:41.225030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 12:16:41.225084 ==
8484 12:16:41.225138
8485 12:16:41.225191 TX Vref early break, caculate TX vref
8486 12:16:41.225246 TX Vref=16, minBit 8, minWin=21, winSum=367
8487 12:16:41.225301 TX Vref=18, minBit 8, minWin=21, winSum=374
8488 12:16:41.225355 TX Vref=20, minBit 8, minWin=23, winSum=386
8489 12:16:41.225408 TX Vref=22, minBit 8, minWin=23, winSum=396
8490 12:16:41.225461 TX Vref=24, minBit 8, minWin=24, winSum=406
8491 12:16:41.225515 TX Vref=26, minBit 9, minWin=24, winSum=412
8492 12:16:41.225761 TX Vref=28, minBit 0, minWin=25, winSum=419
8493 12:16:41.225843 TX Vref=30, minBit 0, minWin=25, winSum=418
8494 12:16:41.225939 TX Vref=32, minBit 0, minWin=24, winSum=404
8495 12:16:41.226030 TX Vref=34, minBit 0, minWin=23, winSum=394
8496 12:16:41.226087 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
8497 12:16:41.226142
8498 12:16:41.226196 Final TX Range 0 Vref 28
8499 12:16:41.226251
8500 12:16:41.226305 ==
8501 12:16:41.226359 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 12:16:41.226413 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 12:16:41.226467 ==
8504 12:16:41.226520
8505 12:16:41.226573
8506 12:16:41.226626 TX Vref Scan disable
8507 12:16:41.226680 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8508 12:16:41.226734 == TX Byte 0 ==
8509 12:16:41.226788 u2DelayCellOfst[0]=17 cells (5 PI)
8510 12:16:41.226841 u2DelayCellOfst[1]=10 cells (3 PI)
8511 12:16:41.226895 u2DelayCellOfst[2]=0 cells (0 PI)
8512 12:16:41.226950 u2DelayCellOfst[3]=7 cells (2 PI)
8513 12:16:41.227003 u2DelayCellOfst[4]=10 cells (3 PI)
8514 12:16:41.227056 u2DelayCellOfst[5]=17 cells (5 PI)
8515 12:16:41.227109 u2DelayCellOfst[6]=17 cells (5 PI)
8516 12:16:41.227162 u2DelayCellOfst[7]=7 cells (2 PI)
8517 12:16:41.227216 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8518 12:16:41.227270 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8519 12:16:41.227323 == TX Byte 1 ==
8520 12:16:41.227382 u2DelayCellOfst[8]=0 cells (0 PI)
8521 12:16:41.227437 u2DelayCellOfst[9]=0 cells (0 PI)
8522 12:16:41.227491 u2DelayCellOfst[10]=7 cells (2 PI)
8523 12:16:41.227544 u2DelayCellOfst[11]=3 cells (1 PI)
8524 12:16:41.227597 u2DelayCellOfst[12]=10 cells (3 PI)
8525 12:16:41.227650 u2DelayCellOfst[13]=10 cells (3 PI)
8526 12:16:41.227703 u2DelayCellOfst[14]=14 cells (4 PI)
8527 12:16:41.227757 u2DelayCellOfst[15]=14 cells (4 PI)
8528 12:16:41.227810 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8529 12:16:41.227864 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8530 12:16:41.227917 DramC Write-DBI on
8531 12:16:41.227970 ==
8532 12:16:41.228024 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 12:16:41.228077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 12:16:41.228131 ==
8535 12:16:41.228185
8536 12:16:41.228238
8537 12:16:41.228291 TX Vref Scan disable
8538 12:16:41.228345 == TX Byte 0 ==
8539 12:16:41.228399 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8540 12:16:41.228452 == TX Byte 1 ==
8541 12:16:41.228505 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8542 12:16:41.228570 DramC Write-DBI off
8543 12:16:41.228621
8544 12:16:41.228671 [DATLAT]
8545 12:16:41.228721 Freq=1600, CH1 RK0
8546 12:16:41.228771
8547 12:16:41.228821 DATLAT Default: 0xf
8548 12:16:41.228872 0, 0xFFFF, sum = 0
8549 12:16:41.228923 1, 0xFFFF, sum = 0
8550 12:16:41.228974 2, 0xFFFF, sum = 0
8551 12:16:41.229026 3, 0xFFFF, sum = 0
8552 12:16:41.229077 4, 0xFFFF, sum = 0
8553 12:16:41.229128 5, 0xFFFF, sum = 0
8554 12:16:41.229179 6, 0xFFFF, sum = 0
8555 12:16:41.229230 7, 0xFFFF, sum = 0
8556 12:16:41.229281 8, 0xFFFF, sum = 0
8557 12:16:41.229332 9, 0xFFFF, sum = 0
8558 12:16:41.229383 10, 0xFFFF, sum = 0
8559 12:16:41.229434 11, 0xFFFF, sum = 0
8560 12:16:41.229485 12, 0xFFFF, sum = 0
8561 12:16:41.229536 13, 0xFFFF, sum = 0
8562 12:16:41.229588 14, 0x0, sum = 1
8563 12:16:41.229638 15, 0x0, sum = 2
8564 12:16:41.229688 16, 0x0, sum = 3
8565 12:16:41.229739 17, 0x0, sum = 4
8566 12:16:41.229790 best_step = 15
8567 12:16:41.229839
8568 12:16:41.229889 ==
8569 12:16:41.229939 Dram Type= 6, Freq= 0, CH_1, rank 0
8570 12:16:41.229990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8571 12:16:41.230041 ==
8572 12:16:41.230091 RX Vref Scan: 1
8573 12:16:41.230141
8574 12:16:41.230192 Set Vref Range= 24 -> 127
8575 12:16:41.230242
8576 12:16:41.230292 RX Vref 24 -> 127, step: 1
8577 12:16:41.230343
8578 12:16:41.230393 RX Delay 19 -> 252, step: 4
8579 12:16:41.230443
8580 12:16:41.230493 Set Vref, RX VrefLevel [Byte0]: 24
8581 12:16:41.230543 [Byte1]: 24
8582 12:16:41.230593
8583 12:16:41.230643 Set Vref, RX VrefLevel [Byte0]: 25
8584 12:16:41.230693 [Byte1]: 25
8585 12:16:41.230743
8586 12:16:41.230793 Set Vref, RX VrefLevel [Byte0]: 26
8587 12:16:41.230844 [Byte1]: 26
8588 12:16:41.230894
8589 12:16:41.230944 Set Vref, RX VrefLevel [Byte0]: 27
8590 12:16:41.230994 [Byte1]: 27
8591 12:16:41.231044
8592 12:16:41.231094 Set Vref, RX VrefLevel [Byte0]: 28
8593 12:16:41.231144 [Byte1]: 28
8594 12:16:41.231193
8595 12:16:41.231243 Set Vref, RX VrefLevel [Byte0]: 29
8596 12:16:41.231293 [Byte1]: 29
8597 12:16:41.231344
8598 12:16:41.231433 Set Vref, RX VrefLevel [Byte0]: 30
8599 12:16:41.231484 [Byte1]: 30
8600 12:16:41.231534
8601 12:16:41.231584 Set Vref, RX VrefLevel [Byte0]: 31
8602 12:16:41.231634 [Byte1]: 31
8603 12:16:41.231683
8604 12:16:41.231734 Set Vref, RX VrefLevel [Byte0]: 32
8605 12:16:41.231784 [Byte1]: 32
8606 12:16:41.231834
8607 12:16:41.231884 Set Vref, RX VrefLevel [Byte0]: 33
8608 12:16:41.231935 [Byte1]: 33
8609 12:16:41.231984
8610 12:16:41.232034 Set Vref, RX VrefLevel [Byte0]: 34
8611 12:16:41.232084 [Byte1]: 34
8612 12:16:41.232134
8613 12:16:41.232184 Set Vref, RX VrefLevel [Byte0]: 35
8614 12:16:41.232234 [Byte1]: 35
8615 12:16:41.232284
8616 12:16:41.232334 Set Vref, RX VrefLevel [Byte0]: 36
8617 12:16:41.232385 [Byte1]: 36
8618 12:16:41.232436
8619 12:16:41.232485 Set Vref, RX VrefLevel [Byte0]: 37
8620 12:16:41.232536 [Byte1]: 37
8621 12:16:41.232587
8622 12:16:41.232637 Set Vref, RX VrefLevel [Byte0]: 38
8623 12:16:41.232687 [Byte1]: 38
8624 12:16:41.232737
8625 12:16:41.232786 Set Vref, RX VrefLevel [Byte0]: 39
8626 12:16:41.232837 [Byte1]: 39
8627 12:16:41.232887
8628 12:16:41.232937 Set Vref, RX VrefLevel [Byte0]: 40
8629 12:16:41.232991 [Byte1]: 40
8630 12:16:41.233045
8631 12:16:41.233096 Set Vref, RX VrefLevel [Byte0]: 41
8632 12:16:41.233146 [Byte1]: 41
8633 12:16:41.233197
8634 12:16:41.233253 Set Vref, RX VrefLevel [Byte0]: 42
8635 12:16:41.233303 [Byte1]: 42
8636 12:16:41.233353
8637 12:16:41.233407 Set Vref, RX VrefLevel [Byte0]: 43
8638 12:16:41.233458 [Byte1]: 43
8639 12:16:41.233509
8640 12:16:41.233560 Set Vref, RX VrefLevel [Byte0]: 44
8641 12:16:41.233616 [Byte1]: 44
8642 12:16:41.233666
8643 12:16:41.233716 Set Vref, RX VrefLevel [Byte0]: 45
8644 12:16:41.233770 [Byte1]: 45
8645 12:16:41.233821
8646 12:16:41.233871 Set Vref, RX VrefLevel [Byte0]: 46
8647 12:16:41.233921 [Byte1]: 46
8648 12:16:41.233975
8649 12:16:41.234026 Set Vref, RX VrefLevel [Byte0]: 47
8650 12:16:41.234076 [Byte1]: 47
8651 12:16:41.234126
8652 12:16:41.234177 Set Vref, RX VrefLevel [Byte0]: 48
8653 12:16:41.234227 [Byte1]: 48
8654 12:16:41.234277
8655 12:16:41.234516 Set Vref, RX VrefLevel [Byte0]: 49
8656 12:16:41.234597 [Byte1]: 49
8657 12:16:41.234650
8658 12:16:41.234702 Set Vref, RX VrefLevel [Byte0]: 50
8659 12:16:41.234753 [Byte1]: 50
8660 12:16:41.234805
8661 12:16:41.234856 Set Vref, RX VrefLevel [Byte0]: 51
8662 12:16:41.234908 [Byte1]: 51
8663 12:16:41.234959
8664 12:16:41.235011 Set Vref, RX VrefLevel [Byte0]: 52
8665 12:16:41.235076 [Byte1]: 52
8666 12:16:41.235126
8667 12:16:41.235176 Set Vref, RX VrefLevel [Byte0]: 53
8668 12:16:41.235227 [Byte1]: 53
8669 12:16:41.235277
8670 12:16:41.235327 Set Vref, RX VrefLevel [Byte0]: 54
8671 12:16:41.235422 [Byte1]: 54
8672 12:16:41.235501
8673 12:16:41.235551 Set Vref, RX VrefLevel [Byte0]: 55
8674 12:16:41.235602 [Byte1]: 55
8675 12:16:41.235652
8676 12:16:41.235702 Set Vref, RX VrefLevel [Byte0]: 56
8677 12:16:41.235752 [Byte1]: 56
8678 12:16:41.235803
8679 12:16:41.235853 Set Vref, RX VrefLevel [Byte0]: 57
8680 12:16:41.235904 [Byte1]: 57
8681 12:16:41.235955
8682 12:16:41.236006 Set Vref, RX VrefLevel [Byte0]: 58
8683 12:16:41.236056 [Byte1]: 58
8684 12:16:41.236107
8685 12:16:41.236157 Set Vref, RX VrefLevel [Byte0]: 59
8686 12:16:41.236208 [Byte1]: 59
8687 12:16:41.236258
8688 12:16:41.236309 Set Vref, RX VrefLevel [Byte0]: 60
8689 12:16:41.236359 [Byte1]: 60
8690 12:16:41.236409
8691 12:16:41.236459 Set Vref, RX VrefLevel [Byte0]: 61
8692 12:16:41.236509 [Byte1]: 61
8693 12:16:41.236560
8694 12:16:41.236610 Set Vref, RX VrefLevel [Byte0]: 62
8695 12:16:41.236661 [Byte1]: 62
8696 12:16:41.236711
8697 12:16:41.236778 Set Vref, RX VrefLevel [Byte0]: 63
8698 12:16:41.236830 [Byte1]: 63
8699 12:16:41.236881
8700 12:16:41.236932 Set Vref, RX VrefLevel [Byte0]: 64
8701 12:16:41.236984 [Byte1]: 64
8702 12:16:41.237046
8703 12:16:41.237096 Set Vref, RX VrefLevel [Byte0]: 65
8704 12:16:41.237173 [Byte1]: 65
8705 12:16:41.237224
8706 12:16:41.237274 Set Vref, RX VrefLevel [Byte0]: 66
8707 12:16:41.237324 [Byte1]: 66
8708 12:16:41.237375
8709 12:16:41.237425 Set Vref, RX VrefLevel [Byte0]: 67
8710 12:16:41.237476 [Byte1]: 67
8711 12:16:41.237526
8712 12:16:41.237576 Set Vref, RX VrefLevel [Byte0]: 68
8713 12:16:41.237626 [Byte1]: 68
8714 12:16:41.237676
8715 12:16:41.237725 Set Vref, RX VrefLevel [Byte0]: 69
8716 12:16:41.237776 [Byte1]: 69
8717 12:16:41.237826
8718 12:16:41.237876 Set Vref, RX VrefLevel [Byte0]: 70
8719 12:16:41.237927 [Byte1]: 70
8720 12:16:41.237977
8721 12:16:41.238027 Final RX Vref Byte 0 = 60 to rank0
8722 12:16:41.238078 Final RX Vref Byte 1 = 63 to rank0
8723 12:16:41.238129 Final RX Vref Byte 0 = 60 to rank1
8724 12:16:41.238180 Final RX Vref Byte 1 = 63 to rank1==
8725 12:16:41.238231 Dram Type= 6, Freq= 0, CH_1, rank 0
8726 12:16:41.238282 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8727 12:16:41.238348 ==
8728 12:16:41.238413 DQS Delay:
8729 12:16:41.238463 DQS0 = 0, DQS1 = 0
8730 12:16:41.238513 DQM Delay:
8731 12:16:41.238563 DQM0 = 133, DQM1 = 128
8732 12:16:41.238614 DQ Delay:
8733 12:16:41.238664 DQ0 =138, DQ1 =130, DQ2 =118, DQ3 =132
8734 12:16:41.238715 DQ4 =130, DQ5 =142, DQ6 =146, DQ7 =128
8735 12:16:41.238794 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =120
8736 12:16:41.238845 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8737 12:16:41.238895
8738 12:16:41.238946
8739 12:16:41.238996
8740 12:16:41.239046 [DramC_TX_OE_Calibration] TA2
8741 12:16:41.239096 Original DQ_B0 (3 6) =30, OEN = 27
8742 12:16:41.239147 Original DQ_B1 (3 6) =30, OEN = 27
8743 12:16:41.239197 24, 0x0, End_B0=24 End_B1=24
8744 12:16:41.239249 25, 0x0, End_B0=25 End_B1=25
8745 12:16:41.239300 26, 0x0, End_B0=26 End_B1=26
8746 12:16:41.239351 27, 0x0, End_B0=27 End_B1=27
8747 12:16:41.239441 28, 0x0, End_B0=28 End_B1=28
8748 12:16:41.239493 29, 0x0, End_B0=29 End_B1=29
8749 12:16:41.239544 30, 0x0, End_B0=30 End_B1=30
8750 12:16:41.239595 31, 0x4141, End_B0=30 End_B1=30
8751 12:16:41.239647 Byte0 end_step=30 best_step=27
8752 12:16:41.239697 Byte1 end_step=30 best_step=27
8753 12:16:41.239747 Byte0 TX OE(2T, 0.5T) = (3, 3)
8754 12:16:41.239797 Byte1 TX OE(2T, 0.5T) = (3, 3)
8755 12:16:41.239847
8756 12:16:41.239897
8757 12:16:41.239965 [DQSOSCAuto] RK0, (LSB)MR18= 0xb14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
8758 12:16:41.240030 CH1 RK0: MR19=303, MR18=B14
8759 12:16:41.240081 CH1_RK0: MR19=0x303, MR18=0xB14, DQSOSC=399, MR23=63, INC=23, DEC=15
8760 12:16:41.240132
8761 12:16:41.240182 ----->DramcWriteLeveling(PI) begin...
8762 12:16:41.240234 ==
8763 12:16:41.240284 Dram Type= 6, Freq= 0, CH_1, rank 1
8764 12:16:41.240336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8765 12:16:41.240387 ==
8766 12:16:41.240438 Write leveling (Byte 0): 22 => 22
8767 12:16:41.240489 Write leveling (Byte 1): 25 => 25
8768 12:16:41.240540 DramcWriteLeveling(PI) end<-----
8769 12:16:41.240590
8770 12:16:41.240641 ==
8771 12:16:41.240691 Dram Type= 6, Freq= 0, CH_1, rank 1
8772 12:16:41.240755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8773 12:16:41.240807 ==
8774 12:16:41.240859 [Gating] SW mode calibration
8775 12:16:41.240911 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8776 12:16:41.240963 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8777 12:16:41.241015 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 12:16:41.241067 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 12:16:41.241119 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8780 12:16:41.241170 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8781 12:16:41.241222 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 12:16:41.241273 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 12:16:41.241324 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 12:16:41.241375 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 12:16:41.241426 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 12:16:41.241477 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 12:16:41.241528 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8788 12:16:41.241579 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8789 12:16:41.241631 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 12:16:41.241682 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 12:16:41.241922 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 12:16:41.241980 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 12:16:41.242063 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 12:16:41.242169 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8795 12:16:41.242274 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8796 12:16:41.242379 1 6 12 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
8797 12:16:41.242479 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 12:16:41.242568 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 12:16:41.242644 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 12:16:41.242699 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 12:16:41.242752 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 12:16:41.242803 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8803 12:16:41.242855 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8804 12:16:41.242907 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8805 12:16:41.242959 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8806 12:16:41.243010 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 12:16:41.243062 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 12:16:41.243114 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 12:16:41.243165 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 12:16:41.243217 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 12:16:41.243268 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 12:16:41.243320 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 12:16:41.243382 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 12:16:41.243474 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 12:16:41.243525 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 12:16:41.243577 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 12:16:41.243629 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 12:16:41.243680 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 12:16:41.243732 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8820 12:16:41.243783 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8821 12:16:41.243835 Total UI for P1: 0, mck2ui 16
8822 12:16:41.243887 best dqsien dly found for B0: ( 1, 9, 8)
8823 12:16:41.243939 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8824 12:16:41.243991 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 12:16:41.244042 Total UI for P1: 0, mck2ui 16
8826 12:16:41.244094 best dqsien dly found for B1: ( 1, 9, 14)
8827 12:16:41.244145 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8828 12:16:41.244198 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8829 12:16:41.244249
8830 12:16:41.244300 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8831 12:16:41.244351 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8832 12:16:41.244413 [Gating] SW calibration Done
8833 12:16:41.244472 ==
8834 12:16:41.244525 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 12:16:41.244577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 12:16:41.244629 ==
8837 12:16:41.244681 RX Vref Scan: 0
8838 12:16:41.244732
8839 12:16:41.244783 RX Vref 0 -> 0, step: 1
8840 12:16:41.244835
8841 12:16:41.244886 RX Delay 0 -> 252, step: 8
8842 12:16:41.244937 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8843 12:16:41.244989 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8844 12:16:41.245041 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8845 12:16:41.245092 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8846 12:16:41.245143 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8847 12:16:41.245194 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8848 12:16:41.245245 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8849 12:16:41.245296 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8850 12:16:41.245347 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8851 12:16:41.245398 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8852 12:16:41.245449 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8853 12:16:41.245500 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8854 12:16:41.245551 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8855 12:16:41.245603 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8856 12:16:41.245654 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8857 12:16:41.245705 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8858 12:16:41.245756 ==
8859 12:16:41.245807 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 12:16:41.245859 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 12:16:41.245911 ==
8862 12:16:41.245962 DQS Delay:
8863 12:16:41.246013 DQS0 = 0, DQS1 = 0
8864 12:16:41.246065 DQM Delay:
8865 12:16:41.246116 DQM0 = 134, DQM1 = 131
8866 12:16:41.246168 DQ Delay:
8867 12:16:41.246219 DQ0 =143, DQ1 =131, DQ2 =119, DQ3 =131
8868 12:16:41.246271 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8869 12:16:41.246322 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8870 12:16:41.246373 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8871 12:16:41.246424
8872 12:16:41.246475
8873 12:16:41.246526 ==
8874 12:16:41.246592 Dram Type= 6, Freq= 0, CH_1, rank 1
8875 12:16:41.246645 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8876 12:16:41.246697 ==
8877 12:16:41.246749
8878 12:16:41.246800
8879 12:16:41.246852 TX Vref Scan disable
8880 12:16:41.246903 == TX Byte 0 ==
8881 12:16:41.246955 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8882 12:16:41.247007 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8883 12:16:41.247058 == TX Byte 1 ==
8884 12:16:41.247110 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8885 12:16:41.247162 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8886 12:16:41.247213 ==
8887 12:16:41.247264 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 12:16:41.247316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 12:16:41.247375 ==
8890 12:16:41.247462
8891 12:16:41.247513 TX Vref early break, caculate TX vref
8892 12:16:41.247565 TX Vref=16, minBit 9, minWin=21, winSum=376
8893 12:16:41.247616 TX Vref=18, minBit 9, minWin=22, winSum=385
8894 12:16:41.247667 TX Vref=20, minBit 9, minWin=22, winSum=392
8895 12:16:41.247718 TX Vref=22, minBit 9, minWin=23, winSum=404
8896 12:16:41.247770 TX Vref=24, minBit 9, minWin=24, winSum=410
8897 12:16:41.247821 TX Vref=26, minBit 9, minWin=24, winSum=416
8898 12:16:41.247872 TX Vref=28, minBit 9, minWin=25, winSum=423
8899 12:16:41.247923 TX Vref=30, minBit 9, minWin=24, winSum=417
8900 12:16:41.247975 TX Vref=32, minBit 0, minWin=25, winSum=411
8901 12:16:41.248222 TX Vref=34, minBit 0, minWin=24, winSum=403
8902 12:16:41.248313 TX Vref=36, minBit 0, minWin=24, winSum=395
8903 12:16:41.248418 [TxChooseVref] Worse bit 9, Min win 25, Win sum 423, Final Vref 28
8904 12:16:41.248523
8905 12:16:41.248627 Final TX Range 0 Vref 28
8906 12:16:41.248731
8907 12:16:41.248820 ==
8908 12:16:41.248904 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 12:16:41.248959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 12:16:41.249013 ==
8911 12:16:41.249064
8912 12:16:41.249115
8913 12:16:41.249167 TX Vref Scan disable
8914 12:16:41.249219 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8915 12:16:41.249271 == TX Byte 0 ==
8916 12:16:41.249323 u2DelayCellOfst[0]=10 cells (3 PI)
8917 12:16:41.249375 u2DelayCellOfst[1]=7 cells (2 PI)
8918 12:16:41.249426 u2DelayCellOfst[2]=0 cells (0 PI)
8919 12:16:41.249478 u2DelayCellOfst[3]=3 cells (1 PI)
8920 12:16:41.249529 u2DelayCellOfst[4]=7 cells (2 PI)
8921 12:16:41.249580 u2DelayCellOfst[5]=10 cells (3 PI)
8922 12:16:41.249632 u2DelayCellOfst[6]=10 cells (3 PI)
8923 12:16:41.249683 u2DelayCellOfst[7]=3 cells (1 PI)
8924 12:16:41.249734 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8925 12:16:41.249786 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8926 12:16:41.249837 == TX Byte 1 ==
8927 12:16:41.249888 u2DelayCellOfst[8]=0 cells (0 PI)
8928 12:16:41.249940 u2DelayCellOfst[9]=0 cells (0 PI)
8929 12:16:41.249991 u2DelayCellOfst[10]=10 cells (3 PI)
8930 12:16:41.250042 u2DelayCellOfst[11]=3 cells (1 PI)
8931 12:16:41.250094 u2DelayCellOfst[12]=14 cells (4 PI)
8932 12:16:41.250145 u2DelayCellOfst[13]=14 cells (4 PI)
8933 12:16:41.250197 u2DelayCellOfst[14]=17 cells (5 PI)
8934 12:16:41.250248 u2DelayCellOfst[15]=17 cells (5 PI)
8935 12:16:41.250300 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8936 12:16:41.250352 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8937 12:16:41.250403 DramC Write-DBI on
8938 12:16:41.250454 ==
8939 12:16:41.250505 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 12:16:41.250557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 12:16:41.250608 ==
8942 12:16:41.250660
8943 12:16:41.250711
8944 12:16:41.250762 TX Vref Scan disable
8945 12:16:41.250813 == TX Byte 0 ==
8946 12:16:41.250863 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8947 12:16:41.250915 == TX Byte 1 ==
8948 12:16:41.250966 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8949 12:16:41.251017 DramC Write-DBI off
8950 12:16:41.251068
8951 12:16:41.251119 [DATLAT]
8952 12:16:41.251170 Freq=1600, CH1 RK1
8953 12:16:41.251222
8954 12:16:41.251273 DATLAT Default: 0xf
8955 12:16:41.251324 0, 0xFFFF, sum = 0
8956 12:16:41.251413 1, 0xFFFF, sum = 0
8957 12:16:41.251482 2, 0xFFFF, sum = 0
8958 12:16:41.251535 3, 0xFFFF, sum = 0
8959 12:16:41.251587 4, 0xFFFF, sum = 0
8960 12:16:41.251640 5, 0xFFFF, sum = 0
8961 12:16:41.251692 6, 0xFFFF, sum = 0
8962 12:16:41.251744 7, 0xFFFF, sum = 0
8963 12:16:41.251796 8, 0xFFFF, sum = 0
8964 12:16:41.251849 9, 0xFFFF, sum = 0
8965 12:16:41.251901 10, 0xFFFF, sum = 0
8966 12:16:41.251952 11, 0xFFFF, sum = 0
8967 12:16:41.252005 12, 0xFFFF, sum = 0
8968 12:16:41.252057 13, 0xFFFF, sum = 0
8969 12:16:41.252110 14, 0x0, sum = 1
8970 12:16:41.252162 15, 0x0, sum = 2
8971 12:16:41.252214 16, 0x0, sum = 3
8972 12:16:41.252266 17, 0x0, sum = 4
8973 12:16:41.252318 best_step = 15
8974 12:16:41.252369
8975 12:16:41.252420 ==
8976 12:16:41.252471 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 12:16:41.252523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 12:16:41.252573 ==
8979 12:16:41.252624 RX Vref Scan: 0
8980 12:16:41.252676
8981 12:16:41.252727 RX Vref 0 -> 0, step: 1
8982 12:16:41.252778
8983 12:16:41.252829 RX Delay 11 -> 252, step: 4
8984 12:16:41.252881 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8985 12:16:41.252932 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8986 12:16:41.252984 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8987 12:16:41.253035 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8988 12:16:41.253086 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8989 12:16:41.253137 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8990 12:16:41.253188 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8991 12:16:41.253239 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8992 12:16:41.253291 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8993 12:16:41.253342 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8994 12:16:41.253393 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8995 12:16:41.253444 iDelay=195, Bit 11, Center 122 (71 ~ 174) 104
8996 12:16:41.253495 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8997 12:16:41.253546 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8998 12:16:41.438127 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8999 12:16:41.438658 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9000 12:16:41.439017 ==
9001 12:16:41.439347 Dram Type= 6, Freq= 0, CH_1, rank 1
9002 12:16:41.439716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9003 12:16:41.440034 ==
9004 12:16:41.440339 DQS Delay:
9005 12:16:41.440645 DQS0 = 0, DQS1 = 0
9006 12:16:41.440946 DQM Delay:
9007 12:16:41.441244 DQM0 = 131, DQM1 = 128
9008 12:16:41.441542 DQ Delay:
9009 12:16:41.441839 DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128
9010 12:16:41.442135 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =128
9011 12:16:41.442429 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =122
9012 12:16:41.442725 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
9013 12:16:41.443018
9014 12:16:41.443309
9015 12:16:41.443623
9016 12:16:41.443917 [DramC_TX_OE_Calibration] TA2
9017 12:16:41.444210 Original DQ_B0 (3 6) =30, OEN = 27
9018 12:16:41.444503 Original DQ_B1 (3 6) =30, OEN = 27
9019 12:16:41.444831 24, 0x0, End_B0=24 End_B1=24
9020 12:16:41.445192 25, 0x0, End_B0=25 End_B1=25
9021 12:16:41.445497 26, 0x0, End_B0=26 End_B1=26
9022 12:16:41.445797 27, 0x0, End_B0=27 End_B1=27
9023 12:16:41.446095 28, 0x0, End_B0=28 End_B1=28
9024 12:16:41.446395 29, 0x0, End_B0=29 End_B1=29
9025 12:16:41.446693 30, 0x0, End_B0=30 End_B1=30
9026 12:16:41.447044 31, 0x4545, End_B0=30 End_B1=30
9027 12:16:41.447359 Byte0 end_step=30 best_step=27
9028 12:16:41.447683 Byte1 end_step=30 best_step=27
9029 12:16:41.447979 Byte0 TX OE(2T, 0.5T) = (3, 3)
9030 12:16:41.448274 Byte1 TX OE(2T, 0.5T) = (3, 3)
9031 12:16:41.448565
9032 12:16:41.448853
9033 12:16:41.449144 [DQSOSCAuto] RK1, (LSB)MR18= 0x101f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
9034 12:16:41.449446 CH1 RK1: MR19=303, MR18=101F
9035 12:16:41.449744 CH1_RK1: MR19=0x303, MR18=0x101F, DQSOSC=394, MR23=63, INC=23, DEC=15
9036 12:16:41.450043 [RxdqsGatingPostProcess] freq 1600
9037 12:16:41.450336 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9038 12:16:41.450629 best DQS0 dly(2T, 0.5T) = (1, 1)
9039 12:16:41.450919 best DQS1 dly(2T, 0.5T) = (1, 1)
9040 12:16:41.451209 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9041 12:16:41.451523 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9042 12:16:41.451819 best DQS0 dly(2T, 0.5T) = (1, 1)
9043 12:16:41.452541 best DQS1 dly(2T, 0.5T) = (1, 1)
9044 12:16:41.453215 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9045 12:16:41.453868 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9046 12:16:41.454455 Pre-setting of DQS Precalculation
9047 12:16:41.455013 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9048 12:16:41.455492 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9049 12:16:41.455934 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9050 12:16:41.456356
9051 12:16:41.456770
9052 12:16:41.457186 [Calibration Summary] 3200 Mbps
9053 12:16:41.457631 CH 0, Rank 0
9054 12:16:41.458093 SW Impedance : PASS
9055 12:16:41.458576 DUTY Scan : NO K
9056 12:16:41.458991 ZQ Calibration : PASS
9057 12:16:41.459433 Jitter Meter : NO K
9058 12:16:41.459855 CBT Training : PASS
9059 12:16:41.460271 Write leveling : PASS
9060 12:16:41.460683 RX DQS gating : PASS
9061 12:16:41.461096 RX DQ/DQS(RDDQC) : PASS
9062 12:16:41.461509 TX DQ/DQS : PASS
9063 12:16:41.461923 RX DATLAT : PASS
9064 12:16:41.462333 RX DQ/DQS(Engine): PASS
9065 12:16:41.462745 TX OE : PASS
9066 12:16:41.463155 All Pass.
9067 12:16:41.463549
9068 12:16:41.463762 CH 0, Rank 1
9069 12:16:41.463952 SW Impedance : PASS
9070 12:16:41.464144 DUTY Scan : NO K
9071 12:16:41.464333 ZQ Calibration : PASS
9072 12:16:41.464522 Jitter Meter : NO K
9073 12:16:41.464744 CBT Training : PASS
9074 12:16:41.465053 Write leveling : PASS
9075 12:16:41.465345 RX DQS gating : PASS
9076 12:16:41.465636 RX DQ/DQS(RDDQC) : PASS
9077 12:16:41.465927 TX DQ/DQS : PASS
9078 12:16:41.466219 RX DATLAT : PASS
9079 12:16:41.466509 RX DQ/DQS(Engine): PASS
9080 12:16:41.466800 TX OE : PASS
9081 12:16:41.467090 All Pass.
9082 12:16:41.467398
9083 12:16:41.467602 CH 1, Rank 0
9084 12:16:41.467796 SW Impedance : PASS
9085 12:16:41.467992 DUTY Scan : NO K
9086 12:16:41.468183 ZQ Calibration : PASS
9087 12:16:41.468375 Jitter Meter : NO K
9088 12:16:41.468570 CBT Training : PASS
9089 12:16:41.468715 Write leveling : PASS
9090 12:16:41.468859 RX DQS gating : PASS
9091 12:16:41.469003 RX DQ/DQS(RDDQC) : PASS
9092 12:16:41.469148 TX DQ/DQS : PASS
9093 12:16:41.469292 RX DATLAT : PASS
9094 12:16:41.469435 RX DQ/DQS(Engine): PASS
9095 12:16:41.469579 TX OE : PASS
9096 12:16:41.469724 All Pass.
9097 12:16:41.469867
9098 12:16:41.470010 CH 1, Rank 1
9099 12:16:41.470154 SW Impedance : PASS
9100 12:16:41.470300 DUTY Scan : NO K
9101 12:16:41.470443 ZQ Calibration : PASS
9102 12:16:41.470587 Jitter Meter : NO K
9103 12:16:41.470731 CBT Training : PASS
9104 12:16:41.470875 Write leveling : PASS
9105 12:16:41.471018 RX DQS gating : PASS
9106 12:16:41.471161 RX DQ/DQS(RDDQC) : PASS
9107 12:16:41.471303 TX DQ/DQS : PASS
9108 12:16:41.471473 RX DATLAT : PASS
9109 12:16:41.471620 RX DQ/DQS(Engine): PASS
9110 12:16:41.471764 TX OE : PASS
9111 12:16:41.471907 All Pass.
9112 12:16:41.472051
9113 12:16:41.472195 DramC Write-DBI on
9114 12:16:41.472338 PER_BANK_REFRESH: Hybrid Mode
9115 12:16:41.472483 TX_TRACKING: ON
9116 12:16:41.472628 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9117 12:16:41.472777 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9118 12:16:41.472923 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9119 12:16:41.473070 [FAST_K] Save calibration result to emmc
9120 12:16:41.473214 sync common calibartion params.
9121 12:16:41.473357 sync cbt_mode0:1, 1:1
9122 12:16:41.473499 dram_init: ddr_geometry: 2
9123 12:16:41.473636 dram_init: ddr_geometry: 2
9124 12:16:41.473752 dram_init: ddr_geometry: 2
9125 12:16:41.473867 0:dram_rank_size:100000000
9126 12:16:41.473985 1:dram_rank_size:100000000
9127 12:16:41.474103 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9128 12:16:41.474220 DFS_SHUFFLE_HW_MODE: ON
9129 12:16:41.474336 dramc_set_vcore_voltage set vcore to 725000
9130 12:16:41.474453 Read voltage for 1600, 0
9131 12:16:41.474568 Vio18 = 0
9132 12:16:41.474686 Vcore = 725000
9133 12:16:41.474802 Vdram = 0
9134 12:16:41.474917 Vddq = 0
9135 12:16:41.475032 Vmddr = 0
9136 12:16:41.475147 switch to 3200 Mbps bootup
9137 12:16:41.475263 [DramcRunTimeConfig]
9138 12:16:41.475387 PHYPLL
9139 12:16:41.475505 DPM_CONTROL_AFTERK: ON
9140 12:16:41.475622 PER_BANK_REFRESH: ON
9141 12:16:41.475738 REFRESH_OVERHEAD_REDUCTION: ON
9142 12:16:41.475854 CMD_PICG_NEW_MODE: OFF
9143 12:16:41.475969 XRTWTW_NEW_MODE: ON
9144 12:16:41.476084 XRTRTR_NEW_MODE: ON
9145 12:16:41.476200 TX_TRACKING: ON
9146 12:16:41.476315 RDSEL_TRACKING: OFF
9147 12:16:41.476431 DQS Precalculation for DVFS: ON
9148 12:16:41.476546 RX_TRACKING: OFF
9149 12:16:41.476660 HW_GATING DBG: ON
9150 12:16:41.476774 ZQCS_ENABLE_LP4: ON
9151 12:16:41.476889 RX_PICG_NEW_MODE: ON
9152 12:16:41.477002 TX_PICG_NEW_MODE: ON
9153 12:16:41.477116 ENABLE_RX_DCM_DPHY: ON
9154 12:16:41.477231 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9155 12:16:41.477346 DUMMY_READ_FOR_TRACKING: OFF
9156 12:16:41.477461 !!! SPM_CONTROL_AFTERK: OFF
9157 12:16:41.477594 !!! SPM could not control APHY
9158 12:16:41.477711 IMPEDANCE_TRACKING: ON
9159 12:16:41.477827 TEMP_SENSOR: ON
9160 12:16:41.477942 HW_SAVE_FOR_SR: OFF
9161 12:16:41.478057 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9162 12:16:41.478173 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9163 12:16:41.478287 Read ODT Tracking: ON
9164 12:16:41.478402 Refresh Rate DeBounce: ON
9165 12:16:41.478529 DFS_NO_QUEUE_FLUSH: ON
9166 12:16:41.478626 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9167 12:16:41.478723 ENABLE_DFS_RUNTIME_MRW: OFF
9168 12:16:41.478820 DDR_RESERVE_NEW_MODE: ON
9169 12:16:41.478917 MR_CBT_SWITCH_FREQ: ON
9170 12:16:41.479012 =========================
9171 12:16:41.479109 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9172 12:16:41.479206 dram_init: ddr_geometry: 2
9173 12:16:41.479302 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9174 12:16:41.479406 dram_init: dram init end (result: 0)
9175 12:16:41.479513 DRAM-K: Full calibration passed in 24401 msecs
9176 12:16:41.479617 MRC: failed to locate region type 0.
9177 12:16:41.479714 DRAM rank0 size:0x100000000,
9178 12:16:41.479810 DRAM rank1 size=0x100000000
9179 12:16:41.479906 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9180 12:16:41.480005 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9181 12:16:41.480102 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9182 12:16:41.480436 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9183 12:16:41.480626 DRAM rank0 size:0x100000000,
9184 12:16:41.480827 DRAM rank1 size=0x100000000
9185 12:16:41.481026 CBMEM:
9186 12:16:41.481225 IMD: root @ 0xfffff000 254 entries.
9187 12:16:41.481381 IMD: root @ 0xffffec00 62 entries.
9188 12:16:41.481533 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9189 12:16:41.481684 WARNING: RO_VPD is uninitialized or empty.
9190 12:16:41.481835 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9191 12:16:41.481988 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9192 12:16:41.482139 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9193 12:16:41.482290 BS: romstage times (exec / console): total (unknown) / 23937 ms
9194 12:16:41.482438
9195 12:16:41.482585
9196 12:16:41.482737 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9197 12:16:41.482888 ARM64: Exception handlers installed.
9198 12:16:41.483038 ARM64: Testing exception
9199 12:16:41.483187 ARM64: Done test exception
9200 12:16:41.483336 Enumerating buses...
9201 12:16:41.483503 Show all devs... Before device enumeration.
9202 12:16:41.483649 Root Device: enabled 1
9203 12:16:41.483778 CPU_CLUSTER: 0: enabled 1
9204 12:16:41.483906 CPU: 00: enabled 1
9205 12:16:41.484034 Compare with tree...
9206 12:16:41.484162 Root Device: enabled 1
9207 12:16:41.484289 CPU_CLUSTER: 0: enabled 1
9208 12:16:41.484417 CPU: 00: enabled 1
9209 12:16:41.484545 Root Device scanning...
9210 12:16:41.484673 scan_static_bus for Root Device
9211 12:16:41.484801 CPU_CLUSTER: 0 enabled
9212 12:16:41.484929 scan_static_bus for Root Device done
9213 12:16:41.485058 scan_bus: bus Root Device finished in 8 msecs
9214 12:16:41.485186 done
9215 12:16:41.485315 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9216 12:16:41.485445 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9217 12:16:41.485575 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9218 12:16:41.485705 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9219 12:16:41.485833 Allocating resources...
9220 12:16:41.485960 Reading resources...
9221 12:16:41.486088 Root Device read_resources bus 0 link: 0
9222 12:16:41.486217 DRAM rank0 size:0x100000000,
9223 12:16:41.486344 DRAM rank1 size=0x100000000
9224 12:16:41.486473 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9225 12:16:41.486601 CPU: 00 missing read_resources
9226 12:16:41.486729 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9227 12:16:41.486858 Root Device read_resources bus 0 link: 0 done
9228 12:16:41.486986 Done reading resources.
9229 12:16:41.487114 Show resources in subtree (Root Device)...After reading.
9230 12:16:41.487243 Root Device child on link 0 CPU_CLUSTER: 0
9231 12:16:41.487380 CPU_CLUSTER: 0 child on link 0 CPU: 00
9232 12:16:41.487514 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9233 12:16:41.487644 CPU: 00
9234 12:16:41.487773 Root Device assign_resources, bus 0 link: 0
9235 12:16:41.487902 CPU_CLUSTER: 0 missing set_resources
9236 12:16:41.488031 Root Device assign_resources, bus 0 link: 0 done
9237 12:16:41.488159 Done setting resources.
9238 12:16:41.488288 Show resources in subtree (Root Device)...After assigning values.
9239 12:16:41.488417 Root Device child on link 0 CPU_CLUSTER: 0
9240 12:16:41.488555 CPU_CLUSTER: 0 child on link 0 CPU: 00
9241 12:16:41.488670 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9242 12:16:41.488782 CPU: 00
9243 12:16:41.488894 Done allocating resources.
9244 12:16:41.489008 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9245 12:16:41.489120 Enabling resources...
9246 12:16:41.489232 done.
9247 12:16:41.489345 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9248 12:16:41.489457 Initializing devices...
9249 12:16:41.489569 Root Device init
9250 12:16:41.489680 init hardware done!
9251 12:16:41.489793 0x00000018: ctrlr->caps
9252 12:16:41.489908 52.000 MHz: ctrlr->f_max
9253 12:16:41.490025 0.400 MHz: ctrlr->f_min
9254 12:16:41.490141 0x40ff8080: ctrlr->voltages
9255 12:16:41.490257 sclk: 390625
9256 12:16:41.490369 Bus Width = 1
9257 12:16:41.490481 sclk: 390625
9258 12:16:41.490594 Bus Width = 1
9259 12:16:41.490705 Early init status = 3
9260 12:16:41.490818 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9261 12:16:41.490932 in-header: 03 fc 00 00 01 00 00 00
9262 12:16:41.491044 in-data: 00
9263 12:16:41.491157 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9264 12:16:41.491271 in-header: 03 fd 00 00 00 00 00 00
9265 12:16:41.491387 in-data:
9266 12:16:41.491465 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9267 12:16:41.491538 in-header: 03 fc 00 00 01 00 00 00
9268 12:16:41.491611 in-data: 00
9269 12:16:41.491684 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9270 12:16:41.491758 in-header: 03 fd 00 00 00 00 00 00
9271 12:16:41.491830 in-data:
9272 12:16:41.491902 [SSUSB] Setting up USB HOST controller...
9273 12:16:41.491975 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9274 12:16:41.492048 [SSUSB] phy power-on done.
9275 12:16:41.492121 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9276 12:16:41.492195 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9277 12:16:41.492269 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9278 12:16:41.492342 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9279 12:16:41.492415 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9280 12:16:41.492488 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9281 12:16:41.492561 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9282 12:16:41.492634 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9283 12:16:41.492708 SPM: binary array size = 0x9dc
9284 12:16:41.492780 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9285 12:16:41.492854 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9286 12:16:41.492927 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9287 12:16:41.493212 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9288 12:16:41.493347 configure_display: Starting display init
9289 12:16:41.493496 anx7625_power_on_init: Init interface.
9290 12:16:41.493650 anx7625_disable_pd_protocol: Disabled PD feature.
9291 12:16:41.493783 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9292 12:16:41.493909 anx7625_start_dp_work: Secure OCM version=00
9293 12:16:41.494022 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9294 12:16:41.494125 sp_tx_get_edid_block: EDID Block = 1
9295 12:16:41.494226 Extracted contents:
9296 12:16:41.494328 header: 00 ff ff ff ff ff ff 00
9297 12:16:41.494429 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9298 12:16:41.494530 version: 01 04
9299 12:16:41.494634 basic params: 95 1f 11 78 0a
9300 12:16:41.494736 chroma info: 76 90 94 55 54 90 27 21 50 54
9301 12:16:41.494837 established: 00 00 00
9302 12:16:41.494938 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9303 12:16:41.495041 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9304 12:16:41.495143 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9305 12:16:41.495245 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9306 12:16:41.495347 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9307 12:16:41.495429 extensions: 00
9308 12:16:41.495495 checksum: fb
9309 12:16:41.495560
9310 12:16:41.495624 Manufacturer: IVO Model 57d Serial Number 0
9311 12:16:41.495690 Made week 0 of 2020
9312 12:16:41.495754 EDID version: 1.4
9313 12:16:41.495819 Digital display
9314 12:16:41.495884 6 bits per primary color channel
9315 12:16:41.495951 DisplayPort interface
9316 12:16:41.496016 Maximum image size: 31 cm x 17 cm
9317 12:16:41.496081 Gamma: 220%
9318 12:16:41.496146 Check DPMS levels
9319 12:16:41.496222 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9320 12:16:41.496293 First detailed timing is preferred timing
9321 12:16:41.496359 Established timings supported:
9322 12:16:41.496424 Standard timings supported:
9323 12:16:41.496490 Detailed timings
9324 12:16:41.496554 Hex of detail: 383680a07038204018303c0035ae10000019
9325 12:16:41.496620 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9326 12:16:41.496686 0780 0798 07c8 0820 hborder 0
9327 12:16:41.496751 0438 043b 0447 0458 vborder 0
9328 12:16:41.496816 -hsync -vsync
9329 12:16:41.496881 Did detailed timing
9330 12:16:41.496946 Hex of detail: 000000000000000000000000000000000000
9331 12:16:41.497010 Manufacturer-specified data, tag 0
9332 12:16:41.497075 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9333 12:16:41.497140 ASCII string: InfoVision
9334 12:16:41.497205 Hex of detail: 000000fe00523134304e574635205248200a
9335 12:16:41.497270 ASCII string: R140NWF5 RH
9336 12:16:41.497334 Checksum
9337 12:16:41.497399 Checksum: 0xfb (valid)
9338 12:16:41.497464 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9339 12:16:41.497528 DSI data_rate: 832800000 bps
9340 12:16:41.497594 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9341 12:16:41.497659 anx7625_parse_edid: pixelclock(138800).
9342 12:16:41.497725 hactive(1920), hsync(48), hfp(24), hbp(88)
9343 12:16:41.497789 vactive(1080), vsync(12), vfp(3), vbp(17)
9344 12:16:41.497854 anx7625_dsi_config: config dsi.
9345 12:16:41.497918 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9346 12:16:41.497983 anx7625_dsi_config: success to config DSI
9347 12:16:41.498047 anx7625_dp_start: MIPI phy setup OK.
9348 12:16:41.498112 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9349 12:16:41.498177 mtk_ddp_mode_set invalid vrefresh 60
9350 12:16:41.498241 main_disp_path_setup
9351 12:16:41.498305 ovl_layer_smi_id_en
9352 12:16:41.498370 ovl_layer_smi_id_en
9353 12:16:41.498434 ccorr_config
9354 12:16:41.498498 aal_config
9355 12:16:41.498570 gamma_config
9356 12:16:41.498628 postmask_config
9357 12:16:41.498686 dither_config
9358 12:16:41.498744 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9359 12:16:41.498803 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9360 12:16:41.498863 Root Device init finished in 552 msecs
9361 12:16:41.498921 CPU_CLUSTER: 0 init
9362 12:16:41.498980 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9363 12:16:41.499039 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9364 12:16:41.499096 APU_MBOX 0x190000b0 = 0x10001
9365 12:16:41.499154 APU_MBOX 0x190001b0 = 0x10001
9366 12:16:41.499212 APU_MBOX 0x190005b0 = 0x10001
9367 12:16:41.499269 APU_MBOX 0x190006b0 = 0x10001
9368 12:16:41.499327 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9369 12:16:41.499397 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9370 12:16:41.499457 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9371 12:16:41.499515 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9372 12:16:41.499573 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9373 12:16:41.499631 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9374 12:16:41.499689 CPU_CLUSTER: 0 init finished in 81 msecs
9375 12:16:41.499747 Devices initialized
9376 12:16:41.499805 Show all devs... After init.
9377 12:16:41.499863 Root Device: enabled 1
9378 12:16:41.499920 CPU_CLUSTER: 0: enabled 1
9379 12:16:41.499978 CPU: 00: enabled 1
9380 12:16:41.500036 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9381 12:16:41.500094 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9382 12:16:41.500152 ELOG: NV offset 0x57f000 size 0x1000
9383 12:16:41.500217 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9384 12:16:41.500278 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9385 12:16:41.500336 ELOG: Event(17) added with size 13 at 2024-01-31 12:16:35 UTC
9386 12:16:41.500394 out: cmd=0x121: 03 db 21 01 00 00 00 00
9387 12:16:41.500452 in-header: 03 45 00 00 2c 00 00 00
9388 12:16:41.500716 in-data: 1a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9389 12:16:41.500834 ELOG: Event(A1) added with size 10 at 2024-01-31 12:16:35 UTC
9390 12:16:41.500954 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9391 12:16:41.501074 ELOG: Event(A0) added with size 9 at 2024-01-31 12:16:35 UTC
9392 12:16:41.501192 elog_add_boot_reason: Logged dev mode boot
9393 12:16:41.501296 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9394 12:16:41.501398 Finalize devices...
9395 12:16:41.501463 Devices finalized
9396 12:16:41.501523 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9397 12:16:41.501582 Writing coreboot table at 0xffe64000
9398 12:16:41.501640 0. 000000000010a000-0000000000113fff: RAMSTAGE
9399 12:16:41.501698 1. 0000000040000000-00000000400fffff: RAM
9400 12:16:41.501756 2. 0000000040100000-000000004032afff: RAMSTAGE
9401 12:16:41.501814 3. 000000004032b000-00000000545fffff: RAM
9402 12:16:41.501871 4. 0000000054600000-000000005465ffff: BL31
9403 12:16:41.501929 5. 0000000054660000-00000000ffe63fff: RAM
9404 12:16:41.501987 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9405 12:16:41.502045 7. 0000000100000000-000000023fffffff: RAM
9406 12:16:41.502103 Passing 5 GPIOs to payload:
9407 12:16:41.502160 NAME | PORT | POLARITY | VALUE
9408 12:16:41.502218 EC in RW | 0x000000aa | low | undefined
9409 12:16:41.502276 EC interrupt | 0x00000005 | low | undefined
9410 12:16:41.502334 TPM interrupt | 0x000000ab | high | undefined
9411 12:16:41.502392 SD card detect | 0x00000011 | high | undefined
9412 12:16:41.502450 speaker enable | 0x00000093 | high | undefined
9413 12:16:41.502508 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9414 12:16:41.502566 in-header: 03 f9 00 00 02 00 00 00
9415 12:16:41.502624 in-data: 02 00
9416 12:16:41.502681 ADC[4]: Raw value=903325 ID=7
9417 12:16:41.502738 ADC[3]: Raw value=213916 ID=1
9418 12:16:41.502796 RAM Code: 0x71
9419 12:16:41.502853 ADC[6]: Raw value=74630 ID=0
9420 12:16:41.502910 ADC[5]: Raw value=213546 ID=1
9421 12:16:41.502967 SKU Code: 0x1
9422 12:16:41.503025 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 550f
9423 12:16:41.503083 coreboot table: 964 bytes.
9424 12:16:41.503141 IMD ROOT 0. 0xfffff000 0x00001000
9425 12:16:41.503198 IMD SMALL 1. 0xffffe000 0x00001000
9426 12:16:41.503255 RO MCACHE 2. 0xffffc000 0x00001104
9427 12:16:41.503313 CONSOLE 3. 0xfff7c000 0x00080000
9428 12:16:41.503377 FMAP 4. 0xfff7b000 0x00000452
9429 12:16:41.503436 TIME STAMP 5. 0xfff7a000 0x00000910
9430 12:16:41.503493 VBOOT WORK 6. 0xfff66000 0x00014000
9431 12:16:41.503562 RAMOOPS 7. 0xffe66000 0x00100000
9432 12:16:41.503619 COREBOOT 8. 0xffe64000 0x00002000
9433 12:16:41.503675 IMD small region:
9434 12:16:41.503737 IMD ROOT 0. 0xffffec00 0x00000400
9435 12:16:41.503796 VPD 1. 0xffffeb80 0x0000006c
9436 12:16:41.503852 MMC STATUS 2. 0xffffeb60 0x00000004
9437 12:16:41.503905 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9438 12:16:41.503958 Probing TPM: done!
9439 12:16:41.504018 Connected to device vid:did:rid of 1ae0:0028:00
9440 12:16:41.504072 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9441 12:16:41.504126 Initialized TPM device CR50 revision 0
9442 12:16:41.504181 Checking cr50 for pending updates
9443 12:16:41.504234 Reading cr50 TPM mode
9444 12:16:41.504287 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9445 12:16:41.504340 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9446 12:16:41.504398 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9447 12:16:41.504451 Checking segment from ROM address 0x40100000
9448 12:16:41.504504 Checking segment from ROM address 0x4010001c
9449 12:16:41.504561 Loading segment from ROM address 0x40100000
9450 12:16:41.504614 code (compression=0)
9451 12:16:41.504667 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9452 12:16:41.504723 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9453 12:16:41.504776 it's not compressed!
9454 12:16:41.504829 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9455 12:16:41.504881 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9456 12:16:41.504937 Loading segment from ROM address 0x4010001c
9457 12:16:41.504989 Entry Point 0x80000000
9458 12:16:41.505041 Loaded segments
9459 12:16:41.505093 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9460 12:16:41.505148 Jumping to boot code at 0x80000000(0xffe64000)
9461 12:16:41.505201 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9462 12:16:41.505254 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9463 12:16:41.505307 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9464 12:16:41.505360 Checking segment from ROM address 0x40100000
9465 12:16:41.505413 Checking segment from ROM address 0x4010001c
9466 12:16:41.505466 Loading segment from ROM address 0x40100000
9467 12:16:41.505519 code (compression=1)
9468 12:16:41.505571 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9469 12:16:41.505624 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9470 12:16:41.505676 using LZMA
9471 12:16:41.505729 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9472 12:16:41.505781 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9473 12:16:41.505834 Loading segment from ROM address 0x4010001c
9474 12:16:41.505886 Entry Point 0x54601000
9475 12:16:41.505938 Loaded segments
9476 12:16:41.505990 NOTICE: MT8192 bl31_setup
9477 12:16:41.506238 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9478 12:16:41.506343 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9479 12:16:41.506453 WARNING: region 0:
9480 12:16:41.506561 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 12:16:41.506668 WARNING: region 1:
9482 12:16:41.506764 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9483 12:16:41.506856 WARNING: region 2:
9484 12:16:41.506915 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9485 12:16:41.506970 WARNING: region 3:
9486 12:16:41.507023 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9487 12:16:41.507077 WARNING: region 4:
9488 12:16:41.507130 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9489 12:16:41.507183 WARNING: region 5:
9490 12:16:41.507235 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 12:16:41.507288 WARNING: region 6:
9492 12:16:41.507342 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 12:16:41.507402 WARNING: region 7:
9494 12:16:41.507455 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 12:16:41.507508 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9496 12:16:41.507560 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9497 12:16:41.507613 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9498 12:16:41.507665 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9499 12:16:41.507718 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9500 12:16:41.507770 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9501 12:16:41.507823 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9502 12:16:41.507876 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9503 12:16:41.507928 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9504 12:16:41.507981 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9505 12:16:41.508033 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9506 12:16:41.508085 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9507 12:16:41.508137 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9508 12:16:41.508189 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9509 12:16:41.508259 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9510 12:16:41.508354 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9511 12:16:41.508413 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9512 12:16:41.508467 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9513 12:16:41.508520 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9514 12:16:41.508584 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9515 12:16:41.508635 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9516 12:16:41.508686 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9517 12:16:41.508736 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9518 12:16:41.508787 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9519 12:16:41.508837 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9520 12:16:41.508888 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9521 12:16:41.508938 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9522 12:16:41.508989 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9523 12:16:41.509039 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9524 12:16:41.509089 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9525 12:16:41.509139 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9526 12:16:41.509190 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9527 12:16:41.509240 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9528 12:16:41.509290 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9529 12:16:41.509340 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9530 12:16:41.509390 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9531 12:16:41.509440 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9532 12:16:41.509490 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9533 12:16:41.509540 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9534 12:16:41.509592 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9535 12:16:41.509643 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9536 12:16:41.509693 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9537 12:16:41.509743 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9538 12:16:41.509793 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9539 12:16:41.509844 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9540 12:16:41.509894 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9541 12:16:41.509945 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9542 12:16:41.509995 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9543 12:16:41.510045 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9544 12:16:41.510095 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9545 12:16:41.510146 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9546 12:16:41.510195 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9547 12:16:41.510246 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9548 12:16:41.510295 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9549 12:16:41.510346 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9550 12:16:41.510396 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9551 12:16:41.510446 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9552 12:16:41.510497 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9553 12:16:41.510547 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9554 12:16:41.510597 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9555 12:16:41.510647 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9556 12:16:41.510697 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9557 12:16:41.510747 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9558 12:16:41.510797 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9559 12:16:41.511041 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9560 12:16:41.511129 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9561 12:16:41.511233 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9562 12:16:41.511337 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9563 12:16:41.511485 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9564 12:16:41.511580 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9565 12:16:41.511669 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9566 12:16:41.511729 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9567 12:16:41.511782 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9568 12:16:41.511833 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9569 12:16:41.511884 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9570 12:16:41.511934 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9571 12:16:41.511985 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9572 12:16:41.512036 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9573 12:16:41.512087 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9574 12:16:41.512137 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9575 12:16:41.512188 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9576 12:16:41.512239 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9577 12:16:41.512289 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9578 12:16:41.512339 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9579 12:16:41.512389 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9580 12:16:41.512440 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9581 12:16:41.512490 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9582 12:16:41.512540 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9583 12:16:41.512590 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9584 12:16:41.512640 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9585 12:16:41.512690 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9586 12:16:41.512740 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9587 12:16:41.512790 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9588 12:16:41.512840 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9589 12:16:41.512891 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9590 12:16:41.512941 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9591 12:16:41.512991 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9592 12:16:41.513042 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9593 12:16:41.513092 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9594 12:16:41.513142 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9595 12:16:41.513192 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9596 12:16:41.513242 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9597 12:16:41.513292 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9598 12:16:41.513342 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9599 12:16:41.513393 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9600 12:16:41.513444 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9601 12:16:41.513494 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9602 12:16:41.513544 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9603 12:16:41.513594 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9604 12:16:41.513645 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9605 12:16:41.513696 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9606 12:16:41.513746 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9607 12:16:41.513796 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9608 12:16:41.513846 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9609 12:16:41.513897 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9610 12:16:41.513947 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9611 12:16:41.513997 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9612 12:16:41.514047 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9613 12:16:41.514097 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9614 12:16:41.514147 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9615 12:16:41.514198 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9616 12:16:41.514247 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9617 12:16:41.514298 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9618 12:16:41.514348 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9619 12:16:41.514398 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9620 12:16:41.514448 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9621 12:16:41.514498 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9622 12:16:41.514548 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9623 12:16:41.514598 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9624 12:16:41.514651 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9625 12:16:41.514702 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9626 12:16:41.514752 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9627 12:16:41.514806 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9628 12:16:41.514857 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9629 12:16:41.514907 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9630 12:16:41.514957 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9631 12:16:41.515007 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9632 12:16:41.515058 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9633 12:16:41.515108 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9634 12:16:41.515158 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9635 12:16:41.515208 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9636 12:16:41.515441 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9637 12:16:41.515584 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9638 12:16:41.515665 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9639 12:16:41.515745 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9640 12:16:41.515825 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9641 12:16:41.515904 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9642 12:16:41.515983 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9643 12:16:41.516062 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9644 12:16:41.516141 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9645 12:16:41.516220 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9646 12:16:41.516298 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9647 12:16:41.516377 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9648 12:16:41.516456 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9649 12:16:41.516535 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9650 12:16:41.516614 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9651 12:16:41.516692 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9652 12:16:41.516771 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9653 12:16:41.516850 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9654 12:16:41.516929 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9655 12:16:41.517007 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9656 12:16:41.517086 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9657 12:16:41.517167 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9658 12:16:41.517246 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9659 12:16:41.517321 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9660 12:16:41.517373 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9661 12:16:41.517424 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9662 12:16:41.517474 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9663 12:16:41.517528 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9664 12:16:41.517582 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9665 12:16:41.517633 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9666 12:16:41.517686 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9667 12:16:41.517737 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9668 12:16:41.517788 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9669 12:16:41.517839 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9670 12:16:41.517889 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9671 12:16:41.517938 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9672 12:16:41.517988 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9673 12:16:41.518038 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9674 12:16:41.518088 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9675 12:16:41.518138 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9676 12:16:41.518188 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9677 12:16:41.518237 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9678 12:16:41.518288 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9679 12:16:41.518337 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9680 12:16:41.518387 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9681 12:16:41.518437 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9682 12:16:41.518487 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9683 12:16:41.518536 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9684 12:16:41.518586 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9685 12:16:41.518637 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9686 12:16:41.518688 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9687 12:16:41.518738 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9688 12:16:41.518788 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9689 12:16:41.518838 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9690 12:16:41.518888 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9691 12:16:41.518938 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9692 12:16:41.518988 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9693 12:16:41.519038 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9694 12:16:41.519088 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9695 12:16:41.519138 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9696 12:16:41.519188 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9697 12:16:41.519239 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9698 12:16:41.519290 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9699 12:16:41.519340 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9700 12:16:41.519421 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9701 12:16:41.519485 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9702 12:16:41.519535 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9703 12:16:41.519585 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9704 12:16:41.519635 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9705 12:16:41.519686 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9706 12:16:41.519736 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9707 12:16:41.519801 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9708 12:16:41.519864 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9709 12:16:41.519915 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9710 12:16:41.519965 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9711 12:16:41.520208 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9712 12:16:41.520265 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9713 12:16:41.520317 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9714 12:16:41.520369 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9715 12:16:41.520419 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9716 12:16:41.520470 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9717 12:16:41.520521 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9718 12:16:41.520572 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9719 12:16:41.520622 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9720 12:16:41.520673 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9721 12:16:41.520723 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9722 12:16:41.520774 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9723 12:16:41.520824 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9724 12:16:41.520874 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9725 12:16:41.520924 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9726 12:16:41.520974 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9727 12:16:41.521024 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9728 12:16:41.521074 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9729 12:16:41.521124 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9730 12:16:41.521174 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9731 12:16:41.521225 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9732 12:16:41.521276 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9733 12:16:41.521326 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9734 12:16:41.521377 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9735 12:16:41.521426 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9736 12:16:41.521476 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9737 12:16:41.521527 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9738 12:16:41.521577 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9739 12:16:41.521627 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9740 12:16:41.521678 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9741 12:16:41.521728 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9742 12:16:41.521778 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9743 12:16:41.521828 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9744 12:16:41.521879 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9745 12:16:41.521929 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9746 12:16:41.521979 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9747 12:16:41.522029 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9748 12:16:41.522079 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9749 12:16:41.522129 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9750 12:16:41.522179 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9751 12:16:41.522230 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9752 12:16:41.522280 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9753 12:16:41.522330 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9754 12:16:41.522380 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9755 12:16:41.522430 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9756 12:16:41.522480 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9757 12:16:41.522530 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9758 12:16:41.522580 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9759 12:16:41.522631 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9760 12:16:41.522681 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9761 12:16:41.522731 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9762 12:16:41.522781 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9763 12:16:41.522831 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9764 12:16:41.522882 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9765 12:16:41.522933 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9766 12:16:41.522983 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9767 12:16:41.523034 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9768 12:16:41.523084 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9769 12:16:41.523134 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9770 12:16:41.523185 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9771 12:16:41.523235 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9772 12:16:41.523285 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9773 12:16:41.523335 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9774 12:16:41.523412 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9775 12:16:41.523476 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9776 12:16:41.523527 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9777 12:16:41.523577 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9778 12:16:41.523627 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9779 12:16:41.523677 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9780 12:16:41.523727 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9781 12:16:41.523777 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9782 12:16:41.523843 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9783 12:16:41.523894 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9784 12:16:41.523945 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9785 12:16:41.523996 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9786 12:16:41.524059 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9787 12:16:41.524109 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9788 12:16:41.524160 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9789 12:16:41.524210 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9790 12:16:41.524455 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9791 12:16:41.524516 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9792 12:16:41.524568 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9793 12:16:41.524620 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9794 12:16:41.524671 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9795 12:16:41.524721 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9796 12:16:41.524771 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9797 12:16:41.524823 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9798 12:16:41.524874 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9799 12:16:41.524924 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9800 12:16:41.524975 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9801 12:16:41.525025 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9802 12:16:41.525076 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9803 12:16:41.525127 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9804 12:16:41.525177 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9805 12:16:41.525227 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9806 12:16:41.525277 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9807 12:16:41.525328 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9808 12:16:41.525378 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9809 12:16:41.525428 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9810 12:16:41.525478 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9811 12:16:41.525529 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9812 12:16:41.525579 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9813 12:16:41.525629 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9814 12:16:41.525679 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9815 12:16:41.525729 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9816 12:16:41.525779 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9817 12:16:41.525829 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9818 12:16:41.525879 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9819 12:16:41.525929 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9820 12:16:41.525979 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9821 12:16:41.526030 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9822 12:16:41.526079 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9823 12:16:41.526129 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9824 12:16:41.526180 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9825 12:16:41.526229 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9826 12:16:41.526280 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9827 12:16:41.526330 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9828 12:16:41.526380 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9829 12:16:41.526431 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9830 12:16:41.526481 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9831 12:16:41.526530 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9832 12:16:41.526580 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9833 12:16:41.526630 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9834 12:16:41.526679 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9835 12:16:41.526730 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9836 12:16:41.526780 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9837 12:16:41.526830 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9838 12:16:41.526881 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9839 12:16:41.526931 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9840 12:16:41.526981 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9841 12:16:41.527031 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9842 12:16:41.527081 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9843 12:16:41.527131 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9844 12:16:41.527182 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9845 12:16:41.527231 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9846 12:16:41.527281 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9847 12:16:41.527331 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9848 12:16:41.527407 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9849 12:16:41.527471 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9850 12:16:41.527521 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9851 12:16:41.527572 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9852 12:16:41.527621 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9853 12:16:41.527672 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9854 12:16:41.527722 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9855 12:16:41.527773 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9856 12:16:41.527823 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9857 12:16:41.527873 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9858 12:16:41.527923 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9859 12:16:41.527974 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9860 12:16:41.528024 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9861 12:16:41.528075 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9862 12:16:41.528126 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9863 12:16:41.528176 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9864 12:16:41.528225 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9865 12:16:41.528474 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9866 12:16:41.528532 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9867 12:16:41.528583 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9868 12:16:41.528634 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9869 12:16:41.528685 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9870 12:16:41.528736 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9871 12:16:41.528787 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9872 12:16:41.528838 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9873 12:16:41.528888 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9874 12:16:41.528939 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9875 12:16:41.528989 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9876 12:16:41.529039 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9877 12:16:41.529089 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9878 12:16:41.529140 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9879 12:16:41.529190 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9880 12:16:41.529240 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9881 12:16:41.529290 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9882 12:16:41.529341 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9883 12:16:41.529391 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9884 12:16:41.529441 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9885 12:16:41.529491 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9886 12:16:41.529542 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9887 12:16:41.529612 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9888 12:16:41.529664 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9889 12:16:41.529714 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9890 12:16:41.529765 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9891 12:16:41.529815 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9892 12:16:41.529866 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9893 12:16:41.808325 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9894 12:16:41.808832 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9895 12:16:41.809158 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9896 12:16:41.809459 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9897 12:16:41.809747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9898 12:16:41.810033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9899 12:16:41.810310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9900 12:16:41.810585 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9901 12:16:41.810856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9902 12:16:41.811126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9903 12:16:41.811460 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9904 12:16:41.811744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9905 12:16:41.812014 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9906 12:16:41.812285 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9907 12:16:41.812551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9908 12:16:41.812820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9909 12:16:41.813084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9910 12:16:41.813351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9911 12:16:41.813616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9912 12:16:41.813880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9913 12:16:41.814144 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9914 12:16:41.814413 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9915 12:16:41.814677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9916 12:16:41.814944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9917 12:16:41.815210 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9918 12:16:41.815516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9919 12:16:41.815786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9920 12:16:41.816051 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9921 12:16:41.816408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9922 12:16:41.816685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9923 12:16:41.816951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9924 12:16:41.817219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9925 12:16:41.817487 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9926 12:16:41.817755 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9927 12:16:41.818019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9928 12:16:41.818284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9929 12:16:41.818548 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9930 12:16:41.818814 INFO: [APUAPC] vio 0
9931 12:16:41.819078 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9932 12:16:41.819343 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9933 12:16:41.819654 INFO: [APUAPC] D0_APC_0: 0x400510
9934 12:16:41.819921 INFO: [APUAPC] D0_APC_1: 0x0
9935 12:16:41.820185 INFO: [APUAPC] D0_APC_2: 0x1540
9936 12:16:41.820447 INFO: [APUAPC] D0_APC_3: 0x0
9937 12:16:41.820709 INFO: [APUAPC] D1_APC_0: 0xffffffff
9938 12:16:41.820972 INFO: [APUAPC] D1_APC_1: 0xffffffff
9939 12:16:41.821234 INFO: [APUAPC] D1_APC_2: 0x3fffff
9940 12:16:41.821498 INFO: [APUAPC] D1_APC_3: 0x0
9941 12:16:41.821762 INFO: [APUAPC] D2_APC_0: 0xffffffff
9942 12:16:41.822408 INFO: [APUAPC] D2_APC_1: 0xffffffff
9943 12:16:41.822710 INFO: [APUAPC] D2_APC_2: 0x3fffff
9944 12:16:41.822985 INFO: [APUAPC] D2_APC_3: 0x0
9945 12:16:41.823252 INFO: [APUAPC] D3_APC_0: 0xffffffff
9946 12:16:41.823570 INFO: [APUAPC] D3_APC_1: 0xffffffff
9947 12:16:41.823838 INFO: [APUAPC] D3_APC_2: 0x3fffff
9948 12:16:41.824104 INFO: [APUAPC] D3_APC_3: 0x0
9949 12:16:41.824370 INFO: [APUAPC] D4_APC_0: 0xffffffff
9950 12:16:41.824635 INFO: [APUAPC] D4_APC_1: 0xffffffff
9951 12:16:41.824899 INFO: [APUAPC] D4_APC_2: 0x3fffff
9952 12:16:41.825165 INFO: [APUAPC] D4_APC_3: 0x0
9953 12:16:41.825431 INFO: [APUAPC] D5_APC_0: 0xffffffff
9954 12:16:41.825694 INFO: [APUAPC] D5_APC_1: 0xffffffff
9955 12:16:41.825960 INFO: [APUAPC] D5_APC_2: 0x3fffff
9956 12:16:41.826223 INFO: [APUAPC] D5_APC_3: 0x0
9957 12:16:41.826486 INFO: [APUAPC] D6_APC_0: 0xffffffff
9958 12:16:41.826751 INFO: [APUAPC] D6_APC_1: 0xffffffff
9959 12:16:41.827017 INFO: [APUAPC] D6_APC_2: 0x3fffff
9960 12:16:41.827279 INFO: [APUAPC] D6_APC_3: 0x0
9961 12:16:41.827595 INFO: [APUAPC] D7_APC_0: 0xffffffff
9962 12:16:41.827864 INFO: [APUAPC] D7_APC_1: 0xffffffff
9963 12:16:41.828128 INFO: [APUAPC] D7_APC_2: 0x3fffff
9964 12:16:41.828389 INFO: [APUAPC] D7_APC_3: 0x0
9965 12:16:41.828651 INFO: [APUAPC] D8_APC_0: 0xffffffff
9966 12:16:41.828914 INFO: [APUAPC] D8_APC_1: 0xffffffff
9967 12:16:41.829176 INFO: [APUAPC] D8_APC_2: 0x3fffff
9968 12:16:41.829437 INFO: [APUAPC] D8_APC_3: 0x0
9969 12:16:41.829700 INFO: [APUAPC] D9_APC_0: 0xffffffff
9970 12:16:41.829964 INFO: [APUAPC] D9_APC_1: 0xffffffff
9971 12:16:41.830225 INFO: [APUAPC] D9_APC_2: 0x3fffff
9972 12:16:41.830489 INFO: [APUAPC] D9_APC_3: 0x0
9973 12:16:41.830750 INFO: [APUAPC] D10_APC_0: 0xffffffff
9974 12:16:41.831014 INFO: [APUAPC] D10_APC_1: 0xffffffff
9975 12:16:41.831276 INFO: [APUAPC] D10_APC_2: 0x3fffff
9976 12:16:41.831562 INFO: [APUAPC] D10_APC_3: 0x0
9977 12:16:41.831831 INFO: [APUAPC] D11_APC_0: 0xffffffff
9978 12:16:41.832020 INFO: [APUAPC] D11_APC_1: 0xffffffff
9979 12:16:41.832212 INFO: [APUAPC] D11_APC_2: 0x3fffff
9980 12:16:41.832403 INFO: [APUAPC] D11_APC_3: 0x0
9981 12:16:41.832590 INFO: [APUAPC] D12_APC_0: 0xffffffff
9982 12:16:41.832781 INFO: [APUAPC] D12_APC_1: 0xffffffff
9983 12:16:41.832969 INFO: [APUAPC] D12_APC_2: 0x3fffff
9984 12:16:41.833159 INFO: [APUAPC] D12_APC_3: 0x0
9985 12:16:41.833348 INFO: [APUAPC] D13_APC_0: 0xffffffff
9986 12:16:41.833539 INFO: [APUAPC] D13_APC_1: 0xffffffff
9987 12:16:41.833729 INFO: [APUAPC] D13_APC_2: 0x3fffff
9988 12:16:41.833919 INFO: [APUAPC] D13_APC_3: 0x0
9989 12:16:41.834106 INFO: [APUAPC] D14_APC_0: 0xffffffff
9990 12:16:41.834294 INFO: [APUAPC] D14_APC_1: 0xffffffff
9991 12:16:41.834484 INFO: [APUAPC] D14_APC_2: 0x3fffff
9992 12:16:41.834672 INFO: [APUAPC] D14_APC_3: 0x0
9993 12:16:41.834862 INFO: [APUAPC] D15_APC_0: 0xffffffff
9994 12:16:41.835050 INFO: [APUAPC] D15_APC_1: 0xffffffff
9995 12:16:41.835239 INFO: [APUAPC] D15_APC_2: 0x3fffff
9996 12:16:41.835444 INFO: [APUAPC] D15_APC_3: 0x0
9997 12:16:41.835636 INFO: [APUAPC] APC_CON: 0x4
9998 12:16:41.835823 INFO: [NOCDAPC] D0_APC_0: 0x0
9999 12:16:41.836014 INFO: [NOCDAPC] D0_APC_1: 0x0
10000 12:16:41.836203 INFO: [NOCDAPC] D1_APC_0: 0x0
10001 12:16:41.836392 INFO: [NOCDAPC] D1_APC_1: 0xfff
10002 12:16:41.836583 INFO: [NOCDAPC] D2_APC_0: 0x0
10003 12:16:41.836808 INFO: [NOCDAPC] D2_APC_1: 0xfff
10004 12:16:41.836973 INFO: [NOCDAPC] D3_APC_0: 0x0
10005 12:16:41.837117 INFO: [NOCDAPC] D3_APC_1: 0xfff
10006 12:16:41.837261 INFO: [NOCDAPC] D4_APC_0: 0x0
10007 12:16:41.837404 INFO: [NOCDAPC] D4_APC_1: 0xfff
10008 12:16:41.837549 INFO: [NOCDAPC] D5_APC_0: 0x0
10009 12:16:41.837692 INFO: [NOCDAPC] D5_APC_1: 0xfff
10010 12:16:41.837834 INFO: [NOCDAPC] D6_APC_0: 0x0
10011 12:16:41.837975 INFO: [NOCDAPC] D6_APC_1: 0xfff
10012 12:16:41.838119 INFO: [NOCDAPC] D7_APC_0: 0x0
10013 12:16:41.838260 INFO: [NOCDAPC] D7_APC_1: 0xfff
10014 12:16:41.838403 INFO: [NOCDAPC] D8_APC_0: 0x0
10015 12:16:41.838546 INFO: [NOCDAPC] D8_APC_1: 0xfff
10016 12:16:41.838691 INFO: [NOCDAPC] D9_APC_0: 0x0
10017 12:16:41.838833 INFO: [NOCDAPC] D9_APC_1: 0xfff
10018 12:16:41.838976 INFO: [NOCDAPC] D10_APC_0: 0x0
10019 12:16:41.839119 INFO: [NOCDAPC] D10_APC_1: 0xfff
10020 12:16:41.839264 INFO: [NOCDAPC] D11_APC_0: 0x0
10021 12:16:41.839428 INFO: [NOCDAPC] D11_APC_1: 0xfff
10022 12:16:41.839576 INFO: [NOCDAPC] D12_APC_0: 0x0
10023 12:16:41.839720 INFO: [NOCDAPC] D12_APC_1: 0xfff
10024 12:16:41.839864 INFO: [NOCDAPC] D13_APC_0: 0x0
10025 12:16:41.840006 INFO: [NOCDAPC] D13_APC_1: 0xfff
10026 12:16:41.840149 INFO: [NOCDAPC] D14_APC_0: 0x0
10027 12:16:41.840293 INFO: [NOCDAPC] D14_APC_1: 0xfff
10028 12:16:41.840436 INFO: [NOCDAPC] D15_APC_0: 0x0
10029 12:16:41.840578 INFO: [NOCDAPC] D15_APC_1: 0xfff
10030 12:16:41.840739 INFO: [NOCDAPC] APC_CON: 0x4
10031 12:16:41.840889 INFO: [APUAPC] set_apusys_apc done
10032 12:16:41.841033 INFO: [DEVAPC] devapc_init done
10033 12:16:41.841176 INFO: GICv3 without legacy support detected.
10034 12:16:41.841319 INFO: ARM GICv3 driver initialized in EL3
10035 12:16:41.841463 INFO: Maximum SPI INTID supported: 639
10036 12:16:41.841607 INFO: BL31: Initializing runtime services
10037 12:16:41.841750 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10038 12:16:41.841890 INFO: SPM: enable CPC mode
10039 12:16:41.842007 INFO: mcdi ready for mcusys-off-idle and system suspend
10040 12:16:41.842123 INFO: BL31: Preparing for EL3 exit to normal world
10041 12:16:41.842238 INFO: Entry point address = 0x80000000
10042 12:16:41.842353 INFO: SPSR = 0x8
10043 12:16:41.842468
10044 12:16:41.842582
10045 12:16:41.842697
10046 12:16:41.842811 Starting depthcharge on Spherion...
10047 12:16:41.842926
10048 12:16:41.843042 Wipe memory regions:
10049 12:16:41.843157
10050 12:16:41.843271 [0x00000040000000, 0x00000054600000)
10051 12:16:41.843403
10052 12:16:41.843521 [0x00000054660000, 0x00000080000000)
10053 12:16:41.843636
10054 12:16:41.843750 [0x000000821a7280, 0x000000ffe64000)
10055 12:16:41.843864
10056 12:16:41.843979 [0x00000100000000, 0x00000240000000)
10057 12:16:41.845098 end: 2.2.3 depthcharge-start (duration 00:00:32) [common]
10058 12:16:41.845342 start: 2.2.4 bootloader-commands (timeout 00:04:22) [common]
10059 12:16:41.845514 Setting prompt string to ['asurada:']
10060 12:16:41.845686 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:22)
10061 12:16:41.879686
10062 12:16:41.881982 Initializing XHCI USB controller at 0x11200000.
10063 12:16:42.921333
10064 12:16:42.924102 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10065 12:16:42.924525
10066 12:16:42.924855
10067 12:16:42.925167
10068 12:16:42.925922 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10070 12:16:43.027218 asurada: tftpboot 192.168.201.1 12669531/tftp-deploy-vtw011t9/kernel/image.itb 12669531/tftp-deploy-vtw011t9/kernel/cmdline
10071 12:16:43.027949 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10072 12:16:43.028477 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10073 12:16:43.032965 tftpboot 192.168.201.1 12669531/tftp-deploy-vtw011t9/kernel/image.itp-deploy-vtw011t9/kernel/cmdline
10074 12:16:43.033548
10075 12:16:43.033913 Waiting for link
10076 12:16:43.193718
10077 12:16:43.194273 R8152: Initializing
10078 12:16:43.194644
10079 12:16:43.196736 Version 6 (ocp_data = 5c30)
10080 12:16:43.197293
10081 12:16:43.200136 R8152: Done initializing
10082 12:16:43.200709
10083 12:16:43.201079 Adding net device
10084 12:16:45.099263
10085 12:16:45.099896 done.
10086 12:16:45.100280
10087 12:16:45.100624 MAC: 00:24:32:30:7c:7b
10088 12:16:45.100951
10089 12:16:45.102351 Sending DHCP discover... done.
10090 12:16:45.102814
10091 12:16:45.106296 Waiting for reply... done.
10092 12:16:45.106756
10093 12:16:45.109312 Sending DHCP request... done.
10094 12:16:45.109728
10095 12:16:45.110054 Waiting for reply... done.
10096 12:16:45.110360
10097 12:16:45.112294 My ip is 192.168.201.14
10098 12:16:45.112710
10099 12:16:45.115835 The DHCP server ip is 192.168.201.1
10100 12:16:45.116252
10101 12:16:45.119252 TFTP server IP predefined by user: 192.168.201.1
10102 12:16:45.119826
10103 12:16:45.125933 Bootfile predefined by user: 12669531/tftp-deploy-vtw011t9/kernel/image.itb
10104 12:16:45.126478
10105 12:16:45.129263 Sending tftp read request... done.
10106 12:16:45.129776
10107 12:16:45.138556 Waiting for the transfer...
10108 12:16:45.139016
10109 12:16:45.792426 00000000 ################################################################
10110 12:16:45.792937
10111 12:16:46.446417 00080000 ################################################################
10112 12:16:46.446937
10113 12:16:47.130389 00100000 ################################################################
10114 12:16:47.130897
10115 12:16:47.801669 00180000 ################################################################
10116 12:16:47.802180
10117 12:16:48.463009 00200000 ################################################################
10118 12:16:48.463565
10119 12:16:49.142027 00280000 ################################################################
10120 12:16:49.142550
10121 12:16:49.818112 00300000 ################################################################
10122 12:16:49.818643
10123 12:16:50.489937 00380000 ################################################################
10124 12:16:50.490460
10125 12:16:51.163258 00400000 ################################################################
10126 12:16:51.163848
10127 12:16:51.842853 00480000 ################################################################
10128 12:16:51.843415
10129 12:16:52.522777 00500000 ################################################################
10130 12:16:52.523292
10131 12:16:53.195642 00580000 ################################################################
10132 12:16:53.196146
10133 12:16:53.868539 00600000 ################################################################
10134 12:16:53.869046
10135 12:16:54.545512 00680000 ################################################################
10136 12:16:54.546056
10137 12:16:55.223209 00700000 ################################################################
10138 12:16:55.223815
10139 12:16:55.903888 00780000 ################################################################
10140 12:16:55.904469
10141 12:16:56.581615 00800000 ################################################################
10142 12:16:56.582174
10143 12:16:57.271823 00880000 ################################################################
10144 12:16:57.272397
10145 12:16:57.946097 00900000 ################################################################
10146 12:16:57.946632
10147 12:16:58.608973 00980000 ################################################################
10148 12:16:58.609627
10149 12:16:59.279876 00a00000 ################################################################
10150 12:16:59.280397
10151 12:16:59.953232 00a80000 ################################################################
10152 12:16:59.953748
10153 12:17:00.603639 00b00000 ################################################################
10154 12:17:00.604253
10155 12:17:01.288291 00b80000 ################################################################
10156 12:17:01.288788
10157 12:17:01.893258 00c00000 ################################################################
10158 12:17:01.893410
10159 12:17:02.421425 00c80000 ################################################################
10160 12:17:02.421561
10161 12:17:02.961117 00d00000 ################################################################
10162 12:17:02.961287
10163 12:17:03.521548 00d80000 ################################################################
10164 12:17:03.521698
10165 12:17:04.082301 00e00000 ################################################################
10166 12:17:04.082448
10167 12:17:04.652941 00e80000 ################################################################
10168 12:17:04.653088
10169 12:17:05.221416 00f00000 ################################################################
10170 12:17:05.221565
10171 12:17:05.775250 00f80000 ################################################################
10172 12:17:05.775439
10173 12:17:06.329240 01000000 ################################################################
10174 12:17:06.329390
10175 12:17:06.869008 01080000 ################################################################
10176 12:17:06.869159
10177 12:17:07.433096 01100000 ################################################################
10178 12:17:07.433247
10179 12:17:08.005667 01180000 ################################################################
10180 12:17:08.005817
10181 12:17:08.585545 01200000 ################################################################
10182 12:17:08.585680
10183 12:17:09.162074 01280000 ################################################################
10184 12:17:09.162226
10185 12:17:09.729092 01300000 ################################################################
10186 12:17:09.729243
10187 12:17:10.302141 01380000 ################################################################
10188 12:17:10.302283
10189 12:17:10.885943 01400000 ################################################################
10190 12:17:10.886092
10191 12:17:11.474955 01480000 ################################################################
10192 12:17:11.475102
10193 12:17:12.052978 01500000 ################################################################
10194 12:17:12.053131
10195 12:17:12.600230 01580000 ################################################################
10196 12:17:12.600380
10197 12:17:13.136540 01600000 ################################################################
10198 12:17:13.136686
10199 12:17:13.659237 01680000 ################################################################
10200 12:17:13.659408
10201 12:17:14.269033 01700000 ################################################################
10202 12:17:14.269493
10203 12:17:14.892747 01780000 ################################################################
10204 12:17:14.892926
10205 12:17:15.513825 01800000 ################################################################
10206 12:17:15.513973
10207 12:17:16.146807 01880000 ################################################################
10208 12:17:16.146962
10209 12:17:16.773629 01900000 ################################################################
10210 12:17:16.773778
10211 12:17:17.404706 01980000 ################################################################
10212 12:17:17.404865
10213 12:17:18.032028 01a00000 ################################################################
10214 12:17:18.032178
10215 12:17:18.658242 01a80000 ################################################################
10216 12:17:18.658480
10217 12:17:19.286972 01b00000 ################################################################
10218 12:17:19.287146
10219 12:17:19.878996 01b80000 ################################################################
10220 12:17:19.879202
10221 12:17:20.455275 01c00000 ################################################################
10222 12:17:20.455450
10223 12:17:20.982224 01c80000 ################################################################
10224 12:17:20.982415
10225 12:17:21.459022 01d00000 ####################################################### done.
10226 12:17:21.459188
10227 12:17:21.461404 The bootfile was 30853282 bytes long.
10228 12:17:21.461487
10229 12:17:21.464789 Sending tftp read request... done.
10230 12:17:21.464872
10231 12:17:21.468156 Waiting for the transfer...
10232 12:17:21.468262
10233 12:17:21.471133 00000000 # done.
10234 12:17:21.471217
10235 12:17:21.477817 Command line loaded dynamically from TFTP file: 12669531/tftp-deploy-vtw011t9/kernel/cmdline
10236 12:17:21.477902
10237 12:17:21.500916 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12669531/extract-nfsrootfs-kiz8_ci8,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10238 12:17:21.501004
10239 12:17:21.501070 Loading FIT.
10240 12:17:21.501131
10241 12:17:21.504737 Image ramdisk-1 has 18756686 bytes.
10242 12:17:21.504819
10243 12:17:21.507634 Image fdt-1 has 47278 bytes.
10244 12:17:21.507716
10245 12:17:21.510670 Image kernel-1 has 12047284 bytes.
10246 12:17:21.510752
10247 12:17:21.517586 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10248 12:17:21.517669
10249 12:17:21.537283 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10250 12:17:21.537369
10251 12:17:21.540787 Choosing best match conf-1 for compat google,spherion-rev2.
10252 12:17:21.545947
10253 12:17:21.551229 Connected to device vid:did:rid of 1ae0:0028:00
10254 12:17:21.557695
10255 12:17:21.560871 tpm_get_response: command 0x17b, return code 0x0
10256 12:17:21.560952
10257 12:17:21.563923 ec_init: CrosEC protocol v3 supported (256, 248)
10258 12:17:21.567919
10259 12:17:21.571721 tpm_cleanup: add release locality here.
10260 12:17:21.571802
10261 12:17:21.571881 Shutting down all USB controllers.
10262 12:17:21.574909
10263 12:17:21.574989 Removing current net device
10264 12:17:21.575052
10265 12:17:21.581694 Exiting depthcharge with code 4 at timestamp: 71947314
10266 12:17:21.581775
10267 12:17:21.584590 LZMA decompressing kernel-1 to 0x821a6718
10268 12:17:21.584671
10269 12:17:21.588728 LZMA decompressing kernel-1 to 0x40000000
10270 12:17:23.088156
10271 12:17:23.088303 jumping to kernel
10272 12:17:23.088754 end: 2.2.4 bootloader-commands (duration 00:00:41) [common]
10273 12:17:23.088850 start: 2.2.5 auto-login-action (timeout 00:03:41) [common]
10274 12:17:23.088925 Setting prompt string to ['Linux version [0-9]']
10275 12:17:23.088990 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10276 12:17:23.089056 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10277 12:17:23.171079
10278 12:17:23.173966 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10279 12:17:23.177715 start: 2.2.5.1 login-action (timeout 00:03:41) [common]
10280 12:17:23.177805 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10281 12:17:23.177874 Setting prompt string to []
10282 12:17:23.177948 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10283 12:17:23.178019 Using line separator: #'\n'#
10284 12:17:23.178077 No login prompt set.
10285 12:17:23.178136 Parsing kernel messages
10286 12:17:23.178190 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10287 12:17:23.178287 [login-action] Waiting for messages, (timeout 00:03:41)
10288 12:17:23.197203 [ 0.000000] Linux version 6.1.72-cip13 (KernelCI@build-j93261-arm64-gcc-10-defconfig-arm64-chromebook-cwjwh) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024
10289 12:17:23.200489 [ 0.000000] random: crng init done
10290 12:17:23.206772 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10291 12:17:23.210254 [ 0.000000] efi: UEFI not found.
10292 12:17:23.217143 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10293 12:17:23.227080 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10294 12:17:23.236870 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10295 12:17:23.243821 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10296 12:17:23.249919 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10297 12:17:23.256230 [ 0.000000] printk: bootconsole [mtk8250] enabled
10298 12:17:23.263705 [ 0.000000] NUMA: No NUMA configuration found
10299 12:17:23.269889 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10300 12:17:23.275997 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10301 12:17:23.276076 [ 0.000000] Zone ranges:
10302 12:17:23.282459 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10303 12:17:23.286238 [ 0.000000] DMA32 empty
10304 12:17:23.292691 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10305 12:17:23.295763 [ 0.000000] Movable zone start for each node
10306 12:17:23.299186 [ 0.000000] Early memory node ranges
10307 12:17:23.306036 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10308 12:17:23.312511 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10309 12:17:23.319147 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10310 12:17:23.325393 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10311 12:17:23.332017 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10312 12:17:23.338513 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10313 12:17:23.395080 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10314 12:17:23.401891 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10315 12:17:23.408095 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10316 12:17:23.412186 [ 0.000000] psci: probing for conduit method from DT.
10317 12:17:23.418499 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10318 12:17:23.421429 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10319 12:17:23.428057 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10320 12:17:23.431588 [ 0.000000] psci: SMC Calling Convention v1.2
10321 12:17:23.438221 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10322 12:17:23.441714 [ 0.000000] Detected VIPT I-cache on CPU0
10323 12:17:23.447946 [ 0.000000] CPU features: detected: GIC system register CPU interface
10324 12:17:23.454423 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10325 12:17:23.460828 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10326 12:17:23.467296 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10327 12:17:23.477599 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10328 12:17:23.484068 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10329 12:17:23.487334 [ 0.000000] alternatives: applying boot alternatives
10330 12:17:23.493941 [ 0.000000] Fallback order for Node 0: 0
10331 12:17:23.500408 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10332 12:17:23.503811 [ 0.000000] Policy zone: Normal
10333 12:17:23.526829 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12669531/extract-nfsrootfs-kiz8_ci8,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10334 12:17:23.536557 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10335 12:17:23.548006 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10336 12:17:23.558034 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10337 12:17:23.564697 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10338 12:17:23.567366 <6>[ 0.000000] software IO TLB: area num 8.
10339 12:17:23.624096 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10340 12:17:23.773997 <6>[ 0.000000] Memory: 7948936K/8385536K available (17984K kernel code, 4116K rwdata, 19604K rodata, 8448K init, 615K bss, 403832K reserved, 32768K cma-reserved)
10341 12:17:23.780272 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10342 12:17:23.786845 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10343 12:17:23.789959 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10344 12:17:23.796876 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10345 12:17:23.803914 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10346 12:17:23.806914 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10347 12:17:23.817266 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10348 12:17:23.822848 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10349 12:17:23.829721 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10350 12:17:23.836058 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10351 12:17:23.839411 <6>[ 0.000000] GICv3: 608 SPIs implemented
10352 12:17:23.843040 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10353 12:17:23.849229 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10354 12:17:23.852637 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10355 12:17:23.859401 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10356 12:17:23.872368 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10357 12:17:23.885458 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10358 12:17:23.892148 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10359 12:17:23.901094 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10360 12:17:23.913234 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10361 12:17:23.919783 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10362 12:17:23.926708 <6>[ 0.009235] Console: colour dummy device 80x25
10363 12:17:23.936770 <6>[ 0.013964] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10364 12:17:23.943315 <6>[ 0.024406] pid_max: default: 32768 minimum: 301
10365 12:17:23.946586 <6>[ 0.029271] LSM: Security Framework initializing
10366 12:17:23.953020 <6>[ 0.034239] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10367 12:17:23.963234 <6>[ 0.042101] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10368 12:17:23.973841 <6>[ 0.051512] cblist_init_generic: Setting adjustable number of callback queues.
10369 12:17:23.976122 <6>[ 0.058955] cblist_init_generic: Setting shift to 3 and lim to 1.
10370 12:17:23.986326 <6>[ 0.065294] cblist_init_generic: Setting adjustable number of callback queues.
10371 12:17:23.992440 <6>[ 0.072721] cblist_init_generic: Setting shift to 3 and lim to 1.
10372 12:17:23.996180 <6>[ 0.079122] rcu: Hierarchical SRCU implementation.
10373 12:17:24.002515 <6>[ 0.084136] rcu: Max phase no-delay instances is 1000.
10374 12:17:24.009115 <6>[ 0.091159] EFI services will not be available.
10375 12:17:24.012164 <6>[ 0.096114] smp: Bringing up secondary CPUs ...
10376 12:17:24.020998 <6>[ 0.101161] Detected VIPT I-cache on CPU1
10377 12:17:24.027815 <6>[ 0.101230] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10378 12:17:24.034484 <6>[ 0.101261] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10379 12:17:24.037433 <6>[ 0.101602] Detected VIPT I-cache on CPU2
10380 12:17:24.047400 <6>[ 0.101654] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10381 12:17:24.054029 <6>[ 0.101672] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10382 12:17:24.056984 <6>[ 0.101929] Detected VIPT I-cache on CPU3
10383 12:17:24.064222 <6>[ 0.101974] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10384 12:17:24.070303 <6>[ 0.101988] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10385 12:17:24.077027 <6>[ 0.102292] CPU features: detected: Spectre-v4
10386 12:17:24.080658 <6>[ 0.102299] CPU features: detected: Spectre-BHB
10387 12:17:24.083834 <6>[ 0.102303] Detected PIPT I-cache on CPU4
10388 12:17:24.089893 <6>[ 0.102360] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10389 12:17:24.099913 <6>[ 0.102377] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10390 12:17:24.103324 <6>[ 0.102667] Detected PIPT I-cache on CPU5
10391 12:17:24.109624 <6>[ 0.102729] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10392 12:17:24.116814 <6>[ 0.102747] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10393 12:17:24.119595 <6>[ 0.103029] Detected PIPT I-cache on CPU6
10394 12:17:24.129947 <6>[ 0.103094] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10395 12:17:24.136077 <6>[ 0.103110] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10396 12:17:24.139686 <6>[ 0.103409] Detected PIPT I-cache on CPU7
10397 12:17:24.147038 <6>[ 0.103472] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10398 12:17:24.152572 <6>[ 0.103490] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10399 12:17:24.156011 <6>[ 0.103537] smp: Brought up 1 node, 8 CPUs
10400 12:17:24.162780 <6>[ 0.244902] SMP: Total of 8 processors activated.
10401 12:17:24.168982 <6>[ 0.249823] CPU features: detected: 32-bit EL0 Support
10402 12:17:24.175703 <6>[ 0.255219] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10403 12:17:24.182339 <6>[ 0.264019] CPU features: detected: Common not Private translations
10404 12:17:24.189148 <6>[ 0.270495] CPU features: detected: CRC32 instructions
10405 12:17:24.195583 <6>[ 0.275847] CPU features: detected: RCpc load-acquire (LDAPR)
10406 12:17:24.198896 <6>[ 0.281806] CPU features: detected: LSE atomic instructions
10407 12:17:24.205611 <6>[ 0.287588] CPU features: detected: Privileged Access Never
10408 12:17:24.212160 <6>[ 0.293367] CPU features: detected: RAS Extension Support
10409 12:17:24.218448 <6>[ 0.298976] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10410 12:17:24.222148 <6>[ 0.306196] CPU: All CPU(s) started at EL2
10411 12:17:24.228142 <6>[ 0.310539] alternatives: applying system-wide alternatives
10412 12:17:24.239126 <6>[ 0.321253] devtmpfs: initialized
10413 12:17:24.251188 <6>[ 0.330127] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10414 12:17:24.260851 <6>[ 0.340088] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10415 12:17:24.267365 <6>[ 0.347917] pinctrl core: initialized pinctrl subsystem
10416 12:17:24.271050 <6>[ 0.354549] DMI not present or invalid.
10417 12:17:24.278388 <6>[ 0.358956] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10418 12:17:24.283904 <6>[ 0.365834] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10419 12:17:24.294174 <6>[ 0.373418] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10420 12:17:24.300609 <6>[ 0.381636] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10421 12:17:24.307205 <6>[ 0.389880] audit: initializing netlink subsys (disabled)
10422 12:17:24.317186 <5>[ 0.395572] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10423 12:17:24.323767 <6>[ 0.396264] thermal_sys: Registered thermal governor 'step_wise'
10424 12:17:24.330328 <6>[ 0.403539] thermal_sys: Registered thermal governor 'power_allocator'
10425 12:17:24.333541 <6>[ 0.409795] cpuidle: using governor menu
10426 12:17:24.337061 <6>[ 0.420759] NET: Registered PF_QIPCRTR protocol family
10427 12:17:24.347092 <6>[ 0.426244] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10428 12:17:24.350211 <6>[ 0.433347] ASID allocator initialised with 32768 entries
10429 12:17:24.357283 <6>[ 0.439906] Serial: AMBA PL011 UART driver
10430 12:17:24.366342 <4>[ 0.448630] Trying to register duplicate clock ID: 134
10431 12:17:24.419721 <6>[ 0.505731] KASLR enabled
10432 12:17:24.434542 <6>[ 0.513476] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10433 12:17:24.441154 <6>[ 0.520492] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10434 12:17:24.447918 <6>[ 0.526981] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10435 12:17:24.453998 <6>[ 0.533988] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10436 12:17:24.460295 <6>[ 0.540476] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10437 12:17:24.467792 <6>[ 0.547479] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10438 12:17:24.473918 <6>[ 0.553965] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10439 12:17:24.479861 <6>[ 0.560967] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10440 12:17:24.483899 <6>[ 0.568481] ACPI: Interpreter disabled.
10441 12:17:24.492578 <6>[ 0.574890] iommu: Default domain type: Translated
10442 12:17:24.498871 <6>[ 0.580000] iommu: DMA domain TLB invalidation policy: strict mode
10443 12:17:24.502608 <5>[ 0.586659] SCSI subsystem initialized
10444 12:17:24.508789 <6>[ 0.590826] usbcore: registered new interface driver usbfs
10445 12:17:24.515823 <6>[ 0.596558] usbcore: registered new interface driver hub
10446 12:17:24.518682 <6>[ 0.602108] usbcore: registered new device driver usb
10447 12:17:24.525570 <6>[ 0.608209] pps_core: LinuxPPS API ver. 1 registered
10448 12:17:24.535529 <6>[ 0.613403] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10449 12:17:24.538649 <6>[ 0.622750] PTP clock support registered
10450 12:17:24.541934 <6>[ 0.626994] EDAC MC: Ver: 3.0.0
10451 12:17:24.550053 <6>[ 0.632156] FPGA manager framework
10452 12:17:24.556027 <6>[ 0.635837] Advanced Linux Sound Architecture Driver Initialized.
10453 12:17:24.559545 <6>[ 0.642606] vgaarb: loaded
10454 12:17:24.565841 <6>[ 0.645755] clocksource: Switched to clocksource arch_sys_counter
10455 12:17:24.569333 <5>[ 0.652195] VFS: Disk quotas dquot_6.6.0
10456 12:17:24.576325 <6>[ 0.656381] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10457 12:17:24.579369 <6>[ 0.663573] pnp: PnP ACPI: disabled
10458 12:17:24.587759 <6>[ 0.670301] NET: Registered PF_INET protocol family
10459 12:17:24.597445 <6>[ 0.675894] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10460 12:17:24.608867 <6>[ 0.688216] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10461 12:17:24.618665 <6>[ 0.697029] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10462 12:17:24.625577 <6>[ 0.704998] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10463 12:17:24.635086 <6>[ 0.713699] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10464 12:17:24.642249 <6>[ 0.723459] TCP: Hash tables configured (established 65536 bind 65536)
10465 12:17:24.648200 <6>[ 0.730323] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10466 12:17:24.658727 <6>[ 0.737523] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10467 12:17:24.664893 <6>[ 0.745225] NET: Registered PF_UNIX/PF_LOCAL protocol family
10468 12:17:24.671272 <6>[ 0.751373] RPC: Registered named UNIX socket transport module.
10469 12:17:24.674637 <6>[ 0.757524] RPC: Registered udp transport module.
10470 12:17:24.681228 <6>[ 0.762456] RPC: Registered tcp transport module.
10471 12:17:24.687923 <6>[ 0.767388] RPC: Registered tcp NFSv4.1 backchannel transport module.
10472 12:17:24.691067 <6>[ 0.774053] PCI: CLS 0 bytes, default 64
10473 12:17:24.694338 <6>[ 0.778385] Unpacking initramfs...
10474 12:17:24.718653 <6>[ 0.797876] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10475 12:17:24.728652 <6>[ 0.806559] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10476 12:17:24.731547 <6>[ 0.815410] kvm [1]: IPA Size Limit: 40 bits
10477 12:17:24.738092 <6>[ 0.819941] kvm [1]: GICv3: no GICV resource entry
10478 12:17:24.741444 <6>[ 0.824964] kvm [1]: disabling GICv2 emulation
10479 12:17:24.748546 <6>[ 0.829653] kvm [1]: GIC system register CPU interface enabled
10480 12:17:24.751393 <6>[ 0.835827] kvm [1]: vgic interrupt IRQ18
10481 12:17:24.757897 <6>[ 0.840181] kvm [1]: VHE mode initialized successfully
10482 12:17:24.765056 <5>[ 0.846704] Initialise system trusted keyrings
10483 12:17:24.771951 <6>[ 0.851569] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10484 12:17:24.779165 <6>[ 0.861570] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10485 12:17:24.785583 <5>[ 0.867972] NFS: Registering the id_resolver key type
10486 12:17:24.788655 <5>[ 0.873282] Key type id_resolver registered
10487 12:17:24.795354 <5>[ 0.877699] Key type id_legacy registered
10488 12:17:24.801846 <6>[ 0.881978] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10489 12:17:24.808435 <6>[ 0.888898] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10490 12:17:24.815719 <6>[ 0.896637] 9p: Installing v9fs 9p2000 file system support
10491 12:17:24.851651 <5>[ 0.934143] Key type asymmetric registered
10492 12:17:24.855059 <5>[ 0.938478] Asymmetric key parser 'x509' registered
10493 12:17:24.864807 <6>[ 0.943667] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10494 12:17:24.868029 <6>[ 0.951286] io scheduler mq-deadline registered
10495 12:17:24.871284 <6>[ 0.956054] io scheduler kyber registered
10496 12:17:24.890319 <6>[ 0.973100] EINJ: ACPI disabled.
10497 12:17:24.923051 <4>[ 0.998604] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10498 12:17:24.932358 <4>[ 1.009229] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10499 12:17:24.947240 <6>[ 1.030087] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10500 12:17:24.955742 <6>[ 1.038147] printk: console [ttyS0] disabled
10501 12:17:24.983366 <6>[ 1.062808] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10502 12:17:24.989817 <6>[ 1.072296] printk: console [ttyS0] enabled
10503 12:17:24.993426 <6>[ 1.072296] printk: console [ttyS0] enabled
10504 12:17:24.999993 <6>[ 1.081194] printk: bootconsole [mtk8250] disabled
10505 12:17:25.003390 <6>[ 1.081194] printk: bootconsole [mtk8250] disabled
10506 12:17:25.009908 <6>[ 1.092480] SuperH (H)SCI(F) driver initialized
10507 12:17:25.013738 <6>[ 1.097767] msm_serial: driver initialized
10508 12:17:25.027253 <6>[ 1.106703] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10509 12:17:25.037232 <6>[ 1.115250] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10510 12:17:25.044069 <6>[ 1.123792] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10511 12:17:25.053862 <6>[ 1.132420] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10512 12:17:25.060476 <6>[ 1.141129] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10513 12:17:25.070588 <6>[ 1.149851] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10514 12:17:25.080516 <6>[ 1.158392] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10515 12:17:25.086851 <6>[ 1.167196] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10516 12:17:25.096905 <6>[ 1.175740] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10517 12:17:25.108673 <6>[ 1.191324] loop: module loaded
10518 12:17:25.115751 <6>[ 1.197314] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10519 12:17:25.137674 <4>[ 1.220315] mtk-pmic-keys: Failed to locate of_node [id: -1]
10520 12:17:25.144644 <6>[ 1.227438] megasas: 07.719.03.00-rc1
10521 12:17:25.154370 <6>[ 1.237070] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10522 12:17:25.162419 <6>[ 1.245128] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10523 12:17:25.180047 <6>[ 1.261856] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10524 12:17:25.235922 <6>[ 1.311929] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10525 12:17:25.488198 <6>[ 1.570644] Freeing initrd memory: 18316K
10526 12:17:25.499511 <6>[ 1.582146] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10527 12:17:25.511135 <6>[ 1.593069] tun: Universal TUN/TAP device driver, 1.6
10528 12:17:25.513713 <6>[ 1.599125] thunder_xcv, ver 1.0
10529 12:17:25.516817 <6>[ 1.602631] thunder_bgx, ver 1.0
10530 12:17:25.520145 <6>[ 1.606126] nicpf, ver 1.0
10531 12:17:25.530898 <6>[ 1.610148] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10532 12:17:25.534424 <6>[ 1.617623] hns3: Copyright (c) 2017 Huawei Corporation.
10533 12:17:25.540657 <6>[ 1.623211] hclge is initializing
10534 12:17:25.544138 <6>[ 1.626791] e1000: Intel(R) PRO/1000 Network Driver
10535 12:17:25.550514 <6>[ 1.631919] e1000: Copyright (c) 1999-2006 Intel Corporation.
10536 12:17:25.554107 <6>[ 1.637931] e1000e: Intel(R) PRO/1000 Network Driver
10537 12:17:25.560740 <6>[ 1.643147] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10538 12:17:25.567139 <6>[ 1.649331] igb: Intel(R) Gigabit Ethernet Network Driver
10539 12:17:25.573754 <6>[ 1.654981] igb: Copyright (c) 2007-2014 Intel Corporation.
10540 12:17:25.580523 <6>[ 1.660816] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10541 12:17:25.587237 <6>[ 1.667334] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10542 12:17:25.590734 <6>[ 1.673813] sky2: driver version 1.30
10543 12:17:25.597080 <6>[ 1.678804] VFIO - User Level meta-driver version: 0.3
10544 12:17:25.604195 <6>[ 1.687038] usbcore: registered new interface driver usb-storage
10545 12:17:25.611286 <6>[ 1.693484] usbcore: registered new device driver onboard-usb-hub
10546 12:17:25.620010 <6>[ 1.702640] mt6397-rtc mt6359-rtc: registered as rtc0
10547 12:17:25.630044 <6>[ 1.708115] mt6397-rtc mt6359-rtc: setting system clock to 2024-01-31T12:17:25 UTC (1706703445)
10548 12:17:25.633250 <6>[ 1.717703] i2c_dev: i2c /dev entries driver
10549 12:17:25.650170 <6>[ 1.729335] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10550 12:17:25.670093 <6>[ 1.752318] cpu cpu0: EM: created perf domain
10551 12:17:25.673574 <6>[ 1.757238] cpu cpu4: EM: created perf domain
10552 12:17:25.679868 <6>[ 1.762808] sdhci: Secure Digital Host Controller Interface driver
10553 12:17:25.686690 <6>[ 1.769241] sdhci: Copyright(c) Pierre Ossman
10554 12:17:25.693862 <6>[ 1.774195] Synopsys Designware Multimedia Card Interface Driver
10555 12:17:25.699769 <6>[ 1.780817] sdhci-pltfm: SDHCI platform and OF driver helper
10556 12:17:25.703077 <6>[ 1.780934] mmc0: CQHCI version 5.10
10557 12:17:25.709974 <6>[ 1.790797] ledtrig-cpu: registered to indicate activity on CPUs
10558 12:17:25.716658 <6>[ 1.797731] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10559 12:17:25.723139 <6>[ 1.804790] usbcore: registered new interface driver usbhid
10560 12:17:25.726833 <6>[ 1.810612] usbhid: USB HID core driver
10561 12:17:25.733919 <6>[ 1.814816] spi_master spi0: will run message pump with realtime priority
10562 12:17:25.777478 <6>[ 1.853775] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10563 12:17:25.796979 <6>[ 1.869659] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10564 12:17:25.801177 <6>[ 1.883239] mmc0: Command Queue Engine enabled
10565 12:17:25.807162 <6>[ 1.887997] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10566 12:17:25.813768 <6>[ 1.895152] cros-ec-spi spi0.0: Chrome EC device registered
10567 12:17:25.816930 <6>[ 1.895415] mmcblk0: mmc0:0001 DA4128 116 GiB
10568 12:17:25.828463 <6>[ 1.911216] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10569 12:17:25.836587 <6>[ 1.918821] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10570 12:17:25.842798 <6>[ 1.925048] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10571 12:17:25.849858 <6>[ 1.931284] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10572 12:17:25.859014 <6>[ 1.937948] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10573 12:17:25.866027 <6>[ 1.948686] NET: Registered PF_PACKET protocol family
10574 12:17:25.869438 <6>[ 1.954116] 9pnet: Installing 9P2000 support
10575 12:17:25.875867 <5>[ 1.958711] Key type dns_resolver registered
10576 12:17:25.879859 <6>[ 1.963838] registered taskstats version 1
10577 12:17:25.885830 <5>[ 1.968245] Loading compiled-in X.509 certificates
10578 12:17:25.915812 <4>[ 1.991642] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10579 12:17:25.925763 <4>[ 2.002508] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10580 12:17:25.932610 <3>[ 2.013052] debugfs: File 'uA_load' in directory '/' already present!
10581 12:17:25.939093 <3>[ 2.019780] debugfs: File 'min_uV' in directory '/' already present!
10582 12:17:25.945467 <3>[ 2.026396] debugfs: File 'max_uV' in directory '/' already present!
10583 12:17:25.951817 <3>[ 2.033006] debugfs: File 'constraint_flags' in directory '/' already present!
10584 12:17:25.963969 <3>[ 2.043036] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10585 12:17:25.977227 <6>[ 2.059593] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10586 12:17:25.983675 <6>[ 2.066387] xhci-mtk 11200000.usb: xHCI Host Controller
10587 12:17:25.990292 <6>[ 2.071907] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10588 12:17:26.000616 <6>[ 2.079870] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10589 12:17:26.007213 <6>[ 2.089337] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10590 12:17:26.013590 <6>[ 2.095433] xhci-mtk 11200000.usb: xHCI Host Controller
10591 12:17:26.020921 <6>[ 2.100927] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10592 12:17:26.027350 <6>[ 2.108684] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10593 12:17:26.033808 <6>[ 2.116704] hub 1-0:1.0: USB hub found
10594 12:17:26.037762 <6>[ 2.120737] hub 1-0:1.0: 1 port detected
10595 12:17:26.048039 <6>[ 2.125056] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10596 12:17:26.050559 <6>[ 2.133922] hub 2-0:1.0: USB hub found
10597 12:17:26.053664 <6>[ 2.137949] hub 2-0:1.0: 1 port detected
10598 12:17:26.062745 <6>[ 2.145571] mtk-msdc 11f70000.mmc: Got CD GPIO
10599 12:17:26.075207 <6>[ 2.154547] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10600 12:17:26.081976 <6>[ 2.162592] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10601 12:17:26.091923 <4>[ 2.170515] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10602 12:17:26.101731 <6>[ 2.180090] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10603 12:17:26.108055 <6>[ 2.188174] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10604 12:17:26.117932 <6>[ 2.196204] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10605 12:17:26.124830 <6>[ 2.204122] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10606 12:17:26.131168 <6>[ 2.211939] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10607 12:17:26.141256 <6>[ 2.219756] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10608 12:17:26.151787 <6>[ 2.230226] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10609 12:17:26.158102 <6>[ 2.238590] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10610 12:17:26.167896 <6>[ 2.246929] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10611 12:17:26.174718 <6>[ 2.255269] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10612 12:17:26.185499 <6>[ 2.263607] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10613 12:17:26.191085 <6>[ 2.271945] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10614 12:17:26.200929 <6>[ 2.280284] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10615 12:17:26.210985 <6>[ 2.288623] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10616 12:17:26.217277 <6>[ 2.296967] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10617 12:17:26.227610 <6>[ 2.305306] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10618 12:17:26.234636 <6>[ 2.313645] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10619 12:17:26.243673 <6>[ 2.321983] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10620 12:17:26.250187 <6>[ 2.330322] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10621 12:17:26.260766 <6>[ 2.338660] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10622 12:17:26.267150 <6>[ 2.347003] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10623 12:17:26.273365 <6>[ 2.355723] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10624 12:17:26.279975 <6>[ 2.362874] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10625 12:17:26.287074 <6>[ 2.369637] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10626 12:17:26.297251 <6>[ 2.376395] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10627 12:17:26.304066 <6>[ 2.383336] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10628 12:17:26.310191 <6>[ 2.390182] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10629 12:17:26.319798 <6>[ 2.399315] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10630 12:17:26.329927 <6>[ 2.408433] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10631 12:17:26.340203 <6>[ 2.417728] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10632 12:17:26.349640 <6>[ 2.427194] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10633 12:17:26.359566 <6>[ 2.436660] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10634 12:17:26.366252 <6>[ 2.445780] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10635 12:17:26.376221 <6>[ 2.455245] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10636 12:17:26.385808 <6>[ 2.464363] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10637 12:17:26.395935 <6>[ 2.473656] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10638 12:17:26.405780 <6>[ 2.483816] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10639 12:17:26.416283 <6>[ 2.495836] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10640 12:17:26.422711 <6>[ 2.505676] Trying to probe devices needed for running init ...
10641 12:17:26.466022 <6>[ 2.546029] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10642 12:17:26.621519 <6>[ 2.704179] hub 1-1:1.0: USB hub found
10643 12:17:26.624529 <6>[ 2.708695] hub 1-1:1.0: 4 ports detected
10644 12:17:26.634348 <6>[ 2.716918] hub 1-1:1.0: USB hub found
10645 12:17:26.638041 <6>[ 2.721344] hub 1-1:1.0: 4 ports detected
10646 12:17:26.746868 <6>[ 2.826369] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10647 12:17:26.772936 <6>[ 2.855802] hub 2-1:1.0: USB hub found
10648 12:17:26.776229 <6>[ 2.860298] hub 2-1:1.0: 3 ports detected
10649 12:17:26.785435 <6>[ 2.868441] hub 2-1:1.0: USB hub found
10650 12:17:26.788798 <6>[ 2.872885] hub 2-1:1.0: 3 ports detected
10651 12:17:26.962607 <6>[ 3.042054] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10652 12:17:27.094896 <6>[ 3.177664] hub 1-1.4:1.0: USB hub found
10653 12:17:27.098206 <6>[ 3.182305] hub 1-1.4:1.0: 2 ports detected
10654 12:17:27.107665 <6>[ 3.190418] hub 1-1.4:1.0: USB hub found
10655 12:17:27.110676 <6>[ 3.195017] hub 1-1.4:1.0: 2 ports detected
10656 12:17:27.174407 <6>[ 3.254170] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10657 12:17:27.406756 <6>[ 3.486057] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10658 12:17:27.598397 <6>[ 3.678073] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10659 12:17:38.711448 <6>[ 14.799068] ALSA device list:
10660 12:17:38.718390 <6>[ 14.802360] No soundcards found.
10661 12:17:38.725993 <6>[ 14.810344] Freeing unused kernel memory: 8448K
10662 12:17:38.729611 <6>[ 14.815367] Run /init as init process
10663 12:17:38.740718 Loading, please wait...
10664 12:17:38.770675 Starting systemd-udevd version 252.19-1~deb12u1
10665 12:17:39.054325 <6>[ 15.135260] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10666 12:17:39.072616 <6>[ 15.156702] remoteproc remoteproc0: scp is available
10667 12:17:39.079370 <6>[ 15.162019] remoteproc remoteproc0: powering up scp
10668 12:17:39.085790 <6>[ 15.167309] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10669 12:17:39.092861 <6>[ 15.175768] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10670 12:17:39.098967 <6>[ 15.176524] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10671 12:17:39.109104 <3>[ 15.182344] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10672 12:17:39.116100 <6>[ 15.189192] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10673 12:17:39.125400 <6>[ 15.205850] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10674 12:17:39.132137 <3>[ 15.206049] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10675 12:17:39.141948 <4>[ 15.211257] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10676 12:17:39.148867 <4>[ 15.211381] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10677 12:17:39.155685 <6>[ 15.211390] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10678 12:17:39.162454 <6>[ 15.218478] usbcore: registered new device driver r8152-cfgselector
10679 12:17:39.171767 <3>[ 15.222676] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 12:17:39.178252 <3>[ 15.225766] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10681 12:17:39.181684 <6>[ 15.253893] mc: Linux media interface: v0.10
10682 12:17:39.191815 <3>[ 15.259777] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 12:17:39.198226 <3>[ 15.280442] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10684 12:17:39.208675 <3>[ 15.288671] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 12:17:39.215009 <3>[ 15.297329] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 12:17:39.226492 <3>[ 15.306976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 12:17:39.236072 <4>[ 15.314632] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10688 12:17:39.239253 <4>[ 15.314632] Fallback method does not support PEC.
10689 12:17:39.249260 <3>[ 15.315242] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10690 12:17:39.255840 <6>[ 15.320509] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10691 12:17:39.262837 <6>[ 15.321918] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10692 12:17:39.273244 <6>[ 15.321962] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10693 12:17:39.280240 <6>[ 15.321969] remoteproc remoteproc0: remote processor scp is now up
10694 12:17:39.290618 <6>[ 15.338049] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10695 12:17:39.299558 <6>[ 15.338367] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10696 12:17:39.306084 <6>[ 15.338635] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10697 12:17:39.313025 <6>[ 15.342142] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10698 12:17:39.319231 <6>[ 15.342147] pci_bus 0000:00: root bus resource [bus 00-ff]
10699 12:17:39.325939 <6>[ 15.342150] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10700 12:17:39.335772 <6>[ 15.342153] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10701 12:17:39.342481 <6>[ 15.342179] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10702 12:17:39.349301 <6>[ 15.342192] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10703 12:17:39.355615 <6>[ 15.342255] pci 0000:00:00.0: supports D1 D2
10704 12:17:39.362850 <6>[ 15.342257] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10705 12:17:39.369000 <6>[ 15.343203] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10706 12:17:39.375877 <6>[ 15.343289] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10707 12:17:39.385450 <6>[ 15.343313] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10708 12:17:39.393080 <6>[ 15.343330] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10709 12:17:39.399208 <6>[ 15.343345] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10710 12:17:39.405521 <6>[ 15.343449] pci 0000:01:00.0: supports D1 D2
10711 12:17:39.411928 <6>[ 15.343451] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10712 12:17:39.418413 <3>[ 15.346160] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 12:17:39.425227 <3>[ 15.346174] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 12:17:39.435241 <3>[ 15.346263] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10715 12:17:39.442125 <6>[ 15.348165] videodev: Linux video capture interface: v2.00
10716 12:17:39.448015 <6>[ 15.349813] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10717 12:17:39.454997 <6>[ 15.349840] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10718 12:17:39.464578 <6>[ 15.349844] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10719 12:17:39.471126 <6>[ 15.349852] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10720 12:17:39.478010 <6>[ 15.349864] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10721 12:17:39.487849 <6>[ 15.349877] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10722 12:17:39.491051 <6>[ 15.349889] pci 0000:00:00.0: PCI bridge to [bus 01]
10723 12:17:39.501849 <6>[ 15.349895] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10724 12:17:39.508583 <6>[ 15.350027] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10725 12:17:39.511675 <6>[ 15.350491] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10726 12:17:39.518060 <6>[ 15.350790] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10727 12:17:39.528106 <6>[ 15.363480] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10728 12:17:39.534613 <3>[ 15.365408] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10729 12:17:39.544554 <6>[ 15.366375] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10730 12:17:39.551776 <3>[ 15.369092] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10731 12:17:39.557868 <6>[ 15.379210] Bluetooth: Core ver 2.22
10732 12:17:39.564211 <5>[ 15.381053] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10733 12:17:39.570842 <3>[ 15.387423] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 12:17:39.580726 <3>[ 15.387434] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 12:17:39.587839 <5>[ 15.393908] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10736 12:17:39.594397 <5>[ 15.394146] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10737 12:17:39.604485 <4>[ 15.394209] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10738 12:17:39.610482 <6>[ 15.394214] cfg80211: failed to load regulatory.db
10739 12:17:39.614149 <6>[ 15.396528] NET: Registered PF_BLUETOOTH protocol family
10740 12:17:39.624340 <4>[ 15.401013] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10741 12:17:39.630772 <4>[ 15.401022] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10742 12:17:39.640470 <3>[ 15.403332] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 12:17:39.647248 <6>[ 15.409085] Bluetooth: HCI device and connection manager initialized
10744 12:17:39.653603 <3>[ 15.416255] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 12:17:39.663254 <6>[ 15.418285] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10746 12:17:39.673230 <6>[ 15.419316] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10747 12:17:39.679834 <6>[ 15.419420] usbcore: registered new interface driver uvcvideo
10748 12:17:39.686636 <6>[ 15.426144] Bluetooth: HCI socket layer initialized
10749 12:17:39.689717 <6>[ 15.459664] r8152 2-1.3:1.0 eth0: v1.12.13
10750 12:17:39.696555 <6>[ 15.460733] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10751 12:17:39.702885 <6>[ 15.466244] Bluetooth: L2CAP socket layer initialized
10752 12:17:39.706461 <6>[ 15.473500] usbcore: registered new interface driver r8152
10753 12:17:39.712765 <6>[ 15.480797] Bluetooth: SCO socket layer initialized
10754 12:17:39.719276 <6>[ 15.493834] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10755 12:17:39.726249 <6>[ 15.529892] usbcore: registered new interface driver cdc_ether
10756 12:17:39.732850 <6>[ 15.536644] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10757 12:17:39.739546 <6>[ 15.536996] usbcore: registered new interface driver btusb
10758 12:17:39.749212 <4>[ 15.537832] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10759 12:17:39.755848 <3>[ 15.537853] Bluetooth: hci0: Failed to load firmware file (-2)
10760 12:17:39.758827 <3>[ 15.537858] Bluetooth: hci0: Failed to set up firmware (-2)
10761 12:17:39.772202 <4>[ 15.537862] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10762 12:17:39.775715 <6>[ 15.560754] usbcore: registered new interface driver r8153_ecm
10763 12:17:39.781940 <6>[ 15.585881] mt7921e 0000:01:00.0: ASIC revision: 79610010
10764 12:17:39.791835 <3>[ 15.596639] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10765 12:17:39.799916 <6>[ 15.623699] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10766 12:17:39.805488 <6>[ 15.698811] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20231109190918a
10767 12:17:39.808695 <6>[ 15.698811]
10768 12:17:39.838610 Begin: Loading essential drivers ... done.
10769 12:17:39.841977 Begin: Running /scripts/init-premount ... done.
10770 12:17:39.848646 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10771 12:17:39.858337 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10772 12:17:39.861601 Device /sys/class/net/enx002432307c7b found
10773 12:17:39.861686 done.
10774 12:17:39.882105 Begin: Waiting up to 180 secs for any network device to become available ... done.
10775 12:17:39.948872 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10776 12:17:40.077343 <6>[ 16.158633] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20231109190959
10777 12:17:40.914862 <6>[ 16.999420] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10778 12:17:40.941481 <6>[ 17.026003] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10779 12:17:41.123794 IP-Config: no response after 2 secs - giving up
10780 12:17:41.157511 IP-Config: wlp1s0 hardware address d8:f3:bc:78:0c:a1 mtu 1500 DHCP
10781 12:17:41.860577 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10782 12:17:41.863569 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10783 12:17:41.870205 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10784 12:17:41.880811 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10785 12:17:41.886695 host : mt8192-asurada-spherion-r0-cbg-2
10786 12:17:41.893215 domain : lava-rack
10787 12:17:41.896685 rootserver: 192.168.201.1 rootpath:
10788 12:17:41.896766 filename :
10789 12:17:41.978266 done.
10790 12:17:41.986589 Begin: Running /scripts/nfs-bottom ... done.
10791 12:17:42.003222 Begin: Running /scripts/init-bottom ... done.
10792 12:17:43.360956 <6>[ 19.445810] NET: Registered PF_INET6 protocol family
10793 12:17:43.369110 <6>[ 19.453598] Segment Routing with IPv6
10794 12:17:43.372071 <6>[ 19.457571] In-situ OAM (IOAM) with IPv6
10795 12:17:43.552036 <30>[ 19.609952] systemd[1]: systemd 252.19-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10796 12:17:43.558887 <30>[ 19.643048] systemd[1]: Detected architecture arm64.
10797 12:17:43.574656
10798 12:17:43.578000 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10799 12:17:43.578091
10800 12:17:43.602795 <30>[ 19.687697] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10801 12:17:44.750117 <30>[ 20.831371] systemd[1]: Queued start job for default target graphical.target.
10802 12:17:44.779162 <30>[ 20.859304] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10803 12:17:44.785075 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10804 12:17:44.806803 <30>[ 20.887928] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10805 12:17:44.816510 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10806 12:17:44.835011 <30>[ 20.915757] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10807 12:17:44.844928 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10808 12:17:44.863329 <30>[ 20.944245] systemd[1]: Created slice user.slice - User and Session Slice.
10809 12:17:44.869790 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10810 12:17:44.892918 <30>[ 20.970822] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10811 12:17:44.902877 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10812 12:17:44.920382 <30>[ 20.998292] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10813 12:17:44.926810 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10814 12:17:44.955530 <30>[ 21.026693] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10815 12:17:44.965679 <30>[ 21.046710] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10816 12:17:44.972042 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10817 12:17:44.994219 <30>[ 21.074554] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10818 12:17:45.003478 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10819 12:17:45.018073 <30>[ 21.102633] systemd[1]: Reached target paths.target - Path Units.
10820 12:17:45.025273 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10821 12:17:45.046122 <30>[ 21.126539] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10822 12:17:45.051929 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10823 12:17:45.065628 <30>[ 21.150039] systemd[1]: Reached target slices.target - Slice Units.
10824 12:17:45.075486 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10825 12:17:45.090651 <30>[ 21.174551] systemd[1]: Reached target swap.target - Swaps.
10826 12:17:45.097239 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10827 12:17:45.117646 <30>[ 21.198550] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10828 12:17:45.127801 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10829 12:17:45.145810 <30>[ 21.226942] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10830 12:17:45.155577 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10831 12:17:45.177202 <30>[ 21.258537] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10832 12:17:45.186898 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10833 12:17:45.206876 <30>[ 21.287815] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10834 12:17:45.216677 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10835 12:17:45.233854 <30>[ 21.314807] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10836 12:17:45.239813 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10837 12:17:45.259058 <30>[ 21.339864] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10838 12:17:45.268635 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10839 12:17:45.289213 <30>[ 21.370542] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10840 12:17:45.299095 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10841 12:17:45.317666 <30>[ 21.398584] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10842 12:17:45.326910 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10843 12:17:45.376930 <30>[ 21.458458] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10844 12:17:45.383348 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10845 12:17:45.402767 <30>[ 21.484557] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10846 12:17:45.409358 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10847 12:17:45.432331 <30>[ 21.513841] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10848 12:17:45.438722 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10849 12:17:45.463653 <30>[ 21.538765] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10850 12:17:45.479201 <30>[ 21.560661] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10851 12:17:45.489050 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10852 12:17:45.510499 <30>[ 21.592005] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10853 12:17:45.516959 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10854 12:17:45.541984 <30>[ 21.623699] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10855 12:17:45.550005 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10856 12:17:45.574240 <30>[ 21.656123] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10857 12:17:45.587601 Starting [0;1;39mmodprobe@drm.service[0m - Load Kerne<6>[ 21.668990] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10858 12:17:45.590904 l Module drm...
10859 12:17:45.614889 <30>[ 21.696107] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10860 12:17:45.624479 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10861 12:17:45.646347 <30>[ 21.728013] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10862 12:17:45.652968 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10863 12:17:45.677945 <30>[ 21.759812] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10864 12:17:45.684659 Starting [0;1;39mmodpr<6>[ 21.770368] fuse: init (API version 7.37)
10865 12:17:45.687949 obe@loop.ser…e[0m - Load Kernel Module loop...
10866 12:17:45.718155 <30>[ 21.799923] systemd[1]: Starting systemd-journald.service - Journal Service...
10867 12:17:45.725327 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10868 12:17:45.790471 <30>[ 21.871158] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10869 12:17:45.796425 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10870 12:17:45.823997 <30>[ 21.901815] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10871 12:17:45.830813 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10872 12:17:45.858368 <30>[ 21.939106] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10873 12:17:45.874819 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems..<3>[ 21.954625] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10874 12:17:45.875264 .
10875 12:17:45.898371 <30>[ 21.979667] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10876 12:17:45.915603 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices..<3>[ 21.995413] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10877 12:17:45.916034 .
10878 12:17:45.938592 <30>[ 22.019891] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10879 12:17:45.952915 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File S<3>[ 22.033672] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10880 12:17:45.955764 ystem.
10881 12:17:45.974475 <30>[ 22.054500] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10882 12:17:45.984115 [[0;32m OK [0m] Mounted [0;<3>[ 22.064906] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 12:17:45.990371 1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10884 12:17:46.009580 <30>[ 22.090562] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10885 12:17:46.016629 <3>[ 22.098307] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 12:17:46.026997 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10887 12:17:46.047079 <30>[ 22.127448] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10888 12:17:46.056908 <3>[ 22.135830] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 12:17:46.063499 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10890 12:17:46.083788 <30>[ 22.163563] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10891 12:17:46.089814 <30>[ 22.171939] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10892 12:17:46.099853 <3>[ 22.171951] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 12:17:46.109196 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10894 12:17:46.123107 <30>[ 22.206798] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10895 12:17:46.133603 <30>[ 22.214900] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10896 12:17:46.144221 <3>[ 22.215989] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 12:17:46.150523 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10898 12:17:46.170967 <30>[ 22.251780] systemd[1]: modprobe@drm.service: Deactivated successfully.
10899 12:17:46.177903 <3>[ 22.254159] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 12:17:46.184457 <30>[ 22.259927] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10901 12:17:46.194155 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10902 12:17:46.211547 <3>[ 22.292479] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 12:17:46.223133 <30>[ 22.303983] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10904 12:17:46.232911 <30>[ 22.312568] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10905 12:17:46.239723 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10906 12:17:46.263801 <30>[ 22.344426] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10907 12:17:46.269947 <30>[ 22.352646] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10908 12:17:46.280663 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10909 12:17:46.301917 <30>[ 22.383121] systemd[1]: Started systemd-journald.service - Journal Service.
10910 12:17:46.308776 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10911 12:17:46.330833 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10912 12:17:46.356717 <4>[ 22.431473] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10913 12:17:46.367214 <3>[ 22.447142] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10914 12:17:46.373248 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10915 12:17:46.396298 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10916 12:17:46.418599 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10917 12:17:46.438753 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10918 12:17:46.460068 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10919 12:17:46.517994 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10920 12:17:46.543261 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10921 12:17:46.569976 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10922 12:17:46.597606 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10923 12:17:46.634089 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10924 12:17:46.651248 <46>[ 22.733110] systemd-journald[299]: Received client request to flush runtime journal.
10925 12:17:46.698605 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10926 12:17:46.984656 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10927 12:17:47.001527 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10928 12:17:47.022216 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10929 12:17:47.042910 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10930 12:17:48.064410 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10931 12:17:48.086559 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10932 12:17:48.154338 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10933 12:17:48.274283 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10934 12:17:48.297131 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10935 12:17:48.316636 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10936 12:17:48.360955 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
10937 12:17:48.382276 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10938 12:17:48.409610 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10939 12:17:48.449173 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
10940 12:17:48.461822 See 'systemctl status systemd-binfmt.service' for details.
10941 12:17:48.724346 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10942 12:17:48.790507 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10943 12:17:48.832232 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10944 12:17:49.159735 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10945 12:17:49.177573 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10946 12:17:49.235821 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10947 12:17:49.258406 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10948 12:17:49.352702 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10949 12:17:49.377535 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10950 12:17:49.402620 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10951 12:17:49.460592 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10952 12:17:49.478684 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10953 12:17:49.501961 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10954 12:17:49.550076 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10955 12:17:49.570230 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10956 12:17:49.618701 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10957 12:17:49.655561 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10958 12:17:49.673550 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10959 12:17:49.693008 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10960 12:17:49.708495 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10961 12:17:49.733946 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10962 12:17:49.788366 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10963 12:17:49.805002 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10964 12:17:49.824670 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10965 12:17:49.845073 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10966 12:17:49.860931 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10967 12:17:49.879463 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10968 12:17:49.896436 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10969 12:17:49.912581 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10970 12:17:49.965783 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10971 12:17:50.003607 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10972 12:17:50.072881 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10973 12:17:50.097231 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10974 12:17:50.248543 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10975 12:17:50.302242 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10976 12:17:50.345709 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10977 12:17:50.369354 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10978 12:17:50.394605 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10979 12:17:50.420941 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10980 12:17:50.459930 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10981 12:17:50.502092 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10982 12:17:50.520438 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10983 12:17:50.593391 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
10984 12:17:50.614559 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10985 12:17:50.682113 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10986 12:17:50.749353 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
10987 12:17:50.854333
10988 12:17:50.854848
10989 12:17:50.857607 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10990 12:17:50.858029
10991 12:17:50.861144 debian-bookworm-arm64 login: root (automatic login)
10992 12:17:50.861562
10993 12:17:50.861889
10994 12:17:51.200831 Linux debian-bookworm-arm64 6.1.72-cip13 #1 SMP PREEMPT Wed Jan 31 11:52:55 UTC 2024 aarch64
10995 12:17:51.201319
10996 12:17:51.207572 The programs included with the Debian GNU/Linux system are free software;
10997 12:17:51.214381 the exact distribution terms for each program are described in the
10998 12:17:51.217673 individual files in /usr/share/doc/*/copyright.
10999 12:17:51.218096
11000 12:17:51.223868 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11001 12:17:51.227474 permitted by applicable law.
11002 12:17:52.443835 Matched prompt #10: / #
11004 12:17:52.444342 Setting prompt string to ['/ #']
11005 12:17:52.444532 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11007 12:17:52.444942 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11008 12:17:52.445129 start: 2.2.6 expect-shell-connection (timeout 00:03:12) [common]
11009 12:17:52.445273 Setting prompt string to ['/ #']
11010 12:17:52.445419 Forcing a shell prompt, looking for ['/ #']
11012 12:17:52.496011 / #
11013 12:17:52.496890 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11014 12:17:52.497511 Waiting using forced prompt support (timeout 00:02:30)
11015 12:17:52.502352
11016 12:17:52.503161 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11017 12:17:52.503686 start: 2.2.7 export-device-env (timeout 00:03:12) [common]
11019 12:17:52.604807 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12669531/extract-nfsrootfs-kiz8_ci8'
11020 12:17:52.612118 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12669531/extract-nfsrootfs-kiz8_ci8'
11022 12:17:52.713648 / # export NFS_SERVER_IP='192.168.201.1'
11023 12:17:52.718582 export NFS_SERVER_IP='192.168.201.1'
11024 12:17:52.718959 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11025 12:17:52.719098 end: 2.2 depthcharge-retry (duration 00:01:49) [common]
11026 12:17:52.719209 end: 2 depthcharge-action (duration 00:01:49) [common]
11027 12:17:52.719323 start: 3 lava-test-retry (timeout 00:07:26) [common]
11028 12:17:52.719446 start: 3.1 lava-test-shell (timeout 00:07:26) [common]
11029 12:17:52.719542 Using namespace: common
11031 12:17:52.820280 / # #
11032 12:17:52.820949 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11033 12:17:52.826845 #
11034 12:17:52.827778 Using /lava-12669531
11036 12:17:52.929012 / # export SHELL=/bin/bash
11037 12:17:52.935397 export SHELL=/bin/bash
11039 12:17:53.037013 / # . /lava-12669531/environment
11040 12:17:53.043256 . /lava-12669531/environment
11042 12:17:53.152345 / # /lava-12669531/bin/lava-test-runner /lava-12669531/0
11043 12:17:53.152985 Test shell timeout: 10s (minimum of the action and connection timeout)
11044 12:17:53.159479 /lava-12669531/bin/lava-test-runner /lava-12669531/0
11045 12:17:53.475508 + export TESTRUN_ID=0_timesync-off
11046 12:17:53.478837 + TESTRUN_ID=0_timesync-off
11047 12:17:53.482240 + cd /lava-12669531/0/tests/0_timesync-off
11048 12:17:53.485144 ++ cat uuid
11049 12:17:53.494166 + UUID=12669531_1.6.2.3.1
11050 12:17:53.494607 + set +x
11051 12:17:53.501155 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12669531_1.6.2.3.1>
11052 12:17:53.501853 Received signal: <STARTRUN> 0_timesync-off 12669531_1.6.2.3.1
11053 12:17:53.502243 Starting test lava.0_timesync-off (12669531_1.6.2.3.1)
11054 12:17:53.502663 Skipping test definition patterns.
11055 12:17:53.504549 + systemctl stop systemd-timesyncd
11056 12:17:53.592944 + set +x
11057 12:17:53.597123 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12669531_1.6.2.3.1>
11058 12:17:53.597803 Received signal: <ENDRUN> 0_timesync-off 12669531_1.6.2.3.1
11059 12:17:53.598216 Ending use of test pattern.
11060 12:17:53.598537 Ending test lava.0_timesync-off (12669531_1.6.2.3.1), duration 0.10
11062 12:17:53.695597 + export TESTRUN_ID=1_kselftest-alsa
11063 12:17:53.697845 + TESTRUN_ID=1_kselftest-alsa
11064 12:17:53.704458 + cd /lava-12669531/0/tests/1_kselftest-alsa
11065 12:17:53.704881 ++ cat uuid
11066 12:17:53.713414 + UUID=12669531_1.6.2.3.5
11067 12:17:53.713835 + set +x
11068 12:17:53.720222 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 12669531_1.6.2.3.5>
11069 12:17:53.720905 Received signal: <STARTRUN> 1_kselftest-alsa 12669531_1.6.2.3.5
11070 12:17:53.721276 Starting test lava.1_kselftest-alsa (12669531_1.6.2.3.5)
11071 12:17:53.721671 Skipping test definition patterns.
11072 12:17:53.723476 + cd ./automated/linux/kselftest/
11073 12:17:53.750083 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11074 12:17:53.806988 INFO: install_deps skipped
11075 12:17:54.335415 --2024-01-31 12:17:54-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.72-cip13-32-gf60d2e8cb51c/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11076 12:17:54.347971 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11077 12:17:54.482244 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11078 12:17:54.615565 HTTP request sent, awaiting response... 200 OK
11079 12:17:54.618936 Length: 2966336 (2.8M) [application/octet-stream]
11080 12:17:54.621902 Saving to: 'kselftest.tar.xz'
11081 12:17:54.621985
11082 12:17:54.622049
11083 12:17:54.882120 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11084 12:17:55.166300 kselftest.tar.xz 1%[ ] 47.81K 179KB/s
11085 12:17:55.415428 kselftest.tar.xz 7%[> ] 205.70K 371KB/s
11086 12:17:55.681480 kselftest.tar.xz 19%[==> ] 563.94K 700KB/s
11087 12:17:55.947550 kselftest.tar.xz 30%[=====> ] 879.28K 819KB/s
11088 12:17:56.213805 kselftest.tar.xz 41%[=======> ] 1.19M 905KB/s
11089 12:17:56.482385 kselftest.tar.xz 53%[=========> ] 1.53M 972KB/s
11090 12:17:56.749748 kselftest.tar.xz 66%[============> ] 1.88M 1.00MB/s
11091 12:17:56.950148 kselftest.tar.xz 79%[==============> ] 2.25M 1.05MB/s
11092 12:17:57.162761 kselftest.tar.xz 92%[=================> ] 2.62M 1.12MB/s
11093 12:17:57.174125 kselftest.tar.xz 96%[==================> ] 2.73M 1.06MB/s
11094 12:17:57.181043 kselftest.tar.xz 100%[===================>] 2.83M 1.10MB/s in 2.6s
11095 12:17:57.181127
11096 12:17:57.439148 2024-01-31 12:17:57 (1.10 MB/s) - 'kselftest.tar.xz' saved [2966336/2966336]
11097 12:17:57.439299
11098 12:18:03.923888 skiplist:
11099 12:18:03.926396 ========================================
11100 12:18:03.930106 ========================================
11101 12:18:03.982348 alsa:mixer-test
11102 12:18:04.006138 ============== Tests to run ===============
11103 12:18:04.009537 alsa:mixer-test
11104 12:18:04.012211 ===========End Tests to run ===============
11105 12:18:04.017578 shardfile-alsa pass
11106 12:18:04.133696 <12>[ 40.220932] kselftest: Running tests in alsa
11107 12:18:04.143623 TAP version 13
11108 12:18:04.161398 1..1
11109 12:18:04.178236 # selftests: alsa: mixer-test
11110 12:18:04.688051 # TAP version 13
11111 12:18:04.688203 # 1..0
11112 12:18:04.694819 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11113 12:18:04.697533 ok 1 selftests: alsa: mixer-test
11114 12:18:05.429384 alsa_mixer-test pass
11115 12:18:05.472948 + ../../utils/send-to-lava.sh ./output/result.txt
11116 12:18:05.557160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11117 12:18:05.557452 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11119 12:18:05.607788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11120 12:18:05.607881 + set +x
11121 12:18:05.608119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11123 12:18:05.614127 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 12669531_1.6.2.3.5>
11124 12:18:05.614380 Received signal: <ENDRUN> 1_kselftest-alsa 12669531_1.6.2.3.5
11125 12:18:05.614456 Ending use of test pattern.
11126 12:18:05.614518 Ending test lava.1_kselftest-alsa (12669531_1.6.2.3.5), duration 11.89
11128 12:18:05.616903 <LAVA_TEST_RUNNER EXIT>
11129 12:18:05.617155 ok: lava_test_shell seems to have completed
11130 12:18:05.617255 alsa_mixer-test: pass
shardfile-alsa: pass
11131 12:18:05.617343 end: 3.1 lava-test-shell (duration 00:00:13) [common]
11132 12:18:05.617426 end: 3 lava-test-retry (duration 00:00:13) [common]
11133 12:18:05.617514 start: 4 finalize (timeout 00:07:13) [common]
11134 12:18:05.617604 start: 4.1 power-off (timeout 00:00:30) [common]
11135 12:18:05.617751 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11136 12:18:05.696421 >> Command sent successfully.
11137 12:18:05.698851 Returned 0 in 0 seconds
11138 12:18:05.799258 end: 4.1 power-off (duration 00:00:00) [common]
11140 12:18:05.799592 start: 4.2 read-feedback (timeout 00:07:13) [common]
11141 12:18:05.799860 Listened to connection for namespace 'common' for up to 1s
11142 12:18:06.800806 Finalising connection for namespace 'common'
11143 12:18:06.800978 Disconnecting from shell: Finalise
11144 12:18:06.801062 / #
11145 12:18:06.901360 end: 4.2 read-feedback (duration 00:00:01) [common]
11146 12:18:06.901528 end: 4 finalize (duration 00:00:01) [common]
11147 12:18:06.901645 Cleaning after the job
11148 12:18:06.901745 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669531/tftp-deploy-vtw011t9/ramdisk
11149 12:18:06.904729 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669531/tftp-deploy-vtw011t9/kernel
11150 12:18:06.917649 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669531/tftp-deploy-vtw011t9/dtb
11151 12:18:06.917835 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669531/tftp-deploy-vtw011t9/nfsrootfs
11152 12:18:07.018808 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12669531/tftp-deploy-vtw011t9/modules
11153 12:18:07.025853 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12669531
11154 12:18:07.690812 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12669531
11155 12:18:07.690992 Job finished correctly